From c96186151d7a1f452ab6634703e63c6063d3b5ce Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Fri, 9 Feb 2024 16:07:26 +0100 Subject: [PATCH 01/21] system(WBA) add STM32WBAxx HAL Drivers to v1.2.0 Included in STM32CubeWBA FW v1.2.0 Signed-off-by: Frederic Pillon --- .../Inc/Legacy/stm32_hal_legacy.h | 4332 +++++++++ .../Inc/stm32_assert_template.h | 53 + .../Inc/stm32wbaxx_hal.h | 552 ++ .../Inc/stm32wbaxx_hal_adc.h | 1850 ++++ .../Inc/stm32wbaxx_hal_adc_ex.h | 186 + .../Inc/stm32wbaxx_hal_comp.h | 793 ++ .../Inc/stm32wbaxx_hal_conf_template.h | 350 + .../Inc/stm32wbaxx_hal_cortex.h | 380 + .../Inc/stm32wbaxx_hal_crc.h | 342 + .../Inc/stm32wbaxx_hal_crc_ex.h | 150 + .../Inc/stm32wbaxx_hal_cryp.h | 724 ++ .../Inc/stm32wbaxx_hal_cryp_ex.h | 154 + .../Inc/stm32wbaxx_hal_def.h | 209 + .../Inc/stm32wbaxx_hal_dma.h | 837 ++ .../Inc/stm32wbaxx_hal_dma_ex.h | 589 ++ .../Inc/stm32wbaxx_hal_exti.h | 345 + .../Inc/stm32wbaxx_hal_flash.h | 1065 +++ .../Inc/stm32wbaxx_hal_flash_ex.h | 328 + .../Inc/stm32wbaxx_hal_gpio.h | 400 + .../Inc/stm32wbaxx_hal_gpio_ex.h | 394 + .../Inc/stm32wbaxx_hal_gtzc.h | 475 + .../Inc/stm32wbaxx_hal_hash.h | 566 ++ .../Inc/stm32wbaxx_hal_hsem.h | 238 + .../Inc/stm32wbaxx_hal_i2c.h | 846 ++ .../Inc/stm32wbaxx_hal_i2c_ex.h | 356 + .../Inc/stm32wbaxx_hal_icache.h | 294 + .../Inc/stm32wbaxx_hal_irda.h | 897 ++ .../Inc/stm32wbaxx_hal_irda_ex.h | 224 + .../Inc/stm32wbaxx_hal_iwdg.h | 302 + .../Inc/stm32wbaxx_hal_lptim.h | 1259 +++ .../Inc/stm32wbaxx_hal_pka.h | 670 ++ .../Inc/stm32wbaxx_hal_pwr.h | 931 ++ .../Inc/stm32wbaxx_hal_pwr_ex.h | 375 + .../Inc/stm32wbaxx_hal_ramcfg.h | 431 + .../Inc/stm32wbaxx_hal_rcc.h | 2385 +++++ .../Inc/stm32wbaxx_hal_rcc_ex.h | 987 ++ .../Inc/stm32wbaxx_hal_rng.h | 388 + .../Inc/stm32wbaxx_hal_rng_ex.h | 262 + .../Inc/stm32wbaxx_hal_rtc.h | 966 ++ .../Inc/stm32wbaxx_hal_rtc_ex.h | 1833 ++++ .../Inc/stm32wbaxx_hal_sai.h | 970 ++ .../Inc/stm32wbaxx_hal_sai_ex.h | 103 + .../Inc/stm32wbaxx_hal_smartcard.h | 1227 +++ .../Inc/stm32wbaxx_hal_smartcard_ex.h | 335 + .../Inc/stm32wbaxx_hal_smbus.h | 789 ++ .../Inc/stm32wbaxx_hal_smbus_ex.h | 334 + .../Inc/stm32wbaxx_hal_spi.h | 1128 +++ .../Inc/stm32wbaxx_hal_spi_ex.h | 285 + .../Inc/stm32wbaxx_hal_tim.h | 2520 +++++ .../Inc/stm32wbaxx_hal_tim_ex.h | 808 ++ .../Inc/stm32wbaxx_hal_tsc.h | 804 ++ .../Inc/stm32wbaxx_hal_uart.h | 1764 ++++ .../Inc/stm32wbaxx_hal_uart_ex.h | 576 ++ .../Inc/stm32wbaxx_hal_usart.h | 1000 ++ .../Inc/stm32wbaxx_hal_usart_ex.h | 397 + .../Inc/stm32wbaxx_hal_wwdg.h | 306 + .../Inc/stm32wbaxx_ll_adc.h | 5084 ++++++++++ .../Inc/stm32wbaxx_ll_bus.h | 1757 ++++ .../Inc/stm32wbaxx_ll_comp.h | 849 ++ .../Inc/stm32wbaxx_ll_cortex.h | 1316 +++ .../Inc/stm32wbaxx_ll_crc.h | 461 + .../Inc/stm32wbaxx_ll_dma.h | 4561 +++++++++ .../Inc/stm32wbaxx_ll_exti.h | 1295 +++ .../Inc/stm32wbaxx_ll_gpio.h | 1086 +++ .../Inc/stm32wbaxx_ll_hsem.h | 819 ++ .../Inc/stm32wbaxx_ll_i2c.h | 2611 ++++++ .../Inc/stm32wbaxx_ll_icache.h | 782 ++ .../Inc/stm32wbaxx_ll_iwdg.h | 453 + .../Inc/stm32wbaxx_ll_lptim.h | 2426 +++++ .../Inc/stm32wbaxx_ll_lpuart.h | 2744 ++++++ .../Inc/stm32wbaxx_ll_pka.h | 601 ++ .../Inc/stm32wbaxx_ll_pwr.h | 1802 ++++ .../Inc/stm32wbaxx_ll_rcc.h | 3273 +++++++ .../Inc/stm32wbaxx_ll_rng.h | 723 ++ .../Inc/stm32wbaxx_ll_rtc.h | 5888 ++++++++++++ .../Inc/stm32wbaxx_ll_spi.h | 2735 ++++++ .../Inc/stm32wbaxx_ll_system.h | 1102 +++ .../Inc/stm32wbaxx_ll_tim.h | 6100 ++++++++++++ .../Inc/stm32wbaxx_ll_usart.h | 4491 +++++++++ .../Inc/stm32wbaxx_ll_utils.h | 304 + .../Inc/stm32wbaxx_ll_wwdg.h | 328 + .../Drivers/STM32WBAxx_HAL_Driver/LICENSE.md | 27 + .../Drivers/STM32WBAxx_HAL_Driver/README.md | 36 + .../STM32WBAxx_HAL_Driver/Release_Notes.html | 373 + .../Src/stm32wbaxx_hal.c | 756 ++ .../Src/stm32wbaxx_hal_adc.c | 3005 ++++++ .../Src/stm32wbaxx_hal_adc_ex.c | 350 + .../Src/stm32wbaxx_hal_comp.c | 1062 +++ .../Src/stm32wbaxx_hal_cortex.c | 702 ++ .../Src/stm32wbaxx_hal_crc.c | 516 ++ .../Src/stm32wbaxx_hal_crc_ex.c | 232 + .../Src/stm32wbaxx_hal_cryp.c | 6498 +++++++++++++ .../Src/stm32wbaxx_hal_cryp_ex.c | 902 ++ .../Src/stm32wbaxx_hal_dma.c | 1670 ++++ .../Src/stm32wbaxx_hal_dma_ex.c | 4324 +++++++++ .../Src/stm32wbaxx_hal_exti.c | 856 ++ .../Src/stm32wbaxx_hal_flash.c | 820 ++ .../Src/stm32wbaxx_hal_flash_ex.c | 1656 ++++ .../Src/stm32wbaxx_hal_gpio.c | 663 ++ .../Src/stm32wbaxx_hal_gtzc.c | 1509 +++ .../Src/stm32wbaxx_hal_hash.c | 3073 ++++++ .../Src/stm32wbaxx_hal_hsem.c | 482 + .../Src/stm32wbaxx_hal_i2c.c | 7810 ++++++++++++++++ .../Src/stm32wbaxx_hal_i2c_ex.c | 506 + .../Src/stm32wbaxx_hal_icache.c | 651 ++ .../Src/stm32wbaxx_hal_irda.c | 3006 ++++++ .../Src/stm32wbaxx_hal_iwdg.c | 510 + .../Src/stm32wbaxx_hal_lptim.c | 3717 ++++++++ .../Src/stm32wbaxx_hal_msp_template.c | 100 + .../Src/stm32wbaxx_hal_pka.c | 3042 ++++++ .../Src/stm32wbaxx_hal_pwr.c | 1149 +++ .../Src/stm32wbaxx_hal_pwr_ex.c | 1053 +++ .../Src/stm32wbaxx_hal_ramcfg.c | 1122 +++ .../Src/stm32wbaxx_hal_rcc.c | 1820 ++++ .../Src/stm32wbaxx_hal_rcc_ex.c | 1361 +++ .../Src/stm32wbaxx_hal_rng.c | 1027 ++ .../Src/stm32wbaxx_hal_rng_ex.c | 338 + .../Src/stm32wbaxx_hal_rtc.c | 2221 +++++ .../Src/stm32wbaxx_hal_rtc_ex.c | 2886 ++++++ .../Src/stm32wbaxx_hal_sai.c | 2862 ++++++ .../Src/stm32wbaxx_hal_sai_ex.c | 131 + .../Src/stm32wbaxx_hal_smartcard.c | 3267 +++++++ .../Src/stm32wbaxx_hal_smartcard_ex.c | 494 + .../Src/stm32wbaxx_hal_smbus.c | 2813 ++++++ .../Src/stm32wbaxx_hal_smbus_ex.c | 388 + .../Src/stm32wbaxx_hal_spi.c | 3753 ++++++++ .../Src/stm32wbaxx_hal_spi_ex.c | 346 + .../Src/stm32wbaxx_hal_tim.c | 8241 +++++++++++++++++ .../Src/stm32wbaxx_hal_tim_ex.c | 3314 +++++++ ...32wbaxx_hal_timebase_rtc_wakeup_template.c | 268 + .../stm32wbaxx_hal_timebase_tim_template.c | 205 + .../Src/stm32wbaxx_hal_tsc.c | 1111 +++ .../Src/stm32wbaxx_hal_uart.c | 4804 ++++++++++ .../Src/stm32wbaxx_hal_uart_ex.c | 1144 +++ .../Src/stm32wbaxx_hal_usart.c | 3943 ++++++++ .../Src/stm32wbaxx_hal_usart_ex.c | 656 ++ .../Src/stm32wbaxx_hal_wwdg.c | 419 + .../Src/stm32wbaxx_ll_adc.c | 697 ++ .../Src/stm32wbaxx_ll_comp.c | 249 + .../Src/stm32wbaxx_ll_crc.c | 103 + .../Src/stm32wbaxx_ll_dma.c | 909 ++ .../Src/stm32wbaxx_ll_exti.c | 219 + .../Src/stm32wbaxx_ll_gpio.c | 254 + .../Src/stm32wbaxx_ll_i2c.c | 225 + .../Src/stm32wbaxx_ll_icache.c | 139 + .../Src/stm32wbaxx_ll_lptim.c | 193 + .../Src/stm32wbaxx_ll_lpuart.c | 285 + .../Src/stm32wbaxx_ll_pka.c | 163 + .../Src/stm32wbaxx_ll_pwr.c | 93 + .../Src/stm32wbaxx_ll_rcc.c | 1035 +++ .../Src/stm32wbaxx_ll_rng.c | 157 + .../Src/stm32wbaxx_ll_rtc.c | 858 ++ .../Src/stm32wbaxx_ll_spi.c | 408 + .../Src/stm32wbaxx_ll_tim.c | 1346 +++ .../Src/stm32wbaxx_ll_usart.c | 392 + .../Src/stm32wbaxx_ll_utils.c | 622 ++ .../_htmresc/Add button.svg | 2 + .../STM32WBAxx_HAL_Driver/_htmresc/Update.svg | 2 + .../_htmresc/favicon.png | Bin 0 -> 4126 bytes .../_htmresc/mini-st_2020.css | 1711 ++++ .../_htmresc/st_logo_2020.png | Bin 0 -> 7520 bytes .../Drivers/STM32YYxx_HAL_Driver_version.md | 1 + 162 files changed, 205708 insertions(+) create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32_assert_template.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_adc.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_adc_ex.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_comp.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_conf_template.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_cortex.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_crc.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_crc_ex.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_cryp.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_cryp_ex.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_def.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_dma.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_dma_ex.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_exti.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_flash.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_flash_ex.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_gpio.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_gpio_ex.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_gtzc.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_hash.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_hsem.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_i2c.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_i2c_ex.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_icache.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_irda.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_irda_ex.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_iwdg.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_lptim.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_pka.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_pwr.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_pwr_ex.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_ramcfg.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rcc.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rcc_ex.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rng.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rng_ex.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rtc.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rtc_ex.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_sai.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_sai_ex.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_smartcard.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_smartcard_ex.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_smbus.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_smbus_ex.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_spi.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_spi_ex.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_tim.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_tim_ex.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_tsc.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_uart.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_uart_ex.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_usart.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_usart_ex.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_wwdg.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_adc.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_bus.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_comp.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_cortex.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_crc.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_dma.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_exti.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_gpio.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_hsem.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_i2c.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_icache.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_iwdg.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_lptim.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_lpuart.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_pka.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_pwr.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_rcc.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_rng.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_rtc.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_spi.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_system.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_tim.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_usart.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_utils.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_wwdg.h create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/LICENSE.md create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/README.md create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Release_Notes.html create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_adc.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_adc_ex.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_comp.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_cortex.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_crc.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_crc_ex.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_cryp.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_cryp_ex.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_dma.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_dma_ex.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_exti.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_flash.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_flash_ex.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_gpio.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_gtzc.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_hash.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_hsem.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_i2c.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_i2c_ex.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_icache.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_irda.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_iwdg.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_lptim.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_msp_template.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_pka.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_pwr.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_pwr_ex.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_ramcfg.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_rcc.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_rcc_ex.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_rng.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_rng_ex.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_rtc.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_rtc_ex.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_sai.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_sai_ex.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_smartcard.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_smartcard_ex.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_smbus.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_smbus_ex.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_spi.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_spi_ex.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_tim.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_tim_ex.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_timebase_rtc_wakeup_template.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_timebase_tim_template.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_tsc.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_uart.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_uart_ex.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_usart.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_usart_ex.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_wwdg.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_adc.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_comp.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_crc.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_dma.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_exti.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_gpio.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_i2c.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_icache.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_lptim.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_lpuart.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_pka.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_pwr.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_rcc.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_rng.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_rtc.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_spi.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_tim.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_usart.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_utils.c create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/_htmresc/Add button.svg create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/_htmresc/Update.svg create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/_htmresc/favicon.png create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/_htmresc/mini-st_2020.css create mode 100644 system/Drivers/STM32WBAxx_HAL_Driver/_htmresc/st_logo_2020.png diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h new file mode 100644 index 0000000000..f8322d1b40 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -0,0 +1,4332 @@ +/** + ****************************************************************************** + * @file stm32_hal_legacy.h + * @author MCD Application Team + * @brief This file contains aliases definition for the STM32Cube HAL constants + * macros and functions maintained for legacy purpose. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32_HAL_LEGACY +#define STM32_HAL_LEGACY + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose + * @{ + */ +#define AES_FLAG_RDERR CRYP_FLAG_RDERR +#define AES_FLAG_WRERR CRYP_FLAG_WRERR +#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF +#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR +#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR +#if defined(STM32H7) || defined(STM32MP1) +#define CRYP_DATATYPE_32B CRYP_NO_SWAP +#define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP +#define CRYP_DATATYPE_8B CRYP_BYTE_SWAP +#define CRYP_DATATYPE_1B CRYP_BIT_SWAP +#endif /* STM32H7 || STM32MP1 */ +/** + * @} + */ + +/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose + * @{ + */ +#define ADC_RESOLUTION12b ADC_RESOLUTION_12B +#define ADC_RESOLUTION10b ADC_RESOLUTION_10B +#define ADC_RESOLUTION8b ADC_RESOLUTION_8B +#define ADC_RESOLUTION6b ADC_RESOLUTION_6B +#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN +#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED +#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV +#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV +#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV +#define REGULAR_GROUP ADC_REGULAR_GROUP +#define INJECTED_GROUP ADC_INJECTED_GROUP +#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP +#define AWD_EVENT ADC_AWD_EVENT +#define AWD1_EVENT ADC_AWD1_EVENT +#define AWD2_EVENT ADC_AWD2_EVENT +#define AWD3_EVENT ADC_AWD3_EVENT +#define OVR_EVENT ADC_OVR_EVENT +#define JQOVF_EVENT ADC_JQOVF_EVENT +#define ALL_CHANNELS ADC_ALL_CHANNELS +#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS +#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS +#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR +#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT +#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 +#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 +#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 +#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6 +#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8 +#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO +#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 +#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO +#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 +#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO +#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11 +#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1 +#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE +#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING +#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING +#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING +#define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5 + +#define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY +#define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY +#define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC +#define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC +#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL +#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL +#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 + +#if defined(STM32H7) +#define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT +#endif /* STM32H7 */ + +#if defined(STM32U5) +#define ADC_SAMPLETIME_5CYCLE ADC_SAMPLETIME_5CYCLES +#define ADC_SAMPLETIME_391CYCLES_5 ADC_SAMPLETIME_391CYCLES +#define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5 +#endif /* STM32U5 */ + +#if defined(STM32H5) +#define ADC_CHANNEL_VCORE ADC_CHANNEL_VDDCORE +#endif /* STM32H5 */ +/** + * @} + */ + +/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG + +/** + * @} + */ + +/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose + * @{ + */ +#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE +#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE +#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1 +#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2 +#define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3 +#define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4 +#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 +#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 +#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 +#if defined(STM32L0) +#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM + input 1 for COMP1, LPTIM input 2 for COMP2 */ +#endif +#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR +#if defined(STM32F373xC) || defined(STM32F378xx) +#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 +#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR +#endif /* STM32F373xC || STM32F378xx */ + +#if defined(STM32L0) || defined(STM32L4) +#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON + +#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1 +#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2 +#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3 +#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4 +#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5 +#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6 + +#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT +#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT +#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT +#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT +#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1 +#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1 +#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1 +#if defined(STM32L0) +/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */ +/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */ +/* to the second dedicated IO (only for COMP2). */ +#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2 +#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2 +#else +#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2 +#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3 +#endif +#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4 +#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5 + +#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW +#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH + +/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */ +/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */ +#if defined(COMP_CSR_LOCK) +#define COMP_FLAG_LOCK COMP_CSR_LOCK +#elif defined(COMP_CSR_COMP1LOCK) +#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK +#elif defined(COMP_CSR_COMPxLOCK) +#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK +#endif + +#if defined(STM32L4) +#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1 +#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1 +#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1 +#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2 +#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2 +#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2 +#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE +#endif + +#if defined(STM32L0) +#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED +#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER +#else +#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED +#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED +#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER +#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER +#endif + +#endif + +#if defined(STM32U5) +#define __HAL_COMP_COMP1_EXTI_CLEAR_RASING_FLAG __HAL_COMP_COMP1_EXTI_CLEAR_RISING_FLAG +#endif + +/** + * @} + */ + +/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose + * @{ + */ +#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig +#if defined(STM32U5) +#define MPU_DEVICE_nGnRnE MPU_DEVICE_NGNRNE +#define MPU_DEVICE_nGnRE MPU_DEVICE_NGNRE +#define MPU_DEVICE_nGRE MPU_DEVICE_NGRE +#endif /* STM32U5 */ +/** + * @} + */ + +/** @defgroup CRC_Aliases CRC API aliases + * @{ + */ +#if defined(STM32H5) || defined(STM32C0) +#else +#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for + inter STM32 series compatibility */ +#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for + inter STM32 series compatibility */ +#endif +/** + * @} + */ + +/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE +#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE + +/** + * @} + */ + +/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define DAC1_CHANNEL_1 DAC_CHANNEL_1 +#define DAC1_CHANNEL_2 DAC_CHANNEL_2 +#define DAC2_CHANNEL_1 DAC_CHANNEL_1 +#define DAC_WAVE_NONE 0x00000000U +#define DAC_WAVE_NOISE DAC_CR_WAVE1_0 +#define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1 +#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE +#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE +#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE + +#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5) +#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL +#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL +#endif + +#if defined(STM32U5) +#define DAC_TRIGGER_STOP_LPTIM1_OUT DAC_TRIGGER_STOP_LPTIM1_CH1 +#define DAC_TRIGGER_STOP_LPTIM3_OUT DAC_TRIGGER_STOP_LPTIM3_CH1 +#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1 +#define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1 +#endif + +#if defined(STM32H5) +#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1 +#define DAC_TRIGGER_LPTIM2_OUT DAC_TRIGGER_LPTIM2_CH1 +#endif + +#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || \ + defined(STM32F4) || defined(STM32G4) +#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID +#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID +#endif + +/** + * @} + */ + +/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 +#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 +#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 +#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 +#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 +#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 +#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6 +#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 +#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 +#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 +#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 +#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 +#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 +#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 + +#define IS_HAL_REMAPDMA IS_DMA_REMAP +#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE +#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE + +#if defined(STM32L4) + +#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI1 HAL_DMAMUX1_REQ_GEN_EXTI1 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI2 HAL_DMAMUX1_REQ_GEN_EXTI2 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI3 HAL_DMAMUX1_REQ_GEN_EXTI3 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI4 HAL_DMAMUX1_REQ_GEN_EXTI4 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI5 HAL_DMAMUX1_REQ_GEN_EXTI5 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI6 HAL_DMAMUX1_REQ_GEN_EXTI6 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI7 HAL_DMAMUX1_REQ_GEN_EXTI7 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI8 HAL_DMAMUX1_REQ_GEN_EXTI8 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI9 HAL_DMAMUX1_REQ_GEN_EXTI9 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI10 HAL_DMAMUX1_REQ_GEN_EXTI10 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI11 HAL_DMAMUX1_REQ_GEN_EXTI11 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI12 HAL_DMAMUX1_REQ_GEN_EXTI12 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI13 HAL_DMAMUX1_REQ_GEN_EXTI13 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI14 HAL_DMAMUX1_REQ_GEN_EXTI14 +#define HAL_DMAMUX1_REQUEST_GEN_EXTI15 HAL_DMAMUX1_REQ_GEN_EXTI15 +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE HAL_DMAMUX1_REQ_GEN_DSI_TE +#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT HAL_DMAMUX1_REQ_GEN_DSI_EOT +#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT HAL_DMAMUX1_REQ_GEN_DMA2D_EOT +#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT HAL_DMAMUX1_REQ_GEN_LTDC_IT + +#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT +#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING +#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING +#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING + +#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || \ + defined(STM32L4S7xx) || defined(STM32L4S9xx) +#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI +#endif + +#endif /* STM32L4 */ + +#if defined(STM32G0) +#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1 +#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2 +#define DMA_REQUEST_TIM16_TRIG_COM DMA_REQUEST_TIM16_COM +#define DMA_REQUEST_TIM17_TRIG_COM DMA_REQUEST_TIM17_COM + +#define LL_DMAMUX_REQ_TIM16_TRIG_COM LL_DMAMUX_REQ_TIM16_COM +#define LL_DMAMUX_REQ_TIM17_TRIG_COM LL_DMAMUX_REQ_TIM17_COM +#endif + +#if defined(STM32H7) + +#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 +#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2 + +#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX +#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX + +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT +#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT +#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 +#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO + +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT +#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT +#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT +#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP +#define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0 +#define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2 +#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT +#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT +#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT +#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT +#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT +#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT +#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT + +#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT +#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING +#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING +#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING + +#define DFSDM_FILTER_EXT_TRIG_LPTIM1 DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT +#define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT +#define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT + +#define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT +#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT + +#endif /* STM32H7 */ + +#if defined(STM32U5) +#define GPDMA1_REQUEST_DCMI GPDMA1_REQUEST_DCMI_PSSI +#endif /* STM32U5 */ +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose + * @{ + */ + +#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE +#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD +#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD +#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD +#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS +#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES +#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES +#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE +#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE +#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE +#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE +#define OBEX_PCROP OPTIONBYTE_PCROP +#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG +#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE +#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE +#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE +#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD +#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD +#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE +#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD +#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD +#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE +#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD +#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD +#define PAGESIZE FLASH_PAGE_SIZE +#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE +#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD +#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD +#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1 +#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2 +#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3 +#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4 +#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST +#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST +#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA +#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB +#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA +#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB +#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE +#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN +#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE +#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN +#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE +#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD +#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG +#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS +#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP +#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV +#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR +#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG +#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION +#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA +#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE +#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE +#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS +#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS +#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST +#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR +#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO +#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION +#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS +#define OB_WDG_SW OB_IWDG_SW +#define OB_WDG_HW OB_IWDG_HW +#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET +#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET +#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET +#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET +#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR +#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 +#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 +#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 +#if defined(STM32G0) || defined(STM32C0) +#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE +#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH +#else +#define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE +#define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE +#endif +#if defined(STM32H7) +#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1 +#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1 +#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1 +#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2 +#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2 +#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2 +#define FLASH_FLAG_WDW FLASH_FLAG_WBNE +#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL +#endif /* STM32H7 */ +#if defined(STM32U5) +#define OB_USER_nRST_STOP OB_USER_NRST_STOP +#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY +#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW +#define OB_USER_nSWBOOT0 OB_USER_NSWBOOT0 +#define OB_USER_nBOOT0 OB_USER_NBOOT0 +#define OB_nBOOT0_RESET OB_NBOOT0_RESET +#define OB_nBOOT0_SET OB_NBOOT0_SET +#define OB_USER_SRAM134_RST OB_USER_SRAM_RST +#define OB_SRAM134_RST_ERASE OB_SRAM_RST_ERASE +#define OB_SRAM134_RST_NOT_ERASE OB_SRAM_RST_NOT_ERASE +#endif /* STM32U5 */ + +/** + * @} + */ + +/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose + * @{ + */ + +#if defined(STM32H7) +#define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE +#define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE +#define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET +#define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET +#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE +#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE +#endif /* STM32H7 */ + +/** + * @} + */ + +/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose + * @{ + */ + +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8 +#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9 +#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 +#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 +#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 +#if defined(STM32G4) + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOSwitchBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOSwitchBooster +#define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD +#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD +#endif /* STM32G4 */ + +#if defined(STM32H5) +#define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC +#define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC +#define SYSCFG_IT_FPU_UFC SBS_IT_FPU_UFC +#define SYSCFG_IT_FPU_OFC SBS_IT_FPU_OFC +#define SYSCFG_IT_FPU_IDC SBS_IT_FPU_IDC +#define SYSCFG_IT_FPU_IXC SBS_IT_FPU_IXC + +#define SYSCFG_BREAK_FLASH_ECC SBS_BREAK_FLASH_ECC +#define SYSCFG_BREAK_PVD SBS_BREAK_PVD +#define SYSCFG_BREAK_SRAM_ECC SBS_BREAK_SRAM_ECC +#define SYSCFG_BREAK_LOCKUP SBS_BREAK_LOCKUP + +#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 VREFBUF_VOLTAGE_SCALE0 +#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_VOLTAGE_SCALE1 +#define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_VOLTAGE_SCALE2 +#define SYSCFG_VREFBUF_VOLTAGE_SCALE3 VREFBUF_VOLTAGE_SCALE3 + +#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE VREFBUF_HIGH_IMPEDANCE_DISABLE +#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_HIGH_IMPEDANCE_ENABLE + +#define SYSCFG_FASTMODEPLUS_PB6 SBS_FASTMODEPLUS_PB6 +#define SYSCFG_FASTMODEPLUS_PB7 SBS_FASTMODEPLUS_PB7 +#define SYSCFG_FASTMODEPLUS_PB8 SBS_FASTMODEPLUS_PB8 +#define SYSCFG_FASTMODEPLUS_PB9 SBS_FASTMODEPLUS_PB9 + +#define SYSCFG_ETH_MII SBS_ETH_MII +#define SYSCFG_ETH_RMII SBS_ETH_RMII +#define IS_SYSCFG_ETHERNET_CONFIG IS_SBS_ETHERNET_CONFIG + +#define SYSCFG_MEMORIES_ERASE_FLAG_IPMEE SBS_MEMORIES_ERASE_FLAG_IPMEE +#define SYSCFG_MEMORIES_ERASE_FLAG_MCLR SBS_MEMORIES_ERASE_FLAG_MCLR +#define IS_SYSCFG_MEMORIES_ERASE_FLAG IS_SBS_MEMORIES_ERASE_FLAG + +#define IS_SYSCFG_CODE_CONFIG IS_SBS_CODE_CONFIG + +#define SYSCFG_MPU_NSEC SBS_MPU_NSEC +#define SYSCFG_VTOR_NSEC SBS_VTOR_NSEC +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define SYSCFG_SAU SBS_SAU +#define SYSCFG_MPU_SEC SBS_MPU_SEC +#define SYSCFG_VTOR_AIRCR_SEC SBS_VTOR_AIRCR_SEC +#define SYSCFG_LOCK_ALL SBS_LOCK_ALL +#else +#define SYSCFG_LOCK_ALL SBS_LOCK_ALL +#endif /* __ARM_FEATURE_CMSE */ + +#define SYSCFG_CLK SBS_CLK +#define SYSCFG_CLASSB SBS_CLASSB +#define SYSCFG_FPU SBS_FPU +#define SYSCFG_ALL SBS_ALL + +#define SYSCFG_SEC SBS_SEC +#define SYSCFG_NSEC SBS_NSEC + +#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE __HAL_SBS_FPU_INTERRUPT_ENABLE +#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE __HAL_SBS_FPU_INTERRUPT_DISABLE + +#define __HAL_SYSCFG_BREAK_ECC_LOCK __HAL_SBS_BREAK_ECC_LOCK +#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK __HAL_SBS_BREAK_LOCKUP_LOCK +#define __HAL_SYSCFG_BREAK_PVD_LOCK __HAL_SBS_BREAK_PVD_LOCK +#define __HAL_SYSCFG_BREAK_SRAM_ECC_LOCK __HAL_SBS_BREAK_SRAM_ECC_LOCK + +#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE __HAL_SBS_FASTMODEPLUS_ENABLE +#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE __HAL_SBS_FASTMODEPLUS_DISABLE + +#define __HAL_SYSCFG_GET_MEMORIES_ERASE_STATUS __HAL_SBS_GET_MEMORIES_ERASE_STATUS +#define __HAL_SYSCFG_CLEAR_MEMORIES_ERASE_STATUS __HAL_SBS_CLEAR_MEMORIES_ERASE_STATUS + +#define IS_SYSCFG_FPU_INTERRUPT IS_SBS_FPU_INTERRUPT +#define IS_SYSCFG_BREAK_CONFIG IS_SBS_BREAK_CONFIG +#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE IS_VREFBUF_VOLTAGE_SCALE +#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE IS_VREFBUF_HIGH_IMPEDANCE +#define IS_SYSCFG_VREFBUF_TRIMMING IS_VREFBUF_TRIMMING +#define IS_SYSCFG_FASTMODEPLUS IS_SBS_FASTMODEPLUS +#define IS_SYSCFG_ITEMS_ATTRIBUTES IS_SBS_ITEMS_ATTRIBUTES +#define IS_SYSCFG_ATTRIBUTES IS_SBS_ATTRIBUTES +#define IS_SYSCFG_LOCK_ITEMS IS_SBS_LOCK_ITEMS + +#define HAL_SYSCFG_VREFBUF_VoltageScalingConfig HAL_VREFBUF_VoltageScalingConfig +#define HAL_SYSCFG_VREFBUF_HighImpedanceConfig HAL_VREFBUF_HighImpedanceConfig +#define HAL_SYSCFG_VREFBUF_TrimmingConfig HAL_VREFBUF_TrimmingConfig +#define HAL_SYSCFG_EnableVREFBUF HAL_EnableVREFBUF +#define HAL_SYSCFG_DisableVREFBUF HAL_DisableVREFBUF + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SBS_EnableIOAnalogSwitchBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SBS_DisableIOAnalogSwitchBooster +#define HAL_SYSCFG_ETHInterfaceSelect HAL_SBS_ETHInterfaceSelect + +#define HAL_SYSCFG_Lock HAL_SBS_Lock +#define HAL_SYSCFG_GetLock HAL_SBS_GetLock + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define HAL_SYSCFG_ConfigAttributes HAL_SBS_ConfigAttributes +#define HAL_SYSCFG_GetConfigAttributes HAL_SBS_GetConfigAttributes +#endif /* __ARM_FEATURE_CMSE */ + +#endif /* STM32H5 */ + + +/** + * @} + */ + + +/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose + * @{ + */ +#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4) +#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE +#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE +#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 +#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16 +#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) +#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE +#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE +#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8 +#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16 +#endif +/** + * @} + */ + +/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef +#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef +/** + * @} + */ + +/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose + * @{ + */ +#define GET_GPIO_SOURCE GPIO_GET_INDEX +#define GET_GPIO_INDEX GPIO_GET_INDEX + +#if defined(STM32F4) +#define GPIO_AF12_SDMMC GPIO_AF12_SDIO +#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO +#endif + +#if defined(STM32F7) +#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 +#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 +#endif + +#if defined(STM32L4) +#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 +#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 +#endif + +#if defined(STM32H7) +#define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1 +#define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1 +#define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1 +#define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2 +#define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2 +#define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2 + +#if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || \ + defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx) +#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS +#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS +#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS +#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || \ + STM32H757xx */ +#endif /* STM32H7 */ + +#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 +#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 +#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 + +#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || \ + defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5) +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB || STM32U5*/ + +#if defined(STM32L1) +#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#endif /* STM32L1 */ + +#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH +#endif /* STM32F0 || STM32F3 || STM32F1 */ + +#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 + +#if defined(STM32U5) || defined(STM32H5) +#define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ +#endif /* STM32U5 || STM32H5 */ +#if defined(STM32U5) +#define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP +#define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1 +#endif /* STM32U5 */ +/** + * @} + */ + +/** @defgroup HAL_GTZC_Aliased_Defines HAL GTZC Aliased Defines maintained for legacy purpose + * @{ + */ +#if defined(STM32U5) +#define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI +#define GTZC_PERIPH_LTDC GTZC_PERIPH_LTDCUSB +#endif /* STM32U5 */ +#if defined(STM32H5) +#define GTZC_PERIPH_DAC12 GTZC_PERIPH_DAC1 +#define GTZC_PERIPH_ADC12 GTZC_PERIPH_ADC +#define GTZC_PERIPH_USBFS GTZC_PERIPH_USB +#endif /* STM32H5 */ +#if defined(STM32H5) || defined(STM32U5) +#define GTZC_MCPBB_NB_VCTR_REG_MAX GTZC_MPCBB_NB_VCTR_REG_MAX +#define GTZC_MCPBB_NB_LCK_VCTR_REG_MAX GTZC_MPCBB_NB_LCK_VCTR_REG_MAX +#define GTZC_MCPBB_SUPERBLOCK_UNLOCKED GTZC_MPCBB_SUPERBLOCK_UNLOCKED +#define GTZC_MCPBB_SUPERBLOCK_LOCKED GTZC_MPCBB_SUPERBLOCK_LOCKED +#define GTZC_MCPBB_BLOCK_NSEC GTZC_MPCBB_BLOCK_NSEC +#define GTZC_MCPBB_BLOCK_SEC GTZC_MPCBB_BLOCK_SEC +#define GTZC_MCPBB_BLOCK_NPRIV GTZC_MPCBB_BLOCK_NPRIV +#define GTZC_MCPBB_BLOCK_PRIV GTZC_MPCBB_BLOCK_PRIV +#define GTZC_MCPBB_LOCK_OFF GTZC_MPCBB_LOCK_OFF +#define GTZC_MCPBB_LOCK_ON GTZC_MPCBB_LOCK_ON +#endif /* STM32H5 || STM32U5 */ +/** + * @} + */ + +/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose + * @{ + */ +#define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 +#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 +#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 + +#define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER +#define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER +#define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD +#define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD +#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER +#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER +#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE +#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE + +#if defined(STM32G4) +#define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig +#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable +#define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable +#define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset +#define HRTIM_TIMEEVENT_A HRTIM_EVENTCOUNTER_A +#define HRTIM_TIMEEVENT_B HRTIM_EVENTCOUNTER_B +#define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL +#define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL +#endif /* STM32G4 */ + +#if defined(STM32H7) +#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 + +#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 +#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 +#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 +#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 +#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 +#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 +#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 +#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 +#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 +#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 +#endif /* STM32H7 */ + +#if defined(STM32F3) +/** @brief Constants defining available sources associated to external events. + */ +#define HRTIM_EVENTSRC_1 (0x00000000U) +#define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0) +#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1) +#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) + +/** @brief Constants defining the DLL calibration periods (in micro seconds) + */ +#define HRTIM_CALIBRATIONRATE_7300 0x00000000U +#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) +#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) +#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) + +#endif /* STM32F3 */ +/** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose + * @{ + */ +#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE +#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE +#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE +#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE +#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE +#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE +#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE +#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE +#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || \ + defined(STM32L1) || defined(STM32F7) +#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX +#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX +#define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX +#define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX +#endif +/** + * @} + */ + +/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose + * @{ + */ +#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE +#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE + +/** + * @} + */ + +/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose + * @{ + */ +#define KR_KEY_RELOAD IWDG_KEY_RELOAD +#define KR_KEY_ENABLE IWDG_KEY_ENABLE +#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE +#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE +/** + * @} + */ + +/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose + * @{ + */ + +#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION +#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS +#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS +#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS + +#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING +#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING +#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING + +#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION +#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS + +/* The following 3 definition have also been present in a temporary version of lptim.h */ +/* They need to be renamed also to the right name, just in case */ +#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS +#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS + + +/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_LPTIM_ReadCompare HAL_LPTIM_ReadCapturedValue +/** + * @} + */ + +#if defined(STM32U5) +#define LPTIM_ISR_CC1 LPTIM_ISR_CC1IF +#define LPTIM_ISR_CC2 LPTIM_ISR_CC2IF +#define LPTIM_CHANNEL_ALL 0x00000000U +#endif /* STM32U5 */ +/** + * @} + */ + +/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b +#define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b +#define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b +#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b + +#define NAND_AddressTypedef NAND_AddressTypeDef + +#define __ARRAY_ADDRESS ARRAY_ADDRESS +#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE +#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE +#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE +#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE +/** + * @} + */ + +/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose + * @{ + */ +#define NOR_StatusTypedef HAL_NOR_StatusTypeDef +#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS +#define NOR_ONGOING HAL_NOR_STATUS_ONGOING +#define NOR_ERROR HAL_NOR_STATUS_ERROR +#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT + +#define __NOR_WRITE NOR_WRITE +#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT +/** + * @} + */ + +/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose + * @{ + */ + +#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0 +#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1 +#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2 +#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3 + +#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0 +#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1 +#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2 +#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 + +#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 +#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 + +#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 +#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 + +#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0 +#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 + +#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1 + +#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO +#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 +#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 + +#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) || defined(STM32U5) +#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID +#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID +#endif + +#if defined(STM32L4) || defined(STM32L5) +#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALPOWER +#elif defined(STM32G4) +#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALSPEED +#endif + +/** + * @} + */ + +/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose + * @{ + */ +#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS + +#if defined(STM32H7) +#define I2S_IT_TXE I2S_IT_TXP +#define I2S_IT_RXNE I2S_IT_RXP + +#define I2S_FLAG_TXE I2S_FLAG_TXP +#define I2S_FLAG_RXNE I2S_FLAG_RXP +#endif + +#if defined(STM32F7) +#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL +#endif +/** + * @} + */ + +/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose + * @{ + */ + +/* Compact Flash-ATA registers description */ +#define CF_DATA ATA_DATA +#define CF_SECTOR_COUNT ATA_SECTOR_COUNT +#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER +#define CF_CYLINDER_LOW ATA_CYLINDER_LOW +#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH +#define CF_CARD_HEAD ATA_CARD_HEAD +#define CF_STATUS_CMD ATA_STATUS_CMD +#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE +#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA + +/* Compact Flash-ATA commands */ +#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD +#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD +#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD +#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD + +#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef +#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS +#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING +#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR +#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT +/** + * @} + */ + +/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define FORMAT_BIN RTC_FORMAT_BIN +#define FORMAT_BCD RTC_FORMAT_BCD + +#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE +#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE +#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE +#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE + +#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE +#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE +#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE +#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT +#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT + +#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT +#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 + +#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE +#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1 +#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1 + +#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT +#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 +#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 + +#if defined(STM32H5) +#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE +#define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM +#endif /* STM32H5 */ + +#if defined(STM32WBA) +#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE +#define TAMP_SECRETDEVICE_ERASE_SRAM2 TAMP_DEVICESECRETS_ERASE_SRAM2 +#define TAMP_SECRETDEVICE_ERASE_RHUK TAMP_DEVICESECRETS_ERASE_RHUK +#define TAMP_SECRETDEVICE_ERASE_ICACHE TAMP_DEVICESECRETS_ERASE_ICACHE +#define TAMP_SECRETDEVICE_ERASE_SAES_AES_HASH TAMP_DEVICESECRETS_ERASE_SAES_AES_HASH +#define TAMP_SECRETDEVICE_ERASE_PKA_SRAM TAMP_DEVICESECRETS_ERASE_PKA_SRAM +#define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL +#endif /* STM32WBA */ + +#if defined(STM32H5) || defined(STM32WBA) +#define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE +#define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL +#endif /* STM32H5 || STM32WBA */ + +#if defined(STM32F7) +#define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK +#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK +#endif /* STM32F7 */ + +#if defined(STM32H7) +#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X +#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT +#endif /* STM32H7 */ + +#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0) +#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1 +#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2 +#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3 +#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP +#endif /* STM32F7 || STM32H7 || STM32L0 */ + +/** + * @} + */ + + +/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose + * @{ + */ +#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE +#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE + +#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE +#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE +#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE +#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE + +#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE +#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE + +#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE +#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE +/** + * @} + */ + + +/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose + * @{ + */ +#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE +#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE +#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE +#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE +#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE +#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE +#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE +#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE +#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE +#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE +#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose + * @{ + */ +#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE +#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE + +#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE +#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE + +#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE +#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE + +#if defined(STM32H7) + +#define SPI_FLAG_TXE SPI_FLAG_TXP +#define SPI_FLAG_RXNE SPI_FLAG_RXP + +#define SPI_IT_TXE SPI_IT_TXP +#define SPI_IT_RXNE SPI_IT_RXP + +#define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET +#define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET +#define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET +#define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET + +#endif /* STM32H7 */ + +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose + * @{ + */ +#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK +#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK + +#define TIM_DMABase_CR1 TIM_DMABASE_CR1 +#define TIM_DMABase_CR2 TIM_DMABASE_CR2 +#define TIM_DMABase_SMCR TIM_DMABASE_SMCR +#define TIM_DMABase_DIER TIM_DMABASE_DIER +#define TIM_DMABase_SR TIM_DMABASE_SR +#define TIM_DMABase_EGR TIM_DMABASE_EGR +#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1 +#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2 +#define TIM_DMABase_CCER TIM_DMABASE_CCER +#define TIM_DMABase_CNT TIM_DMABASE_CNT +#define TIM_DMABase_PSC TIM_DMABASE_PSC +#define TIM_DMABase_ARR TIM_DMABASE_ARR +#define TIM_DMABase_RCR TIM_DMABASE_RCR +#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1 +#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2 +#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3 +#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4 +#define TIM_DMABase_BDTR TIM_DMABASE_BDTR +#define TIM_DMABase_DCR TIM_DMABASE_DCR +#define TIM_DMABase_DMAR TIM_DMABASE_DMAR +#define TIM_DMABase_OR1 TIM_DMABASE_OR1 +#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3 +#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5 +#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6 +#define TIM_DMABase_OR2 TIM_DMABASE_OR2 +#define TIM_DMABase_OR3 TIM_DMABASE_OR3 +#define TIM_DMABase_OR TIM_DMABASE_OR + +#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE +#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1 +#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2 +#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3 +#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4 +#define TIM_EventSource_COM TIM_EVENTSOURCE_COM +#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER +#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK +#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2 + +#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER +#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS +#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS +#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS +#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS +#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS +#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS +#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS +#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS +#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS +#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS +#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS +#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS +#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS +#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS +#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS +#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS +#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS + +#if defined(STM32L0) +#define TIM22_TI1_GPIO1 TIM22_TI1_GPIO +#define TIM22_TI1_GPIO2 TIM22_TI1_GPIO +#endif + +#if defined(STM32F3) +#define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE +#endif + +#if defined(STM32H7) +#define TIM_TIM1_ETR_COMP1_OUT TIM_TIM1_ETR_COMP1 +#define TIM_TIM1_ETR_COMP2_OUT TIM_TIM1_ETR_COMP2 +#define TIM_TIM8_ETR_COMP1_OUT TIM_TIM8_ETR_COMP1 +#define TIM_TIM8_ETR_COMP2_OUT TIM_TIM8_ETR_COMP2 +#define TIM_TIM2_ETR_COMP1_OUT TIM_TIM2_ETR_COMP1 +#define TIM_TIM2_ETR_COMP2_OUT TIM_TIM2_ETR_COMP2 +#define TIM_TIM3_ETR_COMP1_OUT TIM_TIM3_ETR_COMP1 +#define TIM_TIM1_TI1_COMP1_OUT TIM_TIM1_TI1_COMP1 +#define TIM_TIM8_TI1_COMP2_OUT TIM_TIM8_TI1_COMP2 +#define TIM_TIM2_TI4_COMP1_OUT TIM_TIM2_TI4_COMP1 +#define TIM_TIM2_TI4_COMP2_OUT TIM_TIM2_TI4_COMP2 +#define TIM_TIM2_TI4_COMP1COMP2_OUT TIM_TIM2_TI4_COMP1_COMP2 +#define TIM_TIM3_TI1_COMP1_OUT TIM_TIM3_TI1_COMP1 +#define TIM_TIM3_TI1_COMP2_OUT TIM_TIM3_TI1_COMP2 +#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 +#endif + +#if defined(STM32U5) +#define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS +#define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK +#endif +/** + * @} + */ + +/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose + * @{ + */ +#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING +#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose + * @{ + */ +#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE +#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE +#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE +#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE + +#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE +#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE + +#define __DIV_SAMPLING16 UART_DIV_SAMPLING16 +#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16 +#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16 +#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16 + +#define __DIV_SAMPLING8 UART_DIV_SAMPLING8 +#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8 +#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8 +#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8 + +#define __DIV_LPUART UART_DIV_LPUART + +#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE +#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK + +/** + * @} + */ + + +/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose + * @{ + */ + +#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE +#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE + +#define USARTNACK_ENABLED USART_NACK_ENABLE +#define USARTNACK_DISABLED USART_NACK_DISABLE +/** + * @} + */ + +/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose + * @{ + */ +#define CFR_BASE WWDG_CFR_BASE + +/** + * @} + */ + +/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose + * @{ + */ +#define CAN_FilterFIFO0 CAN_FILTER_FIFO0 +#define CAN_FilterFIFO1 CAN_FILTER_FIFO1 +#define CAN_IT_RQCP0 CAN_IT_TME +#define CAN_IT_RQCP1 CAN_IT_TME +#define CAN_IT_RQCP2 CAN_IT_TME +#define INAK_TIMEOUT CAN_TIMEOUT_VALUE +#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE +#define CAN_TXSTATUS_FAILED ((uint8_t)0x00U) +#define CAN_TXSTATUS_OK ((uint8_t)0x01U) +#define CAN_TXSTATUS_PENDING ((uint8_t)0x02U) + +/** + * @} + */ + +/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose + * @{ + */ + +#define VLAN_TAG ETH_VLAN_TAG +#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD +#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD +#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD +#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK +#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK +#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK +#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK + +#define ETH_MMCCR 0x00000100U +#define ETH_MMCRIR 0x00000104U +#define ETH_MMCTIR 0x00000108U +#define ETH_MMCRIMR 0x0000010CU +#define ETH_MMCTIMR 0x00000110U +#define ETH_MMCTGFSCCR 0x0000014CU +#define ETH_MMCTGFMSCCR 0x00000150U +#define ETH_MMCTGFCR 0x00000168U +#define ETH_MMCRFCECR 0x00000194U +#define ETH_MMCRFAECR 0x00000198U +#define ETH_MMCRGUFCR 0x000001C4U + +#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ +#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ +#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ +#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ +#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to + the MAC transmitter) */ +#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from + MAC transmitter */ +#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus + or flushing the TxFIFO */ +#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status + of previous frame or IFG/backoff period to be over */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and + transmitting a Pause control frame (in full duplex mode) */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input + frame for transmission */ +#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */ +#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */ +#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control + de-activate threshold */ +#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control + activate threshold */ +#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */ +#if defined(STM32F1) +#else +#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */ +#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */ +#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status + (or time-stamp) */ +#endif +#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and + status */ +#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */ +#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */ +#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */ +#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */ +#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ +#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ + +#define ETH_TxPacketConfig ETH_TxPacketConfig_t /* Transmit Packet Configuration structure definition */ + +/** + * @} + */ + +/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR +#define DCMI_IT_OVF DCMI_IT_OVR +#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI +#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI + +#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop +#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop +#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop + +/** + * @} + */ + +#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ + || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ + || defined(STM32H7) +/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose + * @{ + */ +#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888 +#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 +#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 +#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555 +#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444 + +#define CM_ARGB8888 DMA2D_INPUT_ARGB8888 +#define CM_RGB888 DMA2D_INPUT_RGB888 +#define CM_RGB565 DMA2D_INPUT_RGB565 +#define CM_ARGB1555 DMA2D_INPUT_ARGB1555 +#define CM_ARGB4444 DMA2D_INPUT_ARGB4444 +#define CM_L8 DMA2D_INPUT_L8 +#define CM_AL44 DMA2D_INPUT_AL44 +#define CM_AL88 DMA2D_INPUT_AL88 +#define CM_L4 DMA2D_INPUT_L4 +#define CM_A8 DMA2D_INPUT_A8 +#define CM_A4 DMA2D_INPUT_A4 +/** + * @} + */ +#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */ + +#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ + || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ + || defined(STM32H7) || defined(STM32U5) +/** @defgroup DMA2D_Aliases DMA2D API Aliases + * @{ + */ +#define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort + for compatibility with legacy code */ +/** + * @} + */ + +#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 || STM32U5 */ + +/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback +/** + * @} + */ + +/** @defgroup HAL_DCACHE_Aliased_Functions HAL DCACHE Aliased Functions maintained for legacy purpose + * @{ + */ + +#if defined(STM32U5) +#define HAL_DCACHE_CleanInvalidateByAddr HAL_DCACHE_CleanInvalidByAddr +#define HAL_DCACHE_CleanInvalidateByAddr_IT HAL_DCACHE_CleanInvalidByAddr_IT +#endif /* STM32U5 */ + +/** + * @} + */ + +#if !defined(STM32F2) +/** @defgroup HASH_alias HASH API alias + * @{ + */ +#define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< Redirection for compatibility with legacy code */ +/** + * + * @} + */ +#endif /* STM32F2 */ +/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef +#define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef +#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish +#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish +#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish +#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish + +/*HASH Algorithm Selection*/ + +#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 +#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224 +#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256 +#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5 + +#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH +#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC + +#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY +#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY + +#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7) + +#define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt +#define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End +#define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT +#define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT + +#define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt +#define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End +#define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT +#define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT + +#define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt +#define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End +#define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT +#define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT + +#define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt +#define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End +#define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT +#define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT + +#endif /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */ +/** + * @} + */ + +/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode +#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode +#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode +#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode +#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode +#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode +#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\ + )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : \ + HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) +#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect +#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) +#if defined(STM32L0) +#else +#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) +#endif +#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) +#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\ + )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : \ + HAL_ADCEx_DisableVREFINTTempSensor()) +#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || \ + defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ) +#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode +#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode +#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode +#define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode +#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ || STM32H7B0xxQ */ + +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose + * @{ + */ +#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram +#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown +#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown +#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock +#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock +#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase +#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program + +/** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter +#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter +#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter +#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter + +#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) ((cmd == ENABLE)? \ + HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \ + HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) + +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || \ + defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || \ + defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1) +#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT +#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT +#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT +#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || + STM32L4 || STM32L5 || STM32G4 || STM32L1 */ +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || \ + defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1) +#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA +#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA +#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA +#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ + +#if defined(STM32F4) +#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT +#define HAL_FMPI2C_Master_Sequential_Receive_IT HAL_FMPI2C_Master_Seq_Receive_IT +#define HAL_FMPI2C_Slave_Sequential_Transmit_IT HAL_FMPI2C_Slave_Seq_Transmit_IT +#define HAL_FMPI2C_Slave_Sequential_Receive_IT HAL_FMPI2C_Slave_Seq_Receive_IT +#define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA +#define HAL_FMPI2C_Master_Sequential_Receive_DMA HAL_FMPI2C_Master_Seq_Receive_DMA +#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA +#define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA +#endif /* STM32F4 */ +/** + * @} + */ + +/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose + * @{ + */ + +#if defined(STM32G0) +#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD +#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD +#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD +#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler +#endif +#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD +#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg +#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown +#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor +#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg +#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown +#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor +#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler +#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD +#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler +#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback +#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive +#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive +#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC +#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC +#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM + +#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL +#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING +#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING +#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING +#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING +#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING +#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING + +#define CR_OFFSET_BB PWR_CR_OFFSET_BB +#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB +#define PMODE_BIT_NUMBER VOS_BIT_NUMBER +#define CR_PMODE_BB CR_VOS_BB + +#define DBP_BitNumber DBP_BIT_NUMBER +#define PVDE_BitNumber PVDE_BIT_NUMBER +#define PMODE_BitNumber PMODE_BIT_NUMBER +#define EWUP_BitNumber EWUP_BIT_NUMBER +#define FPDS_BitNumber FPDS_BIT_NUMBER +#define ODEN_BitNumber ODEN_BIT_NUMBER +#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER +#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER +#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER +#define BRE_BitNumber BRE_BIT_NUMBER + +#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL + +#if defined (STM32U5) +#define PWR_SRAM1_PAGE1_STOP_RETENTION PWR_SRAM1_PAGE1_STOP +#define PWR_SRAM1_PAGE2_STOP_RETENTION PWR_SRAM1_PAGE2_STOP +#define PWR_SRAM1_PAGE3_STOP_RETENTION PWR_SRAM1_PAGE3_STOP +#define PWR_SRAM1_PAGE4_STOP_RETENTION PWR_SRAM1_PAGE4_STOP +#define PWR_SRAM1_PAGE5_STOP_RETENTION PWR_SRAM1_PAGE5_STOP +#define PWR_SRAM1_PAGE6_STOP_RETENTION PWR_SRAM1_PAGE6_STOP +#define PWR_SRAM1_PAGE7_STOP_RETENTION PWR_SRAM1_PAGE7_STOP +#define PWR_SRAM1_PAGE8_STOP_RETENTION PWR_SRAM1_PAGE8_STOP +#define PWR_SRAM1_PAGE9_STOP_RETENTION PWR_SRAM1_PAGE9_STOP +#define PWR_SRAM1_PAGE10_STOP_RETENTION PWR_SRAM1_PAGE10_STOP +#define PWR_SRAM1_PAGE11_STOP_RETENTION PWR_SRAM1_PAGE11_STOP +#define PWR_SRAM1_PAGE12_STOP_RETENTION PWR_SRAM1_PAGE12_STOP +#define PWR_SRAM1_FULL_STOP_RETENTION PWR_SRAM1_FULL_STOP + +#define PWR_SRAM2_PAGE1_STOP_RETENTION PWR_SRAM2_PAGE1_STOP +#define PWR_SRAM2_PAGE2_STOP_RETENTION PWR_SRAM2_PAGE2_STOP +#define PWR_SRAM2_FULL_STOP_RETENTION PWR_SRAM2_FULL_STOP + +#define PWR_SRAM3_PAGE1_STOP_RETENTION PWR_SRAM3_PAGE1_STOP +#define PWR_SRAM3_PAGE2_STOP_RETENTION PWR_SRAM3_PAGE2_STOP +#define PWR_SRAM3_PAGE3_STOP_RETENTION PWR_SRAM3_PAGE3_STOP +#define PWR_SRAM3_PAGE4_STOP_RETENTION PWR_SRAM3_PAGE4_STOP +#define PWR_SRAM3_PAGE5_STOP_RETENTION PWR_SRAM3_PAGE5_STOP +#define PWR_SRAM3_PAGE6_STOP_RETENTION PWR_SRAM3_PAGE6_STOP +#define PWR_SRAM3_PAGE7_STOP_RETENTION PWR_SRAM3_PAGE7_STOP +#define PWR_SRAM3_PAGE8_STOP_RETENTION PWR_SRAM3_PAGE8_STOP +#define PWR_SRAM3_PAGE9_STOP_RETENTION PWR_SRAM3_PAGE9_STOP +#define PWR_SRAM3_PAGE10_STOP_RETENTION PWR_SRAM3_PAGE10_STOP +#define PWR_SRAM3_PAGE11_STOP_RETENTION PWR_SRAM3_PAGE11_STOP +#define PWR_SRAM3_PAGE12_STOP_RETENTION PWR_SRAM3_PAGE12_STOP +#define PWR_SRAM3_PAGE13_STOP_RETENTION PWR_SRAM3_PAGE13_STOP +#define PWR_SRAM3_FULL_STOP_RETENTION PWR_SRAM3_FULL_STOP + +#define PWR_SRAM4_FULL_STOP_RETENTION PWR_SRAM4_FULL_STOP + +#define PWR_SRAM5_PAGE1_STOP_RETENTION PWR_SRAM5_PAGE1_STOP +#define PWR_SRAM5_PAGE2_STOP_RETENTION PWR_SRAM5_PAGE2_STOP +#define PWR_SRAM5_PAGE3_STOP_RETENTION PWR_SRAM5_PAGE3_STOP +#define PWR_SRAM5_PAGE4_STOP_RETENTION PWR_SRAM5_PAGE4_STOP +#define PWR_SRAM5_PAGE5_STOP_RETENTION PWR_SRAM5_PAGE5_STOP +#define PWR_SRAM5_PAGE6_STOP_RETENTION PWR_SRAM5_PAGE6_STOP +#define PWR_SRAM5_PAGE7_STOP_RETENTION PWR_SRAM5_PAGE7_STOP +#define PWR_SRAM5_PAGE8_STOP_RETENTION PWR_SRAM5_PAGE8_STOP +#define PWR_SRAM5_PAGE9_STOP_RETENTION PWR_SRAM5_PAGE9_STOP +#define PWR_SRAM5_PAGE10_STOP_RETENTION PWR_SRAM5_PAGE10_STOP +#define PWR_SRAM5_PAGE11_STOP_RETENTION PWR_SRAM5_PAGE11_STOP +#define PWR_SRAM5_PAGE12_STOP_RETENTION PWR_SRAM5_PAGE12_STOP +#define PWR_SRAM5_PAGE13_STOP_RETENTION PWR_SRAM5_PAGE13_STOP +#define PWR_SRAM5_FULL_STOP_RETENTION PWR_SRAM5_FULL_STOP + +#define PWR_SRAM6_PAGE1_STOP_RETENTION PWR_SRAM6_PAGE1_STOP +#define PWR_SRAM6_PAGE2_STOP_RETENTION PWR_SRAM6_PAGE2_STOP +#define PWR_SRAM6_PAGE3_STOP_RETENTION PWR_SRAM6_PAGE3_STOP +#define PWR_SRAM6_PAGE4_STOP_RETENTION PWR_SRAM6_PAGE4_STOP +#define PWR_SRAM6_PAGE5_STOP_RETENTION PWR_SRAM6_PAGE5_STOP +#define PWR_SRAM6_PAGE6_STOP_RETENTION PWR_SRAM6_PAGE6_STOP +#define PWR_SRAM6_PAGE7_STOP_RETENTION PWR_SRAM6_PAGE7_STOP +#define PWR_SRAM6_PAGE8_STOP_RETENTION PWR_SRAM6_PAGE8_STOP +#define PWR_SRAM6_FULL_STOP_RETENTION PWR_SRAM6_FULL_STOP + + +#define PWR_ICACHE_FULL_STOP_RETENTION PWR_ICACHE_FULL_STOP +#define PWR_DCACHE1_FULL_STOP_RETENTION PWR_DCACHE1_FULL_STOP +#define PWR_DCACHE2_FULL_STOP_RETENTION PWR_DCACHE2_FULL_STOP +#define PWR_DMA2DRAM_FULL_STOP_RETENTION PWR_DMA2DRAM_FULL_STOP +#define PWR_PERIPHRAM_FULL_STOP_RETENTION PWR_PERIPHRAM_FULL_STOP +#define PWR_PKA32RAM_FULL_STOP_RETENTION PWR_PKA32RAM_FULL_STOP +#define PWR_GRAPHICPRAM_FULL_STOP_RETENTION PWR_GRAPHICPRAM_FULL_STOP +#define PWR_DSIRAM_FULL_STOP_RETENTION PWR_DSIRAM_FULL_STOP +#define PWR_JPEGRAM_FULL_STOP_RETENTION PWR_JPEGRAM_FULL_STOP + + +#define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_SRAM2_PAGE1_STANDBY +#define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_SRAM2_PAGE2_STANDBY +#define PWR_SRAM2_FULL_STANDBY_RETENTION PWR_SRAM2_FULL_STANDBY + +#define PWR_SRAM1_FULL_RUN_RETENTION PWR_SRAM1_FULL_RUN +#define PWR_SRAM2_FULL_RUN_RETENTION PWR_SRAM2_FULL_RUN +#define PWR_SRAM3_FULL_RUN_RETENTION PWR_SRAM3_FULL_RUN +#define PWR_SRAM4_FULL_RUN_RETENTION PWR_SRAM4_FULL_RUN +#define PWR_SRAM5_FULL_RUN_RETENTION PWR_SRAM5_FULL_RUN +#define PWR_SRAM6_FULL_RUN_RETENTION PWR_SRAM6_FULL_RUN + +#define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK +#endif + +/** + * @} + */ + +/** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose + * @{ + */ +#if defined(STM32H5) || defined(STM32WBA) +#define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey +#define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock +#define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock +#define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets +#endif /* STM32H5 || STM32WBA */ + +/** + * @} + */ + +/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT +#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback +#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt +#define HAL_TIM_DMAError TIM_DMAError +#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt +#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt +#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || \ + defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) +#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro +#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT +#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback +#define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent +#define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT +#define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA +#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */ +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback +/** + * @} + */ + +/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback +#define HAL_LTDC_Relaod HAL_LTDC_Reload +#define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig +#define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig +/** + * @} + */ + + +/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +/* Exported macros ------------------------------------------------------------*/ + +/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose + * @{ + */ +#define AES_IT_CC CRYP_IT_CC +#define AES_IT_ERR CRYP_IT_ERR +#define AES_FLAG_CCF CRYP_FLAG_CCF +/** + * @} + */ + +/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE +#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH +#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH +#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM +#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC +#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM +#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC +#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI +#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK +#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG +#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG +#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE +#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE +#define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE + +#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY +#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48 +#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS +#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER +#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER + +/** + * @} + */ + + +/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __ADC_ENABLE __HAL_ADC_ENABLE +#define __ADC_DISABLE __HAL_ADC_DISABLE +#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS +#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS +#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE +#define __ADC_IS_ENABLED ADC_IS_ENABLE +#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR +#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR +#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING +#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE + +#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION +#define __HAL_ADC_JSQR_RK ADC_JSQR_RK +#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT +#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR +#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION +#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE +#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS +#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS +#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM +#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT +#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS +#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN +#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ +#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET +#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET +#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL +#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL +#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET +#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET +#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD + +#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION +#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION +#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION +#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER +#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI +#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE +#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE +#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER +#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER +#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE + +#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT +#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT +#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL +#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM +#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET +#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE +#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE +#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER + +#define __HAL_ADC_SQR1 ADC_SQR1 +#define __HAL_ADC_SMPR1 ADC_SMPR1 +#define __HAL_ADC_SMPR2 ADC_SMPR2 +#define __HAL_ADC_SQR3_RK ADC_SQR3_RK +#define __HAL_ADC_SQR2_RK ADC_SQR2_RK +#define __HAL_ADC_SQR1_RK ADC_SQR1_RK +#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS +#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS +#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV +#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection +#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq +#define __HAL_ADC_JSQR ADC_JSQR + +#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL +#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS +#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF +#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT +#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS +#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN +#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR +#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ + +/** + * @} + */ + +/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT +#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT +#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT +#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE + +/** + * @} + */ + +/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1 +#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1 +#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2 +#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2 +#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3 +#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3 +#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4 +#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4 +#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5 +#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5 +#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6 +#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6 +#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7 +#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7 +#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8 +#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8 + +#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9 +#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9 +#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10 +#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10 +#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11 +#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11 +#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12 +#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12 +#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13 +#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13 +#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14 +#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14 +#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2 +#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2 + + +#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15 +#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15 +#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16 +#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16 +#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17 +#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17 +#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC +#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC +#if defined(STM32H7) +#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1 +#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1 +#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1 +#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1 +#else +#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG +#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG +#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG +#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG +#endif /* STM32H7 */ +#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT +#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT +#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT +#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT +#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT +#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT +#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1 +#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1 +#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1 +#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1 +#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2 +#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2 + +/** + * @} + */ + +/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined(STM32F3) +#define COMP_START __HAL_COMP_ENABLE +#define COMP_STOP __HAL_COMP_DISABLE +#define COMP_LOCK __HAL_COMP_LOCK + +#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || \ + defined(STM32F334x8) || defined(STM32F328xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP6_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) +# endif +# if defined(STM32F302xE) || defined(STM32F302xC) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP6_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP6_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) +# endif +# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP7_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \ + ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP7_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP7_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \ + ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) +# endif +# if defined(STM32F373xC) ||defined(STM32F378xx) +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP2_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) +# endif +#else +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP2_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) +#endif + +#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE + +#if defined(STM32L0) || defined(STM32L4) +/* Note: On these STM32 families, the only argument of this macro */ +/* is COMP_FLAG_LOCK. */ +/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */ +/* argument. */ +#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__)) +#endif +/** + * @} + */ + +#if defined(STM32L0) || defined(STM32L4) +/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is + done into HAL_COMP_Init() */ +#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is + done into HAL_COMP_Init() */ +/** + * @} + */ +#endif + +/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ + ((WAVE) == DAC_WAVE_NOISE)|| \ + ((WAVE) == DAC_WAVE_TRIANGLE)) + +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_WRPAREA IS_OB_WRPAREA +#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM +#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM +#define IS_TYPEERASE IS_FLASH_TYPEERASE +#define IS_NBSECTORS IS_FLASH_NBSECTORS +#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE + +/** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2 +#define __HAL_I2C_GENERATE_START I2C_GENERATE_START +#if defined(STM32F1) +#define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE +#else +#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE +#endif /* STM32F1 */ +#define __HAL_I2C_RISE_TIME I2C_RISE_TIME +#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD +#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST +#define __HAL_I2C_SPEED I2C_SPEED +#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE +#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ +#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS +#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE +#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ +#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB +#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB +#define __HAL_I2C_FREQRANGE I2C_FREQRANGE +/** + * @} + */ + +/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE +#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT + +#if defined(STM32H7) +#define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG +#endif + +/** + * @} + */ + +/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __IRDA_DISABLE __HAL_IRDA_DISABLE +#define __IRDA_ENABLE __HAL_IRDA_ENABLE + +#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE +#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION +#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE +#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION + +#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE + + +/** + * @} + */ + + +/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS +#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS +/** + * @} + */ + + +/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT +#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT +#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE + +/** + * @} + */ + + +/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose + * @{ + */ +#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD +#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX +#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX +#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX +#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX +#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L +#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H +#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM +#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES +#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX +#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT +#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION +#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET + +/** + * @} + */ + + +/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT +#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT +#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE +#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE +#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE +#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE +#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE +#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE +#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE +#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine +#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine +#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig +#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig +#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0) +#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT +#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT +#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE +#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2(); \ + HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); \ + } while(0) +#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2(); \ + HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); \ + } while(0) +#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention +#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention +#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 +#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2 +#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB +#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB + +#if defined (STM32F4) +#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT() +#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT() +#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() +#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG() +#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT() +#else +#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG +#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT +#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT +#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT +#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG +#endif /* STM32F4 */ +/** + * @} + */ + + +/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose + * @{ + */ + +#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI +#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI + +#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback +#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? \ + HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) + +#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE +#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE +#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE +#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE +#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET +#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET +#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE +#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE +#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET +#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET +#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE +#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE +#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE +#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE +#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET +#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET +#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE +#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE +#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET +#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET +#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE +#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE +#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE +#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE +#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET +#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET +#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE +#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE +#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE +#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE +#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET +#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET +#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE +#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE +#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET +#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET +#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET +#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET +#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET +#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET +#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET +#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET +#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET +#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET +#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET +#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET +#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET +#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET +#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE +#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE +#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET +#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET +#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE +#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE +#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE +#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE +#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET +#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET +#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE +#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE +#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET +#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET +#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE +#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE +#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET +#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET +#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE +#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE +#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE +#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE +#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET +#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET +#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE +#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE +#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET +#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET +#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE +#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE +#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE +#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE +#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET +#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET +#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE +#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE +#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET +#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET +#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE +#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE +#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE +#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE +#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET +#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET +#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE +#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE +#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET +#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET +#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE +#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE +#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE +#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE +#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET +#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET +#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE +#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE +#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE +#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE +#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET +#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET +#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE +#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE +#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE +#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE +#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET +#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET +#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE +#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE +#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET +#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET +#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE +#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE +#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE +#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE +#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE +#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE +#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE +#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE +#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE +#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE +#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET +#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET +#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE +#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE +#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET +#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET +#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE +#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE +#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE +#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE +#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE +#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE +#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET +#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET +#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE +#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE +#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE +#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE +#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE +#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE +#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET +#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET +#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE +#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE +#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE +#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE +#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET +#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET +#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE +#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE +#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE +#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE +#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET +#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET +#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE +#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE +#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE +#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE +#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET +#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET +#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE +#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE +#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE +#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE +#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET +#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET +#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE +#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE +#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE +#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE +#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET +#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET +#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE +#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE +#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE +#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE +#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET +#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET +#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE +#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE +#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE +#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE +#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET +#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET +#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE +#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE +#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE +#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE +#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET +#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET +#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE +#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE +#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE +#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE +#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET +#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET +#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE +#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE +#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE +#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE +#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET +#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET +#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE +#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE +#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE +#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE +#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET +#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET +#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE +#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE +#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE +#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE +#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET +#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET +#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE +#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE +#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE +#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE +#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET +#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET +#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE +#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE +#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE +#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE +#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET +#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET +#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE +#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE +#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE +#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE +#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET +#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET +#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE +#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE +#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE +#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE +#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET +#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET +#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE +#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE +#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE +#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE +#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET +#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET +#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE +#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE +#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE +#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE +#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET +#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET + +#if defined(STM32WB) +#define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE +#define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE +#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE +#define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET +#define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET +#define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED +#define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED +#define QSPI_IRQHandler QUADSPI_IRQHandler +#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */ + +#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE +#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE +#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE +#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE +#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET +#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET +#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE +#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE +#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE +#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE +#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET +#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET +#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE +#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE +#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE +#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE +#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET +#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET +#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE +#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE +#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE +#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE +#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE +#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE +#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET +#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET +#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE +#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE +#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE +#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE +#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET +#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET +#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE +#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE +#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE +#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE +#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET +#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET +#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE +#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE +#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE +#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE +#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET +#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET +#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE +#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE +#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE +#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE +#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE +#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE +#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE +#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE +#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE +#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE +#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET +#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET +#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE +#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE +#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE +#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE +#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET +#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET +#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE +#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE +#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE +#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE +#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET +#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET +#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE +#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE +#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET +#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET +#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE +#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE +#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET +#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET +#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE +#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE +#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET +#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET +#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE +#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE +#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET +#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET +#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE +#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE +#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET +#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET +#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE +#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE +#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE +#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE +#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET +#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET +#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE +#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE +#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE +#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE +#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET +#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET +#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE +#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE +#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE +#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE +#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET +#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET +#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE +#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE +#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE +#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE +#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET +#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET +#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE +#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE +#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE +#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE +#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET +#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET +#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE +#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE +#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE +#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE +#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET +#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET +#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE +#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE +#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE +#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE +#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET +#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET +#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE +#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE +#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE +#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE +#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET +#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET +#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE +#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE +#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE +#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE +#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET +#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET +#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE +#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE +#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE +#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE +#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET +#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET +#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE +#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE +#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET +#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET +#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE +#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE +#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE +#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE +#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET +#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET +#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE +#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE +#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE +#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE +#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET +#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET +#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE +#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE +#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE +#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE +#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET +#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET +#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE +#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE +#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE +#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE +#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET +#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET +#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE +#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE +#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE +#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE +#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET +#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET +#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE +#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE +#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE +#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE +#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET +#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET +#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE +#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE +#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE +#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE +#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET +#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET +#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE +#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE +#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE +#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE +#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET +#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET +#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE +#define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE +#define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET +#define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET +#define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE +#define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE +#define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET +#define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET +#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE +#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE +#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET +#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE +#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE +#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE +#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE +#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET + +#if defined(STM32H7) +#define __HAL_RCC_WWDG_CLK_DISABLE __HAL_RCC_WWDG1_CLK_DISABLE +#define __HAL_RCC_WWDG_CLK_ENABLE __HAL_RCC_WWDG1_CLK_ENABLE +#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE +#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE + +#define __HAL_RCC_WWDG_FORCE_RESET ((void)0U) /* Not available on the STM32H7*/ +#define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/ + + +#define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED +#define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED +#define RCC_SPI4CLKSOURCE_D2PCLK1 RCC_SPI4CLKSOURCE_D2PCLK2 +#define RCC_SPI5CLKSOURCE_D2PCLK1 RCC_SPI5CLKSOURCE_D2PCLK2 +#define RCC_SPI45CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK2 +#define RCC_SPI45CLKSOURCE_CDPCLK1 RCC_SPI45CLKSOURCE_CDPCLK2 +#define RCC_SPI45CLKSOURCE_PCLK1 RCC_SPI45CLKSOURCE_PCLK2 +#endif + +#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE +#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE +#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE +#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE +#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET +#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET + +#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE +#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE +#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET +#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET +#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE +#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE +#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE +#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE +#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET +#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET +#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE +#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE +#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE +#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE +#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE +#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE +#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET +#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET +#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE +#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE + +#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET +#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET +#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE +#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE +#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE +#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE +#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE +#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE +#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE +#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE +#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE +#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE +#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE +#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE +#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE +#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE +#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE +#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE +#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE +#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET +#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET +#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE +#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE +#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE +#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE +#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE +#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET +#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET +#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE +#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE +#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE +#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE +#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET +#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET +#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE +#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE +#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE +#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE +#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET +#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET +#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE +#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE +#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE +#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE +#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE +#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE +#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE +#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE +#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE +#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE +#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE +#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE +#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE +#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE +#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE +#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE +#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE +#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE +#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE +#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE +#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE +#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET +#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET +#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE +#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE +#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE +#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE +#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET +#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET +#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE +#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE +#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE +#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE +#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET +#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET +#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE +#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE +#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE +#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE +#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET +#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET +#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE +#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE +#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE +#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE +#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET +#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE +#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE +#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE +#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE +#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE +#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE +#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET +#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET +#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE +#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE +#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE +#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE +#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET +#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET +#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE +#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE +#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE +#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE +#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET +#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET +#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE +#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE +#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE +#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE +#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET +#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET +#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE +#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE +#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED +#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET +#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET +#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE +#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE +#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED +#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE +#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE +#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE +#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE +#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE +#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE +#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE +#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE +#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE +#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET +#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET +#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE +#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE +#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET +#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET +#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE +#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE +#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE +#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE +#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET +#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET +#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE +#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE + +/* alias define maintained for legacy */ +#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET +#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET + +#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE +#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE +#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE +#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE +#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE +#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE +#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE +#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE +#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE +#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE +#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE +#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE +#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE +#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE +#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE +#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE +#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE +#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE +#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE +#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE + +#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET +#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET +#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET +#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET +#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET +#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET +#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET +#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET +#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET +#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET +#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET +#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET +#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET +#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET +#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET +#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET +#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET +#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET +#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET +#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET + +#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED +#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED +#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED +#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED +#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED +#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED +#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED +#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED +#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED +#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED +#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED +#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED +#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED +#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED +#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED +#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED +#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED +#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED +#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED +#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED +#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED +#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED +#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED +#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED +#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED +#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED +#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED +#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED +#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED +#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED +#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED +#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED +#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED +#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED +#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED +#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED +#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED +#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED +#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED +#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED +#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED +#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED +#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED +#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED +#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED +#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED +#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED +#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED +#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED +#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED +#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED +#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED +#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED +#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED +#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED +#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED +#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED +#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED +#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED +#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED +#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED +#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED +#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED +#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED +#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED +#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED +#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED +#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED +#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED +#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED +#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED +#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED +#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED +#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED +#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED +#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED +#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED +#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED +#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED +#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED +#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED +#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED +#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED +#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED +#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED +#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED +#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED +#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED +#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED +#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED +#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED +#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED +#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED +#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED +#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED +#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED +#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED +#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED +#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED +#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED +#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED +#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED +#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED +#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED +#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED +#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED +#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED +#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED +#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED +#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED +#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED +#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED +#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED +#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED +#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED +#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED + +#if defined(STM32L1) +#define __HAL_RCC_CRYP_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE +#define __HAL_RCC_CRYP_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE +#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE +#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE +#define __HAL_RCC_CRYP_FORCE_RESET __HAL_RCC_AES_FORCE_RESET +#define __HAL_RCC_CRYP_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET +#endif /* STM32L1 */ + +#if defined(STM32F4) +#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET +#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET +#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE +#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE +#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE +#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE +#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED +#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED +#define Sdmmc1ClockSelection SdioClockSelection +#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO +#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48 +#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK +#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG +#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE +#endif + +#if defined(STM32F7) || defined(STM32L4) +#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET +#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET +#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE +#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE +#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE +#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE +#define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED +#define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED +#define SdioClockSelection Sdmmc1ClockSelection +#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1 +#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG +#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE +#endif + +#if defined(STM32F7) +#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48 +#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK +#endif + +#if defined(STM32H7) +#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET() +#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() + +#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE() +#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() +#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET() +#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET() +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() +#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() +#endif + +#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG +#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG + +#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE + +#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE +#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE +#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK +#define IS_RCC_HCLK_DIV IS_RCC_PCLK +#define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK + +#define RCC_IT_HSI14 RCC_IT_HSI14RDY + +#define RCC_IT_CSSLSE RCC_IT_LSECSS +#define RCC_IT_CSSHSE RCC_IT_CSS + +#define RCC_PLLMUL_3 RCC_PLL_MUL3 +#define RCC_PLLMUL_4 RCC_PLL_MUL4 +#define RCC_PLLMUL_6 RCC_PLL_MUL6 +#define RCC_PLLMUL_8 RCC_PLL_MUL8 +#define RCC_PLLMUL_12 RCC_PLL_MUL12 +#define RCC_PLLMUL_16 RCC_PLL_MUL16 +#define RCC_PLLMUL_24 RCC_PLL_MUL24 +#define RCC_PLLMUL_32 RCC_PLL_MUL32 +#define RCC_PLLMUL_48 RCC_PLL_MUL48 + +#define RCC_PLLDIV_2 RCC_PLL_DIV2 +#define RCC_PLLDIV_3 RCC_PLL_DIV3 +#define RCC_PLLDIV_4 RCC_PLL_DIV4 + +#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE +#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG +#define RCC_MCO_NODIV RCC_MCODIV_1 +#define RCC_MCO_DIV1 RCC_MCODIV_1 +#define RCC_MCO_DIV2 RCC_MCODIV_2 +#define RCC_MCO_DIV4 RCC_MCODIV_4 +#define RCC_MCO_DIV8 RCC_MCODIV_8 +#define RCC_MCO_DIV16 RCC_MCODIV_16 +#define RCC_MCO_DIV32 RCC_MCODIV_32 +#define RCC_MCO_DIV64 RCC_MCODIV_64 +#define RCC_MCO_DIV128 RCC_MCODIV_128 +#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK +#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI +#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE +#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK +#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI +#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14 +#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48 +#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE +#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK +#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK +#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 + +#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \ + defined(STM32WL) || defined(STM32C0) +#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE +#else +#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK +#endif + +#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1 +#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL +#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI +#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL +#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL +#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5 +#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2 +#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3 + +#define HSION_BitNumber RCC_HSION_BIT_NUMBER +#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER +#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER +#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER +#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER +#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER +#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER +#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER +#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER +#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER +#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER +#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER +#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER +#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER +#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER +#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER +#define LSION_BitNumber RCC_LSION_BIT_NUMBER +#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER +#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER +#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER +#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER +#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER +#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER +#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER +#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER +#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER +#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS +#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS +#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS +#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS +#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE +#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE + +#define CR_HSION_BB RCC_CR_HSION_BB +#define CR_CSSON_BB RCC_CR_CSSON_BB +#define CR_PLLON_BB RCC_CR_PLLON_BB +#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB +#define CR_MSION_BB RCC_CR_MSION_BB +#define CSR_LSION_BB RCC_CSR_LSION_BB +#define CSR_LSEON_BB RCC_CSR_LSEON_BB +#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB +#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB +#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB +#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB +#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB +#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB +#define CR_HSEON_BB RCC_CR_HSEON_BB +#define CSR_RMVF_BB RCC_CSR_RMVF_BB +#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB +#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB + +#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE +#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE +#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE +#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE +#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE + +#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT + +#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN +#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF + +#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48 +#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ +#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP +#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ +#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE +#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48 + +#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE +#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE +#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED +#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED +#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET +#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET +#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE +#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE +#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED +#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED +#define DfsdmClockSelection Dfsdm1ClockSelection +#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1 +#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK +#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG +#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE +#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 +#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 +#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 + +#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1 +#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2 +#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1 +#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2 +#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2 +#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 +#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 +#if defined(STM32U5) +#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL +#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL +#define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE +#define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE +#define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE +#define __HAL_RCC_AHB21_CLK_Disable_Clear __HAL_RCC_AHB2_1_CLK_ENABLE +#define __HAL_RCC_AHB22_CLK_Disable_Clear __HAL_RCC_AHB2_2_CLK_ENABLE +#define __HAL_RCC_AHB3_CLK_Disable_Clear __HAL_RCC_AHB3_CLK_ENABLE +#define __HAL_RCC_APB1_CLK_Disable_Clear __HAL_RCC_APB1_CLK_ENABLE +#define __HAL_RCC_APB2_CLK_Disable_Clear __HAL_RCC_APB2_CLK_ENABLE +#define __HAL_RCC_APB3_CLK_Disable_Clear __HAL_RCC_APB3_CLK_ENABLE +#define IS_RCC_MSIPLLModeSelection IS_RCC_MSIPLLMODE_SELECT +#define RCC_PERIPHCLK_CLK48 RCC_PERIPHCLK_ICLK +#define RCC_CLK48CLKSOURCE_HSI48 RCC_ICLK_CLKSOURCE_HSI48 +#define RCC_CLK48CLKSOURCE_PLL2 RCC_ICLK_CLKSOURCE_PLL2 +#define RCC_CLK48CLKSOURCE_PLL1 RCC_ICLK_CLKSOURCE_PLL1 +#define RCC_CLK48CLKSOURCE_MSIK RCC_ICLK_CLKSOURCE_MSIK +#define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE +#define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE +#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED +#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED +#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET +#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET +#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE +#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE +#define __HAL_RCC_GET_CLK48_SOURCE __HAL_RCC_GET_ICLK_SOURCE +#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE +#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE +#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG +#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE +#endif /* STM32U5 */ + +#if defined(STM32H5) +#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE +#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE +#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG +#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE + +#define RCC_PLLSOURCE_NONE RCC_PLL1_SOURCE_NONE +#define RCC_PLLSOURCE_HSI RCC_PLL1_SOURCE_HSI +#define RCC_PLLSOURCE_CSI RCC_PLL1_SOURCE_CSI +#define RCC_PLLSOURCE_HSE RCC_PLL1_SOURCE_HSE +#define RCC_PLLVCIRANGE_0 RCC_PLL1_VCIRANGE_0 +#define RCC_PLLVCIRANGE_1 RCC_PLL1_VCIRANGE_1 +#define RCC_PLLVCIRANGE_2 RCC_PLL1_VCIRANGE_2 +#define RCC_PLLVCIRANGE_3 RCC_PLL1_VCIRANGE_3 +#define RCC_PLL1VCOWIDE RCC_PLL1_VCORANGE_WIDE +#define RCC_PLL1VCOMEDIUM RCC_PLL1_VCORANGE_MEDIUM + +#define IS_RCC_PLLSOURCE IS_RCC_PLL1_SOURCE +#define IS_RCC_PLLRGE_VALUE IS_RCC_PLL1_VCIRGE_VALUE +#define IS_RCC_PLLVCORGE_VALUE IS_RCC_PLL1_VCORGE_VALUE +#define IS_RCC_PLLCLOCKOUT_VALUE IS_RCC_PLL1_CLOCKOUT_VALUE +#define IS_RCC_PLL_FRACN_VALUE IS_RCC_PLL1_FRACN_VALUE +#define IS_RCC_PLLM_VALUE IS_RCC_PLL1_DIVM_VALUE +#define IS_RCC_PLLN_VALUE IS_RCC_PLL1_MULN_VALUE +#define IS_RCC_PLLP_VALUE IS_RCC_PLL1_DIVP_VALUE +#define IS_RCC_PLLQ_VALUE IS_RCC_PLL1_DIVQ_VALUE +#define IS_RCC_PLLR_VALUE IS_RCC_PLL1_DIVR_VALUE + +#define __HAL_RCC_PLL_ENABLE __HAL_RCC_PLL1_ENABLE +#define __HAL_RCC_PLL_DISABLE __HAL_RCC_PLL1_DISABLE +#define __HAL_RCC_PLL_FRACN_ENABLE __HAL_RCC_PLL1_FRACN_ENABLE +#define __HAL_RCC_PLL_FRACN_DISABLE __HAL_RCC_PLL1_FRACN_DISABLE +#define __HAL_RCC_PLL_CONFIG __HAL_RCC_PLL1_CONFIG +#define __HAL_RCC_PLL_PLLSOURCE_CONFIG __HAL_RCC_PLL1_PLLSOURCE_CONFIG +#define __HAL_RCC_PLL_DIVM_CONFIG __HAL_RCC_PLL1_DIVM_CONFIG +#define __HAL_RCC_PLL_FRACN_CONFIG __HAL_RCC_PLL1_FRACN_CONFIG +#define __HAL_RCC_PLL_VCIRANGE __HAL_RCC_PLL1_VCIRANGE +#define __HAL_RCC_PLL_VCORANGE __HAL_RCC_PLL1_VCORANGE +#define __HAL_RCC_GET_PLL_OSCSOURCE __HAL_RCC_GET_PLL1_OSCSOURCE +#define __HAL_RCC_PLLCLKOUT_ENABLE __HAL_RCC_PLL1_CLKOUT_ENABLE +#define __HAL_RCC_PLLCLKOUT_DISABLE __HAL_RCC_PLL1_CLKOUT_DISABLE +#define __HAL_RCC_GET_PLLCLKOUT_CONFIG __HAL_RCC_GET_PLL1_CLKOUT_CONFIG + +#define __HAL_RCC_PLL2FRACN_ENABLE __HAL_RCC_PLL2_FRACN_ENABLE +#define __HAL_RCC_PLL2FRACN_DISABLE __HAL_RCC_PLL2_FRACN_DISABLE +#define __HAL_RCC_PLL2CLKOUT_ENABLE __HAL_RCC_PLL2_CLKOUT_ENABLE +#define __HAL_RCC_PLL2CLKOUT_DISABLE __HAL_RCC_PLL2_CLKOUT_DISABLE +#define __HAL_RCC_PLL2FRACN_CONFIG __HAL_RCC_PLL2_FRACN_CONFIG +#define __HAL_RCC_GET_PLL2CLKOUT_CONFIG __HAL_RCC_GET_PLL2_CLKOUT_CONFIG + +#define __HAL_RCC_PLL3FRACN_ENABLE __HAL_RCC_PLL3_FRACN_ENABLE +#define __HAL_RCC_PLL3FRACN_DISABLE __HAL_RCC_PLL3_FRACN_DISABLE +#define __HAL_RCC_PLL3CLKOUT_ENABLE __HAL_RCC_PLL3_CLKOUT_ENABLE +#define __HAL_RCC_PLL3CLKOUT_DISABLE __HAL_RCC_PLL3_CLKOUT_DISABLE +#define __HAL_RCC_PLL3FRACN_CONFIG __HAL_RCC_PLL3_FRACN_CONFIG +#define __HAL_RCC_GET_PLL3CLKOUT_CONFIG __HAL_RCC_GET_PLL3_CLKOUT_CONFIG + +#define RCC_PLL2VCIRANGE_0 RCC_PLL2_VCIRANGE_0 +#define RCC_PLL2VCIRANGE_1 RCC_PLL2_VCIRANGE_1 +#define RCC_PLL2VCIRANGE_2 RCC_PLL2_VCIRANGE_2 +#define RCC_PLL2VCIRANGE_3 RCC_PLL2_VCIRANGE_3 + +#define RCC_PLL2VCOWIDE RCC_PLL2_VCORANGE_WIDE +#define RCC_PLL2VCOMEDIUM RCC_PLL2_VCORANGE_MEDIUM + +#define RCC_PLL2SOURCE_NONE RCC_PLL2_SOURCE_NONE +#define RCC_PLL2SOURCE_HSI RCC_PLL2_SOURCE_HSI +#define RCC_PLL2SOURCE_CSI RCC_PLL2_SOURCE_CSI +#define RCC_PLL2SOURCE_HSE RCC_PLL2_SOURCE_HSE + +#define RCC_PLL3VCIRANGE_0 RCC_PLL3_VCIRANGE_0 +#define RCC_PLL3VCIRANGE_1 RCC_PLL3_VCIRANGE_1 +#define RCC_PLL3VCIRANGE_2 RCC_PLL3_VCIRANGE_2 +#define RCC_PLL3VCIRANGE_3 RCC_PLL3_VCIRANGE_3 + +#define RCC_PLL3VCOWIDE RCC_PLL3_VCORANGE_WIDE +#define RCC_PLL3VCOMEDIUM RCC_PLL3_VCORANGE_MEDIUM + +#define RCC_PLL3SOURCE_NONE RCC_PLL3_SOURCE_NONE +#define RCC_PLL3SOURCE_HSI RCC_PLL3_SOURCE_HSI +#define RCC_PLL3SOURCE_CSI RCC_PLL3_SOURCE_CSI +#define RCC_PLL3SOURCE_HSE RCC_PLL3_SOURCE_HSE + + +#endif /* STM32H5 */ + +/** + * @} + */ + +/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose + * @{ + */ +#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) + +/** + * @} + */ + +/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \ + defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \ + defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) +#else +#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG +#endif +#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT +#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT + +#if defined (STM32F1) +#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() + +#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT() + +#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT() + +#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG() + +#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() +#else +#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) +#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) +#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) +#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) +#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \ + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) +#endif /* STM32F1 */ + +#if defined (STM32F0) || defined (STM32F2) || defined (STM32F3) || defined (STM32F4) || defined (STM32F7) || \ + defined (STM32H7) || \ + defined (STM32L0) || defined (STM32L1) || \ + defined (STM32WB) +#define __HAL_RTC_TAMPER_GET_IT __HAL_RTC_TAMPER_GET_FLAG +#endif + +#define IS_ALARM IS_RTC_ALARM +#define IS_ALARM_MASK IS_RTC_ALARM_MASK +#define IS_TAMPER IS_RTC_TAMPER +#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE +#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER +#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT +#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE +#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION +#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE +#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ +#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION +#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER +#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK +#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER + +#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE +#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE + +#if defined (STM32H5) +#define __HAL_RCC_RTCAPB_CLK_ENABLE __HAL_RCC_RTC_CLK_ENABLE +#define __HAL_RCC_RTCAPB_CLK_DISABLE __HAL_RCC_RTC_CLK_DISABLE +#endif /* STM32H5 */ + +/** + * @} + */ + +/** @defgroup HAL_SD_Aliased_Macros HAL SD/MMC Aliased Macros maintained for legacy purpose + * @{ + */ + +#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE +#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS + +#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32L1) +#define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE +#define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE +#define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE + +#define SDMMC_NSpeed_CLK_DIV SDMMC_NSPEED_CLK_DIV +#define SDMMC_HSpeed_CLK_DIV SDMMC_HSPEED_CLK_DIV +#endif + +#if defined(STM32F4) || defined(STM32F2) +#define SD_SDMMC_DISABLED SD_SDIO_DISABLED +#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY +#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED +#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION +#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND +#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT +#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED +#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE +#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE +#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE +#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL +#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT +#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT +#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG +#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG +#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT +#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT +#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS +#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT +#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND +/* alias CMSIS */ +#define SDMMC1_IRQn SDIO_IRQn +#define SDMMC1_IRQHandler SDIO_IRQHandler +#endif + +#if defined(STM32F7) || defined(STM32L4) +#define SD_SDIO_DISABLED SD_SDMMC_DISABLED +#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY +#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED +#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION +#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND +#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT +#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED +#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE +#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE +#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE +#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE +#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT +#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT +#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG +#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG +#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT +#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT +#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS +#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT +#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND +/* alias CMSIS for compatibilities */ +#define SDIO_IRQn SDMMC1_IRQn +#define SDIO_IRQHandler SDMMC1_IRQHandler +#endif + +#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7) +#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef +#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef +#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef +#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef +#endif + +#if defined(STM32H7) || defined(STM32L5) +#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback +#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback +#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback +#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback +#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback +#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback +#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback +#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback +#define HAL_SD_DriveTransciver_1_8V_Callback HAL_SD_DriveTransceiver_1_8V_Callback +#endif +/** + * @} + */ + +/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT +#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT +#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE +#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE +#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE +#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE + +#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE +#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE + +#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE + +/** + * @} + */ + +/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1 +#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2 +#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START +#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH +#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR +#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE +#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE +#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_SPI_1LINE_TX SPI_1LINE_TX +#define __HAL_SPI_1LINE_RX SPI_1LINE_RX +#define __HAL_SPI_RESET_CRC SPI_RESET_CRC + +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE +#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION +#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE +#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION + +#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD + +#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE +#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE + +/** + * @} + */ + + +/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT +#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT +#define __USART_ENABLE __HAL_USART_ENABLE +#define __USART_DISABLE __HAL_USART_DISABLE + +#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE +#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE + +#if defined(STM32F0) || defined(STM32F3) || defined(STM32F7) +#define USART_OVERSAMPLING_16 0x00000000U +#define USART_OVERSAMPLING_8 USART_CR1_OVER8 + +#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \ + ((__SAMPLING__) == USART_OVERSAMPLING_8)) +#endif /* STM32F0 || STM32F3 || STM32F7 */ +/** + * @} + */ + +/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose + * @{ + */ +#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE + +#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE +#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE +#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE +#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE + +#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE +#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE +#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE +#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE + +#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE + +#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE +#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT + +#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE +#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT + +#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup +#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup + +#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo +#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE +#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE + +#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE +#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT + +#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE + +#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN +#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER +#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER +#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER +#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD +#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD +#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION +#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION +#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER +#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER +#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE +#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE + +#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 +/** + * @} + */ + +/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT +#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT +#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG +#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER +#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER +#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER + +#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE +#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE +#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE +/** + * @} + */ + +/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_LTDC_LAYER LTDC_LAYER +#define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG +/** + * @} + */ + +/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose + * @{ + */ +#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE +#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE +#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE +#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE +#define SAI_STREOMODE SAI_STEREOMODE +#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY +#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL +#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL +#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL +#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL +#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL +#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE +#define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1 +#define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE +/** + * @} + */ + +/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined(STM32H7) +#define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow +#define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT +#define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA +#endif +/** + * @} + */ + +/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose + * @{ + */ +#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3) +#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT +#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA +#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart +#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT +#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA +#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop +#endif +/** + * @} + */ + +/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7) +#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE +#endif /* STM32L4 || STM32F4 || STM32F7 */ +/** + * @} + */ + +/** @defgroup HAL_Generic_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined (STM32F7) +#define ART_ACCLERATOR_ENABLE ART_ACCELERATOR_ENABLE +#endif /* STM32F7 */ +/** + * @} + */ + +/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32_HAL_LEGACY */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32_assert_template.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32_assert_template.h new file mode 100644 index 0000000000..1858dca91d --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32_assert_template.h @@ -0,0 +1,53 @@ +/** + ****************************************************************************** + * @file stm32_assert.h + * @author MCD Application Team + * @brief STM32 assert template file. + * This file should be copied to the application folder and renamed + * to stm32_assert.h. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32_ASSERT_H +#define __STM32_ASSERT_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Includes ------------------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ +#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ +void assert_failed(uint8_t *file, uint32_t line); +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32_ASSERT_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal.h new file mode 100644 index 0000000000..6e351d0168 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal.h @@ -0,0 +1,552 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal.h + * @author MCD Application Team + * @brief This file contains all the functions prototypes for the HAL + * module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32WBAxx_HAL_H +#define __STM32WBAxx_HAL_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal_conf.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @addtogroup HAL + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup HAL_Exported_Types HAL Exported Types + * @{ + */ + +/** @defgroup HAL_TICK_FREQ Tick Frequency + * @{ + */ +typedef enum +{ + HAL_TICK_FREQ_10HZ = 100U, + HAL_TICK_FREQ_100HZ = 10U, + HAL_TICK_FREQ_1KHZ = 1U, + HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ +} HAL_TickFreqTypeDef; +/** + * @} + */ + +/** + * @} + */ + +/* Exported variables --------------------------------------------------------*/ +/** @defgroup HAL_Exported_Variables HAL Exported Variables + * @{ + */ +extern __IO uint32_t uwTick; +extern uint32_t uwTickPrio; +extern HAL_TickFreqTypeDef uwTickFreq; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup HAL_Exported_Constants HAL Exported Constants + * @{ + */ + +/** + * @brief STM32WBAxx HAL Driver version number + */ +#define __STM32WBAxx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ +#define __STM32WBAxx_HAL_VERSION_SUB1 (0x02U) /*!< [23:16] sub1 version */ +#define __STM32WBAxx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ +#define __STM32WBAxx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ +#define __STM32WBAxx_HAL_VERSION ((__STM32WBAxx_HAL_VERSION_MAIN << 24U)\ + |(__STM32WBAxx_HAL_VERSION_SUB1 << 16U)\ + |(__STM32WBAxx_HAL_VERSION_SUB2 << 8U )\ + |(__STM32WBAxx_HAL_VERSION_RC)) + +/** + * @} + */ + +/** @defgroup REV_ID device revision ID + * @{ + */ +#define REV_ID_A 0x1000U /*!< STM32WBA_2 rev.A */ +#define REV_ID_B 0x2000U /*!< STM32WBA_2 rev.B */ +/** + * @} + */ + +/** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants + * @{ + */ + +/** @defgroup SYSCFG_FPU_Interrupts FPU Interrupts + * @{ + */ +#define SYSCFG_IT_FPU_IOC SYSCFG_FPUIMR_FPU_IE_0 /*!< Floating Point Unit Invalid operation Interrupt */ +#define SYSCFG_IT_FPU_DZC SYSCFG_FPUIMR_FPU_IE_1 /*!< Floating Point Unit Divide-by-zero Interrupt */ +#define SYSCFG_IT_FPU_UFC SYSCFG_FPUIMR_FPU_IE_2 /*!< Floating Point Unit Underflow Interrupt */ +#define SYSCFG_IT_FPU_OFC SYSCFG_FPUIMR_FPU_IE_3 /*!< Floating Point Unit Overflow Interrupt */ +#define SYSCFG_IT_FPU_IDC SYSCFG_FPUIMR_FPU_IE_4 /*!< Floating Point Unit Input denormal Interrupt */ +#define SYSCFG_IT_FPU_IXC SYSCFG_FPUIMR_FPU_IE_5 /*!< Floating Point Unit Inexact Interrupt */ +#define SYSCFG_IT_FPU_ALL (SYSCFG_IT_FPU_IOC|SYSCFG_IT_FPU_DZC|SYSCFG_IT_FPU_UFC|SYSCFG_IT_FPU_OFC|SYSCFG_IT_FPU_IDC|SYSCFG_IT_FPU_IXC) /*!< All */ + +/** + * @} + */ + +/** @defgroup SYSCFG_Flags_Definition Flags + * @{ + */ + +#define SYSCFG_FLAG_MCLR SYSCFG_MESR_MCLR /*!< Device memories erase status */ +#define SYSCFG_FLAG_IPMEE SYSCFG_MESR_IPMEE /*!< ICACHE and PKA SRAM erase status */ + +/** + * @} + */ + +/** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO + * @{ + */ + +/** @brief Fast-mode Plus driving capability on a specific GPIO + */ +#define SYSCFG_FASTMODEPLUS_PA6 SYSCFG_CFGR1_PA6_FMP /*!< Enable Fast-mode Plus on PA6 */ +#define SYSCFG_FASTMODEPLUS_PA7 SYSCFG_CFGR1_PA7_FMP /*!< Enable Fast-mode Plus on PA7 */ +#define SYSCFG_FASTMODEPLUS_PA15 SYSCFG_CFGR1_PA15_FMP /*!< Enable Fast-mode Plus on PA15 */ +#define SYSCFG_FASTMODEPLUS_PB3 SYSCFG_CFGR1_PB3_FMP /*!< Enable Fast-mode Plus on PB3 */ +#define SYSCFG_FASTMODEPLUS_ALL (SYSCFG_FASTMODEPLUS_PA6|SYSCFG_FASTMODEPLUS_PA7|SYSCFG_FASTMODEPLUS_PA15|SYSCFG_FASTMODEPLUS_PB3) /*!< All */ + +/** + * @} + */ + +/** @defgroup SYSCFG_Lock_items SYSCFG Lock items + * @brief SYSCFG items to set lock on + * @{ + */ +#define SYSCFG_MPU_NSEC SYSCFG_CNSLCKR_LOCKNSMPU /*!< Non-secure MPU lock (privileged secure or non-secure only) */ +#define SYSCFG_VTOR_NSEC SYSCFG_CNSLCKR_LOCKNSVTOR /*!< Non-secure VTOR lock (privileged secure or non-secure only) */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define SYSCFG_SAU (SYSCFG_CSLCKR_LOCKSAU << 16U) /*!< SAU lock (privileged secure code only) */ +#define SYSCFG_MPU_SEC (SYSCFG_CSLCKR_LOCKSMPU << 16U) /*!< Secure MPU lock (privileged secure code only) */ +#define SYSCFG_VTOR_AIRCR_SEC (SYSCFG_CSLCKR_LOCKSVTAIRCR << 16U) /*!< VTOR_S and AIRCR lock (privileged secure code only) */ +#define SYSCFG_LOCK_ALL (SYSCFG_MPU_NSEC|SYSCFG_VTOR_NSEC|SYSCFG_SAU|SYSCFG_MPU_SEC|SYSCFG_VTOR_AIRCR_SEC) /*!< All */ +#else +#define SYSCFG_LOCK_ALL (SYSCFG_MPU_NSEC|SYSCFG_VTOR_NSEC) /*!< All (privileged secure or non-secure only) */ +#endif /* __ARM_FEATURE_CMSE */ +/** + * @} + */ + +#if defined (SYSCFG_SECCFGR_SYSCFGSEC) +/** @defgroup SYSCFG_Attributes_items SYSCFG Attributes items + * @brief SYSCFG items to configure secure or non-secure attributes on + * @{ + */ +#define SYSCFG_CLK SYSCFG_SECCFGR_SYSCFGSEC /*!< SYSCFG clock control */ +#define SYSCFG_CLASSB SYSCFG_SECCFGR_CLASSBSEC /*!< Class B */ +#define SYSCFG_FPU SYSCFG_SECCFGR_FPUSEC /*!< FPU */ +#define SYSCFG_ALL (SYSCFG_CLK | SYSCFG_CLASSB | SYSCFG_FPU) /*!< All */ +/** + * @} + */ +#endif /* SYSCFG_SECCFGR_SYSCFGSEC */ + +/** @defgroup SYSCFG_attributes SYSCFG attributes + * @brief SYSCFG secure or non-secure attributes + * @{ + */ +#define SYSCFG_SEC 0x00000001U /*!< Secure attribute */ +#define SYSCFG_NSEC 0x00000000U /*!< Non-secure attribute */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ + +/** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros + * @{ + */ + +/** @brief Freeze/Unfreeze Peripherals in Debug mode + */ +#if defined(DBGMCU_APB1LFZR_DBG_TIM2_STOP) +#define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1LFZR, DBGMCU_APB1LFZR_DBG_TIM2_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1LFZR, DBGMCU_APB1LFZR_DBG_TIM2_STOP) +#endif /* DBGMCU_APB1LFZR_DBG_TIM2_STOP */ + +#if defined(DBGMCU_APB1LFZR_DBG_TIM3_STOP) +#define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1LFZR, DBGMCU_APB1LFZR_DBG_TIM3_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1LFZR, DBGMCU_APB1LFZR_DBG_TIM3_STOP) +#endif /* DBGMCU_APB1LFZR_DBG_TIM3_STOP */ + +#if defined(DBGMCU_APB1LFZR_DBG_WWDG_STOP) +#define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1LFZR, DBGMCU_APB1LFZR_DBG_WWDG_STOP) +#define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1LFZR, DBGMCU_APB1LFZR_DBG_WWDG_STOP) +#endif /* DBGMCU_APB1LFZR_DBG_WWDG_STOP */ + +#if defined(DBGMCU_APB1LFZR_DBG_IWDG_STOP) +#define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1LFZR, DBGMCU_APB1LFZR_DBG_IWDG_STOP) +#define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1LFZR, DBGMCU_APB1LFZR_DBG_IWDG_STOP) +#endif /* DBGMCU_APB1LFZR_DBG_IWDG_STOP */ + +#if defined(DBGMCU_APB1LFZR_DBG_I2C1_STOP) +#define __HAL_DBGMCU_FREEZE_I2C1() SET_BIT(DBGMCU->APB1LFZR, DBGMCU_APB1LFZR_DBG_I2C1_STOP) +#define __HAL_DBGMCU_UNFREEZE_I2C1() CLEAR_BIT(DBGMCU->APB1LFZR, DBGMCU_APB1LFZR_DBG_I2C1_STOP) +#endif /* DBGMCU_APB1LFZR_DBG_I2C1_STOP */ + +#if defined(DBGMCU_APB1HFZR_DBG_LPTIM2_STOP) +#define __HAL_DBGMCU_FREEZE_LPTIM2() SET_BIT(DBGMCU->APB1HFZR, DBGMCU_APB1HFZR_DBG_LPTIM2_STOP) +#define __HAL_DBGMCU_UNFREEZE_LPTIM2() CLEAR_BIT(DBGMCU->APB1HFZR, DBGMCU_APB1HFZR_DBG_LPTIM2_STOP) +#endif /* DBGMCU_APB1HFZR_DBG_LPTIM2_STOP */ + +#if defined(DBGMCU_APB2FZR_DBG_TIM1_STOP) +#define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM1_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM1_STOP) +#endif /* DBGMCU_APB2FZR_DBG_TIM1_STOP */ + +#if defined(DBGMCU_APB2FZR_DBG_TIM16_STOP) +#define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM16_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM16_STOP) +#endif /* DBGMCU_APB2FZR_DBG_TIM16_STOP */ + +#if defined(DBGMCU_APB2FZR_DBG_TIM17_STOP) +#define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM17_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM17_STOP) +#endif /* DBGMCU_APB2FZR_DBG_TIM17_STOP */ + +#if defined(DBGMCU_APB7FZR_DBG_I2C3_STOP) +#define __HAL_DBGMCU_FREEZE_I2C3() SET_BIT(DBGMCU->APB7FZR, DBGMCU_APB7FZR_DBG_I2C3_STOP) +#define __HAL_DBGMCU_UNFREEZE_I2C3() CLEAR_BIT(DBGMCU->APB7FZR, DBGMCU_APB7FZR_DBG_I2C3_STOP) +#endif /* DBGMCU_APB7FZR_DBG_I2C3_STOP */ + +#if defined(DBGMCU_APB7FZR_DBG_LPTIM1_STOP) +#define __HAL_DBGMCU_FREEZE_LPTIM1() SET_BIT(DBGMCU->APB7FZR, DBGMCU_APB7FZR_DBG_LPTIM1_STOP) +#define __HAL_DBGMCU_UNFREEZE_LPTIM1() CLEAR_BIT(DBGMCU->APB7FZR, DBGMCU_APB7FZR_DBG_LPTIM1_STOP) +#endif /* DBGMCU_APB7FZR_DBG_LPTIM1_STOP */ + +#if defined(DBGMCU_APB7FZR_DBG_RTC_STOP) +#define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB7FZR, DBGMCU_APB7FZR_DBG_RTC_STOP) +#define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB7FZR, DBGMCU_APB7FZR_DBG_RTC_STOP) +#endif /* DBGMCU_APB7FZR_DBG_RTC_STOP */ + +#if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA0() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA0() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP) +#endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP */ + +#if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA1() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA1() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP) +#endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP */ + +#if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA2() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA2() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP) +#endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP */ + +#if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA3() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA3() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP) +#endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP */ + +#if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA4() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA4() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP) +#endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP */ + +#if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA5() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA5() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP) +#endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP */ + +#if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA6() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA6() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP) +#endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP */ + +#if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP) +#define __HAL_DBGMCU_FREEZE_GPDMA7() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP) +#define __HAL_DBGMCU_UNFREEZE_GPDMA7() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP) +#endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP */ + +/** + * @} + */ + +/** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros + * @{ + */ + +/** @brief Floating Point Unit interrupt enable/disable macros + * @param __INTERRUPT__: This parameter can be a value of @ref SYSCFG_FPU_Interrupts + */ +#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\ + SET_BIT(SYSCFG->FPUIMR, (__INTERRUPT__));\ + }while(0) + +#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\ + CLEAR_BIT(SYSCFG->FPUIMR, (__INTERRUPT__));\ + }while(0) + +/** @brief SYSCFG Break ECC lock. + * Enable and lock the connection of Flash ECC error connection to TIM1/8/15/16/17 Break input. + * @note The selected configuration is locked and can be unlocked only by system reset. + */ +#define __HAL_SYSCFG_BREAK_ECC_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL) + +/** @brief SYSCFG Break Cortex-M33 Lockup lock. + * Enable and lock the connection of Cortex-M33 LOCKUP (Hardfault) output to TIM1/8/15/16/17 Break input. + * @note The selected configuration is locked and can be unlocked only by system reset. + */ +#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL) + +/** @brief SYSCFG Break PVD lock. + * Enable and lock the PVD connection to Timer1/8/15/16/17 Break input, as well as the PVDE and PLS[2:0] in + * the PWR_CR2 register. + * @note The selected configuration is locked and can be unlocked only by system reset. + */ +#define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL) + +/** @brief SYSCFG Break SRAM2 parity lock. + * Enable and lock the SRAM2 parity error signal connection to TIM1/8/15/16/17 Break input. + * @note The selected configuration is locked and can be unlocked by system reset. + */ +#define __HAL_SYSCFG_BREAK_SRAM2PARITY_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPL) + +/** @brief Check SYSCFG flag is set or not. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref SYSCFG_FLAG_MCLR Device memories erase status flag + * @arg @ref SYSCFG_FLAG_IPMEE ICACHE and PKA SRAM erase status flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_SYSCFG_GET_FLAG(__FLAG__) (READ_BIT(SYSCFG->MESR, (__FLAG__)) == (__FLAG__)) + +/** @brief Clear SYSCFG flag. + * @param __FLAG__ specifies the flag(s) to clear. + * This parameter can be any combination of the following values: + * @arg @ref SYSCFG_FLAG_MCLR Device memories erase status flag + * @arg @ref SYSCFG_FLAG_IPMEE ICACHE and PKA SRAM erase status flag + */ +#define __HAL_SYSCFG_CLEAR_FLAG(__FLAG__) SET_BIT(SYSCFG->MESR, (__FLAG__)) + +/** @brief Fast-mode Plus driving capability enable/disable macros + * @param __FASTMODEPLUS__: This parameter can be a value of : + * @arg @ref SYSCFG_FASTMODEPLUS_PA6 Fast-mode Plus driving capability activation on PA6 + * @arg @ref SYSCFG_FASTMODEPLUS_PA7 Fast-mode Plus driving capability activation on PA7 + * @arg @ref SYSCFG_FASTMODEPLUS_PA15 Fast-mode Plus driving capability activation on PA15 + * @arg @ref SYSCFG_FASTMODEPLUS_PB3 Fast-mode Plus driving capability activation on PB3 + */ +#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) \ + do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ + SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ + }while(0) + +#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) \ + do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ + CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ + }while(0) + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ + +/** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros + * @{ + */ + +#define IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_IT_FPU_ALL) != 0x00U) && \ + (((__INTERRUPT__) & ~SYSCFG_IT_FPU_ALL) == 0x00U)) + +#define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_BREAK_ECC) || \ + ((__CONFIG__) == SYSCFG_BREAK_PVD) || \ + ((__CONFIG__) == SYSCFG_BREAK_SRAM2_PARITY) || \ + ((__CONFIG__) == SYSCFG_BREAK_LOCKUP)) + +#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_ALL) != 0x00U) && \ + (((__PIN__) & ~SYSCFG_FASTMODEPLUS_ALL) == 0x00U)) + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +#define IS_SYSCFG_ATTRIBUTES(__ATTRIBUTES__) (((__ATTRIBUTES__) == SYSCFG_SEC) ||\ + ((__ATTRIBUTES__) == SYSCFG_NSEC)) + +#define IS_SYSCFG_ITEMS_ATTRIBUTES(__ITEM__) ((((__ITEM__) & SYSCFG_ALL) != 0x00U) && \ + (((__ITEM__) & ~SYSCFG_ALL) == 0x00U)) + +#endif /* __ARM_FEATURE_CMSE */ + +#if defined (SYSCFG_SECCFGR_SYSCFGSEC) +#define IS_SYSCFG_SINGLE_ITEMS_ATTRIBUTES(__ITEM__) (((__ITEM__) == (SYSCFG_CLK)) || \ + ((__ITEM__) == (SYSCFG_CLASSB)) || \ + ((__ITEM__) == (SYSCFG_FPU))) +#endif /* SYSCFG_SECCFGR_SYSCFGSEC */ + +#define IS_SYSCFG_LOCK_ITEMS(__ITEM__) ((((__ITEM__) & SYSCFG_LOCK_ALL) != 0x00U) && \ + (((__ITEM__) & ~SYSCFG_LOCK_ALL) == 0x00U)) + + +/** + * @} + */ + +/** @defgroup HAL_Private_Macros HAL Private Macros + * @{ + */ +#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \ + ((FREQ) == HAL_TICK_FREQ_100HZ) || \ + ((FREQ) == HAL_TICK_FREQ_1KHZ)) +/** + * @} + */ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup HAL_Exported_Functions + * @{ + */ + +/** @addtogroup HAL_Exported_Functions_Group1 + * @{ + */ + +/* Initialization and de-initialization functions ******************************/ +HAL_StatusTypeDef HAL_Init(void); +HAL_StatusTypeDef HAL_DeInit(void); +void HAL_MspInit(void); +void HAL_MspDeInit(void); +HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority); + +/** + * @} + */ + +/** @addtogroup HAL_Exported_Functions_Group2 + * @{ + */ + +/* Peripheral Control functions ************************************************/ +void HAL_IncTick(void); +void HAL_Delay(uint32_t Delay); +uint32_t HAL_GetTick(void); +uint32_t HAL_GetTickPrio(void); +HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq); +HAL_TickFreqTypeDef HAL_GetTickFreq(void); +void HAL_SuspendTick(void); +void HAL_ResumeTick(void); +uint32_t HAL_GetHalVersion(void); +uint32_t HAL_GetREVID(void); +uint32_t HAL_GetDEVID(void); +uint32_t HAL_GetUIDw0(void); +uint32_t HAL_GetUIDw1(void); +uint32_t HAL_GetUIDw2(void); + +/** + * @} + */ + +/** @addtogroup HAL_Exported_Functions_Group3 + * @{ + */ + +/* DBGMCU Peripheral Control functions *****************************************/ +void HAL_DBGMCU_EnableDBGStopMode(void); +void HAL_DBGMCU_DisableDBGStopMode(void); +void HAL_DBGMCU_EnableDBGStandbyMode(void); +void HAL_DBGMCU_DisableDBGStandbyMode(void); + +/** + * @} + */ + +/** @addtogroup HAL_Exported_Functions_Group4 + * @{ + */ + +/* SYSCFG Control functions ****************************************************/ +void HAL_SYSCFG_SRAM2Erase(void); +void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void); +void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void); + +/** + * @} + */ + +/** @addtogroup HAL_Exported_Functions_Group5 + * @{ + */ + +/* SYSCFG Lock functions ********************************************/ +void HAL_SYSCFG_Lock(uint32_t Item); +HAL_StatusTypeDef HAL_SYSCFG_GetLock(uint32_t *pItem); + +/** + * @} + */ + + +/** @addtogroup HAL_Exported_Functions_Group6 + * @{ + */ + +#if defined (SYSCFG_SECCFGR_SYSCFGSEC) +/* SYSCFG Attributes functions ********************************************/ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +void HAL_SYSCFG_ConfigAttributes(uint32_t Item, uint32_t Attributes); +#endif /* __ARM_FEATURE_CMSE */ +HAL_StatusTypeDef HAL_SYSCFG_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes); +#endif /* SYSCFG_SECCFGR_SYSCFGSEC */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32WBAxx_HAL_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_adc.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_adc.h new file mode 100644 index 0000000000..9632613a07 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_adc.h @@ -0,0 +1,1850 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_adc.h + * @author MCD Application Team + * @brief Header file of ADC HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_HAL_ADC_H +#define STM32WBAxx_HAL_ADC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal_def.h" + +/* Include low level driver */ +#include "stm32wbaxx_ll_adc.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @addtogroup ADC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup ADC_Exported_Types ADC Exported Types + * @{ + */ + +/** + * @brief ADC group regular oversampling structure definition + */ +typedef struct +{ + uint32_t Ratio; /*!< Configures the oversampling ratio. + This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */ + + uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler. + This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */ + + uint32_t TriggeredMode; /*!< Selects the regular triggered oversampling mode. + This parameter can be a value of @ref ADC_HAL_EC_OVS_DISCONT_MODE */ + +} ADC_OversamplingTypeDef; + +/** + * @brief Structure definition of ADC instance and ADC group regular. + * @note Parameters of this structure are shared within 2 scopes: + * - Scope entire ADC (differentiation done for compatibility with some other STM32 series featuring ADC + * groups regular and injected): ClockPrescaler, Resolution, DataAlign, + * ScanConvMode, EOCSelection, LowPowerAutoWait. + * - Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, + * ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling. + * @note The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state. + * ADC state can be either: + * - For all parameters: ADC disabled + * - For all parameters except 'ClockPrescaler' and 'Resolution': ADC enabled without conversion on going on + * group regular. + * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed + * without error reporting (as it can be the expected behavior in case of intended action to update another + * parameter (which fulfills the ADC state condition) on the fly). + */ +typedef struct +{ + uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous + clock derived from system clock or PLL (Refer to reference manual for list of + clocks available)) and clock prescaler. + This parameter can be a value of @ref ADC_HAL_EC_COMMON_CLOCK_SOURCE. + Note: The ADC clock configuration is common to all ADC instances. + Note: In case of synchronous clock mode based on HCLK/1, the configuration must + be enabled only if the system clock has a 50% duty clock cycle (APB + prescaler configured inside RCC must be bypassed and PCLK clock must have + 50% duty cycle). Refer to reference manual for details. + Note: In case of usage of asynchronous clock, the selected clock must be + preliminarily enabled at RCC top level. + Note: This parameter can be modified only if all ADC instances are disabled. */ + + uint32_t Resolution; /*!< Configure the ADC resolution. + This parameter can be a value of @ref ADC_HAL_EC_RESOLUTION */ + + uint32_t DataAlign; /*!< Specify ADC data alignment in conversion data register (right or left). + Refer to reference manual for alignments formats versus resolutions. + This parameter can be a value of @ref ADC_HAL_EC_DATA_ALIGN */ + + uint32_t ScanConvMode; /*!< Configure the sequencer of ADC group regular. + On this STM32 series, ADC group regular sequencer both modes "fully configurable" + or "not fully configurable" are available: + - sequencer configured to fully configurable: + sequencer length and each rank affectation to a channel are configurable. + - Sequence length: Set number of ranks in the scan sequence. + - Sequence direction: Unless specified in parameters, sequencer + scan direction is forward (from rank 1 to rank n). + - sequencer configured to not fully configurable: + sequencer length and each rank affectation to a channel are fixed by channel + HW number. + - Sequence length: Number of ranks in the scan sequence is + defined by number of channels set in the sequence, + rank of each channel is fixed by channel HW number. + (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). + - Sequence direction: Unless specified in parameters, sequencer + scan direction is forward (from lowest channel number to + highest channel number). + This parameter can be associated to parameter 'DiscontinuousConvMode' to have + main sequence subdivided in successive parts. Sequencer is automatically enabled + if several channels are set (sequencer cannot be disabled, as it can be the case + on other STM32 devices): + If only 1 channel is set: Conversion is performed in single mode. + If several channels are set: Conversions are performed in sequence mode. + This parameter can be a value of @ref ADC_Scan_mode */ + + uint32_t EOCSelection; /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and + interruption: end of unitary conversion or end of sequence conversions. + This parameter can be a value of @ref ADC_EOCSelection. */ + + FunctionalState LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the + previous conversion (for ADC group regular) has been retrieved by user software, + using function HAL_ADC_GetValue(). + This feature automatically adapts the frequency of ADC conversions triggers to + the speed of the system that reads the data. Moreover, this avoids risk of + overrun for low frequency applications. + This parameter can be set to ENABLE or DISABLE. + Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(), + HAL_ADC_Start_DMA()) since these modes have to clear immediately the EOC + flag (by CPU to free the IRQ pending event or by DMA). + Auto wait will work but fort a very short time, discarding its intended + benefit (except specific case of high load of CPU or DMA transfers which + can justify usage of auto wait). + Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, + when ADC conversion data is needed: + use HAL_ADC_PollForConversion() to ensure that conversion is completed and + HAL_ADC_GetValue() to retrieve conversion result and trig another + conversion start. */ + + FunctionalState LowPowerAutoPowerOff; /*!< Select the auto-off mode: the ADC automatically powers-off after a + conversion and automatically wakes-up when a new conversion is triggered + (with startup time between trigger and start of sampling). + This feature can be combined with automatic wait mode + (parameter 'LowPowerAutoWait'). + This parameter can be set to ENABLE or DISABLE. */ + + uint32_t LowPowerAutonomousDPD; /*!< Set ADC low power mode: deep power down in autonomous mode. + This parameter can be a value of + @ref ADC_HAL_EC_AUTONOMOUS_DEEP_POWER_DOWN_MODE. */ + + FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) + or continuous mode for ADC group regular, after the first ADC conversion + start trigger occurred (software start or external trigger). This parameter + can be set to ENABLE or DISABLE. */ + + uint32_t NbrOfConversion; /*!< Specify the number of ranks that will be converted within the regular group + sequencer. + This parameter is dependent on ScanConvMode: + - sequencer configured to fully configurable: + Number of ranks in the scan sequence is configurable using this parameter. + Note: After the first call of 'HAL_ADC_Init()', each rank corresponding to + parameter "NbrOfConversion" must be set using 'HAL_ADC_ConfigChannel()'. + Afterwards, when all needed sequencer ranks are set, parameter + 'NbrOfConversion' can be updated without modifying configuration of + sequencer ranks (sequencer ranks above 'NbrOfConversion' are discarded). + - sequencer configured to not fully configurable: + Number of ranks in the scan sequence is defined by number of channels set in + the sequence. This parameter is discarded. + This parameter must be a number between Min_Data = 1 and Max_Data = 8. + Note: This parameter must be modified when no conversion is on going on regular + group (ADC disabled, or ADC enabled without continuous mode or external + trigger that could launch a conversion). */ + + FunctionalState DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed + in Complete-sequence/Discontinuous-sequence (main sequence subdivided in + successive parts). + Discontinuous mode is used only if sequencer is enabled (parameter + 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. + Discontinuous mode can be enabled only if continuous mode is disabled. + If continuous mode is enabled, this parameter setting is discarded. + This parameter can be set to ENABLE or DISABLE. + Note: On this STM32 series, ADC group regular number of discontinuous + ranks increment is fixed to one-by-one. */ + + uint32_t ExternalTrigConv; /*!< Select the external event source used to trigger ADC group regular conversion + start. + If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger + is used instead. + This parameter can be a value of @ref ADC_regular_external_trigger_source. + Caution: external trigger source is common to all ADC instances. */ + + uint32_t ExternalTrigConvEdge; /*!< Select the external event edge used to trigger ADC group regular conversion start + If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded. + This parameter can be a value of @ref ADC_regular_external_trigger_edge */ + + FunctionalState DMAContinuousRequests; /*!< Specify whether the DMA requests are performed in one shot mode (DMA + transfer stops when number of conversions is reached) or in continuous + mode (DMA transfer unlimited, whatever number of conversions). + This parameter can be set to ENABLE or DISABLE. + Note: In continuous mode, DMA must be configured in circular mode. + Otherwise an overrun will be triggered when DMA buffer maximum + pointer is reached. */ + + uint32_t Overrun; /*!< Select the behavior in case of overrun: data overwritten or preserved (default). + This parameter can be a value of @ref ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR. + Note: In case of overrun set to data preserved and usage with programming model + with interruption (HAL_Start_IT()): ADC IRQ handler has to clear end of + conversion flags, this induces the release of the preserved data. If + needed, this data can be saved in function HAL_ADC_ConvCpltCallback(), + placed in user program code (called before end of conversion flags clear) + Note: Error reporting with respect to the conversion mode: + - Usage with ADC conversion by polling for event or interruption: Error is + reported only if overrun is set to data preserved. If overrun is set to + data overwritten, user can willingly not read all the converted data, + this is not considered as an erroneous case. + - Usage with ADC conversion by DMA: Error is reported whatever overrun + setting (DMA is expected to process all data from data register). */ + + uint32_t SamplingTimeCommon1; /*!< Set sampling time common to a group of channels. + Unit: ADC clock cycles + Conversion time is the addition of sampling time and processing time + (12.5 ADC clock cycles at ADC resolution 12 bits, + 10.5 cycles at 10 bits, + 8.5 cycles at 8 bits, + 6.5 cycles at 6 bits). + Note: On this STM32 family, two different sampling time settings are available, + each channel can use one of these two settings. On some other STM32 devices + this parameter in channel wise and is located into ADC channel + initialization structure. + This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME + Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor) + sampling time constraints must be respected (sampling time can be adjusted + in function of ADC clock frequency and sampling time setting) + Refer to device datasheet for timings values, parameters TS_vrefint, + TS_vbat, TS_temp (values rough order: few tens of microseconds). */ + + uint32_t SamplingTimeCommon2; /*!< Set sampling time common to a group of channels, second common setting possible. + Unit: ADC clock cycles + Conversion time is the addition of sampling time and processing time + (12.5 ADC clock cycles at ADC resolution 12 bits, + 10.5 cycles at 10 bits, + 8.5 cycles at 8 bits, + 6.5 cycles at 6 bits). + Note: On this STM32 family, two different sampling time settings are available, + each channel can use one of these two settings. On some other STM32 devices + this parameter in channel wise and is located into ADC channel + initialization structure. + This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME + Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor) + sampling time constraints must be respected (sampling time can be adjusted + in function of ADC clock frequency and sampling time setting) + Refer to device datasheet for timings values, parameters TS_vrefint, + TS_vbat, TS_temp (values rough order: few tens of microseconds). */ + + FunctionalState OversamplingMode; /*!< Specify whether the oversampling feature is enabled or disabled. + This parameter can be set to ENABLE or DISABLE. + Note: This parameter can be modified only if there is no conversion is + ongoing on ADC group regular. */ + + ADC_OversamplingTypeDef Oversampling; /*!< Specify the Oversampling parameters. + Caution: this setting overwrites the previous oversampling configuration + if oversampling is already enabled. */ + + uint32_t TriggerFrequencyMode; /*!< Set ADC trigger frequency mode. + This parameter can be a value of @ref ADC_HAL_EC_REG_TRIGGER_FREQ. + Note: ADC trigger frequency mode must be set to low frequency when + a duration is exceeded before ADC conversion start trigger event + (between ADC enable and ADC conversion start trigger event + or between two ADC conversion start trigger event). + Duration value: Refer to device datasheet, parameter "tIdle". + Note: When ADC trigger frequency mode is set to low frequency, + some rearm cycles are inserted before performing ADC conversion + start, inducing a delay of 2 ADC clock cycles. */ + +} ADC_InitTypeDef; + +/** + * @brief Structure definition of ADC channel for regular group + * @note The setting of these parameters by function HAL_ADC_ConfigChannel() is conditioned to ADC state. + * ADC state can be either: + * - For all parameters: ADC disabled or enabled without conversion on going on regular group. + * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed + * without error reporting (as it can be the expected behavior in case of intended action to update another + * parameter (which fulfills the ADC state condition) on the fly). + */ +typedef struct +{ + uint32_t Channel; /*!< Specify the channel to configure into ADC regular group. + This parameter can be a value of @ref ADC_HAL_EC_CHANNEL + Note: Depending on devices and ADC instances, some channels may not be available + on device package pins. Refer to device datasheet for channels + availability. */ + + uint32_t Rank; /*!< Add or remove the channel from ADC regular group sequencer and specify its + conversion rank. + This parameter is dependent on ScanConvMode: + - sequencer configured to fully configurable: + Channels ordering into each rank of scan sequence: + whatever channel can be placed into whatever rank. + - sequencer configured to not fully configurable: + rank of each channel is fixed by channel HW number. + (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). + Despite the channel rank is fixed, this parameter allow an additional + possibility: to remove the selected rank (selected channel) from sequencer. + This parameter can be a value of @ref ADC_HAL_EC_REG_SEQ_RANKS */ + + uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. + Unit: ADC clock cycles + Conversion time is the addition of sampling time and processing time + (12.5 ADC clock cycles at ADC resolution 12 bits, + 10.5 cycles at 10 bits, + 8.5 cycles at 8 bits, + 6.5 cycles at 6 bits). + This parameter can be a value of @ref ADC_HAL_EC_SAMPLINGTIME_COMMON + Note: On this STM32 family, two different sampling time settings are available + (refer to parameters "SamplingTimeCommon1" and "SamplingTimeCommon2"), + each channel can use one of these two settings. + + Note: In case of usage of internal measurement channels (VrefInt/Vbat/ + TempSensor), sampling time constraints must be respected (sampling time + can be adjusted in function of ADC clock frequency and sampling time + setting) + Refer to device datasheet for timings values. */ + +} ADC_ChannelConfTypeDef; + +/** + * @brief Structure definition of ADC analog watchdog + * @note The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state. + * ADC state can be either: + * - For all parameters except 'HighThreshold', 'LowThreshold': ADC disabled or ADC enabled without conversion + on going on ADC groups regular. + * - For parameters 'HighThreshold', 'LowThreshold': ADC enabled with conversion on going on regular. + */ +typedef struct +{ + uint32_t WatchdogNumber; /*!< Select which ADC analog watchdog is monitoring the selected channel. + For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels + by setting parameter 'WatchdogMode') + For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls + of 'HAL_ADC_AnalogWDGConfig()' for each channel) + This parameter can be a value of @ref ADC_HAL_EC_AWD_NUMBER. */ + + uint32_t WatchdogMode; /*!< Configure the ADC analog watchdog mode: single/all/none channels. + For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel or all + channels, ADC group regular. + For Analog Watchdog 2 and 3: Several channels can be monitored by applying + successively the AWD init structure. + This parameter can be a value of @ref ADC_analog_watchdog_mode. */ + + uint32_t Channel; /*!< Select which ADC channel to monitor by analog watchdog. + For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' + is configured on single channel (only 1 channel can be + monitored). + For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature, + call successively the function HAL_ADC_AnalogWDGConfig() + for each channel to be added (or removed with value + 'ADC_ANALOGWATCHDOG_NONE'). + This parameter can be a value of @ref ADC_HAL_EC_CHANNEL. */ + + FunctionalState ITMode; /*!< Specify whether the analog watchdog is configured in interrupt or polling mode. + This parameter can be set to ENABLE or DISABLE */ + + uint32_t HighThreshold; /*!< Configure the ADC analog watchdog High threshold value. + Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a + number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F + respectively. + Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC + resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2 + LSB are ignored. + Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are + impacted: the comparison of analog watchdog thresholds is done on + oversampling final computation (after ratio and shift application): + ADC data register bitfield [15:4] (12 most significant bits). */ + + uint32_t LowThreshold; /*!< Configures the ADC analog watchdog Low threshold value. + Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a + number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F + respectively. + Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC + resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2 + LSB are ignored. + Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are + impacted: the comparison of analog watchdog thresholds is done on + oversampling final computation (after ratio and shift application): + ADC data register bitfield [15:4] (12 most significant bits).*/ +} ADC_AnalogWDGConfTypeDef; + +/** @defgroup ADC_States ADC States + * @{ + */ + +/** + * @brief HAL ADC state machine: ADC states definition (bitfields) + * @note ADC state machine is managed by bitfields, state must be compared + * with bit by bit. + * For example: + * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) " + * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " + */ +/* States of ADC global scope */ +#define HAL_ADC_STATE_RESET (0x00000000UL) /*!< ADC not yet initialized or disabled */ +#define HAL_ADC_STATE_READY (0x00000001UL) /*!< ADC peripheral ready for use */ +#define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002UL) /*!< ADC is busy from internal process (ex : calibration, ...) */ +#define HAL_ADC_STATE_TIMEOUT (0x00000004UL) /*!< TimeOut occurrence */ + +/* States of ADC errors */ +#define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010UL) /*!< Internal error occurrence */ +#define HAL_ADC_STATE_ERROR_CONFIG (0x00000020UL) /*!< Configuration error occurrence */ +#define HAL_ADC_STATE_ERROR_DMA (0x00000040UL) /*!< DMA error occurrence */ + +/* States of ADC group regular */ +#define HAL_ADC_STATE_REG_BUSY (0x00000100UL) /*!< A conversion on ADC group regular is ongoing or can occur + (either by continuous mode, external trigger, low power + auto power-on (if feature available), multimode ADC master + control (if feature available)) */ +#define HAL_ADC_STATE_REG_EOC (0x00000200UL) /*!< Conversion data available on group regular */ +#define HAL_ADC_STATE_REG_OVR (0x00000400UL) /*!< Overrun occurrence */ +#define HAL_ADC_STATE_REG_EOSMP (0x00000800UL) /*!< Not available on this STM32 series: End Of Sampling flag + raised */ + +/* States of ADC group injected */ +#define HAL_ADC_STATE_INJ_BUSY (0x00001000UL) /*!< Not available on this STM32 series: A conversion on group + injected is ongoing or can occur (either by auto-injection + mode, external trigger, low power auto power-on (if feature + available), multimode ADC master control (if feature + available))*/ +#define HAL_ADC_STATE_INJ_EOC (0x00002000UL) /*!< Not available on this STM32 series: Conversion data + available on group injected */ +#define HAL_ADC_STATE_INJ_JQOVF (0x00004000UL) /*!< Not available on this STM32 series: Injected queue overflow + occurrence */ + +/* States of ADC analog watchdogs */ +#define HAL_ADC_STATE_AWD1 (0x00010000UL) /*!< Out-of-window occurrence of ADC analog watchdog 1 */ +#define HAL_ADC_STATE_AWD2 (0x00020000UL) /*!< Out-of-window occurrence of ADC analog watchdog 2 */ +#define HAL_ADC_STATE_AWD3 (0x00040000UL) /*!< Out-of-window occurrence of ADC analog watchdog 3 */ + +/* States of ADC multi-mode */ +#define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000UL) /*!< Not available on this STM32 series: ADC in multimode slave + state, controlled by another ADC master (when feature + available) */ + + +/** + * @} + */ + +/** + * @brief ADC handle Structure definition + */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +typedef struct __ADC_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ +{ + ADC_TypeDef *Instance; /*!< Register base address */ + ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular conversions setting */ + DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ + HAL_LockTypeDef Lock; /*!< ADC locking object */ + __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */ + __IO uint32_t ErrorCode; /*!< ADC Error code */ + + uint32_t ADCGroupRegularSequencerRanks; /*!< ADC group regular sequencer memorization of ranks + setting, used in mode "fully configurable" (refer to + parameter 'ScanConvMode') */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */ + void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer + callback */ + void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */ + void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */ + void (* LevelOutOfWindow2Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 2 callback */ + void (* LevelOutOfWindow3Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 3 callback */ + void (* EndOfSamplingCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC end of sampling callback */ + void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */ + void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */ +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ +} ADC_HandleTypeDef; + +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +/** + * @brief HAL ADC Callback ID enumeration definition + */ +typedef enum +{ + HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /*!< ADC conversion complete callback ID */ + HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /*!< ADC conversion DMA half-transfer callback ID */ + HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /*!< ADC analog watchdog 1 callback ID */ + HAL_ADC_ERROR_CB_ID = 0x03U, /*!< ADC error callback ID */ + HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID = 0x06U, /*!< ADC analog watchdog 2 callback ID */ + HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID = 0x07U, /*!< ADC analog watchdog 3 callback ID */ + HAL_ADC_END_OF_SAMPLING_CB_ID = 0x08U, /*!< ADC end of sampling callback ID */ + HAL_ADC_MSPINIT_CB_ID = 0x09U, /*!< ADC Msp Init callback ID */ + HAL_ADC_MSPDEINIT_CB_ID = 0x0AU /*!< ADC Msp DeInit callback ID */ +} HAL_ADC_CallbackIDTypeDef; + +/** + * @brief HAL ADC Callback pointer definition + */ +typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */ + +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + +/** + * @} + */ + + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup ADC_Exported_Constants ADC Exported Constants + * @{ + */ + +/** @defgroup ADC_Error_Code ADC Error Code + * @{ + */ +#define HAL_ADC_ERROR_NONE (0x00U) /*!< No error */ +#define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC peripheral internal error (problem of clocking, + enable/disable, erroneous state, ...) */ +#define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */ +#define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +#define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */ +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup ADC_HAL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source + * @{ + */ +#define ADC_CLOCK_ASYNC_DIV1 (LL_ADC_CLOCK_ASYNC_DIV1) /*!< ADC asynchronous clock without + prescaler */ +#define ADC_CLOCK_ASYNC_DIV2 (LL_ADC_CLOCK_ASYNC_DIV2) /*!< ADC asynchronous clock with prescaler + division by 2 */ +#define ADC_CLOCK_ASYNC_DIV4 (LL_ADC_CLOCK_ASYNC_DIV4) /*!< ADC asynchronous clock with prescaler + division by 4 */ +#define ADC_CLOCK_ASYNC_DIV6 (LL_ADC_CLOCK_ASYNC_DIV6) /*!< ADC asynchronous clock with prescaler + division by 6 */ +#define ADC_CLOCK_ASYNC_DIV8 (LL_ADC_CLOCK_ASYNC_DIV8) /*!< ADC asynchronous clock with prescaler + division by 8 */ +#define ADC_CLOCK_ASYNC_DIV10 (LL_ADC_CLOCK_ASYNC_DIV10) /*!< ADC asynchronous clock with prescaler + division by 10 */ +#define ADC_CLOCK_ASYNC_DIV12 (LL_ADC_CLOCK_ASYNC_DIV12) /*!< ADC asynchronous clock with prescaler + division by 12 */ +#define ADC_CLOCK_ASYNC_DIV16 (LL_ADC_CLOCK_ASYNC_DIV16) /*!< ADC asynchronous clock with prescaler + division by 16 */ +#define ADC_CLOCK_ASYNC_DIV32 (LL_ADC_CLOCK_ASYNC_DIV32) /*!< ADC asynchronous clock with prescaler + division by 32 */ +#define ADC_CLOCK_ASYNC_DIV64 (LL_ADC_CLOCK_ASYNC_DIV64) /*!< ADC asynchronous clock with prescaler + division by 64 */ +#define ADC_CLOCK_ASYNC_DIV128 (LL_ADC_CLOCK_ASYNC_DIV128) /*!< ADC asynchronous clock with prescaler + division by 128 */ +#define ADC_CLOCK_ASYNC_DIV256 (LL_ADC_CLOCK_ASYNC_DIV256) /*!< ADC asynchronous clock with prescaler + division by 256 */ +/** + * @} + */ + +/** @defgroup ADC_HAL_EC_RESOLUTION ADC instance - Resolution + * @{ + */ +#define ADC_RESOLUTION_12B (LL_ADC_RESOLUTION_12B) /*!< ADC resolution 12 bits */ +#define ADC_RESOLUTION_10B (LL_ADC_RESOLUTION_10B) /*!< ADC resolution 10 bits */ +#define ADC_RESOLUTION_8B (LL_ADC_RESOLUTION_8B) /*!< ADC resolution 8 bits */ +#define ADC_RESOLUTION_6B (LL_ADC_RESOLUTION_6B) /*!< ADC resolution 6 bits */ +/** + * @} + */ + +/** @defgroup ADC_HAL_EC_DATA_ALIGN ADC conversion data alignment + * @{ + */ +#define ADC_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT) /*!< ADC conversion data alignment: right aligned + (alignment on data register LSB bit 0)*/ +#define ADC_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT) /*!< ADC conversion data alignment: left aligned + (alignment on data register MSB bit 15)*/ +/** + * @} + */ + +/** @defgroup ADC_Scan_mode ADC sequencer scan mode + * @{ + */ +/* Note: On this STM32 family, ADC group regular sequencer both modes */ +/* "fully configurable" or "not fully configurable" are */ +/* available. */ +/* Scan mode values must be compatible with other STM32 devices having */ +/* a configurable sequencer. */ +/* Scan direction setting values are defined by taking in account */ +/* already defined values for other STM32 devices: */ +/* ADC_SCAN_DISABLE (0x00000000UL) */ +/* ADC_SCAN_ENABLE (0x00000001UL) */ +/* Sequencer fully configurable with only rank 1 enabled is considered */ +/* as default setting equivalent to scan enable. */ +/* In case of migration from another STM32 device, the user will be */ +/* warned of change of setting choices with assert check. */ +/* Sequencer set to fully configurable */ +#define ADC_SCAN_DISABLE (0x00000000UL) /*!< Sequencer set to fully configurable: + only the rank 1 is enabled (no scan sequence on several ranks) */ +#define ADC_SCAN_ENABLE (ADC_CFGR1_CHSELRMOD) /*!< Sequencer set to fully configurable: + sequencer length and each rank affectation to a channel are configurable. */ + +/* Sequencer set to not fully configurable */ +#define ADC_SCAN_SEQ_FIXED (ADC_SCAN_SEQ_FIXED_INT) /*!< Sequencer set to not fully configurable: + sequencer length and each rank affectation to a channel are fixed by + channel HW number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). + Scan direction forward: from channel 0 to channel 18 */ +#define ADC_SCAN_SEQ_FIXED_BACKWARD (ADC_SCAN_SEQ_FIXED_INT \ + | ADC_CFGR1_SCANDIR) /*!< Sequencer set to not fully configurable: + sequencer length and each rank affectation to a channel are fixed by + channel HW number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). + Scan direction backward: from channel 18 to channel 0 */ + +#define ADC_SCAN_DIRECTION_FORWARD (ADC_SCAN_SEQ_FIXED) /* For compatibility with other STM32 series */ +#define ADC_SCAN_DIRECTION_BACKWARD (ADC_SCAN_SEQ_FIXED_BACKWARD) /* For compatibility with other STM32 series */ +/** + * @} + */ + +/** @defgroup ADC_HAL_EC_AUTONOMOUS_DEEP_POWER_DOWN_MODE ADC autonomous deep power down mode + * @{ + */ +#define ADC_LP_AUTONOMOUS_DPD_DISABLE (LL_ADC_LP_AUTONOMOUS_DPD_DISABLE) /*!< ADC deep power down in autonomous + mode disabled */ +#define ADC_LP_AUTONOMOUS_DPD_ENABLE (LL_ADC_LP_AUTONOMOUS_DPD_ENABLE) /*!< ADC deep power down in autonomous + mode enabled */ +/** + * @} + */ + +/** @defgroup ADC_regular_external_trigger_source ADC group regular trigger source + * @{ + */ +/* ADC group regular trigger sources for all ADC instances */ +#define ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE) /*!< ADC group regular conversion + trigger software start */ +#define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< ADC group regular conversion + trigger from external peripheral: TIM1 TRGO. */ +#define ADC_EXTERNALTRIG_T1_CC4 (LL_ADC_REG_TRIG_EXT_TIM1_CH4) /*!< TIM1 channel 4 event (capture + compare: input capture or output capture). + Trigger edge set to rising edge (default setting). */ +#define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion + trigger from external peripheral: TIM1 channel 4 event (capture compare). */ +#define ADC_EXTERNALTRIG_LPTIM1_CC1 (LL_ADC_REG_TRIG_EXT_LPTIM1_CH1) /*!< ADC group regular conversion + trigger from external peripheral: LPTIM1 channel 1 event. */ +#define ADC_EXTERNALTRIG_EXT_IT15 (LL_ADC_REG_TRIG_EXT_EXTI_LINE15) /*!< ADC group regular conversion + trigger from external peripheral: external interrupt line 15. */ +/** + * @} + */ + +/** @defgroup ADC_regular_external_trigger_edge ADC group regular trigger edge (when external trigger is selected) + * @{ + */ +#define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000UL) /*!< ADC group regular trigger + disabled (SW start)*/ +#define ADC_EXTERNALTRIGCONVEDGE_RISING (LL_ADC_REG_TRIG_EXT_RISING) /*!< ADC group regular conversion + trigger polarity set to rising edge */ +#define ADC_EXTERNALTRIGCONVEDGE_FALLING (LL_ADC_REG_TRIG_EXT_FALLING) /*!< ADC group regular conversion + trigger polarity set to falling edge */ +#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (LL_ADC_REG_TRIG_EXT_RISINGFALLING) /*!< ADC group regular conversion + trigger polarity set to both rising and falling edges */ +/** + * @} + */ + +/** @defgroup ADC_EOCSelection ADC sequencer end of unitary conversion or sequence conversions + * @{ + */ +#define ADC_EOC_SINGLE_CONV (ADC_ISR_EOC) /*!< End of unitary conversion flag */ +#define ADC_EOC_SEQ_CONV (ADC_ISR_EOS) /*!< End of sequence conversions flag */ +/** + * @} + */ + +/** @defgroup ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data + * @{ + */ +#define ADC_OVR_DATA_PRESERVED (LL_ADC_REG_OVR_DATA_PRESERVED) /*!< ADC group regular behavior in case + of overrun: data preserved */ +#define ADC_OVR_DATA_OVERWRITTEN (LL_ADC_REG_OVR_DATA_OVERWRITTEN) /*!< ADC group regular behavior in case + of overrun: data overwritten */ +/** + * @} + */ + +/** @defgroup ADC_HAL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks + * @{ + */ +#define ADC_RANK_CHANNEL_NUMBER (0x00000001U) /*!< Enable the rank of the selected channels. Number of + ranks in the sequence is defined by number of channels enabled, rank of + each channel is defined by channel number (channel 0 fixed on rank 0, + channel 1 fixed on rank1, ...). + Setting relevant if parameter "ScanConvMode" is set to sequencer not fully + configurable. */ +#define ADC_RANK_NONE (0x00000002U) /*!< Disable the selected rank (selected channel) from + sequencer. + Setting relevant if parameter "ScanConvMode" is set to sequencer not fully + configurable. */ + +#define ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1) /*!< ADC group regular sequencer rank 1 */ +#define ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2) /*!< ADC group regular sequencer rank 2 */ +#define ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3) /*!< ADC group regular sequencer rank 3 */ +#define ADC_REGULAR_RANK_4 (LL_ADC_REG_RANK_4) /*!< ADC group regular sequencer rank 4 */ +#define ADC_REGULAR_RANK_5 (LL_ADC_REG_RANK_5) /*!< ADC group regular sequencer rank 5 */ +#define ADC_REGULAR_RANK_6 (LL_ADC_REG_RANK_6) /*!< ADC group regular sequencer rank 6 */ +#define ADC_REGULAR_RANK_7 (LL_ADC_REG_RANK_7) /*!< ADC group regular sequencer rank 7 */ +#define ADC_REGULAR_RANK_8 (LL_ADC_REG_RANK_8) /*!< ADC group regular sequencer rank 8 */ +/** + * @} + */ + +/** @defgroup ADC_HAL_EC_SAMPLINGTIME_COMMON ADC instance - Sampling time common to a group of channels + * @{ + */ +#define ADC_SAMPLINGTIME_COMMON_1 (LL_ADC_SAMPLINGTIME_COMMON_1) /*!< Set sampling time common to a group of + channels: sampling time nb 1 */ +#define ADC_SAMPLINGTIME_COMMON_2 (LL_ADC_SAMPLINGTIME_COMMON_2) /*!< Set sampling time common to a group of + channels: sampling time nb 2 */ +/** + * @} + */ + +/** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time + * @{ + */ +#define ADC_SAMPLETIME_1CYCLE_5 (LL_ADC_SAMPLINGTIME_1CYCLE_5) /*!< Sampling time 1.5 ADC clock cycle */ +#define ADC_SAMPLETIME_3CYCLES_5 (LL_ADC_SAMPLINGTIME_3CYCLES_5) /*!< Sampling time 3.5 ADC clock cycles */ +#define ADC_SAMPLETIME_7CYCLES_5 (LL_ADC_SAMPLINGTIME_7CYCLES_5) /*!< Sampling time 7.5 ADC clock cycles */ +#define ADC_SAMPLETIME_12CYCLES_5 (LL_ADC_SAMPLINGTIME_12CYCLES_5) /*!< Sampling time 12.5 ADC clock cycles */ +#define ADC_SAMPLETIME_19CYCLES_5 (LL_ADC_SAMPLINGTIME_19CYCLES_5) /*!< Sampling time 19.5 ADC clock cycles */ +#define ADC_SAMPLETIME_39CYCLES_5 (LL_ADC_SAMPLINGTIME_39CYCLES_5) /*!< Sampling time 39.5 ADC clock cycles */ +#define ADC_SAMPLETIME_79CYCLES_5 (LL_ADC_SAMPLINGTIME_79CYCLES_5) /*!< Sampling time 79.5 ADC clock cycle */ +#define ADC_SAMPLETIME_814CYCLES_5 (LL_ADC_SAMPLINGTIME_814CYCLES_5) /*!< Sampling time 814.5 ADC clock cycles */ +/** + * @} + */ + +/** @defgroup ADC_HAL_EC_CHANNEL ADC instance - Channel number + * @{ + */ +#define ADC_CHANNEL_0 (LL_ADC_CHANNEL_0) /*!< External channel (GPIO pin) ADCx_IN0 */ +#define ADC_CHANNEL_1 (LL_ADC_CHANNEL_1) /*!< External channel (GPIO pin) ADCx_IN1 */ +#define ADC_CHANNEL_2 (LL_ADC_CHANNEL_2) /*!< External channel (GPIO pin) ADCx_IN2 */ +#define ADC_CHANNEL_3 (LL_ADC_CHANNEL_3) /*!< External channel (GPIO pin) ADCx_IN3 */ +#define ADC_CHANNEL_4 (LL_ADC_CHANNEL_4) /*!< External channel (GPIO pin) ADCx_IN4 */ +#define ADC_CHANNEL_5 (LL_ADC_CHANNEL_5) /*!< External channel (GPIO pin) ADCx_IN5 */ +#define ADC_CHANNEL_6 (LL_ADC_CHANNEL_6) /*!< External channel (GPIO pin) ADCx_IN6 */ +#define ADC_CHANNEL_7 (LL_ADC_CHANNEL_7) /*!< External channel (GPIO pin) ADCx_IN7 */ +#define ADC_CHANNEL_8 (LL_ADC_CHANNEL_8) /*!< External channel (GPIO pin) ADCx_IN8 */ +#define ADC_CHANNEL_9 (LL_ADC_CHANNEL_9) /*!< External channel (GPIO pin) ADCx_IN9 */ +#define ADC_CHANNEL_10 (LL_ADC_CHANNEL_10) /*!< External channel (GPIO pin) ADCx_IN10 */ +#define ADC_CHANNEL_11 (LL_ADC_CHANNEL_11) /*!< External channel (GPIO pin) ADCx_IN11 */ +#define ADC_CHANNEL_12 (LL_ADC_CHANNEL_12) /*!< External channel (GPIO pin) ADCx_IN12 */ +#define ADC_CHANNEL_13 (LL_ADC_CHANNEL_13) /*!< External channel (GPIO pin) ADCx_IN13 */ +#define ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT) /*!< Internal channel VrefInt: Internal + voltage reference. */ +#define ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_TEMPSENSOR) /*!< Internal channel Temperature sensor. */ +#define ADC_CHANNEL_VCORE (LL_ADC_CHANNEL_VCORE) /*!< ADC internal channel to Vcore. */ +/** + * @} + */ + +/** @defgroup ADC_HAL_EC_AWD_NUMBER Analog watchdog - ADC analog watchdog (AWD) number + * @{ + */ +#define ADC_ANALOGWATCHDOG_1 (LL_ADC_AWD1) /*!< ADC analog watchdog number 1 */ +#define ADC_ANALOGWATCHDOG_2 (LL_ADC_AWD2) /*!< ADC analog watchdog number 2 */ +#define ADC_ANALOGWATCHDOG_3 (LL_ADC_AWD3) /*!< ADC analog watchdog number 3 */ +/** + * @} + */ + +/** @defgroup ADC_analog_watchdog_mode ADC analog watchdog (AWD) mode + * @{ + */ +#define ADC_ANALOGWATCHDOG_NONE (0x00000000UL) /*!< ADC AWD not selected */ +#define ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR1_AWD1SGL | ADC_CFGR1_AWD1EN) /*!< ADC AWD applied to a regular + group single channel */ +#define ADC_ANALOGWATCHDOG_ALL_REG (ADC_CFGR1_AWD1EN) /*!< ADC AWD applied to regular + group all channels */ +/** + * @} + */ + +/** @defgroup ADC_HAL_EC_OVS_RATIO Oversampling - Ratio + * @note The oversampling ratio is the number of ADC conversions performed, sum of these conversions data is computed + * to result as the ADC oversampling conversion data (before potential shift) + * @{ + */ +#define ADC_OVERSAMPLING_RATIO_2 (LL_ADC_OVS_RATIO_2) /*!< ADC oversampling ratio 2 */ +#define ADC_OVERSAMPLING_RATIO_4 (LL_ADC_OVS_RATIO_4) /*!< ADC oversampling ratio 4 */ +#define ADC_OVERSAMPLING_RATIO_8 (LL_ADC_OVS_RATIO_8) /*!< ADC oversampling ratio 8 */ +#define ADC_OVERSAMPLING_RATIO_16 (LL_ADC_OVS_RATIO_16) /*!< ADC oversampling ratio 16 */ +#define ADC_OVERSAMPLING_RATIO_32 (LL_ADC_OVS_RATIO_32) /*!< ADC oversampling ratio 32 */ +#define ADC_OVERSAMPLING_RATIO_64 (LL_ADC_OVS_RATIO_64) /*!< ADC oversampling ratio 64 */ +#define ADC_OVERSAMPLING_RATIO_128 (LL_ADC_OVS_RATIO_128) /*!< ADC oversampling ratio 128 */ +#define ADC_OVERSAMPLING_RATIO_256 (LL_ADC_OVS_RATIO_256) /*!< ADC oversampling ratio 256 */ +/** + * @} + */ + +/** @defgroup ADC_HAL_EC_OVS_SHIFT Oversampling - Data shift + * @note The sum of the ADC conversions data is divided by "Rightbitshift" number to result as the ADC oversampling + * conversion data + * @{ + */ +#define ADC_RIGHTBITSHIFT_NONE (LL_ADC_OVS_SHIFT_NONE) /*!< ADC oversampling no shift */ +#define ADC_RIGHTBITSHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1) /*!< ADC oversampling right shift of 1 rank */ +#define ADC_RIGHTBITSHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2) /*!< ADC oversampling right shift of 2 rank */ +#define ADC_RIGHTBITSHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3) /*!< ADC oversampling right shift of 3 rank */ +#define ADC_RIGHTBITSHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4) /*!< ADC oversampling right shift of 4 rank */ +#define ADC_RIGHTBITSHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5) /*!< ADC oversampling right shift of 5 rank */ +#define ADC_RIGHTBITSHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6) /*!< ADC oversampling right shift of 6 rank */ +#define ADC_RIGHTBITSHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7) /*!< ADC oversampling right shift of 7 rank */ +#define ADC_RIGHTBITSHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8) /*!< ADC oversampling right shift of 8 rank */ +/** + * @} + */ + +/** @defgroup ADC_HAL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode + * @{ + */ +#define ADC_TRIGGEREDMODE_SINGLE_TRIGGER (LL_ADC_OVS_REG_CONT) /*!< ADC oversampling discontinuous mode: + continuous mode (all conversions of OVS ratio are done from 1 trigger) */ +#define ADC_TRIGGEREDMODE_MULTI_TRIGGER (LL_ADC_OVS_REG_DISCONT) /*!< ADC oversampling discontinuous mode: + discontinuous mode (each conversion of OVS ratio needs a trigger) */ +/** + * @} + */ + +/** @defgroup ADC_HAL_EC_REG_TRIGGER_FREQ ADC group regular - Trigger frequency mode + * @note ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion + * start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion + * start trigger event). + * Duration value: Refer to device datasheet, parameter "tIdle". + * @{ + */ +#define ADC_TRIGGER_FREQ_HIGH (LL_ADC_TRIGGER_FREQ_HIGH) /*!< Trigger frequency mode set to high frequency. */ +#define ADC_TRIGGER_FREQ_LOW (LL_ADC_TRIGGER_FREQ_LOW) /*!< Trigger frequency mode set to low frequency. */ +/** + * @} + */ + +/** @defgroup ADC_Event_type ADC Event type + * @note Analog watchdog 1 is available on all stm32 series + * Analog watchdog 2 and 3 are not available on all series + * @{ + */ +#define ADC_EOSMP_EVENT (ADC_FLAG_EOSMP) /*!< ADC End of Sampling event */ +#define ADC_AWD1_EVENT (ADC_FLAG_AWD1) /*!< ADC Analog watchdog 1 event (main analog watchdog) */ +#define ADC_AWD2_EVENT (ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog watchdog) */ +#define ADC_AWD3_EVENT (ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog watchdog) */ +#define ADC_OVR_EVENT (ADC_FLAG_OVR) /*!< ADC overrun event */ +/** + * @} + */ +#define ADC_AWD_EVENT ADC_AWD1_EVENT /*!< ADC Analog watchdog 1 event: Naming for compatibility + with other STM32 devices having only one analog watchdog */ + +/** @defgroup ADC_interrupts_definition ADC interrupts definition + * @{ + */ +#define ADC_IT_RDY ADC_IER_ADRDYIE /*!< ADC Ready interrupt source */ +#define ADC_IT_LDORDY ADC_IER_LDORDYIE /*!< ADC internal voltage regulator ready interrupt source */ +#define ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC End of sampling interrupt source */ +#define ADC_IT_EOC ADC_IER_EOCIE /*!< ADC End of regular conversion interrupt source */ +#define ADC_IT_EOS ADC_IER_EOSIE /*!< ADC End of regular sequence of conversions interrupt source */ +#define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC overrun interrupt source */ +#define ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */ +#define ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC Analog watchdog 2 interrupt source (additional analog + watchdog) */ +#define ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC Analog watchdog 3 interrupt source (additional analog + watchdog) */ +/** + * @} + */ + +/** @defgroup ADC_flags_definition ADC flags definition + * @{ + */ +#define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready flag */ +#define ADC_FLAG_LDORDY ADC_ISR_LDORDY /*!< ADC internal voltage regulator ready flag */ +#define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */ +#define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */ +#define ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC End of Regular sequence of Conversions flag */ +#define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */ +#define ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC Analog watchdog 1 flag (main analog watchdog) */ +#define ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC Analog watchdog 2 flag (additional analog watchdog) */ +#define ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC Analog watchdog 3 flag (additional analog watchdog) */ +/** + * @} + */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ + +/** @defgroup ADC_Private_Macros ADC Private Macros + * @{ + */ +/* Macro reserved for internal HAL driver usage, not intended to be used in */ +/* code of final user. */ + +/** + * @brief Test if conversion trigger of regular group is software start + * or external trigger. + * @param __HANDLE__ ADC handle + * @retval SET (software start) or RESET (external trigger) + */ +#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \ + (((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_EXTEN) == 0UL) + +/** + * @brief Return resolution bits in CFGR1 register RES[1:0] field. + * @param __HANDLE__ ADC handle + * @retval Value of bitfield RES in CFGR1 register. + */ +#define ADC_GET_RESOLUTION(__HANDLE__) \ + (LL_ADC_GetResolution((__HANDLE__)->Instance)) + +/** + * @brief Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE"). + * @param __HANDLE__ ADC handle + * @retval None + */ +#define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) + +/** + * @brief Simultaneously clear and set specific bits of the handle State. + * @note ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), + * the first parameter is the ADC handle State, the second parameter is the + * bit field to clear, the third and last parameter is the bit field to set. + * @retval None + */ +#define ADC_STATE_CLR_SET MODIFY_REG + +/** + * @brief Enable ADC discontinuous conversion mode for regular group + * @param _REG_DISCONTINUOUS_MODE_: Regular discontinuous mode. + * @retval None + */ +#define ADC_CFGR1_REG_DISCCONTINUOUS(_REG_DISCONTINUOUS_MODE_) \ + ((_REG_DISCONTINUOUS_MODE_) << 16U) + +/** + * @brief Enable the ADC auto off mode. + * @param _AUTOOFF_ Auto off bit enable or disable. + * @retval None + */ +#define ADC_CFGR1_AUTOOFF(_AUTOOFF_) \ + ((_AUTOOFF_) << 15U) + +/** + * @brief Enable the ADC auto delay mode. + * @param _AUTOWAIT_ Auto delay bit enable or disable. + * @retval None + */ +#define ADC_CFGR1_AUTOWAIT(_AUTOWAIT_) \ + ((_AUTOWAIT_) << 14U) + +/** + * @brief Enable ADC continuous conversion mode. + * @param _CONTINUOUS_MODE_ Continuous mode. + * @retval None + */ +#define ADC_CFGR1_CONTINUOUS(_CONTINUOUS_MODE_) \ + ((_CONTINUOUS_MODE_) << 13U) + +/** + * @brief Enable ADC overrun mode. + * @param _OVERRUN_MODE_ Overrun mode. + * @retval Overrun bit setting to be programmed into CFGR register + */ +/* Note: Bit ADC_CFGR1_OVRMOD not used directly in constant */ +/* "ADC_OVR_DATA_OVERWRITTEN" to have this case defined to 0x00, to set it */ +/* as the default case to be compliant with other STM32 devices. */ +#define ADC_CFGR1_OVERRUN(_OVERRUN_MODE_) \ + ( ( (_OVERRUN_MODE_) != (ADC_OVR_DATA_PRESERVED) \ + )? (ADC_CFGR1_OVRMOD) : (0x00000000UL) \ + ) + +/** + * @brief Set ADC scan mode with differentiation of sequencer setting + * fixed or configurable + * @param _SCAN_MODE_ Scan conversion mode. + * @retval None + */ +/* Note: Scan mode set using this macro (instead of parameter direct set) */ +/* due to different modes on other STM32 devices: */ +/* if scan mode is disabled, sequencer is set to fully configurable */ +/* with setting of only rank 1 enabled afterwards. */ +#define ADC_SCAN_SEQ_MODE(_SCAN_MODE_) \ + ( (((_SCAN_MODE_) & ADC_SCAN_SEQ_FIXED_INT) != 0UL \ + )? \ + ((_SCAN_MODE_) & (~ADC_SCAN_SEQ_FIXED_INT)) \ + : \ + (ADC_CFGR1_CHSELRMOD) \ + ) + +/** + * @brief Enable the ADC DMA continuous request. + * @param _DMACONTREQ_MODE_: DMA continuous request mode. + * @retval None + */ +#define ADC_CFGR1_DMACONTREQ(_DMACONTREQ_MODE_) \ + ((_DMACONTREQ_MODE_) << 1U) + +/** + * @brief Shift the AWD threshold in function of the selected ADC resolution. + * Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0. + * If resolution 12 bits, no shift. + * If resolution 10 bits, shift of 2 ranks on the left. + * If resolution 8 bits, shift of 4 ranks on the left. + * If resolution 6 bits, shift of 6 ranks on the left. + * therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)) + * @param __HANDLE__ ADC handle + * @param _Threshold_ Value to be shifted + * @retval None + */ +#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_) \ + ((_Threshold_) << ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) >> 2U)*2U)) + +#define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1) ||\ + ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV2 ) ||\ + ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV4 ) ||\ + ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV6 ) ||\ + ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV8 ) ||\ + ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV10 ) ||\ + ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV12 ) ||\ + ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV16 ) ||\ + ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV32 ) ||\ + ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV64 ) ||\ + ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV128 ) ||\ + ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV256)) + +#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \ + ((RESOLUTION) == ADC_RESOLUTION_10B) || \ + ((RESOLUTION) == ADC_RESOLUTION_8B) || \ + ((RESOLUTION) == ADC_RESOLUTION_6B) ) + +#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \ + ((ALIGN) == ADC_DATAALIGN_LEFT) ) + +#define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) || \ + ((SCAN_MODE) == ADC_SCAN_ENABLE) || \ + ((SCAN_MODE) == ADC_SCAN_SEQ_FIXED) || \ + ((SCAN_MODE) == ADC_SCAN_SEQ_FIXED_BACKWARD) ) + +#define IS_ADC_AUTONOMOUS_DPD(AUTONOMOUS_DPD) (((AUTONOMOUS_DPD) == ADC_LP_AUTONOMOUS_DPD_DISABLE) || \ + ((AUTONOMOUS_DPD) == ADC_LP_AUTONOMOUS_DPD_ENABLE) ) + +#define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ + ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \ + ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \ + ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) ) + +#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIG_T1_TRGO2) || \ + ((REGTRIG) == ADC_EXTERNALTRIG_T1_CC4) || \ + ((REGTRIG) == ADC_EXTERNALTRIG_T2_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIG_LPTIM1_CC1) || \ + ((REGTRIG) == ADC_EXTERNALTRIG_EXT_IT15) || \ + ((REGTRIG) == ADC_SOFTWARE_START) ) + +#define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV) || \ + ((EOC_SELECTION) == ADC_EOC_SEQ_CONV)) + +#define IS_ADC_OVERRUN(OVR) (((OVR) == ADC_OVR_DATA_PRESERVED) || \ + ((OVR) == ADC_OVR_DATA_OVERWRITTEN) ) + +#define IS_ADC_REGULAR_RANK_SEQ_FIXED(RANK) (((RANK) == ADC_RANK_CHANNEL_NUMBER) || \ + ((RANK) == ADC_RANK_NONE) ) + +#define IS_ADC_REGULAR_RANK(RANK) (((RANK) == ADC_REGULAR_RANK_1 ) || \ + ((RANK) == ADC_REGULAR_RANK_2 ) || \ + ((RANK) == ADC_REGULAR_RANK_3 ) || \ + ((RANK) == ADC_REGULAR_RANK_4 ) || \ + ((RANK) == ADC_REGULAR_RANK_5 ) || \ + ((RANK) == ADC_REGULAR_RANK_6 ) || \ + ((RANK) == ADC_REGULAR_RANK_7 ) || \ + ((RANK) == ADC_REGULAR_RANK_8 ) ) + +#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \ + ((CHANNEL) == ADC_CHANNEL_1) || \ + ((CHANNEL) == ADC_CHANNEL_2) || \ + ((CHANNEL) == ADC_CHANNEL_3) || \ + ((CHANNEL) == ADC_CHANNEL_4) || \ + ((CHANNEL) == ADC_CHANNEL_5) || \ + ((CHANNEL) == ADC_CHANNEL_6) || \ + ((CHANNEL) == ADC_CHANNEL_7) || \ + ((CHANNEL) == ADC_CHANNEL_8) || \ + ((CHANNEL) == ADC_CHANNEL_9) || \ + ((CHANNEL) == ADC_CHANNEL_10) || \ + ((CHANNEL) == ADC_CHANNEL_11) || \ + ((CHANNEL) == ADC_CHANNEL_12) || \ + ((CHANNEL) == ADC_CHANNEL_13) || \ + ((CHANNEL) == ADC_CHANNEL_VREFINT) || \ + ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) || \ + ((CHANNEL) == ADC_CHANNEL_VCORE) ) + +#define IS_ADC_SAMPLING_TIME_COMMON(SAMPLING_TIME_COMMON) (((SAMPLING_TIME_COMMON) == ADC_SAMPLINGTIME_COMMON_1) || \ + ((SAMPLING_TIME_COMMON) == ADC_SAMPLINGTIME_COMMON_2) ) + +#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5) || \ + ((TIME) == ADC_SAMPLETIME_3CYCLES_5) || \ + ((TIME) == ADC_SAMPLETIME_7CYCLES_5) || \ + ((TIME) == ADC_SAMPLETIME_12CYCLES_5) || \ + ((TIME) == ADC_SAMPLETIME_19CYCLES_5) || \ + ((TIME) == ADC_SAMPLETIME_39CYCLES_5) || \ + ((TIME) == ADC_SAMPLETIME_79CYCLES_5) || \ + ((TIME) == ADC_SAMPLETIME_814CYCLES_5) ) + +#define IS_ADC_ANALOG_WATCHDOG_NUMBER(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_1) || \ + ((WATCHDOG) == ADC_ANALOGWATCHDOG_2) || \ + ((WATCHDOG) == ADC_ANALOGWATCHDOG_3) ) + +#define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) || \ + ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ + ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) ) + +#define IS_ADC_TRIGGER_FREQ(TRIGGER_FREQ) (((TRIGGER_FREQ) == LL_ADC_TRIGGER_FREQ_HIGH) || \ + ((TRIGGER_FREQ) == LL_ADC_TRIGGER_FREQ_LOW) ) + +#define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_EOSMP_EVENT) || \ + ((EVENT) == ADC_AWD1_EVENT) || \ + ((EVENT) == ADC_AWD2_EVENT) || \ + ((EVENT) == ADC_AWD3_EVENT) || \ + ((EVENT) == ADC_OVR_EVENT) ) + +/** + * @brief Verify that a given value is aligned with the ADC resolution range. + * @param __RESOLUTION__ ADC resolution (12, 10, 8 or 6 bits). + * @param __ADC_VALUE__ value checked against the resolution. + * @retval SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__) + */ +#define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \ + ((__ADC_VALUE__) <= __LL_ADC_DIGITAL_SCALE(__RESOLUTION__)) + +/** @defgroup ADC_regular_nb_conv_verification ADC Regular Conversion Number Verification + * @{ + */ +#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= 1UL) && ((LENGTH) <= 8UL)) +/** + * @} + */ + + +/* Private constants ---------------------------------------------------------*/ + +/** @defgroup ADC_Private_Constants ADC Private Constants + * @{ + */ + +/* Combination of all post-conversion flags bits: EOC/EOS, OVR, AWD */ +#define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_AWD | ADC_FLAG_OVR | ADC_FLAG_EOS | ADC_FLAG_EOC) + +/* Internal definition to differentiate sequencer setting fixed or configurable */ +#define ADC_SCAN_SEQ_FIXED_INT 0x80000000U + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup ADC_Exported_Macros ADC Exported Macros + * @{ + */ +/* Macro for internal HAL driver usage, and possibly can be used into code of */ +/* final user. */ + +/** @defgroup ADC_HAL_EM_HANDLE_IT_FLAG HAL ADC macro to manage HAL ADC handle, IT and flags. + * @{ + */ + +/** @brief Reset ADC handle state. + * @param __HANDLE__ ADC handle + * @retval None + */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ + do{ \ + (__HANDLE__)->State = HAL_ADC_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ + ((__HANDLE__)->State = HAL_ADC_STATE_RESET) +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + +/** + * @brief Enable ADC interrupt. + * @param __HANDLE__ ADC handle + * @param __INTERRUPT__ ADC Interrupt + * This parameter can be one of the following values: + * @arg @ref ADC_IT_RDY ADC Ready interrupt source + * @arg @ref ADC_IT_LDORDY ADC channel internal voltage regulator ready interrupt source + * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source + * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source + * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source + * @arg @ref ADC_IT_OVR ADC overrun interrupt source + * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) + * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) + * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) + * @retval None + */ +#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ + (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) + +/** + * @brief Disable ADC interrupt. + * @param __HANDLE__ ADC handle + * @param __INTERRUPT__ ADC Interrupt + * This parameter can be one of the following values: + * @arg @ref ADC_IT_RDY ADC Ready interrupt source + * @arg @ref ADC_IT_LDORDY ADC channel internal voltage regulator ready interrupt source + * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source + * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source + * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source + * @arg @ref ADC_IT_OVR ADC overrun interrupt source + * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) + * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) + * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) + * @retval None + */ +#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ + (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) + +/** @brief Checks if the specified ADC interrupt source is enabled or disabled. + * @param __HANDLE__ ADC handle + * @param __INTERRUPT__ ADC interrupt source to check + * This parameter can be one of the following values: + * @arg @ref ADC_IT_RDY ADC Ready interrupt source + * @arg @ref ADC_IT_LDORDY ADC channel internal voltage regulator ready interrupt source + * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source + * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source + * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source + * @arg @ref ADC_IT_OVR ADC overrun interrupt source + * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) + * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) + * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) + * @retval State of interruption (SET or RESET) + */ +#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ + (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) + +/** + * @brief Check whether the specified ADC flag is set or not. + * @param __HANDLE__ ADC handle + * @param __FLAG__ ADC flag + * This parameter can be one of the following values: + * @arg @ref ADC_FLAG_RDY ADC Ready flag + * @arg @ref ADC_FLAG_LDORDY ADC channel internal voltage regulator ready flag + * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag + * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag + * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag + * @arg @ref ADC_FLAG_OVR ADC overrun flag + * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog) + * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog) + * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog) + * @retval State of flag (TRUE or FALSE). + */ +#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \ + ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) + +/** + * @brief Clear the specified ADC flag. + * @param __HANDLE__ ADC handle + * @param __FLAG__ ADC flag + * This parameter can be one of the following values: + * @arg @ref ADC_FLAG_RDY ADC Ready flag + * @arg @ref ADC_FLAG_LDORDY ADC channel internal voltage regulator ready flag + * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag + * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag + * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag + * @arg @ref ADC_FLAG_OVR ADC overrun flag + * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog) + * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog) + * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog) + * @retval None + */ +/* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */ +#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \ + (((__HANDLE__)->Instance->ISR) = (__FLAG__)) + +/** + * @} + */ + +/** @defgroup ADC_HAL_EM_HELPER_MACRO HAL ADC helper macro + * @{ + */ + +/** + * @brief Helper macro to get ADC channel number in decimal format + * from literals ADC_CHANNEL_x. + * @note Example: + * __HAL_ADC_CHANNEL_TO_DECIMAL_NB(ADC_CHANNEL_4) + * will return decimal number "4". + * @note The input can be a value from functions where a channel + * number is returned, either defined with number + * or with bitfield (only one bit must be set). + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref ADC_CHANNEL_0 + * @arg @ref ADC_CHANNEL_1 + * @arg @ref ADC_CHANNEL_2 + * @arg @ref ADC_CHANNEL_3 + * @arg @ref ADC_CHANNEL_4 + * @arg @ref ADC_CHANNEL_5 + * @arg @ref ADC_CHANNEL_6 + * @arg @ref ADC_CHANNEL_7 + * @arg @ref ADC_CHANNEL_8 + * @arg @ref ADC_CHANNEL_9 + * @arg @ref ADC_CHANNEL_10 + * @arg @ref ADC_CHANNEL_11 + * @arg @ref ADC_CHANNEL_12 + * @arg @ref ADC_CHANNEL_13 + * @arg @ref ADC_CHANNEL_VREFINT + * @arg @ref ADC_CHANNEL_TEMPSENSOR + * @arg @ref ADC_CHANNEL_VCORE + * @retval Value between Min_Data=0 and Max_Data=18 + */ +#define __HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ + __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__)) + +/** + * @brief Helper macro to get ADC channel in literal format ADC_CHANNEL_x + * from number in decimal format. + * @note Example: + * __HAL_ADC_DECIMAL_NB_TO_CHANNEL(4) + * will return a data equivalent to "ADC_CHANNEL_4". + * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18 + * @retval Returned value can be one of the following values: + * @arg @ref ADC_CHANNEL_0 + * @arg @ref ADC_CHANNEL_1 + * @arg @ref ADC_CHANNEL_2 + * @arg @ref ADC_CHANNEL_3 + * @arg @ref ADC_CHANNEL_4 + * @arg @ref ADC_CHANNEL_5 + * @arg @ref ADC_CHANNEL_6 + * @arg @ref ADC_CHANNEL_7 + * @arg @ref ADC_CHANNEL_8 + * @arg @ref ADC_CHANNEL_9 + * @arg @ref ADC_CHANNEL_10 + * @arg @ref ADC_CHANNEL_11 + * @arg @ref ADC_CHANNEL_12 + * @arg @ref ADC_CHANNEL_13 + * @arg @ref ADC_CHANNEL_VREFINT (1) + * @arg @ref ADC_CHANNEL_TEMPSENSOR (1) + * @arg @ref ADC_CHANNEL_VCORE (1) + * + * (1) For ADC channel read back from ADC register, + * comparison with internal channel parameter to be done + * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). + */ +#define __HAL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ + __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__)) + +/** + * @brief Helper macro to determine whether the selected channel + * corresponds to literal definitions of driver. + * @note The different literal definitions of ADC channels are: + * - ADC internal channel: + * ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ... + * - ADC external channel (channel connected to a GPIO pin): + * ADC_CHANNEL_1, ADC_CHANNEL_2, ... + * @note The channel parameter must be a value defined from literal + * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, + * ADC_CHANNEL_TEMPSENSOR, ...), + * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...), + * must not be a value from functions where a channel number is + * returned from ADC registers, + * because internal and external channels share the same channel + * number in ADC registers. The differentiation is made only with + * parameters definitions of driver. + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref ADC_CHANNEL_0 + * @arg @ref ADC_CHANNEL_1 + * @arg @ref ADC_CHANNEL_2 + * @arg @ref ADC_CHANNEL_3 + * @arg @ref ADC_CHANNEL_4 + * @arg @ref ADC_CHANNEL_5 + * @arg @ref ADC_CHANNEL_6 + * @arg @ref ADC_CHANNEL_7 + * @arg @ref ADC_CHANNEL_8 + * @arg @ref ADC_CHANNEL_9 + * @arg @ref ADC_CHANNEL_10 + * @arg @ref ADC_CHANNEL_11 + * @arg @ref ADC_CHANNEL_12 + * @arg @ref ADC_CHANNEL_13 + * @arg @ref ADC_CHANNEL_VREFINT + * @arg @ref ADC_CHANNEL_TEMPSENSOR + * @arg @ref ADC_CHANNEL_VCORE + * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel + * (channel connected to a GPIO pin). + * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel. + */ +#define __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \ + __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__)) + +/** + * @brief Helper macro to convert a channel defined from parameter + * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, + * ADC_CHANNEL_TEMPSENSOR, ...), + * to its equivalent parameter definition of a ADC external channel + * (ADC_CHANNEL_1, ADC_CHANNEL_2, ...). + * @note The channel parameter can be, additionally to a value + * defined from parameter definition of a ADC internal channel + * (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...), + * a value defined from parameter definition of + * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...) + * or a value from functions where a channel number is returned + * from ADC registers. + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref ADC_CHANNEL_0 + * @arg @ref ADC_CHANNEL_1 + * @arg @ref ADC_CHANNEL_2 + * @arg @ref ADC_CHANNEL_3 + * @arg @ref ADC_CHANNEL_4 + * @arg @ref ADC_CHANNEL_5 + * @arg @ref ADC_CHANNEL_6 + * @arg @ref ADC_CHANNEL_7 + * @arg @ref ADC_CHANNEL_8 + * @arg @ref ADC_CHANNEL_9 + * @arg @ref ADC_CHANNEL_10 + * @arg @ref ADC_CHANNEL_11 + * @arg @ref ADC_CHANNEL_12 + * @arg @ref ADC_CHANNEL_13 + * @arg @ref ADC_CHANNEL_VREFINT + * @arg @ref ADC_CHANNEL_TEMPSENSOR + * @arg @ref ADC_CHANNEL_VCORE + * @retval Returned value can be one of the following values: + * @arg @ref ADC_CHANNEL_0 + * @arg @ref ADC_CHANNEL_1 + * @arg @ref ADC_CHANNEL_2 + * @arg @ref ADC_CHANNEL_3 + * @arg @ref ADC_CHANNEL_4 + * @arg @ref ADC_CHANNEL_5 + * @arg @ref ADC_CHANNEL_6 + * @arg @ref ADC_CHANNEL_7 + * @arg @ref ADC_CHANNEL_8 + * @arg @ref ADC_CHANNEL_9 + * @arg @ref ADC_CHANNEL_10 + * @arg @ref ADC_CHANNEL_11 + * @arg @ref ADC_CHANNEL_12 + * @arg @ref ADC_CHANNEL_13 + */ +#define __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \ + __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__)) + +/** + * @brief Helper macro to determine whether the internal channel + * selected is available on the ADC instance selected. + * @note The channel parameter must be a value defined from parameter + * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, + * ADC_CHANNEL_TEMPSENSOR, ...), + * must not be a value defined from parameter definition of + * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...) + * or a value from functions where a channel number is + * returned from ADC registers, + * because internal and external channels share the same channel + * number in ADC registers. The differentiation is made only with + * parameters definitions of driver. + * @param __ADC_INSTANCE__ ADC instance + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref ADC_CHANNEL_VREFINT + * @arg @ref ADC_CHANNEL_TEMPSENSOR + * @arg @ref ADC_CHANNEL_VCORE + * @retval Value "0" if the internal channel selected is not available on the ADC instance selected. + * Value "1" if the internal channel selected is available on the ADC instance selected. + */ +#define __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ + __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__)) + +/** + * @brief Helper macro to select the ADC common instance + * to which is belonging the selected ADC instance. + * @note ADC common register instance can be used for: + * - Set parameters common to several ADC instances + * - Multimode (for devices with several ADC instances) + * Refer to functions having argument "ADCxy_COMMON" as parameter. + * @param __ADCx__ ADC instance + * @retval ADC common register instance + */ +#define __HAL_ADC_COMMON_INSTANCE(__ADCx__) \ + __LL_ADC_COMMON_INSTANCE((__ADCx__)) + +/** + * @brief Helper macro to check if all ADC instances sharing the same + * ADC common instance are disabled. + * @note This check is required by functions with setting conditioned to + * ADC state: + * All ADC instances of the ADC common group must be disabled. + * Refer to functions having argument "ADCxy_COMMON" as parameter. + * @note On devices with only 1 ADC common instance, parameter of this macro + * is useless and can be ignored (parameter kept for compatibility + * with devices featuring several ADC common instances). + * @param __ADCXY_COMMON__ ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval Value "0" if all ADC instances sharing the same ADC common instance + * are disabled. + * Value "1" if at least one ADC instance sharing the same ADC common instance + * is enabled. + */ +#define __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ + __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__)) + +/** + * @brief Helper macro to define the ADC conversion data full-scale digital + * value corresponding to the selected ADC resolution. + * @note ADC conversion data full-scale corresponds to voltage range + * determined by analog voltage references Vref+ and Vref- + * (refer to reference manual). + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref ADC_RESOLUTION_12B + * @arg @ref ADC_RESOLUTION_10B + * @arg @ref ADC_RESOLUTION_8B + * @arg @ref ADC_RESOLUTION_6B + * @retval ADC conversion data full-scale digital value + */ +#define __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ + __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__)) + +/** + * @brief Helper macro to convert the ADC conversion data from + * a resolution to another resolution. + * @param __DATA__ ADC conversion data to be converted + * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted + * This parameter can be one of the following values: + * @arg @ref ADC_RESOLUTION_12B + * @arg @ref ADC_RESOLUTION_10B + * @arg @ref ADC_RESOLUTION_8B + * @arg @ref ADC_RESOLUTION_6B + * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion + * This parameter can be one of the following values: + * @arg @ref ADC_RESOLUTION_12B + * @arg @ref ADC_RESOLUTION_10B + * @arg @ref ADC_RESOLUTION_8B + * @arg @ref ADC_RESOLUTION_6B + * @retval ADC conversion data to the requested resolution + */ +#define __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\ + __ADC_RESOLUTION_CURRENT__,\ + __ADC_RESOLUTION_TARGET__) \ +__LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__),\ + (__ADC_RESOLUTION_CURRENT__),\ + (__ADC_RESOLUTION_TARGET__)) + +/** + * @brief Helper macro to calculate the voltage (unit: mVolt) + * corresponding to a ADC conversion data (unit: digital value). + * @note Analog reference voltage (Vref+) must be either known from + * user board environment or can be calculated using ADC measurement + * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). + * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) + * @param __ADC_DATA__ ADC conversion data (resolution 12 bits) + * (unit: digital value). + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref ADC_RESOLUTION_12B + * @arg @ref ADC_RESOLUTION_10B + * @arg @ref ADC_RESOLUTION_8B + * @arg @ref ADC_RESOLUTION_6B + * @retval ADC conversion data equivalent voltage value (unit: mVolt) + */ +#define __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ + __ADC_DATA__,\ + __ADC_RESOLUTION__) \ +__LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\ + (__ADC_DATA__),\ + (__ADC_RESOLUTION__)) + +/** + * @brief Helper macro to calculate analog reference voltage (Vref+) + * (unit: mVolt) from ADC conversion data of internal voltage + * reference VrefInt. + * @note Computation is using VrefInt calibration value + * stored in system memory for each device during production. + * @note This voltage depends on user board environment: voltage level + * connected to pin Vref+. + * On devices with small package, the pin Vref+ is not present + * and internally bonded to pin Vdda. + * @note On this STM32 series, calibration data of internal voltage reference + * VrefInt corresponds to a resolution of 12 bits, + * this is the recommended ADC resolution to convert voltage of + * internal voltage reference VrefInt. + * Otherwise, this macro performs the processing to scale + * ADC conversion data to 12 bits. + * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits) + * of internal voltage reference VrefInt (unit: digital value). + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref ADC_RESOLUTION_12B + * @arg @ref ADC_RESOLUTION_10B + * @arg @ref ADC_RESOLUTION_8B + * @arg @ref ADC_RESOLUTION_6B + * @retval Analog reference voltage (unit: mV) + */ +#define __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\ + __ADC_RESOLUTION__) \ +__LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__),\ + (__ADC_RESOLUTION__)) + +/** + * @brief Helper macro to calculate the temperature (unit: degree Celsius) + * from ADC conversion data of internal temperature sensor. + * @note Computation is using temperature sensor calibration values + * stored in system memory for each device during production. + * @note Calculation formula: + * Temperature = ((TS_ADC_DATA - TS_CAL1) + * * (TS_CAL2_TEMP - TS_CAL1_TEMP)) + * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP + * with TS_ADC_DATA = temperature sensor raw data measured by ADC + * Avg_Slope = (TS_CAL2 - TS_CAL1) + * / (TS_CAL2_TEMP - TS_CAL1_TEMP) + * TS_CAL1 = equivalent TS_ADC_DATA at temperature + * TEMP_DEGC_CAL1 (calibrated in factory) + * TS_CAL2 = equivalent TS_ADC_DATA at temperature + * TEMP_DEGC_CAL2 (calibrated in factory) + * Caution: Calculation relevancy under reserve that calibration + * parameters are correct (address and data). + * To calculate temperature using temperature sensor + * datasheet typical values (generic values less, therefore + * less accurate than calibrated values), + * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(). + * @note As calculation input, the analog reference voltage (Vref+) must be + * defined as it impacts the ADC LSB equivalent voltage. + * @note Analog reference voltage (Vref+) must be either known from + * user board environment or can be calculated using ADC measurement + * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). + * @note On this STM32 series, calibration data of temperature sensor + * corresponds to a resolution of 12 bits, + * this is the recommended ADC resolution to convert voltage of + * temperature sensor. + * Otherwise, this macro performs the processing to scale + * ADC conversion data to 12 bits. + * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) + * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal + * temperature sensor (unit: digital value). + * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature + * sensor voltage has been measured. + * This parameter can be one of the following values: + * @arg @ref ADC_RESOLUTION_12B + * @arg @ref ADC_RESOLUTION_10B + * @arg @ref ADC_RESOLUTION_8B + * @arg @ref ADC_RESOLUTION_6B + * @retval Temperature (unit: degree Celsius) + */ +#define __HAL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\ + __TEMPSENSOR_ADC_DATA__,\ + __ADC_RESOLUTION__) \ +__LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__),\ + (__TEMPSENSOR_ADC_DATA__),\ + (__ADC_RESOLUTION__)) + +/** + * @brief Helper macro to calculate the temperature (unit: degree Celsius) + * from ADC conversion data of internal temperature sensor. + * @note Computation is using temperature sensor typical values + * (refer to device datasheet). + * @note Calculation formula: + * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV) + * / Avg_Slope + CALx_TEMP + * with TS_ADC_DATA = temperature sensor raw data measured by ADC + * (unit: digital value) + * Avg_Slope = temperature sensor slope + * (unit: uV/Degree Celsius) + * TS_TYP_CALx_VOLT = temperature sensor digital value at + * temperature CALx_TEMP (unit: mV) + * Caution: Calculation relevancy under reserve the temperature sensor + * of the current device has characteristics in line with + * datasheet typical values. + * If temperature sensor calibration values are available on + * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()), + * temperature calculation will be more accurate using + * helper macro @ref __LL_ADC_CALC_TEMPERATURE(). + * @note As calculation input, the analog reference voltage (Vref+) must be + * defined as it impacts the ADC LSB equivalent voltage. + * @note Analog reference voltage (Vref+) must be either known from + * user board environment or can be calculated using ADC measurement + * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). + * @note ADC measurement data must correspond to a resolution of 12bits + * (full scale digital value 4095). If not the case, the data must be + * preliminarily rescaled to an equivalent resolution of 12 bits. + * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value + (unit: uV/DegCelsius). + * On this STM32 series, refer to device datasheet parameter "Avg_Slope". + * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at + temperature and Vref+ defined in parameters below) (unit: mV). + * On this STM32 series, refer to device datasheet parameter "V30" + * (corresponding to TS_CAL1). + * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see + parameter above) is corresponding (unit: mV) + * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV) + * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value). + * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. + * This parameter can be one of the following values: + * @arg @ref ADC_RESOLUTION_12B + * @arg @ref ADC_RESOLUTION_10B + * @arg @ref ADC_RESOLUTION_8B + * @arg @ref ADC_RESOLUTION_6B + * @retval Temperature (unit: degree Celsius) + */ +#define __HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\ + __TEMPSENSOR_TYP_CALX_V__,\ + __TEMPSENSOR_CALX_TEMP__,\ + __VREFANALOG_VOLTAGE__,\ + __TEMPSENSOR_ADC_DATA__,\ + __ADC_RESOLUTION__) \ +__LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__),\ + (__TEMPSENSOR_TYP_CALX_V__),\ + (__TEMPSENSOR_CALX_TEMP__),\ + (__VREFANALOG_VOLTAGE__),\ + (__TEMPSENSOR_ADC_DATA__),\ + (__ADC_RESOLUTION__)) + +/** + * @} + */ + +/** + * @} + */ + +/* Include ADC HAL Extended module */ +#include "stm32wbaxx_hal_adc_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup ADC_Exported_Functions + * @{ + */ + +/** @addtogroup ADC_Exported_Functions_Group1 + * @brief Initialization and Configuration functions + * @{ + */ +/* Initialization and de-initialization functions ****************************/ +HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); +void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc); +void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc); + +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +/* Callbacks Register/UnRegister functions ***********************************/ +HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, + pADC_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @addtogroup ADC_Exported_Functions_Group2 + * @brief IO operation functions + * @{ + */ +/* IO operation functions *****************************************************/ + +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout); +HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout); + +/* Non-blocking mode: Interruption */ +HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc); + +/* Non-blocking mode: DMA */ +HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); +HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc); + +/* ADC retrieve conversion value intended to be used with polling or interruption */ +uint32_t HAL_ADC_GetValue(const ADC_HandleTypeDef *hadc); + +/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */ +void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc); +void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc); +void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc); +void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc); +void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); +/** + * @} + */ + +/** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions + * @brief Peripheral Control functions + * @{ + */ +/* Peripheral Control functions ***********************************************/ +HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, const ADC_ChannelConfTypeDef *pConfig); +HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, + const ADC_AnalogWDGConfTypeDef *pAnalogWDGConfig); + +/** + * @} + */ + +/* Peripheral State functions *************************************************/ +/** @addtogroup ADC_Exported_Functions_Group4 + * @{ + */ +uint32_t HAL_ADC_GetState(const ADC_HandleTypeDef *hadc); +uint32_t HAL_ADC_GetError(const ADC_HandleTypeDef *hadc); + +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32WBAxx_HAL_ADC_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_adc_ex.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_adc_ex.h new file mode 100644 index 0000000000..8609f236de --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_adc_ex.h @@ -0,0 +1,186 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_adc_ex.h + * @author MCD Application Team + * @brief Header file of ADC HAL extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_HAL_ADC_EX_H +#define STM32WBAxx_HAL_ADC_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal_def.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @addtogroup ADCEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup ADCEx_Exported_Types ADC Extended Exported Types + * @{ + */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup ADCEx_Exported_Constants ADC Extended Exported Constants + * @{ + */ + +/** @defgroup ADC_HAL_EC_GROUPS ADC instance - Groups + * @{ + */ +#define ADC_REGULAR_GROUP (LL_ADC_GROUP_REGULAR) /*!< ADC group regular (available on + all STM32 devices) */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ + +/** @defgroup ADCEx_Private_Macro_internal_HAL_driver ADC Extended Private Macros + * @{ + */ +/* Macro reserved for internal HAL driver usage, not intended to be used in */ +/* code of final user. */ + +/** + * @brief Check whether or not ADC is independent. + * @param __HANDLE__ ADC handle. + * @note When multimode feature is not available, the macro always returns SET. + * @retval SET (ADC is independent) or RESET (ADC is not). + */ +#define ADC_IS_INDEPENDENT(__HANDLE__) (SET) + + +/** + * @brief Calibration factor size verification (7 bits maximum). + * @param __CALIBRATION_FACTOR__ Calibration factor value. + * @retval SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large) + */ +#define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FU)) + +/** + * @brief Verify the ADC oversampling ratio. + * @param __RATIO__ programmed ADC oversampling ratio. + * @retval SET (__RATIO__ is a valid value) or RESET (__RATIO__ is invalid) + */ +#define IS_ADC_OVERSAMPLING_RATIO(__RATIO__) (((__RATIO__) == ADC_OVERSAMPLING_RATIO_2 ) || \ + ((__RATIO__) == ADC_OVERSAMPLING_RATIO_4 ) || \ + ((__RATIO__) == ADC_OVERSAMPLING_RATIO_8 ) || \ + ((__RATIO__) == ADC_OVERSAMPLING_RATIO_16 ) || \ + ((__RATIO__) == ADC_OVERSAMPLING_RATIO_32 ) || \ + ((__RATIO__) == ADC_OVERSAMPLING_RATIO_64 ) || \ + ((__RATIO__) == ADC_OVERSAMPLING_RATIO_128 ) || \ + ((__RATIO__) == ADC_OVERSAMPLING_RATIO_256 )) + +/** + * @brief Verify the ADC oversampling shift. + * @param __SHIFT__ programmed ADC oversampling shift. + * @retval SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid) + */ +#define IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__) (((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) || \ + ((__SHIFT__) == ADC_RIGHTBITSHIFT_1 ) || \ + ((__SHIFT__) == ADC_RIGHTBITSHIFT_2 ) || \ + ((__SHIFT__) == ADC_RIGHTBITSHIFT_3 ) || \ + ((__SHIFT__) == ADC_RIGHTBITSHIFT_4 ) || \ + ((__SHIFT__) == ADC_RIGHTBITSHIFT_5 ) || \ + ((__SHIFT__) == ADC_RIGHTBITSHIFT_6 ) || \ + ((__SHIFT__) == ADC_RIGHTBITSHIFT_7 ) || \ + ((__SHIFT__) == ADC_RIGHTBITSHIFT_8 )) + +/** + * @brief Verify the ADC oversampling triggered mode. + * @param __MODE__ programmed ADC oversampling triggered mode. + * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) + */ +#define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \ + ((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) ) + + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup ADCEx_Exported_Functions + * @{ + */ + +/** @addtogroup ADCEx_Exported_Functions_Group1 + * @{ + */ +/* IO operation functions *****************************************************/ + +/* ADC calibration */ +HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc); +uint32_t HAL_ADCEx_Calibration_GetValue(const ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t CalibrationFactor); + +/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */ +void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc); +void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc); +void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc); +void HAL_ADCEx_LDOReadyCallback(ADC_HandleTypeDef *hadc); + +/** + * @} + */ + +/** @addtogroup ADCEx_Exported_Functions_Group2 + * @{ + */ +/* Peripheral Control functions ***********************************************/ +HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WBAxx_HAL_ADC_EX_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_comp.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_comp.h new file mode 100644 index 0000000000..8403ffa5d7 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_comp.h @@ -0,0 +1,793 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_comp.h + * @author MCD Application Team + * @brief Header file of COMP HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_HAL_COMP_H +#define STM32WBAxx_HAL_COMP_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal_def.h" +#include "stm32wbaxx_ll_exti.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ +#if defined (COMP1) || defined (COMP2) + +/** @addtogroup COMP + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup COMP_Exported_Types COMP Exported Types + * @{ + */ + +/** + * @brief COMP Init structure definition + */ +typedef struct +{ + + uint32_t WindowMode; /*!< Set window mode of a pair of comparators instances + (2 consecutive instances odd and even COMP and COMP). + Note: HAL COMP driver allows to set window mode from any COMP + instance of the pair of COMP instances composing window mode. + This parameter can be a value of @ref COMP_WindowMode */ + + uint32_t WindowOutput; /*!< Set window mode output. + This parameter can be a value of @ref COMP_WindowOutput */ + + uint32_t Mode; /*!< Set comparator operating mode to adjust power and speed. + Note: For the characteristics of comparator power modes + (propagation delay and power consumption), refer to device datasheet. + This parameter can be a value of @ref COMP_PowerMode */ + + uint32_t InputPlus; /*!< Set comparator input plus (non-inverting input). + This parameter can be a value of @ref COMP_InputPlus */ + + uint32_t InputMinus; /*!< Set comparator input minus (inverting input). + This parameter can be a value of @ref COMP_InputMinus */ + + uint32_t Hysteresis; /*!< Set comparator hysteresis mode of the input minus. + This parameter can be a value of @ref COMP_Hysteresis */ + + uint32_t OutputPol; /*!< Set comparator output polarity. + This parameter can be a value of @ref COMP_OutputPolarity */ + + uint32_t BlankingSrce; /*!< Set comparator blanking source. + This parameter can be a value of @ref COMP_BlankingSrce */ + + uint32_t TriggerMode; /*!< Set the comparator output triggering External Interrupt Line (EXTI). + This parameter can be a value of @ref COMP_EXTI_TriggerMode */ + +} COMP_InitTypeDef; + +/** + * @brief HAL COMP state machine: HAL COMP states definition + */ +#define COMP_STATE_BITFIELD_LOCK (0x10U) +typedef enum +{ + HAL_COMP_STATE_RESET = 0x00U, /*!< COMP not yet initialized */ + HAL_COMP_STATE_RESET_LOCKED = (HAL_COMP_STATE_RESET | COMP_STATE_BITFIELD_LOCK), /*!< COMP not yet initialized and configuration is locked */ + HAL_COMP_STATE_READY = 0x01U, /*!< COMP initialized and ready for use */ + HAL_COMP_STATE_READY_LOCKED = (HAL_COMP_STATE_READY | COMP_STATE_BITFIELD_LOCK), /*!< COMP initialized but configuration is locked */ + HAL_COMP_STATE_BUSY = 0x02U, /*!< COMP is running */ + HAL_COMP_STATE_BUSY_LOCKED = (HAL_COMP_STATE_BUSY | COMP_STATE_BITFIELD_LOCK) /*!< COMP is running and configuration is locked */ +} HAL_COMP_StateTypeDef; + +/** + * @brief COMP Handle Structure definition + */ +#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1) +typedef struct __COMP_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */ +{ + COMP_TypeDef *Instance; /*!< Register base address */ + COMP_InitTypeDef Init; /*!< COMP required parameters */ + HAL_LockTypeDef Lock; /*!< Locking object */ + __IO HAL_COMP_StateTypeDef State; /*!< COMP communication state */ + __IO uint32_t ErrorCode; /*!< COMP error code */ +#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1) + void (* TriggerCallback)(struct __COMP_HandleTypeDef *hcomp); /*!< COMP trigger callback */ + void (* MspInitCallback)(struct __COMP_HandleTypeDef *hcomp); /*!< COMP Msp Init callback */ + void (* MspDeInitCallback)(struct __COMP_HandleTypeDef *hcomp); /*!< COMP Msp DeInit callback */ +#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */ +} COMP_HandleTypeDef; + +#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1) +/** + * @brief HAL COMP Callback ID enumeration definition + */ +typedef enum +{ + HAL_COMP_TRIGGER_CB_ID = 0x00U, /*!< COMP trigger callback ID */ + HAL_COMP_MSPINIT_CB_ID = 0x01U, /*!< COMP Msp Init callback ID */ + HAL_COMP_MSPDEINIT_CB_ID = 0x02U /*!< COMP Msp DeInit callback ID */ +} HAL_COMP_CallbackIDTypeDef; + +/** + * @brief HAL COMP Callback pointer definition + */ +typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer to a COMP callback function */ + +#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup COMP_Exported_Constants COMP Exported Constants + * @{ + */ + +/** @defgroup COMP_Error_Code COMP Error Code + * @{ + */ +#define HAL_COMP_ERROR_NONE (0x00UL) /*!< No error */ +#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1) +#define HAL_COMP_ERROR_INVALID_CALLBACK (0x01UL) /*!< Invalid Callback error */ +#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */ +/** + * @} + */ + + +/** @defgroup COMP_WindowMode COMP Window Mode + * @{ + */ +#define COMP_WINDOWMODE_DISABLE (0x00000000UL) /*!< Window mode disable: Comparators + instances pair COMP1 and COMP2 are + independent */ +#define COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_WINMODE) /*!< Window mode enable: Comparators instances + pair COMP1 and COMP2 have their input + plus connected together. + The common input is COMP1 input plus + (COMP2 input plus is no more accessible). + */ +#define COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON (COMP_CSR_WINMODE \ + | COMP_WINDOWMODE_COMP2) /*!< Window mode enable: if used from COMP1 or + COMP2 instance, comparators instances + pair COMP1 and COMP2 have their input + plus connected together, the common input + is COMP2 input plus (COMP1 input plus is + no more accessible). */ +/** + * @} + */ + +/** @defgroup COMP_WindowOutput COMP Window output + * @{ + */ +#define COMP_WINDOWOUTPUT_EACH_COMP (0x00000000UL) /*!< Window output default mode: Comparators output are + indicating each their own state. + To know window mode state: each comparator output + must be read, if "((COMPx exclusive or COMPy) == 1)" + then monitored signal is within comparators window.*/ +#define COMP_WINDOWOUTPUT_COMP1 (COMP_CSR_WINOUT) /*!< Window output synthesized on COMP1 output: + COMP1 output is no more indicating its own state, but + global window mode state (logical high means + monitored signal is within comparators window). + Note: impacts only comparator output signal level + (COMPx_OUT propagated to GPIO, EXTI lines, + timers, ...), does not impact output digital state + of comparator (COMPx_VALUE) always reflecting each + comparator output state.*/ +#define COMP_WINDOWOUTPUT_COMP2 (COMP_CSR_WINOUT \ + | COMP_WINDOWMODE_COMP2) /*!< Window output synthesized on COMP2 output: + COMP2 output is no more indicating its own state, but + global window mode state (logical high means + monitored signal is within comparators window). + Note: impacts only comparator output signal level + (COMPx_OUT propagated to GPIO, EXTI lines, + timers, ...), does not impact output digital state + of comparator (COMPx_VALUE) always reflecting each + comparator output state.*/ +#define COMP_WINDOWOUTPUT_BOTH (0x00000001UL) /*!< Window output synthesized on both comparators output + of pair of comparator selected (COMP1 and COMP2: + both comparators outputs are no more indicating their + own state, but global window mode state (logical high + means monitored signal is within comparators window). + This is a specific configuration (technically + possible but not relevant from application + point of view: + 2 comparators output used for the same signal level), + standard configuration for window mode is one of the + settings above. */ +/** + * @} + */ + + +/** @defgroup COMP_PowerMode COMP power mode + * @{ + */ +/* Note: For the characteristics of comparator power modes */ +/* (propagation delay and power consumption), */ +/* refer to device datasheet. */ +#define COMP_POWERMODE_HIGHSPEED (0x00000000UL) /*!< High Speed */ +#define COMP_POWERMODE_MEDIUMSPEED (COMP_CSR_PWRMODE_0) /*!< Medium Speed */ +/** + * @} + */ + +/** @defgroup COMP_InputPlus COMP input plus (non-inverting input) + * @{ + */ +#define COMP_INPUT_PLUS_IO1 (0x00000000UL) /*!< Comparator input plus connected to IO1 (pin PA2 for COMP1, pin PA0 for COMP2) */ +/** + * @} + */ + +/** @defgroup COMP_InputMinus COMP input minus (inverting input) + * @{ + */ +#define COMP_INPUT_MINUS_1_4VREFINT (0x00000000UL) /*!< Comparator input minus connected to 1/4 VrefInt */ +#define COMP_INPUT_MINUS_1_2VREFINT ( COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to 1/2 VrefInt */ +#define COMP_INPUT_MINUS_3_4VREFINT ( COMP_CSR_INMSEL_1 ) /*!< Comparator input minus connected to 3/4 VrefInt */ +#define COMP_INPUT_MINUS_VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to VrefInt */ +#define COMP_INPUT_MINUS_IO1 ( COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 ) /*!< Comparator input minus connected to IO1 (pin PA1 for COMP1, pin PB9 for COMP2) */ +/** + * @} + */ + +/** @defgroup COMP_Hysteresis COMP hysteresis + * @{ + */ +#define COMP_HYSTERESIS_NONE (0x00000000UL) /*!< No hysteresis */ +#define COMP_HYSTERESIS_LOW ( COMP_CSR_HYST_0) /*!< Hysteresis level low */ +#define COMP_HYSTERESIS_MEDIUM (COMP_CSR_HYST_1 ) /*!< Hysteresis level medium */ +#define COMP_HYSTERESIS_HIGH (COMP_CSR_HYST_1 | COMP_CSR_HYST_0) /*!< Hysteresis level high */ +/** + * @} + */ + +/** @defgroup COMP_OutputPolarity COMP output Polarity + * @{ + */ +#define COMP_OUTPUTPOL_NONINVERTED (0x00000000UL) /*!< COMP output level is not inverted (comparator output is high when the input plus is at a higher voltage than the input minus) */ +#define COMP_OUTPUTPOL_INVERTED (COMP_CSR_POLARITY) /*!< COMP output level is inverted (comparator output is low when the input plus is at a higher voltage than the input minus) */ +/** + * @} + */ + +/** @defgroup COMP_BlankingSrce COMP blanking source + * @{ + */ +#define COMP_BLANKINGSRC_NONE (0x00000000UL) /*!State = HAL_COMP_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_COMP_STATE_RESET) +#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */ + +/** + * @brief Clear COMP error code (set it to no error code "HAL_COMP_ERROR_NONE"). + * @param __HANDLE__ COMP handle + * @retval None + */ +#define COMP_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_COMP_ERROR_NONE) + +/** + * @brief Enable the specified comparator. + * @param __HANDLE__ COMP handle + * @retval None + */ +#define __HAL_COMP_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN) + +/** + * @brief Disable the specified comparator. + * @param __HANDLE__ COMP handle + * @retval None + */ +#define __HAL_COMP_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN) + +/** + * @brief Lock the specified comparator configuration. + * @note Using this macro induce HAL COMP handle state machine being no + * more in line with COMP instance state. + * To keep HAL COMP handle state machine updated, it is recommended + * to use function "HAL_COMP_Lock')". + * @param __HANDLE__ COMP handle + * @retval None + */ +#define __HAL_COMP_LOCK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK) + +/** + * @brief Check whether the specified comparator is locked. + * @param __HANDLE__ COMP handle + * @retval Value 0 if COMP instance is not locked, value 1 if COMP instance is locked + */ +#define __HAL_COMP_IS_LOCKED(__HANDLE__) (READ_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK) == COMP_CSR_LOCK) + +/** + * @} + */ + +/** @defgroup COMP_Exti_Management COMP external interrupt line management + * @{ + */ +/** + * @brief Enable the COMP1 EXTI line rising edge trigger. + * @retval None + */ +#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP1) + +/** + * @brief Disable the COMP1 EXTI line rising edge trigger. + * @retval None + */ +#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP1) + +/** + * @brief Enable the COMP1 EXTI line falling edge trigger. + * @retval None + */ +#define __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP1) + +/** + * @brief Disable the COMP1 EXTI line falling edge trigger. + * @retval None + */ +#define __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP1) + +/** + * @brief Enable the COMP1 EXTI line rising & falling edge trigger. + * @retval None + */ +#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ + LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \ + LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP1);\ + } while(0) + +/** + * @brief Disable the COMP1 EXTI line rising & falling edge trigger. + * @retval None + */ +#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ + LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \ + LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP1);\ + } while(0) + +/** + * @brief Enable the COMP1 EXTI line in interrupt mode. + * @retval None + */ +#define __HAL_COMP_COMP1_EXTI_ENABLE_IT() LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP1) + +/** + * @brief Disable the COMP1 EXTI line in interrupt mode. + * @retval None + */ +#define __HAL_COMP_COMP1_EXTI_DISABLE_IT() LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP1) + +/** + * @brief Generate a software interrupt on the COMP1 EXTI line. + * @retval None + */ +#define __HAL_COMP_COMP1_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP1) + +/** + * @brief Enable the COMP1 EXTI line in event mode. + * @retval None + */ +#define __HAL_COMP_COMP1_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP1) + +/** + * @brief Disable the COMP1 EXTI line in event mode. + * @retval None + */ +#define __HAL_COMP_COMP1_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP1) + +/** + * @brief Check whether the COMP1 EXTI line rising flag is set. + * @retval RESET or SET + */ +#define __HAL_COMP_COMP1_EXTI_GET_RISING_FLAG() LL_EXTI_IsActiveRisingFlag_0_31(COMP_EXTI_LINE_COMP1) + +/** + * @brief Clear the COMP1 EXTI rising flag. + * @retval None + */ +#define __HAL_COMP_COMP1_EXTI_CLEAR_RISING_FLAG() LL_EXTI_ClearRisingFlag_0_31(COMP_EXTI_LINE_COMP1) + +/** + * @brief Check whether the COMP1 EXTI line falling flag is set. + * @retval RESET or SET + */ +#define __HAL_COMP_COMP1_EXTI_GET_FALLING_FLAG() LL_EXTI_IsActiveFallingFlag_0_31(COMP_EXTI_LINE_COMP1) + +/** + * @brief Clear the COMP1 EXTI falling flag. + * @retval None + */ +#define __HAL_COMP_COMP1_EXTI_CLEAR_FALLING_FLAG() LL_EXTI_ClearFallingFlag_0_31(COMP_EXTI_LINE_COMP1) + +/** + * @brief Enable the COMP2 EXTI line rising edge trigger. + * @retval None + */ +#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP2) + +/** + * @brief Disable the COMP2 EXTI line rising edge trigger. + * @retval None + */ +#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP2) + +/** + * @brief Enable the COMP2 EXTI line falling edge trigger. + * @retval None + */ +#define __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP2) + +/** + * @brief Disable the COMP2 EXTI line falling edge trigger. + * @retval None + */ +#define __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP2) + +/** + * @brief Enable the COMP2 EXTI line rising & falling edge trigger. + * @retval None + */ +#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ + LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP2);\ + LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP2);\ + } while(0) + +/** + * @brief Disable the COMP2 EXTI line rising & falling edge trigger. + * @retval None + */ +#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ + LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP2);\ + LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP2);\ + } while(0) + +/** + * @brief Enable the COMP2 EXTI line in interrupt mode. + * @retval None + */ +#define __HAL_COMP_COMP2_EXTI_ENABLE_IT() LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP2) + +/** + * @brief Disable the COMP2 EXTI line in interrupt mode. + * @retval None + */ +#define __HAL_COMP_COMP2_EXTI_DISABLE_IT() LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP2) + +/** + * @brief Generate a software interrupt on the COMP2 EXTI line. + * @retval None + */ +#define __HAL_COMP_COMP2_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP2) + +/** + * @brief Enable the COMP2 EXTI line in event mode. + * @retval None + */ +#define __HAL_COMP_COMP2_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP2) + +/** + * @brief Disable the COMP2 EXTI line in event mode. + * @retval None + */ +#define __HAL_COMP_COMP2_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP2) + +/** + * @brief Check whether the COMP2 EXTI line rising flag is set. + * @retval RESET or SET + */ +#define __HAL_COMP_COMP2_EXTI_GET_RISING_FLAG() LL_EXTI_IsActiveRisingFlag_0_31(COMP_EXTI_LINE_COMP2) + +/** + * @brief Clear the COMP2 EXTI rising flag. + * @retval None + */ +#define __HAL_COMP_COMP2_EXTI_CLEAR_RISING_FLAG() LL_EXTI_ClearRisingFlag_0_31(COMP_EXTI_LINE_COMP2) + +/** + * @brief Check whether the COMP2 EXTI line falling flag is set. + * @retval RESET or SET + */ +#define __HAL_COMP_COMP2_EXTI_GET_FALLING_FLAG() LL_EXTI_IsActiveFallingFlag_0_31(COMP_EXTI_LINE_COMP2) + +/** + * @brief Clear the COMP2 EXTI falling flag. + * @retval None + */ +#define __HAL_COMP_COMP2_EXTI_CLEAR_FALLING_FLAG() LL_EXTI_ClearFallingFlag_0_31(COMP_EXTI_LINE_COMP2) + +/** + * @} + */ + +/** + * @} + */ + + +/* Private types -------------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup COMP_Private_Constants COMP Private Constants + * @{ + */ + +/** @defgroup COMP_WindowMode_Instance_Differentiator COMP window mode instance differentiator + * @{ + */ +#define COMP_WINDOWMODE_COMP2 0x00001000U /*!< COMP window mode using common input of COMP instance: COMP2 */ +/** + * @} + */ + +/** @defgroup COMP_ExtiLine COMP EXTI Lines + * @{ + */ +#define COMP_EXTI_LINE_COMP1 (EXTI_IMR1_IM17) /*!< EXTI line 17 connected to COMP1 output */ +#define COMP_EXTI_LINE_COMP2 (EXTI_IMR1_IM18) /*!< EXTI line 18 connected to COMP2 output */ +/** + * @} + */ + +/** @defgroup COMP_ExtiLine COMP EXTI Lines + * @{ + */ +#define COMP_EXTI_IT (0x00000001UL) /*!< EXTI line event with interruption */ +#define COMP_EXTI_EVENT (0x00000002UL) /*!< EXTI line event only (without interruption) */ +#define COMP_EXTI_RISING (0x00000010UL) /*!< EXTI line event on rising edge */ +#define COMP_EXTI_FALLING (0x00000020UL) /*!< EXTI line event on falling edge */ +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup COMP_Private_Macros COMP Private Macros + * @{ + */ + +/** @defgroup COMP_GET_EXTI_LINE COMP private macros to get EXTI line associated with comparators + * @{ + */ +/** + * @brief Get the specified EXTI line for a comparator instance. + * @param __INSTANCE__ specifies the COMP instance. + * @retval value of @ref COMP_ExtiLine + */ +#define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 \ + : COMP_EXTI_LINE_COMP2) +/** + * @} + */ + +/** @defgroup COMP_IS_COMP_Private_Definitions COMP private macros to check input parameters + * @{ + */ +#define IS_COMP_WINDOWMODE(__INSTANCE__, __WINDOWMODE__) \ + (((__WINDOWMODE__) == COMP_WINDOWMODE_DISABLE) || \ + ((__WINDOWMODE__) == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON)|| \ + ((__WINDOWMODE__) == COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON) ) + +#define IS_COMP_WINDOWOUTPUT(__WINDOWOUTPUT__) (((__WINDOWOUTPUT__) == COMP_WINDOWOUTPUT_EACH_COMP) || \ + ((__WINDOWOUTPUT__) == COMP_WINDOWOUTPUT_COMP1) || \ + ((__WINDOWOUTPUT__) == COMP_WINDOWOUTPUT_COMP2) || \ + ((__WINDOWOUTPUT__) == COMP_WINDOWOUTPUT_BOTH) ) + +#define IS_COMP_POWERMODE(__POWERMODE__) (((__POWERMODE__) == COMP_POWERMODE_HIGHSPEED) || \ + ((__POWERMODE__) == COMP_POWERMODE_MEDIUMSPEED) ) + +#define IS_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO1) + +/* Note: On this STM32 series, comparator input minus parameters are */ +/* the same on all COMP instances. */ +/* However, comparator instance kept as macro parameter for */ +/* compatibility with other STM32 families. */ +#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT) ||\ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT) ||\ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT) ||\ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT) ||\ + ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1)) + +#define IS_COMP_HYSTERESIS(__HYSTERESIS__) (((__HYSTERESIS__) == COMP_HYSTERESIS_NONE) || \ + ((__HYSTERESIS__) == COMP_HYSTERESIS_LOW) || \ + ((__HYSTERESIS__) == COMP_HYSTERESIS_MEDIUM) || \ + ((__HYSTERESIS__) == COMP_HYSTERESIS_HIGH)) + +#define IS_COMP_OUTPUTPOL(__POL__) (((__POL__) == COMP_OUTPUTPOL_NONINVERTED) || \ + ((__POL__) == COMP_OUTPUTPOL_INVERTED)) + +#define IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \ + ((((__INSTANCE__) == COMP1) && \ + (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \ + ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) || \ + ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1) || \ + ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1))) \ + || \ + (((__INSTANCE__) == COMP2) && \ + (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \ + ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4_COMP2)))) + + +#define IS_COMP_TRIGGERMODE(__MODE__) (((__MODE__) == COMP_TRIGGERMODE_NONE) || \ + ((__MODE__) == COMP_TRIGGERMODE_IT_RISING) || \ + ((__MODE__) == COMP_TRIGGERMODE_IT_FALLING) || \ + ((__MODE__) == COMP_TRIGGERMODE_IT_RISING_FALLING) || \ + ((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING) || \ + ((__MODE__) == COMP_TRIGGERMODE_EVENT_FALLING) || \ + ((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING_FALLING)) + +#define IS_COMP_OUTPUT_LEVEL(__OUTPUT_LEVEL__) (((__OUTPUT_LEVEL__) == COMP_OUTPUT_LEVEL_LOW) || \ + ((__OUTPUT_LEVEL__) == COMP_OUTPUT_LEVEL_HIGH)) + +/** + * @} + */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup COMP_Exported_Functions + * @{ + */ + +/** @addtogroup COMP_Exported_Functions_Group1 + * @{ + */ + +/* Initialization and de-initialization functions **********************************/ +HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp); +HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp); +void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp); +void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp); + +#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1) +/* Callbacks Register/UnRegister functions ***********************************/ +HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID, + pCOMP_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_COMP_UnRegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */ +/** + * @} + */ + +/* IO operation functions *****************************************************/ +/** @addtogroup COMP_Exported_Functions_Group2 + * @{ + */ +HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp); +HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp); +void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp); +/** + * @} + */ + +/* Peripheral Control functions ************************************************/ +/** @addtogroup COMP_Exported_Functions_Group3 + * @{ + */ +HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp); +uint32_t HAL_COMP_GetOutputLevel(const COMP_HandleTypeDef *hcomp); +/* Callback in interrupt mode */ +void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp); +/** + * @} + */ + +/* Peripheral State functions **************************************************/ +/** @addtogroup COMP_Exported_Functions_Group4 + * @{ + */ +HAL_COMP_StateTypeDef HAL_COMP_GetState(const COMP_HandleTypeDef *hcomp); +uint32_t HAL_COMP_GetError(const COMP_HandleTypeDef *hcomp); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* COMP1 || COMP2 */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WBAxx_HAL_COMP_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_conf_template.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_conf_template.h new file mode 100644 index 0000000000..4f8c0988be --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_conf_template.h @@ -0,0 +1,350 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_conf_template.h + * @author MCD Application Team + * @brief HAL configuration template file. + * This file should be copied to the application folder and renamed + * to stm32wbaxx_hal_conf.h. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_HAL_CONF_H +#define STM32WBAxx_HAL_CONF_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED +#define HAL_ADC_MODULE_ENABLED +#define HAL_COMP_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED +#define HAL_CRC_MODULE_ENABLED +#define HAL_CRYP_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_GPIO_MODULE_ENABLED +#define HAL_GTZC_MODULE_ENABLED +#define HAL_HASH_MODULE_ENABLED +#define HAL_HSEM_MODULE_ENABLED +#define HAL_I2C_MODULE_ENABLED +#define HAL_ICACHE_MODULE_ENABLED +#define HAL_IRDA_MODULE_ENABLED +#define HAL_IWDG_MODULE_ENABLED +#define HAL_LPTIM_MODULE_ENABLED +#define HAL_PKA_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_RAMCFG_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_RNG_MODULE_ENABLED +#define HAL_RTC_MODULE_ENABLED +#define HAL_SAI_MODULE_ENABLED +#define HAL_SMARTCARD_MODULE_ENABLED +#define HAL_SMBUS_MODULE_ENABLED +#define HAL_SPI_MODULE_ENABLED +#define HAL_TIM_MODULE_ENABLED +#define HAL_TSC_MODULE_ENABLED +#define HAL_UART_MODULE_ENABLED +#define HAL_USART_MODULE_ENABLED +#define HAL_WWDG_MODULE_ENABLED + +/* ########################## Oscillator Values adaptation ####################*/ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) +#define HSE_VALUE 32000000UL /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) +#define HSE_STARTUP_TIMEOUT 100UL /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) +#define HSI_VALUE 16000000UL /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) +#define LSI_VALUE 32000UL /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz. The real value may vary depending on the variations in voltage and temperature.*/ + +#if defined (RCC_LSI2_SUPPORT) +#if !defined (LSI2_VALUE) +#define LSI2_VALUE 32000UL /*!< LSI2 Typical Value in Hz*/ +#endif /* LSI2_VALUE */ +#endif + +/** + * @brief External Low Speed oscillator (LSE) value. + * This value is used by the UART, RTC HAL module to compute the system frequency + */ +#if !defined (LSE_VALUE) +#define LSE_VALUE 32768UL /*!< Value of the External oscillator in Hz*/ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) +#define LSE_STARTUP_TIMEOUT 5000UL /*!< Time out for LSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief External clock source for SAI1 peripheral + * This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source + * frequency. + */ +#if !defined (EXTERNAL_SAI1_CLOCK_VALUE) +#define EXTERNAL_SAI1_CLOCK_VALUE 48000UL /*!< Value of the SAI1 External clock source in Hz*/ +#endif /* EXTERNAL_SAI1_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE 3300UL /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((1UL<<__NVIC_PRIO_BITS) - 1UL) /*!< tick interrupt priority (lowest by default) */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 1U /*!< Enable prefetch */ + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* ################## Register callback feature configuration ############### */ +/** + * @brief Set below the peripheral configuration to "1U" to add the support + * of HAL callback registration/unregistration feature for the HAL + * driver(s). This allows user application to provide specific callback + * functions thanks to HAL_PPP_RegisterCallback() rather than overwriting + * the default weak callback functions (see each stm32wbaxx_hal_ppp.h file + * for possible callback identifiers defined in HAL_PPP_CallbackIDTypeDef + * for each PPP peripheral). + */ +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ +#define USE_HAL_COMP_REGISTER_CALLBACKS 0U /* COMP register callback disabled */ +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ +#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ +#define USE_HAL_IWDG_REGISTER_CALLBACKS 0U /* IWDG register callback disabled */ +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ +#define USE_HAL_PKA_REGISTER_CALLBACKS 0U /* PKA register callback disabled */ +#define USE_HAL_RAMCFG_REGISTER_CALLBACKS 0U /* RAMCFG register callback disabled */ +#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ +#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ +#define USE_HAL_TSC_REGISTER_CALLBACKS 0U /* TSC register callback disabled */ +#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ +#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver + * Activated: CRC code is present inside driver + * Deactivated: CRC code cleaned from driver + */ +#define USE_SPI_CRC 1U + +/* ################## CRYP peripheral configuration ########################## */ + +#define USE_HAL_CRYP_SUSPEND_RESUME 0U + +/* ################## HASH peripheral configuration ########################## */ + +#define USE_HAL_HASH_SUSPEND_RESUME 0U + + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_DMA_MODULE_ENABLED +#include "stm32wbaxx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED +#include "stm32wbaxx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_COMP_MODULE_ENABLED +#include "stm32wbaxx_hal_comp.h" +#endif /* HAL_COMP_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED +#include "stm32wbaxx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED +#include "stm32wbaxx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED +#include "stm32wbaxx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED +#include "stm32wbaxx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED +#include "stm32wbaxx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED +#include "stm32wbaxx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_GTZC_MODULE_ENABLED +#include "stm32wbaxx_hal_gtzc.h" +#endif /* HAL_GTZC_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED +#include "stm32wbaxx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_HSEM_MODULE_ENABLED +#include "stm32wbaxx_hal_hsem.h" +#endif /* HAL_HSEM_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED +#include "stm32wbaxx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_ICACHE_MODULE_ENABLED +#include "stm32wbaxx_hal_icache.h" +#endif /* HAL_ICACHE_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED +#include "stm32wbaxx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED +#include "stm32wbaxx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED +#include "stm32wbaxx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_PKA_MODULE_ENABLED +#include "stm32wbaxx_hal_pka.h" +#endif /* HAL_PKA_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED +#include "stm32wbaxx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_RAMCFG_MODULE_ENABLED +#include "stm32wbaxx_hal_ramcfg.h" +#endif /* HAL_RAMCFG_MODULE_ENABLED */ + +#ifdef HAL_RCC_MODULE_ENABLED +#include "stm32wbaxx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED +#include "stm32wbaxx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED +#include "stm32wbaxx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED +#include "stm32wbaxx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED +#include "stm32wbaxx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED +#include "stm32wbaxx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED +#include "stm32wbaxx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED +#include "stm32wbaxx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_TSC_MODULE_ENABLED +#include "stm32wbaxx_hal_tsc.h" +#endif /* HAL_TSC_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED +#include "stm32wbaxx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED +#include "stm32wbaxx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED +#include "stm32wbaxx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ +#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ +void assert_failed(uint8_t *file, uint32_t line); +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WBAxx_HAL_CONF_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_cortex.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_cortex.h new file mode 100644 index 0000000000..38b2480f14 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_cortex.h @@ -0,0 +1,380 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_cortex.h + * @author MCD Application Team + * @brief Header file of CORTEX HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32WBAxx_HAL_CORTEX_H +#define __STM32WBAxx_HAL_CORTEX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal_def.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @defgroup CORTEX CORTEX + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup CORTEX_Exported_Types CORTEX Exported Types + * @{ + */ + +/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition + * @{ + */ +typedef struct +{ + uint8_t Enable; /*!< Specifies the status of the region. + This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ + uint8_t Number; /*!< Specifies the number of the region to protect. + This parameter can be a value of @ref CORTEX_MPU_Region_Number */ + uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ + uint32_t LimitAddress; /*!< Specifies the limit address of the region to protect. */ + uint8_t AttributesIndex; /*!< Specifies the memory attributes index. + This parameter can be a value of @ref CORTEX_MPU_Attributes_Number */ + uint8_t AccessPermission; /*!< Specifies the region access permission type. + This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ + uint8_t DisableExec; /*!< Specifies the instruction access status. + This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ + uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. + This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ +} MPU_Region_InitTypeDef; +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Attributes_Initialization_Structure_definition MPU Attributes Initialization Structure Definition + * @{ + */ +typedef struct +{ + uint8_t Number; /*!< Specifies the number of the memory attributes to configure. + This parameter can be a value of @ref CORTEX_MPU_Attributes_Number */ + + uint8_t Attributes; /*!< Specifies the memory attributes vue. + This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */ + +} MPU_Attributes_InitTypeDef; +/** + * @} + */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants + * @{ + */ + +/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group + * @{ + */ +#define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bit for pre-emption priority, + 4 bits for subpriority */ +#define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bit for pre-emption priority, + 3 bits for subpriority */ +#define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority, + 2 bits for subpriority */ +#define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority, + 1 bit for subpriority */ +#define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority, + 0 bit for subpriority */ +/** + * @} + */ + +/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source + * @{ + */ +#define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source */ +#define SYSTICK_CLKSOURCE_LSI 0x00000001U /*!< LSI clock selected as SysTick clock source */ +#define SYSTICK_CLKSOURCE_LSE 0x00000002U /*!< LSE clock selected as SysTick clock source */ +#define SYSTICK_CLKSOURCE_HCLK 0x00000004U /*!< AHB clock selected as SysTick clock source */ +/** + * @} + */ + +/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control + * @{ + */ +#define MPU_HFNMI_PRIVDEF_NONE 0U +#define MPU_HARDFAULT_NMI 2U +#define MPU_PRIVILEGED_DEFAULT 4U +#define MPU_HFNMI_PRIVDEF 6U +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable + * @{ + */ +#define MPU_REGION_ENABLE 1U +#define MPU_REGION_DISABLE 0U +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access + * @{ + */ +#define MPU_INSTRUCTION_ACCESS_ENABLE 0U +#define MPU_INSTRUCTION_ACCESS_DISABLE 1U +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable + * @{ + */ +#define MPU_ACCESS_NOT_SHAREABLE 0U +#define MPU_ACCESS_OUTER_SHAREABLE 2U +#define MPU_ACCESS_INNER_SHAREABLE 3U +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes + * @{ + */ +#define MPU_REGION_PRIV_RW 0U +#define MPU_REGION_ALL_RW 1U +#define MPU_REGION_PRIV_RO 2U +#define MPU_REGION_ALL_RO 3U +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number + * @{ + */ +#define MPU_REGION_NUMBER0 0U +#define MPU_REGION_NUMBER1 1U +#define MPU_REGION_NUMBER2 2U +#define MPU_REGION_NUMBER3 3U +#define MPU_REGION_NUMBER4 4U +#define MPU_REGION_NUMBER5 5U +#define MPU_REGION_NUMBER6 6U +#define MPU_REGION_NUMBER7 7U +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Attributes_Number CORTEX MPU Memory Attributes Number + * @{ + */ +#define MPU_ATTRIBUTES_NUMBER0 0U +#define MPU_ATTRIBUTES_NUMBER1 1U +#define MPU_ATTRIBUTES_NUMBER2 2U +#define MPU_ATTRIBUTES_NUMBER3 3U +#define MPU_ATTRIBUTES_NUMBER4 4U +#define MPU_ATTRIBUTES_NUMBER5 5U +#define MPU_ATTRIBUTES_NUMBER6 6U +#define MPU_ATTRIBUTES_NUMBER7 7U +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Attributes CORTEX MPU Attributes + * @{ + */ +#define MPU_DEVICE_nGnRnE 0x0U /* Device, noGather, noReorder, noEarly acknowledge. */ +#define MPU_DEVICE_nGnRE 0x4U /* Device, noGather, noReorder, Early acknowledge. */ +#define MPU_DEVICE_nGRE 0x8U /* Device, noGather, Reorder, Early acknowledge. */ +#define MPU_DEVICE_GRE 0xCU /* Device, Gather, Reorder, Early acknowledge. */ + +#define MPU_WRITE_THROUGH 0x0U /* Normal memory, write-through. */ +#define MPU_NOT_CACHEABLE 0x4U /* Normal memory, non-cacheable. */ +#define MPU_WRITE_BACK 0x4U /* Normal memory, write-back. */ + +#define MPU_TRANSIENT 0x0U /* Normal memory, transient. */ +#define MPU_NON_TRANSIENT 0x8U /* Normal memory, non-transient. */ + +#define MPU_NO_ALLOCATE 0x0U /* Normal memory, no allocate. */ +#define MPU_W_ALLOCATE 0x1U /* Normal memory, write allocate. */ +#define MPU_R_ALLOCATE 0x2U /* Normal memory, read allocate. */ +#define MPU_RW_ALLOCATE 0x3U /* Normal memory, read/write allocate. */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros + * @{ + */ + +/** @defgroup CORTEX_MPU_Normal_Memory_Attributes CORTEX MPU Normal Memory Attributes + * @{ + */ +/* __ATTR__ being a combination of MPU Normal memory attributes */ +#define OUTER(__ATTR__) ((__ATTR__) << 4U) +#define INNER_OUTER(__ATTR__) ((__ATTR__) | ((__ATTR__) << 4U)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions + * @{ + */ + +/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * @{ + */ +/* Initialization and Configuration functions *****************************/ +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); +void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); +void HAL_NVIC_SystemReset(void); +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); +/** + * @} + */ + +/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions + * @brief Cortex control functions + * @{ + */ +/* Peripheral Control functions ***********************************************/ +uint32_t HAL_NVIC_GetPriorityGrouping(void); +void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority); +uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); +void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); +void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); +uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); +void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); +uint32_t HAL_SYSTICK_GetCLKSourceConfig(void); +void HAL_SYSTICK_IRQHandler(void); +void HAL_SYSTICK_Callback(void); + +void HAL_MPU_Enable(uint32_t MPU_Control); +void HAL_MPU_Disable(void); +void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_RegionInit); +void HAL_MPU_ConfigMemoryAttributes(MPU_Attributes_InitTypeDef *MPU_AttributesInit); +#ifdef MPU_NS +void HAL_MPU_Enable_NS(uint32_t MPU_Control); +void HAL_MPU_Disable_NS(void); +void HAL_MPU_ConfigRegion_NS(MPU_Region_InitTypeDef *MPU_RegionInit); +void HAL_MPU_ConfigMemoryAttributes_NS(MPU_Attributes_InitTypeDef *MPU_AttributesInit); +#endif /* MPU_NS */ +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup CORTEX_Private_Macros CORTEX Private Macros + * @{ + */ +#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ + ((GROUP) == NVIC_PRIORITYGROUP_1) || \ + ((GROUP) == NVIC_PRIORITYGROUP_2) || \ + ((GROUP) == NVIC_PRIORITYGROUP_3) || \ + ((GROUP) == NVIC_PRIORITYGROUP_4)) + +#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY, GROUP) (((0x07U - (GROUP)) < __NVIC_PRIO_BITS) ?\ + ((PRIORITY) < (0x1UL << (0x07U - (GROUP)))) :\ + ((PRIORITY) < (0x1UL << __NVIC_PRIO_BITS))) + +#define IS_NVIC_SUB_PRIORITY(PRIORITY, GROUP) (((GROUP) < (0x07U - __NVIC_PRIO_BITS)) ?\ + ((PRIORITY) < (0x1UL)): \ + ((PRIORITY) < (0x1UL << ((GROUP) - (0x07U - __NVIC_PRIO_BITS))))) + +#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) > SysTick_IRQn) + +#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_LSI) || \ + ((SOURCE) == SYSTICK_CLKSOURCE_LSE) || \ + ((SOURCE) == SYSTICK_CLKSOURCE_HCLK)|| \ + ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) + +#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ + ((STATE) == MPU_REGION_DISABLE)) + +#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ + ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) + +#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_OUTER_SHAREABLE) || \ + ((STATE) == MPU_ACCESS_INNER_SHAREABLE) || \ + ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) + +#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_PRIV_RW) || \ + ((TYPE) == MPU_REGION_ALL_RW) || \ + ((TYPE) == MPU_REGION_PRIV_RO) || \ + ((TYPE) == MPU_REGION_ALL_RO)) + +#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ + ((NUMBER) == MPU_REGION_NUMBER1) || \ + ((NUMBER) == MPU_REGION_NUMBER2) || \ + ((NUMBER) == MPU_REGION_NUMBER3) || \ + ((NUMBER) == MPU_REGION_NUMBER4) || \ + ((NUMBER) == MPU_REGION_NUMBER5) || \ + ((NUMBER) == MPU_REGION_NUMBER6) || \ + ((NUMBER) == MPU_REGION_NUMBER7)) + +#define IS_MPU_ATTRIBUTES_NUMBER(NUMBER) (((NUMBER) == MPU_ATTRIBUTES_NUMBER0) || \ + ((NUMBER) == MPU_ATTRIBUTES_NUMBER1) || \ + ((NUMBER) == MPU_ATTRIBUTES_NUMBER2) || \ + ((NUMBER) == MPU_ATTRIBUTES_NUMBER3) || \ + ((NUMBER) == MPU_ATTRIBUTES_NUMBER4) || \ + ((NUMBER) == MPU_ATTRIBUTES_NUMBER5) || \ + ((NUMBER) == MPU_ATTRIBUTES_NUMBER6) || \ + ((NUMBER) == MPU_ATTRIBUTES_NUMBER7)) + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32WBAxx_HAL_CORTEX_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_crc.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_crc.h new file mode 100644 index 0000000000..e0c8fe98c0 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_crc.h @@ -0,0 +1,342 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_crc.h + * @author MCD Application Team + * @brief Header file of CRC HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_HAL_CRC_H +#define STM32WBAxx_HAL_CRC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal_def.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @addtogroup CRC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup CRC_Exported_Types CRC Exported Types + * @{ + */ + +/** + * @brief CRC HAL State Structure definition + */ +typedef enum +{ + HAL_CRC_STATE_RESET = 0x00U, /*!< CRC not yet initialized or disabled */ + HAL_CRC_STATE_READY = 0x01U, /*!< CRC initialized and ready for use */ + HAL_CRC_STATE_BUSY = 0x02U, /*!< CRC internal process is ongoing */ + HAL_CRC_STATE_TIMEOUT = 0x03U, /*!< CRC timeout state */ + HAL_CRC_STATE_ERROR = 0x04U /*!< CRC error state */ +} HAL_CRC_StateTypeDef; + +/** + * @brief CRC Init Structure definition + */ +typedef struct +{ + uint8_t DefaultPolynomialUse; /*!< This parameter is a value of @ref CRC_Default_Polynomial and indicates if default polynomial is used. + If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default + X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + + X^4 + X^2+ X +1. + In that case, there is no need to set GeneratingPolynomial field. + If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and + CRCLength fields must be set. */ + + uint8_t DefaultInitValueUse; /*!< This parameter is a value of @ref CRC_Default_InitValue_Use and indicates if default init value is used. + If set to DEFAULT_INIT_VALUE_ENABLE, resort to default + 0xFFFFFFFF value. In that case, there is no need to set InitValue field. If + otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set. */ + + uint32_t GeneratingPolynomial; /*!< Set CRC generating polynomial as a 7, 8, 16 or 32-bit long value for a polynomial degree + respectively equal to 7, 8, 16 or 32. This field is written in normal, + representation e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 + is written 0x65. No need to specify it if DefaultPolynomialUse is set to + DEFAULT_POLYNOMIAL_ENABLE. */ + + uint32_t CRCLength; /*!< This parameter is a value of @ref CRC_Polynomial_Sizes and indicates CRC length. + Value can be either one of + @arg @ref CRC_POLYLENGTH_32B (32-bit CRC), + @arg @ref CRC_POLYLENGTH_16B (16-bit CRC), + @arg @ref CRC_POLYLENGTH_8B (8-bit CRC), + @arg @ref CRC_POLYLENGTH_7B (7-bit CRC). */ + + uint32_t InitValue; /*!< Init value to initiate CRC computation. No need to specify it if DefaultInitValueUse + is set to DEFAULT_INIT_VALUE_ENABLE. */ + + uint32_t InputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Input_Data_Inversion and specifies input data inversion mode. + Can be either one of the following values + @arg @ref CRC_INPUTDATA_INVERSION_NONE no input data inversion + @arg @ref CRC_INPUTDATA_INVERSION_BYTE byte-wise inversion, 0x1A2B3C4D + becomes 0x58D43CB2 + @arg @ref CRC_INPUTDATA_INVERSION_HALFWORD halfword-wise inversion, + 0x1A2B3C4D becomes 0xD458B23C + @arg @ref CRC_INPUTDATA_INVERSION_WORD word-wise inversion, 0x1A2B3C4D + becomes 0xB23CD458 */ + + uint32_t OutputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode. + Can be either + @arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion, + @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE CRC 0x11223344 is converted + into 0x22CC4488 */ +} CRC_InitTypeDef; + +/** + * @brief CRC Handle Structure definition + */ +typedef struct +{ + CRC_TypeDef *Instance; /*!< Register base address */ + + CRC_InitTypeDef Init; /*!< CRC configuration parameters */ + + HAL_LockTypeDef Lock; /*!< CRC Locking object */ + + __IO HAL_CRC_StateTypeDef State; /*!< CRC communication state */ + + uint32_t InputDataFormat; /*!< This parameter is a value of @ref CRC_Input_Buffer_Format and specifies input data format. + Can be either + @arg @ref CRC_INPUTDATA_FORMAT_BYTES input data is a stream of bytes + (8-bit data) + @arg @ref CRC_INPUTDATA_FORMAT_HALFWORDS input data is a stream of + half-words (16-bit data) + @arg @ref CRC_INPUTDATA_FORMAT_WORDS input data is a stream of words + (32-bit data) + + Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization + error must occur if InputBufferFormat is not one of the three values listed + above */ +} CRC_HandleTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CRC_Exported_Constants CRC Exported Constants + * @{ + */ + +/** @defgroup CRC_Default_Polynomial_Value Default CRC generating polynomial + * @{ + */ +#define DEFAULT_CRC32_POLY 0x04C11DB7U /*!< X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1 */ +/** + * @} + */ + +/** @defgroup CRC_Default_InitValue Default CRC computation initialization value + * @{ + */ +#define DEFAULT_CRC_INITVALUE 0xFFFFFFFFU /*!< Initial CRC default value */ +/** + * @} + */ + +/** @defgroup CRC_Default_Polynomial Indicates whether or not default polynomial is used + * @{ + */ +#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00U) /*!< Enable default generating polynomial 0x04C11DB7 */ +#define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01U) /*!< Disable default generating polynomial 0x04C11DB7 */ +/** + * @} + */ + +/** @defgroup CRC_Default_InitValue_Use Indicates whether or not default init value is used + * @{ + */ +#define DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00U) /*!< Enable initial CRC default value */ +#define DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01U) /*!< Disable initial CRC default value */ +/** + * @} + */ + +/** @defgroup CRC_Polynomial_Sizes Polynomial sizes to configure the peripheral + * @{ + */ +#define CRC_POLYLENGTH_32B 0x00000000U /*!< Resort to a 32-bit long generating polynomial */ +#define CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0 /*!< Resort to a 16-bit long generating polynomial */ +#define CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1 /*!< Resort to a 8-bit long generating polynomial */ +#define CRC_POLYLENGTH_7B CRC_CR_POLYSIZE /*!< Resort to a 7-bit long generating polynomial */ +/** + * @} + */ + +/** @defgroup CRC_Polynomial_Size_Definitions CRC polynomial possible sizes actual definitions + * @{ + */ +#define HAL_CRC_LENGTH_32B 32U /*!< 32-bit long CRC */ +#define HAL_CRC_LENGTH_16B 16U /*!< 16-bit long CRC */ +#define HAL_CRC_LENGTH_8B 8U /*!< 8-bit long CRC */ +#define HAL_CRC_LENGTH_7B 7U /*!< 7-bit long CRC */ +/** + * @} + */ + +/** @defgroup CRC_Input_Buffer_Format Input Buffer Format + * @{ + */ +/* WARNING: CRC_INPUT_FORMAT_UNDEFINED is created for reference purposes but + * an error is triggered in HAL_CRC_Init() if InputDataFormat field is set + * to CRC_INPUT_FORMAT_UNDEFINED: the format MUST be defined by the user for + * the CRC APIs to provide a correct result */ +#define CRC_INPUTDATA_FORMAT_UNDEFINED 0x00000000U /*!< Undefined input data format */ +#define CRC_INPUTDATA_FORMAT_BYTES 0x00000001U /*!< Input data in byte format */ +#define CRC_INPUTDATA_FORMAT_HALFWORDS 0x00000002U /*!< Input data in half-word format */ +#define CRC_INPUTDATA_FORMAT_WORDS 0x00000003U /*!< Input data in word format */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup CRC_Exported_Macros CRC Exported Macros + * @{ + */ + +/** @brief Reset CRC handle state. + * @param __HANDLE__ CRC handle. + * @retval None + */ +#define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET) + +/** + * @brief Reset CRC Data Register. + * @param __HANDLE__ CRC handle + * @retval None + */ +#define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET) + +/** + * @brief Set CRC INIT non-default value + * @param __HANDLE__ CRC handle + * @param __INIT__ 32-bit initial value + * @retval None + */ +#define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__)) + +/** + * @brief Store data in the Independent Data (ID) register. + * @param __HANDLE__ CRC handle + * @param __VALUE__ Value to be stored in the ID register + * @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits + * @retval None + */ +#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__))) + +/** + * @brief Return the data stored in the Independent Data (ID) register. + * @param __HANDLE__ CRC handle + * @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits + * @retval Value of the ID register + */ +#define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR) +/** + * @} + */ + + +/* Private macros --------------------------------------------------------*/ +/** @defgroup CRC_Private_Macros CRC Private Macros + * @{ + */ + +#define IS_DEFAULT_POLYNOMIAL(DEFAULT) (((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE) || \ + ((DEFAULT) == DEFAULT_POLYNOMIAL_DISABLE)) + +#define IS_DEFAULT_INIT_VALUE(VALUE) (((VALUE) == DEFAULT_INIT_VALUE_ENABLE) || \ + ((VALUE) == DEFAULT_INIT_VALUE_DISABLE)) + +#define IS_CRC_POL_LENGTH(LENGTH) (((LENGTH) == CRC_POLYLENGTH_32B) || \ + ((LENGTH) == CRC_POLYLENGTH_16B) || \ + ((LENGTH) == CRC_POLYLENGTH_8B) || \ + ((LENGTH) == CRC_POLYLENGTH_7B)) + +#define IS_CRC_INPUTDATA_FORMAT(FORMAT) (((FORMAT) == CRC_INPUTDATA_FORMAT_BYTES) || \ + ((FORMAT) == CRC_INPUTDATA_FORMAT_HALFWORDS) || \ + ((FORMAT) == CRC_INPUTDATA_FORMAT_WORDS)) + +/** + * @} + */ + +/* Include CRC HAL Extended module */ +#include "stm32wbaxx_hal_crc_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup CRC_Exported_Functions CRC Exported Functions + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ +/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc); +HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc); +void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc); +void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc); +/** + * @} + */ + +/* Peripheral Control functions ***********************************************/ +/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions + * @{ + */ +uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength); +uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength); +/** + * @} + */ + +/* Peripheral State and Error functions ***************************************/ +/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions + * @{ + */ +HAL_CRC_StateTypeDef HAL_CRC_GetState(const CRC_HandleTypeDef *hcrc); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WBAxx_HAL_CRC_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_crc_ex.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_crc_ex.h new file mode 100644 index 0000000000..ca0c11564b --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_crc_ex.h @@ -0,0 +1,150 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_crc_ex.h + * @author MCD Application Team + * @brief Header file of CRC HAL extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_HAL_CRC_EX_H +#define STM32WBAxx_HAL_CRC_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal_def.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @addtogroup CRCEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CRCEx_Exported_Constants CRC Extended Exported Constants + * @{ + */ + +/** @defgroup CRCEx_Input_Data_Inversion Input Data Inversion Modes + * @{ + */ +#define CRC_INPUTDATA_INVERSION_NONE 0x00000000U /*!< No input data inversion */ +#define CRC_INPUTDATA_INVERSION_BYTE CRC_CR_REV_IN_0 /*!< Byte-wise input data inversion */ +#define CRC_INPUTDATA_INVERSION_HALFWORD CRC_CR_REV_IN_1 /*!< HalfWord-wise input data inversion */ +#define CRC_INPUTDATA_INVERSION_WORD CRC_CR_REV_IN /*!< Word-wise input data inversion */ +/** + * @} + */ + +/** @defgroup CRCEx_Output_Data_Inversion Output Data Inversion Modes + * @{ + */ +#define CRC_OUTPUTDATA_INVERSION_DISABLE 0x00000000U /*!< No output data inversion */ +#define CRC_OUTPUTDATA_INVERSION_ENABLE CRC_CR_REV_OUT /*!< Bit-wise output data inversion */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup CRCEx_Exported_Macros CRC Extended Exported Macros + * @{ + */ + +/** + * @brief Set CRC output reversal + * @param __HANDLE__ CRC handle + * @retval None + */ +#define __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT) + +/** + * @brief Unset CRC output reversal + * @param __HANDLE__ CRC handle + * @retval None + */ +#define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT)) + +/** + * @brief Set CRC non-default polynomial + * @param __HANDLE__ CRC handle + * @param __POLYNOMIAL__ 7, 8, 16 or 32-bit polynomial + * @retval None + */ +#define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__)) + +/** + * @} + */ + +/* Private macros --------------------------------------------------------*/ +/** @defgroup CRCEx_Private_Macros CRC Extended Private Macros + * @{ + */ + +#define IS_CRC_INPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_INPUTDATA_INVERSION_NONE) || \ + ((MODE) == CRC_INPUTDATA_INVERSION_BYTE) || \ + ((MODE) == CRC_INPUTDATA_INVERSION_HALFWORD) || \ + ((MODE) == CRC_INPUTDATA_INVERSION_WORD)) + +#define IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \ + ((MODE) == CRC_OUTPUTDATA_INVERSION_ENABLE)) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup CRCEx_Exported_Functions + * @{ + */ + +/** @addtogroup CRCEx_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions ****************************/ +HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength); +HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode); +HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WBAxx_HAL_CRC_EX_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_cryp.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_cryp.h new file mode 100644 index 0000000000..b862c06d5c --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_cryp.h @@ -0,0 +1,724 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_cryp.h + * @author MCD Application Team + * @brief Header file of CRYP HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_HAL_CRYP_H +#define STM32WBAxx_HAL_CRYP_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal_def.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +#if defined(AES) + +/** @defgroup CRYP CRYP + * @brief CRYP HAL module driver. + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup CRYP_Exported_Types CRYP Exported Types + * @{ + */ + +/** + * @brief CRYP Init Structure definition + */ + +typedef struct +{ + uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string. + This parameter can be a value of @ref CRYP_Data_Type */ + uint32_t KeySize; /*!< Used only in AES mode : 128, 192 or 256 bit key length in CRYP1. + 128 or 256 bit key length in TinyAES This parameter can be a value + of @ref CRYP_Key_Size */ + uint32_t *pKey; /*!< The key used for encryption/decryption */ + uint32_t *pInitVect; /*!< The initialization vector used also as initialization + counter in CTR mode */ + uint32_t Algorithm; /*!< DES/ TDES Algorithm ECB/CBC + AES Algorithm ECB/CBC/CTR/GCM or CCM + This parameter can be a value of @ref CRYP_Algorithm_Mode */ + uint32_t *Header; /*!< used only in AES GCM and CCM Algorithm for authentication, + GCM : also known as Additional Authentication Data + CCM : named B1 composed of the associated data length and Associated Data. */ + uint32_t HeaderSize; /*!< The size of header buffer */ + uint32_t *B0; /*!< B0 is first authentication block used only in AES CCM mode */ + uint32_t DataWidthUnit; /*!< Payload Data Width Unit, this parameter can be value of @ref CRYP_Data_Width_Unit */ + uint32_t HeaderWidthUnit; /*!< Header Width Unit, this parameter can be value of @ref CRYP_Header_Width_Unit */ + uint32_t KeyIVConfigSkip; /*!< CRYP peripheral Key and IV configuration skip, to config Key and Initialization + Vector only once and to skip configuration for consecutive processings. + This parameter can be a value of @ref CRYP_Configuration_Skip */ + uint32_t KeyMode; /*!< Key mode selection, this parameter can be value of @ref CRYP_Key_Mode */ + uint32_t KeySelect; /*!< Only for SAES : Key selection, this parameter can be value of @ref CRYP_Key_Select */ + uint32_t KeyProtection; /*!< Only for SAES : Key protection, this parameter can be value of @ref CRYP_Key_Protection */ + +} CRYP_ConfigTypeDef; + +/** + * @brief CRYP State Structure definition + */ + +typedef enum +{ + HAL_CRYP_STATE_RESET = 0x00U, /*!< CRYP not yet initialized or disabled */ + HAL_CRYP_STATE_READY = 0x01U, /*!< CRYP initialized and ready for use */ + HAL_CRYP_STATE_BUSY = 0x02U, /*!< CRYP BUSY, internal processing is ongoing */ +#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) + HAL_CRYP_STATE_SUSPENDED = 0x03U, /*!< CRYP suspended */ +#endif /* USE_HAL_CRYP_SUSPEND_RESUME */ +} HAL_CRYP_STATETypeDef; + +/** + * @brief CRYP Context Structure definition + */ + +typedef struct +{ + uint32_t DataType; /*!< This parameter can be a value of @ref CRYP_Data_Type */ + uint32_t KeySize; /*!< This parameter can be a value of @ref CRYP_Key_Size */ + uint32_t *pKey; /*!< The key used for encryption/decryption */ + uint32_t *pInitVect; /*!< The initialization vector, counter with CBC and CTR Algorithm */ + uint32_t Algorithm; /*!< This parameter can be a value of @ref CRYP_Algorithm_Mode */ + uint32_t DataWidthUnit; /*!< This parameter can be value of @ref CRYP_Data_Width_Unit */ + uint32_t KeyIVConfigSkip; /*!< This parameter can be a value of @ref CRYP_Configuration_Skip */ + uint32_t KeyMode; /*!< This parameter can be value of @ref CRYP_Key_Mode */ + uint32_t Phase; /*!< CRYP peripheral phase */ + uint32_t KeyIVConfig; /*!< CRYP peripheral Key and IV configuration flag */ + uint32_t CR_Reg; /*!< CRYP CR register */ + uint32_t IER_Reg; /*!< CRYP IER register */ + uint32_t IVR0_Reg; /*!< CRYP IVR0 register */ + uint32_t IVR1_Reg; /*!< CRYP IVR1 register */ + uint32_t IVR2_Reg; /*!< CRYP IVR2 register */ + uint32_t IVR3_Reg; /*!< CRYP IVR3 register */ + +} CRYP_ContextTypeDef; + +#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) +/** + * @brief HAL CRYP mode suspend definitions + */ +typedef enum +{ + HAL_CRYP_SUSPEND_NONE = 0x00U, /*!< CRYP processing suspension not requested */ + HAL_CRYP_SUSPEND = 0x01U /*!< CRYP processing suspension requested */ +} HAL_SuspendTypeDef; +#endif /* USE_HAL_CRYP_SUSPEND_RESUME */ + +/** + * @brief CRYP handle Structure definition + */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) +typedef struct __CRYP_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ +{ + AES_TypeDef *Instance; /*!< AES Register base address */ + + CRYP_ConfigTypeDef Init; /*!< CRYP required parameters */ + uint32_t *pCrypInBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */ + + uint32_t *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */ + + __IO uint16_t CrypHeaderCount; /*!< Counter of header data in words */ + + __IO uint16_t CrypInCount; /*!< Counter of input data in words */ + + __IO uint16_t CrypOutCount; /*!< Counter of output data in words */ + + uint16_t Size; /*!< length of input data in word or in byte, according to DataWidthUnit */ + + uint32_t Phase; /*!< CRYP peripheral phase */ + + DMA_HandleTypeDef *hdmain; /*!< CRYP In DMA handle parameters */ + + DMA_HandleTypeDef *hdmaout; /*!< CRYP Out DMA handle parameters */ + + HAL_LockTypeDef Lock; /*!< CRYP locking object */ + + __IO HAL_CRYP_STATETypeDef State; /*!< CRYP peripheral state */ + + __IO uint32_t ErrorCode; /*!< CRYP peripheral error code */ + + uint32_t KeyIVConfig; /*!< CRYP peripheral Key and IV configuration flag, used when + configuration can be skipped */ + + uint32_t SizesSum; /*!< Sum of successive payloads lengths (in bytes), stored + for a single signature computation after several + messages processing */ + +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + void (*InCpltCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Input FIFO transfer completed callback */ + void (*OutCpltCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Output FIFO transfer completed callback */ + void (*ErrorCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Error callback */ + + void (* MspInitCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Msp Init callback */ + void (* MspDeInitCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Msp DeInit callback */ + +#endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */ + +#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) + + __IO HAL_SuspendTypeDef SuspendRequest; /*!< CRYP peripheral suspension request flag */ + + CRYP_ConfigTypeDef Init_saved; /*!< copy of CRYP required parameters when processing is suspended */ + + uint32_t *pCrypInBuffPtr_saved; /*!< copy of CRYP input pointer when processing is suspended */ + + uint32_t *pCrypOutBuffPtr_saved; /*!< copy of CRYP output pointer when processing is suspended */ + + uint32_t CrypInCount_saved; /*!< copy of CRYP input data counter when processing is suspended */ + + uint32_t CrypOutCount_saved; /*!< copy of CRYP output data counter when processing is suspended */ + + uint32_t Phase_saved; /*!< copy of CRYP authentication phase when processing is suspended */ + + __IO HAL_CRYP_STATETypeDef State_saved; /*!< copy of CRYP peripheral state when processing is suspended */ + + uint32_t IV_saved[4]; /*!< copy of Initialisation Vector registers */ + + uint32_t SUSPxR_saved[8]; /*!< copy of suspension registers */ + + uint32_t CR_saved; /*!< copy of CRYP control register when processing is suspended*/ + + uint32_t Key_saved[8]; /*!< copy of key registers */ + + uint16_t Size_saved; /*!< copy of input buffer size */ + + uint16_t CrypHeaderCount_saved; /*!< copy of CRYP header data counter when processing is suspended */ + + uint32_t SizesSum_saved; /*!< copy of SizesSum when processing is suspended */ + + uint32_t ResumingFlag; /*!< resumption flag to bypass steps already carried out */ +#endif /* USE_HAL_CRYP_SUSPEND_RESUME */ + +} CRYP_HandleTypeDef; + +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + +/** + * @brief HAL CRYP Callback ID enumeration definition + */ +typedef enum +{ + HAL_CRYP_MSPINIT_CB_ID = 0x00U, /*!< CRYP MspInit callback ID */ + HAL_CRYP_MSPDEINIT_CB_ID = 0x01U, /*!< CRYP MspDeInit callback ID */ + HAL_CRYP_INPUT_COMPLETE_CB_ID = 0x02U, /*!< CRYP Input FIFO transfer completed callback ID */ + HAL_CRYP_OUTPUT_COMPLETE_CB_ID = 0x03U, /*!< CRYP Output FIFO transfer completed callback ID */ + HAL_CRYP_ERROR_CB_ID = 0x04U, /*!< CRYP Error callback ID */ +} HAL_CRYP_CallbackIDTypeDef; + +/** + * @brief HAL CRYP Callback pointer definition + */ +typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< pointer to a common CRYP callback function */ + +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CRYP_Exported_Constants CRYP Exported Constants + * @{ + */ + +/** @defgroup CRYP_Error_Definition CRYP Error Definition + * @{ + */ +#define HAL_CRYP_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_CRYP_ERROR_WRITE 0x00000001U /*!< Write error */ +#define HAL_CRYP_ERROR_READ 0x00000002U /*!< Read error */ +#define HAL_CRYP_ERROR_DMA 0x00000004U /*!< DMA error */ +#define HAL_CRYP_ERROR_BUSY 0x00000008U /*!< Busy flag error */ +#define HAL_CRYP_ERROR_TIMEOUT 0x00000010U /*!< Timeout error */ +#define HAL_CRYP_ERROR_NOT_SUPPORTED 0x00000020U /*!< Not supported mode */ +#define HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE 0x00000040U /*!< Sequence are not respected only for GCM or CCM */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) +#define HAL_CRYP_ERROR_INVALID_CALLBACK ((uint32_t)0x00000080U) /*!< Invalid Callback error */ +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ +#define HAL_CRYP_ERROR_KEY 0x00000100U /*!< Key error */ +#define HAL_CRYP_ERROR_RNG 0x00000200U /*!< Rng error */ +/** + * @} + */ + +/** @defgroup CRYP_Data_Width_Unit CRYP Data Width Unit + * @{ + */ + +#define CRYP_DATAWIDTHUNIT_WORD 0x00000000U /*!< By default, size unit is word */ +#define CRYP_DATAWIDTHUNIT_BYTE 0x00000001U /*!< By default, size unit is byte */ + +/** + * @} + */ + +/** @defgroup CRYP_Header_Width_Unit CRYP Header Width Unit + * @{ + */ + +#define CRYP_HEADERWIDTHUNIT_WORD 0x00000000U /*!< By default, header size unit is word */ +#define CRYP_HEADERWIDTHUNIT_BYTE 0x00000001U /*!< By default, header size unit is byte */ + +/** + * @} + */ + +/** @defgroup CRYP_Algorithm_Mode CRYP Algorithm Mode + * @{ + */ + +#define CRYP_AES_ECB 0x00000000U /*!< Electronic codebook chaining algorithm */ +#define CRYP_AES_CBC AES_CR_CHMOD_0 /*!< Cipher block chaining algorithm */ +#define CRYP_AES_CTR AES_CR_CHMOD_1 /*!< Counter mode chaining algorithm */ +#define CRYP_AES_GCM_GMAC (AES_CR_CHMOD_0 | AES_CR_CHMOD_1) /*!< Galois counter mode - Galois message authentication code */ +#define CRYP_AES_CCM AES_CR_CHMOD_2 /*!< Counter with Cipher Mode */ + +/** + * @} + */ + +/** @defgroup CRYP_Key_Size CRYP Key Size + * @{ + */ + +#define CRYP_KEYSIZE_128B 0x00000000U /*!< 128-bit long key */ +#define CRYP_KEYSIZE_256B AES_CR_KEYSIZE /*!< 256-bit long key */ + +/** + * @} + */ + +/** @defgroup CRYP_Key_Mode CRYP Key Mode + * @{ + */ + +#define CRYP_KEYMODE_NORMAL 0x00000000U /*!< Normal key usage, Key registers are freely usable */ +#define CRYP_KEYMODE_SHARED AES_CR_KMOD_1 /*!< Shared key */ +#define CRYP_KEYMODE_WRAPPED AES_CR_KMOD_0 /*!< Only for SAES, Wrapped key: to encrypt or decrypt AES keys */ + +/** + * @} + */ + +/** @defgroup CRYP_Key_Select CRYP Key Select + * @{ + */ + +#define CRYP_KEYSEL_NORMAL 0x00000000U /*!< Normal key, key registers SAES_KEYx or CRYP_KEYx */ +#define CRYP_KEYSEL_HW AES_CR_KEYSEL_0 /*!< Only for SAES, Hardware key : derived hardware unique key (DHUK 256-bit) */ +#define CRYP_KEYSEL_SW AES_CR_KEYSEL_1 /*!< Only for SAES, Software key : boot hardware key BHK (256-bit) */ +#define CRYP_KEYSEL_HSW AES_CR_KEYSEL_2 /*!< Only for SAES, DHUK XOR BHK Hardware unique key XOR software key */ + +/** + * @} + */ + +/** @defgroup CRYP_Key_ShareID CRYP Key Share ID + * @{ + */ + +#define CRYP_KSHAREID_AES 0x00000000U /*!< Share SAES Key with AES peripheral */ + +/** + * @} + */ + +/** @defgroup CRYP_Key_Protection CRYP Key Protection + * @{ + */ + +#define CRYP_KEYPROT_ENABLE AES_CR_KEYPROT /*!< Only for SAES, Key protection between 2 applications with different security contexts */ +#define CRYP_KEYPROT_DISABLE 0x00000000U /*!< Only for SAES, Key not protected between 2 applications with different security contexts */ +/** + * @} + */ + + +/** @defgroup CRYP_Data_Type CRYP Data Type + * @{ + */ + +#define CRYP_DATATYPE_32B 0x00000000U +#define CRYP_DATATYPE_16B AES_CR_DATATYPE_0 +#define CRYP_DATATYPE_8B AES_CR_DATATYPE_1 +#define CRYP_DATATYPE_1B AES_CR_DATATYPE + +#define CRYP_NO_SWAP CRYP_DATATYPE_32B /*!< 32-bit data type (no swapping) */ +#define CRYP_HALFWORD_SWAP CRYP_DATATYPE_16B /*!< 16-bit data type (half-word swapping) */ +#define CRYP_BYTE_SWAP CRYP_DATATYPE_8B /*!< 8-bit data type (byte swapping) */ +#define CRYP_BIT_SWAP CRYP_DATATYPE_1B /*!< 1-bit data type (bit swapping) */ + +/** + * @} + */ + +/** @defgroup CRYP_Interrupt CRYP Interrupt + * @{ + */ +#define CRYP_IT_CCFIE AES_IER_CCFIE /*!< Computation Complete interrupt enable */ +#define CRYP_IT_RWEIE AES_IER_RWEIE /*!< Read or write Error interrupt enable */ +#define CRYP_IT_KEIE AES_IER_KEIE /*!< Key error interrupt enable */ +#define CRYP_IT_RNGEIE AES_IER_RNGEIE /*!< Rng error interrupt enable */ + +/** + * @} + */ + +/** @defgroup CRYP_Flags CRYP Flags + * @{ + */ + +#define CRYP_FLAG_BUSY AES_SR_BUSY /*!< GCM process suspension forbidden also set when + transferring a shared key from SAES peripheral */ +#define CRYP_FLAG_WRERR (AES_SR_WRERR | 0x80000000U) /*!< Write Error flag */ +#define CRYP_FLAG_RDERR (AES_SR_RDERR | 0x80000000U) /*!< Read error flag */ +#define CRYP_FLAG_CCF AES_ISR_CCF /*!< Computation completed flag as AES_ISR_CCF */ +#define CRYP_FLAG_KEYVALID AES_SR_KEYVALID /*!< Key Valid flag */ +#define CRYP_FLAG_KEIF AES_ISR_KEIF /*!State = HAL_CRYP_STATE_RESET;\ + (__HANDLE__)->MspInitCallback = NULL;\ + (__HANDLE__)->MspDeInitCallback = NULL;\ + }while(0U) +#else +#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ( (__HANDLE__)->State = HAL_CRYP_STATE_RESET) +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + +/** + * @brief Enable/Disable the CRYP peripheral. + * @param __HANDLE__ specifies the CRYP handle. + * @retval None + */ + +#define __HAL_CRYP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= AES_CR_EN) +#define __HAL_CRYP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~AES_CR_EN) + + +/** @brief Check whether the specified CRYP status flag is set or not. + * @param __HANDLE__ specifies the CRYP handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values for TinyAES: + * @arg @ref CRYP_FLAG_KEYVALID Key valid flag + * @arg @ref CRYP_FLAG_BUSY GCM process suspension forbidden or + * transferring a shared key from SAES IP. + * @arg @ref CRYP_FLAG_WRERR Write Error flag + * @arg @ref CRYP_FLAG_RDERR Read Error flag + * @arg @ref CRYP_FLAG_CCF Computation Complete flag + * @arg @ref CRYP_FLAG_KEIF Key error flag + * @arg @ref CRYP_FLAG_RWEIF Read/write Error flag + + * @retval The state of __FLAG__ (TRUE or FALSE). + */ + +#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) (\ + ((__FLAG__) == CRYP_FLAG_KEYVALID )?(((__HANDLE__)->Instance->SR \ + & (CRYP_FLAG_KEYVALID)) == (CRYP_FLAG_KEYVALID)) : \ + ((__FLAG__) == CRYP_FLAG_BUSY )?(((__HANDLE__)->Instance->SR \ + & (CRYP_FLAG_BUSY)) == (CRYP_FLAG_BUSY)) : \ + ((__FLAG__) == CRYP_FLAG_WRERR )?(((__HANDLE__)->Instance->SR \ + & (CRYP_FLAG_WRERR & 0x7FFFFFFFU)) == \ + (CRYP_FLAG_WRERR & 0x7FFFFFFFU)) : \ + ((__FLAG__) == CRYP_FLAG_RDERR )?(((__HANDLE__)->Instance->SR \ + & (CRYP_FLAG_RDERR & 0x7FFFFFFFU)) == \ + (CRYP_FLAG_RDERR & 0x7FFFFFFFU)) : \ + ((__FLAG__) == CRYP_FLAG_KEIF )?(((__HANDLE__)->Instance->ISR \ + & (CRYP_FLAG_KEIF)) == (CRYP_FLAG_KEIF)) : \ + ((__FLAG__) == CRYP_FLAG_RWEIF )?(((__HANDLE__)->Instance->ISR \ + & (CRYP_FLAG_RWEIF)) == (CRYP_FLAG_RWEIF)) : \ + (((__HANDLE__)->Instance->ISR & (CRYP_FLAG_CCF)) == (CRYP_FLAG_CCF))) + +/** @brief Clear the CRYP pending status flag. + * @param __HANDLE__ specifies the CRYP handle. + * @param __FLAG__ specifies the flag to clear. + * This parameter can be one of the following values: + * @arg @ref CRYP_CLEAR_RWEIF Read (RDERR), Write (WRERR) or Read/write (RWEIF) Error Flag Clear + * @arg @ref CRYP_CLEAR_CCF Computation Complete Flag (CCF) Clear + * @arg @ref CRYP_CLEAR_KEIF Key error interrupt flag clear + * @retval None + */ + +#define __HAL_CRYP_CLEAR_FLAG(__HANDLE__, __FLAG__) SET_BIT((__HANDLE__)->Instance->ICR, (__FLAG__)) + + +/** @brief Check whether the specified CRYP interrupt source is enabled or not. + * @param __HANDLE__ specifies the CRYP handle. + * @param __INTERRUPT__ CRYP interrupt source to check + * This parameter can be one of the following values for TinyAES: + * @arg @ref CRYP_IT_RWEIE Error interrupt (used for RDERR and WRERR) + * @arg @ref CRYP_IT_CCFIE Computation Complete interrupt + * @arg @ref CRYP_IT_KEIE Key error interrupt + * @retval State of interruption (TRUE or FALSE). + */ + +#define __HAL_CRYP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER\ + & (__INTERRUPT__)) == (__INTERRUPT__)) + +/** + * @brief Enable the CRYP interrupt. + * @param __HANDLE__ specifies the CRYP handle. + * @param __INTERRUPT__ CRYP Interrupt. + * This parameter can be one of the following values for TinyAES: + * @arg @ref CRYP_IT_RWEIE Error interrupt (used for RDERR and WRERR) + * @arg @ref CRYP_IT_CCFIE Computation Complete interrupt + * @arg @ref CRYP_IT_KEIE Key error interrupt + * @retval None + */ + +#define __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) + +/** + * @brief Disable the CRYP interrupt. + * @param __HANDLE__ specifies the CRYP handle. + * @param __INTERRUPT__ CRYP Interrupt. + * This parameter can be one of the following values for TinyAES: + * @arg @ref CRYP_IT_RWEIE Error interrupt (used for RDERR and WRERR) + * @arg @ref CRYP_IT_CCFIE Computation Complete interrupt + * @arg @ref CRYP_IT_KEIE Key error interrupt + * @retval None + */ + +#define __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) + +/** + * @} + */ + +/* Include CRYP HAL Extended module */ +#include "stm32wbaxx_hal_cryp_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup CRYP_Exported_Functions CRYP Exported Functions + * @{ + */ + +/** @addtogroup CRYP_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp); +HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp); +void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp); +void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp); +HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf); +HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf); +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) +HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, + pCRYP_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ +#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) +void HAL_CRYP_ProcessSuspend(CRYP_HandleTypeDef *hcryp); +HAL_StatusTypeDef HAL_CRYP_Suspend(CRYP_HandleTypeDef *hcryp); +HAL_StatusTypeDef HAL_CRYP_Resume(CRYP_HandleTypeDef *hcryp); +#endif /* defined (USE_HAL_CRYP_SUSPEND_RESUME) */ +HAL_StatusTypeDef HAL_CRYP_SaveContext(CRYP_HandleTypeDef *hcryp, CRYP_ContextTypeDef *pcont); +HAL_StatusTypeDef HAL_CRYP_RestoreContext(CRYP_HandleTypeDef *hcryp, CRYP_ContextTypeDef *pcont); + +/** + * @} + */ + +/** @addtogroup CRYP_Exported_Functions_Group2 + * @{ + */ + +/* encryption/decryption ***********************************/ +HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *pInput, uint16_t Size, uint32_t *pOutput, + uint32_t Timeout); +HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *pInput, uint16_t Size, uint32_t *pOutput, + uint32_t Timeout); +HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *pInput, uint16_t Size, uint32_t *pOutput); +HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *pInput, uint16_t Size, uint32_t *pOutput); +HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *pInput, uint16_t Size, uint32_t *pOutput); +HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *pInput, uint16_t Size, uint32_t *pOutput); + +/** + * @} + */ + + +/** @addtogroup CRYP_Exported_Functions_Group3 + * @{ + */ +/* Interrupt Handler functions **********************************************/ +void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp); +HAL_CRYP_STATETypeDef HAL_CRYP_GetState(const CRYP_HandleTypeDef *hcryp); +void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp); +void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp); +void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp); +uint32_t HAL_CRYP_GetError(const CRYP_HandleTypeDef *hcryp); + +/** + * @} + */ + +/** + * @} + */ + +/* Private macros --------------------------------------------------------*/ +/** @defgroup CRYP_Private_Macros CRYP Private Macros + * @{ + */ + +#define IS_CRYP_INSTANCE(INSTANCE)(((INSTANCE) == AES) || \ + ((INSTANCE) == SAES)) + +#define IS_CRYP_ALGORITHM(ALGORITHM) (((ALGORITHM) == CRYP_AES_ECB) || \ + ((ALGORITHM) == CRYP_AES_CBC) || \ + ((ALGORITHM) == CRYP_AES_CTR) || \ + ((ALGORITHM) == CRYP_AES_GCM_GMAC)|| \ + ((ALGORITHM) == CRYP_AES_CCM)) + + +#define IS_CRYP_KEYSIZE(KEYSIZE)(((KEYSIZE) == CRYP_KEYSIZE_128B) || \ + ((KEYSIZE) == CRYP_KEYSIZE_256B)) + +#define IS_CRYP_DATATYPE(DATATYPE)(((DATATYPE) == CRYP_NO_SWAP) || \ + ((DATATYPE) == CRYP_HALFWORD_SWAP) || \ + ((DATATYPE) == CRYP_BYTE_SWAP) || \ + ((DATATYPE) == CRYP_BIT_SWAP)) + +#define IS_CRYP_INIT(CONFIG)(((CONFIG) == CRYP_KEYIVCONFIG_ALWAYS) || \ + ((CONFIG) == CRYP_KEYNOCONFIG) || \ + ((CONFIG) == CRYP_IVCONFIG_ONCE) || \ + ((CONFIG) == CRYP_KEYIVCONFIG_ONCE)) + +#define IS_CRYP_BUFFERSIZE(ALGO, DATAWIDTH, SIZE) \ + (((((ALGO) == CRYP_AES_CTR)) && \ + ((((DATAWIDTH) == CRYP_DATAWIDTHUNIT_WORD) && (((SIZE) % 4U) == 0U)) || \ + (((DATAWIDTH) == CRYP_DATAWIDTHUNIT_BYTE) && (((SIZE) % 16U) == 0U)))) || \ + (((ALGO) == CRYP_AES_ECB) || ((ALGO) == CRYP_AES_CBC) || \ + ((ALGO)== CRYP_AES_GCM_GMAC) || ((ALGO) == CRYP_AES_CCM))) + + +/** + * @} + */ + + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup CRYP_Private_Constants CRYP Private Constants + * @{ + */ + +/** + * @} + */ +/* Private defines -----------------------------------------------------------*/ +/** @defgroup CRYP_Private_Defines CRYP Private Defines + * @{ + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup CRYP_Private_Variables CRYP Private Variables + * @{ + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup CRYP_Private_Functions CRYP Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* AES */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WBAxx_HAL_CRYP_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_cryp_ex.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_cryp_ex.h new file mode 100644 index 0000000000..aef6d54879 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_cryp_ex.h @@ -0,0 +1,154 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_cryp_ex.h + * @author MCD Application Team + * @brief Header file of CRYPEx HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_HAL_CRYP_EX_H +#define STM32WBAxx_HAL_CRYP_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal_def.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +#if defined(AES) + +/** @defgroup CRYPEx CRYPEx + * @brief CRYP Extension HAL module driver. + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup CRYPEx_Exported_Types CRYPEx Exported Types + * @{ + */ + +/** + * @} + */ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CRYPEx_Exported_Constants CRYPEx Constants + * @{ + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/** @defgroup CRYPEx_Private_Types CRYPEx Private Types + * @{ + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup CRYPEx_Private_Variables CRYPEx Private Variables + * @{ + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup CRYPEx_Private_Constants CRYPEx Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup CRYPEx_Private_Macros CRYPEx Private Macros + * @{ + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup CRYPEx_Private_Functions CRYPEx Private Functions + * @{ + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup CRYPEx_Exported_Functions CRYPEx Exported Functions + * @{ + */ + +/** @addtogroup CRYPEx_Exported_Functions_Group1 Extended AES processing functions + * @{ + */ +HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, const uint32_t *pAuthTag, + uint32_t Timeout); +HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, const uint32_t *pAuthTag, + uint32_t Timeout); +/** + * @} + */ + +/** @addtogroup CRYPEx_Exported_Functions_Group2 Wrap and Unwrap key functions + * @{ + */ +HAL_StatusTypeDef HAL_CRYPEx_UnwrapKey(CRYP_HandleTypeDef *hcryp, uint32_t *pInput, uint32_t Timeout); +HAL_StatusTypeDef HAL_CRYPEx_WrapKey(CRYP_HandleTypeDef *hcryp, uint32_t *pInput, uint32_t *pOutput, uint32_t Timeout); +/** + * @} + */ + +/** @addtogroup CRYPEx_Exported_Functions_Group3 Encrypt and Decrypt Shared key functions + * @{ + */ +HAL_StatusTypeDef HAL_CRYPEx_EncryptSharedKey(CRYP_HandleTypeDef *hcryp, uint32_t *pKey, uint32_t *pOutput, uint32_t ID, + uint32_t Timeout); +HAL_StatusTypeDef HAL_CRYPEx_DecryptSharedKey(CRYP_HandleTypeDef *hcryp, uint32_t *pKey, uint32_t ID, uint32_t Timeout); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* AES */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WBAxx_HAL_CRYP_EX_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_def.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_def.h new file mode 100644 index 0000000000..45b7a00a65 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_def.h @@ -0,0 +1,209 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_def.h + * @author MCD Application Team + * @brief This file contains HAL common defines, enumeration, macros and + * structures definitions. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32WBAxx_HAL_DEF +#define __STM32WBAxx_HAL_DEF + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#include +#endif + +#include "stm32wbaxx.h" +#include "Legacy/stm32_hal_legacy.h" /* Aliases file for old names compatibility */ +#include +#include + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief HAL Status structures definition + */ +typedef enum +{ + HAL_OK = 0x00, + HAL_ERROR = 0x01, + HAL_BUSY = 0x02, + HAL_TIMEOUT = 0x03 +} HAL_StatusTypeDef; + +/** + * @brief HAL Lock structures definition + */ +typedef enum +{ + HAL_UNLOCKED = 0x00, + HAL_LOCKED = 0x01 +} HAL_LockTypeDef; + +/* Exported macros -----------------------------------------------------------*/ + +#if !defined(UNUSED) +#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */ +#endif /* UNUSED */ + +#define HAL_MAX_DELAY 0xFFFFFFFFU + +#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT)) +#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U) + +#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \ + do{ \ + (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \ + (__DMA_HANDLE__).Parent = (__HANDLE__); \ + } while(0) + +/** @brief Reset the Handle's State field. + * @param __HANDLE__ specifies the Peripheral Handle. + * @note This macro can be used for the following purpose: + * - When the Handle is declared as local variable; before passing it as parameter + * to HAL_PPP_Init() for the first time, it is mandatory to use this macro + * to set to 0 the Handle's "State" field. + * Otherwise, "State" field may have any random value and the first time the function + * HAL_PPP_Init() is called, the low level hardware initialization will be missed + * (i.e. HAL_PPP_MspInit() will not be executed). + * - When there is a need to reconfigure the low level hardware: instead of calling + * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init(). + * In this later function, when the Handle's "State" field is set to 0, it will execute the function + * HAL_PPP_MspInit() which will reconfigure the low level hardware. + * @retval None + */ +#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0) + +#if (USE_RTOS == 1) +/* Reserved for future use */ +#error " USE_RTOS should be 0 in the current HAL release " +#else +#define __HAL_LOCK(__HANDLE__) \ + do{ \ + if((__HANDLE__)->Lock == HAL_LOCKED) \ + { \ + return HAL_BUSY; \ + } \ + else \ + { \ + (__HANDLE__)->Lock = HAL_LOCKED; \ + } \ + }while (0) + +#define __HAL_UNLOCK(__HANDLE__) \ + do{ \ + (__HANDLE__)->Lock = HAL_UNLOCKED; \ + }while (0) +#endif /* USE_RTOS */ + +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ +#ifndef __packed +#define __packed __attribute__((packed)) +#endif /* __packed */ +#elif defined (__GNUC__) /* GNU Compiler */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ +#ifndef __packed +#define __packed __attribute__((__packed__)) +#endif /* __packed */ +#endif /* __ARMCC_VERSION */ + +/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) || defined (__GNUC__) +/* ARM Compiler V6 & GNU Compiler */ +#ifndef __ALIGN_BEGIN +#define __ALIGN_BEGIN +#endif /* __ALIGN_BEGIN */ +#ifndef __ALIGN_END +#define __ALIGN_END __attribute__((aligned (4))) +#endif /* __ALIGN_END */ +#else +#ifndef __ALIGN_BEGIN +#define __ALIGN_BEGIN +#endif /* __ALIGN_BEGIN */ +#ifndef __ALIGN_END +#define __ALIGN_END +#endif /* __ALIGN_END */ +#endif /* __ARMCC_VERSION || __GNUC__ */ + +/* Macro to get variable aligned on 32-bytes, needed for cache maintenance purpose */ +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ +#define ALIGN_32BYTES(buf) __ALIGNED(32) buf +#elif defined (__ICCARM__) /* IAR Compiler */ +#define ALIGN_32BYTES(buf) _Pragma("data_alignment=32") buf +#elif defined (__GNUC__) /* GNU Compiler */ +#define ALIGN_32BYTES(buf) buf __attribute__ ((aligned (32))) +#endif /* __ARMCC_VERSION */ + +/** + * @brief __RAM_FUNC definition + */ +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +/* ARM Compiler V6 + --------------- + RAM functions are defined using the toolchain options. + Functions that are executed in RAM should reside in a separate source module. + Using the 'Options for File' dialog you can simply change the 'Code / Const' + area of a module to a memory space in physical RAM. + Available memory areas are declared in the 'Target' tab of the 'Options for Target' + dialog. +*/ +#define __RAM_FUNC + +#elif defined (__ICCARM__) +/* ICCARM Compiler + --------------- + RAM functions are defined using a specific toolchain keyword "__ramfunc". +*/ +#define __RAM_FUNC __ramfunc + +#elif defined (__GNUC__) +/* GNU Compiler + ------------ + RAM functions are defined using a specific toolchain attribute + "__attribute__((section(".RamFunc")))". +*/ +#define __RAM_FUNC __attribute__((section(".RamFunc"))) + +#endif /* __ARMCC_VERSION */ + +/** + * @brief __NOINLINE definition + */ +#if (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined (__GNUC__) +/* ARM Compiler V6 & GNU Compiler */ +#define __NOINLINE __attribute__((noinline)) + +#elif defined ( __ICCARM__ ) +/* ICCARM Compiler */ +#define __NOINLINE _Pragma("optimize = no_inline") + +#endif /* __ARMCC_VERSION || __GNUC__ */ + + +#ifdef __cplusplus +} +#endif + +#endif /* ___STM32WBAxx_HAL_DEF */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_dma.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_dma.h new file mode 100644 index 0000000000..d8c9946e31 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_dma.h @@ -0,0 +1,837 @@ +/** + ********************************************************************************************************************** + * @file stm32wbaxx_hal_dma.h + * @author MCD Application Team + * @brief Header file of DMA HAL module. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/ +#ifndef STM32WBAxx_HAL_DMA_H +#define STM32WBAxx_HAL_DMA_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32wbaxx_hal_def.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @addtogroup DMA + * @{ + */ + + +/* Exported types ----------------------------------------------------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Types DMA Exported Types + * @brief DMA Exported Types + * @{ + */ + +/** + * @brief DMA Transfer Configuration Structure definition. + */ +typedef struct +{ + uint32_t Request; /*!< Specifies the DMA channel request. + This parameter can be a value of @ref DMA_Request_Selection */ + + uint32_t BlkHWRequest; /*!< Specifies the Block hardware request mode for DMA channel. + Block Hardware request feature can be used only with dedicated peripherals. + This parameter can be a value of @ref DMA_Block_Request */ + + uint32_t Direction; /*!< Specifies the transfer direction for DMA channel. + This parameter can be a value of @ref DMA_Transfer_Direction */ + + uint32_t SrcInc; /*!< Specifies the source increment mode for the DMA channel. + This parameter can be a value of @ref DMA_Source_Increment_Mode */ + + uint32_t DestInc; /*!< Specifies the destination increment mode for the DMA channel. + This parameter can be a value of @ref DMA_Destination_Increment_Mode */ + + uint32_t SrcDataWidth; /*!< Specifies the source data width for the DMA channel. + This parameter can be a value of @ref DMA_Source_Data_Width */ + + uint32_t DestDataWidth; /*!< Specifies the destination data width for the DMA channel. + This parameter can be a value of @ref DMA_Destination_Data_Width */ + + uint32_t Priority; /*!< Specifies the priority level for the DMA channel. + This parameter can be a value of @ref DMA_Priority_Level */ + + uint32_t SrcBurstLength; /*!< Specifies the source burst length (number of beats within a burst) for the DMA + channel. + This parameter can be a value between 1 and 64 */ + + uint32_t DestBurstLength; /*!< Specifies the destination burst length (number of beats within a burst) for the + DMA channel. + This parameter can be a value between 1 and 64 */ + + uint32_t TransferAllocatedPort; /*!< Specifies the transfer allocated ports. + This parameter can be a combination of @ref DMA_Transfer_Allocated_Port */ + + uint32_t TransferEventMode; /*!< Specifies the transfer event mode for the DMA channel. + This parameter can be a value of @ref DMA_Transfer_Event_Mode */ + + uint32_t Mode; /*!< Specifies the transfer mode for the DMA channel. + This parameter can be a value of @ref DMA_Transfer_Mode */ + +} DMA_InitTypeDef; + +/** + * @brief DMA Linked-List Configuration Structure Definition. + */ +typedef struct +{ + uint32_t Priority; /*!< Specifies the priority level for the DMA channel. + This parameter can be a value of @ref DMA_Priority_Level */ + + uint32_t LinkStepMode; /*!< Specifies the link step mode for the DMA channel. + This parameter can be a value of @ref DMAEx_Link_Step_Mode */ + + uint32_t LinkAllocatedPort; /*!< Specifies the linked-list allocated port for the DMA channel. + This parameter can be a value of @ref DMAEx_Link_Allocated_Port */ + + uint32_t TransferEventMode; /*!< Specifies the transfer event mode for the DMA channel. + This parameter can be a value of @ref DMA_Transfer_Event_Mode */ + + uint32_t LinkedListMode; /*!< Specifies linked-list transfer mode for the DMA channel. + This parameter can be a value of @ref DMAEx_LinkedList_Mode */ + +} DMA_InitLinkedListTypeDef; + +/** + * @brief HAL DMA State Enumeration Definition. + */ +typedef enum +{ + HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ + HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ + HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ + HAL_DMA_STATE_ERROR = 0x03U, /*!< DMA error state */ + HAL_DMA_STATE_ABORT = 0x04U, /*!< DMA Abort state */ + HAL_DMA_STATE_SUSPEND = 0x05U, /*!< DMA Suspend state */ + +} HAL_DMA_StateTypeDef; + +/** + * @brief HAL DMA Level Complete Enumeration Definition. + */ +typedef enum +{ + HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full channel transfer */ + HAL_DMA_HALF_TRANSFER = 0x01U, /*!< Half channel transfer */ + +} HAL_DMA_LevelCompleteTypeDef; + +/** + * @brief HAL DMA Callbacks IDs Enumeration Definition. + */ +typedef enum +{ + HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Complete transfer callback ID */ + HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half complete transfer callback ID */ + HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error transfer callback ID */ + HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort transfer callback ID */ + HAL_DMA_XFER_SUSPEND_CB_ID = 0x04U, /*!< Suspend transfer callback ID */ + HAL_DMA_XFER_ALL_CB_ID = 0x05U /*!< All callback ID */ + +} HAL_DMA_CallbackIDTypeDef; + +/** + * @brief DMA handle Structure definition + */ +typedef struct __DMA_HandleTypeDef +{ + DMA_Channel_TypeDef *Instance; /*!< Register the DMA channel base address */ + + DMA_InitTypeDef Init; /*!< DMA channel init parameters */ + + DMA_InitLinkedListTypeDef InitLinkedList; /*!< DMA channel linked-list init parameters */ + + HAL_LockTypeDef Lock; /*!< DMA locking object */ + + uint32_t Mode; /*!< DMA transfer mode */ + + __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ + + __IO uint32_t ErrorCode; /*!< DMA error code */ + + void *Parent; /*!< Parent object state */ + + void (* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer complete callback */ + + void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA half transfer complete callback */ + + void (* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer error callback */ + + void (* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer Abort callback */ + + void (* XferSuspendCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer Suspend callback */ + + struct __DMA_QListTypeDef *LinkedListQueue; /*!< DMA linked-list queue */ + +} DMA_HandleTypeDef; +/** + * @} + */ + + +/* Exported constants ------------------------------------------------------------------------------------------------*/ +/** @defgroup DMA_Exported_Constants DMA Exported Constants + * @brief DMA Exported constants + * @{ + */ + +/** @defgroup DMA_Error_Codes DMA Error Codes + * @brief DMA Error Codes + * @{ + */ +#define HAL_DMA_ERROR_NONE (0x0000U) /*!< No error */ +#define HAL_DMA_ERROR_DTE (0x0001U) /*!< Data transfer error */ +#define HAL_DMA_ERROR_ULE (0x0002U) /*!< Update linked-list item error */ +#define HAL_DMA_ERROR_USE (0x0004U) /*!< User setting error */ +#define HAL_DMA_ERROR_TO (0x0008U) /*!< Trigger overrun error */ +#define HAL_DMA_ERROR_TIMEOUT (0x0010U) /*!< Timeout error */ +#define HAL_DMA_ERROR_NO_XFER (0x0020U) /*!< No transfer ongoing error */ +#define HAL_DMA_ERROR_BUSY (0x0040U) /*!< Busy error */ +#define HAL_DMA_ERROR_INVALID_CALLBACK (0x0080U) /*!< Invalid callback error */ +#define HAL_DMA_ERROR_NOT_SUPPORTED (0x0100U) /*!< Not supported mode */ +/** + * @} + */ + +/** @defgroup DMA_Interrupt_Enable_Definition DMA Interrupt Enable Definition + * @brief DMA Interrupt Enable Definition + * @{ + */ +#define DMA_IT_TC DMA_CCR_TCIE /*!< Transfer complete interrupt */ +#define DMA_IT_HT DMA_CCR_HTIE /*!< Half transfer complete interrupt */ +#define DMA_IT_DTE DMA_CCR_DTEIE /*!< Data transfer error interrupt */ +#define DMA_IT_ULE DMA_CCR_ULEIE /*!< Update linked-list item error interrupt */ +#define DMA_IT_USE DMA_CCR_USEIE /*!< User eetting error interrupt */ +#define DMA_IT_SUSP DMA_CCR_SUSPIE /*!< Completed suspension interrupt */ +#define DMA_IT_TO DMA_CCR_TOIE /*!< Trigger overrun interrupt */ +/** + * @} + */ + +/** @defgroup DMA_Flag_Definition DMA Flag Definition + * @brief DMA Flag Definition + * @{ + */ +#define DMA_FLAG_IDLE DMA_CSR_IDLEF /*!< Idle flag */ +#define DMA_FLAG_TC DMA_CSR_TCF /*!< Transfer complete flag */ +#define DMA_FLAG_HT DMA_CSR_HTF /*!< Half transfer complete flag */ +#define DMA_FLAG_DTE DMA_CSR_DTEF /*!< Data transfer error flag */ +#define DMA_FLAG_ULE DMA_CSR_ULEF /*!< Update linked-list item error flag */ +#define DMA_FLAG_USE DMA_CSR_USEF /*!< User setting error flag */ +#define DMA_FLAG_SUSP DMA_CSR_SUSPF /*!< Completed suspension flag */ +#define DMA_FLAG_TO DMA_CSR_TOF /*!< Trigger overrun flag */ +/** + * @} + */ + +/** @defgroup DMA_Request_Selection DMA Request Selection + * @brief DMA Request Selection + * @{ + */ +/* GPDMA1 requests */ +#define GPDMA1_REQUEST_ADC4 0U /*!< GPDMA1 HW request is ADC4 */ +#if defined (SPI1) +#define GPDMA1_REQUEST_SPI1_RX 1U /*!< GPDMA1 HW request is SPI1_RX */ +#define GPDMA1_REQUEST_SPI1_TX 2U /*!< GPDMA1 HW request is SPI1_TX */ +#endif /* SPI1 */ +#define GPDMA1_REQUEST_SPI3_RX 3U /*!< GPDMA1 HW request is SPI3_RX */ +#define GPDMA1_REQUEST_SPI3_TX 4U /*!< GPDMA1 HW request is SPI3_TX */ +#if defined (I2C1) +#define GPDMA1_REQUEST_I2C1_RX 5U /*!< GPDMA1 HW request is I2C1_RX */ +#define GPDMA1_REQUEST_I2C1_TX 6U /*!< GPDMA1 HW request is I2C1_TX */ +#define GPDMA1_REQUEST_I2C1_EVC 7U /*!< GPDMA1 HW request is I2C1_EVC */ +#endif /* I2C1 */ +#define GPDMA1_REQUEST_I2C3_RX 8U /*!< GPDMA1 HW request is I2C3_RX */ +#define GPDMA1_REQUEST_I2C3_TX 9U /*!< GPDMA1 HW request is I2C3_TX */ +#define GPDMA1_REQUEST_I2C3_EVC 10U /*!< GPDMA1 HW request is I2C3_EVC */ +#define GPDMA1_REQUEST_USART1_RX 11U /*!< GPDMA1 HW request is USART1_RX */ +#define GPDMA1_REQUEST_USART1_TX 12U /*!< GPDMA1 HW request is USART1_TX */ +#if defined (USART2) +#define GPDMA1_REQUEST_USART2_RX 13U /*!< GPDMA1 HW request is USART2_RX */ +#define GPDMA1_REQUEST_USART2_TX 14U /*!< GPDMA1 HW request is USART2_TX */ +#endif /* USART2 */ +#define GPDMA1_REQUEST_LPUART1_RX 15U /*!< GPDMA1 HW request is LPUART1_RX */ +#define GPDMA1_REQUEST_LPUART1_TX 16U /*!< GPDMA1 HW request is LPUART1_TX */ +#if defined (SAI1) +#define GPDMA1_REQUEST_SAI1_A 17U /*!< GPDMA1 HW request is SAI1_A */ +#define GPDMA1_REQUEST_SAI1_B 18U /*!< GPDMA1 HW request is SAI1_B */ +#endif /* SAI1 */ +#define GPDMA1_REQUEST_TIM1_CH1 19U /*!< GPDMA1 HW request is TIM1_CH1 */ +#define GPDMA1_REQUEST_TIM1_CH2 20U /*!< GPDMA1 HW request is TIM1_CH2 */ +#define GPDMA1_REQUEST_TIM1_CH3 21U /*!< GPDMA1 HW request is TIM1_CH3 */ +#define GPDMA1_REQUEST_TIM1_CH4 22U /*!< GPDMA1 HW request is TIM1_CH4 */ +#define GPDMA1_REQUEST_TIM1_UP 23U /*!< GPDMA1 HW request is TIM1_UP */ +#define GPDMA1_REQUEST_TIM1_TRIG 24U /*!< GPDMA1 HW request is TIM1_TRIG */ +#define GPDMA1_REQUEST_TIM1_COM 25U /*!< GPDMA1 HW request is TIM1_COM */ +#define GPDMA1_REQUEST_TIM2_CH1 26U /*!< GPDMA1 HW request is TIM2_CH1 */ +#define GPDMA1_REQUEST_TIM2_CH2 27U /*!< GPDMA1 HW request is TIM2_CH2 */ +#define GPDMA1_REQUEST_TIM2_CH3 28U /*!< GPDMA1 HW request is TIM2_CH3 */ +#define GPDMA1_REQUEST_TIM2_CH4 29U /*!< GPDMA1 HW request is TIM2_CH4 */ +#define GPDMA1_REQUEST_TIM2_UP 30U /*!< GPDMA1 HW request is TIM2_UP */ +#if defined (TIM3) +#define GPDMA1_REQUEST_TIM3_CH1 31U /*!< GPDMA1 HW request is TIM3_CH1 */ +#define GPDMA1_REQUEST_TIM3_CH2 32U /*!< GPDMA1 HW request is TIM3_CH2 */ +#define GPDMA1_REQUEST_TIM3_CH3 33U /*!< GPDMA1 HW request is TIM3_CH3 */ +#define GPDMA1_REQUEST_TIM3_CH4 34U /*!< GPDMA1 HW request is TIM3_CH4 */ +#define GPDMA1_REQUEST_TIM3_UP 35U /*!< GPDMA1 HW request is TIM3_UP */ +#define GPDMA1_REQUEST_TIM3_TRIG 36U /*!< GPDMA1 HW request is TIM3_TRIG */ +#endif /* TIM3 */ +#define GPDMA1_REQUEST_TIM16_CH1 37U /*!< GPDMA1 HW request is TIM16_CH1 */ +#define GPDMA1_REQUEST_TIM16_UP 38U /*!< GPDMA1 HW request is TIM16_UP */ +#if defined (TIM17) +#define GPDMA1_REQUEST_TIM17_CH1 39U /*!< GPDMA1 HW request is TIM17_CH1 */ +#define GPDMA1_REQUEST_TIM17_UP 40U /*!< GPDMA1 HW request is TIM17_UP */ +#endif /* TIM17 */ +#if defined (AES) +#define GPDMA1_REQUEST_AES_IN 41U /*!< GPDMA1 HW request is AES_IN */ +#define GPDMA1_REQUEST_AES_OUT 42U /*!< GPDMA1 HW request is AES_OUT */ +#endif /* AES */ +#define GPDMA1_REQUEST_HASH_IN 43U /*!< GPDMA1 HW request is HASH_IN */ +#if defined (SAES) +#define GPDMA1_REQUEST_SAES_IN 44U /*!< GPDMA1 HW request is SAES_IN */ +#define GPDMA1_REQUEST_SAES_OUT 45U /*!< GPDMA1 HW request is SAES_OUT */ +#endif /* defined (SAES) */ +#define GPDMA1_REQUEST_LPTIM1_IC1 46U /*!< GPDMA1 HW request is LPTIM1_IC1 */ +#define GPDMA1_REQUEST_LPTIM1_IC2 47U /*!< GPDMA1 HW request is LPTIM1_IC2 */ +#define GPDMA1_REQUEST_LPTIM1_UE 48U /*!< GPDMA1 HW request is LPTIM1_UE */ +#if defined (LPTIM2) +#define GPDMA1_REQUEST_LPTIM2_IC1 49U /*!< GPDMA1 HW request is LPTIM2_IC1 */ +#define GPDMA1_REQUEST_LPTIM2_IC2 50U /*!< GPDMA1 HW request is LPTIM2_IC2 */ +#define GPDMA1_REQUEST_LPTIM2_UE 51U /*!< GPDMA1 HW request is LPTIM2_UE */ +#endif /* LPTIM2 */ + +/* Software request */ +#define DMA_REQUEST_SW DMA_CTR2_SWREQ /*!< DMA SW request */ +/** + * @} + */ + +/** @defgroup DMA_Block_Request DMA Block Request + * @brief DMA Block Request + * @{ + */ +#define DMA_BREQ_SINGLE_BURST 0x00000000U /*!< Hardware request protocol at a single / burst level */ +#define DMA_BREQ_BLOCK DMA_CTR2_BREQ /*!< Hardware request protocol at a block level */ +/** + * @} + */ + +/** @defgroup DMA_Transfer_Direction DMA Transfer Direction + * @brief DMA transfer direction + * @{ + */ +#define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ +#define DMA_MEMORY_TO_PERIPH DMA_CTR2_DREQ /*!< Memory to peripheral direction */ +#define DMA_MEMORY_TO_MEMORY DMA_CTR2_SWREQ /*!< Memory to memory direction */ +/** + * @} + */ + +/** @defgroup DMA_Source_Increment_Mode DMA Source Increment Mode + * @brief DMA Source Increment Mode + * @{ + */ +#define DMA_SINC_FIXED 0x00000000U /*!< Source fixed single / burst */ +#define DMA_SINC_INCREMENTED DMA_CTR1_SINC /*!< Source incremented single / burst */ +/** + * @} + */ + +/** @defgroup DMA_Destination_Increment_Mode DMA Destination Increment Mode + * @brief DMA Destination Increment Mode + * @{ + */ +#define DMA_DINC_FIXED 0x00000000U /*!< Destination fixed single / burst */ +#define DMA_DINC_INCREMENTED DMA_CTR1_DINC /*!< Destination incremented single / burst */ +/** + * @} + */ + +/** @defgroup DMA_Source_Data_Width DMA Source Data Width + * @brief DMA Source Data Width + * @{ + */ +#define DMA_SRC_DATAWIDTH_BYTE 0x00000000U /*!< Source data width : Byte */ +#define DMA_SRC_DATAWIDTH_HALFWORD DMA_CTR1_SDW_LOG2_0 /*!< Source data width : HalfWord */ +#define DMA_SRC_DATAWIDTH_WORD DMA_CTR1_SDW_LOG2_1 /*!< Source data width : Word */ +/** + * @} + */ + +/** @defgroup DMA_Destination_Data_Width DMA destination Data Width + * @brief DMA destination Data Width + * @{ + */ +#define DMA_DEST_DATAWIDTH_BYTE 0x00000000U /*!< Destination data width : Byte */ +#define DMA_DEST_DATAWIDTH_HALFWORD DMA_CTR1_DDW_LOG2_0 /*!< Destination data width : HalfWord */ +#define DMA_DEST_DATAWIDTH_WORD DMA_CTR1_DDW_LOG2_1 /*!< Destination data width : Word */ + +/** + * @} + */ + +/** @defgroup DMA_Priority_Level DMA Priority Level + * @brief DMA Priority Level + * @{ + */ +#define DMA_LOW_PRIORITY_LOW_WEIGHT 0x00000000U /*!< Priority level : Low Priority, Low weight */ +#define DMA_LOW_PRIORITY_MID_WEIGHT DMA_CCR_PRIO_0 /*!< Priority level : Low Priority, Mid weight */ +#define DMA_LOW_PRIORITY_HIGH_WEIGHT DMA_CCR_PRIO_1 /*!< Priority level : Low Priority, High weight */ +#define DMA_HIGH_PRIORITY DMA_CCR_PRIO /*!< Priority level : HIGH Priority */ +/** + * @} + */ + +/** @defgroup DMA_Transfer_Allocated_Port DMA Transfer Allocated Port + * @brief DMA Transfer Allocated Port + * @{ + */ +#define DMA_SRC_ALLOCATED_PORT0 0x00000000U /*!< Source allocated Port 0 */ +#define DMA_SRC_ALLOCATED_PORT1 DMA_CTR1_SAP /*!< Source allocated Port 1 */ +#define DMA_DEST_ALLOCATED_PORT0 0x00000000U /*!< Destination allocated Port 0 */ +#define DMA_DEST_ALLOCATED_PORT1 DMA_CTR1_DAP /*!< Destination allocated Port 1 */ +/** + * @} + */ + +/** @defgroup DMA_Transfer_Event_Mode DMA Transfer Event Mode + * @brief DMA Transfer Event Mode + * @{ + */ +#define DMA_TCEM_BLOCK_TRANSFER 0x00000000U /*!< The TC event is generated at the end of each block and the + HT event is generated at the half of each block */ +#define DMA_TCEM_EACH_LL_ITEM_TRANSFER DMA_CTR2_TCEM_1 /*!< The TC event is generated at the end of each linked-list + item and the HT event is generated at the half of each + linked-list item */ +#define DMA_TCEM_LAST_LL_ITEM_TRANSFER DMA_CTR2_TCEM /*!< The TC event is generated at the end of the last + linked-list item and the HT event is generated at the half + of the last linked-list item */ +/** + * @} + */ + +/** @defgroup DMA_Transfer_Mode DMA Transfer Mode + * @brief DMA Transfer Mode + * @{ + */ +#define DMA_NORMAL (0x00U) /*!< Normal DMA transfer */ +/** + * @} + */ + +/** @defgroup DMA_Channel_Attributes DMA Channel Attributes + * @brief DMA Channel Security and Privilege Attributes + * @note Secure and non-secure attributes are only available from the secure world when TZEN = 1 + * @{ + */ +#define DMA_CHANNEL_PRIV (DMA_CHANNEL_ATTR_PRIV_MASK | 0x01U) /*!< Channel is privileged */ +#define DMA_CHANNEL_NPRIV (DMA_CHANNEL_ATTR_PRIV_MASK) /*!< Channel is unprivileged */ + +#define DMA_CHANNEL_SEC (DMA_CHANNEL_ATTR_SEC_MASK | 0x02U) /*!< Channel is secure */ +#define DMA_CHANNEL_NSEC (DMA_CHANNEL_ATTR_SEC_MASK) /*!< Channel is non-secure */ +#define DMA_CHANNEL_SRC_SEC (DMA_CHANNEL_ATTR_SEC_SRC_MASK | 0x04U) /*!< Channel source is secure */ +#define DMA_CHANNEL_SRC_NSEC (DMA_CHANNEL_ATTR_SEC_SRC_MASK) /*!< Channel source is non-secure */ +#define DMA_CHANNEL_DEST_SEC (DMA_CHANNEL_ATTR_SEC_DEST_MASK | 0x08U) /*!< Channel destination is secure */ +#define DMA_CHANNEL_DEST_NSEC (DMA_CHANNEL_ATTR_SEC_DEST_MASK) /*!< Channel destination is non-secure */ + +#define DMA_CHANNEL_ATTRIBUTE_UNLOCKED (0x00U) /*!< Channel attribute is unlocked */ +#define DMA_CHANNEL_ATTRIBUTE_LOCKED (0x01U) /*!< Channel attribute is locked */ +/** + * @} + */ + + + +/** + * @} + */ + + +/* Exported macro ----------------------------------------------------------------------------------------------------*/ +/** @defgroup DMA_Exported_Macros DMA Exported Macros + * @brief DMA Exported Macros + * @{ + */ + +/** @brief Reset DMA handle state. + * @param __HANDLE__ : DMA handle. + * @retval None. + */ +#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) \ + ((__HANDLE__)->State = HAL_DMA_STATE_RESET) + +/** + * @brief Enable the specified DMA Channel. + * @param __HANDLE__ : DMA handle. + * @retval None + */ +#define __HAL_DMA_ENABLE(__HANDLE__) \ + ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN) + +/** + * @brief Disable the specified DMA Channel. + * @param __HANDLE__ : DMA handle. + * @retval None + */ +#define __HAL_DMA_DISABLE(__HANDLE__) \ + ((__HANDLE__)->Instance->CCR |= (DMA_CCR_SUSP | DMA_CCR_RESET)) + +/** + * @brief Get the DMA channel pending flags. + * @param __HANDLE__ : DMA handle. + * @param __FLAG__ : Get the specified flag. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TC : Transfer Complete flag. + * @arg DMA_FLAG_HT : Half Transfer Complete flag. + * @arg DMA_FLAG_DTE : Data Transfer Error flag. + * @arg DMA_FLAG_ULE : Update linked-list Error flag. + * @arg DMA_FLAG_USE : User Setting Error flag. + * @arg DMA_FLAG_TO : Trigger Overrun flag. + * @arg DMA_FLAG_SUSP : Completed Suspension flag. + * @arg DMA_FLAG_IDLEF : Idle flag. + * @retval The state of FLAG (SET or RESET). + */ +#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) \ + ((__HANDLE__)->Instance->CSR & (__FLAG__)) + +/** + * @brief Clear the DMA Channel pending flags. + * @param __HANDLE__ : DMA handle. + * @param __FLAG__ : Specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TC : Transfer Complete flag. + * @arg DMA_FLAG_HT : Half Transfer Complete flag. + * @arg DMA_FLAG_DTE : Data Transfer Error flag. + * @arg DMA_FLAG_ULE : Update Linked-List Error flag. + * @arg DMA_FLAG_USE : User Setting Error flag. + * @arg DMA_FLAG_TO : Trigger Overrun flag. + * @arg DMA_FLAG_SUSP : Completed Suspension flag. + * @retval None + */ +#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ + ((__HANDLE__)->Instance->CFCR = (__FLAG__)) + +/** + * @brief Enable the specified DMA Channel interrupts. + * @param __HANDLE__ : DMA handle. + * @param __INTERRUPT__ : Specifies the DMA interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg DMA_IT_TC : Transfer Complete interrupt. + * @arg DMA_IT_HT : Half Transfer Complete interrupt. + * @arg DMA_IT_DTE : Data Transfer Error interrupt. + * @arg DMA_IT_ULE : Update Linked-List Error interrupt. + * @arg DMA_IT_USE : User Setting Error interrupt. + * @arg DMA_IT_TO : Trigger Overrun interrupt. + * @arg DMA_IT_SUSP : Completed Suspension interrupt. + * @retval None + */ +#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ + ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__)) + +/** + * @brief Disable the specified DMA Channel interrupts. + * @param __HANDLE__ : DMA handle. + * @param __INTERRUPT__ : specifies the DMA interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg DMA_IT_TC : Transfer Complete interrupt. + * @arg DMA_IT_HT : Half Transfer Complete interrupt. + * @arg DMA_IT_DTE : Data Transfer Error interrupt. + * @arg DMA_IT_ULE : Update Linked-List Error interrupt. + * @arg DMA_IT_USE : User Setting Error interrupt. + * @arg DMA_IT_TO : Trigger Overrun interrupt. + * @arg DMA_IT_SUSP : Completed Suspension interrupt. + * @retval None + */ +#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ + ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__)) + +/** + * @brief Checks whether the specified DMA Channel interrupt is enabled or not. + * @param __HANDLE__ : DMA handle. + * @param __INTERRUPT__ : specifies the DMA interrupt source to check. + * @arg DMA_IT_TC : Transfer Complete interrupt. + * @arg DMA_IT_HT : Half Transfer Complete interrupt. + * @arg DMA_IT_DTE : Data Transfer Error interrupt. + * @arg DMA_IT_ULE : Update Linked-List Error interrupt. + * @arg DMA_IT_USE : User Setting Error interrupt. + * @arg DMA_IT_TO : Trigger Overrun interrupt. + * @arg DMA_IT_SUSP : Completed Suspension interrupt. + * @retval The state of DMA_IT (SET or RESET). + */ +#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ + (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) + +/** + * @brief Writes the block number of bytes to be transferred from the source on the DMA Channel. + * @param __HANDLE__ : DMA handle. + * @param __COUNTER__ : Number of data bytes to be transferred from the source (from 0 to 65535). + */ +#define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) \ + MODIFY_REG((__HANDLE__)->Instance->CBR1, DMA_CBR1_BNDT, (__COUNTER__)) + +/** + * @brief Returns the number of remaining data bytes in the current DMA Channel transfer. + * @param __HANDLE__ : DMA handle. + * @retval The number of remaining data units in the current DMA Stream transfer. + */ +#define __HAL_DMA_GET_COUNTER(__HANDLE__) \ + (((__HANDLE__)->Instance->CBR1) & DMA_CBR1_BNDT) +/** + * @} + */ + + +/* Include DMA HAL Extension module */ +#include "stm32wbaxx_hal_dma_ex.h" + + +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @defgroup DMA_Exported_Functions DMA Exported Functions + * @brief DMA Exported Functions + * @{ + */ + +/** @defgroup DMA_Exported_Functions_Group1 Initialization and De-Initialization Functions + * @brief Initialization and De-Initialization Functions + * @{ + */ +HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *const hdma); +HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *const hdma); +/** + * @} + */ + +/** @defgroup DMA_Exported_Functions_Group2 I/O Operation Functions + * @brief I/O Operation Functions + * @{ + */ +HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *const hdma, + uint32_t SrcAddress, + uint32_t DstAddress, + uint32_t SrcDataSize); +HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *const hdma, + uint32_t SrcAddress, + uint32_t DstAddress, + uint32_t SrcDataSize); +HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *const hdma); +HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *const hdma); +HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *const hdma, + HAL_DMA_LevelCompleteTypeDef CompleteLevel, + uint32_t Timeout); +void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma); +HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *const hdma, + HAL_DMA_CallbackIDTypeDef CallbackID, + void (*const pCallback)(DMA_HandleTypeDef *const _hdma)); +HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *const hdma, + HAL_DMA_CallbackIDTypeDef CallbackID); +/** + * @} + */ + +/** @defgroup DMA_Exported_Functions_Group3 State and Error Functions + * @brief State and Error Functions + * @{ + */ +HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef const *const hdma); +uint32_t HAL_DMA_GetError(DMA_HandleTypeDef const *const hdma); +/** + * @} + */ + +/** @defgroup DMA_Exported_Functions_Group4 DMA Attributes Functions + * @brief DMA Attributes Functions + * @{ + */ +#if defined (DMA_PRIVCFGR_PRIV0) +HAL_StatusTypeDef HAL_DMA_ConfigChannelAttributes(DMA_HandleTypeDef *const hdma, + uint32_t ChannelAttributes); +HAL_StatusTypeDef HAL_DMA_GetConfigChannelAttributes(DMA_HandleTypeDef const *const hdma, + uint32_t *const pChannelAttributes); +#if defined (DMA_RCFGLOCKR_LOCK0) +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +HAL_StatusTypeDef HAL_DMA_LockChannelAttributes(DMA_HandleTypeDef const *const hdma); +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *const hdma, + uint32_t *const pLockState); + +#endif /* DMA_RCFGLOCKR_LOCK0 */ +#endif /* DMA_PRIVCFGR_PRIV0 */ +/** + * @} + */ + +/** + * @} + */ + + +/* Private constants -------------------------------------------------------------------------------------------------*/ +/** @defgroup DMA_Private_Constants DMA Private Constants + * @brief DMA Private Constants + * @{ + */ +#define HAL_TIMEOUT_DMA_ABORT (0x00000005U) /* DMA channel abort timeout 5 milli-second */ +#define HAL_DMA_CHANNEL_START (0x00000050U) /* DMA channel offset */ +#define HAL_DMA_CHANNEL_SIZE (0x00000080U) /* DMA channel size */ +#define HAL_DMA_OFFSET_MASK (0x00000FFFU) /* DMA channel offset mask */ +#define DMA_CHANNEL_ATTR_PRIV_MASK (0x00000010U) /* DMA channel privilege mask */ +#define DMA_CHANNEL_ATTR_SEC_MASK (0x00000020U) /* DMA channel secure mask */ +#define DMA_CHANNEL_ATTR_SEC_SRC_MASK (0x00000040U) /* DMA channel source secure mask */ +#define DMA_CHANNEL_ATTR_SEC_DEST_MASK (0x00000080U) /* DMA channel destination secure mask */ +#define DMA_CHANNEL_ATTR_VALUE_MASK (0x0000000FU) /* DMA channel attributes value mask */ +#define DMA_CHANNEL_ATTR_ITEM_MASK (0x000000F0U) /* DMA channel attributes item mask */ +#define DMA_CHANNEL_BURST_MIN (0x00000001U) /* DMA channel minimum burst size */ +#define DMA_CHANNEL_BURST_MAX (0x00000040U) /* DMA channel maximum burst size */ +/** + * @} + */ + + +/* Private macros ----------------------------------------------------------------------------------------------------*/ +/** @defgroup DMA_Private_Macros DMA Private Macros + * @brief DMA Private Macros + * @{ + */ +#define GET_DMA_INSTANCE(__HANDLE__) \ + ((DMA_TypeDef *)((uint32_t)((__HANDLE__)->Instance) & (~HAL_DMA_OFFSET_MASK))) + +#define GET_DMA_CHANNEL(__HANDLE__) \ + ((((uint32_t)((__HANDLE__)->Instance) & HAL_DMA_OFFSET_MASK) - HAL_DMA_CHANNEL_START) / HAL_DMA_CHANNEL_SIZE) + +#define IS_DMA_MODE(MODE) \ + ((MODE) == DMA_NORMAL) + +#define IS_DMA_DIRECTION(DIRECTION) \ + (((DIRECTION) == DMA_PERIPH_TO_MEMORY) || \ + ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ + ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) + +#define IS_DMA_LEVEL_COMPLETE(LEVEL) \ + (((LEVEL) == HAL_DMA_FULL_TRANSFER) || \ + ((LEVEL) == HAL_DMA_HALF_TRANSFER)) + +#define IS_DMA_SOURCE_INC(INC) \ + (((INC) == DMA_SINC_FIXED) || \ + ((INC) == DMA_SINC_INCREMENTED)) + +#define IS_DMA_DESTINATION_INC(INC) \ + (((INC) == DMA_DINC_FIXED) || \ + ((INC) == DMA_DINC_INCREMENTED)) + +#define IS_DMA_SOURCE_DATA_WIDTH(WIDTH) \ + (((WIDTH) == DMA_SRC_DATAWIDTH_BYTE) || \ + ((WIDTH) == DMA_SRC_DATAWIDTH_HALFWORD) || \ + ((WIDTH) == DMA_SRC_DATAWIDTH_WORD)) + +#define IS_DMA_DESTINATION_DATA_WIDTH(WIDTH) \ + (((WIDTH) == DMA_DEST_DATAWIDTH_BYTE) || \ + ((WIDTH) == DMA_DEST_DATAWIDTH_HALFWORD) || \ + ((WIDTH) == DMA_DEST_DATAWIDTH_WORD)) + +#define IS_DMA_BURST_LENGTH(LENGTH) \ + (((LENGTH) >= DMA_CHANNEL_BURST_MIN) && \ + ((LENGTH) <= DMA_CHANNEL_BURST_MAX)) + +#define IS_DMA_PRIORITY(PRIORITY) \ + (((PRIORITY) == DMA_LOW_PRIORITY_LOW_WEIGHT) || \ + ((PRIORITY) == DMA_LOW_PRIORITY_MID_WEIGHT) || \ + ((PRIORITY) == DMA_LOW_PRIORITY_HIGH_WEIGHT) || \ + ((PRIORITY) == DMA_HIGH_PRIORITY)) + +#define IS_DMA_TRANSFER_ALLOCATED_PORT(ALLOCATED_PORT) \ + (((ALLOCATED_PORT) & (~(DMA_CTR1_SAP | DMA_CTR1_DAP))) == 0U) + +#if defined (LPTIM2) +#define IS_DMA_REQUEST(REQUEST) \ + (((REQUEST) == DMA_REQUEST_SW) || \ + ((REQUEST) <= GPDMA1_REQUEST_LPTIM2_UE)) +#else +#define IS_DMA_REQUEST(REQUEST) \ + (((REQUEST) == DMA_REQUEST_SW) || \ + ((REQUEST) <= GPDMA1_REQUEST_LPTIM1_UE)) +#endif /* LPTIM2 */ + +#define IS_DMA_BLOCK_HW_REQUEST(MODE) \ + (((MODE) == DMA_BREQ_SINGLE_BURST) || \ + ((MODE) == DMA_BREQ_BLOCK)) + +#define IS_DMA_TCEM_EVENT_MODE(MODE) \ + (((MODE) == DMA_TCEM_BLOCK_TRANSFER) || \ + ((MODE) == DMA_TCEM_EACH_LL_ITEM_TRANSFER) || \ + ((MODE) == DMA_TCEM_LAST_LL_ITEM_TRANSFER)) + +#define IS_DMA_BLOCK_SIZE(SIZE) \ + (((SIZE) > 0U) && ((SIZE) <= DMA_CBR1_BNDT)) + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define IS_DMA_ATTRIBUTES(ATTRIBUTE) \ + (((ATTRIBUTE) != 0U) && (((ATTRIBUTE) & (~(DMA_CHANNEL_ATTR_VALUE_MASK | DMA_CHANNEL_ATTR_ITEM_MASK))) == 0U) && \ + (((((ATTRIBUTE) & DMA_CHANNEL_ATTR_ITEM_MASK) >> 4U) | ((ATTRIBUTE) & DMA_CHANNEL_ATTR_VALUE_MASK)) == \ + (((ATTRIBUTE) & DMA_CHANNEL_ATTR_ITEM_MASK) >> 4U))) +#else +#define IS_DMA_ATTRIBUTES(ATTRIBUTE) \ + (((ATTRIBUTE) == DMA_CHANNEL_PRIV) || \ + ((ATTRIBUTE) == DMA_CHANNEL_NPRIV)) +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define IS_DMA_GLOBAL_ACTIVE_FLAG_S(INSTANCE, GLOBAL_FLAG) \ + (((INSTANCE)->SMISR & (GLOBAL_FLAG))) +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#define IS_DMA_GLOBAL_ACTIVE_FLAG_NS(INSTANCE, GLOBAL_FLAG) \ + (((INSTANCE)->MISR & (GLOBAL_FLAG))) + +/** + * @} + */ + + +/* Private functions -------------------------------------------------------------------------------------------------*/ +/** @defgroup DMA_Private_Functions DMA Private Functions + * @brief DMA Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WBAxx_HAL_DMA_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_dma_ex.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_dma_ex.h new file mode 100644 index 0000000000..e880d3556f --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_dma_ex.h @@ -0,0 +1,589 @@ +/** + ********************************************************************************************************************** + * @file stm32wbaxx_hal_dma_ex.h + * @author MCD Application Team + * @brief Header file of DMA HAL extension module. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/ +#ifndef STM32WBAxx_HAL_DMA_EX_H +#define STM32WBAxx_HAL_DMA_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32wbaxx_hal_def.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @addtogroup DMAEx + * @{ + */ + +/* Exported types ----------------------------------------------------------------------------------------------------*/ +/** @defgroup DMAEx_Exported_Types DMAEx Exported Types + * @brief DMAEx Exported types + * @{ + */ + +/** + * @brief DMAEx Data Handling Configuration Structure Definition. + */ +typedef struct +{ + uint32_t DataExchange; /*!< Specifies the DMA channel data exchange mode. + This parameter can be a value of @ref DMAEx_Data_Exchange */ + + uint32_t DataAlignment; /*!< Specifies the DMA channel data padding and alignment mode + This parameter can be a value of @ref DMAEx_Data_Alignment */ + +} DMA_DataHandlingConfTypeDef; + +/** + * @brief DMAEx Trigger Configuration Structure Definition. + */ +typedef struct +{ + uint32_t TriggerMode; /*!< Specifies the DMA channel trigger mode. + This parameter can be a value of @ref DMAEx_Trigger_Mode */ + + uint32_t TriggerPolarity; /*!< Specifies the DMA channel trigger event polarity. + This parameter can be a value of @ref DMAEx_Trigger_Polarity */ + + uint32_t TriggerSelection; /*!< Specifies the DMA channel trigger event selection. + This parameter can be a value of @ref DMAEx_Trigger_Selection */ + +} DMA_TriggerConfTypeDef; + +/** + * @brief DMAEx Queue State Enumeration Definition. + */ +typedef enum +{ + HAL_DMA_QUEUE_STATE_RESET = 0x00U, /*!< DMA queue empty */ + HAL_DMA_QUEUE_STATE_READY = 0x01U, /*!< DMA queue ready for use */ + HAL_DMA_QUEUE_STATE_BUSY = 0x02U /*!< DMA queue execution on going */ + +} HAL_DMA_QStateTypeDef; + +/** + * @brief DMAEx Linked-List Node Configuration Structure Definition. + */ +typedef struct +{ + uint32_t NodeType; /*!< Specifies the DMA channel node type. + This parameter can be a value of @ref DMAEx_Node_Type */ + + DMA_InitTypeDef Init; /*!< Specifies the DMA channel basic configuration */ + + DMA_DataHandlingConfTypeDef DataHandlingConfig; /*!< Specifies the DMA channel data handling channel configuration */ + + DMA_TriggerConfTypeDef TriggerConfig; /*!< Specifies the DMA channel trigger configuration */ + + uint32_t SrcAddress; /*!< Specifies the source memory address */ + uint32_t DstAddress; /*!< Specifies the destination memory address */ + uint32_t DataSize; /*!< Specifies the source data size in bytes */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + uint32_t SrcSecure; /*!< Specifies the source security attribute */ + uint32_t DestSecure; /*!< Specifies the destination security attribute */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +} DMA_NodeConfTypeDef; + +/** + * @brief DMAEx Linked-List Node Structure Definition. + */ +typedef struct +{ + uint32_t LinkRegisters[6U]; /*!< Physical Node register description */ + uint32_t NodeInfo; /*!< Node information */ + +} DMA_NodeTypeDef; + +/** + * @brief DMAEx Linked-List Queue Structure Definition. + */ +typedef struct __DMA_QListTypeDef +{ + DMA_NodeTypeDef *Head; /*!< Specifies the queue head node */ + + DMA_NodeTypeDef *FirstCircularNode; /*!< Specifies the queue first circular node */ + + uint32_t NodeNumber; /*!< Specifies the queue node number */ + + __IO HAL_DMA_QStateTypeDef State; /*!< Specifies the queue state */ + + __IO uint32_t ErrorCode; /*!< Specifies the queue error code */ + + __IO uint32_t Type; /*!< Specifies whether the queue is static or dynamic */ + +} DMA_QListTypeDef; +/** + * @} + */ + +/* Exported constants ------------------------------------------------------------------------------------------------*/ +/** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants + * @brief DMAEx Exported Constants + * @{ + */ + +/** @defgroup Queue_Error_Codes Queue Error Codes + * @brief Queue Error Codes + * @{ + */ +#define HAL_DMA_QUEUE_ERROR_NONE (0x00U) /*!< No error */ +#define HAL_DMA_QUEUE_ERROR_BUSY (0x01U) /*!< Error busy */ +#define HAL_DMA_QUEUE_ERROR_EMPTY (0x02U) /*!< Error unallowed operation for empty queue */ +#define HAL_DMA_QUEUE_ERROR_UNSUPPORTED (0x03U) /*!< Error unsupported feature */ +#define HAL_DMA_QUEUE_ERROR_INVALIDTYPE (0x04U) /*!< Error incompatible node type or circular initialization + and queue circular types are incompatible */ +#define HAL_DMA_QUEUE_ERROR_OUTOFRANGE (0x05U) /*!< Error out of range node memory */ +#define HAL_DMA_QUEUE_ERROR_NOTFOUND (0x06U) /*!< Error node not found in queue */ +/** + * @} + */ + +/** @defgroup DMAEx_LinkedList_Mode DMAEx LinkedList Mode + * @brief DMAEx LinkedList Mode + * @{ + */ +#define DMA_LINKEDLIST_NORMAL DMA_LINKEDLIST /*!< Linear linked-list DMA channel transfer */ +#define DMA_LINKEDLIST_CIRCULAR (DMA_LINKEDLIST | (0x01U)) /*!< Circular linked-list DMA channel transfer */ +/** + * @} + */ + +/** @defgroup DMAEx_Data_Alignment DMAEx Data Alignment + * @brief DMAEx Data Alignment + * @{ + */ +#define DMA_DATA_RIGHTALIGN_ZEROPADDED 0x00000000U /*!< If source data width < destination data width + => Right aligned padded with 0 up to destination data + width */ +#define DMA_DATA_RIGHTALIGN_LEFTTRUNC 0x00000000U /*!< If source data width > destination data width + => Right aligned left Truncated down to destination + data width */ +#define DMA_DATA_RIGHTALIGN_SIGNEXT DMA_CTR1_PAM_0 /*!< If source data width < destination data width + => Right Aligned padded with sign extended up to + destination data width */ +#define DMA_DATA_LEFTALIGN_RIGHTTRUNC DMA_CTR1_PAM_0 /*!< If source data width > destination data width + => Left Aligned Right Truncated down to the + destination data width */ +#define DMA_DATA_PACK DMA_CTR1_PAM_1 /*!< If source data width < destination data width + => Packed at the destination data width */ +#define DMA_DATA_UNPACK DMA_CTR1_PAM_1 /*!< If source data width > destination data width + => Unpacked at the destination data width */ +/** + * @} + */ + +/** @defgroup DMAEx_Data_Exchange DMAEx Data Exchange + * @brief DMAEx Data Exchange + * @{ + */ +#define DMA_EXCHANGE_NONE 0x00000000U /*!< No data exchange */ +#define DMA_EXCHANGE_DEST_BYTE DMA_CTR1_DBX /*!< Destination Byte exchange when destination data width is > Byte */ +#define DMA_EXCHANGE_DEST_HALFWORD DMA_CTR1_DHX /*!< Destination Half-Word exchange when destination data width is > Half-Word */ +#define DMA_EXCHANGE_SRC_BYTE DMA_CTR1_SBX /*!< Source Byte endianness exchange when source data width is word */ +/** + * @} + */ + +/** @defgroup DMAEx_Trigger_Polarity DMAEx Trigger Polarity + * @brief DMAEx Trigger Polarity + * @{ + */ +#define DMA_TRIG_POLARITY_MASKED 0x00000000U /*!< No trigger of the selected DMA request. Masked trigger event */ +#define DMA_TRIG_POLARITY_RISING DMA_CTR2_TRIGPOL_0 /*!< Trigger of the selected DMA request on the rising edge of the selected trigger event input */ +#define DMA_TRIG_POLARITY_FALLING DMA_CTR2_TRIGPOL_1 /*!< Trigger of the selected DMA request on the falling edge of the selected trigger event input */ +/** + * @} + */ + +/** @defgroup DMAEx_Trigger_Mode DMAEx Trigger Mode + * @brief DMAEx Trigger Mode + * @{ + */ +#define DMA_TRIGM_BLOCK_TRANSFER 0x00000000U /*!< A block transfer is conditioned by (at least) one hit trigger */ +#define DMA_TRIGM_LLI_LINK_TRANSFER DMA_CTR2_TRIGM_1 /*!< A LLI link transfer is conditioned by (at least) one hit trigger */ +#define DMA_TRIGM_SINGLE_BURST_TRANSFER DMA_CTR2_TRIGM /*!< A single/burst transfer is conditioned by (at least) one hit trigger */ +/** + * @} + */ + +/** @defgroup DMAEx_Trigger_Selection DMAEx Trigger Selection + * @brief DMAEx Trigger Selection + * @{ + */ +/* GPDMA1 triggers */ +#define GPDMA1_TRIGGER_EXTI_LINE0 0U /*!< GPDMA1 HW Trigger signal is EXTI_LINE0 */ +#define GPDMA1_TRIGGER_EXTI_LINE1 1U /*!< GPDMA1 HW Trigger signal is EXTI_LINE1 */ +#define GPDMA1_TRIGGER_EXTI_LINE2 2U /*!< GPDMA1 HW Trigger signal is EXTI_LINE2 */ +#define GPDMA1_TRIGGER_EXTI_LINE3 3U /*!< GPDMA1 HW Trigger signal is EXTI_LINE3 */ +#define GPDMA1_TRIGGER_EXTI_LINE4 4U /*!< GPDMA1 HW Trigger signal is EXTI_LINE4 */ +#define GPDMA1_TRIGGER_EXTI_LINE5 5U /*!< GPDMA1 HW Trigger signal is EXTI_LINE5 */ +#define GPDMA1_TRIGGER_EXTI_LINE6 6U /*!< GPDMA1 HW Trigger signal is EXTI_LINE6 */ +#define GPDMA1_TRIGGER_EXTI_LINE7 7U /*!< GPDMA1 HW Trigger signal is EXTI_LINE7 */ +#define GPDMA1_TRIGGER_TAMP_TRG1 8U /*!< GPDMA1 HW Trigger signal is TAMP_TRG1 */ +#define GPDMA1_TRIGGER_TAMP_TRG2 9U /*!< GPDMA1 HW Trigger signal is TAMP_TRG2 */ +#define GPDMA1_TRIGGER_TAMP_TRG3 10U /*!< GPDMA1 HW Trigger signal is TAMP_TRG3 */ +#define GPDMA1_TRIGGER_LPTIM1_CH1 11U /*!< GPDMA1 HW Trigger signal is LPTIM1_CH1 */ +#define GPDMA1_TRIGGER_LPTIM1_CH2 12U /*!< GPDMA1 HW Trigger signal is LPTIM1_CH2 */ +#if defined (LPTIM2) +#define GPDMA1_TRIGGER_LPTIM2_CH1 13U /*!< GPDMA1 HW Trigger signal is LPTIM2_CH1 */ +#define GPDMA1_TRIGGER_LPTIM2_CH2 14U /*!< GPDMA1 HW Trigger signal is LPTIM2_CH2 */ +#endif /* LPTIM2 */ +#if defined (COMP1) +#define GPDMA1_TRIGGER_COMP1_OUT 15U /*!< GPDMA1 HW Trigger signal is COMP1_OUT */ +#endif /* COMP1 */ +#if defined (COMP2) +#define GPDMA1_TRIGGER_COMP2_OUT 16U /*!< GPDMA1 HW Trigger signal is COMP2_OUT */ +#endif /* COMP2 */ +#define GPDMA1_TRIGGER_RTC_ALRA_TRG 17U /*!< GPDMA1 HW Trigger signal is RTC_ALRA_TRG */ +#define GPDMA1_TRIGGER_RTC_ALRB_TRG 18U /*!< GPDMA1 HW Trigger signal is RTC_ALRB_TRG */ +#define GPDMA1_TRIGGER_RTC_WUT_TRG 19U /*!< GPDMA1 HW Trigger signal is RTC_WUT_TRG */ +#define GPDMA1_TRIGGER_GPDMA1_CH0_TCF 20U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH0_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH1_TCF 21U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH1_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH2_TCF 22U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH2_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH3_TCF 23U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH3_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH4_TCF 24U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH4_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH5_TCF 25U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH5_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH6_TCF 26U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH6_TCF */ +#define GPDMA1_TRIGGER_GPDMA1_CH7_TCF 27U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH7_TCF */ +#define GPDMA1_TRIGGER_TIM2_TRGO 28U /*!< GPDMA1 HW Trigger signal is TIM2_TRGO */ +#define GPDMA1_TRIGGER_ADC4_AWD1 29U /*!< GPDMA1 HW Trigger signal is ADC4_ADW1 */ +#if defined (TIM3) +#define GPDMA1_TRIGGER_TIM3_TRGO 30U /*!< GPDMA1 HW Trigger signal is TIM3_TRGO */ +#endif /* TIM3 */ +/** + * @} + */ + +/** @defgroup DMAEx_Node_Type DMAEx Node Type + * @brief DMAEx Node Type + * @{ + */ +#define DMA_GPDMA_LINEAR_NODE (DMA_CHANNEL_TYPE_GPDMA | DMA_CHANNEL_TYPE_LINEAR_ADDR) /*!< Defines the GPDMA linear addressing node type */ +/** + * @} + */ + +/** @defgroup DMAEx_Link_Allocated_Port DMAEx Linked-List Allocated Port + * @brief DMAEx Linked-List Allocated Port + * @{ + */ +#define DMA_LINK_ALLOCATED_PORT0 0x00000000U /*!< Link allocated port 0 */ +#define DMA_LINK_ALLOCATED_PORT1 DMA_CCR_LAP /*!< Link allocated port 1 */ +/** + * @} + */ + +/** @defgroup DMAEx_Link_Step_Mode DMAEx Link Step Mode + * @brief DMAEx Link Step Mode + * @{ + */ +#define DMA_LSM_FULL_EXECUTION 0x00000000U /*!< Channel is executed for the full linked-list */ +#define DMA_LSM_1LINK_EXECUTION DMA_CCR_LSM /*!< Channel is executed once for the current LLI */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions ------------------------------------------------------------------------------------------------*/ +/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions + * @brief DMAEx Exported functions + * @{ + */ + +/** @defgroup DMAEx_Exported_Functions_Group1 Linked-List Initialization and De-Initialization Functions + * @brief Linked-List Initialization and De-Initialization Functions + * @{ + */ +HAL_StatusTypeDef HAL_DMAEx_List_Init(DMA_HandleTypeDef *const hdma); +HAL_StatusTypeDef HAL_DMAEx_List_DeInit(DMA_HandleTypeDef *const hdma); +/** + * @} + */ + +/** @defgroup DMAEx_Exported_Functions_Group2 Linked-List IO Operation Functions + * @brief Linked-List IO Operation Functions + * @{ + */ +HAL_StatusTypeDef HAL_DMAEx_List_Start(DMA_HandleTypeDef *const hdma); +HAL_StatusTypeDef HAL_DMAEx_List_Start_IT(DMA_HandleTypeDef *const hdma); +/** + * @} + */ + +/** @defgroup DMAEx_Exported_Functions_Group3 Linked-List Management Functions + * @brief Linked-List Management Functions + * @{ + */ +HAL_StatusTypeDef HAL_DMAEx_List_BuildNode(DMA_NodeConfTypeDef const *const pNodeConfig, + DMA_NodeTypeDef *const pNode); +HAL_StatusTypeDef HAL_DMAEx_List_GetNodeConfig(DMA_NodeConfTypeDef *const pNodeConfig, + DMA_NodeTypeDef const *const pNode); + +HAL_StatusTypeDef HAL_DMAEx_List_InsertNode(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pPrevNode, + DMA_NodeTypeDef *const pNewNode); +HAL_StatusTypeDef HAL_DMAEx_List_InsertNode_Head(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pNewNode); +HAL_StatusTypeDef HAL_DMAEx_List_InsertNode_Tail(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pNewNode); + +HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pNode); +HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode_Head(DMA_QListTypeDef *const pQList); +HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode_Tail(DMA_QListTypeDef *const pQList); + +HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pOldNode, + DMA_NodeTypeDef *const pNewNode); +HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode_Head(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pNewNode); +HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode_Tail(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pNewNode); + +HAL_StatusTypeDef HAL_DMAEx_List_ResetQ(DMA_QListTypeDef *const pQList); + +HAL_StatusTypeDef HAL_DMAEx_List_InsertQ(DMA_QListTypeDef *const pSrcQList, + DMA_NodeTypeDef const *const pPrevNode, + DMA_QListTypeDef *const pDestQList); +HAL_StatusTypeDef HAL_DMAEx_List_InsertQ_Head(DMA_QListTypeDef *const pSrcQList, + DMA_QListTypeDef *const pDestQList); +HAL_StatusTypeDef HAL_DMAEx_List_InsertQ_Tail(DMA_QListTypeDef *const pSrcQList, + DMA_QListTypeDef *const pDestQList); + +HAL_StatusTypeDef HAL_DMAEx_List_SetCircularModeConfig(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pFirstCircularNode); +HAL_StatusTypeDef HAL_DMAEx_List_SetCircularMode(DMA_QListTypeDef *const pQList); +HAL_StatusTypeDef HAL_DMAEx_List_ClearCircularMode(DMA_QListTypeDef *const pQList); + +HAL_StatusTypeDef HAL_DMAEx_List_ConvertQToDynamic(DMA_QListTypeDef *const pQList); +HAL_StatusTypeDef HAL_DMAEx_List_ConvertQToStatic(DMA_QListTypeDef *const pQList); + +HAL_StatusTypeDef HAL_DMAEx_List_LinkQ(DMA_HandleTypeDef *const hdma, + DMA_QListTypeDef *const pQList); +HAL_StatusTypeDef HAL_DMAEx_List_UnLinkQ(DMA_HandleTypeDef *const hdma); +/** + * @} + */ + +/** @defgroup DMAEx_Exported_Functions_Group4 Data Handling, Repeated Block and Trigger Configuration Functions + * @brief Data Handling, Repeated Block and Trigger Configuration Functions + * @{ + */ +HAL_StatusTypeDef HAL_DMAEx_ConfigDataHandling(DMA_HandleTypeDef *const hdma, + DMA_DataHandlingConfTypeDef const *const pConfigDataHandling); +HAL_StatusTypeDef HAL_DMAEx_ConfigTrigger(DMA_HandleTypeDef *const hdma, + DMA_TriggerConfTypeDef const *const pConfigTrigger); +/** + * @} + */ + +/** @defgroup DMAEx_Exported_Functions_Group5 Suspend and Resume Operation Functions + * @brief Suspend and Resume Operation Functions + * @{ + */ +HAL_StatusTypeDef HAL_DMAEx_Suspend(DMA_HandleTypeDef *const hdma); +HAL_StatusTypeDef HAL_DMAEx_Suspend_IT(DMA_HandleTypeDef *const hdma); +HAL_StatusTypeDef HAL_DMAEx_Resume(DMA_HandleTypeDef *const hdma); +/** + * @} + */ + +/** @defgroup DMAEx_Exported_Functions_Group6 FIFO Status Function + * @brief FIFO Status Function + * @{ + */ +uint32_t HAL_DMAEx_GetFifoLevel(DMA_HandleTypeDef const *const hdma); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -----------------------------------------------------------------------------------------------------*/ +/** @defgroup DMAEx_Private_Types DMAEx Private Types + * @brief DMAEx Private Types + * @{ + */ + +/** + * @brief DMA Node in Queue Information Structure Definition. + */ +typedef struct +{ + uint32_t cllr_offset; /* CLLR register offset */ + + uint32_t previousnode_addr; /* Previous node address */ + + uint32_t currentnode_pos; /* Current node position */ + + uint32_t currentnode_addr; /* Current node address */ + + uint32_t nextnode_addr; /* Next node address */ + +} DMA_NodeInQInfoTypeDef; +/** + * @} + */ + +/* Private constants -------------------------------------------------------------------------------------------------*/ +/** @defgroup DMAEx_Private_Constants DMAEx Private Constants + * @brief DMAEx Private Constants + * @{ + */ +#define DMA_LINKEDLIST (0x0080U) /* DMA channel linked-list mode */ + +#define DMA_CHANNEL_TYPE_LINEAR_ADDR (0x0001U) /* DMA channel linear addressing mode */ +#define DMA_CHANNEL_TYPE_GPDMA (0x0020U) /* GPDMA channel node */ + +#define NODE_TYPE_MASK (0x00FFU) /* DMA channel node type */ +#define NODE_CLLR_IDX (0x0700U) /* DMA channel node CLLR index mask */ +#define NODE_CLLR_IDX_POS (0x0008U) /* DMA channel node CLLR index position */ + +#define NODE_MAXIMUM_SIZE (0x0006U) /* Amount of registers of the node */ + +#define NODE_STATIC_FORMAT (0x0000U) /* DMA channel node static format */ +#define NODE_DYNAMIC_FORMAT (0x0001U) /* DMA channel node dynamic format */ + +#define UPDATE_CLLR_POSITION (0x0000U) /* DMA channel update CLLR position */ +#define UPDATE_CLLR_VALUE (0x0001U) /* DMA channel update CLLR value */ + +#define LASTNODE_ISNOT_CIRCULAR (0x0000U) /* Last node is not first circular node */ +#define LASTNODE_IS_CIRCULAR (0x0001U) /* Last node is first circular node */ + +#define QUEUE_TYPE_STATIC (0x0000U) /* DMA channel static queue */ +#define QUEUE_TYPE_DYNAMIC (0x0001U) /* DMA channel dynamic queue */ + +#define NODE_CTR1_DEFAULT_OFFSET (0x0000U) /* CTR1 default offset */ +#define NODE_CTR2_DEFAULT_OFFSET (0x0001U) /* CTR2 default offset */ +#define NODE_CBR1_DEFAULT_OFFSET (0x0002U) /* CBR1 default offset */ +#define NODE_CSAR_DEFAULT_OFFSET (0x0003U) /* CSAR default offset */ +#define NODE_CDAR_DEFAULT_OFFSET (0x0004U) /* CDAR default offset */ +#define NODE_CLLR_LINEAR_DEFAULT_OFFSET (0x0005U) /* CLLR linear addressing default offset */ + +#define DMA_BURST_ADDR_OFFSET_MIN (-8192L) /* DMA burst minimum address offset */ +#define DMA_BURST_ADDR_OFFSET_MAX (8192L) /* DMA burst maximum address offset */ +#define DMA_BLOCK_ADDR_OFFSET_MIN (-65536L) /* DMA block minimum address offset */ +#define DMA_BLOCK_ADDR_OFFSET_MAX (65536L) /* DMA block maximum address offset */ +/** + * @} + */ + +/* Private macros ----------------------------------------------------------------------------------------------------*/ +/** @defgroup DMAEx_Private_Macros DMAEx Private Macros + * @brief DMAEx Private Macros + * @{ + */ +#define IS_DMA_DATA_ALIGNMENT(ALIGNMENT) \ + (((ALIGNMENT) == DMA_DATA_RIGHTALIGN_ZEROPADDED) || \ + ((ALIGNMENT) == DMA_DATA_RIGHTALIGN_SIGNEXT) || \ + ((ALIGNMENT) == DMA_DATA_PACK)) + +#define IS_DMA_DATA_EXCHANGE(EXCHANGE) \ + (((EXCHANGE) & (~(DMA_EXCHANGE_SRC_BYTE | DMA_EXCHANGE_DEST_BYTE | DMA_EXCHANGE_DEST_HALFWORD))) == 0U) + +#define IS_DMA_REPEAT_COUNT(COUNT) \ + (((COUNT) > 0U) && ((COUNT) <= (DMA_CBR1_BRC >> DMA_CBR1_BRC_Pos))) + +#define IS_DMA_BURST_ADDR_OFFSET(BURST_ADDR_OFFSET) \ + (((BURST_ADDR_OFFSET) > DMA_BURST_ADDR_OFFSET_MIN) && \ + ((BURST_ADDR_OFFSET) < DMA_BURST_ADDR_OFFSET_MAX)) + +#define IS_DMA_BLOCK_ADDR_OFFSET(BLOCK_ADDR_OFFSET) \ + (((BLOCK_ADDR_OFFSET) > DMA_BLOCK_ADDR_OFFSET_MIN) && \ + ((BLOCK_ADDR_OFFSET) < DMA_BLOCK_ADDR_OFFSET_MAX)) + +#define IS_DMA_LINK_ALLOCATED_PORT(LINK_ALLOCATED_PORT) \ + (((LINK_ALLOCATED_PORT) & (~(DMA_CCR_LAP))) == 0U) + +#define IS_DMA_LINK_STEP_MODE(MODE) \ + (((MODE) == DMA_LSM_FULL_EXECUTION) || \ + ((MODE) == DMA_LSM_1LINK_EXECUTION)) + +#define IS_DMA_TRIGGER_MODE(MODE) \ + (((MODE) == DMA_TRIGM_BLOCK_TRANSFER) || \ + ((MODE) == DMA_TRIGM_LLI_LINK_TRANSFER) || \ + ((MODE) == DMA_TRIGM_SINGLE_BURST_TRANSFER)) + +#define IS_DMA_TCEM_LINKEDLIST_EVENT_MODE(MODE) \ + (((MODE) == DMA_TCEM_BLOCK_TRANSFER) || \ + ((MODE) == DMA_TCEM_EACH_LL_ITEM_TRANSFER) || \ + ((MODE) == DMA_TCEM_LAST_LL_ITEM_TRANSFER)) + +#define IS_DMA_LINKEDLIST_MODE(MODE) \ + (((MODE) == DMA_LINKEDLIST_NORMAL) || \ + ((MODE) == DMA_LINKEDLIST_CIRCULAR)) + +#define IS_DMA_TRIGGER_POLARITY(POLARITY) \ + (((POLARITY) == DMA_TRIG_POLARITY_MASKED) || \ + ((POLARITY) == DMA_TRIG_POLARITY_RISING) || \ + ((POLARITY) == DMA_TRIG_POLARITY_FALLING)) + +#if defined (TIM3) +#define IS_DMA_TRIGGER_SELECTION(TRIGGER) \ + ((TRIGGER) <= GPDMA1_TRIGGER_TIM3_TRGO) +#else +#define IS_DMA_TRIGGER_SELECTION(TRIGGER) \ + ((TRIGGER) <= GPDMA1_TRIGGER_ADC4_AWD1) +#endif /* TIM3 */ + +#define IS_DMA_NODE_TYPE(TYPE) \ + ((TYPE) == DMA_GPDMA_LINEAR_NODE) +/** + * @} + */ + + +/* Private functions -------------------------------------------------------------------------------------------------*/ +/** @defgroup DMAEx_Private_Functions DMAEx Private Functions + * @brief DMAEx Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STM32WBAxx_HAL_DMA_EX_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_exti.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_exti.h new file mode 100644 index 0000000000..4f57a58a77 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_exti.h @@ -0,0 +1,345 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_exti.h + * @author MCD Application Team + * @brief Header file of EXTI HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_HAL_EXTI_H +#define STM32WBAxx_HAL_EXTI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal_def.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @defgroup EXTI EXTI + * @brief EXTI HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup EXTI_Exported_Types EXTI Exported Types + * @{ + */ +typedef enum +{ + HAL_EXTI_COMMON_CB_ID = 0x00U, + HAL_EXTI_RISING_CB_ID = 0x01U, + HAL_EXTI_FALLING_CB_ID = 0x02U, +} EXTI_CallbackIDTypeDef; + + +/** + * @brief EXTI Handle structure definition + */ +typedef struct +{ + uint32_t Line; /*!< Exti line number */ + void (* RisingCallback)(void); /*!< Exti rising callback */ + void (* FallingCallback)(void); /*!< Exti falling callback */ +} EXTI_HandleTypeDef; + +/** + * @brief EXTI Configuration structure definition + */ +typedef struct +{ + uint32_t Line; /*!< The Exti line to be configured. This parameter + can be a value of @ref EXTI_Line */ + uint32_t Mode; /*!< The Exit Mode to be configured for a core. + This parameter can be a combination of @ref EXTI_Mode */ + uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter + can be a value of @ref EXTI_Trigger */ + uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured. + This parameter is only possible for line 0 to 15. It + can be a value of @ref EXTI_GPIOSel */ +} EXTI_ConfigTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Constants EXTI Exported Constants + * @{ + */ + +/** @defgroup EXTI_Line EXTI Line + * @{ + */ +#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | 0x00U) +#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | 0x01U) +#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | 0x02U) +#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | 0x03U) +#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | 0x04U) +#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | 0x05U) +#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | 0x06U) +#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | 0x07U) +#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | 0x08U) +#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | 0x09U) +#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | 0x0AU) +#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | 0x0BU) +#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | 0x0CU) +#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | 0x0DU) +#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | 0x0EU) +#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | 0x0FU) +#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | 0x10U) +#if defined(COMP1) +#define EXTI_LINE_17 (EXTI_CONFIG | EXTI_REG1 | 0x11U) +#endif /* COMP1 */ +#if defined(COMP2) +#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | 0x12U) +#endif /* COMP2 */ +/** + * @} + */ + +/** @defgroup EXTI_Mode EXTI Mode + * @{ + */ +#define EXTI_MODE_NONE 0x00000000U +#define EXTI_MODE_INTERRUPT 0x00000001U +#define EXTI_MODE_EVENT 0x00000002U +/** + * @} + */ + +/** @defgroup EXTI_Trigger EXTI Trigger + * @{ + */ +#define EXTI_TRIGGER_NONE 0x00000000U +#define EXTI_TRIGGER_RISING 0x00000001U +#define EXTI_TRIGGER_FALLING 0x00000002U +#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) +/** + * @} + */ + +/** @defgroup EXTI_GPIOSel EXTI GPIOSel + * @brief + * @{ + */ +#define EXTI_GPIOA 0x00000000U +#define EXTI_GPIOB 0x00000001U +#define EXTI_GPIOC 0x00000002U +#define EXTI_GPIOH 0x00000007U +/** + * @} + */ + +#if defined(EXTI_SECCFGR1_SEC0) +/** @defgroup EXTI_Line_attributes EXTI line attributes + * @brief EXTI line secure or non-secure and privileged or non-privileged attributes + * @note secure and non-secure attributes are only available from secure state when the system + * implement the security (TZEN=1) + * @{ + */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define EXTI_LINE_SEC (EXTI_LINE_ATTR_SEC_MASK | 0x00000001U) /*!< Secure line attribute */ +#define EXTI_LINE_NSEC (EXTI_LINE_ATTR_SEC_MASK | 0x00000000U) /*!< Non-secure line attribute */ +#endif /* __ARM_FEATURE_CMSE */ +#define EXTI_LINE_PRIV (EXTI_LINE_ATTR_PRIV_MASK | 0x00000002U) /*!< Privileged line attribute */ +#define EXTI_LINE_NPRIV (EXTI_LINE_ATTR_PRIV_MASK | 0x00000000U) /*!< Non-privileged line attribute */ +/** + * @} + */ +#endif /* #if defined(EXTI_SECCFGR1_SEC0) */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Private constants --------------------------------------------------------*/ +/** @defgroup EXTI_Private_Constants EXTI Private Constants + * @{ + */ +/** + * @brief EXTI Line property definition + */ +#define EXTI_PROPERTY_SHIFT 24U +#define EXTI_DIRECT (0x01U << EXTI_PROPERTY_SHIFT) +#define EXTI_CONFIG (0x02U << EXTI_PROPERTY_SHIFT) +#define EXTI_GPIO ((0x04U << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG) +#define EXTI_RESERVED (0x08U << EXTI_PROPERTY_SHIFT) +#define EXTI_PROPERTY_MASK (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO) + +/** + * @brief EXTI Register and bit usage + */ +#define EXTI_REG_SHIFT 16U +#define EXTI_REG1 (0x00U << EXTI_REG_SHIFT) +#define EXTI_REG2 (0x01U << EXTI_REG_SHIFT) +#define EXTI_REG_MASK (EXTI_REG1 | EXTI_REG2) +#define EXTI_PIN_MASK 0x0000001FU + +/** + * @brief EXTI Mask for interrupt & event mode + */ +#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT) + +/** + * @brief EXTI Mask for trigger possibilities + */ +#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) + +/** + * @brief EXTI Line number + */ +#define EXTI_LINE_NB 18U + +#if defined(EXTI_SECCFGR1_SEC0) +/** + * @brief EXTI Mask for secure & privilege attributes + */ +#define EXTI_LINE_ATTR_SEC_MASK 0x100U +#define EXTI_LINE_ATTR_PRIV_MASK 0x200U +/** + * @} + */ +#endif /* #if defined(EXTI_SECCFGR1_SEC0) */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup EXTI_Private_Macros EXTI Private Macros + * @{ + */ +#define IS_EXTI_LINE(__LINE__) ((((__LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00U) && \ + ((((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \ + (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \ + (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \ + (((__LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) < \ + (((EXTI_LINE_NB / 32U) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32U)))) + +#define IS_EXTI_MODE(__LINE__) ((((__LINE__) & EXTI_MODE_MASK) != 0x00U) && \ + (((__LINE__) & ~EXTI_MODE_MASK) == 0x00U)) + +#define IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00U) + +#define IS_EXTI_PENDING_EDGE(__LINE__) (((__LINE__) == EXTI_TRIGGER_RISING) || \ + ((__LINE__) == EXTI_TRIGGER_FALLING)) + +#define IS_EXTI_CONFIG_LINE(__LINE__) (((__LINE__) & EXTI_CONFIG) != 0x00U) + +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOH)) + +#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16U) + +#if defined(EXTI_SECCFGR1_SEC0) +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +#define IS_EXTI_LINE_ATTRIBUTES(__ATTRIBUTES__) (((((__ATTRIBUTES__) & EXTI_LINE_SEC) == EXTI_LINE_SEC) || \ + (((__ATTRIBUTES__) & EXTI_LINE_NSEC) == EXTI_LINE_NSEC) || \ + (((__ATTRIBUTES__) & EXTI_LINE_PRIV) == EXTI_LINE_PRIV) || \ + (((__ATTRIBUTES__) & EXTI_LINE_NPRIV) == EXTI_LINE_NPRIV)) && \ + (((__ATTRIBUTES__) & ~(EXTI_LINE_SEC|EXTI_LINE_NSEC|EXTI_LINE_PRIV|EXTI_LINE_NPRIV)) == 0U)) + +#else + +#define IS_EXTI_LINE_ATTRIBUTES(__ATTRIBUTES__) (((((__ATTRIBUTES__) & EXTI_LINE_PRIV) == EXTI_LINE_PRIV) || \ + (((__ATTRIBUTES__) & EXTI_LINE_NPRIV) == EXTI_LINE_NPRIV)) && \ + (((__ATTRIBUTES__) & ~(EXTI_LINE_PRIV|EXTI_LINE_NPRIV)) == 0U)) + +#endif /* __ARM_FEATURE_CMSE */ +#endif /* #if defined(EXTI_SECCFGR1_SEC0) */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Functions EXTI Exported Functions + * @brief EXTI Exported Functions + * @{ + */ + +/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions + * @brief Configuration functions + * @{ + */ +/* Configuration functions ****************************************************/ +HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); +HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); +HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(const EXTI_HandleTypeDef *hexti); +HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)); +HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine); +/** + * @} + */ + +/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * @{ + */ +/* IO operation functions *****************************************************/ +void HAL_EXTI_IRQHandler(const EXTI_HandleTypeDef *hexti); +uint32_t HAL_EXTI_GetPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge); +void HAL_EXTI_ClearPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge); +void HAL_EXTI_GenerateSWI(const EXTI_HandleTypeDef *hexti); + +/** + * @} + */ + +/** @addtogroup EXTI_Exported_Functions_Group3 EXTI line attributes management functions + * @{ + */ + +#if defined(EXTI_SECCFGR1_SEC0) +/* EXTI line attributes management functions **********************************/ +void HAL_EXTI_ConfigLineAttributes(uint32_t ExtiLine, uint32_t LineAttributes); +HAL_StatusTypeDef HAL_EXTI_GetConfigLineAttributes(uint32_t ExtiLine, uint32_t *pLineAttributes); +#endif /* #if defined(EXTI_SECCFGR1_SEC0) */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +void HAL_EXTI_LockAttributes(void); +uint32_t HAL_EXTI_GetLockAttributes(void); +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WBAxx_HAL_EXTI_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_flash.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_flash.h new file mode 100644 index 0000000000..4bba62cdc0 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_flash.h @@ -0,0 +1,1065 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_flash.h + * @author MCD Application Team + * @brief Header file of FLASH HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_HAL_FLASH_H +#define STM32WBAxx_HAL_FLASH_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal_def.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @addtogroup FLASH + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Types FLASH Exported Types + * @{ + */ + +/** + * @brief FLASH Erase structure definition + */ +typedef struct +{ + uint32_t TypeErase; /*!< Mass erase or page erase. + This parameter can be a value of @ref FLASH_Type_Erase */ + uint32_t Page; /*!< Initial Flash page to erase when page erase is enabled + This parameter must be a value between 0 and (max number of pages - 1) */ + uint32_t NbPages; /*!< Number of pages to be erased. + This parameter must be a value between 1 and (max number of pages - value of initial page)*/ +} FLASH_EraseInitTypeDef; + +/** + * @brief FLASH Option Bytes Program structure definition + */ +typedef struct +{ + uint32_t OptionType; /*!< Option byte to be configured. + This parameter can be a combination of the values of @ref FLASH_OB_Type */ + uint32_t WRPArea; /*!< Write protection area to be programmed (used for OPTIONBYTE_WRP). + Only one WRP area could be programmed at the same time. + This parameter can be value of @ref FLASH_OB_WRP_Area */ + uint32_t WRPStartOffset; /*!< Write protection start offset (used for OPTIONBYTE_WRP). + This parameter must be a value between 0 and (max number of pages - 1) */ + uint32_t WRPEndOffset; /*!< Write protection end offset (used for OPTIONBYTE_WRP). + This parameter must be a value between WRPStartOffset and (max number of pages - 1) */ + FunctionalState WRPLock; /*!< Write protection lock (used for OPTIONBYTE_WRP). + This parameter can be set to ENABLE or DISABLE */ + uint32_t RDPLevel; /*!< Set the read protection level (used for OPTIONBYTE_RDP). + This parameter can be a value of @ref FLASH_OB_Read_Protection */ + uint32_t USERType; /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER). + This parameter can be a combination of @ref FLASH_OB_USER_Type */ + uint32_t USERConfig; /*!< Value of the user option byte (used for OPTIONBYTE_USER). + This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEVEL, + @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY, + @ref FLASH_OB_USER_SRAM1_RST, @ref FLASH_OB_USER_IWDG_SW, + @ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY, + @ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_SRAM2_PAR, + @ref FLASH_OB_USER_SRAM2_RST, @ref FLASH_OB_USER_nSWBOOT0, + @ref FLASH_OB_USER_nBOOT0 and @ref FLASH_OB_USER_TZEN */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + uint32_t WMSecConfig; /*!< Configuration of the Watermark-based Secure Area (used for OPTIONBYTE_WMSEC). + This parameter must be a value of @ref FLASH_OB_WMSEC */ + uint32_t WMSecStartPage; /*!< Start page of secure area (used for OPTIONBYTE_WMSEC). + This parameter must be a value between 0 and (max number of pages in the bank - 1) */ + uint32_t WMSecEndPage; /*!< End page of secure area (used for OPTIONBYTE_WMSEC). + This parameter must be a value between WMSecStartPage and (max number of pages in the bank - 1) */ + uint32_t WMHDPEndPage; /*!< End page of the secure hide protection (used for OPTIONBYTE_WMSEC). + This parameter must be a value between WMSecStartPage and WMSecEndPage */ + uint32_t BootLock; /*!< Configuration of the boot lock (used for OPTIONBYTE_BOOT_LOCK). + This parameter must be a value of @ref FLASH_OB_BOOT_LOCK */ +#endif /* __ARM_FEATURE_CMSE */ + uint32_t BootAddrConfig; /*!< Configuration of the Boot address (used for OPTIONBYTE_BOOTADDR). + This parameter must be a value of @ref FLASH_OB_BOOTADDR */ + uint32_t BootAddr; /*!< Boot address (used for OPTIONBYTE_BOOTADDR). + This parameter must be a value between 0x0 and 0xFFFFFF00 */ + uint32_t RDPKeyType; /*!< Configuration of the RDP OEM keys (used for OPTIONBYTE_RDPKEY). + This parameter can be a value of @ref FLASH_OB_RDP_Key_Type */ + uint32_t RDPKey1; /*!< Value of the RDP OEM key 1 (used for OPTIONBYTE_RDPKEY) */ + uint32_t RDPKey2; /*!< Value of the RDP OEM key 2 (used for OPTIONBYTE_RDPKEY) */ +} FLASH_OBProgramInitTypeDef; + +/** + * @brief FLASH handle Structure definition + */ +typedef struct +{ + HAL_LockTypeDef Lock; /*!< FLASH locking object */ + uint32_t ErrorCode; /*!< FLASH error code */ + uint32_t ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */ + uint32_t Address; /*!< Internal variable to save address selected for program in IT context */ + uint32_t Page; /*!< Internal variable to define the current page which is erasing in IT context */ + uint32_t NbPagesToErase; /*!< Internal variable to save the remaining pages to erase in IT context */ +} FLASH_ProcessTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Constants FLASH Exported Constants + * @{ + */ + +/** @defgroup FLASH_Flags FLASH Flags Definition + * @{ + */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define FLASH_FLAG_EOP FLASH_SECSR_EOP /*!< FLASH End of operation flag */ +#define FLASH_FLAG_OPERR FLASH_SECSR_OPERR /*!< FLASH Operation error flag */ +#define FLASH_FLAG_PROGERR FLASH_SECSR_PROGERR /*!< FLASH Programming error flag */ +#define FLASH_FLAG_WRPERR FLASH_SECSR_WRPERR /*!< FLASH Write protection error flag */ +#define FLASH_FLAG_PGAERR FLASH_SECSR_PGAERR /*!< FLASH Programming alignment error flag */ +#define FLASH_FLAG_SIZERR FLASH_SECSR_SIZERR /*!< FLASH Size error flag */ +#define FLASH_FLAG_PGSERR FLASH_SECSR_PGSERR /*!< FLASH Programming sequence error flag */ +#define FLASH_FLAG_OPTWERR FLASH_NSSR_OPTWERR /*!< FLASH Option modification error flag */ +#define FLASH_FLAG_BSY FLASH_SECSR_BSY /*!< FLASH Busy flag */ +#define FLASH_FLAG_WDW FLASH_SECSR_WDW /*!< FLASH Wait Data to Write flag */ +#define FLASH_FLAG_ECCC FLASH_ECCR_ECCC /*!< FLASH ECC correction */ +#define FLASH_FLAG_ECCD FLASH_ECCR_ECCD /*!< FLASH ECC detection */ + +#define FLASH_FLAG_SR_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \ + FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | FLASH_FLAG_PGSERR) /*!< Flash all flags from Status Register */ +#define FLASH_FLAG_ECCR_ERRORS (FLASH_FLAG_ECCD | FLASH_FLAG_ECCC) /*!< Flash all flags from ECC Register */ +#define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_SR_ERRORS | FLASH_FLAG_OPTWERR | FLASH_FLAG_ECCR_ERRORS) /*!< Flash all flags */ +#else +#define FLASH_FLAG_EOP FLASH_NSSR_EOP /*!< FLASH End of operation flag */ +#define FLASH_FLAG_OPERR FLASH_NSSR_OPERR /*!< FLASH Operation error flag */ +#define FLASH_FLAG_PROGERR FLASH_NSSR_PROGERR /*!< FLASH Programming error flag */ +#define FLASH_FLAG_WRPERR FLASH_NSSR_WRPERR /*!< FLASH Write protection error flag */ +#define FLASH_FLAG_PGAERR FLASH_NSSR_PGAERR /*!< FLASH Programming alignment error flag */ +#define FLASH_FLAG_SIZERR FLASH_NSSR_SIZERR /*!< FLASH Size error flag */ +#define FLASH_FLAG_PGSERR FLASH_NSSR_PGSERR /*!< FLASH Programming sequence error flag */ +#define FLASH_FLAG_OPTWERR FLASH_NSSR_OPTWERR /*!< FLASH Option modification error flag */ +#define FLASH_FLAG_BSY FLASH_NSSR_BSY /*!< FLASH Busy flag */ +#define FLASH_FLAG_WDW FLASH_NSSR_WDW /*!< FLASH Wait Data to Write flag */ +#define FLASH_FLAG_OEM1LOCK FLASH_NSSR_OEM1LOCK /*!< FLASH OEM1 key RDP lock flag */ +#define FLASH_FLAG_OEM2LOCK FLASH_NSSR_OEM2LOCK /*!< FLASH OEM2 key RDP lock flag */ +#define FLASH_FLAG_PD FLASH_NSSR_PD /*!< FLASH in power-down lock flag */ +#define FLASH_FLAG_ECCC FLASH_ECCR_ECCC /*!< FLASH ECC correction */ +#define FLASH_FLAG_ECCD FLASH_ECCR_ECCD /*!< FLASH ECC detection */ + +#define FLASH_FLAG_SR_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \ + FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | FLASH_FLAG_PGSERR | \ + FLASH_FLAG_OPTWERR) /*!< Flash all flags from Status Register */ +#define FLASH_FLAG_ECCR_ERRORS (FLASH_FLAG_ECCD | FLASH_FLAG_ECCC) /*!< Flash all flags from ECC Register */ +#define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_SR_ERRORS | FLASH_FLAG_ECCR_ERRORS) /*!< Flash all flags */ +#endif /* __ARM_FEATURE_CMSE */ +/** + * @} + */ + +/** @defgroup FLASH_Interrupt_definition FLASH Interrupts Definition + * @brief FLASH Interrupt definition + * @{ + */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define FLASH_IT_EOP FLASH_SECCR1_EOPIE /*!< End of FLASH Operation Interrupt source */ +#define FLASH_IT_OPERR FLASH_SECCR1_ERRIE /*!< Error Interrupt source */ +#define FLASH_IT_ECCC (FLASH_ECCR_ECCIE >> FLASH_ECCR_ECCIE_Pos) /*!< ECC Correction Interrupt source */ +#else +#define FLASH_IT_EOP FLASH_NSCR1_EOPIE /*!< End of FLASH Operation Interrupt source */ +#define FLASH_IT_OPERR FLASH_NSCR1_ERRIE /*!< Error Interrupt source */ +#define FLASH_IT_ECCC (FLASH_ECCR_ECCIE >> FLASH_ECCR_ECCIE_Pos) /*!< ECC Correction Interrupt source */ +#endif /* __ARM_FEATURE_CMSE */ +/** + * @} + */ + +/** @defgroup FLASH_Error FLASH Error + * @{ + */ +#define HAL_FLASH_ERROR_NONE 0x00000000U /*!< Flash no error */ +#define HAL_FLASH_ERROR_OP FLASH_FLAG_OPERR /*!< Flash operation error */ +#define HAL_FLASH_ERROR_PROG FLASH_FLAG_PROGERR /*!< Flash programming error */ +#define HAL_FLASH_ERROR_WRP FLASH_FLAG_WRPERR /*!< Flash write protection error */ +#define HAL_FLASH_ERROR_PGA FLASH_FLAG_PGAERR /*!< Flash programming alignment error */ +#define HAL_FLASH_ERROR_SIZ FLASH_FLAG_SIZERR /*!< Flash size error */ +#define HAL_FLASH_ERROR_PGS FLASH_FLAG_PGSERR /*!< Flash programming sequence error */ +#define HAL_FLASH_ERROR_OPTW FLASH_FLAG_OPTWERR /*!< Flash option modification error */ +#define HAL_FLASH_ERROR_ECCC FLASH_FLAG_ECCC /*!< Flash ECC correction error */ +#define HAL_FLASH_ERROR_ECCD FLASH_FLAG_ECCD /*!< Flash ECC detection error */ +/** + * @} + */ + +/** @defgroup FLASH_Type_Erase FLASH Erase Type + * @{ + */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define FLASH_TYPEERASE_PAGES FLASH_SECCR1_PER /*!< Secure pages erase activation */ +#define FLASH_TYPEERASE_PAGES_NS (FLASH_NSCR1_PER | FLASH_NON_SECURE_MASK) /*!< Non-secure pages erase activation */ +#define FLASH_TYPEERASE_MASSERASE FLASH_SECCR1_MER /*!< Secure flash mass erase activation */ +#define FLASH_TYPEERASE_MASSERASE_NS (FLASH_NSCR1_MER | FLASH_NON_SECURE_MASK) /*!< Non-secure flash mass erase activation */ +#else +#define FLASH_TYPEERASE_PAGES FLASH_NSCR1_PER /*!< Pages erase activation */ +#define FLASH_TYPEERASE_MASSERASE FLASH_NSCR1_MER /*!< Flash mass erase activation */ +#endif /* __ARM_FEATURE_CMSE */ +/** + * @} + */ + +/** @defgroup FLASH_Banks FLASH Banks + * @{ + */ +#define FLASH_BANK_1 FLASH_NSCR1_MER /*!< Bank 1 */ +#define FLASH_BANK_BOTH FLASH_BANK_1 /*!< Bank 1 */ +/** + * @} + */ + +/** @defgroup FLASH_TYPE_PROGRAM FLASH Program Type + * @{ + */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define FLASH_TYPEPROGRAM_QUADWORD FLASH_SECCR1_PG /*!< Program a quad-word (128-bit) at a specified secure address */ +#define FLASH_TYPEPROGRAM_QUADWORD_NS (FLASH_NSCR1_PG | FLASH_NON_SECURE_MASK) /*!< Program a quad-word (128-bit) at a specified non-secure address */ +#define FLASH_TYPEPROGRAM_BURST (FLASH_SECCR1_PG | FLASH_SECCR1_BWR) /*!< Program a burst (8xquad-word) at a specified secure address */ +#define FLASH_TYPEPROGRAM_BURST_NS (FLASH_NSCR1_PG | FLASH_NSCR1_BWR | FLASH_NON_SECURE_MASK) /*!< Program a burst (8xquad-word) at a specified non-secure address */ +#else +#define FLASH_TYPEPROGRAM_QUADWORD FLASH_NSCR1_PG /*!ACR, FLASH_ACR_LATENCY, (__LATENCY__))) + +/** + * @brief Get the FLASH Latency. + * @retval FLASH Latency + * Returned value can be one of the following values : + * @arg @ref FLASH_LATENCY_0 FLASH Zero wait state + * @arg @ref FLASH_LATENCY_1 FLASH One wait state + * @arg @ref FLASH_LATENCY_2 FLASH Two wait states + * @arg @ref FLASH_LATENCY_3 FLASH Three wait states + * @arg @ref FLASH_LATENCY_4 FLASH Four wait states + * @arg @ref FLASH_LATENCY_5 FLASH Five wait states + * @arg @ref FLASH_LATENCY_6 FLASH Six wait states + * @arg @ref FLASH_LATENCY_7 FLASH Seven wait states + * @arg @ref FLASH_LATENCY_8 FLASH Eight wait states + * @arg @ref FLASH_LATENCY_9 FLASH Nine wait states + * @arg @ref FLASH_LATENCY_10 FLASH Ten wait states + * @arg @ref FLASH_LATENCY_11 FLASH Eleven wait states + * @arg @ref FLASH_LATENCY_12 FLASH Twelve wait states + * @arg @ref FLASH_LATENCY_13 FLASH Thirteen wait states + * @arg @ref FLASH_LATENCY_14 FLASH Fourteen wait states + * @arg @ref FLASH_LATENCY_15 FLASH Fifteen wait states + */ +#define __HAL_FLASH_GET_LATENCY() READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY) + +/** + * @brief Enable the FLASH prefetch buffer. + * @retval None + */ +#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) + +/** + * @brief Disable the FLASH prefetch buffer. + * @retval None + */ +#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) + +/** + * @brief Enable the FLASH power down during Low-Power sleep mode + * @retval None + */ +#define __HAL_FLASH_SLEEP_POWERDOWN_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD) + +/** + * @brief Disable the FLASH power down during Low-Power sleep mode + * @retval None + */ +#define __HAL_FLASH_SLEEP_POWERDOWN_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD) + +/** + * @} + */ + +/** @defgroup FLASH_Interrupt FLASH Interrupts Macros + * @brief macros to handle FLASH interrupts + * @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Enable secure FLASH interrupts from the secure world. + * @param __INTERRUPT__ FLASH interrupt + * This parameter can be any combination of the following values: + * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt + * @arg @ref FLASH_IT_OPERR Error Interrupt + * @arg @ref FLASH_IT_ECCC ECC Correction Interrupt + * @retval None + */ +#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\ + if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { SET_BIT(FLASH->SECCR1, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ + } while(0) +/** + * @brief Enable non-secure FLASH interrupts from the secure world. + * @param __INTERRUPT__ FLASH interrupt. + * This parameter can be any combination of the following values: + * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt + * @arg @ref FLASH_IT_OPERR Error Interrupt + * @arg @ref FLASH_IT_ECCC ECC Correction Interrupt + * @retval None + */ +#define __HAL_FLASH_ENABLE_IT_NS(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\ + if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { SET_BIT(FLASH->NSCR1, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ + } while(0) +#else +/** + * @brief Enable non-secure FLASH interrupts from the non-secure world. + * @param __INTERRUPT__ FLASH interrupt. + * This parameter can be any combination of the following values: + * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt + * @arg @ref FLASH_IT_OPERR Error Interrupt + * @arg @ref FLASH_IT_ECCC ECC Correction Interrupt + * @retval None + */ +#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\ + if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { SET_BIT(FLASH->NSCR1, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ + } while(0) +#endif /* __ARM_FEATURE_CMSE */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Disable secure FLASH interrupts from the secure world. + * @param __INTERRUPT__ FLASH interrupt. + * This parameter can be any combination of the following values: + * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt + * @arg @ref FLASH_IT_OPERR Error Interrupt + * @arg @ref FLASH_IT_ECCC ECC Correction Interrupt + * @retval None + */ +#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\ + if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { CLEAR_BIT(FLASH->SECCR1, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ + } while(0) +/** + * @brief Disable non-secure FLASH interrupts from the secure world. + * @param __INTERRUPT__ FLASH interrupt. + * This parameter can be any combination of the following values: + * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt + * @arg @ref FLASH_IT_OPERR Error Interrupt + * @arg @ref FLASH_IT_ECCC ECC Correction Interrupt + * @retval None + */ +#define __HAL_FLASH_DISABLE_IT_NS(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\ + if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { CLEAR_BIT(FLASH->NSCR1, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ + } while(0) +#else +/** + * @brief Disable non-secure FLASH interrupts from the non-secure world. + * @param __INTERRUPT__ FLASH interrupt. + * This parameter can be any combination of the following values: + * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt + * @arg @ref FLASH_IT_OPERR Error Interrupt + * @arg @ref FLASH_IT_ECCC ECC Correction Interrupt + * @retval None + */ +#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\ + if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { CLEAR_BIT(FLASH->NSCR1, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ + } while(0) +#endif /* __ARM_FEATURE_CMSE */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Check whether the specified secure FLASH flags from the secure world is set or not. + * @param __FLAG__ specifies the FLASH flag to check. + * This parameter can be one of the following values: + * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag + * @arg @ref FLASH_FLAG_OPERR FLASH Operation error flag + * @arg @ref FLASH_FLAG_PROGERR FLASH Programming error flag + * @arg @ref FLASH_FLAG_WRPERR FLASH Write protection error flag + * @arg @ref FLASH_FLAG_PGAERR FLASH Programming alignment error flag + * @arg @ref FLASH_FLAG_SIZERR FLASH Size error flag + * @arg @ref FLASH_FLAG_PGSERR FLASH Programming sequence error flag + * @arg @ref FLASH_FLAG_OPTWERR FLASH Option modification error flag + * @arg @ref FLASH_FLAG_BSY FLASH write/erase operations in progress flag + * @arg @ref FLASH_FLAG_WDW FLASH Wait Data to Write flag + * @arg @ref FLASH_FLAG_ECCC FLASH one ECC error has been detected and corrected + * @arg @ref FLASH_FLAG_ECCD FLASH two ECC errors have been detected + * @retval The new state of FLASH_FLAG (SET or RESET). + */ +#define __HAL_FLASH_GET_FLAG(__FLAG__) ((((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) ? \ + (READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__)) : \ + ((((__FLAG__) & (FLASH_FLAG_OPTWERR)) != 0U) ? \ + (READ_BIT(FLASH->NSSR, (__FLAG__)) == (__FLAG__)) : \ + (READ_BIT(FLASH->SECSR, (__FLAG__)) == (__FLAG__)))) +/** + * @brief Check whether the specified non-secure FLASH flags from the secure world is set or not. + * @param __FLAG__ specifies the FLASH flag to check. + * This parameter can be one of the following values: + * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag + * @arg @ref FLASH_FLAG_OPERR FLASH Operation error flag + * @arg @ref FLASH_FLAG_PROGERR FLASH Programming error flag + * @arg @ref FLASH_FLAG_WRPERR FLASH Write protection error flag + * @arg @ref FLASH_FLAG_PGAERR FLASH Programming alignment error flag + * @arg @ref FLASH_FLAG_SIZERR FLASH Size error flag + * @arg @ref FLASH_FLAG_PGSERR FLASH Programming sequence error flag + * @arg @ref FLASH_FLAG_OPTWERR FLASH Option modification error flag + * @arg @ref FLASH_FLAG_BSY FLASH write/erase operations in progress flag + * @arg @ref FLASH_FLAG_WDW FLASH Wait Data to Write flag + * @arg @ref FLASH_FLAG_ECCC FLASH one ECC error has been detected and corrected + * @arg @ref FLASH_FLAG_ECCD FLASH two ECC errors have been detected + * @retval The new state of FLASH_FLAG (SET or RESET). + */ +#define __HAL_FLASH_GET_FLAG_NS(__FLAG__) ((((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) ? \ + (READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__)) : \ + (READ_BIT(FLASH->NSSR, (__FLAG__)) == (__FLAG__))) +#else +/** + * @brief Check whether the specified non-secure FLASH flags from the non-secure world is set or not. + * @param __FLAG__ specifies the FLASH flag to check. + * This parameter can be one of the following values: + * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag + * @arg @ref FLASH_FLAG_OPERR FLASH Operation error flag + * @arg @ref FLASH_FLAG_PROGERR FLASH Programming error flag + * @arg @ref FLASH_FLAG_WRPERR FLASH Write protection error flag + * @arg @ref FLASH_FLAG_PGAERR FLASH Programming alignment error flag + * @arg @ref FLASH_FLAG_SIZERR FLASH Size error flag + * @arg @ref FLASH_FLAG_PGSERR FLASH Programming sequence error flag + * @arg @ref FLASH_FLAG_OPTWERR FLASH Option modification error flag + * @arg @ref FLASH_FLAG_BSY FLASH write/erase operations in progress flag + * @arg @ref FLASH_FLAG_WDW FLASH Wait Data to Write flag + * @arg @ref FLASH_FLAG_OEM1LOCK FLASH OEM1 key RDP lock flag + * @arg @ref FLASH_FLAG_OEM2LOCK FLASH OEM2 key RDP lock flag + * @arg @ref FLASH_FLAG_PD FLASH in power-down lock flag + * @arg @ref FLASH_FLAG_ECCC FLASH one ECC error has been detected and corrected + * @arg @ref FLASH_FLAG_ECCD FLASH two ECC errors have been detected + * @retval The new state of FLASH_FLAG (SET or RESET). + */ +#define __HAL_FLASH_GET_FLAG(__FLAG__) ((((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) ? \ + (READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__)) : \ + (READ_BIT(FLASH->NSSR, (__FLAG__)) == (__FLAG__))) +#endif /* __ARM_FEATURE_CMSE */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Clear secure FLASH flags from the secure world. + * @param __FLAG__ specifies the FLASH flags to clear. + * This parameter can be any combination of the following values: + * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag + * @arg @ref FLASH_FLAG_OPERR FLASH Operation error flag + * @arg @ref FLASH_FLAG_PROGERR FLASH Programming error flag + * @arg @ref FLASH_FLAG_WRPERR FLASH Write protection error flag + * @arg @ref FLASH_FLAG_PGAERR FLASH Programming alignment error flag + * @arg @ref FLASH_FLAG_SIZERR FLASH Size error flag + * @arg @ref FLASH_FLAG_PGSERR FLASH Programming sequence error flag + * @arg @ref FLASH_FLAG_ECCC FLASH one ECC error has been detected and corrected + * @arg @ref FLASH_FLAG_ECCD FLASH two ECC errors have been detected + * @arg @ref FLASH_FLAG_ALL_ERRORS FLASH All errors flags + * @retval None + */ +#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if(((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) { SET_BIT(FLASH->ECCR, ((__FLAG__) & FLASH_FLAG_ECCR_ERRORS)); }\ + if(((__FLAG__) & FLASH_FLAG_OPTWERR) != 0U) { SET_BIT(FLASH->NSSR, ((__FLAG__) & (FLASH_FLAG_OPTWERR))); }\ + if(((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS | FLASH_FLAG_OPTWERR)) != 0U) { WRITE_REG(FLASH->SECSR, ((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS | FLASH_FLAG_OPTWERR))); } \ + } while(0) +/** + * @brief Clear non-secure FLASH flags from the secure world. + * @param __FLAG__ specifies the FLASH flags to clear. + * This parameter can be any combination of the following values: + * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag + * @arg @ref FLASH_FLAG_OPERR FLASH Operation error flag + * @arg @ref FLASH_FLAG_PROGERR FLASH Programming error flag + * @arg @ref FLASH_FLAG_WRPERR FLASH Write protection error flag + * @arg @ref FLASH_FLAG_PGAERR FLASH Programming alignment error flag + * @arg @ref FLASH_FLAG_SIZERR FLASH Size error flag + * @arg @ref FLASH_FLAG_PGSERR FLASH Programming sequence error flag + * @arg @ref FLASH_FLAG_OPTWERR FLASH Option modification error flag + * @arg @ref FLASH_FLAG_ECCC FLASH one ECC error has been detected and corrected + * @arg @ref FLASH_FLAG_ECCD FLASH two ECC errors have been detected + * @arg @ref FLASH_FLAG_ALL_ERRORS FLASH All errors flags + * @retval None + */ +#define __HAL_FLASH_CLEAR_FLAG_NS(__FLAG__) do { if(((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) { SET_BIT(FLASH->ECCR, ((__FLAG__) & FLASH_FLAG_ECCR_ERRORS)); }\ + if(((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS)) != 0U) { WRITE_REG(FLASH->NSSR, ((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS))); }\ + } while(0) +#else +/** + * @brief Clear non-secure FLASH flags from the non-secure world. + * @param __FLAG__ specifies the FLASH flags to clear. + * This parameter can be any combination of the following values: + * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag + * @arg @ref FLASH_FLAG_OPERR FLASH Operation error flag + * @arg @ref FLASH_FLAG_PROGERR FLASH Programming error flag + * @arg @ref FLASH_FLAG_WRPERR FLASH Write protection error flag + * @arg @ref FLASH_FLAG_PGAERR FLASH Programming alignment error flag + * @arg @ref FLASH_FLAG_SIZERR FLASH Size error flag + * @arg @ref FLASH_FLAG_PGSERR FLASH Programming sequence error flag + * @arg @ref FLASH_FLAG_OPTWERR FLASH Option modification error flag + * @arg @ref FLASH_FLAG_ECCC FLASH one ECC error has been detected and corrected + * @arg @ref FLASH_FLAG_ECCD FLASH two ECC errors have been detected + * @arg @ref FLASH_FLAG_ALL_ERRORS FLASH All errors flags + * @retval None + */ +#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if(((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) { SET_BIT(FLASH->ECCR, ((__FLAG__) & FLASH_FLAG_ECCR_ERRORS)); }\ + if(((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS)) != 0U) { WRITE_REG(FLASH->NSSR, ((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS))); }\ + } while(0) +#endif /* __ARM_FEATURE_CMSE */ +/** + * @} + */ + +/* Include FLASH HAL Extended module */ +#include "stm32wbaxx_hal_flash_ex.h" + + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup FLASH_Exported_Functions + * @{ + */ + +/* Program operation functions ***********************************************/ +/** @addtogroup FLASH_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint32_t DataAddress); +HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint32_t DataAddress); +/* FLASH IRQ handler method */ +void HAL_FLASH_IRQHandler(void); +/* Callbacks in non blocking modes */ +void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); +void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); +/** + * @} + */ + +/* Peripheral Control functions **********************************************/ +/** @addtogroup FLASH_Exported_Functions_Group2 + * @{ + */ +HAL_StatusTypeDef HAL_FLASH_Unlock(void); +HAL_StatusTypeDef HAL_FLASH_Lock(void); +/* Option bytes control */ +HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); +HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); +HAL_StatusTypeDef HAL_FLASH_OB_Launch(void); +/** + * @} + */ + +/* Peripheral State functions ************************************************/ +/** @addtogroup FLASH_Exported_Functions_Group3 + * @{ + */ +uint32_t HAL_FLASH_GetError(void); +/** + * @} + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @addtogroup FLASH_Private_Variables FLASH Private Variables + * @{ + */ +extern FLASH_ProcessTypeDef pFlash; +/** + * @} + */ + +/* Private function ----------------------------------------------------------*/ +/** @addtogroup FLASH_Private_Functions FLASH Private Functions + * @{ + */ +HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup FLASH_Private_Constants FLASH Private Constants + * @{ + */ +#define FLASH_BANK_SIZE FLASH_SIZE +#define FLASH_PAGE_SIZE 0x2000U /* 8 KB */ + +#define FLASH_PAGE_NB (FLASH_SIZE / FLASH_PAGE_SIZE) + +#define FLASH_TIMEOUT_VALUE 1000U /* 1 s */ + +#define FLASH_NON_SECURE_MASK 0x80000000U +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup FLASH_Private_Macros FLASH Private Macros + * @{ + */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || \ + ((VALUE) == FLASH_TYPEERASE_PAGES_NS) || \ + ((VALUE) == FLASH_TYPEERASE_MASSERASE) || \ + ((VALUE) == FLASH_TYPEERASE_MASSERASE_NS)) +#else +#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || \ + ((VALUE) == FLASH_TYPEERASE_MASSERASE)) +#endif /* __ARM_FEATURE_CMSE */ + +#define IS_FLASH_BANK(BANK) ((BANK) == FLASH_BANK_1) + +#define IS_FLASH_BANK_EXCLUSIVE(BANK) ((BANK) == FLASH_BANK_1) + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_QUADWORD) || \ + ((VALUE) == FLASH_TYPEPROGRAM_QUADWORD_NS) || \ + ((VALUE) == FLASH_TYPEPROGRAM_BURST) || \ + ((VALUE) == FLASH_TYPEPROGRAM_BURST_NS)) +#else +#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_QUADWORD) || \ + ((VALUE) == FLASH_TYPEPROGRAM_BURST)) +#endif /* __ARM_FEATURE_CMSE */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) ((((ADDRESS) >= FLASH_BASE) && ((ADDRESS) < (FLASH_BASE+FLASH_SIZE))) || \ + (((ADDRESS) >= FLASH_BASE_NS) && ((ADDRESS) < (FLASH_BASE_NS+FLASH_SIZE)))) +#else +#define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) < (FLASH_BASE+FLASH_SIZE))) +#endif /* __ARM_FEATURE_CMSE */ + +#define IS_FLASH_OTP_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_OTP_BASE) && ((ADDRESS) < (FLASH_OTP_BASE + FLASH_OTP_SIZE))) + +#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) ((IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS)) || (IS_FLASH_OTP_ADDRESS(ADDRESS))) + +#define IS_FLASH_PAGE(PAGE) ((PAGE) < FLASH_PAGE_NB) + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | \ + OPTIONBYTE_WMSEC | OPTIONBYTE_BOOT_LOCK | OPTIONBYTE_BOOTADDR | \ + OPTIONBYTE_RDPKEY))) +#else +#define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | \ + OPTIONBYTE_BOOTADDR | OPTIONBYTE_RDPKEY))) +#endif /* __ARM_FEATURE_CMSE */ + +#define IS_OB_WRPAREA(VALUE) (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB)) + +#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\ + ((LEVEL) == OB_RDP_LEVEL_0_5) ||\ + ((LEVEL) == OB_RDP_LEVEL_1) ||\ + ((LEVEL) == OB_RDP_LEVEL_2)) + +#define IS_OB_USER_TYPE(TYPE) ((((TYPE) & OB_USER_ALL) != 0x00U) && (((TYPE) & ~OB_USER_ALL) == 0x00U)) + +#define IS_OB_USER_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL_0) || ((LEVEL) == OB_BOR_LEVEL_1) || \ + ((LEVEL) == OB_BOR_LEVEL_2) || ((LEVEL) == OB_BOR_LEVEL_3) || \ + ((LEVEL) == OB_BOR_LEVEL_4)) + +#define IS_OB_USER_STOP(VALUE) (((VALUE) == OB_STOP_RST) || ((VALUE) == OB_STOP_NORST)) + +#define IS_OB_USER_STANDBY(VALUE) (((VALUE) == OB_STANDBY_RST) || ((VALUE) == OB_STANDBY_NORST)) + +#define IS_OB_USER_SRAM1_RST(VALUE) (((VALUE) == OB_SRAM1_RST_ERASE) || ((VALUE) == OB_SRAM1_RST_NOT_ERASE)) + +#define IS_OB_USER_IWDG(VALUE) (((VALUE) == OB_IWDG_HW) || ((VALUE) == OB_IWDG_SW)) + +#define IS_OB_USER_IWDG_STOP(VALUE) (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_RUN)) + +#define IS_OB_USER_IWDG_STDBY(VALUE) (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_RUN)) + +#define IS_OB_USER_WWDG(VALUE) (((VALUE) == OB_WWDG_HW) || ((VALUE) == OB_WWDG_SW)) + + +#define IS_OB_USER_SRAM2_PARITY(VALUE) (((VALUE) == OB_SRAM2_PARITY_ENABLE) || ((VALUE) == OB_SRAM2_PARITY_DISABLE)) + +#define IS_OB_USER_SRAM2_RST(VALUE) (((VALUE) == OB_SRAM2_RST_ERASE) || ((VALUE) == OB_SRAM2_RST_NOT_ERASE)) + +#define IS_OB_USER_SWBOOT0(VALUE) (((VALUE) == OB_BOOT0_FROM_OB) || ((VALUE) == OB_BOOT0_FROM_PIN)) + +#define IS_OB_USER_BOOT0(VALUE) (((VALUE) == OB_nBOOT0_RESET) || ((VALUE) == OB_nBOOT0_SET)) + + +#define IS_OB_USER_TZEN(VALUE) (((VALUE) == OB_TZEN_DISABLE) || ((VALUE) == OB_TZEN_ENABLE)) + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define IS_OB_BOOT_LOCK(VALUE) (((VALUE) == OB_BOOT_LOCK_DISABLE) || ((VALUE) == OB_BOOT_LOCK_ENABLE)) + +#define IS_OB_WMSEC_CONFIG(CFG) ((((CFG) & 0x7F1U) != 0U) && (((CFG) & 0x1U) != 0U) && (((CFG) & 0xFFFFF80EU) == 0U)) + +#define IS_OB_WMSEC_AREA_EXCLUSIVE(WMSEC) (((WMSEC) & OB_WMSEC_AREA1) != 0U) +#endif /* __ARM_FEATURE_CMSE */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define IS_OB_BOOTADDR_CONFIG(CFG) (((CFG) == OB_BOOTADDR_NS0) || ((CFG) == OB_BOOTADDR_NS1) || \ + ((CFG) == OB_BOOTADDR_SEC0)) +#else +#define IS_OB_BOOTADDR_CONFIG(CFG) (((CFG) == OB_BOOTADDR_NS0) || ((CFG) == OB_BOOTADDR_NS1)) +#endif /* __ARM_FEATURE_CMSE */ + +#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || ((LATENCY) == FLASH_LATENCY_1) || \ + ((LATENCY) == FLASH_LATENCY_2) || ((LATENCY) == FLASH_LATENCY_3) || \ + ((LATENCY) == FLASH_LATENCY_4) || ((LATENCY) == FLASH_LATENCY_5) || \ + ((LATENCY) == FLASH_LATENCY_6) || ((LATENCY) == FLASH_LATENCY_7) || \ + ((LATENCY) == FLASH_LATENCY_8) || ((LATENCY) == FLASH_LATENCY_9) || \ + ((LATENCY) == FLASH_LATENCY_10) || ((LATENCY) == FLASH_LATENCY_11) || \ + ((LATENCY) == FLASH_LATENCY_12) || ((LATENCY) == FLASH_LATENCY_13) || \ + ((LATENCY) == FLASH_LATENCY_14) || ((LATENCY) == FLASH_LATENCY_15)) + +#define IS_OB_RDP_KEY_TYPE(TYPE) (((TYPE) == OB_RDP_KEY_OEM1) || \ + ((TYPE) == OB_RDP_KEY_OEM2)) + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define IS_FLASH_SECURE_OPERATION() ((pFlash.ProcedureOnGoing & FLASH_NON_SECURE_MASK) == 0U) +#else +#define IS_FLASH_SECURE_OPERATION() (0U) +#endif /* __ARM_FEATURE_CMSE */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WBAxx_HAL_FLASH_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_flash_ex.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_flash_ex.h new file mode 100644 index 0000000000..72ace1ff34 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_flash_ex.h @@ -0,0 +1,328 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_flash_ex.h + * @author MCD Application Team + * @brief Header file of FLASH HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_HAL_FLASH_EX_H +#define STM32WBAxx_HAL_FLASH_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal_def.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @addtogroup FLASHEx + * @{ + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup FLASHEx_Private_Constants FLASH Extended Private Constants + * @{ + */ +#if defined(FLASH_SECBBR1_SECBB0) || defined(FLASH_PRIVBBR1_PRIVBB0) || defined(FLASH_SECBB1R1_SECBB0) || defined(FLASH_PRIVBB1R1_PRIVBB0) +#define FLASH_BLOCKBASED_NB_REG (4U) /*!< Number of block-based registers available */ +#endif /* FLASH_SECBBR1_SECBB0 || FLASH_PRIVBBR1_PRIVBB0 */ +/** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup FLASHEx_Exported_Types FLASH Exported Types + * @{ + */ + +#if defined(FLASH_SECBBR1_SECBB0) || defined(FLASH_PRIVBBR1_PRIVBB0) || defined(FLASH_SECBB1R1_SECBB0) || defined(FLASH_PRIVBB1R1_PRIVBB0) +/** + * @brief FLASHEx Block-based attributes structure definition + */ +typedef struct +{ + uint32_t BBAttributesType; /*!< Block-Based Attributes type. + This parameter must be a value of @ref FLASHEx_BB_Attributes */ + uint32_t BBAttributes_array[FLASH_BLOCKBASED_NB_REG]; /*!< Each bit specifies the block-based attribute configuration of a page: + 0 means page non-protected, 1 means page protected. + Protection (secure or privilege) depends on BBAttributesType value */ +} FLASH_BBAttributesTypeDef; +#endif /* FLASH_SECBBR1_SECBB0 || FLASH_PRIVBBR1_PRIVBB0 */ + +/** + * @brief FLASHEx Operation structure definition + */ +typedef struct +{ + uint32_t OperationType; /*!< Flash operation Type. + This parameter must be a value of @ref FLASHEx_Operation_Type */ + uint32_t FlashArea; /*!< Flash operation memory area. + This parameter must be a value of FLASH_Operation_Area */ + uint32_t Address; /*!< Flash operation Address offset. + This parameter is given by bank, and must be a value between 0x0 and 0xFFFF0 */ +} FLASH_OperationTypeDef; + +/** + * @brief FLASH ECC information structure definition + */ +typedef struct +{ + uint32_t Area; /*!< Area from which an ECC was detected. + This parameter can be a value of @ref FLASHEx_ECC_Area */ + uint32_t Address; /*!< Flash address from which en ECC error was detected. + This parameter must be a value between begin address and end address of the Flash */ + uint32_t MasterID; /*!< Master that initiated transfer on which error was detected + This parameter can be a value of @ref FLASHEx_ECC_Master */ +} FLASH_EccInfoTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup FLASHEx_Exported_Constants FLASH Extended Exported Constants + * @{ + */ + +#if defined(FLASH_PRIVCFGR_SPRIV) +/** @defgroup FLASHEx_PRIV_MODE_CFG FLASH privilege mode configuration + * @{ + */ +#define FLASH_NSPRIV_GRANTED 0x00000000U /*!< access to non-secure Flash registers is granted to privileged or unprivileged access */ +#define FLASH_NSPRIV_DENIED FLASH_PRIVCFGR_NSPRIV /*!< access to non-secure Flash registers is denied to non-privilege access */ + +#define FLASH_SPRIV_GRANTED 0x00000000U /*!< access to secure Flash registers is granted to privileged or unprivileged access */ +#define FLASH_SPRIV_DENIED FLASH_PRIVCFGR_SPRIV /*!< access to secure Flash registers is denied to non-privilege access */ +/** + * @} + */ +#endif /* FLASH_PRIVCFGR_SPRIV */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** @defgroup FLASHEx_SEC_INVERSION_CFG FLASH security inversion configuration + * @{ + */ +#define FLASH_INV_DISABLE 0x00000000U /*!< Security state of Flash is not inverted */ +#define FLASH_INV_ENABLE FLASH_SECCR1_INV /*!< Security state of Flash is inverted */ +/** + * @} + */ +#endif /* __ARM_FEATURE_CMSE */ + +/** @defgroup FLASHEx_LPM_CFG FLASH LPM configuration + * @{ + */ +#define FLASH_LPM_DISABLE 0x00000000U /*!< Flash is in normal read mode */ +#define FLASH_LPM_ENABLE FLASH_ACR_LPM /*!< Flash is in low-power read mode */ +/** + * @} + */ + +#if defined(FLASH_SECBBR1_SECBB0) || defined(FLASH_PRIVBBR1_PRIVBB0) || defined(FLASH_SECBB1R1_SECBB0) || defined(FLASH_PRIVBB1R1_PRIVBB0) +/** @defgroup FLASHEx_BB_Attributes FLASH Block-Based Attributes + * @{ + */ +#define FLASH_BB_SEC 0x00000001U /*!< Flash Block-Based Security Attributes */ +#define FLASH_BB_PRIV 0x00000002U /*!< Flash Block-Based Privilege Attributes */ +/** + * @} + */ +#endif /* FLASH_SECBBR1_SECBB0 || FLASH_PRIVBBR1_PRIVBB0 */ + +/** @defgroup FLASHEx_Operation_Type FLASH Operation Type + * @{ + */ +#define FLASH_OPERATION_TYPE_NONE 00000000U /*!< No Flash operation */ +#define FLASH_OPERATION_TYPE_QUADWORD FLASH_OPSR_CODE_OP_0 /*!< Single write operation */ +#define FLASH_OPERATION_TYPE_BURST FLASH_OPSR_CODE_OP_1 /*!< Burst write operation */ +#define FLASH_OPERATION_TYPE_PAGEERASE (FLASH_OPSR_CODE_OP_1 | FLASH_OPSR_CODE_OP_0) /*!< Page erase operation */ +#define FLASH_OPERATION_TYPE_MASSERASE (FLASH_OPSR_CODE_OP_2 | FLASH_OPSR_CODE_OP_0) /*!< Mass erase operation */ +#define FLASH_OPERATION_TYPE_OPTIONCHANGE (FLASH_OPSR_CODE_OP_2 | FLASH_OPSR_CODE_OP_1) /*!< Option change operation */ +/** + * @} + */ + +/** @defgroup FLASHEx_ECC_Area FLASH ECC Area + * @{ + */ +#define FLASH_ECC_AREA_USER_BANK1 0x00000000U /*!< FLASH bank 1 area */ +#define FLASH_ECC_AREA_SYSTEM FLASH_ECCR_SYSF_ECC /*!< System FLASH area */ +/** + * @} + */ + +/** @defgroup FLASHEx_ECC_Master FLASH ECC Master + * @{ + */ +#define FLASH_ECC_MASTER_CPU1 0x00000000U /*!< ECC error occurs on a CPU1 transaction */ +/** + * @} + */ + +/** @defgroup FLASHEx_Suspend_Request FLASH Suspend Request + * @{ + */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define FLASH_SUSPEND_PROGRAM FLASH_SECCR2_PS /*!< Suspend all program requests */ +#define FLASH_SUSPEND_ERASE FLASH_SECCR2_ES /*!< Suspend all erase requests */ +#define FLASH_SUSPEND_PROGRAM_ERASE (FLASH_SECCR2_PS | FLASH_SECCR2_ES) /*!< Suspend all requests (program and erase) */ +#else +#define FLASH_SUSPEND_PROGRAM FLASH_NSCR2_PS /*!< Suspend all program requests */ +#define FLASH_SUSPEND_ERASE FLASH_NSCR2_ES /*!< Suspend all erase requests */ +#define FLASH_SUSPEND_PROGRAM_ERASE (FLASH_NSCR2_PS | FLASH_NSCR2_ES) /*!< Suspend all requests (program and erase) */ +#endif /* __ARM_FEATURE_CMSE */ +/** + * @} + */ + +/** @defgroup FLASHEx_Allow_Request FLASH Allow Request + * @{ + */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define FLASH_ALLOW_PROGRAM FLASH_SECCR2_PS /*!< Allow all program requests */ +#define FLASH_ALLOW_ERASE FLASH_SECCR2_ES /*!< Allow all erase requests */ +#define FLASH_ALLOW_PROGRAM_ERASE (FLASH_SECCR2_PS | FLASH_SECCR2_ES) /*!< Allow all requests (program and erase) */ +#else +#define FLASH_ALLOW_PROGRAM FLASH_NSCR2_PS /*!< Allow all program requests */ +#define FLASH_ALLOW_ERASE FLASH_NSCR2_ES /*!< Allow all erase requests */ +#define FLASH_ALLOW_PROGRAM_ERASE (FLASH_NSCR2_PS | FLASH_NSCR2_ES) /*!< Allow all requests (program and erase) */ +#endif /* __ARM_FEATURE_CMSE */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup FLASHEx_Exported_Functions + * @{ + */ + +/* Extended Program operation functions *************************************/ +/** @addtogroup FLASHEx_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError); +HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit); +HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); +void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); +#if defined(FLASH_SECBBR1_SECBB0) || defined(FLASH_PRIVBBR1_PRIVBB0) || defined(FLASH_SECBB1R1_SECBB0) || defined(FLASH_PRIVBB1R1_PRIVBB0) +HAL_StatusTypeDef HAL_FLASHEx_ConfigBBAttributes(FLASH_BBAttributesTypeDef *pBBAttributes); +void HAL_FLASHEx_GetConfigBBAttributes(FLASH_BBAttributesTypeDef *pBBAttributes); +#endif /* FLASH_SECBBR1_SECBB0 || FLASH_PRIVBBR1_PRIVBB0 */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +void HAL_FLASHEx_EnableSecHideProtection(uint32_t Banks); +#endif /* __ARM_FEATURE_CMSE */ +/** + * @} + */ + +/** @addtogroup FLASHEx_Exported_Functions_Group2 + * @{ + */ +void HAL_FLASHEx_SuspendOperation(uint32_t Request); +void HAL_FLASHEx_AllowOperation(uint32_t Request); +uint32_t HAL_FLASHEx_IsOperationSuspended(void); +#if defined(FLASH_PRIVCFGR_SPRIV) +void HAL_FLASHEx_ConfigPrivMode(uint32_t PrivMode); +uint32_t HAL_FLASHEx_GetPrivMode(void); +#endif /* FLASH_PRIVCFGR_SPRIV */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +HAL_StatusTypeDef HAL_FLASHEx_ConfigSecInversion(uint32_t SecInvState); +uint32_t HAL_FLASHEx_GetSecInversion(void); +#endif /* __ARM_FEATURE_CMSE */ +HAL_StatusTypeDef HAL_FLASHEx_EnablePowerDown(void); +HAL_StatusTypeDef HAL_FLASHEx_ConfigLowPowerRead(uint32_t ConfigLPM); +uint32_t HAL_FLASHEx_GetLowPowerRead(void); +void HAL_FLASHEx_GetOperation(FLASH_OperationTypeDef *pFlashOperation); +/** + * @} + */ + +/** @addtogroup FLASHEx_Exported_Functions_Group3 + * @{ + */ +void HAL_FLASHEx_EnableEccCorrectionInterrupt(void); +void HAL_FLASHEx_DisableEccCorrectionInterrupt(void); +void HAL_FLASHEx_GetEccInfo(FLASH_EccInfoTypeDef *pData); +void HAL_FLASHEx_ECCD_IRQHandler(void); +__weak void HAL_FLASHEx_EccDetectionCallback(void); +__weak void HAL_FLASHEx_EccCorrectionCallback(void); +/** + * @} + */ + +/** + * @} + */ + +/* Private function ----------------------------------------------------------*/ +/** @addtogroup FLASHEx_Private_Functions FLASHEx Private Functions + * @{ + */ +void FLASH_PageErase(uint32_t Page); +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup FLASHEx_Private_Macros FLASH Private Macros + * @{ + */ +#define IS_FLASH_BB_EXCLUSIVE(CFG) (((CFG) == FLASH_BB_SEC) || \ + ((CFG) == FLASH_BB_PRIV)) + +#define IS_FLASH_CFGPRIVMODE(CFG) (((CFG) & 0xFFFFFFFCU) == 0U) + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define IS_FLASH_CFGSECINV(CFG) (((CFG) == FLASH_INV_DISABLE) || \ + ((CFG) == FLASH_INV_ENABLE)) +#endif /* __ARM_FEATURE_CMSE */ + +#define IS_FLASH_CFGLPM(CFG) (((CFG) == FLASH_LPM_DISABLE) || \ + ((CFG) == FLASH_LPM_ENABLE)) + +#define IS_FLASH_SUSPEND_REQ(VALUE) (((VALUE) == FLASH_SUSPEND_PROGRAM) || \ + ((VALUE) == FLASH_SUSPEND_ERASE) || \ + ((VALUE) == FLASH_SUSPEND_PROGRAM_ERASE)) + +#define IS_FLASH_ALLOW_REQ(VALUE) (((VALUE) == FLASH_ALLOW_PROGRAM) || \ + ((VALUE) == FLASH_ALLOW_ERASE) || \ + ((VALUE) == FLASH_ALLOW_PROGRAM_ERASE)) +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WBAxx_HAL_FLASH_EX_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_gpio.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_gpio.h new file mode 100644 index 0000000000..5b2efdef2f --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_gpio.h @@ -0,0 +1,400 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_gpio.h + * @author MCD Application Team + * @brief Header file of GPIO HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_HAL_GPIO_H +#define STM32WBAxx_HAL_GPIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal_def.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @defgroup GPIO GPIO + * @brief GPIO HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup GPIO_Exported_Types GPIO Exported Types + * @{ + */ +/** + * @brief GPIO Init structure definition + */ +typedef struct +{ + uint32_t Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_pins */ + + uint32_t Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIO_mode */ + + uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins. + This parameter can be a value of @ref GPIO_pull */ + + uint32_t Speed; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIO_speed */ + + uint32_t Alternate; /*!< Peripheral to be connected to the selected pins + This parameter can be a value of @ref GPIOEx_Alternate_function_selection */ +} GPIO_InitTypeDef; + +/** + * @brief GPIO Bit SET and Bit RESET enumeration + */ +typedef enum +{ + GPIO_PIN_RESET = 0U, + GPIO_PIN_SET +} GPIO_PinState; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Constants GPIO Exported Constants + * @{ + */ +/** @defgroup GPIO_pins GPIO pins + * @{ + */ +#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */ +#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */ +#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */ +#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */ +#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */ +#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */ +#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */ +#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */ +#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */ +#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */ +#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */ +#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */ +#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */ +#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */ +#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */ +#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */ +#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */ + +#define GPIO_PIN_MASK (0x0000FFFFu) /* PIN mask for assert test */ +/** + * @} + */ + +/** @defgroup GPIO_mode GPIO mode + * @brief GPIO Configuration Mode + * Elements values convention: 0x00WX00YZ + * - W : EXTI trigger detection on 3 bits + * - X : EXTI mode (IT or Event) on 2 bits + * - Y : Output type (Push Pull or Open Drain) on 1 bit + * - Z : GPIO mode (Input, Output, Alternate or Analog) on 2 bits + * @{ + */ +#define GPIO_MODE_INPUT MODE_INPUT /*!< Input Floating Mode */ +#define GPIO_MODE_OUTPUT_PP (MODE_OUTPUT | OUTPUT_PP) /*!< Output Push Pull Mode */ +#define GPIO_MODE_OUTPUT_OD (MODE_OUTPUT | OUTPUT_OD) /*!< Output Open Drain Mode */ +#define GPIO_MODE_AF_PP (MODE_AF | OUTPUT_PP) /*!< Alternate Function Push Pull Mode */ +#define GPIO_MODE_AF_OD (MODE_AF | OUTPUT_OD) /*!< Alternate Function Open Drain Mode */ +#define GPIO_MODE_ANALOG MODE_ANALOG /*!< Analog Mode */ +#define GPIO_MODE_IT_RISING (MODE_INPUT | EXTI_IT | TRIGGER_RISING) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define GPIO_MODE_IT_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_FALLING) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define GPIO_MODE_IT_RISING_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ +#define GPIO_MODE_EVT_RISING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING) /*!< External Event Mode with Rising edge trigger detection */ +#define GPIO_MODE_EVT_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING) /*!< External Event Mode with Falling edge trigger detection */ +#define GPIO_MODE_EVT_RISING_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Event Mode with Rising/Falling edge trigger detection */ +/** + * @} + */ + +/** @defgroup GPIO_speed GPIO speed + * @brief GPIO Output Maximum frequency + * @{ + */ +#define GPIO_SPEED_FREQ_LOW 0x00000000u /*!< Low speed */ +#define GPIO_SPEED_FREQ_MEDIUM 0x00000001u /*!< Medium speed */ +#define GPIO_SPEED_FREQ_HIGH 0x00000002u /*!< High speed */ +/** + * @} + */ + +/** @defgroup GPIO_pull GPIO pull + * @brief GPIO Pull-Up or Pull-Down Activation + * @{ + */ +#define GPIO_NOPULL 0x00000000u /*!< No Pull-up or Pull-down activation */ +#define GPIO_PULLUP 0x00000001u /*!< Pull-up activation */ +#define GPIO_PULLDOWN 0x00000002u /*!< Pull-down activation */ +/** + * @} + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** @defgroup GPIO_attributes GPIO attributes + * @brief GPIO pin secure or non-secure attributes + * @{ + */ +#define GPIO_PIN_SEC (0x00000001U) /*!< Secure pin attribute */ +#define GPIO_PIN_NSEC (0x00000000U) /*!< Non-secure pin attribute */ +/** + * @} + */ + +#endif /* __ARM_FEATURE_CMSE */ +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Macros GPIO Exported Macros + * @{ + */ + +/** + * @brief Check whether the specified EXTI line is rising edge asserted or not. + * @param __EXTI_LINE__ specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTI_GET_RISING_IT(__EXTI_LINE__) (EXTI->RPR1 & (__EXTI_LINE__)) + +/** + * @brief Clear the EXTI line rising pending bits. + * @param __EXTI_LINE__ specifies the EXTI lines to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_CLEAR_RISING_IT(__EXTI_LINE__) (EXTI->RPR1 = (__EXTI_LINE__)) + +/** + * @brief Check whether the specified EXTI line is falling edge asserted or not. + * @param __EXTI_LINE__ specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTI_GET_FALLING_IT(__EXTI_LINE__) (EXTI->FPR1 & (__EXTI_LINE__)) + +/** + * @brief Clear the EXTI line falling pending bits. + * @param __EXTI_LINE__ specifies the EXTI lines to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_CLEAR_FALLING_IT(__EXTI_LINE__) (EXTI->FPR1 = (__EXTI_LINE__)) + +/** + * @brief Check whether the specified EXTI line is asserted or not. + * @param __EXTI_LINE__ specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (__HAL_GPIO_EXTI_GET_RISING_IT(__EXTI_LINE__) || \ + __HAL_GPIO_EXTI_GET_FALLING_IT(__EXTI_LINE__)) + +/** + * @brief Clear the EXTI's line pending bits. + * @param __EXTI_LINE__ specifies the EXTI lines to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) \ + do { \ + __HAL_GPIO_EXTI_CLEAR_RISING_IT(__EXTI_LINE__); \ + __HAL_GPIO_EXTI_CLEAR_FALLING_IT(__EXTI_LINE__); \ + } while(0) + + +/** + * @brief Generate a Software interrupt on selected EXTI line(s). + * @param __EXTI_LINE__ specifies the EXTI line to be set. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER1 = (__EXTI_LINE__)) +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup GPIO_Private_Constants GPIO Private Constants + * @{ + */ +#define GPIO_MODE_Pos 0u +#define GPIO_MODE (0x3uL << GPIO_MODE_Pos) +#define MODE_INPUT (0x0uL << GPIO_MODE_Pos) +#define MODE_OUTPUT (0x1uL << GPIO_MODE_Pos) +#define MODE_AF (0x2uL << GPIO_MODE_Pos) +#define MODE_ANALOG (0x3uL << GPIO_MODE_Pos) +#define OUTPUT_TYPE_Pos 4u +#define OUTPUT_TYPE (0x1uL << OUTPUT_TYPE_Pos) +#define OUTPUT_PP (0x0uL << OUTPUT_TYPE_Pos) +#define OUTPUT_OD (0x1uL << OUTPUT_TYPE_Pos) +#define EXTI_MODE_Pos 16u +#define EXTI_MODE (0x3uL << EXTI_MODE_Pos) +#define EXTI_IT (0x1uL << EXTI_MODE_Pos) +#define EXTI_EVT (0x2uL << EXTI_MODE_Pos) +#define TRIGGER_MODE_Pos 20u +#define TRIGGER_MODE (0x7uL << TRIGGER_MODE_Pos) +#define TRIGGER_RISING (0x1uL << TRIGGER_MODE_Pos) +#define TRIGGER_FALLING (0x2uL << TRIGGER_MODE_Pos) +/** + * @} + */ + +/** @defgroup GPIO_Private_Macros GPIO Private Macros + * @{ + */ +#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) + +#define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00u) &&\ + (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00u)) + +#define IS_GPIO_SINGLE_PIN(__PIN__) (((__PIN__) == GPIO_PIN_0) ||\ + ((__PIN__) == GPIO_PIN_1) ||\ + ((__PIN__) == GPIO_PIN_2) ||\ + ((__PIN__) == GPIO_PIN_3) ||\ + ((__PIN__) == GPIO_PIN_4) ||\ + ((__PIN__) == GPIO_PIN_5) ||\ + ((__PIN__) == GPIO_PIN_6) ||\ + ((__PIN__) == GPIO_PIN_7) ||\ + ((__PIN__) == GPIO_PIN_8) ||\ + ((__PIN__) == GPIO_PIN_9) ||\ + ((__PIN__) == GPIO_PIN_10) ||\ + ((__PIN__) == GPIO_PIN_11) ||\ + ((__PIN__) == GPIO_PIN_12) ||\ + ((__PIN__) == GPIO_PIN_13) ||\ + ((__PIN__) == GPIO_PIN_14) ||\ + ((__PIN__) == GPIO_PIN_15)) + +#define IS_GPIO_COMMON_PIN(__RESETMASK__, __SETMASK__) \ + (((uint32_t)(__RESETMASK__) & (uint32_t)(__SETMASK__)) == 0x00u) + +#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\ + ((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\ + ((__MODE__) == GPIO_MODE_OUTPUT_OD) ||\ + ((__MODE__) == GPIO_MODE_AF_PP) ||\ + ((__MODE__) == GPIO_MODE_AF_OD) ||\ + ((__MODE__) == GPIO_MODE_IT_RISING) ||\ + ((__MODE__) == GPIO_MODE_IT_FALLING) ||\ + ((__MODE__) == GPIO_MODE_IT_RISING_FALLING) ||\ + ((__MODE__) == GPIO_MODE_EVT_RISING) ||\ + ((__MODE__) == GPIO_MODE_EVT_FALLING) ||\ + ((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) ||\ + ((__MODE__) == GPIO_MODE_ANALOG)) + +#define IS_GPIO_SPEED(__SPEED__) (((__SPEED__) == GPIO_SPEED_FREQ_LOW) ||\ + ((__SPEED__) == GPIO_SPEED_FREQ_MEDIUM) ||\ + ((__SPEED__) == GPIO_SPEED_FREQ_HIGH)) + +#define IS_GPIO_PULL(__PULL__) (((__PULL__) == GPIO_NOPULL) ||\ + ((__PULL__) == GPIO_PULLUP) || \ + ((__PULL__) == GPIO_PULLDOWN)) + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +#define IS_GPIO_PIN_ATTRIBUTES(__ATTRIBUTES__) (((__ATTRIBUTES__) == GPIO_PIN_SEC) ||\ + ((__ATTRIBUTES__) == GPIO_PIN_NSEC)) + +#endif /* __ARM_FEATURE_CMSE */ + +/* Include GPIO HAL Extended module */ +#include "stm32wbaxx_hal_gpio_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Functions GPIO Exported Functions + * @brief GPIO Exported Functions + * @{ + */ + +/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions + * @brief Initialization and Configuration functions + * @{ + */ + +/* Initialization and de-initialization functions *****************************/ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *GPIO_Init); +void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); + +/** + * @} + */ + +/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * @{ + */ + +/* IO operation functions *****************************************************/ +GPIO_PinState HAL_GPIO_ReadPin(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); +void HAL_GPIO_WriteMultipleStatePin(GPIO_TypeDef *GPIOx, uint16_t PinReset, uint16_t PinSet); +void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin); +void HAL_GPIO_EXTI_Rising_Callback(uint16_t GPIO_Pin); +void HAL_GPIO_EXTI_Falling_Callback(uint16_t GPIO_Pin); + +/** + * @} + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** @defgroup GPIO_Exported_Functions_Group3 IO attributes management functions + * @{ + */ + +/* IO attributes management functions *****************************************/ +void HAL_GPIO_ConfigPinAttributes(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, uint32_t PinAttributes); +HAL_StatusTypeDef HAL_GPIO_GetConfigPinAttributes(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, uint32_t *pPinAttributes); + +/** + * @} + */ + +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WBAxx_HAL_GPIO_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_gpio_ex.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_gpio_ex.h new file mode 100644 index 0000000000..25bda94e3a --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_gpio_ex.h @@ -0,0 +1,394 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_gpio_ex.h + * @author MCD Application Team + * @brief Header file of GPIO HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_HAL_GPIO_EX_H +#define STM32WBAxx_HAL_GPIO_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal_def.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @defgroup GPIOEx GPIOEx + * @brief GPIO Extended HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ + +/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants + * @{ + */ + +/** @defgroup GPIOEx_Alternate_function_selection GPIOEx Alternate function selection + * @{ + */ + +#if defined(STM32WBA54xx) || defined(STM32WBA55xx) +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /*!< RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< MCO Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /*!< SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00) /*!< TRACE Alternate Function mapping */ +#define GPIO_AF0_LPTIM1 ((uint8_t)0x00) /*!< LPTIM1 Alternate Function mapping */ +#define GPIO_AF0_PWR ((uint8_t)0x00) /*!< PWR Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01) /*!< TIM2 Alternate Function mapping */ +#define GPIO_AF1_IR ((uint8_t)0x01) /*!< IR Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02) /*!< TIM2 Alternate Function mapping */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02) /*!< TIM3 Alternate Function mapping */ +#define GPIO_AF2_LPTIM1 ((uint8_t)0x02) /*!< LPTIM1 Alternate Function mapping */ +#define GPIO_AF2_LPTIM2 ((uint8_t)0x02) /*!< LPTIM2 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_SAI1 ((uint8_t)0x03) /*!< SAI1 Alternate Function mapping */ +#define GPIO_AF3_USART2 ((uint8_t)0x03) /*!< USART2 Alternate Function mapping */ +#define GPIO_AF3_IR ((uint8_t)0x03) /*!< IR Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /*!< I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C3 ((uint8_t)0x04) /*!< I2C3 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /*!< SPI1 Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_I2C3 ((uint8_t)0x06) /*!< I2C3 Alternate Function mapping */ +#define GPIO_AF6_SPI3 ((uint8_t)0x06) /*!< SPI3 Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_USART1 ((uint8_t)0x07) /*!< USART1 Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_LPUART1 ((uint8_t)0x08) /*!< LPUART1 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_TSC ((uint8_t)0x09) /*!< TSC Alternate Function mapping */ + +/** + * @brief AF 11 selection + */ +#define GPIO_AF11_RF_ANTSW0 ((uint8_t)0x0B) /*!< RF_ANTSW0 Alternate Function mapping */ +#define GPIO_AF11_RF_ANTSW1 ((uint8_t)0x0B) /*!< RF_ANTSW1 Alternate Function mapping */ +#define GPIO_AF11_RF_ANTSW2 ((uint8_t)0x0B) /*!< RF_ANTSW2 Alternate Function mapping */ +#define GPIO_AF11_RF_IO1 ((uint8_t)0x0B) /*!< RF_IO1 Alternate Function mapping */ +#define GPIO_AF11_RF_IO2 ((uint8_t)0x0B) /*!< RF_IO2 Alternate Function mapping */ +#define GPIO_AF11_RF_IO3 ((uint8_t)0x0B) /*!< RF_IO3 Alternate Function mapping */ +#define GPIO_AF11_RF_IO4 ((uint8_t)0x0B) /*!< RF_IO4 Alternate Function mapping */ +#define GPIO_AF11_RF_IO5 ((uint8_t)0x0B) /*!< RF_IO5 Alternate Function mapping */ +#define GPIO_AF11_RF_IO6 ((uint8_t)0x0B) /*!< RF_IO6 Alternate Function mapping */ +#define GPIO_AF11_RF_IO7 ((uint8_t)0x0B) /*!< RF_IO7 Alternate Function mapping */ +#define GPIO_AF11_RF_IO8 ((uint8_t)0x0B) /*!< RF_IO8 Alternate Function mapping */ +#define GPIO_AF11_RF_IO9 ((uint8_t)0x0B) /*!< RF_IO9 Alternate Function mapping */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF12_COMP1 ((uint8_t)0x0C) /*!< COMP1 Alternate Function mapping */ +#define GPIO_AF12_COMP2 ((uint8_t)0x0C) /*!< COMP2 Alternate Function mapping */ + +/** + * @brief AF 13 selection + */ +#define GPIO_AF13_SAI1 ((uint8_t)0x0D) /*!< SAI1 Alternate Function mapping */ +#define GPIO_AF13_LPTIM2 ((uint8_t)0x0D) /*!< LPTIM2 Alternate Function mapping */ + +/** + * @brief AF 14 selection + */ +#define GPIO_AF14_LPTIM2 ((uint8_t)0x0E) /*!< LPTIM2 Alternate Function mapping */ +#define GPIO_AF14_TIM3 ((uint8_t)0x0E) /*!< TIM3 Alternate Function mapping */ +#define GPIO_AF14_TIM16 ((uint8_t)0x0E) /*!< TIM16 Alternate Function mapping */ +#define GPIO_AF14_TIM17 ((uint8_t)0x0E) /*!< TIM17 Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /*!< EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F) + +#endif /* (defined(STM32WBA54xx) || defined(STM32WBA55xx)) */ + +#if defined(STM32WBA52xx) +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /*!< RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< MCO Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /*!< SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00) /*!< TRACE Alternate Function mapping */ +#define GPIO_AF0_LPTIM1 ((uint8_t)0x00) /*!< LPTIM1 Alternate Function mapping */ +#define GPIO_AF0_PWR ((uint8_t)0x00) /*!< PWR Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01) /*!< TIM2 Alternate Function mapping */ +#define GPIO_AF1_IR ((uint8_t)0x01) /*!< IR Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02) /*!< TIM2 Alternate Function mapping */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02) /*!< TIM3 Alternate Function mapping */ +#define GPIO_AF2_LPTIM1 ((uint8_t)0x02) /*!< LPTIM1 Alternate Function mapping */ +#define GPIO_AF2_LPTIM2 ((uint8_t)0x02) /*!< LPTIM2 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_SAI1 ((uint8_t)0x03) /*!< SAI1 Alternate Function mapping */ +#define GPIO_AF3_USART2 ((uint8_t)0x03) /*!< USART2 Alternate Function mapping */ +#define GPIO_AF3_IR ((uint8_t)0x03) /*!< IR Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /*!< I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C3 ((uint8_t)0x04) /*!< I2C3 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05) /*!< SPI1 Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_I2C3 ((uint8_t)0x06) /*!< I2C3 Alternate Function mapping */ +#define GPIO_AF6_SPI3 ((uint8_t)0x06) /*!< SPI3 Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_USART1 ((uint8_t)0x07) /*!< USART1 Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_LPUART1 ((uint8_t)0x08) /*!< LPUART1 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_TSC ((uint8_t)0x09) /*!< TSC Alternate Function mapping */ + +/** + * @brief AF 11 selection + */ +#define GPIO_AF11_RF_ANTSW0 ((uint8_t)0x0B) /*!< RF_ANTSW0 Alternate Function mapping */ +#define GPIO_AF11_RF_ANTSW1 ((uint8_t)0x0B) /*!< RF_ANTSW1 Alternate Function mapping */ +#define GPIO_AF11_RF_ANTSW2 ((uint8_t)0x0B) /*!< RF_ANTSW2 Alternate Function mapping */ +#define GPIO_AF11_RF_IO1 ((uint8_t)0x0B) /*!< RF_IO1 Alternate Function mapping */ +#define GPIO_AF11_RF_IO2 ((uint8_t)0x0B) /*!< RF_IO2 Alternate Function mapping */ +#define GPIO_AF11_RF_IO3 ((uint8_t)0x0B) /*!< RF_IO3 Alternate Function mapping */ +#define GPIO_AF11_RF_IO4 ((uint8_t)0x0B) /*!< RF_IO4 Alternate Function mapping */ +#define GPIO_AF11_RF_IO5 ((uint8_t)0x0B) /*!< RF_IO5 Alternate Function mapping */ +#define GPIO_AF11_RF_IO6 ((uint8_t)0x0B) /*!< RF_IO6 Alternate Function mapping */ +#define GPIO_AF11_RF_IO7 ((uint8_t)0x0B) /*!< RF_IO7 Alternate Function mapping */ +#define GPIO_AF11_RF_IO8 ((uint8_t)0x0B) /*!< RF_IO8 Alternate Function mapping */ +#define GPIO_AF11_RF_IO9 ((uint8_t)0x0B) /*!< RF_IO9 Alternate Function mapping */ + +/** + * @brief AF 13 selection + */ +#define GPIO_AF13_LPTIM2 ((uint8_t)0x0D) /*!< LPTIM2 Alternate Function mapping */ + +/** + * @brief AF 14 selection + */ +#define GPIO_AF14_LPTIM2 ((uint8_t)0x0E) /*!< LPTIM2 Alternate Function mapping */ +#define GPIO_AF14_TIM3 ((uint8_t)0x0E) /*!< TIM3 Alternate Function mapping */ +#define GPIO_AF14_TIM16 ((uint8_t)0x0E) /*!< TIM16 Alternate Function mapping */ +#define GPIO_AF14_TIM17 ((uint8_t)0x0E) /*!< TIM17 Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /*!< EVENTOUT Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F) + +#endif /* (defined(STM32WBA54xx) || defined(STM32WBA55xx)) */ + +#if defined(STM32WBA50xx) +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /*!< RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< MCO Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00) /*!< SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00) /*!< TRACE Alternate Function mapping */ +#define GPIO_AF0_LPTIM1 ((uint8_t)0x00) /*!< LPTIM1 Alternate Function mapping */ +#define GPIO_AF0_PWR ((uint8_t)0x00) /*!< PWR Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01) /*!< TIM2 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02) /*!< TIM2 Alternate Function mapping */ +#define GPIO_AF2_LPTIM1 ((uint8_t)0x02) /*!< LPTIM1 Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_I2C3 ((uint8_t)0x04) /*!< I2C3 Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_I2C3 ((uint8_t)0x06) /*!< I2C3 Alternate Function mapping */ +#define GPIO_AF6_SPI3 ((uint8_t)0x06) /*!< SPI3 Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_USART1 ((uint8_t)0x07) /*!< USART1 Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_LPUART1 ((uint8_t)0x08) /*!< LPUART1 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_TSC ((uint8_t)0x09) /*!< TSC Alternate Function mapping */ + +/** + * @brief AF 11 selection + */ +#define GPIO_AF11_RF_ANTSW0 ((uint8_t)0x0B) /*!< RF_ANTSW0 Alternate Function mapping */ +#define GPIO_AF11_RF_ANTSW1 ((uint8_t)0x0B) /*!< RF_ANTSW1 Alternate Function mapping */ +#define GPIO_AF11_RF_ANTSW2 ((uint8_t)0x0B) /*!< RF_ANTSW2 Alternate Function mapping */ +#define GPIO_AF11_RF_IO1 ((uint8_t)0x0B) /*!< RF_IO1 Alternate Function mapping */ +#define GPIO_AF11_RF_IO2 ((uint8_t)0x0B) /*!< RF_IO2 Alternate Function mapping */ +#define GPIO_AF11_RF_IO3 ((uint8_t)0x0B) /*!< RF_IO3 Alternate Function mapping */ +#define GPIO_AF11_RF_IO4 ((uint8_t)0x0B) /*!< RF_IO4 Alternate Function mapping */ +#define GPIO_AF11_RF_IO5 ((uint8_t)0x0B) /*!< RF_IO5 Alternate Function mapping */ +#define GPIO_AF11_RF_IO6 ((uint8_t)0x0B) /*!< RF_IO6 Alternate Function mapping */ +#define GPIO_AF11_RF_IO7 ((uint8_t)0x0B) /*!< RF_IO7 Alternate Function mapping */ +#define GPIO_AF11_RF_IO8 ((uint8_t)0x0B) /*!< RF_IO8 Alternate Function mapping */ +#define GPIO_AF11_RF_IO9 ((uint8_t)0x0B) /*!< RF_IO9 Alternate Function mapping */ + +/** + * @brief AF 14 selection + */ +#define GPIO_AF14_TIM16 ((uint8_t)0x0E) /*!< TIM16 Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /*!< EVENTOUT Alternate Function mapping */ +#define GPIO_AF15_RF_DTB0 ((uint8_t)0x0F) /*!< RF_DTB0 Alternate Function mapping */ +#define GPIO_AF15_RF_DTB1 ((uint8_t)0x0F) /*!< RF_DTB1 Alternate Function mapping */ +#define GPIO_AF15_RF_DTB2 ((uint8_t)0x0F) /*!< RF_DTB2 Alternate Function mapping */ +#define GPIO_AF15_RF_DTB3 ((uint8_t)0x0F) /*!< RF_DTB3 Alternate Function mapping */ +#define GPIO_AF15_RF_DTB4 ((uint8_t)0x0F) /*!< RF_DTB4 Alternate Function mapping */ +#define GPIO_AF15_RF_DTB5 ((uint8_t)0x0F) /*!< RF_DTB5 Alternate Function mapping */ +#define GPIO_AF15_RF_DTB6 ((uint8_t)0x0F) /*!< RF_DTB6 Alternate Function mapping */ +#define GPIO_AF15_RF_DTB7 ((uint8_t)0x0F) /*!< RF_DTB7 Alternate Function mapping */ + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F) + +#endif /* defined(STM32WBA50xx) */ + + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIOEx_Exported_Macros GPIOEx Exported Macros + * @{ + */ + +/** @defgroup GPIOEx_Get_Port_Index GPIOEx Get Port Index + * @{ + */ +#define GPIO_GET_INDEX(__GPIOx__) (((uint32_t )(__GPIOx__) & (~GPIOA_BASE)) >> 10) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WBAxx_HAL_GPIO_EX_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_gtzc.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_gtzc.h new file mode 100644 index 0000000000..0d756f4de5 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_gtzc.h @@ -0,0 +1,475 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_gtzc.h + * @author MCD Application Team + * @brief Header file of GTZC HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_HAL_GTZC_H +#define STM32WBAxx_HAL_GTZC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal_def.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +#if defined(GTZC_TZSC) && defined(HAL_GTZC_MODULE_ENABLED) + +/** @addtogroup GTZC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup GTZC_Exported_Types GTZC Exported Types + * @{ + */ + +/*!< Values needed for MPCBB_Attribute_ConfigTypeDef structure sizing */ +#if defined (STM32WBA52xx) || defined (STM32WBA54xx) || defined (STM32WBA55xx) +#define GTZC_MPCBB_NB_VCTR_REG_MAX 4U /*!< Maximum number of superblocks */ +#endif +#define GTZC_MPCBB_NB_LCK_VCTR_REG_MAX 1U /*!< Maximum number of 32-bit registers to lock superblocks */ +typedef struct +{ + uint32_t MPCBB_SecConfig_array[GTZC_MPCBB_NB_VCTR_REG_MAX]; /*!< Each element specifies secure access mode for a super-block. + Each bit corresponds to a block inside the super-block. + 0 means non-secure, 1 means secure */ + uint32_t MPCBB_PrivConfig_array[GTZC_MPCBB_NB_VCTR_REG_MAX]; /*!< Each element specifies privilege access mode for a super-block. + Each bit corresponds to a block inside the super-block. + 0 means non-privilege, 1 means privilege */ + uint32_t MPCBB_LockConfig_array[GTZC_MPCBB_NB_LCK_VCTR_REG_MAX]; /*!< Each bit specifies the lock configuration of a super-block (32 blocks). + 0 means unlocked, 1 means locked */ +} MPCBB_Attribute_ConfigTypeDef; + +typedef struct +{ + uint32_t SecureRWIllegalMode; /*!< Secure read/write illegal access + field. It can be a value of @ref GTZC_MPCBB_SecureRWIllegalMode */ + uint32_t InvertSecureState; /*!< Default security state field (can be inverted or not). + It can be a value of @ref GTZC_MPCBB_InvertSecureState */ + MPCBB_Attribute_ConfigTypeDef AttributeConfig; /*!< MPCBB attribute configuration sub-structure */ +} MPCBB_ConfigTypeDef; + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ + +/** @defgroup GTZC_Private_Constants GTZC Private Constants + * @{ + */ + +/** @defgroup GTZC_Private_PeriphId_composition GTZC Peripheral identifier composition + * @{ + */ + +/* composition definition for Peripheral identifier parameter (PeriphId) used in + * HAL_GTZC_TZSC_ConfigPeriphAttributes() and HAL_GTZC_TZSC_GetConfigPeriphAttributes() + * functions and also in all HAL_GTZC_TZIC relative functions. + * Bitmap Definition + * bits[31:28] Field "register". Define the register index a peripheral belongs to. + * Each bit is dedicated to a single register. + * bit[5] Field "all peripherals". If this bit is set then the PeriphId targets + * all peripherals within all registers. + * bits[4:0] Field "bit position". Define the bit position within the + * register dedicated to the peripheral, value from 0 to 31. + */ +#define GTZC_PERIPH_REG_SHIFT (28U) +#define GTZC_PERIPH_REG (0xF0000000U) +#define GTZC_PERIPH_REG1 (0x00000000U) +#define GTZC_PERIPH_REG2 (0x10000000U) +#define GTZC_PERIPH_REG3 (0x20000000U) +#define GTZC_PERIPH_REG4 (0x30000000U) +#define GTZC_PERIPH_BIT_POSITION (0x0000001FU) + +/** + * @} + */ + +/** @defgroup GTZC_Private_Attributes_Msk GTZC Attributes Masks + * @{ + */ +#define GTZC_ATTR_SEC_MASK 0x100U +#define GTZC_ATTR_PRIV_MASK 0x200U + +/** + * @} + */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup GTZC_Exported_Constants GTZC Exported Constants + * @{ + */ + +/** @defgroup GTZC_MPCBB_SecureRWIllegalMode GTZC MPCBB SRWILADIS values + * @{ + */ + +#define GTZC_MPCBB_SRWILADIS_ENABLE 0U +#define GTZC_MPCBB_SRWILADIS_DISABLE GTZC_MPCBB_CR_SRWILADIS_Msk + +/** + * @} + */ + +/** @defgroup GTZC_MPCBB_InvertSecureState GTZC MPCBB INVSECSTATE values + * @{ + */ + +#define GTZC_MPCBB_INVSECSTATE_NOT_INVERTED 0U +#define GTZC_MPCBB_INVSECSTATE_INVERTED GTZC_MPCBB_CR_INVSECSTATE_Msk + +/** + * @} + */ + +/** @defgroup GTZC_TZSC_TZIC_PeriphId GTZC TZSC and TZIC Peripheral identifier values + * @{ + */ +/* GTZC */ +#define GTZC_PERIPH_TIM2 (GTZC_PERIPH_REG1 | GTZC_CFGR1_TIM2_Pos) +#define GTZC_PERIPH_TIM3 (GTZC_PERIPH_REG1 | GTZC_CFGR1_TIM3_Pos) +#define GTZC_PERIPH_WWDG (GTZC_PERIPH_REG1 | GTZC_CFGR1_WWDG_Pos) +#define GTZC_PERIPH_IWDG (GTZC_PERIPH_REG1 | GTZC_CFGR1_IWDG_Pos) +#define GTZC_PERIPH_USART2 (GTZC_PERIPH_REG1 | GTZC_CFGR1_USART2_Pos) +#define GTZC_PERIPH_I2C1 (GTZC_PERIPH_REG1 | GTZC_CFGR1_I2C1_Pos) +#define GTZC_PERIPH_LPTIM2 (GTZC_PERIPH_REG1 | GTZC_CFGR1_LPTIM2_Pos) + +#define GTZC_PERIPH_TIM1 (GTZC_PERIPH_REG2 | GTZC_CFGR2_TIM1_Pos) +#define GTZC_PERIPH_SPI1 (GTZC_PERIPH_REG2 | GTZC_CFGR2_SPI1_Pos) +#define GTZC_PERIPH_USART1 (GTZC_PERIPH_REG2 | GTZC_CFGR2_USART1_Pos) +#define GTZC_PERIPH_TIM16 (GTZC_PERIPH_REG2 | GTZC_CFGR2_TIM16_Pos) +#define GTZC_PERIPH_TIM17 (GTZC_PERIPH_REG2 | GTZC_CFGR2_TIM17_Pos) +#if defined (SAI1) +#define GTZC_PERIPH_SAI1 (GTZC_PERIPH_REG2 | GTZC_CFGR2_SAI1_Pos) +#endif /* SAI1 */ +#define GTZC_PERIPH_SPI3 (GTZC_PERIPH_REG2 | GTZC_CFGR2_SPI3_Pos) +#define GTZC_PERIPH_LPUART1 (GTZC_PERIPH_REG2 | GTZC_CFGR2_LPUART1_Pos) +#define GTZC_PERIPH_I2C3 (GTZC_PERIPH_REG2 | GTZC_CFGR2_I2C3_Pos) +#define GTZC_PERIPH_LPTIM1 (GTZC_PERIPH_REG2 | GTZC_CFGR2_LPTIM1_Pos) +#if defined (COMP1) +#define GTZC_PERIPH_COMP (GTZC_PERIPH_REG2 | GTZC_CFGR2_COMP_Pos) +#endif /* COMP1 */ +#define GTZC_PERIPH_ADC4 (GTZC_PERIPH_REG2 | GTZC_CFGR2_ADC4_Pos) + +#define GTZC_PERIPH_CRC (GTZC_PERIPH_REG3 | GTZC_CFGR3_CRC_Pos) +#define GTZC_PERIPH_TSC (GTZC_PERIPH_REG3 | GTZC_CFGR3_TSC_Pos) +#define GTZC_PERIPH_ICACHE_REG (GTZC_PERIPH_REG3 | GTZC_CFGR3_ICACHE_REG_Pos) +#define GTZC_PERIPH_AES (GTZC_PERIPH_REG3 | GTZC_CFGR3_AES_Pos) +#define GTZC_PERIPH_HASH (GTZC_PERIPH_REG3 | GTZC_CFGR3_HASH_Pos) +#define GTZC_PERIPH_RNG (GTZC_PERIPH_REG3 | GTZC_CFGR3_RNG_Pos) +#define GTZC_PERIPH_SAES (GTZC_PERIPH_REG3 | GTZC_CFGR3_SAES_Pos) +#define GTZC_PERIPH_HSEM (GTZC_PERIPH_REG3 | GTZC_CFGR3_HSEM_Pos) +#define GTZC_PERIPH_PKA (GTZC_PERIPH_REG3 | GTZC_CFGR3_PKA_Pos) +#define GTZC_PERIPH_RAMCFG (GTZC_PERIPH_REG3 | GTZC_CFGR3_RAMCFG_Pos) +#define GTZC_PERIPH_RADIO (GTZC_PERIPH_REG3 | GTZC_CFGR3_RADIO_Pos) +#if defined (PTACONV) +#define GTZC_PERIPH_PTACONV (GTZC_PERIPH_REG3 | GTZC_CFGR3_PTACONV_Pos) +#endif /* PTACONV */ + +#define GTZC_PERIPH_GPDMA1 (GTZC_PERIPH_REG4 | GTZC_CFGR4_GPDMA1_Pos) +#define GTZC_PERIPH_FLASH (GTZC_PERIPH_REG4 | GTZC_CFGR4_FLASH_Pos) +#define GTZC_PERIPH_FLASH_REG (GTZC_PERIPH_REG4 | GTZC_CFGR4_FLASH_REG_Pos) +#define GTZC_PERIPH_SYSCFG (GTZC_PERIPH_REG4 | GTZC_CFGR4_SYSCFG_Pos) +#define GTZC_PERIPH_RTC (GTZC_PERIPH_REG4 | GTZC_CFGR4_RTC_Pos) +#define GTZC_PERIPH_TAMP (GTZC_PERIPH_REG4 | GTZC_CFGR4_TAMP_Pos) +#define GTZC_PERIPH_PWR (GTZC_PERIPH_REG4 | GTZC_CFGR4_PWR_Pos) +#define GTZC_PERIPH_RCC (GTZC_PERIPH_REG4 | GTZC_CFGR4_RCC_Pos) +#define GTZC_PERIPH_EXTI (GTZC_PERIPH_REG4 | GTZC_CFGR4_EXTI_Pos) +#define GTZC_PERIPH_TZSC (GTZC_PERIPH_REG4 | GTZC_CFGR4_TZSC_Pos) +#define GTZC_PERIPH_TZIC (GTZC_PERIPH_REG4 | GTZC_CFGR4_TZIC_Pos) +#define GTZC_PERIPH_SRAM1 (GTZC_PERIPH_REG4 | GTZC_CFGR4_SRAM1_Pos) +#define GTZC_PERIPH_MPCBB1_REG (GTZC_PERIPH_REG4 | GTZC_CFGR4_MPCBB1_REG_Pos) +#define GTZC_PERIPH_SRAM2 (GTZC_PERIPH_REG4 | GTZC_CFGR4_SRAM2_Pos) +#define GTZC_PERIPH_MPCBB2_REG (GTZC_PERIPH_REG4 | GTZC_CFGR4_MPCBB2_REG_Pos) +#define GTZC_PERIPH_SRAM6 (GTZC_PERIPH_REG4 | GTZC_CFGR4_SRAM6_Pos) +#define GTZC_PERIPH_MPCBB6_REG (GTZC_PERIPH_REG4 | GTZC_CFGR4_MPCBB6_REG_Pos) + +#define GTZC_PERIPH_ALL (0x00000020U) + +/* Note that two maximum values are also defined here: + * - max number of securable AHB/APB peripherals or masters + * (used in TZSC sub-block) + * - max number of securable and TrustZone-aware AHB/APB peripherals or masters + * (used in TZIC sub-block) + */ +#if defined (PTACONV) +#define GTZC_TZSC_PERIPH_NUMBER (HAL_GTZC_GET_ARRAY_INDEX(GTZC_PERIPH_PTACONV) + 1U) +#else +#define GTZC_TZSC_PERIPH_NUMBER (HAL_GTZC_GET_ARRAY_INDEX(GTZC_PERIPH_RADIO) + 1U) +#endif /* PTACONV */ +#define GTZC_TZIC_PERIPH_NUMBER (HAL_GTZC_GET_ARRAY_INDEX(GTZC_PERIPH_MPCBB6_REG) + 1U) + +/** + * @} + */ + +/** @defgroup GTZC_TZSC_PeriphAttributes GTZC TZSC peripheral attribute values + * @{ + */ + +/* user-oriented definitions for attribute parameter (PeriphAttributes) used in + * HAL_GTZC_TZSC_ConfigPeriphAttributes() and HAL_GTZC_TZSC_GetConfigPeriphAttributes() + * functions + */ +#define GTZC_TZSC_PERIPH_SEC (GTZC_ATTR_SEC_MASK | 0x00000001U) /*!< Secure attribute */ +#define GTZC_TZSC_PERIPH_NSEC (GTZC_ATTR_SEC_MASK | 0x00000000U) /*!< Non-secure attribute */ +#define GTZC_TZSC_PERIPH_PRIV (GTZC_ATTR_PRIV_MASK | 0x00000002U) /*!< Privilege attribute */ +#define GTZC_TZSC_PERIPH_NPRIV (GTZC_ATTR_PRIV_MASK | 0x00000000U) /*!< Non-privilege attribute */ + +/** + * @} + */ + +/** @defgroup GTZC_TZSC_Lock GTZC TZSC lock values + * @{ + */ + +/* user-oriented definitions for HAL_GTZC_TZSC_GetLock() returned value */ +#define GTZC_TZSC_LOCK_OFF 0U +#define GTZC_TZSC_LOCK_ON GTZC_TZSC_CR_LCK_Msk + +/** + * @} + */ + +/** @defgroup GTZC_MPCBB_Group GTZC MPCBB values + * @{ + */ + +/* user-oriented definitions for MPCBB */ +#define GTZC_MPCBB_BLOCK_SIZE 0x200U /* 512 Bytes */ +#define GTZC_MPCBB_SUPERBLOCK_SIZE (GTZC_MPCBB_BLOCK_SIZE * 32U) /* 16 KBytes */ +#define GTZC_MCPBB_SUPERBLOCK_UNLOCKED 0U +#define GTZC_MCPBB_SUPERBLOCK_LOCKED 1U + +#define GTZC_MCPBB_BLOCK_NSEC (GTZC_ATTR_SEC_MASK | 0U) +#define GTZC_MCPBB_BLOCK_SEC (GTZC_ATTR_SEC_MASK | 1U) +#define GTZC_MCPBB_BLOCK_NPRIV (GTZC_ATTR_PRIV_MASK | 0U) +#define GTZC_MCPBB_BLOCK_PRIV (GTZC_ATTR_PRIV_MASK | 2U) + +/* user-oriented definitions for HAL_GTZC_MPCBB_GetLock() returned value */ +#define GTZC_MCPBB_LOCK_OFF 0U +#define GTZC_MCPBB_LOCK_ON 1U + +/** + * @} + */ + +/** @defgroup GTZC_TZIC_Flag GTZC TZIC flag values + * @{ + */ + +/* user-oriented definitions for HAL_GTZC_TZIC_GetFlag() flag parameter */ +#define GTZC_TZIC_NO_ILA_EVENT 0U +#define GTZC_TZIC_ILA_EVENT_PENDING 1U + +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ + +/** @defgroup GTZC_Private_Macros GTZC Private Macros + * @{ + */ + +/* retrieve information to access register for a specific PeriphId */ +#define GTZC_GET_REG_INDEX(periph_id)\ + (((periph_id) & GTZC_PERIPH_REG) >> GTZC_PERIPH_REG_SHIFT) +#define GTZC_GET_REG_INDEX_IN_INSTANCE(periph_id)\ + ((((periph_id) & GTZC_PERIPH_REG) <= GTZC_PERIPH_REG4) ? \ + (((periph_id) & GTZC_PERIPH_REG) >> GTZC_PERIPH_REG_SHIFT) : \ + ((((periph_id) & GTZC_PERIPH_REG) >> GTZC_PERIPH_REG_SHIFT) - 4U)) +#define GTZC_GET_PERIPH_POS(periph_id) ((periph_id) & GTZC_PERIPH_BIT_POSITION) + +#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define IS_GTZC_BASE_ADDRESS(mem, address)\ + ( ( (uint32_t)(address) == (uint32_t)GTZC_BASE_ADDRESS_NS(mem) ) || \ + ( (uint32_t)(address) == (uint32_t)GTZC_BASE_ADDRESS_S(mem) ) ) +#else +#define IS_GTZC_BASE_ADDRESS(mem, address)\ + ( (uint32_t)(address) == (uint32_t)GTZC_BASE_ADDRESS_NS(mem) ) +#endif /* #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/* MISRA C:2012 Rule-20.10 deviation granted to use the definition of */ +/* GTZC_MEM_SIZE(), GTZC_BASE_ADDRESS_S() and GTZC_BASE_ADDRESS_NS() */ +#define GTZC_MEM_SIZE(mem)\ + ( mem ## _SIZE ) + +#define GTZC_BASE_ADDRESS_S(mem)\ + ( mem ## _BASE_S ) + +#define GTZC_BASE_ADDRESS_NS(mem)\ + ( mem ## _BASE_NS ) + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ + +/** @defgroup GTZC_Exported_Macros GTZC Exported Macros + * @{ + */ + +/* user-oriented macro to get array index of a specific PeriphId + * in case of GTZC_PERIPH_ALL usage in the two following functions: + * HAL_GTZC_TZSC_ConfigPeriphAttributes() and HAL_GTZC_TZSC_GetConfigPeriphAttributes() + */ +#define HAL_GTZC_GET_ARRAY_INDEX(periph_id) \ + ((GTZC_GET_REG_INDEX((periph_id)) * 32U) + GTZC_GET_PERIPH_POS((periph_id))) + +#define HAL_GTZC_TZSC_GET_ARRAY_INDEX(periph_id) \ + (((GTZC_GET_REG_INDEX(periph_id) * 32U) + GTZC_GET_PERIPH_POS(periph_id))) + +#define HAL_GTZC_TZIC_GET_ARRAY_INDEX(periph_id) \ + ((GTZC_GET_REG_INDEX((periph_id)) * 32U) + GTZC_GET_PERIPH_POS((periph_id))) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup GTZC_Exported_Functions + * @{ + */ + +/** @addtogroup GTZC_Exported_Functions_Group1 + * @brief TZSC Initialization and Configuration functions + * @{ + */ + +HAL_StatusTypeDef HAL_GTZC_TZSC_ConfigPeriphAttributes(uint32_t PeriphId, + uint32_t PeriphAttributes); +HAL_StatusTypeDef HAL_GTZC_TZSC_GetConfigPeriphAttributes(uint32_t PeriphId, + uint32_t *PeriphAttributes); + +/** + * @} + */ + +#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** @addtogroup GTZC_Exported_Functions_Group3 + * @brief TZSC and TZSC-MPCWM Lock functions + * @{ + */ + +void HAL_GTZC_TZSC_Lock(GTZC_TZSC_TypeDef *TZSC_Instance); +uint32_t HAL_GTZC_TZSC_GetLock(const GTZC_TZSC_TypeDef *TZSC_Instance); + +/** + * @} + */ +#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/** @addtogroup GTZC_Exported_Functions_Group4 + * @brief MPCBB Initialization and Configuration functions + * @{ + */ + +HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMem(uint32_t MemBaseAddress, + const MPCBB_ConfigTypeDef *pMPCBB_desc); +HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMem(uint32_t MemBaseAddress, + MPCBB_ConfigTypeDef *pMPCBB_desc); +HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMemAttributes(uint32_t MemAddress, + uint32_t NbBlocks, + const uint32_t *pMemAttributes); +HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMemAttributes(uint32_t MemAddress, + uint32_t NbBlocks, + uint32_t *pMemAttributes); + +#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +HAL_StatusTypeDef HAL_GTZC_MPCBB_LockConfig(uint32_t MemAddress, + uint32_t NbSuperBlocks, + const uint32_t *pLockAttributes); +HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLockConfig(uint32_t MemAddress, + uint32_t NbSuperBlocks, + uint32_t *pLockAttributes); +HAL_StatusTypeDef HAL_GTZC_MPCBB_Lock(uint32_t MemBaseAddress); +HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLock(uint32_t MemBaseAddress, + uint32_t *pLockState); +#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/** + * @} + */ + +#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** @addtogroup GTZC_Exported_Functions_Group5 + * @brief TZIC functions + * @{ + */ + +HAL_StatusTypeDef HAL_GTZC_TZIC_DisableIT(uint32_t PeriphId); +HAL_StatusTypeDef HAL_GTZC_TZIC_EnableIT(uint32_t PeriphId); +HAL_StatusTypeDef HAL_GTZC_TZIC_GetFlag(uint32_t PeriphId, uint32_t *pFlag); +HAL_StatusTypeDef HAL_GTZC_TZIC_ClearFlag(uint32_t PeriphId); + +/** + * @} + */ + +/** @addtogroup GTZC_Exported_Functions_Group6 + * @brief IRQ related Functions + * @{ + */ + +void HAL_GTZC_IRQHandler(void); +void HAL_GTZC_TZIC_Callback(uint32_t PeriphId); + +/** + * @} + */ + +#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(GTZC_TZSC) && defined(HAL_GTZC_MODULE_ENABLED) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WBAxx_HAL_GTZC_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_hash.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_hash.h new file mode 100644 index 0000000000..7ee602ab7f --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_hash.h @@ -0,0 +1,566 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_hash.h + * @author MCD Application Team + * @brief Header file of HASH HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_HAL_HASH_H +#define STM32WBAxx_HAL_HASH_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal_def.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ +#if defined (HASH) +/** @defgroup HASH HASH + * @brief HASH HAL module driver. + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup HASH_Exported_Types HASH Exported Types + * @{ + */ + +/** + * @brief HASH Configuration Structure definition + */ +typedef struct +{ + uint32_t DataType; /*!< no swap (32-bit data), half word swap (16-bit data), byte swap (8-bit data) or bit swap + (1-bit data). This parameter can be a value of @ref HASH_Data_Type. */ + + uint32_t KeySize; /*!< The key size is used only in HMAC operation. */ + + uint8_t *pKey; /*!< The key is used only in HMAC operation. */ + + uint32_t Algorithm; /*!< HASH algorithm MD5, SHA1 or SHA2. + This parameter can be a value of @ref HASH_Algorithm_Selection */ + + +} HASH_ConfigTypeDef; + +/** + * @brief HAL State structure definition + */ +typedef enum +{ + HAL_HASH_STATE_RESET = 0x00U, /*!< Peripheral is not initialized */ + HAL_HASH_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_HASH_STATE_BUSY = 0x02U, /*!< Processing (hashing) is ongoing */ + HAL_HASH_STATE_SUSPENDED = 0x03U /*!< Suspended state */ +} HAL_HASH_StateTypeDef; + +/** + * @brief HAL phase structure definition + */ +typedef enum +{ + HAL_HASH_PHASE_READY = 0x01U, /*!< HASH peripheral is ready to start */ + HAL_HASH_PHASE_PROCESS = 0x02U, /*!< HASH peripheral is in HASH processing phase */ + HAL_HASH_PHASE_HMAC_STEP_1 = 0x03U, /*!< HASH peripheral is in HMAC step 1 processing phase + (step 1 consists in entering the inner hash function key)*/ + HAL_HASH_PHASE_HMAC_STEP_2 = 0x04U, /*!< HASH peripheral is in HMAC step 2 processing phase + (step 2 consists in entering the message text) */ + HAL_HASH_PHASE_HMAC_STEP_3 = 0x05U /*!< HASH peripheral is in HMAC step 3 processing phase + (step 3 consists in entering the outer hash function key)*/ + +} HAL_HASH_PhaseTypeDef; + +#if (USE_HAL_HASH_SUSPEND_RESUME == 1U) +/** + * @brief HAL HASH mode suspend definitions + */ +typedef enum +{ + HAL_HASH_SUSPEND_NONE = 0x00U, /*!< HASH peripheral suspension not requested */ + HAL_HASH_SUSPEND = 0x01U /*!< HASH peripheral suspension is requested */ +} HAL_HASH_SuspendTypeDef; +#endif /* USE_HAL_HASH_SUSPEND_RESUME */ + + +/** + * @brief HASH Handle Structure definition + */ +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) +typedef struct __HASH_HandleTypeDef +#else +typedef struct +#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */ +{ + HASH_TypeDef *Instance; /*!< HASH Register base address */ + + HASH_ConfigTypeDef Init; /*!< HASH required parameters */ + + uint8_t const *pHashInBuffPtr; /*!< Pointer to input buffer */ + + uint8_t *pHashOutBuffPtr; /*!< Pointer to output buffer (digest) */ + + __IO uint32_t HashInCount; /*!< Counter of inputted data */ + + uint32_t Size; /*!< Size of buffer to be processed in bytes */ + + uint8_t *pHashKeyBuffPtr; /*!< Pointer to key buffer (HMAC only) */ + + HAL_HASH_PhaseTypeDef Phase; /*!< HASH peripheral phase */ + + DMA_HandleTypeDef *hdmain; /*!< HASH In DMA Handle parameters */ + + HAL_LockTypeDef Lock; /*!< Locking object */ + + __IO uint32_t ErrorCode; /*!< HASH Error code */ + + __IO HAL_HASH_StateTypeDef State; /*!< HASH peripheral state */ + + __IO uint32_t Accumulation; /*!< HASH multi buffers accumulation flag */ + +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) + void (* InCpltCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH input completion callback */ + + void (* DgstCpltCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH digest computation complete callback */ + + void (* ErrorCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH error callback */ + + void (* MspInitCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH Msp Init callback */ + + void (* MspDeInitCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH Msp DeInit callback */ + +#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */ +#if (USE_HAL_HASH_SUSPEND_RESUME == 1U) + __IO HAL_HASH_SuspendTypeDef SuspendRequest; /*!< HASH peripheral suspension request flag */ + + HASH_ConfigTypeDef Init_saved; /*!< Saved HASH required parameters */ + + uint8_t const *pHashInBuffPtr_saved; /*!< Saved pointer to input buffer */ + + uint8_t *pHashOutBuffPtr_saved; /*!< Saved pointer to output buffer (digest) */ + + __IO uint32_t HashInCount_saved; /*!< Saved counter of inputted data */ + + uint32_t Size_saved; /*!< Saved size of buffer to be processed */ + + uint8_t *pHashKeyBuffPtr_saved; /*!< Saved pointer to key buffer (HMAC only) */ + + HAL_HASH_PhaseTypeDef Phase_saved; /*!< Saved HASH peripheral phase */ +#endif /* USE_HAL_HASH_SUSPEND_RESUME */ + +} HASH_HandleTypeDef; + +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U) +/** + * @brief HAL HASH common Callback ID enumeration definition + */ +typedef enum +{ + HAL_HASH_MSPINIT_CB_ID = 0x00U, /*!< HASH MspInit callback ID */ + HAL_HASH_MSPDEINIT_CB_ID = 0x01U, /*!< HASH MspDeInit callback ID */ + HAL_HASH_INPUTCPLT_CB_ID = 0x02U, /*!< HASH input completion callback ID */ + HAL_HASH_DGSTCPLT_CB_ID = 0x03U, /*!< HASH digest computation completion callback ID */ + HAL_HASH_ERROR_CB_ID = 0x04U, /*!< HASH error callback ID */ +} HAL_HASH_CallbackIDTypeDef; + +/** + * @brief HAL HASH Callback pointer definition + */ +typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef *hhash); /*!< pointer to a HASH common callback functions */ + +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ + + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup HASH_Exported_Constants HASH Exported Constants + * @{ + */ + +/** @defgroup HASH_Error_Definition HASH Error Definition + * @{ + */ +#define HAL_HASH_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_HASH_ERROR_BUSY 0x00000001U /*!< Busy flag error */ +#define HAL_HASH_ERROR_DMA 0x00000002U /*!< DMA-based process error */ +#define HAL_HASH_ERROR_TIMEOUT 0x00000004U /*!< Timeout error */ +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U) +#define HAL_HASH_ERROR_INVALID_CALLBACK 0x00000010U /*!< Invalid Callback error */ +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup HASH_Algorithm_Selection HASH algorithm selection + * @{ + */ +#define HASH_ALGOSELECTION_SHA1 0x00000000U /*!< HASH function is SHA1 */ +#define HASH_ALGOSELECTION_MD5 HASH_CR_ALGO_0 /*!< HASH function is MD5 */ +#define HASH_ALGOSELECTION_SHA224 HASH_CR_ALGO_1 /*!< HASH function is SHA224 */ +#define HASH_ALGOSELECTION_SHA256 HASH_CR_ALGO /*!< HASH function is SHA256 */ +/** + * @} + */ + +/** @defgroup HASH_Mode HASH Mode + * @{ + */ +#define HASH_ALGOMODE_HASH 0x00000000U /*!< HASH mode */ +#define HASH_ALGOMODE_HMAC HASH_CR_MODE /*!< HMAC mode */ +/** + * @} + */ + +/** @defgroup HASH_Data_Type HASH Data Type + * @{ + */ +#define HASH_NO_SWAP 0x00000000U /*!< 32-bit data. No swapping */ +#define HASH_HALFWORD_SWAP HASH_CR_DATATYPE_0 /*!< 16-bit data. Each half word is swapped */ +#define HASH_BYTE_SWAP HASH_CR_DATATYPE_1 /*!< 8-bit data. All bytes are swapped */ +#define HASH_BIT_SWAP HASH_CR_DATATYPE /*!< 1-bit data. In the word all bits are swapped */ +/** + * @} + */ + +/** @defgroup HASH_HMAC_KEY key length only for HMAC mode + * @{ + */ +#define HASH_SHORTKEY 0x00000000U /*!< HMAC Key size is <= block size (64 or 128 bytes) */ +#define HASH_LONGKEY HASH_CR_LKEY /*!< HMAC Key size is > block size (64 or 128 bytes) */ +/** + * @} + */ + +/** @defgroup HASH_flags_definition HASH flags definitions + * @{ + */ +#define HASH_FLAG_DINIS HASH_SR_DINIS /*!< 16 locations are free in the DIN : new block can be entered + in the Peripheral */ +#define HASH_FLAG_DCIS HASH_SR_DCIS /*!< Digest calculation complete */ +#define HASH_FLAG_DMAS HASH_SR_DMAS /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing */ +#define HASH_FLAG_BUSY HASH_SR_BUSY /*!< The hash core is Busy, processing a block of data */ +#define HASH_FLAG_DINNE HASH_CR_DINNE /*!< DIN not empty : input buffer contains at least one word of data*/ +/** + * @} + */ + +/** @defgroup HASH_interrupts_definition HASH interrupts definitions + * @{ + */ +#define HASH_IT_DINI HASH_IMR_DINIE /*!< A new block can be entered into the input buffer (DIN) */ +#define HASH_IT_DCI HASH_IMR_DCIE /*!< Digest calculation complete */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup HASH_Exported_Macros HASH Exported Macros + * @{ + */ + +/** @brief Check whether or not the specified HASH flag is set. + * @param __HANDLE__ specifies the HASH handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref HASH_FLAG_DINIS A new block can be entered into the input buffer. + * @arg @ref HASH_FLAG_DCIS Digest calculation complete. + * @arg @ref HASH_FLAG_DMAS DMA interface is enabled (DMAE=1) or a transfer is ongoing. + * @arg @ref HASH_FLAG_BUSY The hash core is Busy : processing a block of data. + * @arg @ref HASH_FLAG_DINNE DIN not empty : the input buffer contains at least one word of data. + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_HASH_GET_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) > 8U) ? \ + (((__HANDLE__)->Instance->CR & (__FLAG__)) == (__FLAG__)) :\ + (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) ) + +/** @brief Clear the specified HASH flag. + * @param __HANDLE__ specifies the HASH handle. + * @param __FLAG__ specifies the flag to clear. + * This parameter can be one of the following values: + * @arg @ref HASH_FLAG_DINIS A new block can be entered into the input buffer. + * @arg @ref HASH_FLAG_DCIS Digest calculation complete + * @retval None + */ +#define __HAL_HASH_CLEAR_FLAG(__HANDLE__, __FLAG__) CLEAR_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) + +/** @brief Check whether the specified HASH interrupt source is enabled or not. + * @param __HANDLE__ specifies the HASH handle. + * @param __INTERRUPT__ HASH interrupt source to check + * This parameter can be one of the following values : + * @arg @ref HASH_IT_DINI A new block can be entered into the input buffer (DIN) + * @arg @ref HASH_IT_DCI Digest calculation complete + * @retval State of interruption (TRUE or FALSE). + */ +#define __HAL_HASH_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMR\ + & (__INTERRUPT__)) == (__INTERRUPT__)) + +/** @brief Enable the specified HASH interrupt. + * @param __HANDLE__ specifies the HASH handle. + * @param __INTERRUPT__ specifies the HASH interrupt source to enable. + * This parameter can be one of the following values: + * @arg @ref HASH_IT_DINI A new block can be entered into the input buffer (DIN) + * @arg @ref HASH_IT_DCI Digest calculation complete + * @retval None + */ +#define __HAL_HASH_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->IMR, (__INTERRUPT__)) + +/** @brief Disable the specified HASH interrupt. + * @param __HANDLE__ specifies the HASH handle. + * @param __INTERRUPT__ specifies the HASH interrupt source to disable. + * This parameter can be one of the following values: + * @arg @ref HASH_IT_DINI A new block can be entered into the input buffer (DIN) + * @arg @ref HASH_IT_DCI Digest calculation complete + * @retval None + */ +#define __HAL_HASH_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->IMR, (__INTERRUPT__)) + +/** @brief Reset HASH handle state. + * @param __HANDLE__ HASH handle. + * @retval None + */ +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) +#define __HAL_HASH_RESET_HANDLE_STATE(__HANDLE__) do{\ + (__HANDLE__)->State = HAL_HASH_STATE_RESET;\ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + }while(0) +#else +#define __HAL_HASH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HASH_STATE_RESET) +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ + +/** + * @brief Enable the multi-buffer DMA transfer mode. + * @note This bit is set when hashing large files when multiple DMA transfers are needed. + * @retval None + */ +#define __HAL_HASH_SET_MDMAT() SET_BIT(HASH->CR, HASH_CR_MDMAT) + +/** + * @brief Disable the multi-buffer DMA transfer mode. + * @retval None + */ +#define __HAL_HASH_RESET_MDMAT() CLEAR_BIT(HASH->CR, HASH_CR_MDMAT) + +/** + * @brief HAL HASH driver version. + * @retval None + */ +#define HAL_HASH_VERSION 200 /*!< HAL HASH driver version 2.0.0*/ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup HASH_Exported_Functions HASH Exported Functions + * @{ + */ + +/** @addtogroup HASH_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash); +HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash); +void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash); +void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash); +HAL_StatusTypeDef HAL_HASH_GetConfig(HASH_HandleTypeDef *hhash, HASH_ConfigTypeDef *pConf); +HAL_StatusTypeDef HAL_HASH_SetConfig(HASH_HandleTypeDef *hhash, HASH_ConfigTypeDef *pConf); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_HASH_RegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID, + pHASH_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ + +HAL_StatusTypeDef HAL_HASH_ProcessSuspend(HASH_HandleTypeDef *hhash); +void HAL_HASH_Resume(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer); +void HAL_HASH_Suspend(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer); +/** + * @} + */ + +/** @addtogroup HASH_Exported_Functions_Group2 HASH processing functions + * @{ + */ + +HAL_StatusTypeDef HAL_HASH_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *const pOutBuffer, + uint32_t Timeout); +HAL_StatusTypeDef HAL_HASH_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *const pOutBuffer); +HAL_StatusTypeDef HAL_HASH_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *const pOutBuffer); + +HAL_StatusTypeDef HAL_HASH_Accumulate(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint32_t Timeout); +HAL_StatusTypeDef HAL_HASH_AccumulateLast(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *const pOutBuffer, + uint32_t Timeout); +HAL_StatusTypeDef HAL_HASH_AccumulateLast_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *const pOutBuffer); +HAL_StatusTypeDef HAL_HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); + +/** + * @} + */ + +/** @addtogroup HASH_Exported_Functions_Group3 HMAC processing functions + * @{ + */ +HAL_StatusTypeDef HAL_HASH_HMAC_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *const pOutBuffer, + uint32_t Timeout); +HAL_StatusTypeDef HAL_HASH_HMAC_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *const pOutBuffer); +HAL_StatusTypeDef HAL_HASH_HMAC_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *const pOutBuffer); + +HAL_StatusTypeDef HAL_HASH_HMAC_Accumulate(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint32_t Timeout); +HAL_StatusTypeDef HAL_HASH_HMAC_AccumulateLast(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *const pOutBuffer, uint32_t Timeout); +HAL_StatusTypeDef HAL_HASH_HMAC_Accumulate_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASH_HMAC_AccumulateLast_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, + uint32_t Size, uint8_t *const pOutBuffer); + +/** + * @} + */ + +/** @addtogroup HASH_Exported_Functions_Group4 HASH IRQ handler management + * @{ + */ +void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash); +void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash); +void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash); +void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash); +HAL_HASH_StateTypeDef HAL_HASH_GetState(const HASH_HandleTypeDef *hhash); +uint32_t HAL_HASH_GetError(const HASH_HandleTypeDef *hhash); + +/** + * @} + */ + +/** + * @} + */ + +/* Private macros --------------------------------------------------------*/ +/** @defgroup HASH_Private_Macros HASH Private Macros + * @{ + */ + +/** + * @brief Return digest length in bytes. + * @retval Digest length + */ +#define HASH_DIGEST_LENGTH(__HANDLE__) (((READ_BIT((__HANDLE__)->Instance->CR, HASH_CR_ALGO) \ + == HASH_ALGOSELECTION_MD5) ? 16U : \ + ((READ_BIT((__HANDLE__)->Instance->CR, HASH_CR_ALGO) \ + == HASH_ALGOSELECTION_SHA1) ? 20U : \ + ((READ_BIT((__HANDLE__)->Instance->CR, HASH_CR_ALGO) \ + == HASH_ALGOSELECTION_SHA224) ? 28U : \ + ((READ_BIT((__HANDLE__)->Instance->CR, HASH_CR_ALGO) \ + == HASH_ALGOSELECTION_SHA256) ? 32U : 16U) )))) + + +/** + * @brief Ensure that HASH input data type is valid. + * @param __DATATYPE__ HASH input data type. + * @retval SET (__DATATYPE__ is valid) or RESET (__DATATYPE__ is invalid) + */ +#define IS_HASH_DATATYPE(__DATATYPE__) (((__DATATYPE__) == HASH_NO_SWAP)|| \ + ((__DATATYPE__) == HASH_HALFWORD_SWAP)|| \ + ((__DATATYPE__) == HASH_BYTE_SWAP) || \ + ((__DATATYPE__) == HASH_BIT_SWAP)) + +/** + * @brief Ensure that HASH input algorithm is valid. + * @param __ALGORITHM__ HASH algorithm. + * @retval SET (__ALGORITHM__ is valid) or RESET (__ALGORITHM__ is invalid) + */ +#define IS_HASH_ALGORITHM(__ALGORITHM__) (((__ALGORITHM__) == HASH_ALGOSELECTION_SHA1)|| \ + ((__ALGORITHM__) == HASH_ALGOSELECTION_MD5)|| \ + ((__ALGORITHM__) == HASH_ALGOSELECTION_SHA224)|| \ + ((__ALGORITHM__) == HASH_ALGOSELECTION_SHA256)) + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup HASH_Private_Constants HASH Private Constants + * @{ + */ + +/** + * @} + */ +/* Private defines -----------------------------------------------------------*/ +/** @defgroup HASH_Private_Defines HASH Private Defines + * @{ + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup HASH_Private_Variables HASH Private Variables + * @{ + */ + +/** + * @} + */ +/* Private functions -----------------------------------------------------------*/ + +/** @addtogroup HASH_Private_Functions HASH Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* HASH*/ +/** + * @} + */ + + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32WBAxx_HAL_HASH_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_hsem.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_hsem.h new file mode 100644 index 0000000000..c55dfa9be9 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_hsem.h @@ -0,0 +1,238 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_hsem.h + * @author MCD Application Team + * @brief Header file of HSEM HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_HAL_HSEM_H +#define STM32WBAxx_HAL_HSEM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal_def.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @addtogroup HSEM + * @{ + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup HSEM_Exported_Constants HSEM + * @{ + */ +/** @defgroup HSEM_Attributes HSEM Attributes + * @brief HSEM Privilege/NPrivilege and Secure/NSecure Attributes + * @{ + */ +#define HSEM_NSEC_PRIV HSEM_R_PRIV /*!< NSecure and Privileged attribute */ +#define HSEM_NSEC_NPRIV 0x0U /*!< NSecure and NPrivileged attribute */ +#define HSEM_SEC_PRIV (HSEM_R_SEC | HSEM_R_PRIV) /*!< Secure and Privileged attribute */ +#define HSEM_SEC_NPRIV HSEM_R_SEC /*!< Secure and NPrivileged attribute */ +/** + * @} + */ + +/** + * @} + */ +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup HSEM_Exported_Macros HSEM Exported Macros + * @{ + */ + +/** + * @brief SemID to mask helper Macro. + * @param __SEMID__: semaphore ID from 0 to 15 + * @retval Semaphore Mask. + */ +#define __HAL_HSEM_SEMID_TO_MASK(__SEMID__) (1 << (__SEMID__)) + +/** + * @brief Enables the specified HSEM interrupts. + * @param __SEM_MASK__: semaphores Mask + * @retval None. + */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define __HAL_HSEM_ENABLE_IT(__SEM_MASK__) (HSEM->SIER |= (__SEM_MASK__)) +#else +#define __HAL_HSEM_ENABLE_IT(__SEM_MASK__) (HSEM->IER |= (__SEM_MASK__)) +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/** + * @brief Disables the specified HSEM interrupts. + * @param __SEM_MASK__: semaphores Mask + * @retval None. + */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define __HAL_HSEM_DISABLE_IT(__SEM_MASK__) (HSEM->SIER &= ~(__SEM_MASK__)) +#else +#define __HAL_HSEM_DISABLE_IT(__SEM_MASK__) (HSEM->IER &= ~(__SEM_MASK__)) +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/** + * @brief Checks whether interrupt has occurred or not for semaphores specified by a mask. + * @param __SEM_MASK__: semaphores Mask + * @retval semaphores Mask : Semaphores where an interrupt occurred. + */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define __HAL_HSEM_GET_IT(__SEM_MASK__) ((__SEM_MASK__) & HSEM->SMISR) +#else +#define __HAL_HSEM_GET_IT(__SEM_MASK__) ((__SEM_MASK__) & HSEM->MISR) +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/** + * @brief Get the semaphores release status flags. + * @param __SEM_MASK__: semaphores Mask + * @retval semaphores Mask : Semaphores where Release flags rise. + */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define __HAL_HSEM_GET_FLAG(__SEM_MASK__) ((__SEM_MASK__) & HSEM->SISR) +#else +#define __HAL_HSEM_GET_FLAG(__SEM_MASK__) ((__SEM_MASK__) & HSEM->ISR) +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/** + * @brief Clears the HSEM Interrupt flags. + * @param __SEM_MASK__: semaphores Mask + * @retval None. + */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define __HAL_HSEM_CLEAR_FLAG(__SEM_MASK__) (HSEM->SICR |= (__SEM_MASK__)) +#else +#define __HAL_HSEM_CLEAR_FLAG(__SEM_MASK__) (HSEM->ICR |= (__SEM_MASK__)) +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup HSEM_Exported_Functions HSEM Exported Functions + * @{ + */ + +/** @addtogroup HSEM_Exported_Functions_Group1 Take and Release functions + * @brief HSEM Take and Release functions + * @{ + */ + +/* HSEM semaphore take (lock) using 2-Step method ****************************/ +HAL_StatusTypeDef HAL_HSEM_Take(uint32_t SemID, uint32_t ProcessID, uint32_t Attribute); +/* HSEM semaphore fast take (lock) using 1-Step method ***********************/ +HAL_StatusTypeDef HAL_HSEM_FastTake(uint32_t SemID, uint32_t Attribute); +/* HSEM Release **************************************************************/ +void HAL_HSEM_Release(uint32_t SemID, uint32_t ProcessID, uint32_t Attribute); +/* HSEM Release All************************************************************/ +void HAL_HSEM_ReleaseAll(uint32_t Key, uint32_t CoreID, uint32_t Attribute); +/* HSEM Check semaphore state Taken or not **********************************/ +uint32_t HAL_HSEM_IsSemTaken(uint32_t SemID); + +/** + * @} + */ + +/** @addtogroup HSEM_Exported_Functions_Group2 HSEM Set and Get Key functions + * @brief HSEM Set and Get Key functions. + * @{ + */ +/* HSEM Set Clear Key *********************************************************/ +void HAL_HSEM_SetClearKey(uint32_t Key); +/* HSEM Get Clear Key *********************************************************/ +uint32_t HAL_HSEM_GetClearKey(void); +/** + * @} + */ + +/** @addtogroup HSEM_Exported_Functions_Group3 + * @brief HSEM Notification functions + * @{ + */ +/* HSEM Activate HSEM Notification (When a semaphore is released) ) *****************/ +void HAL_HSEM_ActivateNotification(uint32_t SemMask); +/* HSEM Deactivate HSEM Notification (When a semaphore is released) ****************/ +void HAL_HSEM_DeactivateNotification(uint32_t SemMask); +/* HSEM Free Callback (When a semaphore is released) *******************************/ +void HAL_HSEM_FreeCallback(uint32_t SemMask); +/* HSEM IRQ Handler **********************************************************/ +void HAL_HSEM_IRQHandler(void); + +/** + * @} + */ + +/** @addtogroup HSEM_Exported_Functions_Group4 + * @brief HSEM Attributes functions. + * @{ + */ +#if defined(HSEM_SECCFGR_SEC0) +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +void HAL_HSEM_SetSemaphoreSecure(uint32_t SemMask); +void HAL_HSEM_SetSemaphoreNonSecure(uint32_t SemMask); +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +uint32_t HAL_HSEM_GetSemaphoreSecure(void); +#endif /* (HSEM_SECCFGR_SEC0) */ + +#if defined(HSEM_PRIVCFGR_PRIV0) +void HAL_HSEM_SetSemaphorePrivilege(uint32_t SemMask); +void HAL_HSEM_SetSemaphoreNonPrivilege(uint32_t SemMask); +uint32_t HAL_HSEM_GetSemaphorePrivilege(void); +#endif /* (HSEM_PRIVCFGR_PRIV0) */ + +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup HSEM_Private_Macros HSEM Private Macros + * @{ + */ + +#define IS_HSEM_SEMID(__SEMID__) ((__SEMID__) <= HSEM_SEMID_MAX ) + +#define IS_HSEM_PROCESSID(__PROCESSID__) ((__PROCESSID__) <= HSEM_PROCESSID_MAX ) + +#define IS_HSEM_KEY(__KEY__) ((__KEY__) <= HSEM_CLEAR_KEY_MAX ) + +#define IS_HSEM_LOCKID(__LOCKID__) ((__LOCKID__) == HSEM_CPU1_LOCKID) + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WBAxx_HAL_HSEM_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_i2c.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_i2c.h new file mode 100644 index 0000000000..094b2cb335 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_i2c.h @@ -0,0 +1,846 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_i2c.h + * @author MCD Application Team + * @brief Header file of I2C HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_HAL_I2C_H +#define STM32WBAxx_HAL_I2C_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal_def.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @addtogroup I2C + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup I2C_Exported_Types I2C Exported Types + * @{ + */ + +/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition + * @brief I2C Configuration Structure definition + * @{ + */ +typedef struct +{ + uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value. + This parameter calculated by referring to I2C initialization section + in Reference manual */ + + uint32_t OwnAddress1; /*!< Specifies the first device own address. + This parameter can be a 7-bit or 10-bit address. */ + + uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected. + This parameter can be a value of @ref I2C_ADDRESSING_MODE */ + + uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. + This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */ + + uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected + This parameter can be a 7-bit address. */ + + uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing + mode is selected. + This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */ + + uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. + This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */ + + uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. + This parameter can be a value of @ref I2C_NOSTRETCH_MODE */ + +} I2C_InitTypeDef; + +/** + * @} + */ + +/** @defgroup HAL_state_structure_definition HAL state structure definition + * @brief HAL State structure definition + * @note HAL I2C State value coding follow below described bitmap :\n + * b7-b6 Error information\n + * 00 : No Error\n + * 01 : Abort (Abort user request on going)\n + * 10 : Timeout\n + * 11 : Error\n + * b5 Peripheral initialization status\n + * 0 : Reset (peripheral not initialized)\n + * 1 : Init done (peripheral initialized and ready to use. HAL I2C Init function called)\n + * b4 (not used)\n + * x : Should be set to 0\n + * b3\n + * 0 : Ready or Busy (No Listen mode ongoing)\n + * 1 : Listen (peripheral in Address Listen Mode)\n + * b2 Intrinsic process state\n + * 0 : Ready\n + * 1 : Busy (peripheral busy with some configuration or internal operations)\n + * b1 Rx state\n + * 0 : Ready (no Rx operation ongoing)\n + * 1 : Busy (Rx operation ongoing)\n + * b0 Tx state\n + * 0 : Ready (no Tx operation ongoing)\n + * 1 : Busy (Tx operation ongoing) + * @{ + */ +typedef enum +{ + HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */ + HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */ + HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */ + HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */ + HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ + HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */ + HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission + process is ongoing */ + HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception + process is ongoing */ + HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */ + +} HAL_I2C_StateTypeDef; + +/** + * @} + */ + +/** @defgroup HAL_mode_structure_definition HAL mode structure definition + * @brief HAL Mode structure definition + * @note HAL I2C Mode value coding follow below described bitmap :\n + * b7 (not used)\n + * x : Should be set to 0\n + * b6\n + * 0 : None\n + * 1 : Memory (HAL I2C communication is in Memory Mode)\n + * b5\n + * 0 : None\n + * 1 : Slave (HAL I2C communication is in Slave Mode)\n + * b4\n + * 0 : None\n + * 1 : Master (HAL I2C communication is in Master Mode)\n + * b3-b2-b1-b0 (not used)\n + * xxxx : Should be set to 0000 + * @{ + */ +typedef enum +{ + HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */ + HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */ + HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */ + HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */ + +} HAL_I2C_ModeTypeDef; + +/** + * @} + */ + +/** @defgroup I2C_Error_Code_definition I2C Error Code definition + * @brief I2C Error Code definition + * @{ + */ +#define HAL_I2C_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_I2C_ERROR_BERR (0x00000001U) /*!< BERR error */ +#define HAL_I2C_ERROR_ARLO (0x00000002U) /*!< ARLO error */ +#define HAL_I2C_ERROR_AF (0x00000004U) /*!< ACKF error */ +#define HAL_I2C_ERROR_OVR (0x00000008U) /*!< OVR error */ +#define HAL_I2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#define HAL_I2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */ +#define HAL_I2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */ +#define HAL_I2C_ERROR_DMA_PARAM (0x00000080U) /*!< DMA Parameter Error */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +#define HAL_I2C_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */ +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +#define HAL_I2C_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */ +/** + * @} + */ + +/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition + * @brief I2C handle Structure definition + * @{ + */ +typedef struct __I2C_HandleTypeDef +{ + I2C_TypeDef *Instance; /*!< I2C registers base address */ + + I2C_InitTypeDef Init; /*!< I2C communication parameters */ + + uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */ + + uint16_t XferSize; /*!< I2C transfer size */ + + __IO uint16_t XferCount; /*!< I2C transfer counter */ + + __IO uint32_t XferOptions; /*!< I2C sequantial transfer options, this parameter can + be a value of @ref I2C_XFEROPTIONS */ + + __IO uint32_t PreviousState; /*!< I2C communication Previous state */ + + HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); + /*!< I2C transfer IRQ handler function pointer */ + +#if defined(HAL_DMA_MODULE_ENABLED) + DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */ + +#endif /*HAL_DMA_MODULE_ENABLED*/ + + HAL_LockTypeDef Lock; /*!< I2C locking object */ + + __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */ + + __IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */ + + __IO uint32_t ErrorCode; /*!< I2C Error code */ + + __IO uint32_t AddrEventCount; /*!< I2C Address Event counter */ + + __IO uint32_t Devaddress; /*!< I2C Target device address */ + + __IO uint32_t Memaddress; /*!< I2C Target memory address */ + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Master Tx Transfer completed callback */ + void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Master Rx Transfer completed callback */ + void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Slave Tx Transfer completed callback */ + void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Slave Rx Transfer completed callback */ + void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Listen Complete callback */ + void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Memory Tx Transfer completed callback */ + void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Memory Rx Transfer completed callback */ + void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Error callback */ + void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Abort callback */ + + void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); + /*!< I2C Slave Address Match callback */ + + void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Msp Init callback */ + void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Msp DeInit callback */ + +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +} I2C_HandleTypeDef; + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +/** + * @brief HAL I2C Callback ID enumeration definition + */ +typedef enum +{ + HAL_I2C_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< I2C Master Tx Transfer completed callback ID */ + HAL_I2C_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< I2C Master Rx Transfer completed callback ID */ + HAL_I2C_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< I2C Slave Tx Transfer completed callback ID */ + HAL_I2C_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< I2C Slave Rx Transfer completed callback ID */ + HAL_I2C_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< I2C Listen Complete callback ID */ + HAL_I2C_MEM_TX_COMPLETE_CB_ID = 0x05U, /*!< I2C Memory Tx Transfer callback ID */ + HAL_I2C_MEM_RX_COMPLETE_CB_ID = 0x06U, /*!< I2C Memory Rx Transfer completed callback ID */ + HAL_I2C_ERROR_CB_ID = 0x07U, /*!< I2C Error callback ID */ + HAL_I2C_ABORT_CB_ID = 0x08U, /*!< I2C Abort callback ID */ + + HAL_I2C_MSPINIT_CB_ID = 0x09U, /*!< I2C Msp Init callback ID */ + HAL_I2C_MSPDEINIT_CB_ID = 0x0AU /*!< I2C Msp DeInit callback ID */ + +} HAL_I2C_CallbackIDTypeDef; + +/** + * @brief HAL I2C Callback pointer definition + */ +typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); +/*!< pointer to an I2C callback function */ +typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, + uint16_t AddrMatchCode); +/*!< pointer to an I2C Address Match callback function */ + +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** + * @} + */ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup I2C_Exported_Constants I2C Exported Constants + * @{ + */ + +/** @defgroup I2C_XFEROPTIONS I2C Sequential Transfer Options + * @{ + */ +#define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE) +#define I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE)) +#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE)) +#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) +#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) +#define I2C_LAST_FRAME_NO_STOP ((uint32_t)I2C_SOFTEND_MODE) + +/* List of XferOptions in usage of : + * 1- Restart condition in all use cases (direction change or not) + */ +#define I2C_OTHER_FRAME (0x000000AAU) +#define I2C_OTHER_AND_LAST_FRAME (0x0000AA00U) +/** + * @} + */ + +/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode + * @{ + */ +#define I2C_ADDRESSINGMODE_7BIT (0x00000001U) +#define I2C_ADDRESSINGMODE_10BIT (0x00000002U) +/** + * @} + */ + +/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode + * @{ + */ +#define I2C_DUALADDRESS_DISABLE (0x00000000U) +#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN +/** + * @} + */ + +/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks + * @{ + */ +#define I2C_OA2_NOMASK ((uint8_t)0x00U) +#define I2C_OA2_MASK01 ((uint8_t)0x01U) +#define I2C_OA2_MASK02 ((uint8_t)0x02U) +#define I2C_OA2_MASK03 ((uint8_t)0x03U) +#define I2C_OA2_MASK04 ((uint8_t)0x04U) +#define I2C_OA2_MASK05 ((uint8_t)0x05U) +#define I2C_OA2_MASK06 ((uint8_t)0x06U) +#define I2C_OA2_MASK07 ((uint8_t)0x07U) +/** + * @} + */ + +/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode + * @{ + */ +#define I2C_GENERALCALL_DISABLE (0x00000000U) +#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN +/** + * @} + */ + +/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode + * @{ + */ +#define I2C_NOSTRETCH_DISABLE (0x00000000U) +#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH +/** + * @} + */ + +/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size + * @{ + */ +#define I2C_MEMADD_SIZE_8BIT (0x00000001U) +#define I2C_MEMADD_SIZE_16BIT (0x00000002U) +/** + * @} + */ + +/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View + * @{ + */ +#define I2C_DIRECTION_TRANSMIT (0x00000000U) +#define I2C_DIRECTION_RECEIVE (0x00000001U) +/** + * @} + */ + +/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode + * @{ + */ +#define I2C_RELOAD_MODE I2C_CR2_RELOAD +#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND +#define I2C_SOFTEND_MODE (0x00000000U) +/** + * @} + */ + +/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode + * @{ + */ +#define I2C_NO_STARTSTOP (0x00000000U) +#define I2C_GENERATE_NO_START_READ (uint32_t)(0x80000000U | I2C_CR2_RD_WRN) +#define I2C_GENERATE_NO_START_WRITE (uint32_t)(0x80000000U) +#define I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) +#define I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) +#define I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) +/** + * @} + */ + +/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition + * @brief I2C Interrupt definition + * Elements values convention: 0xXXXXXXXX + * - XXXXXXXX : Interrupt control mask + * @{ + */ +#define I2C_IT_ERRI I2C_CR1_ERRIE +#define I2C_IT_TCI I2C_CR1_TCIE +#define I2C_IT_STOPI I2C_CR1_STOPIE +#define I2C_IT_NACKI I2C_CR1_NACKIE +#define I2C_IT_ADDRI I2C_CR1_ADDRIE +#define I2C_IT_RXI I2C_CR1_RXIE +#define I2C_IT_TXI I2C_CR1_TXIE +/** + * @} + */ + +/** @defgroup I2C_Flag_definition I2C Flag definition + * @{ + */ +#define I2C_FLAG_TXE I2C_ISR_TXE +#define I2C_FLAG_TXIS I2C_ISR_TXIS +#define I2C_FLAG_RXNE I2C_ISR_RXNE +#define I2C_FLAG_ADDR I2C_ISR_ADDR +#define I2C_FLAG_AF I2C_ISR_NACKF +#define I2C_FLAG_STOPF I2C_ISR_STOPF +#define I2C_FLAG_TC I2C_ISR_TC +#define I2C_FLAG_TCR I2C_ISR_TCR +#define I2C_FLAG_BERR I2C_ISR_BERR +#define I2C_FLAG_ARLO I2C_ISR_ARLO +#define I2C_FLAG_OVR I2C_ISR_OVR +#define I2C_FLAG_PECERR I2C_ISR_PECERR +#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT +#define I2C_FLAG_ALERT I2C_ISR_ALERT +#define I2C_FLAG_BUSY I2C_ISR_BUSY +#define I2C_FLAG_DIR I2C_ISR_DIR +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ + +/** @defgroup I2C_Exported_Macros I2C Exported Macros + * @{ + */ + +/** @brief Reset I2C handle state. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_I2C_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET) +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + +/** @brief Enable the specified I2C interrupt. + * @param __HANDLE__ specifies the I2C Handle. + * @param __INTERRUPT__ specifies the interrupt source to enable. + * This parameter can be one of the following values: + * @arg @ref I2C_IT_ERRI Errors interrupt enable + * @arg @ref I2C_IT_TCI Transfer complete interrupt enable + * @arg @ref I2C_IT_STOPI STOP detection interrupt enable + * @arg @ref I2C_IT_NACKI NACK received interrupt enable + * @arg @ref I2C_IT_ADDRI Address match interrupt enable + * @arg @ref I2C_IT_RXI RX interrupt enable + * @arg @ref I2C_IT_TXI TX interrupt enable + * + * @retval None + */ +#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__)) + +/** @brief Disable the specified I2C interrupt. + * @param __HANDLE__ specifies the I2C Handle. + * @param __INTERRUPT__ specifies the interrupt source to disable. + * This parameter can be one of the following values: + * @arg @ref I2C_IT_ERRI Errors interrupt enable + * @arg @ref I2C_IT_TCI Transfer complete interrupt enable + * @arg @ref I2C_IT_STOPI STOP detection interrupt enable + * @arg @ref I2C_IT_NACKI NACK received interrupt enable + * @arg @ref I2C_IT_ADDRI Address match interrupt enable + * @arg @ref I2C_IT_RXI RX interrupt enable + * @arg @ref I2C_IT_TXI TX interrupt enable + * + * @retval None + */ +#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) + +/** @brief Check whether the specified I2C interrupt source is enabled or not. + * @param __HANDLE__ specifies the I2C Handle. + * @param __INTERRUPT__ specifies the I2C interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref I2C_IT_ERRI Errors interrupt enable + * @arg @ref I2C_IT_TCI Transfer complete interrupt enable + * @arg @ref I2C_IT_STOPI STOP detection interrupt enable + * @arg @ref I2C_IT_NACKI NACK received interrupt enable + * @arg @ref I2C_IT_ADDRI Address match interrupt enable + * @arg @ref I2C_IT_RXI RX interrupt enable + * @arg @ref I2C_IT_TXI TX interrupt enable + * + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & \ + (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Check whether the specified I2C flag is set or not. + * @param __HANDLE__ specifies the I2C Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref I2C_FLAG_TXE Transmit data register empty + * @arg @ref I2C_FLAG_TXIS Transmit interrupt status + * @arg @ref I2C_FLAG_RXNE Receive data register not empty + * @arg @ref I2C_FLAG_ADDR Address matched (slave mode) + * @arg @ref I2C_FLAG_AF Acknowledge failure received flag + * @arg @ref I2C_FLAG_STOPF STOP detection flag + * @arg @ref I2C_FLAG_TC Transfer complete (master mode) + * @arg @ref I2C_FLAG_TCR Transfer complete reload + * @arg @ref I2C_FLAG_BERR Bus error + * @arg @ref I2C_FLAG_ARLO Arbitration lost + * @arg @ref I2C_FLAG_OVR Overrun/Underrun + * @arg @ref I2C_FLAG_PECERR PEC error in reception + * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag + * @arg @ref I2C_FLAG_ALERT SMBus alert + * @arg @ref I2C_FLAG_BUSY Bus busy + * @arg @ref I2C_FLAG_DIR Transfer direction (slave mode) + * + * @retval The new state of __FLAG__ (SET or RESET). + */ +#define I2C_FLAG_MASK (0x0001FFFFU) +#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & \ + (__FLAG__)) == (__FLAG__)) ? SET : RESET) + +/** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit. + * @param __HANDLE__ specifies the I2C Handle. + * @param __FLAG__ specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg @ref I2C_FLAG_TXE Transmit data register empty + * @arg @ref I2C_FLAG_ADDR Address matched (slave mode) + * @arg @ref I2C_FLAG_AF Acknowledge failure received flag + * @arg @ref I2C_FLAG_STOPF STOP detection flag + * @arg @ref I2C_FLAG_BERR Bus error + * @arg @ref I2C_FLAG_ARLO Arbitration lost + * @arg @ref I2C_FLAG_OVR Overrun/Underrun + * @arg @ref I2C_FLAG_PECERR PEC error in reception + * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag + * @arg @ref I2C_FLAG_ALERT SMBus alert + * + * @retval None + */ +#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? \ + ((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \ + ((__HANDLE__)->Instance->ICR = (__FLAG__))) + +/** @brief Enable the specified I2C peripheral. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) + +/** @brief Disable the specified I2C peripheral. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) + +/** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK)) +/** + * @} + */ + +/* Include I2C HAL Extended module */ +#include "stm32wbaxx_hal_i2c_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup I2C_Exported_Functions + * @{ + */ + +/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +/* Initialization and de-initialization functions******************************/ +HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, + pI2C_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions + * @{ + */ +/* IO operation functions ****************************************************/ +/******* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, + uint32_t Timeout); + +/******* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); + +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress); + +#if defined(HAL_DMA_MODULE_ENABLED) +/******* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); + +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); +#endif /*HAL_DMA_MODULE_ENABLED*/ +/** + * @} + */ + +/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks + * @{ + */ +/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */ +void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c); +void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); +void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c); +/** + * @} + */ + +/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions + * @{ + */ +/* Peripheral State, Mode and Error functions *********************************/ +HAL_I2C_StateTypeDef HAL_I2C_GetState(const I2C_HandleTypeDef *hi2c); +HAL_I2C_ModeTypeDef HAL_I2C_GetMode(const I2C_HandleTypeDef *hi2c); +uint32_t HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c); + +/** + * @} + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup I2C_Private_Constants I2C Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup I2C_Private_Macro I2C Private Macros + * @{ + */ + +#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \ + ((MODE) == I2C_ADDRESSINGMODE_10BIT)) + +#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \ + ((ADDRESS) == I2C_DUALADDRESS_ENABLE)) + +#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \ + ((MASK) == I2C_OA2_MASK01) || \ + ((MASK) == I2C_OA2_MASK02) || \ + ((MASK) == I2C_OA2_MASK03) || \ + ((MASK) == I2C_OA2_MASK04) || \ + ((MASK) == I2C_OA2_MASK05) || \ + ((MASK) == I2C_OA2_MASK06) || \ + ((MASK) == I2C_OA2_MASK07)) + +#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \ + ((CALL) == I2C_GENERALCALL_ENABLE)) + +#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \ + ((STRETCH) == I2C_NOSTRETCH_ENABLE)) + +#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \ + ((SIZE) == I2C_MEMADD_SIZE_16BIT)) + +#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \ + ((MODE) == I2C_AUTOEND_MODE) || \ + ((MODE) == I2C_SOFTEND_MODE)) + +#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \ + ((REQUEST) == I2C_GENERATE_START_READ) || \ + ((REQUEST) == I2C_GENERATE_START_WRITE) || \ + ((REQUEST) == I2C_GENERATE_NO_START_READ) || \ + ((REQUEST) == I2C_GENERATE_NO_START_WRITE)|| \ + ((REQUEST) == I2C_NO_STARTSTOP)) + +#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \ + ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \ + ((REQUEST) == I2C_NEXT_FRAME) || \ + ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \ + ((REQUEST) == I2C_LAST_FRAME) || \ + ((REQUEST) == I2C_LAST_FRAME_NO_STOP) || \ + IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)) + +#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME) || \ + ((REQUEST) == I2C_OTHER_AND_LAST_FRAME)) + +#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \ + (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | \ + I2C_CR2_NBYTES | I2C_CR2_RELOAD | \ + I2C_CR2_RD_WRN))) + +#define I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) \ + >> 16U)) +#define I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) \ + >> 16U)) +#define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND) +#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1)) +#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2)) + +#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU) +#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU) + +#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & \ + (uint16_t)(0xFF00U))) >> 8U))) +#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU)))) + +#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? \ + (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \ + (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \ + (~I2C_CR2_RD_WRN)) : \ + (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \ + (I2C_CR2_ADD10) | (I2C_CR2_START) | \ + (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN))) + +#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \ + ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET) +#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET) +/** + * @} + */ + +/* Private Functions ---------------------------------------------------------*/ +/** @defgroup I2C_Private_Functions I2C Private Functions + * @{ + */ +/* Private functions are defined in stm32wbaxx_hal_i2c.c file */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32WBAxx_HAL_I2C_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_i2c_ex.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_i2c_ex.h new file mode 100644 index 0000000000..cc84e89e04 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_i2c_ex.h @@ -0,0 +1,356 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_i2c_ex.h + * @author MCD Application Team + * @brief Header file of I2C HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_HAL_I2C_EX_H +#define STM32WBAxx_HAL_I2C_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal_def.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @addtogroup I2CEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup I2C_Exported_Types I2C Exported Types + * @{ + */ + +/** @defgroup I2C_Autonomous_Mode_Configuration_Structure_definition Autonomous Mode Configuration Structure definition + * @brief I2C Autonomous Mode Configuration structure definition + * @{ + */ +typedef struct +{ + uint32_t TriggerState; /*!< Specifies the trigger state. This parameter can be a value + of @ref I2CEx_AutonomousMode_FunctionalState */ + + uint32_t TriggerSelection; /*!< Specifies the autonomous mode trigger signal selection. This parameter + can be a value of @ref I2CEx_AutonomousMode_TriggerSelection */ + + uint32_t TriggerPolarity; /*!< Specifies the autonomous mode trigger signal polarity sensitivity. This parameter + can be a value of @ref I2CEx_AutonomousMode_TriggerPolarity */ + +} I2C_AutonomousModeConfTypeDef; +/** + * @} + */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants + * @{ + */ + +/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter + * @{ + */ +#define I2C_ANALOGFILTER_ENABLE 0x00000000U +#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF +/** + * @} + */ + +/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus + * @{ + */ +#define I2C_FASTMODEPLUS_ENABLE 0x00000000U /*!< Enable Fast Mode Plus */ +#define I2C_FASTMODEPLUS_DISABLE 0x00000001U /*!< Disable Fast Mode Plus */ +/** + * @} + */ + +/** @defgroup I2CEx_AutonomousMode_FunctionalState I2C Extended Autonomous Mode State + * @{ + */ +#define I2C_AUTO_MODE_DISABLE (0x00000000U) /*!< Autonomous mode disable */ +#define I2C_AUTO_MODE_ENABLE I2C_AUTOCR_TRIGEN /*!< Autonomous mode enable */ +/** + * @} + */ + +/** @defgroup I2CEx_AutonomousMode_TriggerSelection I2C Extended Autonomous Mode Trigger Selection + * @{ + */ +#if defined(I2C1) +#define I2C_TRIG_GRP1 (0x10000000U) /*!< Trigger Group for I2C1 */ +#endif /* I2C1 */ +#define I2C_TRIG_GRP2 (0x20000000U) /*!< Trigger Group for I2C3 */ + +#if defined(I2C_TRIG_GRP1) +#define I2C_GRP1_GPDMA_CH0_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x00000000U)) +/*!< HW Trigger signal is GPDMA_CH0_TRG */ +#define I2C_GRP1_GPDMA_CH1_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x1U << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is GPDMA_CH1_TRG */ +#define I2C_GRP1_GPDMA_CH2_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x2U << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is GPDMA_CH2_TRG */ +#define I2C_GRP1_GPDMA_CH3_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x3U << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is GPDMA_CH3_TRG */ +#define I2C_GRP1_EXTI5_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x4U << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is EXTI5_TRG */ +#define I2C_GRP1_EXTI9_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x5U << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is EXTI9_TRG */ +#define I2C_GRP1_LPTIM1_CH1_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x6U << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is LPTIM1_CH1_TRG */ +#define I2C_GRP1_LPTIM2_CH1_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x7U << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is LPTIM2_CH1_TRG */ +#if defined(COMP1) +#define I2C_GRP1_COMP1_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x8U << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is COMP1_TRG */ +#endif /* COMP1 */ +#if defined(COMP2) +#define I2C_GRP1_COMP2_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x9U << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is COMP2_TRG */ +#endif /* COMP2 */ +#define I2C_GRP1_RTC_ALRA_TRG (uint32_t)(I2C_TRIG_GRP1 | (0xAU << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is RTC_ALRA_TRG */ +#define I2C_GRP1_RTC_WUT_TRG (uint32_t)(I2C_TRIG_GRP1 | (0xBU << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is RTC_WUT_TRG */ +#endif /* I2C_TRIG_GRP1 */ + +#define I2C_GRP2_GPDMA_CH0_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x00000000U)) +/*!< HW Trigger signal is GPDMA_CH0_TRG */ +#define I2C_GRP2_GPDMA_CH1_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x1U << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is GPDMA_CH1_TRG */ +#define I2C_GRP2_GPDMA_CH2_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x2U << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is GPDMA_CH2_TRG */ +#define I2C_GRP2_GPDMA_CH3_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x3U << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is GPDMA_CH3_TRG */ +#define I2C_GRP2_EXTI5_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x4U << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is EXTI5_TRG */ +#define I2C_GRP2_EXTI8_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x5U << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is EXTI8_TRG */ +#define I2C_GRP2_LPTIM1_CH1_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x6U << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is LPTIM1_CH1_TRG */ +#if defined(COMP1) +#define I2C_GRP2_COMP1_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x8U << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is COMP1_TRG */ +#endif /* COMP1 */ +#if defined(COMP2) +#define I2C_GRP2_COMP2_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x9U << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is COMP2_TRG */ +#endif /* COMP2 */ +#define I2C_GRP2_RTC_ALRA_TRG (uint32_t)(I2C_TRIG_GRP2 | (0xAU << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is RTC_ALRA_TRG */ +#define I2C_GRP2_RTC_WUT_TRG (uint32_t)(I2C_TRIG_GRP2 | (0xBU << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is RTC_WUT_TRG */ +/** + * @} + */ + +/** @defgroup I2CEx_AutonomousMode_TriggerPolarity Extended Autonomous Mode Trigger Polarity + * @{ + */ +#define I2C_TRIG_POLARITY_RISING (0x00000000U) /*!< I2C HW Trigger signal on rising edge */ +#define I2C_TRIG_POLARITY_FALLING I2C_AUTOCR_TRIGPOL /*!< I2C HW Trigger signal on falling edge */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup I2CEx_Exported_Macros I2C Extended Exported Macros + * @{ + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions + * @{ + */ + +/** @addtogroup I2CEx_Exported_Functions_Group1 Filter Mode Functions + * @{ + */ +/* Peripheral Control functions ************************************************/ +HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter); +HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter); +/** + * @} + */ + +/** @addtogroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions + * @{ + */ +HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c); +/** + * @} + */ + +/** @addtogroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions + * @{ + */ +HAL_StatusTypeDef HAL_I2CEx_ConfigFastModePlus(I2C_HandleTypeDef *hi2c, uint32_t FastModePlus); +/** + * @} + */ + +/** @addtogroup I2CEx_Exported_Functions_Group4 Autonomous Mode Functions + * @{ + */ +HAL_StatusTypeDef HAL_I2CEx_SetConfigAutonomousMode(I2C_HandleTypeDef *hi2c, + const I2C_AutonomousModeConfTypeDef *sConfig); +HAL_StatusTypeDef HAL_I2CEx_GetConfigAutonomousMode(const I2C_HandleTypeDef *hi2c, + I2C_AutonomousModeConfTypeDef *sConfig); +HAL_StatusTypeDef HAL_I2CEx_ClearConfigAutonomousMode(I2C_HandleTypeDef *hi2c); +/** + * @} + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros + * @{ + */ +#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \ + ((FILTER) == I2C_ANALOGFILTER_DISABLE)) + +#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) + +#define IS_I2C_FASTMODEPLUS(__CONFIG__) (((__CONFIG__) == (I2C_FASTMODEPLUS_ENABLE)) || \ + ((__CONFIG__) == (I2C_FASTMODEPLUS_DISABLE))) + +#define IS_I2C_AUTO_MODE(__MODE__) (((__MODE__) == I2C_AUTO_MODE_DISABLE) || \ + ((__MODE__) == I2C_AUTO_MODE_ENABLE)) + +#if defined(I2C_TRIG_GRP1) +#define IS_I2C_TRIG_SOURCE(__INSTANCE__, __SOURCE__) (((__INSTANCE__) == I2C3) ? \ + IS_I2C_GRP2_TRIG_SOURCE(__SOURCE__) : \ + IS_I2C_GRP1_TRIG_SOURCE(__SOURCE__)) +#else +#define IS_I2C_TRIG_SOURCE(__INSTANCE__, __SOURCE__) (IS_I2C_GRP2_TRIG_SOURCE(__SOURCE__)) +#endif /* I2C_TRIG_GRP1 */ + +#if defined(COMP1) && defined(COMP2) +#if defined(I2C_TRIG_GRP1) +#define IS_I2C_GRP1_TRIG_SOURCE(__SOURCE__) (((__SOURCE__) == I2C_GRP1_GPDMA_CH0_TCF_TRG ) || \ + ((__SOURCE__) == I2C_GRP1_GPDMA_CH1_TCF_TRG ) || \ + ((__SOURCE__) == I2C_GRP1_GPDMA_CH2_TCF_TRG ) || \ + ((__SOURCE__) == I2C_GRP1_GPDMA_CH3_TCF_TRG ) || \ + ((__SOURCE__) == I2C_GRP1_EXTI5_TRG ) || \ + ((__SOURCE__) == I2C_GRP1_EXTI9_TRG ) || \ + ((__SOURCE__) == I2C_GRP1_LPTIM1_CH1_TRG ) || \ + ((__SOURCE__) == I2C_GRP1_LPTIM2_CH1_TRG ) || \ + ((__SOURCE__) == I2C_GRP1_COMP1_TRG ) || \ + ((__SOURCE__) == I2C_GRP1_COMP2_TRG ) || \ + ((__SOURCE__) == I2C_GRP1_RTC_ALRA_TRG ) || \ + ((__SOURCE__) == I2C_GRP1_RTC_WUT_TRG )) +#endif /* I2C_TRIG_GRP1 */ + +#define IS_I2C_GRP2_TRIG_SOURCE(__SOURCE__) (((__SOURCE__) == I2C_GRP2_GPDMA_CH0_TCF_TRG ) || \ + ((__SOURCE__) == I2C_GRP2_GPDMA_CH1_TCF_TRG ) || \ + ((__SOURCE__) == I2C_GRP2_GPDMA_CH2_TCF_TRG ) || \ + ((__SOURCE__) == I2C_GRP2_GPDMA_CH3_TCF_TRG ) || \ + ((__SOURCE__) == I2C_GRP2_EXTI5_TRG ) || \ + ((__SOURCE__) == I2C_GRP2_EXTI8_TRG ) || \ + ((__SOURCE__) == I2C_GRP2_LPTIM1_CH1_TRG ) || \ + ((__SOURCE__) == I2C_GRP2_COMP1_TRG ) || \ + ((__SOURCE__) == I2C_GRP2_COMP2_TRG ) || \ + ((__SOURCE__) == I2C_GRP2_RTC_ALRA_TRG ) || \ + ((__SOURCE__) == I2C_GRP2_RTC_WUT_TRG )) + +#else + +#define IS_I2C_GRP1_TRIG_SOURCE(__SOURCE__) (((__SOURCE__) == I2C_GRP1_GPDMA_CH0_TCF_TRG ) || \ + ((__SOURCE__) == I2C_GRP1_GPDMA_CH1_TCF_TRG ) || \ + ((__SOURCE__) == I2C_GRP1_GPDMA_CH2_TCF_TRG ) || \ + ((__SOURCE__) == I2C_GRP1_GPDMA_CH3_TCF_TRG ) || \ + ((__SOURCE__) == I2C_GRP1_EXTI5_TRG ) || \ + ((__SOURCE__) == I2C_GRP1_EXTI9_TRG ) || \ + ((__SOURCE__) == I2C_GRP1_LPTIM1_CH1_TRG ) || \ + ((__SOURCE__) == I2C_GRP1_LPTIM2_CH1_TRG ) || \ + ((__SOURCE__) == I2C_GRP1_RTC_ALRA_TRG ) || \ + ((__SOURCE__) == I2C_GRP1_RTC_WUT_TRG )) + +#define IS_I2C_GRP2_TRIG_SOURCE(__SOURCE__) (((__SOURCE__) == I2C_GRP2_GPDMA_CH0_TCF_TRG ) || \ + ((__SOURCE__) == I2C_GRP2_GPDMA_CH1_TCF_TRG ) || \ + ((__SOURCE__) == I2C_GRP2_GPDMA_CH2_TCF_TRG ) || \ + ((__SOURCE__) == I2C_GRP2_GPDMA_CH3_TCF_TRG ) || \ + ((__SOURCE__) == I2C_GRP2_EXTI5_TRG ) || \ + ((__SOURCE__) == I2C_GRP2_EXTI8_TRG ) || \ + ((__SOURCE__) == I2C_GRP2_LPTIM1_CH1_TRG ) || \ + ((__SOURCE__) == I2C_GRP2_RTC_ALRA_TRG ) || \ + ((__SOURCE__) == I2C_GRP2_RTC_WUT_TRG )) +#endif /* COMP1 && COMP2 */ + +#if defined(I2C_TRIG_GRP1) +#define IS_I2C_TRIG_INPUT_INSTANCE(__INSTANCE__) (IS_I2C_GRP1_INSTANCE(__INSTANCE__) || \ + IS_I2C_GRP2_INSTANCE(__INSTANCE__)) +#else +#define IS_I2C_TRIG_INPUT_INSTANCE(__INSTANCE__) IS_I2C_GRP1_INSTANCE(__INSTANCE__) +#endif /* I2C_TRIG_GRP1 */ + +#define IS_I2C_AUTO_MODE_TRG_POL(__POLARITY__) (((__POLARITY__) == I2C_TRIG_POLARITY_RISING) || \ + ((__POLARITY__) == I2C_TRIG_POLARITY_FALLING)) +/** + * @} + */ + +/* Private Functions ---------------------------------------------------------*/ +/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions + * @{ + */ +/* Private functions are defined in stm32wbaxx_hal_i2c_ex.c file */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WBAxx_HAL_I2C_EX_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_icache.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_icache.h new file mode 100644 index 0000000000..83e18ee7dd --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_icache.h @@ -0,0 +1,294 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_icache.h + * @author MCD Application Team + * @brief Header file of ICACHE HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion ------------------------------------*/ +#ifndef STM32WBAxx_HAL_ICACHE_H +#define STM32WBAxx_HAL_ICACHE_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes -----------------------------------------------------------------*/ +#include "stm32wbaxx_hal_def.h" + +#if defined(ICACHE) +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @addtogroup ICACHE + * @{ + */ + +/* Exported types -----------------------------------------------------------*/ +/** @defgroup ICACHE_Exported_Types ICACHE Exported Types + * @{ + */ + +/** + * @brief HAL ICACHE region configuration structure definition + */ +typedef struct +{ + uint32_t BaseAddress; /*!< Configures the Base address of Region i to be remapped */ + + uint32_t RemapAddress; /*!< Configures the Remap address of Region i to be remapped */ + + uint32_t Size; /*!< Configures the Region size. + This parameter can be a value of @ref ICACHE_Region_Size */ + + uint32_t TrafficRoute; /*!< Selects the traffic route. + This parameter can be a value of @ref ICACHE_Traffic_Route */ + + uint32_t OutputBurstType; /*!< Selects the output burst type. + This parameter can be a value of @ref ICACHE_Output_Burst_Type */ +} ICACHE_RegionConfigTypeDef; +/** + * @} + */ + +/* Exported constants -------------------------------------------------------*/ +/** @defgroup ICACHE_Exported_Constants ICACHE Exported Constants + * @{ + */ + +/** @defgroup ICACHE_WaysSelection Ways selection + * @{ + */ +#define ICACHE_1WAY 0U /*!< 1-way cache (direct mapped cache) */ +#define ICACHE_2WAYS ICACHE_CR_WAYSEL /*!< 2-ways set associative cache (default) */ +/** + * @} + */ + +/** @defgroup ICACHE_Monitor_Type Monitor type + * @{ + */ +#define ICACHE_MONITOR_HIT_MISS (ICACHE_CR_HITMEN | ICACHE_CR_MISSMEN) /*!< Hit & Miss monitoring */ +#define ICACHE_MONITOR_HIT ICACHE_CR_HITMEN /*!< Hit monitoring */ +#define ICACHE_MONITOR_MISS ICACHE_CR_MISSMEN /*!< Miss monitoring */ +/** + * @} + */ + +/** @defgroup ICACHE_Region Remapped Region number + * @{ + */ +#define ICACHE_REGION_0 0U /*!< Region 0 */ +#define ICACHE_REGION_1 1U /*!< Region 1 */ +#define ICACHE_REGION_2 2U /*!< Region 2 */ +#define ICACHE_REGION_3 3U /*!< Region 3 */ +/** + * @} + */ + +/** @defgroup ICACHE_Region_Size Remapped Region size + * @{ + */ +#define ICACHE_REGIONSIZE_2MB 1U /*!< Region size 2MB */ +#define ICACHE_REGIONSIZE_4MB 2U /*!< Region size 4MB */ +#define ICACHE_REGIONSIZE_8MB 3U /*!< Region size 8MB */ +#define ICACHE_REGIONSIZE_16MB 4U /*!< Region size 16MB */ +#define ICACHE_REGIONSIZE_32MB 5U /*!< Region size 32MB */ +#define ICACHE_REGIONSIZE_64MB 6U /*!< Region size 64MB */ +#define ICACHE_REGIONSIZE_128MB 7U /*!< Region size 128MB */ +/** + * @} + */ + +/** @defgroup ICACHE_Traffic_Route Remapped Traffic route + * @{ + */ +#define ICACHE_MASTER1_PORT 0U /*!< Master1 port */ +#define ICACHE_MASTER2_PORT ICACHE_CRRx_MSTSEL /*!< Master2 port */ +/** + * @} + */ + +/** @defgroup ICACHE_Output_Burst_Type Remapped Output burst type + * @{ + */ +#define ICACHE_OUTPUT_BURST_WRAP 0U /*!< WRAP */ +#define ICACHE_OUTPUT_BURST_INCR ICACHE_CRRx_HBURST /*!< INCR */ +/** + * @} + */ + +/** @defgroup ICACHE_Interrupts Interrupts + * @{ + */ +#define ICACHE_IT_BUSYEND ICACHE_IER_BSYENDIE /*!< Busy end interrupt */ +#define ICACHE_IT_ERROR ICACHE_IER_ERRIE /*!< Cache error interrupt */ +/** + * @} + */ + +/** @defgroup ICACHE_Flags Flags + * @{ + */ +#define ICACHE_FLAG_BUSY ICACHE_SR_BUSYF /*!< Busy flag */ +#define ICACHE_FLAG_BUSYEND ICACHE_SR_BSYENDF /*!< Busy end flag */ +#define ICACHE_FLAG_ERROR ICACHE_SR_ERRF /*!< Cache error flag */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros ----------------------------------------------------------*/ +/** @defgroup ICACHE_Exported_Macros ICACHE Exported Macros + * @{ + */ + +/** @defgroup ICACHE_Flags_Interrupts_Management Flags and Interrupts Management + * @brief macros to manage the specified ICACHE flags and interrupts. + * @{ + */ + +/** @brief Enable ICACHE interrupts. + * @param __INTERRUPT__ specifies the ICACHE interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg @ref ICACHE_IT_BUSYEND Busy end interrupt + * @arg @ref ICACHE_IT_ERROR Cache error interrupt + */ +#define __HAL_ICACHE_ENABLE_IT(__INTERRUPT__) SET_BIT(ICACHE->IER, (__INTERRUPT__)) + +/** @brief Disable ICACHE interrupts. + * @param __INTERRUPT__ specifies the ICACHE interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg @ref ICACHE_IT_BUSYEND Busy end interrupt + * @arg @ref ICACHE_IT_ERROR Cache error interrupt + */ +#define __HAL_ICACHE_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(ICACHE->IER, (__INTERRUPT__)) + +/** @brief Check whether the specified ICACHE interrupt source is enabled or not. + * @param __INTERRUPT__ specifies the ICACHE interrupt source to check. + * This parameter can be any combination of the following values: + * @arg @ref ICACHE_IT_BUSYEND Busy end interrupt + * @arg @ref ICACHE_IT_ERROR Cache error interrupt + * @retval The state of __INTERRUPT__ (0 or 1). + */ +#define __HAL_ICACHE_GET_IT_SOURCE(__INTERRUPT__) \ + ((READ_BIT(ICACHE->IER, (__INTERRUPT__)) == (__INTERRUPT__)) ? 1U : 0U) + +/** @brief Check whether the selected ICACHE flag is set or not. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref ICACHE_FLAG_BUSY Busy flag + * @arg @ref ICACHE_FLAG_BUSYEND Busy end flag + * @arg @ref ICACHE_FLAG_ERROR Cache error flag + * @retval The state of __FLAG__ (0 or 1). + */ +#define __HAL_ICACHE_GET_FLAG(__FLAG__) ((READ_BIT(ICACHE->SR, (__FLAG__)) != 0U) ? 1U : 0U) + +/** @brief Clear the selected ICACHE flags. + * @param __FLAG__ specifies the ICACHE flags to clear. + * This parameter can be any combination of the following values: + * @arg @ref ICACHE_FLAG_BUSYEND Busy end flag + * @arg @ref ICACHE_FLAG_ERROR Cache error flag + */ +#define __HAL_ICACHE_CLEAR_FLAG(__FLAG__) WRITE_REG(ICACHE->FCR, (__FLAG__)) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions -------------------------------------------------------*/ +/** @addtogroup ICACHE_Exported_Functions + * @{ + */ + +/** @addtogroup ICACHE_Exported_Functions_Group1 + * @brief Initialization and control functions + * @{ + */ +/* Peripheral Control functions **********************************************/ +HAL_StatusTypeDef HAL_ICACHE_Enable(void); +HAL_StatusTypeDef HAL_ICACHE_Disable(void); +uint32_t HAL_ICACHE_IsEnabled(void); +HAL_StatusTypeDef HAL_ICACHE_ConfigAssociativityMode(uint32_t AssociativityMode); +HAL_StatusTypeDef HAL_ICACHE_DeInit(void); + +/******* Invalidate in blocking mode (Polling) */ +HAL_StatusTypeDef HAL_ICACHE_Invalidate(void); +/******* Invalidate in non-blocking mode (Interrupt) */ +HAL_StatusTypeDef HAL_ICACHE_Invalidate_IT(void); +/******* Wait for Invalidate complete in blocking mode (Polling) */ +HAL_StatusTypeDef HAL_ICACHE_WaitForInvalidateComplete(void); + +/******* Performance instruction cache monitoring functions */ +HAL_StatusTypeDef HAL_ICACHE_Monitor_Start(uint32_t MonitorType); +HAL_StatusTypeDef HAL_ICACHE_Monitor_Stop(uint32_t MonitorType); +HAL_StatusTypeDef HAL_ICACHE_Monitor_Reset(uint32_t MonitorType); +uint32_t HAL_ICACHE_Monitor_GetHitValue(void); +uint32_t HAL_ICACHE_Monitor_GetMissValue(void); + +/** + * @} + */ + +/** @addtogroup ICACHE_Exported_Functions_Group2 + * @brief IRQ and callback functions + * @{ + */ +/******* IRQHandler and Callbacks used in non-blocking mode (Interrupt) */ +void HAL_ICACHE_IRQHandler(void); +void HAL_ICACHE_InvalidateCompleteCallback(void); +void HAL_ICACHE_ErrorCallback(void); + +/** + * @} + */ + +/** @addtogroup ICACHE_Exported_Functions_Group3 + * @brief Memory remapped regions functions + * @{ + */ +/******* Memory remapped regions functions */ +HAL_StatusTypeDef HAL_ICACHE_EnableRemapRegion(uint32_t Region, const ICACHE_RegionConfigTypeDef *const pRegionConfig); +HAL_StatusTypeDef HAL_ICACHE_DisableRemapRegion(uint32_t Region); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* ICACHE */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WBAxx_HAL_ICACHE_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_irda.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_irda.h new file mode 100644 index 0000000000..494afd2bfd --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_irda.h @@ -0,0 +1,897 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_irda.h + * @author MCD Application Team + * @brief Header file of IRDA HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_HAL_IRDA_H +#define STM32WBAxx_HAL_IRDA_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal_def.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @addtogroup IRDA + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup IRDA_Exported_Types IRDA Exported Types + * @{ + */ + +/** + * @brief IRDA Init Structure definition + */ +typedef struct +{ + uint32_t BaudRate; /*!< This member configures the IRDA communication baud rate. + The baud rate register is computed using the following formula: + Baud Rate Register = ((usart_ker_ckpres) / ((hirda->Init.BaudRate))) + where usart_ker_ckpres is the IRDA input clock divided by a prescaler */ + + uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref IRDAEx_Word_Length */ + + uint32_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref IRDA_Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ + + uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref IRDA_Transfer_Mode */ + + uint8_t Prescaler; /*!< Specifies the Prescaler value for dividing the UART/USART source clock + to achieve low-power frequency. + @note Prescaler value 0 is forbidden */ + + uint16_t PowerMode; /*!< Specifies the IRDA power mode. + This parameter can be a value of @ref IRDA_Low_Power */ + + uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the IRDA clock source. + This parameter can be a value of @ref IRDA_ClockPrescaler. */ + +} IRDA_InitTypeDef; + +/** + * @brief HAL IRDA State definition + * @note HAL IRDA State value is a combination of 2 different substates: + * gState and RxState (see @ref IRDA_State_Definition). + * - gState contains IRDA state information related to global Handle management + * and also information related to Tx operations. + * gState value coding follow below described bitmap : + * b7-b6 Error information + * 00 : No Error + * 01 : (Not Used) + * 10 : Timeout + * 11 : Error + * b5 Peripheral initialization status + * 0 : Reset (Peripheral not initialized) + * 1 : Init done (Peripheral initialized. HAL IRDA Init function already called) + * b4-b3 (not used) + * xx : Should be set to 00 + * b2 Intrinsic process state + * 0 : Ready + * 1 : Busy (Peripheral busy with some configuration or internal operations) + * b1 (not used) + * x : Should be set to 0 + * b0 Tx state + * 0 : Ready (no Tx operation ongoing) + * 1 : Busy (Tx operation ongoing) + * - RxState contains information related to Rx operations. + * RxState value coding follow below described bitmap : + * b7-b6 (not used) + * xx : Should be set to 00 + * b5 Peripheral initialization status + * 0 : Reset (Peripheral not initialized) + * 1 : Init done (Peripheral initialized) + * b4-b2 (not used) + * xxx : Should be set to 000 + * b1 Rx state + * 0 : Ready (no Rx operation ongoing) + * 1 : Busy (Rx operation ongoing) + * b0 (not used) + * x : Should be set to 0. + */ +typedef uint32_t HAL_IRDA_StateTypeDef; + +/** + * @brief IRDA clock sources definition + */ +typedef enum +{ + IRDA_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */ + IRDA_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */ + IRDA_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */ + IRDA_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */ + IRDA_CLOCKSOURCE_LSE = 0x10U, /*!< LSE clock source */ + IRDA_CLOCKSOURCE_UNDEFINED = 0x20U /*!< Undefined clock source */ +} IRDA_ClockSourceTypeDef; + +/** + * @brief IRDA handle Structure definition + */ +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) +typedef struct __IRDA_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ +{ + USART_TypeDef *Instance; /*!< USART registers base address */ + + IRDA_InitTypeDef Init; /*!< IRDA communication parameters */ + + const uint8_t *pTxBuffPtr; /*!< Pointer to IRDA Tx transfer Buffer */ + + uint16_t TxXferSize; /*!< IRDA Tx Transfer size */ + + __IO uint16_t TxXferCount; /*!< IRDA Tx Transfer Counter */ + + uint8_t *pRxBuffPtr; /*!< Pointer to IRDA Rx transfer Buffer */ + + uint16_t RxXferSize; /*!< IRDA Rx Transfer size */ + + __IO uint16_t RxXferCount; /*!< IRDA Rx Transfer Counter */ + + uint16_t Mask; /*!< USART RX RDR register mask */ + +#if defined(HAL_DMA_MODULE_ENABLED) + DMA_HandleTypeDef *hdmatx; /*!< IRDA Tx DMA Handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< IRDA Rx DMA Handle parameters */ + +#endif /* HAL_DMA_MODULE_ENABLED */ + HAL_LockTypeDef Lock; /*!< Locking object */ + + __IO HAL_IRDA_StateTypeDef gState; /*!< IRDA state information related to global Handle management + and also related to Tx operations. + This parameter can be a value of @ref HAL_IRDA_StateTypeDef */ + + __IO HAL_IRDA_StateTypeDef RxState; /*!< IRDA state information related to Rx operations. + This parameter can be a value of @ref HAL_IRDA_StateTypeDef */ + + __IO uint32_t ErrorCode; /*!< IRDA Error code */ + +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + void (* TxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Tx Half Complete Callback */ + + void (* TxCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Tx Complete Callback */ + + void (* RxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Rx Half Complete Callback */ + + void (* RxCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Rx Complete Callback */ + + void (* ErrorCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Error Callback */ + + void (* AbortCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Complete Callback */ + + void (* AbortTransmitCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Transmit Complete Callback */ + + void (* AbortReceiveCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Receive Complete Callback */ + + + void (* MspInitCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Msp Init callback */ + + void (* MspDeInitCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Msp DeInit callback */ +#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ + +} IRDA_HandleTypeDef; + +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) +/** + * @brief HAL IRDA Callback ID enumeration definition + */ +typedef enum +{ + HAL_IRDA_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< IRDA Tx Half Complete Callback ID */ + HAL_IRDA_TX_COMPLETE_CB_ID = 0x01U, /*!< IRDA Tx Complete Callback ID */ + HAL_IRDA_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< IRDA Rx Half Complete Callback ID */ + HAL_IRDA_RX_COMPLETE_CB_ID = 0x03U, /*!< IRDA Rx Complete Callback ID */ + HAL_IRDA_ERROR_CB_ID = 0x04U, /*!< IRDA Error Callback ID */ + HAL_IRDA_ABORT_COMPLETE_CB_ID = 0x05U, /*!< IRDA Abort Complete Callback ID */ + HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, /*!< IRDA Abort Transmit Complete Callback ID */ + HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U, /*!< IRDA Abort Receive Complete Callback ID */ + + HAL_IRDA_MSPINIT_CB_ID = 0x08U, /*!< IRDA MspInit callback ID */ + HAL_IRDA_MSPDEINIT_CB_ID = 0x09U /*!< IRDA MspDeInit callback ID */ + +} HAL_IRDA_CallbackIDTypeDef; + +/** + * @brief HAL IRDA Callback pointer definition + */ +typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer to an IRDA callback function */ + +#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup IRDA_Exported_Constants IRDA Exported Constants + * @{ + */ + +/** @defgroup IRDA_State_Definition IRDA State Code Definition + * @{ + */ +#define HAL_IRDA_STATE_RESET 0x00000000U /*!< Peripheral is not initialized + Value is allowed for gState and RxState */ +#define HAL_IRDA_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for use + Value is allowed for gState and RxState */ +#define HAL_IRDA_STATE_BUSY 0x00000024U /*!< An internal process is ongoing + Value is allowed for gState only */ +#define HAL_IRDA_STATE_BUSY_TX 0x00000021U /*!< Data Transmission process is ongoing + Value is allowed for gState only */ +#define HAL_IRDA_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing + Value is allowed for RxState only */ +#define HAL_IRDA_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing + Not to be used for neither gState nor RxState. + Value is result of combination (Or) between + gState and RxState values */ +#define HAL_IRDA_STATE_TIMEOUT 0x000000A0U /*!< Timeout state + Value is allowed for gState only */ +#define HAL_IRDA_STATE_ERROR 0x000000E0U /*!< Error + Value is allowed for gState only */ +/** + * @} + */ + +/** @defgroup IRDA_Error_Definition IRDA Error Code Definition + * @{ + */ +#define HAL_IRDA_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_IRDA_ERROR_PE (0x00000001U) /*!< Parity error */ +#define HAL_IRDA_ERROR_NE (0x00000002U) /*!< Noise error */ +#define HAL_IRDA_ERROR_FE (0x00000004U) /*!< frame error */ +#define HAL_IRDA_ERROR_ORE (0x00000008U) /*!< Overrun error */ +#if defined(HAL_DMA_MODULE_ENABLED) +#define HAL_IRDA_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#endif /* HAL_DMA_MODULE_ENABLED */ +#define HAL_IRDA_ERROR_BUSY (0x00000020U) /*!< Busy Error */ +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) +#define HAL_IRDA_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */ +#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup IRDA_Parity IRDA Parity + * @{ + */ +#define IRDA_PARITY_NONE 0x00000000U /*!< No parity */ +#define IRDA_PARITY_EVEN USART_CR1_PCE /*!< Even parity */ +#define IRDA_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Odd parity */ +/** + * @} + */ + +/** @defgroup IRDA_Transfer_Mode IRDA Transfer Mode + * @{ + */ +#define IRDA_MODE_RX USART_CR1_RE /*!< RX mode */ +#define IRDA_MODE_TX USART_CR1_TE /*!< TX mode */ +#define IRDA_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< RX and TX mode */ +/** + * @} + */ + +/** @defgroup IRDA_Low_Power IRDA Low Power + * @{ + */ +#define IRDA_POWERMODE_NORMAL 0x00000000U /*!< IRDA normal power mode */ +#define IRDA_POWERMODE_LOWPOWER USART_CR3_IRLP /*!< IRDA low power mode */ +/** + * @} + */ + +/** @defgroup IRDA_ClockPrescaler IRDA Clock Prescaler + * @{ + */ +#define IRDA_PRESCALER_DIV1 0x00000000U /*!< fclk_pres = fclk */ +#define IRDA_PRESCALER_DIV2 0x00000001U /*!< fclk_pres = fclk/2 */ +#define IRDA_PRESCALER_DIV4 0x00000002U /*!< fclk_pres = fclk/4 */ +#define IRDA_PRESCALER_DIV6 0x00000003U /*!< fclk_pres = fclk/6 */ +#define IRDA_PRESCALER_DIV8 0x00000004U /*!< fclk_pres = fclk/8 */ +#define IRDA_PRESCALER_DIV10 0x00000005U /*!< fclk_pres = fclk/10 */ +#define IRDA_PRESCALER_DIV12 0x00000006U /*!< fclk_pres = fclk/12 */ +#define IRDA_PRESCALER_DIV16 0x00000007U /*!< fclk_pres = fclk/16 */ +#define IRDA_PRESCALER_DIV32 0x00000008U /*!< fclk_pres = fclk/32 */ +#define IRDA_PRESCALER_DIV64 0x00000009U /*!< fclk_pres = fclk/64 */ +#define IRDA_PRESCALER_DIV128 0x0000000AU /*!< fclk_pres = fclk/128 */ +#define IRDA_PRESCALER_DIV256 0x0000000BU /*!< fclk_pres = fclk/256 */ +/** + * @} + */ + +/** @defgroup IRDA_State IRDA State + * @{ + */ +#define IRDA_STATE_DISABLE 0x00000000U /*!< IRDA disabled */ +#define IRDA_STATE_ENABLE USART_CR1_UE /*!< IRDA enabled */ +/** + * @} + */ + +/** @defgroup IRDA_Mode IRDA Mode + * @{ + */ +#define IRDA_MODE_DISABLE 0x00000000U /*!< Associated UART disabled in IRDA mode */ +#define IRDA_MODE_ENABLE USART_CR3_IREN /*!< Associated UART enabled in IRDA mode */ +/** + * @} + */ + +/** @defgroup IRDA_One_Bit IRDA One Bit Sampling + * @{ + */ +#define IRDA_ONE_BIT_SAMPLE_DISABLE 0x00000000U /*!< One-bit sampling disabled */ +#define IRDA_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT /*!< One-bit sampling enabled */ +/** + * @} + */ + +/** @defgroup IRDA_DMA_Tx IRDA DMA Tx + * @{ + */ +#define IRDA_DMA_TX_DISABLE 0x00000000U /*!< IRDA DMA TX disabled */ +#define IRDA_DMA_TX_ENABLE USART_CR3_DMAT /*!< IRDA DMA TX enabled */ +/** + * @} + */ + +/** @defgroup IRDA_DMA_Rx IRDA DMA Rx + * @{ + */ +#define IRDA_DMA_RX_DISABLE 0x00000000U /*!< IRDA DMA RX disabled */ +#define IRDA_DMA_RX_ENABLE USART_CR3_DMAR /*!< IRDA DMA RX enabled */ +/** + * @} + */ + +/** @defgroup IRDA_Request_Parameters IRDA Request Parameters + * @{ + */ +#define IRDA_AUTOBAUD_REQUEST USART_RQR_ABRRQ /*!< Auto-Baud Rate Request */ +#define IRDA_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ /*!< Receive Data flush Request */ +#define IRDA_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ /*!< Transmit data flush Request */ +/** + * @} + */ + +/** @defgroup IRDA_Flags IRDA Flags + * Elements values convention: 0xXXXX + * - 0xXXXX : Flag mask in the ISR register + * @{ + */ +#define IRDA_FLAG_REACK USART_ISR_REACK /*!< IRDA receive enable acknowledge flag */ +#define IRDA_FLAG_TEACK USART_ISR_TEACK /*!< IRDA transmit enable acknowledge flag */ +#define IRDA_FLAG_BUSY USART_ISR_BUSY /*!< IRDA busy flag */ +#define IRDA_FLAG_ABRF USART_ISR_ABRF /*!< IRDA auto Baud rate flag */ +#define IRDA_FLAG_ABRE USART_ISR_ABRE /*!< IRDA auto Baud rate error */ +#define IRDA_FLAG_TXE USART_ISR_TXE_TXFNF /*!< IRDA transmit data register empty */ +#define IRDA_FLAG_TC USART_ISR_TC /*!< IRDA transmission complete */ +#define IRDA_FLAG_RXNE USART_ISR_RXNE_RXFNE /*!< IRDA read data register not empty */ +#define IRDA_FLAG_ORE USART_ISR_ORE /*!< IRDA overrun error */ +#define IRDA_FLAG_NE USART_ISR_NE /*!< IRDA noise error */ +#define IRDA_FLAG_FE USART_ISR_FE /*!< IRDA frame error */ +#define IRDA_FLAG_PE USART_ISR_PE /*!< IRDA parity error */ +/** + * @} + */ + +/** @defgroup IRDA_Interrupt_definition IRDA Interrupts Definition + * Elements values convention: 0000ZZZZ0XXYYYYYb + * - YYYYY : Interrupt source position in the XX register (5bits) + * - XX : Interrupt source register (2bits) + * - 01: CR1 register + * - 10: CR2 register + * - 11: CR3 register + * - ZZZZ : Flag position in the ISR register(4bits) + * @{ + */ +#define IRDA_IT_PE 0x0028U /*!< IRDA Parity error interruption */ +#define IRDA_IT_TXE 0x0727U /*!< IRDA Transmit data register empty interruption */ +#define IRDA_IT_TC 0x0626U /*!< IRDA Transmission complete interruption */ +#define IRDA_IT_RXNE 0x0525U /*!< IRDA Read data register not empty interruption */ +#define IRDA_IT_IDLE 0x0424U /*!< IRDA Idle interruption */ + +/* Elements values convention: 000000000XXYYYYYb + - YYYYY : Interrupt source position in the XX register (5bits) + - XX : Interrupt source register (2bits) + - 01: CR1 register + - 10: CR2 register + - 11: CR3 register */ +#define IRDA_IT_ERR 0x0060U /*!< IRDA Error interruption */ + +/* Elements values convention: 0000ZZZZ00000000b + - ZZZZ : Flag position in the ISR register(4bits) */ +#define IRDA_IT_ORE 0x0300U /*!< IRDA Overrun error interruption */ +#define IRDA_IT_NE 0x0200U /*!< IRDA Noise error interruption */ +#define IRDA_IT_FE 0x0100U /*!< IRDA Frame error interruption */ +/** + * @} + */ + +/** @defgroup IRDA_IT_CLEAR_Flags IRDA Interruption Clear Flags + * @{ + */ +#define IRDA_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */ +#define IRDA_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */ +#define IRDA_CLEAR_NEF USART_ICR_NECF /*!< Noise Error detected Clear Flag */ +#define IRDA_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */ +#define IRDA_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */ +#define IRDA_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */ +/** + * @} + */ + +/** @defgroup IRDA_Interruption_Mask IRDA interruptions flags mask + * @{ + */ +#define IRDA_IT_MASK 0x001FU /*!< IRDA Interruptions flags mask */ +#define IRDA_CR_MASK 0x00E0U /*!< IRDA control register mask */ +#define IRDA_CR_POS 5U /*!< IRDA control register position */ +#define IRDA_ISR_MASK 0x1F00U /*!< IRDA ISR register mask */ +#define IRDA_ISR_POS 8U /*!< IRDA ISR register position */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup IRDA_Exported_Macros IRDA Exported Macros + * @{ + */ + +/** @brief Reset IRDA handle state. + * @param __HANDLE__ IRDA handle. + * @retval None + */ +#if USE_HAL_IRDA_REGISTER_CALLBACKS == 1 +#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->gState = HAL_IRDA_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0U) +#else +#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->gState = HAL_IRDA_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET; \ + } while(0U) +#endif /*USE_HAL_IRDA_REGISTER_CALLBACKS */ + +/** @brief Flush the IRDA DR register. + * @param __HANDLE__ specifies the IRDA Handle. + * @retval None + */ +#define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__) \ + do{ \ + SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); \ + SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \ + } while(0U) + +/** @brief Clear the specified IRDA pending flag. + * @param __HANDLE__ specifies the IRDA Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be any combination of the following values: + * @arg @ref IRDA_CLEAR_PEF + * @arg @ref IRDA_CLEAR_FEF + * @arg @ref IRDA_CLEAR_NEF + * @arg @ref IRDA_CLEAR_OREF + * @arg @ref IRDA_CLEAR_TCF + * @arg @ref IRDA_CLEAR_IDLEF + * @retval None + */ +#define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) + +/** @brief Clear the IRDA PE pending flag. + * @param __HANDLE__ specifies the IRDA Handle. + * @retval None + */ +#define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_PEF) + + +/** @brief Clear the IRDA FE pending flag. + * @param __HANDLE__ specifies the IRDA Handle. + * @retval None + */ +#define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_FEF) + +/** @brief Clear the IRDA NE pending flag. + * @param __HANDLE__ specifies the IRDA Handle. + * @retval None + */ +#define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_NEF) + +/** @brief Clear the IRDA ORE pending flag. + * @param __HANDLE__ specifies the IRDA Handle. + * @retval None + */ +#define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_OREF) + +/** @brief Clear the IRDA IDLE pending flag. + * @param __HANDLE__ specifies the IRDA Handle. + * @retval None + */ +#define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_IDLEF) + +/** @brief Check whether the specified IRDA flag is set or not. + * @param __HANDLE__ specifies the IRDA Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref IRDA_FLAG_REACK Receive enable acknowledge flag + * @arg @ref IRDA_FLAG_TEACK Transmit enable acknowledge flag + * @arg @ref IRDA_FLAG_BUSY Busy flag + * @arg @ref IRDA_FLAG_ABRF Auto Baud rate detection flag + * @arg @ref IRDA_FLAG_ABRE Auto Baud rate detection error flag + * @arg @ref IRDA_FLAG_TXE Transmit data register empty flag + * @arg @ref IRDA_FLAG_TC Transmission Complete flag + * @arg @ref IRDA_FLAG_RXNE Receive data register not empty flag + * @arg @ref IRDA_FLAG_ORE OverRun Error flag + * @arg @ref IRDA_FLAG_NE Noise Error flag + * @arg @ref IRDA_FLAG_FE Framing Error flag + * @arg @ref IRDA_FLAG_PE Parity Error flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) + + +/** @brief Enable the specified IRDA interrupt. + * @param __HANDLE__ specifies the IRDA Handle. + * @param __INTERRUPT__ specifies the IRDA interrupt source to enable. + * This parameter can be one of the following values: + * @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt + * @arg @ref IRDA_IT_TC Transmission complete interrupt + * @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt + * @arg @ref IRDA_IT_IDLE Idle line detection interrupt + * @arg @ref IRDA_IT_PE Parity Error interrupt + * @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error) + * @retval None + */ +#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? \ + ((__HANDLE__)->Instance->CR1 |= (1U << \ + ((__INTERRUPT__) & IRDA_IT_MASK))):\ + ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? \ + ((__HANDLE__)->Instance->CR2 |= (1U << \ + ((__INTERRUPT__) & IRDA_IT_MASK))):\ + ((__HANDLE__)->Instance->CR3 |= (1U << \ + ((__INTERRUPT__) & IRDA_IT_MASK)))) + +/** @brief Disable the specified IRDA interrupt. + * @param __HANDLE__ specifies the IRDA Handle. + * @param __INTERRUPT__ specifies the IRDA interrupt source to disable. + * This parameter can be one of the following values: + * @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt + * @arg @ref IRDA_IT_TC Transmission complete interrupt + * @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt + * @arg @ref IRDA_IT_IDLE Idle line detection interrupt + * @arg @ref IRDA_IT_PE Parity Error interrupt + * @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error) + * @retval None + */ +#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? \ + ((__HANDLE__)->Instance->CR1 &= ~ (1U << \ + ((__INTERRUPT__) & IRDA_IT_MASK))): \ + ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? \ + ((__HANDLE__)->Instance->CR2 &= ~ (1U << \ + ((__INTERRUPT__) & IRDA_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 &= ~ (1U << \ + ((__INTERRUPT__) & IRDA_IT_MASK)))) + +/** @brief Check whether the specified IRDA interrupt has occurred or not. + * @param __HANDLE__ specifies the IRDA Handle. + * @param __INTERRUPT__ specifies the IRDA interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt + * @arg @ref IRDA_IT_TC Transmission complete interrupt + * @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt + * @arg @ref IRDA_IT_IDLE Idle line detection interrupt + * @arg @ref IRDA_IT_ORE OverRun Error interrupt + * @arg @ref IRDA_IT_NE Noise Error interrupt + * @arg @ref IRDA_IT_FE Framing Error interrupt + * @arg @ref IRDA_IT_PE Parity Error interrupt + * @retval The new state of __IT__ (SET or RESET). + */ +#define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) \ + ((((__HANDLE__)->Instance->ISR& (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>>IRDA_ISR_POS))) != 0U) ? SET : RESET) + +/** @brief Check whether the specified IRDA interrupt source is enabled or not. + * @param __HANDLE__ specifies the IRDA Handle. + * @param __INTERRUPT__ specifies the IRDA interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt + * @arg @ref IRDA_IT_TC Transmission complete interrupt + * @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt + * @arg @ref IRDA_IT_IDLE Idle line detection interrupt + * @arg @ref IRDA_IT_ERR Framing, overrun or noise error interrupt + * @arg @ref IRDA_IT_PE Parity Error interrupt + * @retval The new state of __IT__ (SET or RESET). + */ +#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ + ((((((((__INTERRUPT__) & IRDA_CR_MASK) >>IRDA_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 :(((((__INTERRUPT__) \ + & IRDA_CR_MASK) >> IRDA_CR_POS)== 0x02U)? (__HANDLE__)->Instance->CR2 :(__HANDLE__)->Instance->CR3)) \ + & (0x01U <<(((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET) + +/** @brief Clear the specified IRDA ISR flag, in setting the proper ICR register flag. + * @param __HANDLE__ specifies the IRDA Handle. + * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set + * to clear the corresponding interrupt + * This parameter can be one of the following values: + * @arg @ref IRDA_CLEAR_PEF Parity Error Clear Flag + * @arg @ref IRDA_CLEAR_FEF Framing Error Clear Flag + * @arg @ref IRDA_CLEAR_NEF Noise detected Clear Flag + * @arg @ref IRDA_CLEAR_OREF OverRun Error Clear Flag + * @arg @ref IRDA_CLEAR_TCF Transmission Complete Clear Flag + * @retval None + */ +#define __HAL_IRDA_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__)) + + +/** @brief Set a specific IRDA request flag. + * @param __HANDLE__ specifies the IRDA Handle. + * @param __REQ__ specifies the request flag to set + * This parameter can be one of the following values: + * @arg @ref IRDA_AUTOBAUD_REQUEST Auto-Baud Rate Request + * @arg @ref IRDA_RXDATA_FLUSH_REQUEST Receive Data flush Request + * @arg @ref IRDA_TXDATA_FLUSH_REQUEST Transmit data flush Request + * @retval None + */ +#define __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) + +/** @brief Enable the IRDA one bit sample method. + * @param __HANDLE__ specifies the IRDA Handle. + * @retval None + */ +#define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) + +/** @brief Disable the IRDA one bit sample method. + * @param __HANDLE__ specifies the IRDA Handle. + * @retval None + */ +#define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\ + &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT)) + +/** @brief Enable UART/USART associated to IRDA Handle. + * @param __HANDLE__ specifies the IRDA Handle. + * @retval None + */ +#define __HAL_IRDA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) + +/** @brief Disable UART/USART associated to IRDA Handle. + * @param __HANDLE__ specifies the IRDA Handle. + * @retval None + */ +#define __HAL_IRDA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) + +/** + * @} + */ + +/* Private macros --------------------------------------------------------*/ +/** @addtogroup IRDA_Private_Macros + * @{ + */ + +/** @brief Ensure that IRDA Baud rate is less or equal to maximum value. + * @param __BAUDRATE__ specifies the IRDA Baudrate set by the user. + * @retval True or False + */ +#define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201U) + +/** @brief Ensure that IRDA prescaler value is strictly larger than 0. + * @param __PRESCALER__ specifies the IRDA prescaler value set by the user. + * @retval True or False + */ +#define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0U) + +/** @brief Ensure that IRDA frame parity is valid. + * @param __PARITY__ IRDA frame parity. + * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid) + */ +#define IS_IRDA_PARITY(__PARITY__) (((__PARITY__) == IRDA_PARITY_NONE) || \ + ((__PARITY__) == IRDA_PARITY_EVEN) || \ + ((__PARITY__) == IRDA_PARITY_ODD)) + +/** @brief Ensure that IRDA communication mode is valid. + * @param __MODE__ IRDA communication mode. + * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) + */ +#define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__)\ + & (~((uint32_t)(IRDA_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U)) + +/** @brief Ensure that IRDA power mode is valid. + * @param __MODE__ IRDA power mode. + * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) + */ +#define IS_IRDA_POWERMODE(__MODE__) (((__MODE__) == IRDA_POWERMODE_LOWPOWER) || \ + ((__MODE__) == IRDA_POWERMODE_NORMAL)) + +/** @brief Ensure that IRDA clock Prescaler is valid. + * @param __CLOCKPRESCALER__ IRDA clock Prescaler value. + * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid) + */ +#define IS_IRDA_CLOCKPRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV1) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV2) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV4) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV6) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV8) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV10) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV12) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV16) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV32) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV64) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV128) || \ + ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV256)) + +/** @brief Ensure that IRDA state is valid. + * @param __STATE__ IRDA state mode. + * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid) + */ +#define IS_IRDA_STATE(__STATE__) (((__STATE__) == IRDA_STATE_DISABLE) || \ + ((__STATE__) == IRDA_STATE_ENABLE)) + +/** @brief Ensure that IRDA associated UART/USART mode is valid. + * @param __MODE__ IRDA associated UART/USART mode. + * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) + */ +#define IS_IRDA_MODE(__MODE__) (((__MODE__) == IRDA_MODE_DISABLE) || \ + ((__MODE__) == IRDA_MODE_ENABLE)) + +/** @brief Ensure that IRDA sampling rate is valid. + * @param __ONEBIT__ IRDA sampling rate. + * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid) + */ +#define IS_IRDA_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_DISABLE) || \ + ((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_ENABLE)) + +/** @brief Ensure that IRDA DMA TX mode is valid. + * @param __DMATX__ IRDA DMA TX mode. + * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid) + */ +#define IS_IRDA_DMA_TX(__DMATX__) (((__DMATX__) == IRDA_DMA_TX_DISABLE) || \ + ((__DMATX__) == IRDA_DMA_TX_ENABLE)) + +/** @brief Ensure that IRDA DMA RX mode is valid. + * @param __DMARX__ IRDA DMA RX mode. + * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid) + */ +#define IS_IRDA_DMA_RX(__DMARX__) (((__DMARX__) == IRDA_DMA_RX_DISABLE) || \ + ((__DMARX__) == IRDA_DMA_RX_ENABLE)) + +/** @brief Ensure that IRDA request is valid. + * @param __PARAM__ IRDA request. + * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid) + */ +#define IS_IRDA_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == IRDA_AUTOBAUD_REQUEST) || \ + ((__PARAM__) == IRDA_RXDATA_FLUSH_REQUEST) || \ + ((__PARAM__) == IRDA_TXDATA_FLUSH_REQUEST)) +/** + * @} + */ + +/* Include IRDA HAL Extended module */ +#include "stm32wbaxx_hal_irda_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup IRDA_Exported_Functions IRDA Exported Functions + * @{ + */ + +/** @addtogroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ +HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda); +HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda); +void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda); +void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda); + +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) +/* Callbacks Register/UnRegister functions ***********************************/ +HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID, + pIRDA_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @addtogroup IRDA_Exported_Functions_Group2 IO operation functions + * @{ + */ + +/* IO operation functions *****************************************************/ +HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size); +#if defined(HAL_DMA_MODULE_ENABLED) +HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda); +HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda); +HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda); +#endif /* HAL_DMA_MODULE_ENABLED */ +/* Transfer Abort functions */ +HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda); +HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda); +HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda); +HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda); +HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda); +HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda); + +void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda); +void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda); +void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda); +void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda); +void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda); +void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda); +void HAL_IRDA_AbortCpltCallback(IRDA_HandleTypeDef *hirda); +void HAL_IRDA_AbortTransmitCpltCallback(IRDA_HandleTypeDef *hirda); +void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda); + +/** + * @} + */ + +/* Peripheral Control functions ************************************************/ + +/** @addtogroup IRDA_Exported_Functions_Group4 Peripheral State and Error functions + * @{ + */ + +/* Peripheral State and Error functions ***************************************/ +HAL_IRDA_StateTypeDef HAL_IRDA_GetState(const IRDA_HandleTypeDef *hirda); +uint32_t HAL_IRDA_GetError(const IRDA_HandleTypeDef *hirda); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WBAxx_HAL_IRDA_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_irda_ex.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_irda_ex.h new file mode 100644 index 0000000000..0419be8e2a --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_irda_ex.h @@ -0,0 +1,224 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_irda_ex.h + * @author MCD Application Team + * @brief Header file of IRDA HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_HAL_IRDA_EX_H +#define STM32WBAxx_HAL_IRDA_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal_def.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @defgroup IRDAEx IRDAEx + * @brief IRDA Extended HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup IRDAEx_Extended_Exported_Constants IRDAEx Extended Exported Constants + * @{ + */ + +/** @defgroup IRDAEx_Word_Length IRDAEx Word Length + * @{ + */ +#define IRDA_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long frame */ +#define IRDA_WORDLENGTH_8B 0x00000000U /*!< 8-bit long frame */ +#define IRDA_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long frame */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ + +/** @defgroup IRDAEx_Private_Macros IRDAEx Private Macros + * @{ + */ + +/** @brief Report the IRDA clock source. + * @param __HANDLE__ specifies the IRDA Handle. + * @param __CLOCKSOURCE__ output variable. + * @retval IRDA clocking source, written in __CLOCKSOURCE__. + */ +#if defined(USART2) +#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK2: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ + case RCC_USART2CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART2CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART2CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART2CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0U) +#else +#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK2: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0U) +#endif /* USART2 */ + +/** @brief Compute the mask to apply to retrieve the received data + * according to the word length and to the parity bits activation. + * @param __HANDLE__ specifies the IRDA Handle. + * @retval None, the mask to apply to the associated UART RDR register is stored in (__HANDLE__)->Mask field. + */ +#define IRDA_MASK_COMPUTATION(__HANDLE__) \ + do { \ + if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B) \ + { \ + if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x01FFU ; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x00FFU ; \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B) \ + { \ + if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x00FFU ; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x007FU ; \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_7B) \ + { \ + if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x007FU ; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x003FU ; \ + } \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x0000U; \ + } \ + } while(0U) + +/** @brief Ensure that IRDA frame length is valid. + * @param __LENGTH__ IRDA frame length. + * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) + */ +#define IS_IRDA_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == IRDA_WORDLENGTH_7B) || \ + ((__LENGTH__) == IRDA_WORDLENGTH_8B) || \ + ((__LENGTH__) == IRDA_WORDLENGTH_9B)) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WBAxx_HAL_IRDA_EX_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_iwdg.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_iwdg.h new file mode 100644 index 0000000000..a782c0a940 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_iwdg.h @@ -0,0 +1,302 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_iwdg.h + * @author MCD Application Team + * @brief Header file of IWDG HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_HAL_IWDG_H +#define STM32WBAxx_HAL_IWDG_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal_def.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @defgroup IWDG IWDG + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup IWDG_Exported_Types IWDG Exported Types + * @{ + */ + +/** + * @brief IWDG Init structure definition + */ +typedef struct +{ + uint32_t Prescaler; /*!< Select the prescaler of the IWDG. + This parameter can be a value of @ref IWDG_Prescaler */ + + uint32_t Reload; /*!< Specifies the IWDG down-counter reload value. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */ + + uint32_t Window; /*!< Specifies the window value to be compared to the down-counter. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */ + + uint32_t EWI; /*!< Specifies if IWDG Early Wakeup Interrupt is enable or not and the comparator value. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF + value 0 means that EWI is disabled */ +} IWDG_InitTypeDef; + +/** + * @brief IWDG Handle Structure definition + */ +#if (USE_HAL_IWDG_REGISTER_CALLBACKS == 1) +typedef struct __IWDG_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_IWDG_REGISTER_CALLBACKS */ +{ + IWDG_TypeDef *Instance; /*!< Register base address */ + + IWDG_InitTypeDef Init; /*!< IWDG required parameters */ + +#if (USE_HAL_IWDG_REGISTER_CALLBACKS == 1) + void (* EwiCallback)(struct __IWDG_HandleTypeDef *hiwdg); /*!< IWDG Early WakeUp Interrupt callback */ + void (* MspInitCallback)(struct __IWDG_HandleTypeDef *hiwdg); /*!< IWDG Msp Init callback */ +#endif /* USE_HAL_IWDG_REGISTER_CALLBACKS */ +} IWDG_HandleTypeDef; + +#if (USE_HAL_IWDG_REGISTER_CALLBACKS == 1) +/** + * @brief HAL IWDG common Callback ID enumeration definition + */ +typedef enum +{ + HAL_IWDG_EWI_CB_ID = 0x00U, /*!< IWDG EWI callback ID */ + HAL_IWDG_MSPINIT_CB_ID = 0x01U, /*!< IWDG MspInit callback ID */ +} HAL_IWDG_CallbackIDTypeDef; + +/** + * @brief HAL IWDG Callback pointer definition + */ +typedef void (*pIWDG_CallbackTypeDef)(IWDG_HandleTypeDef *hppp); /*!< pointer to a IWDG common callback functions */ +#endif /* USE_HAL_IWDG_REGISTER_CALLBACKS */ + + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup IWDG_Exported_Constants IWDG Exported Constants + * @{ + */ + +/** @defgroup IWDG_Prescaler IWDG Prescaler + * @{ + */ +#define IWDG_PRESCALER_4 0x00000000u /*!< IWDG prescaler set to 4 */ +#define IWDG_PRESCALER_8 IWDG_PR_PR_0 /*!< IWDG prescaler set to 8 */ +#define IWDG_PRESCALER_16 IWDG_PR_PR_1 /*!< IWDG prescaler set to 16 */ +#define IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 32 */ +#define IWDG_PRESCALER_64 IWDG_PR_PR_2 /*!< IWDG prescaler set to 64 */ +#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */ +#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */ +#define IWDG_PRESCALER_512 (IWDG_PR_PR_2 | IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 512 */ +#define IWDG_PRESCALER_1024 IWDG_PR_PR_3 /*!< IWDG prescaler set to 1024 */ +/** + * @} + */ + +/** @defgroup IWDG_Window_option IWDG Window option + * @{ + */ +#define IWDG_WINDOW_DISABLE IWDG_WINR_WIN +/** + * @} + */ + +/** @defgroup IWDG_EWI_Mode IWDG Early Wakeup Interrupt Mode + * @{ + */ +#define IWDG_EWI_DISABLE 0x00000000u /*!< EWI Disable */ +/** + * @} + */ + +/** @defgroup IWDG_Active_Status IWDG Active Status + * @{ + */ +#define IWDG_STATUS_DISABLE 0x00000000u +#define IWDG_STATUS_ENABLE IWDG_SR_ONF +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup IWDG_Exported_Macros IWDG Exported Macros + * @{ + */ + +/** + * @brief Enable the IWDG peripheral. + * @param __HANDLE__ IWDG handle + * @retval None + */ +#define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE) + +/** + * @brief Reload IWDG counter with value defined in the reload register + * (write access to IWDG_PR, IWDG_RLR, IWDG_WINR and EWCR registers disabled). + * @param __HANDLE__ IWDG handle + * @retval None + */ +#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup IWDG_Exported_Functions IWDG Exported Functions + * @{ + */ + +/** @defgroup IWDG_Exported_Functions_Group1 Initialization and Start functions + * @{ + */ +/* Initialization/Start functions ********************************************/ +HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg); +void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg); +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_IWDG_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_IWDG_RegisterCallback(IWDG_HandleTypeDef *hiwdg, HAL_IWDG_CallbackIDTypeDef CallbackID, + pIWDG_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_IWDG_UnRegisterCallback(IWDG_HandleTypeDef *hiwdg, HAL_IWDG_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_IWDG_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions + * @{ + */ +/* I/O operation functions ****************************************************/ +HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg); +uint32_t HAL_IWDG_GetActiveStatus(const IWDG_HandleTypeDef *hiwdg); +void HAL_IWDG_IRQHandler(IWDG_HandleTypeDef *hiwdg); +void HAL_IWDG_EarlyWakeupCallback(IWDG_HandleTypeDef *hiwdg); +/** + * @} + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup IWDG_Private_Constants IWDG Private Constants + * @{ + */ + +/** + * @brief IWDG Key Register BitMask + */ +#define IWDG_KEY_RELOAD 0x0000AAAAu /*!< IWDG Reload Counter Enable */ +#define IWDG_KEY_ENABLE 0x0000CCCCu /*!< IWDG Peripheral Enable */ +#define IWDG_KEY_WRITE_ACCESS_ENABLE 0x00005555u /*!< IWDG KR Write Access Enable */ +#define IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000u /*!< IWDG KR Write Access Disable */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup IWDG_Private_Macros IWDG Private Macros + * @{ + */ + +/** + * @brief Enable write access to IWDG_PR, IWDG_RLR, IWDG_WINR and EWCR registers. + * @param __HANDLE__ IWDG handle + * @retval None + */ +#define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE) + +/** + * @brief Disable write access to IWDG_PR, IWDG_RLR, IWDG_WINR and EWCR registers. + * @param __HANDLE__ IWDG handle + * @retval None + */ +#define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE) + +/** + * @brief Check IWDG prescaler value. + * @param __PRESCALER__ IWDG prescaler value + * @retval None + */ +#define IS_IWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDG_PRESCALER_4) || \ + ((__PRESCALER__) == IWDG_PRESCALER_8) || \ + ((__PRESCALER__) == IWDG_PRESCALER_16) || \ + ((__PRESCALER__) == IWDG_PRESCALER_32) || \ + ((__PRESCALER__) == IWDG_PRESCALER_64) || \ + ((__PRESCALER__) == IWDG_PRESCALER_128)|| \ + ((__PRESCALER__) == IWDG_PRESCALER_256)|| \ + ((__PRESCALER__) == IWDG_PRESCALER_512)|| \ + ((__PRESCALER__) == IWDG_PRESCALER_1024)) + +/** + * @brief Check IWDG reload value. + * @param __RELOAD__ IWDG reload value + * @retval None + */ +#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= IWDG_RLR_RL) + +/** + * @brief Check IWDG window value. + * @param __WINDOW__ IWDG window value + * @retval None + */ +#define IS_IWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= IWDG_WINR_WIN) + +/** + * @brief Check IWDG ewi value. + * @param __EWI__ IWDG ewi value + * @retval None + */ +#define IS_IWDG_EWI(__EWI__) ((__EWI__) <= IWDG_EWCR_EWIT) + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WBAxx_HAL_IWDG_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_lptim.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_lptim.h new file mode 100644 index 0000000000..9186ab7096 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_lptim.h @@ -0,0 +1,1259 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_lptim.h + * @author MCD Application Team + * @brief Header file of LPTIM HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_HAL_LPTIM_H +#define STM32WBAxx_HAL_LPTIM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal_def.h" + +/* Include low level driver */ +#include "stm32wbaxx_ll_lptim.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +#if defined (LPTIM1) || defined (LPTIM2) + +/** @addtogroup LPTIM + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup LPTIM_Exported_Types LPTIM Exported Types + * @{ + */ + +/** + * @brief LPTIM Clock configuration definition + */ +typedef struct +{ + uint32_t Source; /*!< Selects the clock source. + This parameter can be a value of @ref LPTIM_Clock_Source */ + + uint32_t Prescaler; /*!< Specifies the counter clock Prescaler. + This parameter can be a value of @ref LPTIM_Clock_Prescaler */ + +} LPTIM_ClockConfigTypeDef; + +/** + * @brief LPTIM Clock configuration definition + */ +typedef struct +{ + uint32_t Polarity; /*!< Selects the polarity of the active edge for the counter unit + if the ULPTIM input is selected. + Note: This parameter is used only when Ultra low power clock source is used. + Note: If the polarity is configured on 'both edges', an auxiliary clock + (one of the Low power oscillator) must be active. + This parameter can be a value of @ref LPTIM_Clock_Polarity */ + + uint32_t SampleTime; /*!< Selects the clock sampling time to configure the clock glitch filter. + Note: This parameter is used only when Ultra low power clock source is used. + This parameter can be a value of @ref LPTIM_Clock_Sample_Time */ + +} LPTIM_ULPClockConfigTypeDef; + +/** + * @brief LPTIM Trigger configuration definition + */ +typedef struct +{ + uint32_t Source; /*!< Selects the Trigger source. + This parameter can be a value of @ref LPTIM_Trigger_Source */ + + uint32_t ActiveEdge; /*!< Selects the Trigger active edge. + Note: This parameter is used only when an external trigger is used. + This parameter can be a value of @ref LPTIM_External_Trigger_Polarity */ + + uint32_t SampleTime; /*!< Selects the trigger sampling time to configure the clock glitch filter. + Note: This parameter is used only when an external trigger is used. + This parameter can be a value of @ref LPTIM_Trigger_Sample_Time */ +} LPTIM_TriggerConfigTypeDef; + +/** + * @brief LPTIM Initialization Structure definition + */ +typedef struct +{ + LPTIM_ClockConfigTypeDef Clock; /*!< Specifies the clock parameters */ + + LPTIM_ULPClockConfigTypeDef UltraLowPowerClock;/*!< Specifies the Ultra Low Power clock parameters */ + + LPTIM_TriggerConfigTypeDef Trigger; /*!< Specifies the Trigger parameters */ + + uint32_t Period; /*!< Specifies the period value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter can be a number between + Min_Data = 0x0001 and Max_Data = 0xFFFF. */ + + uint32_t UpdateMode; /*!< Specifies whether the update of the autoreload and the compare + values is done immediately or after the end of current period. + This parameter can be a value of @ref LPTIM_Updating_Mode */ + + uint32_t CounterSource; /*!< Specifies whether the counter is incremented each internal event + or each external event. + This parameter can be a value of @ref LPTIM_Counter_Source */ + + uint32_t Input1Source; /*!< Specifies source selected for input1 (GPIO or comparator output). + This parameter can be a value of @ref LPTIM_Input1_Source */ + + uint32_t Input2Source; /*!< Specifies source selected for input2 (GPIO or comparator output). + Note: This parameter is used only for encoder feature so is used only + for LPTIM1 instance. + This parameter can be a value of @ref LPTIM_Input2_Source */ + + uint32_t RepetitionCounter;/*!< Specifies the repetition counter value. + Each time the RCR downcounter reaches zero, an update event is + generated and counting restarts from the RCR value (N). + Note: When using repetition counter the UpdateMode field must be + set to LPTIM_UPDATE_ENDOFPERIOD otherwise unpredictable + behavior may occur. + This parameter must be a number between Min_Data = 0x00 and + Max_Data = 0xFF. */ +} LPTIM_InitTypeDef; + +/** + * @brief LPTIM Output Compare Configuration Structure definition + */ +typedef struct +{ + uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + uint32_t OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref LPTIM_Output_Compare_Polarity */ +} LPTIM_OC_ConfigTypeDef; + +/** + * @brief LPTIM Input Capture Configuration Structure definition + */ +typedef struct +{ + uint32_t ICInputSource; /*!< Specifies source selected for IC channel. + This parameter can be a value of @ref LPTIM_Input_Capture_Source */ + + uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref LPTIM_Input_Capture_Prescaler */ + + uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref LPTIM_Input_Capture_Polarity */ + + uint32_t ICFilter; /*!< Specifies the input capture filter. + This parameter can be a value of @ref LPTIM_Input_Capture_Filter */ +} LPTIM_IC_ConfigTypeDef; + +/** + * @brief HAL LPTIM State structure definition + */ +typedef enum +{ + HAL_LPTIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ + HAL_LPTIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_LPTIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ + HAL_LPTIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ + HAL_LPTIM_STATE_ERROR = 0x04U /*!< Internal Process is ongoing */ +} HAL_LPTIM_StateTypeDef; + +/** + * @brief HAL Active channel structures definition + */ +typedef enum +{ + HAL_LPTIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ + HAL_LPTIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ + HAL_LPTIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ +} HAL_LPTIM_ActiveChannel; + +/** + * @brief LPTIM Channel States definition + */ +typedef enum +{ + HAL_LPTIM_CHANNEL_STATE_RESET = 0x00U, /*!< LPTIM Channel initial state */ + HAL_LPTIM_CHANNEL_STATE_READY = 0x01U, /*!< LPTIM Channel ready for use */ + HAL_LPTIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the LPTIM channel */ +} HAL_LPTIM_ChannelStateTypeDef; + +/** + * @brief LPTIM handle Structure definition + */ +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) +typedef struct __LPTIM_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ +{ + LPTIM_TypeDef *Instance; /*!< Register base address */ + + LPTIM_InitTypeDef Init; /*!< LPTIM required parameters */ + + HAL_LPTIM_ActiveChannel Channel; /*!< Active channel */ + + DMA_HandleTypeDef *hdma[3]; /*!< DMA Handlers array, This array is accessed by a @ref LPTIM_DMA_Handle_index */ + + HAL_StatusTypeDef Status; /*!< LPTIM peripheral status */ + + HAL_LockTypeDef Lock; /*!< LPTIM locking object */ + + __IO HAL_LPTIM_StateTypeDef State; /*!< LPTIM peripheral state */ + + __IO HAL_LPTIM_ChannelStateTypeDef ChannelState[2]; /*!< LPTIM channel operation state */ +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + void (* MspInitCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Base Msp Init Callback */ + void (* MspDeInitCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Base Msp DeInit Callback */ + void (* CompareMatchCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Compare match Callback */ + void (* AutoReloadMatchCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Auto-reload match Callback */ + void (* TriggerCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< External trigger event detection Callback */ + void (* CompareWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Compare register write complete Callback */ + void (* AutoReloadWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Auto-reload register write complete Callback */ + void (* DirectionUpCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Up-counting direction change Callback */ + void (* DirectionDownCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Down-counting direction change Callback */ + void (* UpdateEventCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Update event detection Callback */ + void (* RepCounterWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Repetition counter register write complete Callback */ + void (* UpdateEventHalfCpltCallback)(struct __LPTIM_HandleTypeDef *hlptim);/*!< Update event half complete detection Callback */ + void (* ErrorCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Error Callback */ + void (* IC_CaptureCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Input capture Callback */ + void (* IC_CaptureHalfCpltCallback)(struct __LPTIM_HandleTypeDef *htim); /*!< Input Capture half complete Callback */ + void (* IC_OverCaptureCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Over capture Callback */ +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ +} LPTIM_HandleTypeDef; + +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) +/** + * @brief HAL LPTIM Callback ID enumeration definition + */ +typedef enum +{ + HAL_LPTIM_MSPINIT_CB_ID = 0x00U, /*!< LPTIM Base Msp Init Callback ID */ + HAL_LPTIM_MSPDEINIT_CB_ID = 0x01U, /*!< LPTIM Base Msp DeInit Callback ID */ + HAL_LPTIM_COMPARE_MATCH_CB_ID = 0x02U, /*!< Compare match Callback ID */ + HAL_LPTIM_AUTORELOAD_MATCH_CB_ID = 0x03U, /*!< Auto-reload match Callback ID */ + HAL_LPTIM_TRIGGER_CB_ID = 0x04U, /*!< External trigger event detection Callback ID */ + HAL_LPTIM_COMPARE_WRITE_CB_ID = 0x05U, /*!< Compare register write complete Callback ID */ + HAL_LPTIM_AUTORELOAD_WRITE_CB_ID = 0x06U, /*!< Auto-reload register write complete Callback ID */ + HAL_LPTIM_DIRECTION_UP_CB_ID = 0x07U, /*!< Up-counting direction change Callback ID */ + HAL_LPTIM_DIRECTION_DOWN_CB_ID = 0x08U, /*!< Down-counting direction change Callback ID */ + HAL_LPTIM_UPDATE_EVENT_CB_ID = 0x09U, /*!< Update event detection Callback ID */ + HAL_LPTIM_REP_COUNTER_WRITE_CB_ID = 0x0AU, /*!< Repetition counter register write complete Callback ID */ + HAL_LPTIM_UPDATE_EVENT_HALF_CB_ID = 0x0BU, /*!< Update event half complete detection Callback ID */ + HAL_LPTIM_ERROR_CB_ID = 0x0CU, /*!< LPTIM Error Callback ID */ + HAL_LPTIM_IC_CAPTURE_CB_ID = 0x0DU, /*!< Input capture Callback ID */ + HAL_LPTIM_IC_CAPTURE_HALF_CB_ID = 0x0EU, /*!< Input capture half complete Callback ID */ + HAL_LPTIM_OVER_CAPTURE_CB_ID = 0x0FU, /*!< Over capture Callback ID */ +} HAL_LPTIM_CallbackIDTypeDef; + +/** + * @brief HAL TIM Callback pointer definition + */ +typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< pointer to the LPTIM callback function */ + +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup LPTIM_Exported_Constants LPTIM Exported Constants + * @{ + */ + +/** @defgroup LPTIM_Clock_Source LPTIM Clock Source + * @{ + */ +#define LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC 0x00000000U +#define LPTIM_CLOCKSOURCE_ULPTIM LPTIM_CFGR_CKSEL +/** + * @} + */ + +/** @defgroup LPTIM_Clock_Prescaler LPTIM Clock Prescaler + * @{ + */ +#define LPTIM_PRESCALER_DIV1 0x00000000U +#define LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0 +#define LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1 +#define LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1) +#define LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2 +#define LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2) +#define LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2) +#define LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC +/** + * @} + */ + +/** @defgroup LPTIM_Clock_Sample_Time LPTIM Clock Sample Time + * @{ + */ +#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION 0x00000000U +#define LPTIM_CLOCKSAMPLETIME_2TRANSITIONS LPTIM_CFGR_CKFLT_0 +#define LPTIM_CLOCKSAMPLETIME_4TRANSITIONS LPTIM_CFGR_CKFLT_1 +#define LPTIM_CLOCKSAMPLETIME_8TRANSITIONS LPTIM_CFGR_CKFLT +/** + * @} + */ + +/** @defgroup LPTIM_Clock_Polarity LPTIM Clock Polarity + * @{ + */ +#define LPTIM_CLOCKPOLARITY_RISING 0x00000000U +#define LPTIM_CLOCKPOLARITY_FALLING LPTIM_CFGR_CKPOL_0 +#define LPTIM_CLOCKPOLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1 +/** + * @} + */ + +/** @defgroup LPTIM_Trigger_Source LPTIM Trigger Source + * @{ + */ +#define LPTIM_TRIGSOURCE_SOFTWARE 0x0000FFFFU +#define LPTIM_TRIGSOURCE_0 0x00000000U +#define LPTIM_TRIGSOURCE_1 LPTIM_CFGR_TRIGSEL_0 +#define LPTIM_TRIGSOURCE_2 LPTIM_CFGR_TRIGSEL_1 +#define LPTIM_TRIGSOURCE_3 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1) +#define LPTIM_TRIGSOURCE_4 LPTIM_CFGR_TRIGSEL_2 +#define LPTIM_TRIGSOURCE_5 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2) +#define LPTIM_TRIGSOURCE_6 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_2) +#define LPTIM_TRIGSOURCE_7 LPTIM_CFGR_TRIGSEL +/** + * @} + */ + +/** @defgroup LPTIM_External_Trigger_Polarity LPTIM External Trigger Polarity + * @{ + */ +#define LPTIM_ACTIVEEDGE_RISING LPTIM_CFGR_TRIGEN_0 +#define LPTIM_ACTIVEEDGE_FALLING LPTIM_CFGR_TRIGEN_1 +#define LPTIM_ACTIVEEDGE_RISING_FALLING LPTIM_CFGR_TRIGEN +/** + * @} + */ + +/** @defgroup LPTIM_Trigger_Sample_Time LPTIM Trigger Sample Time + * @{ + */ +#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION 0x00000000U +#define LPTIM_TRIGSAMPLETIME_2TRANSITIONS LPTIM_CFGR_TRGFLT_0 +#define LPTIM_TRIGSAMPLETIME_4TRANSITIONS LPTIM_CFGR_TRGFLT_1 +#define LPTIM_TRIGSAMPLETIME_8TRANSITIONS LPTIM_CFGR_TRGFLT +/** + * @} + */ + +/** @defgroup LPTIM_Updating_Mode LPTIM Updating Mode + * @{ + */ + +#define LPTIM_UPDATE_IMMEDIATE 0x00000000U +#define LPTIM_UPDATE_ENDOFPERIOD LPTIM_CFGR_PRELOAD +/** + * @} + */ + +/** @defgroup LPTIM_Counter_Source LPTIM Counter Source + * @{ + */ + +#define LPTIM_COUNTERSOURCE_INTERNAL 0x00000000U +#define LPTIM_COUNTERSOURCE_EXTERNAL LPTIM_CFGR_COUNTMODE +/** + * @} + */ + +/** @defgroup LPTIM_Input1_Source LPTIM Input1 Source + * @{ + */ + +#define LPTIM_INPUT1SOURCE_GPIO 0x00000000UL /*!< For LPTIM1 and LPTIM2 */ +#if defined(COMP1) +#define LPTIM_INPUT1SOURCE_COMP1 LPTIM_CFGR2_IN1SEL_0 /*!< For LPTIM1 and LPTIM2 */ +#endif /* COMP1 */ +/** + * @} + */ + +/** @defgroup LPTIM_Input2_Source LPTIM Input2 Source + * @{ + */ + +#define LPTIM_INPUT2SOURCE_GPIO 0x00000000UL /*!< For LPTIM1 and LPTIM2 */ +#if defined(COMP2) +#define LPTIM_INPUT2SOURCE_COMP2 LPTIM_CFGR2_IN2SEL_0 /*!< For LPTIM1 and LPTIM2 */ +#endif /* COMP2 */ +/** + * @} + */ + +/** @defgroup LPTIM_Flag_Definition LPTIM Flags Definition + * @{ + */ + +#define LPTIM_FLAG_CC1O LPTIM_ISR_CC1OF +#define LPTIM_FLAG_CC2O LPTIM_ISR_CC2OF +#define LPTIM_FLAG_CC1 LPTIM_ISR_CC1IF +#define LPTIM_FLAG_CC2 LPTIM_ISR_CC2IF +#define LPTIM_FLAG_CMP1OK LPTIM_ISR_CMP1OK +#define LPTIM_FLAG_CMP2OK LPTIM_ISR_CMP2OK +#define LPTIM_FLAG_DIEROK LPTIM_ISR_DIEROK +#define LPTIM_FLAG_REPOK LPTIM_ISR_REPOK +#define LPTIM_FLAG_UPDATE LPTIM_ISR_UE +#define LPTIM_FLAG_DOWN LPTIM_ISR_DOWN +#define LPTIM_FLAG_UP LPTIM_ISR_UP +#define LPTIM_FLAG_ARROK LPTIM_ISR_ARROK +#define LPTIM_FLAG_EXTTRIG LPTIM_ISR_EXTTRIG +#define LPTIM_FLAG_ARRM LPTIM_ISR_ARRM +/** + * @} + */ + +/** @defgroup LPTIM_DMA_sources LPTIM DMA Sources + * @{ + */ +#define LPTIM_DMA_UPDATE LPTIM_DIER_UEDE /*!< DMA request is triggered by the update event */ +#define LPTIM_DMA_CC1 LPTIM_DIER_CC1DE /*!< DMA request is triggered by the capture 1 event */ +#define LPTIM_DMA_CC2 LPTIM_DIER_CC2DE /*!< DMA request is triggered by the capture 2 event */ + +/** + * @} + */ + +/** @defgroup LPTIM_DMA_Handle_index LPTIM DMA Handle Index + * @{ + */ +#define LPTIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */ +#define LPTIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Update event 1 DMA request */ +#define LPTIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Update event 2 DMA request */ +/** + * @} + */ + +/** @defgroup LPTIM_Interrupts_Definition LPTIM Interrupts Definition + * @{ + */ +#define LPTIM_IT_CC1O LPTIM_DIER_CC1OIE +#define LPTIM_IT_CC2O LPTIM_DIER_CC2OIE +#define LPTIM_IT_CC1 LPTIM_DIER_CC1IE +#define LPTIM_IT_CC2 LPTIM_DIER_CC2IE +#define LPTIM_IT_CMP1OK LPTIM_DIER_CMP1OKIE +#define LPTIM_IT_CMP2OK LPTIM_DIER_CMP2OKIE +#define LPTIM_IT_REPOK LPTIM_DIER_REPOKIE +#define LPTIM_IT_UPDATE LPTIM_DIER_UEIE +#define LPTIM_IT_DOWN LPTIM_DIER_DOWNIE +#define LPTIM_IT_UP LPTIM_DIER_UPIE +#define LPTIM_IT_ARROK LPTIM_DIER_ARROKIE +#define LPTIM_IT_EXTTRIG LPTIM_DIER_EXTTRIGIE +#define LPTIM_IT_ARRM LPTIM_DIER_ARRMIE +/** + * @} + */ + +/** @defgroup LPTIM_Channel LPTIM Channel + * @{ + */ +#define LPTIM_CHANNEL_1 LL_LPTIM_CHANNEL_CH1 /*!< Capture/compare channel 1 identifier */ +#define LPTIM_CHANNEL_2 LL_LPTIM_CHANNEL_CH2 /*!< Capture/compare channel 2 identifier */ +/** + * @} + */ + +/** @defgroup LPTIM_Output_Compare_Polarity LPTIM Output Compare Polarity + * @{ + */ +#define LPTIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */ +#define LPTIM_OCPOLARITY_LOW 0x00000001U /*!< Capture/Compare output polarity */ +/** + * @} + */ + +/** @defgroup LPTIM_Input_Capture_Prescaler LPTIM Input Capture Prescaler + * @{ + */ +#define LPTIM_ICPSC_DIV1 0x00000000UL /*!< Capture performed each time an edge is detected on the capture input */ +#define LPTIM_ICPSC_DIV2 LPTIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */ +#define LPTIM_ICPSC_DIV4 LPTIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */ +#define LPTIM_ICPSC_DIV8 (LPTIM_CCMR1_IC1PSC_0|LPTIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 8 events */ +/** + * @} + */ + +/** @defgroup LPTIM_Input_Capture_Polarity LPTIM Input Capture Polarity + * @{ + */ +#define LPTIM_ICPOLARITY_RISING 0x00000000UL /*!< Capture/Compare input rising polarity */ +#define LPTIM_ICPOLARITY_FALLING LPTIM_CCMR1_CC1P_0 /*!< Capture/Compare input falling polarity */ +#define LPTIM_ICPOLARITY_RISING_FALLING (LPTIM_CCMR1_CC1P_0|LPTIM_CCMR1_CC1P_1) /*!< Capture/Compare input rising and falling polarities */ +/** + * @} + */ + +/** @defgroup LPTIM_Input_Capture_Filter LPTIM Input Capture Filter + * @{ + */ +#define LPTIM_ICFLT_CLOCK_DIV1 0x00000000UL /*!< any external input capture signal level change is considered as a valid transition */ +#define LPTIM_ICFLT_CLOCK_DIV2 LPTIM_CCMR1_IC1F_0 /*!< external input capture signal level change must be stable for at least 2 clock periods before it is considered as valid transition */ +#define LPTIM_ICFLT_CLOCK_DIV4 LPTIM_CCMR1_IC1F_1 /*!< external input capture signal level change must be stable for at least 4 clock periods before it is considered as valid transition */ +#define LPTIM_ICFLT_CLOCK_DIV8 (LPTIM_CCMR1_IC1F_0|LPTIM_CCMR1_IC1F_1) /*!< external input capture signal level change must be stable for at least 8 clock periods before it is considered as valid transition */ +/** + * @} + */ + +/** @defgroup LPTIM_Input_Capture_Source LPTIM Input Capture Source + * @{ + */ +#define LPTIM_IC1SOURCE_GPIO 0x00000000UL /*!< For LPTIM1 and LPTIM2 */ +#if defined(COMP1) && defined(COMP2) +#define LPTIM_IC1SOURCE_COMP1 LPTIM_CFGR2_IC1SEL_0 /*!< For LPTIM1 and LPTIM2 */ +#define LPTIM_IC1SOURCE_COMP2 LPTIM_CFGR2_IC1SEL_1 /*!< For LPTIM1 and LPTIM2 */ +#endif /* COMP1 && COMP2 */ +#define LPTIM_IC2SOURCE_GPIO 0x00000000UL /*!< For LPTIM1 and LPTIM2 */ +#define LPTIM_IC2SOURCE_LSI LPTIM_CFGR2_IC2SEL_0 /*!< For LPTIM1 */ +#define LPTIM_IC2SOURCE_LSE LPTIM_CFGR2_IC2SEL_1 /*!< For LPTIM1 */ +#define LPTIM_IC2SOURCE_HSI_256 LPTIM_CFGR2_IC2SEL_0 /*!< For LPTIM2 */ +/** + * @} + */ +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup LPTIM_Exported_Macros LPTIM Exported Macros + * @{ + */ + +/** @brief Reset LPTIM handle state. + * @param __HANDLE__ LPTIM handle + * @retval None + */ +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) +#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_LPTIM_STATE_RESET; \ + (__HANDLE__)->ChannelState[0] = HAL_LPTIM_CHANNEL_STATE_RESET;\ + (__HANDLE__)->ChannelState[1] = HAL_LPTIM_CHANNEL_STATE_RESET;\ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_LPTIM_STATE_RESET; \ + (__HANDLE__)->ChannelState[0] = HAL_LPTIM_CHANNEL_STATE_RESET;\ + (__HANDLE__)->ChannelState[1] = HAL_LPTIM_CHANNEL_STATE_RESET;\ + } while(0) +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + +/** + * @brief Enable the LPTIM peripheral. + * @param __HANDLE__ LPTIM handle + * @retval None + */ +#define __HAL_LPTIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (LPTIM_CR_ENABLE)) + +/** + * @brief Disable the LPTIM peripheral. + * @param __HANDLE__ LPTIM handle + * @retval None + */ +#define __HAL_LPTIM_DISABLE(__HANDLE__) \ + do { \ + if (((__HANDLE__)->Instance->CCMR1 & LPTIM_CCMR1_CC1E) == 0UL) \ + { \ + if(((__HANDLE__)->Instance->CCMR1 & LPTIM_CCMR1_CC2E) == 0UL) \ + { \ + (__HANDLE__)->Instance->CR &= ~(LPTIM_CR_ENABLE); \ + } \ + } \ + } while(0) + +/** + * @brief Start the LPTIM peripheral in Continuous mode. + * @param __HANDLE__ LPTIM handle + * @retval None + */ +#define __HAL_LPTIM_START_CONTINUOUS(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_CNTSTRT) +/** + * @brief Start the LPTIM peripheral in single mode. + * @param __HANDLE__ LPTIM handle + * @retval None + */ +#define __HAL_LPTIM_START_SINGLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_SNGSTRT) + +/** + * @brief Reset the LPTIM Counter register in synchronous mode. + * @param __HANDLE__ LPTIM handle + * @retval None + */ +#define __HAL_LPTIM_RESET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_COUNTRST) + +/** + * @brief Reset after read of the LPTIM Counter register in asynchronous mode. + * @param __HANDLE__ LPTIM handle + * @retval None + */ +#define __HAL_LPTIM_RESET_COUNTER_AFTERREAD(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_RSTARE) + +/** + * @brief Write the passed parameter in the Autoreload register. + * @param __HANDLE__ LPTIM handle + * @param __VALUE__ Autoreload value + * @retval None + * @note The ARR register can only be modified when the LPTIM instance is enabled. + */ +#define __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->ARR = (__VALUE__)) + +/** + * @brief Write the passed parameter in the Compare register. + * @param __HANDLE__ LPTIM handle + * @param __VALUE__ Compare value + * @param __CHANNEL__ TIM Channel to be configured + * @retval None + * @note The CCRx registers can only be modified when the LPTIM instance is enabled. + */ +#define __HAL_LPTIM_COMPARE_SET(__HANDLE__ , __CHANNEL__, __VALUE__) \ + (((__CHANNEL__) == LPTIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__VALUE__)) :\ + ((__CHANNEL__) == LPTIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__VALUE__)) : 0U) + +/** + * @brief Write the passed parameter in the Repetition register. + * @param __HANDLE__ LPTIM handle + * @param __VALUE__ Repetition value + * @retval None + */ +#define __HAL_LPTIM_REPETITIONCOUNTER_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->RCR = (__VALUE__)) + +/** + * @brief Return the current Repetition value. + * @param __HANDLE__ LPTIM handle + * @retval Repetition register value + * @note The RCR register can only be modified when the LPTIM instance is enabled. + */ +#define __HAL_LPTIM_REPETITIONCOUNTER_GET(__HANDLE__) ((__HANDLE__)->Instance->RCR) + +/** + * @brief Enable the LPTIM signal input/output on the corresponding pin. + * @param __HANDLE__ LPTIM handle + * @param __CHANNEL__ LPTIM Channels to be enabled. + * This parameter can be one of the following values: + * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected + * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected + * @retval None + */ +#define __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(__HANDLE__, __CHANNEL__) \ + do { \ + switch (__CHANNEL__) \ + { \ + case LPTIM_CHANNEL_1: \ + ((__HANDLE__)->Instance->CCMR1 |= LPTIM_CCMR1_CC1E); \ + break; \ + case LPTIM_CHANNEL_2: \ + ((__HANDLE__)->Instance->CCMR1 |= LPTIM_CCMR1_CC2E); \ + break; \ + default: \ + break; \ + } \ + } \ + while(0) + +/** + * @brief Disable the LPTIM signal input/output on the corresponding pin. + * @param __HANDLE__ LPTIM handle + * @param __CHANNEL__ LPTIM Channels to be disabled. + * This parameter can be one of the following values: + * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected + * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected + * @retval None + */ +#define __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(__HANDLE__, __CHANNEL__) \ + do { \ + switch (__CHANNEL__) \ + { \ + case LPTIM_CHANNEL_1: \ + ((__HANDLE__)->Instance->CCMR1 &= ~LPTIM_CCMR1_CC1E); \ + break; \ + case LPTIM_CHANNEL_2: \ + ((__HANDLE__)->Instance->CCMR1 &= ~LPTIM_CCMR1_CC2E); \ + break; \ + default: \ + break; \ + } \ + } \ + while(0) + +/** + * @brief Check whether the specified LPTIM flag is set or not. + * @param __HANDLE__ LPTIM handle + * @param __FLAG__ LPTIM flag to check + * This parameter can be a value of: + * @arg LPTIM_FLAG_REPOK : Repetition register update OK Flag. + * @arg LPTIM_FLAG_UPDATE : Update event Flag. + * @arg LPTIM_FLAG_DOWN : Counter direction change up Flag. + * @arg LPTIM_FLAG_UP : Counter direction change down to up Flag. + * @arg LPTIM_FLAG_ARROK : Autoreload register update OK Flag. + * @arg LPTIM_FLAG_CMP1OK : Compare register 1 update OK Flag. + * @arg LPTIM_FLAG_CMP2OK : Compare register 2 update OK Flag. + * @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag. + * @arg LPTIM_FLAG_ARRM : Autoreload match Flag. + * @arg LPTIM_FLAG_CC1 : Capture/Compare 1 interrupt flag. + * @arg LPTIM_FLAG_CC2 : Capture/Compare 2 interrupt flag. + * @arg LPTIM_FLAG_CC1O : Capture/Compare 1 over-capture flag. + * @arg LPTIM_FLAG_CC2O : Capture/Compare 2 over-capture flag. + * @arg LPTIM_FLAG_DIEROK : DMA & interrupt enable update OK flag. + * @retval The state of the specified flag (SET or RESET). + */ +#define __HAL_LPTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR &(__FLAG__)) == (__FLAG__)) + +/** + * @brief Clear the specified LPTIM flag. + * @param __HANDLE__ LPTIM handle. + * @param __FLAG__ LPTIM flag to clear. + * This parameter can be a value of: + * @arg LPTIM_FLAG_REPOK : Repetition register update OK Flag. + * @arg LPTIM_FLAG_UPDATE : Update event Flag. + * @arg LPTIM_FLAG_DOWN : Counter direction change up Flag. + * @arg LPTIM_FLAG_UP : Counter direction change down to up Flag. + * @arg LPTIM_FLAG_ARROK : Autoreload register update OK Flag. + * @arg LPTIM_FLAG_CMP1OK : Compare register 1 update OK Flag. + * @arg LPTIM_FLAG_CMP2OK : Compare register 2 update OK Flag. + * @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag. + * @arg LPTIM_FLAG_ARRM : Autoreload match Flag. + * @arg LPTIM_FLAG_CC1 : Capture/Compare 1 interrupt flag. + * @arg LPTIM_FLAG_CC2 : Capture/Compare 2 interrupt flag. + * @arg LPTIM_FLAG_CC1O : Capture/Compare 1 over-capture flag. + * @arg LPTIM_FLAG_CC2O : Capture/Compare 2 over-capture flag. + * @arg LPTIM_FLAG_DIEROK : DMA & interrupt enable update OK flag. + * @retval None. + */ +#define __HAL_LPTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) + +/** + * @brief Enable the specified LPTIM interrupt. + * @param __HANDLE__ LPTIM handle. + * @param __INTERRUPT__ LPTIM interrupt to set. + * This parameter can be a value of: + * @arg LPTIM_IT_REPOK : Repetition register update OK Interrupt. + * @arg LPTIM_IT_UPDATE : Update event register Interrupt. + * @arg LPTIM_IT_DOWN : Counter direction change up Interrupt. + * @arg LPTIM_IT_UP : Counter direction change down to up Interrupt. + * @arg LPTIM_IT_ARROK : Autoreload register update OK Interrupt. + * @arg LPTIM_IT_CMP1OK : Compare register 1 update OK Interrupt. + * @arg LPTIM_IT_CMP2OK : Compare register 2 update OK Interrupt. + * @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt. + * @arg LPTIM_IT_ARRM : Autoreload match Interrupt. + * @arg LPTIM_IT_CC1 : Capture/Compare 1 interrupt Interrupt. + * @arg LPTIM_IT_CC2 : Capture/Compare 2 interrupt Interrupt. + * @arg LPTIM_IT_CC1O : Capture/Compare 1 over-capture Interrupt. + * @arg LPTIM_IT_CC2O : Capture/Compare 2 over-capture Interrupt. + * @retval None. + * @note The LPTIM interrupts can only be enabled when the LPTIM instance is enabled. + */ +#define __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) + +/** + * @brief Disable the specified LPTIM interrupt. + * @param __HANDLE__ LPTIM handle. + * @param __INTERRUPT__ LPTIM interrupt to set. + * This parameter can be a value of: + * @arg LPTIM_IT_REPOK : Repetition register update OK Interrupt. + * @arg LPTIM_IT_UPDATE : Update event register Interrupt. + * @arg LPTIM_IT_DOWN : Counter direction change up Interrupt. + * @arg LPTIM_IT_UP : Counter direction change down to up Interrupt. + * @arg LPTIM_IT_ARROK : Autoreload register update OK Interrupt. + * @arg LPTIM_IT_CMP1OK : Compare register 1 update OK Interrupt. + * @arg LPTIM_IT_CMP2OK : Compare register 2 update OK Interrupt. + * @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt. + * @arg LPTIM_IT_ARRM : Autoreload match Interrupt. + * @arg LPTIM_IT_CC1 : Capture/Compare 1 interrupt Interrupt. + * @arg LPTIM_IT_CC2 : Capture/Compare 2 interrupt Interrupt. + * @arg LPTIM_IT_CC1O : Capture/Compare 1 over-capture Interrupt. + * @arg LPTIM_IT_CC2O : Capture/Compare 2 over-capture Interrupt. + * @retval None. + * @note The LPTIM interrupts can only be disabled when the LPTIM instance is enabled. + */ +#define __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= (~(__INTERRUPT__))) + +/** @brief Enable the specified DMA request. + * @param __HANDLE__ specifies the TIM Handle. + * @param __DMA__ specifies the LPTIM DMA request to enable. + * This parameter can be one of the following values: + * @arg LPTIM_DMA_UPDATE: Update DMA request + * @arg LPTIM_DMA_CC1: Capture/Compare 1 DMA request + * @arg LPTIM_DMA_CC2: Capture/Compare 2 DMA request + * @retval None + */ +#define __HAL_LPTIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) + +/** @brief Disable the specified DMA request. + * @param __HANDLE__ specifies the LPTIM Handle. + * @param __DMA__ specifies the LPTIM DMA request to disable. + * This parameter can be one of the following values: + * @arg LPTIM_DMA_UPDATE: Update DMA request + * @arg LPTIM_DMA_CC1: Capture/Compare 1 DMA request + * @arg LPTIM_DMA_CC2: Capture/Compare 2 DMA request + * @retval None + */ +#define __HAL_LPTIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) + +/** + * @brief Check whether the specified LPTIM interrupt source is enabled or not. + * @param __HANDLE__ LPTIM handle. + * @param __INTERRUPT__ LPTIM interrupt to check. + * This parameter can be a value of: + * @arg LPTIM_IT_REPOK : Repetition register update OK Interrupt. + * @arg LPTIM_IT_UPDATE : Update event register Interrupt. + * @arg LPTIM_IT_DOWN : Counter direction change up Interrupt. + * @arg LPTIM_IT_UP : Counter direction change down to up Interrupt. + * @arg LPTIM_IT_ARROK : Autoreload register update OK Interrupt. + * @arg LPTIM_IT_CMP1OK : Compare register 1 update OK Interrupt. + * @arg LPTIM_IT_CMP2OK : Compare register 2 update OK Interrupt. + * @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt. + * @arg LPTIM_IT_ARRM : Autoreload match Interrupt. + * @arg LPTIM_IT_CC1 : Capture/Compare 1 interrupt Interrupt. + * @arg LPTIM_IT_CC2 : Capture/Compare 2 interrupt Interrupt. + * @arg LPTIM_IT_CC1O : Capture/Compare 1 over-capture Interrupt. + * @arg LPTIM_IT_CC2O : Capture/Compare 2 over-capture Interrupt. + * @retval Interrupt status. + */ + +#define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER\ + & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions + * @{ + */ + +/** @addtogroup LPTIM_Exported_Functions_Group1 + * @brief Initialization and Configuration functions. + * @{ + */ +/* Initialization/de-initialization functions ********************************/ +HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim); +HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim); + +/* MSP functions *************************************************************/ +void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim); +void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim); +/** + * @} + */ + +/** @addtogroup LPTIM_Exported_Functions_Group2 + * @brief Start-Stop operation functions. + * @{ + */ +/* Config functions **********************************************************/ +HAL_StatusTypeDef HAL_LPTIM_OC_ConfigChannel(LPTIM_HandleTypeDef *hlptim, const LPTIM_OC_ConfigTypeDef *sConfig, + uint32_t Channel); + +/* Start/Stop operation functions *********************************************/ +/* ################################# PWM Mode ################################*/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Channel); +HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel); +HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel); +HAL_StatusTypeDef HAL_LPTIM_PWM_Start_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t Channel, const uint32_t *pData, + uint32_t Length); +HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t Channel); + +/* ############################# One Pulse Mode ##############################*/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Channel); +HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel); +HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel); + +/* ############################## Set once Mode ##############################*/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Channel); +HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel); +HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel); + +/* ############################### Encoder Mode ##############################*/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim); +HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim); +HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim); + +/* ############################# Time out Mode ##############################*/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Timeout); +HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Timeout); +HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim); + +/* ############################## Counter Mode ###############################*/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim); +HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim); +HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim); + +/* ############################## Input Capture Mode ###############################*/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_LPTIM_IC_ConfigChannel(LPTIM_HandleTypeDef *hlptim, const LPTIM_IC_ConfigTypeDef *sConfig, + uint32_t Channel); +HAL_StatusTypeDef HAL_LPTIM_IC_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Channel); +HAL_StatusTypeDef HAL_LPTIM_IC_Stop(LPTIM_HandleTypeDef *hlptim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_LPTIM_IC_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel); +HAL_StatusTypeDef HAL_LPTIM_IC_Stop_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel); +HAL_StatusTypeDef HAL_LPTIM_IC_Start_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t Channel, uint32_t *pData, + uint32_t Length); +HAL_StatusTypeDef HAL_LPTIM_IC_Stop_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup LPTIM_Exported_Functions_Group3 + * @brief Read operation functions. + * @{ + */ +/* Reading operation functions ************************************************/ +uint32_t HAL_LPTIM_ReadCounter(const LPTIM_HandleTypeDef *hlptim); +uint32_t HAL_LPTIM_ReadAutoReload(const LPTIM_HandleTypeDef *hlptim); +uint32_t HAL_LPTIM_ReadCapturedValue(const LPTIM_HandleTypeDef *hlptim, uint32_t Channel); +uint8_t HAL_LPTIM_IC_GetOffset(const LPTIM_HandleTypeDef *hlptim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup LPTIM_Exported_Functions_Group4 + * @brief LPTIM IRQ handler and callback functions. + * @{ + */ +/* LPTIM IRQ functions *******************************************************/ +void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim); + +/* CallBack functions ********************************************************/ +void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim); +void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim); +void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim); +void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim); +void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim); +void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim); +void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim); +void HAL_LPTIM_ErrorCallback(LPTIM_HandleTypeDef *hlptim); +void HAL_LPTIM_UpdateEventCallback(LPTIM_HandleTypeDef *hlptim); +void HAL_LPTIM_UpdateEventHalfCpltCallback(LPTIM_HandleTypeDef *hlptim); +void HAL_LPTIM_RepCounterWriteCallback(LPTIM_HandleTypeDef *hlptim); +void HAL_LPTIM_IC_CaptureCallback(LPTIM_HandleTypeDef *hlptim); +void HAL_LPTIM_IC_CaptureHalfCpltCallback(LPTIM_HandleTypeDef *hlptim); +void HAL_LPTIM_IC_OverCaptureCallback(LPTIM_HandleTypeDef *hlptim); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID, + pLPTIM_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @addtogroup LPTIM_Group5 + * @brief Peripheral State functions. + * @{ + */ +/* Peripheral State functions ************************************************/ +HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(const LPTIM_HandleTypeDef *hlptim); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/** @defgroup LPTIM_Private_Types LPTIM Private Types + * @{ + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup LPTIM_Private_Variables LPTIM Private Variables + * @{ + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup LPTIM_Private_Constants LPTIM Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup LPTIM_Private_Macros LPTIM Private Macros + * @{ + */ + +#define IS_LPTIM_CLOCK_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_CLOCKSOURCE_ULPTIM) || \ + ((__SOURCE__) == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC)) + + +#define IS_LPTIM_CLOCK_PRESCALER(__PRESCALER__) (((__PRESCALER__) == LPTIM_PRESCALER_DIV1 ) || \ + ((__PRESCALER__) == LPTIM_PRESCALER_DIV2 ) || \ + ((__PRESCALER__) == LPTIM_PRESCALER_DIV4 ) || \ + ((__PRESCALER__) == LPTIM_PRESCALER_DIV8 ) || \ + ((__PRESCALER__) == LPTIM_PRESCALER_DIV16 ) || \ + ((__PRESCALER__) == LPTIM_PRESCALER_DIV32 ) || \ + ((__PRESCALER__) == LPTIM_PRESCALER_DIV64 ) || \ + ((__PRESCALER__) == LPTIM_PRESCALER_DIV128)) + +#define IS_LPTIM_CLOCK_PRESCALERDIV1(__PRESCALER__) ((__PRESCALER__) == LPTIM_PRESCALER_DIV1) +#define IS_LPTIM_CLOCK_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION) || \ + ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_2TRANSITIONS) || \ + ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_4TRANSITIONS) || \ + ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_8TRANSITIONS)) + +#define IS_LPTIM_CLOCK_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING) || \ + ((__POLARITY__) == LPTIM_CLOCKPOLARITY_FALLING) || \ + ((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING_FALLING)) + +#define IS_LPTIM_TRG_SOURCE(__TRIG__) (((__TRIG__) == LPTIM_TRIGSOURCE_SOFTWARE) || \ + ((__TRIG__) == LPTIM_TRIGSOURCE_0) || \ + ((__TRIG__) == LPTIM_TRIGSOURCE_1) || \ + ((__TRIG__) == LPTIM_TRIGSOURCE_2) || \ + ((__TRIG__) == LPTIM_TRIGSOURCE_3) || \ + ((__TRIG__) == LPTIM_TRIGSOURCE_4) || \ + ((__TRIG__) == LPTIM_TRIGSOURCE_5) || \ + ((__TRIG__) == LPTIM_TRIGSOURCE_6) || \ + ((__TRIG__) == LPTIM_TRIGSOURCE_7)) + +#define IS_LPTIM_EXT_TRG_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING ) || \ + ((__POLARITY__) == LPTIM_ACTIVEEDGE_FALLING ) || \ + ((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING_FALLING )) + +#define IS_LPTIM_TRIG_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION) || \ + ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_2TRANSITIONS ) || \ + ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_4TRANSITIONS ) || \ + ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_8TRANSITIONS )) + +#define IS_LPTIM_UPDATE_MODE(__MODE__) (((__MODE__) == LPTIM_UPDATE_IMMEDIATE) || \ + ((__MODE__) == LPTIM_UPDATE_ENDOFPERIOD)) + +#define IS_LPTIM_COUNTER_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \ + ((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL)) + +#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((0x00000001UL <= (__AUTORELOAD__)) &&\ + ((__AUTORELOAD__) <= 0x0000FFFFUL)) + +#define IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFFUL) + +#define IS_LPTIM_PERIOD(__PERIOD__) ((0x00000001UL <= (__PERIOD__)) &&\ + ((__PERIOD__) <= 0x0000FFFFUL)) + +#define IS_LPTIM_PULSE(__PULSE__) ((__PULSE__) <= 0x0000FFFFUL) + +#define IS_LPTIM_OC_POLARITY(__OCPOLARITY__) (((__OCPOLARITY__) == LPTIM_OCPOLARITY_LOW) || \ + ((__OCPOLARITY__) == LPTIM_OCPOLARITY_HIGH)) +#define IS_LPTIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == LPTIM_ICPSC_DIV1) ||\ + ((__PRESCALER__) == LPTIM_ICPSC_DIV2) ||\ + ((__PRESCALER__) == LPTIM_ICPSC_DIV4) ||\ + ((__PRESCALER__) == LPTIM_ICPSC_DIV8)) + +#define IS_LPTIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_ICPOLARITY_RISING) || \ + ((__POLARITY__) == LPTIM_ICPOLARITY_FALLING) ||\ + ((__POLARITY__) == LPTIM_ICPOLARITY_RISING_FALLING)) + +#define IS_LPTIM_IC_FILTER(__FILTER__) (((__FILTER__) == LPTIM_ICFLT_CLOCK_DIV1) ||\ + ((__FILTER__) == LPTIM_ICFLT_CLOCK_DIV2) ||\ + ((__FILTER__) == LPTIM_ICFLT_CLOCK_DIV4) ||\ + ((__FILTER__) == LPTIM_ICFLT_CLOCK_DIV8)) + +#define IS_LPTIM_REPETITION(__REPETITION__) ((__REPETITION__) <= 0x000000FFUL) + +#if defined(LPTIM2) +#if defined(COMP1) +#define IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__) \ + ((((__INSTANCE__) == LPTIM1) || \ + ((__INSTANCE__) == LPTIM2)) && \ + (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \ + ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1))) +#else +#define IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__) \ + ((((__INSTANCE__) == LPTIM1) || \ + ((__INSTANCE__) == LPTIM2)) && \ + (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO))) +#endif /* COMP1 */ +#else +#if defined(COMP1) +#define IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__) \ + (((__INSTANCE__) == LPTIM1) && \ + (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \ + ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1))) +#else +#define IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__) \ + (((__INSTANCE__) == LPTIM1) && \ + (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO))) +#endif /* COMP1*/ +#endif /* LPTIM2 */ + +#if defined(LPTIM2) +#if defined(COMP2) +#define IS_LPTIM_INPUT2_SOURCE(__INSTANCE__, __SOURCE__) \ + ((((__INSTANCE__) == LPTIM1) || \ + ((__INSTANCE__) == LPTIM2)) && \ + (((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO) || \ + ((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP2))) +#else +#define IS_LPTIM_INPUT2_SOURCE(__INSTANCE__, __SOURCE__) \ + ((((__INSTANCE__) == LPTIM1) || \ + ((__INSTANCE__) == LPTIM2)) && \ + (((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO))) +#endif /* COMP2 */ +#else +#if defined(COMP2) +#define IS_LPTIM_INPUT2_SOURCE(__INSTANCE__, __SOURCE__) \ + (((__INSTANCE__) == LPTIM1) && \ + (((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO) || \ + ((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP2))) +#else +#define IS_LPTIM_INPUT2_SOURCE(__INSTANCE__, __SOURCE__) \ + (((__INSTANCE__) == LPTIM1) && \ + (((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO))) +#endif /* COMP2 */ +#endif /* LPTIM2 */ + +#if defined(LPTIM2) +#if defined(COMP1) && defined(COMP2) +#define IS_LPTIM_IC1_SOURCE(__INSTANCE__, __SOURCE__) \ + ((((__INSTANCE__) == LPTIM1) || \ + ((__INSTANCE__) == LPTIM2)) && \ + (((__SOURCE__) == LPTIM_IC1SOURCE_GPIO) || \ + ((__SOURCE__) == LPTIM_IC1SOURCE_COMP1) || \ + ((__SOURCE__) == LPTIM_IC1SOURCE_COMP2))) +#else +#define IS_LPTIM_IC1_SOURCE(__INSTANCE__, __SOURCE__) \ + ((((__INSTANCE__) == LPTIM1) || \ + ((__INSTANCE__) == LPTIM2)) && \ + (((__SOURCE__) == LPTIM_IC1SOURCE_GPIO))) +#endif /* COMP1 && COMP2 */ + +#define IS_LPTIM_IC2_SOURCE(__INSTANCE__, __SOURCE__) \ + ((((__INSTANCE__) == LPTIM1) && \ + (((__SOURCE__) == LPTIM_IC2SOURCE_GPIO) || \ + ((__SOURCE__) == LPTIM_IC2SOURCE_LSI) || \ + ((__SOURCE__) == LPTIM_IC2SOURCE_LSE))) \ + || \ + (((__INSTANCE__) == LPTIM2) && \ + (((__SOURCE__) == LPTIM_IC2SOURCE_GPIO) || \ + ((__SOURCE__) == LPTIM_IC2SOURCE_HSI_256)))) +#else +#if defined(COMP1) && defined(COMP2) +#define IS_LPTIM_IC1_SOURCE(__INSTANCE__, __SOURCE__) \ + (((__INSTANCE__) == LPTIM1) && \ + (((__SOURCE__) == LPTIM_IC1SOURCE_GPIO) || \ + ((__SOURCE__) == LPTIM_IC1SOURCE_COMP1) || \ + ((__SOURCE__) == LPTIM_IC1SOURCE_COMP2))) +#else +#define IS_LPTIM_IC1_SOURCE(__INSTANCE__, __SOURCE__) \ + (((__INSTANCE__) == LPTIM1) && \ + (((__SOURCE__) == LPTIM_IC1SOURCE_GPIO))) +#endif /* COMP1 && COMP2 */ + +#define IS_LPTIM_IC2_SOURCE(__INSTANCE__, __SOURCE__) \ + (((__INSTANCE__) == LPTIM1) && \ + (((__SOURCE__) == LPTIM_IC2SOURCE_GPIO) || \ + ((__SOURCE__) == LPTIM_IC2SOURCE_LSI) || \ + ((__SOURCE__) == LPTIM_IC2SOURCE_LSE))) +#endif /* LPTIM2 */ + +#define LPTIM_CHANNEL_STATE_GET(__INSTANCE__, __CHANNEL__)\ + (((__CHANNEL__) == LPTIM_CHANNEL_1) ? (__INSTANCE__)->ChannelState[0] :\ + (__INSTANCE__)->ChannelState[1]) + +#define LPTIM_CHANNEL_STATE_SET(__INSTANCE__, __CHANNEL__, __CHANNEL_STATE__) \ + (((__CHANNEL__) == LPTIM_CHANNEL_1) ? ((__INSTANCE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\ + ((__INSTANCE__)->ChannelState[1] = (__CHANNEL_STATE__))) + +#define LPTIM_CHANNEL_STATE_SET_ALL(__INSTANCE__, __CHANNEL_STATE__) do { \ + (__INSTANCE__)->ChannelState[0] =\ + (__CHANNEL_STATE__); \ + (__INSTANCE__)->ChannelState[1] =\ + (__CHANNEL_STATE__); \ + } while(0) + +#if defined(LPTIM2) +#define IS_LPTIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) \ + ((((__INSTANCE__) == LPTIM1) && \ + (((__CHANNEL__) == LPTIM_CHANNEL_1) || \ + ((__CHANNEL__) == LPTIM_CHANNEL_2))) \ + || \ + (((__INSTANCE__) == LPTIM2) && \ + (((__CHANNEL__) == LPTIM_CHANNEL_1) || \ + ((__CHANNEL__) == LPTIM_CHANNEL_2)))) +#else +#define IS_LPTIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) \ + (((__INSTANCE__) == LPTIM1) && \ + (((__CHANNEL__) == LPTIM_CHANNEL_1) || \ + ((__CHANNEL__) == LPTIM_CHANNEL_2))) +#endif /* LPTIM2 */ +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup LPTIM_Private_Functions LPTIM Private Functions + * @{ + */ +/** + * @} + */ + +/** + * @} + */ + +#endif /* LPTIM1 || LPTIM2 */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WBAxx_HAL_LPTIM_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_pka.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_pka.h new file mode 100644 index 0000000000..3ec411a3ec --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_pka.h @@ -0,0 +1,670 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_pka.h + * @author MCD Application Team + * @brief Header file of PKA HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_HAL_PKA_H +#define STM32WBAxx_HAL_PKA_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal_def.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +#if defined(PKA) && defined(HAL_PKA_MODULE_ENABLED) + +/** @addtogroup PKA + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup PKA_Exported_Types PKA Exported Types + * @{ + */ + +/** @defgroup HAL_state_structure_definition HAL state structure definition + * @brief HAL State structures definition + * @{ + */ +typedef enum +{ + HAL_PKA_STATE_RESET = 0x00U, /*!< PKA not yet initialized or disabled */ + HAL_PKA_STATE_READY = 0x01U, /*!< PKA initialized and ready for use */ + HAL_PKA_STATE_BUSY = 0x02U, /*!< PKA internal processing is ongoing */ + HAL_PKA_STATE_ERROR = 0x03U, /*!< PKA error state */ +} +HAL_PKA_StateTypeDef; + +/** + * @} + */ + +#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1) +/** @defgroup HAL_callback_id HAL callback ID enumeration + * @{ + */ +typedef enum +{ + HAL_PKA_OPERATION_COMPLETE_CB_ID = 0x00U, /*!< PKA End of operation callback ID */ + HAL_PKA_ERROR_CB_ID = 0x01U, /*!< PKA Error callback ID */ + HAL_PKA_MSPINIT_CB_ID = 0x02U, /*!< PKA Msp Init callback ID */ + HAL_PKA_MSPDEINIT_CB_ID = 0x03U /*!< PKA Msp DeInit callback ID */ +} HAL_PKA_CallbackIDTypeDef; + +/** + * @} + */ + +#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */ + +/** @defgroup PKA_Error_Code_definition PKA Error Code definition + * @brief PKA Error Code definition + * @{ + */ +#define HAL_PKA_ERROR_NONE (0x00000000U) +#define HAL_PKA_ERROR_ADDRERR (0x00000001U) +#define HAL_PKA_ERROR_RAMERR (0x00000002U) +#define HAL_PKA_ERROR_TIMEOUT (0x00000004U) +#define HAL_PKA_ERROR_OPERATION (0x00000008U) +#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1) +#define HAL_PKA_ERROR_INVALID_CALLBACK (0x00000010U) /*!< Invalid Callback error */ +#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup PKA_handle_Structure_definition PKA handle Structure definition + * @brief PKA handle Structure definition + * @{ + */ +#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1) +typedef struct __PKA_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */ +{ + PKA_TypeDef *Instance; /*!< Register base address */ + __IO HAL_PKA_StateTypeDef State; /*!< PKA state */ + __IO uint32_t ErrorCode; /*!< PKA Error code */ +#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1) + void (* OperationCpltCallback)(struct __PKA_HandleTypeDef *hpka); /*!< PKA End of operation callback */ + void (* ErrorCallback)(struct __PKA_HandleTypeDef *hpka); /*!< PKA Error callback */ + void (* MspInitCallback)(struct __PKA_HandleTypeDef *hpka); /*!< PKA Msp Init callback */ + void (* MspDeInitCallback)(struct __PKA_HandleTypeDef *hpka); /*!< PKA Msp DeInit callback */ +#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */ +} PKA_HandleTypeDef; +/** + * @} + */ + +#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1) +/** @defgroup PKA_Callback_definition PKA Callback pointer definition + * @brief PKA Callback pointer definition + * @{ + */ +typedef void (*pPKA_CallbackTypeDef)(PKA_HandleTypeDef *hpka); /*!< Pointer to a PKA callback function */ +/** + * @} + */ +#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */ +/** @defgroup PKA_Operation PKA operation structure definition + * @brief Input and output data definition + * @{ + */ + +typedef struct +{ + uint32_t scalarMulSize; /*!< Number of element in scalarMul array */ + uint32_t modulusSize; /*!< Number of element in modulus, coefA, pointX and pointY arrays */ + uint32_t coefSign; /*!< Curve coefficient a sign */ + const uint8_t *coefA; /*!< Pointer to curve coefficient |a| (Array of modulusSize elements) */ + const uint8_t *coefB; /*!< pointer to curve coefficient b */ + const uint8_t *modulus; /*!< Pointer to curve modulus value p (Array of modulusSize elements) */ + const uint8_t *pointX; /*!< Pointer to point P coordinate xP (Array of modulusSize elements) */ + const uint8_t *pointY; /*!< Pointer to point P coordinate yP (Array of modulusSize elements) */ + const uint8_t *scalarMul; /*!< Pointer to scalar multiplier k (Array of scalarMulSize elements) */ + const uint8_t *primeOrder; /*!< pointer to order of the curve */ +} PKA_ECCMulInTypeDef; + +typedef struct +{ + uint32_t primeOrderSize; /*!< Number of element in primeOrder array */ + uint32_t scalarMulSize; /*!< Number of element in scalarMul array */ + uint32_t modulusSize; /*!< Number of element in modulus, coefA, pointX and pointY arrays */ + uint32_t coefSign; /*!< Curve coefficient a sign */ + const uint8_t *coefA; /*!< Pointer to curve coefficient |a| (Array of modulusSize elements) */ + const uint8_t *coefB; /*!< pointer to curve coefficient b */ + const uint8_t *modulus; /*!< Pointer to curve modulus value p (Array of modulusSize elements) */ + const uint8_t *pointX; /*!< Pointer to point P coordinate xP (Array of modulusSize elements) */ + const uint8_t *pointY; /*!< Pointer to point P coordinate yP (Array of modulusSize elements) */ + const uint8_t *scalarMul; /*!< Pointer to scalar multiplier k (Array of scalarMulSize elements) */ + const uint8_t *primeOrder; /*!< pointer to order of the curve */ +} PKA_ECCMulExInTypeDef; + +typedef struct +{ + uint32_t modulusSize; /*!< Number of element in coefA, coefB, modulus, pointX and pointY arrays */ + uint32_t coefSign; /*!< Curve coefficient a sign */ + const uint8_t *coefA; /*!< Pointer to curve coefficient |a| (Array of modulusSize elements) */ + const uint8_t *coefB; /*!< Pointer to curve coefficient b (Array of modulusSize elements) */ + const uint8_t *modulus; /*!< Pointer to curve modulus value p (Array of modulusSize elements) */ + const uint8_t *pointX; /*!< Pointer to point P coordinate xP (Array of modulusSize elements) */ + const uint8_t *pointY; /*!< Pointer to point P coordinate yP (Array of modulusSize elements) */ + const uint32_t *pMontgomeryParam; /*!< pointer to montgomery param R2 (modulus N) */ +} PKA_PointCheckInTypeDef; + +typedef struct +{ + uint32_t size; /*!< Number of element in popA array */ + const uint8_t *pOpDp; /*!< Pointer to operand dP (Array of size/2 elements) */ + const uint8_t *pOpDq; /*!< Pointer to operand dQ (Array of size/2 elements) */ + const uint8_t *pOpQinv; /*!< Pointer to operand qinv (Array of size/2 elements) */ + const uint8_t *pPrimeP; /*!< Pointer to prime p (Array of size/2 elements) */ + const uint8_t *pPrimeQ; /*!< Pointer to prime Q (Array of size/2 elements) */ + const uint8_t *popA; /*!< Pointer to operand A (Array of size elements) */ +} PKA_RSACRTExpInTypeDef; + +typedef struct +{ + uint32_t primeOrderSize; /*!< Number of element in primeOrder array */ + uint32_t modulusSize; /*!< Number of element in modulus array */ + uint32_t coefSign; /*!< Curve coefficient a sign */ + const uint8_t *coef; /*!< Pointer to curve coefficient |a| (Array of modulusSize elements) */ + const uint8_t *modulus; /*!< Pointer to curve modulus value p (Array of modulusSize elements) */ + const uint8_t *basePointX; /*!< Pointer to curve base point xG (Array of modulusSize elements) */ + const uint8_t *basePointY; /*!< Pointer to curve base point yG (Array of modulusSize elements) */ + const uint8_t *pPubKeyCurvePtX; /*!< Pointer to public-key curve point xQ (Array of modulusSize elements) */ + const uint8_t *pPubKeyCurvePtY; /*!< Pointer to public-key curve point yQ (Array of modulusSize elements) */ + const uint8_t *RSign; /*!< Pointer to signature part r (Array of primeOrderSize elements) */ + const uint8_t *SSign; /*!< Pointer to signature part s (Array of primeOrderSize elements) */ + const uint8_t *hash; /*!< Pointer to hash of the message e (Array of primeOrderSize elements) */ + const uint8_t *primeOrder; /*!< Pointer to order of the curve n (Array of primeOrderSize elements) */ +} PKA_ECDSAVerifInTypeDef; + +typedef struct +{ + uint32_t primeOrderSize; /*!< Number of element in primeOrder array */ + uint32_t modulusSize; /*!< Number of element in modulus array */ + uint32_t coefSign; /*!< Curve coefficient a sign */ + const uint8_t *coef; /*!< Pointer to curve coefficient |a| (Array of modulusSize elements) */ + const uint8_t *coefB; /*!< Pointer to B coefficient (Array of modulusSize elements) */ + const uint8_t *modulus; /*!< Pointer to curve modulus value p (Array of modulusSize elements) */ + const uint8_t *integer; /*!< Pointer to random integer k (Array of primeOrderSize elements) */ + const uint8_t *basePointX; /*!< Pointer to curve base point xG (Array of modulusSize elements) */ + const uint8_t *basePointY; /*!< Pointer to curve base point yG (Array of modulusSize elements) */ + const uint8_t *hash; /*!< Pointer to hash of the message (Array of primeOrderSize elements) */ + const uint8_t *privateKey; /*!< Pointer to private key d (Array of primeOrderSize elements) */ + const uint8_t *primeOrder; /*!< Pointer to order of the curve n (Array of primeOrderSize elements) */ +} PKA_ECDSASignInTypeDef; + +typedef struct +{ + uint8_t *RSign; /*!< Pointer to signature part r (Array of modulusSize elements) */ + uint8_t *SSign; /*!< Pointer to signature part s (Array of modulusSize elements) */ +} PKA_ECDSASignOutTypeDef; + +typedef struct +{ + uint8_t *ptX; /*!< Pointer to point P coordinate xP (Array of modulusSize elements) */ + uint8_t *ptY; /*!< Pointer to point P coordinate yP (Array of modulusSize elements) */ +} PKA_ECDSASignOutExtParamTypeDef, PKA_ECCMulOutTypeDef, PKA_ECCProjective2AffineOutTypeDef, +PKA_ECCDoubleBaseLadderOutTypeDef; + +typedef struct +{ + uint8_t *ptX; /*!< pointer to point P coordinate xP */ + uint8_t *ptY; /*!< pointer to point P coordinate yP */ + uint8_t *ptZ; /*!< pointer to point P coordinate zP */ +} PKA_ECCCompleteAdditionOutTypeDef; + +typedef struct +{ + uint32_t expSize; /*!< Number of element in pExp array */ + uint32_t OpSize; /*!< Number of element in pOp1 and pMod arrays */ + const uint8_t *pExp; /*!< Pointer to Exponent (Array of expSize elements) */ + const uint8_t *pOp1; /*!< Pointer to Operand (Array of OpSize elements) */ + const uint8_t *pMod; /*!< Pointer to modulus (Array of OpSize elements) */ +} PKA_ModExpInTypeDef; + +typedef struct +{ + uint32_t expSize; /*!< Size of the operand in bytes */ + uint32_t OpSize; /*!< Size of the operand in bytes */ + const uint8_t *pOp1; /*!< Pointer to Operand 1 */ + const uint8_t *pExp; /*!< Pointer to Exponent */ + const uint8_t *pMod; /*!< Pointer to Operand 1 */ + const uint8_t *pPhi; /*!< Pointer to Phi value */ +} PKA_ModExpProtectModeInTypeDef; + +typedef struct +{ + uint32_t expSize; /*!< Number of element in pExp and pMontgomeryParam arrays */ + uint32_t OpSize; /*!< Number of element in pOp1 and pMod arrays */ + const uint8_t *pExp; /*!< Pointer to Exponent (Array of expSize elements) */ + const uint8_t *pOp1; /*!< Pointer to Operand (Array of OpSize elements) */ + const uint8_t *pMod; /*!< Pointer to modulus (Array of OpSize elements) */ + const uint32_t *pMontgomeryParam; /*!< Pointer to Montgomery parameter (Array of expSize/4 elements) */ +} PKA_ModExpFastModeInTypeDef; + +typedef struct +{ + uint32_t size; /*!< Number of element in pOp1 array */ + const uint8_t *pOp1; /*!< Pointer to Operand (Array of size elements) */ +} PKA_MontgomeryParamInTypeDef; + +typedef struct +{ + uint32_t size; /*!< Number of element in pOp1 and pOp2 arrays */ + const uint32_t *pOp1; /*!< Pointer to Operand 1 (Array of size elements) */ + const uint32_t *pOp2; /*!< Pointer to Operand 2 (Array of size elements) */ +} PKA_AddInTypeDef, PKA_SubInTypeDef, PKA_MulInTypeDef, PKA_CmpInTypeDef; + +typedef struct +{ + uint32_t size; /*!< Number of element in pOp1 array */ + const uint32_t *pOp1; /*!< Pointer to Operand 1 (Array of size elements) */ + const uint8_t *pMod; /*!< Pointer to modulus value n (Array of size*4 elements) */ +} PKA_ModInvInTypeDef; + +typedef struct +{ + uint32_t OpSize; /*!< Number of element in pOp1 array */ + uint32_t modSize; /*!< Number of element in pMod array */ + const uint32_t *pOp1; /*!< Pointer to Operand 1 (Array of OpSize elements) */ + const uint8_t *pMod; /*!< Pointer to modulus value n (Array of modSize elements) */ +} PKA_ModRedInTypeDef; + +typedef struct +{ + uint32_t size; /*!< Number of element in pOp1 and pOp2 arrays */ + const uint32_t *pOp1; /*!< Pointer to Operand 1 (Array of size elements) */ + const uint32_t *pOp2; /*!< Pointer to Operand 2 (Array of size elements) */ + const uint8_t *pOp3; /*!< Pointer to Operand 3 (Array of size*4 elements) */ +} PKA_ModAddInTypeDef, PKA_ModSubInTypeDef, PKA_MontgomeryMulInTypeDef; + +typedef struct +{ + uint32_t primeOrderSize; /*!< curve prime order n length */ + uint32_t modulusSize; /*!< curve modulus p length */ + uint32_t coefSign; /*!< curve coefficient a sign */ + const uint8_t *coefA; /*!< pointer to curve coefficient |a| */ + const uint8_t *modulus; /*!< pointer to curve modulus value p */ + const uint8_t *integerK; /*!< pointer to cryptographically secure random integer k */ + const uint8_t *integerM; /*!< pointer to cryptographically secure random integer m */ + const uint8_t *basePointX1; /*!< pointer to curve base first point coordinate x */ + const uint8_t *basePointY1; /*!< pointer to curve base first point coordinate y */ + const uint8_t *basePointZ1; /*!< pointer to curve base first point coordinate z */ + const uint8_t *basePointX2; /*!< pointer to curve base second point coordinate x */ + const uint8_t *basePointY2; /*!< pointer to curve base second point coordinate y */ + const uint8_t *basePointZ2; /*!< pointer to curve base second point coordinate z */ +} PKA_ECCDoubleBaseLadderInTypeDef; + +typedef struct +{ + uint32_t modulusSize; /*!< curve modulus p length */ + const uint8_t *modulus; /*!< pointer to curve modulus value p */ + const uint8_t *basePointX; /*!< pointer to curve base point coordinate x */ + const uint8_t *basePointY; /*!< pointer to curve base point coordinate y */ + const uint8_t *basePointZ; /*!< pointer to curve base point coordinate z */ + const uint32_t *pMontgomeryParam; /*!< pointer to montgomery parameter R2 modulus n*/ +} PKA_ECCProjective2AffineInTypeDef; + +typedef struct +{ + uint32_t modulusSize; /*!< curve modulus p length */ + uint32_t coefSign; /*!< curve coefficient a sign */ + const uint8_t *modulus; /*!< pointer to curve modulus value p */ + const uint8_t *coefA; /*!< pointer to curve coefficient |a| */ + const uint8_t *basePointX1; /*!< pointer to curve base first point coordinate x */ + const uint8_t *basePointY1; /*!< pointer to curve base first point coordinate y */ + const uint8_t *basePointZ1; /*!< pointer to curve base first point coordinate z */ + const uint8_t *basePointX2; /*!< pointer to curve base second point coordinate x */ + const uint8_t *basePointY2; /*!< pointer to curve base second point coordinate y */ + const uint8_t *basePointZ2; /*!< pointer to curve base second point coordinate z */ +} PKA_ECCCompleteAdditionInTypeDef; +/** + * @} + */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup PKA_Exported_Constants PKA Exported Constants + * @{ + */ + +/** @defgroup PKA_Mode PKA mode + * @{ + */ +#define PKA_MODE_MONTGOMERY_PARAM (0x00000001U) +#define PKA_MODE_MODULAR_EXP (0x00000000U) +#define PKA_MODE_MODULAR_EXP_FAST_MODE (0x00000002U) +#define PKA_MODE_ECC_MUL (0x00000020U) +#define PKA_MODE_ECDSA_SIGNATURE (0x00000024U) +#define PKA_MODE_ECDSA_VERIFICATION (0x00000026U) +#define PKA_MODE_POINT_CHECK (0x00000028U) +#define PKA_MODE_RSA_CRT_EXP (0x00000007U) +#define PKA_MODE_MODULAR_INV (0x00000008U) +#define PKA_MODE_ARITHMETIC_ADD (0x00000009U) +#define PKA_MODE_ARITHMETIC_SUB (0x0000000AU) +#define PKA_MODE_ARITHMETIC_MUL (0x0000000BU) +#define PKA_MODE_COMPARISON (0x0000000CU) +#define PKA_MODE_MODULAR_RED (0x0000000DU) +#define PKA_MODE_MODULAR_ADD (0x0000000EU) +#define PKA_MODE_MODULAR_SUB (0x0000000FU) +#define PKA_MODE_MONTGOMERY_MUL (0x00000010U) +#define PKA_MODE_ECC_PROJECTIVE_AFF (0x0000002FU) +#define PKA_MODE_DOUBLE_BASE_LADDER (0x00000027U) +#define PKA_MODE_ECC_COMPLETE_ADD (0x00000023U) +#define PKA_MODE_MODULAR_EXP_PROTECT (0x00000003U) +/** + * @} + */ + +/** @defgroup PKA_Interrupt_configuration_definition PKA Interrupt configuration definition + * @brief PKA Interrupt definition + * @{ + */ +#define PKA_IT_PROCEND PKA_CR_PROCENDIE +#define PKA_IT_ADDRERR PKA_CR_ADDRERRIE +#define PKA_IT_RAMERR PKA_CR_RAMERRIE +#define PKA_IT_OPERR PKA_CR_OPERRIE + +/** + * @} + */ + +/** @defgroup PKA_Flag_definition PKA Flag definition + * @{ + */ +#define PKA_FLAG_PROCEND PKA_SR_PROCENDF +#define PKA_FLAG_ADDRERR PKA_SR_ADDRERRF +#define PKA_FLAG_RAMERR PKA_SR_RAMERRF +#define PKA_FLAG_OPERR PKA_SR_OPERRF + +/** + * @} + */ + +/** @defgroup PKA_Operation_Status PKA Operation Status + * @{ + */ +#define PKA_NO_ERROR 0xD60DUL +#define PKA_FAILED_COMPUTATION 0xCBC9UL +#define PKA_RPART_SIGNATURE_NULL 0xA3B7UL +#define PKA_SPART_SIGNATURE_NULL 0xF946UL + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ + +/** @defgroup PKA_Exported_Macros PKA Exported Macros + * @{ + */ + +/** @brief Reset PKA handle state. + * @param __HANDLE__ specifies the PKA Handle + * @retval None + */ +#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1) +#define __HAL_PKA_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_PKA_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_PKA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_PKA_STATE_RESET) +#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */ + +/** @brief Enable the specified PKA interrupt. + * @param __HANDLE__ specifies the PKA Handle + * @param __INTERRUPT__ specifies the interrupt source to enable. + * This parameter can be one of the following values: + * @arg @ref PKA_IT_PROCEND End Of Operation interrupt enable + * @arg @ref PKA_IT_ADDRERR Address error interrupt enable + * @arg @ref PKA_IT_RAMERR RAM error interrupt enable + * @arg @ref PKA_IT_OPERR Operation error interrupt enable + * @retval None + */ +#define __HAL_PKA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) + +/** @brief Disable the specified PKA interrupt. + * @param __HANDLE__ specifies the PKA Handle + * @param __INTERRUPT__ specifies the interrupt source to disable. + * This parameter can be one of the following values: + * @arg @ref PKA_IT_PROCEND End Of Operation interrupt enable + * @arg @ref PKA_IT_ADDRERR Address error interrupt enable + * @arg @ref PKA_IT_RAMERR RAM error interrupt enable + * @arg @ref PKA_IT_OPERR Operation error interrupt enable + * @retval None + */ +#define __HAL_PKA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= (~(__INTERRUPT__))) + +/** @brief Check whether the specified PKA interrupt source is enabled or not. + * @param __HANDLE__ specifies the PKA Handle + * @param __INTERRUPT__ specifies the PKA interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref PKA_IT_PROCEND End Of Operation interrupt enable + * @arg @ref PKA_IT_ADDRERR Address error interrupt enable + * @arg @ref PKA_IT_RAMERR RAM error interrupt enable + * @arg @ref PKA_IT_OPERR Operation error interrupt enable + * @retval The new state of __INTERRUPT__ (SET or RESET) + */ +#define __HAL_PKA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR\ + & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Check whether the specified PKA flag is set or not. + * @param __HANDLE__ specifies the PKA Handle + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref PKA_FLAG_PROCEND End Of Operation + * @arg @ref PKA_FLAG_ADDRERR Address error + * @arg @ref PKA_FLAG_RAMERR RAM error + * @arg @ref PKA_FLAG_OPERR Operation error + * @retval The new state of __FLAG__ (SET or RESET) + */ +#define __HAL_PKA_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->SR)\ + & (__FLAG__)) == (__FLAG__)) ? SET : RESET) + +/** @brief Clear the PKA pending flags which are cleared by writing 1 in a specific bit. + * @param __HANDLE__ specifies the PKA Handle + * @param __FLAG__ specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg @ref PKA_FLAG_PROCEND End Of Operation + * @arg @ref PKA_FLAG_ADDRERR Address error + * @arg @ref PKA_FLAG_RAMERR RAM error + * @arg @ref PKA_FLAG_OPERR Operation error + * @retval None + */ +#define __HAL_PKA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR = (__FLAG__)) + +/** @brief Enable the specified PKA peripheral. + * @param __HANDLE__ specifies the PKA Handle + * @retval None + */ +#define __HAL_PKA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR, PKA_CR_EN)) + +/** @brief Disable the specified PKA peripheral. + * @param __HANDLE__ specifies the PKA Handle + * @retval None + */ +#define __HAL_PKA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR, PKA_CR_EN)) + +/** @brief Start a PKA operation. + * @param __HANDLE__ specifies the PKA Handle + * @retval None + */ +#define __HAL_PKA_START(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR, PKA_CR_START)) +/** + * @} + */ + +/* Private macros --------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup PKA_Exported_Functions + * @{ + */ + +/** @addtogroup PKA_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +HAL_StatusTypeDef HAL_PKA_Init(PKA_HandleTypeDef *hpka); +HAL_StatusTypeDef HAL_PKA_DeInit(PKA_HandleTypeDef *hpka); +void HAL_PKA_MspInit(PKA_HandleTypeDef *hpka); +void HAL_PKA_MspDeInit(PKA_HandleTypeDef *hpka); + +#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1) +/* Callbacks Register/UnRegister functions ***********************************/ +HAL_StatusTypeDef HAL_PKA_RegisterCallback(PKA_HandleTypeDef *hpka, HAL_PKA_CallbackIDTypeDef CallbackID, + pPKA_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PKA_UnRegisterCallback(PKA_HandleTypeDef *hpka, HAL_PKA_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @addtogroup PKA_Exported_Functions_Group2 + * @{ + */ +/* IO operation functions *****************************************************/ +/* High Level Functions *******************************************************/ +HAL_StatusTypeDef HAL_PKA_ModExp(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef *in, uint32_t Timeout); +HAL_StatusTypeDef HAL_PKA_ModExp_IT(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef *in); +HAL_StatusTypeDef HAL_PKA_ModExpFastMode(PKA_HandleTypeDef *hpka, PKA_ModExpFastModeInTypeDef *in, uint32_t Timeout); +HAL_StatusTypeDef HAL_PKA_ModExpFastMode_IT(PKA_HandleTypeDef *hpka, PKA_ModExpFastModeInTypeDef *in); +HAL_StatusTypeDef HAL_PKA_ModExpProtectMode(PKA_HandleTypeDef *hpka, PKA_ModExpProtectModeInTypeDef *in, + uint32_t Timeout); +HAL_StatusTypeDef HAL_PKA_ModExpProtectMode_IT(PKA_HandleTypeDef *hpka, PKA_ModExpProtectModeInTypeDef *in); +void HAL_PKA_ModExp_GetResult(PKA_HandleTypeDef *hpka, uint8_t *pRes); + +HAL_StatusTypeDef HAL_PKA_ECDSASign(PKA_HandleTypeDef *hpka, PKA_ECDSASignInTypeDef *in, uint32_t Timeout); +HAL_StatusTypeDef HAL_PKA_ECDSASign_IT(PKA_HandleTypeDef *hpka, PKA_ECDSASignInTypeDef *in); +void HAL_PKA_ECDSASign_GetResult(PKA_HandleTypeDef *hpka, PKA_ECDSASignOutTypeDef *out, + PKA_ECDSASignOutExtParamTypeDef *outExt); + +HAL_StatusTypeDef HAL_PKA_ECDSAVerif(PKA_HandleTypeDef *hpka, PKA_ECDSAVerifInTypeDef *in, uint32_t Timeout); +HAL_StatusTypeDef HAL_PKA_ECDSAVerif_IT(PKA_HandleTypeDef *hpka, PKA_ECDSAVerifInTypeDef *in); +uint32_t HAL_PKA_ECDSAVerif_IsValidSignature(PKA_HandleTypeDef const *const hpka); + +HAL_StatusTypeDef HAL_PKA_RSACRTExp(PKA_HandleTypeDef *hpka, PKA_RSACRTExpInTypeDef *in, uint32_t Timeout); +HAL_StatusTypeDef HAL_PKA_RSACRTExp_IT(PKA_HandleTypeDef *hpka, PKA_RSACRTExpInTypeDef *in); +void HAL_PKA_RSACRTExp_GetResult(PKA_HandleTypeDef *hpka, uint8_t *pRes); + +HAL_StatusTypeDef HAL_PKA_PointCheck(PKA_HandleTypeDef *hpka, PKA_PointCheckInTypeDef *in, uint32_t Timeout); +HAL_StatusTypeDef HAL_PKA_PointCheck_IT(PKA_HandleTypeDef *hpka, PKA_PointCheckInTypeDef *in); +uint32_t HAL_PKA_PointCheck_IsOnCurve(PKA_HandleTypeDef const *const hpka); + +HAL_StatusTypeDef HAL_PKA_ECCMul(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in, uint32_t Timeout); +HAL_StatusTypeDef HAL_PKA_ECCMul_IT(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in); +HAL_StatusTypeDef HAL_PKA_ECCMulEx(PKA_HandleTypeDef *hpka, PKA_ECCMulExInTypeDef *in, uint32_t Timeout); +HAL_StatusTypeDef HAL_PKA_ECCMulEx_IT(PKA_HandleTypeDef *hpka, PKA_ECCMulExInTypeDef *in); +void HAL_PKA_ECCMul_GetResult(PKA_HandleTypeDef *hpka, PKA_ECCMulOutTypeDef *out); + +HAL_StatusTypeDef HAL_PKA_Add(PKA_HandleTypeDef *hpka, PKA_AddInTypeDef *in, uint32_t Timeout); +HAL_StatusTypeDef HAL_PKA_Add_IT(PKA_HandleTypeDef *hpka, PKA_AddInTypeDef *in); +HAL_StatusTypeDef HAL_PKA_Sub(PKA_HandleTypeDef *hpka, PKA_SubInTypeDef *in, uint32_t Timeout); +HAL_StatusTypeDef HAL_PKA_Sub_IT(PKA_HandleTypeDef *hpka, PKA_SubInTypeDef *in); +HAL_StatusTypeDef HAL_PKA_Cmp(PKA_HandleTypeDef *hpka, PKA_CmpInTypeDef *in, uint32_t Timeout); +HAL_StatusTypeDef HAL_PKA_Cmp_IT(PKA_HandleTypeDef *hpka, PKA_CmpInTypeDef *in); +HAL_StatusTypeDef HAL_PKA_Mul(PKA_HandleTypeDef *hpka, PKA_MulInTypeDef *in, uint32_t Timeout); +HAL_StatusTypeDef HAL_PKA_Mul_IT(PKA_HandleTypeDef *hpka, PKA_MulInTypeDef *in); +HAL_StatusTypeDef HAL_PKA_ModAdd(PKA_HandleTypeDef *hpka, PKA_ModAddInTypeDef *in, uint32_t Timeout); +HAL_StatusTypeDef HAL_PKA_ModAdd_IT(PKA_HandleTypeDef *hpka, PKA_ModAddInTypeDef *in); +HAL_StatusTypeDef HAL_PKA_ModSub(PKA_HandleTypeDef *hpka, PKA_ModSubInTypeDef *in, uint32_t Timeout); +HAL_StatusTypeDef HAL_PKA_ModSub_IT(PKA_HandleTypeDef *hpka, PKA_ModSubInTypeDef *in); +HAL_StatusTypeDef HAL_PKA_ModInv(PKA_HandleTypeDef *hpka, PKA_ModInvInTypeDef *in, uint32_t Timeout); +HAL_StatusTypeDef HAL_PKA_ModInv_IT(PKA_HandleTypeDef *hpka, PKA_ModInvInTypeDef *in); +HAL_StatusTypeDef HAL_PKA_ModRed(PKA_HandleTypeDef *hpka, PKA_ModRedInTypeDef *in, uint32_t Timeout); +HAL_StatusTypeDef HAL_PKA_ModRed_IT(PKA_HandleTypeDef *hpka, PKA_ModRedInTypeDef *in); +HAL_StatusTypeDef HAL_PKA_MontgomeryMul(PKA_HandleTypeDef *hpka, PKA_MontgomeryMulInTypeDef *in, uint32_t Timeout); +HAL_StatusTypeDef HAL_PKA_MontgomeryMul_IT(PKA_HandleTypeDef *hpka, PKA_MontgomeryMulInTypeDef *in); +void HAL_PKA_Arithmetic_GetResult(PKA_HandleTypeDef *hpka, uint32_t *pRes); + +HAL_StatusTypeDef HAL_PKA_MontgomeryParam(PKA_HandleTypeDef *hpka, PKA_MontgomeryParamInTypeDef *in, uint32_t Timeout); +HAL_StatusTypeDef HAL_PKA_MontgomeryParam_IT(PKA_HandleTypeDef *hpka, PKA_MontgomeryParamInTypeDef *in); +void HAL_PKA_MontgomeryParam_GetResult(PKA_HandleTypeDef *hpka, uint32_t *pRes); + +HAL_StatusTypeDef HAL_PKA_ECCDoubleBaseLadder(PKA_HandleTypeDef *hpka, PKA_ECCDoubleBaseLadderInTypeDef *in, + uint32_t Timeout); +HAL_StatusTypeDef HAL_PKA_ECCDoubleBaseLadder_IT(PKA_HandleTypeDef *hpka, PKA_ECCDoubleBaseLadderInTypeDef *in); +void HAL_PKA_ECCDoubleBaseLadder_GetResult(PKA_HandleTypeDef *hpka, PKA_ECCDoubleBaseLadderOutTypeDef *out); + +HAL_StatusTypeDef HAL_PKA_ECCProjective2Affine(PKA_HandleTypeDef *hpka, PKA_ECCProjective2AffineInTypeDef *in, + uint32_t Timeout); +HAL_StatusTypeDef HAL_PKA_ECCProjective2Affine_IT(PKA_HandleTypeDef *hpka, PKA_ECCProjective2AffineInTypeDef *in); +void HAL_PKA_ECCProjective2Affine_GetResult(PKA_HandleTypeDef *hpka, PKA_ECCProjective2AffineOutTypeDef *out); + +HAL_StatusTypeDef HAL_PKA_ECCCompleteAddition(PKA_HandleTypeDef *hpka, PKA_ECCCompleteAdditionInTypeDef *in, + uint32_t Timeout); +HAL_StatusTypeDef HAL_PKA_ECCCompleteAddition_IT(PKA_HandleTypeDef *hpka, PKA_ECCCompleteAdditionInTypeDef *in); +void HAL_PKA_ECCCompleteAddition_GetResult(PKA_HandleTypeDef *hpka, PKA_ECCCompleteAdditionOutTypeDef *out); + +HAL_StatusTypeDef HAL_PKA_Abort(PKA_HandleTypeDef *hpka); +void HAL_PKA_RAMReset(PKA_HandleTypeDef *hpka); +void HAL_PKA_OperationCpltCallback(PKA_HandleTypeDef *hpka); +void HAL_PKA_ErrorCallback(PKA_HandleTypeDef *hpka); +void HAL_PKA_IRQHandler(PKA_HandleTypeDef *hpka); +/** + * @} + */ + +/** @addtogroup PKA_Exported_Functions_Group3 + * @{ + */ +/* Peripheral State and Error functions ***************************************/ +HAL_PKA_StateTypeDef HAL_PKA_GetState(const PKA_HandleTypeDef *hpka); +uint32_t HAL_PKA_GetError(const PKA_HandleTypeDef *hpka); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(PKA) && defined(HAL_PKA_MODULE_ENABLED) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WBAxx_HAL_PKA_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_pwr.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_pwr.h new file mode 100644 index 0000000000..71785bda28 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_pwr.h @@ -0,0 +1,931 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_pwr.h + * @author MCD Application Team + * @brief Header file of PWR HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_HAL_PWR_H +#define STM32WBAxx_HAL_PWR_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal_def.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @addtogroup PWR + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup PWR_Exported_Types PWR Exported Types + * @{ + */ + +/** + * @brief PWR PVD configuration structure definition + */ +typedef struct +{ + uint32_t PVDLevel; /*!< Specifies the PVD detection level. + This parameter can be a value of + @ref PWR_PVD_Detection_Level. */ + + uint32_t Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref PWR_PVD_Mode. */ +} PWR_PVDTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup PWR_Exported_Constants PWR Exported Constants + * @{ + */ + +/** @defgroup PWR_PVD_Detection_Level Programmable Voltage Detection Level + * @{ + */ +#define PWR_PVDLEVEL_0 0x00000000UL /*!< PVD threshold around 2.0 V */ +#define PWR_PVDLEVEL_1 (PWR_SVMCR_PVDLS_0) /*!< PVD threshold around 2.2 V */ +#define PWR_PVDLEVEL_2 (PWR_SVMCR_PVDLS_1) /*!< PVD threshold around 2.4 V */ +#define PWR_PVDLEVEL_3 (PWR_SVMCR_PVDLS_0 | PWR_SVMCR_PVDLS_1) /*!< PVD threshold around 2.5 V */ +#define PWR_PVDLEVEL_4 (PWR_SVMCR_PVDLS_2) /*!< PVD threshold around 2.6 V */ +#define PWR_PVDLEVEL_5 (PWR_SVMCR_PVDLS_0 | PWR_SVMCR_PVDLS_2) /*!< PVD threshold around 2.8 V */ +#define PWR_PVDLEVEL_6 (PWR_SVMCR_PVDLS_1 | PWR_SVMCR_PVDLS_2) /*!< PVD threshold around 2.9 V */ +#define PWR_PVDLEVEL_7 (PWR_SVMCR_PVDLS) /*!< External input analog voltage + (compared internally to VREFINT) */ +/** + * @} + */ + +/** @defgroup PWR_PVD_Mode PWR PVD Mode + * @{ + */ +#define PWR_PVD_MODE_NORMAL (0x00U) /*!< Basic Mode is used */ +#define PWR_PVD_MODE_IT_RISING (0x05U) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define PWR_PVD_MODE_IT_FALLING (0x06U) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define PWR_PVD_MODE_IT_RISING_FALLING (0x07U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING (0x09U) /*!< Event Mode with Rising edge trigger detection */ +#define PWR_PVD_MODE_EVENT_FALLING (0x0AU) /*!< Event Mode with Falling edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING_FALLING (0x0BU) /*!< Event Mode with Rising/Falling edge trigger detection */ +/** + * @} + */ + +/** @defgroup PWR_Regulator_In_LowPower_Mode PWR Regulator State in Sleep/Stop Mode + * @{ + */ +#define PWR_MAINREGULATOR_ON (0x00U) /*!< Main Regulator ON in Run Mode */ +#define PWR_LOWPOWERREGULATOR_ON (PWR_CR1_LPMS_0) /*!< Main Regulator ON in Low Power Mode */ +/** + * @} + */ + +/** @defgroup PWR_Low_Power_Mode_Selection PWR Low Power Mode Selection + * @{ + */ +#define PWR_LOWPOWERMODE_STOP0 (0x00000000u) /*!< Stop 0: stop mode with main regulator */ +#define PWR_LOWPOWERMODE_STOP1 (PWR_CR1_LPMS_0) /*!< Stop 1: stop mode with low power regulator */ +#define PWR_LOWPOWERMODE_STANDBY (PWR_CR1_LPMS_2) /*!< Standby mode */ +/** + * @} + */ + +/** @defgroup PWR_Sleep_Mode_Entry PWR Sleep Mode Entry + * @{ + */ +#define PWR_SLEEPENTRY_WFI (0x01U) /*!< Wait For Interruption instruction to enter Sleep mode */ +#define PWR_SLEEPENTRY_WFE (0x02U) /*!< Wait For Event instruction to enter Sleep mode */ +/** + * @} + */ + +/** @defgroup PWR_Stop_Mode_Entry PWR Stop Mode Entry + * @{ + */ +#define PWR_STOPENTRY_WFI (0x01U) /*!< Wait For Interruption instruction to enter Stop mode */ +#define PWR_STOPENTRY_WFE (0x02U) /*!< Wait For Event instruction to enter Stop mode */ +/** + * @} + */ + +/** @defgroup PWR_Flags PWR Flags + * @{ + */ +#define PWR_FLAG_VOSRDY (1U) /*!< Voltage scaling ready flag */ +#define PWR_FLAG_STOPF (2U) /*!< Stop flag */ +#define PWR_FLAG_SBF (3U) /*!< Standby flag */ +#define PWR_FLAG_ACTVOSRDY (4U) /*!< Currently applied VOS ready flag */ +#define PWR_FLAG_PVDO (5U) /*!< VDD voltage detector output flag */ +#if defined(PWR_SVMSR_REGS) +#define PWR_FLAG_REGS (6U) /*!< Regulator selection flag */ +#endif /* defined(PWR_SVMSR_REGS) */ +#define PWR_FLAG_REGPARDYVDDRFPA (7U) /*!< Ready bit for VDDHPA voltage level when selecting VDDRFPA input */ +#if defined(PWR_RADIOSCR_REGPARDYV11) +#define PWR_FLAG_REGPARDYV11 (8U) /*!< Ready bit for VDDHPA voltage level when selecting VDD11 input */ +#endif /* defined(PWR_RADIOSCR_REGPARDYV11) */ +/** + * @} + */ + +/** @defgroup PWR_WakeUp_Lines_Flags PWR Wakeup Lines Flags + * @{ + */ +#define PWR_WAKEUP_FLAG1 (0x10U) /*!< Wakeup flag 1 */ +#if defined(PWR_WUCR1_WUPEN2) +#define PWR_WAKEUP_FLAG2 (0x20U) /*!< Wakeup flag 2 */ +#endif /* defined(PWR_WUCR1_WUPEN2) */ +#define PWR_WAKEUP_FLAG3 (0x30U) /*!< Wakeup flag 3 */ +#define PWR_WAKEUP_FLAG4 (0x40U) /*!< Wakeup flag 4 */ +#if defined(PWR_WUCR1_WUPEN5) +#define PWR_WAKEUP_FLAG5 (0x50U) /*!< Wakeup flag 5 */ +#endif /* defined(PWR_WUCR1_WUPEN5) */ +#define PWR_WAKEUP_FLAG6 (0x60U) /*!< Wakeup flag 6 */ +#define PWR_WAKEUP_FLAG7 (0x70U) /*!< Wakeup flag 7 */ +#define PWR_WAKEUP_FLAG8 (0x80U) /*!< Wakeup flag 8 */ +#define PWR_WAKEUP_ALL_FLAG (0x90U) /*!< Wakeup flag all */ +/** + * @} + */ + +/** @defgroup PWR_WakeUp_Pin_High_Polarity PWR Wake Up Pins High Polarity + * @{ + */ +#define PWR_WAKEUP_PIN1_HIGH_0 (PWR_WUCR1_WUPEN1 | PWR_WAKEUP1_SOURCE_SELECTION_0) /*!< PA0 : Wakeup pin 1 (high polarity) */ +#if defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) +#define PWR_WAKEUP_PIN1_HIGH_1 (PWR_WUCR1_WUPEN1 | PWR_WAKEUP1_SOURCE_SELECTION_1) /*!< PB2 : Wakeup pin 1 (high polarity) */ +#endif /* defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) */ + +#if defined(PWR_WUCR1_WUPEN2) +#define PWR_WAKEUP_PIN2_HIGH_0 (PWR_WUCR1_WUPEN2 | PWR_WAKEUP2_SOURCE_SELECTION_0) /*!< PA4 : Wakeup pin 2 (high polarity) */ +#define PWR_WAKEUP_PIN2_HIGH_1 (PWR_WUCR1_WUPEN2 | PWR_WAKEUP2_SOURCE_SELECTION_1) /*!< PC13 : Wakeup pin 2 (high polarity) */ +#endif /* defined(PWR_WUCR1_WUPEN2) */ + +#define PWR_WAKEUP_PIN3_HIGH_1 (PWR_WUCR1_WUPEN3 | PWR_WAKEUP3_SOURCE_SELECTION_1) /*!< PA1 : Wakeup pin 3 (high polarity) */ +#if defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) +#define PWR_WAKEUP_PIN3_HIGH_2 (PWR_WUCR1_WUPEN3 | PWR_WAKEUP3_SOURCE_SELECTION_2) /*!< PB6 : Wakeup pin 3 (high polarity) */ +#endif /* defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) */ + +#define PWR_WAKEUP_PIN4_HIGH_0 (PWR_WUCR1_WUPEN4 | PWR_WAKEUP4_SOURCE_SELECTION_0) /*!< PA2 : Wakeup pin 4 (high polarity) */ +#if defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) +#define PWR_WAKEUP_PIN4_HIGH_1 (PWR_WUCR1_WUPEN4 | PWR_WAKEUP4_SOURCE_SELECTION_1) /*!< PB1 : Wakeup pin 4 (high polarity) */ +#endif /* defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) */ + +#if defined(PWR_WUCR1_WUPEN5) +#define PWR_WAKEUP_PIN5_HIGH_1 (PWR_WUCR1_WUPEN5 | PWR_WAKEUP5_SOURCE_SELECTION_1) /*!< PA3 : Wakeup pin 5 (high polarity) */ +#define PWR_WAKEUP_PIN5_HIGH_2 (PWR_WUCR1_WUPEN5 | PWR_WAKEUP5_SOURCE_SELECTION_2) /*!< PB7 : Wakeup pin 5 (high polarity) */ +#endif /* defined(PWR_WUCR1_WUPEN5) */ + +#define PWR_WAKEUP_PIN6_HIGH_0 (PWR_WUCR1_WUPEN6 | PWR_WAKEUP6_SOURCE_SELECTION_0) /*!< PA12 : Wakeup pin 6 (high polarity) */ +#define PWR_WAKEUP_PIN6_HIGH_1 (PWR_WUCR1_WUPEN6 | PWR_WAKEUP6_SOURCE_SELECTION_1) /*!< PA5 : Wakeup pin 6 (high polarity) */ +#define PWR_WAKEUP_PIN6_HIGH_3 (PWR_WUCR1_WUPEN6 | PWR_WAKEUP6_SOURCE_SELECTION_3) /*!< RTC : Wakeup pin 6 (high polarity) */ + +#if defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) +#define PWR_WAKEUP_PIN7_HIGH_0 (PWR_WUCR1_WUPEN7 | PWR_WAKEUP7_SOURCE_SELECTION_0) /*!< PB14 : Wakeup pin 7 (high polarity) */ +#endif /* defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) */ +#define PWR_WAKEUP_PIN7_HIGH_1 (PWR_WUCR1_WUPEN7 | PWR_WAKEUP7_SOURCE_SELECTION_1) /*!< PA6 : Wakeup pin 7 (high polarity) */ +#define PWR_WAKEUP_PIN7_HIGH_3 (PWR_WUCR1_WUPEN7 | PWR_WAKEUP7_SOURCE_SELECTION_3) /*!< RTC : Wakeup pin 7 (high polarity) */ + +#define PWR_WAKEUP_PIN8_HIGH_1 (PWR_WUCR1_WUPEN8 | PWR_WAKEUP8_SOURCE_SELECTION_1) /*!< PA7 : Wakeup pin 8 (high polarity) */ +#define PWR_WAKEUP_PIN8_HIGH_2 (PWR_WUCR1_WUPEN8 | PWR_WAKEUP8_SOURCE_SELECTION_2) /*!< PB9 : Wakeup pin 8 (high polarity) */ +#define PWR_WAKEUP_PIN8_HIGH_3 (PWR_WUCR1_WUPEN8 | PWR_WAKEUP8_SOURCE_SELECTION_3) /*!< TAMP : Wakeup pin 8 (high polarity) */ +/** + * @} + */ + +/** @defgroup PWR_WakeUp_Pin_Low_Polarity PWR Wake Up Pins Low Polarity + * @{ + */ +#define PWR_WAKEUP_PIN1_LOW_0 (PWR_WUCR1_WUPEN1 | PWR_WAKEUP1_POLARITY_LOW | PWR_WAKEUP1_SOURCE_SELECTION_0) /*!< PA0 : Wakeup pin 1 (low polarity) */ +#if defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) +#define PWR_WAKEUP_PIN1_LOW_1 (PWR_WUCR1_WUPEN1 | PWR_WAKEUP1_POLARITY_LOW | PWR_WAKEUP1_SOURCE_SELECTION_1) /*!< PB2 : Wakeup pin 1 (low polarity) */ +#endif /* defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) */ + +#if defined(PWR_WUCR1_WUPEN2) +#define PWR_WAKEUP_PIN2_LOW_0 (PWR_WUCR1_WUPEN2 | PWR_WAKEUP2_POLARITY_LOW | PWR_WAKEUP2_SOURCE_SELECTION_0) /*!< PA4 : Wakeup pin 2 (low polarity) */ +#define PWR_WAKEUP_PIN2_LOW_1 (PWR_WUCR1_WUPEN2 | PWR_WAKEUP2_POLARITY_LOW | PWR_WAKEUP2_SOURCE_SELECTION_1) /*!< PC13 : Wakeup pin 2 (low polarity) */ +#endif /* defined(PWR_WUCR1_WUPEN2) */ + +#define PWR_WAKEUP_PIN3_LOW_1 (PWR_WUCR1_WUPEN3 | PWR_WAKEUP3_POLARITY_LOW | PWR_WAKEUP3_SOURCE_SELECTION_1) /*!< PA1 : Wakeup pin 3 (low polarity) */ +#if defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) +#define PWR_WAKEUP_PIN3_LOW_2 (PWR_WUCR1_WUPEN3 | PWR_WAKEUP3_POLARITY_LOW | PWR_WAKEUP3_SOURCE_SELECTION_2) /*!< PB6 : Wakeup pin 3 (low polarity) */ +#endif /* defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) */ + +#define PWR_WAKEUP_PIN4_LOW_0 (PWR_WUCR1_WUPEN4 | PWR_WAKEUP4_POLARITY_LOW | PWR_WAKEUP4_SOURCE_SELECTION_0) /*!< PA2 : Wakeup pin 4 (low polarity) */ +#if defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) +#define PWR_WAKEUP_PIN4_LOW_1 (PWR_WUCR1_WUPEN4 | PWR_WAKEUP4_POLARITY_LOW | PWR_WAKEUP4_SOURCE_SELECTION_1) /*!< PB1 : Wakeup pin 4 (low polarity) */ +#endif /* defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) */ + +#if defined(PWR_WUCR1_WUPEN5) +#define PWR_WAKEUP_PIN5_LOW_1 (PWR_WUCR1_WUPEN5 | PWR_WAKEUP5_POLARITY_LOW | PWR_WAKEUP5_SOURCE_SELECTION_1) /*!< PA3 : Wakeup pin 5 (low polarity) */ +#define PWR_WAKEUP_PIN5_LOW_2 (PWR_WUCR1_WUPEN5 | PWR_WAKEUP5_POLARITY_LOW | PWR_WAKEUP5_SOURCE_SELECTION_2) /*!< PB7 : Wakeup pin 5 (low polarity) */ +#endif /* defined(PWR_WUCR1_WUPEN5) */ + +#define PWR_WAKEUP_PIN6_LOW_0 (PWR_WUCR1_WUPEN6 | PWR_WAKEUP6_POLARITY_LOW | PWR_WAKEUP6_SOURCE_SELECTION_0) /*!< PA12 : Wakeup pin 6 (low polarity) */ +#define PWR_WAKEUP_PIN6_LOW_1 (PWR_WUCR1_WUPEN6 | PWR_WAKEUP6_POLARITY_LOW | PWR_WAKEUP6_SOURCE_SELECTION_1) /*!< PA5 : Wakeup pin 6 (low polarity) */ +#define PWR_WAKEUP_PIN6_LOW_3 (PWR_WUCR1_WUPEN6 | PWR_WAKEUP6_POLARITY_LOW | PWR_WAKEUP6_SOURCE_SELECTION_3) /*!< RTC : Wakeup pin 6 (low polarity) */ + +#if defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) +#define PWR_WAKEUP_PIN7_LOW_0 (PWR_WUCR1_WUPEN7 | PWR_WAKEUP7_POLARITY_LOW | PWR_WAKEUP7_SOURCE_SELECTION_0) /*!< PB14 : Wakeup pin 7 (low polarity) */ +#endif /* defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) */ +#define PWR_WAKEUP_PIN7_LOW_1 (PWR_WUCR1_WUPEN7 | PWR_WAKEUP7_POLARITY_LOW | PWR_WAKEUP7_SOURCE_SELECTION_1) /*!< PA6 : Wakeup pin 7 (low polarity) */ +#define PWR_WAKEUP_PIN7_LOW_3 (PWR_WUCR1_WUPEN7 | PWR_WAKEUP7_POLARITY_LOW | PWR_WAKEUP7_SOURCE_SELECTION_3) /*!< RTC : Wakeup pin 7 (low polarity) */ + +#define PWR_WAKEUP_PIN8_LOW_1 (PWR_WUCR1_WUPEN8 | PWR_WAKEUP8_POLARITY_LOW | PWR_WAKEUP8_SOURCE_SELECTION_1) /*!< PA7 : Wakeup pin 8 (low polarity) */ +#define PWR_WAKEUP_PIN8_LOW_2 (PWR_WUCR1_WUPEN8 | PWR_WAKEUP8_POLARITY_LOW | PWR_WAKEUP8_SOURCE_SELECTION_2) /*!< PB9 : Wakeup pin 8 (low polarity) */ +#define PWR_WAKEUP_PIN8_LOW_3 (PWR_WUCR1_WUPEN8 | PWR_WAKEUP8_POLARITY_LOW | PWR_WAKEUP8_SOURCE_SELECTION_3) /*!< TAMP : Wakeup pin 8 (low polarity) */ +/** + * @} + */ + +/** @defgroup PWR_WakeUp_Pins PWR Wake Up Pins (Default polarity and default pin selection) + * @{ + */ +#define PWR_WAKEUP_PIN1 (PWR_WUCR1_WUPEN1) /*!< PA0 : Wakeup pin 1 (high polarity) */ +#if defined(PWR_WUCR1_WUPEN2) +#define PWR_WAKEUP_PIN2 (PWR_WUCR1_WUPEN2) /*!< PA4 : Wakeup pin 2 (high polarity) */ +#endif /* defined(PWR_WUCR1_WUPEN2) */ +#define PWR_WAKEUP_PIN3 (PWR_WUCR1_WUPEN3) /*!< reserved */ +#define PWR_WAKEUP_PIN4 (PWR_WUCR1_WUPEN4) /*!< PA2 : Wakeup pin 4 (high polarity) */ +#if defined(PWR_WUCR1_WUPEN5) +#define PWR_WAKEUP_PIN5 (PWR_WUCR1_WUPEN5) /*!< reserved */ +#endif /* defined(PWR_WUCR1_WUPEN5) */ +#define PWR_WAKEUP_PIN6 (PWR_WUCR1_WUPEN6) /*!< PA12 : Wakeup pin 6 (high polarity) */ +#define PWR_WAKEUP_PIN7 (PWR_WUCR1_WUPEN7) /*!< PB14 : Wakeup pin 7 (high polarity) */ +#define PWR_WAKEUP_PIN8 (PWR_WUCR1_WUPEN8) /*!< reserved */ +/** + * @} + */ + +/** @defgroup PWR_Items PWR Items + * @{ + */ +#define PWR_WKUP1 (PWR_SECCFGR_WUP1SEC) /*!< WUP1 secure protection */ +#if defined(PWR_WUCR1_WUPEN2) +#define PWR_WKUP2 (PWR_SECCFGR_WUP2SEC) /*!< WUP2 secure protection */ +#endif /* defined(PWR_WUCR1_WUPEN2) */ +#define PWR_WKUP3 (PWR_SECCFGR_WUP3SEC) /*!< WUP3 secure protection */ +#define PWR_WKUP4 (PWR_SECCFGR_WUP4SEC) /*!< WUP4 secure protection */ +#if defined(PWR_WUCR1_WUPEN5) +#define PWR_WKUP5 (PWR_SECCFGR_WUP5SEC) /*!< WUP5 secure protection */ +#endif /* defined(PWR_WUCR1_WUPEN5) */ +#define PWR_WKUP6 (PWR_SECCFGR_WUP6SEC) /*!< WUP6 secure protection */ +#define PWR_WKUP7 (PWR_SECCFGR_WUP7SEC) /*!< WUP7 secure protection */ +#define PWR_WKUP8 (PWR_SECCFGR_WUP8SEC) /*!< WUP8 secure protection */ +#define PWR_LPM (PWR_SECCFGR_LPMSEC) /*!< Low power modes secure protection */ +#define PWR_VDM (PWR_SECCFGR_VDMSEC) /*!< Voltage detection and monitoring secure protection */ +#define PWR_VB (PWR_SECCFGR_VBSEC) /*!< Backup domain secure protection */ +#if defined(PWR_WUCR1_WUPEN2) && defined(PWR_WUCR1_WUPEN5) +#define PWR_ALL (PWR_WKUP1 | PWR_WKUP2 | PWR_WKUP3 | PWR_WKUP4 | \ + PWR_WKUP5 | PWR_WKUP7 | PWR_WKUP6 | PWR_WKUP8 | \ + PWR_LPM | PWR_VDM | PWR_VB) +#else +#define PWR_ALL (PWR_WKUP1 | PWR_WKUP3 | PWR_WKUP4 | \ + PWR_WKUP7 | PWR_WKUP6 | PWR_WKUP8 | \ + PWR_LPM | PWR_VDM | PWR_VB) +#endif /* defined(PWR_WUCR1_WUPEN2) && defined(PWR_WUCR1_WUPEN5) */ +/** + * @} + */ + +#if defined(PWR_PRIVCFGR_SPRIV) +/** @defgroup PWR_Attributes PWR Attributes + * @brief PWR Privilege/NPrivilege and Secure/NSecure Attributes + * @{ + */ +#define PWR_NSEC_PRIV (PWR_ITEM_ATTR_NSEC_PRIV_MASK | 0x01U) /*!< NSecure and Privileged attribute */ +#define PWR_NSEC_NPRIV (PWR_ITEM_ATTR_NSEC_PRIV_MASK) /*!< NSecure and NPrivileged attribute */ +#define PWR_SEC_PRIV (PWR_ITEM_ATTR_SEC_PRIV_MASK | 0x02U) /*!< Secure and Privileged attribute */ +#define PWR_SEC_NPRIV (PWR_ITEM_ATTR_SEC_PRIV_MASK) /*!< Secure and NPrivileged attribute */ +/** + * @} + */ +#endif /* defined(PWR_PRIVCFGR_SPRIV) */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ + +/** @defgroup PWR_Exported_Macros PWR Exported Macros + * @{ + */ + +/** @brief Check PWR flags are set or not. + * @param __FLAG__ : Specifies the flag to check. + * This parameter can be one of the following values when available : + * @arg @ref PWR_FLAG_VOSRDY : Voltage scaling ready flag. + * Indicates that the Vcore level at or above VOS selected level. + * @arg @ref PWR_FLAG_STOPF : Stop flag. + * Indicates that the device was resumed from Stop mode. + * @arg @ref PWR_FLAG_SBF : Standby flag. + * Indicates that the device was resumed from Standby mode. + * @arg @ref PWR_FLAG_ACTVOSRDY : Currently applied VOS ready flag. + * Indicates that Vcore is equal to the current + * voltage scaling provided by ACTVOS. + * @arg @ref PWR_FLAG_PVDO VDD : Voltage detector output flag. + * Indicates that Vdd is equal or above + * the PVD threshold selected by PVDLS. + * @arg @ref PWR_FLAG_REGS : Regulator selection flag. + * Indicates the regulator selected.(*) + * @arg @ref PWR_FLAG_REGPARDYVDDRFPA : Ready bit for VDDHPA voltage level when selecting VDDRFPA + * input. + * Indicates VDDHPA voltage level is ready. + * @arg @ref PWR_FLAG_REGPARDYV11 : Ready bit for VDDHPA voltage level when selecting VDD11 + * input. + * Indicates VDDHPA voltage level is ready.(*) + * @arg @ref PWR_WAKEUP_FLAG1 : Wakeup flag 1. + * Indicates that a wakeup event was received from the WKUP line 1. + * @arg @ref PWR_WAKEUP_FLAG2 : Wakeup flag 2. + * Indicates that a wakeup event was received from the WKUP line 2. + * @arg @ref PWR_WAKEUP_FLAG3 : Wakeup flag 3. + * Indicates that a wakeup event was received from the WKUP line 3. + * @arg @ref PWR_WAKEUP_FLAG4 : Wakeup flag 4. + * Indicates that a wakeup event was received from the WKUP line 4. + * @arg @ref PWR_WAKEUP_FLAG5 : Wakeup flag 5. + * Indicates that a wakeup event was received from the WKUP line 5. + * @arg @ref PWR_WAKEUP_FLAG6 : Wakeup flag 6. + * Indicates that a wakeup event was received from the WKUP line 6. + * @arg @ref PWR_WAKEUP_FLAG7 : Wakeup flag 7. + * Indicates that a wakeup event was received from the WKUP line 7. + * @arg @ref PWR_WAKEUP_FLAG8 : Wakeup flag 8. + * Indicates that a wakeup event was received from the WKUP line 8. + * (*) Feature not available on all devices of the family + * @retval The state of __FLAG__ (TRUE or FALSE). + */ +#if defined(PWR_FLAG_REGPARDYV11) +#if defined(PWR_FLAG_REGS) +#define __HAL_PWR_GET_FLAG(__FLAG__)( \ + ((__FLAG__) == PWR_FLAG_VOSRDY) ? (READ_BIT(PWR->VOSR, PWR_VOSR_VOSRDY)== \ + PWR_VOSR_VOSRDY) : \ + ((__FLAG__) == PWR_FLAG_STOPF) ? (READ_BIT(PWR->SR, PWR_SR_STOPF)== \ + PWR_SR_STOPF) : \ + ((__FLAG__) == PWR_FLAG_SBF) ? (READ_BIT(PWR->SR, PWR_SR_SBF)== \ + PWR_SR_SBF) : \ + ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ?(READ_BIT(PWR->SVMSR, PWR_SVMSR_ACTVOSRDY)== \ + PWR_SVMSR_ACTVOSRDY): \ + ((__FLAG__) == PWR_FLAG_PVDO) ?(READ_BIT(PWR->SVMSR, PWR_SVMSR_PVDO)== \ + PWR_SVMSR_PVDO) : \ + ((__FLAG__) == PWR_FLAG_REGS) ?(READ_BIT(PWR->SVMSR, PWR_SVMSR_REGS)== \ + PWR_SVMSR_REGS) : \ + ((__FLAG__) == PWR_FLAG_REGPARDYVDDRFPA) ?(READ_BIT(PWR->RADIOSCR, PWR_RADIOSCR_REGPARDYVDDRFPA)== \ + PWR_RADIOSCR_REGPARDYVDDRFPA) : \ + ((__FLAG__) == PWR_FLAG_REGPARDYV11) ?(READ_BIT(PWR->RADIOSCR, PWR_RADIOSCR_REGPARDYV11)== \ + PWR_RADIOSCR_REGPARDYV11) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG1) ?(READ_BIT(PWR->WUSR, PWR_WUSR_WUF1) == \ + PWR_WUSR_WUF1) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG2) ?(READ_BIT(PWR->WUSR, PWR_WUSR_WUF2) == \ + PWR_WUSR_WUF2) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG3) ?(READ_BIT(PWR->WUSR, PWR_WUSR_WUF3) == \ + PWR_WUSR_WUF3) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG4) ?(READ_BIT(PWR->WUSR, PWR_WUSR_WUF4) == \ + PWR_WUSR_WUF4) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG5) ?(READ_BIT(PWR->WUSR, PWR_WUSR_WUF5) == \ + PWR_WUSR_WUF5) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG6) ?(READ_BIT(PWR->WUSR, PWR_WUSR_WUF6) == \ + PWR_WUSR_WUF6) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG7) ?(READ_BIT(PWR->WUSR, PWR_WUSR_WUF7) == \ + PWR_WUSR_WUF7) : \ + (READ_BIT(PWR->WUSR, PWR_WUSR_WUF8) == PWR_WUSR_WUF8)) +#else +#define __HAL_PWR_GET_FLAG(__FLAG__)( \ + ((__FLAG__) == PWR_FLAG_VOSRDY) ? (READ_BIT(PWR->VOSR, PWR_VOSR_VOSRDY)== \ + PWR_VOSR_VOSRDY) : \ + ((__FLAG__) == PWR_FLAG_STOPF) ? (READ_BIT(PWR->SR, PWR_SR_STOPF)== \ + PWR_SR_STOPF) : \ + ((__FLAG__) == PWR_FLAG_SBF) ? (READ_BIT(PWR->SR, PWR_SR_SBF)== \ + PWR_SR_SBF) : \ + ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ?(READ_BIT(PWR->SVMSR, PWR_SVMSR_ACTVOSRDY)== \ + PWR_SVMSR_ACTVOSRDY): \ + ((__FLAG__) == PWR_FLAG_PVDO) ?(READ_BIT(PWR->SVMSR, PWR_SVMSR_PVDO)== \ + PWR_SVMSR_PVDO) : \ + ((__FLAG__) == PWR_FLAG_REGPARDYVDDRFPA) ?(READ_BIT(PWR->RADIOSCR, PWR_RADIOSCR_REGPARDYVDDRFPA)== \ + PWR_RADIOSCR_REGPARDYVDDRFPA) : \ + ((__FLAG__) == PWR_FLAG_REGPARDYV11) ?(READ_BIT(PWR->RADIOSCR, PWR_RADIOSCR_REGPARDYV11)== \ + PWR_RADIOSCR_REGPARDYV11) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG1) ?(READ_BIT(PWR->WUSR, PWR_WUSR_WUF1) == \ + PWR_WUSR_WUF1) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG2) ?(READ_BIT(PWR->WUSR, PWR_WUSR_WUF2) == \ + PWR_WUSR_WUF2) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG3) ?(READ_BIT(PWR->WUSR, PWR_WUSR_WUF3) == \ + PWR_WUSR_WUF3) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG4) ?(READ_BIT(PWR->WUSR, PWR_WUSR_WUF4) == \ + PWR_WUSR_WUF4) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG5) ?(READ_BIT(PWR->WUSR, PWR_WUSR_WUF5) == \ + PWR_WUSR_WUF5) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG6) ?(READ_BIT(PWR->WUSR, PWR_WUSR_WUF6) == \ + PWR_WUSR_WUF6) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG7) ?(READ_BIT(PWR->WUSR, PWR_WUSR_WUF7) == \ + PWR_WUSR_WUF7) : \ + (READ_BIT(PWR->WUSR, PWR_WUSR_WUF8) == PWR_WUSR_WUF8)) +#endif /* defined(PWR_FLAG_REGS) */ +#else +#define __HAL_PWR_GET_FLAG(__FLAG__)( \ + ((__FLAG__) == PWR_FLAG_VOSRDY) ? (READ_BIT(PWR->VOSR, PWR_VOSR_VOSRDY)== \ + PWR_VOSR_VOSRDY) : \ + ((__FLAG__) == PWR_FLAG_STOPF) ? (READ_BIT(PWR->SR, PWR_SR_STOPF)== \ + PWR_SR_STOPF) : \ + ((__FLAG__) == PWR_FLAG_SBF) ? (READ_BIT(PWR->SR, PWR_SR_SBF)== \ + PWR_SR_SBF) : \ + ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ?(READ_BIT(PWR->SVMSR, PWR_SVMSR_ACTVOSRDY)== \ + PWR_SVMSR_ACTVOSRDY): \ + ((__FLAG__) == PWR_FLAG_PVDO) ?(READ_BIT(PWR->SVMSR, PWR_SVMSR_PVDO)== \ + PWR_SVMSR_PVDO) : \ + ((__FLAG__) == PWR_FLAG_REGPARDYVDDRFPA) ?(READ_BIT(PWR->RADIOSCR, PWR_RADIOSCR_REGPARDYVDDRFPA)== \ + PWR_RADIOSCR_REGPARDYVDDRFPA) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG1) ?(READ_BIT(PWR->WUSR, PWR_WUSR_WUF1) == \ + PWR_WUSR_WUF1) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG3) ?(READ_BIT(PWR->WUSR, PWR_WUSR_WUF3) == \ + PWR_WUSR_WUF3) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG4) ?(READ_BIT(PWR->WUSR, PWR_WUSR_WUF4) == \ + PWR_WUSR_WUF4) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG6) ?(READ_BIT(PWR->WUSR, PWR_WUSR_WUF6) == \ + PWR_WUSR_WUF6) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG7) ?(READ_BIT(PWR->WUSR, PWR_WUSR_WUF7) == \ + PWR_WUSR_WUF7) : \ + (READ_BIT(PWR->WUSR, PWR_WUSR_WUF8) == PWR_WUSR_WUF8)) +#endif /* defined(PWR_FLAG_REGPARDYV11) */ + +/** @brief Clear PWR flags. + * @param __FLAG__ : Specifies the flag to clear. + * This parameter can be one of the following values when available: + * @arg @ref PWR_FLAG_STOPF : Stop flag. + * Indicates that the device was resumed from Stop mode. + * @arg @ref PWR_FLAG_SBF : Standby flag. + * Indicates that the device was resumed from Standby mode. + * @arg @ref PWR_WAKEUP_FLAG1 : Wakeup flag 1. + * Indicates that a wakeup event was received from the WKUP line 1. + * @arg @ref PWR_WAKEUP_FLAG2 : Wakeup flag 2. + * Indicates that a wakeup event was received from the WKUP line 2. + * @arg @ref PWR_WAKEUP_FLAG3 : Wakeup flag 3. + * Indicates that a wakeup event was received from the WKUP line 3. + * @arg @ref PWR_WAKEUP_FLAG4 : Wakeup flag 4. + * Indicates that a wakeup event was received from the WKUP line 4. + * @arg @ref PWR_WAKEUP_FLAG5 : Wakeup flag 5. + * Indicates that a wakeup event was received from the WKUP line 5. + * @arg @ref PWR_WAKEUP_FLAG6 : Wakeup flag 6. + * Indicates that a wakeup event was received from the WKUP line 6. + * @arg @ref PWR_WAKEUP_FLAG7 : Wakeup flag 7. + * Indicates that a wakeup event was received from the WKUP line 7. + * @arg @ref PWR_WAKEUP_FLAG8 : Wakeup flag 8. + * Indicates that a wakeup event was received from the WKUP line 8. + * @arg @ref PWR_WAKEUP_ALL_FLAG : all Wakeup flags. + * @retval None. + */ +#if defined(PWR_WUCR1_WUPEN2) && defined(PWR_WUCR1_WUPEN5) +#define __HAL_PWR_CLEAR_FLAG(__FLAG__) ( \ + ((__FLAG__) == PWR_FLAG_STOPF) ? (SET_BIT(PWR->SR, PWR_SR_CSSF)) : \ + ((__FLAG__) == PWR_FLAG_SBF) ? (SET_BIT(PWR->SR, PWR_SR_CSSF)) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG1) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF1)) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG2) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF2)) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG3) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF3)) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG4) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF4)) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG5) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF5)) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG6) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF6)) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG7) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF7)) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG8) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF8)) : \ + (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF))) +#else +#define __HAL_PWR_CLEAR_FLAG(__FLAG__) ( \ + ((__FLAG__) == PWR_FLAG_STOPF) ? (SET_BIT(PWR->SR, PWR_SR_CSSF)) : \ + ((__FLAG__) == PWR_FLAG_SBF) ? (SET_BIT(PWR->SR, PWR_SR_CSSF)) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG1) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF1)) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG3) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF3)) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG4) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF4)) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG6) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF6)) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG7) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF7)) : \ + ((__FLAG__) == PWR_WAKEUP_FLAG8) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF8)) : \ + (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF))) +#endif /* defined(PWR_WUCR1_WUPEN2) && defined(PWR_WUCR1_WUPEN5) */ + +/** + * @brief Enable the PVD Extended Interrupt Line. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD) + +/** + * @brief Disable the PVD Extended Interrupt Line. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD) + +/** + * @brief Enable the PVD Event Line. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD) + +/** + * @brief Disable the PVD Event Line. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD) + +/** + * @brief Enable the PVD Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD) + +/** + * @brief Disable the PVD Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD) + +/** + * @brief Enable the PVD Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD) + +/** + * @brief Disable the PVD Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD) + +/** + * @brief Enable the PVD Extended Interrupt Rising & Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \ + do \ + { \ + __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); \ + } while(0) + +/** + * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \ + do \ + { \ + __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0) + +/** + * @brief Generate a Software Interrupt on selected EXTI line. + * @retval None + */ +#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD) + +/** + * @brief Check whether or not the PVD EXTI interrupt Rising flag is set. + * @retval EXTI PVD Line Status. + */ +#define __HAL_PWR_PVD_EXTI_GET_RISING_FLAG() (EXTI->RPR1 & PWR_EXTI_LINE_PVD) + +/** + * @brief Check whether or not the PVD EXTI interrupt Falling flag is set. + * @retval EXTI PVD Line Status. + */ +#define __HAL_PWR_PVD_EXTI_GET_FALLING_FLAG() (EXTI->FPR1 & PWR_EXTI_LINE_PVD) + +/** + * @brief Clear the PVD EXTI interrupt Rising flag. + * @retval None + */ +#define __HAL_PWR_PVD_EXTI_CLEAR_RISING_FLAG() WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_PVD) + +/** + * @brief Clear the PVD EXTI interrupt Falling flag. + * @retval None + */ +#define __HAL_PWR_PVD_EXTI_CLEAR_FALLING_FLAG() WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_PVD) +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ + +/** @addtogroup PWR_Private_Constants PWR Private Constants + * @{ + */ +/* Define PVD extended interrupts and event line */ +#define PWR_EXTI_LINE_PVD (0x00010000UL) /*!< PVD EXTI Line */ + +/* Defines wake up lines shift */ +#define PWR_WUP_POLARITY_SHIFT (0x08U) /*!< Internal constant used to retrieve wakeup signal polariry */ +#define PWR_WUP_SELECT_SIGNAL_SHIFT (0x10U) /*!< Internal constant used to retrieve wakeup signal selection */ + +/* Defines wake up lines mask */ +#define PWR_EWUP_MASK (0x000000FFUL) /*!< Internal constant used to retrieve wakeup signal enable */ +#define PWR_WUP_POLARITY_MASK (0x0000FF00UL) /*!< Internal constant used to retrieve wakeup signal polariry */ +#define PWR_WUP_SELECT_MASK (0xFFFF0000UL) /*!< Internal constant used to retrieve wakeup signal selection */ + +/* Defines wake up lines selection */ +#define PWR_WAKEUP1_SOURCE_SELECTION_0 (0U) +#if defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) +#define PWR_WAKEUP1_SOURCE_SELECTION_1 (PWR_WUCR3_WUSEL1_0 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ +#endif /* defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) */ + +#if defined(PWR_WUCR1_WUPEN2) +#define PWR_WAKEUP2_SOURCE_SELECTION_0 (0U) /*!< Internal constant used to retrieve wakeup signal selection */ +#define PWR_WAKEUP2_SOURCE_SELECTION_1 (PWR_WUCR3_WUSEL2_0 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ +#endif /* defined(PWR_WUCR1_WUPEN2) */ + +#define PWR_WAKEUP3_SOURCE_SELECTION_1 (PWR_WUCR3_WUSEL3_0 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ +#if defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) +#define PWR_WAKEUP3_SOURCE_SELECTION_2 (PWR_WUCR3_WUSEL3_1 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ +#endif /* defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) */ + +#define PWR_WAKEUP4_SOURCE_SELECTION_0 (0U) /*!< Internal constant used to retrieve wakeup signal selection */ +#if defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) +#define PWR_WAKEUP4_SOURCE_SELECTION_1 (PWR_WUCR3_WUSEL4_0 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ +#endif /* defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) */ + +#if defined(PWR_WUCR1_WUPEN5) +#define PWR_WAKEUP5_SOURCE_SELECTION_1 (PWR_WUCR3_WUSEL5_0 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ +#define PWR_WAKEUP5_SOURCE_SELECTION_2 (PWR_WUCR3_WUSEL5_1 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ +#endif /* defined(PWR_WUCR1_WUPEN5) */ + +#define PWR_WAKEUP6_SOURCE_SELECTION_0 (0U) /*!< Internal constant used to retrieve wakeup signal selection */ +#define PWR_WAKEUP6_SOURCE_SELECTION_1 (PWR_WUCR3_WUSEL6_0 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ +#define PWR_WAKEUP6_SOURCE_SELECTION_3 ((PWR_WUCR3_WUSEL6_0 | PWR_WUCR3_WUSEL6_1) << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ + +#if defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) +#define PWR_WAKEUP7_SOURCE_SELECTION_0 (0U) /*!< Internal constant used to retrieve wakeup signal selection */ +#endif /* defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) */ +#define PWR_WAKEUP7_SOURCE_SELECTION_1 (PWR_WUCR3_WUSEL7_0 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ +#define PWR_WAKEUP7_SOURCE_SELECTION_3 ((PWR_WUCR3_WUSEL7_0 | PWR_WUCR3_WUSEL7_1) << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ + +#define PWR_WAKEUP8_SOURCE_SELECTION_1 (PWR_WUCR3_WUSEL8_0 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ +#define PWR_WAKEUP8_SOURCE_SELECTION_2 (PWR_WUCR3_WUSEL8_1 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ +#define PWR_WAKEUP8_SOURCE_SELECTION_3 ((PWR_WUCR3_WUSEL8_0 | PWR_WUCR3_WUSEL8_1) << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ + +/* Defines wake up lines low polarity */ +#define PWR_WAKEUP1_POLARITY_LOW (PWR_WUCR2_WUPP1 << PWR_WUP_POLARITY_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ +#if defined(PWR_WUCR1_WUPEN2) +#define PWR_WAKEUP2_POLARITY_LOW (PWR_WUCR2_WUPP2 << PWR_WUP_POLARITY_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ +#endif /* defined(PWR_WUCR1_WUPEN2) */ +#define PWR_WAKEUP3_POLARITY_LOW (PWR_WUCR2_WUPP3 << PWR_WUP_POLARITY_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ +#define PWR_WAKEUP4_POLARITY_LOW (PWR_WUCR2_WUPP4 << PWR_WUP_POLARITY_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ +#if defined(PWR_WUCR1_WUPEN5) +#define PWR_WAKEUP5_POLARITY_LOW (PWR_WUCR2_WUPP5 << PWR_WUP_POLARITY_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ +#endif /* defined(PWR_WUCR1_WUPEN5) */ +#define PWR_WAKEUP6_POLARITY_LOW (PWR_WUCR2_WUPP6 << PWR_WUP_POLARITY_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ +#define PWR_WAKEUP7_POLARITY_LOW (PWR_WUCR2_WUPP7 << PWR_WUP_POLARITY_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ +#define PWR_WAKEUP8_POLARITY_LOW (PWR_WUCR2_WUPP8 << PWR_WUP_POLARITY_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ + +/* Defines attribute */ +#define PWR_ITEM_ATTR_NSEC_PRIV_MASK (0x10U) /*!< NSecure Privilege / NPrivilege attribute item mask */ +#define PWR_ITEM_ATTR_SEC_PRIV_MASK (0x20U) /*!< Secure Privilege / NPrivilege attribute item mask */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ + +/** @addtogroup PWR_Private_Macros PWR Private Macros + * @{ + */ + +/* Stop mode entry check macro */ +#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_LOWPOWERMODE_STOP0) || \ + ((REGULATOR) == PWR_LOWPOWERMODE_STOP1)) + +/* Wake up pins check macro */ +#if defined(PWR_WUCR1_WUPEN2) && defined(PWR_WUCR1_WUPEN5) +#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1_HIGH_0) ||\ + ((PIN) == PWR_WAKEUP_PIN1_HIGH_1) ||\ + ((PIN) == PWR_WAKEUP_PIN2_HIGH_0) ||\ + ((PIN) == PWR_WAKEUP_PIN2_HIGH_1) ||\ + ((PIN) == PWR_WAKEUP_PIN3_HIGH_1) ||\ + ((PIN) == PWR_WAKEUP_PIN3_HIGH_2) ||\ + ((PIN) == PWR_WAKEUP_PIN4_HIGH_0) ||\ + ((PIN) == PWR_WAKEUP_PIN4_HIGH_1) ||\ + ((PIN) == PWR_WAKEUP_PIN5_HIGH_1) ||\ + ((PIN) == PWR_WAKEUP_PIN5_HIGH_2) ||\ + ((PIN) == PWR_WAKEUP_PIN6_HIGH_0) ||\ + ((PIN) == PWR_WAKEUP_PIN6_HIGH_1) ||\ + ((PIN) == PWR_WAKEUP_PIN6_HIGH_3) ||\ + ((PIN) == PWR_WAKEUP_PIN7_HIGH_0) ||\ + ((PIN) == PWR_WAKEUP_PIN7_HIGH_1) ||\ + ((PIN) == PWR_WAKEUP_PIN7_HIGH_3) ||\ + ((PIN) == PWR_WAKEUP_PIN8_HIGH_1) ||\ + ((PIN) == PWR_WAKEUP_PIN8_HIGH_2) ||\ + ((PIN) == PWR_WAKEUP_PIN8_HIGH_3) ||\ + ((PIN) == PWR_WAKEUP_PIN1_LOW_0) ||\ + ((PIN) == PWR_WAKEUP_PIN1_LOW_1) ||\ + ((PIN) == PWR_WAKEUP_PIN2_LOW_0) ||\ + ((PIN) == PWR_WAKEUP_PIN2_LOW_1) ||\ + ((PIN) == PWR_WAKEUP_PIN3_LOW_1) ||\ + ((PIN) == PWR_WAKEUP_PIN3_LOW_2) ||\ + ((PIN) == PWR_WAKEUP_PIN4_LOW_0) ||\ + ((PIN) == PWR_WAKEUP_PIN4_LOW_1) ||\ + ((PIN) == PWR_WAKEUP_PIN5_LOW_1) ||\ + ((PIN) == PWR_WAKEUP_PIN5_LOW_2) ||\ + ((PIN) == PWR_WAKEUP_PIN6_LOW_0) ||\ + ((PIN) == PWR_WAKEUP_PIN6_LOW_1) ||\ + ((PIN) == PWR_WAKEUP_PIN6_LOW_3) ||\ + ((PIN) == PWR_WAKEUP_PIN7_LOW_0) ||\ + ((PIN) == PWR_WAKEUP_PIN7_LOW_1) ||\ + ((PIN) == PWR_WAKEUP_PIN7_LOW_3) ||\ + ((PIN) == PWR_WAKEUP_PIN8_LOW_1) ||\ + ((PIN) == PWR_WAKEUP_PIN8_LOW_2) ||\ + ((PIN) == PWR_WAKEUP_PIN8_LOW_3) ||\ + ((PIN) == PWR_WAKEUP_PIN1) ||\ + ((PIN) == PWR_WAKEUP_PIN2) ||\ + ((PIN) == PWR_WAKEUP_PIN3) ||\ + ((PIN) == PWR_WAKEUP_PIN4) ||\ + ((PIN) == PWR_WAKEUP_PIN5) ||\ + ((PIN) == PWR_WAKEUP_PIN6) ||\ + ((PIN) == PWR_WAKEUP_PIN7) ||\ + ((PIN) == PWR_WAKEUP_PIN8)) +#else +#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1_HIGH_0) ||\ + ((PIN) == PWR_WAKEUP_PIN3_HIGH_1) ||\ + ((PIN) == PWR_WAKEUP_PIN4_HIGH_0) ||\ + ((PIN) == PWR_WAKEUP_PIN6_HIGH_0) ||\ + ((PIN) == PWR_WAKEUP_PIN6_HIGH_1) ||\ + ((PIN) == PWR_WAKEUP_PIN6_HIGH_3) ||\ + ((PIN) == PWR_WAKEUP_PIN7_HIGH_1) ||\ + ((PIN) == PWR_WAKEUP_PIN7_HIGH_3) ||\ + ((PIN) == PWR_WAKEUP_PIN8_HIGH_1) ||\ + ((PIN) == PWR_WAKEUP_PIN8_HIGH_2) ||\ + ((PIN) == PWR_WAKEUP_PIN8_HIGH_3) ||\ + ((PIN) == PWR_WAKEUP_PIN1_LOW_0) ||\ + ((PIN) == PWR_WAKEUP_PIN3_LOW_1) ||\ + ((PIN) == PWR_WAKEUP_PIN4_LOW_0) ||\ + ((PIN) == PWR_WAKEUP_PIN6_LOW_0) ||\ + ((PIN) == PWR_WAKEUP_PIN6_LOW_1) ||\ + ((PIN) == PWR_WAKEUP_PIN6_LOW_3) ||\ + ((PIN) == PWR_WAKEUP_PIN7_LOW_1) ||\ + ((PIN) == PWR_WAKEUP_PIN7_LOW_3) ||\ + ((PIN) == PWR_WAKEUP_PIN8_LOW_1) ||\ + ((PIN) == PWR_WAKEUP_PIN8_LOW_2) ||\ + ((PIN) == PWR_WAKEUP_PIN8_LOW_3) ||\ + ((PIN) == PWR_WAKEUP_PIN1) ||\ + ((PIN) == PWR_WAKEUP_PIN3) ||\ + ((PIN) == PWR_WAKEUP_PIN4) ||\ + ((PIN) == PWR_WAKEUP_PIN6) ||\ + ((PIN) == PWR_WAKEUP_PIN7) ||\ + ((PIN) == PWR_WAKEUP_PIN8)) +#endif /* defined(PWR_WUCR1_WUPEN2) && defined(PWR_WUCR1_WUPEN5) */ + +/* PVD level check macro */ +#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1) || \ + ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3) || \ + ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5) || \ + ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) + +/* PVD mode check macro */ +#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_NORMAL) ||\ + ((MODE) == PWR_PVD_MODE_IT_RISING) ||\ + ((MODE) == PWR_PVD_MODE_IT_FALLING) ||\ + ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) ||\ + ((MODE) == PWR_PVD_MODE_EVENT_RISING) ||\ + ((MODE) == PWR_PVD_MODE_EVENT_FALLING) ||\ + ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING)) + +/* Sleep mode entry check macro */ +#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) + +/* Stop mode entry check macro */ +#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE)) + +/* PWR items check macro */ +#define IS_PWR_ITEMS_ATTRIBUTES(ITEM) ((((ITEM) & (~PWR_ALL)) == 0U) && ((ITEM) != 0U)) + +#if defined(PWR_PRIVCFGR_SPRIV) +#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/* PWR attribute check macro (Secure) */ +#define IS_PWR_ATTRIBUTES(ATTRIBUTES) ((((~(((ATTRIBUTES)& \ + 0xF0U) >> 4U)) & ((ATTRIBUTES) & 0x0FU)) == 0U) && \ + (((ATTRIBUTES) & 0xFFFFFFCCU) == 0U)) +#else +/* PWR attribute check macro (NSecure) */ +#define IS_PWR_ATTRIBUTES(ATTRIBUTES) (((ATTRIBUTES) == PWR_NSEC_NPRIV) || ((ATTRIBUTES) == PWR_NSEC_PRIV)) +#endif /* __ARM_FEATURE_CMSE */ +#endif /* defined(PWR_PRIVCFGR_SPRIV) */ + +/* PWR regulation VDDHPA input supply selection */ +#define IS_PWR_REGPASEL_SUPPLYSELECTION(SUPPLYSELECTION) (((SUPPLYSELECTION) == PWR_RADIO_REG_VDDRFPA) ||\ + ((SUPPLYSELECTION) == PWR_RADIO_REG_VDDHPA_VD11)) +/** + * @} + */ + +/* Include PWR HAL Extended module */ +#include "stm32wbaxx_hal_pwr_ex.h" + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup PWR_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @addtogroup PWR_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +void HAL_PWR_DeInit(void); +void HAL_PWR_EnableBkUpAccess(void); +void HAL_PWR_DisableBkUpAccess(void); +/** + * @} + */ + +/** @addtogroup PWR_Exported_Functions_Group2 + * @{ + */ +/* Programmable voltage detector functions ************************************/ +HAL_StatusTypeDef HAL_PWR_ConfigPVD(const PWR_PVDTypeDef *sConfigPVD); +void HAL_PWR_EnablePVD(void); +void HAL_PWR_DisablePVD(void); + +/* Wake up pins configuration functions ***************************************/ +void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPin); +void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPin); +uint32_t HAL_PWR_GetClearWakeupSource(void); + +/* Low power modes configuration functions ************************************/ +void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); +void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); +void HAL_PWR_EnterSTANDBYMode(void); + +/* Sleep on exit and sev on pending configuration functions *******************/ +void HAL_PWR_EnableSleepOnExit(void); +void HAL_PWR_DisableSleepOnExit(void); +void HAL_PWR_EnableSEVOnPend(void); +void HAL_PWR_DisableSEVOnPend(void); + +/* Interrupt handler functions ************************************************/ +void HAL_PWR_PVD_IRQHandler(void); +void HAL_PWR_PVD_Rising_Callback(void); +void HAL_PWR_PVD_Falling_Callback(void); +void HAL_PWR_WKUP_IRQHandler(void); +void HAL_PWR_WKUP1_Callback(void); +#if defined(PWR_WUCR1_WUPEN2) +void HAL_PWR_WKUP2_Callback(void); +#endif /* defined(PWR_WUCR1_WUPEN2) */ +void HAL_PWR_WKUP3_Callback(void); +void HAL_PWR_WKUP4_Callback(void); +#if defined(PWR_WUCR1_WUPEN5) +void HAL_PWR_WKUP5_Callback(void); +#endif /* defined(PWR_WUCR1_WUPEN5) */ +void HAL_PWR_WKUP6_Callback(void); +void HAL_PWR_WKUP7_Callback(void); +void HAL_PWR_WKUP8_Callback(void); +/** + * @} + */ + +/** @addtogroup PWR_Exported_Functions_Group3 + * @{ + */ +/* Privileges and security configuration functions ****************************/ +void HAL_PWR_ConfigAttributes(uint32_t Item, uint32_t Attributes); +HAL_StatusTypeDef HAL_PWR_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STM32WBAxx_HAL_PWR_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_pwr_ex.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_pwr_ex.h new file mode 100644 index 0000000000..0c6b190396 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_pwr_ex.h @@ -0,0 +1,375 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_pwr_ex.h + * @author MCD Application Team + * @brief Header file of PWR HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_HAL_PWR_EX_H +#define STM32WBAxx_HAL_PWR_EX_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal_def.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @addtogroup PWREx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup PWREx_Exported_Types PWR Extended Exported Types + * @{ + */ + + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup PWREx_Exported_Constants PWR Extended Exported Constants + * @{ + */ + +/** @defgroup PWREx_RAM_Contents_Stop_Retention PWR Extended SRAM Contents Stop Retention + * @{ + */ +/* SRAM1 pages retention defines */ +#define PWR_SRAM1_FULL_STOP_RETENTION PWR_CR2_SRAM1PDS1 /*!< SRAM1 full retention in Stop modes */ +/* SRAM2 pages retention defines */ +#define PWR_SRAM2_FULL_STOP_RETENTION PWR_CR2_SRAM2PDS1 /*!< SRAM2 full retention in Stop modes */ +/* Cache RAMs retention defines */ +#define PWR_ICACHE_FULL_STOP_RETENTION PWR_CR2_ICRAMPDS /*!< ICACHE SRAM retention in Stop modes */ +/** + * @} + */ + + +/** @defgroup PWREx_RAM_Contents_Standby_Retention PWR Extended SRAM Contents Standby Retention + * @{ + */ +#define PWR_SRAM1_FULL_STANDBY_RETENTION PWR_CR1_R1RSB1 /*!< SRAM1 full retention in Standby mode */ + +#define PWR_SRAM2_FULL_STANDBY_RETENTION PWR_CR1_R2RSB1 /*!< SRAM2 full retention in Standby mode */ +#define PWR_RADIOSRAM_FULL_STANDBY_RETENTION PWR_CR1_RADIORSB /*!< 2.4GHz RADIO SRAMs (TXRX and Sequence) + and Sleep clock retention in Standby mode */ +/** + * @} + */ + +#if defined(PWR_CR3_REGSEL) +/** @defgroup PWREx_Supply_Configuration PWR Extended Supply Configuration + * @{ + */ +#define PWR_LDO_SUPPLY (0U) /* LDO supply */ +#define PWR_SMPS_SUPPLY PWR_CR3_REGSEL /* SMPS supply */ +/** + * @} + */ +#endif /* defined(PWR_CR3_REGSEL) */ + +/** @defgroup PWREx_Regulator_Voltage_Scale PWR Extended Regulator Voltage Scale + * @{ + */ +#define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_VOSR_VOS /*!< Voltage scaling range 1 */ +#define PWR_REGULATOR_VOLTAGE_SCALE2 (0U) /*!< Voltage scaling range 2 */ +/** + * @} + */ + +/** @defgroup PWREx_GPIO_Port PWR Extended GPIO Port + * @{ + */ +#define PWR_GPIO_A (0x00U) /*!< GPIO port A */ +#define PWR_GPIO_B (0x01U) /*!< GPIO port B */ +#define PWR_GPIO_C (0x02U) /*!< GPIO port C */ +#define PWR_GPIO_H (0x07U) /*!< GPIO port H */ +/** + * @} + */ + +/** @defgroup PWREx_GPIO_Pin_Mask PWR Extended GPIO Pin Mask + * @{ + */ +#define PWR_GPIO_BIT_0 (0x00001U) /*!< GPIO port I/O pin 0 */ +#define PWR_GPIO_BIT_1 (0x00002U) /*!< GPIO port I/O pin 1 */ +#define PWR_GPIO_BIT_2 (0x00004U) /*!< GPIO port I/O pin 2 */ +#define PWR_GPIO_BIT_3 (0x00008U) /*!< GPIO port I/O pin 3 */ +#define PWR_GPIO_BIT_4 (0x00010U) /*!< GPIO port I/O pin 4 */ +#define PWR_GPIO_BIT_5 (0x00020U) /*!< GPIO port I/O pin 5 */ +#define PWR_GPIO_BIT_6 (0x00040U) /*!< GPIO port I/O pin 6 */ +#define PWR_GPIO_BIT_7 (0x00080U) /*!< GPIO port I/O pin 7 */ +#define PWR_GPIO_BIT_8 (0x00100U) /*!< GPIO port I/O pin 8 */ +#define PWR_GPIO_BIT_9 (0x00200U) /*!< GPIO port I/O pin 9 */ +#define PWR_GPIO_BIT_10 (0x00400U) /*!< GPIO port I/O pin 10 */ +#define PWR_GPIO_BIT_11 (0x00800U) /*!< GPIO port I/O pin 11 */ +#define PWR_GPIO_BIT_12 (0x01000U) /*!< GPIO port I/O pin 12 */ +#define PWR_GPIO_BIT_13 (0x02000U) /*!< GPIO port I/O pin 13 */ +#define PWR_GPIO_BIT_14 (0x04000U) /*!< GPIO port I/O pin 14 */ +#define PWR_GPIO_BIT_15 (0x08000U) /*!< GPIO port I/O pin 15 */ +#define PWR_GPIO_PIN_MASK (0x0FFFFU) +/** + * @} + */ + +/** @defgroup PWREx_RADIO_Mode PWR Extended 2.4 GHz RADIO operating mode + * @{ + */ +#define PWR_RADIO_DEEPSLEEP_MODE (0x0U) /*!< 2.4 GHz RADIO deep sleep mode */ +#define PWR_RADIO_SLEEP_MODE PWR_RADIOSCR_MODE_0 /*!< 2.4 GHz RADIO sleep mode */ +#define PWR_RADIO_ACTIVE_MODE PWR_RADIOSCR_MODE_1 /*!< 2.4 GHz RADIO active mode */ +/** + * @} + */ + +/** @defgroup PWREx_RADIO_PHY_Mode PWR Extended 2.4 GHz RADIO PHY operating mode + * @{ + */ +#define PWR_RADIO_PHY_SLEEP_MODE (0x0U) /*!< 2.4 GHz RADIO PHY sleep mode */ +#define PWR_RADIO_PHY_STANDBY_MODE PWR_RADIOSCR_PHYMODE /*!< 2.4 GHz RADIO PHY standby mode */ +/** + * @} + */ + +/** @defgroup PWREx_RADIO_ENCODE_Mode PWR Extended 2.4 GHz RADIO encryption operating mode + * @{ + */ +#define PWR_RADIO_ENCMODE_DISABLED (0x0U) /*!< 2.4 GHz RADIO encryption function disabled */ +#define PWR_RADIO_ENCMODE_ENABLED PWR_RADIOSCR_ENCMODE /*!< 2.4 GHz RADIO encryption function enabled */ +/** + * @} + */ + +#if defined(PWR_RADIOSCR_REGPASEL) +/** @defgroup PWREx_Regulator_Input_Supply_Selection PWR Extended RADIO regulator input supply selection + * @{ + */ +#define PWR_RADIO_REG_VDDRFPA (0x0U) /*!< VDDRFPA pin selected as regulator REG_VDDHPA input supply */ +#define PWR_RADIO_REG_VDDHPA_VD11 PWR_RADIOSCR_REGPASEL +/*!< Regulator REG_VDDHPA input supply selection between VDDRFPA + and VDD11 dependent on requested regulated output voltage */ +/** + * @} + */ +#endif /* defined(PWR_RADIOSCR_REGPASEL) */ + + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ + +/** @defgroup PWREx_Exported_Macros PWR Extended Exported Macros + * @{ + */ + +/** + * @brief Configure the main internal regulator output voltage. + * @note This macro is similar to HAL_PWREx_ControlVoltageScaling() API but + * doesn't check whether or not VOSRDY flag is set. User may resort + * to __HAL_PWR_GET_FLAG() macro to check VOSRDY bit state. + * @param __REGULATOR__ : Specifies the regulator output voltage to achieve a + * tradeoff between performance and power consumption. + * This parameter can be one of the following values : + * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 : Regulator voltage output scale 1. + * Provides a typical output voltage at 1.2 V. + * It allows a system clock frequency up to 100 MHz, + * and is required for any 2.4 GHz RADIO transmit and + * receive operation. + * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 : Regulator voltage output scale 2. + * The system clock frequency can be up to 16 MHz. + * The 2.4 GHz RADIO shall not transmit nor receive. + * @retval None. + */ +#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) \ + do \ + { \ + __IO uint32_t tmpreg; \ + MODIFY_REG(PWR->VOSR, PWR_VOSR_VOS, (__REGULATOR__)); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(PWR->VOSR, PWR_VOSR_VOS); \ + UNUSED(tmpreg); \ + } while(0) +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ + +/** @addtogroup PWREx_Private_Constants PWR Extended Private Constants + * @{ + */ + +/* All available RAM retention in Stop mode define */ +#define PWR_ALL_RAM_STOP_RETENTION_MASK (PWR_SRAM1_FULL_STOP_RETENTION | PWR_SRAM2_FULL_STOP_RETENTION | \ + PWR_ICACHE_FULL_STOP_RETENTION ) + +/* All available RAM retention in Standby mode define */ +#define PWR_ALL_RAM_STANDBY_RETENTION_MASK (PWR_SRAM1_FULL_STANDBY_RETENTION | PWR_SRAM2_FULL_STANDBY_RETENTION) +/** + * @} + */ + +/* Private macros --------------------------------------------------------*/ + +/** @addtogroup PWREx_Private_Macros PWR Extended Private Macros + * @{ + */ + +#if defined(PWR_CR3_REGSEL) +/* Supply selection check macro */ +#define IS_PWR_SUPPLY(PWR_SOURCE) (((PWR_SOURCE) == PWR_LDO_SUPPLY) ||\ + ((PWR_SOURCE) == PWR_SMPS_SUPPLY)) +#endif /* defined(PWR_CR3_REGSEL) */ + +/* Voltage scaling range check macro */ +#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) ||\ + ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2)) +/* GPIO port check macro */ +#define IS_PWR_GPIO_PORT(GPIO_PORT) (((GPIO_PORT) == PWR_GPIO_A) ||\ + ((GPIO_PORT) == PWR_GPIO_B) ||\ + ((GPIO_PORT) == PWR_GPIO_C) ||\ + ((GPIO_PORT) == PWR_GPIO_H)) + +/* GPIO pin mask check macro */ +#define IS_PWR_GPIO_PIN_MASK(BIT_MASK) ((((BIT_MASK) & PWR_GPIO_PIN_MASK) != 0U) &&\ + ((BIT_MASK) <= PWR_GPIO_PIN_MASK)) + +/* SRAM1 retention in Standby mode check macro */ +#define IS_PWR_SRAM1_STANDBY_RETENTION(CONTENT) ((CONTENT) == PWR_SRAM1_FULL_STANDBY_RETENTION) + +/* SRAM2 retention in Standby mode check macro */ +#define IS_PWR_SRAM2_STANDBY_RETENTION(CONTENT) ((CONTENT) == PWR_SRAM2_FULL_STANDBY_RETENTION) + +/* RADIO SRAM retention in Standby mode check macro */ +#define IS_PWR_RADIOSRAM_STANDBY_RETENTION(CONTENT) ((CONTENT) == PWR_RADIOSRAM_FULL_STANDBY_RETENTION) + +/* RAMs retention in Stop mode check macro */ +#define IS_PWR_RAM_STOP_RETENTION(RAMCONTENT) (((RAMCONTENT) == PWR_SRAM1_FULL_STOP_RETENTION) ||\ + ((RAMCONTENT) == PWR_SRAM2_FULL_STOP_RETENTION) ||\ + ((RAMCONTENT) == PWR_ICACHE_FULL_STOP_RETENTION)) +/** + * @} + */ + +/** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions + * @{ + */ + +/** @addtogroup PWREx_Exported_Functions_Group1 Power Supply Control Functions + * @{ + */ +HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling); +uint32_t HAL_PWREx_GetVoltageRange(void); + +#if defined(PWR_CR3_REGSEL) +HAL_StatusTypeDef HAL_PWREx_ConfigSupply(uint32_t SupplySource); +uint32_t HAL_PWREx_GetSupplyConfig(void); +#endif /* defined(PWR_CR3_REGSEL) */ +#if defined(PWR_CR2_FPWM) +void HAL_PWREx_EnableSMPSPWM(void); +void HAL_PWREx_DisableSMPSPWM(void); +#endif /* defined(PWR_CR2_FPWM) */ +void HAL_PWREx_EnableFastSoftStart(void); +void HAL_PWREx_DisableFastSoftStart(void); +/** + * @} + */ + +/** @addtogroup PWREx_Exported_Functions_Group2 Low Power Control Functions + * @{ + */ +void HAL_PWREx_EnableUltraLowPowerMode(void); +void HAL_PWREx_DisableUltraLowPowerMode(void); +/** + * @} + */ + +/** @addtogroup PWREx_Exported_Functions_Group4 Memories Retention Functions + * @{ + */ +void HAL_PWREx_EnableSRAM2ContentStandbyRetention(uint32_t SRAM2Pages); +void HAL_PWREx_DisableSRAM2ContentStandbyRetention(void); +void HAL_PWREx_EnableRadioSRAMClockStandbyRetention(uint32_t RadioSRAM); +void HAL_PWREx_DisableRadioSRAMClockStandbyRetention(void); +void HAL_PWREx_EnableSRAM1ContentStandbyRetention(uint32_t SRAM1Pages); +void HAL_PWREx_DisableSRAM1ContentStandbyRetention(void); +void HAL_PWREx_EnableRAMsContentStopRetention(uint32_t RAMSelection); +void HAL_PWREx_DisableRAMsContentStopRetention(uint32_t RAMSelection); +void HAL_PWREx_EnableFlashFastWakeUp(void); +void HAL_PWREx_DisableFlashFastWakeUp(void); +/** + * @} + */ + +/** @addtogroup PWREx_Exported_Functions_Group5 I/O Retention Functions + * @{ + */ +HAL_StatusTypeDef HAL_PWREx_EnableStandbyIORetention(uint32_t GPIO_Port, uint32_t GPIO_Pin); +HAL_StatusTypeDef HAL_PWREx_DisableStandbyIORetention(uint32_t GPIO_Port, uint32_t GPIO_Pin); +uint32_t HAL_PWREx_GetStandbyIORetentionStatus(uint32_t GPIO_Port); +HAL_StatusTypeDef HAL_PWREx_DisableStandbyRetainedIOState(uint32_t GPIO_Port, uint32_t GPIO_Pin); +/** + * @} + */ + +/** @addtogroup PWREx_Exported_Functions_Group6 I/O RADIO Configuration and Status Reading Functions + * @{ + */ +uint32_t HAL_PWREx_GetRADIOOperatingMode(void); +uint32_t HAL_PWREx_GetRADIOPHYOperatingMode(void); +uint32_t HAL_PWREx_GetRADIOEncryptionOperatingMode(void); +uint32_t HAL_PWREx_GetRFVDDHPA(void); + +#if defined(PWR_RADIOSCR_REGPASEL) +HAL_StatusTypeDef HAL_PWREx_SetREGVDDHPAInputSupply(uint32_t SupplySelection); +uint32_t HAL_PWREx_GetREGVDDHPAInputSupply(void); +#endif /* defined(PWR_RADIOSCR_REGPASEL) */ +#if defined(PWR_RADIOSCR_REGPABYPEN) +void HAL_PWREx_EnableREGVDDHPABypass(void); +void HAL_PWREx_DisableREGVDDHPABypass(void); +#endif /* defined(PWR_RADIOSCR_REGPABYPEN) */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** +* @} +*/ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + + +#endif /* STM32WBAxx_HAL_PWR_EX_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_ramcfg.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_ramcfg.h new file mode 100644 index 0000000000..926969e5fd --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_ramcfg.h @@ -0,0 +1,431 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_ramcfg.h + * @author MCD Application Team + * @brief Header file of RAMCFG HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_HAL_RAMCFG_H +#define STM32WBAxx_HAL_RAMCFG_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal_def.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @addtogroup RAMCFG + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup RAMCFG_Exported_Types RAMCFG Exported Types + * @brief RAMCFG Exported Types + * @{ + */ + +/** + * @brief HAL RAMCFG State Enumeration Definition + */ +typedef enum +{ + HAL_RAMCFG_STATE_RESET = 0x00U, /*!< RAMCFG not yet initialized or disabled */ + HAL_RAMCFG_STATE_READY = 0x01U, /*!< RAMCFG initialized and ready for use */ + HAL_RAMCFG_STATE_BUSY = 0x02U, /*!< RAMCFG process is ongoing */ + HAL_RAMCFG_STATE_ERROR = 0x03U, /*!< RAMCFG error state */ +} HAL_RAMCFG_StateTypeDef; + +#if (USE_HAL_RAMCFG_REGISTER_CALLBACKS == 1) +/** + * @brief HAL RAMCFG Callbacks IDs Enumeration Definition + */ +typedef enum +{ + HAL_RAMCFG_MSPINIT_CB_ID = 0x00U, /*!< RAMCFG MSP Init Callback ID */ + HAL_RAMCFG_MSPDEINIT_CB_ID = 0x01U, /*!< RAMCFG MSP DeInit Callback ID */ + HAL_RAMCFG_PE_DETECT_CB_ID = 0x02U, /*!< RAMCFG Parity Error Detect Callback ID */ + HAL_RAMCFG_ALL_CB_ID = 0x03U, /*!< RAMCFG All callback ID */ +} HAL_RAMCFG_CallbackIDTypeDef; +#endif /* USE_HAL_RAMCFG_REGISTER_CALLBACKS */ + +/** + * @brief RAMCFG Handle Structure Definition + */ +#if (USE_HAL_RAMCFG_REGISTER_CALLBACKS == 1U) +typedef struct __RAMCFG_HandleTypeDef +#else +typedef struct +#endif /* (USE_HAL_RAMCFG_REGISTER_CALLBACKS) */ +{ + RAMCFG_TypeDef *Instance; /*!< RAMCFG Register Base Address */ + __IO HAL_RAMCFG_StateTypeDef State; /*!< RAMCFG State */ + __IO uint32_t ErrorCode; /*!< RAMCFG Error Code */ +#if (USE_HAL_RAMCFG_REGISTER_CALLBACKS == 1U) + void (* MspInitCallback)(struct __RAMCFG_HandleTypeDef *hramcfg); /*!< RAMCFG MSP Init Callback */ + void (* MspDeInitCallback)(struct __RAMCFG_HandleTypeDef *hramcfg); /*!< RAMCFG MSP DeInit Callback */ + void (* DetectParityErrorCallback)(struct __RAMCFG_HandleTypeDef *hramcfg); /*!< RAMCFG Parity Error Detect Callback */ +#endif /* USE_HAL_RAMCFG_REGISTER_CALLBACKS */ +} RAMCFG_HandleTypeDef; + +/** + * @brief RAMCFG Parity Error Address Register Definition + */ +typedef struct +{ + uint32_t Byte; /*!< Byte parity error flag */ + /*!< 1xxx: parity error detected on 4th byte in word aligned address */ + /*!< x1xx: parity error detected on 3rd byte in word aligned address */ + /*!< xx1x: parity error detected on 2th byte in word aligned address */ + /*!< xxx1: parity error detected on 1st byte in word aligned address */ + uint32_t BusMasterId; /*!< Parity error AHB bus master ID */ + uint32_t AddressOffset; /*!< Parity error SRAM word aligned address offset */ +} RAMCFG_PEAddressTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup RAMCFG_Exported_Constants RAMCFG Exported Constants + * @brief RAMCFG Exported Constants + * @{ + */ + +/** @defgroup RAMCFG_Error_Codes RAMCFG Error Codes + * @brief RAMCFG Error Codes + * @{ + */ +#define HAL_RAMCFG_ERROR_NONE 0x00000000U /*!< RAMCFG No Error */ +#define HAL_RAMCFG_ERROR_TIMEOUT 0x00000001U /*!< RAMCFG Timeout Error */ +#define HAL_RAMCFG_ERROR_BUSY 0x00000002U /*!< RAMCFG Busy Error */ +#if (USE_HAL_RAMCFG_REGISTER_CALLBACKS == 1U) +#define HAL_RAMCFG_ERROR_INVALID_CALLBACK 0x00000003U /*!< Invalid Callback error */ +#endif /* USE_HAL_RAMCFG_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup RAMCFG_Interrupt RAMCFG Interrupts + * @brief RAMCFG Interrupts + * @{ + */ +#define RAMCFG_IT_PARITYERR RAMCFG_IER_PEIE /*!< RAMCFG Parity Error Interrupt */ +#define RAMCFG_IT_NMIERR RAMCFG_IER_PENMI /*!< RAMCFG Parity Error redirected to NMI Interrupt */ +#define RAMCFG_IT_ALL (RAMCFG_IER_PEIE | \ + RAMCFG_IER_PENMI) /*!< RAMCFG All RAMCFG interrupt */ +/** + * @} + */ + +/** @defgroup RAMCFG_FLAG RAMCFG Monitor Flags + * @brief RAMCFG Monitor Flags + * @{ + */ +#define RAMCFG_FLAG_PARITYERR RAMCFG_ISR_PED /*!< RAMCFG Parity Error Detected Flag */ +#define RAMCFG_FLAG_SRAMBUSY RAMCFG_ISR_SRAMBUSY /*!< RAMCFG SRAM busy Flag */ +#define RAMCFG_FLAGS_ALL (RAMCFG_ISR_PED | \ + RAMCFG_ISR_SRAMBUSY) /*!< RAMCFG All Flags */ +/** + * @} + */ + +/** @defgroup RAMCFG_WaitState RAMCFG Wait State + * @brief RAMCFG Wait State + * @{ + */ +#define RAMCFG_WAITSTATE_0 (0U) /*!< RAMCFG 0 Wait State */ +#define RAMCFG_WAITSTATE_1 (RAMCFG_CR_WSC_0) /*!< RAMCFG 1 Wait State */ +#define RAMCFG_WAITSTATE_2 (RAMCFG_CR_WSC_1) /*!< RAMCFG 2 Wait State */ +#define RAMCFG_WAITSTATE_3 (RAMCFG_CR_WSC_0 | RAMCFG_CR_WSC_1) /*!< RAMCFG 3 Wait State */ +#define RAMCFG_WAITSTATE_4 (RAMCFG_CR_WSC_2) /*!< RAMCFG 4 Wait State */ +#define RAMCFG_WAITSTATE_5 (RAMCFG_CR_WSC_0 | RAMCFG_CR_WSC_2) /*!< RAMCFG 5 Wait State */ +#define RAMCFG_WAITSTATE_6 (RAMCFG_CR_WSC_1 | RAMCFG_CR_WSC_2) /*!< RAMCFG 6 Wait State */ +#define RAMCFG_WAITSTATE_7 (RAMCFG_CR_WSC_0 | RAMCFG_CR_WSC_1 | RAMCFG_CR_WSC_2) /*!< RAMCFG 7 Wait State */ +/** + * @} + */ + +/** @defgroup RAMCFG_Keys RAMCFG Keys + * @brief RAMCFG Keys + * @{ + */ +#define RAMCFG_ERASE_KEY1 (0xCAU) /*!< RAMCFG launch Erase Key 1 */ +#define RAMCFG_ERASE_KEY2 (0x53U) /*!< RAMCFG launch Erase Key 2 */ + +#define RAMCFG_PED_KEY1 (0xAEU) /*!< RAMCFG launch PED Key 1 */ +#define RAMCFG_PED_KEY2 (0x75U) /*!< RAMCFG launch PED Key 2 */ +/** + * @} + */ + +/** @defgroup RAMCFG_ParityError_BusMasterId RAMCFG Parity error AHB bus master IDs + * @brief RAMCFG Parity error AHB bus master IDs + * @{ + */ +#define RAMCFG_PARITY_ERROR_CPU_ACCESS (2U) +#define RAMCFG_PARITY_ERROR_DEBUGGER_ACCESS (3U) +#define RAMCFG_PARITY_ERROR_DMA_PORT0_ACCESS (6U) +#define RAMCFG_PARITY_ERROR_DMA_PORT1_ACCESS (7U) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup RAMCFG_Exported_Macros RAMCFG Exported Macros + * @brief RAMCFG Exported Macros + * @{ + */ + +/** + * @brief Enable the specified RAMCFG interrupts. + * @param __HANDLE__ : Specifies RAMCFG handle. + * @param __INTERRUPT__: Specifies the RAMCFG interrupt sources to be enabled. + * This parameter can be one of the following values: + * @arg RAMCFG_IT_PARITYERR : Parity Error Interrupt Mask. + * @arg RAMCFG_IT_NMIERR : Parity Error Interrupt redirection to NMI Mask. + * @arg RAMCFG_IT_ALL : All Interrupt Mask. + * @retval None + */ +#define __HAL_RAMCFG_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) + +/** + * @brief Disable the specified RAMCFG interrupts. + * @note This macros is used only to disable RAMCFG_IT_PARITYERR interrupt. + * RAMCFG_IT_NMIERR interrupt can only be disabled by global + * peripheral reset or system reset. + * @param __HANDLE__ : Specifies RAMCFG handle. + * @param __INTERRUPT__: Specifies the RAMCFG interrupt sources to be disabled. + * This parameter can be one of the following values: + * @arg RAMCFG_IT_PARITYERR : Parity Error Interrupt Mask. + * @retval None + */ +#define __HAL_RAMCFG_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__)) + +/** + * @brief Check whether the specified RAMCFG interrupt source is enabled or not. + * @param __HANDLE__ : Specifies the RAMCFG Handle. + * @param __INTERRUPT__ : Specifies the RAMCFG interrupt source to check. + * This parameter can be one of the following values: + * @arg RAMCFG_IT_PARITYERR : Parity Error Interrupt Mask. + * @arg RAMCFG_IT_NMIERR : Parity Error Interrupt redirection to NMI Mask. + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_RAMCFG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER\ + & (__INTERRUPT__)) == (__INTERRUPT__)) ? 1U : 0U) + +/** + * @brief Get the RAMCFG pending flags. + * @param __HANDLE__ : Specifies RAMCFG handle. + * @param __FLAG__ : Specifies the flag to be checked. + * This parameter can be one of the following values: + * @arg RAMCFG_FLAG_PARITYERR : Parity Error Detected Flag. + * @arg RAMCFG_FLAG_SRAMBUSY : SRAM Busy Flag. + * @retval The state of FLAG (SET or RESET). + */ +#define __HAL_RAMCFG_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->ISR, (__FLAG__)) == (__FLAG__)) + +/** + * @brief Clear the RAMCFG pending flags. + * @param __HANDLE__ : Specifies RAMCFG handle. + * @param __FLAG__ : Specifies the flag to be cleared. + * This parameter can be any combination of the following values: + * @arg RAMCFG_FLAG_PARITYERR : Parity Error Detected and Flag. + * @retval None. + */ +#define __HAL_RAMCFG_CLEAR_FLAG(__HANDLE__, __FLAG__) (WRITE_REG((__HANDLE__)->Instance->ICR, (__FLAG__))) + +/** @brief Reset the RAMCFG handle state. + * @param __HANDLE__ : Specifies the RAMCFG Handle. + * @retval None. + */ +#if (USE_HAL_RAMCFG_REGISTER_CALLBACKS == 1) +#define __HAL_RAMCFG_RESET_HANDLE_STATE(__HANDLE__) do{\ + (__HANDLE__)->State = HAL_RAMCFG_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + }while(0) +#else +#define __HAL_RAMCFG_RESET_HANDLE_STATE(__HANDLE__) do{\ + (__HANDLE__)->State = HAL_RAMCFG_STATE_RESET; \ + }while(0) +#endif /* USE_HAL_RAMCFG_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup RAMCFG_Exported_Functions RAMCFG Exported Functions + * @brief RAMCFG Exported Functions + * @{ + */ + +/** @defgroup RAMCFG_Exported_Functions_Group1 Initialization and De-Initialization Functions + * @brief Initialization and De-Initialization Functions + * @{ + */ +HAL_StatusTypeDef HAL_RAMCFG_Init(RAMCFG_HandleTypeDef *hramcfg); +HAL_StatusTypeDef HAL_RAMCFG_DeInit(RAMCFG_HandleTypeDef *hramcfg); +void HAL_RAMCFG_MspInit(RAMCFG_HandleTypeDef *hramcfg); +void HAL_RAMCFG_MspDeInit(RAMCFG_HandleTypeDef *hramcfg); +/** + * @} + */ + +/** @defgroup RAMCFG_Exported_Functions_Group2 Parity Error Detection Functions + * @brief Parity Error Detection Functions + * @{ + */ +HAL_StatusTypeDef HAL_RAMCFG_LatchParityErrorAddress(RAMCFG_HandleTypeDef *hramcfg); +HAL_StatusTypeDef HAL_RAMCFG_UnlatchParityErrorAddress(RAMCFG_HandleTypeDef *hramcfg); +HAL_StatusTypeDef HAL_RAMCFG_EnableNotification(RAMCFG_HandleTypeDef *hramcfg, uint32_t Notifications); +HAL_StatusTypeDef HAL_RAMCFG_DisableNotification(RAMCFG_HandleTypeDef *hramcfg, uint32_t Notifications); +uint32_t HAL_RAMCFG_IsParityErrorDetected(const RAMCFG_HandleTypeDef *hramcfg); +HAL_StatusTypeDef HAL_RAMCFG_GetParityErrorAddress(const RAMCFG_HandleTypeDef *hramcfg, RAMCFG_PEAddressTypeDef *sPEAddress); +/** + * @} + */ + +/** @defgroup RAMCFG_Exported_Functions_Group3 Configure Wait State Functions + * @brief Configure Wait State Functions + * @{ + */ +HAL_StatusTypeDef HAL_RAMCFG_ConfigWaitState(RAMCFG_HandleTypeDef *hramcfg, uint32_t WaitState); +uint32_t HAL_RAMCFG_GetWaitState(const RAMCFG_HandleTypeDef *hramcfg); +/** + * @} + */ + +/** @defgroup RAMCFG_Exported_Functions_Group4 Write Protection Functions + * @brief Write Protection Functions + * @{ + */ +HAL_StatusTypeDef HAL_RAMCFG_EnableWriteProtection(RAMCFG_HandleTypeDef *hramcfg, uint32_t StartPage, uint32_t NbPage); +/** + * @} + */ + +/** @defgroup RAMCFG_Exported_Functions_Group5 Erase Operation Functions + * @brief Erase Operation Functions + * @{ + */ +HAL_StatusTypeDef HAL_RAMCFG_Erase(RAMCFG_HandleTypeDef *hramcfg); +/** + * @} + */ + +/** @defgroup RAMCFG_Exported_Functions_Group6 Handle Interrupt and Callbacks Functions + * @brief Handle Interrupt and Callbacks Functions + * @{ + */ +void HAL_RAMCFG_IRQHandler(RAMCFG_HandleTypeDef *hramcfg); +void HAL_RAMCFG_DetectParityErrorCallback(RAMCFG_HandleTypeDef *hramcfg); +#if (USE_HAL_RAMCFG_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_RAMCFG_RegisterCallback(RAMCFG_HandleTypeDef *hramcfg, + HAL_RAMCFG_CallbackIDTypeDef CallbackID, + void (* pCallback)(RAMCFG_HandleTypeDef *_hramcfg)); +HAL_StatusTypeDef HAL_RAMCFG_UnRegisterCallback(RAMCFG_HandleTypeDef *hramcfg, HAL_RAMCFG_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_RAMCFG_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup RAMCFG_Exported_Functions_Group7 State and Error Functions + * @brief State and Error Functions + * @{ + */ +uint32_t HAL_RAMCFG_GetError(const RAMCFG_HandleTypeDef *hramcfg); +HAL_RAMCFG_StateTypeDef HAL_RAMCFG_GetState(const RAMCFG_HandleTypeDef *hramcfg); +/** + * @} + */ + +/** + * @} + */ + +/* Private Constants ---------------------------------------------------------*/ + +/** @defgroup RAMCFG_Private_Constants RAMCFG Private Defines and Constants + * @brief RAMCFG Private Defines and Constants + * @{ + */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ + +/** @defgroup RAMCFG_Private_Macros RAMCFG Private Macros + * @brief RAMCFG Private Macros + * @{ + */ +#define IS_RAMCFG_INTERRUPT(INTERRUPT) (((INTERRUPT) != 0U) &&\ + (((INTERRUPT) & ~(RAMCFG_IT_PARITYERR | RAMCFG_IT_NMIERR)) == 0U)) + +#define IS_RAMCFG_WAITSTATE(WAITSTATE) (((WAITSTATE) == RAMCFG_WAITSTATE_0) || ((WAITSTATE) == RAMCFG_WAITSTATE_1) || \ + ((WAITSTATE) == RAMCFG_WAITSTATE_2) || ((WAITSTATE) == RAMCFG_WAITSTATE_3) || \ + ((WAITSTATE) == RAMCFG_WAITSTATE_4) || ((WAITSTATE) == RAMCFG_WAITSTATE_5) || \ + ((WAITSTATE) == RAMCFG_WAITSTATE_6) || ((WAITSTATE) == RAMCFG_WAITSTATE_7)) + +#define IS_RAMCFG_WRITEPROTECTION_PAGE(PAGE) ((PAGE) <= 64U) + + + +/** + * @} + */ + + + + + +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup RAMCFG_Private_Functions RAMCFG Private Functions + * @brief RAMCFG Private Functions + * @{ + */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32WBAxx_HAL_RAMCFG_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rcc.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rcc.h new file mode 100644 index 0000000000..3b9bb50e29 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rcc.h @@ -0,0 +1,2385 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_rcc.h + * @author MCD Application Team + * @brief Header file of RCC HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32WBAxx_HAL_RCC_H +#define __STM32WBAxx_HAL_RCC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal_def.h" +#include "stm32wbaxx_ll_rcc.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @addtogroup RCC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup RCC_Exported_Types RCC Exported Types + * @{ + */ + +/** + * @brief RCC PLL1 configuration structure definition + */ +typedef struct +{ + uint32_t PLLState; /*!< The new state of the PLL1. + This parameter can be a value of @ref RCC_PLL_Config */ + + uint32_t PLLSource; /*!< RCC_PLLSource: PLL1 entry clock source. + This parameter must be a value of @ref RCC_PLL_Clock_Source */ + + uint32_t PLLM; /*!< PLLM: Division factor for PLL1 VCO input clock. + This parameter must be a number between Min_Data = 1 and Max_Data = 8 */ + + uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL1 VCO output clock. + This parameter must be a number between Min_Data = 4 and Max_Data = 512 */ + + uint32_t PLLP; /*!< PLLP: Division factor for system clock. + This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ + + uint32_t PLLQ; /*!< PLLQ: Division factor for peripheral clocks. + This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ + + uint32_t PLLR; /*!< PLLR: Division factor for peripheral clocks. + This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ + + uint32_t PLLFractional; /*!< PLLFRACN: Specifies Fractional Part Of The Multiplication Factor for + PLL1 VCO It should be a value between 0 and 0x1FFF */ + +} RCC_PLLInitTypeDef; + +/** + * @brief RCC Internal/External Oscillator (HSE, HSI, MSI, LSE and LSI1) configuration structure definition + */ +typedef struct +{ + uint32_t OscillatorType; /*!< The oscillators to be configured. + This parameter can be a value of @ref RCC_Oscillator_Type */ + + uint32_t HSEState; /*!< The new state of the HSE. + This parameter can be a value of @ref RCC_HSE_Config */ + + uint32_t HSEDiv; /*!< The division factor of the HSE. Applicable only to SYSCLK when HSE is source. + This parameter can be a value of @ref RCC_HSE_Div */ + + uint32_t LSEState; /*!< The new state of the LSE. + This parameter can be a value of @ref RCC_LSE_Config */ + + uint32_t HSIState; /*!< The new state of the HSI. + This parameter can be a value of @ref RCC_HSI_Config */ + + uint32_t HSICalibrationValue; /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F + on the other devices */ + + uint32_t LSIState; /*!< The new state of the LSI (LSI1 or LSI2 when applicable). + This parameter can be a value of @ref RCC_LSI_Config */ + + uint32_t LSIDiv; /*!< The division factor of the LSI. Applicable only to LSI1. + This parameter can be a value of @ref RCC_LSI_Div */ + + RCC_PLLInitTypeDef PLL1; /*!< Main PLL1 structure parameters */ + +} RCC_OscInitTypeDef; + +/** + * @brief RCC System, AHB and APB busses clock configuration structure definition + */ +typedef struct +{ + uint32_t ClockType; /*!< The clock to be configured. + This parameter can be a value of @ref RCC_System_Clock_Type */ + + uint32_t SYSCLKSource; /*!< The clock source used as system clock (SYSCLK). + This parameter can be a value of @ref RCC_System_Clock_Source */ + + uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). + This parameter can be a value of @ref RCC_AHB_Clock_Source */ + + uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_APB1_APB2_APB7_Clock_Source */ + + uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_APB1_APB2_APB7_Clock_Source */ + + uint32_t APB7CLKDivider; /*!< The APB7 clock (PCLK7) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_APB1_APB2_APB7_Clock_Source */ + + uint32_t AHB5_PLL1_CLKDivider; /*!< The AHB5 clock (HCLK5) divider when PLL1 is source of SYSCLK. This clock is derived from the system clock (SYSCLK). + This parameter can be a value of @ref RCC_AHB5_PLL1_Clock_Source */ + + uint32_t AHB5_HSEHSI_CLKDivider; /*!< The AHB5 clock (HCLK5) divider when HSI or HSE are sources of SYSCLK. This clock is derived from the system clock (SYSCLK). + This parameter can be a value of @ref RCC_AHB5_HSEHSI_Clock_Source */ + +} RCC_ClkInitTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RCC_Exported_Constants RCC Exported Constants + * @{ + */ + +/** @defgroup RCC_Peripheral_Memory_Mapping Peripheral Memory Mapping + * @{ + */ + +/** + * @} + */ + +/** @defgroup RCC_Timeout_Value Timeout Values + * @{ + */ +#define RCC_DBP_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ +#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT +/** + * @} + */ + +/** @defgroup RCC_Oscillator_Type Oscillator Type + * @{ + */ +#define RCC_OSCILLATORTYPE_NONE 0x00000000U /*!< Oscillator configuration unchanged */ +#define RCC_OSCILLATORTYPE_HSE 0x00000001U /*!< HSE32 to configure */ +#define RCC_OSCILLATORTYPE_HSI 0x00000002U /*!< HSI16 to configure */ +#define RCC_OSCILLATORTYPE_LSE 0x00000004U /*!< LSE to configure */ +#define RCC_OSCILLATORTYPE_LSI 0x00000008U /*!< LSI to configure */ +/** + * @} + */ + +/** @defgroup RCC_HSE_Config HSE Config + * @{ + */ +#define RCC_HSE_OFF 0x00000000U /*!< HSE clock deactivation */ +#define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */ +/** + * @} + */ + +/** @defgroup RCC_HSE_Div HSE Div + * @{ + */ +#define RCC_HSE_DIV1 0x00000000U /*!< HSE clock divided by 1 for SYSCLK */ +#define RCC_HSE_DIV2 RCC_CR_HSEPRE /*!< HSE clock divided by 2 for SYSCLK */ +/** + * @} + */ + +/** @defgroup RCC_LSE_Config LSE Config + * @{ + */ +#define RCC_LSE_OFF 0U /*!< LSE clock deactivation */ +#define RCC_LSE_ON_RTC_ONLY RCC_BDCR1_LSEON /*!< LSE clock activation for RTC only */ +#define RCC_LSE_ON (RCC_BDCR1_LSESYSEN | RCC_BDCR1_LSEON) /*!< LSE clock activation for RCC and peripherals */ +#define RCC_LSE_BYPASS_RTC_ONLY (RCC_BDCR1_LSEBYP | RCC_BDCR1_LSEON) /*!< External clock source for LSE clock */ +#define RCC_LSE_BYPASS (RCC_BDCR1_LSEBYP | RCC_BDCR1_LSESYSEN | RCC_BDCR1_LSEON) /*!< External clock source for LSE clock */ +/** + * @} + */ + +/** @defgroup RCC_HSI_Config HSI Config + * @{ + */ +#define RCC_HSI_OFF 0x00000000U /*!< HSI clock deactivation */ +#define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ + +#define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */ +/** + * @} + */ + +/** @defgroup RCC_LSI_Config LSI Config + * @{ + */ +#define RCC_LSI_OFF 0x00000000U /*!< LSI clock deactivation */ +#define RCC_LSI1_ON RCC_BDCR1_LSI1ON /*!< LSI1 clock activation */ +#if defined(RCC_LSI2_SUPPORT) +#define RCC_LSI2_ON RCC_BDCR1_LSI2ON /*!< LSI2 clock activation */ +#endif +/** + * @} + */ + +/** @defgroup RCC_LSI_Div LSI Div + * @{ + */ +#define RCC_LSI_DIV1 0U /*!< LSI1 clock is not divided */ +#define RCC_LSI_DIV128 RCC_BDCR1_LSI1PREDIV /*!< LSI1 clock is divided by 128 */ +/** + * @} + */ + +/** @defgroup RCC_PLL_Config RCC PLL1 Config + * @{ + */ +#define RCC_PLL_NONE 0x00000000U +#define RCC_PLL_OFF 0x00000001U +#define RCC_PLL_ON 0x00000002U +/** + * @} + */ + +/** @defgroup RCC_PLL_Clock_Source RCC PLL1 Clock Source + * @{ + */ +#define RCC_PLLSOURCE_NONE 0x00000000U +#define RCC_PLLSOURCE_HSI RCC_PLL1CFGR_PLL1SRC_1 +#define RCC_PLLSOURCE_HSE (RCC_PLL1CFGR_PLL1SRC_1 | RCC_PLL1CFGR_PLL1SRC_0) +/** + * @} + */ + +/** @defgroup RCC_PLL_Clock_Output RCC PLL1 Clock Output + * @{ + */ +#define RCC_PLL1_PCLK RCC_PLL1CFGR_PLL1PEN +#define RCC_PLL1_QCLK RCC_PLL1CFGR_PLL1QEN +#define RCC_PLL1_RCLK RCC_PLL1CFGR_PLL1REN +/** + * @} + */ + +/** @defgroup RCC_PLL_VCO_Input_Range RCC PLL1 VCO Input Range + * @{ + */ +#define RCC_PLL_VCOINPUT_RANGE0 0x00000000U +#define RCC_PLL_VCOINPUT_RANGE1 (RCC_PLL1CFGR_PLL1RGE_1 | RCC_PLL1CFGR_PLL1RGE_0) +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Type System Clock Type + * @{ + */ +#define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure */ +#define RCC_CLOCKTYPE_HCLK 0x00000002U /*!< HCLK to configure */ +#define RCC_CLOCKTYPE_PCLK1 0x00000004U /*!< PCLK1 to configure */ +#define RCC_CLOCKTYPE_PCLK2 0x00000008U /*!< PCLK2 to configure */ +#define RCC_CLOCKTYPE_PCLK7 0x00000010U /*!< PCLK7 to configure */ +#define RCC_CLOCKTYPE_HCLK5 0x00000020U /*!< HCLK5 to configure */ +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Source System Clock Source + * @{ + */ +#define RCC_SYSCLKSOURCE_HSI 0x00000000U /*!< HSI16 selection as system clock */ +#define RCC_SYSCLKSOURCE_HSE RCC_CFGR1_SW_1 /*!< HSE32 or HSE32/32 (depending on HSEPRE) selection as system clock */ +#define RCC_SYSCLKSOURCE_PLLCLK (RCC_CFGR1_SW_1 | RCC_CFGR1_SW_0) /*!< PLL1R selection as system clock */ +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status + * @{ + */ +#define RCC_SYSCLKSOURCE_STATUS_HSI 0x00000000U /*!< HSI16 used as system clock */ +#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR1_SWS_1 /*!< HSE32 or HSE32/32 (depending on HSEPRE) used as system clock */ +#define RCC_SYSCLKSOURCE_STATUS_PLLCLK (RCC_CFGR1_SWS_1 | RCC_CFGR1_SWS_0) /*!< PLL1R used as system clock */ +/** + * @} + */ + +/** @defgroup RCC_AHB_Clock_Source AHB Clock Source + * @{ + */ +#define RCC_SYSCLK_DIV1 0x00000000U /*!< SYSCLK not divided */ +#define RCC_SYSCLK_DIV2 RCC_CFGR2_HPRE_2 /*!< SYSCLK divided by 2 */ +#define RCC_SYSCLK_DIV4 (RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_0) /*!< SYSCLK divided by 4 */ +#define RCC_SYSCLK_DIV8 (RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_1) /*!< SYSCLK divided by 8 */ +#define RCC_SYSCLK_DIV16 (RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_0) /*!< SYSCLK divided by 16 */ +/** + * @} + */ + +/** @defgroup RCC_APB1_APB2_APB7_Clock_Source APB1 APB2 APB7 Clock Source + * @{ + */ +#define RCC_HCLK_DIV1 (0x00000000U) /*!< HCLK not divided */ +#define RCC_HCLK_DIV2 RCC_CFGR2_PPRE1_2 /*!< HCLK divided by 2 */ +#define RCC_HCLK_DIV4 (RCC_CFGR2_PPRE1_2 | RCC_CFGR2_PPRE1_0) /*!< HCLK divided by 4 */ +#define RCC_HCLK_DIV8 (RCC_CFGR2_PPRE1_2 | RCC_CFGR2_PPRE1_1) /*!< HCLK divided by 8 */ +#define RCC_HCLK_DIV16 (RCC_CFGR2_PPRE1_2 | RCC_CFGR2_PPRE1_1 | RCC_CFGR2_PPRE1_0) /*!< HCLK divided by 16 */ +/** + * @} + */ + +/** @defgroup RCC_AHB5_PLL1_Clock_Source AHB5 PLL1 Clock Source + * @{ + */ +#define RCC_SYSCLK_PLL1_DIV1 0x00000000U /*!< SYSCLK when PLL1 is source not divided */ +#define RCC_SYSCLK_PLL1_DIV2 RCC_CFGR4_HPRE5_2 /*!< SYSCLK when PLL1 is source divided by 2 */ +#define RCC_SYSCLK_PLL1_DIV3 (RCC_CFGR4_HPRE5_2 | RCC_CFGR4_HPRE5_0) /*!< SYSCLK when PLL1 is source divided by 3 */ +#define RCC_SYSCLK_PLL1_DIV4 (RCC_CFGR4_HPRE5_2 | RCC_CFGR4_HPRE5_1) /*!< SYSCLK when PLL1 is source divided by 4 */ +#define RCC_SYSCLK_PLL1_DIV6 (RCC_CFGR4_HPRE5_2 | RCC_CFGR4_HPRE5_1 | RCC_CFGR4_HPRE5_0) /*!< SYSCLK when PLL1 is source divided by 6 */ +/** + * @} + */ + +/** @defgroup RCC_AHB5_HSEHSI_Clock_Source AHB5 HSEHSI Clock Source + * @{ + */ +#define RCC_SYSCLK_HSEHSI_DIV1 0x00000000U /*!< SYSCLK when HSE or HSI is source not divided */ +#define RCC_SYSCLK_HSEHSI_DIV2 RCC_CFGR4_HDIV5 /*!< SYSCLK when HSE or HSI is source divided by 2 */ +/** + * @} + */ + +/** @defgroup RCC_RTC_Clock_Source RTC Clock Source + * @{ + */ +#define RCC_RTCCLKSOURCE_DISABLE 0x00000000U /*!< RTC clock is disabled */ +#define RCC_RTCCLKSOURCE_LSE RCC_BDCR1_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ +#define RCC_RTCCLKSOURCE_LSI RCC_BDCR1_RTCSEL_1 /*!< LSI1 or LIS2 oscillator clock used as RTC clock */ +#define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR1_RTCSEL /*!< HSE32 oscillator clock divided by 32 used as RTC clock */ +/** + * @} + */ + +/** @defgroup RCC_MCO_Index MCO Index + * @{ + */ +#define RCC_MCO1 0x00000000U +#define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/ +/** + * @} + */ + +/** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source + * @{ + */ +#define RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO1 output disabled, no clock on MCO1 */ +#define RCC_MCO1SOURCE_SYSCLK RCC_CFGR1_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */ +#define RCC_MCO1SOURCE_HSI (RCC_CFGR1_MCOSEL_1 | RCC_CFGR1_MCOSEL_0) /*!< HSI16 selection as MCO1 source */ +#define RCC_MCO1SOURCE_HSE RCC_CFGR1_MCOSEL_2 /*!< HSE32 selection as MCO1 source */ +#define RCC_MCO1SOURCE_PLL1RCLK (RCC_CFGR1_MCOSEL_2 | RCC_CFGR1_MCOSEL_0) /*!< PLL1RCLK selection as MCO1 source */ +#define RCC_MCO1SOURCE_LSI (RCC_CFGR1_MCOSEL_2 | RCC_CFGR1_MCOSEL_1) /*!< LSI selection as MCO1 source */ +#define RCC_MCO1SOURCE_LSE (RCC_CFGR1_MCOSEL_2 | RCC_CFGR1_MCOSEL_1 | RCC_CFGR1_MCOSEL_0) /*!< LSE selection as MCO1 source */ +#define RCC_MCO1SOURCE_PLL1PCLK RCC_CFGR1_MCOSEL_3 /*!< PLL1PCLK selection as MCO1 source */ +#define RCC_MCO1SOURCE_PLL1QCLK (RCC_CFGR1_MCOSEL_3 | RCC_CFGR1_MCOSEL_0) /*!< PLL1QCLK selection as MCO1 source */ +#define RCC_MCO1SOURCE_HCLK5 (RCC_CFGR1_MCOSEL_3 | RCC_CFGR1_MCOSEL_1) /*!< HCLK5 selection as MCO1 source */ +/** + * @} + */ + +/** @defgroup RCC_MCOx_Clock_Prescaler MCO1 Clock Prescaler + * @{ + */ +#define RCC_MCODIV_1 0x00000000U /*!< MCO is divided by 1 */ +#define RCC_MCODIV_2 RCC_CFGR1_MCOPRE_0 /*!< MCO is divided by 2 */ +#define RCC_MCODIV_4 RCC_CFGR1_MCOPRE_1 /*!< MCO is divided by 4 */ +#define RCC_MCODIV_8 (RCC_CFGR1_MCOPRE_1 | RCC_CFGR1_MCOPRE_0) /*!< MCO is divided by 8 */ +#define RCC_MCODIV_16 RCC_CFGR1_MCOPRE_2 /*!< MCO is divided by 16 */ +/** + * @} + */ + +/** @defgroup RCC_Interrupt Interrupts + * @{ + */ +#define RCC_IT_LSI1RDY RCC_CIFR_LSI1RDYF /*!< LSI1 Ready Interrupt flag */ +#define RCC_IT_LSERDY RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */ +#define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF /*!< HSI16 Ready Interrupt flag */ +#define RCC_IT_HSERDY RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */ +#define RCC_IT_PLL1RDY RCC_CIFR_PLL1RDYF /*!< PLL1 Ready Interrupt flag */ +#define RCC_IT_CSS RCC_CIFR_HSECSSF /*!< HSE32 Clock Security System Interrupt flag */ +#if defined(RCC_LSI2_SUPPORT) +#define RCC_IT_LSI2RDY RCC_CIFR_LSI2RDYF /*!< LSI2 Ready Interrupt flag */ +#endif /* RCC_BDCR1_LSI2ON */ +/** + * @} + */ + +/** @defgroup RCC_Flag Flags + * Elements values convention: XXXYYYYYb + * - YYYYY : Flag position in the register + * - XXX : Register index + * - 001: CR register + * - 010: BDCR1 register + * - 011: CSR register + * @{ + */ +/* Flags in the CR register */ +#define RCC_FLAG_HSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos) /*!< HSI Ready flag */ +#define RCC_FLAG_HSERDY ((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos) /*!< HSE Ready flag */ +#define RCC_FLAG_PLL1RDY ((CR_REG_INDEX << 5U) | RCC_CR_PLL1RDY_Pos) /*!< PLL1 Ready flag */ + +/* Flags in the BDCR1 register */ +#define RCC_FLAG_LSERDY ((BDCR1_REG_INDEX << 5U) | RCC_BDCR1_LSERDY_Pos) /*!< LSE Ready flag */ +#define RCC_FLAG_LSESYSRDY ((BDCR1_REG_INDEX << 5U) | RCC_BDCR1_LSESYSRDY_Pos) /*!< LSESYS Ready flag */ +#define RCC_FLAG_LSECSSD ((BDCR1_REG_INDEX << 5U) | RCC_BDCR1_LSECSSD_Pos) /*!< LSE Clock Security System Interrupt flag */ +#define RCC_FLAG_LSI1RDY ((BDCR1_REG_INDEX << 5U) | RCC_BDCR1_LSI1RDY_Pos) /*!< LSI1 Ready flag */ +#if defined(RCC_LSI2_SUPPORT) +#define RCC_FLAG_LSI2RDY ((BDCR1_REG_INDEX << 5U) | RCC_BDCR1_LSI2RDY_Pos) /*!< LSI2 Ready flag */ +#endif /* RCC_BDCR1_LSI2ON */ + +/* Flags in the CSR register */ +#define RCC_FLAG_OBLRST ((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos) /*!< Option Byte Loader reset flag */ +#define RCC_FLAG_PINRST ((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos) /*!< PIN reset flag */ +#define RCC_FLAG_BORRST ((CSR_REG_INDEX << 5U) | RCC_CSR_BORRSTF_Pos) /*!< BOR reset flag */ +#define RCC_FLAG_SFTRST ((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos) /*!< Software Reset flag */ +#define RCC_FLAG_IWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos) /*!< Independent Watchdog reset flag */ +#define RCC_FLAG_WWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos) /*!< Window watchdog reset flag */ +#define RCC_FLAG_LPWRRST ((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos) /*!< Low-Power reset flag */ +/** + * @} + */ + +/** @defgroup RCC_LSEDrive_Config LSE Drive Config + * @{ + */ +#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR1_LSEDRV_0 /*!< LSE medium low drive capability */ +#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR1_LSEDRV_1 /*!< LSE medium high drive capability */ +#define RCC_LSEDRIVE_HIGH RCC_BDCR1_LSEDRV /*!< LSE high drive capability */ +/** + * @} + */ + +/** @defgroup RCC_Reset_Flag Reset Flag + * @{ + */ +#define RCC_RESET_FLAG_OBL RCC_CSR_OBLRSTF /*!< Option Byte Loader reset flag */ +#define RCC_RESET_FLAG_PIN RCC_CSR_PINRSTF /*!< PIN reset flag */ +#define RCC_RESET_FLAG_PWR RCC_CSR_BORRSTF /*!< BOR or POR/PDR reset flag */ +#define RCC_RESET_FLAG_SW RCC_CSR_SFTRSTF /*!< Software Reset flag */ +#define RCC_RESET_FLAG_IWDG RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */ +#define RCC_RESET_FLAG_WWDG RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */ +#define RCC_RESET_FLAG_LPWR RCC_CSR_LPWRRSTF /*!< Low power reset flag */ +#define RCC_RESET_FLAG_ALL (RCC_RESET_FLAG_OBL | RCC_RESET_FLAG_PIN | RCC_RESET_FLAG_PWR | \ + RCC_RESET_FLAG_SW | RCC_RESET_FLAG_IWDG | RCC_RESET_FLAG_WWDG | \ + RCC_RESET_FLAG_LPWR) +/** + * @} + */ + +/** @defgroup RCC_items RCC items + * @brief RCC items to configure attributes on + * @{ + */ +#define RCC_HSI RCC_SECCFGR_HSISEC +#define RCC_HSE RCC_SECCFGR_HSESEC +#define RCC_LSI RCC_SECCFGR_LSISEC +#define RCC_LSE RCC_SECCFGR_LSESEC +#define RCC_SYSCLK RCC_SECCFGR_SYSCLKSEC +#define RCC_PRESC RCC_SECCFGR_PRESCSEC +#define RCC_PLL1 RCC_SECCFGR_PLL1SEC +#define RCC_RMVF RCC_SECCFGR_RMVFSEC +#define RCC_ALL (RCC_HSI|RCC_HSE|RCC_LSI|RCC_LSE|RCC_SYSCLK| \ + RCC_PRESC|RCC_PLL1|RCC_RMVF) +/** + * @} + */ + +/** @defgroup RCC_attributes RCC attributes + * @brief RCC privilege/non-privilege and secure/non-secure attributes + * @{ + */ +#define RCC_NSEC_PRIV 0x00000001U /*!< Non-secure Privilege attribute item */ +#define RCC_NSEC_NPRIV 0x00000002U /*!< Non-secure Non-privilege attribute item */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define RCC_SEC_PRIV 0x00000010U /*!< Secure Privilege attribute item */ +#define RCC_SEC_NPRIV 0x00000020U /*!< Secure Non-privilege attribute item */ +#endif +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Macros RCC Exported Macros + * @{ + */ + +/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable + * @brief Enable or disable the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_GPDMA1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_FLASH_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_CRC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TSC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_RAMCFG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN); \ + UNUSED(tmpreg); \ + } while(0) + +#if defined(GTZC_TZSC) +#define __HAL_RCC_GTZC1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZC1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZC1EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* GTZC_TZSC */ + +#define __HAL_RCC_SRAM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPDMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN) +#define __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) +#define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) +#define __HAL_RCC_TSC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) +#define __HAL_RCC_RAMCFG_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN) +#if defined(GTZC_TZSC) +#define __HAL_RCC_GTZC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZC1EN) +#endif +#define __HAL_RCC_SRAM1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN) + +/** + * @} + */ + +/** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable + * @brief Enable or disable the AHB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \ + UNUSED(tmpreg); \ + } while(0) + + +#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \ + UNUSED(tmpreg); \ + } while(0) + + +#define __HAL_RCC_AES_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_HASH_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_RNG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \ + UNUSED(tmpreg); \ + } while(0) + +#if defined(SAES) +#define __HAL_RCC_SAES_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SAESEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SAESEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* SAES */ + +#define __HAL_RCC_HSEM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HSEMEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HSEMEN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_PKA_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SRAM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM2EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) +#define __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) +#define __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) +#define __HAL_RCC_GPIOH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) +#define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) +#define __HAL_RCC_HASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) +#define __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) +#if defined(SAES) +#define __HAL_RCC_SAES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SAESEN) +#endif +#define __HAL_RCC_HSEM_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HSEMEN) +#define __HAL_RCC_PKA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN) +#define __HAL_RCC_SRAM2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM2EN) +/** + * @} + */ + +/** @defgroup RCC_AHB4_Clock_Enable_Disable AHB4ENR Peripheral Clock Enable Disable + * @brief Enable or disable the AHB4ENR peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_PWR_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_PWREN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_PWREN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_ADC4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_ADC4EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_ADC4EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_PWREN) +#define __HAL_RCC_ADC4_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_ADC4EN) +/** + * @} + */ + +/** @defgroup RCC_AHB5_Clock_Enable_Disable AHB5ENR Peripheral Clock Enable Disable + * @brief Enable or disable the AHB5ENR peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_RADIO_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB5ENR, RCC_AHB5ENR_RADIOEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB5ENR, RCC_AHB5ENR_RADIOEN); \ + UNUSED(tmpreg); \ + } while(0) + +#if defined(PTACONV) +#define __HAL_RCC_PTACONV_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB5ENR, RCC_AHB5ENR_PTACONVEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB5ENR, RCC_AHB5ENR_PTACONVEN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* PTACONV */ + +#define __HAL_RCC_RADIO_CLK_DISABLE() CLEAR_BIT(RCC->AHB5ENR, RCC_AHB5ENR_RADIOEN) + +#if defined(PTACONV) +#define __HAL_RCC_PTACONV_CLK_DISABLE() CLEAR_BIT(RCC->AHB5ENR, RCC_AHB5ENR_PTACONVEN) +#endif +/** + * @} + */ + +/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable + * @brief Enable or disable the APB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +#define __HAL_RCC_TIM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \ + UNUSED(tmpreg); \ + } while(0) + +#if defined(TIM3) +#define __HAL_RCC_TIM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* TIM3 */ + + +#define __HAL_RCC_WWDG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \ + UNUSED(tmpreg); \ + } while(0) + + +#if defined(USART2) +#define __HAL_RCC_USART2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* USART2 */ + + +#if defined(I2C1) +#define __HAL_RCC_I2C1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* I2C1 */ + + + +#if defined(LPTIM2) +#define __HAL_RCC_LPTIM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* LPTIM2 */ + +#define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) +#if defined(TIM3) +#define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) +#endif +#if defined(USART2) +#define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) +#endif +#if defined(I2C1) +#define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) +#endif +#if defined(LPTIM2) +#define __HAL_RCC_LPTIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) +#endif +/** + * @} + */ + +/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable + * @brief Enable or disable the APB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_TIM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ + UNUSED(tmpreg); \ + } while(0) + +#if defined(SPI1) +#define __HAL_RCC_SPI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* SPI1 */ + +#define __HAL_RCC_USART1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM16_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ + UNUSED(tmpreg); \ + } while(0) + +#if defined(TIM17) +#define __HAL_RCC_TIM17_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* TIM17 */ + +#if defined(SAI1) +#define __HAL_RCC_SAI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \ + UNUSED(tmpreg); \ + } while(0) +#endif /* SAI1 */ + +#define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) +#if defined(SPI1) +#define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) +#endif +#define __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) +#define __HAL_RCC_TIM16_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) +#if defined(TIM17) +#define __HAL_RCC_TIM17_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) +#endif +#if defined(SAI1) +#define __HAL_RCC_SAI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) +#endif +/** + * @} + */ + +/** @defgroup RCC_APB7_Clock_Enable_Disable APB7 Peripheral Clock Enable Disable + * @brief Enable or disable the APB7 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB7ENR, RCC_APB7ENR_SYSCFGEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB7ENR, RCC_APB7ENR_SYSCFGEN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SPI3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB7ENR, RCC_APB7ENR_SPI3EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB7ENR, RCC_APB7ENR_SPI3EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_LPUART1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB7ENR, RCC_APB7ENR_LPUART1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB7ENR, RCC_APB7ENR_LPUART1EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_I2C3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB7ENR, RCC_APB7ENR_I2C3EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB7ENR, RCC_APB7ENR_I2C3EN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_COMP_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB7ENR, RCC_APB7ENR_COMPEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB7ENR, RCC_APB7ENR_COMPEN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB7ENR, RCC_APB7ENR_LPTIM1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB7ENR, RCC_APB7ENR_LPTIM1EN); \ + UNUSED(tmpreg); \ + } while(0) + + +#define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB7ENR, RCC_APB7ENR_RTCAPBEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB7ENR, RCC_APB7ENR_RTCAPBEN); \ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APB7ENR, RCC_APB7ENR_SYSCFGEN) +#define __HAL_RCC_SPI3_CLK_DISABLE() CLEAR_BIT(RCC->APB7ENR, RCC_APB7ENR_SPI3EN) +#define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB7ENR, RCC_APB7ENR_LPUART1EN) +#define __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APB7ENR, RCC_APB7ENR_I2C3EN) +#define __HAL_RCC_COMP_CLK_DISABLE() CLEAR_BIT(RCC->APB7ENR, RCC_APB7ENR_COMPEN) +#define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB7ENR, RCC_APB7ENR_LPTIM1EN) +#define __HAL_RCC_RTCAPB_CLK_DISABLE() CLEAR_BIT(RCC->APB7ENR, RCC_APB7ENR_RTCAPBEN) +/** + * @} + */ + +/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enabled or Disabled Status + * @brief Check whether the AHB1 peripheral clock is enabled or not. + * @{ + */ +#define __HAL_RCC_GPDMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN) != 0U) +#define __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != 0U) +#define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != 0U) +#define __HAL_RCC_TSC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) != 0U) +#define __HAL_RCC_RAMCFG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN) != 0U) +#if defined(GTZC_TZSC) +#define __HAL_RCC_GTZC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZC1EN) != 0U) +#endif +#define __HAL_RCC_SRAM1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN) != 0U) +/** + * @} + */ + +/** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enabled or Disabled Status + * @brief Check whether the AHB2 peripheral clock is enabled or not. + * @{ + */ +#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) != 0U) +#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) != 0U) +#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != 0U) +#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) != 0U) +#define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) != 0U) +#define __HAL_RCC_HASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN) != 0U) +#define __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) != 0U) +#if defined(SAES) +#define __HAL_RCC_SAES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SAESEN) != 0U) +#endif +#define __HAL_RCC_HSEM_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HSEMEN) != 0U) +#define __HAL_RCC_PKA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN) != 0U) +#define __HAL_RCC_SRAM2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SRAM2EN) != 0U) +/** + * @} + */ + +/** @defgroup RCC_AHB4_Peripheral_Clock_Enable_Disable_Status AHB4 Peripheral Clock Enabled or Disabled Status + * @brief Check whether the AHB4 peripheral clock is enabled or not. + * @{ + */ +#define __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_PWREN) != 0U) +#define __HAL_RCC_ADC4_IS_CLK_ENABLED() (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_ADC4EN) != 0U) +/** + * @} + */ + +/** @defgroup RCC_AHB5_Peripheral_Clock_Enable_Disable_Status AHB5 Peripheral Clock Enabled or Disabled Status + * @brief Check whether the AHB5 peripheral clock is enabled or not. + * @{ + */ +#define __HAL_RCC_RADIO_IS_CLK_ENABLED() (READ_BIT(RCC->AHB5ENR, RCC_AHB5ENR_RADIOEN) != 0U) +#if defined(PTACONV) +#define __HAL_RCC_PTACONV_IS_CLK_ENABLED() (READ_BIT(RCC->AHB5ENR, RCC_AHB5ENR_PTACONVEN) != 0U) +#endif +/** + * @} + */ + +/** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status + * @brief Check whether the APB1 peripheral clock is enabled or not. + * @{ + */ +#define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) != 0U) +#if defined(TIM3) +#define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) != 0U) +#endif +#define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) != 0U) +#if defined(USART2) +#define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) != 0U) +#endif +#if defined(I2C1) +#define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) != 0U) +#endif +#if defined(LPTIM2) +#define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) != 0U) +#endif +/** + * @} + */ + +/** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status + * @brief Check whether the APB2 peripheral clock is enabled or not. + * @{ + */ +#define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != 0U) +#if defined(SPI1) +#define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != 0U) +#endif +#define __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != 0U) +#define __HAL_RCC_TIM16_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) != 0U) +#if defined(TIM17) +#define __HAL_RCC_TIM17_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) != 0U) +#endif +#if defined(SAI1) +#define __HAL_RCC_SAI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != 0U) +#endif +/** + * @} + */ + +/** @defgroup RCC_APB7_Peripheral_Clock_Enable_Disable_Status APB7 Peripheral Clock Enabled or Disabled Status + * @brief Check whether the APB7 peripheral clock is enabled or not. + * @{ + */ +#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APB7ENR, RCC_APB7ENR_SYSCFGEN) != 0U) +#define __HAL_RCC_SPI3_IS_CLK_ENABLED() (READ_BIT(RCC->APB7ENR, RCC_APB7ENR_SPI3EN) != 0U) +#define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB7ENR, RCC_APB7ENR_LPUART1EN) != 0U) +#define __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APB7ENR, RCC_APB7ENR_I2C3EN) != 0U) +#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB7ENR, RCC_APB7ENR_LPTIM1EN) != 0U) +#define __HAL_RCC_COMP_IS_CLK_ENABLED() (READ_BIT(RCC->APB7ENR, RCC_APB7ENR_COMPEN) != 0U) +#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() (READ_BIT(RCC->APB7ENR, RCC_APB7ENR_RTCAPBEN) != 0U) +/** + * @} + */ + +/** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Peripheral Force Release Reset + * @brief Force or release AHB1 peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB1_FORCE_RESET() WRITE_REG(RCC->AHB1RSTR, 0xFFFFFFFFU) +#define __HAL_RCC_GPDMA1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPDMA1RST) +#define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST) +#define __HAL_RCC_TSC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST) + +#define __HAL_RCC_AHB1_RELEASE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x00000000U) +#define __HAL_RCC_GPDMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPDMA1RST) +#define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST) +#define __HAL_RCC_TSC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST) +/** + * @} + */ + +/** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Peripheral Force Release Reset + * @brief Force or release AHB2 peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB2_FORCE_RESET() WRITE_REG(RCC->AHB2RSTR, 0xFFFFFFFFU) +#define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST) +#define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST) +#define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST) +#define __HAL_RCC_GPIOH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST) +#define __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST) +#define __HAL_RCC_HASH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HASHRST) +#define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST) +#if defined(SAES) +#define __HAL_RCC_SAES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SAESRST) +#endif +#define __HAL_RCC_HSEM_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HSEMRST) +#define __HAL_RCC_PKA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_PKARST) + +#define __HAL_RCC_AHB2_RELEASE_RESET() WRITE_REG(RCC->AHB2RSTR, 0x00000000U) +#define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST) +#define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST) +#define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST) +#define __HAL_RCC_GPIOH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST) +#define __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST) +#define __HAL_RCC_HASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HASHRST) +#define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST) +#if defined(SAES) +#define __HAL_RCC_SAES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SAESRST) +#endif +#define __HAL_RCC_HSEM_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_HSEMRST) +#define __HAL_RCC_PKA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_PKARST) +/** + * @} + */ + +/** @defgroup RCC_AHB4_Force_Release_Reset AHB4 Peripheral Force Release Reset + * @brief Force or release AHB4 peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB4_FORCE_RESET() WRITE_REG(RCC->AHB4RSTR, 0xFFFFFFFFU) +#define __HAL_RCC_ADC4_FORCE_RESET() SET_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_ADC4RST) + +#define __HAL_RCC_AHB4_RELEASE_RESET() WRITE_REG(RCC->AHB4RSTR, 0x00000000U) +#define __HAL_RCC_ADC4_RELEASE_RESET() CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4RSTR_ADC4RST) +/** + * @} + */ + +/** @defgroup RCC_AHB5_Force_Release_Reset AHB5 Peripheral Force Release Reset + * @brief Force or release AHB5 peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB5_FORCE_RESET() WRITE_REG(RCC->AHB5RSTR, 0xFFFFFFFFU) +#define __HAL_RCC_RADIO_FORCE_RESET() SET_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_RADIORST) +#if defined(PTACONV) +#define __HAL_RCC_PTACONV_FORCE_RESET() SET_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_PTACONVRST) +#endif + +#define __HAL_RCC_AHB5_RELEASE_RESET() WRITE_REG(RCC->AHB5RSTR, 0x00000000U) +#define __HAL_RCC_RADIO_RELEASE_RESET() CLEAR_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_RADIORST) +#if defined(PTACONV) +#define __HAL_RCC_PTACONV_RELEASE_RESET() CLEAR_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_PTACONVRST) +#endif +/** + * @} + */ + +/** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset + * @brief Force or release APB1 peripheral reset. + * @{ + */ +#define __HAL_RCC_APB1_FORCE_RESET() do { \ + WRITE_REG(RCC->APB1RSTR1, 0xFFFFFFFFU); \ + WRITE_REG(RCC->APB1RSTR2, 0xFFFFFFFFU); \ + } while(0) +#define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST) +#if defined(TIM3) +#define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST) +#endif +#if defined(USART2) +#define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST) +#endif +#if defined(I2C1) +#define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST) +#endif +#if defined(LPTIM2) +#define __HAL_RCC_LPTIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST) +#endif + +#define __HAL_RCC_APB1_RELEASE_RESET() do { \ + WRITE_REG(RCC->APB1RSTR1, 0x00000000U); \ + WRITE_REG(RCC->APB1RSTR2, 0x00000000U); \ + } while(0) +#define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST) +#if defined(TIM3) +#define __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST) +#endif +#if defined(USART2) +#define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST) +#endif +#if defined(I2C1) +#define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST) +#endif +#if defined(LPTIM2) +#define __HAL_RCC_LPTIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST) +#endif +/** + * @} + */ + +/** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset + * @brief Force or release APB2 peripheral reset. + * @{ + */ +#define __HAL_RCC_APB2_FORCE_RESET() WRITE_REG(RCC->APB2RSTR, 0xFFFFFFFFU) +#define __HAL_RCC_TIM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST) +#if defined(SPI1) +#define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST) +#endif +#define __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST) +#define __HAL_RCC_TIM16_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST) +#if defined(TIM17) +#define __HAL_RCC_TIM17_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST) +#endif +#if defined(SAI1) +#define __HAL_RCC_SAI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) +#endif + +#define __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00000000U) +#define __HAL_RCC_TIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST) +#if defined(SPI1) +#define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST) +#endif +#define __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST) +#define __HAL_RCC_TIM16_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST) +#if defined(TIM17) +#define __HAL_RCC_TIM17_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST) +#endif +#if defined(SAI1) +#define __HAL_RCC_SAI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) +#endif +/** + * @} + */ + +/** @defgroup RCC_APB7_Force_Release_Reset APB7 Peripheral Force Release Reset + * @brief Force or release APB7 peripheral reset. + * @{ + */ +#define __HAL_RCC_APB7_FORCE_RESET() WRITE_REG(RCC->APB7RSTR, 0xFFFFFFFFU) +#define __HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APB7RSTR, RCC_APB7RSTR_SYSCFGRST) +#define __HAL_RCC_SPI3_FORCE_RESET() SET_BIT(RCC->APB7RSTR, RCC_APB7RSTR_SPI3RST) +#define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB7RSTR, RCC_APB7RSTR_LPUART1RST) +#define __HAL_RCC_I2C3_FORCE_RESET() SET_BIT(RCC->APB7RSTR, RCC_APB7RSTR_I2C3RST) +#define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB7RSTR, RCC_APB7RSTR_LPTIM1RST) +#define __HAL_RCC_COMP_FORCE_RESET() SET_BIT(RCC->APB7RSTR, RCC_APB7RSTR_COMPRST) + +#define __HAL_RCC_APB7_RELEASE_RESET() WRITE_REG(RCC->APB7RSTR, 0x00000000U) +#define __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APB7RSTR, RCC_APB7RSTR_SYSCFGRST) +#define __HAL_RCC_SPI3_RELEASE_RESET() CLEAR_BIT(RCC->APB7RSTR, RCC_APB7RSTR_SPI3RST) +#define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB7RSTR, RCC_APB7RSTR_LPUART1RST) +#define __HAL_RCC_I2C3_RELEASE_RESET() CLEAR_BIT(RCC->APB7RSTR, RCC_APB7RSTR_I2C3RST) +#define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB7RSTR, RCC_APB7RSTR_LPTIM1RST) +#define __HAL_RCC_COMP_RELEASE_RESET() CLEAR_BIT(RCC->APB7RSTR, RCC_APB7RSTR_COMPRST) +/** + * @} + */ + +/** @defgroup RCC_AHB1_Peripheral_Clock_Sleep_Enable_Disable AHB1 Peripheral Clock Sleep Enable Disable + * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep and Stop) mode. + * @note Peripheral clock gating in SLEEP and STOP modes can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP or STOP modes, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode,in STOP mode peripheral clock + * is enabled only when a peripheral requests AHB clock. + * @{ + */ +#define __HAL_RCC_GPDMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GPDMA1SMEN) +#define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) +#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) +#define __HAL_RCC_TSC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) +#define __HAL_RCC_RAMCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_RAMCFGSMEN) +#if defined(GTZC_TZSC) +#define __HAL_RCC_GTZC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GTZC1SMEN) +#endif +#define __HAL_RCC_ICACHE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_ICACHESMEN) +#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) + +#define __HAL_RCC_GPDMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GPDMA1SMEN) +#define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) +#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) +#define __HAL_RCC_TSC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) +#define __HAL_RCC_RAMCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_RAMCFGSMEN) +#if defined(GTZC_TZSC) +#define __HAL_RCC_GTZC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GTZC1SMEN) +#endif +#define __HAL_RCC_ICACHE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_ICACHESMEN) +#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) +/** + * @} + */ + +/** @defgroup RCC_AHB2_Peripheral_Clock_Sleep_Enable_Disable AHB2 Peripheral Clock Sleep Enable Disable + * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep and Stop) mode. + * @note Peripheral clock gating in SLEEP and STOP modes can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP or STOP modes, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode,in STOP mode peripheral clock + * is enabled only when a peripheral requests AHB clock. + * @{ + */ +#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) +#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) +#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) +#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) +#define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) +#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) +#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) +#if defined(SAES) +#define __HAL_RCC_SAES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SAESSMEN) +#endif +#define __HAL_RCC_PKA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_PKASMEN) +#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) + +#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) +#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) +#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) +#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) +#define __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) +#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) +#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) +#if defined(SAES) +#define __HAL_RCC_SAES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SAESSMEN) +#endif +#define __HAL_RCC_PKA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_PKASMEN) +#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) +/** + * @} + */ + +/** @defgroup RCC_AHB4_Clock_Sleep_Enable_Disable AHB4SMENR Peripheral Clock Sleep Enable Disable + * @brief Enable or disable the AHB4SMENR peripheral clock during Low Power (Sleep and STOP ) mode. + * @note Peripheral clock gating in SLEEP and STOP modes can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP or STOP modes, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode,in STOP mode peripheral clock + * is enabled only when a peripheral requests AHB clock. + * @{ + */ +#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4SMENR, RCC_AHB4SMENR_PWRSMEN) +#define __HAL_RCC_ADC4_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB4SMENR, RCC_AHB4SMENR_ADC4SMEN) + +#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4SMENR, RCC_AHB4SMENR_PWRSMEN) +#define __HAL_RCC_ADC4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB4SMENR, RCC_AHB4SMENR_ADC4SMEN) +/** + * @} + */ + +/** @defgroup RCC_AHB5_Clock_Sleep_Enable_Disable AHB5SMENR Peripheral Clock Sleep Enable Disable + * @brief Enable or disable the AHB5SMENR peripheral clock during Low Power (Sleep and STOP ) mode. + * @note Peripheral clock gating in SLEEP and STOP modes can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP or STOP modes, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode,in STOP mode peripheral clock + * is enabled only when a peripheral requests AHB clock. + * @{ + */ +#define __HAL_RCC_RADIO_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB5SMENR, RCC_AHB5SMENR_RADIOSMEN) +#define __HAL_RCC_RADIO_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB5SMENR, RCC_AHB5SMENR_RADIOSMEN) + +#if defined(PTACONV) +#define __HAL_RCC_PTACONV_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB5SMENR, RCC_AHB5SMENR_PTACONVSMEN) +#define __HAL_RCC_PTACONV_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB5SMENR, RCC_AHB5SMENR_PTACONVSMEN) +#endif +/** + * @} + */ + +/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable + * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep and Stop) mode. + * @note Peripheral clock gating in SLEEP and STOP modes can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP or STOP modes, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode,in STOP mode peripheral clock + * is enabled only when a peripheral requests APB clock. + * @{ + */ +#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) +#if defined(TIM3) +#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) +#endif +#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) +#if defined(USART2) +#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) +#endif +#if defined(I2C1) +#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) +#endif +#if defined(LPTIM2) +#define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) +#endif + +#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) +#if defined(TIM3) +#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) +#endif +#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) +#if defined(USART2) +#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) +#endif +#if defined(I2C1) +#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) +#endif +#if defined(LPTIM2) +#define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) +#endif +/** + * @} + */ + +/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable + * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep and Stop) mode. + * @note Peripheral clock gating in SLEEP and STOP modes can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP or STOP mode, the pseripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode,in STOP mode peripheral clock + * is enabled only when a peripheral requests APB clock. + * @{ + */ +#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) +#if defined(SPI1) +#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) +#endif +#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) +#define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) +#if defined(TIM17) +#define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) +#endif +#if defined(SAI1) +#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) +#endif + +#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) +#if defined(SPI1) +#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) +#endif +#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) +#define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) +#if defined(TIM17) +#define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) +#endif +#if defined(SAI1) +#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) +#endif +/** + * @} + */ + +/** @defgroup RCC_APB7_Clock_Sleep_Enable_Disable APB7 Peripheral Clock Sleep Enable Disable + * @brief Enable or disable the APB7 peripheral clock during Low Power (Sleep and Stop) mode. + * @note Peripheral clock gating in SLEEP and STOP modes can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP or STOP modes, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode,in STOP mode peripheral clock + * is enabled only when a peripheral requests APB clock. + * @{ + */ +#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB7SMENR, RCC_APB7SMENR_SYSCFGSMEN) +#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB7SMENR, RCC_APB7SMENR_SPI3SMEN) +#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB7SMENR, RCC_APB7SMENR_LPUART1SMEN) +#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB7SMENR, RCC_APB7SMENR_I2C3SMEN) +#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB7SMENR, RCC_APB7SMENR_LPTIM1SMEN) +#define __HAL_RCC_COMP_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB7SMENR, RCC_APB7SMENR_COMPSMEN) +#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB7SMENR, RCC_APB7SMENR_RTCAPBSMEN) + +#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB7SMENR, RCC_APB7SMENR_SYSCFGSMEN) +#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB7SMENR, RCC_APB7SMENR_SPI3SMEN) +#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB7SMENR, RCC_APB7SMENR_LPUART1SMEN) +#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB7SMENR, RCC_APB7SMENR_I2C3SMEN) +#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB7SMENR, RCC_APB7SMENR_LPTIM1SMEN) +#define __HAL_RCC_COMP_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB7SMENR, RCC_APB7SMENR_COMPSMEN) +#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB7SMENR, RCC_APB7SMENR_RTCAPBSMEN) +/** + * @} + */ + +/** @defgroup RCC_AHB1_Peripheral_Clock_Sleep_Enabled_Status AHB1 Peripheral Clock Sleep Enabled Status + * @brief Check whether the AHB1 peripheral clock during Low Power (Sleep) is enabled or not. + * @{ + */ +#define __HAL_RCC_GPDMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GPDMA1SMEN) != 0U) +#define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) != 0U) +#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) != 0U) +#define __HAL_RCC_TSC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) != 0U) +#define __HAL_RCC_RAMCFG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_RAMCFGSMEN) != 0U) +#if defined(GTZC_TZSC) +#define __HAL_RCC_GTZC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GTZC1SMEN) != 0U) +#endif +#define __HAL_RCC_ICACHE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_ICACHESMEN) != 0U) +#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) != 0U) +/** + * @} + */ + +/** @defgroup RCC_AHB2_Peripheral_Clock_Sleep_Enabled_Status AHB2 Peripheral Clock Sleep Enabled Status + * @brief Check whether the AHB2 peripheral clock during Low Power (Sleep) is enabled or not. + * @{ + */ +#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) != 0U) +#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) != 0U) +#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) != 0U) +#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) != 0U) +#define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) != 0U) +#define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_HASHSMEN) != 0U) +#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) != 0U) +#if defined(SAES) +#define __HAL_RCC_SAES_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SAESSMEN) != 0U) +#endif +#define __HAL_RCC_PKA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_PKASMEN) != 0U) +#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) != 0U) +/** + * @} + */ + +/** @defgroup RCC_AHB4_Peripheral_Clock_Sleep_Enabled_Status AHB4 Peripheral Clock Sleep Enabled Status + * @brief Check whether the AHB4 peripheral clock during Low Power (Sleep) is enabled or not. + * @{ + */ +#define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB4SMENR, RCC_AHB4SMENR_PWRSMEN) != 0U) +#define __HAL_RCC_ADC4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB4SMENR, RCC_AHB4SMENR_ADC4SMEN) != 0U) +/** + * @} + */ + +/** @defgroup RCC_AHB5_Peripheral_Clock_Sleep_Enabled_Status AHB5 Peripheral Clock Sleep Enabled Status + * @brief Check whether the AHB5 peripheral clock during Low Power (Sleep) is enabled or not. + * @{ + */ +#define __HAL_RCC_RADIO_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB5SMENR, RCC_AHB5SMENR_RADIOSMEN) != 0U) +#if defined(PTACONV) +#define __HAL_RCC_PTACONV_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB5SMENR, RCC_AHB5SMENR_PTACONVSMEN) != 0U) +#endif +/** + * @} + */ + +/** @defgroup RCC_APB1_Peripheral_Clock_Sleep_Enabled_Status APB1 Peripheral Clock Sleep Enabled Status + * @brief Check whether the APB1 peripheral clock during Low Power (Sleep) is enabled or not. + * @{ + */ +#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) != 0U) +#if defined(TIM3) +#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) != 0U) +#endif +#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) != 0U) +#if defined(USART2) +#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) != 0U) +#endif +#if defined(I2C1) +#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) != 0U) +#endif +#if defined(LPTIM2) +#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) != 0U) +#endif +/** + * @} + */ + +/** @defgroup RCC_APB2_Peripheral_Clock_Sleep_Enabled_Status APB2 Peripheral Clock Sleep Enabled Status + * @brief Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not. + * @{ + */ +#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) != 0U) +#if defined(SPI1) +#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != 0U) +#endif +#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != 0U) +#define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) != 0U) +#if defined(TIM17) +#define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) != 0U) +#endif +#if defined(SAI1) +#define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) != 0U) +#endif +/** + * @} + */ + +/** @defgroup RCC_APB7_Peripheral_Clock_Sleep_Enabled_Status APB7 Peripheral Clock Sleep Enabled Status + * @brief Check whether the APB7 peripheral clock during Low Power (Sleep) mode is enabled or not. + * @{ + */ +#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB7SMENR, RCC_APB7SMENR_SYSCFGSMEN) != 0U) +#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB7SMENR, RCC_APB7SMENR_SPI3SMEN) != 0U) +#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB7SMENR, RCC_APB7SMENR_LPUART1SMEN) != 0U) +#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB7SMENR, RCC_APB7SMENR_I2C3SMEN) != 0U) +#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB7SMENR, RCC_APB7SMENR_LPTIM1SMEN) != 0U) +#define __HAL_RCC_COMP_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB7SMENR, RCC_APB7SMENR_COMPSMEN) != 0U) +#define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB7SMENR, RCC_APB7SMENR_RTCAPBSMEN) != 0U) +/** + * @} + */ + + + +/** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset + * @{ + */ + +/** @brief Macros to force or release the Backup domain reset. + * @note This function resets the RTC peripheral (including the backup registers) + * and the RTC clock source selection in RCC_CSR register. + * @retval None + */ +#define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR1, RCC_BDCR1_BDRST) +#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR1, RCC_BDCR1_BDRST) +/** + * @} + */ + + +/** @brief Macros to enable or disable the Internal High Speed 16MHz oscillator (HSI). + * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. + * It is used (enabled by hardware) as system clock source after startup + * from Reset, wakeup from STOP and STANDBY mode, or in case of failure + * of the HSE used directly or indirectly as system clock (if the Clock + * Security System CSS is enabled). + * @note HSI can not be stopped if it is used as system clock source. In this case, + * you have to select another source of the system clock then stop the HSI. + * @note After enabling the HSI, the application software should wait on HSIRDY + * flag to be set indicating that HSI clock is stable and can be used as + * system clock source. + * This parameter can be: ENABLE or DISABLE. + * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator + * clock cycles. + * @retval None + */ +#define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION) +#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION) + +/** @brief Macro to adjust the Internal High Speed 16MHz oscillator (HSI) calibration value. + * @note The calibration is used to compensate for the variations in voltage + * and temperature that influence the frequency of the internal HSI RC. + * @param __HSICALIBRATIONVALUE__: specifies the calibration trimming value + * (default is RCC_HSICALIBRATION_DEFAULT). + * This parameter must be a number between 0 and 0x1F. + * @retval None + */ +#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \ + MODIFY_REG(RCC->ICSCR3, RCC_ICSCR3_HSITRIM, (__HSICALIBRATIONVALUE__) << RCC_ICSCR3_HSITRIM_Pos) + +/** + * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI) + * in STOP mode to be quickly available as kernel clock for USARTs, LPUART and I2Cs. + * @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication + * speed because of the HSI startup time. + * @note The enable of this function has not effect on the HSION bit. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +#define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON) +#define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON) + + + +/** @brief Macros to enable or disable the Internal Low Speed oscillator LSI1. + * @note After enabling the LSI1, the application software should wait on + * LSI1RDY flag to be set indicating that LSI1 clock is stable and can + * be used to clock the IWDG and/or the RTC. + * @note When the IWDG is started the LSI clock is forced on and cannot be disabled. + * When both LSI1 and LSI2 are disabled LSI1 will be forced on. When LSI selects + * LSI2 RC source, the LSI1 RC source can be disabled. + * @note When the LSI1 is stopped, LSI1RDY flag goes low after 3 LSI1 oscillator + * clock cycles. + * @retval None + */ +#define __HAL_RCC_LSI1_ENABLE() SET_BIT(RCC->BDCR1, RCC_BDCR1_LSI1ON) +#define __HAL_RCC_LSI1_DISABLE() CLEAR_BIT(RCC->BDCR1, RCC_BDCR1_LSI1ON) + +/** @brief Macro to set Low-speed clock LSI1 divider. + * @note Only LSI1 clock can be divided + * @note This bit can be written only when the LSI1 is disabled (LSI1ON = 0 and LSI1RDY = 0). + * The LSI1PREDIV cannot be changed if the LSI1 is used by the IWDG or by the RTC. + * @param __DIVIDER__ : specifies the divider value + * This parameter can be one of the following values + * @arg @ref RCC_LSI_DIV1 + * @arg @ref RCC_LSI_DIV128 + * @retval None + */ +#define __HAL_RCC_LSI_DIV_CONFIG(__DIVIDER__) MODIFY_REG(RCC->BDCR1, RCC_BDCR1_LSI1PREDIV, __DIVIDER__) + +#if defined(RCC_LSI2_SUPPORT) +/** @brief Macros to enable or disable the Internal Low Speed oscillator LSI2. + * @note After enabling the LSI2, the application software should wait on + * LSI2RDY flag to be set indicating that LSI2 clock is stable and can + * be used to clock the IWDG and/or the RTC. + * @note When the IWDG is started the LSI clock is forced on and cannot be disabled. + * When both LSI1 and LSI2 are disabled LSI1 will be forced on. When LSI selects + * LSI2 RC source, the LSI1 RC source can be disabled. + * @note When the LSI2 is stopped, LSI2RDY flag goes low after 3 LSI1 oscillator + * clock cycles. + * @retval None + */ +#define __HAL_RCC_LSI2_ENABLE() SET_BIT(RCC->BDCR1, RCC_BDCR1_LSI2ON) +#define __HAL_RCC_LSI2_DISABLE() CLEAR_BIT(RCC->BDCR1, RCC_BDCR1_LSI2ON) +#endif /* RCC_BDCR1_LSI2ON */ + +/** + * @brief Macro to configure the External High Speed oscillator (HSE). + * @note After enabling the HSE (RCC_HSE_ON), the application + * software should wait on HSERDY flag to be set indicating that HSE clock + * is stable and can be used to clock the PLL1 and/or system clock. + * @note HSE state can not be changed if it is used directly or through the + * PLL1 as system clock. In this case, you have to select another source + * of the system clock then change the HSE state (ex. disable it). + * @note The HSE is stopped by hardware when entering STOP and STANDBY or shutdown modes. + * @note HSERDY flag may remain high when HSEON bit is cleared. This is when the 2.4 GHz + * RADIO uses the HSE32 as its kernel clock. + * @param __STATE__: specifies the new state of the HSE. + * This parameter can be a combination of the following values: + * @arg @ref RCC_HSE_OFF Turn OFF the HSE oscillator, HSERDY flag goes low after + * 6 HSE oscillator clock cycles. + * @arg @ref RCC_HSE_ON Turn ON the HSE oscillator. + * @arg @ref RCC_HSE_DIV1 Divide HSE by 1 for SYSCLK + * @arg @ref RCC_HSE_DIV2 Divide HSE by 2 for SYSCLK + * @retval None + */ +#define __HAL_RCC_HSE_CONFIG(__STATE__) MODIFY_REG(RCC->CR, (RCC_CR_HSEON | RCC_CR_HSEPRE), __STATE__) + + +/** @brief Macro to enable or disable the LSE system clock. + * @note This clock can be used by any peripheral when its source clock is the LSE or at system + * in case of one of the LSCOSEL, MCO or CSS on LSE is needed. + * @note The LSESYS clock can be generated even if LSESYSEN= 0 if the LSE clock is requested by + * the CSS on LSE, by a peripheral or any other source clock using LSE. + * @retval None + */ +#define __HAL_RCC_LSESYS_ENABLE() SET_BIT(RCC->BDCR1,RCC_BDCR1_LSESYSEN) +#define __HAL_RCC_LSESYS_DISABLE() CLEAR_BIT(RCC->BDCR1,RCC_BDCR1_LSESYSEN) + + +/** @brief Macros to enable or disable LSE clock glitch filter . + * @note The glitches on LSE can be filtred by setting the LSEGFON. + * @note LSEGFON must be written when the LSE is disabled (LSEON = 0 and LSERDY = 0). + * @retval None + */ +#define __HAL_RCC_LSE_GlitchFilter_ENABLE() SET_BIT(RCC->BDCR1, RCC_BDCR1_LSEGFON ) +#define __HAL_RCC_LSE_GlitchFilter_DISABLE() CLEAR_BIT(RCC->BDCR1, RCC_BDCR1_LSEGFON ) + +/** + * @brief Macro to configure the External Low Speed oscillator (LSE). + * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not + * supported by this macro. User should request a transition to LSE Off + * first and then LSE On or LSE Bypass. + * @note As the LSE is in the Backup domain and write access is denied to + * this domain after reset, you have to enable write access using + * HAL_PWR_EnableBkUpAccess() function before to configure the LSE + * (to be done once after reset). + * @note After enabling the LSE, the application + * software should wait on LSERDY flag to be set indicating that LSE clock + * is stable and can be used to clock the RTC. + * @param __STATE__: specifies the new state of the LSE. + * This parameter can be one of the following values: + * @arg @ref RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after + * 6 LSE oscillator clock cycles. + * @arg @ref RCC_LSE_ON_RTC_ONLY Turn ON the LSE oscillator to be used only for RTC. + * @arg @ref RCC_LSE_ON Turn ON the LSE oscillator to be used by any peripheral. + * @arg @ref RCC_LSE_BYPASS_RTC_ONLY LSE oscillator bypassed with external clock to be used only for RTC. + * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock to be used by any peripheral. + * @retval None + */ +#define __HAL_RCC_LSE_CONFIG(__STATE__) do { \ + if((__STATE__) == RCC_LSE_ON_RTC_ONLY) \ + { \ + SET_BIT(RCC->BDCR1, RCC_BDCR1_LSEON); \ + } \ + else if((__STATE__) == RCC_LSE_ON) \ + { \ + SET_BIT(RCC->BDCR1, (RCC_BDCR1_LSEON | RCC_BDCR1_LSESYSEN)); \ + } \ + else if((__STATE__) == RCC_LSE_BYPASS) \ + { \ + SET_BIT(RCC->BDCR1, RCC_BDCR1_LSEBYP); \ + SET_BIT(RCC->BDCR1, (RCC_BDCR1_LSEON | RCC_BDCR1_LSESYSEN)); \ + } \ + else if((__STATE__) == RCC_LSE_BYPASS) \ + { \ + SET_BIT(RCC->BDCR1, RCC_BDCR1_LSEBYP); \ + SET_BIT(RCC->BDCR1, RCC_BDCR1_LSEON); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->BDCR1, (RCC_BDCR1_LSEON | RCC_BDCR1_LSESYSEN)); \ + CLEAR_BIT(RCC->BDCR1, RCC_BDCR1_LSEBYP); \ + } \ + } while(0) + + +/** @brief Macros to configure the RTC clock (RTCCLK). + * @note As the RTC clock configuration bits are in the Backup domain and write + * access is denied to this domain after reset, you have to enable write + * access using the Power Backup Access macro before to configure + * the RTC clock source (to be done once after reset). + * @note Once the RTC clock is configured it cannot be changed unless the + * Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by + * a Power On Reset (POR). + * + * @param __RTC_CLKSOURCE__: specifies the RTC clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_RTCCLKSOURCE_DISABLE RTC clock is disabled. + * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected + * + * @note If the LSE or LSI is used as RTC clock source, the RTC continues to + * work in STOP and STANDBY modes, and can be used as wakeup source. + * However, when the HSE clock is used as RTC clock source, the RTC + * cannot be used in STOP and STANDBY modes. + * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as + * RTC clock source). + * @retval None + */ +#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) \ + MODIFY_REG(RCC->BDCR1, RCC_BDCR1_RTCSEL, (__RTC_CLKSOURCE__)) + + +/** @brief Macro to get the RTC clock source. + * @retval The returned value can be one of the following: + * @arg @ref RCC_RTCCLKSOURCE_DISABLE RTC clock is disabled. + * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected + */ +#define __HAL_RCC_GET_RTC_SOURCE() READ_BIT(RCC->BDCR1, RCC_BDCR1_RTCSEL) + +/** @brief Macros to enable or disable the main PLL1. + * @note After enabling the main PLL1, the application software should wait on + * PLLRDY flag to be set indicating that PLL1 clock is stable and can + * be used as system clock source. + * @note The main PLL1 can not be disabled if it is used as system clock source + * @note The main PLL1 is disabled by hardware when entering STOP and STANDBY modes. + */ +#define __HAL_RCC_PLL1_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL1ON) +#define __HAL_RCC_PLL1_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON) + +/** + * @brief Enables or disables each clock output (PLL_PCLK, PLL_QCLK, PLL_RCLK) + * @note Enabling/disabling Those Clocks can be any time without the need to stop the PLL1, + * This is mainly used to save Power. + * @param __PLL1_CLOCKOUT__: specifies the PLL1 clock to be output + * This parameter can be a combination of the following values: + * @arg RCC_PLL1_PCLK: This clock can be used to generate an accurate clock for SAI1 + * interface and/or ADC4 + * @arg RCC_PLL1_QCLK: This Clock is used to generate an accurate clock for RNG (<= 48 MHz). + * @arg RCC_PLL1_RCLK: This Clock is used to generate and high speed system clock (up to 100MHz) + * @retval None + * + */ +#define __HAL_RCC_PLL1CLKOUT_ENABLE(__PLL1_CLOCKOUT__) SET_BIT(RCC->PLL1CFGR, (__PLL1_CLOCKOUT__)) +#define __HAL_RCC_PLL1CLKOUT_DISABLE(__PLL1_CLOCKOUT__) CLEAR_BIT(RCC->PLL1CFGR, (__PLL1_CLOCKOUT__)) + +/** + * @brief Macro to get the PLL1 clock output enable status. + * @param __PLL1_CLOCKOUT__ specifies the PLL1 clock to be output. + * This parameter can be one of the following values: + * @arg RCC_PLL1_PCLK + * @arg RCC_PLL1_QCLK + * @arg RCC_PLL1_RCLK + * @retval SET / RESET + */ +#define __HAL_RCC_GET_PLL1CLKOUT_CONFIG(__PLL1_CLOCKOUT__) READ_BIT(RCC->PLL1CFGR, (__PLL1_CLOCKOUT__)) + +/** + * @brief Macro to configures the main PLL1 clock source, multiplication and division factors. + * @note This function must be used only when the main PLL1 is disabled. + * @param __PLL1SOURCE__: specifies the PLL1 entry clock source. + * This parameter can be one of the following values: + * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL1 clock entry + * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL1 clock entry + * @param __PLL1M__: specifies the division factor for PLL1 VCO input clock + * This parameter must be a number between 1 and 8. + * @note You have to set the PLLM parameter correctly to ensure that the VCO input + * frequency ranges from 4 to 16 MHz. + * @param __PLL1N__: specifies the multiplication factor for PLL1 VCO output clock + * This parameter must be a number between 4 and 512. + * @note You have to set the PLLN parameter correctly to ensure that the VCO output + * frequency is between 128 and 544 MHz. + * @param __PLL1P__: specifies the division factor for system clock. + * This parameter must be an even number between 2 and 128. + * @param __PLL1Q__: specifies the division factor for peripheral kernel clocks + * This parameter must be a number between 1 and 128 + * @param __PLL1R__: specifies the division factor for peripheral kernel clocks + * This parameter must be a number between 1 and 128 + * @retval None + */ +#define __HAL_RCC_PLL1_CONFIG(__PLL1SOURCE__, __PLL1M__, __PLL1N__, __PLL1P__, __PLL1Q__, __PLL1R__) \ + do{ \ + MODIFY_REG(RCC->PLL1CFGR, (RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1M), ((__PLL1SOURCE__) | (((__PLL1M__) - 1U) << RCC_PLL1CFGR_PLL1M_Pos))); \ + WRITE_REG(RCC->PLL1DIVR, (((__PLL1N__) - 1U) | (((__PLL1P__) - 1U) << RCC_PLL1DIVR_PLL1P_Pos) | (((__PLL1Q__) - 1U) << RCC_PLL1DIVR_PLL1Q_Pos) | \ + (((__PLL1R__) - 1U) << RCC_PLL1DIVR_PLL1R_Pos))); \ + } while(0) + +/** + * @brief Macro to configure the PLL1 clock source. + * @note This function must be used only when PLL1 is disabled. + * @param __PLL1SOURCE__: specifies the PLLs entry clock source. + * This parameter can be one of the following values: + * @arg RCC_PLLSOURCE_NONE: No clock selected as PLL1 clock entry (used to save Power) + * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL1 clock entry + * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL1 clock entry + * + */ +#define __HAL_RCC_PLL1_PLLSOURCE_CONFIG(__PLL1SOURCE__) \ + MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC, (__PLL1SOURCE__)) + +/** + *@brief Macro to select the PLL1 VCO input frequency range. + * @param __VCOINPUTRANGE__: specifies VCO input frequency range + * This parameter can be one of the following values: + * @arg RCC_PLL_VCOINPUT_RANGE0: Range frequency is between 4 and 8 MHz + * @arg RCC_PLL_VCOINPUT_RANGE1: Range frequency is between 8 and 16 MHz + * @retval None + */ +#define __HAL_RCC_PLL1_VCOINPUTRANGE_CONFIG(__VCOINPUTRANGE__) \ + MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1RGE, (__VCOINPUTRANGE__)) + +/** + * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL1 VCO + * @note Enabling/disabling Fractional Part can be any time without the need to stop the PLL1 + * @retval None + */ +#define __HAL_RCC_PLL1_FRACN_ENABLE() SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN) +#define __HAL_RCC_PLL1_FRACN_DISABLE() CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN) + +/** + * @brief Macro to configures the main PLL1 clock fractional part of The multiplication factor + * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO + * @param __PLL1FRACN__: specifies Fractional part of the multiplication factor for PLL1 VCO + * It should be a value between 0 and 8191 + * @retval None + */ +#define __HAL_RCC_PLL1_FRACN_CONFIG(__PLL1FRACN__) WRITE_REG(RCC->PLL1FRACR, (__PLL1FRACN__) << RCC_PLL1FRACR_PLL1FRACN_Pos) + + +/** + * @brief Macro to get the oscillator used as PLL1 clock source. + * @retval The oscillator used as PLL1 clock source. The returned value can be one + * of the following: + * - RCC_PLLSOURCE_NONE: No oscillator is used as PLL1 clock source. + * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL1 clock source. + * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL1 clock source. + */ +#define __HAL_RCC_GET_PLL1_OSCSOURCE() (RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC) + +/** + * @brief Macro to configure the system clock source. + * @param __SYSCLKSOURCE__: specifies the system clock source. + * This parameter can be one of the following values: + * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source. + * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source. + * - RCC_SYSCLKSOURCE_PLLCLK: PLL1 output is used as system clock source. + * @retval None + */ +#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR1, RCC_CFGR1_SW, (__SYSCLKSOURCE__)) + +/** + * @brief Macro to get the clock source used as system clock. + * @retval The clock source used as system clock. The returned value can be one + * of the following: + * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock. + * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock. + * - RCC_SYSCLKSOURCE_STATUS_PLL1CLK: PLL1 used as system clock. + */ +#define __HAL_RCC_GET_SYSCLK_SOURCE() (RCC->CFGR1 & RCC_CFGR1_SWS) + +/** + * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability. + * @note As the LSE is in the Backup domain and write access is denied to + * this domain after reset, you have to enable write access using + * HAL_PWR_EnableBkUpAccess() function before to configure the LSE + * (to be done once after reset). + * @note The LSE drive can be decreased to the lower drive capability (LSEDRV = 0) + * when the LSE is ON. However, once LSEDRV is selected, the drive + * capability can not be increased if LSEON = 1. + * @param __LSEDRIVE__: specifies the new state of the LSE drive capability. + * This parameter can be one of the following values: + * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability. + * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability. + * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability. + * @retval None + */ +#define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) MODIFY_REG(RCC->BDCR1, RCC_BDCR1_LSEDRV, (__LSEDRIVE__)) + +/** + * @brief Macro to configure the MCO clock. + * @param __MCOCLKSOURCE__ specifies the MCO clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled + * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_PLL1RCLK Main PLL1 clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_PLL1PCLK pll1pclk selected as MCO source + * @arg @ref RCC_MCO1SOURCE_PLL1QCLK pll1qclk selected as MCO source + * @arg @ref RCC_MCO1SOURCE_HCLK5 phclk5 selected as MCO source + * @param __MCODIV__ specifies the MCO clock prescaler. + * This parameter can be one of the following values: + * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1 + * @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2 + * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4 + * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8 + * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16 + */ +#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ + MODIFY_REG(RCC->CFGR1, (RCC_CFGR1_MCOSEL | RCC_CFGR1_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) + +/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management + * @brief macros to manage the specified RCC Flags and interrupts. + * @{ + */ + +/** + * @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable + * the selected interrupts). + * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg @ref RCC_IT_LSI1RDY LSI1 ready interrupt + * @arg @ref RCC_IT_LSERDY LSE ready interrupt + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt + * @arg @ref RCC_IT_HSERDY HSE ready interrupt + * @arg @ref RCC_IT_PLL1RDY PLL1 ready interrupt + * @arg @ref RCC_IT_LSI2RDY LSI2 ready interrupt(*) + * (*) Feature not available on all devices of the family + * @retval None + */ +#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__)) + +/** + * @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable + * the selected interrupts). + * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg @ref RCC_IT_LSI1RDY LSI1 ready interrupt + * @arg @ref RCC_IT_LSERDY LSE ready interrupt + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt + * @arg @ref RCC_IT_HSERDY HSE ready interrupt + * @arg @ref RCC_IT_PLL1RDY PLL1 ready interrupt + * @arg @ref RCC_IT_LSI2RDY LSI2 ready interrupt(*) + * (*) Feature not available on all devices of the family + * @retval None + */ +#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__)) + +/** + * @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16] + * bits to clear the selected interrupt pending bits. + * @param __INTERRUPT__: specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg @ref RCC_IT_LSI1RDY LSI1 ready interrupt + * @arg @ref RCC_IT_LSERDY LSE ready interrupt + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt + * @arg @ref RCC_IT_HSERDY HSE ready interrupt + * @arg @ref RCC_IT_PLL1RDY PLL1 ready interrupt + * @arg @ref RCC_IT_CSS High speed external clock security system interrupt + * @arg @ref RCC_IT_LSI2RDY LSI2 ready interrupt(*) + * (*) Feature not available on all devices of the family + * @retval None + */ +#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) WRITE_REG(RCC->CICR, (__INTERRUPT__)) + +/** @brief Check whether the RCC interrupt has occurred or not. + * @param __INTERRUPT__: specifies the RCC interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref RCC_IT_LSI1RDY LSI1 ready interrupt + * @arg @ref RCC_IT_LSERDY LSE ready interrupt + * @arg @ref RCC_IT_HSIRDY HSI ready interrupt + * @arg @ref RCC_IT_HSERDY HSE ready interrupt + * @arg @ref RCC_IT_PLL1RDY PLL1 ready interrupt + * @arg @ref RCC_IT_CSS High speed external clock security system interrupt + * @arg @ref RCC_IT_LSI2RDY LSI2 ready interrupt(*) + * (*) Feature not available on all devices of the family + * @retval The new state of __INTERRUPT__ (TRUE or FALSE). + */ +#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__)) + +/** @brief Set RMVF bit to clear the reset flags. + * The reset flags are: RCC_FLAG_FWRRST, RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_BORRST, + * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST. + * @retval None + */ +#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF) + +/** + * @brief Check whether the selected RCC flag is set or not. + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready + * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready + * @arg @ref RCC_FLAG_PLL1RDY PLL1 clock ready + * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready + * @arg @ref RCC_FLAG_LSECSSD Clock security system failure on LSE oscillator detection + * @arg @ref RCC_FLAG_LSI1RDY LSI1 oscillator clock ready + * @arg @ref RCC_FLAG_LSI2RDY LSI2 oscillator clock ready(*) + * @arg @ref RCC_FLAG_BORRST BOR reset + * @arg @ref RCC_FLAG_OBLRST OBLRST reset + * @arg @ref RCC_FLAG_PINRST Pin reset + * @arg @ref RCC_FLAG_SFTRST Software reset + * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset + * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset + * @arg @ref RCC_FLAG_LPWRRST Low Power reset + * (*) Feature not available on all devices of the family + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_RCC_GET_FLAG(__FLAG__) ((((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \ + ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR1 : \ + ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR)))) & \ + (1U << ((__FLAG__) & RCC_FLAG_MASK))) != 0U) ? 1U : 0U) +/** + * @} + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup RCC_Private_Constants RCC Private Constants + * @{ + */ +#define PLL_VCOINPUTFREQ_MAX 16000000U /* Maximum VCO input frequency is 16 MHz */ +#define PLL_VCOINPUTFREQ_MIN 4000000U /* Minimum VCO input frequency is 4 MHz */ +#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT +#define HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ + + +/* Defines used for Flags */ +#define CR_REG_INDEX (1U) +#define BDCR1_REG_INDEX (2U) +#define CSR_REG_INDEX (3U) + +#define RCC_FLAG_MASK (0x1FU) + +/* Define used for IS_RCC_* below */ +#define RCC_CLOCKTYPE_ALL (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_HCLK5 | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK7) /*!< All clocktype to configure */ +#define RCC_OSCILLATORTYPE_ALL (RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI) /*!< All Oscillator to configure */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup RCC_Private_Macros + * @{ + */ +#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ + (((__OSCILLATOR__) & ~RCC_OSCILLATORTYPE_ALL) == 0x00U)) + +#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON)) + +#define IS_RCC_HSEDIV(__HSEDIV__) (((__HSEDIV__) == RCC_HSE_DIV1) || ((__HSEDIV__) == RCC_HSE_DIV2)) + +#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON_RTC_ONLY) || \ + ((__LSE__) == RCC_LSE_ON) || ((__LSE__) == RCC_LSE_BYPASS_RTC_ONLY) || \ + ((__LSE__) == RCC_LSE_BYPASS)) + +#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) + +#define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)( RCC_ICSCR3_HSITRIM >> RCC_ICSCR3_HSITRIM_Pos)) + +#if defined(RCC_LSI2_SUPPORT) +#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI1_ON) || \ + ((__LSI__) == RCC_LSI2_ON)) +#else +#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI1_ON)) +#endif /* RCC_BDCR1_LSI2ON */ + +#define IS_RCC_LSIDIV(__LSIDIV__) (((__LSIDIV__) == RCC_LSI_DIV1) || ((__LSIDIV__) == RCC_LSI_DIV128)) + +#define IS_RCC_PLL(PLL1) (((PLL1) == RCC_PLL_NONE) ||((PLL1) == RCC_PLL_OFF) || \ + ((PLL1) == RCC_PLL_ON)) + +#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \ + ((SOURCE) == RCC_PLLSOURCE_HSE)) + +#define IS_RCC_PLLM_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 8U)) +#define IS_RCC_PLLN_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U)) +#define IS_RCC_PLLP_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) +#define IS_RCC_PLLQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) +#define IS_RCC_PLLR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) + +#define IS_RCC_PLL_VCOINPUTFREQ(VALUE) ((PLL_VCOINPUTFREQ_MIN <= (VALUE)) && ((VALUE) <= PLL_VCOINPUTFREQ_MAX)) + +#define IS_RCC_PLLFRACN_VALUE(VALUE) ((VALUE) <= (RCC_PLL1FRACR_PLL1FRACN >> RCC_PLL1FRACR_PLL1FRACN_Pos)) + +#define IS_RCC_CLOCKTYPE(__CLK__) ((((__CLK__) & RCC_CLOCKTYPE_ALL) != 0x00UL) && (((__CLK__) & ~RCC_CLOCKTYPE_ALL) == 0x00UL)) + +#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK)) + +#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \ + ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \ + ((__HCLK__) == RCC_SYSCLK_DIV16)) + +#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \ + ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \ + ((__PCLK__) == RCC_HCLK_DIV16)) + +#define IS_RCC_HCLK5_PLL1(__HCLK5__) (((__HCLK5__) == RCC_SYSCLK_PLL1_DIV1) || ((__HCLK5__) == RCC_SYSCLK_PLL1_DIV2) || \ + ((__HCLK5__) == RCC_SYSCLK_PLL1_DIV3) || ((__HCLK5__) == RCC_SYSCLK_PLL1_DIV4) || \ + ((__HCLK5__) == RCC_SYSCLK_PLL1_DIV6)) + +#define IS_RCC_HCLK5_HSEHSI(__HCLK5__) (((__HCLK5__) == RCC_SYSCLK_HSEHSI_DIV1) || ((__HCLK5__) == RCC_SYSCLK_HSEHSI_DIV2)) + +#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_DISABLE) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32)) + +#define IS_RCC_MCO(__MCOX__) ((__MCOX__) == RCC_MCO1) + +#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_PLL1RCLK) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_PLL1PCLK) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_PLL1QCLK) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_HCLK5)) + +#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \ + ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \ + ((__DIV__) == RCC_MCODIV_16)) + +#define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \ + ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \ + ((__DRIVE__) == RCC_LSEDRIVE_HIGH)) + +#define IS_RCC_ITEM_ATTRIBUTES(__ITEM__) (((__ITEM__) != 0x00U) && (((__ITEM__) & ~RCC_ALL) == 0x00U)) + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define IS_RCC_ATTRIBUTES(__ATTRIBUTES__) (((__ATTRIBUTES__) == RCC_SEC_PRIV) || \ + ((__ATTRIBUTES__) == RCC_SEC_NPRIV) || \ + ((__ATTRIBUTES__) == RCC_NSEC_PRIV) || \ + ((__ATTRIBUTES__) == RCC_NSEC_NPRIV)) +#else +#define IS_RCC_ATTRIBUTES(__ATTRIBUTES__) (((__ATTRIBUTES__) == RCC_NSEC_NPRIV) || ((__ATTRIBUTES__) == RCC_NSEC_PRIV)) +#endif /* __ARM_FEATURE_CMSE */ +/** + * @} + */ + +/** + * @} + */ +/* Include RCC HAL Extended module */ +#include "stm32wbaxx_hal_rcc_ex.h" + +/* Exported functions ----------------------------------------------------------*/ +/** @addtogroup RCC_Exported_Functions + * @{ + */ + +/** @addtogroup RCC_Exported_Functions_Group1 + * @{ + */ + +/* Initialization and de-initialization functions ******************************/ +HAL_StatusTypeDef HAL_RCC_DeInit(void); +HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *RCC_OscInitStruct); +HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); + +/** + * @} + */ + +/** @addtogroup RCC_Exported_Functions_Group2 + * @{ + */ +/* Peripheral Control functions **********************************************/ +void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); +void HAL_RCC_EnableCSS(void); +uint32_t HAL_RCC_GetSysClockFreq(void); +uint32_t HAL_RCC_GetHCLKFreq(void); +uint32_t HAL_RCC_GetPCLK1Freq(void); +uint32_t HAL_RCC_GetPCLK2Freq(void); +uint32_t HAL_RCC_GetPCLK7Freq(void); +uint32_t HAL_RCC_GetHCLK5Freq(void); +uint32_t HAL_RCC_GetPLL1PFreq(void); +uint32_t HAL_RCC_GetPLL1QFreq(void); +uint32_t HAL_RCC_GetPLL1RFreq(void); +void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); +void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); +/* CSS NMI IRQ handler */ +void HAL_RCC_NMI_IRQHandler(void); +/* User Callbacks in non blocking mode (IT mode) */ +void HAL_RCC_CSSCallback(void); +uint32_t HAL_RCC_GetResetSource(void); +/** + * @} + */ + +/** @addtogroup RCC_Exported_Functions_Group3 + * @{ + */ +/* Attributes management functions ********************************************/ +void HAL_RCC_ConfigAttributes(uint32_t Item, uint32_t Attributes); +HAL_StatusTypeDef HAL_RCC_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32WBAxx_HAL_RCC_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rcc_ex.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rcc_ex.h new file mode 100644 index 0000000000..20e5dd3ad5 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rcc_ex.h @@ -0,0 +1,987 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_rcc_ex.h + * @author MCD Application Team + * @brief Header file of RCC HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32WBAxx_HAL_RCC_EX_H +#define __STM32WBAxx_HAL_RCC_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal_def.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @addtogroup RCCEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup RCCEx_Exported_Types RCCEx Exported Types + * @{ + */ +#if defined(RCC_LSI2_SUPPORT) +/** + * @brief RCC LSI2 configuration structure definition + */ +typedef struct +{ + uint32_t FreqTempSens; /*!< The temperature at which the frequency temperature sensitivity is close to zero. + This parameter can be a value of @ref RCCEx_LSI2_Frequency_Temperature_Sensitivity */ + + uint32_t OpMode; /*!< The operating mode of power consumption versus accuracy. + This parameter can be a value of @ref RCCEx_LSI2_Operating_Mode */ +} RCC_LSIConfigTypeDef; +#endif + +/** + * @brief RCC extended clocks structure definition + */ +typedef struct +{ + uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + uint32_t Usart1ClockSelection; /*!< Specifies USART1 clock source. + This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ + +#if defined (USART2) + uint32_t Usart2ClockSelection; /*!< Specifies USART2 clock source. + This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ +#endif + + +#if defined (I2C1) + uint32_t I2c1ClockSelection; /*!< Specifies I2C1 clock source. + This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */ +#endif + + + + +#if defined (LPTIM2) + uint32_t Lptim2ClockSelection; /*!< Specifies LPTIM2 clock source. + This parameter can be a value of @ref RCCEx_LPTIM2_Clock_Source */ +#endif + +#if defined (SPI1) + uint32_t Spi1ClockSelection; /*!< Specifies SPI1 clock source + This parameter can be a value of @ref RCCEx_SPI1_Clock_Source */ +#endif + + uint32_t SystickClockSelection; /*!< Specifies SYSTICK clock source. + This parameter can be a value of @ref RCCEx_SYSTICK_Clock_Source */ + + uint32_t TimIcClockSelection; /*!< Specifies TIMIC clock source. + This parameter can be a value of @ref RCCEx_TIMIC_Clock_Source */ + +#if defined (SAI1) + uint32_t Sai1ClockSelection; /*!< Specifies SAI1 clock source. + This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */ +#endif + + uint32_t RngClockSelection; /*!< Specifies RNG clock source + This parameter can be a value of @ref RCCEx_RNG_Clock_Source */ + + +#if defined (RCC_CCIPR2_ASSEL) + uint32_t AudioSyncClockSelection; /*!< Specifies Audio Sync clock source. + This parameter can be a value of @ref RCCEx_AudioSync_Clock_Source */ +#endif + + uint32_t Lpuart1ClockSelection; /*!< Specifies LPUART1 clock source. + This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */ + + uint32_t Spi3ClockSelection; /*!< Specifies SPI3 clock source + This parameter can be a value of @ref RCCEx_SPI3_Clock_Source */ + + uint32_t I2c3ClockSelection; /*!< Specifies I2C3 clock source. + This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ + + uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source. + This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ + + uint32_t AdcClockSelection; /*!< Specifies ADC4 interface clock source. + This parameter can be a value of @ref RCCEx_ADC_Clock_Source */ + + uint32_t RTCClockSelection; /*!< Specifies RTC clock source. + This parameter can be a value of @ref RCC_RTC_Clock_Source */ + + uint32_t RadioSlpTimClockSelection; /*!< Specifies Radio Sleep Timer clock source. + This parameter can be a value of @ref RCC_RadioSleepTimer_Clock_Source */ +} RCC_PeriphCLKInitTypeDef; +/** + * @} + */ + + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants + * @{ + */ + +/** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection + * @{ + */ +#define RCC_PERIPHCLK_USART1 0x00000001U +#if defined (USART2) +#define RCC_PERIPHCLK_USART2 0x00000002U +#endif +#if defined (I2C1) +#define RCC_PERIPHCLK_I2C1 0x00000004U +#endif +#if defined (LPTIM2) +#define RCC_PERIPHCLK_LPTIM2 0x00000008U +#endif +#if defined (SPI1) +#define RCC_PERIPHCLK_SPI1 0x00000010U +#endif +#define RCC_PERIPHCLK_SYSTICK 0x00000020U +#define RCC_PERIPHCLK_TIMIC 0x00000040U +#if defined (SAI1) +#define RCC_PERIPHCLK_SAI1 0x00000080U +#endif +#define RCC_PERIPHCLK_RNG 0x00000100U +#define RCC_PERIPHCLK_LPUART1 0x00000200U +#define RCC_PERIPHCLK_SPI3 0x00000400U +#define RCC_PERIPHCLK_I2C3 0x00000800U +#define RCC_PERIPHCLK_LPTIM1 0x00001000U +#define RCC_PERIPHCLK_ADC 0x00002000U +#define RCC_PERIPHCLK_RTC 0x00004000U +#define RCC_PERIPHCLK_RADIOST 0x00008000U +#if defined (RCC_CCIPR2_ASSEL) +#define RCC_PERIPHCLK_AUDIOSYNC 0x00200000U +#endif +/** + * @} + */ + +/** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source + * @{ + */ +#define RCC_USART1CLKSOURCE_PCLK2 0x00000000U +#define RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR1_USART1SEL_0 +#define RCC_USART1CLKSOURCE_HSI RCC_CCIPR1_USART1SEL_1 +#define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR1_USART1SEL_0 | RCC_CCIPR1_USART1SEL_1) +/** + * @} + */ + +#if defined (USART2) +/** @defgroup RCCEx_USART2_Clock_Source USART2 Clock Source + * @{ + */ +#define RCC_USART2CLKSOURCE_PCLK1 0x00000000U +#define RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR1_USART2SEL_0 +#define RCC_USART2CLKSOURCE_HSI RCC_CCIPR1_USART2SEL_1 +#define RCC_USART2CLKSOURCE_LSE (RCC_CCIPR1_USART2SEL_0 | RCC_CCIPR1_USART2SEL_1) +/** + * @} + */ +#endif + + +#if defined (I2C1) +/** @defgroup RCCEx_I2C1_Clock_Source I2C1 Clock Source + * @{ + */ +#define RCC_I2C1CLKSOURCE_PCLK1 0x00000000U +#define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR1_I2C1SEL_0 +#define RCC_I2C1CLKSOURCE_HSI RCC_CCIPR1_I2C1SEL_1 +/** + * @} + */ +#endif + + + + +#if defined (LPTIM2) +/** @defgroup RCCEx_LPTIM2_Clock_Source LPTIM2 Clock Source + * @{ + */ +#define RCC_LPTIM2CLKSOURCE_PCLK1 0x00000000U +#define RCC_LPTIM2CLKSOURCE_LSI RCC_CCIPR1_LPTIM2SEL_0 +#define RCC_LPTIM2CLKSOURCE_HSI RCC_CCIPR1_LPTIM2SEL_1 +#define RCC_LPTIM2CLKSOURCE_LSE RCC_CCIPR1_LPTIM2SEL +/** + * @} + */ +#endif + +#if defined (SPI1) +/** @defgroup RCCEx_SPI1_Clock_Source SPI1 Clock Source + * @{ + */ +#define RCC_SPI1CLKSOURCE_PCLK2 0x00000000U +#define RCC_SPI1CLKSOURCE_SYSCLK RCC_CCIPR1_SPI1SEL_0 +#define RCC_SPI1CLKSOURCE_HSI RCC_CCIPR1_SPI1SEL_1 +/** + * @} + */ +#endif + +/** @defgroup RCCEx_SYSTICK_Clock_Source SYSTICK Clock Source + * @{ + */ +#define RCC_SYSTICKCLKSOURCE_HCLK_DIV8 0x00000000U +#define RCC_SYSTICKCLKSOURCE_LSI RCC_CCIPR1_SYSTICKSEL_0 +#define RCC_SYSTICKCLKSOURCE_LSE RCC_CCIPR1_SYSTICKSEL_1 +/** + * @} + */ + +/** @defgroup RCCEx_TIMIC_Clock_Source RCC Timicsel Items + * @{ + */ +#define RCC_TIMICCLKSOURCE_HSI 0x00000000U /*!< HSI selected for Timer16/17 and LPTimer2 */ +#define RCC_TIMICCLKSOURCE_HSI_DIV256 RCC_CCIPR1_TIMICSEL /*!< HSI/256 selected for Timer16/17 and LPTimer2 */ +/* + * @} + */ + +#if defined (SAI1) +/** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source + * @{ + */ +#define RCC_SAI1CLKSOURCE_PLL1P 0x00000000U +#define RCC_SAI1CLKSOURCE_PLL1Q RCC_CCIPR2_SAI1SEL_0 +#define RCC_SAI1CLKSOURCE_SYSCLK RCC_CCIPR2_SAI1SEL_1 +#define RCC_SAI1CLKSOURCE_PIN (RCC_CCIPR2_SAI1SEL_1 | RCC_CCIPR2_SAI1SEL_0) +#define RCC_SAI1CLKSOURCE_HSI RCC_CCIPR2_SAI1SEL_2 +/** + * @} + */ +#endif + +/** @defgroup RCCEx_RNG_Clock_Source RCCEx RNG Clock Source + * @{ + */ +#define RCC_RNGCLKSOURCE_LSE 0x00000000U +#define RCC_RNGCLKSOURCE_LSI RCC_CCIPR2_RNGSEL_0 +#define RCC_RNGCLKSOURCE_HSI RCC_CCIPR2_RNGSEL_1 +#define RCC_RNGCLKSOURCE_PLL1Q (RCC_CCIPR2_RNGSEL_0 | RCC_CCIPR2_RNGSEL_1) +/** + * @} + */ + + +#if defined (RCC_CCIPR2_ASSEL) +/** @defgroup RCCEx_AudioSync_Clock_Source Audio Sync Clock Source + * @{ + */ +#define RCC_ASCLKSOURCE_PLL1P 0x00000000U +#define RCC_ASCLKSOURCE_PLL1Q RCC_CCIPR2_ASSEL +/** + * @} + */ +#endif + +/** @defgroup RCCEx_LPUART1_Clock_Source LPUART1 Clock Source + * @{ + */ +#define RCC_LPUART1CLKSOURCE_PCLK7 0x00000000U +#define RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR3_LPUART1SEL_0 +#define RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR3_LPUART1SEL_1 +#define RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR3_LPUART1SEL_0 | RCC_CCIPR3_LPUART1SEL_1) +/** + * @} + */ + +/** @defgroup RCCEx_SPI3_Clock_Source SPI3 Clock Source + * @{ + */ +#define RCC_SPI3CLKSOURCE_PCLK7 0x00000000U +#define RCC_SPI3CLKSOURCE_SYSCLK RCC_CCIPR3_SPI3SEL_0 +#define RCC_SPI3CLKSOURCE_HSI RCC_CCIPR3_SPI3SEL_1 +/** + * @} + */ + +/** @defgroup RCCEx_I2C3_Clock_Source I2C3 Clock Source + * @{ + */ +#define RCC_I2C3CLKSOURCE_PCLK7 0x00000000U +#define RCC_I2C3CLKSOURCE_SYSCLK RCC_CCIPR3_I2C3SEL_0 +#define RCC_I2C3CLKSOURCE_HSI RCC_CCIPR3_I2C3SEL_1 +/** + * @} + */ + +/** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source + * @{ + */ +#define RCC_LPTIM1CLKSOURCE_PCLK7 0x00000000U +#define RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR3_LPTIM1SEL_0 +#define RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR3_LPTIM1SEL_1 +#define RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR3_LPTIM1SEL +/** + * @} + */ + +/** @defgroup RCCEx_ADC_Clock_Source ADC4 Clock Source + * @{ + */ +#define RCC_ADCCLKSOURCE_HCLK 0x00000000U +#define RCC_ADCCLKSOURCE_SYSCLK RCC_CCIPR3_ADCSEL_0 +#define RCC_ADCCLKSOURCE_PLL1P RCC_CCIPR3_ADCSEL_1 +#define RCC_ADCCLKSOURCE_HSE (RCC_CCIPR3_ADCSEL_0 | RCC_CCIPR3_ADCSEL_1) +#define RCC_ADCCLKSOURCE_HSI RCC_CCIPR3_ADCSEL_2 +/** + * @} + */ + +/** @defgroup RCC_RadioSleepTimer_Clock_Source Radio Sleep Timer Source + * @{ + */ +#define RCC_RADIOSTCLKSOURCE_DISABLE 0x00000000U /*!< No clock selected, 2.4 GHz RADIO sleep timer kernel clock disabled */ +#define RCC_RADIOSTCLKSOURCE_LSE RCC_BDCR1_RADIOSTSEL_0 /*!< LSE oscillator clock selected */ +#define RCC_RADIOSTCLKSOURCE_LSI RCC_BDCR1_RADIOSTSEL_1 /*!< LSI oscillator clock selected */ +#define RCC_RADIOSTCLKSOURCE_HSE_DIV1000 RCC_BDCR1_RADIOSTSEL /*!< HSE32 oscillator clock divided by 1000 selected */ +/** + * @} + */ + +/** @defgroup RCCEx_LSCO_Clock_Source Low Speed Clock Source + * @{ + */ +#define RCC_LSCOSOURCE_LSI 0x00000000U /*!< LSI selection for low speed clock output */ +#define RCC_LSCOSOURCE_LSE RCC_BDCR1_LSCOSEL /*!< LSE selection for low speed clock output */ +/** + * @} + */ + +/** @defgroup RCCEx_LSE_Trimming LSE Trimming + * @{ + */ +#define RCC_LSETRIMMING_R 0x00000000U /*!< Current source resistance R */ +#define RCC_LSETRIMMING_3_4_R RCC_BDCR1_LSETRIM_0 /*!< Current source resistance 3/4 * R */ +#define RCC_LSETRIMMING_2_3_R RCC_BDCR1_LSETRIM_1 /*!< Current source resistance 2/3 * R */ +#define RCC_LSETRIMMING_1_2_R RCC_BDCR1_LSETRIM /*!< Current source resistance 1/2 * R */ +/** + * @} + */ + +#if defined(RCC_LSI2_SUPPORT) +/** @defgroup RCCEx_LSI2_Frequency_Temperature_Sensitivity LSI2 Frequency Temperature Sensitivity + * @{ + */ +#define RCC_LSI2_FREQTEMPSENS_80 0x00000000U /*!< LSI2 frequency temperature sensitivity is close to zero at +80 degrees C */ +#define RCC_LSI2_FREQTEMPSENS_50 RCC_BDCR2_LSI2CFG_0 /*!< LSI2 frequency temperature sensitivity is close to zero at +50 degrees C */ +#define RCC_LSI2_FREQTEMPSENS_20 RCC_BDCR2_LSI2CFG_1 /*!< LSI2 frequency temperature sensitivity is close to zero at +20 degrees C */ +/** + * @} + */ + +/** @defgroup RCCEx_LSI2_Operating_Mode LSI2 Operating Mode + * @{ + */ +#define RCC_LSI2_MODE_NOMINAL 0x00000000U /*!< Nominal-power, high accuracy */ +#define RCC_LSI2_MODE_LP RCC_BDCR2_LSI2MODE_0 /*!< Low-power, medium accuracy */ +#define RCC_LSI2_MODE_ULP RCC_BDCR2_LSI2MODE_1 /*!< Ultra-low-power, low accuracy */ +/** + * @} + */ +#endif /* RCC_BDCR1_LSI2ON */ + + +/** @defgroup RCCEx_RADIO_Bus_Clock_Readiness 2.4 GHz RADIO bus clock readiness + * @{ + */ +#define RCC_RADIO_BUS_CLOCK_NOT_READY 0x00000000U /*!< 2.4 GHz RADIO bus clock not ready */ +#define RCC_RADIO_BUS_CLOCK_READY RCC_RADIOENR_RADIOCLKRDY /*!< 2.4 GHz RADIO bus clock ready */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros + * @{ + */ + +/** @brief Macro to configure the USART1 clock (USART1CLK). + * @param __USART1_CLKSOURCE__ specifies the USART1 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK1 selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock + * @retval None + */ +#define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_USART1SEL, (__USART1_CLKSOURCE__)) + +/** @brief Macro to get the USART1 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK1 selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock + * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock + */ +#define __HAL_RCC_GET_USART1_SOURCE() READ_BIT(RCC->CCIPR1, RCC_CCIPR1_USART1SEL) + +#if defined (USART2) +/** @brief Macro to configure the USART2 clock (USART2CLK). + * @param __USART2_CLKSOURCE__ specifies the USART2 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock + * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock + * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock + * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock + * @retval None + */ +#define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_USART2SEL, (__USART2_CLKSOURCE__)) + +/** @brief Macro to get the USART2 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock + * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock + * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock + * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock + */ +#define __HAL_RCC_GET_USART2_SOURCE() READ_BIT(RCC->CCIPR1, RCC_CCIPR1_USART2SEL) +#endif + + +#if defined (I2C1) +/** @brief Macro to configure the I2C1 clock (I2C1CLK). + * @param __I2C1_CLKSOURCE__ specifies the I2C1 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock + * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock + * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock + * @retval None + */ +#define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_I2C1SEL, (__I2C1_CLKSOURCE__)) + +/** @brief Macro to get the I2C1 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock + * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock + * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock + */ +#define __HAL_RCC_GET_I2C1_SOURCE() READ_BIT(RCC->CCIPR1, RCC_CCIPR1_I2C1SEL) +#endif + + + + +#if defined (LPTIM2) +/** @brief Macro to configure the LPTIM2 clock (LPTIM2CLK). + * @param __LPTIM2_CLKSOURCE__ specifies the LPTIM2 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1 PCLK1 selected as LPTIM2 clock + * @arg @ref RCC_LPTIM2CLKSOURCE_LSI LSI selected as LPTIM2 clock + * @arg @ref RCC_LPTIM2CLKSOURCE_HSI HSI selected as LPTIM2 clock + * @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPTIM2 clock + * @retval None + */ +#define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_LPTIM2SEL, (__LPTIM2_CLKSOURCE__)) + +/** @brief Macro to get the LPTIM2 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1 PCLK1 selected as LPTIM2 clock + * @arg @ref RCC_LPTIM2CLKSOURCE_LSI HSI selected as LPTIM2 clock + * @arg @ref RCC_LPTIM2CLKSOURCE_HSI HSI selected as LPTIM2 clock + * @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPTIM2 clock + */ +#define __HAL_RCC_GET_LPTIM2_SOURCE() READ_BIT(RCC->CCIPR1, RCC_CCIPR1_LPTIM2SEL) +#endif + +#if defined (SPI1) +/** @brief macro to configure the SPI1 clock source. + * @param __SPI1_CLKSOURCE__ specifies the SPI1 clock source. + * This parameter can be one of the following values: + * @arg RCC_SPI1CLKSOURCE_PCLK2 : PCLK2 Clock selected as SPI1 clock + * @arg RCC_SPI1CLKSOURCE_SYSCLK : SYSCLK Clock selected as SPI1 clock + * @arg RCC_SPI1CLKSOURCE_HSI : HSI Clock selected as SPI1 clock + */ +#define __HAL_RCC_SPI1_CONFIG(__SPI1_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_SPI1SEL, (__SPI1_CLKSOURCE__)) + +/** @brief macro to get the SPI1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SPI1CLKSOURCE_PCLK2 : PCLK2 Clock used as SPI1 clock + * @arg RCC_SPI1CLKSOURCE_SYSCLK : SYSCLK Clock used as SPI1 clock + * @arg RCC_SPI1CLKSOURCE_HSI : HSI Clock used as SPI1 clock + */ +#define __HAL_RCC_GET_SPI1_SOURCE() READ_BIT(RCC->CCIPR1, RCC_CCIPR1_SPI1SEL) +#endif + +/** @brief macro to configure the SYSTICK clock source. + * @param __SYSTICK_CLKSOURCE__ specifies the SYSTICK clock source. + * @arg RCC_SYSTICKCLKSOURCE_HCLK_DIV8 : HCLK divided by 8 Clock selected as SYSTICK clock + * @arg RCC_SYSTICKCLKSOURCE_LSI : LSI Clock selected as SYSTICK clock + * @arg RCC_SYSTICKCLKSOURCE_LSE : LSE Clock selected as SYSTICK clock + */ +#define __HAL_RCC_SYSTICK_CONFIG(__SYSTICK_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_SYSTICKSEL, (__SYSTICK_CLKSOURCE__)) + +/** @brief macro to get the SYSTICK clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SYSTICKCLKSOURCE_HCLK_DIV8 : HCLK divided by 8 Clock selected as SYSTICK clock + * @arg RCC_SYSTICKCLKSOURCE_LSI : LSI Clock selected as SYSTICK clock + * @arg RCC_SYSTICKCLKSOURCE_LSE : LSE Clock selected as SYSTICK clock + */ +#define __HAL_RCC_GET_SYSTICK_SOURCE() READ_BIT(RCC->CCIPR1, RCC_CCIPR1_SYSTICKSEL) + +/** @brief macro to configure the TIMIC clock source. + * @param __TIMIC_CLKSOURCE__ specifies the TIMIC clock source. + * @arg RCC_TIMICCLKSOURCE_HSI : HSI Clock selected as TIMIC clock + * @arg RCC_TIMICCLKSOURCE_HSI_DIV256 : HSI divided by 256 Clock selected as TIMIC clock + */ +#define __HAL_RCC_TIMIC_CONFIG(__TIMIC_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_TIMICSEL, (__TIMIC_CLKSOURCE__)) + +/** @brief macro to get the TIMIC clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_TIMICCLKSOURCE_HSI : HSI Clock selected as TIMIC clock + * @arg RCC_TIMICCLKSOURCE_HSI_DIV256 : HSI divided by 256 Clock selected as TIMIC clock + */ +#define __HAL_RCC_GET_TIMIC_SOURCE() READ_BIT(RCC->CCIPR1, RCC_CCIPR1_TIMICSEL) + +#if defined (SAI1) +/** + * @brief Macro to configure the SAI1 clock source. + * @param __SAI1_CLKSOURCE__ defines the SAI1 clock source. This clock is derived + * from the PLL2, system PLL1 or external clock (through a dedicated pin). + * This parameter can be one of the following values: + * @arg @ref RCC_SAI1CLKSOURCE_PLL1P SAI1 clock = PLL1 "P" clock (PLL1PCLK) + * @arg @ref RCC_SAI1CLKSOURCE_PLL1Q SAI1 clock = PLL1 "Q" clock (PLL1QCLK) + * @arg @ref RCC_SAI1CLKSOURCE_SYSCLK SAI1 clock = System Clock + * @arg @ref RCC_SAI1CLKSOURCE_PIN SAI1 clock = External Clock (SAI1_EXTCLK) + * @arg @ref RCC_SAI1CLKSOURCE_HSI SAI1 clock = HSI16 + * @retval None + */ +#define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SAI1SEL, (__SAI1_CLKSOURCE__)) + +/** @brief Macro to get the SAI1 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_SAI1CLKSOURCE_PLL1P SAI1 clock = PLL1 "P" clock (PLL1PCLK) + * @arg @ref RCC_SAI1CLKSOURCE_PLL1Q SAI1 clock = PLL1 "Q" clock (PLL1QCLK) + * @arg @ref RCC_SAI1CLKSOURCE_SYSCLK SAI1 clock = System Clock + * @arg @ref RCC_SAI1CLKSOURCE_PIN SAI1 clock = External Clock (SAI1_EXTCLK) + * @arg @ref RCC_SAI1CLKSOURCE_HSI SAI1 clock = HSI16 + */ +#define __HAL_RCC_GET_SAI1_SOURCE() READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SAI1SEL) +#endif + + +#if defined (RCC_CCIPR2_ASSEL) +/** @brief macro to configure the Audio Sync clock source. + * @param __AS_CLKSOURCE__ specifies the Audio Sync clock source. + * @arg RCC_ASCLKSOURCE_PLL1P : PLL1P Clock selected as Audio Sync clock + * @arg RCC_ASCLKSOURCE_PLL1Q : PLL1Q Clock selected as Audio Sync clock + */ +#define __HAL_RCC_AUDIOSYNC_CONFIG(__AS_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_ASSEL, (__AS_CLKSOURCE__)) + +/** @brief macro to get the Audio Sync clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_ASCLKSOURCE_PLL1P : PLL1P Clock selected as Audio Sync clock + * @arg RCC_ASCLKSOURCE_PLL1Q : PLL1Q Clock selected as Audio Sync clock + */ +#define __HAL_RCC_GET_AUDIOSYNC_SOURCE() READ_BIT(RCC->CCIPR2, RCC_CCIPR2_ASSEL) +#endif + +/** @brief macro to configure the RNG clock (RNGCLK). + * @param __RNG_CLKSOURCE__: specifies the RNG clock source. + * This parameter can be one of the following values: + * @arg RCC_RNGCLKSOURCE_HSI: HSI selected as RNG clock + * @arg RCC_RNGCLKSOURCE_LSI: LSI selected as RNG clock + * @arg RCC_RNGCLKSOURCE_LSE: LSE selected as RNG clock + * @arg RCC_RNGCLKSOURCE_PLL1Q: PLL1Q selected as RNG clock + * @retval None + */ +#define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_RNGSEL, (__RNG_CLKSOURCE__)) + +/** @brief macro to get the RNG clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_RNGCLKSOURCE_HSI: HSI selected as RNG clock + * @arg RCC_RNGCLKSOURCE_LSI: LSI selected as RNG clock + * @arg RCC_RNGCLKSOURCE_LSE: LSE selected as RNG clock + * @arg RCC_RNGCLKSOURCE_PLL1Q: PLL1Q selected as RNG clock + */ +#define __HAL_RCC_GET_RNG_SOURCE() READ_BIT(RCC->CCIPR2, RCC_CCIPR2_RNGSEL) + +/** @brief Macro to configure the LPUART1 clock (LPUART1CLK). + * @param __LPUART1_CLKSOURCE__ specifies the LPUART1 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_LPUART1CLKSOURCE_PCLK7 PCLK7 selected as LPUART1 clock + * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock + * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock + * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock + * @retval None + */ +#define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_LPUART1SEL, (__LPUART1_CLKSOURCE__)) + +/** @brief Macro to get the LPUART1 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_LPUART1CLKSOURCE_PCLK7 PCLK7 selected as LPUART1 clock + * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock + * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock + * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock + */ +#define __HAL_RCC_GET_LPUART1_SOURCE() READ_BIT(RCC->CCIPR3, RCC_CCIPR3_LPUART1SEL) + +/** @brief macro to configure the SPI3 clock source. + * @param __SPI3_CLKSOURCE__ specifies the SPI3 clock source.es: + * @arg RCC_SPI3CLKSOURCE_PCLK7 : PCLK7 selected as SPI3 clock + * @arg RCC_SPI3CLKSOURCE_SYSCLK : SYSCLK Clock selected as SPI3 clock + * @arg RCC_SPI3CLKSOURCE_HSI : HSI Clock selected as SPI3 clock + */ +#define __HAL_RCC_SPI3_CONFIG(__SPI3_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_SPI3SEL, (__SPI3_CLKSOURCE__)) + +/** @brief macro to get the SPI3 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SPI3CLKSOURCE_PCLK7 : PCLK7 selected as SPI3 clock + * @arg RCC_SPI3CLKSOURCE_SYSCLK : SYSCLK Clock selected as SPI3 clock + * @arg RCC_SPI3CLKSOURCE_HSI : HSI Clock selected as SPI3 clock + */ +#define __HAL_RCC_GET_SPI3_SOURCE() READ_BIT(RCC->CCIPR3, RCC_CCIPR3_SPI3SEL) + +/** @brief Macro to configure the I2C3 clock (I2C3CLK). + * @param __I2C3_CLKSOURCE__ specifies the I2C3 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_I2C3CLKSOURCE_PCLK7 : PCLK7 selected as I2C3 clock + * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK : HSI selected as I2C3 clock + * @arg @ref RCC_I2C3CLKSOURCE_HSI : MSIK selected as I2C3 clock + * @retval None + */ +#define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_I2C3SEL, (__I2C3_CLKSOURCE__)) + +/** @brief Macro to get the I2C3 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_I2C3CLKSOURCE_PCLK7 : PCLK7 selected as I2C3 clock + * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK : HSI selected as I2C3 clock + * @arg @ref RCC_I2C3CLKSOURCE_HSI : MSIK selected as I2C3 clock + */ +#define __HAL_RCC_GET_I2C3_SOURCE() READ_BIT(RCC->CCIPR3, RCC_CCIPR3_I2C3SEL) + + +/** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK). + * @param __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK7 PCLK7 selected as LPTIM1 clock + * @arg @ref RCC_LPTIM1CLKSOURCE_LSI LSI selected as LPTIM1 clock + * @arg @ref RCC_LPTIM1CLKSOURCE_HSI HSI selected as LPTIM1 clock + * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock + * @retval None + */ +#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_LPTIM1SEL, (__LPTIM1_CLKSOURCE__)) + +/** @brief Macro to get the LPTIM1 clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_LPTIM1CLKSOURCE_PCLK7 PCLK7 selected as LPTIM1 clock + * @arg @ref RCC_LPTIM1CLKSOURCE_LSI LSI selected as LPTIM1 clock + * @arg @ref RCC_LPTIM1CLKSOURCE_HSI HSI selected as LPTIM1 clock + * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock + */ +#define __HAL_RCC_GET_LPTIM1_SOURCE() READ_BIT(RCC->CCIPR3, RCC_CCIPR3_LPTIM1SEL) + +/** @brief Macro to configure the ADC4 interface clock. + * @param __ADC_CLKSOURCE__ specifies the ADC4 digital interface clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_ADCCLKSOURCE_HCLK HCLK clock selected as ADC4 clock + * @arg @ref RCC_ADCCLKSOURCE_SYSCLK SYSCLK clock selected as ADC4 clock + * @arg @ref RCC_ADCCLKSOURCE_PLL1P PLL1P clock selected as ADC4 clock + * @arg @ref RCC_ADCCLKSOURCE_HSE HSE clock selected as ADC4 clock + * @arg @ref RCC_ADCCLKSOURCE_HSI HSI clock selected as ADC4 clock + * @retval None + */ +#define __HAL_RCC_ADC_CONFIG(__ADC_CLKSOURCE__) \ + MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_ADCSEL, (__ADC_CLKSOURCE__)) + +/** @brief Macro to get the ADC clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_ADCCLKSOURCE_HCLK HCLK clock used as ADC4 clock + * @arg @ref RCC_ADCCLKSOURCE_SYSCLK SYSCLK clock used as ADC4 clock + * @arg @ref RCC_ADCCLKSOURCE_PLL1P PLL1P clock used as ADC4 clock + * @arg @ref RCC_ADCCLKSOURCE_HSE HSE clock used as ADC4 clock + * @arg @ref RCC_ADCCLKSOURCE_HSI HSI clock used as ADC4 clock + */ +#define __HAL_RCC_GET_ADC_SOURCE() READ_BIT(RCC->CCIPR3, RCC_CCIPR3_ADCSEL) + +/** @brief Macro to configure the RADIO Sleep timer clock source. + * @param __RADIOST_CLKSOURCE__ specifies the Radio sleep timer clock source. + * This parameter can be one of the following values: + * @arg @ref RCC_RADIOSTCLKSOURCE_DISABLE 2.4 GHz RADIO sleep timer kernel clock disabled + * @arg @ref RCC_RADIOSTCLKSOURCE_LSE LSE oscillator clock selected + * @arg @ref RCC_RADIOSTCLKSOURCE_LSI LSI oscillator clock selected + * @arg @ref RCC_RADIOSTCLKSOURCE_HSE_DIV1000 HSE32 oscillator clock divided by 1000 selected + * @retval None + */ +#define __HAL_RCC_RADIOSLPTIM_CONFIG(__RADIOST_CLKSOURCE__) \ + MODIFY_REG(RCC->BDCR1, RCC_BDCR1_RADIOSTSEL, (__RADIOST_CLKSOURCE__)) + +/** @brief Macro to get the RADIO Sleep timer clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_RADIOSTCLKSOURCE_DISABLE 2.4 GHz RADIO sleep timer kernel clock disabled + * @arg @ref RCC_RADIOSTCLKSOURCE_LSE LSE oscillator clock selected + * @arg @ref RCC_RADIOSTCLKSOURCE_LSI LSI oscillator clock selected + * @arg @ref RCC_RADIOSTCLKSOURCE_HSE_DIV1000 HSE32 oscillator clock divided by 1000 selected + */ +#define __HAL_RCC_GET_RADIOSLPTIM_SOURCE() READ_BIT(RCC->BDCR1, RCC_BDCR1_RADIOSTSEL) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RCCEx_Exported_Functions + * @{ + */ + +/** @addtogroup RCCEx_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef *PeriphClkInit); +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); +/** + * @} + */ + +/** @addtogroup RCCEx_Exported_Functions_Group2 + * @{ + */ +void HAL_RCCEx_EnableLSECSS(void); +void HAL_RCCEx_DisableLSECSS(void); +void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource); +void HAL_RCCEx_DisableLSCO(void); +void HAL_RCCEx_HSESetTrimming(uint32_t Trimming); +uint32_t HAL_RCCEx_HSEGetTrimming(void); +void HAL_RCCEx_LSESetTrimming(uint32_t Trimming); +uint32_t HAL_RCCEx_LSEGetTrimming(void); +#if defined(RCC_LSI2_SUPPORT) +void HAL_RCCEx_LSI2SetConfig(const RCC_LSIConfigTypeDef *pConfig); +void HAL_RCCEx_LSI2GetConfig(RCC_LSIConfigTypeDef *pConfig); +#endif /* RCC_BDCR1_LSI2ON */ +/** + * @} + */ + +/** @addtogroup RCCEx_Exported_Functions_Group3 + * @{ + */ +void HAL_RCCEx_EnableRadioBBClock(void); +void HAL_RCCEx_DisableRadioBBClock(void); +void HAL_RCCEx_EnableRequestUponRadioWakeUpEvent(void); +void HAL_RCCEx_DisableRequestUponRadioWakeUpEvent(void); +uint32_t HAL_RCCEx_GetRadioBusClockReadiness(void); +/** + * @} + */ + +/** + * @} + */ +/** @addtogroup RCCEx_Private_Constants + * @{ + */ +/* Define used for IS_RCC_* macros below */ +#if defined (STM32WBA54xx) || defined (STM32WBA55xx) +#if !defined (STM32WBAXX_SI_CUT1_0) +#define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_I2C1 | \ + RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SYSTICK | \ + RCC_PERIPHCLK_TIMIC | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_RNG | \ + RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_I2C3 | \ + RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_RTC | \ + RCC_PERIPHCLK_RADIOST | RCC_PERIPHCLK_AUDIOSYNC) +#else +#define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_I2C1 | \ + RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SYSTICK | \ + RCC_PERIPHCLK_TIMIC | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_RNG | \ + RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_I2C3 | \ + RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_RTC | \ + RCC_PERIPHCLK_RADIOST) +#endif +#elif defined (STM32WBA52xx) +#define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_I2C1 | \ + RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SYSTICK | \ + RCC_PERIPHCLK_TIMIC | RCC_PERIPHCLK_RNG | \ + RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_I2C3 | \ + RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_RTC | \ + RCC_PERIPHCLK_RADIOST) +#elif defined (STM32WBA50xx) +#define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | \ + RCC_PERIPHCLK_SYSTICK | \ + RCC_PERIPHCLK_TIMIC | RCC_PERIPHCLK_RNG | \ + RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_I2C3 | \ + RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_RTC | \ + RCC_PERIPHCLK_RADIOST) +#endif +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup RCCEx_Private_Macros + * @{ + */ +#define IS_RCC_PERIPHCLOCK(__SELECTION__) ((((__SELECTION__) & RCC_PERIPHCLOCK_ALL) != 0x00u) && \ + (((__SELECTION__) & ~RCC_PERIPHCLOCK_ALL) == 0x00u)) + +#define IS_RCC_USART1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \ + ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE)) + +#if defined(USART2) +#define IS_RCC_USART2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE)) +#endif + + +#if defined(I2C1) +#define IS_RCC_I2C1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI)) +#endif + + + + +#if defined (LPTIM2) +#define IS_RCC_LPTIM2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE)) +#endif + +#define IS_RCC_LPTIM1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK7) || \ + ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE)) + +#if defined (SPI1) +#define IS_RCC_SPI1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SPI1CLKSOURCE_PCLK2) || \ + ((__SOURCE__) == RCC_SPI1CLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_SPI1CLKSOURCE_HSI)) +#endif + +#define IS_RCC_SYSTICKCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSTICKCLKSOURCE_HCLK_DIV8) || \ + ((__SOURCE__) == RCC_SYSTICKCLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_SYSTICKCLKSOURCE_LSE)) + +#define IS_RCC_TIMICCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_TIMICCLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_TIMICCLKSOURCE_HSI_DIV256)) + +#if defined(SAI1) +#define IS_RCC_SAI1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL1P) || \ + ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL1Q) || \ + ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN) || \ + ((__SOURCE__) == RCC_SAI1CLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_SAI1CLKSOURCE_HSI)) +#endif + +#define IS_RCC_RNGCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RNGCLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_RNGCLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_RNGCLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL1Q)) + + +#if defined (RCC_CCIPR2_ASSEL) +#define IS_RCC_ASCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_ASCLKSOURCE_PLL1P) || \ + ((__SOURCE__) == RCC_ASCLKSOURCE_PLL1Q)) +#endif + +#define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK7) || \ + ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE)) + +#define IS_RCC_SPI3CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SPI3CLKSOURCE_PCLK7) || \ + ((__SOURCE__) == RCC_SPI3CLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_SPI3CLKSOURCE_HSI)) + +#define IS_RCC_I2C3CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK7) || \ + ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK ) || \ + ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI)) + +#define IS_RCC_ADCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_ADCCLKSOURCE_HCLK) || \ + ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_ADCCLKSOURCE_PLL1P) || \ + ((__SOURCE__) == RCC_ADCCLKSOURCE_HSE) || \ + ((__SOURCE__) == RCC_ADCCLKSOURCE_HSI)) + +#define IS_RCC_RADIOSLEEPTIMERSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RADIOSTCLKSOURCE_DISABLE) || \ + ((__SOURCE__) == RCC_RADIOSTCLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_RADIOSTCLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_RADIOSTCLKSOURCE_HSE_DIV1000)) + +#define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \ + ((__SOURCE__) == RCC_LSCOSOURCE_LSE)) + +#define IS_RCC_HSETRIM(__TRIM__) ((__TRIM__) <= (RCC_ECSCR1_HSETRIM >> RCC_ECSCR1_HSETRIM_Pos)) + +#define IS_RCC_LSETRIM(__SOURCE__) (((__SOURCE__) == RCC_LSETRIMMING_R) || \ + ((__SOURCE__) == RCC_LSETRIMMING_3_4_R) || \ + ((__SOURCE__) == RCC_LSETRIMMING_2_3_R) || \ + ((__SOURCE__) == RCC_LSETRIMMING_1_2_R)) + +#if defined(RCC_LSI2_SUPPORT) +#define IS_RCC_LSI2_FREQTEMPSENS(__SENS__) (((__SENS__) == RCC_LSI2_FREQTEMPSENS_80) || \ + ((__SENS__) == RCC_LSI2_FREQTEMPSENS_50) || \ + ((__SENS__) == RCC_LSI2_FREQTEMPSENS_20)) + +#define IS_RCC_LSI2_OPERATINGMODE(__MODE__) (((__MODE__) == RCC_LSI2_MODE_NOMINAL) || \ + ((__MODE__) == RCC_LSI2_MODE_LP) || \ + ((__MODE__) == RCC_LSI2_MODE_ULP)) +#endif /* RCC_BDCR1_LSI2ON */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** +* @} +*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32WBAxx_HAL_RCC_EX_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rng.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rng.h new file mode 100644 index 0000000000..c6e13320e4 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rng.h @@ -0,0 +1,388 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_rng.h + * @author MCD Application Team + * @brief Header file of RNG HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_HAL_RNG_H +#define STM32WBAxx_HAL_RNG_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal_def.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +#if defined (RNG) + +/** @defgroup RNG RNG + * @brief RNG HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup RNG_Exported_Types RNG Exported Types + * @{ + */ + +/** @defgroup RNG_Exported_Types_Group1 RNG Init Structure definition + * @{ + */ +typedef struct +{ + uint32_t ClockErrorDetection; /*!< CED Clock error detection */ +} RNG_InitTypeDef; + +/** + * @} + */ + +/** @defgroup RNG_Exported_Types_Group2 RNG State Structure definition + * @{ + */ +typedef enum +{ + HAL_RNG_STATE_RESET = 0x00U, /*!< RNG not yet initialized or disabled */ + HAL_RNG_STATE_READY = 0x01U, /*!< RNG initialized and ready for use */ + HAL_RNG_STATE_BUSY = 0x02U, /*!< RNG internal process is ongoing */ + HAL_RNG_STATE_TIMEOUT = 0x03U, /*!< RNG timeout state */ + HAL_RNG_STATE_ERROR = 0x04U /*!< RNG error state */ + +} HAL_RNG_StateTypeDef; + +/** + * @} + */ + +/** @defgroup RNG_Exported_Types_Group3 RNG Handle Structure definition + * @{ + */ +#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) +typedef struct __RNG_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ +{ + RNG_TypeDef *Instance; /*!< Register base address */ + + RNG_InitTypeDef Init; /*!< RNG configuration parameters */ + + HAL_LockTypeDef Lock; /*!< RNG locking object */ + + __IO HAL_RNG_StateTypeDef State; /*!< RNG communication state */ + + __IO uint32_t ErrorCode; /*!< RNG Error code */ + + uint32_t RandomNumber; /*!< Last Generated RNG Data */ + +#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) + void (* ReadyDataCallback)(struct __RNG_HandleTypeDef *hrng, uint32_t random32bit); /*!< RNG Data Ready Callback */ + void (* ErrorCallback)(struct __RNG_HandleTypeDef *hrng); /*!< RNG Error Callback */ + + void (* MspInitCallback)(struct __RNG_HandleTypeDef *hrng); /*!< RNG Msp Init callback */ + void (* MspDeInitCallback)(struct __RNG_HandleTypeDef *hrng); /*!< RNG Msp DeInit callback */ +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ + +} RNG_HandleTypeDef; + +#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) +/** + * @brief HAL RNG Callback ID enumeration definition + */ +typedef enum +{ + HAL_RNG_ERROR_CB_ID = 0x00U, /*!< RNG Error Callback ID */ + + HAL_RNG_MSPINIT_CB_ID = 0x01U, /*!< RNG MspInit callback ID */ + HAL_RNG_MSPDEINIT_CB_ID = 0x02U /*!< RNG MspDeInit callback ID */ + +} HAL_RNG_CallbackIDTypeDef; + +/** + * @brief HAL RNG Callback pointer definition + */ +typedef void (*pRNG_CallbackTypeDef)(RNG_HandleTypeDef *hrng); /*!< pointer to a common RNG callback function */ +typedef void (*pRNG_ReadyDataCallbackTypeDef)(RNG_HandleTypeDef *hrng, uint32_t random32bit); /*!< pointer to an RNG Data Ready specific callback function */ + +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RNG_Exported_Constants RNG Exported Constants + * @{ + */ + +/** @defgroup RNG_Exported_Constants_Group1 RNG Interrupt definition + * @{ + */ +#define RNG_IT_DRDY RNG_SR_DRDY /*!< Data Ready interrupt */ +#define RNG_IT_CEI RNG_SR_CEIS /*!< Clock error interrupt */ +#define RNG_IT_SEI RNG_SR_SEIS /*!< Seed error interrupt */ +/** + * @} + */ + +/** @defgroup RNG_Exported_Constants_Group2 RNG Flag definition + * @{ + */ +#define RNG_FLAG_DRDY RNG_SR_DRDY /*!< Data ready */ +#define RNG_FLAG_CECS RNG_SR_CECS /*!< Clock error current status */ +#define RNG_FLAG_SECS RNG_SR_SECS /*!< Seed error current status */ +/** + * @} + */ + +/** @defgroup RNG_Exported_Constants_Group3 RNG Clock Error Detection + * @{ + */ +#define RNG_CED_ENABLE 0x00000000U /*!< Clock error detection Enabled */ +#define RNG_CED_DISABLE RNG_CR_CED /*!< Clock error detection Disabled */ +/** + * @} + */ + +/** @defgroup RNG_Error_Definition RNG Error Definition + * @{ + */ +#define HAL_RNG_ERROR_NONE 0x00000000U /*!< No error */ +#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) +#define HAL_RNG_ERROR_INVALID_CALLBACK 0x00000001U /*!< Invalid Callback error */ +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ +#define HAL_RNG_ERROR_TIMEOUT 0x00000002U /*!< Timeout error */ +#define HAL_RNG_ERROR_BUSY 0x00000004U /*!< Busy error */ +#define HAL_RNG_ERROR_SEED 0x00000008U /*!< Seed error */ +#define HAL_RNG_ERROR_CLOCK 0x00000010U /*!< Clock error */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup RNG_Exported_Macros RNG Exported Macros + * @{ + */ + +/** @brief Reset RNG handle state + * @param __HANDLE__ RNG Handle + * @retval None + */ +#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) +#define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_RNG_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0U) +#else +#define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET) +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ + +/** + * @brief Enables the RNG peripheral. + * @param __HANDLE__ RNG Handle + * @retval None + */ +#define __HAL_RNG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_RNGEN) + +/** + * @brief Disables the RNG peripheral. + * @param __HANDLE__ RNG Handle + * @retval None + */ +#define __HAL_RNG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN) + +/** + * @brief Check the selected RNG flag status. + * @param __HANDLE__ RNG Handle + * @param __FLAG__ RNG flag + * This parameter can be one of the following values: + * @arg RNG_FLAG_DRDY: Data ready + * @arg RNG_FLAG_CECS: Clock error current status + * @arg RNG_FLAG_SECS: Seed error current status + * @retval The new state of __FLAG__ (SET or RESET). + */ +#define __HAL_RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) + +/** + * @brief Clears the selected RNG flag status. + * @param __HANDLE__ RNG handle + * @param __FLAG__ RNG flag to clear + * @note WARNING: This is a dummy macro for HAL code alignment, + * flags RNG_FLAG_DRDY, RNG_FLAG_CECS and RNG_FLAG_SECS are read-only. + * @retval None + */ +#define __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__) /* dummy macro */ + +/** + * @brief Enables the RNG interrupts. + * @param __HANDLE__ RNG Handle + * @retval None + */ +#define __HAL_RNG_ENABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_IE) + +/** + * @brief Disables the RNG interrupts. + * @param __HANDLE__ RNG Handle + * @retval None + */ +#define __HAL_RNG_DISABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE) + +/** + * @brief Checks whether the specified RNG interrupt has occurred or not. + * @param __HANDLE__ RNG Handle + * @param __INTERRUPT__ specifies the RNG interrupt status flag to check. + * This parameter can be one of the following values: + * @arg RNG_IT_DRDY: Data ready interrupt + * @arg RNG_IT_CEI: Clock error interrupt + * @arg RNG_IT_SEI: Seed error interrupt + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_RNG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__)) + +/** + * @brief Clear the RNG interrupt status flags. + * @param __HANDLE__ RNG Handle + * @param __INTERRUPT__ specifies the RNG interrupt status flag to clear. + * This parameter can be one of the following values: + * @arg RNG_IT_CEI: Clock error interrupt + * @arg RNG_IT_SEI: Seed error interrupt + * @note RNG_IT_DRDY flag is read-only, reading RNG_DR register automatically clears RNG_IT_DRDY. + * @retval None + */ +#define __HAL_RNG_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR) = ~(__INTERRUPT__)) + +/** + * @} + */ + +/* Include RNG HAL Extended module */ +#include "stm32wbaxx_hal_rng_ex.h" +/* Exported functions --------------------------------------------------------*/ +/** @defgroup RNG_Exported_Functions RNG Exported Functions + * @{ + */ + +/** @defgroup RNG_Exported_Functions_Group1 Initialization and configuration functions + * @{ + */ +HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng); +HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng); +void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng); +void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID, + pRNG_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_RNG_RegisterReadyDataCallback(RNG_HandleTypeDef *hrng, pRNG_ReadyDataCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback(RNG_HandleTypeDef *hrng); +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup RNG_Exported_Functions_Group2 Peripheral Control functions + * @{ + */ +HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit); +HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng); +uint32_t HAL_RNG_ReadLastRandomNumber(const RNG_HandleTypeDef *hrng); + +void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng); +void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng); +void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit); + +/** + * @} + */ + +/** @defgroup RNG_Exported_Functions_Group3 Peripheral State functions + * @{ + */ +HAL_RNG_StateTypeDef HAL_RNG_GetState(const RNG_HandleTypeDef *hrng); +uint32_t HAL_RNG_GetError(const RNG_HandleTypeDef *hrng); +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup RNG_Private_Macros RNG Private Macros + * @{ + */ +#define IS_RNG_IT(IT) (((IT) == RNG_IT_CEI) || \ + ((IT) == RNG_IT_SEI)) + +#define IS_RNG_FLAG(FLAG) (((FLAG) == RNG_FLAG_DRDY) || \ + ((FLAG) == RNG_FLAG_CECS) || \ + ((FLAG) == RNG_FLAG_SECS)) + +/** + * @brief Verify the RNG Clock Error Detection mode. + * @param __MODE__ RNG Clock Error Detection mode + * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) + */ +#define IS_RNG_CED(__MODE__) (((__MODE__) == RNG_CED_ENABLE) || \ + ((__MODE__) == RNG_CED_DISABLE)) +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup RNG_Private_Functions RNG Private functions + * @{ + */ +HAL_StatusTypeDef RNG_RecoverSeedError(RNG_HandleTypeDef *hrng); +/** + * @} + */ +/** + * @} + */ + +#endif /* RNG */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32WBAxx_HAL_RNG_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rng_ex.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rng_ex.h new file mode 100644 index 0000000000..6cc6a399f0 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rng_ex.h @@ -0,0 +1,262 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_rng_ex.h + * @author MCD Application Team + * @brief Header file of RNG HAL Extension module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_HAL_RNG_EX_H +#define STM32WBAxx_HAL_RNG_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal_def.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +#if defined(RNG) +#if defined(RNG_CR_CONDRST) + +/** @defgroup RNG_Ex RNG_Ex + * @brief RNG Extension HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup RNG_Ex_Exported_Types RNG_Ex Exported Types + * @brief RNG_Ex Exported types + * @{ + */ + +/** + * @brief RNG_Ex Configuration Structure definition + */ + +typedef struct +{ + uint32_t Config1; /*!< Config1 must be a value between 0 and 0x3F */ + uint32_t Config2; /*!< Config2 must be a value between 0 and 0x7 */ + uint32_t Config3; /*!< Config3 must be a value between 0 and 0xF */ + uint32_t ClockDivider; /*!< Clock Divider factor.This parameter can + be a value of @ref RNG_Ex_Clock_Divider_Factor */ + uint32_t NistCompliance; /*!< NIST compliance.This parameter can be a + value of @ref RNG_Ex_NIST_Compliance */ + uint32_t AutoReset; /*!< automatic reset When a noise source error occurs + value of @ref RNG_Ex_Auto_Reset */ + uint32_t HealthTest; /*!< RNG health test control must be a value + between 0x0FFCABFF and 0x00005200 */ +} RNG_ConfigTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RNG_Ex_Exported_Constants RNG_Ex Exported Constants + * @{ + */ + +/** @defgroup RNG_Ex_Clock_Divider_Factor Value used to configure an internal + * programmable divider acting on the incoming RNG clock + * @{ + */ +#define RNG_CLKDIV_BY_1 (0x00000000UL) /*!< No clock division */ +#define RNG_CLKDIV_BY_2 (RNG_CR_CLKDIV_0) +/*!< 2 RNG clock cycles per internal RNG clock */ +#define RNG_CLKDIV_BY_4 (RNG_CR_CLKDIV_1) +/*!< 4 RNG clock cycles per internal RNG clock */ +#define RNG_CLKDIV_BY_8 (RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0) +/*!< 8 RNG clock cycles per internal RNG clock */ +#define RNG_CLKDIV_BY_16 (RNG_CR_CLKDIV_2) +/*!< 16 RNG clock cycles per internal RNG clock */ +#define RNG_CLKDIV_BY_32 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0) +/*!< 32 RNG clock cycles per internal RNG clock */ +#define RNG_CLKDIV_BY_64 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1) +/*!< 64 RNG clock cycles per internal RNG clock */ +#define RNG_CLKDIV_BY_128 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0) +/*!< 128 RNG clock cycles per internal RNG clock */ +#define RNG_CLKDIV_BY_256 (RNG_CR_CLKDIV_3) +/*!< 256 RNG clock cycles per internal RNG clock */ +#define RNG_CLKDIV_BY_512 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_0) +/*!< 512 RNG clock cycles per internal RNG clock */ +#define RNG_CLKDIV_BY_1024 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1) +/*!< 1024 RNG clock cycles per internal RNG clock */ +#define RNG_CLKDIV_BY_2048 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0) +/*!< 2048 RNG clock cycles per internal RNG clock */ +#define RNG_CLKDIV_BY_4096 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2) +/*!< 4096 RNG clock cycles per internal RNG clock */ +#define RNG_CLKDIV_BY_8192 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0) +/*!< 8192 RNG clock cycles per internal RNG clock */ +#define RNG_CLKDIV_BY_16384 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1) +/*!< 16384 RNG clock cycles per internal RNG clock */ +#define RNG_CLKDIV_BY_32768 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0) +/*!< 32768 RNG clock cycles per internal RNG clock */ +/** + * @} + */ + +/** @defgroup RNG_Ex_NIST_Compliance NIST Compliance configuration + * @{ + */ +#define RNG_NIST_COMPLIANT (0x00000000UL) /*!< NIST compliant configuration*/ +#define RNG_CUSTOM_NIST (RNG_CR_NISTC) /*!< Custom NIST configuration */ + +/** + * @} + */ +/** @defgroup RNG_Ex_Auto_Reset Auto Reset configuration + * @{ + */ +#define RNG_ARDIS_ENABLE (0x00000000UL) /*!< automatic reset after seed error*/ +#define RNG_ARDIS_DISABLE (RNG_CR_ARDIS) /*!< Disable automatic reset after seed error */ + +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/** @defgroup RNG_Ex_Private_Types RNG_Ex Private Types + * @{ + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup RNG_Ex_Private_Variables RNG_Ex Private Variables + * @{ + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup RNG_Ex_Private_Constants RNG_Ex Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup RNG_Ex_Private_Macros RNG_Ex Private Macros + * @{ + */ + +#define IS_RNG_CLOCK_DIVIDER(__CLOCK_DIV__) (((__CLOCK_DIV__) == RNG_CLKDIV_BY_1) || \ + ((__CLOCK_DIV__) == RNG_CLKDIV_BY_2) || \ + ((__CLOCK_DIV__) == RNG_CLKDIV_BY_4) || \ + ((__CLOCK_DIV__) == RNG_CLKDIV_BY_8) || \ + ((__CLOCK_DIV__) == RNG_CLKDIV_BY_16) || \ + ((__CLOCK_DIV__) == RNG_CLKDIV_BY_32) || \ + ((__CLOCK_DIV__) == RNG_CLKDIV_BY_64) || \ + ((__CLOCK_DIV__) == RNG_CLKDIV_BY_128) || \ + ((__CLOCK_DIV__) == RNG_CLKDIV_BY_256) || \ + ((__CLOCK_DIV__) == RNG_CLKDIV_BY_512) || \ + ((__CLOCK_DIV__) == RNG_CLKDIV_BY_1024) || \ + ((__CLOCK_DIV__) == RNG_CLKDIV_BY_2048) || \ + ((__CLOCK_DIV__) == RNG_CLKDIV_BY_4096) || \ + ((__CLOCK_DIV__) == RNG_CLKDIV_BY_8192) || \ + ((__CLOCK_DIV__) == RNG_CLKDIV_BY_16384) || \ + ((__CLOCK_DIV__) == RNG_CLKDIV_BY_32768)) + + +#define IS_RNG_NIST_COMPLIANCE(__NIST_COMPLIANCE__) (((__NIST_COMPLIANCE__) == RNG_NIST_COMPLIANT) || \ + ((__NIST_COMPLIANCE__) == RNG_CUSTOM_NIST)) + +#define IS_RNG_CONFIG1(__CONFIG1__) ((__CONFIG1__) <= 0x3FUL) + +#define IS_RNG_CONFIG2(__CONFIG2__) ((__CONFIG2__) <= 0x07UL) + +#define IS_RNG_CONFIG3(__CONFIG3__) ((__CONFIG3__) <= 0xFUL) +#define IS_RNG_ARDIS(__ARDIS__) (((__ARDIS__) == RNG_ARDIS_ENABLE) || \ + ((__ARDIS__) == RNG_ARDIS_DISABLE)) + + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup RNG_Ex_Private_Functions RNG_Ex Private Functions + * @{ + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RNG_Ex_Exported_Functions + * @{ + */ + +/** @addtogroup RNG_Ex_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, const RNG_ConfigTypeDef *pConf); +HAL_StatusTypeDef HAL_RNGEx_GetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef *pConf); +HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng); + +/** + * @} + */ + +/** @addtogroup RNG_Ex_Exported_Functions_Group2 + * @{ + */ +HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* RNG_CR_CONDRST */ +#endif /* RNG */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32WBAxx_HAL_RNG_EX_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rtc.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rtc.h new file mode 100644 index 0000000000..eea5b45652 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rtc.h @@ -0,0 +1,966 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_rtc.h + * @author MCD Application Team + * @brief Header file of RTC HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_HAL_RTC_H +#define STM32WBAxx_HAL_RTC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal_def.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @defgroup RTC RTC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup RTC_Exported_Types RTC Exported Types + * @{ + */ + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_RTC_STATE_RESET = 0x00U, /*!< RTC not yet initialized or disabled */ + HAL_RTC_STATE_READY = 0x01U, /*!< RTC initialized and ready for use */ + HAL_RTC_STATE_BUSY = 0x02U, /*!< RTC process is ongoing */ + HAL_RTC_STATE_TIMEOUT = 0x03U, /*!< RTC timeout state */ + HAL_RTC_STATE_ERROR = 0x04U /*!< RTC error state */ + +} HAL_RTCStateTypeDef; + +/** + * @brief RTC Configuration Structure definition + */ +typedef struct +{ + uint32_t HourFormat; /*!< Specifies the RTC Hour Format. + This parameter can be a value of @ref RTC_Hour_Formats */ + + uint32_t AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */ + + uint32_t SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF */ + + uint32_t OutPut; /*!< Specifies which signal will be routed to the RTC output. + This parameter can be a value of @ref RTCEx_Output_selection_Definitions */ + + uint32_t OutPutRemap; /*!< Specifies the remap for RTC output. + This parameter can be a value of @ref RTC_Output_ALARM_OUT_Remap */ + + uint32_t OutPutPolarity; /*!< Specifies the polarity of the output signal. + This parameter can be a value of @ref RTC_Output_Polarity_Definitions */ + + uint32_t OutPutType; /*!< Specifies the RTC Output Pin mode. + This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */ + + uint32_t OutPutPullUp; /*!< Specifies the RTC Output Pull-Up mode. + This parameter can be a value of @ref RTC_Output_PullUp_ALARM_OUT */ + + uint32_t BinMode; /*!< Specifies the RTC binary mode. + This parameter can be a value of @ref RTCEx_Binary_Mode */ + + uint32_t BinMixBcdU; /*!< Specifies the BCD calendar update if and only if BinMode = RTC_BINARY_MIX. + This parameter can be a value of @ref RTCEx_Binary_mix_BCDU */ +} RTC_InitTypeDef; + +/** + * @brief RTC Time structure definition + */ +typedef struct +{ + uint8_t Hours; /*!< Specifies the RTC Time Hour. + This parameter must be a number between: + Min_Data = 0 and Max_Data = 12 if the RTC_HOURFORMAT_12 is selected. + This parameter must be a number between: + Min_Data = 0 and Max_Data = 23 if the RTC_HOURFORMAT_24 is selected */ + + uint8_t Minutes; /*!< Specifies the RTC Time Minutes. + This parameter must be a number between Min_Data = 0 and Max_Data = 59 */ + + uint8_t Seconds; /*!< Specifies the RTC Time Seconds. + This parameter must be a number between Min_Data = 0 and Max_Data = 59 */ + + uint8_t TimeFormat; /*!< Specifies the RTC AM/PM Time. + This parameter can be a value of @ref RTC_AM_PM_Definitions */ + + uint32_t SubSeconds; /*!< Specifies the RTC_SSR RTC Sub Second register content. + This field is not used by HAL_RTC_SetTime. + If the free running 32 bit counter is not activated (mode binary none) + - This parameter corresponds to a time unit range + between [0-1] Second with [1 Sec / SecondFraction +1] granularity + else + - This parameter corresponds to the free running 32 bit counter. */ + + uint32_t SecondFraction; /*!< Specifies the range or granularity of Sub Second register content + corresponding to Synchronous pre-scaler factor value (PREDIV_S) + This parameter corresponds to a time unit range between [0-1] Second + with [1 Sec / SecondFraction +1] granularity. + This field will be used only by HAL_RTC_GetTime function */ + + uint32_t DayLightSaving; /*!< This interface is deprecated. + To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions */ + + uint32_t StoreOperation; /*!< This interface is deprecated. + To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions */ +} RTC_TimeTypeDef; + +/** + * @brief RTC Date structure definition + */ +typedef struct +{ + uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay. + This parameter can be a value of @ref RTC_WeekDay_Definitions */ + + uint8_t Month; /*!< Specifies the RTC Date Month (in BCD format). + This parameter can be a value of @ref RTC_Month_Date_Definitions */ + + uint8_t Date; /*!< Specifies the RTC Date. + This parameter must be a number between Min_Data = 1 and Max_Data = 31 */ + + uint8_t Year; /*!< Specifies the RTC Date Year. + This parameter must be a number between Min_Data = 0 and Max_Data = 99 */ +} RTC_DateTypeDef; + +/** + * @brief RTC Alarm structure definition + */ +typedef struct +{ + RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members */ + + uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks. + This parameter can be a value of @ref RTC_AlarmMask_Definitions */ + + uint32_t AlarmSubSecondMask; /*!< Specifies the RTC Alarm SubSeconds Masks. + if Binary mode is RTC_BINARY_ONLY or is RTC_BINARY_MIX + This parameter can be a value of + @ref RTCEx_Alarm_Sub_Seconds_binary_Masks_Definitions + else if Binary mode is RTC_BINARY_NONE + This parameter can be a value of + @ref RTC_Alarm_Sub_Seconds_BCD_Masks_Definitions */ + + uint32_t BinaryAutoClr; /*!< Clear synchronously counter (RTC_SSR) on binary alarm. + RTC_ALARMSUBSECONDBIN_AUTOCLR_YES must only be used if Binary mode + is RTC_BINARY_ONLY + This parameter can be a value of + @ref RTCEx_Alarm_Sub_Seconds_binary_Clear_Definitions */ + + uint32_t AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay. + This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */ + + uint8_t AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay. + If the Alarm Date is selected, this parameter must be set to a value + in the 1-31 range. + If the Alarm WeekDay is selected, this parameter can be a value of + @ref RTC_WeekDay_Definitions */ + + uint32_t FlagAutoClr; /*!< Specifies the alarm trigger generation. This feature is meaningful + to avoid any RTC software execution after configuration. + This parameter can be a value of @ref RTC_ALARM_Flag_AutoClear_Definitions */ + + uint32_t Alarm; /*!< Specifies the alarm. + This parameter can be a value of @ref RTC_Alarms_Definitions */ +} RTC_AlarmTypeDef; + +/** + * @brief RTC Handle Structure definition + */ +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) +typedef struct __RTC_HandleTypeDef +#else +typedef struct +#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ +{ + RTC_TypeDef *Instance; /*!< Legacy register base address. Not used anymore, the driver directly uses cmsis base address */ + + RTC_InitTypeDef Init; /*!< RTC required parameters */ + + HAL_LockTypeDef Lock; /*!< RTC locking object */ + + __IO HAL_RTCStateTypeDef State; /*!< Time communication state */ + +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + void (* AlarmAEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Alarm A Event callback */ + void (* AlarmBEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Alarm B Event callback */ + void (* TimeStampEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC TimeStamp Event callback */ + void (* WakeUpTimerEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC WakeUpTimer Event callback */ + void (* SSRUEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC SSRU Event callback */ + void (* Tamper1EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 1 Event callback */ + void (* Tamper2EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 2 Event callback */ + void (* Tamper3EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 3 Event callback */ + void (* Tamper4EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 4 Event callback */ + void (* Tamper5EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 5 Event callback */ + void (* Tamper6EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 6 Event callback */ + void (* InternalTamper3EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 3 Event callback */ + void (* InternalTamper5EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 5 Event callback */ + void (* InternalTamper6EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 6 Event callback */ + void (* InternalTamper7EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 7 Event callback */ + void (* InternalTamper8EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 8 Event callback */ + void (* InternalTamper9EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 9 Event callback */ + void (* InternalTamper11EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 11 Event callback */ + void (* InternalTamper12EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 12 Event callback */ + void (* InternalTamper13EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 13 Event callback */ + void (* MspInitCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Msp Init callback */ + void (* MspDeInitCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Msp DeInit callback */ + +#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ + +} RTC_HandleTypeDef; + +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) +/** + * @brief HAL RTC Callback ID enumeration definition + */ +typedef enum +{ + HAL_RTC_ALARM_A_EVENT_CB_ID = 0U, /*!< RTC Alarm A Event Callback ID */ + HAL_RTC_ALARM_B_EVENT_CB_ID = 1U, /*!< RTC Alarm B Event Callback ID */ + HAL_RTC_TIMESTAMP_EVENT_CB_ID = 2U, /*!< RTC TimeStamp Event Callback ID */ + HAL_RTC_WAKEUPTIMER_EVENT_CB_ID = 3U, /*!< RTC WakeUp Timer Event Callback ID */ + HAL_RTC_SSRU_EVENT_CB_ID = 4U, /*!< RTC SSRU Event Callback ID */ + HAL_RTC_TAMPER1_EVENT_CB_ID = 5U, /*!< RTC Tamper 1 Callback ID */ + HAL_RTC_TAMPER2_EVENT_CB_ID = 6U, /*!< RTC Tamper 2 Callback ID */ + HAL_RTC_TAMPER3_EVENT_CB_ID = 7U, /*!< RTC Tamper 3 Callback ID */ + HAL_RTC_TAMPER4_EVENT_CB_ID = 8U, /*!< RTC Tamper 4 Callback ID */ + HAL_RTC_TAMPER5_EVENT_CB_ID = 9U, /*!< RTC Tamper 5 Callback ID */ + HAL_RTC_TAMPER6_EVENT_CB_ID = 10U, /*!< RTC Tamper 6 Callback ID */ + HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID = 11U, /*!< RTC Internal Tamper 3 Callback ID */ + HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID = 12U, /*!< RTC Internal Tamper 5 Callback ID */ + HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID = 13U, /*!< RTC Internal Tamper 6 Callback ID */ + HAL_RTC_INTERNAL_TAMPER7_EVENT_CB_ID = 14U, /*!< RTC Internal Tamper 7 Callback ID */ + HAL_RTC_INTERNAL_TAMPER8_EVENT_CB_ID = 15U, /*!< RTC Internal Tamper 8 Callback ID */ + HAL_RTC_INTERNAL_TAMPER9_EVENT_CB_ID = 16U, /*!< RTC Internal Tamper 9 Callback ID */ + HAL_RTC_INTERNAL_TAMPER11_EVENT_CB_ID = 17U, /*!< RTC Internal Tamper 11 Callback ID */ + HAL_RTC_INTERNAL_TAMPER12_EVENT_CB_ID = 18U, /*!< RTC Internal Tamper 12 Callback ID */ + HAL_RTC_INTERNAL_TAMPER13_EVENT_CB_ID = 19U, /*!< RTC Internal Tamper 13 Callback ID */ + HAL_RTC_MSPINIT_CB_ID = 20U, /*!< RTC Msp Init callback ID */ + HAL_RTC_MSPDEINIT_CB_ID = 21U /*!< RTC Msp DeInit callback ID */ +} HAL_RTC_CallbackIDTypeDef; + +/** + * @brief HAL RTC Callback pointer definition + */ +typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to an RTC callback function */ +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RTC_Exported_Constants RTC Exported Constants + * @{ + */ + +/** @defgroup RTC_Hour_Formats RTC Hour Formats + * @{ + */ +#define RTC_HOURFORMAT_24 0U +#define RTC_HOURFORMAT_12 RTC_CR_FMT +/** + * @} + */ + +/** @defgroup RTCEx_Output_selection_Definitions RTCEx Output Selection Definition + * @{ + */ +#define RTC_OUTPUT_DISABLE 0U +#define RTC_OUTPUT_ALARMA RTC_CR_OSEL_0 +#define RTC_OUTPUT_ALARMB RTC_CR_OSEL_1 +#define RTC_OUTPUT_WAKEUP RTC_CR_OSEL +#define RTC_OUTPUT_TAMPER RTC_CR_TAMPOE +/** + * @} + */ + +/** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions + * @{ + */ +#define RTC_OUTPUT_POLARITY_HIGH 0U +#define RTC_OUTPUT_POLARITY_LOW RTC_CR_POL +/** + * @} + */ + +/** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT + * @{ + */ +#define RTC_OUTPUT_TYPE_PUSHPULL 0U +#define RTC_OUTPUT_TYPE_OPENDRAIN RTC_CR_TAMPALRM_TYPE +/** + * @} + */ + +/** @defgroup RTC_Output_PullUp_ALARM_OUT RTC Output Pull-Up ALARM OUT + * @{ + */ +#define RTC_OUTPUT_PULLUP_NONE 0U +#define RTC_OUTPUT_PULLUP_ON RTC_CR_TAMPALRM_PU +/** + * @} + */ + +#if defined(RTC_CR_OUT2EN) +/** @defgroup RTC_Output_ALARM_OUT_Remap RTC Output ALARM OUT Remap + * @{ + */ +#define RTC_OUTPUT_REMAP_NONE 0U +#define RTC_OUTPUT_REMAP_POS1 RTC_CR_OUT2EN +/** + * @} + */ +#endif /* RTC_CR_OUT2EN */ + +/** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions + * @{ + */ +#define RTC_HOURFORMAT12_AM 0U +#define RTC_HOURFORMAT12_PM 1U +/** + * @} + */ + +/** @defgroup RTC_DayLightSaving_Definitions RTC DayLightSaving Definitions + * @{ + */ +#define RTC_DAYLIGHTSAVING_SUB1H RTC_CR_SUB1H +#define RTC_DAYLIGHTSAVING_ADD1H RTC_CR_ADD1H +#define RTC_DAYLIGHTSAVING_NONE 0U +/** + * @} + */ + +/** @defgroup RTC_StoreOperation_Definitions RTC StoreOperation Definitions + * @{ + */ +#define RTC_STOREOPERATION_RESET 0U +#define RTC_STOREOPERATION_SET RTC_CR_BKP +/** + * @} + */ + +/** @defgroup RTC_Input_parameter_format_definitions RTC Input Parameter Format Definitions + * @{ + */ +#define RTC_FORMAT_BIN 0U +#define RTC_FORMAT_BCD 1U +/** + * @} + */ + +/** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions + * @{ + */ + +/* Coded in BCD format */ +#define RTC_MONTH_JANUARY ((uint8_t)0x01U) +#define RTC_MONTH_FEBRUARY ((uint8_t)0x02U) +#define RTC_MONTH_MARCH ((uint8_t)0x03U) +#define RTC_MONTH_APRIL ((uint8_t)0x04U) +#define RTC_MONTH_MAY ((uint8_t)0x05U) +#define RTC_MONTH_JUNE ((uint8_t)0x06U) +#define RTC_MONTH_JULY ((uint8_t)0x07U) +#define RTC_MONTH_AUGUST ((uint8_t)0x08U) +#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09U) +#define RTC_MONTH_OCTOBER ((uint8_t)0x10U) +#define RTC_MONTH_NOVEMBER ((uint8_t)0x11U) +#define RTC_MONTH_DECEMBER ((uint8_t)0x12U) + +/** + * @} + */ + +/** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions + * @{ + */ +#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01U) +#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02U) +#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03U) +#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04U) +#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05U) +#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06U) +#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07U) + +/** + * @} + */ + +/** @defgroup RTC_AlarmDateWeekDay_Definitions RTC AlarmDateWeekDay Definitions + * @{ + */ +#define RTC_ALARMDATEWEEKDAYSEL_DATE 0U +#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL + +/** + * @} + */ + +/** @defgroup RTC_AlarmMask_Definitions RTC AlarmMask Definitions + * @{ + */ +#define RTC_ALARMMASK_NONE 0U +#define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4 +#define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3 +#define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2 +#define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1 +#define RTC_ALARMMASK_ALL (RTC_ALARMMASK_DATEWEEKDAY | RTC_ALARMMASK_HOURS | \ + RTC_ALARMMASK_MINUTES | RTC_ALARMMASK_SECONDS) + +/** + * @} + */ + +/** @defgroup RTC_Alarms_Definitions RTC Alarms Definitions + * @{ + */ +#define RTC_ALARM_A RTC_CR_ALRAE +#define RTC_ALARM_B RTC_CR_ALRBE + +/** + * @} + */ +/** @defgroup RTC_ALARM_Flag_AutoClear_Definitions RTC Alarms Flag Auto Clear Definitions + * @{ + */ +#define ALARM_FLAG_AUTOCLR_ENABLE 1U +#define ALARM_FLAG_AUTOCLR_DISABLE 0U +/** + * @} + */ + +/** @defgroup RTC_Alarm_Sub_Seconds_BCD_Masks_Definitions RTC Alarm Sub Seconds BCD Masks Definitions + * In BCD mode (BIN=00) the overflow bits of the synchronous counter (bits 31:15) are never compared. + * @{ + */ +#define RTC_ALARMSUBSECONDMASK_ALL 0U /*!< All Alarm SS fields are masked. There is no comparison on sub seconds for Alarm */ +#define RTC_ALARMSUBSECONDMASK_SS14_1 RTC_ALRMASSR_MASKSS_0 /*!< SS[14:1] not used in Alarmcomparison. Only SS[0] is compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_2 RTC_ALRMASSR_MASKSS_1 /*!< SS[14:2] not used in Alarm comparison. Only SS[1:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_3 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1) /*!< SS[14:3] not used in Alarm comparison. Only SS[2:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_4 RTC_ALRMASSR_MASKSS_2 /*!< SS[14:4] not used in Alarm comparison. Only SS[3:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_5 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2) /*!< SS[14:5] not used in Alarm comparison. Only SS[4:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_6 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2) /*!< SS[14:6] not used in Alarm comparison. Only SS[5:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_7 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2) /*!< SS[14:7] not used in Alarm comparison. Only SS[6:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_8 RTC_ALRMASSR_MASKSS_3 /*!< SS[14:8] not used in Alarm comparison. Only SS[7:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_9 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:9] not used in Alarm comparison. Only SS[8:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_10 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:10] not used in Alarm comparison. Only SS[9:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_11 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:11] not used in Alarm comparison. Only SS[10:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_12 (RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:12] not used in Alarm comparison.Only SS[11:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_13 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:13] not used in Alarm comparison. Only SS[12:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14] not used in Alarm comparison. Only SS[13:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_NONE RTC_ALRMASSR_MASKSS /*!< SS[14:0] are compared and must match to activate alarm */ +/** + * @} + */ + +/** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions + * @{ + */ +#define RTC_IT_TS RTC_CR_TSIE /*!< Enable Timestamp Interrupt */ +#define RTC_IT_WUT RTC_CR_WUTIE /*!< Enable Wakeup timer Interrupt */ +#define RTC_IT_SSRU RTC_CR_SSRUIE /*!< Enable SSR Underflow Interrupt */ +#define RTC_IT_ALRA RTC_CR_ALRAIE /*!< Enable Alarm A Interrupt */ +#define RTC_IT_ALRB RTC_CR_ALRBIE /*!< Enable Alarm B Interrupt */ +/** + * @} + */ + +/** @defgroup RTC_Flags_Definitions RTC Flags Definitions + * @{ + */ +#define RTC_FLAG_RECALPF (1U) /*!< Recalibration pending flag */ +#define RTC_FLAG_INITF (2U) /*!< Initialization flag */ +#define RTC_FLAG_RSF (3U) /*!< Registers synchronization flag */ +#define RTC_FLAG_INITS (4U) /*!< Initialization status flag */ +#define RTC_FLAG_SHPF (5U) /*!< Shift operation pending flag */ +#define RTC_FLAG_WUTWF (6U) /*!< Wakeup timer write flag */ +#define RTC_FLAG_SSRUF (7U) /*!< SSR underflow flag */ +#define RTC_FLAG_TSOVF (8U) /*!< Time-stamp overflow flag */ +#define RTC_FLAG_TSF (9U) /*!< Time-stamp flag */ +#define RTC_FLAG_WUTF (10U) /*!< Wakeup timer flag */ +#define RTC_FLAG_ALRBF (11U) /*!< Alarm B flag */ +#define RTC_FLAG_ALRAF (12U) /*!< Alarm A flag */ +/** + * @} + */ + +/** @defgroup RTC_Clear_Flags_Definitions RTC Clear Flags Definitions + * @{ + */ +#define RTC_CLEAR_SSRUF RTC_SCR_CSSRUF /*!< Clear SSR underflow flag */ +#define RTC_CLEAR_TSOVF RTC_SCR_CTSOVF /*!< Clear Time-stamp overflow flag */ +#define RTC_CLEAR_TSF RTC_SCR_CTSF /*!< Clear Time-stamp flag */ +#define RTC_CLEAR_WUTF RTC_SCR_CWUTF /*!< Clear Wakeup timer flag */ +#define RTC_CLEAR_ALRBF RTC_SCR_CALRBF /*!< Clear Alarm B flag */ +#define RTC_CLEAR_ALRAF RTC_SCR_CALRAF /*!< Clear Alarm A flag */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup RTC_Exported_Macros RTC Exported Macros + * @{ + */ + +/** @brief Reset RTC handle state + * @param __HANDLE__ RTC handle. + * @retval None + */ +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) +#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) do{\ + (__HANDLE__)->State = HAL_RTC_STATE_RESET;\ + (__HANDLE__)->MspInitCallback = NULL;\ + (__HANDLE__)->MspDeInitCallback = NULL;\ + }while(0) +#else +#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET) +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + +/** + * @brief Disable the write protection for RTC registers. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) \ + do{ \ + RTC->WPR = 0xCAU; \ + RTC->WPR = 0x53U; \ + } while(0U) + +/** + * @brief Enable the write protection for RTC registers. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) \ + do{ \ + RTC->WPR = 0xFFU; \ + } while(0U) + +/** + * @brief Add 1 hour (summer time change). + * @note This interface is deprecated. + * To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions + * @param __HANDLE__ specifies the RTC handle. + * @param __BKP__ Backup + * This parameter can be: + * @arg @ref RTC_STOREOPERATION_RESET + * @arg @ref RTC_STOREOPERATION_SET + * @retval None + */ +#define __HAL_RTC_DAYLIGHT_SAVING_TIME_ADD1H(__HANDLE__, __BKP__) \ + do { \ + __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__); \ + SET_BIT(RTC->CR, RTC_CR_ADD1H); \ + MODIFY_REG(RTC->CR, RTC_CR_BKP , (__BKP__)); \ + __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__); \ + } while(0); + +/** + * @brief Subtract 1 hour (winter time change). + * @note This interface is deprecated. + * To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions + * @param __HANDLE__ specifies the RTC handle. + * @param __BKP__ Backup + * This parameter can be: + * @arg @ref RTC_STOREOPERATION_RESET + * @arg @ref RTC_STOREOPERATION_SET + * @retval None + */ +#define __HAL_RTC_DAYLIGHT_SAVING_TIME_SUB1H(__HANDLE__, __BKP__) \ + do { \ + __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__); \ + SET_BIT(RTC->CR, RTC_CR_SUB1H); \ + MODIFY_REG(RTC->CR, RTC_CR_BKP , (__BKP__)); \ + __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__); \ + } while(0); + +/** + * @brief Enable the RTC ALARMA peripheral. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_ALARMA_ENABLE(__HANDLE__) (RTC->CR |= (RTC_CR_ALRAE)) + +/** + * @brief Disable the RTC ALARMA peripheral. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_ALARMA_DISABLE(__HANDLE__) (RTC->CR &= ~(RTC_CR_ALRAE)) + +/** + * @brief Enable the RTC ALARMB peripheral. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_ALARMB_ENABLE(__HANDLE__) (RTC->CR |= (RTC_CR_ALRBE)) + +/** + * @brief Disable the RTC ALARMB peripheral. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_ALARMB_DISABLE(__HANDLE__) (RTC->CR &= ~(RTC_CR_ALRBE)) + +/** + * @brief Enable the RTC Alarm interrupt. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg @ref RTC_IT_ALRA Alarm A interrupt + * @arg @ref RTC_IT_ALRB Alarm B interrupt + * @retval None + */ +#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__)( \ + ((__INTERRUPT__) == RTC_IT_ALRA) ? (SET_BIT(RTC->CR, RTC_CR_ALRAIE)):\ + ((__INTERRUPT__) == RTC_IT_ALRB) ? (SET_BIT(RTC->CR, RTC_CR_ALRBIE)):\ + (0U)) /* Dummy action because is an invalid parameter value */ + +/** + * @brief Disable the RTC Alarm interrupt. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg @ref RTC_IT_ALRA Alarm A interrupt + * @arg @ref RTC_IT_ALRB Alarm B interrupt + * @retval None + */ +#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__)( \ + ((__INTERRUPT__) == RTC_IT_ALRA) ? (CLEAR_BIT(RTC->CR, RTC_CR_ALRAIE)):\ + ((__INTERRUPT__) == RTC_IT_ALRB) ? (CLEAR_BIT(RTC->CR, RTC_CR_ALRBIE)):\ + (0U)) /* Dummy action because is an invalid parameter value */ + +/** + * @brief Check whether the specified RTC Alarm interrupt has occurred or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to check. + * This parameter can be: + * @arg @ref RTC_IT_ALRA Alarm A interrupt + * @arg @ref RTC_IT_ALRB Alarm B interrupt + * @retval The state of __INTERRUPT__ (TRUE or FALSE). + */ +#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__)( \ + ((__INTERRUPT__) == RTC_IT_ALRA) ? (READ_BIT(RTC->MISR, RTC_MISR_ALRAMF) == RTC_MISR_ALRAMF):\ + ((__INTERRUPT__) == RTC_IT_ALRB) ? (READ_BIT(RTC->MISR, RTC_MISR_ALRBMF) == RTC_MISR_ALRBMF):\ + (0U)) /* Return 0 because it is an invalid parameter value */ + +/** + * @brief Check whether the specified RTC Alarm interrupt has been enabled or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to check. + * This parameter can be: + * @arg @ref RTC_IT_ALRA Alarm A interrupt + * @arg @ref RTC_IT_ALRB Alarm B interrupt + * @retval The state of __INTERRUPT__ (TRUE or FALSE). + */ +#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)( \ + ((__INTERRUPT__) == RTC_IT_ALRA) ? (READ_BIT(RTC->CR, RTC_CR_ALRAIE) == RTC_CR_ALRAIE):\ + ((__INTERRUPT__) == RTC_IT_ALRB) ? (READ_BIT(RTC->CR, RTC_CR_ALRBIE) == RTC_CR_ALRBIE):\ + (0U)) /* Return 0 because it is an invalid parameter value */ + +/** + * @brief Get the selected RTC Alarms flag status. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Alarm Flag sources to check. + * This parameter can be: + * @arg @ref RTC_FLAG_ALRAF + * @arg @ref RTC_FLAG_ALRBF + * @retval The state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__)( \ + ((__FLAG__) == RTC_FLAG_ALRAF) ? (READ_BIT(RTC->SR, RTC_SR_ALRAF) == RTC_SR_ALRAF):\ + ((__FLAG__) == RTC_FLAG_ALRBF) ? (READ_BIT(RTC->SR, RTC_SR_ALRBF) == RTC_SR_ALRBF):\ + (0U)) /* Return 0 because it is an invalid parameter value */ + +/** + * @brief Clear the RTC Alarms pending flags. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Alarm Flag sources to clear. + * This parameter can be: + * @arg @ref RTC_FLAG_ALRAF + * @arg @ref RTC_FLAG_ALRBF + * @retval None + */ +#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__)( \ + ((__FLAG__) == RTC_FLAG_ALRAF) ? (SET_BIT(RTC->SCR, RTC_SCR_CALRAF)):\ + ((__FLAG__) == RTC_FLAG_ALRBF) ? (SET_BIT(RTC->SCR, RTC_SCR_CALRBF)):\ + (0U)) /* Dummy action because is an invalid parameter value */ + +/** + * @brief Check whether if the RTC Calendar is initialized. + * @param __HANDLE__ specifies the RTC handle. + * @retval The state of RTC Calendar initialization (TRUE or FALSE). + */ +#define __HAL_RTC_IS_CALENDAR_INITIALIZED(__HANDLE__) ((((RTC->ICSR) & (RTC_ICSR_INITS)) == RTC_ICSR_INITS)) + +/** + * @} + */ + +/* Include RTC HAL Extended module */ +#include "stm32wbaxx_hal_rtc_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup RTC_Exported_Functions RTC Exported Functions + * @{ + */ + +/** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +/* Initialization and de-initialization functions ****************************/ +HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc); + +void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc); +void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, + pRTC_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup RTC_Exported_Functions_Group2 RTC Time and Date functions + * @{ + */ +/* RTC Time and Date functions ************************************************/ +HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); +HAL_StatusTypeDef HAL_RTC_GetTime(const RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); +HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); +HAL_StatusTypeDef HAL_RTC_GetDate(const RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); +void HAL_RTC_DST_Add1Hour(const RTC_HandleTypeDef *hrtc); +void HAL_RTC_DST_Sub1Hour(const RTC_HandleTypeDef *hrtc); +void HAL_RTC_DST_SetStoreOperation(const RTC_HandleTypeDef *hrtc); +void HAL_RTC_DST_ClearStoreOperation(const RTC_HandleTypeDef *hrtc); +uint32_t HAL_RTC_DST_ReadStoreOperation(const RTC_HandleTypeDef *hrtc); +/** + * @} + */ + +/** @defgroup RTC_Exported_Functions_Group3 RTC Alarm functions + * @{ + */ +/* RTC Alarm functions ********************************************************/ +HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format); +HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format); +HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm); +HAL_StatusTypeDef HAL_RTC_GetAlarm(const RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, + uint32_t Format); +void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(const RTC_HandleTypeDef *hrtc, uint32_t Timeout); +void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc); + +/** + * @} + */ + +/** @defgroup RTC_Exported_Functions_Group4 Peripheral Control functions + * @{ + */ +/* Peripheral Control functions ***********************************************/ +HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc); +/** + * @} + */ + +/** @defgroup RTC_Exported_Functions_Group5 Peripheral State functions + * @{ + */ +/* Peripheral State functions *************************************************/ +HAL_RTCStateTypeDef HAL_RTC_GetState(const RTC_HandleTypeDef *hrtc); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup RTC_Private_Constants RTC Private Constants + * @{ + */ +/* Masks Definition */ +#define RTC_TR_RESERVED_MASK (RTC_TR_PM | RTC_TR_HT | RTC_TR_HU | \ + RTC_TR_MNT | RTC_TR_MNU| RTC_TR_ST | \ + RTC_TR_SU) +#define RTC_DR_RESERVED_MASK (RTC_DR_YT | RTC_DR_YU | RTC_DR_WDU | \ + RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | \ + RTC_DR_DU) +#define RTC_INIT_MASK 0xFFFFFFFFU +#define RTC_RSF_MASK (~(RTC_ICSR_INIT | RTC_ICSR_RSF)) + +#define RTC_TIMEOUT_VALUE 1000U + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup RTC_Private_Macros RTC Private Macros + * @{ + */ + +/** @defgroup RTC_IS_RTC_Definitions RTC Private macros to check input parameters + * @{ + */ +#if defined(RTC_CR_OSEL) +#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \ + ((OUTPUT) == RTC_OUTPUT_ALARMA) || \ + ((OUTPUT) == RTC_OUTPUT_ALARMB) || \ + ((OUTPUT) == RTC_OUTPUT_WAKEUP) || \ + ((OUTPUT) == RTC_OUTPUT_TAMPER)) +#endif /* RTC_CR_OSEL */ + +#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HOURFORMAT_12) || \ + ((FORMAT) == RTC_HOURFORMAT_24)) + +#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \ + ((POL) == RTC_OUTPUT_POLARITY_LOW)) + +#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \ + ((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL)) + +#define IS_RTC_OUTPUT_PULLUP(TYPE) (((TYPE) == RTC_OUTPUT_PULLUP_NONE) || \ + ((TYPE) == RTC_OUTPUT_PULLUP_ON)) + +#if defined(RTC_CR_OUT2EN) +#define IS_RTC_OUTPUT_REMAP(REMAP) (((REMAP) == RTC_OUTPUT_REMAP_NONE) || \ + ((REMAP) == RTC_OUTPUT_REMAP_POS1)) +#endif /* RTC_CR_OUT2EN */ + +#define IS_RTC_HOURFORMAT12(PM) (((PM) == RTC_HOURFORMAT12_AM) || \ + ((PM) == RTC_HOURFORMAT12_PM)) + +#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \ + ((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \ + ((SAVE) == RTC_DAYLIGHTSAVING_NONE)) + +#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \ + ((OPERATION) == RTC_STOREOPERATION_SET)) + +#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || \ + ((FORMAT) == RTC_FORMAT_BCD)) + +#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99U) + +#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1U) && ((MONTH) <= 12U)) + +#define IS_RTC_DATE(DATE) (((DATE) >= 1U) && ((DATE) <= 31U)) + +#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_SUNDAY)) + +#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0U) && ((DATE) <= 31U)) + +#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \ + ((WEEKDAY) == RTC_WEEKDAY_SUNDAY)) + +#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \ + ((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY)) + +#define IS_RTC_ALARM_MASK(MASK) (((MASK) & ~(RTC_ALARMMASK_ALL)) == 0UL) + +#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_ALARM_A) || \ + ((ALARM) == RTC_ALARM_B)) + +#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= RTC_ALRMASSR_SS) + +#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == 0UL) || \ + (((MASK) >= RTC_ALARMSUBSECONDMASK_SS14_1) && \ + ((MASK) <= RTC_ALARMSUBSECONDMASK_NONE))) + +#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= (RTC_PRER_PREDIV_A >> RTC_PRER_PREDIV_A_Pos)) + +#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= (RTC_PRER_PREDIV_S >> RTC_PRER_PREDIV_S_Pos)) + +#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0U) && ((HOUR) <= 12U)) + +#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23U) + +#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59U) + +#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59U) + +/** + * @} + */ + +/** + * @} + */ + +/* Private functions -------------------------------------------------------------*/ +/** @defgroup RTC_Private_Functions RTC Private Functions + * @{ + */ +HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc); +uint8_t RTC_ByteToBcd2(uint8_t Value); +uint8_t RTC_Bcd2ToByte(uint8_t Value); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WBAxx_HAL_RTC_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rtc_ex.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rtc_ex.h new file mode 100644 index 0000000000..dc6227d0b3 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_rtc_ex.h @@ -0,0 +1,1833 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_rtc_ex.h + * @author MCD Application Team + * @brief Header file of RTC HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_HAL_RTC_EX_H +#define STM32WBAxx_HAL_RTC_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal_def.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @defgroup RTCEx RTCEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup RTCEx_Exported_Types RTCEx Exported Types + * @{ + */ + +/** @defgroup RTCEx_Tamper_structure_definition RTCEx Tamper structure definition + * @{ + */ +typedef struct +{ + uint32_t Tamper; /*!< Specifies the Tamper Pin. + This parameter can be a value of @ref RTCEx_Tamper_Pins */ + + uint32_t Trigger; /*!< Specifies the Tamper Trigger. + This parameter can be a value of @ref RTCEx_Tamper_Trigger */ + + uint32_t NoErase; /*!< Specifies the Tamper no erase mode. + This parameter can be a value of @ref RTCEx_Tamper_EraseBackUp */ + + uint32_t MaskFlag; /*!< Specifies the Tamper Flag masking. + This parameter can be a value of @ref RTCEx_Tamper_MaskFlag */ + + uint32_t Filter; /*!< Specifies the TAMP Filter Tamper. + This parameter can be a value of @ref RTCEx_Tamper_Filter */ + + uint32_t SamplingFrequency; /*!< Specifies the sampling frequency. + This parameter can be a value of + @ref RTCEx_Tamper_Sampling_Frequencies */ + + uint32_t PrechargeDuration; /*!< Specifies the Precharge Duration. + This parameter can be a value of + @ref RTCEx_Tamper_Pin_Precharge_Duration */ + + uint32_t TamperPullUp; /*!< Specifies the Tamper PullUp. + This parameter can be a value of @ref RTCEx_Tamper_Pull_UP */ + + uint32_t TimeStampOnTamperDetection; /*!< Specifies the TimeStampOnTamperDetection. + This parameter can be a value of + @ref RTCEx_Tamper_TimeStampOnTamperDetection */ +} RTC_TamperTypeDef; +/** + * @} + */ + + +/** @defgroup RTCEx_Active_Seed_Size Seed size Definitions + * @{ + */ +#define RTC_ATAMP_SEED_NB_UINT32 4U +/** + * @} + */ + + +/** @defgroup RTCEx_ActiveTamper_structures_definition RTCEx Active Tamper structures definitions + * @{ + */ +typedef struct +{ + uint32_t Enable; /*!< Specifies the Tamper input is active. + This parameter can be a value of @ref RTCEx_ActiveTamper_Enable */ + + uint32_t Interrupt; /*!< Specifies the interrupt mode. + This parameter can be a value of @ref RTCEx_ActiveTamper_Interrupt */ + + uint32_t Output; /*!< Specifies the TAMP output to be compared with. + The same output can be used for several tamper inputs. + This parameter can be a value of @ref RTCEx_ActiveTamper_Sel */ + + uint32_t NoErase; /*!< Specifies the Tamper no erase mode. + This parameter can be a value of @ref RTCEx_Tamper_EraseBackUp */ + + uint32_t MaskFlag; /*!< Specifies the Tamper Flag masking. + This parameter can be a value of @ref RTCEx_Tamper_MaskFlag */ + +} RTC_ATampInputTypeDef; + + +typedef struct +{ + uint32_t ActiveFilter; /*!< Specifies the Active tamper filter enable. + This parameter can be a value of @ref RTCEx_ActiveTamper_Filter */ + + uint32_t ActiveAsyncPrescaler; /*!< Specifies the Active Tamper asynchronous Prescaler clock. + This parameter can be a value of + @ref RTCEx_ActiveTamper_Async_prescaler */ + + uint32_t TimeStampOnTamperDetection; /*!< Specifies the timeStamp on tamper detection. + This parameter can be a value of + @ref RTCEx_Tamper_TimeStampOnTamperDetection */ + + uint32_t ActiveOutputChangePeriod; /*!< Specifies the Active Tamper output change period. + This parameter can be a value from 0 to 7 */ + + uint32_t Seed[RTC_ATAMP_SEED_NB_UINT32]; + /*!< Specifies the RNG Seed value. + This parameter is an array of value from 0 to 0xFFFFFFFF */ + + RTC_ATampInputTypeDef TampInput[RTC_TAMP_NB]; + /*!< Specifies configuration of all active tampers. + The index of TampInput[RTC_TAMP_NB] can be a value of RTCEx_ActiveTamper_Sel */ +} RTC_ActiveTampersTypeDef; +/** + * @} + */ + +/** @defgroup RTCEx_Internal_Tamper_structure_definition RTCEx Internal Tamper structure definition + * @{ + */ +typedef struct +{ + uint32_t IntTamper; /*!< Specifies the Internal Tamper Pin. + This parameter can be a value of @ref RTCEx_Internal_Tamper_Pins */ + + uint32_t TimeStampOnTamperDetection; /*!< Specifies the TimeStampOnTamperDetection. + This parameter can be a value of + @ref RTCEx_Tamper_TimeStampOnTamperDetection */ + + uint32_t NoErase; /*!< Specifies the internal Tamper no erase mode. + This parameter can be a value of @ref RTCEx_Tamper_EraseBackUp */ + +} RTC_InternalTamperTypeDef; +/** + * @} + */ + +/** @defgroup RTCEx_Secure_State_structure_definition RTCEx Secure structure definition + * @{ + */ +typedef struct +{ + uint32_t rtcSecureFull; /*!< Specifies If the RTC is fully secure or not. + This parameter can be a value of @ref RTCEx_RTC_Secure_Full */ + + uint32_t rtcNonSecureFeatures; /*!< Specifies the non-secure features. + This parameter is only relevant if RTC is not fully secure + (rtcSecureFull == RTC_SECURE_FULL_NO). + This parameter can be a combination of + @ref RTCEx_RTC_NonSecure_Features */ + + uint32_t tampSecureFull; /*!< Specifies If the TAMP is fully secure or not execpt monotonic counters + and BackUp registers. + This parameter can be a value of @ref RTCEx_TAMP_Secure_Full */ + + uint32_t backupRegisterStartZone2; /*!< Specifies the backup register start zone 2. + Zone 1 : read secure write secure. + Zone 2 : read non-secure write secure. + This parameter can be RTC_BKP_DRx where x can be from 0 to 31 to specify + the register. + Warning : this parameter is shared with RTC_PrivilegeStateTypeDef */ + + uint32_t backupRegisterStartZone3; /*!< Specifies the backup register start zone 3. + Zone 3 : read non-secure write non-secure. + This parameter can be RTC_BKP_DRx where x can be from 0 to 31 to + specify the register. + Warning : this parameter is shared with RTC_PrivilegeStateTypeDef */ + + uint32_t MonotonicCounterSecure; /*!< Specifies If the monotonic counter is secure or not. + This parameter can be a value of + @ref RTCEx_TAMP_Monotonic_Counter_Secure */ +} RTC_SecureStateTypeDef; +/** + * @} + */ + +/** @defgroup RTCEx_Privilege_State_structure_definition RTCEx Privilege structure definition + * @{ + */ +typedef struct +{ + uint32_t rtcPrivilegeFull; /*!< Specifies If the RTC is fully privileged or not. + This parameter can be a value of @ref RTCEx_RTC_Privilege_Full */ + + uint32_t rtcPrivilegeFeatures; /*!< Specifies the privileged features. + This parameter is only relevant if RTC is not fully privileged + (rtcPrivilegeFull == RTC_PRIVILEGE_FULL_NO). + This parameter can be a combination of + @ref RTCEx_RTC_Privilege_Features */ + + uint32_t tampPrivilegeFull; /*!< Specifies If the TAMP is fully privileged or not execpt monotonic + counters and BackUp registers. + This parameter can be a value of @ref RTCEx_TAMP_Privilege_Full */ + + uint32_t backupRegisterPrivZone; /*!< Specifies backup register zone to be privileged. + This parameter can be a combination of + @ref RTCEx_Backup_Reg_Privilege_zone. + Warning : this parameter is writable in secure mode or if trustzone is + disabled */ + + uint32_t backupRegisterStartZone2; /*!< Specifies the backup register start zone 2. + Zone 1 : read secure write secure. + Zone 2 : read non-secure write secure. + This parameter can be RTC_BKP_DRx where x can be from 0 to 31 to specify + the register . + Warning : this parameter is writable in secure mode or if trustzone is + disabled. + Warning : this parameter is shared with RTC_SecureStateTypeDef */ + + uint32_t backupRegisterStartZone3; /*!< Specifies the backup register start zone 3. + Zone 3 : read non-secure write non-secure. + This parameter can be RTC_BKP_DRx where x can be from 0 to 31 to specify + the register. + Warning : this parameter is writable in secure mode or if trustzone is + disabled. + Warning : this parameter is shared with RTC_SecureStateTypeDef */ + + uint32_t MonotonicCounterPrivilege; /*!< Specifies If the monotonic counter is privileged or not. + This parameter can be a value of + @ref RTCEx_TAMP_Monotonic_Counter_Privilege */ +} RTC_PrivilegeStateTypeDef; +/** + * @} + */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RTCEx_Exported_Constants RTCEx Exported Constants + * @{ + */ + +#if defined(RTC_CR_TSEDGE) +/** @defgroup RTCEx_Time_Stamp_Edges_definitions RTCEx Time Stamp Edges definition + * @{ + */ +#define RTC_TIMESTAMPEDGE_RISING 0U +#define RTC_TIMESTAMPEDGE_FALLING RTC_CR_TSEDGE +/** + * @} + */ +#endif /* RTC_CR_TSEDGE */ + +/** @defgroup RTCEx_TimeStamp_Pin_Selections RTCEx TimeStamp Pin Selection + * @{ + */ +#define RTC_TIMESTAMPPIN_DEFAULT 0U +/** + * @} + */ + +/** @defgroup RTCEx_Wakeup_Timer_Definitions RTCEx Wakeup Timer Definitions + * @{ + */ +#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 0U +#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 RTC_CR_WUCKSEL_0 +#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 RTC_CR_WUCKSEL_1 +#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 (RTC_CR_WUCKSEL_0 | RTC_CR_WUCKSEL_1) +#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS RTC_CR_WUCKSEL_2 +#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_2) +/** + * @} + */ + +/** @defgroup RTCEx_Smooth_calib_period_Definitions RTCEx Smooth calib period Definitions + * @{ + */ +#define RTC_SMOOTHCALIB_PERIOD_32SEC 0U /*!< If RTCCLK = 32768 Hz, Smooth calibration period + is 32s, else 2exp20 RTCCLK pulses */ +#define RTC_SMOOTHCALIB_PERIOD_16SEC RTC_CALR_CALW16 /*!< If RTCCLK = 32768 Hz, Smooth calibration period + is 16s, else 2exp19 RTCCLK pulses */ +#define RTC_SMOOTHCALIB_PERIOD_8SEC RTC_CALR_CALW8 /*!< If RTCCLK = 32768 Hz, Smooth calibration period + is 8s, else 2exp18 RTCCLK pulses */ +/** + * @} + */ + +/** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions RTCEx Smooth calib Plus pulses Definitions + * @{ + */ +#define RTC_SMOOTHCALIB_PLUSPULSES_SET RTC_CALR_CALP /*!< The number of RTCCLK pulses added + during a X -second window = Y - CALM[8:0] + with Y = 512, 256, 128 when X = 32, 16, 8 */ +#define RTC_SMOOTHCALIB_PLUSPULSES_RESET 0U /*!< The number of RTCCLK pulses subbstited + during a 32-second window = CALM[8:0] */ +/** + * @} + */ + +/** @defgroup RTCEx_Smooth_calib_low_power_Definitions RTCEx Smooth calib Low Power Definitions + * @{ + */ +#define RTC_LPCAL_SET RTC_CALR_LPCAL /*!< Calibration window is 2exp20 ck_apre, which is the required configuration for ultra-low consumption mode. */ +#define RTC_LPCAL_RESET 0U /*!< Calibration window is 2exp20 RTCCLK, which is a high-consumption mode. + This mode should be set only when less + than 32s calibration window is required. */ +/** + * @} + */ + +#if defined(RTC_CR_COSEL) +/** @defgroup RTCEx_Calib_Output_selection_Definitions RTCEx Calib Output selection Definitions + * @{ + */ +#define RTC_CALIBOUTPUT_512HZ 0U +#define RTC_CALIBOUTPUT_1HZ RTC_CR_COSEL +/** + * @} + */ +#endif /* RTC_CR_COSEL */ + +/** @defgroup RTCEx_Add_1_Second_Parameter_Definition RTCEx Add 1 Second Parameter Definitions + * @{ + */ +#define RTC_SHIFTADD1S_RESET 0U +#define RTC_SHIFTADD1S_SET RTC_SHIFTR_ADD1S +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_Pins RTCEx Tamper Pins Definition + * @{ + */ +#define RTC_TAMPER_1 TAMP_CR1_TAMP1E +#define RTC_TAMPER_2 TAMP_CR1_TAMP2E +#define RTC_TAMPER_3 TAMP_CR1_TAMP3E +#ifdef TAMP_CR1_TAMP4E +#define RTC_TAMPER_4 TAMP_CR1_TAMP4E +#define RTC_TAMPER_5 TAMP_CR1_TAMP5E +#define RTC_TAMPER_6 TAMP_CR1_TAMP6E +#endif /* TAMP_CR1_TAMP4E */ + +#ifdef TAMP_CR1_TAMP4E +#define RTC_TAMPER_ALL (RTC_TAMPER_1 | RTC_TAMPER_2 |\ + RTC_TAMPER_3 | RTC_TAMPER_4 |\ + RTC_TAMPER_5 | RTC_TAMPER_6) +#else +#define RTC_TAMPER_ALL (RTC_TAMPER_1 | RTC_TAMPER_2 |\ + RTC_TAMPER_3) +#endif /* TAMP_CR1_TAMP4E */ +/** + * @} + */ + +/** @defgroup RTCEx_Internal_Tamper_Pins RTCEx Internal Tamper Pins Definition + * @{ + */ +#define RTC_INT_TAMPER_3 TAMP_CR1_ITAMP3E +#define RTC_INT_TAMPER_5 TAMP_CR1_ITAMP5E +#define RTC_INT_TAMPER_6 TAMP_CR1_ITAMP6E +#define RTC_INT_TAMPER_7 TAMP_CR1_ITAMP7E +#define RTC_INT_TAMPER_8 TAMP_CR1_ITAMP8E +#define RTC_INT_TAMPER_9 TAMP_CR1_ITAMP9E +#define RTC_INT_TAMPER_11 TAMP_CR1_ITAMP11E +#define RTC_INT_TAMPER_12 TAMP_CR1_ITAMP12E +#define RTC_INT_TAMPER_13 TAMP_CR1_ITAMP13E + +#define RTC_INT_TAMPER_ALL (RTC_INT_TAMPER_3 | RTC_INT_TAMPER_5 |\ + RTC_INT_TAMPER_6 | RTC_INT_TAMPER_7 |\ + RTC_INT_TAMPER_8 | RTC_INT_TAMPER_9 |\ + RTC_INT_TAMPER_11| RTC_INT_TAMPER_12|\ + RTC_INT_TAMPER_13) +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_Trigger RTCEx Tamper Trigger + * @{ + */ +#define RTC_TAMPERTRIGGER_RISINGEDGE 0U /*!< Warning : Filter must be RTC_TAMPERFILTER_DISABLE */ +#define RTC_TAMPERTRIGGER_FALLINGEDGE 1U /*!< Warning : Filter must be RTC_TAMPERFILTER_DISABLE */ +#define RTC_TAMPERTRIGGER_LOWLEVEL 2U /*!< Warning : Filter must not be RTC_TAMPERFILTER_DISABLE */ +#define RTC_TAMPERTRIGGER_HIGHLEVEL 3U /*!< Warning : Filter must not be RTC_TAMPERFILTER_DISABLE */ +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_MaskFlag RTCEx Tamper MaskFlag + * @{ + */ +#define RTC_TAMPERMASK_FLAG_DISABLE 0U +#define RTC_TAMPERMASK_FLAG_ENABLE 1U +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_Maskable_nb RTCEx Tampers maskable number + * @{ + */ +#define RTC_TAMPER_MASKABLE_NB 3U +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_EraseBackUp RTCEx Tamper EraseBackUp + * @{ + */ +#define RTC_TAMPER_ERASE_BACKUP_ENABLE 0U +#define RTC_TAMPER_ERASE_BACKUP_DISABLE 1U +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_Filter RTCEx Tamper Filter + * @{ + */ +#define RTC_TAMPERFILTER_DISABLE 0U /*!< Tamper filter is disabled */ +#define RTC_TAMPERFILTER_2SAMPLE TAMP_FLTCR_TAMPFLT_0 /*!< Tamper is activated after 2 consecutive samples at the active level */ +#define RTC_TAMPERFILTER_4SAMPLE TAMP_FLTCR_TAMPFLT_1 /*!< Tamper is activated after 4 consecutive samples at the active level */ +#define RTC_TAMPERFILTER_8SAMPLE TAMP_FLTCR_TAMPFLT /*!< Tamper is activated after 8 consecutive samples at the active level */ +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_Sampling_Frequencies RTCEx Tamper Sampling Frequencies + * @{ + */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 0U /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 32768 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 TAMP_FLTCR_TAMPFREQ_0 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 16384 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 TAMP_FLTCR_TAMPFREQ_1 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 8192 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 (TAMP_FLTCR_TAMPFREQ_0 | TAMP_FLTCR_TAMPFREQ_1) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 4096 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 TAMP_FLTCR_TAMPFREQ_2 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 2048 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 (TAMP_FLTCR_TAMPFREQ_0 | TAMP_FLTCR_TAMPFREQ_2) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 1024 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 (TAMP_FLTCR_TAMPFREQ_1 | TAMP_FLTCR_TAMPFREQ_2) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 512 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 (TAMP_FLTCR_TAMPFREQ_0 | TAMP_FLTCR_TAMPFREQ_1 | \ + TAMP_FLTCR_TAMPFREQ_2) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 256 */ +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_Pin_Precharge_Duration RTCEx Tamper Pin Precharge Duration + * @{ + */ +#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK 0U /*!< Tamper pins are pre-charged before sampling during 1 RTCCLK cycle */ +#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK TAMP_FLTCR_TAMPPRCH_0 /*!< Tamper pins are pre-charged before sampling during 2 RTCCLK cycles */ +#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK TAMP_FLTCR_TAMPPRCH_1 /*!< Tamper pins are pre-charged before sampling during 4 RTCCLK cycles */ +#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK (TAMP_FLTCR_TAMPPRCH_0 | TAMP_FLTCR_TAMPPRCH_1) /*!< Tamper pins are pre-charged before sampling during 8 RTCCLK cycles */ +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_Pull_UP RTCEx Tamper Pull UP + * @{ + */ +#define RTC_TAMPER_PULLUP_ENABLE 0U /*!< Tamper pins are pre-charged before sampling */ +#define RTC_TAMPER_PULLUP_DISABLE TAMP_FLTCR_TAMPPUDIS /*!< Tamper pins pre-charge is disabled */ +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection RTCEx Tamper TimeStamp On Tamper Detection Definitions + * @{ + */ +#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE 0U /*!< TimeStamp on Tamper Detection event is not saved */ +#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE RTC_CR_TAMPTS /*!< TimeStamp on Tamper Detection event saved */ +/** + * @} + */ + +/** @defgroup RTCEx_Tamper_Detection_Output RTCEx Tamper detection output Definitions + * @{ + */ +#if defined(RTC_CR_TAMPOE) +#define RTC_TAMPERDETECTIONOUTPUT_DISABLE 0U /*!< Tamper detection output disable on TAMPALRM */ +#define RTC_TAMPERDETECTIONOUTPUT_ENABLE RTC_CR_TAMPOE /*!< Tamper detection output enable on TAMPALRM */ +#endif /* RTC_CR_TAMPOE */ +/** + * @} + */ + + +/** @defgroup RTCEx_Tamper_Interrupt RTCEx Tamper Interrupt + * @{ + */ +#define RTC_IT_TAMP_1 TAMP_IER_TAMP1IE /*!< Tamper 1 Interrupt */ +#define RTC_IT_TAMP_2 TAMP_IER_TAMP2IE /*!< Tamper 2 Interrupt */ +#define RTC_IT_TAMP_3 TAMP_IER_TAMP3IE /*!< Tamper 3 Interrupt */ +#ifdef TAMP_IER_TAMP4IE +#define RTC_IT_TAMP_4 TAMP_IER_TAMP4IE /*!< Tamper 4 Interrupt */ +#define RTC_IT_TAMP_5 TAMP_IER_TAMP5IE /*!< Tamper 5 Interrupt */ +#define RTC_IT_TAMP_6 TAMP_IER_TAMP6IE /*!< Tamper 6 Interrupt */ +#define RTC_IT_TAMP_ALL (RTC_IT_TAMP_1 | RTC_IT_TAMP_2 |\ + RTC_IT_TAMP_3 | RTC_IT_TAMP_4 |\ + RTC_IT_TAMP_5 | RTC_IT_TAMP_6) +#else +#define RTC_IT_TAMP_ALL (RTC_IT_TAMP_1 | RTC_IT_TAMP_2 | RTC_IT_TAMP_3) +#endif /* TAMP_IER_TAMP4IE */ +/** + * @} + */ + +/** @defgroup RTCEx_Internal_Tamper_Interrupt RTCEx Internal Tamper Interrupt + * @{ + */ +#define RTC_IT_INT_TAMP_3 TAMP_IER_ITAMP3IE /*!< Tamper 3 internal Interrupt */ +#define RTC_IT_INT_TAMP_5 TAMP_IER_ITAMP5IE /*!< Tamper 5 internal Interrupt */ +#define RTC_IT_INT_TAMP_6 TAMP_IER_ITAMP6IE /*!< Tamper 6 internal Interrupt */ +#define RTC_IT_INT_TAMP_7 TAMP_IER_ITAMP7IE /*!< Tamper 7 internal Interrupt */ +#define RTC_IT_INT_TAMP_8 TAMP_IER_ITAMP8IE /*!< Tamper 8 internal Interrupt */ +#define RTC_IT_INT_TAMP_9 TAMP_IER_ITAMP9IE /*!< Tamper 9 internal Interrupt */ +#define RTC_IT_INT_TAMP_11 TAMP_IER_ITAMP11IE /*!< Tamper 11 internal Interrupt */ +#define RTC_IT_INT_TAMP_12 TAMP_IER_ITAMP12IE /*!< Tamper 12 internal Interrupt */ +#define RTC_IT_INT_TAMP_13 TAMP_IER_ITAMP13IE /*!< Tamper 13 internal Interrupt */ +#define RTC_IT_INT_TAMP_ALL (RTC_IT_INT_TAMP_3 | RTC_IT_INT_TAMP_5 |\ + RTC_IT_INT_TAMP_6 | RTC_IT_INT_TAMP_7 |\ + RTC_IT_INT_TAMP_8 | RTC_IT_INT_TAMP_9 |\ + RTC_IT_INT_TAMP_11| RTC_IT_INT_TAMP_12|\ + RTC_IT_INT_TAMP_13) +/** + * @} + */ + +/** @defgroup RTCEx_Flags RTCEx Flags + * @{ + */ +#define RTC_FLAG_TAMP_1 TAMP_SR_TAMP1F +#define RTC_FLAG_TAMP_2 TAMP_SR_TAMP2F +#define RTC_FLAG_TAMP_3 TAMP_SR_TAMP3F +#ifdef TAMP_SR_TAMP4F +#define RTC_FLAG_TAMP_4 TAMP_SR_TAMP4F +#define RTC_FLAG_TAMP_5 TAMP_SR_TAMP5F +#define RTC_FLAG_TAMP_6 TAMP_SR_TAMP6F +#define RTC_FLAG_TAMP_ALL (RTC_FLAG_TAMP_1 | RTC_FLAG_TAMP_2 | RTC_FLAG_TAMP_3 |\ + RTC_FLAG_TAMP_4 | RTC_FLAG_TAMP_5 | RTC_FLAG_TAMP_6) +#else +#define RTC_FLAG_TAMP_ALL (RTC_FLAG_TAMP_1 | RTC_FLAG_TAMP_2 | RTC_FLAG_TAMP_3) +#endif /* TAMP_SR_TAMP4F */ + + +#define RTC_FLAG_INT_TAMP_3 TAMP_SR_ITAMP3F +#define RTC_FLAG_INT_TAMP_5 TAMP_SR_ITAMP5F +#define RTC_FLAG_INT_TAMP_6 TAMP_SR_ITAMP6F +#define RTC_FLAG_INT_TAMP_7 TAMP_SR_ITAMP7F +#define RTC_FLAG_INT_TAMP_8 TAMP_SR_ITAMP8F +#define RTC_FLAG_INT_TAMP_9 TAMP_SR_ITAMP9F +#define RTC_FLAG_INT_TAMP_11 TAMP_SR_ITAMP11F +#define RTC_FLAG_INT_TAMP_12 TAMP_SR_ITAMP12F +#define RTC_FLAG_INT_TAMP_13 TAMP_SR_ITAMP13F +#define RTC_FLAG_INT_TAMP_ALL (RTC_FLAG_INT_TAMP_3 | RTC_FLAG_INT_TAMP_5 |\ + RTC_FLAG_INT_TAMP_6 | RTC_FLAG_INT_TAMP_7 |\ + RTC_FLAG_INT_TAMP_8 | RTC_FLAG_INT_TAMP_9 |\ + RTC_FLAG_INT_TAMP_11| RTC_FLAG_INT_TAMP_12|\ + RTC_FLAG_INT_TAMP_13) +/** + * @} + */ + + +/** @defgroup RTCEx_ActiveTamper_Enable RTCEx_ActiveTamper_Enable Definitions + * @{ + */ +#define RTC_ATAMP_ENABLE 1U +#define RTC_ATAMP_DISABLE 0U +/** + * @} + */ + +/** @defgroup RTCEx_ActiveTamper_Interrupt RTCEx_ActiveTamper_Interrupt Definitions + * @{ + */ +#define RTC_ATAMP_INTERRUPT_ENABLE 1U +#define RTC_ATAMP_INTERRUPT_DISABLE 0U +/** + * @} + */ + +/** @defgroup RTCEx_ActiveTamper_Filter RTCEx_ActiveTamper_Filter Definitions + * @{ + */ +#define RTC_ATAMP_FILTER_ENABLE TAMP_ATCR1_FLTEN +#define RTC_ATAMP_FILTER_DISABLE 0U +/** + * @} + */ + +/** @defgroup RTCEx_ActiveTamper_Async_prescaler RTCEx Active_Tamper_Asynchronous_Prescaler clock Definitions + * @{ + */ +#define RTC_ATAMP_ASYNCPRES_RTCCLK 0U /*!< RTCCLK */ +#define RTC_ATAMP_ASYNCPRES_RTCCLK_2 TAMP_ATCR1_ATCKSEL_0 /*!< RTCCLK/2 */ +#define RTC_ATAMP_ASYNCPRES_RTCCLK_4 TAMP_ATCR1_ATCKSEL_1 /*!< RTCCLK/4 */ +#define RTC_ATAMP_ASYNCPRES_RTCCLK_8 (TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/8 */ +#define RTC_ATAMP_ASYNCPRES_RTCCLK_16 TAMP_ATCR1_ATCKSEL_2 /*!< RTCCLK/16 */ +#define RTC_ATAMP_ASYNCPRES_RTCCLK_32 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/32 */ +#define RTC_ATAMP_ASYNCPRES_RTCCLK_64 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1) /*!< RTCCLK/64 */ +#define RTC_ATAMP_ASYNCPRES_RTCCLK_128 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/128 */ +/** + * @} + */ + +/** @defgroup RTCEx_ActiveTamper_Sel RTCEx Active Tamper selection Definition + * @{ + */ +#define RTC_ATAMP_1 0U /*!< Tamper 1 */ +#define RTC_ATAMP_2 1U /*!< Tamper 2 */ +#define RTC_ATAMP_3 2U /*!< Tamper 3 */ +#define RTC_ATAMP_4 3U /*!< Tamper 4 */ +#define RTC_ATAMP_5 4U /*!< Tamper 5 */ +#define RTC_ATAMP_6 5U /*!< Tamper 6 */ +/** + * @} + */ + +/** @defgroup RTCEx_MonotonicCounter_Instance RTCEx Monotonic Counter Instance Definition + * @{ + */ +#define RTC_MONOTONIC_COUNTER_1 0U /*!< Monotonic counter 1 */ +/** + * @} + */ + + +/** @defgroup RTCEx_Backup_Registers RTCEx Backup Registers Definition + * @{ + */ +#define RTC_BKP_NUMBER RTC_BKP_NB +#define RTC_BKP_DR0 0x00U +#define RTC_BKP_DR1 0x01U +#define RTC_BKP_DR2 0x02U +#define RTC_BKP_DR3 0x03U +#define RTC_BKP_DR4 0x04U +#define RTC_BKP_DR5 0x05U +#define RTC_BKP_DR6 0x06U +#define RTC_BKP_DR7 0x07U +#define RTC_BKP_DR8 0x08U +#define RTC_BKP_DR9 0x09U +#define RTC_BKP_DR10 0x0AU +#define RTC_BKP_DR11 0x0BU +#define RTC_BKP_DR12 0x0CU +#define RTC_BKP_DR13 0x0DU +#define RTC_BKP_DR14 0x0EU +#define RTC_BKP_DR15 0x0FU +#define RTC_BKP_DR16 0x10U +#define RTC_BKP_DR17 0x11U +#define RTC_BKP_DR18 0x12U +#define RTC_BKP_DR19 0x13U +#define RTC_BKP_DR20 0x14U +#define RTC_BKP_DR21 0x15U +#define RTC_BKP_DR22 0x16U +#define RTC_BKP_DR23 0x17U +#define RTC_BKP_DR24 0x18U +#define RTC_BKP_DR25 0x19U +#define RTC_BKP_DR26 0x1AU +#define RTC_BKP_DR27 0x1BU +#define RTC_BKP_DR28 0x1CU +#define RTC_BKP_DR29 0x1DU +#define RTC_BKP_DR30 0x1EU +#define RTC_BKP_DR31 0x1FU +/** + * @} + */ + +/** @defgroup RTCEx_Binary_Mode RTC Binary Mode (32-bit free-running counter configuration). + * Warning : It Should not be confused with the Binary format @ref RTC_Input_parameter_format_definitions. + * @{ + */ +#define RTC_BINARY_NONE 0U /*!< Free running BCD calendar mode (Binary mode disabled) */ +#define RTC_BINARY_ONLY RTC_ICSR_BIN_0 /*!< Free running Binary mode (BCD mode disabled) */ +#define RTC_BINARY_MIX RTC_ICSR_BIN_1 /*!< Free running BCD calendar and Binary modes */ +/** + * @} + */ + +/** @defgroup RTCEx_Binary_mix_BCDU If Binary mode is RTC_BINARY_MIX, the BCD calendar second is incremented + * using the SSR Least Significant Bits. + * @{ + */ +#define RTC_BINARY_MIX_BCDU_0 0U /*!< The 1s BCD calendar increment is generated each time SS[7:0] = 0 */ +#define RTC_BINARY_MIX_BCDU_1 (0x1UL << RTC_ICSR_BCDU_Pos) /*!< The 1s BCD calendar increment is generated each time SS[8:0] = 0 */ +#define RTC_BINARY_MIX_BCDU_2 (0x2UL << RTC_ICSR_BCDU_Pos) /*!< The 1s BCD calendar increment is generated each time SS[9:0] = 0 */ +#define RTC_BINARY_MIX_BCDU_3 (0x3UL << RTC_ICSR_BCDU_Pos) /*!< The 1s BCD calendar increment is generated each time SS[10:0] = 0 */ +#define RTC_BINARY_MIX_BCDU_4 (0x4UL << RTC_ICSR_BCDU_Pos) /*!< The 1s BCD calendar increment is generated each time SS[11:0] = 0 */ +#define RTC_BINARY_MIX_BCDU_5 (0x5UL << RTC_ICSR_BCDU_Pos) /*!< The 1s BCD calendar increment is generated each time SS[12:0] = 0 */ +#define RTC_BINARY_MIX_BCDU_6 (0x6UL << RTC_ICSR_BCDU_Pos) /*!< The 1s BCD calendar increment is generated each time SS[13:0] = 0 */ +#define RTC_BINARY_MIX_BCDU_7 (0x7UL << RTC_ICSR_BCDU_Pos) /*!< The 1s BCD calendar increment is generated each time SS[14:0] = 0 */ +/** + * @} + */ + +/** @defgroup RTCEx_Alarm_Sub_Seconds_binary_Masks_Definitions RTC Alarm Sub Seconds with binary or mix mode + * Masks Definitions. + * @{ + */ +#define RTC_ALARMSUBSECONDBINMASK_ALL 0U /*!< All Alarm SS fields are masked.There is no comparison on sub seconds for Alarm */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_1 (1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:1] are don't care in Alarm comparison. Only SS[0] is compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_2 (2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:2] are don't care in Alarm comparison. Only SS[1:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_3 (3UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:3] are don't care in Alarm comparison. Only SS[2:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_4 (4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:4] are don't care in Alarm comparison. Only SS[3:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_5 (5UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:5] are don't care in Alarm comparison. Only SS[4:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_6 (6UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:6] are don't care in Alarm comparison. Only SS[5:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_7 (7UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:7] are don't care in Alarm comparison. Only SS[6:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_8 (8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:8] are don't care in Alarm comparison. Only SS[7:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_9 (9UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:9] are don't care in Alarm comparison. Only SS[8:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_10 (10UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:10] are don't care in Alarm comparison. Only SS[9:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_11 (11UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:11] are don't care in Alarm comparison. Only SS[10:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_12 (12UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:12] are don't care in Alarm comparison.Only SS[11:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_13 (13UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:13] are don't care in Alarm comparison. Only SS[12:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_14 (14UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:14] are don't care in Alarm comparison. Only SS[13:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_15 (15UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:15] are don't care in Alarm comparison. Only SS[14:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_16 (16UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:16] are don't care in Alarm comparison. Only SS[15:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_17 (17UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:17] are don't care in Alarm comparison. Only SS[16:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_18 (18UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:18] are don't care in Alarm comparison. Only SS[17:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_19 (19UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:19] are don't care in Alarm comparison. Only SS[18:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_20 (20UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:20] are don't care in Alarm comparison. Only SS[19:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_21 (21UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:21] are don't care in Alarm comparison. Only SS[20:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_22 (22UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:22] are don't care in Alarm comparison. Only SS[21:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_23 (23UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:23] are don't care in Alarm comparison. Only SS[22:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_24 (24UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:24] are don't care in Alarm comparison. Only SS[23:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_25 (25UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:25] are don't care in Alarm comparison. Only SS[24:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_26 (26UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:26] are don't care in Alarm comparison. Only SS[25:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_27 (27UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:27] are don't care in Alarm comparison. Only SS[26:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_28 (28UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:28] are don't care in Alarm comparison. Only SS[27:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_29 (29UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:29] are don't care in Alarm comparison. Only SS[28:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31_30 (30UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31:30] are don't care in Alarm comparison. Only SS[29:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_SS31 (31UL << RTC_ALRMASSR_MASKSS_Pos) /*!< SS[31] is don't care in Alarm comparison. Only SS[30:0] are compared */ +#define RTC_ALARMSUBSECONDBINMASK_NONE RTC_ALRMASSR_MASKSS /*!< SS[31:0] are compared and must match to activate alarm */ +/** + * @} + */ + +/** @defgroup RTCEx_Alarm_Sub_Seconds_binary_Clear_Definitions RTC Alarm Sub Seconds + * with binary mode auto clear Definitions + * @{ + */ +#define RTC_ALARMSUBSECONDBIN_AUTOCLR_NO 0UL /*!< The synchronous Binary counter(SS[31:0] in RTC_SSR) is free-running */ +#define RTC_ALARMSUBSECONDBIN_AUTOCLR_YES RTC_ALRMASSR_SSCLR +/*!< The synchronous Binary counter (SS[31:0] in RTC_SSR) is running from 0xFFFF FFFF to RTC_ALRMABINR -> SS[31:0] + value and is automatically reloaded with 0xFFFF FFFF whenreaching RTC_ALRMABINR -> SS[31:0]. */ +/** + * @} + */ + +#ifdef RTC_SECCFGR_SEC +/** @defgroup RTCEx_RTC_Secure_Full RTCEx Secure Definition + * @{ + */ +#define RTC_SECURE_FULL_YES RTC_SECCFGR_SEC /*!< RTC full secure */ +#define RTC_SECURE_FULL_NO 0U /*!< RTC is not full secure, features can be unsecure. See RTCEx_RTC_NonSecure_Features */ +/** + * @} + */ + +/** @defgroup RTCEx_RTC_NonSecure_Features RTCEx Secure Features Definition + * @{ + */ +#define RTC_NONSECURE_FEATURE_NONE 0U +#define RTC_NONSECURE_FEATURE_INIT RTC_SECCFGR_INITSEC /*!< Initialization */ +#define RTC_NONSECURE_FEATURE_CAL RTC_SECCFGR_CALSEC /*!< Calibration */ +#define RTC_NONSECURE_FEATURE_TS RTC_SECCFGR_TSSEC /*!< Time stamp */ +#define RTC_NONSECURE_FEATURE_WUT RTC_SECCFGR_WUTSEC /*!< Wake up timer */ +#define RTC_NONSECURE_FEATURE_ALRA RTC_SECCFGR_ALRASEC /*!< Alarm A */ +#define RTC_NONSECURE_FEATURE_ALRB RTC_SECCFGR_ALRBSEC /*!< Alarm B */ + +#define RTC_NONSECURE_FEATURE_ALL (RTC_SECCFGR_INITSEC | RTC_SECCFGR_CALSEC | \ + RTC_SECCFGR_TSSEC | RTC_SECCFGR_WUTSEC | \ + RTC_SECCFGR_ALRASEC | RTC_SECCFGR_ALRBSEC) +/** + * @} + */ +#endif /* RTC_SECCFGR_SEC */ + +#ifdef TAMP_SECCFGR_TAMPSEC +/** @defgroup RTCEx_TAMP_Secure_Full RTCEx TAMP Secure Definition + * @{ + */ +#define TAMP_SECURE_FULL_YES TAMP_SECCFGR_TAMPSEC /*!< TAMPER full secure */ +#define TAMP_SECURE_FULL_NO 0U /*!< TAMPER is not secure */ +/** + * @} + */ +#endif /* TAMP_SECCFGR_TAMPSEC*/ + +#ifdef TAMP_SECCFGR_CNT1SEC +/** @defgroup RTCEx_TAMP_Monotonic_Counter_Secure RTCEx TAMP Monotonic Counter Secure Definition + * @{ + */ +#define TAMP_MONOTONIC_CNT_SECURE_YES TAMP_SECCFGR_CNT1SEC /*!< TAMPER Monotonic Counter secure */ +#define TAMP_MONOTONIC_CNT_SECURE_NO 0U /*!< TAMPER Monotonic Counter is not secure */ +/** + * @} + */ +#endif /* TAMP_SECCFGR_CNT1SEC */ + +/** @defgroup RTCEx_RTC_Privilege_Full RTCEx Privilege Full Definition + * @{ + */ +#define RTC_PRIVILEGE_FULL_YES RTC_PRIVCFGR_PRIV +#define RTC_PRIVILEGE_FULL_NO 0U +/** + * @} + */ + +/** @defgroup RTCEx_RTC_Privilege_Features RTCEx Privilege Features Definition + * @{ + */ +#define RTC_PRIVILEGE_FEATURE_NONE 0U +#define RTC_PRIVILEGE_FEATURE_INIT RTC_PRIVCFGR_INITPRIV /*!< Initialization */ +#define RTC_PRIVILEGE_FEATURE_CAL RTC_PRIVCFGR_CALPRIV /*!< Calibration */ +#define RTC_PRIVILEGE_FEATURE_TS RTC_PRIVCFGR_TSPRIV /*!< Time stamp */ +#define RTC_PRIVILEGE_FEATURE_WUT RTC_PRIVCFGR_WUTPRIV /*!< Wake up timer */ +#define RTC_PRIVILEGE_FEATURE_ALRA RTC_PRIVCFGR_ALRAPRIV /*!< Alarm A */ +#define RTC_PRIVILEGE_FEATURE_ALRB RTC_PRIVCFGR_ALRBPRIV /*!< Alarm B */ + +#define RTC_PRIVILEGE_FEATURE_ALL (RTC_PRIVCFGR_INITPRIV | RTC_PRIVCFGR_CALPRIV | \ + RTC_PRIVCFGR_TSPRIV | RTC_PRIVCFGR_WUTPRIV | \ + RTC_PRIVCFGR_ALRAPRIV | RTC_PRIVCFGR_ALRBPRIV) +/** + * @} + */ + +/** @defgroup RTCEx_TAMP_Privilege_Full RTCEx TAMP security Definition + * @{ + */ +#define TAMP_PRIVILEGE_FULL_YES TAMP_PRIVCFGR_TAMPPRIV +#define TAMP_PRIVILEGE_FULL_NO 0U +/** + * @} + */ + +/** @defgroup RTCEx_TAMP_Device_Secrets_Erase_Conf RTCEx TAMP Device Secrets Erase Configuration Definition + * @{ + */ +#define TAMP_DEVICESECRETS_ERASE_NONE 0U /*! < No Erase */ +#define TAMP_DEVICESECRETS_ERASE_SRAM2 TAMP_RPCFGR_RPCFG_1 /*!< SRAM2 */ +#define TAMP_DEVICESECRETS_ERASE_RHUK TAMP_RPCFGR_RPCFG_2 /*!< RHUK */ +#define TAMP_DEVICESECRETS_ERASE_ICACHE TAMP_RPCFGR_RPCFG_3 /*!< ICACHE */ +#define TAMP_DEVICESECRETS_ERASE_SAES_AES_HASH TAMP_RPCFGR_RPCFG_4 /*!< SAES, AES and HASH */ +#define TAMP_DEVICESECRETS_ERASE_PKA_SRAM TAMP_RPCFGR_RPCFG_5 /*!< Initialization */ +#define TAMP_DEVICESECRETS_ERASE_ALL TAMP_RPCFGR_RPCFG /*!< All */ +/** + * @} + */ + +/** @defgroup RTCEx_TAMP_Monotonic_Counter_Privilege RTCEx TAMP Monotonic Counter Privilege Definition + * @{ + */ +#define TAMP_MONOTONIC_CNT_PRIVILEGE_YES TAMP_PRIVCFGR_CNT1PRIV +#define TAMP_MONOTONIC_CNT_PRIVILEGE_NO 0U +/** + * @} + */ + +/** @defgroup RTCEx_Backup_Reg_Privilege_zone RTCEx Privilege Backup register privilege zone Definition + * @{ + */ +#define RTC_PRIVILEGE_BKUP_ZONE_NONE 0U +#define RTC_PRIVILEGE_BKUP_ZONE_1 TAMP_PRIVCFGR_BKPRWPRIV +#define RTC_PRIVILEGE_BKUP_ZONE_2 TAMP_PRIVCFGR_BKPWPRIV +#define RTC_PRIVILEGE_BKUP_ZONE_ALL (RTC_PRIVILEGE_BKUP_ZONE_1 | RTC_PRIVILEGE_BKUP_ZONE_2) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup RTCEx_Exported_Macros RTCEx Exported Macros + * @{ + */ + +/** @brief Clear the specified RTC pending flag. + * @param __HANDLE__ specifies the RTC Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be any combination of the following values: + * @arg @ref RTC_CLEAR_SSRUF Clear SSR underflow flag + * @arg @ref RTC_CLEAR_TSOVF Clear Time-stamp overflow flag + * @arg @ref RTC_CLEAR_TSF Clear Time-stamp flag + * @arg @ref RTC_CLEAR_WUTF Clear Wakeup timer flag + * @arg @ref RTC_CLEAR_ALRBF Clear Alarm B flag + * @arg @ref RTC_CLEAR_ALRAF Clear Alarm A flag + * @retval None + */ +#define __HAL_RTC_CLEAR_FLAG(__HANDLE__, __FLAG__) (RTC->SCR = (__FLAG__)) + +/** @brief Check whether the specified RTC flag is set or not. + * @param __HANDLE__ specifies the RTC Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be any combination of the following values: + * @arg @ref RTC_FLAG_RECALPF Recalibration pending Flag + * @arg @ref RTC_FLAG_INITF Initialization flag + * @arg @ref RTC_FLAG_RSF Registers synchronization flag + * @arg @ref RTC_FLAG_INITS Initialization status flag + * @arg @ref RTC_FLAG_SHPF Shift operation pending flag + * @arg @ref RTC_FLAG_WUTWF Wakeup timer write flag + * @arg @ref RTC_FLAG_TSOVF Time-stamp overflow flag + * @arg @ref RTC_FLAG_TSF Time-stamp flag + * @arg @ref RTC_FLAG_WUTF Wakeup timer flag + * @arg @ref RTC_FLAG_ALRBF Alarm B flag + * @arg @ref RTC_FLAG_ALRAF Alarm A flag + * @retval The state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_RTC_GET_FLAG(__HANDLE__, __FLAG__)( \ + ((__FLAG__) == RTC_FLAG_RECALPF) ? (READ_BIT(RTC->ICSR, RTC_ICSR_RECALPF) == \ + RTC_ICSR_RECALPF) : \ + ((__FLAG__) == RTC_FLAG_INITF) ? (READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == \ + RTC_ICSR_INITF) : \ + ((__FLAG__) == RTC_FLAG_RSF) ? (READ_BIT(RTC->ICSR, RTC_ICSR_RSF) == \ + RTC_ICSR_RSF) : \ + ((__FLAG__) == RTC_FLAG_INITS) ? (READ_BIT(RTC->ICSR, RTC_ICSR_INITS) == \ + RTC_ICSR_INITS) : \ + ((__FLAG__) == RTC_FLAG_SHPF) ? (READ_BIT(RTC->ICSR, RTC_ICSR_SHPF) == \ + RTC_ICSR_SHPF) : \ + ((__FLAG__) == RTC_FLAG_WUTWF) ? (READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == \ + RTC_ICSR_WUTWF) : \ + ((__FLAG__) == RTC_FLAG_SSRUF) ? (READ_BIT(RTC->SR, RTC_SR_SSRUF) == \ + RTC_SR_SSRUF) : \ + ((__FLAG__) == RTC_FLAG_TSOVF) ? (READ_BIT(RTC->SR, RTC_SR_TSOVF) == \ + RTC_SR_TSOVF) : \ + ((__FLAG__) == RTC_FLAG_TSF) ? (READ_BIT(RTC->SR, RTC_SR_TSF) == \ + RTC_SR_TSF): \ + ((__FLAG__) == RTC_FLAG_WUTF) ? (READ_BIT(RTC->SR, RTC_SR_WUTF) == \ + RTC_SR_WUTF): \ + ((__FLAG__) == RTC_FLAG_ALRBF) ? (READ_BIT(RTC->SR, RTC_SR_ALRBF) == \ + RTC_SR_ALRBF) : \ + ((__FLAG__) == RTC_FLAG_ALRAF) ? (READ_BIT(RTC->SR, RTC_SR_ALRAF) == \ + RTC_SR_ALRAF) : \ + (0U)) /* Return 0 because it is an invalid parameter value */ + +/* ---------------------------------WAKEUPTIMER---------------------------------*/ +/** @defgroup RTCEx_WakeUp_Timer RTC WakeUp Timer + * @{ + */ + +/** + * @brief Enable the RTC WakeUp Timer peripheral. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) (RTC->CR |= (RTC_CR_WUTE)) + +/** + * @brief Disable the RTC WakeUp Timer peripheral. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) (RTC->CR &= ~(RTC_CR_WUTE)) + +/** + * @brief Enable the RTC WakeUpTimer interrupt. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be enabled. + * This parameter can be: + * @arg @ref RTC_IT_WUT WakeUpTimer interrupt + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR |= (RTC_CR_WUTIE)) + +/** + * @brief Disable the RTC WakeUpTimer interrupt. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be disabled. + * This parameter can be: + * @arg @ref RTC_IT_WUT WakeUpTimer interrupt + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR &= ~(RTC_CR_WUTIE)) + +/** + * @brief Check whether the specified RTC WakeUpTimer interrupt has occurred or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt to check. + * This parameter can be: + * @arg @ref RTC_IT_WUT WakeUpTimer interrupt + * @retval The state of __INTERRUPT__ (TRUE or FALSE). + */ +#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (((RTC->MISR) & (RTC_MISR_WUTMF)) != 0U) + +/** + * @brief Check whether the specified RTC Wake Up timer interrupt has been enabled or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Wake Up timer interrupt sources to check. + * This parameter can be: + * @arg @ref RTC_IT_WUT WakeUpTimer interrupt + * @retval The state of __INTERRUPT__ (TRUE or FALSE). + */ +#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((RTC->CR) & (RTC_CR_WUTIE)) != 0U) + +/** + * @brief Get the selected RTC WakeUpTimers flag status. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC WakeUpTimer Flag is pending or not. + * This parameter can be: + * @arg @ref RTC_FLAG_WUTF + * @arg @ref RTC_FLAG_WUTWF + * @retval The state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__)( \ + ((__FLAG__) == RTC_FLAG_WUTF) ? (READ_BIT(RTC->SR, RTC_SR_WUTF) == RTC_SR_WUTF):\ + ((__FLAG__) == RTC_FLAG_WUTWF) ? (READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == RTC_ICSR_WUTWF):\ + (0U)) /* Return 0 because it is an invalid parameter value */ + +/** + * @brief Clear the RTC Wake Up timers pending flags. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC WakeUpTimer Flag to clear. + * This parameter can be: + * @arg @ref RTC_FLAG_WUTF + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) (SET_BIT(RTC->SCR, RTC_SCR_CWUTF)) + +/** + * @} + */ + +/* ---------------------------------TIMESTAMP---------------------------------*/ +/** @defgroup RTCEx_Timestamp RTC Timestamp + * @{ + */ + +/** + * @brief Enable the RTC TimeStamp peripheral. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) (RTC->CR |= (RTC_CR_TSE)) + +/** + * @brief Disable the RTC TimeStamp peripheral. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) (RTC->CR &= ~(RTC_CR_TSE)) + +/** + * @brief Enable the RTC TimeStamp interrupt. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt source to be enabled. + * This parameter can be: + * @arg @ref RTC_IT_TS TimeStamp interrupt + * @retval None + */ +#define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR |= (RTC_CR_TSIE)) + +/** + * @brief Disable the RTC TimeStamp interrupt. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt source to be disabled. + * This parameter can be: + * @arg @ref RTC_IT_TS TimeStamp interrupt + * @retval None + */ +#define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR &= ~(RTC_CR_TSIE)) + +/** + * @brief Check whether the specified RTC TimeStamp interrupt has occurred or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt to check. + * This parameter can be: + * @arg @ref RTC_IT_TS TimeStamp interrupt + * @retval The state of __INTERRUPT__ (TRUE or FALSE). + */ +#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (((RTC->MISR) & (RTC_MISR_TSMF)) != 0U) + +/** + * @brief Check whether the specified RTC Time Stamp interrupt has been enabled or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Time Stamp interrupt source to check. + * This parameter can be: + * @arg @ref RTC_IT_TS TimeStamp interrupt + * @retval The state of __INTERRUPT__ (TRUE or FALSE). + */ +#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((RTC->CR) & (RTC_CR_TSIE)) != 0U) + +/** + * @brief Get the selected RTC TimeStamps flag status. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC TimeStamp Flag is pending or not. + * This parameter can be: + * @arg @ref RTC_FLAG_TSF + * @arg @ref RTC_FLAG_TSOVF + * @retval The state of __FLAG__ (TRUE or FALSE) or 255 if invalid parameter. + */ +#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__)( \ + ((__FLAG__) == RTC_FLAG_TSF) ? (READ_BIT(RTC->SR, RTC_SR_TSF) == RTC_SR_TSF):\ + ((__FLAG__) == RTC_FLAG_TSOVF) ? (READ_BIT(RTC->SR, RTC_SR_TSOVF) == RTC_SR_TSOVF):\ + (0U)) /* Return 0 because it is an invalid parameter value */ + +/** + * @brief Clear the RTC Time Stamps pending flags. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC TimeStamp Flag to clear. + * This parameter can be: + * @arg @ref RTC_FLAG_TSF + * @arg @ref RTC_FLAG_TSOVF + * @retval None + */ +#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__)( \ + ((__FLAG__) == RTC_FLAG_TSF) ? (SET_BIT(RTC->SCR, RTC_SCR_CTSF)):\ + ((__FLAG__) == RTC_FLAG_TSOVF) ? (SET_BIT(RTC->SCR, RTC_SCR_CTSOVF)):\ + (0U)) /* Dummy action because is an invalid parameter value */ + +/** + * @brief Enable the RTC TimeStamp on Tamper detection. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_TAMPTS_ENABLE(__HANDLE__) (RTC->CR |= (RTC_CR_TAMPTS)) + +/** + * @brief Disable the RTC TimeStamp on Tamper detection. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_TAMPTS_DISABLE(__HANDLE__) (RTC->CR &= ~(RTC_CR_TAMPTS)) + +#if defined(RTC_CR_TAMPOE) +/** + * @brief Enable the RTC Tamper detection output. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_TAMPOE_ENABLE(__HANDLE__) (RTC->CR |= (RTC_CR_TAMPOE)) + +/** + * @brief Disable the RTC Tamper detection output. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_TAMPOE_DISABLE(__HANDLE__) (RTC->CR &= ~(RTC_CR_TAMPOE)) + +#endif /* RTC_CR_TAMPOE */ + +/** + * @} + */ + + +/* ------------------------------Calibration----------------------------------*/ +/** @defgroup RTCEx_Calibration RTC Calibration + * @{ + */ + +/** + * @brief Enable the RTC calibration output. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__) (RTC->CR |= (RTC_CR_COE)) + +/** + * @brief Disable the calibration output. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__) (RTC->CR &= ~(RTC_CR_COE)) + +/** + * @brief Enable the clock reference detection. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__) (RTC->CR |= (RTC_CR_REFCKON)) + +/** + * @brief Disable the clock reference detection. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) (RTC->CR &= ~(RTC_CR_REFCKON)) + +/** + * @brief Get the selected RTC shift operations flag status. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC shift operation Flag is pending or not. + * This parameter can be: + * @arg @ref RTC_FLAG_SHPF + * @retval The state of __FLAG__ (TRUE or FALSE) + */ +#define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT(RTC->ICSR, RTC_ICSR_SHPF) == RTC_ICSR_SHPF)) +/** + * @} + */ + +/* ------------------------------Tamper----------------------------------*/ +/** @defgroup RTCEx_Tamper RTCEx tamper + * @{ + */ + +/** + * @brief Enable the TAMP Tamper input detection. + * @param __HANDLE__ specifies the RTC handle. + * @param __TAMPER__ specifies the RTC Tamper source to be enabled. + * This parameter can be any combination of the following values: + * @arg RTC_TAMPER_ALL: All tampers + * @arg RTC_TAMPER_1: Tamper1 + * @arg RTC_TAMPER_2: Tamper2 + * @arg RTC_TAMPER_3: Tamper3 + * @arg RTC_TAMPER_4: Tamper4 + * @arg RTC_TAMPER_5: Tamper5 + * @arg RTC_TAMPER_6: Tamper6 + * @retval None + */ +#define __HAL_RTC_TAMPER_ENABLE(__HANDLE__, __TAMPER__) (TAMP->CR1 |= (__TAMPER__)) + +/** + * @brief Disable the TAMP Tamper input detection. + * @param __HANDLE__ specifies the RTC handle. + * @param __TAMPER__ specifies the RTC Tamper sources to be enabled. + * This parameter can be any combination of the following values: + * @arg RTC_TAMPER_ALL: All tampers + * @arg RTC_TAMPER_1: Tamper1 + * @arg RTC_TAMPER_2: Tamper2 + * @arg RTC_TAMPER_3: Tamper3 + * @arg RTC_TAMPER_4: Tamper4 + * @arg RTC_TAMPER_5: Tamper5 + * @arg RTC_TAMPER_6: Tamper6 + */ +#define __HAL_RTC_TAMPER_DISABLE(__HANDLE__, __TAMPER__) (TAMP->CR1 &= ~(__TAMPER__)) + + +/**************************************************************************************************/ +/** + * @brief Enable the TAMP Tamper interrupt. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Tamper interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg RTC_IT_TAMP_ALL: All tampers interrupts + * @arg RTC_IT_TAMP_1: Tamper1 interrupt + * @arg RTC_IT_TAMP_2: Tamper2 interrupt + * @arg RTC_IT_TAMP_3: Tamper3 interrupt + * @arg RTC_IT_TAMP_4: Tamper4 interrupt + * @arg RTC_IT_TAMP_5: Tamper5 interrupt + * @arg RTC_IT_TAMP_6: Tamper6 interrupt + * @arg RTC_IT_INT_TAMP_ALL: All Internal Tamper interrupts + * @arg RTC_IT_INT_TAMP_3: Internal Tamper3 interrupt + * @arg RTC_IT_INT_TAMP_5: Internal Tamper5 interrupt + * @arg RTC_IT_INT_TAMP_6: Internal Tamper6 interrupt + * @arg RTC_IT_INT_TAMP_7: Internal Tamper7 interrupt + * @arg RTC_IT_INT_TAMP_8: Internal Tamper8 interrupt + * @arg RTC_IT_INT_TAMP_9: Internal Tamper9 interrupt + * @arg RTC_IT_INT_TAMP_11: Internal Tamper11 interrupt + * @arg RTC_IT_INT_TAMP_12: Internal Tamper12 interrupt + * @arg RTC_IT_INT_TAMP_13: Internal Tamper13 interrupt + * @retval None + */ +#define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) (TAMP->IER |= (__INTERRUPT__)) + +/** + * @brief Disable the TAMP Tamper interrupt. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Tamper interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg RTC_IT_TAMP_ALL: All tampers interrupts + * @arg RTC_IT_TAMP_1: Tamper1 interrupt + * @arg RTC_IT_TAMP_2: Tamper2 interrupt + * @arg RTC_IT_TAMP_3: Tamper3 interrupt + * @arg RTC_IT_TAMP_4: Tamper4 interrupt + * @arg RTC_IT_TAMP_5: Tamper5 interrupt + * @arg RTC_IT_TAMP_6: Tamper6 interrupt + * @arg RTC_IT_INT_TAMP_ALL: All Internal Tamper interrupts + * @arg RTC_IT_INT_TAMP_3: Internal Tamper3 interrupt + * @arg RTC_IT_INT_TAMP_5: Internal Tamper5 interrupt + * @arg RTC_IT_INT_TAMP_6: Internal Tamper6 interrupt + * @arg RTC_IT_INT_TAMP_7: Internal Tamper7 interrupt + * @arg RTC_IT_INT_TAMP_8: Internal Tamper8 interrupt + * @arg RTC_IT_INT_TAMP_9: Internal Tamper9 interrupt + * @arg RTC_IT_INT_TAMP_11: Internal Tamper11 interrupt + * @arg RTC_IT_INT_TAMP_12: Internal Tamper12 interrupt + * @arg RTC_IT_INT_TAMP_13: Internal Tamper13 interrupt + * @retval None + */ +#define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) (TAMP->IER &= ~(__INTERRUPT__)) + + +/**************************************************************************************************/ +/** + * @brief Check whether the specified RTC Tamper interrupt has occurred or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Tamper interrupt to check. + * This parameter can be: + * @arg RTC_IT_TAMP_ALL: All tampers interrupts + * @arg RTC_IT_TAMP_1: Tamper1 interrupt + * @arg RTC_IT_TAMP_2: Tamper2 interrupt + * @arg RTC_IT_TAMP_3: Tamper3 interrupt + * @arg RTC_IT_TAMP_4: Tamper4 interrupt + * @arg RTC_IT_TAMP_5: Tamper5 interrupt + * @arg RTC_IT_TAMP_6: Tamper6 interrupt + * @arg RTC_IT_INT_TAMP_ALL: All Internal Tamper interrupts + * @arg RTC_IT_INT_TAMP_3: Internal Tamper3 interrupt + * @arg RTC_IT_INT_TAMP_5: Internal Tamper5 interrupt + * @arg RTC_IT_INT_TAMP_6: Internal Tamper6 interrupt + * @arg RTC_IT_INT_TAMP_7: Internal Tamper7 interrupt + * @arg RTC_IT_INT_TAMP_8: Internal Tamper8 interrupt + * @arg RTC_IT_INT_TAMP_9: Internal Tamper9 interrupt + * @arg RTC_IT_INT_TAMP_11: Internal Tamper11 interrupt + * @arg RTC_IT_INT_TAMP_12: Internal Tamper12 interrupt + * @arg RTC_IT_INT_TAMP_13: Internal Tamper13 interrupt + * @retval The state of __INTERRUPT__ (TRUE or FALSE) + */ +#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((TAMP->MISR) & (__INTERRUPT__)) != 0U) + +/** + * @brief Check whether the specified RTC Tamper interrupt has been enabled or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Tamper interrupt source to check. + * This parameter can be: + * @arg RTC_IT_TAMP_ALL: All tampers interrupts + * @arg RTC_IT_TAMP_1: Tamper1 interrupt + * @arg RTC_IT_TAMP_2: Tamper2 interrupt + * @arg RTC_IT_TAMP_3: Tamper3 interrupt + * @arg RTC_IT_TAMP_4: Tamper4 interrupt + * @arg RTC_IT_TAMP_5: Tamper5 interrupt + * @arg RTC_IT_TAMP_6: Tamper6 interrupt + * @arg RTC_IT_INT_TAMP_ALL: All internal tampers interrupts + * @arg RTC_IT_INT_TAMP_3: Internal Tamper3 interrupt + * @arg RTC_IT_INT_TAMP_5: Internal Tamper5 interrupt + * @arg RTC_IT_INT_TAMP_6: Internal Tamper6 interrupt + * @arg RTC_IT_INT_TAMP_7: Internal Tamper7 interrupt + * @arg RTC_IT_INT_TAMP_8: Internal Tamper8 interrupt + * @arg RTC_IT_INT_TAMP_9: Internal Tamper9 interrupt + * @arg RTC_IT_INT_TAMP_11: Internal Tamper11 interrupt + * @arg RTC_IT_INT_TAMP_12: Internal Tamper12 interrupt + * @arg RTC_IT_INT_TAMP_13: Internal Tamper13 interrupt + * @retval The state of __INTERRUPT__ (TRUE or FALSE) + */ +#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((TAMP->IER) & (__INTERRUPT__)) != 0U) + +/** + * @brief Get the selected RTC Tampers flag status. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Tamper Flag is pending or not. + * This parameter can be: + * @arg RTC_FLAG_TAMP_ALL: All tampers flag + * @arg RTC_FLAG_TAMP_1: Tamper1 flag + * @arg RTC_FLAG_TAMP_2: Tamper2 flag + * @arg RTC_FLAG_TAMP_3: Tamper3 flag + * @arg RTC_FLAG_TAMP_4: Tamper4 flag + * @arg RTC_FLAG_TAMP_5: Tamper5 flag + * @arg RTC_FLAG_TAMP_6: Tamper6 flag + * @arg RTC_FLAG_INT_TAMP_ALL: All Internal Tamper flags + * @arg RTC_FLAG_INT_TAMP_3: Internal Tamper3 flag + * @arg RTC_FLAG_INT_TAMP_5: Internal Tamper5 flag + * @arg RTC_FLAG_INT_TAMP_6: Internal Tamper6 flag + * @arg RTC_FLAG_INT_TAMP_7: Internal Tamper7 flag + * @arg RTC_FLAG_INT_TAMP_8: Internal Tamper8 flag + * @arg RTC_FLAG_INT_TAMP_9: Internal Tamper9 flag + * @arg RTC_FLAG_INT_TAMP_11: Internal Tamper11 flag + * @arg RTC_FLAG_INT_TAMP_12: Internal Tamper12 flag + * @arg RTC_FLAG_INT_TAMP_13: Internal Tamper13 flag + * @retval The state of __FLAG__ (TRUE or FALSE) + */ +#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((TAMP->SR) & (__FLAG__)) != 0U) + +/** + * @brief Clear the RTC Tamper's pending flags. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Tamper Flag to clear. + * This parameter can be: + * @arg RTC_FLAG_TAMP_ALL: All tampers flag + * @arg RTC_FLAG_TAMP_1: Tamper1 flag + * @arg RTC_FLAG_TAMP_2: Tamper2 flag + * @arg RTC_FLAG_TAMP_3: Tamper3 flag + * @arg RTC_FLAG_TAMP_4: Tamper4 flag + * @arg RTC_FLAG_TAMP_5: Tamper5 flag + * @arg RTC_FLAG_TAMP_6: Tamper6 flag + * @arg RTC_FLAG_INT_TAMP_ALL: All Internal Tamper flags + * @arg RTC_FLAG_INT_TAMP_3: Internal Tamper3 flag + * @arg RTC_FLAG_INT_TAMP_5: Internal Tamper5 flag + * @arg RTC_FLAG_INT_TAMP_6: Internal Tamper6 flag + * @arg RTC_FLAG_INT_TAMP_7: Internal Tamper7 flag + * @arg RTC_FLAG_INT_TAMP_8: Internal Tamper8 flag + * @arg RTC_FLAG_INT_TAMP_9: Internal Tamper9 flag + * @arg RTC_FLAG_INT_TAMP_11: Internal Tamper11 flag + * @arg RTC_FLAG_INT_TAMP_12: Internal Tamper12 flag + * @arg RTC_FLAG_INT_TAMP_13: Internal Tamper13 flag + * @retval None + */ +#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((TAMP->SCR) = (__FLAG__)) +/** + * @} + */ + +/* --------------------------------- SSR Underflow ---------------------------------*/ +/** @defgroup RTCEx_SSR_Underflow RTC SSR Underflow + * @{ + */ + +/** + * @brief Enable the RTC SSRU interrupt. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC SSRU interrupt sources to be enabled. + * This parameter can be: + * @arg @ref RTC_IT_SSRU SSRU interrupt + * @retval None + */ +#define __HAL_RTC_SSRU_ENABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR |= (RTC_CR_SSRUIE)) + +/** + * @brief Disable the RTC SSRU interrupt. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC SSRU interrupt sources to be disabled. + * This parameter can be: + * @arg @ref RTC_IT_SSRU SSRU interrupt + * @retval None + */ +#define __HAL_RTC_SSRU_DISABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR &= ~(RTC_CR_SSRUIE)) + + +/** + * @brief Check whether the specified RTC SSRU interrupt has occurred or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC SSRU interrupt to check. + * This parameter can be: + * @arg @ref RTC_IT_SSRU SSRU interrupt + * @retval The state of __INTERRUPT__ (TRUE or FALSE) + */ +#define __HAL_RTC_SSRU_GET_IT(__HANDLE__, __INTERRUPT__) (((RTC->MISR) & (RTC_MISR_SSRUMF)) != 0U) +/** + * @brief Check whether the specified RTC Wake Up timer interrupt has been enabled or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Wake Up timer interrupt sources to check. + * This parameter can be: + * @arg @ref RTC_IT_SSRU SSRU interrupt + * @retval The state of __INTERRUPT__ (TRUE or FALSE) + */ +#define __HAL_RTC_SSRU_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((RTC->CR) & (RTC_CR_SSRUIE)) != 0U) + +/** + * @brief Get the selected RTC SSRU's flag status. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC SSRU Flag is pending or not. + * This parameter can be: + * @arg @ref RTC_FLAG_SSRUF + * @retval The state of __FLAG__ (TRUE or FALSE) + */ +#define __HAL_RTC_SSRU_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT(RTC->SR, RTC_SR_SSRUF) == RTC_SR_SSRUF)) + +/** + * @brief Clear the RTC Wake Up timer's pending flags. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC SSRU Flag to clear. + * This parameter can be: + * @arg @ref RTC_FLAG_SSRUF + * @retval None + */ +#define __HAL_RTC_SSRU_CLEAR_FLAG(__HANDLE__, __FLAG__) (SET_BIT(RTC->SCR, RTC_SCR_CSSRUF)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions + * @{ + */ + +/* RTC TimeStamp functions *****************************************/ +/** @defgroup RTCEx_Exported_Functions_Group1 Extended RTC TimeStamp functions + * @{ + */ + +#ifdef RTC_CR_TSE +HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin); +HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin); +HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc); +#endif /* RTC_CR_TSE */ +HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(const RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, + RTC_DateTypeDef *sTimeStampDate, uint32_t Format); +void HAL_RTCEx_TimeStampIRQHandler(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(const RTC_HandleTypeDef *hrtc, uint32_t Timeout); +void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc); +/** + * @} + */ + + +/* RTC Wake-up functions ******************************************************/ +/** @defgroup RTCEx_Exported_Functions_Group2 Extended RTC Wake-up functions + * @{ + */ + +HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock); +HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock, + uint32_t WakeUpAutoClr); +HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc); +uint32_t HAL_RTCEx_GetWakeUpTimer(const RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(const RTC_HandleTypeDef *hrtc, uint32_t Timeout); +/** + * @} + */ + +/* Extended Control functions ************************************************/ +/** @defgroup RTCEx_Exported_Functions_Group3 Extended Peripheral Control functions + * @{ + */ + +HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, + uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue); +HAL_StatusTypeDef HAL_RTCEx_SetLowPowerCalib(RTC_HandleTypeDef *hrtc, uint32_t LowPowerCalib); +HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS); +#if defined(RTC_CR_COSEL) +HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput); +HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc); +#endif /* RTC_CR_COSEL */ +#if defined(RTC_CR_REFCKON) +HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc); +#endif /* RTC_CR_REFCKON */ +HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterIncrement(const RTC_HandleTypeDef *hrtc, uint32_t Instance); +HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterGet(const RTC_HandleTypeDef *hrtc, uint32_t Instance, uint32_t *pValue); +HAL_StatusTypeDef HAL_RTCEx_SetSSRU_IT(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_DeactivateSSRU(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_SSRUIRQHandler(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_SSRUEventCallback(RTC_HandleTypeDef *hrtc); + +/** + * @} + */ + +/* Extended RTC features functions *******************************************/ +/** @defgroup RTCEx_Exported_Functions_Group4 Extended features functions + * @{ + */ + +void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(const RTC_HandleTypeDef *hrtc, uint32_t Timeout); +/** + * @} + */ + +/** @defgroup RTCEx_Exported_Functions_Group5 Extended RTC Tamper functions + * @{ + */ +HAL_StatusTypeDef HAL_RTCEx_SetTamper(const RTC_HandleTypeDef *hrtc, const RTC_TamperTypeDef *sTamper); +HAL_StatusTypeDef HAL_RTCEx_SetActiveTampers(RTC_HandleTypeDef *hrtc, const RTC_ActiveTampersTypeDef *sAllTamper); +HAL_StatusTypeDef HAL_RTCEx_SetActiveSeed(RTC_HandleTypeDef *hrtc, const uint32_t *pSeed); +HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(const RTC_HandleTypeDef *hrtc, const RTC_TamperTypeDef *sTamper); +HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(const RTC_HandleTypeDef *hrtc, uint32_t Tamper); +HAL_StatusTypeDef HAL_RTCEx_DeactivateActiveTampers(const RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_PollForTamperEvent(const RTC_HandleTypeDef *hrtc, uint32_t Tamper, uint32_t Timeout); +HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper(const RTC_HandleTypeDef *hrtc, + const RTC_InternalTamperTypeDef *sIntTamper); +HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper_IT(const RTC_HandleTypeDef *hrtc, + const RTC_InternalTamperTypeDef *sIntTamper); +HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTamper(const RTC_HandleTypeDef *hrtc, uint32_t IntTamper); +HAL_StatusTypeDef HAL_RTCEx_PollForInternalTamperEvent(const RTC_HandleTypeDef *hrtc, uint32_t IntTamper, + uint32_t Timeout); +#if defined(TAMP_SECCFGR_BHKLOCK) +HAL_StatusTypeDef HAL_RTCEx_LockBootHardwareKey(const RTC_HandleTypeDef *hrtc); +#endif /* TAMP_SECCFGR_BHKLOCK */ +void HAL_RTCEx_TamperIRQHandler(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_Tamper4EventCallback(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_Tamper5EventCallback(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_Tamper6EventCallback(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_InternalTamper3EventCallback(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_InternalTamper5EventCallback(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_InternalTamper6EventCallback(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_InternalTamper7EventCallback(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_InternalTamper8EventCallback(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_InternalTamper9EventCallback(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_InternalTamper11EventCallback(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_InternalTamper12EventCallback(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_InternalTamper13EventCallback(RTC_HandleTypeDef *hrtc); + +/** + * @} + */ + +/** @defgroup RTCEx_Exported_Functions_Group6 Extended RTC Backup register functions + * @{ + */ +void HAL_RTCEx_BKUPWrite(const RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data); +uint32_t HAL_RTCEx_BKUPRead(const RTC_HandleTypeDef *hrtc, uint32_t BackupRegister); +void HAL_RTCEx_BKUPErase(const RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_BKUPBlock(const RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_BKUPUnblock(const RTC_HandleTypeDef *hrtc); +#ifdef TAMP_RPCFGR_RPCFG +void HAL_RTCEx_ConfigEraseDeviceSecrets(const RTC_HandleTypeDef *hrtc, uint32_t DeviceSecretConf); +#endif /* TAMP_RPCFGR_RPCFG */ +/** + * @} + */ + +#if defined(RTC_SECCFGR_SEC) +/** @defgroup RTCEx_Exported_Functions_Group7 Extended RTC secure functions + * @{ + */ +HAL_StatusTypeDef HAL_RTCEx_SecureModeGet(const RTC_HandleTypeDef *hrtc, RTC_SecureStateTypeDef *secureState); +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +HAL_StatusTypeDef HAL_RTCEx_SecureModeSet(const RTC_HandleTypeDef *hrtc, const RTC_SecureStateTypeDef *secureState); +#endif /* #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/** + * @} + */ +#endif /* RTC_SECCFGR_SEC */ + +#if defined(TAMP_PRIVCFGR_TAMPPRIV) +/** @defgroup RTCEx_Exported_Functions_Group8 Extended RTC privilege functions + * @{ + */ +HAL_StatusTypeDef HAL_RTCEx_PrivilegeModeSet(const RTC_HandleTypeDef *hrtc, + const RTC_PrivilegeStateTypeDef *privilegeState); +HAL_StatusTypeDef HAL_RTCEx_PrivilegeModeGet(const RTC_HandleTypeDef *hrtc, RTC_PrivilegeStateTypeDef *privilegeState); +/** + * @} + */ +#endif /* TAMP_PRIVCFGR_TAMPPRIV */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup RTCEx_Private_Macros RTCEx Private Macros + * @{ + */ + +/** @defgroup RTCEx_IS_RTC_Definitions Private macros to check input parameters + * @{ + */ +#if defined(RTC_CR_TSEDGE) +#define IS_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \ + ((EDGE) == RTC_TIMESTAMPEDGE_FALLING)) +#endif /* RTC_CR_TSEDGE */ + +#define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_DEFAULT)) + +#define IS_RTC_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \ + ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE)) + +#if defined(RTC_CR_TAMPOE) +#define IS_RTC_TAMPER_TAMPERDETECTIONOUTPUT(MODE) (((MODE) == RTC_TAMPERDETECTIONOUTPUT_ENABLE) || \ + ((MODE) == RTC_TAMPERDETECTIONOUTPUT_DISABLE)) +#endif /* RTC_CR_TAMPOE */ + +#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16) || \ + ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8) || \ + ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4) || \ + ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV2) || \ + ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \ + ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS)) + +#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= RTC_WUTR_WUT) + +#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \ + ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \ + ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_8SEC)) + +#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \ + ((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_RESET)) + +#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= RTC_CALR_CALM) + +#define IS_RTC_LOW_POWER_CALIB(LPCAL) (((LPCAL) == RTC_LPCAL_SET) || \ + ((LPCAL) == RTC_LPCAL_RESET)) + + +#define IS_RTC_TAMPER(__TAMPER__) ((((__TAMPER__) & RTC_TAMPER_ALL) != 0U) && \ + (((__TAMPER__) & ~RTC_TAMPER_ALL) == 0U)) + +#define IS_RTC_INTERNAL_TAMPER(__INT_TAMPER__) ((((__INT_TAMPER__) & RTC_INT_TAMPER_ALL) != 0U) && \ + (((__INT_TAMPER__) & ~RTC_INT_TAMPER_ALL) == 0U)) + +#define IS_RTC_TAMPER_TRIGGER(__TRIGGER__) (((__TRIGGER__) == RTC_TAMPERTRIGGER_RISINGEDGE) || \ + ((__TRIGGER__) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \ + ((__TRIGGER__) == RTC_TAMPERTRIGGER_LOWLEVEL) || \ + ((__TRIGGER__) == RTC_TAMPERTRIGGER_HIGHLEVEL)) + +#define IS_RTC_TAMPER_ERASE_MODE(__MODE__) (((__MODE__) == RTC_TAMPER_ERASE_BACKUP_ENABLE) || \ + ((__MODE__) == RTC_TAMPER_ERASE_BACKUP_DISABLE)) + +#define IS_RTC_TAMPER_MASKFLAG_STATE(__STATE__) (((__STATE__) == RTC_TAMPERMASK_FLAG_ENABLE) || \ + ((__STATE__) == RTC_TAMPERMASK_FLAG_DISABLE)) + +#define IS_RTC_TAMPER_FILTER(__FILTER__) (((__FILTER__) == RTC_TAMPERFILTER_DISABLE) || \ + ((__FILTER__) == RTC_TAMPERFILTER_2SAMPLE) || \ + ((__FILTER__) == RTC_TAMPERFILTER_4SAMPLE) || \ + ((__FILTER__) == RTC_TAMPERFILTER_8SAMPLE)) + +#define IS_RTC_TAMPER_SAMPLING_FREQ(__FREQ__) (((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \ + ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \ + ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \ + ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || \ + ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || \ + ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \ + ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512) || \ + ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256)) + +#define IS_RTC_TAMPER_PRECHARGE_DURATION(__DURATION__) (((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \ + ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \ + ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \ + ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK)) + +#define IS_RTC_TAMPER_PULLUP_STATE(__STATE__) (((__STATE__) == RTC_TAMPER_PULLUP_ENABLE) || \ + ((__STATE__) == RTC_TAMPER_PULLUP_DISABLE)) + +#define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION) \ + (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \ + ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE)) + +#define IS_RTC_ATAMPER_FILTER(__FILTER__) (((__FILTER__) == RTC_ATAMP_FILTER_ENABLE) || \ + ((__FILTER__) == RTC_ATAMP_FILTER_DISABLE)) + +#define IS_RTC_ATAMPER_OUTPUT_CHANGE_PERIOD(__PERIOD__) ((__PERIOD__) <= 7U) + +#define IS_RTC_ATAMPER_ASYNCPRES_RTCCLK(__PRESCALER__) (((__PRESCALER__) == RTC_ATAMP_ASYNCPRES_RTCCLK) || \ + ((__PRESCALER__) == RTC_ATAMP_ASYNCPRES_RTCCLK_2) || \ + ((__PRESCALER__) == RTC_ATAMP_ASYNCPRES_RTCCLK_4) || \ + ((__PRESCALER__) == RTC_ATAMP_ASYNCPRES_RTCCLK_8) || \ + ((__PRESCALER__) == RTC_ATAMP_ASYNCPRES_RTCCLK_16) || \ + ((__PRESCALER__) == RTC_ATAMP_ASYNCPRES_RTCCLK_32) || \ + ((__PRESCALER__) == RTC_ATAMP_ASYNCPRES_RTCCLK_64) || \ + ((__PRESCALER__) == RTC_ATAMP_ASYNCPRES_RTCCLK_128)) + + +#define IS_RTC_BKP(__BKP__) ((__BKP__) < RTC_BKP_NUMBER) + +#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_SHIFTADD1S_RESET) || \ + ((SEL) == RTC_SHIFTADD1S_SET)) + +#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= RTC_SHIFTR_SUBFS) + +#if defined(RTC_CR_COSEL) +#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CALIBOUTPUT_512HZ) || \ + ((OUTPUT) == RTC_CALIBOUTPUT_1HZ)) +#endif /* RTC_CR_COSEL */ + +#define IS_RTC_SECURE_FULL(__STATE__) (((__STATE__) == RTC_SECURE_FULL_YES) || \ + ((__STATE__) == RTC_SECURE_FULL_NO)) + +#define IS_RTC_NONSECURE_FEATURES(__FEATURES__) (((__FEATURES__) & ~RTC_NONSECURE_FEATURE_ALL) == 0U) + +#define IS_TAMP_SECURE_FULL(__STATE__) (((__STATE__) == TAMP_SECURE_FULL_YES) || \ + ((__STATE__) == TAMP_SECURE_FULL_NO)) + +#define IS_TAMP_MONOTONIC_CNT_SECURE(__STATE__) (((__STATE__) == TAMP_MONOTONIC_CNT_SECURE_YES) || \ + ((__STATE__) == TAMP_MONOTONIC_CNT_SECURE_NO)) + +#define IS_RTC_PRIVILEGE_FULL(__STATE__) (((__STATE__) == RTC_PRIVILEGE_FULL_YES) || \ + ((__STATE__) == RTC_PRIVILEGE_FULL_NO)) + +#define IS_RTC_PRIVILEGE_FEATURES(__FEATURES__) (((__FEATURES__) & ~RTC_PRIVILEGE_FEATURE_ALL) == 0U) + +#define IS_TAMP_PRIVILEGE_FULL(__STATE__) (((__STATE__) == TAMP_PRIVILEGE_FULL_YES) || \ + ((__STATE__) == TAMP_PRIVILEGE_FULL_NO)) + +#define IS_TAMP_MONOTONIC_CNT_PRIVILEGE(__STATE__) (((__STATE__) == TAMP_MONOTONIC_CNT_PRIVILEGE_YES) || \ + ((__STATE__) == TAMP_MONOTONIC_CNT_PRIVILEGE_NO)) + +#define IS_RTC_PRIVILEGE_BKUP_ZONE(__ZONES__) (((__ZONES__) & ~RTC_PRIVILEGE_BKUP_ZONE_ALL) == 0U) + +#define IS_RTC_BINARY_MODE(MODE) (((MODE) == RTC_BINARY_NONE) || \ + ((MODE) == RTC_BINARY_ONLY) || \ + ((MODE) == RTC_BINARY_MIX )) + +#define IS_RTC_BINARY_MIX_BCDU(BDCU) (((BDCU) == RTC_BINARY_MIX_BCDU_0) || \ + ((BDCU) == RTC_BINARY_MIX_BCDU_1) || \ + ((BDCU) == RTC_BINARY_MIX_BCDU_2) || \ + ((BDCU) == RTC_BINARY_MIX_BCDU_3) || \ + ((BDCU) == RTC_BINARY_MIX_BCDU_4) || \ + ((BDCU) == RTC_BINARY_MIX_BCDU_5) || \ + ((BDCU) == RTC_BINARY_MIX_BCDU_6) || \ + ((BDCU) == RTC_BINARY_MIX_BCDU_7)) + +#define IS_RTC_ALARM_SUB_SECOND_BINARY_MASK(MASK) (((MASK) == 0U) || \ + (((MASK) >= RTC_ALARMSUBSECONDBINMASK_SS31_1) &&\ + ((MASK) <= RTC_ALARMSUBSECONDBINMASK_NONE))) + +#define IS_RTC_ALARMSUBSECONDBIN_AUTOCLR(SEL) (((SEL) == RTC_ALARMSUBSECONDBIN_AUTOCLR_NO) || \ + ((SEL) == RTC_ALARMSUBSECONDBIN_AUTOCLR_YES)) +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WBAxx_HAL_RTC_EX_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_sai.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_sai.h new file mode 100644 index 0000000000..5a4d728267 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_sai.h @@ -0,0 +1,970 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_sai.h + * @author MCD Application Team + * @brief Header file of SAI HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_HAL_SAI_H +#define STM32WBAxx_HAL_SAI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal_def.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ +#if defined (SAI1) +/** @addtogroup SAI + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup SAI_Exported_Types SAI Exported Types + * @{ + */ + +/** @defgroup SAI_PDM_Structure_definition SAI PDM Structure definition + * @brief SAI PDM Init structure definition + * @{ + */ +typedef struct +{ + FunctionalState Activation; /*!< Enable/disable PDM interface */ + uint32_t MicPairsNbr; /*!< Specifies the number of microphone pairs used. + This parameter must be a number between Min_Data = 1 and Max_Data = 2. */ + uint32_t ClockEnable; /*!< Specifies which clock must be enabled. + This parameter can be a values combination of @ref SAI_PDM_ClockEnable */ +} SAI_PdmInitTypeDef; +/** + * @} + */ + +/** @defgroup SAI_Init_Structure_definition SAI Init Structure definition + * @brief SAI Init Structure definition + * @{ + */ +typedef struct +{ + uint32_t AudioMode; /*!< Specifies the SAI Block audio Mode. + This parameter can be a value of @ref SAI_Block_Mode */ + + uint32_t Synchro; /*!< Specifies SAI Block synchronization + This parameter can be a value of @ref SAI_Block_Synchronization */ + + uint32_t SynchroExt; /*!< Specifies SAI external output synchronization, this setup is common + for BlockA and BlockB + This parameter can be a value of @ref SAI_Block_SyncExt + @note If both audio blocks of same SAI are used, this parameter has + to be set to the same value for each audio block */ + + uint32_t MckOutput; /*!< Specifies whether master clock output will be generated or not. + This parameter can be a value of @ref SAI_Block_MckOutput */ + + uint32_t OutputDrive; /*!< Specifies when SAI Block outputs are driven. + This parameter can be a value of @ref SAI_Block_Output_Drive + @note This value has to be set before enabling the audio block + but after the audio block configuration. */ + + uint32_t NoDivider; /*!< Specifies whether master clock will be divided or not. + This parameter can be a value of @ref SAI_Block_NoDivider + @note If bit NODIV in the SAI_xCR1 register is cleared, the frame length + should be aligned to a number equal to a power of 2, from 8 to 256. + If bit NODIV in the SAI_xCR1 register is set, the frame length can + take any of the values from 8 to 256. */ + + uint32_t FIFOThreshold; /*!< Specifies SAI Block FIFO threshold. + This parameter can be a value of @ref SAI_Block_Fifo_Threshold */ + + uint32_t AudioFrequency; /*!< Specifies the audio frequency sampling. + This parameter can be a value of @ref SAI_Audio_Frequency */ + + uint32_t Mckdiv; /*!< Specifies the master clock divider. + This parameter must be a number between Min_Data = 0 and Max_Data = 63. + @note This parameter is used only if AudioFrequency is set to + SAI_AUDIO_FREQUENCY_MCKDIV otherwise it is internally computed. */ + + uint32_t MckOverSampling; /*!< Specifies the master clock oversampling. + This parameter can be a value of @ref SAI_Block_Mck_OverSampling */ + + uint32_t MonoStereoMode; /*!< Specifies if the mono or stereo mode is selected. + This parameter can be a value of @ref SAI_Mono_Stereo_Mode */ + + uint32_t CompandingMode; /*!< Specifies the companding mode type. + This parameter can be a value of @ref SAI_Block_Companding_Mode */ + + uint32_t TriState; /*!< Specifies the companding mode type. + This parameter can be a value of @ref SAI_TRIState_Management */ + + SAI_PdmInitTypeDef PdmInit; /*!< Specifies the PDM configuration. */ + + /* This part of the structure is automatically filled if your are using the high level initialisation + function HAL_SAI_InitProtocol */ + + uint32_t Protocol; /*!< Specifies the SAI Block protocol. + This parameter can be a value of @ref SAI_Block_Protocol */ + + uint32_t DataSize; /*!< Specifies the SAI Block data size. + This parameter can be a value of @ref SAI_Block_Data_Size */ + + uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. + This parameter can be a value of @ref SAI_Block_MSB_LSB_transmission */ + + uint32_t ClockStrobing; /*!< Specifies the SAI Block clock strobing edge sensitivity. + This parameter can be a value of @ref SAI_Block_Clock_Strobing */ +} SAI_InitTypeDef; + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_SAI_STATE_RESET = 0x00U, /*!< SAI not yet initialized or disabled */ + HAL_SAI_STATE_READY = 0x01U, /*!< SAI initialized and ready for use */ + HAL_SAI_STATE_BUSY = 0x02U, /*!< SAI internal process is ongoing */ + HAL_SAI_STATE_BUSY_TX = 0x12U, /*!< Data transmission process is ongoing */ + HAL_SAI_STATE_BUSY_RX = 0x22U, /*!< Data reception process is ongoing */ +} HAL_SAI_StateTypeDef; + +/** + * @brief SAI Callback prototype + */ +typedef void (*SAIcallback)(void); + +/** + * @} + */ + +/** @defgroup SAI_Frame_Structure_definition SAI Frame Structure definition + * @brief SAI Frame Init structure definition + * @note For SPDIF and AC97 protocol, these parameters are not used (set by hardware). + * @{ + */ +typedef struct +{ + + uint32_t FrameLength; /*!< Specifies the Frame length, the number of SCK clocks for each audio frame. + This parameter must be a number between Min_Data = 8 and Max_Data = 256. + @note If master clock MCLK_x pin is declared as an output, the frame length + should be aligned to a number equal to power of 2 in order to keep + in an audio frame, an integer number of MCLK pulses by bit Clock. */ + + uint32_t ActiveFrameLength; /*!< Specifies the Frame synchronization active level length. + This Parameter specifies the length in number of bit clock (SCK + 1) + of the active level of FS signal in audio frame. + This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ + + uint32_t FSDefinition; /*!< Specifies the Frame synchronization definition. + This parameter can be a value of @ref SAI_Block_FS_Definition */ + + uint32_t FSPolarity; /*!< Specifies the Frame synchronization Polarity. + This parameter can be a value of @ref SAI_Block_FS_Polarity */ + + uint32_t FSOffset; /*!< Specifies the Frame synchronization Offset. + This parameter can be a value of @ref SAI_Block_FS_Offset */ + +} SAI_FrameInitTypeDef; +/** + * @} + */ + +/** @defgroup SAI_Slot_Structure_definition SAI Slot Structure definition + * @brief SAI Block Slot Init Structure definition + * @note For SPDIF protocol, these parameters are not used (set by hardware). + * @note For AC97 protocol, only SlotActive parameter is used (the others are set by hardware). + * @{ + */ +typedef struct +{ + uint32_t FirstBitOffset; /*!< Specifies the position of first data transfer bit in the slot. + This parameter must be a number between Min_Data = 0 and Max_Data = 24 */ + + uint32_t SlotSize; /*!< Specifies the Slot Size. + This parameter can be a value of @ref SAI_Block_Slot_Size */ + + uint32_t SlotNumber; /*!< Specifies the number of slot in the audio frame. + This parameter must be a number between Min_Data = 1 and Max_Data = 16 */ + + uint32_t SlotActive; /*!< Specifies the slots in audio frame that will be activated. + This parameter can be a value of @ref SAI_Block_Slot_Active */ +} SAI_SlotInitTypeDef; +/** + * @} + */ + +/** @defgroup SAI_Handle_Structure_definition SAI Handle Structure definition + * @brief SAI handle Structure definition + * @{ + */ +typedef struct __SAI_HandleTypeDef +{ + SAI_Block_TypeDef *Instance; /*!< SAI Blockx registers base address */ + + SAI_InitTypeDef Init; /*!< SAI communication parameters */ + + SAI_FrameInitTypeDef FrameInit; /*!< SAI Frame configuration parameters */ + + SAI_SlotInitTypeDef SlotInit; /*!< SAI Slot configuration parameters */ + + uint8_t *pBuffPtr; /*!< Pointer to SAI transfer Buffer */ + + uint16_t XferSize; /*!< SAI transfer size */ + + uint16_t XferCount; /*!< SAI transfer counter */ + + DMA_HandleTypeDef *hdmatx; /*!< SAI Tx DMA handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< SAI Rx DMA handle parameters */ + + SAIcallback mutecallback; /*!< SAI mute callback */ + + void (*InterruptServiceRoutine)(struct __SAI_HandleTypeDef *hsai); /* function pointer for IRQ handler */ + + HAL_LockTypeDef Lock; /*!< SAI locking object */ + + __IO HAL_SAI_StateTypeDef State; /*!< SAI communication state */ + + __IO uint32_t ErrorCode; /*!< SAI Error code */ + +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + void (*RxCpltCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI receive complete callback */ + void (*RxHalfCpltCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI receive half complete callback */ + void (*TxCpltCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI transmit complete callback */ + void (*TxHalfCpltCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI transmit half complete callback */ + void (*ErrorCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI error callback */ + void (*MspInitCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI MSP init callback */ + void (*MspDeInitCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI MSP de-init callback */ +#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ +} SAI_HandleTypeDef; + +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) +/** + * @brief SAI callback ID enumeration definition + */ +typedef enum +{ + HAL_SAI_RX_COMPLETE_CB_ID = 0x00U, /*!< SAI receive complete callback ID */ + HAL_SAI_RX_HALFCOMPLETE_CB_ID = 0x01U, /*!< SAI receive half complete callback ID */ + HAL_SAI_TX_COMPLETE_CB_ID = 0x02U, /*!< SAI transmit complete callback ID */ + HAL_SAI_TX_HALFCOMPLETE_CB_ID = 0x03U, /*!< SAI transmit half complete callback ID */ + HAL_SAI_ERROR_CB_ID = 0x04U, /*!< SAI error callback ID */ + HAL_SAI_MSPINIT_CB_ID = 0x05U, /*!< SAI MSP init callback ID */ + HAL_SAI_MSPDEINIT_CB_ID = 0x06U /*!< SAI MSP de-init callback ID */ +} HAL_SAI_CallbackIDTypeDef; + +/** + * @brief SAI callback pointer definition + */ +typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai); +#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SAI_Exported_Constants SAI Exported Constants + * @{ + */ + +/** @defgroup SAI_Error_Code SAI Error Code + * @{ + */ +#define HAL_SAI_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_SAI_ERROR_OVR 0x00000001U /*!< Overrun Error */ +#define HAL_SAI_ERROR_UDR 0x00000002U /*!< Underrun error */ +#define HAL_SAI_ERROR_AFSDET 0x00000004U /*!< Anticipated Frame synchronisation detection */ +#define HAL_SAI_ERROR_LFSDET 0x00000008U /*!< Late Frame synchronisation detection */ +#define HAL_SAI_ERROR_CNREADY 0x00000010U /*!< codec not ready */ +#define HAL_SAI_ERROR_WCKCFG 0x00000020U /*!< Wrong clock configuration */ +#define HAL_SAI_ERROR_TIMEOUT 0x00000040U /*!< Timeout error */ +#define HAL_SAI_ERROR_DMA 0x00000080U /*!< DMA error */ +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) +#define HAL_SAI_ERROR_INVALID_CALLBACK 0x00000100U /*!< Invalid callback error */ +#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup SAI_Block_SyncExt SAI External synchronisation + * @{ + */ +#define SAI_SYNCEXT_DISABLE 0U +#define SAI_SYNCEXT_OUTBLOCKA_ENABLE 1U +#define SAI_SYNCEXT_OUTBLOCKB_ENABLE 2U +/** + * @} + */ + +/** @defgroup SAI_Block_MckOutput SAI Block Master Clock Output + * @{ + */ +#define SAI_MCK_OUTPUT_DISABLE 0x00000000U +#define SAI_MCK_OUTPUT_ENABLE SAI_xCR1_MCKEN +/** + * @} + */ + +/** @defgroup SAI_Protocol SAI Supported protocol + * @{ + */ +#define SAI_I2S_STANDARD 0U +#define SAI_I2S_MSBJUSTIFIED 1U +#define SAI_I2S_LSBJUSTIFIED 2U +#define SAI_PCM_LONG 3U +#define SAI_PCM_SHORT 4U +/** + * @} + */ + +/** @defgroup SAI_Protocol_DataSize SAI protocol data size + * @{ + */ +#define SAI_PROTOCOL_DATASIZE_16BIT 0U +#define SAI_PROTOCOL_DATASIZE_16BITEXTENDED 1U +#define SAI_PROTOCOL_DATASIZE_24BIT 2U +#define SAI_PROTOCOL_DATASIZE_32BIT 3U +/** + * @} + */ + +/** @defgroup SAI_Audio_Frequency SAI Audio Frequency + * @{ + */ +#define SAI_AUDIO_FREQUENCY_192K 192000U +#define SAI_AUDIO_FREQUENCY_96K 96000U +#define SAI_AUDIO_FREQUENCY_48K 48000U +#define SAI_AUDIO_FREQUENCY_44K 44100U +#define SAI_AUDIO_FREQUENCY_32K 32000U +#define SAI_AUDIO_FREQUENCY_24K 24000U +#define SAI_AUDIO_FREQUENCY_22K 22050U +#define SAI_AUDIO_FREQUENCY_16K 16000U +#define SAI_AUDIO_FREQUENCY_11K 11025U +#define SAI_AUDIO_FREQUENCY_8K 8000U +#define SAI_AUDIO_FREQUENCY_MCKDIV 0U +/** + * @} + */ + +/** @defgroup SAI_Block_Mck_OverSampling SAI Block Master Clock OverSampling + * @{ + */ +#define SAI_MCK_OVERSAMPLING_DISABLE 0x00000000U +#define SAI_MCK_OVERSAMPLING_ENABLE SAI_xCR1_OSR +/** + * @} + */ + +/** @defgroup SAI_PDM_ClockEnable SAI PDM Clock Enable + * @{ + */ +#define SAI_PDM_CLOCK1_ENABLE SAI_PDMCR_CKEN1 +#define SAI_PDM_CLOCK2_ENABLE SAI_PDMCR_CKEN2 +/** + * @} + */ + +/** @defgroup SAI_Block_Mode SAI Block Mode + * @{ + */ +#define SAI_MODEMASTER_TX 0x00000000U +#define SAI_MODEMASTER_RX SAI_xCR1_MODE_0 +#define SAI_MODESLAVE_TX SAI_xCR1_MODE_1 +#define SAI_MODESLAVE_RX (SAI_xCR1_MODE_1 | SAI_xCR1_MODE_0) + +/** + * @} + */ + +/** @defgroup SAI_Block_Protocol SAI Block Protocol + * @{ + */ +#define SAI_FREE_PROTOCOL 0x00000000U +#define SAI_SPDIF_PROTOCOL SAI_xCR1_PRTCFG_0 +#define SAI_AC97_PROTOCOL SAI_xCR1_PRTCFG_1 +/** + * @} + */ + +/** @defgroup SAI_Block_Data_Size SAI Block Data Size + * @{ + */ +#define SAI_DATASIZE_8 SAI_xCR1_DS_1 +#define SAI_DATASIZE_10 (SAI_xCR1_DS_1 | SAI_xCR1_DS_0) +#define SAI_DATASIZE_16 SAI_xCR1_DS_2 +#define SAI_DATASIZE_20 (SAI_xCR1_DS_2 | SAI_xCR1_DS_0) +#define SAI_DATASIZE_24 (SAI_xCR1_DS_2 | SAI_xCR1_DS_1) +#define SAI_DATASIZE_32 (SAI_xCR1_DS_2 | SAI_xCR1_DS_1 | SAI_xCR1_DS_0) +/** + * @} + */ + +/** @defgroup SAI_Block_MSB_LSB_transmission SAI Block MSB LSB transmission + * @{ + */ +#define SAI_FIRSTBIT_MSB 0x00000000U +#define SAI_FIRSTBIT_LSB SAI_xCR1_LSBFIRST +/** + * @} + */ + +/** @defgroup SAI_Block_Clock_Strobing SAI Block Clock Strobing + * @{ + */ +#define SAI_CLOCKSTROBING_FALLINGEDGE 0U +#define SAI_CLOCKSTROBING_RISINGEDGE 1U +/** + * @} + */ + +/** @defgroup SAI_Block_Synchronization SAI Block Synchronization + * @{ + */ +#define SAI_ASYNCHRONOUS 0U /*!< Asynchronous */ +#define SAI_SYNCHRONOUS 1U /*!< Synchronous with other block of same SAI */ +#define SAI_SYNCHRONOUS_EXT_SAI1 2U /*!< Synchronous with other SAI, SAI1 */ +#define SAI_SYNCHRONOUS_EXT_SAI2 3U /*!< Synchronous with other SAI, SAI2 */ +/** + * @} + */ + +/** @defgroup SAI_Block_Output_Drive SAI Block Output Drive + * @{ + */ +#define SAI_OUTPUTDRIVE_DISABLE 0x00000000U +#define SAI_OUTPUTDRIVE_ENABLE SAI_xCR1_OUTDRIV +/** + * @} + */ + +/** @defgroup SAI_Block_NoDivider SAI Block NoDivider + * @{ + */ +#define SAI_MASTERDIVIDER_ENABLE 0x00000000U +#define SAI_MASTERDIVIDER_DISABLE SAI_xCR1_NODIV +/** + * @} + */ + +/** @defgroup SAI_Block_FS_Definition SAI Block FS Definition + * @{ + */ +#define SAI_FS_STARTFRAME 0x00000000U +#define SAI_FS_CHANNEL_IDENTIFICATION SAI_xFRCR_FSDEF +/** + * @} + */ + +/** @defgroup SAI_Block_FS_Polarity SAI Block FS Polarity + * @{ + */ +#define SAI_FS_ACTIVE_LOW 0x00000000U +#define SAI_FS_ACTIVE_HIGH SAI_xFRCR_FSPOL +/** + * @} + */ + +/** @defgroup SAI_Block_FS_Offset SAI Block FS Offset + * @{ + */ +#define SAI_FS_FIRSTBIT 0x00000000U +#define SAI_FS_BEFOREFIRSTBIT SAI_xFRCR_FSOFF +/** + * @} + */ + +/** @defgroup SAI_Block_Slot_Size SAI Block Slot Size + * @{ + */ +#define SAI_SLOTSIZE_DATASIZE 0x00000000U +#define SAI_SLOTSIZE_16B SAI_xSLOTR_SLOTSZ_0 +#define SAI_SLOTSIZE_32B SAI_xSLOTR_SLOTSZ_1 +/** + * @} + */ + +/** @defgroup SAI_Block_Slot_Active SAI Block Slot Active + * @{ + */ +#define SAI_SLOT_NOTACTIVE 0x00000000U +#define SAI_SLOTACTIVE_0 0x00000001U +#define SAI_SLOTACTIVE_1 0x00000002U +#define SAI_SLOTACTIVE_2 0x00000004U +#define SAI_SLOTACTIVE_3 0x00000008U +#define SAI_SLOTACTIVE_4 0x00000010U +#define SAI_SLOTACTIVE_5 0x00000020U +#define SAI_SLOTACTIVE_6 0x00000040U +#define SAI_SLOTACTIVE_7 0x00000080U +#define SAI_SLOTACTIVE_8 0x00000100U +#define SAI_SLOTACTIVE_9 0x00000200U +#define SAI_SLOTACTIVE_10 0x00000400U +#define SAI_SLOTACTIVE_11 0x00000800U +#define SAI_SLOTACTIVE_12 0x00001000U +#define SAI_SLOTACTIVE_13 0x00002000U +#define SAI_SLOTACTIVE_14 0x00004000U +#define SAI_SLOTACTIVE_15 0x00008000U +#define SAI_SLOTACTIVE_ALL 0x0000FFFFU +/** + * @} + */ + +/** @defgroup SAI_Mono_Stereo_Mode SAI Mono Stereo Mode + * @{ + */ +#define SAI_STEREOMODE 0x00000000U +#define SAI_MONOMODE SAI_xCR1_MONO +/** + * @} + */ + +/** @defgroup SAI_TRIState_Management SAI TRIState Management + * @{ + */ +#define SAI_OUTPUT_NOTRELEASED 0x00000000U +#define SAI_OUTPUT_RELEASED SAI_xCR2_TRIS +/** + * @} + */ + +/** @defgroup SAI_Block_Fifo_Threshold SAI Block Fifo Threshold + * @{ + */ +#define SAI_FIFOTHRESHOLD_EMPTY 0x00000000U +#define SAI_FIFOTHRESHOLD_1QF SAI_xCR2_FTH_0 +#define SAI_FIFOTHRESHOLD_HF SAI_xCR2_FTH_1 +#define SAI_FIFOTHRESHOLD_3QF (SAI_xCR2_FTH_1 | SAI_xCR2_FTH_0) +#define SAI_FIFOTHRESHOLD_FULL SAI_xCR2_FTH_2 +/** + * @} + */ + +/** @defgroup SAI_Block_Companding_Mode SAI Block Companding Mode + * @{ + */ +#define SAI_NOCOMPANDING 0x00000000U +#define SAI_ULAW_1CPL_COMPANDING SAI_xCR2_COMP_1 +#define SAI_ALAW_1CPL_COMPANDING (SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0) +#define SAI_ULAW_2CPL_COMPANDING (SAI_xCR2_COMP_1 | SAI_xCR2_CPL) +#define SAI_ALAW_2CPL_COMPANDING (SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0 | SAI_xCR2_CPL) +/** + * @} + */ + +/** @defgroup SAI_Block_Mute_Value SAI Block Mute Value + * @{ + */ +#define SAI_ZERO_VALUE 0x00000000U +#define SAI_LAST_SENT_VALUE SAI_xCR2_MUTEVAL +/** + * @} + */ + +/** @defgroup SAI_Block_Interrupts_Definition SAI Block Interrupts Definition + * @{ + */ +#define SAI_IT_OVRUDR SAI_xIMR_OVRUDRIE +#define SAI_IT_MUTEDET SAI_xIMR_MUTEDETIE +#define SAI_IT_WCKCFG SAI_xIMR_WCKCFGIE +#define SAI_IT_FREQ SAI_xIMR_FREQIE +#define SAI_IT_CNRDY SAI_xIMR_CNRDYIE +#define SAI_IT_AFSDET SAI_xIMR_AFSDETIE +#define SAI_IT_LFSDET SAI_xIMR_LFSDETIE +/** + * @} + */ + +/** @defgroup SAI_Block_Flags_Definition SAI Block Flags Definition + * @{ + */ +#define SAI_FLAG_OVRUDR SAI_xSR_OVRUDR +#define SAI_FLAG_MUTEDET SAI_xSR_MUTEDET +#define SAI_FLAG_WCKCFG SAI_xSR_WCKCFG +#define SAI_FLAG_FREQ SAI_xSR_FREQ +#define SAI_FLAG_CNRDY SAI_xSR_CNRDY +#define SAI_FLAG_AFSDET SAI_xSR_AFSDET +#define SAI_FLAG_LFSDET SAI_xSR_LFSDET +/** + * @} + */ + +/** @defgroup SAI_Block_Fifo_Status_Level SAI Block Fifo Status Level + * @{ + */ +#define SAI_FIFOSTATUS_EMPTY 0x00000000U +#define SAI_FIFOSTATUS_LESS1QUARTERFULL 0x00010000U +#define SAI_FIFOSTATUS_1QUARTERFULL 0x00020000U +#define SAI_FIFOSTATUS_HALFFULL 0x00030000U +#define SAI_FIFOSTATUS_3QUARTERFULL 0x00040000U +#define SAI_FIFOSTATUS_FULL 0x00050000U +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup SAI_Exported_Macros SAI Exported Macros + * @brief macros to handle interrupts and specific configurations + * @{ + */ + +/** @brief Reset SAI handle state. + * @param __HANDLE__ specifies the SAI Handle. + * @retval None + */ +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) +#define __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_SAI_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SAI_STATE_RESET) +#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ + +/** @brief Enable the specified SAI interrupts. + * @param __HANDLE__ specifies the SAI Handle. + * @param __INTERRUPT__ specifies the interrupt source to enable or disable. + * This parameter can be one of the following values: + * @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable + * @arg SAI_IT_MUTEDET: Mute detection interrupt enable + * @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable + * @arg SAI_IT_FREQ: FIFO request interrupt enable + * @arg SAI_IT_CNRDY: Codec not ready interrupt enable + * @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable + * @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable + * @retval None + */ +#define __HAL_SAI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__)) + +/** @brief Disable the specified SAI interrupts. + * @param __HANDLE__ specifies the SAI Handle. + * @param __INTERRUPT__ specifies the interrupt source to enable or disable. + * This parameter can be one of the following values: + * @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable + * @arg SAI_IT_MUTEDET: Mute detection interrupt enable + * @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable + * @arg SAI_IT_FREQ: FIFO request interrupt enable + * @arg SAI_IT_CNRDY: Codec not ready interrupt enable + * @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable + * @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable + * @retval None + */ +#define __HAL_SAI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (~(__INTERRUPT__))) + +/** @brief Check whether the specified SAI interrupt source is enabled or not. + * @param __HANDLE__ specifies the SAI Handle. + * @param __INTERRUPT__ specifies the SAI interrupt source to check. + * This parameter can be one of the following values: + * @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable + * @arg SAI_IT_MUTEDET: Mute detection interrupt enable + * @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable + * @arg SAI_IT_FREQ: FIFO request interrupt enable + * @arg SAI_IT_CNRDY: Codec not ready interrupt enable + * @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable + * @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable + * @retval The new state of __INTERRUPT__ (TRUE or FALSE). + */ +#define __HAL_SAI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & \ + (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Check whether the specified SAI flag is set or not. + * @param __HANDLE__ specifies the SAI Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg SAI_FLAG_OVRUDR: Overrun underrun flag. + * @arg SAI_FLAG_MUTEDET: Mute detection flag. + * @arg SAI_FLAG_WCKCFG: Wrong Clock Configuration flag. + * @arg SAI_FLAG_FREQ: FIFO request flag. + * @arg SAI_FLAG_CNRDY: Codec not ready flag. + * @arg SAI_FLAG_AFSDET: Anticipated frame synchronization detection flag. + * @arg SAI_FLAG_LFSDET: Late frame synchronization detection flag. + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_SAI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) + +/** @brief Clear the specified SAI pending flag. + * @param __HANDLE__ specifies the SAI Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be any combination of the following values: + * @arg SAI_FLAG_OVRUDR: Clear Overrun underrun + * @arg SAI_FLAG_MUTEDET: Clear Mute detection + * @arg SAI_FLAG_WCKCFG: Clear Wrong Clock Configuration + * @arg SAI_FLAG_FREQ: Clear FIFO request + * @arg SAI_FLAG_CNRDY: Clear Codec not ready + * @arg SAI_FLAG_AFSDET: Clear Anticipated frame synchronization detection + * @arg SAI_FLAG_LFSDET: Clear Late frame synchronization detection + * + * @retval None + */ +#define __HAL_SAI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR = (__FLAG__)) + +/** @brief Enable SAI. + * @param __HANDLE__ specifies the SAI Handle. + * @retval None + */ +#define __HAL_SAI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SAI_xCR1_SAIEN) + +/** @brief Disable SAI. + * @param __HANDLE__ specifies the SAI Handle. + * @retval None + */ +#define __HAL_SAI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SAI_xCR1_SAIEN) + +/** + * @} + */ + +/* Include SAI HAL Extension module */ +#include "stm32wbaxx_hal_sai_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SAI_Exported_Functions + * @{ + */ + +/* Initialization/de-initialization functions ********************************/ +/** @addtogroup SAI_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot); +HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai); +HAL_StatusTypeDef HAL_SAI_DeInit(SAI_HandleTypeDef *hsai); +void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai); +void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai); + +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) +/* SAI callbacks register/unregister functions ********************************/ +HAL_StatusTypeDef HAL_SAI_RegisterCallback(SAI_HandleTypeDef *hsai, + HAL_SAI_CallbackIDTypeDef CallbackID, + pSAI_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SAI_UnRegisterCallback(SAI_HandleTypeDef *hsai, + HAL_SAI_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ +/** + * @} + */ + +/* I/O operation functions ***************************************************/ +/** @addtogroup SAI_Exported_Functions_Group2 + * @{ + */ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size); + +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SAI_DMAPause(SAI_HandleTypeDef *hsai); +HAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai); +HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai); + +/* Abort function */ +HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai); + +/* Mute management */ +HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val); +HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode(SAI_HandleTypeDef *hsai); +HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter); +HAL_StatusTypeDef HAL_SAI_DisableRxMuteMode(SAI_HandleTypeDef *hsai); + +/* SAI IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */ +void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai); +void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai); +void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai); +void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai); +void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai); +void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai); +/** + * @} + */ + +/** @addtogroup SAI_Exported_Functions_Group3 + * @{ + */ +/* Peripheral State functions ************************************************/ +HAL_SAI_StateTypeDef HAL_SAI_GetState(const SAI_HandleTypeDef *hsai); +uint32_t HAL_SAI_GetError(const SAI_HandleTypeDef *hsai); +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup SAI_Private_Macros SAI Private Macros + * @{ + */ +#define IS_SAI_BLOCK_SYNCEXT(STATE) (((STATE) == SAI_SYNCEXT_DISABLE) ||\ + ((STATE) == SAI_SYNCEXT_OUTBLOCKA_ENABLE) ||\ + ((STATE) == SAI_SYNCEXT_OUTBLOCKB_ENABLE)) + +#define IS_SAI_SUPPORTED_PROTOCOL(PROTOCOL) (((PROTOCOL) == SAI_I2S_STANDARD) ||\ + ((PROTOCOL) == SAI_I2S_MSBJUSTIFIED) ||\ + ((PROTOCOL) == SAI_I2S_LSBJUSTIFIED) ||\ + ((PROTOCOL) == SAI_PCM_LONG) ||\ + ((PROTOCOL) == SAI_PCM_SHORT)) + +#define IS_SAI_PROTOCOL_DATASIZE(DATASIZE) (((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BIT) ||\ + ((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BITEXTENDED) ||\ + ((DATASIZE) == SAI_PROTOCOL_DATASIZE_24BIT) ||\ + ((DATASIZE) == SAI_PROTOCOL_DATASIZE_32BIT)) + +#define IS_SAI_AUDIO_FREQUENCY(AUDIO) (((AUDIO) == SAI_AUDIO_FREQUENCY_192K) || \ + ((AUDIO) == SAI_AUDIO_FREQUENCY_96K) || \ + ((AUDIO) == SAI_AUDIO_FREQUENCY_48K) || \ + ((AUDIO) == SAI_AUDIO_FREQUENCY_44K) || \ + ((AUDIO) == SAI_AUDIO_FREQUENCY_32K) || \ + ((AUDIO) == SAI_AUDIO_FREQUENCY_24K) || \ + ((AUDIO) == SAI_AUDIO_FREQUENCY_22K) || \ + ((AUDIO) == SAI_AUDIO_FREQUENCY_16K) || \ + ((AUDIO) == SAI_AUDIO_FREQUENCY_11K) || \ + ((AUDIO) == SAI_AUDIO_FREQUENCY_8K) || \ + ((AUDIO) == SAI_AUDIO_FREQUENCY_MCKDIV)) + +#define IS_SAI_BLOCK_MCK_OVERSAMPLING(VALUE) (((VALUE) == SAI_MCK_OVERSAMPLING_DISABLE) || \ + ((VALUE) == SAI_MCK_OVERSAMPLING_ENABLE)) + +#define IS_SAI_PDM_MIC_PAIRS_NUMBER(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 2U)) + +#define IS_SAI_PDM_CLOCK_ENABLE(CLOCK) (((CLOCK) != 0U) && \ + (((CLOCK) & ~(SAI_PDM_CLOCK1_ENABLE | SAI_PDM_CLOCK2_ENABLE)) == 0U)) + +#define IS_SAI_BLOCK_MODE(MODE) (((MODE) == SAI_MODEMASTER_TX) || \ + ((MODE) == SAI_MODEMASTER_RX) || \ + ((MODE) == SAI_MODESLAVE_TX) || \ + ((MODE) == SAI_MODESLAVE_RX)) + +#define IS_SAI_BLOCK_PROTOCOL(PROTOCOL) (((PROTOCOL) == SAI_FREE_PROTOCOL) || \ + ((PROTOCOL) == SAI_AC97_PROTOCOL) || \ + ((PROTOCOL) == SAI_SPDIF_PROTOCOL)) + +#define IS_SAI_BLOCK_DATASIZE(DATASIZE) (((DATASIZE) == SAI_DATASIZE_8) || \ + ((DATASIZE) == SAI_DATASIZE_10) || \ + ((DATASIZE) == SAI_DATASIZE_16) || \ + ((DATASIZE) == SAI_DATASIZE_20) || \ + ((DATASIZE) == SAI_DATASIZE_24) || \ + ((DATASIZE) == SAI_DATASIZE_32)) + +#define IS_SAI_BLOCK_FIRST_BIT(BIT) (((BIT) == SAI_FIRSTBIT_MSB) || \ + ((BIT) == SAI_FIRSTBIT_LSB)) + +#define IS_SAI_BLOCK_CLOCK_STROBING(CLOCK) (((CLOCK) == SAI_CLOCKSTROBING_FALLINGEDGE) || \ + ((CLOCK) == SAI_CLOCKSTROBING_RISINGEDGE)) + +#define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_ASYNCHRONOUS) || \ + ((SYNCHRO) == SAI_SYNCHRONOUS) || \ + ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI1) || \ + ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI2)) + +#define IS_SAI_BLOCK_MCK_OUTPUT(VALUE) (((VALUE) == SAI_MCK_OUTPUT_ENABLE) || \ + ((VALUE) == SAI_MCK_OUTPUT_DISABLE)) + +#define IS_SAI_BLOCK_OUTPUT_DRIVE(DRIVE) (((DRIVE) == SAI_OUTPUTDRIVE_DISABLE) || \ + ((DRIVE) == SAI_OUTPUTDRIVE_ENABLE)) + +#define IS_SAI_BLOCK_NODIVIDER(NODIVIDER) (((NODIVIDER) == SAI_MASTERDIVIDER_ENABLE) || \ + ((NODIVIDER) == SAI_MASTERDIVIDER_DISABLE)) + +#define IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63U) + +#define IS_SAI_BLOCK_MUTE_VALUE(VALUE) (((VALUE) == SAI_ZERO_VALUE) || \ + ((VALUE) == SAI_LAST_SENT_VALUE)) + +#define IS_SAI_BLOCK_COMPANDING_MODE(MODE) (((MODE) == SAI_NOCOMPANDING) || \ + ((MODE) == SAI_ULAW_1CPL_COMPANDING) || \ + ((MODE) == SAI_ALAW_1CPL_COMPANDING) || \ + ((MODE) == SAI_ULAW_2CPL_COMPANDING) || \ + ((MODE) == SAI_ALAW_2CPL_COMPANDING)) + +#define IS_SAI_BLOCK_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SAI_FIFOTHRESHOLD_EMPTY) || \ + ((THRESHOLD) == SAI_FIFOTHRESHOLD_1QF) || \ + ((THRESHOLD) == SAI_FIFOTHRESHOLD_HF) || \ + ((THRESHOLD) == SAI_FIFOTHRESHOLD_3QF) || \ + ((THRESHOLD) == SAI_FIFOTHRESHOLD_FULL)) + +#define IS_SAI_BLOCK_TRISTATE_MANAGEMENT(STATE) (((STATE) == SAI_OUTPUT_NOTRELEASED) ||\ + ((STATE) == SAI_OUTPUT_RELEASED)) + +#define IS_SAI_MONO_STEREO_MODE(MODE) (((MODE) == SAI_MONOMODE) ||\ + ((MODE) == SAI_STEREOMODE)) + +#define IS_SAI_SLOT_ACTIVE(ACTIVE) ((ACTIVE) <= SAI_SLOTACTIVE_ALL) + +#define IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1U <= (NUMBER)) && ((NUMBER) <= 16U)) + +#define IS_SAI_BLOCK_SLOT_SIZE(SIZE) (((SIZE) == SAI_SLOTSIZE_DATASIZE) || \ + ((SIZE) == SAI_SLOTSIZE_16B) || \ + ((SIZE) == SAI_SLOTSIZE_32B)) + +#define IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET) ((OFFSET) <= 24U) + +#define IS_SAI_BLOCK_FS_OFFSET(OFFSET) (((OFFSET) == SAI_FS_FIRSTBIT) || \ + ((OFFSET) == SAI_FS_BEFOREFIRSTBIT)) + +#define IS_SAI_BLOCK_FS_POLARITY(POLARITY) (((POLARITY) == SAI_FS_ACTIVE_LOW) || \ + ((POLARITY) == SAI_FS_ACTIVE_HIGH)) + +#define IS_SAI_BLOCK_FS_DEFINITION(DEFINITION) (((DEFINITION) == SAI_FS_STARTFRAME) || \ + ((DEFINITION) == SAI_FS_CHANNEL_IDENTIFICATION)) + +#define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 63U) + +#define IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8U <= (LENGTH)) && ((LENGTH) <= 256U)) + +#define IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1U <= (LENGTH)) && ((LENGTH) <= 128U)) + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup SAI_Private_Functions SAI Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* SAI1 */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WBAxx_HAL_SAI_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_sai_ex.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_sai_ex.h new file mode 100644 index 0000000000..0e870a31c1 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_sai_ex.h @@ -0,0 +1,103 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_sai_ex.h + * @author MCD Application Team + * @brief Header file of SAI HAL extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_HAL_SAI_EX_H +#define STM32WBAxx_HAL_SAI_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal_def.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ +#if defined (SAI1) +/** @addtogroup SAIEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup SAIEx_Exported_Types SAIEx Exported Types + * @{ + */ + +/** + * @brief PDM microphone delay structure definition + */ +typedef struct +{ + uint32_t MicPair; /*!< Specifies which pair of microphones is selected. + This parameter must be a number between Min_Data = 1 and Max_Data = 2. */ + + uint32_t LeftDelay; /*!< Specifies the delay in PDM clock unit to apply on left microphone. + This parameter must be a number between Min_Data = 0 and Max_Data = 7. */ + + uint32_t RightDelay; /*!< Specifies the delay in PDM clock unit to apply on right microphone. + This parameter must be a number between Min_Data = 0 and Max_Data = 7. */ +} SAIEx_PdmMicDelayParamTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/* Exported macros -----------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SAIEx_Exported_Functions SAIEx Extended Exported Functions + * @{ + */ + +/** @addtogroup SAIEx_Exported_Functions_Group1 Peripheral Control functions + * @{ + */ +HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay(const SAI_HandleTypeDef *hsai, + const SAIEx_PdmMicDelayParamTypeDef *pdmMicDelay); +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup SAIEx_Private_Macros SAIEx Extended Private Macros + * @{ + */ +#define IS_SAI_PDM_MIC_DELAY(VALUE) ((VALUE) <= 7U) +/** + * @} + */ + +/** + * @} + */ +#endif /* SAI1 */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WBAxx_HAL_SAI_EX_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_smartcard.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_smartcard.h new file mode 100644 index 0000000000..b175ba0a22 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_smartcard.h @@ -0,0 +1,1227 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_smartcard.h + * @author MCD Application Team + * @brief Header file of SMARTCARD HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_HAL_SMARTCARD_H +#define STM32WBAxx_HAL_SMARTCARD_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal_def.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @addtogroup SMARTCARD + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup SMARTCARD_Exported_Types SMARTCARD Exported Types + * @{ + */ + +/** + * @brief SMARTCARD Init Structure definition + */ +typedef struct +{ + uint32_t BaudRate; /*!< Configures the SmartCard communication baud rate. + The baud rate register is computed using the following formula: + Baud Rate Register = ((usart_ker_ckpres) / ((hsmartcard->Init.BaudRate))) + where usart_ker_ckpres is the USART input clock divided by a prescaler */ + + uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter @ref SMARTCARD_Word_Length can only be + set to 9 (8 data + 1 parity bits). */ + + uint32_t StopBits; /*!< Specifies the number of stop bits. + This parameter can be a value of @ref SMARTCARD_Stop_Bits. */ + + uint16_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref SMARTCARD_Parity + @note The parity is enabled by default (PCE is forced to 1). + Since the WordLength is forced to 8 bits + parity, M is + forced to 1 and the parity bit is the 9th bit. */ + + uint16_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref SMARTCARD_Mode */ + + uint16_t CLKPolarity; /*!< Specifies the steady state of the serial clock. + This parameter can be a value of @ref SMARTCARD_Clock_Polarity */ + + uint16_t CLKPhase; /*!< Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref SMARTCARD_Clock_Phase */ + + uint16_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted + data bit (MSB) has to be output on the SCLK pin in synchronous mode. + This parameter can be a value of @ref SMARTCARD_Last_Bit */ + + uint16_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote + is selected. Selecting the single sample method increases + the receiver tolerance to clock deviations. This parameter can be a value + of @ref SMARTCARD_OneBit_Sampling. */ + + uint8_t Prescaler; /*!< Specifies the SmartCard Prescaler. + This parameter can be any value from 0x01 to 0x1F. Prescaler value is + multiplied by 2 to give the division factor of the source clock frequency */ + + uint8_t GuardTime; /*!< Specifies the SmartCard Guard Time applied after stop bits. */ + + uint16_t NACKEnable; /*!< Specifies whether the SmartCard NACK transmission is enabled + in case of parity error. + This parameter can be a value of @ref SMARTCARD_NACK_Enable */ + + uint32_t TimeOutEnable; /*!< Specifies whether the receiver timeout is enabled. + This parameter can be a value of @ref SMARTCARD_Timeout_Enable*/ + + uint32_t TimeOutValue; /*!< Specifies the receiver time out value in number of baud blocks: + it is used to implement the Character Wait Time (CWT) and + Block Wait Time (BWT). It is coded over 24 bits. */ + + uint8_t BlockLength; /*!< Specifies the SmartCard Block Length in T=1 Reception mode. + This parameter can be any value from 0x0 to 0xFF */ + + uint8_t AutoRetryCount; /*!< Specifies the SmartCard auto-retry count (number of retries in + receive and transmit mode). When set to 0, retransmission is + disabled. Otherwise, its maximum value is 7 (before signalling + an error) */ + + uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the USART clock source. + This parameter can be a value of @ref SMARTCARD_ClockPrescaler. */ + +} SMARTCARD_InitTypeDef; + +/** + * @brief SMARTCARD advanced features initialization structure definition + */ +typedef struct +{ + uint32_t AdvFeatureInit; /*!< Specifies which advanced SMARTCARD features is initialized. Several + advanced features may be initialized at the same time. This parameter + can be a value of @ref SMARTCARDEx_Advanced_Features_Initialization_Type */ + + uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted. + This parameter can be a value of @ref SMARTCARD_Tx_Inv */ + + uint32_t RxPinLevelInvert; /*!< Specifies whether the RX pin active level is inverted. + This parameter can be a value of @ref SMARTCARD_Rx_Inv */ + + uint32_t DataInvert; /*!< Specifies whether data are inverted (positive/direct logic + vs negative/inverted logic). + This parameter can be a value of @ref SMARTCARD_Data_Inv */ + + uint32_t Swap; /*!< Specifies whether TX and RX pins are swapped. + This parameter can be a value of @ref SMARTCARD_Rx_Tx_Swap */ + + uint32_t OverrunDisable; /*!< Specifies whether the reception overrun detection is disabled. + This parameter can be a value of @ref SMARTCARD_Overrun_Disable */ + + uint32_t DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of reception error. + This parameter can be a value of @ref SMARTCARD_DMA_Disable_on_Rx_Error */ + + uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line. + This parameter can be a value of @ref SMARTCARD_MSB_First */ + + uint16_t TxCompletionIndication; /*!< Specifies which transmission completion indication is used: before (when + relevant flag is available) or once guard time period has elapsed. + This parameter can be a value + of @ref SMARTCARDEx_Transmission_Completion_Indication. */ +} SMARTCARD_AdvFeatureInitTypeDef; + +/** + * @brief HAL SMARTCARD State definition + * @note HAL SMARTCARD State value is a combination of 2 different substates: + * gState and RxState (see @ref SMARTCARD_State_Definition). + * - gState contains SMARTCARD state information related to global Handle management + * and also information related to Tx operations. + * gState value coding follow below described bitmap : + * b7-b6 Error information + * 00 : No Error + * 01 : (Not Used) + * 10 : Timeout + * 11 : Error + * b5 Peripheral initialization status + * 0 : Reset (Peripheral not initialized) + * 1 : Init done (Peripheral initialized. HAL SMARTCARD Init function already called) + * b4-b3 (not used) + * xx : Should be set to 00 + * b2 Intrinsic process state + * 0 : Ready + * 1 : Busy (Peripheral busy with some configuration or internal operations) + * b1 (not used) + * x : Should be set to 0 + * b0 Tx state + * 0 : Ready (no Tx operation ongoing) + * 1 : Busy (Tx operation ongoing) + * - RxState contains information related to Rx operations. + * RxState value coding follow below described bitmap : + * b7-b6 (not used) + * xx : Should be set to 00 + * b5 Peripheral initialization status + * 0 : Reset (Peripheral not initialized) + * 1 : Init done (Peripheral initialized) + * b4-b2 (not used) + * xxx : Should be set to 000 + * b1 Rx state + * 0 : Ready (no Rx operation ongoing) + * 1 : Busy (Rx operation ongoing) + * b0 (not used) + * x : Should be set to 0. + */ +typedef uint32_t HAL_SMARTCARD_StateTypeDef; + +/** + * @brief SMARTCARD handle Structure definition + */ +typedef struct __SMARTCARD_HandleTypeDef +{ + USART_TypeDef *Instance; /*!< USART registers base address */ + + SMARTCARD_InitTypeDef Init; /*!< SmartCard communication parameters */ + + SMARTCARD_AdvFeatureInitTypeDef AdvancedInit; /*!< SmartCard advanced features initialization parameters */ + + const uint8_t *pTxBuffPtr; /*!< Pointer to SmartCard Tx transfer Buffer */ + + uint16_t TxXferSize; /*!< SmartCard Tx Transfer size */ + + __IO uint16_t TxXferCount; /*!< SmartCard Tx Transfer Counter */ + + uint8_t *pRxBuffPtr; /*!< Pointer to SmartCard Rx transfer Buffer */ + + uint16_t RxXferSize; /*!< SmartCard Rx Transfer size */ + + __IO uint16_t RxXferCount; /*!< SmartCard Rx Transfer Counter */ + + uint16_t NbRxDataToProcess; /*!< Number of data to process during RX ISR execution */ + + uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */ + + uint32_t FifoMode; /*!< Specifies if the FIFO mode will be used. + This parameter can be a value of + @ref SMARTCARDEx_FIFO_mode. */ + + void (*RxISR)(struct __SMARTCARD_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */ + + void (*TxISR)(struct __SMARTCARD_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */ + +#if defined(HAL_DMA_MODULE_ENABLED) + DMA_HandleTypeDef *hdmatx; /*!< SmartCard Tx DMA Handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< SmartCard Rx DMA Handle parameters */ + +#endif /* HAL_DMA_MODULE_ENABLED */ + HAL_LockTypeDef Lock; /*!< Locking object */ + + __IO HAL_SMARTCARD_StateTypeDef gState; /*!< SmartCard state information related to global + Handle management and also related to Tx operations. + This parameter can be a value + of @ref HAL_SMARTCARD_StateTypeDef */ + + __IO HAL_SMARTCARD_StateTypeDef RxState; /*!< SmartCard state information related to Rx operations. + This parameter can be a value + of @ref HAL_SMARTCARD_StateTypeDef */ + + __IO uint32_t ErrorCode; /*!< SmartCard Error code */ + +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + void (* TxCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Tx Complete Callback */ + + void (* RxCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Rx Complete Callback */ + + void (* ErrorCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Error Callback */ + + void (* AbortCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Abort Complete Callback */ + + void (* AbortTransmitCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Abort Transmit Complete Callback */ + + void (* AbortReceiveCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Abort Receive Complete Callback */ + + void (* RxFifoFullCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Rx Fifo Full Callback */ + + void (* TxFifoEmptyCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Tx Fifo Empty Callback */ + + void (* MspInitCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Msp Init callback */ + + void (* MspDeInitCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Msp DeInit callback */ +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ + +} SMARTCARD_HandleTypeDef; + +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) +/** + * @brief HAL SMARTCARD Callback ID enumeration definition + */ +typedef enum +{ + HAL_SMARTCARD_TX_COMPLETE_CB_ID = 0x00U, /*!< SMARTCARD Tx Complete Callback ID */ + HAL_SMARTCARD_RX_COMPLETE_CB_ID = 0x01U, /*!< SMARTCARD Rx Complete Callback ID */ + HAL_SMARTCARD_ERROR_CB_ID = 0x02U, /*!< SMARTCARD Error Callback ID */ + HAL_SMARTCARD_ABORT_COMPLETE_CB_ID = 0x03U, /*!< SMARTCARD Abort Complete Callback ID */ + HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x04U, /*!< SMARTCARD Abort Transmit Complete Callback ID */ + HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID = 0x05U, /*!< SMARTCARD Abort Receive Complete Callback ID */ + HAL_SMARTCARD_RX_FIFO_FULL_CB_ID = 0x06U, /*!< SMARTCARD Rx Fifo Full Callback ID */ + HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID = 0x07U, /*!< SMARTCARD Tx Fifo Empty Callback ID */ + + HAL_SMARTCARD_MSPINIT_CB_ID = 0x08U, /*!< SMARTCARD MspInit callback ID */ + HAL_SMARTCARD_MSPDEINIT_CB_ID = 0x09U /*!< SMARTCARD MspDeInit callback ID */ + +} HAL_SMARTCARD_CallbackIDTypeDef; + +/** + * @brief HAL SMARTCARD Callback pointer definition + */ +typedef void (*pSMARTCARD_CallbackTypeDef)(SMARTCARD_HandleTypeDef *hsmartcard); /*!< pointer to an SMARTCARD callback function */ + +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ + +/** + * @brief SMARTCARD clock sources + */ +typedef enum +{ + SMARTCARD_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */ + SMARTCARD_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */ + SMARTCARD_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */ + SMARTCARD_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */ + SMARTCARD_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */ + SMARTCARD_CLOCKSOURCE_UNDEFINED = 0x10U /*!< undefined clock source */ +} SMARTCARD_ClockSourceTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SMARTCARD_Exported_Constants SMARTCARD Exported Constants + * @{ + */ + +/** @defgroup SMARTCARD_State_Definition SMARTCARD State Code Definition + * @{ + */ +#define HAL_SMARTCARD_STATE_RESET 0x00000000U /*!< Peripheral is not initialized. Value + is allowed for gState and RxState */ +#define HAL_SMARTCARD_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for + use. Value is allowed for gState + and RxState */ +#define HAL_SMARTCARD_STATE_BUSY 0x00000024U /*!< an internal process is ongoing + Value is allowed for gState only */ +#define HAL_SMARTCARD_STATE_BUSY_TX 0x00000021U /*!< Data Transmission process is ongoing + Value is allowed for gState only */ +#define HAL_SMARTCARD_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing + Value is allowed for RxState only */ +#define HAL_SMARTCARD_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception + process is ongoing Not to be used for + neither gState nor RxState. + Value is result of combination (Or) + between gState and RxState values */ +#define HAL_SMARTCARD_STATE_TIMEOUT 0x000000A0U /*!< Timeout state + Value is allowed for gState only */ +#define HAL_SMARTCARD_STATE_ERROR 0x000000E0U /*!< Error + Value is allowed for gState only */ +/** + * @} + */ + +/** @defgroup SMARTCARD_Error_Definition SMARTCARD Error Code Definition + * @{ + */ +#define HAL_SMARTCARD_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_SMARTCARD_ERROR_PE (0x00000001U) /*!< Parity error */ +#define HAL_SMARTCARD_ERROR_NE (0x00000002U) /*!< Noise error */ +#define HAL_SMARTCARD_ERROR_FE (0x00000004U) /*!< frame error */ +#define HAL_SMARTCARD_ERROR_ORE (0x00000008U) /*!< Overrun error */ +#if defined(HAL_DMA_MODULE_ENABLED) +#define HAL_SMARTCARD_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#endif /* HAL_DMA_MODULE_ENABLED */ +#define HAL_SMARTCARD_ERROR_RTO (0x00000020U) /*!< Receiver TimeOut error */ +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) +#define HAL_SMARTCARD_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */ +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length + * @{ + */ +#define SMARTCARD_WORDLENGTH_9B USART_CR1_M0 /*!< SMARTCARD frame length */ +/** + * @} + */ + +/** @defgroup SMARTCARD_Stop_Bits SMARTCARD Number of Stop Bits + * @{ + */ +#define SMARTCARD_STOPBITS_0_5 USART_CR2_STOP_0 /*!< SMARTCARD frame with 0.5 stop bit */ +#define SMARTCARD_STOPBITS_1_5 USART_CR2_STOP /*!< SMARTCARD frame with 1.5 stop bits */ +/** + * @} + */ + +/** @defgroup SMARTCARD_Parity SMARTCARD Parity + * @{ + */ +#define SMARTCARD_PARITY_EVEN USART_CR1_PCE /*!< SMARTCARD frame even parity */ +#define SMARTCARD_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< SMARTCARD frame odd parity */ +/** + * @} + */ + +/** @defgroup SMARTCARD_Mode SMARTCARD Transfer Mode + * @{ + */ +#define SMARTCARD_MODE_RX USART_CR1_RE /*!< SMARTCARD RX mode */ +#define SMARTCARD_MODE_TX USART_CR1_TE /*!< SMARTCARD TX mode */ +#define SMARTCARD_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< SMARTCARD RX and TX mode */ +/** + * @} + */ + +/** @defgroup SMARTCARD_Clock_Polarity SMARTCARD Clock Polarity + * @{ + */ +#define SMARTCARD_POLARITY_LOW 0x00000000U /*!< SMARTCARD frame low polarity */ +#define SMARTCARD_POLARITY_HIGH USART_CR2_CPOL /*!< SMARTCARD frame high polarity */ +/** + * @} + */ + +/** @defgroup SMARTCARD_Clock_Phase SMARTCARD Clock Phase + * @{ + */ +#define SMARTCARD_PHASE_1EDGE 0x00000000U /*!< SMARTCARD frame phase on first clock transition */ +#define SMARTCARD_PHASE_2EDGE USART_CR2_CPHA /*!< SMARTCARD frame phase on second clock transition */ +/** + * @} + */ + +/** @defgroup SMARTCARD_Last_Bit SMARTCARD Last Bit + * @{ + */ +#define SMARTCARD_LASTBIT_DISABLE 0x00000000U /*!< SMARTCARD frame last data bit clock pulse not output to SCLK pin */ +#define SMARTCARD_LASTBIT_ENABLE USART_CR2_LBCL /*!< SMARTCARD frame last data bit clock pulse output to SCLK pin */ +/** + * @} + */ + +/** @defgroup SMARTCARD_OneBit_Sampling SMARTCARD One Bit Sampling Method + * @{ + */ +#define SMARTCARD_ONE_BIT_SAMPLE_DISABLE 0x00000000U /*!< SMARTCARD frame one-bit sample disabled */ +#define SMARTCARD_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT /*!< SMARTCARD frame one-bit sample enabled */ +/** + * @} + */ + +/** @defgroup SMARTCARD_NACK_Enable SMARTCARD NACK Enable + * @{ + */ +#define SMARTCARD_NACK_DISABLE 0x00000000U /*!< SMARTCARD NACK transmission disabled */ +#define SMARTCARD_NACK_ENABLE USART_CR3_NACK /*!< SMARTCARD NACK transmission enabled */ +/** + * @} + */ + +/** @defgroup SMARTCARD_Timeout_Enable SMARTCARD Timeout Enable + * @{ + */ +#define SMARTCARD_TIMEOUT_DISABLE 0x00000000U /*!< SMARTCARD receiver timeout disabled */ +#define SMARTCARD_TIMEOUT_ENABLE USART_CR2_RTOEN /*!< SMARTCARD receiver timeout enabled */ +/** + * @} + */ + +/** @defgroup SMARTCARD_ClockPrescaler SMARTCARD Clock Prescaler + * @{ + */ +#define SMARTCARD_PRESCALER_DIV1 0x00000000U /*!< fclk_pres = fclk */ +#define SMARTCARD_PRESCALER_DIV2 0x00000001U /*!< fclk_pres = fclk/2 */ +#define SMARTCARD_PRESCALER_DIV4 0x00000002U /*!< fclk_pres = fclk/4 */ +#define SMARTCARD_PRESCALER_DIV6 0x00000003U /*!< fclk_pres = fclk/6 */ +#define SMARTCARD_PRESCALER_DIV8 0x00000004U /*!< fclk_pres = fclk/8 */ +#define SMARTCARD_PRESCALER_DIV10 0x00000005U /*!< fclk_pres = fclk/10 */ +#define SMARTCARD_PRESCALER_DIV12 0x00000006U /*!< fclk_pres = fclk/12 */ +#define SMARTCARD_PRESCALER_DIV16 0x00000007U /*!< fclk_pres = fclk/16 */ +#define SMARTCARD_PRESCALER_DIV32 0x00000008U /*!< fclk_pres = fclk/32 */ +#define SMARTCARD_PRESCALER_DIV64 0x00000009U /*!< fclk_pres = fclk/64 */ +#define SMARTCARD_PRESCALER_DIV128 0x0000000AU /*!< fclk_pres = fclk/128 */ +#define SMARTCARD_PRESCALER_DIV256 0x0000000BU /*!< fclk_pres = fclk/256 */ +/** + * @} + */ + +/** @defgroup SMARTCARD_Tx_Inv SMARTCARD advanced feature TX pin active level inversion + * @{ + */ +#define SMARTCARD_ADVFEATURE_TXINV_DISABLE 0x00000000U /*!< TX pin active level inversion disable */ +#define SMARTCARD_ADVFEATURE_TXINV_ENABLE USART_CR2_TXINV /*!< TX pin active level inversion enable */ +/** + * @} + */ + +/** @defgroup SMARTCARD_Rx_Inv SMARTCARD advanced feature RX pin active level inversion + * @{ + */ +#define SMARTCARD_ADVFEATURE_RXINV_DISABLE 0x00000000U /*!< RX pin active level inversion disable */ +#define SMARTCARD_ADVFEATURE_RXINV_ENABLE USART_CR2_RXINV /*!< RX pin active level inversion enable */ +/** + * @} + */ + +/** @defgroup SMARTCARD_Data_Inv SMARTCARD advanced feature Binary Data inversion + * @{ + */ +#define SMARTCARD_ADVFEATURE_DATAINV_DISABLE 0x00000000U /*!< Binary data inversion disable */ +#define SMARTCARD_ADVFEATURE_DATAINV_ENABLE USART_CR2_DATAINV /*!< Binary data inversion enable */ +/** + * @} + */ + +/** @defgroup SMARTCARD_Rx_Tx_Swap SMARTCARD advanced feature RX TX pins swap + * @{ + */ +#define SMARTCARD_ADVFEATURE_SWAP_DISABLE 0x00000000U /*!< TX/RX pins swap disable */ +#define SMARTCARD_ADVFEATURE_SWAP_ENABLE USART_CR2_SWAP /*!< TX/RX pins swap enable */ +/** + * @} + */ + +/** @defgroup SMARTCARD_Overrun_Disable SMARTCARD advanced feature Overrun Disable + * @{ + */ +#define SMARTCARD_ADVFEATURE_OVERRUN_ENABLE 0x00000000U /*!< RX overrun enable */ +#define SMARTCARD_ADVFEATURE_OVERRUN_DISABLE USART_CR3_OVRDIS /*!< RX overrun disable */ +/** + * @} + */ + +/** @defgroup SMARTCARD_DMA_Disable_on_Rx_Error SMARTCARD advanced feature DMA Disable on Rx Error + * @{ + */ +#define SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR 0x00000000U /*!< DMA enable on Reception Error */ +#define SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR USART_CR3_DDRE /*!< DMA disable on Reception Error */ +/** + * @} + */ + +/** @defgroup SMARTCARD_MSB_First SMARTCARD advanced feature MSB first + * @{ + */ +#define SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U /*!< Most significant bit sent/received first disable */ +#define SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST /*!< Most significant bit sent/received first enable */ +/** + * @} + */ + +/** @defgroup SMARTCARD_Request_Parameters SMARTCARD Request Parameters + * @{ + */ +#define SMARTCARD_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ /*!< Receive data flush request */ +#define SMARTCARD_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ /*!< Transmit data flush request */ +/** + * @} + */ + +/** @defgroup SMARTCARD_Interruption_Mask SMARTCARD interruptions flags mask + * @{ + */ +#define SMARTCARD_IT_MASK 0x001FU /*!< SMARTCARD interruptions flags mask */ +#define SMARTCARD_CR_MASK 0x00E0U /*!< SMARTCARD control register mask */ +#define SMARTCARD_CR_POS 5U /*!< SMARTCARD control register position */ +#define SMARTCARD_ISR_MASK 0x1F00U /*!< SMARTCARD ISR register mask */ +#define SMARTCARD_ISR_POS 8U /*!< SMARTCARD ISR register position */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup SMARTCARD_Exported_Macros SMARTCARD Exported Macros + * @{ + */ + +/** @brief Reset SMARTCARD handle states. + * @param __HANDLE__ SMARTCARD handle. + * @retval None + */ +#if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1 +#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0U) +#else +#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \ + } while(0U) +#endif /*USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ + +/** @brief Flush the Smartcard Data registers. + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @retval None + */ +#define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) \ + do{ \ + SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); \ + SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_TXDATA_FLUSH_REQUEST); \ + } while(0U) + +/** @brief Clear the specified SMARTCARD pending flag. + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be any combination of the following values: + * @arg @ref SMARTCARD_CLEAR_PEF Parity error clear flag + * @arg @ref SMARTCARD_CLEAR_FEF Framing error clear flag + * @arg @ref SMARTCARD_CLEAR_NEF Noise detected clear flag + * @arg @ref SMARTCARD_CLEAR_OREF OverRun error clear flag + * @arg @ref SMARTCARD_CLEAR_IDLEF Idle line detected clear flag + * @arg @ref SMARTCARD_CLEAR_TCF Transmission complete clear flag + * @arg @ref SMARTCARD_CLEAR_TCBGTF Transmission complete before guard time clear flag + * @arg @ref SMARTCARD_CLEAR_RTOF Receiver timeout clear flag + * @arg @ref SMARTCARD_CLEAR_EOBF End of block clear flag + * @arg @ref SMARTCARD_CLEAR_TXFECF TXFIFO empty Clear flag + * @retval None + */ +#define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) + +/** @brief Clear the SMARTCARD PE pending flag. + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @retval None + */ +#define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_PEF) + +/** @brief Clear the SMARTCARD FE pending flag. + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @retval None + */ +#define __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_FEF) + +/** @brief Clear the SMARTCARD NE pending flag. + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @retval None + */ +#define __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_NEF) + +/** @brief Clear the SMARTCARD ORE pending flag. + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @retval None + */ +#define __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_OREF) + +/** @brief Clear the SMARTCARD IDLE pending flag. + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @retval None + */ +#define __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_IDLEF) + +/** @brief Check whether the specified Smartcard flag is set or not. + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref SMARTCARD_FLAG_TCBGT Transmission complete before guard time flag (when flag available) + * @arg @ref SMARTCARD_FLAG_REACK Receive enable acknowledge flag + * @arg @ref SMARTCARD_FLAG_TEACK Transmit enable acknowledge flag + * @arg @ref SMARTCARD_FLAG_BUSY Busy flag + * @arg @ref SMARTCARD_FLAG_EOBF End of block flag + * @arg @ref SMARTCARD_FLAG_RTOF Receiver timeout flag + * @arg @ref SMARTCARD_FLAG_TXE Transmit data register empty flag + * @arg @ref SMARTCARD_FLAG_TC Transmission complete flag + * @arg @ref SMARTCARD_FLAG_RXNE Receive data register not empty flag + * @arg @ref SMARTCARD_FLAG_IDLE Idle line detection flag + * @arg @ref SMARTCARD_FLAG_ORE Overrun error flag + * @arg @ref SMARTCARD_FLAG_NE Noise error flag + * @arg @ref SMARTCARD_FLAG_FE Framing error flag + * @arg @ref SMARTCARD_FLAG_PE Parity error flag + * @arg @ref SMARTCARD_FLAG_TXFNF TXFIFO not full flag + * @arg @ref SMARTCARD_FLAG_RXFNE RXFIFO not empty flag + * @arg @ref SMARTCARD_FLAG_TXFE TXFIFO Empty flag + * @arg @ref SMARTCARD_FLAG_RXFF RXFIFO Full flag + * @arg @ref SMARTCARD_FLAG_RXFT SMARTCARD RXFIFO threshold flag + * @arg @ref SMARTCARD_FLAG_TXFT SMARTCARD TXFIFO threshold flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) + +/** @brief Enable the specified SmartCard interrupt. + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @param __INTERRUPT__ specifies the SMARTCARD interrupt to enable. + * This parameter can be one of the following values: + * @arg @ref SMARTCARD_IT_EOB End of block interrupt + * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt + * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt + * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt + * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before + * guard time interrupt (when interruption available) + * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt + * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt + * @arg @ref SMARTCARD_IT_PE Parity error interrupt + * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error) + * @arg @ref SMARTCARD_IT_TXFNF TX FIFO not full interruption + * @arg @ref SMARTCARD_IT_RXFNE RXFIFO not empty interruption + * @arg @ref SMARTCARD_IT_RXFF RXFIFO full interruption + * @arg @ref SMARTCARD_IT_TXFE TXFIFO empty interruption + * @arg @ref SMARTCARD_IT_RXFT RXFIFO threshold reached interruption + * @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption + * @retval None + */ +#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ + SMARTCARD_CR_POS) == 1U)?\ + ((__HANDLE__)->Instance->CR1 |= (1UL <<\ + ((__INTERRUPT__) & SMARTCARD_IT_MASK))):\ + ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ + SMARTCARD_CR_POS) == 2U)?\ + ((__HANDLE__)->Instance->CR2 |= (1UL <<\ + ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 |= (1UL <<\ + ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) + +/** @brief Disable the specified SmartCard interrupt. + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @param __INTERRUPT__ specifies the SMARTCARD interrupt to disable. + * This parameter can be one of the following values: + * @arg @ref SMARTCARD_IT_EOB End of block interrupt + * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt + * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt + * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt + * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard + * time interrupt (when interruption available) + * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt + * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt + * @arg @ref SMARTCARD_IT_PE Parity error interrupt + * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error) + * @arg @ref SMARTCARD_IT_TXFNF TX FIFO not full interruption + * @arg @ref SMARTCARD_IT_RXFNE RXFIFO not empty interruption + * @arg @ref SMARTCARD_IT_RXFF RXFIFO full interruption + * @arg @ref SMARTCARD_IT_TXFE TXFIFO empty interruption + * @arg @ref SMARTCARD_IT_RXFT RXFIFO threshold reached interruption + * @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption + * @retval None + */ +#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ + SMARTCARD_CR_POS) == 1U)?\ + ((__HANDLE__)->Instance->CR1 &= ~ (1U <<\ + ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ + ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ + SMARTCARD_CR_POS) == 2U)?\ + ((__HANDLE__)->Instance->CR2 &= ~ (1U <<\ + ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 &= ~ (1U <<\ + ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) + +/** @brief Check whether the specified SmartCard interrupt has occurred or not. + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @param __INTERRUPT__ specifies the SMARTCARD interrupt to check. + * This parameter can be one of the following values: + * @arg @ref SMARTCARD_IT_EOB End of block interrupt + * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt + * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt + * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt + * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time + * interrupt (when interruption available) + * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt + * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt + * @arg @ref SMARTCARD_IT_PE Parity error interrupt + * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error) + * @arg @ref SMARTCARD_IT_TXFNF TX FIFO not full interruption + * @arg @ref SMARTCARD_IT_RXFNE RXFIFO not empty interruption + * @arg @ref SMARTCARD_IT_RXFF RXFIFO full interruption + * @arg @ref SMARTCARD_IT_TXFE TXFIFO empty interruption + * @arg @ref SMARTCARD_IT_RXFT RXFIFO threshold reached interruption + * @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__) (\ + (((__HANDLE__)->Instance->ISR & (0x01UL << (((__INTERRUPT__)\ + & SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS)))!= 0U)\ + ? SET : RESET) + +/** @brief Check whether the specified SmartCard interrupt source is enabled or not. + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @param __INTERRUPT__ specifies the SMARTCARD interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref SMARTCARD_IT_EOB End of block interrupt + * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt + * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt + * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt + * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time + * interrupt (when interruption available) + * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt + * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt + * @arg @ref SMARTCARD_IT_PE Parity error interrupt + * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error) + * @arg @ref SMARTCARD_IT_TXFNF TX FIFO not full interruption + * @arg @ref SMARTCARD_IT_RXFNE RXFIFO not empty interruption + * @arg @ref SMARTCARD_IT_RXFF RXFIFO full interruption + * @arg @ref SMARTCARD_IT_TXFE TXFIFO empty interruption + * @arg @ref SMARTCARD_IT_RXFT RXFIFO threshold reached interruption + * @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ + SMARTCARD_CR_POS) == 0x01U)?\ + (__HANDLE__)->Instance->CR1 : \ + (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ + SMARTCARD_CR_POS) == 0x02U)?\ + (__HANDLE__)->Instance->CR2 : \ + (__HANDLE__)->Instance->CR3)) &\ + (0x01UL << (((uint16_t)(__INTERRUPT__))\ + & SMARTCARD_IT_MASK))) != 0U)\ + ? SET : RESET) + +/** @brief Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag. + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set + * to clear the corresponding interrupt. + * This parameter can be one of the following values: + * @arg @ref SMARTCARD_CLEAR_PEF Parity error clear flag + * @arg @ref SMARTCARD_CLEAR_FEF Framing error clear flag + * @arg @ref SMARTCARD_CLEAR_NEF Noise detected clear flag + * @arg @ref SMARTCARD_CLEAR_OREF OverRun error clear flag + * @arg @ref SMARTCARD_CLEAR_IDLEF Idle line detection clear flag + * @arg @ref SMARTCARD_CLEAR_TXFECF TXFIFO empty Clear Flag + * @arg @ref SMARTCARD_CLEAR_TCF Transmission complete clear flag + * @arg @ref SMARTCARD_CLEAR_TCBGTF Transmission complete before guard time clear flag (when flag available) + * @arg @ref SMARTCARD_CLEAR_RTOF Receiver timeout clear flag + * @arg @ref SMARTCARD_CLEAR_EOBF End of block clear flag + * @retval None + */ +#define __HAL_SMARTCARD_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR |= (uint32_t)(__IT_CLEAR__)) + +/** @brief Set a specific SMARTCARD request flag. + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @param __REQ__ specifies the request flag to set + * This parameter can be one of the following values: + * @arg @ref SMARTCARD_RXDATA_FLUSH_REQUEST Receive data flush Request + * @arg @ref SMARTCARD_TXDATA_FLUSH_REQUEST Transmit data flush Request + * @retval None + */ +#define __HAL_SMARTCARD_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) + +/** @brief Enable the SMARTCARD one bit sample method. + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @retval None + */ +#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) + +/** @brief Disable the SMARTCARD one bit sample method. + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @retval None + */ +#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\ + &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT)) + +/** @brief Enable the USART associated to the SMARTCARD Handle. + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @retval None + */ +#define __HAL_SMARTCARD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) + +/** @brief Disable the USART associated to the SMARTCARD Handle + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @retval None + */ +#define __HAL_SMARTCARD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) + +/** + * @} + */ + +/* Private macros -------------------------------------------------------------*/ +/** @defgroup SMARTCARD_Private_Macros SMARTCARD Private Macros + * @{ + */ + +/** @brief Report the SMARTCARD clock source. + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @param __CLOCKSOURCE__ output variable. + * @retval the SMARTCARD clocking source, written in __CLOCKSOURCE__. + */ +#if defined(USART2) +#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK2: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ + case RCC_USART2CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART2CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART2CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART2CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0U) +#else +#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK2: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0U) +#endif /* USART2 */ + +/** @brief Check the Baud rate range. + * @note The maximum Baud Rate is derived from the maximum clock on WBA (100 MHz) + * divided by the oversampling used on the SMARTCARD (i.e. 16). + * @param __BAUDRATE__ Baud rate set by the configuration function. + * @retval Test result (TRUE or FALSE) + */ +#define IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 12500000U) + +/** @brief Check the block length range. + * @note The maximum SMARTCARD block length is 0xFF. + * @param __LENGTH__ block length. + * @retval Test result (TRUE or FALSE) + */ +#define IS_SMARTCARD_BLOCKLENGTH(__LENGTH__) ((__LENGTH__) <= 0xFFU) + +/** @brief Check the receiver timeout value. + * @note The maximum SMARTCARD receiver timeout value is 0xFFFFFF. + * @param __TIMEOUTVALUE__ receiver timeout value. + * @retval Test result (TRUE or FALSE) + */ +#define IS_SMARTCARD_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFFU) + +/** @brief Check the SMARTCARD autoretry counter value. + * @note The maximum number of retransmissions is 0x7. + * @param __COUNT__ number of retransmissions. + * @retval Test result (TRUE or FALSE) + */ +#define IS_SMARTCARD_AUTORETRY_COUNT(__COUNT__) ((__COUNT__) <= 0x7U) + +/** @brief Ensure that SMARTCARD frame length is valid. + * @param __LENGTH__ SMARTCARD frame length. + * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) + */ +#define IS_SMARTCARD_WORD_LENGTH(__LENGTH__) ((__LENGTH__) == SMARTCARD_WORDLENGTH_9B) + +/** @brief Ensure that SMARTCARD frame number of stop bits is valid. + * @param __STOPBITS__ SMARTCARD frame number of stop bits. + * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) + */ +#define IS_SMARTCARD_STOPBITS(__STOPBITS__) (((__STOPBITS__) == SMARTCARD_STOPBITS_0_5) ||\ + ((__STOPBITS__) == SMARTCARD_STOPBITS_1_5)) + +/** @brief Ensure that SMARTCARD frame parity is valid. + * @param __PARITY__ SMARTCARD frame parity. + * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid) + */ +#define IS_SMARTCARD_PARITY(__PARITY__) (((__PARITY__) == SMARTCARD_PARITY_EVEN) || \ + ((__PARITY__) == SMARTCARD_PARITY_ODD)) + +/** @brief Ensure that SMARTCARD communication mode is valid. + * @param __MODE__ SMARTCARD communication mode. + * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) + */ +#define IS_SMARTCARD_MODE(__MODE__) ((((__MODE__) & 0xFFF3U) == 0x00U) && ((__MODE__) != 0x00U)) + +/** @brief Ensure that SMARTCARD frame polarity is valid. + * @param __CPOL__ SMARTCARD frame polarity. + * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid) + */ +#define IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW)\ + || ((__CPOL__) == SMARTCARD_POLARITY_HIGH)) + +/** @brief Ensure that SMARTCARD frame phase is valid. + * @param __CPHA__ SMARTCARD frame phase. + * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid) + */ +#define IS_SMARTCARD_PHASE(__CPHA__) (((__CPHA__) == SMARTCARD_PHASE_1EDGE) || ((__CPHA__) == SMARTCARD_PHASE_2EDGE)) + +/** @brief Ensure that SMARTCARD frame last bit clock pulse setting is valid. + * @param __LASTBIT__ SMARTCARD frame last bit clock pulse setting. + * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid) + */ +#define IS_SMARTCARD_LASTBIT(__LASTBIT__) (((__LASTBIT__) == SMARTCARD_LASTBIT_DISABLE) || \ + ((__LASTBIT__) == SMARTCARD_LASTBIT_ENABLE)) + +/** @brief Ensure that SMARTCARD frame sampling is valid. + * @param __ONEBIT__ SMARTCARD frame sampling. + * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid) + */ +#define IS_SMARTCARD_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_DISABLE) || \ + ((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_ENABLE)) + +/** @brief Ensure that SMARTCARD NACK transmission setting is valid. + * @param __NACK__ SMARTCARD NACK transmission setting. + * @retval SET (__NACK__ is valid) or RESET (__NACK__ is invalid) + */ +#define IS_SMARTCARD_NACK(__NACK__) (((__NACK__) == SMARTCARD_NACK_ENABLE) || \ + ((__NACK__) == SMARTCARD_NACK_DISABLE)) + +/** @brief Ensure that SMARTCARD receiver timeout setting is valid. + * @param __TIMEOUT__ SMARTCARD receiver timeout setting. + * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid) + */ +#define IS_SMARTCARD_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == SMARTCARD_TIMEOUT_DISABLE) || \ + ((__TIMEOUT__) == SMARTCARD_TIMEOUT_ENABLE)) + +/** @brief Ensure that SMARTCARD clock Prescaler is valid. + * @param __CLOCKPRESCALER__ SMARTCARD clock Prescaler value. + * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid) + */ +#define IS_SMARTCARD_CLOCKPRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV1) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV2) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV4) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV6) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV8) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV10) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV12) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV16) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV32) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV64) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV128) || \ + ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV256)) + +/** @brief Ensure that SMARTCARD advanced features initialization is valid. + * @param __INIT__ SMARTCARD advanced features initialization. + * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid) + */ +#define IS_SMARTCARD_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (SMARTCARD_ADVFEATURE_NO_INIT | \ + SMARTCARD_ADVFEATURE_TXINVERT_INIT | \ + SMARTCARD_ADVFEATURE_RXINVERT_INIT | \ + SMARTCARD_ADVFEATURE_DATAINVERT_INIT | \ + SMARTCARD_ADVFEATURE_SWAP_INIT | \ + SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT | \ + SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT | \ + SMARTCARD_ADVFEATURE_MSBFIRST_INIT)) + +/** @brief Ensure that SMARTCARD frame TX inversion setting is valid. + * @param __TXINV__ SMARTCARD frame TX inversion setting. + * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid) + */ +#define IS_SMARTCARD_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_DISABLE) || \ + ((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_ENABLE)) + +/** @brief Ensure that SMARTCARD frame RX inversion setting is valid. + * @param __RXINV__ SMARTCARD frame RX inversion setting. + * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid) + */ +#define IS_SMARTCARD_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_DISABLE) || \ + ((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_ENABLE)) + +/** @brief Ensure that SMARTCARD frame data inversion setting is valid. + * @param __DATAINV__ SMARTCARD frame data inversion setting. + * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid) + */ +#define IS_SMARTCARD_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_DISABLE) || \ + ((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_ENABLE)) + +/** @brief Ensure that SMARTCARD frame RX/TX pins swap setting is valid. + * @param __SWAP__ SMARTCARD frame RX/TX pins swap setting. + * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid) + */ +#define IS_SMARTCARD_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_DISABLE) || \ + ((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_ENABLE)) + +/** @brief Ensure that SMARTCARD frame overrun setting is valid. + * @param __OVERRUN__ SMARTCARD frame overrun setting. + * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid) + */ +#define IS_SMARTCARD_OVERRUN(__OVERRUN__) (((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_ENABLE) || \ + ((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_DISABLE)) + +/** @brief Ensure that SMARTCARD DMA enabling or disabling on error setting is valid. + * @param __DMA__ SMARTCARD DMA enabling or disabling on error setting. + * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid) + */ +#define IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR) || \ + ((__DMA__) == SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR)) + +/** @brief Ensure that SMARTCARD frame MSB first setting is valid. + * @param __MSBFIRST__ SMARTCARD frame MSB first setting. + * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid) + */ +#define IS_SMARTCARD_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE) || \ + ((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE)) + +/** @brief Ensure that SMARTCARD request parameter is valid. + * @param __PARAM__ SMARTCARD request parameter. + * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid) + */ +#define IS_SMARTCARD_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == SMARTCARD_RXDATA_FLUSH_REQUEST) || \ + ((__PARAM__) == SMARTCARD_TXDATA_FLUSH_REQUEST)) + +/** + * @} + */ + +/* Include SMARTCARD HAL Extended module */ +#include "stm32wbaxx_hal_smartcard_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SMARTCARD_Exported_Functions + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ +/** @addtogroup SMARTCARD_Exported_Functions_Group1 + * @{ + */ + +HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard); +HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard); +void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard); +void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard); + +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) +/* Callbacks Register/UnRegister functions ***********************************/ +HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, + HAL_SMARTCARD_CallbackIDTypeDef CallbackID, + pSMARTCARD_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, + HAL_SMARTCARD_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/* IO operation functions *****************************************************/ +/** @addtogroup SMARTCARD_Exported_Functions_Group2 + * @{ + */ + +HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size, + uint32_t Timeout); +HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, + uint32_t Timeout); +HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size); +#if defined(HAL_DMA_MODULE_ENABLED) +HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size); +#endif /* HAL_DMA_MODULE_ENABLED */ +/* Transfer Abort functions */ +HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard); +HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcard); +HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard); +HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard); +HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard); +HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartcard); + +void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard); +void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard); +void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard); +void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard); +void HAL_SMARTCARD_AbortCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard); +void HAL_SMARTCARD_AbortTransmitCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard); +void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard); + +/** + * @} + */ + +/* Peripheral State and Error functions ***************************************/ +/** @addtogroup SMARTCARD_Exported_Functions_Group4 + * @{ + */ + +HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(const SMARTCARD_HandleTypeDef *hsmartcard); +uint32_t HAL_SMARTCARD_GetError(const SMARTCARD_HandleTypeDef *hsmartcard); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WBAxx_HAL_SMARTCARD_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_smartcard_ex.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_smartcard_ex.h new file mode 100644 index 0000000000..d1fc734243 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_smartcard_ex.h @@ -0,0 +1,335 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_smartcard_ex.h + * @author MCD Application Team + * @brief Header file of SMARTCARD HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_HAL_SMARTCARD_EX_H +#define STM32WBAxx_HAL_SMARTCARD_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal_def.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @addtogroup SMARTCARDEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @addtogroup SMARTCARDEx_Exported_Constants SMARTCARD Extended Exported Constants + * @{ + */ + +/** @defgroup SMARTCARDEx_Transmission_Completion_Indication SMARTCARD Transmission Completion Indication + * @{ + */ +#define SMARTCARD_TCBGT SMARTCARD_IT_TCBGT /*!< SMARTCARD transmission complete before guard time */ +#define SMARTCARD_TC SMARTCARD_IT_TC /*!< SMARTCARD transmission complete (flag raised when guard time has elapsed) */ +/** + * @} + */ + +/** @defgroup SMARTCARDEx_Advanced_Features_Initialization_Type SMARTCARD advanced feature initialization type + * @{ + */ +#define SMARTCARD_ADVFEATURE_NO_INIT 0x00000000U /*!< No advanced feature initialization */ +#define SMARTCARD_ADVFEATURE_TXINVERT_INIT 0x00000001U /*!< TX pin active level inversion */ +#define SMARTCARD_ADVFEATURE_RXINVERT_INIT 0x00000002U /*!< RX pin active level inversion */ +#define SMARTCARD_ADVFEATURE_DATAINVERT_INIT 0x00000004U /*!< Binary data inversion */ +#define SMARTCARD_ADVFEATURE_SWAP_INIT 0x00000008U /*!< TX/RX pins swap */ +#define SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT 0x00000010U /*!< RX overrun disable */ +#define SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT 0x00000020U /*!< DMA disable on Reception Error */ +#define SMARTCARD_ADVFEATURE_MSBFIRST_INIT 0x00000080U /*!< Most significant bit sent/received first */ +#define SMARTCARD_ADVFEATURE_TXCOMPLETION 0x00000100U /*!< TX completion indication before of after guard time */ +/** + * @} + */ + +/** @defgroup SMARTCARDEx_FIFO_mode SMARTCARD FIFO mode + * @brief SMARTCARD FIFO mode + * @{ + */ +#define SMARTCARD_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */ +#define SMARTCARD_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */ +/** + * @} + */ + +/** @defgroup SMARTCARDEx_TXFIFO_threshold_level SMARTCARD TXFIFO threshold level + * @brief SMARTCARD TXFIFO level + * @{ + */ +#define SMARTCARD_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TXFIFO reaches 1/8 of its depth */ +#define SMARTCARD_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0 /*!< TXFIFO reaches 1/4 of its depth */ +#define SMARTCARD_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1 /*!< TXFIFO reaches 1/2 of its depth */ +#define SMARTCARD_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TXFIFO reaches 3/4 of its depth */ +#define SMARTCARD_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2 /*!< TXFIFO reaches 7/8 of its depth */ +#define SMARTCARD_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TXFIFO becomes empty */ +/** + * @} + */ + +/** @defgroup SMARTCARDEx_RXFIFO_threshold_level SMARTCARD RXFIFO threshold level + * @brief SMARTCARD RXFIFO level + * @{ + */ +#define SMARTCARD_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RXFIFO FIFO reaches 1/8 of its depth */ +#define SMARTCARD_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0 /*!< RXFIFO FIFO reaches 1/4 of its depth */ +#define SMARTCARD_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1 /*!< RXFIFO FIFO reaches 1/2 of its depth */ +#define SMARTCARD_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RXFIFO FIFO reaches 3/4 of its depth */ +#define SMARTCARD_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2 /*!< RXFIFO FIFO reaches 7/8 of its depth */ +#define SMARTCARD_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RXFIFO FIFO becomes full */ +/** + * @} + */ + +/** @defgroup SMARTCARDEx_Flags SMARTCARD Flags + * Elements values convention: 0xXXXX + * - 0xXXXX : Flag mask in the ISR register + * @{ + */ +#define SMARTCARD_FLAG_TCBGT USART_ISR_TCBGT /*!< SMARTCARD transmission complete before guard time completion */ +#define SMARTCARD_FLAG_REACK USART_ISR_REACK /*!< SMARTCARD receive enable acknowledge flag */ +#define SMARTCARD_FLAG_TEACK USART_ISR_TEACK /*!< SMARTCARD transmit enable acknowledge flag */ +#define SMARTCARD_FLAG_BUSY USART_ISR_BUSY /*!< SMARTCARD busy flag */ +#define SMARTCARD_FLAG_EOBF USART_ISR_EOBF /*!< SMARTCARD end of block flag */ +#define SMARTCARD_FLAG_RTOF USART_ISR_RTOF /*!< SMARTCARD receiver timeout flag */ +#define SMARTCARD_FLAG_TXE USART_ISR_TXE_TXFNF /*!< SMARTCARD transmit data register empty */ +#define SMARTCARD_FLAG_TXFNF USART_ISR_TXE_TXFNF /*!< SMARTCARD TXFIFO not full */ +#define SMARTCARD_FLAG_TC USART_ISR_TC /*!< SMARTCARD transmission complete */ +#define SMARTCARD_FLAG_RXNE USART_ISR_RXNE_RXFNE /*!< SMARTCARD read data register not empty */ +#define SMARTCARD_FLAG_RXFNE USART_ISR_RXNE_RXFNE /*!< SMARTCARD RXFIFO not empty */ +#define SMARTCARD_FLAG_IDLE USART_ISR_IDLE /*!< SMARTCARD idle line detection */ +#define SMARTCARD_FLAG_ORE USART_ISR_ORE /*!< SMARTCARD overrun error */ +#define SMARTCARD_FLAG_NE USART_ISR_NE /*!< SMARTCARD noise error */ +#define SMARTCARD_FLAG_FE USART_ISR_FE /*!< SMARTCARD frame error */ +#define SMARTCARD_FLAG_PE USART_ISR_PE /*!< SMARTCARD parity error */ +#define SMARTCARD_FLAG_TXFE USART_ISR_TXFE /*!< SMARTCARD TXFIFO Empty flag */ +#define SMARTCARD_FLAG_RXFF USART_ISR_RXFF /*!< SMARTCARD RXFIFO Full flag */ +#define SMARTCARD_FLAG_RXFT USART_ISR_RXFT /*!< SMARTCARD RXFIFO threshold flag */ +#define SMARTCARD_FLAG_TXFT USART_ISR_TXFT /*!< SMARTCARD TXFIFO threshold flag */ +/** + * @} + */ + +/** @defgroup SMARTCARDEx_Interrupt_definition SMARTCARD Interrupts Definition + * Elements values convention: 000ZZZZZ0XXYYYYYb + * - YYYYY : Interrupt source position in the XX register (5 bits) + * - XX : Interrupt source register (2 bits) + * - 01: CR1 register + * - 10: CR2 register + * - 11: CR3 register + * - ZZZZZ : Flag position in the ISR register(5 bits) + * @{ + */ +#define SMARTCARD_IT_PE 0x0028U /*!< SMARTCARD parity error interruption */ +#define SMARTCARD_IT_TXE 0x0727U /*!< SMARTCARD transmit data register empty interruption */ +#define SMARTCARD_IT_TXFNF 0x0727U /*!< SMARTCARD TX FIFO not full interruption */ +#define SMARTCARD_IT_TC 0x0626U /*!< SMARTCARD transmission complete interruption */ +#define SMARTCARD_IT_RXNE 0x0525U /*!< SMARTCARD read data register not empty interruption */ +#define SMARTCARD_IT_RXFNE 0x0525U /*!< SMARTCARD RXFIFO not empty interruption */ +#define SMARTCARD_IT_IDLE 0x0424U /*!< SMARTCARD idle line detection interruption */ + +#define SMARTCARD_IT_ERR 0x0060U /*!< SMARTCARD error interruption */ +#define SMARTCARD_IT_ORE 0x0300U /*!< SMARTCARD overrun error interruption */ +#define SMARTCARD_IT_NE 0x0200U /*!< SMARTCARD noise error interruption */ +#define SMARTCARD_IT_FE 0x0100U /*!< SMARTCARD frame error interruption */ + +#define SMARTCARD_IT_EOB 0x0C3BU /*!< SMARTCARD end of block interruption */ +#define SMARTCARD_IT_RTO 0x0B3AU /*!< SMARTCARD receiver timeout interruption */ +#define SMARTCARD_IT_TCBGT 0x1978U /*!< SMARTCARD transmission complete before guard time completion interruption */ + +#define SMARTCARD_IT_RXFF 0x183FU /*!< SMARTCARD RXFIFO full interruption */ +#define SMARTCARD_IT_TXFE 0x173EU /*!< SMARTCARD TXFIFO empty interruption */ +#define SMARTCARD_IT_RXFT 0x1A7CU /*!< SMARTCARD RXFIFO threshold reached interruption */ +#define SMARTCARD_IT_TXFT 0x1B77U /*!< SMARTCARD TXFIFO threshold reached interruption */ +/** + * @} + */ + +/** @defgroup SMARTCARDEx_IT_CLEAR_Flags SMARTCARD Interruption Clear Flags + * @{ + */ +#define SMARTCARD_CLEAR_PEF USART_ICR_PECF /*!< SMARTCARD parity error clear flag */ +#define SMARTCARD_CLEAR_FEF USART_ICR_FECF /*!< SMARTCARD framing error clear flag */ +#define SMARTCARD_CLEAR_NEF USART_ICR_NECF /*!< SMARTCARD noise error detected clear flag */ +#define SMARTCARD_CLEAR_OREF USART_ICR_ORECF /*!< SMARTCARD overrun error clear flag */ +#define SMARTCARD_CLEAR_IDLEF USART_ICR_IDLECF /*!< SMARTCARD idle line detected clear flag */ +#define SMARTCARD_CLEAR_TXFECF USART_ICR_TXFECF /*!< TXFIFO empty Clear Flag */ +#define SMARTCARD_CLEAR_TCF USART_ICR_TCCF /*!< SMARTCARD transmission complete clear flag */ +#define SMARTCARD_CLEAR_TCBGTF USART_ICR_TCBGTCF /*!< SMARTCARD transmission complete before guard time completion clear flag */ +#define SMARTCARD_CLEAR_RTOF USART_ICR_RTOCF /*!< SMARTCARD receiver time out clear flag */ +#define SMARTCARD_CLEAR_EOBF USART_ICR_EOBCF /*!< SMARTCARD end of block clear flag */ +/** + * @} + */ + +/** + * @} + */ +/* Exported macros -----------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup SMARTCARDEx_Private_Macros SMARTCARD Extended Private Macros + * @{ + */ + +/** @brief Set the Transmission Completion flag + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @note If TCBGT (Transmission Complete Before Guard Time) flag is not available or if + * AdvancedInit.TxCompletionIndication is not already filled, the latter is forced + * to SMARTCARD_TC (transmission completion indication when guard time has elapsed). + * @retval None + */ +#define SMARTCARD_TRANSMISSION_COMPLETION_SETTING(__HANDLE__) \ + do { \ + if (HAL_IS_BIT_CLR((__HANDLE__)->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXCOMPLETION)) \ + { \ + (__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC; \ + } \ + else \ + { \ + assert_param(IS_SMARTCARD_TRANSMISSION_COMPLETION((__HANDLE__)->AdvancedInit.TxCompletionIndication)); \ + } \ + } while(0U) + +/** @brief Return the transmission completion flag. + * @param __HANDLE__ specifies the SMARTCARD Handle. + * @note Based on AdvancedInit.TxCompletionIndication setting, return TC or TCBGT flag. + * When TCBGT flag (Transmission Complete Before Guard Time) is not available, TC flag is + * reported. + * @retval Transmission completion flag + */ +#define SMARTCARD_TRANSMISSION_COMPLETION_FLAG(__HANDLE__) \ + (((__HANDLE__)->AdvancedInit.TxCompletionIndication == SMARTCARD_TC) ? (SMARTCARD_FLAG_TC) : (SMARTCARD_FLAG_TCBGT)) + + +/** @brief Ensure that SMARTCARD frame transmission completion used flag is valid. + * @param __TXCOMPLETE__ SMARTCARD frame transmission completion used flag. + * @retval SET (__TXCOMPLETE__ is valid) or RESET (__TXCOMPLETE__ is invalid) + */ +#define IS_SMARTCARD_TRANSMISSION_COMPLETION(__TXCOMPLETE__) (((__TXCOMPLETE__) == SMARTCARD_TCBGT) || \ + ((__TXCOMPLETE__) == SMARTCARD_TC)) + +/** @brief Ensure that SMARTCARD FIFO mode is valid. + * @param __STATE__ SMARTCARD FIFO mode. + * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid) + */ +#define IS_SMARTCARD_FIFOMODE_STATE(__STATE__) (((__STATE__) == SMARTCARD_FIFOMODE_DISABLE ) || \ + ((__STATE__) == SMARTCARD_FIFOMODE_ENABLE)) + +/** @brief Ensure that SMARTCARD TXFIFO threshold level is valid. + * @param __THRESHOLD__ SMARTCARD TXFIFO threshold level. + * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) + */ +#define IS_SMARTCARD_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_8) || \ + ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_4) || \ + ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_2) || \ + ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_3_4) || \ + ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_7_8) || \ + ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_8_8)) + +/** @brief Ensure that SMARTCARD RXFIFO threshold level is valid. + * @param __THRESHOLD__ SMARTCARD RXFIFO threshold level. + * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) + */ +#define IS_SMARTCARD_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_8) || \ + ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_4) || \ + ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_2) || \ + ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_3_4) || \ + ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_7_8) || \ + ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_8_8)) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SMARTCARDEx_Exported_Functions + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ +/* IO operation methods *******************************************************/ + +/** @addtogroup SMARTCARDEx_Exported_Functions_Group1 + * @{ + */ + +/* Peripheral Control functions ***********************************************/ +void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength); +void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue); +HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard); +HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard); + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SMARTCARDEx_Exported_Functions_Group2 + * @{ + */ + +/* IO operation functions *****************************************************/ +void HAL_SMARTCARDEx_RxFifoFullCallback(SMARTCARD_HandleTypeDef *hsmartcard); +void HAL_SMARTCARDEx_TxFifoEmptyCallback(SMARTCARD_HandleTypeDef *hsmartcard); + +/** + * @} + */ + +/** @addtogroup SMARTCARDEx_Exported_Functions_Group3 + * @{ + */ + +/* Peripheral Control functions ***********************************************/ +HAL_StatusTypeDef HAL_SMARTCARDEx_EnableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard); +HAL_StatusTypeDef HAL_SMARTCARDEx_DisableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard); +HAL_StatusTypeDef HAL_SMARTCARDEx_SetTxFifoThreshold(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold); +HAL_StatusTypeDef HAL_SMARTCARDEx_SetRxFifoThreshold(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold); + +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WBAxx_HAL_SMARTCARD_EX_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_smbus.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_smbus.h new file mode 100644 index 0000000000..b347188070 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_smbus.h @@ -0,0 +1,789 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_smbus.h + * @author MCD Application Team + * @brief Header file of SMBUS HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_HAL_SMBUS_H +#define STM32WBAxx_HAL_SMBUS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal_def.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @addtogroup SMBUS + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup SMBUS_Exported_Types SMBUS Exported Types + * @{ + */ + +/** @defgroup SMBUS_Configuration_Structure_definition SMBUS Configuration Structure definition + * @brief SMBUS Configuration Structure definition + * @{ + */ +typedef struct +{ + uint32_t Timing; /*!< Specifies the SMBUS_TIMINGR_register value. + This parameter calculated by referring to SMBUS initialization section + in Reference manual */ + uint32_t AnalogFilter; /*!< Specifies if Analog Filter is enable or not. + This parameter can be a value of @ref SMBUS_Analog_Filter */ + + uint32_t OwnAddress1; /*!< Specifies the first device own address. + This parameter can be a 7-bit address. */ + + uint32_t AddressingMode; /*!< Specifies addressing mode selected. + This parameter can be a value of @ref SMBUS_addressing_mode */ + + uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. + This parameter can be a value of @ref SMBUS_dual_addressing_mode */ + + uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected + This parameter can be a 7-bit address. */ + + uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address + if dual addressing mode is selected + This parameter can be a value of @ref SMBUS_own_address2_masks. */ + + uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. + This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */ + + uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. + This parameter can be a value of @ref SMBUS_nostretch_mode */ + + uint32_t PacketErrorCheckMode; /*!< Specifies if Packet Error Check mode is selected. + This parameter can be a value of @ref SMBUS_packet_error_check_mode */ + + uint32_t PeripheralMode; /*!< Specifies which mode of Periphal is selected. + This parameter can be a value of @ref SMBUS_peripheral_mode */ + + uint32_t SMBusTimeout; /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value. + (Enable bits and different timeout values) + This parameter calculated by referring to SMBUS initialization section + in Reference manual */ +} SMBUS_InitTypeDef; +/** + * @} + */ + +/** @defgroup HAL_state_definition HAL state definition + * @brief HAL State definition + * @{ + */ +#define HAL_SMBUS_STATE_RESET (0x00000000U) /*!< SMBUS not yet initialized or disabled */ +#define HAL_SMBUS_STATE_READY (0x00000001U) /*!< SMBUS initialized and ready for use */ +#define HAL_SMBUS_STATE_BUSY (0x00000002U) /*!< SMBUS internal process is ongoing */ +#define HAL_SMBUS_STATE_MASTER_BUSY_TX (0x00000012U) /*!< Master Data Transmission process is ongoing */ +#define HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U) /*!< Master Data Reception process is ongoing */ +#define HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */ +#define HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */ +#define HAL_SMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */ +/** + * @} + */ + +/** @defgroup SMBUS_Error_Code_definition SMBUS Error Code definition + * @brief SMBUS Error Code definition + * @{ + */ +#define HAL_SMBUS_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_SMBUS_ERROR_BERR (0x00000001U) /*!< BERR error */ +#define HAL_SMBUS_ERROR_ARLO (0x00000002U) /*!< ARLO error */ +#define HAL_SMBUS_ERROR_ACKF (0x00000004U) /*!< ACKF error */ +#define HAL_SMBUS_ERROR_OVR (0x00000008U) /*!< OVR error */ +#define HAL_SMBUS_ERROR_HALTIMEOUT (0x00000010U) /*!< Timeout error */ +#define HAL_SMBUS_ERROR_BUSTIMEOUT (0x00000020U) /*!< Bus Timeout error */ +#define HAL_SMBUS_ERROR_ALERT (0x00000040U) /*!< Alert error */ +#define HAL_SMBUS_ERROR_PECERR (0x00000080U) /*!< PEC error */ +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) +#define HAL_SMBUS_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */ +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ +#define HAL_SMBUS_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */ +/** + * @} + */ + +/** @defgroup SMBUS_handle_Structure_definition SMBUS handle Structure definition + * @brief SMBUS handle Structure definition + * @{ + */ +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) +typedef struct __SMBUS_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ +{ + I2C_TypeDef *Instance; /*!< SMBUS registers base address */ + + SMBUS_InitTypeDef Init; /*!< SMBUS communication parameters */ + + uint8_t *pBuffPtr; /*!< Pointer to SMBUS transfer buffer */ + + uint16_t XferSize; /*!< SMBUS transfer size */ + + __IO uint16_t XferCount; /*!< SMBUS transfer counter */ + + __IO uint32_t XferOptions; /*!< SMBUS transfer options */ + + __IO uint32_t PreviousState; /*!< SMBUS communication Previous state */ + + HAL_LockTypeDef Lock; /*!< SMBUS locking object */ + + __IO uint32_t State; /*!< SMBUS communication state */ + + __IO uint32_t ErrorCode; /*!< SMBUS Error code */ + +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + void (* MasterTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); + /*!< SMBUS Master Tx Transfer completed callback */ + void (* MasterRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); + /*!< SMBUS Master Rx Transfer completed callback */ + void (* SlaveTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); + /*!< SMBUS Slave Tx Transfer completed callback */ + void (* SlaveRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); + /*!< SMBUS Slave Rx Transfer completed callback */ + void (* ListenCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); + /*!< SMBUS Listen Complete callback */ + void (* ErrorCallback)(struct __SMBUS_HandleTypeDef *hsmbus); + /*!< SMBUS Error callback */ + + void (* AddrCallback)(struct __SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); + /*!< SMBUS Slave Address Match callback */ + + void (* MspInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus); + /*!< SMBUS Msp Init callback */ + void (* MspDeInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus); + /*!< SMBUS Msp DeInit callback */ + +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ +} SMBUS_HandleTypeDef; + +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) +/** + * @brief HAL SMBUS Callback ID enumeration definition + */ +typedef enum +{ + HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< SMBUS Master Tx Transfer completed callback ID */ + HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< SMBUS Master Rx Transfer completed callback ID */ + HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< SMBUS Slave Tx Transfer completed callback ID */ + HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< SMBUS Slave Rx Transfer completed callback ID */ + HAL_SMBUS_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< SMBUS Listen Complete callback ID */ + HAL_SMBUS_ERROR_CB_ID = 0x05U, /*!< SMBUS Error callback ID */ + + HAL_SMBUS_MSPINIT_CB_ID = 0x06U, /*!< SMBUS Msp Init callback ID */ + HAL_SMBUS_MSPDEINIT_CB_ID = 0x07U /*!< SMBUS Msp DeInit callback ID */ + +} HAL_SMBUS_CallbackIDTypeDef; + +/** + * @brief HAL SMBUS Callback pointer definition + */ +typedef void (*pSMBUS_CallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus); +/*!< pointer to an SMBUS callback function */ +typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, + uint16_t AddrMatchCode); +/*!< pointer to an SMBUS Address Match callback function */ + +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** + * @} + */ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup SMBUS_Exported_Constants SMBUS Exported Constants + * @{ + */ + +/** @defgroup SMBUS_Analog_Filter SMBUS Analog Filter + * @{ + */ +#define SMBUS_ANALOGFILTER_ENABLE (0x00000000U) +#define SMBUS_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF +/** + * @} + */ + +/** @defgroup SMBUS_addressing_mode SMBUS addressing mode + * @{ + */ +#define SMBUS_ADDRESSINGMODE_7BIT (0x00000001U) +/** + * @} + */ + +/** @defgroup SMBUS_dual_addressing_mode SMBUS dual addressing mode + * @{ + */ + +#define SMBUS_DUALADDRESS_DISABLE (0x00000000U) +#define SMBUS_DUALADDRESS_ENABLE I2C_OAR2_OA2EN +/** + * @} + */ + +/** @defgroup SMBUS_own_address2_masks SMBUS ownaddress2 masks + * @{ + */ + +#define SMBUS_OA2_NOMASK ((uint8_t)0x00U) +#define SMBUS_OA2_MASK01 ((uint8_t)0x01U) +#define SMBUS_OA2_MASK02 ((uint8_t)0x02U) +#define SMBUS_OA2_MASK03 ((uint8_t)0x03U) +#define SMBUS_OA2_MASK04 ((uint8_t)0x04U) +#define SMBUS_OA2_MASK05 ((uint8_t)0x05U) +#define SMBUS_OA2_MASK06 ((uint8_t)0x06U) +#define SMBUS_OA2_MASK07 ((uint8_t)0x07U) +/** + * @} + */ + + +/** @defgroup SMBUS_general_call_addressing_mode SMBUS general call addressing mode + * @{ + */ +#define SMBUS_GENERALCALL_DISABLE (0x00000000U) +#define SMBUS_GENERALCALL_ENABLE I2C_CR1_GCEN +/** + * @} + */ + +/** @defgroup SMBUS_nostretch_mode SMBUS nostretch mode + * @{ + */ +#define SMBUS_NOSTRETCH_DISABLE (0x00000000U) +#define SMBUS_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH +/** + * @} + */ + +/** @defgroup SMBUS_packet_error_check_mode SMBUS packet error check mode + * @{ + */ +#define SMBUS_PEC_DISABLE (0x00000000U) +#define SMBUS_PEC_ENABLE I2C_CR1_PECEN +/** + * @} + */ + +/** @defgroup SMBUS_peripheral_mode SMBUS peripheral mode + * @{ + */ +#define SMBUS_PERIPHERAL_MODE_SMBUS_HOST I2C_CR1_SMBHEN +#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (0x00000000U) +#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP I2C_CR1_SMBDEN +/** + * @} + */ + +/** @defgroup SMBUS_ReloadEndMode_definition SMBUS ReloadEndMode definition + * @{ + */ + +#define SMBUS_SOFTEND_MODE (0x00000000U) +#define SMBUS_RELOAD_MODE I2C_CR2_RELOAD +#define SMBUS_AUTOEND_MODE I2C_CR2_AUTOEND +#define SMBUS_SENDPEC_MODE I2C_CR2_PECBYTE +/** + * @} + */ + +/** @defgroup SMBUS_StartStopMode_definition SMBUS StartStopMode definition + * @{ + */ + +#define SMBUS_NO_STARTSTOP (0x00000000U) +#define SMBUS_GENERATE_NO_START_READ (uint32_t)(0x80000000U | I2C_CR2_RD_WRN) +#define SMBUS_GENERATE_NO_START_WRITE (uint32_t)(0x80000000U) +#define SMBUS_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) +#define SMBUS_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) +#define SMBUS_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) +/** + * @} + */ + +/** @defgroup SMBUS_XferOptions_definition SMBUS XferOptions definition + * @{ + */ + +/* List of XferOptions in usage of : + * 1- Restart condition when direction change + * 2- No Restart condition in other use cases + */ +#define SMBUS_FIRST_FRAME SMBUS_SOFTEND_MODE +#define SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE)) +#define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE +#define SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE +#define SMBUS_FIRST_FRAME_WITH_PEC ((uint32_t)(SMBUS_SOFTEND_MODE | SMBUS_SENDPEC_MODE)) +#define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) +#define SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) + +/* List of XferOptions in usage of : + * 1- Restart condition in all use cases (direction change or not) + */ +#define SMBUS_OTHER_FRAME_NO_PEC (0x000000AAU) +#define SMBUS_OTHER_FRAME_WITH_PEC (0x0000AA00U) +#define SMBUS_OTHER_AND_LAST_FRAME_NO_PEC (0x00AA0000U) +#define SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC (0xAA000000U) +/** + * @} + */ + +/** @defgroup SMBUS_Interrupt_configuration_definition SMBUS Interrupt configuration definition + * @brief SMBUS Interrupt definition + * Elements values convention: 0xXXXXXXXX + * - XXXXXXXX : Interrupt control mask + * @{ + */ +#define SMBUS_IT_ERRI I2C_CR1_ERRIE +#define SMBUS_IT_TCI I2C_CR1_TCIE +#define SMBUS_IT_STOPI I2C_CR1_STOPIE +#define SMBUS_IT_NACKI I2C_CR1_NACKIE +#define SMBUS_IT_ADDRI I2C_CR1_ADDRIE +#define SMBUS_IT_RXI I2C_CR1_RXIE +#define SMBUS_IT_TXI I2C_CR1_TXIE +#define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | \ + SMBUS_IT_NACKI | SMBUS_IT_TXI) +#define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | \ + SMBUS_IT_RXI) +#define SMBUS_IT_ALERT (SMBUS_IT_ERRI) +#define SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI) +/** + * @} + */ + +/** @defgroup SMBUS_Flag_definition SMBUS Flag definition + * @brief Flag definition + * Elements values convention: 0xXXXXYYYY + * - XXXXXXXX : Flag mask + * @{ + */ + +#define SMBUS_FLAG_TXE I2C_ISR_TXE +#define SMBUS_FLAG_TXIS I2C_ISR_TXIS +#define SMBUS_FLAG_RXNE I2C_ISR_RXNE +#define SMBUS_FLAG_ADDR I2C_ISR_ADDR +#define SMBUS_FLAG_AF I2C_ISR_NACKF +#define SMBUS_FLAG_STOPF I2C_ISR_STOPF +#define SMBUS_FLAG_TC I2C_ISR_TC +#define SMBUS_FLAG_TCR I2C_ISR_TCR +#define SMBUS_FLAG_BERR I2C_ISR_BERR +#define SMBUS_FLAG_ARLO I2C_ISR_ARLO +#define SMBUS_FLAG_OVR I2C_ISR_OVR +#define SMBUS_FLAG_PECERR I2C_ISR_PECERR +#define SMBUS_FLAG_TIMEOUT I2C_ISR_TIMEOUT +#define SMBUS_FLAG_ALERT I2C_ISR_ALERT +#define SMBUS_FLAG_BUSY I2C_ISR_BUSY +#define SMBUS_FLAG_DIR I2C_ISR_DIR +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros ------------------------------------------------------------*/ +/** @defgroup SMBUS_Exported_Macros SMBUS Exported Macros + * @{ + */ + +/** @brief Reset SMBUS handle state. + * @param __HANDLE__ specifies the SMBUS Handle. + * @retval None + */ +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) +#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_SMBUS_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET) +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ + +/** @brief Enable the specified SMBUS interrupts. + * @param __HANDLE__ specifies the SMBUS Handle. + * @param __INTERRUPT__ specifies the interrupt source to enable. + * This parameter can be one of the following values: + * @arg @ref SMBUS_IT_ERRI Errors interrupt enable + * @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable + * @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable + * @arg @ref SMBUS_IT_NACKI NACK received interrupt enable + * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable + * @arg @ref SMBUS_IT_RXI RX interrupt enable + * @arg @ref SMBUS_IT_TXI TX interrupt enable + * + * @retval None + */ +#define __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__)) + +/** @brief Disable the specified SMBUS interrupts. + * @param __HANDLE__ specifies the SMBUS Handle. + * @param __INTERRUPT__ specifies the interrupt source to disable. + * This parameter can be one of the following values: + * @arg @ref SMBUS_IT_ERRI Errors interrupt enable + * @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable + * @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable + * @arg @ref SMBUS_IT_NACKI NACK received interrupt enable + * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable + * @arg @ref SMBUS_IT_RXI RX interrupt enable + * @arg @ref SMBUS_IT_TXI TX interrupt enable + * + * @retval None + */ +#define __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) + +/** @brief Check whether the specified SMBUS interrupt source is enabled or not. + * @param __HANDLE__ specifies the SMBUS Handle. + * @param __INTERRUPT__ specifies the SMBUS interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref SMBUS_IT_ERRI Errors interrupt enable + * @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable + * @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable + * @arg @ref SMBUS_IT_NACKI NACK received interrupt enable + * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable + * @arg @ref SMBUS_IT_RXI RX interrupt enable + * @arg @ref SMBUS_IT_TXI TX interrupt enable + * + * @retval The new state of __IT__ (SET or RESET). + */ +#define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ + ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Check whether the specified SMBUS flag is set or not. + * @param __HANDLE__ specifies the SMBUS Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref SMBUS_FLAG_TXE Transmit data register empty + * @arg @ref SMBUS_FLAG_TXIS Transmit interrupt status + * @arg @ref SMBUS_FLAG_RXNE Receive data register not empty + * @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode) + * @arg @ref SMBUS_FLAG_AF NACK received flag + * @arg @ref SMBUS_FLAG_STOPF STOP detection flag + * @arg @ref SMBUS_FLAG_TC Transfer complete (master mode) + * @arg @ref SMBUS_FLAG_TCR Transfer complete reload + * @arg @ref SMBUS_FLAG_BERR Bus error + * @arg @ref SMBUS_FLAG_ARLO Arbitration lost + * @arg @ref SMBUS_FLAG_OVR Overrun/Underrun + * @arg @ref SMBUS_FLAG_PECERR PEC error in reception + * @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag + * @arg @ref SMBUS_FLAG_ALERT SMBus alert + * @arg @ref SMBUS_FLAG_BUSY Bus busy + * @arg @ref SMBUS_FLAG_DIR Transfer direction (slave mode) + * + * @retval The new state of __FLAG__ (SET or RESET). + */ +#define SMBUS_FLAG_MASK (0x0001FFFFU) +#define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) \ + (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == \ + ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET) + +/** @brief Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit. + * @param __HANDLE__ specifies the SMBUS Handle. + * @param __FLAG__ specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg @ref SMBUS_FLAG_TXE Transmit data register empty + * @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode) + * @arg @ref SMBUS_FLAG_AF NACK received flag + * @arg @ref SMBUS_FLAG_STOPF STOP detection flag + * @arg @ref SMBUS_FLAG_BERR Bus error + * @arg @ref SMBUS_FLAG_ARLO Arbitration lost + * @arg @ref SMBUS_FLAG_OVR Overrun/Underrun + * @arg @ref SMBUS_FLAG_PECERR PEC error in reception + * @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag + * @arg @ref SMBUS_FLAG_ALERT SMBus alert + * + * @retval None + */ +#define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == SMBUS_FLAG_TXE) ? \ + ((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \ + ((__HANDLE__)->Instance->ICR = (__FLAG__))) + +/** @brief Enable the specified SMBUS peripheral. + * @param __HANDLE__ specifies the SMBUS Handle. + * @retval None + */ +#define __HAL_SMBUS_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) + +/** @brief Disable the specified SMBUS peripheral. + * @param __HANDLE__ specifies the SMBUS Handle. + * @retval None + */ +#define __HAL_SMBUS_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) + +/** @brief Generate a Non-Acknowledge SMBUS peripheral in Slave mode. + * @param __HANDLE__ specifies the SMBUS Handle. + * @retval None + */ +#define __HAL_SMBUS_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK)) + +/** + * @} + */ + + +/* Private constants ---------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup SMBUS_Private_Macro SMBUS Private Macros + * @{ + */ + +#define IS_SMBUS_ANALOG_FILTER(FILTER) (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \ + ((FILTER) == SMBUS_ANALOGFILTER_DISABLE)) + +#define IS_SMBUS_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) + +#define IS_SMBUS_ADDRESSING_MODE(MODE) ((MODE) == SMBUS_ADDRESSINGMODE_7BIT) + +#define IS_SMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \ + ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE)) + +#define IS_SMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == SMBUS_OA2_NOMASK) || \ + ((MASK) == SMBUS_OA2_MASK01) || \ + ((MASK) == SMBUS_OA2_MASK02) || \ + ((MASK) == SMBUS_OA2_MASK03) || \ + ((MASK) == SMBUS_OA2_MASK04) || \ + ((MASK) == SMBUS_OA2_MASK05) || \ + ((MASK) == SMBUS_OA2_MASK06) || \ + ((MASK) == SMBUS_OA2_MASK07)) + +#define IS_SMBUS_GENERAL_CALL(CALL) (((CALL) == SMBUS_GENERALCALL_DISABLE) || \ + ((CALL) == SMBUS_GENERALCALL_ENABLE)) + +#define IS_SMBUS_NO_STRETCH(STRETCH) (((STRETCH) == SMBUS_NOSTRETCH_DISABLE) || \ + ((STRETCH) == SMBUS_NOSTRETCH_ENABLE)) + +#define IS_SMBUS_PEC(PEC) (((PEC) == SMBUS_PEC_DISABLE) || \ + ((PEC) == SMBUS_PEC_ENABLE)) + +#define IS_SMBUS_PERIPHERAL_MODE(MODE) (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST) || \ + ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \ + ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP)) + +#define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \ + ((MODE) == SMBUS_AUTOEND_MODE) || \ + ((MODE) == SMBUS_SOFTEND_MODE) || \ + ((MODE) == SMBUS_SENDPEC_MODE) || \ + ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \ + ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \ + ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \ + ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | \ + SMBUS_RELOAD_MODE ))) + + +#define IS_SMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == SMBUS_GENERATE_STOP) || \ + ((REQUEST) == SMBUS_GENERATE_START_READ) || \ + ((REQUEST) == SMBUS_GENERATE_START_WRITE) || \ + ((REQUEST) == SMBUS_NO_STARTSTOP)) + + +#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \ + ((REQUEST) == SMBUS_FIRST_FRAME) || \ + ((REQUEST) == SMBUS_NEXT_FRAME) || \ + ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \ + ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \ + ((REQUEST) == SMBUS_FIRST_FRAME_WITH_PEC) || \ + ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \ + ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC)) + +#define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC) || \ + ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \ + ((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC) || \ + ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC)) + +#define SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= \ + (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | \ + I2C_CR1_PECEN))) +#define SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \ + (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | \ + I2C_CR2_NBYTES | I2C_CR2_RELOAD | \ + I2C_CR2_RD_WRN))) + +#define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? \ + (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \ + (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \ + (~I2C_CR2_RD_WRN)) : \ + (uint32_t)((((uint32_t)(__ADDRESS__) & \ + (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | \ + (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) + +#define SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U) +#define SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U) +#define SMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND) +#define SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE) +#define SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN) + +#define SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == \ + ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET) +#define SMBUS_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET) + +#define IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU) +#define IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU) + +/** + * @} + */ + +/* Include SMBUS HAL Extended module */ +#include "stm32wbaxx_hal_smbus_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions + * @{ + */ + +/** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ +HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus); +HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus); +void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus); +void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus); +HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter); +HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, + HAL_SMBUS_CallbackIDTypeDef CallbackID, + pSMBUS_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, + HAL_SMBUS_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, + pSMBUS_AddrCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions + * @{ + */ + +/* IO operation functions *****************************************************/ +/** @addtogroup Blocking_mode_Polling Blocking mode Polling + * @{ + */ +/******* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, + uint32_t Timeout); +/** + * @} + */ + +/** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt + * @{ + */ +/******* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, + uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, + uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress); +HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); +HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); + +HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus); +HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus); +HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus); +HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus); +/** + * @} + */ + +/** @addtogroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks + * @{ + */ +/******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */ +void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus); +void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus); +void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus); +void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus); +void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus); +void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus); +void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); +void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus); +void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus); + +/** + * @} + */ + +/** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions + * @{ + */ + +/* Peripheral State and Errors functions **************************************************/ +uint32_t HAL_SMBUS_GetState(const SMBUS_HandleTypeDef *hsmbus); +uint32_t HAL_SMBUS_GetError(const SMBUS_HandleTypeDef *hsmbus); + +/** + * @} + */ + +/** + * @} + */ + +/* Private Functions ---------------------------------------------------------*/ +/** @defgroup SMBUS_Private_Functions SMBUS Private Functions + * @{ + */ +/* Private functions are defined in stm32wbaxx_hal_smbus.c file */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32WBAxx_HAL_SMBUS_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_smbus_ex.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_smbus_ex.h new file mode 100644 index 0000000000..bf8ff2b2cb --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_smbus_ex.h @@ -0,0 +1,334 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_smbus_ex.h + * @author MCD Application Team + * @brief Header file of SMBUS HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_HAL_SMBUS_EX_H +#define STM32WBAxx_HAL_SMBUS_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal_def.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @addtogroup SMBUSEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup SMBUS_Exported_Types SMBUS Exported Types + * @{ + */ + +/** @defgroup SMBUS_Autonomous_Mode_Configuration_Structure_definition Autonomous Mode Configuration + Structure definition. + * @brief SMBUS Autonomous Mode Configuration structure definition + * @{ + */ +typedef struct +{ + uint32_t TriggerState; /*!< Specifies the trigger state. This parameter can be a value + of @ref SMBUSEx_AutonomousMode_FunctionalState */ + + uint32_t TriggerSelection; /*!< Specifies the autonomous mode trigger signal selection. This parameter + can be a value of @ref SMBUSEx_AutonomousMode_TriggerSelection */ + + uint32_t TriggerPolarity; /*!< Specifies the autonomous mode trigger signal polarity sensitivity. This parameter + can be a value of @ref SMBUSEx_AutonomousMode_TriggerPolarity */ + +} SMBUS_AutonomousModeConfTypeDef; +/** + * @} + */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SMBUSEx_Exported_Constants SMBUS Extended Exported Constants + * @{ + */ + +/** @defgroup SMBUSEx_FastModePlus SMBUS Extended Fast Mode Plus + * @{ + */ +#define SMBUS_FASTMODEPLUS_ENABLE 0x00000000U /*!< Enable Fast Mode Plus */ +#define SMBUS_FASTMODEPLUS_DISABLE 0x00000001U /*!< Disable Fast Mode Plus */ +/** + * @} + */ + +/** @defgroup SMBUSEx_AutonomousMode_FunctionalState SMBUS Extended Autonomous Mode State + * @{ + */ +#define SMBUS_AUTO_MODE_DISABLE (0x00000000U) /* Autonomous mode disable */ +#define SMBUS_AUTO_MODE_ENABLE I2C_AUTOCR_TRIGEN /* Autonomous mode enable */ +/** + * @} + */ + +/** @defgroup SMBUSEx_AutonomousMode_TriggerSelection SMBUS Extended Autonomous Mode Trigger Selection + * @{ + */ +#if defined(I2C1) +#define SMBUS_TRIG_GRP1 (0x10000000U) /*!< Trigger Group for I2C1 */ +#endif /* I2C1 */ +#define SMBUS_TRIG_GRP2 (0x20000000U) /*!< Trigger Group for I2C3 */ + +#if defined(SMBUS_TRIG_GRP1) +#define SMBUS_GRP1_GPDMA_CH0_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x00000000U)) +/*!< HW Trigger signal is GPDMA_CH0_TRG */ +#define SMBUS_GRP1_GPDMA_CH1_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x1U << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is GPDMA_CH1_TRG */ +#define SMBUS_GRP1_GPDMA_CH2_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x2U << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is GPDMA_CH2_TRG */ +#define SMBUS_GRP1_GPDMA_CH3_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x3U << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is GPDMA_CH3_TRG */ +#define SMBUS_GRP1_EXTI5_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x4U << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is EXTI5_TRG */ +#define SMBUS_GRP1_EXTI9_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x5U << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is EXTI9_TRG */ +#define SMBUS_GRP1_LPTIM1_CH1_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x6U << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is LPTIM1_CH1_TRG */ +#define SMBUS_GRP1_LPTIM2_CH1_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x7U << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is LPTIM2_CH1_TRG */ +#if defined(COMP1) +#define SMBUS_GRP1_COMP1_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x8U << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is COMP1_TRG */ +#endif /* COMP1 */ +#if defined(COMP2) +#define SMBUS_GRP1_COMP2_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0x9U << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is COMP2_TRG */ +#endif /* COMP2 */ +#define SMBUS_GRP1_RTC_ALRA_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0xAU << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is RTC_ALRA_TRG */ +#define SMBUS_GRP1_RTC_WUT_TRG (uint32_t)(SMBUS_TRIG_GRP1 | (0xBU << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is RTC_WUT_TRG */ +#endif /* SMBUS_TRIG_GRP1 */ + +#define SMBUS_GRP2_GPDMA_CH0_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x00000000U)) +/*!< HW Trigger signal is GPDMA_CH0_TRG */ +#define SMBUS_GRP2_GPDMA_CH1_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x1U << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is GPDMA_CH1_TRG */ +#define SMBUS_GRP2_GPDMA_CH2_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x2U << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is GPDMA_CH2_TRG */ +#define SMBUS_GRP2_GPDMA_CH3_TCF_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x3U << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is GPDMA_CH3_TRG */ +#define SMBUS_GRP2_EXTI5_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x4U << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is EXTI5_TRG */ +#define SMBUS_GRP2_EXTI8_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x5U << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is EXTI8_TRG */ +#define SMBUS_GRP2_LPTIM1_CH1_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x6U << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is LPTIM1_CH1_TRG */ +#if defined(COMP1) +#define SMBUS_GRP2_COMP1_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x8U << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is COMP1_TRG */ +#endif /* COMP1 */ +#if defined(COMP2) +#define SMBUS_GRP2_COMP2_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0x9U << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is COMP2_TRG */ +#endif /* COMP2 */ +#define SMBUS_GRP2_RTC_ALRA_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0xAU << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is RTC_ALRA_TRG */ +#define SMBUS_GRP2_RTC_WUT_TRG (uint32_t)(SMBUS_TRIG_GRP2 | (0xBU << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is RTC_WUT_TRG */ +/** + * @} + */ + +/** @defgroup SMBUSEx_AutonomousMode_TriggerPolarity Extended Autonomous Mode Trigger Polarity + * @{ + */ +#define SMBUS_TRIG_POLARITY_RISING (0x00000000U) /* SMBUS HW Trigger signal on rising edge */ +#define SMBUS_TRIG_POLARITY_FALLING I2C_AUTOCR_TRIGPOL /* SMBUS HW Trigger signal on falling edge */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup SMBUSEx_Exported_Macros SMBUS Extended Exported Macros + * @{ + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SMBUSEx_Exported_Functions SMBUS Extended Exported Functions + * @{ + */ + +/** @addtogroup SMBUSEx_Exported_Functions_Group2 WakeUp Mode Functions + * @{ + */ +/* Peripheral Control functions ************************************************/ +HAL_StatusTypeDef HAL_SMBUSEx_EnableWakeUp(SMBUS_HandleTypeDef *hsmbus); +HAL_StatusTypeDef HAL_SMBUSEx_DisableWakeUp(SMBUS_HandleTypeDef *hsmbus); +/** + * @} + */ + +/** @addtogroup SMBUSEx_Exported_Functions_Group3 Fast Mode Plus Functions + * @{ + */ +HAL_StatusTypeDef HAL_SMBUSEx_ConfigFastModePlus(SMBUS_HandleTypeDef *hsmbus, uint32_t FastModePlus); +/** + * @} + */ + +/** @addtogroup SMBUSEx_Exported_Functions_Group4 Autonomous Mode Functions + * @{ + */ +HAL_StatusTypeDef HAL_SMBUSEx_SetConfigAutonomousMode(SMBUS_HandleTypeDef *hsmbus, + const SMBUS_AutonomousModeConfTypeDef *sConfig); +HAL_StatusTypeDef HAL_SMBUSEx_GetConfigAutonomousMode(const SMBUS_HandleTypeDef *hsmbus, + SMBUS_AutonomousModeConfTypeDef *sConfig); +HAL_StatusTypeDef HAL_SMBUSEx_ClearConfigAutonomousMode(SMBUS_HandleTypeDef *hsmbus); +/** + * @} + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup SMBUSEx_Private_Constants SMBUS Extended Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup SMBUSEx_Private_Macro SMBUS Extended Private Macros + * @{ + */ +#define IS_SMBUS_FASTMODEPLUS(__CONFIG__) (((__CONFIG__) == (SMBUS_FASTMODEPLUS_ENABLE)) || \ + ((__CONFIG__) == (SMBUS_FASTMODEPLUS_DISABLE))) + +#define IS_SMBUS_AUTO_MODE(__MODE__) (((__MODE__) == SMBUS_AUTO_MODE_DISABLE) || \ + ((__MODE__) == SMBUS_AUTO_MODE_ENABLE)) + +#if defined(SMBUS_TRIG_GRP1) +#define IS_SMBUS_TRIG_SOURCE(__INSTANCE__, __SOURCE__) (((__INSTANCE__) == I2C3) ? \ + IS_SMBUS_GRP2_TRIG_SOURCE(__SOURCE__) : \ + IS_SMBUS_GRP1_TRIG_SOURCE(__SOURCE__)) +#else +#define IS_SMBUS_TRIG_SOURCE(__INSTANCE__, __SOURCE__) (IS_SMBUS_GRP2_TRIG_SOURCE(__SOURCE__)) +#endif /* SMBUS_TRIG_GRP1 */ + +#if defined(COMP1) && defined(COMP2) +#if defined(SMBUS_TRIG_GRP1) +#define IS_SMBUS_GRP1_TRIG_SOURCE(__SOURCE__) (((__SOURCE__) == SMBUS_GRP1_GPDMA_CH0_TCF_TRG ) || \ + ((__SOURCE__) == SMBUS_GRP1_GPDMA_CH1_TCF_TRG ) || \ + ((__SOURCE__) == SMBUS_GRP1_GPDMA_CH2_TCF_TRG ) || \ + ((__SOURCE__) == SMBUS_GRP1_GPDMA_CH3_TCF_TRG ) || \ + ((__SOURCE__) == SMBUS_GRP1_EXTI5_TRG ) || \ + ((__SOURCE__) == SMBUS_GRP1_EXTI9_TRG ) || \ + ((__SOURCE__) == SMBUS_GRP1_LPTIM1_CH1_TRG ) || \ + ((__SOURCE__) == SMBUS_GRP1_LPTIM2_CH1_TRG ) || \ + ((__SOURCE__) == SMBUS_GRP1_COMP1_TRG ) || \ + ((__SOURCE__) == SMBUS_GRP1_COMP2_TRG ) || \ + ((__SOURCE__) == SMBUS_GRP1_RTC_ALRA_TRG ) || \ + ((__SOURCE__) == SMBUS_GRP1_RTC_WUT_TRG )) +#endif /* SMBUS_TRIG_GRP1 */ + +#define IS_SMBUS_GRP2_TRIG_SOURCE(__SOURCE__) (((__SOURCE__) == SMBUS_GRP2_GPDMA_CH0_TCF_TRG ) || \ + ((__SOURCE__) == SMBUS_GRP2_GPDMA_CH1_TCF_TRG ) || \ + ((__SOURCE__) == SMBUS_GRP2_GPDMA_CH2_TCF_TRG ) || \ + ((__SOURCE__) == SMBUS_GRP2_GPDMA_CH3_TCF_TRG ) || \ + ((__SOURCE__) == SMBUS_GRP2_EXTI5_TRG ) || \ + ((__SOURCE__) == SMBUS_GRP2_EXTI8_TRG ) || \ + ((__SOURCE__) == SMBUS_GRP2_LPTIM1_CH1_TRG ) || \ + ((__SOURCE__) == SMBUS_GRP2_COMP1_TRG ) || \ + ((__SOURCE__) == SMBUS_GRP2_COMP2_TRG ) || \ + ((__SOURCE__) == SMBUS_GRP2_RTC_ALRA_TRG ) || \ + ((__SOURCE__) == SMBUS_GRP2_RTC_WUT_TRG )) + +#else + +#define IS_SMBUS_GRP1_TRIG_SOURCE(__SOURCE__) (((__SOURCE__) == SMBUS_GRP1_GPDMA_CH0_TCF_TRG ) || \ + ((__SOURCE__) == SMBUS_GRP1_GPDMA_CH1_TCF_TRG ) || \ + ((__SOURCE__) == SMBUS_GRP1_GPDMA_CH2_TCF_TRG ) || \ + ((__SOURCE__) == SMBUS_GRP1_GPDMA_CH3_TCF_TRG ) || \ + ((__SOURCE__) == SMBUS_GRP1_EXTI5_TRG ) || \ + ((__SOURCE__) == SMBUS_GRP1_EXTI9_TRG ) || \ + ((__SOURCE__) == SMBUS_GRP1_LPTIM1_CH1_TRG ) || \ + ((__SOURCE__) == SMBUS_GRP1_LPTIM2_CH1_TRG ) || \ + ((__SOURCE__) == SMBUS_GRP1_RTC_ALRA_TRG ) || \ + ((__SOURCE__) == SMBUS_GRP1_RTC_WUT_TRG )) + +#define IS_SMBUS_GRP2_TRIG_SOURCE(__SOURCE__) (((__SOURCE__) == SMBUS_GRP2_GPDMA_CH0_TCF_TRG ) || \ + ((__SOURCE__) == SMBUS_GRP2_GPDMA_CH1_TCF_TRG ) || \ + ((__SOURCE__) == SMBUS_GRP2_GPDMA_CH2_TCF_TRG ) || \ + ((__SOURCE__) == SMBUS_GRP2_GPDMA_CH3_TCF_TRG ) || \ + ((__SOURCE__) == SMBUS_GRP2_EXTI5_TRG ) || \ + ((__SOURCE__) == SMBUS_GRP2_EXTI8_TRG ) || \ + ((__SOURCE__) == SMBUS_GRP2_LPTIM1_CH1_TRG ) || \ + ((__SOURCE__) == SMBUS_GRP2_RTC_ALRA_TRG ) || \ + ((__SOURCE__) == SMBUS_GRP2_RTC_WUT_TRG )) +#endif /* COMP1 && COMP2 */ + +#if defined(SMBUS_TRIG_GRP1) +#define IS_SMBUS_TRIG_INPUT_INSTANCE(__INSTANCE__) (IS_SMBUS_GRP1_INSTANCE(__INSTANCE__) || \ + IS_SMBUS_GRP2_INSTANCE(__INSTANCE__)) +#else +#define IS_SMBUS_TRIG_INPUT_INSTANCE(__INSTANCE__) IS_SMBUS_GRP1_INSTANCE(__INSTANCE__) +#endif /* SMBUS_TRIG_GRP1 */ + +#define IS_SMBUS_AUTO_MODE_TRG_POL(__POLARITY__) (((__POLARITY__) == SMBUS_TRIG_POLARITY_RISING) || \ + ((__POLARITY__) == SMBUS_TRIG_POLARITY_FALLING)) +/** + * @} + */ + +/* Private Functions ---------------------------------------------------------*/ +/** @defgroup SMBUSEx_Private_Functions SMBUS Extended Private Functions + * @{ + */ +/* Private functions are defined in stm32wbaxx_hal_smbus_ex.c file */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WBAxx_HAL_SMBUS_EX_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_spi.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_spi.h new file mode 100644 index 0000000000..4b6d5666d2 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_spi.h @@ -0,0 +1,1128 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_spi.h + * @author MCD Application Team + * @brief Header file of SPI HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_HAL_SPI_H +#define STM32WBAxx_HAL_SPI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal_def.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @addtogroup SPI + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup SPI_Exported_Types SPI Exported Types + * @{ + */ + +/** + * @brief SPI Configuration Structure definition + */ +typedef struct +{ + uint32_t Mode; /*!< Specifies the SPI operating mode. + This parameter can be a value of @ref SPI_Mode */ + + uint32_t Direction; /*!< Specifies the SPI bidirectional mode state. + This parameter can be a value of @ref SPI_Direction */ + + uint32_t DataSize; /*!< Specifies the SPI data size. + This parameter can be a value of @ref SPI_Data_Size */ + + uint32_t CLKPolarity; /*!< Specifies the serial clock steady state. + This parameter can be a value of @ref SPI_Clock_Polarity */ + + uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture. + This parameter can be a value of @ref SPI_Clock_Phase */ + + uint32_t NSS; /*!< Specifies whether the NSS signal is managed by + hardware (NSS pin) or by software using the SSI bit. + This parameter can be a value of + @ref SPI_Slave_Select_Management */ + + uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be + used to configure the transmit and receive SCK clock. + This parameter can be a value of @ref SPI_BaudRate_Prescaler + @note The communication clock is derived from the master + clock. The slave clock does not need to be set. */ + + uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. + This parameter can be a value of @ref SPI_MSB_LSB_Transmission */ + + uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not. + This parameter can be a value of @ref SPI_TI_Mode */ + + uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. + This parameter can be a value of @ref SPI_CRC_Calculation */ + + uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. + This parameter must be an odd number between + Min_Data = 0 and Max_Data = 65535 */ + + uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation. + This parameter can be a value of @ref SPI_CRC_length */ + + uint32_t NSSPMode; /*!< Specifies whether the NSSP signal is enabled or not . + This parameter can be a value of @ref SPI_NSSP_Mode + This mode is activated by the SSOM bit in the SPIx_CR2 register + and it takes effect only if the SPI interface is configured + as Motorola SPI master (FRF=0). */ + + uint32_t NSSPolarity; /*!< Specifies which level of SS input/output external signal + (present on SS pin) is considered as active one. + This parameter can be a value of @ref SPI_NSS_Polarity */ + + uint32_t FifoThreshold; /*!< Specifies the FIFO threshold level. + This parameter can be a value of @ref SPI_Fifo_Threshold */ + + uint32_t TxCRCInitializationPattern; /*!< Specifies the transmitter CRC initialization Pattern used for + the CRC calculation. This parameter can be a value of + @ref SPI_CRC_Calculation_Initialization_Pattern */ + + uint32_t RxCRCInitializationPattern; /*!< Specifies the receiver CRC initialization Pattern used for + the CRC calculation. This parameter can be a value of + @ref SPI_CRC_Calculation_Initialization_Pattern */ + + uint32_t MasterSSIdleness; /*!< Specifies an extra delay, expressed in number of SPI clock cycle + periods, inserted additionally between active edge of SS + and first data transaction start in master mode. + This parameter can be a value of @ref SPI_Master_SS_Idleness */ + + uint32_t MasterInterDataIdleness; /*!< Specifies minimum time delay (expressed in SPI clock cycles periods) + inserted between two consecutive data frames in master mode. + This parameter can be a value of + @ref SPI_Master_InterData_Idleness */ + + uint32_t MasterReceiverAutoSusp; /*!< Control continuous SPI transfer in master receiver mode + and automatic management in order to avoid overrun condition. + This parameter can be a value of @ref SPI_Master_RX_AutoSuspend*/ + + uint32_t MasterKeepIOState; /*!< Control of Alternate function GPIOs state + This parameter can be a value of @ref SPI_Master_Keep_IO_State */ + + uint32_t IOSwap; /*!< Invert MISO/MOSI alternate functions + This parameter can be a value of @ref SPI_IO_Swap */ + + uint32_t ReadyMasterManagement; /*!< Specifies if RDY Signal is managed internally or not. + This parameter can be a value of @ref SPI_RDY_Master_Management */ + + uint32_t ReadyPolarity; /*!< Specifies which level of RDY Signal input (present on RDY pin) + is considered as active one. + This parameter can be a value of @ref SPI_RDY_Polarity */ +} SPI_InitTypeDef; + +/** + * @brief HAL SPI State structure definition + */ +typedef enum +{ + HAL_SPI_STATE_RESET = 0x00UL, /*!< Peripheral not Initialized */ + HAL_SPI_STATE_READY = 0x01UL, /*!< Peripheral Initialized and ready for use */ + HAL_SPI_STATE_BUSY = 0x02UL, /*!< an internal process is ongoing */ + HAL_SPI_STATE_BUSY_TX = 0x03UL, /*!< Data Transmission process is ongoing */ + HAL_SPI_STATE_BUSY_RX = 0x04UL, /*!< Data Reception process is ongoing */ + HAL_SPI_STATE_BUSY_TX_RX = 0x05UL, /*!< Data Transmission and Reception process is ongoing */ + HAL_SPI_STATE_ERROR = 0x06UL, /*!< SPI error state */ + HAL_SPI_STATE_ABORT = 0x07UL /*!< SPI abort is ongoing */ +} HAL_SPI_StateTypeDef; + + +/** + * @brief SPI handle Structure definition + */ +typedef struct __SPI_HandleTypeDef +{ + SPI_TypeDef *Instance; /*!< SPI registers base address */ + + SPI_InitTypeDef Init; /*!< SPI communication parameters */ + + const uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ + + uint16_t TxXferSize; /*!< SPI Tx Transfer size */ + + __IO uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */ + + uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */ + + uint16_t RxXferSize; /*!< SPI Rx Transfer size */ + + __IO uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */ + + uint32_t CRCSize; /*!< SPI CRC size used for the transfer */ + + void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx ISR */ + + void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx ISR */ + + DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA Handle parameters */ + + HAL_LockTypeDef Lock; /*!< Locking object */ + + __IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */ + + __IO uint32_t ErrorCode; /*!< SPI Error code */ + + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + void (* TxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Completed callback */ + void (* RxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Completed callback */ + void (* TxRxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Completed callback */ + void (* TxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Half Completed callback */ + void (* RxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Half Completed callback */ + void (* TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Half Completed callback */ + void (* ErrorCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Error callback */ + void (* AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Abort callback */ + void (* SuspendCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Suspend callback */ + void (* MspInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp Init callback */ + void (* MspDeInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp DeInit callback */ + +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} SPI_HandleTypeDef; + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) +/** + * @brief HAL SPI Callback ID enumeration definition + */ +typedef enum +{ + HAL_SPI_TX_COMPLETE_CB_ID = 0x00UL, /*!< SPI Tx Completed callback ID */ + HAL_SPI_RX_COMPLETE_CB_ID = 0x01UL, /*!< SPI Rx Completed callback ID */ + HAL_SPI_TX_RX_COMPLETE_CB_ID = 0x02UL, /*!< SPI TxRx Completed callback ID */ + HAL_SPI_TX_HALF_COMPLETE_CB_ID = 0x03UL, /*!< SPI Tx Half Completed callback ID */ + HAL_SPI_RX_HALF_COMPLETE_CB_ID = 0x04UL, /*!< SPI Rx Half Completed callback ID */ + HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID = 0x05UL, /*!< SPI TxRx Half Completed callback ID */ + HAL_SPI_ERROR_CB_ID = 0x06UL, /*!< SPI Error callback ID */ + HAL_SPI_ABORT_CB_ID = 0x07UL, /*!< SPI Abort callback ID */ + HAL_SPI_SUSPEND_CB_ID = 0x08UL, /*!< SPI Suspend callback ID */ + HAL_SPI_MSPINIT_CB_ID = 0x09UL, /*!< SPI Msp Init callback ID */ + HAL_SPI_MSPDEINIT_CB_ID = 0x0AUL /*!< SPI Msp DeInit callback ID */ + +} HAL_SPI_CallbackIDTypeDef; + +/** + * @brief HAL SPI Callback pointer definition + */ +typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to an SPI callback function */ + +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup SPI_Exported_Constants SPI Exported Constants + * @{ + */ + +/** @defgroup SPI_FIFO_Type SPI FIFO Type + * @{ + */ +#define SPI_LOWEND_FIFO_SIZE 8UL +#define SPI_HIGHEND_FIFO_SIZE 16UL +/** + * @} + */ + +/** @defgroup SPI_Error_Code SPI Error Codes + * @{ + */ +#define HAL_SPI_ERROR_NONE (0x00000000UL) /*!< No error */ +#define HAL_SPI_ERROR_MODF (0x00000001UL) /*!< MODF error */ +#define HAL_SPI_ERROR_CRC (0x00000002UL) /*!< CRC error */ +#define HAL_SPI_ERROR_OVR (0x00000004UL) /*!< OVR error */ +#define HAL_SPI_ERROR_FRE (0x00000008UL) /*!< FRE error */ +#define HAL_SPI_ERROR_DMA (0x00000010UL) /*!< DMA transfer error */ +#define HAL_SPI_ERROR_FLAG (0x00000020UL) /*!< Error on RXP/TXP/DXP/FTLVL/FRLVL Flag */ +#define HAL_SPI_ERROR_ABORT (0x00000040UL) /*!< Error during SPI Abort procedure */ +#define HAL_SPI_ERROR_UDR (0x00000080UL) /*!< Underrun error */ +#define HAL_SPI_ERROR_TIMEOUT (0x00000100UL) /*!< Timeout error */ +#define HAL_SPI_ERROR_UNKNOW (0x00000200UL) /*!< Unknown error */ +#define HAL_SPI_ERROR_NOT_SUPPORTED (0x00000400UL) /*!< Requested operation not supported */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) +#define HAL_SPI_ERROR_INVALID_CALLBACK (0x00001000UL) /*!< Invalid Callback error */ +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup SPI_Mode SPI Mode + * @{ + */ +#define SPI_MODE_SLAVE (0x00000000UL) +#define SPI_MODE_MASTER SPI_CFG2_MASTER +/** + * @} + */ + +/** @defgroup SPI_Direction SPI Direction Mode + * @{ + */ +#define SPI_DIRECTION_2LINES (0x00000000UL) +#define SPI_DIRECTION_2LINES_TXONLY SPI_CFG2_COMM_0 +#define SPI_DIRECTION_2LINES_RXONLY SPI_CFG2_COMM_1 +#define SPI_DIRECTION_1LINE SPI_CFG2_COMM +/** + * @} + */ + +/** @defgroup SPI_Data_Size SPI Data Size + * @{ + */ +#define SPI_DATASIZE_4BIT (0x00000003UL) +#define SPI_DATASIZE_5BIT (0x00000004UL) +#define SPI_DATASIZE_6BIT (0x00000005UL) +#define SPI_DATASIZE_7BIT (0x00000006UL) +#define SPI_DATASIZE_8BIT (0x00000007UL) +#define SPI_DATASIZE_9BIT (0x00000008UL) +#define SPI_DATASIZE_10BIT (0x00000009UL) +#define SPI_DATASIZE_11BIT (0x0000000AUL) +#define SPI_DATASIZE_12BIT (0x0000000BUL) +#define SPI_DATASIZE_13BIT (0x0000000CUL) +#define SPI_DATASIZE_14BIT (0x0000000DUL) +#define SPI_DATASIZE_15BIT (0x0000000EUL) +#define SPI_DATASIZE_16BIT (0x0000000FUL) +#define SPI_DATASIZE_17BIT (0x00000010UL) +#define SPI_DATASIZE_18BIT (0x00000011UL) +#define SPI_DATASIZE_19BIT (0x00000012UL) +#define SPI_DATASIZE_20BIT (0x00000013UL) +#define SPI_DATASIZE_21BIT (0x00000014UL) +#define SPI_DATASIZE_22BIT (0x00000015UL) +#define SPI_DATASIZE_23BIT (0x00000016UL) +#define SPI_DATASIZE_24BIT (0x00000017UL) +#define SPI_DATASIZE_25BIT (0x00000018UL) +#define SPI_DATASIZE_26BIT (0x00000019UL) +#define SPI_DATASIZE_27BIT (0x0000001AUL) +#define SPI_DATASIZE_28BIT (0x0000001BUL) +#define SPI_DATASIZE_29BIT (0x0000001CUL) +#define SPI_DATASIZE_30BIT (0x0000001DUL) +#define SPI_DATASIZE_31BIT (0x0000001EUL) +#define SPI_DATASIZE_32BIT (0x0000001FUL) +/** + * @} + */ + +/** @defgroup SPI_Clock_Polarity SPI Clock Polarity + * @{ + */ +#define SPI_POLARITY_LOW (0x00000000UL) +#define SPI_POLARITY_HIGH SPI_CFG2_CPOL +/** + * @} + */ + +/** @defgroup SPI_Clock_Phase SPI Clock Phase + * @{ + */ +#define SPI_PHASE_1EDGE (0x00000000UL) +#define SPI_PHASE_2EDGE SPI_CFG2_CPHA +/** + * @} + */ + +/** @defgroup SPI_Slave_Select_Management SPI Slave Select Management + * @{ + */ +#define SPI_NSS_SOFT SPI_CFG2_SSM +#define SPI_NSS_HARD_INPUT (0x00000000UL) +#define SPI_NSS_HARD_OUTPUT SPI_CFG2_SSOE +/** + * @} + */ + +/** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode + * @{ + */ +#define SPI_NSS_PULSE_DISABLE (0x00000000UL) +#define SPI_NSS_PULSE_ENABLE SPI_CFG2_SSOM +/** + * @} + */ + +/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler + * @{ + */ +#define SPI_BAUDRATEPRESCALER_BYPASS (0x80000000UL) +#define SPI_BAUDRATEPRESCALER_2 (0x00000000UL) +#define SPI_BAUDRATEPRESCALER_4 (0x10000000UL) +#define SPI_BAUDRATEPRESCALER_8 (0x20000000UL) +#define SPI_BAUDRATEPRESCALER_16 (0x30000000UL) +#define SPI_BAUDRATEPRESCALER_32 (0x40000000UL) +#define SPI_BAUDRATEPRESCALER_64 (0x50000000UL) +#define SPI_BAUDRATEPRESCALER_128 (0x60000000UL) +#define SPI_BAUDRATEPRESCALER_256 (0x70000000UL) +/** + * @} + */ + +/** @defgroup SPI_MSB_LSB_Transmission SPI MSB LSB Transmission + * @{ + */ +#define SPI_FIRSTBIT_MSB (0x00000000UL) +#define SPI_FIRSTBIT_LSB SPI_CFG2_LSBFRST +/** + * @} + */ + +/** @defgroup SPI_TI_Mode SPI TI Mode + * @{ + */ +#define SPI_TIMODE_DISABLE (0x00000000UL) +#define SPI_TIMODE_ENABLE SPI_CFG2_SP_0 +/** + * @} + */ + +/** @defgroup SPI_CRC_Calculation SPI CRC Calculation + * @{ + */ +#define SPI_CRCCALCULATION_DISABLE (0x00000000UL) +#define SPI_CRCCALCULATION_ENABLE SPI_CFG1_CRCEN +/** + * @} + */ + +/** @defgroup SPI_CRC_length SPI CRC Length + * @{ + */ +#define SPI_CRC_LENGTH_DATASIZE (0x00000000UL) +#define SPI_CRC_LENGTH_4BIT (0x00030000UL) +#define SPI_CRC_LENGTH_5BIT (0x00040000UL) +#define SPI_CRC_LENGTH_6BIT (0x00050000UL) +#define SPI_CRC_LENGTH_7BIT (0x00060000UL) +#define SPI_CRC_LENGTH_8BIT (0x00070000UL) +#define SPI_CRC_LENGTH_9BIT (0x00080000UL) +#define SPI_CRC_LENGTH_10BIT (0x00090000UL) +#define SPI_CRC_LENGTH_11BIT (0x000A0000UL) +#define SPI_CRC_LENGTH_12BIT (0x000B0000UL) +#define SPI_CRC_LENGTH_13BIT (0x000C0000UL) +#define SPI_CRC_LENGTH_14BIT (0x000D0000UL) +#define SPI_CRC_LENGTH_15BIT (0x000E0000UL) +#define SPI_CRC_LENGTH_16BIT (0x000F0000UL) +#define SPI_CRC_LENGTH_17BIT (0x00100000UL) +#define SPI_CRC_LENGTH_18BIT (0x00110000UL) +#define SPI_CRC_LENGTH_19BIT (0x00120000UL) +#define SPI_CRC_LENGTH_20BIT (0x00130000UL) +#define SPI_CRC_LENGTH_21BIT (0x00140000UL) +#define SPI_CRC_LENGTH_22BIT (0x00150000UL) +#define SPI_CRC_LENGTH_23BIT (0x00160000UL) +#define SPI_CRC_LENGTH_24BIT (0x00170000UL) +#define SPI_CRC_LENGTH_25BIT (0x00180000UL) +#define SPI_CRC_LENGTH_26BIT (0x00190000UL) +#define SPI_CRC_LENGTH_27BIT (0x001A0000UL) +#define SPI_CRC_LENGTH_28BIT (0x001B0000UL) +#define SPI_CRC_LENGTH_29BIT (0x001C0000UL) +#define SPI_CRC_LENGTH_30BIT (0x001D0000UL) +#define SPI_CRC_LENGTH_31BIT (0x001E0000UL) +#define SPI_CRC_LENGTH_32BIT (0x001F0000UL) +/** + * @} + */ + +/** @defgroup SPI_Fifo_Threshold SPI Fifo Threshold + * @{ + */ +#define SPI_FIFO_THRESHOLD_01DATA (0x00000000UL) +#define SPI_FIFO_THRESHOLD_02DATA (0x00000020UL) +#define SPI_FIFO_THRESHOLD_03DATA (0x00000040UL) +#define SPI_FIFO_THRESHOLD_04DATA (0x00000060UL) +#define SPI_FIFO_THRESHOLD_05DATA (0x00000080UL) +#define SPI_FIFO_THRESHOLD_06DATA (0x000000A0UL) +#define SPI_FIFO_THRESHOLD_07DATA (0x000000C0UL) +#define SPI_FIFO_THRESHOLD_08DATA (0x000000E0UL) +#define SPI_FIFO_THRESHOLD_09DATA (0x00000100UL) +#define SPI_FIFO_THRESHOLD_10DATA (0x00000120UL) +#define SPI_FIFO_THRESHOLD_11DATA (0x00000140UL) +#define SPI_FIFO_THRESHOLD_12DATA (0x00000160UL) +#define SPI_FIFO_THRESHOLD_13DATA (0x00000180UL) +#define SPI_FIFO_THRESHOLD_14DATA (0x000001A0UL) +#define SPI_FIFO_THRESHOLD_15DATA (0x000001C0UL) +#define SPI_FIFO_THRESHOLD_16DATA (0x000001E0UL) +/** + * @} + */ + +/** @defgroup SPI_CRC_Calculation_Initialization_Pattern SPI CRC Calculation Initialization Pattern + * @{ + */ +#define SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN (0x00000000UL) +#define SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN (0x00000001UL) +/** + * @} + */ + +/** @defgroup SPI_NSS_Polarity SPI NSS Polarity + * @{ + */ +#define SPI_NSS_POLARITY_LOW (0x00000000UL) +#define SPI_NSS_POLARITY_HIGH SPI_CFG2_SSIOP +/** + * @} + */ + +/** @defgroup SPI_Master_Keep_IO_State Keep IO State + * @{ + */ +#define SPI_MASTER_KEEP_IO_STATE_DISABLE (0x00000000UL) +#define SPI_MASTER_KEEP_IO_STATE_ENABLE SPI_CFG2_AFCNTR +/** + * @} + */ + +/** @defgroup SPI_IO_Swap Control SPI IO Swap + * @{ + */ +#define SPI_IO_SWAP_DISABLE (0x00000000UL) +#define SPI_IO_SWAP_ENABLE SPI_CFG2_IOSWP +/** + * @} + */ + +/** @defgroup SPI_Master_SS_Idleness SPI Master SS Idleness + * @{ + */ +#define SPI_MASTER_SS_IDLENESS_00CYCLE (0x00000000UL) +#define SPI_MASTER_SS_IDLENESS_01CYCLE (0x00000001UL) +#define SPI_MASTER_SS_IDLENESS_02CYCLE (0x00000002UL) +#define SPI_MASTER_SS_IDLENESS_03CYCLE (0x00000003UL) +#define SPI_MASTER_SS_IDLENESS_04CYCLE (0x00000004UL) +#define SPI_MASTER_SS_IDLENESS_05CYCLE (0x00000005UL) +#define SPI_MASTER_SS_IDLENESS_06CYCLE (0x00000006UL) +#define SPI_MASTER_SS_IDLENESS_07CYCLE (0x00000007UL) +#define SPI_MASTER_SS_IDLENESS_08CYCLE (0x00000008UL) +#define SPI_MASTER_SS_IDLENESS_09CYCLE (0x00000009UL) +#define SPI_MASTER_SS_IDLENESS_10CYCLE (0x0000000AUL) +#define SPI_MASTER_SS_IDLENESS_11CYCLE (0x0000000BUL) +#define SPI_MASTER_SS_IDLENESS_12CYCLE (0x0000000CUL) +#define SPI_MASTER_SS_IDLENESS_13CYCLE (0x0000000DUL) +#define SPI_MASTER_SS_IDLENESS_14CYCLE (0x0000000EUL) +#define SPI_MASTER_SS_IDLENESS_15CYCLE (0x0000000FUL) +/** + * @} + */ + +/** @defgroup SPI_Master_InterData_Idleness SPI Master Inter-Data Idleness + * @{ + */ +#define SPI_MASTER_INTERDATA_IDLENESS_00CYCLE (0x00000000UL) +#define SPI_MASTER_INTERDATA_IDLENESS_01CYCLE (0x00000010UL) +#define SPI_MASTER_INTERDATA_IDLENESS_02CYCLE (0x00000020UL) +#define SPI_MASTER_INTERDATA_IDLENESS_03CYCLE (0x00000030UL) +#define SPI_MASTER_INTERDATA_IDLENESS_04CYCLE (0x00000040UL) +#define SPI_MASTER_INTERDATA_IDLENESS_05CYCLE (0x00000050UL) +#define SPI_MASTER_INTERDATA_IDLENESS_06CYCLE (0x00000060UL) +#define SPI_MASTER_INTERDATA_IDLENESS_07CYCLE (0x00000070UL) +#define SPI_MASTER_INTERDATA_IDLENESS_08CYCLE (0x00000080UL) +#define SPI_MASTER_INTERDATA_IDLENESS_09CYCLE (0x00000090UL) +#define SPI_MASTER_INTERDATA_IDLENESS_10CYCLE (0x000000A0UL) +#define SPI_MASTER_INTERDATA_IDLENESS_11CYCLE (0x000000B0UL) +#define SPI_MASTER_INTERDATA_IDLENESS_12CYCLE (0x000000C0UL) +#define SPI_MASTER_INTERDATA_IDLENESS_13CYCLE (0x000000D0UL) +#define SPI_MASTER_INTERDATA_IDLENESS_14CYCLE (0x000000E0UL) +#define SPI_MASTER_INTERDATA_IDLENESS_15CYCLE (0x000000F0UL) +/** + * @} + */ + +/** @defgroup SPI_Master_RX_AutoSuspend SPI Master Receiver AutoSuspend + * @{ + */ +#define SPI_MASTER_RX_AUTOSUSP_DISABLE (0x00000000UL) +#define SPI_MASTER_RX_AUTOSUSP_ENABLE SPI_CR1_MASRX +/** + * @} + */ + +/** @defgroup SPI_Underrun_Behaviour SPI Underrun Behavior + * @{ + */ +#define SPI_UNDERRUN_BEHAV_REGISTER_PATTERN (0x00000000UL) +#define SPI_UNDERRUN_BEHAV_LAST_RECEIVED SPI_CFG1_UDRCFG +/** + * @} + */ + +/** @defgroup SPI_RDY_Master_Management SPI RDY Signal Input Master Management + * @{ + */ +#define SPI_RDY_MASTER_MANAGEMENT_INTERNALLY (0x00000000UL) +#define SPI_RDY_MASTER_MANAGEMENT_EXTERNALLY SPI_CFG2_RDIMM +/** + * @} + */ + +/** @defgroup SPI_RDY_Polarity SPI RDY Signal Input/Output Polarity + * @{ + */ +#define SPI_RDY_POLARITY_HIGH (0x00000000UL) +#define SPI_RDY_POLARITY_LOW SPI_CFG2_RDIOP +/** + * @} + */ + +/** @defgroup SPI_Interrupt_definition SPI Interrupt Definition + * @{ + */ +#define SPI_IT_RXP SPI_IER_RXPIE +#define SPI_IT_TXP SPI_IER_TXPIE +#define SPI_IT_DXP SPI_IER_DXPIE +#define SPI_IT_EOT SPI_IER_EOTIE +#define SPI_IT_TXTF SPI_IER_TXTFIE +#define SPI_IT_UDR SPI_IER_UDRIE +#define SPI_IT_OVR SPI_IER_OVRIE +#define SPI_IT_CRCERR SPI_IER_CRCEIE +#define SPI_IT_FRE SPI_IER_TIFREIE +#define SPI_IT_MODF SPI_IER_MODFIE +#define SPI_IT_ERR (SPI_IT_UDR | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF | SPI_IT_CRCERR) +/** + * @} + */ + +/** @defgroup SPI_Flags_definition SPI Flags Definition + * @{ + */ +#define SPI_FLAG_RXP SPI_SR_RXP /* SPI status flag : Rx-Packet available flag */ +#define SPI_FLAG_TXP SPI_SR_TXP /* SPI status flag : Tx-Packet space available flag */ +#define SPI_FLAG_DXP SPI_SR_DXP /* SPI status flag : Duplex Packet flag */ +#define SPI_FLAG_EOT SPI_SR_EOT /* SPI status flag : End of transfer flag */ +#define SPI_FLAG_TXTF SPI_SR_TXTF /* SPI status flag : Transmission Transfer Filled flag */ +#define SPI_FLAG_UDR SPI_SR_UDR /* SPI Error flag : Underrun flag */ +#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag : Overrun flag */ +#define SPI_FLAG_CRCERR SPI_SR_CRCE /* SPI Error flag : CRC error flag */ +#define SPI_FLAG_FRE SPI_SR_TIFRE /* SPI Error flag : TI mode frame format error flag */ +#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag : Mode fault flag */ +#define SPI_FLAG_SUSP SPI_SR_SUSP /* SPI status flag : Transfer suspend complete flag */ +#define SPI_FLAG_TXC SPI_SR_TXC /* SPI status flag : TxFIFO transmission complete flag */ +#define SPI_FLAG_FRLVL SPI_SR_RXPLVL /* SPI status flag : Fifo reception level flag */ +#define SPI_FLAG_RXWNE SPI_SR_RXWNE /* SPI status flag : RxFIFO word not empty flag */ +/** + * @} + */ + +/** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level + * @{ + */ +#define SPI_RX_FIFO_0PACKET (0x00000000UL) /* 0 or multiple of 4 packets available in the RxFIFO */ +#define SPI_RX_FIFO_1PACKET (SPI_SR_RXPLVL_0) +#define SPI_RX_FIFO_2PACKET (SPI_SR_RXPLVL_1) +#define SPI_RX_FIFO_3PACKET (SPI_SR_RXPLVL_1 | SPI_SR_RXPLVL_0) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup SPI_Exported_Macros SPI Exported Macros + * @{ + */ + +/** @brief Reset SPI handle state. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. + * @retval None + */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) +#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_SPI_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + +/** @brief Enable the specified SPI interrupts. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. + * @param __INTERRUPT__: specifies the interrupt source to enable or disable. + * This parameter can be one of the following values: + * @arg SPI_IT_RXP : Rx-Packet available interrupt + * @arg SPI_IT_TXP : Tx-Packet space available interrupt + * @arg SPI_IT_DXP : Duplex Packet interrupt + * @arg SPI_IT_EOT : End of transfer interrupt + * @arg SPI_IT_TXTF : Transmission Transfer Filled interrupt + * @arg SPI_IT_UDR : Underrun interrupt + * @arg SPI_IT_OVR : Overrun interrupt + * @arg SPI_IT_CRCERR : CRC error interrupt + * @arg SPI_IT_FRE : TI mode frame format error interrupt + * @arg SPI_IT_MODF : Mode fault interrupt + * @arg SPI_IT_ERR : Error interrupt + * @retval None + */ +#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) + +/** @brief Disable the specified SPI interrupts. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. + * @param __INTERRUPT__: specifies the interrupt source to enable or disable. + * This parameter can be one of the following values: + * @arg SPI_IT_RXP : Rx-Packet available interrupt + * @arg SPI_IT_TXP : Tx-Packet space available interrupt + * @arg SPI_IT_DXP : Duplex Packet interrupt + * @arg SPI_IT_EOT : End of transfer interrupt + * @arg SPI_IT_TXTF : Transmission Transfer Filled interrupt + * @arg SPI_IT_UDR : Underrun interrupt + * @arg SPI_IT_OVR : Overrun interrupt + * @arg SPI_IT_CRCERR : CRC error interrupt + * @arg SPI_IT_FRE : TI mode frame format error interrupt + * @arg SPI_IT_MODF : Mode fault interrupt + * @arg SPI_IT_ERR : Error interrupt + * @retval None + */ +#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__))) + +/** @brief Check whether the specified SPI interrupt source is enabled or not. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. + * @param __INTERRUPT__: specifies the SPI interrupt source to check. + * This parameter can be one of the following values: + * @arg SPI_IT_RXP : Rx-Packet available interrupt + * @arg SPI_IT_TXP : Tx-Packet space available interrupt + * @arg SPI_IT_DXP : Duplex Packet interrupt + * @arg SPI_IT_EOT : End of transfer interrupt + * @arg SPI_IT_TXTF : Transmission Transfer Filled interrupt + * @arg SPI_IT_UDR : Underrun interrupt + * @arg SPI_IT_OVR : Overrun interrupt + * @arg SPI_IT_CRCERR : CRC error interrupt + * @arg SPI_IT_FRE : TI mode frame format error interrupt + * @arg SPI_IT_MODF : Mode fault interrupt + * @arg SPI_IT_ERR : Error interrupt + * @retval The new state of __IT__ (TRUE or FALSE). + */ +#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & \ + (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Check whether the specified SPI flag is set or not. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg SPI_FLAG_RXP : Rx-Packet available flag + * @arg SPI_FLAG_TXP : Tx-Packet space available flag + * @arg SPI_FLAG_DXP : Duplex Packet flag + * @arg SPI_FLAG_EOT : End of transfer flag + * @arg SPI_FLAG_TXTF : Transmission Transfer Filled flag + * @arg SPI_FLAG_UDR : Underrun flag + * @arg SPI_FLAG_OVR : Overrun flag + * @arg SPI_FLAG_CRCERR : CRC error flag + * @arg SPI_FLAG_FRE : TI mode frame format error flag + * @arg SPI_FLAG_MODF : Mode fault flag + * @arg SPI_FLAG_SUSP : Transfer suspend complete flag + * @arg SPI_FLAG_TXC : TxFIFO transmission complete flag + * @arg SPI_FLAG_FRLVL : Fifo reception level flag + * @arg SPI_FLAG_RXWNE : RxFIFO word not empty flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) + +/** @brief Clear the SPI CRCERR pending flag. + * @param __HANDLE__: specifies the SPI Handle. + * @retval None + */ +#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_CRCEC) + +/** @brief Clear the SPI MODF pending flag. + * @param __HANDLE__: specifies the SPI Handle. + * @retval None + */ +#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , (uint32_t)(SPI_IFCR_MODFC)); + +/** @brief Clear the SPI OVR pending flag. + * @param __HANDLE__: specifies the SPI Handle. + * @retval None + */ +#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_OVRC) + +/** @brief Clear the SPI FRE pending flag. + * @param __HANDLE__: specifies the SPI Handle. + * @retval None + */ +#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TIFREC) + +/** @brief Clear the SPI UDR pending flag. + * @param __HANDLE__: specifies the SPI Handle. + * @retval None + */ +#define __HAL_SPI_CLEAR_UDRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_UDRC) + +/** @brief Clear the SPI EOT pending flag. + * @param __HANDLE__: specifies the SPI Handle. + * @retval None + */ +#define __HAL_SPI_CLEAR_EOTFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_EOTC) + +/** @brief Clear the SPI UDR pending flag. + * @param __HANDLE__: specifies the SPI Handle. + * @retval None + */ +#define __HAL_SPI_CLEAR_TXTFFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TXTFC) + +/** @brief Clear the SPI SUSP pending flag. + * @param __HANDLE__: specifies the SPI Handle. + * @retval None + */ +#define __HAL_SPI_CLEAR_SUSPFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_SUSPC) + +/** @brief Enable the SPI peripheral. + * @param __HANDLE__: specifies the SPI Handle. + * @retval None + */ +#define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_SPE) + +/** @brief Disable the SPI peripheral. + * @param __HANDLE__: specifies the SPI Handle. + * @retval None + */ +#define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_SPE) +/** + * @} + */ + + +/* Include SPI HAL Extension module */ +#include "stm32wbaxx_hal_spi_ex.h" + + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SPI_Exported_Functions + * @{ + */ + +/** @addtogroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +/* Initialization/de-initialization functions ********************************/ +HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi); +void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi); +void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, + pSPI_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @addtogroup SPI_Exported_Functions_Group2 IO operation functions + * @{ + */ +/* I/O operation functions ***************************************************/ +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size); + +HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size); + + +HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi); + +/* Transfer Abort functions */ +HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi); + +void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi); +void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_SuspendCallback(SPI_HandleTypeDef *hspi); +/** + * @} + */ + +/** @addtogroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions + * @{ + */ + +/* Peripheral State and Error functions ***************************************/ +HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi); +uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi); +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup SPI_Private_Macros SPI Private Macros + * @{ + */ + +/** @brief Set the SPI transmit-only mode in 1Line configuration. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_HDDIR) + +/** @brief Set the SPI receive-only mode in 1Line configuration. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_HDDIR) + +/** @brief Set the SPI transmit-only mode in 2Lines configuration. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_2LINES_TX(__HANDLE__) MODIFY_REG((__HANDLE__)->Instance->CFG2, SPI_CFG2_COMM, SPI_CFG2_COMM_0) + +/** @brief Set the SPI receive-only mode in 2Lines configuration. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_2LINES_RX(__HANDLE__) MODIFY_REG((__HANDLE__)->Instance->CFG2, SPI_CFG2_COMM, SPI_CFG2_COMM_1) + +/** @brief Set the SPI Transmit-Receive mode in 2Lines configuration. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_2LINES(__HANDLE__) MODIFY_REG((__HANDLE__)->Instance->CFG2, SPI_CFG2_COMM, 0x00000000UL) + +#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \ + ((MODE) == SPI_MODE_MASTER)) + +#define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \ + ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \ + ((MODE) == SPI_DIRECTION_1LINE) || \ + ((MODE) == SPI_DIRECTION_2LINES_TXONLY)) + +#define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES) + +#define IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(MODE) (((MODE) == SPI_DIRECTION_2LINES)|| \ + ((MODE) == SPI_DIRECTION_1LINE) || \ + ((MODE) == SPI_DIRECTION_2LINES_TXONLY)) + +#define IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(MODE) (((MODE) == SPI_DIRECTION_2LINES)|| \ + ((MODE) == SPI_DIRECTION_1LINE) || \ + ((MODE) == SPI_DIRECTION_2LINES_RXONLY)) + +#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_32BIT) || \ + ((DATASIZE) == SPI_DATASIZE_31BIT) || \ + ((DATASIZE) == SPI_DATASIZE_30BIT) || \ + ((DATASIZE) == SPI_DATASIZE_29BIT) || \ + ((DATASIZE) == SPI_DATASIZE_28BIT) || \ + ((DATASIZE) == SPI_DATASIZE_27BIT) || \ + ((DATASIZE) == SPI_DATASIZE_26BIT) || \ + ((DATASIZE) == SPI_DATASIZE_25BIT) || \ + ((DATASIZE) == SPI_DATASIZE_24BIT) || \ + ((DATASIZE) == SPI_DATASIZE_23BIT) || \ + ((DATASIZE) == SPI_DATASIZE_22BIT) || \ + ((DATASIZE) == SPI_DATASIZE_21BIT) || \ + ((DATASIZE) == SPI_DATASIZE_20BIT) || \ + ((DATASIZE) == SPI_DATASIZE_22BIT) || \ + ((DATASIZE) == SPI_DATASIZE_19BIT) || \ + ((DATASIZE) == SPI_DATASIZE_18BIT) || \ + ((DATASIZE) == SPI_DATASIZE_17BIT) || \ + ((DATASIZE) == SPI_DATASIZE_16BIT) || \ + ((DATASIZE) == SPI_DATASIZE_15BIT) || \ + ((DATASIZE) == SPI_DATASIZE_14BIT) || \ + ((DATASIZE) == SPI_DATASIZE_13BIT) || \ + ((DATASIZE) == SPI_DATASIZE_12BIT) || \ + ((DATASIZE) == SPI_DATASIZE_11BIT) || \ + ((DATASIZE) == SPI_DATASIZE_10BIT) || \ + ((DATASIZE) == SPI_DATASIZE_9BIT) || \ + ((DATASIZE) == SPI_DATASIZE_8BIT) || \ + ((DATASIZE) == SPI_DATASIZE_7BIT) || \ + ((DATASIZE) == SPI_DATASIZE_6BIT) || \ + ((DATASIZE) == SPI_DATASIZE_5BIT) || \ + ((DATASIZE) == SPI_DATASIZE_4BIT)) + +/** + * @brief DataSize for limited instance + */ +#define IS_SPI_LIMITED_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \ + ((DATASIZE) == SPI_DATASIZE_8BIT)) + +#define IS_SPI_FIFOTHRESHOLD(THRESHOLD) (((THRESHOLD) == SPI_FIFO_THRESHOLD_01DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_02DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_03DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_04DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_05DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_06DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_07DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_08DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_09DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_10DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_11DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_12DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_13DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_14DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_15DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_16DATA)) + +/** + * @brief FifoThreshold for limited instance + */ +#define IS_SPI_LIMITED_FIFOTHRESHOLD(THRESHOLD) (((THRESHOLD) == SPI_FIFO_THRESHOLD_01DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_02DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_03DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_04DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_05DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_06DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_07DATA) || \ + ((THRESHOLD) == SPI_FIFO_THRESHOLD_08DATA)) + +#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \ + ((CPOL) == SPI_POLARITY_HIGH)) + +#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \ + ((CPHA) == SPI_PHASE_2EDGE)) + +#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \ + ((NSS) == SPI_NSS_HARD_INPUT) || \ + ((NSS) == SPI_NSS_HARD_OUTPUT)) + +#define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLE) || \ + ((NSSP) == SPI_NSS_PULSE_DISABLE)) + +#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_BYPASS) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \ + ((PRESCALER) == SPI_BAUDRATEPRESCALER_256)) + +#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \ + ((BIT) == SPI_FIRSTBIT_LSB)) + +#define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \ + ((MODE) == SPI_TIMODE_ENABLE)) + +#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \ + ((CALCULATION) == SPI_CRCCALCULATION_ENABLE)) + +#define IS_SPI_CRC_INITIALIZATION_PATTERN(PATTERN) (((PATTERN) == SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN) || \ + ((PATTERN) == SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN)) + +#define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_DATASIZE) || \ + ((LENGTH) == SPI_CRC_LENGTH_32BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_31BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_30BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_29BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_28BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_27BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_26BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_25BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_24BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_23BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_22BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_21BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_20BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_19BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_18BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_17BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_16BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_15BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_14BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_13BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_12BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_11BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_10BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_9BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_8BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_7BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_6BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_5BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_4BIT)) + +/** + * @brief CRC Length for limited instance + */ +#define IS_SPI_LIMITED_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_8BIT) || \ + ((LENGTH) == SPI_CRC_LENGTH_16BIT)) + + +#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) > 0x0UL) + + + +#define IS_SPI_UNDERRUN_BEHAVIOUR(MODE) (((MODE) == SPI_UNDERRUN_BEHAV_REGISTER_PATTERN) || \ + ((MODE) == SPI_UNDERRUN_BEHAV_LAST_RECEIVED)) + +#define IS_SPI_RDY_MASTER_MANAGEMENT(MANAGEMENT) (((MANAGEMENT) == SPI_RDY_MASTER_MANAGEMENT_INTERNALLY) || \ + ((MANAGEMENT) == SPI_RDY_MASTER_MANAGEMENT_EXTERNALLY)) + +#define IS_SPI_RDY_POLARITY(POLARITY) (((POLARITY) == SPI_RDY_POLARITY_HIGH) || \ + ((POLARITY) == SPI_RDY_POLARITY_LOW)) + +#define IS_SPI_MASTER_RX_AUTOSUSP(MODE) (((MODE) == SPI_MASTER_RX_AUTOSUSP_DISABLE) || \ + ((MODE) == SPI_MASTER_RX_AUTOSUSP_ENABLE)) +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WBAxx_HAL_SPI_H */ + +/** + * @} + */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_spi_ex.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_spi_ex.h new file mode 100644 index 0000000000..21cd5a75f8 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_spi_ex.h @@ -0,0 +1,285 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_spi_ex.h + * @author MCD Application Team + * @brief Header file of SPI HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_HAL_SPI_EX_H +#define STM32WBAxx_HAL_SPI_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal_def.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @addtogroup SPIEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup SPIEx_Exported_Types SPIEx Exported Types + * @{ + */ + +/** + * @brief SPI Autonomous Mode Configuration structure definition + */ +typedef struct +{ + uint32_t TriggerState; /*!< Specifies the trigger state. This parameter can be a value + of @ref FunctionalState */ + + uint32_t TriggerSelection; /*!< Specifies the autonomous mode trigger signal selection. This parameter + can be a value of @ref SPI_AutonomousMode_TriggerSelection */ + + uint32_t TriggerPolarity; /*!< Specifies the autonomous mode trigger signal polarity sensitivity. This parameter + can be a value of @ref SPI_AutonomousMode_TriggerPolarity */ + +} SPI_AutonomousModeConfTypeDef; + + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SPIEx_Exported_Constants SPIEx Exported Constants + * @{ + */ + +/** @defgroup FunctionalState SPI Autonomous Mode State + * @{ + */ +#define SPI_AUTO_MODE_DISABLE (0x00000000UL) +#define SPI_AUTO_MODE_ENABLE SPI_AUTOCR_TRIGEN +/** + * @} + */ + +/** @defgroup SPI_AutonomousMode_TriggerSelection Autonomous Mode Trigger Selection + * @{ + */ +#if defined (SPI1) +#define SPI_TRIG_GRP1 (0x10000000U) /* Trigger Group for SPI1 */ +#endif /* SPI1 */ +#define SPI_TRIG_GRP2 (0x20000000U) /* Trigger Group for SPI3 */ + +#if defined (SPI_TRIG_GRP1) +/* HW Trigger signal is GPDMA_CH0_TRG */ +#define SPI_GRP1_GPDMA_CH0_TCF_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x00000000U)) +/* HW Trigger signal is GPDMA_CH1_TRG */ +#define SPI_GRP1_GPDMA_CH1_TCF_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x1U << SPI_AUTOCR_TRIGSEL_Pos)) +/* HW Trigger signal is GPDMA_CH2_TRG */ +#define SPI_GRP1_GPDMA_CH2_TCF_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x2U << SPI_AUTOCR_TRIGSEL_Pos)) +/* HW Trigger signal is GPDMA_CH3_TRG */ +#define SPI_GRP1_GPDMA_CH3_TCF_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x3U << SPI_AUTOCR_TRIGSEL_Pos)) +/* HW Trigger signal is EXTI4_TRG */ +#define SPI_GRP1_EXTI4_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x4U << SPI_AUTOCR_TRIGSEL_Pos)) +/* HW Trigger signal is EXTI9_TRG */ +#define SPI_GRP1_EXTI9_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x5U << SPI_AUTOCR_TRIGSEL_Pos)) +/* HW Trigger signal is LPTIM1_CH1_TRG */ +#define SPI_GRP1_LPTIM1_CH1_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x6U << SPI_AUTOCR_TRIGSEL_Pos)) +#if defined(LPTIM2) +/* HW Trigger signal is LPTIM2_CH1_TRG */ +#define SPI_GRP1_LPTIM2_CH1_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x7U << SPI_AUTOCR_TRIGSEL_Pos)) +#endif /* LPTIM2 */ +#if defined(COMP1) +/* HW Trigger signal is COMP1_TRG */ +#define SPI_GRP1_COMP1_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x8U << SPI_AUTOCR_TRIGSEL_Pos)) +#endif /* COMP1 */ +#if defined(COMP2) +/* HW Trigger signal is COMP2_TRG */ +#define SPI_GRP1_COMP2_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x9U << SPI_AUTOCR_TRIGSEL_Pos)) +#endif /* (COMP2) */ +/* HW Trigger signal is RTC_ALRA_TRG */ +#define SPI_GRP1_RTC_ALRA_TRG (uint32_t)(SPI_TRIG_GRP1 | (0xAU << SPI_AUTOCR_TRIGSEL_Pos)) +/* HW Trigger signal is RTC_WUT_TRG */ +#define SPI_GRP1_RTC_WUT_TRG (uint32_t)(SPI_TRIG_GRP1 | (0xBU << SPI_AUTOCR_TRIGSEL_Pos)) +#endif /* SPI_TRIG_GRP1 */ + +/* HW Trigger signal is GPDMA_CH0_TRG */ +#define SPI_GRP2_GPDMA_CH0_TCF_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x00000000U)) +/* HW Trigger signal is GPDMA_CH1_TRG */ +#define SPI_GRP2_GPDMA_CH1_TCF_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x1U << SPI_AUTOCR_TRIGSEL_Pos)) +/* HW Trigger signal is GPDMA_CH2_TRG */ +#define SPI_GRP2_GPDMA_CH2_TCF_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x2U << SPI_AUTOCR_TRIGSEL_Pos)) +/* HW Trigger signal is GPDMA_CH3_TRG */ +#define SPI_GRP2_GPDMA_CH3_TCF_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x3U << SPI_AUTOCR_TRIGSEL_Pos)) +/* HW Trigger signal is EXTI4_TRG */ +#define SPI_GRP2_EXTI4_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x4U << SPI_AUTOCR_TRIGSEL_Pos)) +/* HW Trigger signal is EXTI8_TRG */ +#define SPI_GRP2_EXTI8_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x5U << SPI_AUTOCR_TRIGSEL_Pos)) +/* HW Trigger signal is LPTIM1_CH1_TRG */ +#define SPI_GRP2_LPTIM1_CH1_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x6U << SPI_AUTOCR_TRIGSEL_Pos)) +#if defined(COMP1) +/* HW Trigger signal is COMP1_TRG */ +#define SPI_GRP2_COMP1_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x8U << SPI_AUTOCR_TRIGSEL_Pos)) +#endif /* COMP1 */ +/* HW Trigger signal is RTC_ALRA_TRG */ +#define SPI_GRP2_RTC_ALRA_TRG (uint32_t)(SPI_TRIG_GRP2 | (0xAU << SPI_AUTOCR_TRIGSEL_Pos)) +/* HW Trigger signal is RTC_WUT_TRG */ +#define SPI_GRP2_RTC_WUT_TRG (uint32_t)(SPI_TRIG_GRP2 | (0xBU << SPI_AUTOCR_TRIGSEL_Pos)) +/** + * @} + */ + +/** @defgroup SPI_AutonomousMode_TriggerPolarity Autonomous Mode Trigger Polarity + * @{ + */ +#define SPI_TRIG_POLARITY_RISING (0x00000000UL) /* SPI HW Trigger signal on rising edge */ +#define SPI_TRIG_POLARITY_FALLING SPI_AUTOCR_TRIGPOL /* SPI HW Trigger signal on falling edge */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup SPIEx_Exported_Macros SPIEx Extended Exported Macros + * @{ + */ + +#define IS_SPI_AUTO_MODE(__MODE__) (((__MODE__) == SPI_AUTO_MODE_DISABLE) || \ + ((__MODE__) == SPI_AUTO_MODE_ENABLE)) + +#if defined(SPI_TRIG_GRP1) +#define IS_SPI_AUTONOMOUS_INSTANCE(__INSTANCE__) (IS_SPI_GRP1_INSTANCE(__INSTANCE__) || \ + IS_SPI_GRP2_INSTANCE(__INSTANCE__)) +#else +#define IS_SPI_AUTONOMOUS_INSTANCE(__INSTANCE__) IS_SPI_GRP1_INSTANCE(__INSTANCE__) +#endif /* SPI_TRIG_GRP1 */ + +#if defined (SPI_TRIG_GRP1) +#define IS_SPI_TRIG_SOURCE(__INSTANCE__, __SOURCE__) ((IS_SPI_GRP2_INSTANCE(__INSTANCE__)) ? \ + IS_SPI_GRP2_TRIG_SOURCE(__SOURCE__) : \ + IS_SPI_GRP1_TRIG_SOURCE(__SOURCE__)) +#else +#define IS_SPI_TRIG_SOURCE(__INSTANCE__, __SOURCE__) (IS_SPI_GRP2_TRIG_SOURCE(__SOURCE__)) +#endif /* SPI_TRIG_GRP1 */ + +#if defined(COMP1) && defined(COMP2) +#if defined (SPI_TRIG_GRP1) +#define IS_SPI_GRP1_TRIG_SOURCE(__SOURCE__) (((__SOURCE__) == SPI_GRP1_GPDMA_CH0_TCF_TRG ) || \ + ((__SOURCE__) == SPI_GRP1_GPDMA_CH1_TCF_TRG ) || \ + ((__SOURCE__) == SPI_GRP1_GPDMA_CH2_TCF_TRG ) || \ + ((__SOURCE__) == SPI_GRP1_GPDMA_CH3_TCF_TRG ) || \ + ((__SOURCE__) == SPI_GRP1_EXTI4_TRG ) || \ + ((__SOURCE__) == SPI_GRP1_EXTI9_TRG ) || \ + ((__SOURCE__) == SPI_GRP1_LPTIM1_CH1_TRG ) || \ + ((__SOURCE__) == SPI_GRP1_LPTIM2_CH1_TRG ) || \ + ((__SOURCE__) == SPI_GRP1_COMP1_TRG ) || \ + ((__SOURCE__) == SPI_GRP1_COMP2_TRG ) || \ + ((__SOURCE__) == SPI_GRP1_RTC_ALRA_TRG ) || \ + ((__SOURCE__) == SPI_GRP1_RTC_WUT_TRG )) +#endif /* SPI_TRIG_GRP1 */ + +#define IS_SPI_GRP2_TRIG_SOURCE(__SOURCE__) (((__SOURCE__) == SPI_GRP2_GPDMA_CH0_TCF_TRG ) || \ + ((__SOURCE__) == SPI_GRP2_GPDMA_CH1_TCF_TRG ) || \ + ((__SOURCE__) == SPI_GRP2_GPDMA_CH2_TCF_TRG ) || \ + ((__SOURCE__) == SPI_GRP2_GPDMA_CH3_TCF_TRG ) || \ + ((__SOURCE__) == SPI_GRP2_EXTI4_TRG ) || \ + ((__SOURCE__) == SPI_GRP2_EXTI8_TRG ) || \ + ((__SOURCE__) == SPI_GRP2_LPTIM1_CH1_TRG ) || \ + ((__SOURCE__) == SPI_GRP2_COMP1_TRG ) || \ + ((__SOURCE__) == SPI_GRP2_RTC_ALRA_TRG ) || \ + ((__SOURCE__) == SPI_GRP2_RTC_WUT_TRG )) +#else /* COMP1 && COMP2 */ +#if defined (SPI_TRIG_GRP1) +#define IS_SPI_GRP1_TRIG_SOURCE(__SOURCE__) (((__SOURCE__) == SPI_GRP1_GPDMA_CH0_TCF_TRG ) || \ + ((__SOURCE__) == SPI_GRP1_GPDMA_CH1_TCF_TRG ) || \ + ((__SOURCE__) == SPI_GRP1_GPDMA_CH2_TCF_TRG ) || \ + ((__SOURCE__) == SPI_GRP1_GPDMA_CH3_TCF_TRG ) || \ + ((__SOURCE__) == SPI_GRP1_EXTI4_TRG ) || \ + ((__SOURCE__) == SPI_GRP1_EXTI9_TRG ) || \ + ((__SOURCE__) == SPI_GRP1_LPTIM1_CH1_TRG ) || \ + ((__SOURCE__) == SPI_GRP1_LPTIM2_CH1_TRG ) || \ + ((__SOURCE__) == SPI_GRP1_RTC_ALRA_TRG ) || \ + ((__SOURCE__) == SPI_GRP1_RTC_WUT_TRG )) +#endif /* SPI_TRIG_GRP1 */ + +#define IS_SPI_GRP2_TRIG_SOURCE(__SOURCE__) (((__SOURCE__) == SPI_GRP2_GPDMA_CH0_TCF_TRG ) || \ + ((__SOURCE__) == SPI_GRP2_GPDMA_CH1_TCF_TRG ) || \ + ((__SOURCE__) == SPI_GRP2_GPDMA_CH2_TCF_TRG ) || \ + ((__SOURCE__) == SPI_GRP2_GPDMA_CH3_TCF_TRG ) || \ + ((__SOURCE__) == SPI_GRP2_EXTI4_TRG ) || \ + ((__SOURCE__) == SPI_GRP2_EXTI8_TRG ) || \ + ((__SOURCE__) == SPI_GRP2_LPTIM1_CH1_TRG ) || \ + ((__SOURCE__) == SPI_GRP2_RTC_ALRA_TRG ) || \ + ((__SOURCE__) == SPI_GRP2_RTC_WUT_TRG )) +#endif /* COMP1 && COMP2 */ + +#define IS_SPI_AUTO_MODE_TRG_POL(__POLARITY__) (((__POLARITY__) == SPI_TRIG_POLARITY_RISING) || \ + ((__POLARITY__) == SPI_TRIG_POLARITY_FALLING)) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SPIEx_Exported_Functions + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ +/* IO operation functions *****************************************************/ +/** @addtogroup SPIEx_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(const SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPIEx_EnableLockConfiguration(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPIEx_ConfigureUnderrun(SPI_HandleTypeDef *hspi, uint32_t UnderrunDetection, + uint32_t UnderrunBehaviour); +/** + * @} + */ + +/** @addtogroup SPI_Autonomous_Mode_Functions Autonomous Mode Functions + * @{ + */ +HAL_StatusTypeDef HAL_SPIEx_SetConfigAutonomousMode(SPI_HandleTypeDef *hspi, + const SPI_AutonomousModeConfTypeDef *sConfig); +HAL_StatusTypeDef HAL_SPIEx_GetConfigAutonomousMode(const SPI_HandleTypeDef *hspi, + SPI_AutonomousModeConfTypeDef *sConfig); +HAL_StatusTypeDef HAL_SPIEx_ClearConfigAutonomousMode(SPI_HandleTypeDef *hspi); +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WBAxx_HAL_SPI_EX_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_tim.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_tim.h new file mode 100644 index 0000000000..c0dc4c5a62 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_tim.h @@ -0,0 +1,2520 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_tim.h + * @author MCD Application Team + * @brief Header file of TIM HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_HAL_TIM_H +#define STM32WBAxx_HAL_TIM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal_def.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @addtogroup TIM + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup TIM_Exported_Types TIM Exported Types + * @{ + */ + +/** + * @brief TIM Time base Configuration Structure definition + */ +typedef struct +{ + uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF + Macro __HAL_TIM_CALC_PSC() can be used to calculate prescaler value */ + + uint32_t CounterMode; /*!< Specifies the counter mode. + This parameter can be a value of @ref TIM_Counter_Mode */ + + uint32_t Period; /*!< Specifies the period value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF + (or 0xFFEF if dithering is activated)Macros __HAL_TIM_CALC_PERIOD(), + __HAL_TIM_CALC_PERIOD_DITHER(),__HAL_TIM_CALC_PERIOD_BY_DELAY(), + __HAL_TIM_CALC_PERIOD_DITHER_BY_DELAY()can be used to calculate Period value */ + + uint32_t ClockDivision; /*!< Specifies the clock division. + This parameter can be a value of @ref TIM_ClockDivision */ + + uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter + reaches zero, an update event is generated and counting restarts + from the RCR value (N). + This means in PWM mode that (N+1) corresponds to: + - the number of PWM periods in edge-aligned mode + - the number of half PWM period in center-aligned mode + GP timers: this parameter must be a number between Min_Data = 0x00 and + Max_Data = 0xFF. + Advanced timers: this parameter must be a number between Min_Data = 0x0000 and + Max_Data = 0xFFFF. */ + + uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. + This parameter can be a value of @ref TIM_AutoReloadPreload */ +} TIM_Base_InitTypeDef; + +/** + * @brief TIM Output Compare Configuration Structure definition + */ +typedef struct +{ + uint32_t OCMode; /*!< Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF + (or 0xFFEF if dithering is activated) + Macros __HAL_TIM_CALC_PULSE(), __HAL_TIM_CALC_PULSE_DITHER() can be used to calculate + Pulse value */ + + uint32_t OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCFastMode; /*!< Specifies the Fast mode state. + This parameter can be a value of @ref TIM_Output_Fast_State + @note This parameter is valid only in PWM1 and PWM2 mode. */ + + + uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ +} TIM_OC_InitTypeDef; + +/** + * @brief TIM One Pulse Mode Configuration Structure definition + */ +typedef struct +{ + uint32_t OCMode; /*!< Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF + (or 0xFFEF if dithering is activated) + Macros __HAL_TIM_CALC_PULSE(), __HAL_TIM_CALC_PULSE_DITHER() can be used to calculate + Pulse value */ + + uint32_t OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t ICSelection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t ICFilter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_OnePulse_InitTypeDef; + +/** + * @brief TIM Input Capture Configuration Structure definition + */ +typedef struct +{ + uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t ICSelection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t ICFilter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_IC_InitTypeDef; + +/** + * @brief TIM Encoder Configuration Structure definition + */ +typedef struct +{ + uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Encoder_Mode */ + + uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ + + uint32_t IC1Selection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t IC1Filter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + + uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ + + uint32_t IC2Selection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t IC2Filter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_Encoder_InitTypeDef; + +/** + * @brief Clock Configuration Handle Structure definition + */ +typedef struct +{ + uint32_t ClockSource; /*!< TIM clock sources + This parameter can be a value of @ref TIM_Clock_Source */ + uint32_t ClockPolarity; /*!< TIM clock polarity + This parameter can be a value of @ref TIM_Clock_Polarity */ + uint32_t ClockPrescaler; /*!< TIM clock prescaler + This parameter can be a value of @ref TIM_Clock_Prescaler */ + uint32_t ClockFilter; /*!< TIM clock filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_ClockConfigTypeDef; + +/** + * @brief TIM Clear Input Configuration Handle Structure definition + */ +typedef struct +{ + uint32_t ClearInputState; /*!< TIM clear Input state + This parameter can be ENABLE or DISABLE */ + uint32_t ClearInputSource; /*!< TIM clear Input sources + This parameter can be a value of @ref TIM_ClearInput_Source */ + uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity + This parameter can be a value of @ref TIM_ClearInput_Polarity */ + uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler + This parameter must be 0: When OCRef clear feature is used with ETR source, + ETR prescaler must be off */ + uint32_t ClearInputFilter; /*!< TIM Clear Input filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_ClearInputConfigTypeDef; + +/** + * @brief TIM Master configuration Structure definition + * @note Advanced timers provide TRGO2 internal line which is redirected + * to the ADC + */ +typedef struct +{ + uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection + This parameter can be a value of @ref TIM_Master_Mode_Selection */ + uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection + This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */ + uint32_t MasterSlaveMode; /*!< Master/slave mode selection + This parameter can be a value of @ref TIM_Master_Slave_Mode + @note When the Master/slave mode is enabled, the effect of + an event on the trigger input (TRGI) is delayed to allow a + perfect synchronization between the current timer and its + slaves (through TRGO). It is not mandatory in case of timer + synchronization mode. */ +} TIM_MasterConfigTypeDef; + +/** + * @brief TIM Slave configuration Structure definition + */ +typedef struct +{ + uint32_t SlaveMode; /*!< Slave mode selection + This parameter can be a value of @ref TIM_Slave_Mode */ + uint32_t InputTrigger; /*!< Input Trigger source + This parameter can be a value of @ref TIM_Trigger_Selection */ + uint32_t TriggerPolarity; /*!< Input Trigger polarity + This parameter can be a value of @ref TIM_Trigger_Polarity */ + uint32_t TriggerPrescaler; /*!< Input trigger prescaler + This parameter can be a value of @ref TIM_Trigger_Prescaler */ + uint32_t TriggerFilter; /*!< Input trigger filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + +} TIM_SlaveConfigTypeDef; + +/** + * @brief TIM Break input(s) and Dead time configuration Structure definition + * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable + * filter and polarity. + */ +typedef struct +{ + uint32_t OffStateRunMode; /*!< TIM off state in run mode, This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ + + uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode, This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ + + uint32_t LockLevel; /*!< TIM Lock level, This parameter can be a value of @ref TIM_Lock_level */ + + uint32_t DeadTime; /*!< TIM dead Time, This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ + + uint32_t BreakState; /*!< TIM Break State, This parameter can be a value of @ref TIM_Break_Input_enable_disable */ + + uint32_t BreakPolarity; /*!< TIM Break input polarity, This parameter can be a value of @ref TIM_Break_Polarity */ + + uint32_t BreakFilter; /*!< Specifies the break input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + + uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input.This parameter can be a value of @ref TIM_Break_Input_AF_Mode */ + + uint32_t Break2State; /*!< TIM Break2 State, This parameter can be a value of @ref TIM_Break2_Input_enable_disable */ + + uint32_t Break2Polarity; /*!< TIM Break2 input polarity, This parameter can be a value of @ref TIM_Break2_Polarity */ + + uint32_t Break2Filter; /*!< TIM break2 input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + + uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input.This parameter can be a value of @ref TIM_Break2_Input_AF_Mode */ + + uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state, This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ + +} TIM_BreakDeadTimeConfigTypeDef; + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ + HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ + HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ + HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ +} HAL_TIM_StateTypeDef; + +/** + * @brief TIM Channel States definition + */ +typedef enum +{ + HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */ + HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */ + HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the TIM channel */ +} HAL_TIM_ChannelStateTypeDef; + +/** + * @brief DMA Burst States definition + */ +typedef enum +{ + HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */ + HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */ + HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */ +} HAL_TIM_DMABurstStateTypeDef; + +/** + * @brief HAL Active channel structures definition + */ +typedef enum +{ + HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ + HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ + HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ + HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ + HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, /*!< The active channel is 5 */ + HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, /*!< The active channel is 6 */ + HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ +} HAL_TIM_ActiveChannel; + +/** + * @brief TIM Time Base Handle Structure definition + */ +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +typedef struct __TIM_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +{ + TIM_TypeDef *Instance; /*!< Register base address */ + TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ + HAL_TIM_ActiveChannel Channel; /*!< Active channel */ + DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array + This array is accessed by a @ref DMA_Handle_index */ + HAL_LockTypeDef Lock; /*!< Locking object */ + __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ + __IO HAL_TIM_ChannelStateTypeDef ChannelState[6]; /*!< TIM channel operation state */ + __IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /*!< TIM complementary channel operation state */ + __IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */ + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */ + void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */ + void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */ + void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */ + void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */ + void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */ + void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */ + void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */ + void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */ + void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */ + void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */ + void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */ + void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */ + void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */ + void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */ + void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */ + void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */ + void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */ + void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */ + void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */ + void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */ + void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */ + void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */ + void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */ + void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */ + void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation half complete Callback */ + void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */ + void (* Break2Callback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break2 Callback */ + void (* EncoderIndexCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Index Callback */ + void (* DirectionChangeCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Direction Change Callback */ + void (* IndexErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Index Error Callback */ + void (* TransitionErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Transition Error Callback */ +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} TIM_HandleTypeDef; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +/** + * @brief HAL TIM Callback ID enumeration definition + */ +typedef enum +{ + HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ + , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ + , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ + , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ + , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ + , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ + , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ + , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ + , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ + , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ + , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ + , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ + , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ + , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ + , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ + , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ + , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ + , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ + , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ + , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ + , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ + , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ + , HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ + , HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */ + , HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */ + , HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */ + , HAL_TIM_ENCODER_INDEX_CB_ID = 0x1CU /*!< TIM Encoder Index Callback ID */ + , HAL_TIM_DIRECTION_CHANGE_CB_ID = 0x1DU /*!< TIM Direction Change Callback ID */ + , HAL_TIM_INDEX_ERROR_CB_ID = 0x1EU /*!< TIM Index Error Callback ID */ + , HAL_TIM_TRANSITION_ERROR_CB_ID = 0x1FU /*!< TIM Transition Error Callback ID */ +} HAL_TIM_CallbackIDTypeDef; + +/** + * @brief HAL TIM Callback pointer definition + */ +typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */ + +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ +/* End of exported types -----------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup TIM_Exported_Constants TIM Exported Constants + * @{ + */ + +/** @defgroup TIM_ClearInput_Source TIM Clear Input Source + * @{ + */ +#define TIM_CLEARINPUTSOURCE_NONE 0xFFFFFFFFU /*!< OCREF_CLR is disabled */ +#define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */ +#define TIM_CLEARINPUTSOURCE_COMP1 0x00000000U /*!< OCREF_CLR_INT is connected to COMP1 output */ +#define TIM_CLEARINPUTSOURCE_COMP2 TIM_AF2_OCRSEL_0 /*!< OCREF_CLR_INT is connected to COMP2 output */ +/** + * @} + */ + +/** @defgroup TIM_DMA_Base_address TIM DMA Base Address + * @{ + */ +#define TIM_DMABASE_CR1 0x00000000U +#define TIM_DMABASE_CR2 0x00000001U +#define TIM_DMABASE_SMCR 0x00000002U +#define TIM_DMABASE_DIER 0x00000003U +#define TIM_DMABASE_SR 0x00000004U +#define TIM_DMABASE_EGR 0x00000005U +#define TIM_DMABASE_CCMR1 0x00000006U +#define TIM_DMABASE_CCMR2 0x00000007U +#define TIM_DMABASE_CCER 0x00000008U +#define TIM_DMABASE_CNT 0x00000009U +#define TIM_DMABASE_PSC 0x0000000AU +#define TIM_DMABASE_ARR 0x0000000BU +#define TIM_DMABASE_RCR 0x0000000CU +#define TIM_DMABASE_CCR1 0x0000000DU +#define TIM_DMABASE_CCR2 0x0000000EU +#define TIM_DMABASE_CCR3 0x0000000FU +#define TIM_DMABASE_CCR4 0x00000010U +#define TIM_DMABASE_BDTR 0x00000011U +#define TIM_DMABASE_CCR5 0x00000012U +#define TIM_DMABASE_CCR6 0x00000013U +#define TIM_DMABASE_CCMR3 0x00000014U +#define TIM_DMABASE_DTR2 0x00000015U +#define TIM_DMABASE_ECR 0x00000016U +#define TIM_DMABASE_TISEL 0x00000017U +#define TIM_DMABASE_AF1 0x00000018U +#define TIM_DMABASE_AF2 0x00000019U +#define TIM_DMABASE_OR 0x0000001AU +/** + * @} + */ + +/** @defgroup TIM_Event_Source TIM Event Source + * @{ + */ +#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */ +#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */ +#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */ +#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */ +#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */ +#define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */ +#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */ +#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */ +#define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G /*!< A break 2 event is generated */ +/** + * @} + */ + +/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity + * @{ + */ +#define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */ +#define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */ +#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ +/** + * @} + */ + +/** @defgroup TIM_ETR_Polarity TIM ETR Polarity + * @{ + */ +#define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */ +#define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */ +/** + * @} + */ + +/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler + * @{ + */ +#define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */ +#define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */ +#define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */ +#define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */ +/** + * @} + */ + +/** @defgroup TIM_Counter_Mode TIM Counter Mode + * @{ + */ +#define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */ +#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */ +#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */ +#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */ +#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */ +/** + * @} + */ + +/** @defgroup TIM_Update_Interrupt_Flag_Remap TIM Update Interrupt Flag Remap + * @{ + */ +#define TIM_UIFREMAP_DISABLE 0x00000000U /*!< Update interrupt flag remap disabled */ +#define TIM_UIFREMAP_ENABLE TIM_CR1_UIFREMAP /*!< Update interrupt flag remap enabled */ +/** + * @} + */ + +/** @defgroup TIM_ClockDivision TIM Clock Division + * @{ + */ +#define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */ +#define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */ +#define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_State TIM Output Compare State + * @{ + */ +#define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */ +#define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */ +/** + * @} + */ + +/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload + * @{ + */ +#define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */ +#define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */ + +/** + * @} + */ + +/** @defgroup TIM_Output_Fast_State TIM Output Fast State + * @{ + */ +#define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */ +#define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State + * @{ + */ +#define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */ +#define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity + * @{ + */ +#define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */ +#define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity + * @{ + */ +#define TIM_OCNPOLARITY_HIGH 0x00000000U /*!< Capture/Compare complementary output polarity */ +#define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State + * @{ + */ +#define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */ +#define TIM_OCIDLESTATE_RESET 0x00000000U /*!< Output Idle state: OCx=0 when MOE=0 */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State + * @{ + */ +#define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */ +#define TIM_OCNIDLESTATE_RESET 0x00000000U /*!< Complementary output Idle state: OCxN=0 when MOE=0 */ +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity + * @{ + */ +#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */ +#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */ +#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/ +/** + * @} + */ + +/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity + * @{ + */ +#define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */ +#define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */ +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection + * @{ + */ +#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively */ +#define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler + * @{ + */ +#define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */ +#define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */ +#define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */ +#define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */ +/** + * @} + */ + +/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode + * @{ + */ +#define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ +#define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ +/** + * @} + */ + +/** @defgroup TIM_Encoder_Mode TIM Encoder Mode + * @{ + */ +#define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */ +#define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */ +#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */ +#define TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1) /*!< Encoder mode: Clock plus direction, x2 mode */ +#define TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Encoder mode: Clock plus direction, x1 mode, TI2FP2 edge sensitivity is set by CC2P */ +#define TIM_ENCODERMODE_DIRECTIONALCLOCK_X2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2) /*!< Encoder mode: Directional Clock, x2 mode */ +#define TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Encoder mode: Directional Clock, x1 mode, TI1FP1 and TI2FP2 edge sensitivity is set by CC1P and CC2P */ +#define TIM_ENCODERMODE_X1_TI1 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Quadrature encoder mode: x1 mode, counting on TI1FP1 edges only, edge sensitivity is set by CC1P */ +#define TIM_ENCODERMODE_X1_TI2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode: x1 mode, counting on TI2FP2 edges only, edge sensitivity is set by CC1P */ +/** + * @} + */ + +/** @defgroup TIM_Interrupt_definition TIM interrupt Definition + * @{ + */ +#define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */ +#define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */ +#define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */ +#define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */ +#define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */ +#define TIM_IT_COM TIM_DIER_COMIE /*!< Commutation interrupt */ +#define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */ +#define TIM_IT_BREAK TIM_DIER_BIE /*!< Break interrupt */ +#define TIM_IT_IDX TIM_DIER_IDXIE /*!< Index interrupt */ +#define TIM_IT_DIR TIM_DIER_DIRIE /*!< Direction change interrupt */ +#define TIM_IT_IERR TIM_DIER_IERRIE /*!< Index error interrupt */ +#define TIM_IT_TERR TIM_DIER_TERRIE /*!< Transition error interrupt */ +/** + * @} + */ + +/** @defgroup TIM_Commutation_Source TIM Commutation Source + * @{ + */ +#define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */ +#define TIM_COMMUTATION_SOFTWARE 0x00000000U /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */ +/** + * @} + */ + +/** @defgroup TIM_DMA_sources TIM DMA Sources + * @{ + */ +#define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */ +#define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */ +#define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */ +#define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */ +#define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */ +#define TIM_DMA_COM TIM_DIER_COMDE /*!< DMA request is triggered by the commutation event */ +#define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */ +/** + * @} + */ + +/** @defgroup TIM_CC_DMA_Request CCx DMA request selection + * @{ + */ +#define TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when capture or compare match event occurs */ +#define TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */ +/** + * @} + */ + +/** @defgroup TIM_Flag_definition TIM Flag Definition + * @{ + */ +#define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */ +#define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */ +#define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */ +#define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */ +#define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */ +#define TIM_FLAG_CC5 TIM_SR_CC5IF /*!< Capture/Compare 5 interrupt flag */ +#define TIM_FLAG_CC6 TIM_SR_CC6IF /*!< Capture/Compare 6 interrupt flag */ +#define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */ +#define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */ +#define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */ +#define TIM_FLAG_BREAK2 TIM_SR_B2IF /*!< Break 2 interrupt flag */ +#define TIM_FLAG_SYSTEM_BREAK TIM_SR_SBIF /*!< System Break interrupt flag */ +#define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */ +#define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */ +#define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */ +#define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */ +#define TIM_FLAG_IDX TIM_SR_IDXF /*!< Encoder index flag */ +#define TIM_FLAG_DIR TIM_SR_DIRF /*!< Direction change flag */ +#define TIM_FLAG_IERR TIM_SR_IERRF /*!< Index error flag */ +#define TIM_FLAG_TERR TIM_SR_TERRF /*!< Transition error flag */ +/** + * @} + */ + +/** @defgroup TIM_Channel TIM Channel + * @{ + */ +#define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */ +#define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */ +#define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */ +#define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */ +#define TIM_CHANNEL_5 0x00000010U /*!< Compare channel 5 identifier */ +#define TIM_CHANNEL_6 0x00000014U /*!< Compare channel 6 identifier */ +#define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */ +/** + * @} + */ + +/** @defgroup TIM_Clock_Source TIM Clock Source + * @{ + */ +#define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */ +#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */ +#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */ +#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */ +#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */ +#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */ +#define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */ +#define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */ +#define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */ +#define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */ +#define TIM_CLOCKSOURCE_ITR4 TIM_TS_ITR4 /*!< External clock source mode 1 (ITR4) */ +#define TIM_CLOCKSOURCE_ITR5 TIM_TS_ITR5 /*!< External clock source mode 1 (ITR5) */ +#define TIM_CLOCKSOURCE_ITR6 TIM_TS_ITR6 /*!< External clock source mode 1 (ITR6) */ +#define TIM_CLOCKSOURCE_ITR7 TIM_TS_ITR7 /*!< External clock source mode 1 (ITR7) */ +#define TIM_CLOCKSOURCE_ITR8 TIM_TS_ITR8 /*!< External clock source mode 1 (ITR8) */ +#define TIM_CLOCKSOURCE_ITR9 TIM_TS_ITR9 /*!< External clock source mode 1 (ITR9) */ +#define TIM_CLOCKSOURCE_ITR10 TIM_TS_ITR10 /*!< External clock source mode 1 (ITR10) */ +/** + * @} + */ + +/** @defgroup TIM_Clock_Polarity TIM Clock Polarity + * @{ + */ +#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ +#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ +#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ +#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ +#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ +/** + * @} + */ + +/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler + * @{ + */ +#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ +#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ +#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ +/** + * @} + */ + +/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity + * @{ + */ +#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ +#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ +/** + * @} + */ + +/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler + * @{ + */ +#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ +#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ +#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ +/** + * @} + */ + +/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state + * @{ + */ +#define TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ +#define TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ +/** + * @} + */ + +/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state + * @{ + */ +#define TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ +#define TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ +/** + * @} + */ +/** @defgroup TIM_Lock_level TIM Lock level + * @{ + */ +#define TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF */ +#define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ +#define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ +#define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ +/** + * @} + */ + +/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable + * @{ + */ +#define TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break input BRK is enabled */ +#define TIM_BREAK_DISABLE 0x00000000U /*!< Break input BRK is disabled */ +/** + * @} + */ + +/** @defgroup TIM_Break_Polarity TIM Break Input Polarity + * @{ + */ +#define TIM_BREAKPOLARITY_LOW 0x00000000U /*!< Break input BRK is active low */ +#define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */ +/** + * @} + */ + +/** @defgroup TIM_Break_Input_AF_Mode TIM Break Input Alternate Function Mode + * @{ + */ +#define TIM_BREAK_AFMODE_INPUT 0x00000000U /*!< Break input BRK in input mode */ +#define TIM_BREAK_AFMODE_BIDIRECTIONAL TIM_BDTR_BKBID /*!< Break input BRK in bidirectional mode */ +/** + * @} + */ + +/** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable + * @{ + */ +#define TIM_BREAK2_DISABLE 0x00000000U /*!< Break input BRK2 is disabled */ +#define TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break input BRK2 is enabled */ +/** + * @} + */ + +/** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity + * @{ + */ +#define TIM_BREAK2POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */ +#define TIM_BREAK2POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */ +/** + * @} + */ + +/** @defgroup TIM_Break2_Input_AF_Mode TIM Break2 Input Alternate Function Mode + * @{ + */ +#define TIM_BREAK2_AFMODE_INPUT 0x00000000U /*!< Break2 input BRK2 in input mode */ +#define TIM_BREAK2_AFMODE_BIDIRECTIONAL TIM_BDTR_BK2BID /*!< Break2 input BRK2 in bidirectional mode */ +/** + * @} + */ + +/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable + * @{ + */ +#define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ +#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) */ +/** + * @} + */ + +/** @defgroup TIM_Group_Channel5 TIM Group Channel 5 and Channel 1, 2 or 3 + * @{ + */ +#define TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */ +#define TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */ +#define TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */ +#define TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */ +/** + * @} + */ + +/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection + * @{ + */ +#define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */ +#define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */ +#define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */ +#define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */ +#define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */ +#define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */ +#define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */ +#define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */ +#define TIM_TRGO_ENCODER_CLK TIM_CR2_MMS_3 /*!< Encoder clock is used as trigger output(TRGO) */ +/** + * @} + */ + +/** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2) + * @{ + */ +#define TIM_TRGO2_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO2) */ +#define TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO2) */ +#define TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC1 (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC1REF TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC2REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC3REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC4REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC5REF TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC6REF (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC4REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges generate pulses on TRGO2 */ +#define TIM_TRGO2_OC6REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges generate pulses on TRGO2 */ +#define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges generate pulses on TRGO2 */ +#define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges generate pulses on TRGO2 */ +#define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */ +#define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */ +/** + * @} + */ + +/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode + * @{ + */ +#define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */ +#define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */ +/** + * @} + */ + +/** @defgroup TIM_Slave_Mode TIM Slave mode + * @{ + */ +#define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */ +#define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */ +#define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */ +#define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */ +#define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */ +#define TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode */ +#define TIM_SLAVEMODE_COMBINED_GATEDRESET (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_0) /*!< Combined gated + reset mode */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes + * @{ + */ +#define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */ +#define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */ +#define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */ +#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */ +#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */ +#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */ +#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */ +#define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */ +#define TIM_OCMODE_RETRIGERRABLE_OPM1 TIM_CCMR1_OC1M_3 /*!< Retrigerrable OPM mode 1 */ +#define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!< Retrigerrable OPM mode 2 */ +#define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 1 */ +#define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 2 */ +#define TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */ +#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */ +#define TIM_OCMODE_PULSE_ON_COMPARE (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1) /*!< Pulse on compare (CH3&CH4 only) */ +#define TIM_OCMODE_DIRECTION_OUTPUT (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0) /*!< Direction output (CH3&CH4 only) */ +/** + * @} + */ + +/** @defgroup TIM_Trigger_Selection TIM Trigger Selection + * @{ + */ +#define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */ +#define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */ +#define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */ +#define TIM_TS_ITR7 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 7 (ITR7) */ +#define TIM_TS_ITR8 (TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 8 (ITR8) */ +#define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */ +#define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */ +#define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */ +#define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */ +#define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */ +/** + * @} + */ + +/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity + * @{ + */ +#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ +#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ +#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ +#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ +#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ +/** + * @} + */ + +/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler + * @{ + */ +#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ +#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ +#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ +/** + * @} + */ + +/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection + * @{ + */ +#define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */ +#define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */ +/** + * @} + */ + +/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length + * @{ + */ +#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_19TRANSFERS 0x00001200U /*!< The transfer is done to 19 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_20TRANSFERS 0x00001300U /*!< The transfer is done to 20 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_21TRANSFERS 0x00001400U /*!< The transfer is done to 21 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_22TRANSFERS 0x00001500U /*!< The transfer is done to 22 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_23TRANSFERS 0x00001600U /*!< The transfer is done to 23 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_24TRANSFERS 0x00001700U /*!< The transfer is done to 24 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_25TRANSFERS 0x00001800U /*!< The transfer is done to 25 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_26TRANSFERS 0x00001900U /*!< The transfer is done to 26 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +/** + * @} + */ + +/** @defgroup DMA_Handle_index TIM DMA Handle Index + * @{ + */ +#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */ +#define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ +#define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ +#define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ +#define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ +#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */ +#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */ +/** + * @} + */ + +/** @defgroup Channel_CC_State TIM Capture/Compare Channel State + * @{ + */ +#define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */ +#define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */ +#define TIM_CCxN_ENABLE 0x00000004U /*!< Complementary output channel is enabled */ +#define TIM_CCxN_DISABLE 0x00000000U /*!< Complementary output channel is enabled */ +/** + * @} + */ + +/** @defgroup TIM_Break_System TIM Break System + * @{ + */ +#define TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal with Break Input of TIM1/16/17 */ +#define TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection with TIM1/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface */ +#define TIM_BREAK_SYSTEM_SRAM2_PARITY_ERROR SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM2_PARITY error signal with Break Input of TIM1/16/17 */ +#define TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/16/17 */ +/** + * @} + */ + +/** + * @} + */ +/* End of exported constants -------------------------------------------------*/ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup TIM_Exported_Macros TIM Exported Macros + * @{ + */ + +/** @brief Reset TIM handle state. + * @param __HANDLE__ TIM handle. + * @retval None + */ +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ + (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ + (__HANDLE__)->Base_MspInitCallback = NULL; \ + (__HANDLE__)->Base_MspDeInitCallback = NULL; \ + (__HANDLE__)->IC_MspInitCallback = NULL; \ + (__HANDLE__)->IC_MspDeInitCallback = NULL; \ + (__HANDLE__)->OC_MspInitCallback = NULL; \ + (__HANDLE__)->OC_MspDeInitCallback = NULL; \ + (__HANDLE__)->PWM_MspInitCallback = NULL; \ + (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ + (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ + (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ + (__HANDLE__)->Encoder_MspInitCallback = NULL; \ + (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ + (__HANDLE__)->HallSensor_MspInitCallback = NULL; \ + (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ + (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ + } while(0) +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @brief Enable the TIM peripheral. + * @param __HANDLE__ TIM handle + * @retval None + */ +#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) + +/** + * @brief Enable the TIM main Output. + * @param __HANDLE__ TIM handle + * @retval None + */ +#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) + +/** + * @brief Disable the TIM peripheral. + * @param __HANDLE__ TIM handle + * @retval None + */ +#define __HAL_TIM_DISABLE(__HANDLE__) \ + do { \ + if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ + { \ + if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ + { \ + (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ + } \ + } \ + } while(0) + +/** + * @brief Disable the TIM main Output. + * @param __HANDLE__ TIM handle + * @retval None + * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been + * disabled + */ +#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ + do { \ + if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ + { \ + if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ + { \ + (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ + } \ + } \ + } while(0) + +/** + * @brief Disable the TIM main Output. + * @param __HANDLE__ TIM handle + * @retval None + * @note The Main Output Enable of a timer instance is disabled unconditionally + */ +#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE) + +/** @brief Enable the specified TIM interrupt. + * @param __HANDLE__ specifies the TIM Handle. + * @param __INTERRUPT__ specifies the TIM interrupt source to enable. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @arg TIM_IT_IDX: Index interrupt + * @arg TIM_IT_DIR: Direction change interrupt + * @arg TIM_IT_IERR: Index error interrupt + * @arg TIM_IT_TERR: Transition error interrupt + * @retval None + */ +#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) + +/** @brief Disable the specified TIM interrupt. + * @param __HANDLE__ specifies the TIM Handle. + * @param __INTERRUPT__ specifies the TIM interrupt source to disable. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @arg TIM_IT_IDX: Index interrupt + * @arg TIM_IT_DIR: Direction change interrupt + * @arg TIM_IT_IERR: Index error interrupt + * @arg TIM_IT_TERR: Transition error interrupt + * @retval None + */ +#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) + +/** @brief Enable the specified DMA request. + * @param __HANDLE__ specifies the TIM Handle. + * @param __DMA__ specifies the TIM DMA request to enable. + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: Update DMA request + * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request + * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request + * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request + * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request + * @arg TIM_DMA_COM: Commutation DMA request + * @arg TIM_DMA_TRIGGER: Trigger DMA request + * @retval None + */ +#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) + +/** @brief Disable the specified DMA request. + * @param __HANDLE__ specifies the TIM Handle. + * @param __DMA__ specifies the TIM DMA request to disable. + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: Update DMA request + * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request + * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request + * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request + * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request + * @arg TIM_DMA_COM: Commutation DMA request + * @arg TIM_DMA_TRIGGER: Trigger DMA request + * @retval None + */ +#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) + +/** @brief Check whether the specified TIM interrupt flag is set or not. + * @param __HANDLE__ specifies the TIM Handle. + * @param __FLAG__ specifies the TIM interrupt flag to check. + * This parameter can be one of the following values: + * @arg TIM_FLAG_UPDATE: Update interrupt flag + * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag + * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag + * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag + * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag + * @arg TIM_FLAG_CC5: Compare 5 interrupt flag + * @arg TIM_FLAG_CC6: Compare 6 interrupt flag + * @arg TIM_FLAG_COM: Commutation interrupt flag + * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag + * @arg TIM_FLAG_BREAK: Break interrupt flag + * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag + * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag + * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag + * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag + * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag + * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag + * @arg TIM_FLAG_IDX: Index interrupt flag + * @arg TIM_FLAG_DIR: Direction change interrupt flag + * @arg TIM_FLAG_IERR: Index error interrupt flag + * @arg TIM_FLAG_TERR: Transition error interrupt flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) + +/** @brief Clear the specified TIM interrupt flag. + * @param __HANDLE__ specifies the TIM Handle. + * @param __FLAG__ specifies the TIM interrupt flag to clear. + * This parameter can be one of the following values: + * @arg TIM_FLAG_UPDATE: Update interrupt flag + * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag + * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag + * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag + * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag + * @arg TIM_FLAG_CC5: Compare 5 interrupt flag + * @arg TIM_FLAG_CC6: Compare 6 interrupt flag + * @arg TIM_FLAG_COM: Commutation interrupt flag + * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag + * @arg TIM_FLAG_BREAK: Break interrupt flag + * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag + * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag + * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag + * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag + * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag + * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag + * @arg TIM_FLAG_IDX: Index interrupt flag + * @arg TIM_FLAG_DIR: Direction change interrupt flag + * @arg TIM_FLAG_IERR: Index error interrupt flag + * @arg TIM_FLAG_TERR: Transition error interrupt flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) + +/** + * @brief Check whether the specified TIM interrupt source is enabled or not. + * @param __HANDLE__ TIM handle + * @param __INTERRUPT__ specifies the TIM interrupt source to check. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @arg TIM_IT_IDX: Index interrupt + * @arg TIM_IT_DIR: Direction change interrupt + * @arg TIM_IT_IERR: Index error interrupt + * @arg TIM_IT_TERR: Transition error interrupt + * @retval The state of TIM_IT (SET or RESET). + */ +#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \ + == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Clear the TIM interrupt pending bits. + * @param __HANDLE__ TIM handle + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @arg TIM_IT_IDX: Index interrupt + * @arg TIM_IT_DIR: Direction change interrupt + * @arg TIM_IT_IERR: Index error interrupt + * @arg TIM_IT_TERR: Transition error interrupt + * @retval None + */ +#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) + +/** + * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31). + * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read + * in an atomic way. + * @param __HANDLE__ TIM handle. + * @retval None +mode. + */ +#define __HAL_TIM_UIFREMAP_ENABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 |= TIM_CR1_UIFREMAP)) + +/** + * @brief Disable update interrupt flag (UIF) remapping. + * @param __HANDLE__ TIM handle. + * @retval None +mode. + */ +#define __HAL_TIM_UIFREMAP_DISABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_UIFREMAP)) + +/** + * @brief Get update interrupt flag (UIF) copy status. + * @param __COUNTER__ Counter value. + * @retval The state of UIFCPY (TRUE or FALSE). +mode. + */ +#define __HAL_TIM_GET_UIFCPY(__COUNTER__) (((__COUNTER__) & (TIM_CNT_UIFCPY)) == (TIM_CNT_UIFCPY)) + +/** + * @brief Indicates whether or not the TIM Counter is used as downcounter. + * @param __HANDLE__ TIM handle. + * @retval False (Counter used as upcounter) or True (Counter used as downcounter) + * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode + * or Encoder mode. + */ +#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) + +/** + * @brief Set the TIM Prescaler on runtime. + * @param __HANDLE__ TIM handle. + * @param __PRESC__ specifies the Prescaler new value. + * @retval None + */ +#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) + +/** + * @brief Set the TIM Counter Register value on runtime. + * Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in + * case of 32 bits counter TIM instance. + * Bit 31 of CNT can be enabled/disabled using __HAL_TIM_UIFREMAP_ENABLE()/__HAL_TIM_UIFREMAP_DISABLE() macros. + * @param __HANDLE__ TIM handle. + * @param __COUNTER__ specifies the Counter register new value. + * @retval None + */ +#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) + +/** + * @brief Get the TIM Counter Register value on runtime. + * @param __HANDLE__ TIM handle. + * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) + */ +#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT) + +/** + * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function. + * @param __HANDLE__ TIM handle. + * @param __AUTORELOAD__ specifies the Counter register new value. + * @retval None + */ +#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ + do{ \ + (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ + (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ + } while(0) + +/** + * @brief Get the TIM Autoreload Register value on runtime. + * @param __HANDLE__ TIM handle. + * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) + */ +#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR) + +/** + * @brief Set the TIM Clock Division value on runtime without calling another time any Init function. + * @param __HANDLE__ TIM handle. + * @param __CKD__ specifies the clock division value. + * This parameter can be one of the following value: + * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT + * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT + * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT + * @retval None + */ +#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ + do{ \ + (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \ + (__HANDLE__)->Instance->CR1 |= (__CKD__); \ + (__HANDLE__)->Init.ClockDivision = (__CKD__); \ + } while(0) + +/** + * @brief Get the TIM Clock Division value on runtime. + * @param __HANDLE__ TIM handle. + * @retval The clock division can be one of the following values: + * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT + * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT + * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT + */ +#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) + +/** + * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() + * function. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param __ICPSC__ specifies the Input Capture4 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ + do{ \ + TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ + TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ + } while(0) + +/** + * @brief Get the TIM Input Capture prescaler on runtime. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: get input capture 1 prescaler value + * @arg TIM_CHANNEL_2: get input capture 2 prescaler value + * @arg TIM_CHANNEL_3: get input capture 3 prescaler value + * @arg TIM_CHANNEL_4: get input capture 4 prescaler value + * @retval The input capture prescaler can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + */ +#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ + (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U) + +/** + * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @param __COMPARE__ specifies the Capture Compare register new value. + * @retval None + */ +#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\ + ((__HANDLE__)->Instance->CCR6 = (__COMPARE__))) + +/** + * @brief Get the TIM Capture Compare Register value on runtime. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channel associated with the capture compare register + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: get capture/compare 1 register value + * @arg TIM_CHANNEL_2: get capture/compare 2 register value + * @arg TIM_CHANNEL_3: get capture/compare 3 register value + * @arg TIM_CHANNEL_4: get capture/compare 4 register value + * @arg TIM_CHANNEL_5: get capture/compare 5 register value + * @arg TIM_CHANNEL_6: get capture/compare 6 register value + * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) + */ +#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\ + ((__HANDLE__)->Instance->CCR6)) + +/** + * @brief Set the TIM Output compare preload. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval None + */ +#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\ + ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE)) + +/** + * @brief Reset the TIM Output compare preload. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval None + */ +#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) :\ + ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE)) + +/** + * @brief Enable fast mode for a given channel. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @note When fast mode is enabled an active edge on the trigger input acts + * like a compare match on CCx output. Delay to sample the trigger + * input and to activate CCx output is reduced to 3 clock cycles. + * @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode. + * @retval None + */ +#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5FE) :\ + ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6FE)) + +/** + * @brief Disable fast mode for a given channel. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @note When fast mode is disabled CCx output behaves normally depending + * on counter and CCRx values even when the trigger is ON. The minimum + * delay to activate CCx output when an active edge occurs on the + * trigger input is 5 clock cycles. + * @retval None + */ +#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) :\ + ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE)) + +/** + * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register. + * @param __HANDLE__ TIM handle. + * @note When the URS bit of the TIMx_CR1 register is set, only counter + * overflow/underflow generates an update interrupt or DMA request (if + * enabled) + * @retval None + */ +#define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS) + +/** + * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register. + * @param __HANDLE__ TIM handle. + * @note When the URS bit of the TIMx_CR1 register is reset, any of the + * following events generate an update interrupt or DMA request (if + * enabled): + * _ Counter overflow underflow + * _ Setting the UG bit + * _ Update generation through the slave mode controller + * @retval None + */ +#define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS) + +/** + * @brief Set the TIM Capture x input polarity on runtime. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param __POLARITY__ Polarity for TIx source + * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge + * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge + * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge + * @retval None + */ +#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ + do{ \ + TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ + TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ + }while(0) + +/** @brief Select the Capture/compare DMA request source. + * @param __HANDLE__ specifies the TIM Handle. + * @param __CCDMA__ specifies Capture/compare DMA request source + * This parameter can be one of the following values: + * @arg TIM_CCDMAREQUEST_CC: CCx DMA request generated on Capture/Compare event + * @arg TIM_CCDMAREQUEST_UPDATE: CCx DMA request generated on Update event + * @retval None + */ +#define __HAL_TIM_SELECT_CCDMAREQUEST(__HANDLE__, __CCDMA__) \ + MODIFY_REG((__HANDLE__)->Instance->CR2, TIM_CR2_CCDS, (__CCDMA__)) + +/** + * @} + */ +/* End of exported macros ----------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup TIM_Private_Constants TIM Private Constants + * @{ + */ +/* The counter of a timer instance is disabled only if all the CCx and CCxN + channels have been disabled */ +#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) +#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE | TIM_CCER_CC4NE)) +/** + * @} + */ +/* End of private constants --------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup TIM_Private_Macros TIM Private Macros + * @{ + */ +#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) || \ + ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP1) || \ + ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP2) || \ + ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE)) + +#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ + ((__BASE__) == TIM_DMABASE_CR2) || \ + ((__BASE__) == TIM_DMABASE_SMCR) || \ + ((__BASE__) == TIM_DMABASE_DIER) || \ + ((__BASE__) == TIM_DMABASE_SR) || \ + ((__BASE__) == TIM_DMABASE_EGR) || \ + ((__BASE__) == TIM_DMABASE_CCMR1) || \ + ((__BASE__) == TIM_DMABASE_CCMR2) || \ + ((__BASE__) == TIM_DMABASE_CCER) || \ + ((__BASE__) == TIM_DMABASE_CNT) || \ + ((__BASE__) == TIM_DMABASE_PSC) || \ + ((__BASE__) == TIM_DMABASE_ARR) || \ + ((__BASE__) == TIM_DMABASE_RCR) || \ + ((__BASE__) == TIM_DMABASE_CCR1) || \ + ((__BASE__) == TIM_DMABASE_CCR2) || \ + ((__BASE__) == TIM_DMABASE_CCR3) || \ + ((__BASE__) == TIM_DMABASE_CCR4) || \ + ((__BASE__) == TIM_DMABASE_BDTR) || \ + ((__BASE__) == TIM_DMABASE_CCMR3) || \ + ((__BASE__) == TIM_DMABASE_CCR5) || \ + ((__BASE__) == TIM_DMABASE_CCR6) || \ + ((__BASE__) == TIM_DMABASE_AF1) || \ + ((__BASE__) == TIM_DMABASE_AF2) || \ + ((__BASE__) == TIM_DMABASE_TISEL) || \ + ((__BASE__) == TIM_DMABASE_DTR2) || \ + ((__BASE__) == TIM_DMABASE_ECR) || \ + ((__BASE__) == TIM_DMABASE_OR)) + +#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) + +#define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \ + ((__MODE__) == TIM_COUNTERMODE_DOWN) || \ + ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \ + ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \ + ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) + +#define IS_TIM_UIFREMAP_MODE(__MODE__) (((__MODE__) == TIM_UIFREMAP_DISABLE) || \ + ((__MODE__) == TIM_UIFREMAP_ENABLE)) + +#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \ + ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ + ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) + +#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \ + ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE)) + +#define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \ + ((__STATE__) == TIM_OCFAST_ENABLE)) + +#define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \ + ((__POLARITY__) == TIM_OCPOLARITY_LOW)) + +#define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \ + ((__POLARITY__) == TIM_OCNPOLARITY_LOW)) + +#define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \ + ((__STATE__) == TIM_OCIDLESTATE_RESET)) + +#define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \ + ((__STATE__) == TIM_OCNIDLESTATE_RESET)) + +#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \ + ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING)) + +#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \ + ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \ + ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE)) + +#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \ + ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \ + ((__SELECTION__) == TIM_ICSELECTION_TRC)) + +#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \ + ((__PRESCALER__) == TIM_ICPSC_DIV2) || \ + ((__PRESCALER__) == TIM_ICPSC_DIV4) || \ + ((__PRESCALER__) == TIM_ICPSC_DIV8)) + +#define IS_TIM_CCX_CHANNEL(__INSTANCE__, __CHANNEL__) (IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) && \ + ((__CHANNEL__) != (TIM_CHANNEL_5)) && \ + ((__CHANNEL__) != (TIM_CHANNEL_6))) + +#define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \ + ((__MODE__) == TIM_OPMODE_REPETITIVE)) + +#define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \ + ((__MODE__) == TIM_ENCODERMODE_TI2) || \ + ((__MODE__) == TIM_ENCODERMODE_TI12) || \ + ((__MODE__) == TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2) || \ + ((__MODE__) == TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1) || \ + ((__MODE__) == TIM_ENCODERMODE_DIRECTIONALCLOCK_X2) || \ + ((__MODE__) == TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12) || \ + ((__MODE__) == TIM_ENCODERMODE_X1_TI1) || \ + ((__MODE__) == TIM_ENCODERMODE_X1_TI2)) + +#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) + +#define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ + ((__CHANNEL__) == TIM_CHANNEL_2) || \ + ((__CHANNEL__) == TIM_CHANNEL_3) || \ + ((__CHANNEL__) == TIM_CHANNEL_4) || \ + ((__CHANNEL__) == TIM_CHANNEL_5) || \ + ((__CHANNEL__) == TIM_CHANNEL_6) || \ + ((__CHANNEL__) == TIM_CHANNEL_ALL)) + +#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ + ((__CHANNEL__) == TIM_CHANNEL_2)) + +#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? \ + (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : \ + ((__PERIOD__) > 0U)) + +#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ + ((__CHANNEL__) == TIM_CHANNEL_2) || \ + ((__CHANNEL__) == TIM_CHANNEL_3) || \ + ((__CHANNEL__) == TIM_CHANNEL_4)) + +#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)) + +#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE)) + +#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \ + ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \ + ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \ + ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8)) + +#define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ + ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) + +#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \ + ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \ + ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \ + ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8)) + +#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \ + ((__STATE__) == TIM_OSSR_DISABLE)) + +#define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \ + ((__STATE__) == TIM_OSSI_DISABLE)) + +#define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \ + ((__LEVEL__) == TIM_LOCKLEVEL_1) || \ + ((__LEVEL__) == TIM_LOCKLEVEL_2) || \ + ((__LEVEL__) == TIM_LOCKLEVEL_3)) + +#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL) + +#define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \ + ((__STATE__) == TIM_BREAK_DISABLE)) + +#define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \ + ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH)) + +#define IS_TIM_BREAK_AFMODE(__AFMODE__) (((__AFMODE__) == TIM_BREAK_AFMODE_INPUT) || \ + ((__AFMODE__) == TIM_BREAK_AFMODE_BIDIRECTIONAL)) + + +#define IS_TIM_BREAK2_STATE(__STATE__) (((__STATE__) == TIM_BREAK2_ENABLE) || \ + ((__STATE__) == TIM_BREAK2_DISABLE)) + +#define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \ + ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH)) + +#define IS_TIM_BREAK2_AFMODE(__AFMODE__) (((__AFMODE__) == TIM_BREAK2_AFMODE_INPUT) || \ + ((__AFMODE__) == TIM_BREAK2_AFMODE_BIDIRECTIONAL)) + + +#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \ + ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE)) + +#define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U)) + +#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \ + ((__SOURCE__) == TIM_TRGO_ENABLE) || \ + ((__SOURCE__) == TIM_TRGO_UPDATE) || \ + ((__SOURCE__) == TIM_TRGO_OC1) || \ + ((__SOURCE__) == TIM_TRGO_OC1REF) || \ + ((__SOURCE__) == TIM_TRGO_OC2REF) || \ + ((__SOURCE__) == TIM_TRGO_OC3REF) || \ + ((__SOURCE__) == TIM_TRGO_OC4REF) || \ + ((__SOURCE__) == TIM_TRGO_ENCODER_CLK)) + +#define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET) || \ + ((__SOURCE__) == TIM_TRGO2_ENABLE) || \ + ((__SOURCE__) == TIM_TRGO2_UPDATE) || \ + ((__SOURCE__) == TIM_TRGO2_OC1) || \ + ((__SOURCE__) == TIM_TRGO2_OC1REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC2REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC3REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC3REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC4REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC5REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC6REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING) || \ + ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING) || \ + ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \ + ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \ + ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \ + ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING)) + +#define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \ + ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE)) + +#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \ + ((__MODE__) == TIM_SLAVEMODE_RESET) || \ + ((__MODE__) == TIM_SLAVEMODE_GATED) || \ + ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \ + ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \ + ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER) || \ + ((__MODE__) == TIM_SLAVEMODE_COMBINED_GATEDRESET)) + +#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \ + ((__MODE__) == TIM_OCMODE_PWM2) || \ + ((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \ + ((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \ + ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1) || \ + ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2)) + +#define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \ + ((__MODE__) == TIM_OCMODE_ACTIVE) || \ + ((__MODE__) == TIM_OCMODE_INACTIVE) || \ + ((__MODE__) == TIM_OCMODE_TOGGLE) || \ + ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \ + ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE) || \ + ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \ + ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2) || \ + ((__MODE__) == TIM_OCMODE_DIRECTION_OUTPUT) || \ + ((__MODE__) == TIM_OCMODE_PULSE_ON_COMPARE)) + +#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_NONE)) + +#define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE )) + +#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \ + ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \ + ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \ + ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8)) + +#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \ + ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) + +#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_19TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_20TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_21TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_22TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_23TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_24TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_25TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_26TRANSFERS)) + +#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U)) + +#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU) + +#define IS_TIM_BREAK_SYSTEM(__CONFIG__) (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC) || \ + ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD) || \ + ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM2_PARITY_ERROR) || \ + ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP)) + +#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) (((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) || \ + ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) + +#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ + ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) + +#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\ + ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC)) + +#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ + ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U)))) + +#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ + ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) + +#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\ + (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? (__HANDLE__)->ChannelState[3] :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? (__HANDLE__)->ChannelState[4] :\ + (__HANDLE__)->ChannelState[5]) + +#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__)) :\ + ((__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__))) + +#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ + (__HANDLE__)->ChannelState[0] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[1] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[2] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[3] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[4] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[5] = \ + (__CHANNEL_STATE__); \ + } while(0) + +#define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\ + (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\ + (__HANDLE__)->ChannelNState[3]) + +#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\ + ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__))) + +#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ + (__HANDLE__)->ChannelNState[0] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[1] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[2] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[3] = \ + (__CHANNEL_STATE__); \ + } while(0) + +/** + * @} + */ +/* End of private macros -----------------------------------------------------*/ + +/* Include TIM HAL Extended module */ +#include "stm32wbaxx_hal_tim_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup TIM_Exported_Functions TIM Exported Functions + * @{ + */ + +/** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions + * @brief Time Base functions + * @{ + */ +/* Time Base functions ********************************************************/ +HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions + * @brief TIM Output Compare functions + * @{ + */ +/* Timer Output Compare functions *********************************************/ +HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length); +HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions + * @brief TIM PWM functions + * @{ + */ +/* Timer PWM functions ********************************************************/ +HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length); +HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions + * @brief TIM Input Capture functions + * @{ + */ +/* Timer Input Capture functions **********************************************/ +HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions + * @brief TIM One Pulse functions + * @{ + */ +/* Timer One Pulse functions **************************************************/ +HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); +HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions + * @brief TIM Encoder functions + * @{ + */ +/* Timer Encoder functions ****************************************************/ +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig); +HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, + uint32_t *pData2, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management + * @brief IRQ handler management + * @{ + */ +/* Interrupt Handler functions ***********************************************/ +void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions + * @brief Peripheral Control functions + * @{ + */ +/* Control functions *********************************************************/ +HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, + uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, + uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, + uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, + uint32_t OutputChannel, uint32_t InputChannel); +HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, + const TIM_ClearInputConfigTypeDef *sClearInputConfig, + uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig); +HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, + uint32_t BurstLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); +HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); +uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions + * @brief TIM Callbacks functions + * @{ + */ +/* Callback in non blocking modes (Interrupt and DMA) *************************/ +void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, + pTIM_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions + * @brief Peripheral State functions + * @{ + */ +/* Peripheral State functions ************************************************/ +HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim); + +/* Peripheral Channel state functions ************************************************/ +HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim); +HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** + * @} + */ +/* End of exported functions -------------------------------------------------*/ + +/* Private functions----------------------------------------------------------*/ +/** @defgroup TIM_Private_Functions TIM Private Functions + * @{ + */ +void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure); +void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); +void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, + uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); + +void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma); +void TIM_DMAError(DMA_HandleTypeDef *hdma); +void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); +void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma); +void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState); +HAL_StatusTypeDef TIM_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t src, uint32_t dst, + uint32_t length); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +void TIM_ResetCallback(TIM_HandleTypeDef *htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ +/* End of private functions --------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WBAxx_HAL_TIM_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_tim_ex.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_tim_ex.h new file mode 100644 index 0000000000..bb36840b37 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_tim_ex.h @@ -0,0 +1,808 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_tim_ex.h + * @author MCD Application Team + * @brief Header file of TIM HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_HAL_TIM_EX_H +#define STM32WBAxx_HAL_TIM_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal_def.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @addtogroup TIMEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types + * @{ + */ + +/** + * @brief TIM Hall sensor Configuration Structure definition + */ + +typedef struct +{ + uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t IC1Filter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + + uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ +} TIM_HallSensor_InitTypeDef; + +/** + * @brief TIM Break/Break2 input configuration + */ +typedef struct +{ + uint32_t Source; /*!< Specifies the source of the timer break input. + This parameter can be a value of @ref TIMEx_Break_Input_Source */ + uint32_t Enable; /*!< Specifies whether or not the break input source is enabled. + This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */ + uint32_t Polarity; /*!< Specifies the break input source polarity. + This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity */ +} TIMEx_BreakInputConfigTypeDef; + +/** + * @brief TIM Encoder index configuration + */ +typedef struct +{ + uint32_t Polarity; /*!< TIM Encoder index polarity.This parameter can be a value of @ref TIMEx_Encoder_Index_Polarity */ + + uint32_t Prescaler; /*!< TIM Encoder index prescaler.This parameter can be a value of @ref TIMEx_Encoder_Index_Prescaler */ + + uint32_t Filter; /*!< TIM Encoder index filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + + uint32_t Blanking; /*!< Specifies whether or not the encoder index event is conditioned by TI3 or TI4 input.This parameter can be a value of @ref TIMEx_Encoder_Index_Blanking */ + + FunctionalState FirstIndexEnable; /*!< Specifies whether or not the encoder first index is enabled.This parameter value can be ENABLE or DISABLE. */ + + uint32_t Position; /*!< Specifies in which AB input configuration the index event resets the counter.This parameter can be a value of @ref TIMEx_Encoder_Index_Position */ + + uint32_t Direction; /*!< Specifies in which counter direction the index event resets the counter.This parameter can be a value of @ref TIMEx_Encoder_Index_Direction */ + +} TIMEx_EncoderIndexConfigTypeDef; + +/** + * @} + */ +/* End of exported types -----------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants + * @{ + */ + +/** @defgroup TIMEx_Remap TIM Extended Remapping + * @{ + */ +#define TIM_TIM1_ETR_GPIO 0x00000000UL /*!< TIM1_ETR is not connected to I/O */ +#define TIM_TIM1_ETR_COMP1 TIM_AF1_ETRSEL_0 /*!< TIM1_ETR is connected to COMP1 output */ +#define TIM_TIM1_ETR_COMP2 TIM_AF1_ETRSEL_1 /*!< TIM1_ETR is connected to COMP2 output */ +#define TIM_TIM1_ETR_HSI TIM_AF1_ETRSEL_2 /*!< TIM1_ETR is connected to HSI */ +#define TIM_TIM1_ETR_ADC4_AWD1 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC4 AWD1 */ +#define TIM_TIM1_ETR_ADC4_AWD2 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2) /*!< TIM1_ETR is connected to ADC4 AWD2 */ +#define TIM_TIM1_ETR_ADC4_AWD3 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC4 AWD3 */ + +#define TIM_TIM2_ETR_GPIO 0x00000000UL /*!< TIM2_ETR is not connected to I/O */ +#define TIM_TIM2_ETR_COMP1 TIM_AF1_ETRSEL_0 /*!< TIM2_ETR is connected to COMP1 output */ +#define TIM_TIM2_ETR_COMP2 TIM_AF1_ETRSEL_1 /*!< TIM2_ETR is connected to COMP2 output */ +#define TIM_TIM2_ETR_HSI TIM_AF1_ETRSEL_2 /*!< TIM2_ETR is connected to HSI */ +#define TIM_TIM2_ETR_TIM3_ETR TIM_AF1_ETRSEL_3 /*!< TIM2_ETR is connected to TIM3 ETR */ +#define TIM_TIM2_ETR_LSE (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to LSE */ + +#define TIM_TIM3_ETR_GPIO 0x00000000UL /*!< TIM3_ETR is not connected to I/O */ +#define TIM_TIM3_ETR_COMP1 TIM_AF1_ETRSEL_0 /*!< TIM3_ETR is connected to COMP1 output */ +#define TIM_TIM3_ETR_COMP2 TIM_AF1_ETRSEL_1 /*!< TIM3_ETR is connected to COMP2 output */ +#define TIM_TIM3_ETR_HSI TIM_AF1_ETRSEL_2 /*!< TIM3_ETR is connected to HSI */ +#define TIM_TIM3_ETR_TIM2_ETR TIM_AF1_ETRSEL_3 /*!< TIM3_ETR is connected to TIM2 ETR */ +#define TIM_TIM3_ETR_ADC4_AWD1 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1| TIM_AF1_ETRSEL_0) /*!< TIM3_ETR is connected to ADC4 AWD1 */ +#define TIM_TIM3_ETR_ADC4_AWD2 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2) /*!< TIM3_ETR is connected to ADC4 AWD2 */ +#define TIM_TIM3_ETR_ADC4_AWD3 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) /*!< TIM3_ETR is connected to ADC4 AWD3 */ +/** + * @} + */ + +/** @defgroup TIMEx_Break_Input TIM Extended Break input + * @{ + */ +#define TIM_BREAKINPUT_BRK 0x00000001U /*!< Timer break input */ +#define TIM_BREAKINPUT_BRK2 0x00000002U /*!< Timer break2 input */ +/** + * @} + */ + +/** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source + * @{ + */ +#define TIM_BREAKINPUTSOURCE_BKIN 0x00000001U /*!< An external source (GPIO) is connected to the BKIN pin */ +#define TIM_BREAKINPUTSOURCE_COMP1 0x00000002U /*!< The COMP1 output is connected to the break input */ +#define TIM_BREAKINPUTSOURCE_COMP2 0x00000004U /*!< The COMP2 output is connected to the break input */ +/** + * @} + */ + +/** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling + * @{ + */ +#define TIM_BREAKINPUTSOURCE_DISABLE 0x00000000U /*!< Break input source is disabled */ +#define TIM_BREAKINPUTSOURCE_ENABLE 0x00000001U /*!< Break input source is enabled */ +/** + * @} + */ + +/** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity + * @{ + */ +#define TIM_BREAKINPUTSOURCE_POLARITY_LOW 0x00000001U /*!< Break input source is active low */ +#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH 0x00000000U /*!< Break input source is active_high */ +/** + * @} + */ + +/** @defgroup TIMEx_Timer_Input_Selection TIM Extended Timer input selection + * @{ + */ +#define TIM_TIM1_TI1_GPIO 0x00000000UL /*!< TIM1_TI1 is connected to GPIO */ +#define TIM_TIM1_TI1_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM1_TI1 is connected to COMP1 OUT */ +#define TIM_TIM1_TI1_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM1_TI1 is connected to COMP2 OUT */ +#define TIM_TIM1_TI2_GPIO 0x00000000UL /*!< TIM1_TI2 is connected to GPIO */ +#define TIM_TIM1_TI3_GPIO 0x00000000UL /*!< TIM1_TI3 is connected to GPIO */ +#define TIM_TIM1_TI4_GPIO 0x00000000UL /*!< TIM1_TI4 is connected to GPIO */ + +#define TIM_TIM2_TI1_GPIO 0x00000000UL /*!< TIM2_TI1 is connected to GPIO */ +#define TIM_TIM2_TI1_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM2_TI1 is connected to COMP1 OUT */ +#define TIM_TIM2_TI1_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM2_TI1 is connected to COMP2 OUT */ +#define TIM_TIM2_TI2_GPIO 0x00000000UL /*!< TIM2_TI2 is connected to GPIO */ +#define TIM_TIM2_TI2_COMP1 TIM_TISEL_TI2SEL_0 /*!< TIM2_TI2 is connected to COMP1 OUT */ +#define TIM_TIM2_TI2_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM2_TI2 is connected to COMP2 OUT */ +#define TIM_TIM2_TI3_GPIO 0x00000000UL /*!< TIM2_TI3 is connected to GPIO */ +#define TIM_TIM2_TI4_GPIO 0x00000000UL /*!< TIM2_TI4 is connected to GPIO */ +#define TIM_TIM2_TI4_COMP1 TIM_TISEL_TI4SEL_0 /*!< TIM2_TI4 is connected to COMP1 OUT */ +#define TIM_TIM2_TI4_COMP2 TIM_TISEL_TI4SEL_1 /*!< TIM2_TI4 is connected to COMP2 OUT */ + +#define TIM_TIM3_TI1_GPIO 0x00000000UL /*!< TIM3_TI1 is connected to GPIO */ +#define TIM_TIM3_TI1_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM3_TI1 is connected to COMP1 OUT */ +#define TIM_TIM3_TI1_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM3_TI1 is connected to COMP2 OUT */ +#define TIM_TIM3_TI2_GPIO 0x00000000UL /*!< TIM3_TI2 is connected to GPIO */ +#define TIM_TIM3_TI2_COMP1 TIM_TISEL_TI2SEL_0 /*!< TIM3_TI2 is connected to COMP1 OUT */ +#define TIM_TIM3_TI2_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM3_TI2 is connected to COMP2 OUT */ +#define TIM_TIM3_TI3_GPIO 0x00000000UL /*!< TIM3_TI3 is connected to GPIO */ +#define TIM_TIM3_TI4_GPIO 0x00000000UL /*!< TIM3_TI4 is connected to GPIO */ + +#define TIM_TIM16_TI1_GPIO 0x00000000UL /*!< TIM16_TI1 is connected to GPIO */ +#define TIM_TIM16_TI1_MCO TIM_TISEL_TI1SEL_1 /*!< TIM16_TI1 is connected to MCO */ +#define TIM_TIM16_TI1_HSE_DIV32 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM16_TI1 is connected to HSE/32 */ +#define TIM_TIM16_TI1_RTC_WKUP TIM_TISEL_TI1SEL_2 /*!< TIM16_TI1 is connected to RTC Wakeup */ +#define TIM_TIM16_TI1_LSE (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM16_TI1 is connected to LSE */ +#define TIM_TIM16_TI1_LSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /*!< TIM16_TI1 is connected to LSI */ +#define TIM_TIM16_TI1_HSI_256 (TIM_TISEL_TI1SEL_3 | TIM_TISEL_TI1SEL_0) /*!< TIM16_TI1 is connected to HSI/256 */ + +#define TIM_TIM17_TI1_GPIO 0x00000000UL /*!< TIM17_TI1 is connected to GPIO */ +#define TIM_TIM17_TI1_MCO TIM_TISEL_TI1SEL_1 /*!< TIM17_TI1 is connected to MCO */ +#define TIM_TIM17_TI1_HSE_DIV32 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM17_TI1 is connected to HSE/32 */ +#define TIM_TIM17_TI1_RTC_WKUP TIM_TISEL_TI1SEL_2 /*!< TIM17_TI1 is connected to RTC Wakeup */ +#define TIM_TIM17_TI1_LSE (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM17_TI1 is connected to LSE */ +#define TIM_TIM17_TI1_LSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /*!< TIM17_TI1 is connected to LSI */ +#define TIM_TIM17_TI1_HSI_256 (TIM_TISEL_TI1SEL_3 | TIM_TISEL_TI1SEL_0) /*!< TIM17_TI1 is connected to HSI/256 */ +/** + * @} + */ + +/** @defgroup TIMEx_SMS_Preload_Enable TIM Extended Bitfield SMS preload enabling + * @{ + */ +#define TIM_SMS_PRELOAD_SOURCE_UPDATE 0x00000000U /*!< Prelaod of SMS bitfield is disabled */ +#define TIM_SMS_PRELOAD_SOURCE_INDEX TIM_SMCR_SMSPS /*!< Preload of SMS bitfield is enabled */ +/** + * @} + */ + +/** @defgroup TIMEx_Encoder_Index_Blanking TIM Extended Encoder index blanking + * @{ + */ +#define TIM_ENCODERINDEX_BLANKING_DISABLE 0x00000000U /*!< Encoder index blanking is disabled */ +#define TIM_ENCODERINDEX_BLANKING_TI3 TIM_ECR_IBLK_0 /*!< Encoder index blanking is enabled on TI3 */ +#define TIM_ENCODERINDEX_BLANKING_TI4 TIM_ECR_IBLK_1 /*!< Encoder index blanking is enabled on TI4 */ + +/** + * @} + */ + +/** @defgroup TIMEx_Encoder_Index_Position TIM Extended Encoder index position + * @{ + */ +#define TIM_ENCODERINDEX_POSITION_00 0x00000000U /*!< Encoder index position is AB=00 */ +#define TIM_ENCODERINDEX_POSITION_01 TIM_ECR_IPOS_0 /*!< Encoder index position is AB=01 */ +#define TIM_ENCODERINDEX_POSITION_10 TIM_ECR_IPOS_1 /*!< Encoder index position is AB=10 */ +#define TIM_ENCODERINDEX_POSITION_11 (TIM_ECR_IPOS_1 | TIM_ECR_IPOS_0) /*!< Encoder index position is AB=11 */ +#define TIM_ENCODERINDEX_POSITION_0 0x00000000U /*!< In directional clock mode or clock plus direction mode, index resets the counter when clock is 0 */ +#define TIM_ENCODERINDEX_POSITION_1 TIM_ECR_IPOS_0 /*!< In directional clock mode or clock plus direction mode, index resets the counter when clock is 1 */ +/** + * @} + */ + +/** @defgroup TIMEx_Encoder_Index_Direction TIM Extended Encoder index direction + * @{ + */ +#define TIM_ENCODERINDEX_DIRECTION_UP_DOWN 0x00000000U /*!< Index resets the counter whatever the direction */ +#define TIM_ENCODERINDEX_DIRECTION_UP TIM_ECR_IDIR_0 /*!< Index resets the counter when up-counting only */ +#define TIM_ENCODERINDEX_DIRECTION_DOWN TIM_ECR_IDIR_1 /*!< Index resets the counter when down-counting only */ +/** + * @} + */ + +/** @defgroup TIMEx_Encoder_Index_Polarity TIM Extended Encoder index polarity + * @{ + */ +#define TIM_ENCODERINDEX_POLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ +#define TIM_ENCODERINDEX_POLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ +/** + * @} + */ + +/** @defgroup TIMEx_Encoder_Index_Prescaler TIM Extended Encodder index prescaler + * @{ + */ +#define TIM_ENCODERINDEX_PRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_ENCODERINDEX_PRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ +#define TIM_ENCODERINDEX_PRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ +#define TIM_ENCODERINDEX_PRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ +/** + * @} + */ + +/** + * @} + */ +/* End of exported constants -------------------------------------------------*/ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros + * @{ + */ + +/** + * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency. + * @note ex: @ref __HAL_TIM_CALC_PSC(80000000, 1000000); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __CNTCLK__ counter clock frequency (in Hz) + * @retval Prescaler value (between Min_Data=0 and Max_Data=65535) + */ +#define __HAL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \ + ((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1U) : 0U + +/** + * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency. + * @note ex: @ref __HAL_TIM_CALC_PERIOD(1000000, 0, 10000); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __PSC__ prescaler + * @param __FREQ__ output signal frequency (in Hz) + * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) + */ +#define __HAL_TIM_CALC_PERIOD(__TIMCLK__, __PSC__, __FREQ__) \ + (((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) - 1U) : 0U + +/** + * @brief HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required + * output signal frequency. + * @note ex: @ref __HAL_TIM_CALC_PERIOD_DITHER(1000000, 0, 10000); + * @note This macro should be used only if dithering is already enabled + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __PSC__ prescaler + * @param __FREQ__ output signal frequency (in Hz) + * @retval Auto-reload value (between Min_Data=0 and Max_Data=65519) + */ +#define __HAL_TIM_CALC_PERIOD_DITHER(__TIMCLK__, __PSC__, __FREQ__) \ + (((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? \ + (uint32_t)(((uint64_t)(__TIMCLK__)*16/((__FREQ__) * ((__PSC__) + 1U)) - 16U)) : 0U + +/** + * @brief HELPER macro calculating the compare value required to achieve the required timer output compare + * active/inactive delay. + * @note ex: @ref __HAL_TIM_CALC_PULSE(1000000, 0, 10); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __PSC__ prescaler + * @param __DELAY__ timer output compare active/inactive delay (in us) + * @retval Compare value (between Min_Data=0 and Max_Data=65535) + */ +#define __HAL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__) \ + ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \ + / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U)))) + +/** + * @brief HELPER macro calculating the compare value, with dithering feature enabled, to achieve the required timer + * output compare active/inactive delay. + * @note ex: @ref __HAL_TIM_CALC_PULSE_DITHER(1000000, 0, 10); + * @note This macro should be used only if dithering is already enabled + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __PSC__ prescaler + * @param __DELAY__ timer output compare active/inactive delay (in us) + * @retval Compare value (between Min_Data=0 and Max_Data=65519) + */ +#define __HAL_TIM_CALC_PULSE_DITHER(__TIMCLK__, __PSC__, __DELAY__) \ + ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__) * 16U) \ + / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U)))) + +/** + * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration + * (when the timer operates in one pulse mode). + * @note ex: @ref __HAL_TIM_CALC_PERIOD_BY_DELAY(1000000, 0, 10, 20); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __PSC__ prescaler + * @param __DELAY__ timer output compare active/inactive delay (in us) + * @param __PULSE__ pulse duration (in us) + * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) + */ +#define __HAL_TIM_CALC_PERIOD_BY_DELAY(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \ + ((uint32_t)(__HAL_TIM_CALC_PULSE((__TIMCLK__), (__PSC__), (__PULSE__)) \ + + __HAL_TIM_CALC_PULSE((__TIMCLK__), (__PSC__), (__DELAY__)))) + +/** + * @brief HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required + * pulse duration (when the timer operates in one pulse mode). + * @note ex: @ref __HAL_TIM_CALC_PERIOD_DITHER_BY_DELAY(1000000, 0, 10, 20); + * @note This macro should be used only if dithering is already enabled + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __PSC__ prescaler + * @param __DELAY__ timer output compare active/inactive delay (in us) + * @param __PULSE__ pulse duration (in us) + * @retval Auto-reload value (between Min_Data=0 and Max_Data=65519) + */ +#define __HAL_TIM_CALC_PERIOD_DITHER_BY_DELAY(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \ + ((uint32_t)(__HAL_TIM_CALC_PULSE_DITHER((__TIMCLK__), (__PSC__), (__PULSE__)) \ + + __HAL_TIM_CALC_PULSE_DITHER((__TIMCLK__), (__PSC__), (__DELAY__)))) + +/** + * @} + */ +/* End of exported macro -----------------------------------------------------*/ + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros + * @{ + */ +#define IS_TIM_REMAP(__REMAP__) ((((__REMAP__) & 0xFFFC3FFFU) == 0x00000000U)) +#define IS_TIM_BREAKINPUT(__BREAKINPUT__) (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) || \ + ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2)) + +#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \ + ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \ + ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2)) + +#define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || \ + ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE)) + +#define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW) || \ + ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH)) + +#define IS_TIM_TISEL(__TISEL__) ((((__TISEL__) & 0xF0F0F0F0U) == 0x00000000U)) + +#define IS_TIM_TISEL_TIX_INSTANCE(INSTANCE, CHANNEL) \ + (IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) && ((CHANNEL) < TIM_CHANNEL_5)) + +#if defined(TIM3) +#define IS_TIM_CLOCKSOURCE_INSTANCE(INSTANCE, __CLOCK__) \ + ((((INSTANCE) == TIM1) && \ + (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) \ + || \ + (((INSTANCE) == TIM2) && \ + (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) \ + || \ + (((INSTANCE) == TIM3) && \ + (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)))) +#else +#define IS_TIM_CLOCKSOURCE_INSTANCE(INSTANCE, __CLOCK__) \ + ((((INSTANCE) == TIM1) && \ + (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) \ + || \ + (((INSTANCE) == TIM2) && \ + (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)))) +#endif /* TIM3 */ + +#if defined(TIM3) +#define IS_TIM_TRIGGER_INSTANCE(INSTANCE, __SELECTION__) \ + ((((INSTANCE) == TIM1) && \ + (((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + ((__SELECTION__) == TIM_TS_TI1FP1) || \ + ((__SELECTION__) == TIM_TS_TI2FP2) || \ + ((__SELECTION__) == TIM_TS_ETRF) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8))) \ + || \ + (((INSTANCE) == TIM2) && \ + (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + ((__SELECTION__) == TIM_TS_TI1FP1) || \ + ((__SELECTION__) == TIM_TS_TI2FP2) || \ + ((__SELECTION__) == TIM_TS_ETRF) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8))) \ + || \ + (((INSTANCE) == TIM3) && \ + (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + ((__SELECTION__) == TIM_TS_TI1FP1) || \ + ((__SELECTION__) == TIM_TS_TI2FP2) || \ + ((__SELECTION__) == TIM_TS_ETRF) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8)))) +#else +#define IS_TIM_TRIGGER_INSTANCE(INSTANCE, __SELECTION__) \ + ((((INSTANCE) == TIM1) && \ + (((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + ((__SELECTION__) == TIM_TS_TI1FP1) || \ + ((__SELECTION__) == TIM_TS_TI2FP2) || \ + ((__SELECTION__) == TIM_TS_ETRF) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8))) \ + || \ + (((INSTANCE) == TIM2) && \ + (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + ((__SELECTION__) == TIM_TS_TI1FP1) || \ + ((__SELECTION__) == TIM_TS_TI2FP2) || \ + ((__SELECTION__) == TIM_TS_ETRF) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8)))) +#endif /* TIM3 */ + +#if defined(TIM3) +#define IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(INSTANCE, __SELECTION__) \ + ((((INSTANCE) == TIM1) && \ + (((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_NONE))) \ + || \ + (((INSTANCE) == TIM2) && \ + (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_NONE))) \ + || \ + (((INSTANCE) == TIM3) && \ + (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_NONE)))) +#else +#define IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(INSTANCE, __SELECTION__) \ + ((((INSTANCE) == TIM1) && \ + (((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_NONE))) \ + || \ + (((INSTANCE) == TIM2) && \ + (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR7) || \ + ((__SELECTION__) == TIM_TS_ITR8) || \ + ((__SELECTION__) == TIM_TS_NONE)))) +#endif /* TIM3 */ + +#define IS_TIM_OC_CHANNEL_MODE(__MODE__, __CHANNEL__) \ + (IS_TIM_OC_MODE(__MODE__) \ + && ((((__MODE__) == TIM_OCMODE_DIRECTION_OUTPUT) || ((__MODE__) == TIM_OCMODE_PULSE_ON_COMPARE)) \ + ? (((__CHANNEL__) == TIM_CHANNEL_3) || ((__CHANNEL__) == TIM_CHANNEL_4)) : (1 == 1))) + +#define IS_TIM_PULSEONCOMPARE_CHANNEL(__CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_3) || \ + ((__CHANNEL__) == TIM_CHANNEL_4)) + +#define IS_TIM_PULSEONCOMPARE_INSTANCE(INSTANCE) IS_TIM_CC3_INSTANCE(INSTANCE) + +#define IS_TIM_PULSEONCOMPARE_WIDTH(__WIDTH__) ((__WIDTH__) <= 0xFFU) + +#define IS_TIM_PULSEONCOMPARE_WIDTHPRESCALER(__PRESCALER__) ((__PRESCALER__) <= 0x7U) + +#define IS_TIM_SLAVE_PRELOAD_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_SMS_PRELOAD_SOURCE_UPDATE) \ + || ((__SOURCE__) == TIM_SMS_PRELOAD_SOURCE_INDEX)) + +#define IS_TIM_ENCODERINDEX_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINDEX_POLARITY_INVERTED) || \ + ((__POLARITY__) == TIM_ENCODERINDEX_POLARITY_NONINVERTED)) + +#define IS_TIM_ENCODERINDEX_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ENCODERINDEX_PRESCALER_DIV1) || \ + ((__PRESCALER__) == TIM_ENCODERINDEX_PRESCALER_DIV2) || \ + ((__PRESCALER__) == TIM_ENCODERINDEX_PRESCALER_DIV4) || \ + ((__PRESCALER__) == TIM_ENCODERINDEX_PRESCALER_DIV8)) + +#define IS_TIM_ENCODERINDEX_FILTER(__FILTER__) ((__FILTER__) <= 0xFUL) + +#define IS_TIM_ENCODERINDEX_POSITION(__POSITION__) (((__POSITION__) == TIM_ENCODERINDEX_POSITION_00) || \ + ((__POSITION__) == TIM_ENCODERINDEX_POSITION_01) || \ + ((__POSITION__) == TIM_ENCODERINDEX_POSITION_10) || \ + ((__POSITION__) == TIM_ENCODERINDEX_POSITION_11) || \ + ((__POSITION__) == TIM_ENCODERINDEX_POSITION_0) || \ + ((__POSITION__) == TIM_ENCODERINDEX_POSITION_1)) + +#define IS_TIM_ENCODERINDEX_DIRECTION(__DIRECTION__) (((__DIRECTION__) == TIM_ENCODERINDEX_DIRECTION_UP_DOWN) || \ + ((__DIRECTION__) == TIM_ENCODERINDEX_DIRECTION_UP) || \ + ((__DIRECTION__) == TIM_ENCODERINDEX_DIRECTION_DOWN)) + +#define IS_TIM_ENCODERINDEX_BLANKING(__BLANKING__) (((__BLANKING__) == TIM_ENCODERINDEX_BLANKING_DISABLE) || \ + ((__BLANKING__) == TIM_ENCODERINDEX_BLANKING_TI3) || \ + ((__BLANKING__) == TIM_ENCODERINDEX_BLANKING_TI4)) + +/** + * @} + */ +/* End of private macro ------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions + * @{ + */ + +/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions + * @brief Timer Hall Sensor functions + * @{ + */ +/* Timer Hall Sensor functions **********************************************/ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim); + +void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim); + +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions + * @brief Timer Complementary Output Compare functions + * @{ + */ +/* Timer Complementary Output Compare functions *****************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); + +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions + * @brief Timer Complementary PWM functions + * @{ + */ +/* Timer Complementary PWM functions ****************************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions + * @brief Timer Complementary One Pulse functions + * @{ + */ +/* Timer Complementary One Pulse functions **********************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions + * @brief Peripheral Control functions + * @{ + */ +/* Extended Control functions ************************************************/ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, + const TIM_MasterConfigTypeDef *sMasterConfig); +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, + const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, + const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig); +HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels); +HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); +HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel); + +HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput); +HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(const TIM_HandleTypeDef *htim, uint32_t BreakInput); +HAL_StatusTypeDef HAL_TIMEx_DitheringEnable(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIMEx_DitheringDisable(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIMEx_OC_ConfigPulseOnCompare(TIM_HandleTypeDef *htim, uint32_t PulseWidthPrescaler, + uint32_t PulseWidth); +HAL_StatusTypeDef HAL_TIMEx_ConfigSlaveModePreload(TIM_HandleTypeDef *htim, uint32_t Source); +HAL_StatusTypeDef HAL_TIMEx_EnableSlaveModePreload(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIMEx_DisableSlaveModePreload(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIMEx_EnableDeadTimePreload(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIMEx_DisableDeadTimePreload(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIMEx_ConfigDeadTime(TIM_HandleTypeDef *htim, uint32_t Deadtime); +HAL_StatusTypeDef HAL_TIMEx_ConfigAsymmetricalDeadTime(TIM_HandleTypeDef *htim, uint32_t FallingDeadtime); +HAL_StatusTypeDef HAL_TIMEx_EnableAsymmetricalDeadTime(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIMEx_DisableAsymmetricalDeadTime(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIMEx_ConfigEncoderIndex(TIM_HandleTypeDef *htim, + TIMEx_EncoderIndexConfigTypeDef *sEncoderIndexConfig); +HAL_StatusTypeDef HAL_TIMEx_EnableEncoderIndex(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIMEx_DisableEncoderIndex(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIMEx_EnableEncoderFirstIndex(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIMEx_DisableEncoderFirstIndex(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions + * @brief Extended Callbacks functions + * @{ + */ +/* Extended Callback **********************************************************/ +void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim); +void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim); +void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim); +void HAL_TIMEx_EncoderIndexCallback(TIM_HandleTypeDef *htim); +void HAL_TIMEx_DirectionChangeCallback(TIM_HandleTypeDef *htim); +void HAL_TIMEx_IndexErrorCallback(TIM_HandleTypeDef *htim); +void HAL_TIMEx_TransitionErrorCallback(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions + * @brief Extended Peripheral State functions + * @{ + */ +/* Extended Peripheral State functions ***************************************/ +HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim, uint32_t ChannelN); +/** + * @} + */ + +/** + * @} + */ +/* End of exported functions -------------------------------------------------*/ + +/* Private functions----------------------------------------------------------*/ +/** @addtogroup TIMEx_Private_Functions TIM Extended Private Functions + * @{ + */ +void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); +void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma); +/** + * @} + */ +/* End of private functions --------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32WBAxx_HAL_TIM_EX_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_tsc.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_tsc.h new file mode 100644 index 0000000000..5b79ba051a --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_tsc.h @@ -0,0 +1,804 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_tsc.h + * @author MCD Application Team + * @brief Header file of TSC HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_HAL_TSC_H +#define STM32WBAxx_HAL_TSC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal_def.h" + + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @addtogroup TSC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup TSC_Exported_Types TSC Exported Types + * @{ + */ + +/** + * @brief TSC state structure definition + */ +typedef enum +{ + HAL_TSC_STATE_RESET = 0x00UL, /*!< TSC registers have their reset value */ + HAL_TSC_STATE_READY = 0x01UL, /*!< TSC registers are initialized or acquisition is completed with success */ + HAL_TSC_STATE_BUSY = 0x02UL, /*!< TSC initialization or acquisition is on-going */ + HAL_TSC_STATE_ERROR = 0x03UL /*!< Acquisition is completed with max count error */ +} HAL_TSC_StateTypeDef; + +/** + * @brief TSC group status structure definition + */ +typedef enum +{ + TSC_GROUP_ONGOING = 0x00UL, /*!< Acquisition on group is on-going or not started */ + TSC_GROUP_COMPLETED = 0x01UL /*!< Acquisition on group is completed with success (no max count error) */ +} TSC_GroupStatusTypeDef; + +/** + * @brief TSC init structure definition + */ +typedef struct +{ + uint32_t CTPulseHighLength; /*!< Charge-transfer high pulse length + This parameter can be a value of @ref TSC_CTPulseHL_Config */ + uint32_t CTPulseLowLength; /*!< Charge-transfer low pulse length + This parameter can be a value of @ref TSC_CTPulseLL_Config */ + FunctionalState SpreadSpectrum; /*!< Spread spectrum activation + This parameter can be set to ENABLE or DISABLE. */ + uint32_t SpreadSpectrumDeviation; /*!< Spread spectrum deviation + This parameter must be a number between Min_Data = 0 and Max_Data = 127 */ + uint32_t SpreadSpectrumPrescaler; /*!< Spread spectrum prescaler + This parameter can be a value of @ref TSC_SpreadSpec_Prescaler */ + uint32_t PulseGeneratorPrescaler; /*!< Pulse generator prescaler + This parameter can be a value of @ref TSC_PulseGenerator_Prescaler */ + uint32_t MaxCountValue; /*!< Max count value + This parameter can be a value of @ref TSC_MaxCount_Value */ + uint32_t IODefaultMode; /*!< IO default mode + This parameter can be a value of @ref TSC_IO_Default_Mode */ + uint32_t SynchroPinPolarity; /*!< Synchro pin polarity + This parameter can be a value of @ref TSC_Synchro_Pin_Polarity */ + uint32_t AcquisitionMode; /*!< Acquisition mode + This parameter can be a value of @ref TSC_Acquisition_Mode */ + FunctionalState MaxCountInterrupt;/*!< Max count interrupt activation + This parameter can be set to ENABLE or DISABLE. */ + uint32_t ChannelIOs; /*!< Channel IOs mask */ + uint32_t ShieldIOs; /*!< Shield IOs mask */ + uint32_t SamplingIOs; /*!< Sampling IOs mask */ +} TSC_InitTypeDef; + +/** + * @brief TSC IOs configuration structure definition + */ +typedef struct +{ + uint32_t ChannelIOs; /*!< Channel IOs mask */ + uint32_t ShieldIOs; /*!< Shield IOs mask */ + uint32_t SamplingIOs; /*!< Sampling IOs mask */ +} TSC_IOConfigTypeDef; + +/** + * @brief TSC handle Structure definition + */ +#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) +typedef struct __TSC_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ +{ + TSC_TypeDef *Instance; /*!< Register base address */ + TSC_InitTypeDef Init; /*!< Initialization parameters */ + __IO HAL_TSC_StateTypeDef State; /*!< Peripheral state */ + HAL_LockTypeDef Lock; /*!< Lock feature */ + __IO uint32_t ErrorCode; /*!< TSC Error code */ + +#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) + void (* ConvCpltCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Conversion complete callback */ + void (* ErrorCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Error callback */ + + void (* MspInitCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Msp Init callback */ + void (* MspDeInitCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Msp DeInit callback */ + +#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ +} TSC_HandleTypeDef; + +enum +{ + TSC_GROUP1_IDX = 0x00UL, + TSC_GROUP2_IDX, + TSC_GROUP3_IDX, + TSC_GROUP4_IDX, + TSC_GROUP5_IDX, + TSC_GROUP6_IDX, + TSC_NB_OF_GROUPS +}; + +#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) +/** + * @brief HAL TSC Callback ID enumeration definition + */ +typedef enum +{ + HAL_TSC_CONV_COMPLETE_CB_ID = 0x00UL, /*!< TSC Conversion completed callback ID */ + HAL_TSC_ERROR_CB_ID = 0x01UL, /*!< TSC Error callback ID */ + + HAL_TSC_MSPINIT_CB_ID = 0x02UL, /*!< TSC Msp Init callback ID */ + HAL_TSC_MSPDEINIT_CB_ID = 0x03UL /*!< TSC Msp DeInit callback ID */ + +} HAL_TSC_CallbackIDTypeDef; + +/** + * @brief HAL TSC Callback pointer definition + */ +typedef void (*pTSC_CallbackTypeDef)(TSC_HandleTypeDef *htsc); /*!< pointer to an TSC callback function */ + +#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup TSC_Exported_Constants TSC Exported Constants + * @{ + */ + +/** @defgroup TSC_Error_Code_definition TSC Error Code definition + * @brief TSC Error Code definition + * @{ + */ +#define HAL_TSC_ERROR_NONE 0x00000000UL /*!< No error */ +#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) +#define HAL_TSC_ERROR_INVALID_CALLBACK 0x00000001UL /*!< Invalid Callback error */ +#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup TSC_CTPulseHL_Config CTPulse High Length + * @{ + */ +#define TSC_CTPH_1CYCLE 0x00000000UL +/*!< Charge transfer pulse high during 1 cycle (PGCLK) */ +#define TSC_CTPH_2CYCLES TSC_CR_CTPH_0 +/*!< Charge transfer pulse high during 2 cycles (PGCLK) */ +#define TSC_CTPH_3CYCLES TSC_CR_CTPH_1 +/*!< Charge transfer pulse high during 3 cycles (PGCLK) */ +#define TSC_CTPH_4CYCLES (TSC_CR_CTPH_1 | TSC_CR_CTPH_0) +/*!< Charge transfer pulse high during 4 cycles (PGCLK) */ +#define TSC_CTPH_5CYCLES TSC_CR_CTPH_2 +/*!< Charge transfer pulse high during 5 cycles (PGCLK) */ +#define TSC_CTPH_6CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_0) +/*!< Charge transfer pulse high during 6 cycles (PGCLK) */ +#define TSC_CTPH_7CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_1) +/*!< Charge transfer pulse high during 7 cycles (PGCLK) */ +#define TSC_CTPH_8CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) +/*!< Charge transfer pulse high during 8 cycles (PGCLK) */ +#define TSC_CTPH_9CYCLES TSC_CR_CTPH_3 +/*!< Charge transfer pulse high during 9 cycles (PGCLK) */ +#define TSC_CTPH_10CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_0) +/*!< Charge transfer pulse high during 10 cycles (PGCLK) */ +#define TSC_CTPH_11CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_1) +/*!< Charge transfer pulse high during 11 cycles (PGCLK) */ +#define TSC_CTPH_12CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) +/*!< Charge transfer pulse high during 12 cycles (PGCLK) */ +#define TSC_CTPH_13CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2) +/*!< Charge transfer pulse high during 13 cycles (PGCLK) */ +#define TSC_CTPH_14CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_0) +/*!< Charge transfer pulse high during 14 cycles (PGCLK) */ +#define TSC_CTPH_15CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1) +/*!< Charge transfer pulse high during 15 cycles (PGCLK) */ +#define TSC_CTPH_16CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) +/*!< Charge transfer pulse high during 16 cycles (PGCLK) */ +/** + * @} + */ + +/** @defgroup TSC_CTPulseLL_Config CTPulse Low Length + * @{ + */ +#define TSC_CTPL_1CYCLE 0x00000000UL +/*!< Charge transfer pulse low during 1 cycle (PGCLK) */ +#define TSC_CTPL_2CYCLES TSC_CR_CTPL_0 +/*!< Charge transfer pulse low during 2 cycles (PGCLK) */ +#define TSC_CTPL_3CYCLES TSC_CR_CTPL_1 +/*!< Charge transfer pulse low during 3 cycles (PGCLK) */ +#define TSC_CTPL_4CYCLES (TSC_CR_CTPL_1 | TSC_CR_CTPL_0) +/*!< Charge transfer pulse low during 4 cycles (PGCLK) */ +#define TSC_CTPL_5CYCLES TSC_CR_CTPL_2 +/*!< Charge transfer pulse low during 5 cycles (PGCLK) */ +#define TSC_CTPL_6CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_0) +/*!< Charge transfer pulse low during 6 cycles (PGCLK) */ +#define TSC_CTPL_7CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1) +/*!< Charge transfer pulse low during 7 cycles (PGCLK) */ +#define TSC_CTPL_8CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) +/*!< Charge transfer pulse low during 8 cycles (PGCLK) */ +#define TSC_CTPL_9CYCLES TSC_CR_CTPL_3 +/*!< Charge transfer pulse low during 9 cycles (PGCLK) */ +#define TSC_CTPL_10CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_0) +/*!< Charge transfer pulse low during 10 cycles (PGCLK) */ +#define TSC_CTPL_11CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1) +/*!< Charge transfer pulse low during 11 cycles (PGCLK) */ +#define TSC_CTPL_12CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) +/*!< Charge transfer pulse low during 12 cycles (PGCLK) */ +#define TSC_CTPL_13CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2) +/*!< Charge transfer pulse low during 13 cycles (PGCLK) */ +#define TSC_CTPL_14CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_0) +/*!< Charge transfer pulse low during 14 cycles (PGCLK) */ +#define TSC_CTPL_15CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1) +/*!< Charge transfer pulse low during 15 cycles (PGCLK) */ +#define TSC_CTPL_16CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) +/*!< Charge transfer pulse low during 16 cycles (PGCLK) */ +/** + * @} + */ + +/** @defgroup TSC_SpreadSpec_Prescaler Spread Spectrum Prescaler + * @{ + */ +#define TSC_SS_PRESC_DIV1 0x00000000UL /*!< Spread Spectrum Prescaler Div1 */ +#define TSC_SS_PRESC_DIV2 TSC_CR_SSPSC /*!< Spread Spectrum Prescaler Div2 */ +/** + * @} + */ + +/** @defgroup TSC_PulseGenerator_Prescaler Pulse Generator Prescaler + * @{ + */ +#define TSC_PG_PRESC_DIV1 0x00000000UL /*!< Pulse Generator HCLK Div1 */ +#define TSC_PG_PRESC_DIV2 TSC_CR_PGPSC_0 /*!< Pulse Generator HCLK Div2 */ +#define TSC_PG_PRESC_DIV4 TSC_CR_PGPSC_1 /*!< Pulse Generator HCLK Div4 */ +#define TSC_PG_PRESC_DIV8 (TSC_CR_PGPSC_1 | TSC_CR_PGPSC_0) /*!< Pulse Generator HCLK Div8 */ +#define TSC_PG_PRESC_DIV16 TSC_CR_PGPSC_2 /*!< Pulse Generator HCLK Div16 */ +#define TSC_PG_PRESC_DIV32 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_0) /*!< Pulse Generator HCLK Div32 */ +#define TSC_PG_PRESC_DIV64 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_1) /*!< Pulse Generator HCLK Div64 */ +#define TSC_PG_PRESC_DIV128 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_1 | TSC_CR_PGPSC_0) /*!< Pulse Generator HCLK Div128 */ +/** + * @} + */ + +/** @defgroup TSC_MaxCount_Value Max Count Value + * @{ + */ +#define TSC_MCV_255 0x00000000UL /*!< 255 maximum number of charge transfer pulses */ +#define TSC_MCV_511 TSC_CR_MCV_0 /*!< 511 maximum number of charge transfer pulses */ +#define TSC_MCV_1023 TSC_CR_MCV_1 /*!< 1023 maximum number of charge transfer pulses */ +#define TSC_MCV_2047 (TSC_CR_MCV_1 | TSC_CR_MCV_0) /*!< 2047 maximum number of charge transfer pulses */ +#define TSC_MCV_4095 TSC_CR_MCV_2 /*!< 4095 maximum number of charge transfer pulses */ +#define TSC_MCV_8191 (TSC_CR_MCV_2 | TSC_CR_MCV_0) /*!< 8191 maximum number of charge transfer pulses */ +#define TSC_MCV_16383 (TSC_CR_MCV_2 | TSC_CR_MCV_1) /*!< 16383 maximum number of charge transfer pulses */ +/** + * @} + */ + +/** @defgroup TSC_IO_Default_Mode IO Default Mode + * @{ + */ +#define TSC_IODEF_OUT_PP_LOW 0x00000000UL /*!< I/Os are forced to output push-pull low */ +#define TSC_IODEF_IN_FLOAT TSC_CR_IODEF /*!< I/Os are in input floating */ +/** + * @} + */ + +/** @defgroup TSC_Synchro_Pin_Polarity Synchro Pin Polarity + * @{ + */ +#define TSC_SYNC_POLARITY_FALLING 0x00000000UL /*!< Falling edge only */ +#define TSC_SYNC_POLARITY_RISING TSC_CR_SYNCPOL /*!< Rising edge and high level */ +/** + * @} + */ + +/** @defgroup TSC_Acquisition_Mode Acquisition Mode + * @{ + */ +#define TSC_ACQ_MODE_NORMAL 0x00000000UL +/*!< Normal acquisition mode (acquisition starts as soon as START bit is set) */ +#define TSC_ACQ_MODE_SYNCHRO TSC_CR_AM +/*!< Synchronized acquisition mode (acquisition starts if START bit is set and +when the selected signal is detected on the SYNC input pin) */ +/** + * @} + */ + +/** @defgroup TSC_interrupts_definition Interrupts definition + * @{ + */ +#define TSC_IT_EOA TSC_IER_EOAIE /*!< End of acquisition interrupt enable */ +#define TSC_IT_MCE TSC_IER_MCEIE /*!< Max count error interrupt enable */ +/** + * @} + */ + +/** @defgroup TSC_flags_definition Flags definition + * @{ + */ +#define TSC_FLAG_EOA TSC_ISR_EOAF /*!< End of acquisition flag */ +#define TSC_FLAG_MCE TSC_ISR_MCEF /*!< Max count error flag */ +/** + * @} + */ + +/** @defgroup TSC_Group_definition Group definition + * @{ + */ +#define TSC_GROUP1 (0x1UL << TSC_GROUP1_IDX) +#define TSC_GROUP2 (0x1UL << TSC_GROUP2_IDX) +#define TSC_GROUP3 (0x1UL << TSC_GROUP3_IDX) +#define TSC_GROUP4 (0x1UL << TSC_GROUP4_IDX) +#define TSC_GROUP5 (0x1UL << TSC_GROUP5_IDX) +#define TSC_GROUP6 (0x1UL << TSC_GROUP6_IDX) + +#define TSC_GROUP1_IO1 TSC_IOCCR_G1_IO1 /*!< TSC Group1 IO1 */ +#define TSC_GROUP1_IO2 TSC_IOCCR_G1_IO2 /*!< TSC Group1 IO2 */ +#define TSC_GROUP1_IO3 TSC_IOCCR_G1_IO3 /*!< TSC Group1 IO3 */ +#define TSC_GROUP1_IO4 TSC_IOCCR_G1_IO4 /*!< TSC Group1 IO4 */ + +#define TSC_GROUP2_IO1 TSC_IOCCR_G2_IO1 /*!< TSC Group2 IO1 */ +#define TSC_GROUP2_IO2 TSC_IOCCR_G2_IO2 /*!< TSC Group2 IO2 */ +#define TSC_GROUP2_IO3 TSC_IOCCR_G2_IO3 /*!< TSC Group2 IO3 */ +#define TSC_GROUP2_IO4 TSC_IOCCR_G2_IO4 /*!< TSC Group2 IO4 */ + +#define TSC_GROUP3_IO1 TSC_IOCCR_G3_IO1 /*!< TSC Group3 IO1 */ +#define TSC_GROUP3_IO2 TSC_IOCCR_G3_IO2 /*!< TSC Group3 IO2 */ +#define TSC_GROUP3_IO3 TSC_IOCCR_G3_IO3 /*!< TSC Group3 IO3 */ +#define TSC_GROUP3_IO4 TSC_IOCCR_G3_IO4 /*!< TSC Group3 IO4 */ + +#define TSC_GROUP4_IO1 TSC_IOCCR_G4_IO1 /*!< TSC Group4 IO1 */ +#define TSC_GROUP4_IO2 TSC_IOCCR_G4_IO2 /*!< TSC Group4 IO2 */ +#define TSC_GROUP4_IO3 TSC_IOCCR_G4_IO3 /*!< TSC Group4 IO3 */ +#define TSC_GROUP4_IO4 TSC_IOCCR_G4_IO4 /*!< TSC Group4 IO4 */ + +#define TSC_GROUP5_IO1 TSC_IOCCR_G5_IO1 /*!< TSC Group5 IO1 */ +#define TSC_GROUP5_IO2 TSC_IOCCR_G5_IO2 /*!< TSC Group5 IO2 */ +#define TSC_GROUP5_IO3 TSC_IOCCR_G5_IO3 /*!< TSC Group5 IO3 */ +#define TSC_GROUP5_IO4 TSC_IOCCR_G5_IO4 /*!< TSC Group5 IO4 */ + +#define TSC_GROUP6_IO1 TSC_IOCCR_G6_IO1 /*!< TSC Group6 IO1 */ +#define TSC_GROUP6_IO2 TSC_IOCCR_G6_IO2 /*!< TSC Group6 IO2 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ + +/** @defgroup TSC_Exported_Macros TSC Exported Macros + * @{ + */ + +/** @brief Reset TSC handle state. + * @param __HANDLE__ TSC handle + * @retval None + */ +#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) +#define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_TSC_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TSC_STATE_RESET) +#endif /* (USE_HAL_TSC_REGISTER_CALLBACKS == 1) */ + +/** + * @brief Enable the TSC peripheral. + * @param __HANDLE__ TSC handle + * @retval None + */ +#define __HAL_TSC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_TSCE) + +/** + * @brief Disable the TSC peripheral. + * @param __HANDLE__ TSC handle + * @retval None + */ +#define __HAL_TSC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_TSCE)) + +/** + * @brief Start acquisition. + * @param __HANDLE__ TSC handle + * @retval None + */ +#define __HAL_TSC_START_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_START) + +/** + * @brief Stop acquisition. + * @param __HANDLE__ TSC handle + * @retval None + */ +#define __HAL_TSC_STOP_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_START)) + +/** + * @brief Set IO default mode to output push-pull low. + * @param __HANDLE__ TSC handle + * @retval None + */ +#define __HAL_TSC_SET_IODEF_OUTPPLOW(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_IODEF)) + +/** + * @brief Set IO default mode to input floating. + * @param __HANDLE__ TSC handle + * @retval None + */ +#define __HAL_TSC_SET_IODEF_INFLOAT(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_IODEF) + +/** + * @brief Set synchronization polarity to falling edge. + * @param __HANDLE__ TSC handle + * @retval None + */ +#define __HAL_TSC_SET_SYNC_POL_FALL(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_SYNCPOL)) + +/** + * @brief Set synchronization polarity to rising edge and high level. + * @param __HANDLE__ TSC handle + * @retval None + */ +#define __HAL_TSC_SET_SYNC_POL_RISE_HIGH(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_SYNCPOL) + +/** + * @brief Enable TSC interrupt. + * @param __HANDLE__ TSC handle + * @param __INTERRUPT__ TSC interrupt + * @retval None + */ +#define __HAL_TSC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) + +/** + * @brief Disable TSC interrupt. + * @param __HANDLE__ TSC handle + * @param __INTERRUPT__ TSC interrupt + * @retval None + */ +#define __HAL_TSC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__))) + +/** @brief Check whether the specified TSC interrupt source is enabled or not. + * @param __HANDLE__ TSC Handle + * @param __INTERRUPT__ TSC interrupt + * @retval SET or RESET + */ +#define __HAL_TSC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER\ + & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET :\ + RESET) + +/** + * @brief Check whether the specified TSC flag is set or not. + * @param __HANDLE__ TSC handle + * @param __FLAG__ TSC flag + * @retval SET or RESET + */ +#define __HAL_TSC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR\ + & (__FLAG__)) == (__FLAG__)) ? SET : RESET) + +/** + * @brief Clear the TSC's pending flag. + * @param __HANDLE__ TSC handle + * @param __FLAG__ TSC flag + * @retval None + */ +#define __HAL_TSC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) + +/** + * @brief Enable schmitt trigger hysteresis on a group of IOs. + * @param __HANDLE__ TSC handle + * @param __GX_IOY_MASK__ IOs mask + * @retval None + */ +#define __HAL_TSC_ENABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR |= (__GX_IOY_MASK__)) + +/** + * @brief Disable schmitt trigger hysteresis on a group of IOs. + * @param __HANDLE__ TSC handle + * @param __GX_IOY_MASK__ IOs mask + * @retval None + */ +#define __HAL_TSC_DISABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR\ + &= (~(__GX_IOY_MASK__))) + +/** + * @brief Open analog switch on a group of IOs. + * @param __HANDLE__ TSC handle + * @param __GX_IOY_MASK__ IOs mask + * @retval None + */ +#define __HAL_TSC_OPEN_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR\ + &= (~(__GX_IOY_MASK__))) + +/** + * @brief Close analog switch on a group of IOs. + * @param __HANDLE__ TSC handle + * @param __GX_IOY_MASK__ IOs mask + * @retval None + */ +#define __HAL_TSC_CLOSE_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR |= (__GX_IOY_MASK__)) + +/** + * @brief Enable a group of IOs in channel mode. + * @param __HANDLE__ TSC handle + * @param __GX_IOY_MASK__ IOs mask + * @retval None + */ +#define __HAL_TSC_ENABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR |= (__GX_IOY_MASK__)) + +/** + * @brief Disable a group of channel IOs. + * @param __HANDLE__ TSC handle + * @param __GX_IOY_MASK__ IOs mask + * @retval None + */ +#define __HAL_TSC_DISABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR\ + &= (~(__GX_IOY_MASK__))) + +/** + * @brief Enable a group of IOs in sampling mode. + * @param __HANDLE__ TSC handle + * @param __GX_IOY_MASK__ IOs mask + * @retval None + */ +#define __HAL_TSC_ENABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR |= (__GX_IOY_MASK__)) + +/** + * @brief Disable a group of sampling IOs. + * @param __HANDLE__ TSC handle + * @param __GX_IOY_MASK__ IOs mask + * @retval None + */ +#define __HAL_TSC_DISABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR &= (~(__GX_IOY_MASK__))) + +/** + * @brief Enable acquisition groups. + * @param __HANDLE__ TSC handle + * @param __GX_MASK__ Groups mask + * @retval None + */ +#define __HAL_TSC_ENABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR |= (__GX_MASK__)) + +/** + * @brief Disable acquisition groups. + * @param __HANDLE__ TSC handle + * @param __GX_MASK__ Groups mask + * @retval None + */ +#define __HAL_TSC_DISABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR &= (~(__GX_MASK__))) + +/** @brief Gets acquisition group status. + * @param __HANDLE__ TSC Handle + * @param __GX_INDEX__ Group index + * @retval SET or RESET + */ +#define __HAL_TSC_GET_GROUP_STATUS(__HANDLE__, __GX_INDEX__) \ + ((((__HANDLE__)->Instance->IOGCSR & (uint32_t)(1UL << (((__GX_INDEX__) & 0xFUL) + 16UL))) == \ + (uint32_t)(1UL << (((__GX_INDEX__) & 0xFUL) + 16UL))) ? TSC_GROUP_COMPLETED : TSC_GROUP_ONGOING) + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ + +/** @defgroup TSC_Private_Macros TSC Private Macros + * @{ + */ + +#define IS_TSC_CTPH(__VALUE__) (((__VALUE__) == TSC_CTPH_1CYCLE) || \ + ((__VALUE__) == TSC_CTPH_2CYCLES) || \ + ((__VALUE__) == TSC_CTPH_3CYCLES) || \ + ((__VALUE__) == TSC_CTPH_4CYCLES) || \ + ((__VALUE__) == TSC_CTPH_5CYCLES) || \ + ((__VALUE__) == TSC_CTPH_6CYCLES) || \ + ((__VALUE__) == TSC_CTPH_7CYCLES) || \ + ((__VALUE__) == TSC_CTPH_8CYCLES) || \ + ((__VALUE__) == TSC_CTPH_9CYCLES) || \ + ((__VALUE__) == TSC_CTPH_10CYCLES) || \ + ((__VALUE__) == TSC_CTPH_11CYCLES) || \ + ((__VALUE__) == TSC_CTPH_12CYCLES) || \ + ((__VALUE__) == TSC_CTPH_13CYCLES) || \ + ((__VALUE__) == TSC_CTPH_14CYCLES) || \ + ((__VALUE__) == TSC_CTPH_15CYCLES) || \ + ((__VALUE__) == TSC_CTPH_16CYCLES)) + +#define IS_TSC_CTPL(__VALUE__) (((__VALUE__) == TSC_CTPL_1CYCLE) || \ + ((__VALUE__) == TSC_CTPL_2CYCLES) || \ + ((__VALUE__) == TSC_CTPL_3CYCLES) || \ + ((__VALUE__) == TSC_CTPL_4CYCLES) || \ + ((__VALUE__) == TSC_CTPL_5CYCLES) || \ + ((__VALUE__) == TSC_CTPL_6CYCLES) || \ + ((__VALUE__) == TSC_CTPL_7CYCLES) || \ + ((__VALUE__) == TSC_CTPL_8CYCLES) || \ + ((__VALUE__) == TSC_CTPL_9CYCLES) || \ + ((__VALUE__) == TSC_CTPL_10CYCLES) || \ + ((__VALUE__) == TSC_CTPL_11CYCLES) || \ + ((__VALUE__) == TSC_CTPL_12CYCLES) || \ + ((__VALUE__) == TSC_CTPL_13CYCLES) || \ + ((__VALUE__) == TSC_CTPL_14CYCLES) || \ + ((__VALUE__) == TSC_CTPL_15CYCLES) || \ + ((__VALUE__) == TSC_CTPL_16CYCLES)) + +#define IS_TSC_SS(__VALUE__) (((FunctionalState)(__VALUE__) == DISABLE)\ + || ((FunctionalState)(__VALUE__) == ENABLE)) + +#define IS_TSC_SSD(__VALUE__) (((__VALUE__) == 0UL) || (((__VALUE__) > 0UL) && ((__VALUE__) < 128UL))) + +#define IS_TSC_SS_PRESC(__VALUE__) (((__VALUE__) == TSC_SS_PRESC_DIV1) || ((__VALUE__) == TSC_SS_PRESC_DIV2)) + +#define IS_TSC_PG_PRESC(__VALUE__) (((__VALUE__) == TSC_PG_PRESC_DIV1) || \ + ((__VALUE__) == TSC_PG_PRESC_DIV2) || \ + ((__VALUE__) == TSC_PG_PRESC_DIV4) || \ + ((__VALUE__) == TSC_PG_PRESC_DIV8) || \ + ((__VALUE__) == TSC_PG_PRESC_DIV16) || \ + ((__VALUE__) == TSC_PG_PRESC_DIV32) || \ + ((__VALUE__) == TSC_PG_PRESC_DIV64) || \ + ((__VALUE__) == TSC_PG_PRESC_DIV128)) + +#define IS_TSC_PG_PRESC_VS_CTPL(__PGPSC__, __CTPL__) ((((__PGPSC__) == TSC_PG_PRESC_DIV1) && \ + ((__CTPL__) > TSC_CTPL_2CYCLES)) || \ + (((__PGPSC__) == TSC_PG_PRESC_DIV2) && \ + ((__CTPL__) > TSC_CTPL_1CYCLE)) || \ + (((__PGPSC__) > TSC_PG_PRESC_DIV2) && \ + (((__CTPL__) == TSC_CTPL_1CYCLE) || \ + ((__CTPL__) > TSC_CTPL_1CYCLE)))) + +#define IS_TSC_MCV(__VALUE__) (((__VALUE__) == TSC_MCV_255) || \ + ((__VALUE__) == TSC_MCV_511) || \ + ((__VALUE__) == TSC_MCV_1023) || \ + ((__VALUE__) == TSC_MCV_2047) || \ + ((__VALUE__) == TSC_MCV_4095) || \ + ((__VALUE__) == TSC_MCV_8191) || \ + ((__VALUE__) == TSC_MCV_16383)) + +#define IS_TSC_IODEF(__VALUE__) (((__VALUE__) == TSC_IODEF_OUT_PP_LOW) || ((__VALUE__) == TSC_IODEF_IN_FLOAT)) + +#define IS_TSC_SYNC_POL(__VALUE__) (((__VALUE__) == TSC_SYNC_POLARITY_FALLING)\ + || ((__VALUE__) == TSC_SYNC_POLARITY_RISING)) + +#define IS_TSC_ACQ_MODE(__VALUE__) (((__VALUE__) == TSC_ACQ_MODE_NORMAL) || ((__VALUE__) == TSC_ACQ_MODE_SYNCHRO)) + +#define IS_TSC_MCE_IT(__VALUE__) (((FunctionalState)(__VALUE__) == DISABLE)\ + || ((FunctionalState)(__VALUE__) == ENABLE)) + +#define IS_TSC_GROUP_INDEX(__VALUE__) (((__VALUE__) == 0UL)\ + || (((__VALUE__) > 0UL) && ((__VALUE__) < (uint32_t)TSC_NB_OF_GROUPS))) + +#define IS_TSC_GROUP(__VALUE__) (((__VALUE__) == 0UL) ||\ + (((__VALUE__) & TSC_GROUP1_IO1) == TSC_GROUP1_IO1) ||\ + (((__VALUE__) & TSC_GROUP1_IO2) == TSC_GROUP1_IO2) ||\ + (((__VALUE__) & TSC_GROUP1_IO3) == TSC_GROUP1_IO3) ||\ + (((__VALUE__) & TSC_GROUP1_IO4) == TSC_GROUP1_IO4) ||\ + (((__VALUE__) & TSC_GROUP2_IO1) == TSC_GROUP2_IO1) ||\ + (((__VALUE__) & TSC_GROUP2_IO2) == TSC_GROUP2_IO2) ||\ + (((__VALUE__) & TSC_GROUP2_IO3) == TSC_GROUP2_IO3) ||\ + (((__VALUE__) & TSC_GROUP2_IO4) == TSC_GROUP2_IO4) ||\ + (((__VALUE__) & TSC_GROUP3_IO1) == TSC_GROUP3_IO1) ||\ + (((__VALUE__) & TSC_GROUP3_IO2) == TSC_GROUP3_IO2) ||\ + (((__VALUE__) & TSC_GROUP3_IO3) == TSC_GROUP3_IO3) ||\ + (((__VALUE__) & TSC_GROUP3_IO4) == TSC_GROUP3_IO4) ||\ + (((__VALUE__) & TSC_GROUP4_IO1) == TSC_GROUP4_IO1) ||\ + (((__VALUE__) & TSC_GROUP4_IO2) == TSC_GROUP4_IO2) ||\ + (((__VALUE__) & TSC_GROUP4_IO3) == TSC_GROUP4_IO3) ||\ + (((__VALUE__) & TSC_GROUP4_IO4) == TSC_GROUP4_IO4) ||\ + (((__VALUE__) & TSC_GROUP5_IO1) == TSC_GROUP5_IO1) ||\ + (((__VALUE__) & TSC_GROUP5_IO2) == TSC_GROUP5_IO2) ||\ + (((__VALUE__) & TSC_GROUP5_IO3) == TSC_GROUP5_IO3) ||\ + (((__VALUE__) & TSC_GROUP5_IO4) == TSC_GROUP5_IO4) ||\ + (((__VALUE__) & TSC_GROUP6_IO1) == TSC_GROUP6_IO1) ||\ + (((__VALUE__) & TSC_GROUP6_IO2) == TSC_GROUP6_IO2)) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup TSC_Exported_Functions + * @{ + */ + +/** @addtogroup TSC_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef *htsc); +HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef *htsc); +void HAL_TSC_MspInit(TSC_HandleTypeDef *htsc); +void HAL_TSC_MspDeInit(TSC_HandleTypeDef *htsc); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_TSC_RegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID, + pTSC_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_TSC_UnRegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @addtogroup TSC_Exported_Functions_Group2 Input and Output operation functions + * @{ + */ +/* IO operation functions *****************************************************/ +HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef *htsc); +HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef *htsc); +HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef *htsc); +HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef *htsc); +HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef *htsc); +TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(const TSC_HandleTypeDef *htsc, uint32_t gx_index); +uint32_t HAL_TSC_GroupGetValue(const TSC_HandleTypeDef *htsc, uint32_t gx_index); +/** + * @} + */ + +/** @addtogroup TSC_Exported_Functions_Group3 Peripheral Control functions + * @{ + */ +/* Peripheral Control functions ***********************************************/ +HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef *htsc, const TSC_IOConfigTypeDef *config); +HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef *htsc, FunctionalState choice); +/** + * @} + */ + +/** @addtogroup TSC_Exported_Functions_Group4 Peripheral State and Errors functions + * @{ + */ +/* Peripheral State and Error functions ***************************************/ +HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef *htsc); +/** + * @} + */ + +/** @addtogroup TSC_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks + * @{ + */ +/******* TSC IRQHandler and Callbacks used in Interrupt mode */ +void HAL_TSC_IRQHandler(TSC_HandleTypeDef *htsc); +void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef *htsc); +void HAL_TSC_ErrorCallback(TSC_HandleTypeDef *htsc); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WBAxx_HAL_TSC_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_uart.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_uart.h new file mode 100644 index 0000000000..ccfcceb943 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_uart.h @@ -0,0 +1,1764 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_uart.h + * @author MCD Application Team + * @brief Header file of UART HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_HAL_UART_H +#define STM32WBAxx_HAL_UART_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal_def.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @addtogroup UART + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup UART_Exported_Types UART Exported Types + * @{ + */ + +/** + * @brief UART Init Structure definition + */ +typedef struct +{ + uint32_t BaudRate; /*!< This member configures the UART communication baud rate. + The baud rate register is computed using the following formula: + LPUART: + ======= + Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate))) + where lpuart_ker_ck_pres is the UART input clock divided by a prescaler + UART: + ===== + - If oversampling is 16 or in LIN mode, + Baud Rate Register = ((uart_ker_ckpres) / ((huart->Init.BaudRate))) + - If oversampling is 8, + Baud Rate Register[15:4] = ((2 * uart_ker_ckpres) / + ((huart->Init.BaudRate)))[15:4] + Baud Rate Register[3] = 0 + Baud Rate Register[2:0] = (((2 * uart_ker_ckpres) / + ((huart->Init.BaudRate)))[3:0]) >> 1 + where uart_ker_ck_pres is the UART input clock divided by a prescaler */ + + uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref UARTEx_Word_Length. */ + + uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref UART_Stop_Bits. */ + + uint32_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref UART_Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ + + uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref UART_Mode. */ + + uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled + or disabled. + This parameter can be a value of @ref UART_Hardware_Flow_Control. */ + + uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, + to achieve higher speed (up to f_PCLK/8). + This parameter can be a value of @ref UART_Over_Sampling. */ + + uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected. + Selecting the single sample method increases the receiver tolerance to clock + deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */ + + uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the UART clock source. + This parameter can be a value of @ref UART_ClockPrescaler. */ + +} UART_InitTypeDef; + +/** + * @brief UART Advanced Features initialization structure definition + */ +typedef struct +{ + uint32_t AdvFeatureInit; /*!< Specifies which advanced UART features is initialized. Several + Advanced Features may be initialized at the same time . + This parameter can be a value of + @ref UART_Advanced_Features_Initialization_Type. */ + + uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted. + This parameter can be a value of @ref UART_Tx_Inv. */ + + uint32_t RxPinLevelInvert; /*!< Specifies whether the RX pin active level is inverted. + This parameter can be a value of @ref UART_Rx_Inv. */ + + uint32_t DataInvert; /*!< Specifies whether data are inverted (positive/direct logic + vs negative/inverted logic). + This parameter can be a value of @ref UART_Data_Inv. */ + + uint32_t Swap; /*!< Specifies whether TX and RX pins are swapped. + This parameter can be a value of @ref UART_Rx_Tx_Swap. */ + + uint32_t OverrunDisable; /*!< Specifies whether the reception overrun detection is disabled. + This parameter can be a value of @ref UART_Overrun_Disable. */ + +#if defined(HAL_DMA_MODULE_ENABLED) + uint32_t DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of reception error. + This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error. */ + +#endif /* HAL_DMA_MODULE_ENABLED */ + uint32_t AutoBaudRateEnable; /*!< Specifies whether auto Baud rate detection is enabled. + This parameter can be a value of @ref UART_AutoBaudRate_Enable. */ + + uint32_t AutoBaudRateMode; /*!< If auto Baud rate detection is enabled, specifies how the rate + detection is carried out. + This parameter can be a value of @ref UART_AutoBaud_Rate_Mode. */ + + uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line. + This parameter can be a value of @ref UART_MSB_First. */ +} UART_AdvFeatureInitTypeDef; + +/** + * @brief HAL UART State definition + * @note HAL UART State value is a combination of 2 different substates: + * gState and RxState (see @ref UART_State_Definition). + * - gState contains UART state information related to global Handle management + * and also information related to Tx operations. + * gState value coding follow below described bitmap : + * b7-b6 Error information + * 00 : No Error + * 01 : (Not Used) + * 10 : Timeout + * 11 : Error + * b5 Peripheral initialization status + * 0 : Reset (Peripheral not initialized) + * 1 : Init done (Peripheral initialized. HAL UART Init function already called) + * b4-b3 (not used) + * xx : Should be set to 00 + * b2 Intrinsic process state + * 0 : Ready + * 1 : Busy (Peripheral busy with some configuration or internal operations) + * b1 (not used) + * x : Should be set to 0 + * b0 Tx state + * 0 : Ready (no Tx operation ongoing) + * 1 : Busy (Tx operation ongoing) + * - RxState contains information related to Rx operations. + * RxState value coding follow below described bitmap : + * b7-b6 (not used) + * xx : Should be set to 00 + * b5 Peripheral initialization status + * 0 : Reset (Peripheral not initialized) + * 1 : Init done (Peripheral initialized) + * b4-b2 (not used) + * xxx : Should be set to 000 + * b1 Rx state + * 0 : Ready (no Rx operation ongoing) + * 1 : Busy (Rx operation ongoing) + * b0 (not used) + * x : Should be set to 0. + */ +typedef uint32_t HAL_UART_StateTypeDef; + +/** + * @brief UART clock sources definition + */ +typedef enum +{ + UART_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */ + UART_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */ + UART_CLOCKSOURCE_PCLK7 = 0x02U, /*!< PCLK7 clock source */ + UART_CLOCKSOURCE_HSI = 0x04U, /*!< HSI clock source */ + UART_CLOCKSOURCE_SYSCLK = 0x08U, /*!< SYSCLK clock source */ + UART_CLOCKSOURCE_LSE = 0x10U, /*!< LSE clock source */ + UART_CLOCKSOURCE_UNDEFINED = 0x20U, /*!< Undefined clock source */ +} UART_ClockSourceTypeDef; + +/** + * @brief HAL UART Reception type definition + * @note HAL UART Reception type value aims to identify which type of Reception is ongoing. + * This parameter can be a value of @ref UART_Reception_Type_Values : + * HAL_UART_RECEPTION_STANDARD = 0x00U, + * HAL_UART_RECEPTION_TOIDLE = 0x01U, + * HAL_UART_RECEPTION_TORTO = 0x02U, + * HAL_UART_RECEPTION_TOCHARMATCH = 0x03U, + */ +typedef uint32_t HAL_UART_RxTypeTypeDef; + +/** + * @brief HAL UART Rx Event type definition + * @note HAL UART Rx Event type value aims to identify which type of Event has occurred + * leading to call of the RxEvent callback. + * This parameter can be a value of @ref UART_RxEvent_Type_Values : + * HAL_UART_RXEVENT_TC = 0x00U, + * HAL_UART_RXEVENT_HT = 0x01U, + * HAL_UART_RXEVENT_IDLE = 0x02U, + */ +typedef uint32_t HAL_UART_RxEventTypeTypeDef; + +/** + * @brief UART handle Structure definition + */ +typedef struct __UART_HandleTypeDef +{ + USART_TypeDef *Instance; /*!< UART registers base address */ + + UART_InitTypeDef Init; /*!< UART communication parameters */ + + UART_AdvFeatureInitTypeDef AdvancedInit; /*!< UART Advanced Features initialization parameters */ + + const uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */ + + uint16_t TxXferSize; /*!< UART Tx Transfer size */ + + __IO uint16_t TxXferCount; /*!< UART Tx Transfer Counter */ + + uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */ + + uint16_t RxXferSize; /*!< UART Rx Transfer size */ + + __IO uint16_t RxXferCount; /*!< UART Rx Transfer Counter */ + + uint16_t Mask; /*!< UART Rx RDR register mask */ + + uint32_t FifoMode; /*!< Specifies if the FIFO mode is being used. + This parameter can be a value of @ref UARTEx_FIFO_mode. */ + + uint16_t NbRxDataToProcess; /*!< Number of data to process during RX ISR execution */ + + uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */ + + __IO HAL_UART_RxTypeTypeDef ReceptionType; /*!< Type of ongoing reception */ + + __IO HAL_UART_RxEventTypeTypeDef RxEventType; /*!< Type of Rx Event */ + + void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */ + + void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */ + +#if defined(HAL_DMA_MODULE_ENABLED) + DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */ + +#endif /* HAL_DMA_MODULE_ENABLED */ + HAL_LockTypeDef Lock; /*!< Locking object */ + + __IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management + and also related to Tx operations. This parameter + can be a value of @ref HAL_UART_StateTypeDef */ + + __IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations. This + parameter can be a value of @ref HAL_UART_StateTypeDef */ + + __IO uint32_t ErrorCode; /*!< UART Error code */ + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + void (* TxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Half Complete Callback */ + void (* TxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Complete Callback */ + void (* RxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Half Complete Callback */ + void (* RxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Complete Callback */ + void (* ErrorCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Error Callback */ + void (* AbortCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Complete Callback */ + void (* AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Transmit Complete Callback */ + void (* AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Receive Complete Callback */ + void (* RxFifoFullCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Fifo Full Callback */ + void (* TxFifoEmptyCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Fifo Empty Callback */ + void (* RxEventCallback)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< UART Reception Event Callback */ + + void (* MspInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp Init callback */ + void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp DeInit callback */ +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +} UART_HandleTypeDef; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +/** + * @brief HAL UART Callback ID enumeration definition + */ +typedef enum +{ + HAL_UART_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< UART Tx Half Complete Callback ID */ + HAL_UART_TX_COMPLETE_CB_ID = 0x01U, /*!< UART Tx Complete Callback ID */ + HAL_UART_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< UART Rx Half Complete Callback ID */ + HAL_UART_RX_COMPLETE_CB_ID = 0x03U, /*!< UART Rx Complete Callback ID */ + HAL_UART_ERROR_CB_ID = 0x04U, /*!< UART Error Callback ID */ + HAL_UART_ABORT_COMPLETE_CB_ID = 0x05U, /*!< UART Abort Complete Callback ID */ + HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, /*!< UART Abort Transmit Complete Callback ID */ + HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U, /*!< UART Abort Receive Complete Callback ID */ + HAL_UART_WAKEUP_CB_ID = 0x08U, /*!< UART Wakeup Callback ID */ + HAL_UART_RX_FIFO_FULL_CB_ID = 0x09U, /*!< UART Rx Fifo Full Callback ID */ + HAL_UART_TX_FIFO_EMPTY_CB_ID = 0x0AU, /*!< UART Tx Fifo Empty Callback ID */ + + HAL_UART_MSPINIT_CB_ID = 0x0BU, /*!< UART MspInit callback ID */ + HAL_UART_MSPDEINIT_CB_ID = 0x0CU /*!< UART MspDeInit callback ID */ + +} HAL_UART_CallbackIDTypeDef; + +/** + * @brief HAL UART Callback pointer definition + */ +typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */ +typedef void (*pUART_RxEventCallbackTypeDef) +(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< pointer to a UART Rx Event specific callback function */ + +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup UART_Exported_Constants UART Exported Constants + * @{ + */ + +/** @defgroup UART_State_Definition UART State Code Definition + * @{ + */ +#define HAL_UART_STATE_RESET 0x00000000U /*!< Peripheral is not initialized + Value is allowed for gState and RxState */ +#define HAL_UART_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for use + Value is allowed for gState and RxState */ +#define HAL_UART_STATE_BUSY 0x00000024U /*!< an internal process is ongoing + Value is allowed for gState only */ +#define HAL_UART_STATE_BUSY_TX 0x00000021U /*!< Data Transmission process is ongoing + Value is allowed for gState only */ +#define HAL_UART_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing + Value is allowed for RxState only */ +#define HAL_UART_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing + Not to be used for neither gState nor RxState.Value is result + of combination (Or) between gState and RxState values */ +#define HAL_UART_STATE_TIMEOUT 0x000000A0U /*!< Timeout state + Value is allowed for gState only */ +#define HAL_UART_STATE_ERROR 0x000000E0U /*!< Error + Value is allowed for gState only */ +/** + * @} + */ + +/** @defgroup UART_Error_Definition UART Error Definition + * @{ + */ +#define HAL_UART_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_UART_ERROR_PE (0x00000001U) /*!< Parity error */ +#define HAL_UART_ERROR_NE (0x00000002U) /*!< Noise error */ +#define HAL_UART_ERROR_FE (0x00000004U) /*!< Frame error */ +#define HAL_UART_ERROR_ORE (0x00000008U) /*!< Overrun error */ +#if defined(HAL_DMA_MODULE_ENABLED) +#define HAL_UART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#endif /* HAL_DMA_MODULE_ENABLED */ +#define HAL_UART_ERROR_RTO (0x00000020U) /*!< Receiver Timeout error */ + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +#define HAL_UART_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */ +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup UART_Stop_Bits UART Number of Stop Bits + * @{ + */ +#define UART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< UART frame with 0.5 stop bit */ +#define UART_STOPBITS_1 0x00000000U /*!< UART frame with 1 stop bit */ +#define UART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< UART frame with 1.5 stop bits */ +#define UART_STOPBITS_2 USART_CR2_STOP_1 /*!< UART frame with 2 stop bits */ +/** + * @} + */ + +/** @defgroup UART_Parity UART Parity + * @{ + */ +#define UART_PARITY_NONE 0x00000000U /*!< No parity */ +#define UART_PARITY_EVEN USART_CR1_PCE /*!< Even parity */ +#define UART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Odd parity */ +/** + * @} + */ + +/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control + * @{ + */ +#define UART_HWCONTROL_NONE 0x00000000U /*!< No hardware control */ +#define UART_HWCONTROL_RTS USART_CR3_RTSE /*!< Request To Send */ +#define UART_HWCONTROL_CTS USART_CR3_CTSE /*!< Clear To Send */ +#define UART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< Request and Clear To Send */ +/** + * @} + */ + +/** @defgroup UART_Mode UART Transfer Mode + * @{ + */ +#define UART_MODE_RX USART_CR1_RE /*!< RX mode */ +#define UART_MODE_TX USART_CR1_TE /*!< TX mode */ +#define UART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< RX and TX mode */ +/** + * @} + */ + +/** @defgroup UART_State UART State + * @{ + */ +#define UART_STATE_DISABLE 0x00000000U /*!< UART disabled */ +#define UART_STATE_ENABLE USART_CR1_UE /*!< UART enabled */ +/** + * @} + */ + +/** @defgroup UART_Over_Sampling UART Over Sampling + * @{ + */ +#define UART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */ +#define UART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */ +/** + * @} + */ + +/** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method + * @{ + */ +#define UART_ONE_BIT_SAMPLE_DISABLE 0x00000000U /*!< One-bit sampling disable */ +#define UART_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT /*!< One-bit sampling enable */ +/** + * @} + */ + +/** @defgroup UART_ClockPrescaler UART Clock Prescaler + * @{ + */ +#define UART_PRESCALER_DIV1 0x00000000U /*!< fclk_pres = fclk */ +#define UART_PRESCALER_DIV2 0x00000001U /*!< fclk_pres = fclk/2 */ +#define UART_PRESCALER_DIV4 0x00000002U /*!< fclk_pres = fclk/4 */ +#define UART_PRESCALER_DIV6 0x00000003U /*!< fclk_pres = fclk/6 */ +#define UART_PRESCALER_DIV8 0x00000004U /*!< fclk_pres = fclk/8 */ +#define UART_PRESCALER_DIV10 0x00000005U /*!< fclk_pres = fclk/10 */ +#define UART_PRESCALER_DIV12 0x00000006U /*!< fclk_pres = fclk/12 */ +#define UART_PRESCALER_DIV16 0x00000007U /*!< fclk_pres = fclk/16 */ +#define UART_PRESCALER_DIV32 0x00000008U /*!< fclk_pres = fclk/32 */ +#define UART_PRESCALER_DIV64 0x00000009U /*!< fclk_pres = fclk/64 */ +#define UART_PRESCALER_DIV128 0x0000000AU /*!< fclk_pres = fclk/128 */ +#define UART_PRESCALER_DIV256 0x0000000BU /*!< fclk_pres = fclk/256 */ +/** + * @} + */ + +/** @defgroup UART_AutoBaud_Rate_Mode UART Advanced Feature AutoBaud Rate Mode + * @{ + */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT 0x00000000U /*!< Auto Baud rate detection + on start bit */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0 /*!< Auto Baud rate detection + on falling edge */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME USART_CR2_ABRMODE_1 /*!< Auto Baud rate detection + on 0x7F frame detection */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME USART_CR2_ABRMODE /*!< Auto Baud rate detection + on 0x55 frame detection */ +/** + * @} + */ + +/** @defgroup UART_Receiver_Timeout UART Receiver Timeout + * @{ + */ +#define UART_RECEIVER_TIMEOUT_DISABLE 0x00000000U /*!< UART Receiver Timeout disable */ +#define UART_RECEIVER_TIMEOUT_ENABLE USART_CR2_RTOEN /*!< UART Receiver Timeout enable */ +/** + * @} + */ + +/** @defgroup UART_LIN UART Local Interconnection Network mode + * @{ + */ +#define UART_LIN_DISABLE 0x00000000U /*!< Local Interconnect Network disable */ +#define UART_LIN_ENABLE USART_CR2_LINEN /*!< Local Interconnect Network enable */ +/** + * @} + */ + +/** @defgroup UART_LIN_Break_Detection UART LIN Break Detection + * @{ + */ +#define UART_LINBREAKDETECTLENGTH_10B 0x00000000U /*!< LIN 10-bit break detection length */ +#define UART_LINBREAKDETECTLENGTH_11B USART_CR2_LBDL /*!< LIN 11-bit break detection length */ +/** + * @} + */ + +#if defined(HAL_DMA_MODULE_ENABLED) +/** @defgroup UART_DMA_Tx UART DMA Tx + * @{ + */ +#define UART_DMA_TX_DISABLE 0x00000000U /*!< UART DMA TX disabled */ +#define UART_DMA_TX_ENABLE USART_CR3_DMAT /*!< UART DMA TX enabled */ +/** + * @} + */ + +/** @defgroup UART_DMA_Rx UART DMA Rx + * @{ + */ +#define UART_DMA_RX_DISABLE 0x00000000U /*!< UART DMA RX disabled */ +#define UART_DMA_RX_ENABLE USART_CR3_DMAR /*!< UART DMA RX enabled */ +/** + * @} + */ +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** @defgroup UART_Half_Duplex_Selection UART Half Duplex Selection + * @{ + */ +#define UART_HALF_DUPLEX_DISABLE 0x00000000U /*!< UART half-duplex disabled */ +#define UART_HALF_DUPLEX_ENABLE USART_CR3_HDSEL /*!< UART half-duplex enabled */ +/** + * @} + */ + +/** @defgroup UART_WakeUp_Methods UART WakeUp Methods + * @{ + */ +#define UART_WAKEUPMETHOD_IDLELINE 0x00000000U /*!< UART wake-up on idle line */ +#define UART_WAKEUPMETHOD_ADDRESSMARK USART_CR1_WAKE /*!< UART wake-up on address mark */ +/** + * @} + */ + +/** @defgroup UART_Request_Parameters UART Request Parameters + * @{ + */ +#define UART_AUTOBAUD_REQUEST USART_RQR_ABRRQ /*!< Auto-Baud Rate Request */ +#define UART_SENDBREAK_REQUEST USART_RQR_SBKRQ /*!< Send Break Request */ +#define UART_MUTE_MODE_REQUEST USART_RQR_MMRQ /*!< Mute Mode Request */ +#define UART_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ /*!< Receive Data flush Request */ +#define UART_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ /*!< Transmit data flush Request */ +/** + * @} + */ + +/** @defgroup UART_Advanced_Features_Initialization_Type UART Advanced Feature Initialization Type + * @{ + */ +#define UART_ADVFEATURE_NO_INIT 0x00000000U /*!< No advanced feature initialization */ +#define UART_ADVFEATURE_TXINVERT_INIT 0x00000001U /*!< TX pin active level inversion */ +#define UART_ADVFEATURE_RXINVERT_INIT 0x00000002U /*!< RX pin active level inversion */ +#define UART_ADVFEATURE_DATAINVERT_INIT 0x00000004U /*!< Binary data inversion */ +#define UART_ADVFEATURE_SWAP_INIT 0x00000008U /*!< TX/RX pins swap */ +#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT 0x00000010U /*!< RX overrun disable */ +#if defined(HAL_DMA_MODULE_ENABLED) +#define UART_ADVFEATURE_DMADISABLEONERROR_INIT 0x00000020U /*!< DMA disable on Reception Error */ +#endif /* HAL_DMA_MODULE_ENABLED */ +#define UART_ADVFEATURE_AUTOBAUDRATE_INIT 0x00000040U /*!< Auto Baud rate detection initialization */ +#define UART_ADVFEATURE_MSBFIRST_INIT 0x00000080U /*!< Most significant bit sent/received first */ +/** + * @} + */ + +/** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion + * @{ + */ +#define UART_ADVFEATURE_TXINV_DISABLE 0x00000000U /*!< TX pin active level inversion disable */ +#define UART_ADVFEATURE_TXINV_ENABLE USART_CR2_TXINV /*!< TX pin active level inversion enable */ +/** + * @} + */ + +/** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion + * @{ + */ +#define UART_ADVFEATURE_RXINV_DISABLE 0x00000000U /*!< RX pin active level inversion disable */ +#define UART_ADVFEATURE_RXINV_ENABLE USART_CR2_RXINV /*!< RX pin active level inversion enable */ +/** + * @} + */ + +/** @defgroup UART_Data_Inv UART Advanced Feature Binary Data Inversion + * @{ + */ +#define UART_ADVFEATURE_DATAINV_DISABLE 0x00000000U /*!< Binary data inversion disable */ +#define UART_ADVFEATURE_DATAINV_ENABLE USART_CR2_DATAINV /*!< Binary data inversion enable */ +/** + * @} + */ + +/** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap + * @{ + */ +#define UART_ADVFEATURE_SWAP_DISABLE 0x00000000U /*!< TX/RX pins swap disable */ +#define UART_ADVFEATURE_SWAP_ENABLE USART_CR2_SWAP /*!< TX/RX pins swap enable */ +/** + * @} + */ + +/** @defgroup UART_Overrun_Disable UART Advanced Feature Overrun Disable + * @{ + */ +#define UART_ADVFEATURE_OVERRUN_ENABLE 0x00000000U /*!< RX overrun enable */ +#define UART_ADVFEATURE_OVERRUN_DISABLE USART_CR3_OVRDIS /*!< RX overrun disable */ +/** + * @} + */ + +/** @defgroup UART_AutoBaudRate_Enable UART Advanced Feature Auto BaudRate Enable + * @{ + */ +#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE 0x00000000U /*!< RX Auto Baud rate detection enable */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE USART_CR2_ABREN /*!< RX Auto Baud rate detection disable */ +/** + * @} + */ + +#if defined(HAL_DMA_MODULE_ENABLED) +/** @defgroup UART_DMA_Disable_on_Rx_Error UART Advanced Feature DMA Disable On Rx Error + * @{ + */ +#define UART_ADVFEATURE_DMA_ENABLEONRXERROR 0x00000000U /*!< DMA enable on Reception Error */ +#define UART_ADVFEATURE_DMA_DISABLEONRXERROR USART_CR3_DDRE /*!< DMA disable on Reception Error */ +/** + * @} + */ +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** @defgroup UART_MSB_First UART Advanced Feature MSB First + * @{ + */ +#define UART_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U /*!< Most significant bit sent/received + first disable */ +#define UART_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST /*!< Most significant bit sent/received + first enable */ +/** + * @} + */ + +/** @defgroup UART_Stop_Mode_Enable UART Advanced Feature Stop Mode Enable + * @{ + */ +#define UART_ADVFEATURE_STOPMODE_DISABLE 0x00000000U /*!< UART stop mode disable */ +#define UART_ADVFEATURE_STOPMODE_ENABLE USART_CR1_UESM /*!< UART stop mode enable */ +/** + * @} + */ + +/** @defgroup UART_Mute_Mode UART Advanced Feature Mute Mode Enable + * @{ + */ +#define UART_ADVFEATURE_MUTEMODE_DISABLE 0x00000000U /*!< UART mute mode disable */ +#define UART_ADVFEATURE_MUTEMODE_ENABLE USART_CR1_MME /*!< UART mute mode enable */ +/** + * @} + */ + +/** @defgroup UART_CR2_ADDRESS_LSB_POS UART Address-matching LSB Position In CR2 Register + * @{ + */ +#define UART_CR2_ADDRESS_LSB_POS 24U /*!< UART address-matching LSB position in CR2 register */ +/** + * @} + */ + +/** @defgroup UART_WakeUp_from_Stop_Selection UART WakeUp From Stop Selection + * @{ + */ +#define UART_WAKEUP_ON_ADDRESS 0x00000000U /*!< UART wake-up on address */ +#define UART_WAKEUP_ON_READDATA_NONEMPTY 0x00000001U /*!< UART wake-up on receive data register + not empty or RXFIFO is not empty */ +/** + * @} + */ + +/** @defgroup UART_DriverEnable_Polarity UART DriverEnable Polarity + * @{ + */ +#define UART_DE_POLARITY_HIGH 0x00000000U /*!< Driver enable signal is active high */ +#define UART_DE_POLARITY_LOW USART_CR3_DEP /*!< Driver enable signal is active low */ +/** + * @} + */ + +/** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS UART Driver Enable Assertion Time LSB Position In CR1 Register + * @{ + */ +#define UART_CR1_DEAT_ADDRESS_LSB_POS 21U /*!< UART Driver Enable assertion time LSB + position in CR1 register */ +/** + * @} + */ + +/** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS UART Driver Enable DeAssertion Time LSB Position In CR1 Register + * @{ + */ +#define UART_CR1_DEDT_ADDRESS_LSB_POS 16U /*!< UART Driver Enable de-assertion time LSB + position in CR1 register */ +/** + * @} + */ + +/** @defgroup UART_Interruption_Mask UART Interruptions Flag Mask + * @{ + */ +#define UART_IT_MASK 0x001FU /*!< UART interruptions flags mask */ +/** + * @} + */ + +/** @defgroup UART_TimeOut_Value UART polling-based communications time-out value + * @{ + */ +#define HAL_UART_TIMEOUT_VALUE 0x1FFFFFFU /*!< UART polling-based communications time-out value */ +/** + * @} + */ + +/** @defgroup UART_Flags UART Status Flags + * Elements values convention: 0xXXXX + * - 0xXXXX : Flag mask in the ISR register + * @{ + */ +#define UART_FLAG_TXFT USART_ISR_TXFT /*!< UART TXFIFO threshold flag */ +#define UART_FLAG_RXFT USART_ISR_RXFT /*!< UART RXFIFO threshold flag */ +#define UART_FLAG_RXFF USART_ISR_RXFF /*!< UART RXFIFO Full flag */ +#define UART_FLAG_TXFE USART_ISR_TXFE /*!< UART TXFIFO Empty flag */ +#define UART_FLAG_REACK USART_ISR_REACK /*!< UART receive enable acknowledge flag */ +#define UART_FLAG_TEACK USART_ISR_TEACK /*!< UART transmit enable acknowledge flag */ +#define UART_FLAG_RWU USART_ISR_RWU /*!< UART receiver wake-up from mute mode flag */ +#define UART_FLAG_SBKF USART_ISR_SBKF /*!< UART send break flag */ +#define UART_FLAG_CMF USART_ISR_CMF /*!< UART character match flag */ +#define UART_FLAG_BUSY USART_ISR_BUSY /*!< UART busy flag */ +#define UART_FLAG_ABRF USART_ISR_ABRF /*!< UART auto Baud rate flag */ +#define UART_FLAG_ABRE USART_ISR_ABRE /*!< UART auto Baud rate error */ +#define UART_FLAG_RTOF USART_ISR_RTOF /*!< UART receiver timeout flag */ +#define UART_FLAG_CTS USART_ISR_CTS /*!< UART clear to send flag */ +#define UART_FLAG_CTSIF USART_ISR_CTSIF /*!< UART clear to send interrupt flag */ +#define UART_FLAG_LBDF USART_ISR_LBDF /*!< UART LIN break detection flag */ +#define UART_FLAG_TXE USART_ISR_TXE_TXFNF /*!< UART transmit data register empty */ +#define UART_FLAG_TXFNF USART_ISR_TXE_TXFNF /*!< UART TXFIFO not full */ +#define UART_FLAG_TC USART_ISR_TC /*!< UART transmission complete */ +#define UART_FLAG_RXNE USART_ISR_RXNE_RXFNE /*!< UART read data register not empty */ +#define UART_FLAG_RXFNE USART_ISR_RXNE_RXFNE /*!< UART RXFIFO not empty */ +#define UART_FLAG_IDLE USART_ISR_IDLE /*!< UART idle flag */ +#define UART_FLAG_ORE USART_ISR_ORE /*!< UART overrun error */ +#define UART_FLAG_NE USART_ISR_NE /*!< UART noise error */ +#define UART_FLAG_FE USART_ISR_FE /*!< UART frame error */ +#define UART_FLAG_PE USART_ISR_PE /*!< UART parity error */ +/** + * @} + */ + +/** @defgroup UART_Interrupt_definition UART Interrupts Definition + * Elements values convention: 000ZZZZZ0XXYYYYYb + * - YYYYY : Interrupt source position in the XX register (5bits) + * - XX : Interrupt source register (2bits) + * - 01: CR1 register + * - 10: CR2 register + * - 11: CR3 register + * - ZZZZZ : Flag position in the ISR register(5bits) + * Elements values convention: 000000000XXYYYYYb + * - YYYYY : Interrupt source position in the XX register (5bits) + * - XX : Interrupt source register (2bits) + * - 01: CR1 register + * - 10: CR2 register + * - 11: CR3 register + * Elements values convention: 0000ZZZZ00000000b + * - ZZZZ : Flag position in the ISR register(4bits) + * @{ + */ +#define UART_IT_PE 0x0028U /*!< UART parity error interruption */ +#define UART_IT_TXE 0x0727U /*!< UART transmit data register empty interruption */ +#define UART_IT_TXFNF 0x0727U /*!< UART TX FIFO not full interruption */ +#define UART_IT_TC 0x0626U /*!< UART transmission complete interruption */ +#define UART_IT_RXNE 0x0525U /*!< UART read data register not empty interruption */ +#define UART_IT_RXFNE 0x0525U /*!< UART RXFIFO not empty interruption */ +#define UART_IT_IDLE 0x0424U /*!< UART idle interruption */ +#define UART_IT_LBD 0x0846U /*!< UART LIN break detection interruption */ +#define UART_IT_CTS 0x096AU /*!< UART CTS interruption */ +#define UART_IT_CM 0x112EU /*!< UART character match interruption */ +#define UART_IT_RXFF 0x183FU /*!< UART RXFIFO full interruption */ +#define UART_IT_TXFE 0x173EU /*!< UART TXFIFO empty interruption */ +#define UART_IT_RXFT 0x1A7CU /*!< UART RXFIFO threshold reached interruption */ +#define UART_IT_TXFT 0x1B77U /*!< UART TXFIFO threshold reached interruption */ +#define UART_IT_RTO 0x0B3AU /*!< UART receiver timeout interruption */ + +#define UART_IT_ERR 0x0060U /*!< UART error interruption */ + +#define UART_IT_ORE 0x0300U /*!< UART overrun error interruption */ +#define UART_IT_NE 0x0200U /*!< UART noise error interruption */ +#define UART_IT_FE 0x0100U /*!< UART frame error interruption */ +/** + * @} + */ + +/** @defgroup UART_IT_CLEAR_Flags UART Interruption Clear Flags + * @{ + */ +#define UART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */ +#define UART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */ +#define UART_CLEAR_NEF USART_ICR_NECF /*!< Noise Error detected Clear Flag */ +#define UART_CLEAR_OREF USART_ICR_ORECF /*!< Overrun Error Clear Flag */ +#define UART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */ +#define UART_CLEAR_TXFECF USART_ICR_TXFECF /*!< TXFIFO empty clear flag */ +#define UART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */ +#define UART_CLEAR_LBDF USART_ICR_LBDCF /*!< LIN Break Detection Clear Flag */ +#define UART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */ +#define UART_CLEAR_CMF USART_ICR_CMCF /*!< Character Match Clear Flag */ +#define UART_CLEAR_RTOF USART_ICR_RTOCF /*!< UART receiver timeout clear flag */ +/** + * @} + */ + +/** @defgroup UART_Reception_Type_Values UART Reception type values + * @{ + */ +#define HAL_UART_RECEPTION_STANDARD (0x00000000U) /*!< Standard reception */ +#define HAL_UART_RECEPTION_TOIDLE (0x00000001U) /*!< Reception till completion or IDLE event */ +#define HAL_UART_RECEPTION_TORTO (0x00000002U) /*!< Reception till completion or RTO event */ +#define HAL_UART_RECEPTION_TOCHARMATCH (0x00000003U) /*!< Reception till completion or CM event */ +/** + * @} + */ + +/** @defgroup UART_RxEvent_Type_Values UART RxEvent type values + * @{ + */ +#define HAL_UART_RXEVENT_TC (0x00000000U) /*!< RxEvent linked to Transfer Complete event */ +#define HAL_UART_RXEVENT_HT (0x00000001U) /*!< RxEvent linked to Half Transfer event */ +#define HAL_UART_RXEVENT_IDLE (0x00000002U) /*!< RxEvent linked to IDLE event */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup UART_Exported_Macros UART Exported Macros + * @{ + */ + +/** @brief Reset UART handle states. + * @param __HANDLE__ UART handle. + * @retval None + */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->gState = HAL_UART_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0U) +#else +#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->gState = HAL_UART_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \ + } while(0U) +#endif /*USE_HAL_UART_REGISTER_CALLBACKS */ + +/** @brief Flush the UART Data registers. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) \ + do{ \ + SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \ + SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \ + } while(0U) + +/** @brief Clear the specified UART pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be any combination of the following values: + * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag + * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag + * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag + * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag + * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag + * @arg @ref UART_CLEAR_TXFECF TXFIFO empty clear Flag + * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag + * @arg @ref UART_CLEAR_RTOF Receiver Timeout clear flag + * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag + * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag + * @arg @ref UART_CLEAR_CMF Character Match Clear Flag + * @retval None + */ +#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) + +/** @brief Clear the UART PE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF) + +/** @brief Clear the UART FE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF) + +/** @brief Clear the UART NE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF) + +/** @brief Clear the UART ORE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF) + +/** @brief Clear the UART IDLE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF) + +/** @brief Clear the UART TX FIFO empty clear flag. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_TXFECF(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_TXFECF) + +/** @brief Check whether the specified UART flag is set or not. + * @param __HANDLE__ specifies the UART Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref UART_FLAG_TXFT TXFIFO threshold flag + * @arg @ref UART_FLAG_RXFT RXFIFO threshold flag + * @arg @ref UART_FLAG_RXFF RXFIFO Full flag + * @arg @ref UART_FLAG_TXFE TXFIFO Empty flag + * @arg @ref UART_FLAG_REACK Receive enable acknowledge flag + * @arg @ref UART_FLAG_TEACK Transmit enable acknowledge flag + * @arg @ref UART_FLAG_RWU Receiver wake up flag (if the UART in mute mode) + * @arg @ref UART_FLAG_SBKF Send Break flag + * @arg @ref UART_FLAG_CMF Character match flag + * @arg @ref UART_FLAG_BUSY Busy flag + * @arg @ref UART_FLAG_ABRF Auto Baud rate detection flag + * @arg @ref UART_FLAG_ABRE Auto Baud rate detection error flag + * @arg @ref UART_FLAG_CTS CTS Change flag + * @arg @ref UART_FLAG_LBDF LIN Break detection flag + * @arg @ref UART_FLAG_TXE Transmit data register empty flag + * @arg @ref UART_FLAG_TXFNF UART TXFIFO not full flag + * @arg @ref UART_FLAG_TC Transmission Complete flag + * @arg @ref UART_FLAG_RXNE Receive data register not empty flag + * @arg @ref UART_FLAG_RXFNE UART RXFIFO not empty flag + * @arg @ref UART_FLAG_RTOF Receiver Timeout flag + * @arg @ref UART_FLAG_IDLE Idle Line detection flag + * @arg @ref UART_FLAG_ORE Overrun Error flag + * @arg @ref UART_FLAG_NE Noise Error flag + * @arg @ref UART_FLAG_FE Framing Error flag + * @arg @ref UART_FLAG_PE Parity Error flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) + +/** @brief Enable the specified UART interrupt. + * @param __HANDLE__ specifies the UART Handle. + * @param __INTERRUPT__ specifies the UART interrupt source to enable. + * This parameter can be one of the following values: + * @arg @ref UART_IT_RXFF RXFIFO Full interrupt + * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt + * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt + * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt + * @arg @ref UART_IT_CM Character match interrupt + * @arg @ref UART_IT_CTS CTS change interrupt + * @arg @ref UART_IT_LBD LIN Break detection interrupt + * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt + * @arg @ref UART_IT_TC Transmission complete interrupt + * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref UART_IT_RTO Receive Timeout interrupt + * @arg @ref UART_IT_IDLE Idle line detection interrupt + * @arg @ref UART_IT_PE Parity Error interrupt + * @arg @ref UART_IT_ERR Error interrupt (frame error, noise error, overrun error) + * @retval None + */ +#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (\ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)?\ + ((__HANDLE__)->Instance->CR1 |= (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK))): \ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)?\ + ((__HANDLE__)->Instance->CR2 |= (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 |= (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK)))) + +/** @brief Disable the specified UART interrupt. + * @param __HANDLE__ specifies the UART Handle. + * @param __INTERRUPT__ specifies the UART interrupt source to disable. + * This parameter can be one of the following values: + * @arg @ref UART_IT_RXFF RXFIFO Full interrupt + * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt + * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt + * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt + * @arg @ref UART_IT_CM Character match interrupt + * @arg @ref UART_IT_CTS CTS change interrupt + * @arg @ref UART_IT_LBD LIN Break detection interrupt + * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt + * @arg @ref UART_IT_TC Transmission complete interrupt + * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref UART_IT_RTO Receive Timeout interrupt + * @arg @ref UART_IT_IDLE Idle line detection interrupt + * @arg @ref UART_IT_PE Parity Error interrupt + * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) + * @retval None + */ +#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (\ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)?\ + ((__HANDLE__)->Instance->CR1 &= ~ (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK))): \ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)?\ + ((__HANDLE__)->Instance->CR2 &= ~ (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 &= ~ (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK)))) + +/** @brief Check whether the specified UART interrupt has occurred or not. + * @param __HANDLE__ specifies the UART Handle. + * @param __INTERRUPT__ specifies the UART interrupt to check. + * This parameter can be one of the following values: + * @arg @ref UART_IT_RXFF RXFIFO Full interrupt + * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt + * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt + * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt + * @arg @ref UART_IT_CM Character match interrupt + * @arg @ref UART_IT_CTS CTS change interrupt + * @arg @ref UART_IT_LBD LIN Break detection interrupt + * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt + * @arg @ref UART_IT_TC Transmission complete interrupt + * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref UART_IT_RTO Receive Timeout interrupt + * @arg @ref UART_IT_IDLE Idle line detection interrupt + * @arg @ref UART_IT_PE Parity Error interrupt + * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\ + & (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET) + +/** @brief Check whether the specified UART interrupt source is enabled or not. + * @param __HANDLE__ specifies the UART Handle. + * @param __INTERRUPT__ specifies the UART interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref UART_IT_RXFF RXFIFO Full interrupt + * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt + * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt + * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt + * @arg @ref UART_IT_CM Character match interrupt + * @arg @ref UART_IT_CTS CTS change interrupt + * @arg @ref UART_IT_LBD LIN Break detection interrupt + * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt + * @arg @ref UART_IT_TC Transmission complete interrupt + * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref UART_IT_RTO Receive Timeout interrupt + * @arg @ref UART_IT_IDLE Idle line detection interrupt + * @arg @ref UART_IT_PE Parity Error interrupt + * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ?\ + (__HANDLE__)->Instance->CR1 : \ + (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ?\ + (__HANDLE__)->Instance->CR2 : \ + (__HANDLE__)->Instance->CR3)) & (1U <<\ + (((uint16_t)(__INTERRUPT__)) &\ + UART_IT_MASK))) != RESET) ? SET : RESET) + +/** @brief Clear the specified UART ISR flag, in setting the proper ICR register flag. + * @param __HANDLE__ specifies the UART Handle. + * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set + * to clear the corresponding interrupt + * This parameter can be one of the following values: + * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag + * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag + * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag + * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag + * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag + * @arg @ref UART_CLEAR_RTOF Receiver timeout clear flag + * @arg @ref UART_CLEAR_TXFECF TXFIFO empty Clear Flag + * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag + * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag + * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag + * @arg @ref UART_CLEAR_CMF Character Match Clear Flag + * @retval None + */ +#define __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__)) + +/** @brief Set a specific UART request flag. + * @param __HANDLE__ specifies the UART Handle. + * @param __REQ__ specifies the request flag to set + * This parameter can be one of the following values: + * @arg @ref UART_AUTOBAUD_REQUEST Auto-Baud Rate Request + * @arg @ref UART_SENDBREAK_REQUEST Send Break Request + * @arg @ref UART_MUTE_MODE_REQUEST Mute Mode Request + * @arg @ref UART_RXDATA_FLUSH_REQUEST Receive Data flush Request + * @arg @ref UART_TXDATA_FLUSH_REQUEST Transmit data flush Request + * @retval None + */ +#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) + +/** @brief Enable the UART one bit sample method. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) + +/** @brief Disable the UART one bit sample method. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT) + +/** @brief Enable UART. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) + +/** @brief Disable UART. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) + +/** @brief Enable CTS flow control. + * @note This macro allows to enable CTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled + * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable + * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \ + do{ \ + ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ + (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \ + } while(0U) + +/** @brief Disable CTS flow control. + * @note This macro allows to disable CTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled + * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable + * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \ + do{ \ + ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ + (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \ + } while(0U) + +/** @brief Enable RTS flow control. + * @note This macro allows to enable RTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled + * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable + * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \ + do{ \ + ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \ + (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \ + } while(0U) + +/** @brief Disable RTS flow control. + * @note This macro allows to disable RTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled + * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable + * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \ + do{ \ + ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\ + (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \ + } while(0U) +/** + * @} + */ + +/* Private macros --------------------------------------------------------*/ +/** @defgroup UART_Private_Macros UART Private Macros + * @{ + */ +/** @brief Get UART clok division factor from clock prescaler value. + * @param __CLOCKPRESCALER__ UART prescaler value. + * @retval UART clock division factor + */ +#define UART_GET_DIV_FACTOR(__CLOCKPRESCALER__) \ + (((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1) ? 1U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2) ? 2U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4) ? 4U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6) ? 6U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8) ? 8U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10) ? 10U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12) ? 12U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16) ? 16U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32) ? 32U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64) ? 64U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256) ? 256U : 1U) + +/** @brief BRR division operation to set BRR register with LPUART. + * @param __PCLK__ LPUART clock. + * @param __BAUD__ Baud rate set by the user. + * @param __CLOCKPRESCALER__ UART prescaler value. + * @retval Division result + */ +#define UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__) \ + ((uint32_t)((((((uint64_t)(__PCLK__))/(UARTPrescTable[(__CLOCKPRESCALER__)]))*256U)+ \ + (uint32_t)((__BAUD__)/2U)) / (__BAUD__)) \ + ) + +/** @brief BRR division operation to set BRR register in 8-bit oversampling mode. + * @param __PCLK__ UART clock. + * @param __BAUD__ Baud rate set by the user. + * @param __CLOCKPRESCALER__ UART prescaler value. + * @retval Division result + */ +#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) \ + (((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)])*2U) + ((__BAUD__)/2U)) / (__BAUD__)) + +/** @brief BRR division operation to set BRR register in 16-bit oversampling mode. + * @param __PCLK__ UART clock. + * @param __BAUD__ Baud rate set by the user. + * @param __CLOCKPRESCALER__ UART prescaler value. + * @retval Division result + */ +#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__) \ + ((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)]) + ((__BAUD__)/2U)) / (__BAUD__)) + +/** @brief Check whether or not UART instance is Low Power UART. + * @param __HANDLE__ specifies the UART Handle. + * @retval SET (instance is LPUART) or RESET (instance isn't LPUART) + */ +#define UART_INSTANCE_LOWPOWER(__HANDLE__) (IS_LPUART_INSTANCE((__HANDLE__)->Instance)) + +/** @brief Check UART Baud rate. + * @param __BAUDRATE__ Baudrate specified by the user. + * The maximum Baud Rate is derived from the maximum clock on WBA (i.e. 100 MHz) + * divided by the smallest oversampling used on the USART (i.e. 8) + * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid) + */ +#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 12500000U) + +/** @brief Check UART assertion time. + * @param __TIME__ 5-bit value assertion time. + * @retval Test result (TRUE or FALSE). + */ +#define IS_UART_ASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU) + +/** @brief Check UART deassertion time. + * @param __TIME__ 5-bit value deassertion time. + * @retval Test result (TRUE or FALSE). + */ +#define IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU) + +/** + * @brief Ensure that UART frame number of stop bits is valid. + * @param __STOPBITS__ UART frame number of stop bits. + * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) + */ +#define IS_UART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_0_5) || \ + ((__STOPBITS__) == UART_STOPBITS_1) || \ + ((__STOPBITS__) == UART_STOPBITS_1_5) || \ + ((__STOPBITS__) == UART_STOPBITS_2)) + +/** + * @brief Ensure that LPUART frame number of stop bits is valid. + * @param __STOPBITS__ LPUART frame number of stop bits. + * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) + */ +#define IS_LPUART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_1) || \ + ((__STOPBITS__) == UART_STOPBITS_2)) + +/** + * @brief Ensure that UART frame parity is valid. + * @param __PARITY__ UART frame parity. + * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid) + */ +#define IS_UART_PARITY(__PARITY__) (((__PARITY__) == UART_PARITY_NONE) || \ + ((__PARITY__) == UART_PARITY_EVEN) || \ + ((__PARITY__) == UART_PARITY_ODD)) + +/** + * @brief Ensure that UART hardware flow control is valid. + * @param __CONTROL__ UART hardware flow control. + * @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid) + */ +#define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\ + (((__CONTROL__) == UART_HWCONTROL_NONE) || \ + ((__CONTROL__) == UART_HWCONTROL_RTS) || \ + ((__CONTROL__) == UART_HWCONTROL_CTS) || \ + ((__CONTROL__) == UART_HWCONTROL_RTS_CTS)) + +/** + * @brief Ensure that UART communication mode is valid. + * @param __MODE__ UART communication mode. + * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) + */ +#define IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U)) + +/** + * @brief Ensure that UART state is valid. + * @param __STATE__ UART state. + * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid) + */ +#define IS_UART_STATE(__STATE__) (((__STATE__) == UART_STATE_DISABLE) || \ + ((__STATE__) == UART_STATE_ENABLE)) + +/** + * @brief Ensure that UART oversampling is valid. + * @param __SAMPLING__ UART oversampling. + * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid) + */ +#define IS_UART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == UART_OVERSAMPLING_16) || \ + ((__SAMPLING__) == UART_OVERSAMPLING_8)) + +/** + * @brief Ensure that UART frame sampling is valid. + * @param __ONEBIT__ UART frame sampling. + * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid) + */ +#define IS_UART_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) || \ + ((__ONEBIT__) == UART_ONE_BIT_SAMPLE_ENABLE)) + +/** + * @brief Ensure that UART auto Baud rate detection mode is valid. + * @param __MODE__ UART auto Baud rate detection mode. + * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) + */ +#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__) (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || \ + ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \ + ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME) || \ + ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME)) + +/** + * @brief Ensure that UART receiver timeout setting is valid. + * @param __TIMEOUT__ UART receiver timeout setting. + * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid) + */ +#define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \ + ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE)) + +/** @brief Check the receiver timeout value. + * @note The maximum UART receiver timeout value is 0xFFFFFF. + * @param __TIMEOUTVALUE__ receiver timeout value. + * @retval Test result (TRUE or FALSE) + */ +#define IS_UART_RECEIVER_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFFU) + +/** + * @brief Ensure that UART LIN state is valid. + * @param __LIN__ UART LIN state. + * @retval SET (__LIN__ is valid) or RESET (__LIN__ is invalid) + */ +#define IS_UART_LIN(__LIN__) (((__LIN__) == UART_LIN_DISABLE) || \ + ((__LIN__) == UART_LIN_ENABLE)) + +/** + * @brief Ensure that UART LIN break detection length is valid. + * @param __LENGTH__ UART LIN break detection length. + * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) + */ +#define IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \ + ((__LENGTH__) == UART_LINBREAKDETECTLENGTH_11B)) + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Ensure that UART DMA TX state is valid. + * @param __DMATX__ UART DMA TX state. + * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid) + */ +#define IS_UART_DMA_TX(__DMATX__) (((__DMATX__) == UART_DMA_TX_DISABLE) || \ + ((__DMATX__) == UART_DMA_TX_ENABLE)) + +/** + * @brief Ensure that UART DMA RX state is valid. + * @param __DMARX__ UART DMA RX state. + * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid) + */ +#define IS_UART_DMA_RX(__DMARX__) (((__DMARX__) == UART_DMA_RX_DISABLE) || \ + ((__DMARX__) == UART_DMA_RX_ENABLE)) + +#endif /* HAL_DMA_MODULE_ENABLED */ +/** + * @brief Ensure that UART half-duplex state is valid. + * @param __HDSEL__ UART half-duplex state. + * @retval SET (__HDSEL__ is valid) or RESET (__HDSEL__ is invalid) + */ +#define IS_UART_HALF_DUPLEX(__HDSEL__) (((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) || \ + ((__HDSEL__) == UART_HALF_DUPLEX_ENABLE)) + +/** + * @brief Ensure that UART wake-up method is valid. + * @param __WAKEUP__ UART wake-up method . + * @retval SET (__WAKEUP__ is valid) or RESET (__WAKEUP__ is invalid) + */ +#define IS_UART_WAKEUPMETHOD(__WAKEUP__) (((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) || \ + ((__WAKEUP__) == UART_WAKEUPMETHOD_ADDRESSMARK)) + +/** + * @brief Ensure that UART request parameter is valid. + * @param __PARAM__ UART request parameter. + * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid) + */ +#define IS_UART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == UART_AUTOBAUD_REQUEST) || \ + ((__PARAM__) == UART_SENDBREAK_REQUEST) || \ + ((__PARAM__) == UART_MUTE_MODE_REQUEST) || \ + ((__PARAM__) == UART_RXDATA_FLUSH_REQUEST) || \ + ((__PARAM__) == UART_TXDATA_FLUSH_REQUEST)) + +/** + * @brief Ensure that UART advanced features initialization is valid. + * @param __INIT__ UART advanced features initialization. + * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid) + */ +#if defined(HAL_DMA_MODULE_ENABLED) +#define IS_UART_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (UART_ADVFEATURE_NO_INIT | \ + UART_ADVFEATURE_TXINVERT_INIT | \ + UART_ADVFEATURE_RXINVERT_INIT | \ + UART_ADVFEATURE_DATAINVERT_INIT | \ + UART_ADVFEATURE_SWAP_INIT | \ + UART_ADVFEATURE_RXOVERRUNDISABLE_INIT | \ + UART_ADVFEATURE_DMADISABLEONERROR_INIT | \ + UART_ADVFEATURE_AUTOBAUDRATE_INIT | \ + UART_ADVFEATURE_MSBFIRST_INIT)) +#else +#define IS_UART_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (UART_ADVFEATURE_NO_INIT | \ + UART_ADVFEATURE_TXINVERT_INIT | \ + UART_ADVFEATURE_RXINVERT_INIT | \ + UART_ADVFEATURE_DATAINVERT_INIT | \ + UART_ADVFEATURE_SWAP_INIT | \ + UART_ADVFEATURE_RXOVERRUNDISABLE_INIT | \ + UART_ADVFEATURE_AUTOBAUDRATE_INIT | \ + UART_ADVFEATURE_MSBFIRST_INIT)) +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Ensure that UART frame TX inversion setting is valid. + * @param __TXINV__ UART frame TX inversion setting. + * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid) + */ +#define IS_UART_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) || \ + ((__TXINV__) == UART_ADVFEATURE_TXINV_ENABLE)) + +/** + * @brief Ensure that UART frame RX inversion setting is valid. + * @param __RXINV__ UART frame RX inversion setting. + * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid) + */ +#define IS_UART_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) || \ + ((__RXINV__) == UART_ADVFEATURE_RXINV_ENABLE)) + +/** + * @brief Ensure that UART frame data inversion setting is valid. + * @param __DATAINV__ UART frame data inversion setting. + * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid) + */ +#define IS_UART_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) || \ + ((__DATAINV__) == UART_ADVFEATURE_DATAINV_ENABLE)) + +/** + * @brief Ensure that UART frame RX/TX pins swap setting is valid. + * @param __SWAP__ UART frame RX/TX pins swap setting. + * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid) + */ +#define IS_UART_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) || \ + ((__SWAP__) == UART_ADVFEATURE_SWAP_ENABLE)) + +/** + * @brief Ensure that UART frame overrun setting is valid. + * @param __OVERRUN__ UART frame overrun setting. + * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid) + */ +#define IS_UART_OVERRUN(__OVERRUN__) (((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) || \ + ((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_DISABLE)) + +/** + * @brief Ensure that UART auto Baud rate state is valid. + * @param __AUTOBAUDRATE__ UART auto Baud rate state. + * @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid) + */ +#define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__) (((__AUTOBAUDRATE__) == \ + UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \ + ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)) + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Ensure that UART DMA enabling or disabling on error setting is valid. + * @param __DMA__ UART DMA enabling or disabling on error setting. + * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid) + */ +#define IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \ + ((__DMA__) == UART_ADVFEATURE_DMA_DISABLEONRXERROR)) +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Ensure that UART frame MSB first setting is valid. + * @param __MSBFIRST__ UART frame MSB first setting. + * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid) + */ +#define IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \ + ((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_ENABLE)) + +/** + * @brief Ensure that UART stop mode state is valid. + * @param __STOPMODE__ UART stop mode state. + * @retval SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid) + */ +#define IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__) (((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || \ + ((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_ENABLE)) + +/** + * @brief Ensure that UART mute mode state is valid. + * @param __MUTE__ UART mute mode state. + * @retval SET (__MUTE__ is valid) or RESET (__MUTE__ is invalid) + */ +#define IS_UART_MUTE_MODE(__MUTE__) (((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \ + ((__MUTE__) == UART_ADVFEATURE_MUTEMODE_ENABLE)) + +/** + * @brief Ensure that UART wake-up selection is valid. + * @param __WAKE__ UART wake-up selection. + * @retval SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid) + */ +#define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS) || \ + ((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY)) + +/** + * @brief Ensure that UART driver enable polarity is valid. + * @param __POLARITY__ UART driver enable polarity. + * @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid) + */ +#define IS_UART_DE_POLARITY(__POLARITY__) (((__POLARITY__) == UART_DE_POLARITY_HIGH) || \ + ((__POLARITY__) == UART_DE_POLARITY_LOW)) + +/** + * @brief Ensure that UART Prescaler is valid. + * @param __CLOCKPRESCALER__ UART Prescaler value. + * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid) + */ +#define IS_UART_PRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256)) + +/** + * @} + */ + +/* Include UART HAL Extended module */ +#include "stm32wbaxx_hal_uart_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup UART_Exported_Functions UART Exported Functions + * @{ + */ + +/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ +HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength); +HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod); +HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart); +void HAL_UART_MspInit(UART_HandleTypeDef *huart); +void HAL_UART_MspDeInit(UART_HandleTypeDef *huart); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, + pUART_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @addtogroup UART_Exported_Functions_Group2 IO operation functions + * @{ + */ + +/* IO operation functions *****************************************************/ +HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +#if defined(HAL_DMA_MODULE_ENABLED) +HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart); +#endif /* HAL_DMA_MODULE_ENABLED */ +/* Transfer Abort functions */ +HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart); + +void HAL_UART_IRQHandler(UART_HandleTypeDef *huart); +void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart); +void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart); + +void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size); + +/** + * @} + */ + +/** @addtogroup UART_Exported_Functions_Group3 Peripheral Control functions + * @{ + */ + +/* Peripheral Control functions ************************************************/ +void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue); +HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart); + +HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart); +void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart); + +/** + * @} + */ + +/** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Error functions + * @{ + */ + +/* Peripheral State and Errors functions **************************************************/ +HAL_UART_StateTypeDef HAL_UART_GetState(const UART_HandleTypeDef *huart); +uint32_t HAL_UART_GetError(const UART_HandleTypeDef *huart); + +/** + * @} + */ + +/** + * @} + */ + +/* Private functions -----------------------------------------------------------*/ +/** @addtogroup UART_Private_Functions UART Private Functions + * @{ + */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart); +HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart); +HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout); +void UART_AdvFeatureConfig(UART_HandleTypeDef *huart); +HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +#if defined(HAL_DMA_MODULE_ENABLED) +HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @} + */ + +/* Private variables -----------------------------------------------------------*/ +/** @defgroup UART_Private_variables UART Private variables + * @{ + */ +/* Prescaler Table used in BRR computation macros. + Declared as extern here to allow use of private UART macros, outside of HAL UART functions */ +extern const uint16_t UARTPrescTable[12]; +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WBAxx_HAL_UART_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_uart_ex.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_uart_ex.h new file mode 100644 index 0000000000..22e3c41dcf --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_uart_ex.h @@ -0,0 +1,576 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_uart_ex.h + * @author MCD Application Team + * @brief Header file of UART HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_HAL_UART_EX_H +#define STM32WBAxx_HAL_UART_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal_def.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @addtogroup UARTEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup UARTEx_Exported_Types UARTEx Exported Types + * @{ + */ + +/** + * @brief UART wake up from stop mode parameters + */ +typedef struct +{ + uint32_t WakeUpEvent; /*!< Specifies which event will activate the Wakeup from Stop mode flag (WUF). + This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection. + If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must + be filled up. */ + + uint16_t AddressLength; /*!< Specifies whether the address is 4 or 7-bit long. + This parameter can be a value of @ref UARTEx_WakeUp_Address_Length. */ + + uint8_t Address; /*!< UART/USART node address (7-bit long max). */ +} UART_WakeUpTypeDef; + +/** + * @brief UART Autonomous mode parameters + */ +typedef struct +{ + uint32_t AutonomousModeState; /*!< Specifies the autonomous mode state.This parameter can be a value of + @ref UARTEx_Autonomous_mode.*/ + + uint32_t TriggerSelection; /*!< Specifies which trigger will activate the Transmission automatically. + This parameter can be a value of @ref UARTEx_Autonomous_Trigger_selection + or @ref LPUARTEx_Autonomous_Trigger_selection.*/ + + uint32_t TriggerPolarity; /*!< Specifies the autonomous mode trigger signal polarity. + This parameter can be a value of @ref UARTEx_Autonomous_Trigger_Polarity */ + + uint32_t DataSize; /*!< Specifies the transmitted data size in byte */ + + uint32_t IdleFrame; /*!< Specifies whether the IDLE frame transmission is enabled or disabled. + This parameter can be a value of @ref UARTEx_Autonomous_IDLE_FRAME. */ +} UART_AutonomousModeConfTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants + * @{ + */ + +/** @defgroup UARTEx_Word_Length UARTEx Word Length + * @{ + */ +#define UART_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long UART frame */ +#define UART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long UART frame */ +#define UART_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long UART frame */ +/** + * @} + */ + +/** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length + * @{ + */ +#define UART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit long wake-up address */ +#define UART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit long wake-up address */ +/** + * @} + */ + +/** @defgroup UARTEx_FIFO_mode UARTEx FIFO mode + * @brief UART FIFO mode + * @{ + */ +#define UART_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */ +#define UART_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */ +/** + * @} + */ + +/** @defgroup UARTEx_TXFIFO_threshold_level UARTEx TXFIFO threshold level + * @brief UART TXFIFO threshold level + * @{ + */ +#define UART_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TX FIFO reaches 1/8 of its depth */ +#define UART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0 /*!< TX FIFO reaches 1/4 of its depth */ +#define UART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1 /*!< TX FIFO reaches 1/2 of its depth */ +#define UART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TX FIFO reaches 3/4 of its depth */ +#define UART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2 /*!< TX FIFO reaches 7/8 of its depth */ +#define UART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TX FIFO becomes empty */ +/** + * @} + */ + +/** @defgroup UARTEx_RXFIFO_threshold_level UARTEx RXFIFO threshold level + * @brief UART RXFIFO threshold level + * @{ + */ +#define UART_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RX FIFO reaches 1/8 of its depth */ +#define UART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0 /*!< RX FIFO reaches 1/4 of its depth */ +#define UART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1 /*!< RX FIFO reaches 1/2 of its depth */ +#define UART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RX FIFO reaches 3/4 of its depth */ +#define UART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2 /*!< RX FIFO reaches 7/8 of its depth */ +#define UART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RX FIFO becomes full */ +/** + * @} + */ + +/** @defgroup UARTEx_Autonomous_mode UARTEx Autonomous Mode + * @brief UART Autonomous mode + * @{ + */ +#define UART_AUTONOMOUS_MODE_DISABLE 0x00000000U /*!< Autonomous mode disable */ +#define UART_AUTONOMOUS_MODE_ENABLE USART_AUTOCR_TRIGEN /*!< Autonomous mode enable */ +/** + * @} + */ + +/** @defgroup UARTEx_Autonomous_Trigger_Polarity UARTEx Autonomous Trigger Polarity + * @brief UART Trigger polarity edge selection + * @{ + */ +#define UART_TRIG_POLARITY_RISING 0x00000000U /*!< UART triggered on rising edge */ +#define UART_TRIG_POLARITY_FALLING USART_AUTOCR_TRIGPOL /*!< UART triggered on falling edge */ +/** + * @} + */ + +/** @defgroup UARTEx_Autonomous_IDLE_FRAME UARTEx Autonomous IDLE Frame + * @brief UART IDLE frame transmission + * @{ + */ +#define UART_IDLE_FRAME_ENABLE 0x00000000U /*!< IDLE Frame sent after enabling the transmitter */ +#define UART_IDLE_FRAME_DISABLE USART_AUTOCR_IDLEDIS /*!< IDLE Frame not sent after enabling the transmitter */ +/** + * @} + */ + +/** @defgroup UARTEx_Autonomous_Trigger_selection UARTEx Autonomous trigger selection + * @brief UART Autonomous Trigger selection + * @{ + */ +#define UART_GPDMA1_CH0_TCF_TRG 0U /*!< UART GPDMA1 channel0 Internal Trigger */ +#define UART_GPDMA1_CH1_TCF_TRG 1U /*!< UART GPDMA1 channel1 Internal Trigger */ +#define UART_GPDMA1_CH2_TCF_TRG 2U /*!< UART GPDMA1 channel2 Internal Trigger */ +#define UART_GPDMA1_CH3_TCF_TRG 3U /*!< UART GPDMA1 channel3 Internal Trigger */ +#define UART_EXTI_LINE6_TRG 4U /*!< UART EXTI line 6 Internal Trigger */ +#define UART_EXTI_LINE9_TRG 5U /*!< UART EXTI line 9 Internal Trigger */ +#define UART_LPTIM1_OUT_TRG 6U /*!< UART LPTIM1 out Internal Trigger */ +#if defined(LPTIM2) +#define UART_LPTIM2_OUT_TRG 7U /*!< UART LPTIM2 out Internal Trigger */ +#endif /* LPTIM2 */ +#if defined(COMP12_COMMON) +#define UART_COMP1_OUT_TRG 8U /*!< UART COMP1 out Internal Trigger */ +#define UART_COMP2_OUT_TRG 9U /*!< UART COMP2 out Internal Trigger */ +#endif /* COMP12_COMMON */ +#define UART_RTC_ALRA_TRG 10U /*!< UART RTC alarm Internal Trigger */ +#define UART_RTC_WUT_TRG 11U /*!< UART RTC wakeup Internal Trigger */ +/** + * @} + */ + +/** @defgroup LPUARTEx_Autonomous_Trigger_selection LPUARTEx Autonomous trigger selection + * @brief LPUART Autonomous Trigger selection + * @{ + */ +#define LPUART_GPDMA1_CH0_TCF_TRG 0U /*!< LPUART GPDMA1 channel0 Internal Trigger */ +#define LPUART_GPDMA1_CH1_TCF_TRG 1U /*!< LPUART GPDMA1 channel1 Internal Trigger */ +#define LPUART_GPDMA1_CH2_TCF_TRG 2U /*!< LPUART GPDMA1 channel2 Internal Trigger */ +#define LPUART_GPDMA1_CH3_TCF_TRG 3U /*!< LPUART GPDMA1 channel3 Internal Trigger */ +#define LPUART_EXTI_LINE6_TRG 4U /*!< LPUART EXTI line 6 Internal Trigger */ +#define LPUART_EXTI_LINE8_TRG 5U /*!< LPUART EXTI line 8 Internal Trigger */ +#define LPUART_LPTIM1_OUT_TRG 6U /*!< LPUART LPTIM1 channe11 Internal Trigger */ +#if defined(COMP12_COMMON) +#define LPUART_COMP1_OUT_TRG 8U /*!< LPUART COMP1 out Internal Trigger */ +#define LPUART_COMP2_OUT_TRG 9U /*!< LPUART COMP2 out Internal Trigger */ +#endif /* COMP12_COMMON */ +#define LPUART_RTC_ALRA_TRG 10U /*!< LPUART RTC alarm Internal Trigger */ +#define LPUART_RTC_WUT_TRG 11U /*!< LPUART RTC wakeup Internal Trigger */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup UARTEx_Exported_Functions + * @{ + */ + +/** @addtogroup UARTEx_Exported_Functions_Group1 + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ +HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, + uint32_t DeassertionTime); + +/** + * @} + */ + +/** @addtogroup UARTEx_Exported_Functions_Group2 + * @{ + */ + +void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart); + +void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart); +void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart); + +/** + * @} + */ + +/** @addtogroup UARTEx_Exported_Functions_Group3 + * @{ + */ + +/* Peripheral Control functions **********************************************/ +HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection); +HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart); + +HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength); + +HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold); +HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold); + +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, + uint32_t Timeout); +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +#if defined(HAL_DMA_MODULE_ENABLED) +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +#endif /* HAL_DMA_MODULE_ENABLED */ + +HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart); + +/* Autonomous Mode Control functions **********************************************/ +HAL_StatusTypeDef HAL_UARTEx_SetConfigAutonomousMode(UART_HandleTypeDef *huart, + const UART_AutonomousModeConfTypeDef *sConfig); +HAL_StatusTypeDef HAL_UARTEx_GetConfigAutonomousMode(const UART_HandleTypeDef *huart, + UART_AutonomousModeConfTypeDef *sConfig); +HAL_StatusTypeDef HAL_UARTEx_ClearConfigAutonomousMode(UART_HandleTypeDef *huart); + + +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup UARTEx_Private_Macros UARTEx Private Macros + * @{ + */ + +/** @brief Report the UART clock source. + * @param __HANDLE__ specifies the UART Handle. + * @param __CLOCKSOURCE__ output variable. + * @retval UART clocking source, written in __CLOCKSOURCE__. + */ +#if defined (USART2) +#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK2: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ + case RCC_USART2CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART2CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART2CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART2CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == LPUART1) \ + { \ + switch(__HAL_RCC_GET_LPUART1_SOURCE()) \ + { \ + case RCC_LPUART1CLKSOURCE_PCLK7: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK7; \ + break; \ + case RCC_LPUART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_LPUART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_LPUART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0U) +#else +#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK2: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == LPUART1) \ + { \ + switch(__HAL_RCC_GET_LPUART1_SOURCE()) \ + { \ + case RCC_LPUART1CLKSOURCE_PCLK7: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK7; \ + break; \ + case RCC_LPUART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_LPUART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_LPUART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0U) +#endif /* USART2 */ + +/** @brief Report the UART mask to apply to retrieve the received data + * according to the word length and to the parity bits activation. + * @note If PCE = 1, the parity bit is not included in the data extracted + * by the reception API(). + * This masking operation is not carried out in the case of + * DMA transfers. + * @param __HANDLE__ specifies the UART Handle. + * @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field. + */ +#define UART_MASK_COMPUTATION(__HANDLE__) \ + do { \ + if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \ + { \ + if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x01FFU ; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x00FFU ; \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \ + { \ + if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x00FFU ; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x007FU ; \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \ + { \ + if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x007FU ; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x003FU ; \ + } \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x0000U; \ + } \ + } while(0U) + +/** + * @brief Ensure that UART frame length is valid. + * @param __LENGTH__ UART frame length. + * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) + */ +#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \ + ((__LENGTH__) == UART_WORDLENGTH_8B) || \ + ((__LENGTH__) == UART_WORDLENGTH_9B)) + +/** + * @brief Ensure that UART wake-up address length is valid. + * @param __ADDRESS__ UART wake-up address length. + * @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid) + */ +#define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \ + ((__ADDRESS__) == UART_ADDRESS_DETECT_7B)) + +/** + * @brief Ensure that UART TXFIFO threshold level is valid. + * @param __THRESHOLD__ UART TXFIFO threshold level. + * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) + */ +#define IS_UART_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_8) || \ + ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_4) || \ + ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_2) || \ + ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_3_4) || \ + ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_7_8) || \ + ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_8_8)) + +/** + * @brief Ensure that UART RXFIFO threshold level is valid. + * @param __THRESHOLD__ UART RXFIFO threshold level. + * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) + */ +#define IS_UART_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_8) || \ + ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_4) || \ + ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_2) || \ + ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_3_4) || \ + ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_7_8) || \ + ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_8_8)) + +/** + * @brief Ensure that UART Trigger polarity state is valid. + * @param __POLARITY__ UART Trigger polarity. + * @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid) + */ +#define IS_UART_TRIGGER_POLARITY(__POLARITY__) (((__POLARITY__) == UART_TRIG_POLARITY_RISING) ||\ + ((__POLARITY__) == UART_TRIG_POLARITY_FALLING)) + +/** + * @brief Ensure that UART IDLE Frame Transmit state is valid. + * @param __IDLE__ UART IDLE Frame Transmit state. + * @retval SET (__IDLE__ is valid) or RESET (__IDLE__ is invalid) + */ +#define IS_UART_IDLE_FRAME_TRANSMIT(__IDLE__) (((__IDLE__) == UART_IDLE_FRAME_ENABLE) ||\ + ((__IDLE__) == UART_IDLE_FRAME_DISABLE)) + +/** + * @brief Ensure that UART Trigger source selection is valid. + * @param __SOURCE__ UART Trigger source selection. + * @retval SET (__SOURCE__ is valid) or RESET (__SOURCE__ is invalid) + */ +#define IS_UART_TRIGGER_SELECTION(__SOURCE__) ((__SOURCE__) <= 11U) + +/** + * @brief Ensure that LPUART Trigger source selection is valid. + * @param __SOURCE__ LPUART Trigger source selection. + * @retval SET (__SOURCE__ is valid) or RESET (__SOURCE__ is invalid) + */ +#define IS_LPUART_TRIGGER_SELECTION(__SOURCE__) ((__SOURCE__) <= 11U) + +/** + * @brief Ensure that the number of transferred data is valid. + * @param __SOURCE__ UART TX data size. + * @retval SET (__SOURCE__ is valid) or RESET (__SOURCE__ is invalid) + */ +#define IS_UART_TX_DATA_SIZE(__SOURCE__) ((__SOURCE__) <= 0xFFFFU) + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WBAxx_HAL_UART_EX_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_usart.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_usart.h new file mode 100644 index 0000000000..503a670531 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_usart.h @@ -0,0 +1,1000 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_usart.h + * @author MCD Application Team + * @brief Header file of USART HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_HAL_USART_H +#define STM32WBAxx_HAL_USART_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal_def.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @addtogroup USART + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup USART_Exported_Types USART Exported Types + * @{ + */ + +/** + * @brief USART Init Structure definition + */ +typedef struct +{ + uint32_t BaudRate; /*!< This member configures the Usart communication baud rate. + The baud rate is computed using the following formula: + Baud Rate Register[15:4] = ((2 * fclk_pres) / + ((huart->Init.BaudRate)))[15:4] + Baud Rate Register[3] = 0 + Baud Rate Register[2:0] = (((2 * fclk_pres) / + ((huart->Init.BaudRate)))[3:0]) >> 1 + where fclk_pres is the USART input clock frequency (fclk) + divided by a prescaler. + @note Oversampling by 8 is systematically applied to + achieve high baud rates. */ + + uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref USARTEx_Word_Length. */ + + uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref USART_Stop_Bits. */ + + uint32_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref USART_Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ + + uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref USART_Mode. */ + + uint32_t CLKPolarity; /*!< Specifies the steady state of the serial clock. + This parameter can be a value of @ref USART_Clock_Polarity. */ + + uint32_t CLKPhase; /*!< Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref USART_Clock_Phase. */ + + uint32_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted + data bit (MSB) has to be output on the SCLK pin in synchronous mode. + This parameter can be a value of @ref USART_Last_Bit. */ + + uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the USART clock source. + This parameter can be a value of @ref USART_ClockPrescaler. */ +} USART_InitTypeDef; + +/** + * @brief HAL USART State structures definition + */ +typedef enum +{ + HAL_USART_STATE_RESET = 0x00U, /*!< Peripheral is not initialized */ + HAL_USART_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_USART_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */ + HAL_USART_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */ + HAL_USART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ + HAL_USART_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission Reception process is ongoing */ + HAL_USART_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ + HAL_USART_STATE_ERROR = 0x04U /*!< Error */ +} HAL_USART_StateTypeDef; + +/** + * @brief USART clock sources definitions + */ +typedef enum +{ + USART_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */ + USART_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */ + USART_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */ + USART_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */ + USART_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */ + USART_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */ +} USART_ClockSourceTypeDef; + +/** + * @brief USART handle Structure definition + */ +typedef struct __USART_HandleTypeDef +{ + USART_TypeDef *Instance; /*!< USART registers base address */ + + USART_InitTypeDef Init; /*!< USART communication parameters */ + + const uint8_t *pTxBuffPtr; /*!< Pointer to USART Tx transfer Buffer */ + + uint16_t TxXferSize; /*!< USART Tx Transfer size */ + + __IO uint16_t TxXferCount; /*!< USART Tx Transfer Counter */ + + uint8_t *pRxBuffPtr; /*!< Pointer to USART Rx transfer Buffer */ + + uint16_t RxXferSize; /*!< USART Rx Transfer size */ + + __IO uint16_t RxXferCount; /*!< USART Rx Transfer Counter */ + + uint16_t Mask; /*!< USART Rx RDR register mask */ + + uint16_t NbRxDataToProcess; /*!< Number of data to process during RX ISR execution */ + + uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */ + + uint32_t SlaveMode; /*!< Enable/Disable UART SPI Slave Mode. This parameter can be a value + of @ref USARTEx_Slave_Mode */ + + uint32_t FifoMode; /*!< Specifies if the FIFO mode will be used. This parameter can be a value + of @ref USARTEx_FIFO_mode. */ + + void (*RxISR)(struct __USART_HandleTypeDef *husart); /*!< Function pointer on Rx IRQ handler */ + + void (*TxISR)(struct __USART_HandleTypeDef *husart); /*!< Function pointer on Tx IRQ handler */ + +#if defined(HAL_DMA_MODULE_ENABLED) + DMA_HandleTypeDef *hdmatx; /*!< USART Tx DMA Handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< USART Rx DMA Handle parameters */ + +#endif /* HAL_DMA_MODULE_ENABLED */ + HAL_LockTypeDef Lock; /*!< Locking object */ + + __IO HAL_USART_StateTypeDef State; /*!< USART communication state */ + + __IO uint32_t ErrorCode; /*!< USART Error code */ + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + void (* TxHalfCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Half Complete Callback */ + void (* TxCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Complete Callback */ + void (* RxHalfCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Rx Half Complete Callback */ + void (* RxCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Rx Complete Callback */ + void (* TxRxCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Rx Complete Callback */ + void (* ErrorCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Error Callback */ + void (* AbortCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Abort Complete Callback */ + void (* RxFifoFullCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Rx Fifo Full Callback */ + void (* TxFifoEmptyCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Fifo Empty Callback */ + + void (* MspInitCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Msp Init callback */ + void (* MspDeInitCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Msp DeInit callback */ +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + +} USART_HandleTypeDef; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) +/** + * @brief HAL USART Callback ID enumeration definition + */ +typedef enum +{ + HAL_USART_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< USART Tx Half Complete Callback ID */ + HAL_USART_TX_COMPLETE_CB_ID = 0x01U, /*!< USART Tx Complete Callback ID */ + HAL_USART_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< USART Rx Half Complete Callback ID */ + HAL_USART_RX_COMPLETE_CB_ID = 0x03U, /*!< USART Rx Complete Callback ID */ + HAL_USART_TX_RX_COMPLETE_CB_ID = 0x04U, /*!< USART Tx Rx Complete Callback ID */ + HAL_USART_ERROR_CB_ID = 0x05U, /*!< USART Error Callback ID */ + HAL_USART_ABORT_COMPLETE_CB_ID = 0x06U, /*!< USART Abort Complete Callback ID */ + HAL_USART_RX_FIFO_FULL_CB_ID = 0x07U, /*!< USART Rx Fifo Full Callback ID */ + HAL_USART_TX_FIFO_EMPTY_CB_ID = 0x08U, /*!< USART Tx Fifo Empty Callback ID */ + + HAL_USART_MSPINIT_CB_ID = 0x09U, /*!< USART MspInit callback ID */ + HAL_USART_MSPDEINIT_CB_ID = 0x0AU /*!< USART MspDeInit callback ID */ + +} HAL_USART_CallbackIDTypeDef; + +/** + * @brief HAL USART Callback pointer definition + */ +typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< pointer to an USART callback function */ + +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup USART_Exported_Constants USART Exported Constants + * @{ + */ + +/** @defgroup USART_Error_Definition USART Error Definition + * @{ + */ +#define HAL_USART_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_USART_ERROR_PE (0x00000001U) /*!< Parity error */ +#define HAL_USART_ERROR_NE (0x00000002U) /*!< Noise error */ +#define HAL_USART_ERROR_FE (0x00000004U) /*!< Frame error */ +#define HAL_USART_ERROR_ORE (0x00000008U) /*!< Overrun error */ +#if defined(HAL_DMA_MODULE_ENABLED) +#define HAL_USART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#endif /* HAL_DMA_MODULE_ENABLED */ +#define HAL_USART_ERROR_UDR (0x00000020U) /*!< SPI slave underrun error */ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) +#define HAL_USART_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */ +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ +#define HAL_USART_ERROR_RTO (0x00000080U) /*!< Receiver Timeout error */ +/** + * @} + */ + +/** @defgroup USART_Stop_Bits USART Number of Stop Bits + * @{ + */ +#define USART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< USART frame with 0.5 stop bit */ +#define USART_STOPBITS_1 0x00000000U /*!< USART frame with 1 stop bit */ +#define USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< USART frame with 1.5 stop bits */ +#define USART_STOPBITS_2 USART_CR2_STOP_1 /*!< USART frame with 2 stop bits */ +/** + * @} + */ + +/** @defgroup USART_Parity USART Parity + * @{ + */ +#define USART_PARITY_NONE 0x00000000U /*!< No parity */ +#define USART_PARITY_EVEN USART_CR1_PCE /*!< Even parity */ +#define USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Odd parity */ +/** + * @} + */ + +/** @defgroup USART_Mode USART Mode + * @{ + */ +#define USART_MODE_RX USART_CR1_RE /*!< RX mode */ +#define USART_MODE_TX USART_CR1_TE /*!< TX mode */ +#define USART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< RX and TX mode */ +/** + * @} + */ + +/** @defgroup USART_Clock USART Clock + * @{ + */ +#define USART_CLOCK_DISABLE 0x00000000U /*!< USART clock disable */ +#define USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< USART clock enable */ +/** + * @} + */ + +/** @defgroup USART_Clock_Polarity USART Clock Polarity + * @{ + */ +#define USART_POLARITY_LOW 0x00000000U /*!< Driver enable signal is active high */ +#define USART_POLARITY_HIGH USART_CR2_CPOL /*!< Driver enable signal is active low */ +/** + * @} + */ + +/** @defgroup USART_Clock_Phase USART Clock Phase + * @{ + */ +#define USART_PHASE_1EDGE 0x00000000U /*!< USART frame phase on first clock transition */ +#define USART_PHASE_2EDGE USART_CR2_CPHA /*!< USART frame phase on second clock transition */ +/** + * @} + */ + +/** @defgroup USART_Last_Bit USART Last Bit + * @{ + */ +#define USART_LASTBIT_DISABLE 0x00000000U /*!< USART frame last data bit clock pulse not output to SCLK pin */ +#define USART_LASTBIT_ENABLE USART_CR2_LBCL /*!< USART frame last data bit clock pulse output to SCLK pin */ +/** + * @} + */ + +/** @defgroup USART_ClockPrescaler USART Clock Prescaler + * @{ + */ +#define USART_PRESCALER_DIV1 0x00000000U /*!< fclk_pres = fclk */ +#define USART_PRESCALER_DIV2 0x00000001U /*!< fclk_pres = fclk/2 */ +#define USART_PRESCALER_DIV4 0x00000002U /*!< fclk_pres = fclk/4 */ +#define USART_PRESCALER_DIV6 0x00000003U /*!< fclk_pres = fclk/6 */ +#define USART_PRESCALER_DIV8 0x00000004U /*!< fclk_pres = fclk/8 */ +#define USART_PRESCALER_DIV10 0x00000005U /*!< fclk_pres = fclk/10 */ +#define USART_PRESCALER_DIV12 0x00000006U /*!< fclk_pres = fclk/12 */ +#define USART_PRESCALER_DIV16 0x00000007U /*!< fclk_pres = fclk/16 */ +#define USART_PRESCALER_DIV32 0x00000008U /*!< fclk_pres = fclk/32 */ +#define USART_PRESCALER_DIV64 0x00000009U /*!< fclk_pres = fclk/64 */ +#define USART_PRESCALER_DIV128 0x0000000AU /*!< fclk_pres = fclk/128 */ +#define USART_PRESCALER_DIV256 0x0000000BU /*!< fclk_pres = fclk/256 */ + +/** + * @} + */ + +/** @defgroup USART_Request_Parameters USART Request Parameters + * @{ + */ +#define USART_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ /*!< Receive Data flush Request */ +#define USART_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ /*!< Transmit data flush Request */ +/** + * @} + */ + +/** @defgroup USART_Flags USART Flags + * Elements values convention: 0xXXXX + * - 0xXXXX : Flag mask in the ISR register + * @{ + */ +#define USART_FLAG_TXFT USART_ISR_TXFT /*!< USART TXFIFO threshold flag */ +#define USART_FLAG_RXFT USART_ISR_RXFT /*!< USART RXFIFO threshold flag */ +#define USART_FLAG_RXFF USART_ISR_RXFF /*!< USART RXFIFO Full flag */ +#define USART_FLAG_TXFE USART_ISR_TXFE /*!< USART TXFIFO Empty flag */ +#define USART_FLAG_REACK USART_ISR_REACK /*!< USART receive enable acknowledge flag */ +#define USART_FLAG_TEACK USART_ISR_TEACK /*!< USART transmit enable acknowledge flag */ +#define USART_FLAG_BUSY USART_ISR_BUSY /*!< USART busy flag */ +#define USART_FLAG_UDR USART_ISR_UDR /*!< SPI slave underrun error flag */ +#define USART_FLAG_TXE USART_ISR_TXE_TXFNF /*!< USART transmit data register empty */ +#define USART_FLAG_TXFNF USART_ISR_TXE_TXFNF /*!< USART TXFIFO not full */ +#define USART_FLAG_RTOF USART_ISR_RTOF /*!< USART receiver timeout flag */ +#define USART_FLAG_TC USART_ISR_TC /*!< USART transmission complete */ +#define USART_FLAG_RXNE USART_ISR_RXNE_RXFNE /*!< USART read data register not empty */ +#define USART_FLAG_RXFNE USART_ISR_RXNE_RXFNE /*!< USART RXFIFO not empty */ +#define USART_FLAG_IDLE USART_ISR_IDLE /*!< USART idle flag */ +#define USART_FLAG_ORE USART_ISR_ORE /*!< USART overrun error */ +#define USART_FLAG_NE USART_ISR_NE /*!< USART noise error */ +#define USART_FLAG_FE USART_ISR_FE /*!< USART frame error */ +#define USART_FLAG_PE USART_ISR_PE /*!< USART parity error */ +/** + * @} + */ + +/** @defgroup USART_Interrupt_definition USART Interrupts Definition + * Elements values convention: 0000ZZZZ0XXYYYYYb + * - YYYYY : Interrupt source position in the XX register (5bits) + * - XX : Interrupt source register (2bits) + * - 01: CR1 register + * - 10: CR2 register + * - 11: CR3 register + * - ZZZZ : Flag position in the ISR register(4bits) + * @{ + */ + +#define USART_IT_PE 0x0028U /*!< USART parity error interruption */ +#define USART_IT_TXE 0x0727U /*!< USART transmit data register empty interruption */ +#define USART_IT_TXFNF 0x0727U /*!< USART TX FIFO not full interruption */ +#define USART_IT_TC 0x0626U /*!< USART transmission complete interruption */ +#define USART_IT_RXNE 0x0525U /*!< USART read data register not empty interruption */ +#define USART_IT_RXFNE 0x0525U /*!< USART RXFIFO not empty interruption */ +#define USART_IT_IDLE 0x0424U /*!< USART idle interruption */ +#define USART_IT_ERR 0x0060U /*!< USART error interruption */ +#define USART_IT_ORE 0x0300U /*!< USART overrun error interruption */ +#define USART_IT_NE 0x0200U /*!< USART noise error interruption */ +#define USART_IT_FE 0x0100U /*!< USART frame error interruption */ +#define USART_IT_RXFF 0x183FU /*!< USART RXFIFO full interruption */ +#define USART_IT_TXFE 0x173EU /*!< USART TXFIFO empty interruption */ +#define USART_IT_RXFT 0x1A7CU /*!< USART RXFIFO threshold reached interruption */ +#define USART_IT_TXFT 0x1B77U /*!< USART TXFIFO threshold reached interruption */ + +/** + * @} + */ + +/** @defgroup USART_IT_CLEAR_Flags USART Interruption Clear Flags + * @{ + */ +#define USART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */ +#define USART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */ +#define USART_CLEAR_NEF USART_ICR_NECF /*!< Noise Error detected Clear Flag */ +#define USART_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */ +#define USART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */ +#define USART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */ +#define USART_CLEAR_UDRF USART_ICR_UDRCF /*!< SPI slave underrun error Clear Flag */ +#define USART_CLEAR_TXFECF USART_ICR_TXFECF /*!< TXFIFO Empty Clear Flag */ +#define USART_CLEAR_RTOF USART_ICR_RTOCF /*!< USART receiver timeout clear flag */ +/** + * @} + */ + +/** @defgroup USART_Interruption_Mask USART Interruption Flags Mask + * @{ + */ +#define USART_IT_MASK 0x001FU /*!< USART interruptions flags mask */ +#define USART_CR_MASK 0x00E0U /*!< USART control register mask */ +#define USART_CR_POS 5U /*!< USART control register position */ +#define USART_ISR_MASK 0x1F00U /*!< USART ISR register mask */ +#define USART_ISR_POS 8U /*!< USART ISR register position */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup USART_Exported_Macros USART Exported Macros + * @{ + */ + +/** @brief Reset USART handle state. + * @param __HANDLE__ USART handle. + * @retval None + */ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) +#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_USART_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0U) +#else +#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET) +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + +/** @brief Check whether the specified USART flag is set or not. + * @param __HANDLE__ specifies the USART Handle + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref USART_FLAG_TXFT TXFIFO threshold flag + * @arg @ref USART_FLAG_RXFT RXFIFO threshold flag + * @arg @ref USART_FLAG_RXFF RXFIFO Full flag + * @arg @ref USART_FLAG_TXFE TXFIFO Empty flag + * @arg @ref USART_FLAG_REACK Receive enable acknowledge flag + * @arg @ref USART_FLAG_TEACK Transmit enable acknowledge flag + * @arg @ref USART_FLAG_BUSY Busy flag + * @arg @ref USART_FLAG_UDR SPI slave underrun error flag + * @arg @ref USART_FLAG_TXE Transmit data register empty flag + * @arg @ref USART_FLAG_TXFNF TXFIFO not full flag + * @arg @ref USART_FLAG_TC Transmission Complete flag + * @arg @ref USART_FLAG_RXNE Receive data register not empty flag + * @arg @ref USART_FLAG_RXFNE RXFIFO not empty flag + * @arg @ref USART_FLAG_RTOF Receiver Timeout flag + * @arg @ref USART_FLAG_IDLE Idle Line detection flag + * @arg @ref USART_FLAG_ORE OverRun Error flag + * @arg @ref USART_FLAG_NE Noise Error flag + * @arg @ref USART_FLAG_FE Framing Error flag + * @arg @ref USART_FLAG_PE Parity Error flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) + +/** @brief Clear the specified USART pending flag. + * @param __HANDLE__ specifies the USART Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be any combination of the following values: + * @arg @ref USART_CLEAR_PEF Parity Error Clear Flag + * @arg @ref USART_CLEAR_FEF Framing Error Clear Flag + * @arg @ref USART_CLEAR_NEF Noise detected Clear Flag + * @arg @ref USART_CLEAR_OREF Overrun Error Clear Flag + * @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag + * @arg @ref USART_CLEAR_TXFECF TXFIFO empty clear Flag + * @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag + * @arg @ref USART_CLEAR_RTOF Receiver Timeout clear flag + * @arg @ref USART_CLEAR_UDRF SPI slave underrun error Clear Flag + * @retval None + */ +#define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) + +/** @brief Clear the USART PE pending flag. + * @param __HANDLE__ specifies the USART Handle. + * @retval None + */ +#define __HAL_USART_CLEAR_PEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_PEF) + +/** @brief Clear the USART FE pending flag. + * @param __HANDLE__ specifies the USART Handle. + * @retval None + */ +#define __HAL_USART_CLEAR_FEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_FEF) + +/** @brief Clear the USART NE pending flag. + * @param __HANDLE__ specifies the USART Handle. + * @retval None + */ +#define __HAL_USART_CLEAR_NEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_NEF) + +/** @brief Clear the USART ORE pending flag. + * @param __HANDLE__ specifies the USART Handle. + * @retval None + */ +#define __HAL_USART_CLEAR_OREFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_OREF) + +/** @brief Clear the USART IDLE pending flag. + * @param __HANDLE__ specifies the USART Handle. + * @retval None + */ +#define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_IDLEF) + +/** @brief Clear the USART TX FIFO empty clear flag. + * @param __HANDLE__ specifies the USART Handle. + * @retval None + */ +#define __HAL_USART_CLEAR_TXFECF(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_TXFECF) + +/** @brief Clear SPI slave underrun error flag. + * @param __HANDLE__ specifies the USART Handle. + * @retval None + */ +#define __HAL_USART_CLEAR_UDRFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_UDRF) + +/** @brief Enable the specified USART interrupt. + * @param __HANDLE__ specifies the USART Handle. + * @param __INTERRUPT__ specifies the USART interrupt source to enable. + * This parameter can be one of the following values: + * @arg @ref USART_IT_RXFF RXFIFO Full interrupt + * @arg @ref USART_IT_TXFE TXFIFO Empty interrupt + * @arg @ref USART_IT_RXFT RXFIFO threshold interrupt + * @arg @ref USART_IT_TXFT TXFIFO threshold interrupt + * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref USART_IT_TXFNF TX FIFO not full interrupt + * @arg @ref USART_IT_TC Transmission complete interrupt + * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref USART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref USART_IT_IDLE Idle line detection interrupt + * @arg @ref USART_IT_PE Parity Error interrupt + * @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error) + * @retval None + */ +#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)\ + (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\ + ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\ + ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK)))) + +/** @brief Disable the specified USART interrupt. + * @param __HANDLE__ specifies the USART Handle. + * @param __INTERRUPT__ specifies the USART interrupt source to disable. + * This parameter can be one of the following values: + * @arg @ref USART_IT_RXFF RXFIFO Full interrupt + * @arg @ref USART_IT_TXFE TXFIFO Empty interrupt + * @arg @ref USART_IT_RXFT RXFIFO threshold interrupt + * @arg @ref USART_IT_TXFT TXFIFO threshold interrupt + * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref USART_IT_TXFNF TX FIFO not full interrupt + * @arg @ref USART_IT_TC Transmission complete interrupt + * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref USART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref USART_IT_IDLE Idle line detection interrupt + * @arg @ref USART_IT_PE Parity Error interrupt + * @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error) + * @retval None + */ +#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)\ + (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\ + ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\ + ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK)))) + +/** @brief Check whether the specified USART interrupt has occurred or not. + * @param __HANDLE__ specifies the USART Handle. + * @param __INTERRUPT__ specifies the USART interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref USART_IT_RXFF RXFIFO Full interrupt + * @arg @ref USART_IT_TXFE TXFIFO Empty interrupt + * @arg @ref USART_IT_RXFT RXFIFO threshold interrupt + * @arg @ref USART_IT_TXFT TXFIFO threshold interrupt + * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref USART_IT_TXFNF TX FIFO not full interrupt + * @arg @ref USART_IT_TC Transmission complete interrupt + * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref USART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref USART_IT_IDLE Idle line detection interrupt + * @arg @ref USART_IT_ORE OverRun Error interrupt + * @arg @ref USART_IT_NE Noise Error interrupt + * @arg @ref USART_IT_FE Framing Error interrupt + * @arg @ref USART_IT_PE Parity Error interrupt + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_USART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\ + & (0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>>\ + USART_ISR_POS))) != 0U) ? SET : RESET) + +/** @brief Check whether the specified USART interrupt source is enabled or not. + * @param __HANDLE__ specifies the USART Handle. + * @param __INTERRUPT__ specifies the USART interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref USART_IT_RXFF RXFIFO Full interrupt + * @arg @ref USART_IT_TXFE TXFIFO Empty interrupt + * @arg @ref USART_IT_RXFT RXFIFO threshold interrupt + * @arg @ref USART_IT_TXFT TXFIFO threshold interrupt + * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref USART_IT_TXFNF TX FIFO not full interrupt + * @arg @ref USART_IT_TC Transmission complete interrupt + * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref USART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref USART_IT_IDLE Idle line detection interrupt + * @arg @ref USART_IT_ORE OverRun Error interrupt + * @arg @ref USART_IT_NE Noise Error interrupt + * @arg @ref USART_IT_FE Framing Error interrupt + * @arg @ref USART_IT_PE Parity Error interrupt + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U) ?\ + (__HANDLE__)->Instance->CR1 : \ + (((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U) ?\ + (__HANDLE__)->Instance->CR2 : \ + (__HANDLE__)->Instance->CR3)) & (0x01U <<\ + (((uint16_t)(__INTERRUPT__)) &\ + USART_IT_MASK))) != 0U) ? SET : RESET) + +/** @brief Clear the specified USART ISR flag, in setting the proper ICR register flag. + * @param __HANDLE__ specifies the USART Handle. + * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set + * to clear the corresponding interrupt. + * This parameter can be one of the following values: + * @arg @ref USART_CLEAR_PEF Parity Error Clear Flag + * @arg @ref USART_CLEAR_FEF Framing Error Clear Flag + * @arg @ref USART_CLEAR_NEF Noise detected Clear Flag + * @arg @ref USART_CLEAR_OREF Overrun Error Clear Flag + * @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag + * @arg @ref USART_CLEAR_RTOF Receiver timeout clear flag + * @arg @ref USART_CLEAR_TXFECF TXFIFO empty clear Flag + * @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag + * @retval None + */ +#define __HAL_USART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__)) + +/** @brief Set a specific USART request flag. + * @param __HANDLE__ specifies the USART Handle. + * @param __REQ__ specifies the request flag to set. + * This parameter can be one of the following values: + * @arg @ref USART_RXDATA_FLUSH_REQUEST Receive Data flush Request + * @arg @ref USART_TXDATA_FLUSH_REQUEST Transmit data flush Request + * + * @retval None + */ +#define __HAL_USART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) + +/** @brief Enable the USART one bit sample method. + * @param __HANDLE__ specifies the USART Handle. + * @retval None + */ +#define __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) + +/** @brief Disable the USART one bit sample method. + * @param __HANDLE__ specifies the USART Handle. + * @retval None + */ +#define __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT) + +/** @brief Enable USART. + * @param __HANDLE__ specifies the USART Handle. + * @retval None + */ +#define __HAL_USART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) + +/** @brief Disable USART. + * @param __HANDLE__ specifies the USART Handle. + * @retval None + */ +#define __HAL_USART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) + +/** + * @} + */ + +/* Private macros --------------------------------------------------------*/ +/** @defgroup USART_Private_Macros USART Private Macros + * @{ + */ + +/** @brief Get USART clock division factor from clock prescaler value. + * @param __CLOCKPRESCALER__ USART prescaler value. + * @retval USART clock division factor + */ +#define USART_GET_DIV_FACTOR(__CLOCKPRESCALER__) \ + (((__CLOCKPRESCALER__) == USART_PRESCALER_DIV1) ? 1U : \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV2) ? 2U : \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV4) ? 4U : \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV6) ? 6U : \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV8) ? 8U : \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV10) ? 10U : \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV12) ? 12U : \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV16) ? 16U : \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV32) ? 32U : \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV64) ? 64U : \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) ? 128U : \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV256) ? 256U : 1U) + +/** @brief BRR division operation to set BRR register in 8-bit oversampling mode. + * @param __PCLK__ USART clock. + * @param __BAUD__ Baud rate set by the user. + * @param __CLOCKPRESCALER__ USART prescaler value. + * @retval Division result + */ +#define USART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__)\ + (((((__PCLK__)/USART_GET_DIV_FACTOR(__CLOCKPRESCALER__))*2U)\ + + ((__BAUD__)/2U)) / (__BAUD__)) + +/** @brief Report the USART clock source. + * @param __HANDLE__ specifies the USART Handle. + * @param __CLOCKSOURCE__ output variable. + * @retval the USART clocking source, written in __CLOCKSOURCE__. + */ +#if defined(USART2) +#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK2: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK2; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ + case RCC_USART2CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART2CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART2CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART2CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0U) +#else +#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK2: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK2; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0U) +#endif /* USART2 */ + +/** @brief Check USART Baud rate. + * @param __BAUDRATE__ Baudrate specified by the user. + * The maximum Baud Rate is derived from the maximum clock on WBA (i.e. 100 MHz) + * divided by the smallest oversampling used on the USART (i.e. 8) + * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid) */ +#define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 12500000U) + +/** + * @brief Ensure that USART frame number of stop bits is valid. + * @param __STOPBITS__ USART frame number of stop bits. + * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) + */ +#define IS_USART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == USART_STOPBITS_0_5) || \ + ((__STOPBITS__) == USART_STOPBITS_1) || \ + ((__STOPBITS__) == USART_STOPBITS_1_5) || \ + ((__STOPBITS__) == USART_STOPBITS_2)) + +/** + * @brief Ensure that USART frame parity is valid. + * @param __PARITY__ USART frame parity. + * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid) + */ +#define IS_USART_PARITY(__PARITY__) (((__PARITY__) == USART_PARITY_NONE) || \ + ((__PARITY__) == USART_PARITY_EVEN) || \ + ((__PARITY__) == USART_PARITY_ODD)) + +/** + * @brief Ensure that USART communication mode is valid. + * @param __MODE__ USART communication mode. + * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) + */ +#define IS_USART_MODE(__MODE__) ((((__MODE__) & 0xFFFFFFF3U) == 0x00U) && ((__MODE__) != 0x00U)) + +/** + * @brief Ensure that USART clock state is valid. + * @param __CLOCK__ USART clock state. + * @retval SET (__CLOCK__ is valid) or RESET (__CLOCK__ is invalid) + */ +#define IS_USART_CLOCK(__CLOCK__) (((__CLOCK__) == USART_CLOCK_DISABLE) || \ + ((__CLOCK__) == USART_CLOCK_ENABLE)) + +/** + * @brief Ensure that USART frame polarity is valid. + * @param __CPOL__ USART frame polarity. + * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid) + */ +#define IS_USART_POLARITY(__CPOL__) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH)) + +/** + * @brief Ensure that USART frame phase is valid. + * @param __CPHA__ USART frame phase. + * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid) + */ +#define IS_USART_PHASE(__CPHA__) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE)) + +/** + * @brief Ensure that USART frame last bit clock pulse setting is valid. + * @param __LASTBIT__ USART frame last bit clock pulse setting. + * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid) + */ +#define IS_USART_LASTBIT(__LASTBIT__) (((__LASTBIT__) == USART_LASTBIT_DISABLE) || \ + ((__LASTBIT__) == USART_LASTBIT_ENABLE)) + +/** + * @brief Ensure that USART request parameter is valid. + * @param __PARAM__ USART request parameter. + * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid) + */ +#define IS_USART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == USART_RXDATA_FLUSH_REQUEST) || \ + ((__PARAM__) == USART_TXDATA_FLUSH_REQUEST)) + +/** + * @brief Ensure that USART Prescaler is valid. + * @param __CLOCKPRESCALER__ USART Prescaler value. + * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid) + */ +#define IS_USART_PRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == USART_PRESCALER_DIV1) || \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV2) || \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV4) || \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV6) || \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV8) || \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV10) || \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV12) || \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV16) || \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV32) || \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV64) || \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) || \ + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV256)) + +/** + * @} + */ + +/* Include USART HAL Extended module */ +#include "stm32wbaxx_hal_usart_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup USART_Exported_Functions USART Exported Functions + * @{ + */ + +/** @addtogroup USART_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ +HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart); +HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart); +void HAL_USART_MspInit(USART_HandleTypeDef *husart); +void HAL_USART_MspDeInit(USART_HandleTypeDef *husart); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, + pUSART_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @addtogroup USART_Exported_Functions_Group2 IO operation functions + * @{ + */ + +/* IO operation functions *****************************************************/ +HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size, + uint32_t Timeout); +HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size); +HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size); +HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size); +#if defined(HAL_DMA_MODULE_ENABLED) +HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size); +HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size); +HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size); +HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart); +HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart); +HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart); +#endif /* HAL_DMA_MODULE_ENABLED */ +/* Transfer Abort functions */ +HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart); +HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart); + +void HAL_USART_IRQHandler(USART_HandleTypeDef *husart); +void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart); +void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart); +void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart); +void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart); +void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart); +void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart); +void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart); + +/** + * @} + */ + +/** @addtogroup USART_Exported_Functions_Group4 Peripheral State and Error functions + * @{ + */ + +/* Peripheral State and Error functions ***************************************/ +HAL_USART_StateTypeDef HAL_USART_GetState(const USART_HandleTypeDef *husart); +uint32_t HAL_USART_GetError(const USART_HandleTypeDef *husart); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WBAxx_HAL_USART_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_usart_ex.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_usart_ex.h new file mode 100644 index 0000000000..3de2a21421 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_usart_ex.h @@ -0,0 +1,397 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_usart_ex.h + * @author MCD Application Team + * @brief Header file of USART HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_HAL_USART_EX_H +#define STM32WBAxx_HAL_USART_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal_def.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @addtogroup USARTEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup USARTEx_Exported_Types USARTEx Exported Types + * @{ + */ +/** + * @brief USART Autonomous mode parameters + */ +typedef struct +{ + uint32_t AutonomousModeState; /*!< Specifies the autonomous mode state.This parameter can be a value of + @ref USARTEx_Autonomous_mode.*/ + + uint32_t TriggerSelection; /*!< Specifies which trigger will activate the Transmission automatically. + This parameter can be a value of @ref USARTEx_Autonomous_Trigger_selection */ + + uint32_t TriggerPolarity; /*!< Specifies the autonomous mode trigger signal polarity. + This parameter can be a value of @ref USARTEx_Autonomous_Trigger_Polarity */ + + uint32_t DataSize; /*!< Specifies the transmitted data size in byte */ + + uint32_t IdleFrame; /*!< Specifies whether the IDLE frame transmission is enabled or disabled. + This parameter can be a value of @ref USARTEx_Autonomous_IDLE_FRAME. */ + +} USART_AutonomousModeConfTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup USARTEx_Exported_Constants USARTEx Exported Constants + * @{ + */ + +/** @defgroup USARTEx_Word_Length USARTEx Word Length + * @{ + */ +#define USART_WORDLENGTH_7B (USART_CR1_M1) /*!< 7-bit long USART frame */ +#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */ +#define USART_WORDLENGTH_9B (USART_CR1_M0) /*!< 9-bit long USART frame */ +/** + * @} + */ + +/** @defgroup USARTEx_Slave_Select_management USARTEx Slave Select Management + * @{ + */ +#define USART_NSS_HARD 0x00000000U /*!< SPI slave selection depends on NSS input pin */ +#define USART_NSS_SOFT USART_CR2_DIS_NSS /*!< SPI slave is always selected and NSS input pin is ignored */ +/** + * @} + */ + + +/** @defgroup USARTEx_Slave_Mode USARTEx Synchronous Slave mode enable + * @brief USART SLAVE mode + * @{ + */ +#define USART_SLAVEMODE_DISABLE 0x00000000U /*!< USART SPI Slave Mode Enable */ +#define USART_SLAVEMODE_ENABLE USART_CR2_SLVEN /*!< USART SPI Slave Mode Disable */ +/** + * @} + */ + +/** @defgroup USARTEx_FIFO_mode USARTEx FIFO mode + * @brief USART FIFO mode + * @{ + */ +#define USART_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */ +#define USART_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */ +/** + * @} + */ + +/** @defgroup USARTEx_TXFIFO_threshold_level USARTEx TXFIFO threshold level + * @brief USART TXFIFO level + * @{ + */ +#define USART_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TXFIFO reaches 1/8 of its depth */ +#define USART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0 /*!< TXFIFO reaches 1/4 of its depth */ +#define USART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1 /*!< TXFIFO reaches 1/2 of its depth */ +#define USART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TXFIFO reaches 3/4 of its depth */ +#define USART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2 /*!< TXFIFO reaches 7/8 of its depth */ +#define USART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TXFIFO becomes empty */ +/** + * @} + */ + +/** @defgroup USARTEx_RXFIFO_threshold_level USARTEx RXFIFO threshold level + * @brief USART RXFIFO level + * @{ + */ +#define USART_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RXFIFO FIFO reaches 1/8 of its depth */ +#define USART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0 /*!< RXFIFO FIFO reaches 1/4 of its depth */ +#define USART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1 /*!< RXFIFO FIFO reaches 1/2 of its depth */ +#define USART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RXFIFO FIFO reaches 3/4 of its depth */ +#define USART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2 /*!< RXFIFO FIFO reaches 7/8 of its depth */ +#define USART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RXFIFO FIFO becomes full */ +/** + * @} + */ + +/** @defgroup USARTEx_Autonomous_mode USARTEx Autonomous Mode + * @brief USART Autonomous mode + * @{ + */ +#define USART_AUTONOMOUS_MODE_DISABLE 0x00000000U /*!< Autonomous mode disable */ +#define USART_AUTONOMOUS_MODE_ENABLE USART_AUTOCR_TRIGEN /*!< Autonomous mode enable */ +/** + * @} + */ + +/** @defgroup USARTEx_Autonomous_Trigger_Polarity USARTEx Autonomous Trigger Polarity + * @brief USART Trigger polarity edge selection + * @{ + */ +#define USART_TRIG_POLARITY_RISING 0x00000000U /*!< USART triggered on rising edge */ +#define USART_TRIG_POLARITY_FALLING USART_AUTOCR_TRIGPOL /*!< USART triggered on falling edge */ +/** + * @} + */ + +/** @defgroup USARTEx_Autonomous_IDLE_FRAME USARTEx Autonomous IDLE Frame + * @brief USART IDLE frame transmission + * @{ + */ +#define USART_IDLE_FRAME_ENABLE 0x00000000U /*!< IDLE Frame sent after enabling the transmitter */ +#define USART_IDLE_FRAME_DISABLE USART_AUTOCR_IDLEDIS /*!< IDLE Frame not sent after enabling the transmitter */ +/** + * @} + */ + +/** @defgroup USARTEx_Autonomous_Trigger_selection USARTEx Autonomous trigger selection + * @brief USART Autonomous Trigger selection + * @{ + */ +#define USART_GPDMA1_CH0_TCF_TRG 0U /*!< USART GPDMA1 channel0 Internal Trigger */ +#define USART_GPDMA1_CH1_TCF_TRG 1U /*!< USART GPDMA1 channel1 Internal Trigger */ +#define USART_GPDMA1_CH2_TCF_TRG 2U /*!< USART GPDMA1 channel2 Internal Trigger */ +#define USART_GPDMA1_CH3_TCF_TRG 3U /*!< USART GPDMA1 channel3 Internal Trigger */ +#define USART_EXTI_LINE6_TRG 4U /*!< USART EXTI line 6 Internal Trigger */ +#define USART_EXTI_LINE9_TRG 5U /*!< USART EXTI line 9 Internal Trigger */ +#define USART_LPTIM1_OUT_TRG 6U /*!< USART LPTIM1 out Internal Trigger */ +#if defined(LPTIM2) +#define USART_LPTIM2_OUT_TRG 7U /*!< USART LPTIM2 out Internal Trigger */ +#endif /* LPTIM2 */ +#if defined(COMP12_COMMON) +#define USART_COMP1_OUT_TRG 8U /*!< USART COMP1 out Internal Trigger */ +#define USART_COMP2_OUT_TRG 9U /*!< USART COMP2 out Internal Trigger */ +#endif /* COMP12_COMMON */ +#define USART_RTC_ALRA_TRG 10U /*!< USART RTC alarm Internal Trigger */ +#define USART_RTC_WUT_TRG 11U /*!< USART RTC wakeup Internal Trigger */ +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup USARTEx_Private_Macros USARTEx Private Macros + * @{ + */ + +/** @brief Compute the USART mask to apply to retrieve the received data + * according to the word length and to the parity bits activation. + * @note If PCE = 1, the parity bit is not included in the data extracted + * by the reception API(). + * This masking operation is not carried out in the case of + * DMA transfers. + * @param __HANDLE__ specifies the USART Handle. + * @retval None, the mask to apply to USART RDR register is stored in (__HANDLE__)->Mask field. + */ +#define USART_MASK_COMPUTATION(__HANDLE__) \ + do { \ + if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B) \ + { \ + if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x01FFU; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x00FFU; \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B) \ + { \ + if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x00FFU; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x007FU; \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_7B) \ + { \ + if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x007FU; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x003FU; \ + } \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x0000U; \ + } \ + } while(0U) + +/** + * @brief Ensure that USART frame length is valid. + * @param __LENGTH__ USART frame length. + * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) + */ +#define IS_USART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == USART_WORDLENGTH_7B) || \ + ((__LENGTH__) == USART_WORDLENGTH_8B) || \ + ((__LENGTH__) == USART_WORDLENGTH_9B)) + +/** + * @brief Ensure that USART Negative Slave Select (NSS) pin management is valid. + * @param __NSS__ USART Negative Slave Select pin management. + * @retval SET (__NSS__ is valid) or RESET (__NSS__ is invalid) + */ +#define IS_USART_NSS(__NSS__) (((__NSS__) == USART_NSS_HARD) || \ + ((__NSS__) == USART_NSS_SOFT)) + +/** + * @brief Ensure that USART Slave Mode is valid. + * @param __STATE__ USART Slave Mode. + * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid) + */ +#define IS_USART_SLAVEMODE(__STATE__) (((__STATE__) == USART_SLAVEMODE_DISABLE ) || \ + ((__STATE__) == USART_SLAVEMODE_ENABLE)) + +/** + * @brief Ensure that USART FIFO mode is valid. + * @param __STATE__ USART FIFO mode. + * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid) + */ +#define IS_USART_FIFO_MODE_STATE(__STATE__) (((__STATE__) == USART_FIFOMODE_DISABLE ) || \ + ((__STATE__) == USART_FIFOMODE_ENABLE)) + +/** + * @brief Ensure that USART TXFIFO threshold level is valid. + * @param __THRESHOLD__ USART TXFIFO threshold level. + * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) + */ +#define IS_USART_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_8) || \ + ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_4) || \ + ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_2) || \ + ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_3_4) || \ + ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_7_8) || \ + ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_8_8)) + +/** + * @brief Ensure that USART RXFIFO threshold level is valid. + * @param __THRESHOLD__ USART RXFIFO threshold level. + * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) + */ +#define IS_USART_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_8) || \ + ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_4) || \ + ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_2) || \ + ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_3_4) || \ + ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_7_8) || \ + ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_8_8)) +/** + * @brief Ensure that USART Trigger polarity state is valid. + * @param __POLARITY__ USART Trigger polarity. + * @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid) + */ +#define IS_USART_TRIGGER_POLARITY(__POLARITY__) (((__POLARITY__) == USART_TRIG_POLARITY_RISING) ||\ + ((__POLARITY__) == USART_TRIG_POLARITY_FALLING)) + +/** + * @brief Ensure that USART IDLE Frame Transmit state is valid. + * @param __IDLE__ USART IDLE Frame Transmit state. + * @retval SET (__IDLE__ is valid) or RESET (__IDLE__ is invalid) + */ +#define IS_USART_IDLE_FRAME_TRANSMIT(__IDLE__) (((__IDLE__) == USART_IDLE_FRAME_ENABLE) ||\ + ((__IDLE__) == USART_IDLE_FRAME_DISABLE)) + +/** + * @brief Ensure that USART Trigger source selection is valid. + * @param __SOURCE__ USART Trigger source selection. + * @retval SET (__SOURCE__ is valid) or RESET (__SOURCE__ is invalid) + */ +#define IS_USART_TRIGGER_SELECTION(__SOURCE__) ((__SOURCE__) <= 11U) + +/** + * @brief Ensure that the number of transferred data is valid. + * @param __SOURCE__ USART TX data size. + * @retval SET (__SOURCE__ is valid) or RESET (__SOURCE__ is invalid) + */ +#define IS_USART_TX_DATA_SIZE(__SOURCE__) ((__SOURCE__) <= 0xFFFFU) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup USARTEx_Exported_Functions + * @{ + */ + +/** @addtogroup USARTEx_Exported_Functions_Group1 + * @{ + */ + +/* IO operation functions *****************************************************/ +void HAL_USARTEx_RxFifoFullCallback(USART_HandleTypeDef *husart); +void HAL_USARTEx_TxFifoEmptyCallback(USART_HandleTypeDef *husart); + +/** + * @} + */ + +/** @addtogroup USARTEx_Exported_Functions_Group2 + * @{ + */ + +/* Peripheral Control functions ***********************************************/ +HAL_StatusTypeDef HAL_USARTEx_EnableSlaveMode(USART_HandleTypeDef *husart); +HAL_StatusTypeDef HAL_USARTEx_DisableSlaveMode(USART_HandleTypeDef *husart); +HAL_StatusTypeDef HAL_USARTEx_ConfigNSS(USART_HandleTypeDef *husart, uint32_t NSSConfig); +HAL_StatusTypeDef HAL_USARTEx_EnableFifoMode(USART_HandleTypeDef *husart); +HAL_StatusTypeDef HAL_USARTEx_DisableFifoMode(USART_HandleTypeDef *husart); +HAL_StatusTypeDef HAL_USARTEx_SetTxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold); +HAL_StatusTypeDef HAL_USARTEx_SetRxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold); +HAL_StatusTypeDef HAL_USARTEx_SetConfigAutonomousMode(USART_HandleTypeDef *husart, + const USART_AutonomousModeConfTypeDef *sConfig); +HAL_StatusTypeDef HAL_USARTEx_GetConfigAutonomousMode(const USART_HandleTypeDef *husart, + USART_AutonomousModeConfTypeDef *sConfig); +HAL_StatusTypeDef HAL_USARTEx_ClearConfigAutonomousMode(USART_HandleTypeDef *husart); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WBAxx_HAL_USART_EX_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_wwdg.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_wwdg.h new file mode 100644 index 0000000000..8228dce599 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_hal_wwdg.h @@ -0,0 +1,306 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_wwdg.h + * @author MCD Application Team + * @brief Header file of WWDG HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_HAL_WWDG_H +#define STM32WBAxx_HAL_WWDG_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal_def.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @addtogroup WWDG + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup WWDG_Exported_Types WWDG Exported Types + * @{ + */ + +/** + * @brief WWDG Init structure definition + */ +typedef struct +{ + uint32_t Prescaler; /*!< Specifies the prescaler value of the WWDG. + This parameter can be a value of @ref WWDG_Prescaler */ + + uint32_t Window; /*!< Specifies the WWDG window value to be compared to the downcounter. + This parameter must be a number Min_Data = 0x40 and Max_Data = 0x7F */ + + uint32_t Counter; /*!< Specifies the WWDG free-running downcounter value. + This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */ + + uint32_t EWIMode ; /*!< Specifies if WWDG Early Wakeup Interrupt is enable or not. + This parameter can be a value of @ref WWDG_EWI_Mode */ + +} WWDG_InitTypeDef; + +/** + * @brief WWDG handle Structure definition + */ +#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1) +typedef struct __WWDG_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */ +{ + WWDG_TypeDef *Instance; /*!< Register base address */ + + WWDG_InitTypeDef Init; /*!< WWDG required parameters */ + +#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1) + void (* EwiCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Early WakeUp Interrupt callback */ + + void (* MspInitCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Msp Init callback */ +#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */ +} WWDG_HandleTypeDef; + +#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1) +/** + * @brief HAL WWDG common Callback ID enumeration definition + */ +typedef enum +{ + HAL_WWDG_EWI_CB_ID = 0x00U, /*!< WWDG EWI callback ID */ + HAL_WWDG_MSPINIT_CB_ID = 0x01U, /*!< WWDG MspInit callback ID */ +} HAL_WWDG_CallbackIDTypeDef; + +/** + * @brief HAL WWDG Callback pointer definition + */ +typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef *hppp); /*!< pointer to a WWDG common callback functions */ + +#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */ +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup WWDG_Exported_Constants WWDG Exported Constants + * @{ + */ + +/** @defgroup WWDG_Interrupt_definition WWDG Interrupt definition + * @{ + */ +#define WWDG_IT_EWI WWDG_CFR_EWI /*!< Early wakeup interrupt */ +/** + * @} + */ + +/** @defgroup WWDG_Flag_definition WWDG Flag definition + * @brief WWDG Flag definition + * @{ + */ +#define WWDG_FLAG_EWIF WWDG_SR_EWIF /*!< Early wakeup interrupt flag */ +/** + * @} + */ + +/** @defgroup WWDG_Prescaler WWDG Prescaler + * @{ + */ +#define WWDG_PRESCALER_1 0x00000000u /*!< WWDG counter clock = (PCLK1/4096)/1 */ +#define WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */ +#define WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */ +#define WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0) /*!< WWDG counter clock = (PCLK1/4096)/8 */ +#define WWDG_PRESCALER_16 WWDG_CFR_WDGTB_2 /*!< WWDG counter clock = (PCLK1/4096)/16 */ +#define WWDG_PRESCALER_32 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_0) /*!< WWDG counter clock = (PCLK1/4096)/32 */ +#define WWDG_PRESCALER_64 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1) /*!< WWDG counter clock = (PCLK1/4096)/64 */ +#define WWDG_PRESCALER_128 WWDG_CFR_WDGTB /*!< WWDG counter clock = (PCLK1/4096)/128 */ +/** + * @} + */ + +/** @defgroup WWDG_EWI_Mode WWDG Early Wakeup Interrupt Mode + * @{ + */ +#define WWDG_EWI_DISABLE 0x00000000u /*!< EWI Disable */ +#define WWDG_EWI_ENABLE WWDG_CFR_EWI /*!< EWI Enable */ +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ + +/** @defgroup WWDG_Private_Macros WWDG Private Macros + * @{ + */ +#define IS_WWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == WWDG_PRESCALER_1) || \ + ((__PRESCALER__) == WWDG_PRESCALER_2) || \ + ((__PRESCALER__) == WWDG_PRESCALER_4) || \ + ((__PRESCALER__) == WWDG_PRESCALER_8) || \ + ((__PRESCALER__) == WWDG_PRESCALER_16) || \ + ((__PRESCALER__) == WWDG_PRESCALER_32) || \ + ((__PRESCALER__) == WWDG_PRESCALER_64) || \ + ((__PRESCALER__) == WWDG_PRESCALER_128)) + +#define IS_WWDG_WINDOW(__WINDOW__) (((__WINDOW__) >= WWDG_CFR_W_6) && ((__WINDOW__) <= WWDG_CFR_W)) + +#define IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= WWDG_CR_T_6) && ((__COUNTER__) <= WWDG_CR_T)) + +#define IS_WWDG_EWI_MODE(__MODE__) (((__MODE__) == WWDG_EWI_ENABLE) || \ + ((__MODE__) == WWDG_EWI_DISABLE)) +/** + * @} + */ + + +/* Exported macros ------------------------------------------------------------*/ + +/** @defgroup WWDG_Exported_Macros WWDG Exported Macros + * @{ + */ + +/** + * @brief Enable the WWDG peripheral. + * @param __HANDLE__ WWDG handle + * @retval None + */ +#define __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA) + +/** + * @brief Enable the WWDG early wakeup interrupt. + * @param __HANDLE__: WWDG handle + * @param __INTERRUPT__ specifies the interrupt to enable. + * This parameter can be one of the following values: + * @arg WWDG_IT_EWI: Early wakeup interrupt + * @note Once enabled this interrupt cannot be disabled except by a system reset. + * @retval None + */ +#define __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__)) + +/** + * @brief Check whether the selected WWDG interrupt has occurred or not. + * @param __HANDLE__ WWDG handle + * @param __INTERRUPT__ specifies the it to check. + * This parameter can be one of the following values: + * @arg WWDG_FLAG_EWIF: Early wakeup interrupt IT + * @retval The new state of WWDG_FLAG (SET or RESET). + */ +#define __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__)) + +/** @brief Clear the WWDG interrupt pending bits. + * bits to clear the selected interrupt pending bits. + * @param __HANDLE__ WWDG handle + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. + * This parameter can be one of the following values: + * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag + */ +#define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__)) + +/** + * @brief Check whether the specified WWDG flag is set or not. + * @param __HANDLE__ WWDG handle + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag + * @retval The new state of WWDG_FLAG (SET or RESET). + */ +#define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) + +/** + * @brief Clear the WWDG's pending flags. + * @param __HANDLE__ WWDG handle + * @param __FLAG__ specifies the flag to clear. + * This parameter can be one of the following values: + * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag + * @retval None + */ +#define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) + +/** @brief Check whether the specified WWDG interrupt source is enabled or not. + * @param __HANDLE__ WWDG Handle. + * @param __INTERRUPT__ specifies the WWDG interrupt source to check. + * This parameter can be one of the following values: + * @arg WWDG_IT_EWI: Early Wakeup Interrupt + * @retval state of __INTERRUPT__ (TRUE or FALSE). + */ +#define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR\ + & (__INTERRUPT__)) == (__INTERRUPT__)) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup WWDG_Exported_Functions + * @{ + */ + +/** @addtogroup WWDG_Exported_Functions_Group1 + * @{ + */ +/* Initialization/de-initialization functions **********************************/ +HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg); +void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg); +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, + pWWDG_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @addtogroup WWDG_Exported_Functions_Group2 + * @{ + */ +/* I/O operation functions ******************************************************/ +HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg); +void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg); +void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef *hwwdg); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WBAxx_HAL_WWDG_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_adc.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_adc.h new file mode 100644 index 0000000000..01af3adc42 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_adc.h @@ -0,0 +1,5084 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_ll_adc.h + * @author MCD Application Team + * @brief Header file of ADC LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_LL_ADC_H +#define STM32WBAxx_LL_ADC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx.h" + +/** @addtogroup STM32WBAxx_LL_Driver + * @{ + */ + +#if defined (ADC4) + +/** @defgroup ADC_LL ADC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup ADC_LL_Private_Constants ADC Private Constants + * @{ + */ + +/* Internal mask for ADC group regular sequencer: */ +/* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */ +/* - sequencer rank bits position into the selected register */ + +#define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0) + +/* Definition of ADC group regular sequencer bits information to be inserted */ +/* into ADC group regular sequencer ranks literals definition. */ +#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC_CHSELR_SQ1" position in register */ +#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ( 4UL) /* Equivalent to bitfield "ADC_CHSELR_SQ2" position in register */ +#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS ( 8UL) /* Equivalent to bitfield "ADC_CHSELR_SQ3" position in register */ +#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (12UL) /* Equivalent to bitfield "ADC_CHSELR_SQ4" position in register */ +#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS (16UL) /* Equivalent to bitfield "ADC_CHSELR_SQ5" position in register */ +#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS (20UL) /* Equivalent to bitfield "ADC_CHSELR_SQ6" position in register */ +#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS (24UL) /* Equivalent to bitfield "ADC_CHSELR_SQ7" position in register */ +#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS (28UL) /* Equivalent to bitfield "ADC_CHSELR_SQ8" position in register */ + + + +/* Internal mask for ADC group regular trigger: */ +/* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */ +/* - regular trigger source */ +/* - regular trigger edge */ +#define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR1_EXTEN_0) /* Trigger edge set to rising edge (default setting for + compatibility with some ADC on other STM32 series + having this setting set by HW default value) */ + +/* Mask containing trigger source masks for each of possible */ +/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ +/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ +#define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTSEL) << (4U * 0UL)) | \ + ((ADC_CFGR1_EXTSEL) << (4U * 1UL)) | \ + ((ADC_CFGR1_EXTSEL) << (4U * 2UL)) | \ + ((ADC_CFGR1_EXTSEL) << (4U * 3UL)) ) + +/* Mask containing trigger edge masks for each of possible */ +/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ +/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ +#define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN) << (4U * 0UL)) | \ + ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \ + ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \ + ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) ) + +/* Definition of ADC group regular trigger bits information. */ +#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_CFGR1_EXTSEL" position in register */ +#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (10UL) /* Equivalent to bitfield "ADC_CFGR1_EXTEN" position in register */ + + + +/* Internal mask for ADC channel: */ +/* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */ +/* - channel identifier defined by number */ +/* - channel identifier defined by bitfield */ +/* - channel differentiation between external channels (connected to */ +/* GPIO pins) and internal channels (connected to internal paths) */ +#define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR1_AWD1CH) +#define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_CHSELR_CHSEL) +#define ADC_CHANNEL_ID_NUMBER_MASK_SEQ (ADC_CHSELR_SQ1 << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) /* Equivalent to + ADC_CHANNEL_ID_NUMBER_MASK with reduced range: on this STM32 series, ADC group regular sequencer, + if set to mode "fully configurable", can contain channels with a restricted channel number. + Refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). */ +#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26UL) /* Equivalent to bitfield "ADC_CHANNEL_ID_NUMBER_MASK" + position in register */ +#define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | \ + ADC_CHANNEL_ID_INTERNAL_CH_MASK) +/* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */ +#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (0x0000001FUL) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK + >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */ + +/* Channel differentiation between external and internal channels */ +#define ADC_CHANNEL_ID_INTERNAL_CH (0x80000000UL) /* Marker of internal channel */ +#define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH) + +/* Definition of channels ID number information to be inserted into */ +/* channels literals definition. */ +#define ADC_CHANNEL_0_NUMBER (0x00000000UL) +#define ADC_CHANNEL_1_NUMBER (ADC_CFGR1_AWD1CH_0) +#define ADC_CHANNEL_2_NUMBER (ADC_CFGR1_AWD1CH_1) +#define ADC_CHANNEL_3_NUMBER (ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0) +#define ADC_CHANNEL_4_NUMBER (ADC_CFGR1_AWD1CH_2) +#define ADC_CHANNEL_5_NUMBER (ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_0) +#define ADC_CHANNEL_6_NUMBER (ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1) +#define ADC_CHANNEL_7_NUMBER (ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0) +#define ADC_CHANNEL_8_NUMBER (ADC_CFGR1_AWD1CH_3) +#define ADC_CHANNEL_9_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_0) +#define ADC_CHANNEL_10_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_1) +#define ADC_CHANNEL_11_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0) +#define ADC_CHANNEL_12_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2) +#define ADC_CHANNEL_13_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_0) +#define ADC_CHANNEL_14_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1) +#define ADC_CHANNEL_15_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2 | \ + ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0) +#define ADC_CHANNEL_16_NUMBER (ADC_CFGR1_AWD1CH_4) +#define ADC_CHANNEL_17_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_0) +#define ADC_CHANNEL_18_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_1) + +/* Definition of channels ID bitfield information to be inserted into */ +/* channels literals definition. */ +#define ADC_CHANNEL_0_BITFIELD (ADC_CHSELR_CHSEL0) +#define ADC_CHANNEL_1_BITFIELD (ADC_CHSELR_CHSEL1) +#define ADC_CHANNEL_2_BITFIELD (ADC_CHSELR_CHSEL2) +#define ADC_CHANNEL_3_BITFIELD (ADC_CHSELR_CHSEL3) +#define ADC_CHANNEL_4_BITFIELD (ADC_CHSELR_CHSEL4) +#define ADC_CHANNEL_5_BITFIELD (ADC_CHSELR_CHSEL5) +#define ADC_CHANNEL_6_BITFIELD (ADC_CHSELR_CHSEL6) +#define ADC_CHANNEL_7_BITFIELD (ADC_CHSELR_CHSEL7) +#define ADC_CHANNEL_8_BITFIELD (ADC_CHSELR_CHSEL8) +#define ADC_CHANNEL_9_BITFIELD (ADC_CHSELR_CHSEL9) +#define ADC_CHANNEL_10_BITFIELD (ADC_CHSELR_CHSEL10) +#define ADC_CHANNEL_11_BITFIELD (ADC_CHSELR_CHSEL11) +#define ADC_CHANNEL_12_BITFIELD (ADC_CHSELR_CHSEL12) +#define ADC_CHANNEL_13_BITFIELD (ADC_CHSELR_CHSEL13) +#define ADC_CHANNEL_14_BITFIELD (ADC_CHSELR_CHSEL14) +#define ADC_CHANNEL_15_BITFIELD (ADC_CHSELR_CHSEL15) +#define ADC_CHANNEL_16_BITFIELD (ADC_CHSELR_CHSEL16) +#define ADC_CHANNEL_17_BITFIELD (ADC_CHSELR_CHSEL17) + +/* Internal mask for ADC channel sampling time: */ +/* To select into literals LL_ADC_SAMPLINGTIME_x */ +/* the relevant bits for: */ +/* (concatenation of multiple bits used in register SMPR) */ +/* - ADC channels sampling time: setting channel wise, to map each channel */ +/* on one of the common sampling time available. */ +/* - ADC channels common sampling time: set a sampling time into one of the */ +/* common sampling time available. */ +#define ADC_SAMPLING_TIME_CH_MASK (ADC_CHANNEL_ID_BITFIELD_MASK << ADC_SMPR_SMPSEL0_BITOFFSET_POS) +#define ADC_SAMPLING_TIME_SMP_MASK (ADC_SMPR_SMP2 | ADC_SMPR_SMP1) +#define ADC_SAMPLING_TIME_SMP_SHIFT_MASK (ADC_SMPR_SMP2_BITOFFSET_POS | ADC_SMPR_SMP1_BITOFFSET_POS) + +/* Internal mask for ADC analog watchdog: */ +/* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */ +/* (concatenation of multiple bits used in different analog watchdogs, */ +/* (feature of several watchdogs not available on all STM32 series)). */ +/* - analog watchdog 1: monitored channel defined by number, */ +/* selection of ADC group (ADC group regular). */ +/* - analog watchdog 2 and 3: monitored channel defined by bitfield, no */ +/* selection on groups. */ + +/* Internal register offset for ADC analog watchdog channel configuration */ +#define ADC_AWD_CR1_REGOFFSET (0x00000000UL) +#define ADC_AWD_CR2_REGOFFSET (0x00100000UL) +#define ADC_AWD_CR3_REGOFFSET (0x00200000UL) + +/* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */ +/* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */ +#define ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0) +#define ADC_AWD_CR12_REGOFFSETGAP_VAL (0x00000024UL) + +#define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET) +#define ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS (20UL) + +#define ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR1_AWD1CH | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) +#define ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH) +#define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK) + +#define ADC_AWD_CRX_REGOFFSET_POS (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET + in ADC_AWD_CRX_REGOFFSET_MASK */ + +/* Internal register offset for ADC analog watchdog threshold configuration */ +#define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET) +#define ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET) +#define ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET + (1UL << ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS)) +#define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET) +#define ADC_AWD_TRX_REGOFFSET_POS (ADC_AWD_CRX_REGOFFSET_POS) /* Position of bits ADC_SQRx_REGOFFSET + in ADC_AWD_TRX_REGOFFSET_MASK */ +#define ADC_AWD_TRX_BIT_HIGH_MASK (0x00010000UL) /* Selection of 1 bit to discriminate + threshold high: mask of bit */ +#define ADC_AWD_TRX_BIT_HIGH_POS (16UL) /* Selection of 1 bit to discriminate + threshold high: position of bit */ +#define ADC_AWD_TRX_BIT_HIGH_SHIFT4 (ADC_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC_AWD_TRX_BIT_HIGH to + position to perform a shift of 4 ranks */ +#define ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS (20UL) + + + +/* ADC registers bits positions */ +#define ADC_CHSELR_CHSEL0_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL0" position in register */ +#define ADC_CHSELR_CHSEL1_BITOFFSET_POS ( 1UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL1" position in register */ +#define ADC_CHSELR_CHSEL2_BITOFFSET_POS ( 2UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL2" position in register */ +#define ADC_CHSELR_CHSEL3_BITOFFSET_POS ( 3UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL3" position in register */ +#define ADC_CHSELR_CHSEL4_BITOFFSET_POS ( 4UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL4" position in register */ +#define ADC_CHSELR_CHSEL5_BITOFFSET_POS ( 5UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL5" position in register */ +#define ADC_CHSELR_CHSEL6_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL6" position in register */ +#define ADC_CHSELR_CHSEL7_BITOFFSET_POS ( 7UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL7" position in register */ +#define ADC_CHSELR_CHSEL8_BITOFFSET_POS ( 8UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL8" position in register */ +#define ADC_CHSELR_CHSEL9_BITOFFSET_POS ( 9UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL9" position in register */ +#define ADC_CHSELR_CHSEL10_BITOFFSET_POS (10UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL10" position in register */ +#define ADC_CHSELR_CHSEL11_BITOFFSET_POS (11UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL11" position in register */ +#define ADC_CHSELR_CHSEL12_BITOFFSET_POS (12UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL12" position in register */ +#define ADC_CHSELR_CHSEL13_BITOFFSET_POS (13UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL13" position in register */ +#define ADC_CHSELR_CHSEL14_BITOFFSET_POS (14UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL14" position in register */ +#define ADC_CHSELR_CHSEL15_BITOFFSET_POS (15UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL15" position in register */ +#define ADC_CHSELR_CHSEL16_BITOFFSET_POS (16UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL16" position in register */ +#define ADC_CHSELR_CHSEL17_BITOFFSET_POS (17UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL17" position in register */ +#define ADC_CHSELR_CHSEL18_BITOFFSET_POS (18UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL18" position in register */ +#define ADC_SMPR_SMP1_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC_SMPR_SMP1" position in register */ +#define ADC_SMPR_SMP2_BITOFFSET_POS ( 4UL) /* Equivalent to bitfield "ADC_SMPR_SMP2" position in register */ +#define ADC_SMPR_SMPSEL0_BITOFFSET_POS ( 8UL) /* Equivalent to bitfield "ADC_SMPR_SMPSEL0" position in register */ + + +/* ADC registers bits groups */ +#define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_ADEN | ADC_CR_ADDIS \ + | ADC_CR_ADSTART | ADC_CR_ADSTP) /* ADC register CR bits with + HW property "rs": Software can read as well as set this bit. + Writing '0' has no effect on the bit value. */ + + +/* ADC internal channels related definitions */ +/* Internal voltage reference VrefInt */ +#define VREFINT_CAL_ADDR ((uint16_t*) (0x0BF907A5UL)) /* Internal voltage reference, address of + parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC + (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */ +#define VREFINT_CAL_VREF ( 3000UL) /* Analog voltage reference (Vref+) value + with which VrefInt has been calibrated in production + (tolerance: +-10 mV) (unit: mV). */ +/* Temperature sensor */ +#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x0BF90710UL)) /* Address of parameter TS_CAL1: On this series, + temperature sensor ADC raw data acquired at temperature 30 DegC + (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x0BF90742UL)) /* Address of parameter TS_CAL2: On this series, + temperature sensor ADC raw data acquired at temperature 130 DegC + (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Temperature at which temperature sensor + has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR + (tolerance: +-5 DegC) (unit: DegC). */ +#define TEMPSENSOR_CAL2_TEMP (( int32_t) 130) /* Temperature at which temperature sensor + has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR + (tolerance: +-5 DegC) (unit: DegC). */ +#define TEMPSENSOR_CAL_VREFANALOG ( 3000UL) /* Analog voltage reference (Vref+) value + with which temperature sensor has been calibrated in production + (tolerance: +-10 mV) (unit: mV). */ + +/** + * @} + */ + + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup ADC_LL_Private_Macros ADC Private Macros + * @{ + */ + +/** + * @brief Driver macro reserved for internal use: isolate bits with the + * selected mask and shift them to the register LSB + * (shift mask on register position bit 0). + * @param __BITS__ Bits in register 32 bits + * @param __MASK__ Mask in register 32 bits + * @retval Bits in register 32 bits + */ +#define __ADC_MASK_SHIFT(__BITS__, __MASK__) \ + (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__))) + +/** + * @brief Driver macro reserved for internal use: set a pointer to + * a register from a register basis from which an offset + * is applied. + * @param __REG__ Register basis from which the offset is applied. + * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers). + * @retval Pointer to register address + */ +#define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \ + ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL)))) + +/** + * @} + */ + + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup ADC_LL_ES_INIT ADC Exported Init structure + * @{ + */ + +/** + * @brief Structure definition of some features of ADC common parameters + * and multimode + * (all ADC instances belonging to the same ADC common instance). + * @note The setting of these parameters by function @ref LL_ADC_CommonInit() + * is conditioned to ADC instances state (all ADC instances + * sharing the same ADC common instance): + * All ADC instances sharing the same ADC common instance must be + * disabled. + */ +typedef struct +{ + uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler. + This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE + This feature can be modified afterwards using unitary function + @ref LL_ADC_SetCommonClock(). */ + +} LL_ADC_CommonInitTypeDef; + +/** + * @brief Structure definition of some features of ADC instance. + * @note These parameters have an impact on ADC scope: ADC instance. + * Refer to corresponding unitary functions into + * @ref ADC_LL_EF_Configuration_ADC_Instance . + * @note The setting of these parameters by function @ref LL_ADC_Init() + * is conditioned to ADC state: + * ADC instance must be disabled. + * This condition is applied to all ADC features, for efficiency + * and compatibility over all STM32 series. However, the different + * features can be set under different ADC state conditions + * (setting possible with ADC enabled without conversion on going, + * ADC enabled with conversion on going, ...) + * Each feature can be updated afterwards with a unitary function + * and potentially with ADC in a different state than disabled, + * refer to description of each function for setting + * conditioned to ADC state. + */ +typedef struct +{ + uint32_t Resolution; /*!< Set ADC resolution. + This parameter can be a value of @ref ADC_LL_EC_RESOLUTION + This feature can be modified afterwards using unitary function + @ref LL_ADC_SetResolution(). */ + + uint32_t DataAlignment; /*!< Set ADC conversion data alignment. + This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN + This feature can be modified afterwards using unitary function + @ref LL_ADC_SetDataAlignment(). */ + + +} LL_ADC_InitTypeDef; + +/** + * @brief Structure definition of some features of ADC group regular. + * @note These parameters have an impact on ADC scope: ADC group regular. + * Refer to corresponding unitary functions into + * @ref ADC_LL_EF_Configuration_ADC_Group_Regular + * (functions with prefix "REG"). + * @note The setting of these parameters by function @ref LL_ADC_REG_Init() + * is conditioned to ADC state: + * ADC instance must be disabled. + * This condition is applied to all ADC features, for efficiency + * and compatibility over all STM32 series. However, the different + * features can be set under different ADC state conditions + * (setting possible with ADC enabled without conversion on going, + * ADC enabled with conversion on going, ...) + * Each feature can be updated afterwards with a unitary function + * and potentially with ADC in a different state than disabled, + * refer to description of each function for setting + * conditioned to ADC state. + */ +typedef struct +{ + uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or + from external peripheral (timer event, external interrupt line). + This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE + @note On this STM32 series, setting trigger source to external trigger also + set trigger polarity to rising edge(default setting for compatibility + with some ADC on other STM32 series having this setting set by HW + default value). + In case of need to modify trigger edge, use function + @ref LL_ADC_REG_SetTriggerEdge(). + This feature can be modified afterwards using unitary function + @ref LL_ADC_REG_SetTriggerSource(). */ + + uint32_t SequencerLength; /*!< Set ADC group regular sequencer length. + @note This parameter has an effect only if group regular sequencer is set + to mode "fully configurable". Refer to function + @ref LL_ADC_REG_SetSequencerConfigurable(). + This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH + This feature can be modified afterwards using unitary function + @ref LL_ADC_REG_SetSequencerLength(). */ + + uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided + and scan conversions interrupted every selected number of ranks. + This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE + @note This parameter has an effect only if group regular sequencer is + enabled (depending on the sequencer mode: scan length of 2 ranks or + more, or several ADC channels enabled in group regular sequencer. + Refer to function @ref LL_ADC_REG_SetSequencerConfigurable() ). + This feature can be modified afterwards using unitary function + @ref LL_ADC_REG_SetSequencerDiscont(). */ + + uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC + conversions are performed in single mode (one conversion per trigger) or in + continuous mode (after the first trigger, following conversions launched + successively automatically). + This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE + Note: It is not possible to enable both ADC group regular continuous mode + and discontinuous mode. + This feature can be modified afterwards using unitary function + @ref LL_ADC_REG_SetContinuousMode(). */ + + uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer + by DMA, and DMA requests mode. + This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER + This feature can be modified afterwards using unitary function + @ref LL_ADC_REG_SetDMATransfer(). */ + + uint32_t Overrun; /*!< Set ADC group regular behavior in case of overrun: + data preserved or overwritten. + This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR + This feature can be modified afterwards using unitary function + @ref LL_ADC_REG_SetOverrun(). */ + +} LL_ADC_REG_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup ADC_LL_Exported_Constants ADC Exported Constants + * @{ + */ + +/** @defgroup ADC_LL_EC_FLAG ADC flags + * @brief Flags defines which can be used with LL_ADC_ReadReg function + * @{ + */ +#define LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY /*!< ADC flag ADC instance ready */ +#define LL_ADC_FLAG_LDORDY ADC_ISR_LDORDY /*!< ADC flag ADC internal voltage regulator ready */ +#define LL_ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC flag ADC group regular end of unitary + conversion */ +#define LL_ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC flag ADC group regular end of sequence + conversions */ +#define LL_ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC flag ADC group regular overrun */ +#define LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC flag ADC group regular end of sampling phase */ +#define LL_ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC flag ADC analog watchdog 1 */ +#define LL_ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC flag ADC analog watchdog 2 */ +#define LL_ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC flag ADC analog watchdog 3 */ +#define LL_ADC_FLAG_EOCAL ADC_ISR_EOCAL /*!< ADC flag end of calibration */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable) + * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions + * @{ + */ +#define LL_ADC_IT_ADRDY ADC_IER_ADRDYIE /*!< ADC interruption ADC instance ready */ +#define LL_ADC_IT_LDORDY ADC_IER_LDORDYIE /*!< ADC interruption internal voltage regulator ready */ +#define LL_ADC_IT_EOC ADC_IER_EOCIE /*!< ADC interruption ADC group regular end of unitary + conversion */ +#define LL_ADC_IT_EOS ADC_IER_EOSIE /*!< ADC interruption ADC group regular end of sequence + conversions */ +#define LL_ADC_IT_OVR ADC_IER_OVRIE /*!< ADC interruption ADC group regular overrun */ +#define LL_ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC interruption ADC group regular end of sampling + phase */ +#define LL_ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC interruption ADC analog watchdog 1 */ +#define LL_ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC interruption ADC analog watchdog 2 */ +#define LL_ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC interruption ADC analog watchdog 3 */ +#define LL_ADC_IT_EOCAL ADC_IER_EOCALIE /*!< ADC interruption ADC end of calibration */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose + * @{ + */ +/* List of ADC registers intended to be used (most commonly) with */ +/* DMA transfer. */ +/* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */ +#define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000UL) /* ADC group regular conversion data register + (corresponding to register DR) to be used with ADC configured in independent + mode. Without DMA transfer, register accessed by LL function + @ref LL_ADC_REG_ReadConversionData32() and other + functions @ref LL_ADC_REG_ReadConversionDatax() */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source + * @{ + */ +#define LL_ADC_CLOCK_ASYNC_DIV1 (0x00000000UL) /*!< ADC asynchronous clock without + prescaler */ +#define LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with + prescaler division by 2. Setting common to ADC instances of ADC common + group */ +#define LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with + prescaler division by 4. Setting common to ADC instances of ADC common + group */ +#define LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with + prescaler division by 6. Setting common to ADC instances of ADC common + group */ +#define LL_ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2) /*!< ADC asynchronous clock with + prescaler division by 8. Setting common to ADC instances of ADC common + group */ +#define LL_ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with + prescaler division by 10. Setting common to ADC instances of ADC common + group */ +#define LL_ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with + prescaler division by 12. Setting common to ADC instances of ADC common + group */ +#define LL_ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 \ + | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with + prescaler division by 16. Setting common to ADC instances of ADC common + group */ +#define LL_ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3) /*!< ADC asynchronous clock with + prescaler division by 32. Setting common to ADC instances of ADC common + group */ +#define LL_ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with + prescaler division by 64. Setting common to ADC instances of ADC common + group */ +#define LL_ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with + prescaler division by 128. Setting common to ADC instances of ADC common + group */ +#define LL_ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 \ + | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with + prescaler division by 256. Setting common to ADC instances of ADC common + group */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels + * @{ + */ +/* Note: Other measurement paths to internal channels may be available */ +/* (connections to other peripherals). */ +/* If they are not listed below, they do not require any specific */ +/* path enable. In this case, Access to measurement path is done */ +/* only by selecting the corresponding ADC internal channel. */ +#define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL) /*!< ADC measurement paths all disabled */ +#define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */ +#define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN) /*!< ADC measurement path to internal channel + temperature sensor */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution + * @{ + */ +#define LL_ADC_RESOLUTION_12B (0x00000000UL) /*!< ADC resolution 12 bits */ +#define LL_ADC_RESOLUTION_10B ( ADC_CFGR1_RES_0) /*!< ADC resolution 10 bits */ +#define LL_ADC_RESOLUTION_8B (ADC_CFGR1_RES_1 ) /*!< ADC resolution 8 bits */ +#define LL_ADC_RESOLUTION_6B (ADC_CFGR1_RES_1 | ADC_CFGR1_RES_0) /*!< ADC resolution 6 bits */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment + * @{ + */ +#define LL_ADC_DATA_ALIGN_RIGHT (0x00000000UL) /*!< ADC conversion data alignment: right aligned + (alignment on data register LSB bit 0)*/ +#define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR1_ALIGN) /*!< ADC conversion data alignment: left aligned + (alignment on data register MSB bit 15)*/ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_LP_MODE ADC instance - Low power mode + * @{ + */ +#define LL_ADC_LP_AUTOWAIT_DISABLE (0x00000000UL) /*!< ADC low power mode auto delay disabled. */ +#define LL_ADC_LP_AUTOWAIT_ENABLE (ADC_CFGR1_WAIT) /*!< ADC low power mode auto delay enabled: dynamic + low power mode, ADC conversions are performed only when necessary + (when previous ADC conversion data is read). + See description with function @ref LL_ADC_SetLPModeAutoWait(). */ +/** + * @} + */ +/* Definitions for backward compatibility with legacy STM32 series */ +#define LL_ADC_LP_MODE_NONE LL_ADC_LP_AUTOWAIT_DISABLE +#define LL_ADC_LP_AUTOWAIT LL_ADC_LP_AUTOWAIT_ENABLE + + +/** @defgroup ADC_LL_EC_AUTOPOWEROFF_MODE ADC instance - Low power mode auto power-off + * @{ + */ +#define LL_ADC_LP_AUTOPOWEROFF_DISABLE (0x00000000UL) /*!< ADC low power mode auto power-off disabled */ +#define LL_ADC_LP_AUTOPOWEROFF_ENABLE (ADC_PWRR_AUTOFF) /*!< ADC low power mode auto power-off enabled: the ADC + automatically powers-off after a ADC conversion and automatically wakes up + when a new ADC conversion is triggered (with startup time between trigger + and start of sampling). See description with function + @ref LL_ADC_SetLPModeAutoPowerOff(). + It can be combined with mode low power mode auto wait. */ +/** + * @} + */ + + +/** @defgroup ADC_LL_EC_AUTONOMOUS_DEEP_POWER_DOWN_MODE ADC instance - Autonomous deep power down mode + * @{ + */ +#define LL_ADC_LP_AUTONOMOUS_DPD_DISABLE (0x00000000UL) /*!< ADC deep power down in autonomous mode disabled */ +#define LL_ADC_LP_AUTONOMOUS_DPD_ENABLE (ADC_PWRR_DPD) /*!< ADC deep power down in autonomous mode enabled */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_TRIGGER_FREQ ADC group regular - Trigger frequency mode + * @{ + */ +#define LL_ADC_TRIGGER_FREQ_HIGH (0x00000000UL) /*!< ADC trigger frequency mode set to high frequency. + Note: ADC trigger frequency mode must be set to low frequency when a duration + is exceeded before ADC conversion start trigger event (between ADC enable + and ADC conversion start trigger event or between two ADC conversion start + trigger event). + Duration value: Refer to device datasheet, parameter "tIdle". */ +#define LL_ADC_TRIGGER_FREQ_LOW (ADC_CFGR2_LFTRIG) /*!< ADC trigger frequency mode set to low frequency. + Note: ADC trigger frequency mode must be set to low frequency when a duration + is exceeded before ADC conversion start trigger event (between ADC enable + and ADC conversion start trigger event or between two ADC conversion start + trigger event). + Duration value: Refer to device datasheet, parameter "tIdle". */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_SAMPLINGTIME_COMMON ADC instance - Sampling time common to a group of channels + * @{ + */ +#define LL_ADC_SAMPLINGTIME_COMMON_1 (ADC_SMPR_SMP1_BITOFFSET_POS) /*!< Set sampling time common to a group + of channels: sampling time nb 1 */ +#define LL_ADC_SAMPLINGTIME_COMMON_2 (ADC_SMPR_SMP2_BITOFFSET_POS \ + | ADC_SAMPLING_TIME_CH_MASK) /*!< Set sampling time common to a group + of channels: sampling time nb 2 */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups + * @{ + */ +#define LL_ADC_GROUP_REGULAR (0x00000001UL) /*!< ADC group regular (available on all STM32 devices) */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number + * @{ + */ +#define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER \ + | ADC_CHANNEL_0_BITFIELD ) /*!< ADC channel ADCx_IN0 */ +#define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER \ + | ADC_CHANNEL_1_BITFIELD ) /*!< ADC channel ADCx_IN1 */ +#define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER \ + | ADC_CHANNEL_2_BITFIELD ) /*!< ADC channel ADCx_IN2 */ +#define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER \ + | ADC_CHANNEL_3_BITFIELD ) /*!< ADC channel ADCx_IN3 */ +#define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER \ + | ADC_CHANNEL_4_BITFIELD ) /*!< ADC channel ADCx_IN4 */ +#define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER \ + | ADC_CHANNEL_5_BITFIELD ) /*!< ADC channel ADCx_IN5 */ +#define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER \ + | ADC_CHANNEL_6_BITFIELD ) /*!< ADC channel ADCx_IN6 */ +#define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER \ + | ADC_CHANNEL_7_BITFIELD ) /*!< ADC channel ADCx_IN7 */ +#define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER \ + | ADC_CHANNEL_8_BITFIELD ) /*!< ADC channel ADCx_IN8 */ +#define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER \ + | ADC_CHANNEL_9_BITFIELD ) /*!< ADC channel ADCx_IN9 */ +#define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER \ + | ADC_CHANNEL_10_BITFIELD) /*!< ADC channel ADCx_IN10 */ +#define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER \ + | ADC_CHANNEL_11_BITFIELD) /*!< ADC channel ADCx_IN11 */ +#define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER \ + | ADC_CHANNEL_12_BITFIELD) /*!< ADC channel ADCx_IN12 */ +#define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER \ + | ADC_CHANNEL_13_BITFIELD) /*!< ADC channel ADCx_IN13 */ +#define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER \ + | ADC_CHANNEL_14_BITFIELD) /*!< ADC channel ADCx_IN14 */ +#define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER \ + | ADC_CHANNEL_15_BITFIELD) /*!< ADC channel ADCx_IN15 */ +#define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER \ + | ADC_CHANNEL_16_BITFIELD) /*!< ADC channel ADCx_IN16 */ +#define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER \ + | ADC_CHANNEL_17_BITFIELD) /*!< ADC channel ADCx_IN17 */ +#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_0 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel + connected to VrefInt: Internal voltage reference. */ +#define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel + connected to internal temperature sensor. */ +#define LL_ADC_CHANNEL_VCORE (LL_ADC_CHANNEL_12 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel + connected to Vcore: internal power supply of MCU digital logic */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source + * @{ + */ +#define LL_ADC_REG_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group regular + conversion trigger internal: SW start. */ +#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: TIM1 TRGO. + Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM1_CH4 (ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: TIM1 channel 4 event + (capture compare: input capture or output capture). + Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: TIM2 TRGO. + Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_LPTIM1_CH1 (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_0 \ + | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: LPTIM1 channel 1 event + (capture compare: input capture or output capture). + Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_EXTI_LINE15 (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 \ + | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: external interrupt line 15. + Trigger edge set to rising edge (default setting). */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge + * @{ + */ +#define LL_ADC_REG_TRIG_EXT_RISING (ADC_CFGR1_EXTEN_0) /*!< ADC group regular conversion + trigger polarity set to rising edge */ +#define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR1_EXTEN_1) /*!< ADC group regular conversion + trigger polarity set to falling edge */ +#define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR1_EXTEN_1 | ADC_CFGR1_EXTEN_0) /*!< ADC group regular conversion + trigger polarity set to both rising and falling edges */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode + * @{ + */ +#define LL_ADC_REG_CONV_SINGLE (0x00000000UL) /*!< ADC conversions performed in single mode: + one conversion per trigger */ +#define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR1_CONT) /*!< ADC conversions performed in continuous mode: + after the first trigger, following conversions launched successively + automatically */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data + * @{ + */ +#define LL_ADC_REG_DMA_TRANSFER_NONE (0x00000000UL) /*!< ADC conversions are not transferred by DMA */ +#define LL_ADC_REG_DMA_TRANSFER_LIMITED (ADC_CFGR1_DMAEN) /*!< ADC conversion data are transferred by DMA, + in limited mode (one shot mode): DMA transfer requests are stopped when + number of DMA data transfers (number of ADC conversions) is reached. + This ADC mode is intended to be used with DMA mode non-circular. */ +#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN) /*!< ADC conversion data are + transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, + whatever number of DMA data transferred (number of ADC conversions). + This ADC mode is intended to be used with DMA mode circular. */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data + * @{ + */ +#define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000UL) /*!< ADC group regular behavior in case of overrun: + data preserved */ +#define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR1_OVRMOD) /*!< ADC group regular behavior in case of overrun: + data overwritten */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_SEQ_MODE ADC group regular - Sequencer configuration flexibility + * @{ + */ +#define LL_ADC_REG_SEQ_FIXED (0x00000000UL) /*!< Sequencer configured to not fully configurable: + sequencer length and each rank affectation to a channel are fixed + by channel HW number. Refer to description of function + @ref LL_ADC_REG_SetSequencerChannels(). */ +#define LL_ADC_REG_SEQ_CONFIGURABLE (ADC_CFGR1_CHSELRMOD) /*!< Sequencer configured to fully configurable: + sequencer length and each rank affectation to a channel are configurable. + Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length + * @{ + */ +#define LL_ADC_REG_SEQ_SCAN_DISABLE (ADC_CHSELR_SQ2) /*!< ADC group regular sequencer disable + (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS (ADC_CHSELR_SQ3) /*!< ADC group regular sequencer enable + with 2 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS (ADC_CHSELR_SQ4) /*!< ADC group regular sequencer enable + with 3 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS (ADC_CHSELR_SQ5) /*!< ADC group regular sequencer enable + with 4 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS (ADC_CHSELR_SQ6) /*!< ADC group regular sequencer enable + with 5 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS (ADC_CHSELR_SQ7) /*!< ADC group regular sequencer enable + with 6 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS (ADC_CHSELR_SQ8) /*!< ADC group regular sequencer enable + with 7 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS (0x00000000UL) /*!< ADC group regular sequencer enable + with 8 ranks in the sequence */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_SEQ_SCAN_DIRECTION ADC group regular - Sequencer scan direction + * @{ + */ +#define LL_ADC_REG_SEQ_SCAN_DIR_FORWARD (0x00000000UL) /*!< On this STM32 series, parameter relevant only if + sequencer set to mode not fully configurable, refer to function + @ref LL_ADC_REG_SetSequencerConfigurable(). ADC group regular sequencer scan + direction forward: from lowest channel number to highest channel number + (scan of all ranks, ADC conversion of ranks with channels enabled in + sequencer). On some other STM32 series, this setting is not available + and the default scan direction is forward. */ +#define LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD (ADC_CFGR1_SCANDIR) /*!< On this STM32 series, parameter relevant only if + sequencer set to mode not fully configurable, refer to function + @ref LL_ADC_REG_SetSequencerConfigurable(). ADC group regular sequencer scan + direction backward: from highest channel number to lowest channel number + (scan of all ranks, ADC conversion of ranks with channels enabled in + sequencer) */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode + * @{ + */ +#define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group regular sequencer + discontinuous mode disable */ +#define LL_ADC_REG_SEQ_DISCONT_1RANK (ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer + discontinuous mode enable with sequence interruption every rank */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks + * @{ + */ +#define LL_ADC_REG_RANK_1 (ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 1 */ +#define LL_ADC_REG_RANK_2 (ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 2 */ +#define LL_ADC_REG_RANK_3 (ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 3 */ +#define LL_ADC_REG_RANK_4 (ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 4 */ +#define LL_ADC_REG_RANK_5 (ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 5 */ +#define LL_ADC_REG_RANK_6 (ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 6 */ +#define LL_ADC_REG_RANK_7 (ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 7 */ +#define LL_ADC_REG_RANK_8 (ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 8 */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time + * @{ + */ +#define LL_ADC_SAMPLINGTIME_1CYCLE_5 (0x00000000UL) /*!< Sampling time 1.5 ADC clock cycle */ +#define LL_ADC_SAMPLINGTIME_3CYCLES_5 (ADC_SMPR_SMP1_0) /*!< Sampling time 3.5 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_7CYCLES_5 (ADC_SMPR_SMP1_1) /*!< Sampling time 7.5 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_12CYCLES_5 (ADC_SMPR_SMP1_1 \ + | ADC_SMPR_SMP1_0) /*!< Sampling time 12.5 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_19CYCLES_5 (ADC_SMPR_SMP1_2) /*!< Sampling time 19.5 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_39CYCLES_5 (ADC_SMPR_SMP1_2 \ + | ADC_SMPR_SMP1_0) /*!< Sampling time 39.5 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_79CYCLES_5 (ADC_SMPR_SMP1_2 \ + | ADC_SMPR_SMP1_1) /*!< Sampling time 79.5 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_814CYCLES_5 (ADC_SMPR_SMP1_2 \ + | ADC_SMPR_SMP1_1 \ + | ADC_SMPR_SMP1_0) /*!< Sampling time 814.5 ADC clock cycles */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number + * @{ + */ +#define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK \ + | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */ +#define LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK \ + | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */ +#define LL_ADC_AWD3 (ADC_AWD_CR23_CHANNEL_MASK \ + | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels + * @{ + */ +#define LL_ADC_AWD_DISABLE (0x00000000UL) /*!< ADC analog watchdog monitoring + disabled */ +#define LL_ADC_AWD_ALL_CHANNELS_REG (ADC_AWD_CR23_CHANNEL_MASK \ + | ADC_CFGR1_AWD1EN) /*!< ADC analog watchdog monitoring + of all channels, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN0, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN1, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN2, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN3, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN4, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN5, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN6, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN7, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN8, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN9, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN10, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN11, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN12, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN13, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN14, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN15, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN16, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN17, converted by group regular only */ +#define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC internal channel connected to VrefInt: Internal + voltage reference, converted by group regular only */ +#define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC internal channel connected to internal temperature sensor, + converted by group regular only */ +#define LL_ADC_AWD_CH_VCORE_REG ((LL_ADC_CHANNEL_VCORE & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC internal channel connected to Vcore, + converted by group regular only */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds + * @{ + */ +#define LL_ADC_AWD_THRESHOLD_HIGH (ADC_AWD1TR_HT1) /*!< ADC analog watchdog threshold high */ +#define LL_ADC_AWD_THRESHOLD_LOW (ADC_AWD1TR_LT1) /*!< ADC analog watchdog threshold low */ +#define LL_ADC_AWD_THRESHOLDS_HIGH_LOW (ADC_AWD1TR_HT1 \ + | ADC_AWD1TR_LT1) /*!< ADC analog watchdog both thresholds high and low + concatenated into the same data */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_OVS_SCOPE Oversampling - Oversampling scope + * @{ + */ +#define LL_ADC_OVS_DISABLE (0x00000000UL) /*!< ADC oversampling disabled. */ +#define LL_ADC_OVS_GRP_REGULAR_CONTINUED (ADC_CFGR2_OVSE) /*!< ADC oversampling on conversions of + ADC group regular. Literal suffix "continued" is kept for compatibility + with other STM32 devices featuring ADC group injected, in this case other + oversampling scope parameters are available. */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode + * @{ + */ +#define LL_ADC_OVS_REG_CONT (0x00000000UL) /*!< ADC oversampling discontinuous mode: continuous mode +(all conversions of oversampling ratio are done from 1 trigger) */ +#define LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TOVS) /*!< ADC oversampling discontinuous mode: discontinuous + mode (each conversion of oversampling ratio needs a trigger) */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_OVS_RATIO Oversampling - Ratio + * @{ + */ +#define LL_ADC_OVS_RATIO_2 (0x00000000UL) /*!< ADC oversampling ratio of 2 + (sum of conversions data computed to result as oversampling conversion data + (before potential shift) */ +#define LL_ADC_OVS_RATIO_4 (ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 4 + (sum of conversions data computed to result as oversampling conversion data + (before potential shift) */ +#define LL_ADC_OVS_RATIO_8 (ADC_CFGR2_OVSR_1) /*!< ADC oversampling ratio of 8 + (sum of conversions data computed to result as oversampling conversion data + (before potential shift) */ +#define LL_ADC_OVS_RATIO_16 (ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 16 + (sum of conversions data computed to result as oversampling conversion data + (before potential shift) */ +#define LL_ADC_OVS_RATIO_32 (ADC_CFGR2_OVSR_2) /*!< ADC oversampling ratio of 32 + (sum of conversions data computed to result as oversampling conversion data + (before potential shift) */ +#define LL_ADC_OVS_RATIO_64 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 64 + (sum of conversions data computed to result as oversampling conversion data + (before potential shift) */ +#define LL_ADC_OVS_RATIO_128 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1) /*!< ADC oversampling ratio of 128 + (sum of conversions data computed to result as oversampling conversion data + (before potential shift) */ +#define LL_ADC_OVS_RATIO_256 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 \ + | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 256 + (sum of conversions data computed to result as oversampling conversion data + (before potential shift) */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_OVS_SHIFT Oversampling - Data right shift + * @{ + */ +#define LL_ADC_OVS_SHIFT_NONE (0x00000000UL) /*!< ADC oversampling no shift + (sum of the ADC conversions data is not divided to result as oversampling + conversion data) */ +#define LL_ADC_OVS_SHIFT_RIGHT_1 (ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 1 + (sum of the ADC conversions data (after OVS ratio) is divided by 2 + to result as oversampling conversion data) */ +#define LL_ADC_OVS_SHIFT_RIGHT_2 (ADC_CFGR2_OVSS_1) /*!< ADC oversampling right shift of 2 + (sum of the ADC conversions data (after OVS ratio) is divided by 4 + to result as oversampling conversion data) */ +#define LL_ADC_OVS_SHIFT_RIGHT_3 (ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 3 + (sum of the ADC conversions data (after OVS ratio) is divided by 8 + to result as oversampling conversion data) */ +#define LL_ADC_OVS_SHIFT_RIGHT_4 (ADC_CFGR2_OVSS_2) /*!< ADC oversampling right shift of 4 + (sum of the ADC conversions data (after OVS ratio) is divided by 16 + to result as oversampling conversion data) */ +#define LL_ADC_OVS_SHIFT_RIGHT_5 (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 5 + (sum of the ADC conversions data (after OVS ratio) is divided by 32 + to result as oversampling conversion data) */ +#define LL_ADC_OVS_SHIFT_RIGHT_6 (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1) /*!< ADC oversampling right shift of 6 + (sum of the ADC conversions data (after OVS ratio) is divided by 64 + to result as oversampling conversion data) */ +#define LL_ADC_OVS_SHIFT_RIGHT_7 (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 \ + | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 7 + (sum of the ADC conversions data (after OVS ratio) is divided by 128 + to result as oversampling conversion data) */ +#define LL_ADC_OVS_SHIFT_RIGHT_8 (ADC_CFGR2_OVSS_3) /*!< ADC oversampling right shift of 8 + (sum of the ADC conversions data (after OVS ratio) is divided by 256 + to result as oversampling conversion data) */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_HELPER_MACRO Definitions of constants used by helper macro + * @{ + */ +#define LL_ADC_TEMPERATURE_CALC_ERROR ((int16_t)0x7FFF) /* Temperature calculation error using helper macro + @ref __LL_ADC_CALC_TEMPERATURE(), due to issue on + calibration parameters. This value is coded on 16 bits + (to fit on signed word or double word) and corresponds + to an inconsistent temperature value. */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays + * @note Only ADC peripheral HW delays are defined in ADC LL driver driver, + * not timeout values. + * For details on delays values, refer to descriptions in source code + * above each literal definition. + * @{ + */ + +/* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */ +/* not timeout values. */ +/* Timeout values for ADC operations are dependent to device clock */ +/* configuration (system clock versus ADC clock), */ +/* and therefore must be defined in user application. */ +/* Indications for estimation of ADC timeout delays, for this */ +/* STM32 series: */ +/* - ADC calibration time: maximum delay is 82/fADC. */ +/* (refer to device datasheet, parameter "tCAL") */ +/* - ADC enable time: maximum delay is 1 conversion cycle. */ +/* (refer to device datasheet, parameter "tSTAB") */ +/* - ADC disable time: maximum delay should be a few ADC clock cycles */ +/* - ADC stop conversion time: maximum delay should be a few ADC clock */ +/* cycles */ +/* - ADC conversion time: duration depending on ADC clock and ADC */ +/* configuration. */ +/* (refer to device reference manual, section "Timing") */ + +/* Delay for ADC stabilization time (ADC voltage regulator start-up time) */ +/* Delay set to maximum value (refer to device datasheet, */ +/* parameter "tADCVREG_STUP"). */ +/* Unit: us */ +#define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 20UL) /*!< Delay for ADC stabilization time (ADC voltage + regulator start-up time) */ + +/* Delay for internal voltage reference stabilization time. */ +/* Delay set to maximum value (refer to device datasheet, */ +/* parameter "tstart_vrefint"). */ +/* Unit: us */ +#define LL_ADC_DELAY_VREFINT_STAB_US ( 12UL) /*!< Delay for internal voltage reference stabilization + time */ + +/* Delay for temperature sensor stabilization time. */ +/* Literal set to maximum value (refer to device datasheet, */ +/* parameter "tSTART"). */ +/* Unit: us */ +#define LL_ADC_DELAY_TEMPSENSOR_STAB_US (120UL) /*!< Delay for temperature sensor stabilization time + (starting from temperature sensor enable, refer to + @ref LL_ADC_SetCommonPathInternalCh()) */ +#define LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US ( 15UL) /*!< Delay for temperature sensor buffer stabilization + time (starting from ADC enable, refer to + @ref LL_ADC_Enable()) */ + +/* Delay required between ADC end of calibration and ADC enable. */ +/* Note: On this STM32 series, a minimum number of ADC clock cycles */ +/* are required between ADC end of calibration and ADC enable. */ +/* Wait time can be computed in user application by waiting for the */ +/* equivalent number of CPU cycles, by taking into account */ +/* ratio of CPU clock versus ADC clock prescalers. */ +/* Unit: ADC clock cycles. */ +#define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 2UL) /*!< Delay required between ADC end of calibration + and ADC enable */ + +/** + * @} + */ + +/** + * @} + */ + + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup ADC_LL_Exported_Macros ADC Exported Macros + * @{ + */ + +/** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in ADC register + * @param __INSTANCE__ ADC Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in ADC register + * @param __INSTANCE__ ADC Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro + * @{ + */ + +/** + * @brief Helper macro to get ADC channel number in decimal format + * from literals LL_ADC_CHANNEL_x. + * @note Example: + * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4) + * will return decimal number "4". + * @note The input can be a value from functions where a channel + * number is returned, either defined with number + * or with bitfield (only one bit must be set). + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_VREFINT + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR + * @arg @ref LL_ADC_CHANNEL_VCORE + * @retval Value between Min_Data=0 and Max_Data=18 + */ +#define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ + ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) ? \ + ( \ + ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \ + ) \ + : \ + ( \ + (uint32_t)POSITION_VAL((__CHANNEL__)) \ + ) \ + ) + +/** + * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x + * from number in decimal format. + * @note Example: + * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4) + * will return a data equivalent to "LL_ADC_CHANNEL_4". + * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18 + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) + * @arg @ref LL_ADC_CHANNEL_VCORE (1) + * + * (1) For ADC channel read back from ADC register, + * comparison with internal channel parameter to be done + * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). + */ +#define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ + (((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ + (ADC_CHSELR_CHSEL0 << (__DECIMAL_NB__))) + +/** + * @brief Helper macro to determine whether the selected channel + * corresponds to literal definitions of driver. + * @note The different literal definitions of ADC channels are: + * - ADC internal channel: + * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ... + * - ADC external channel (channel connected to a GPIO pin): + * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ... + * @note The channel parameter must be a value defined from literal + * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, + * LL_ADC_CHANNEL_TEMPSENSOR, ...), + * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...), + * must not be a value from functions where a channel number is + * returned from ADC registers, + * because internal and external channels share the same channel + * number in ADC registers. The differentiation is made only with + * parameters definitions of driver. + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_VREFINT + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR + * @arg @ref LL_ADC_CHANNEL_VCORE + * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel + connected to a GPIO pin). + * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel. + */ +#define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \ + (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL) + +/** + * @brief Helper macro to convert a channel defined from parameter + * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, + * LL_ADC_CHANNEL_TEMPSENSOR, ...), + * to its equivalent parameter definition of a ADC external channel + * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...). + * @note The channel parameter can be, additionally to a value + * defined from parameter definition of a ADC internal channel + * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...), + * a value defined from parameter definition of + * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...) + * or a value from functions where a channel number is returned + * from ADC registers. + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_VREFINT + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR + * @arg @ref LL_ADC_CHANNEL_VCORE + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + */ +#define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \ + ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK) + +/** + * @brief Helper macro to determine whether the internal channel + * selected is available on the ADC instance selected. + * @note The channel parameter must be a value defined from parameter + * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, + * LL_ADC_CHANNEL_TEMPSENSOR, ...), + * must not be a value defined from parameter definition of + * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...) + * or a value from functions where a channel number is + * returned from ADC registers, + * because internal and external channels share the same channel + * number in ADC registers. The differentiation is made only with + * parameters definitions of driver. + * @param __ADC_INSTANCE__ ADC instance + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_VREFINT + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR + * @arg @ref LL_ADC_CHANNEL_VCORE + * @retval Value "0" if the internal channel selected is not available on the ADC instance selected. + * Value "1" if the internal channel selected is available on the ADC instance selected. + */ +#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ + (((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \ + ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \ + ((__CHANNEL__) == LL_ADC_CHANNEL_VCORE)) + +/** + * @brief Helper macro to define ADC analog watchdog parameter: + * define a single channel to monitor with analog watchdog + * from sequencer channel and groups definition. + * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels(). + * Example: + * LL_ADC_SetAnalogWDMonitChannels( + * ADC1, LL_ADC_AWD1, + * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR)) + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) + * @arg @ref LL_ADC_CHANNEL_VCORE (1) + * + * (1) For ADC channel read back from ADC register, + * comparison with internal channel parameter to be done + * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). + * @param __GROUP__ This parameter can be one of the following values: + * @arg @ref LL_ADC_GROUP_REGULAR + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_AWD_DISABLE + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG + * @arg @ref LL_ADC_AWD_CHANNEL_0_REG + * @arg @ref LL_ADC_AWD_CHANNEL_1_REG + * @arg @ref LL_ADC_AWD_CHANNEL_2_REG + * @arg @ref LL_ADC_AWD_CHANNEL_3_REG + * @arg @ref LL_ADC_AWD_CHANNEL_4_REG + * @arg @ref LL_ADC_AWD_CHANNEL_5_REG + * @arg @ref LL_ADC_AWD_CHANNEL_6_REG + * @arg @ref LL_ADC_AWD_CHANNEL_7_REG + * @arg @ref LL_ADC_AWD_CHANNEL_10_REG + * @arg @ref LL_ADC_AWD_CHANNEL_11_REG + * @arg @ref LL_ADC_AWD_CHANNEL_12_REG + * @arg @ref LL_ADC_AWD_CHANNEL_13_REG + * @arg @ref LL_ADC_AWD_CH_VREFINT_REG + * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG + * @arg @ref LL_ADC_AWD_CH_VCORE_REG + */ +#define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \ + (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) + +/** + * @brief Helper macro to set the value of ADC analog watchdog threshold high + * or low in function of ADC resolution, when ADC resolution is + * different of 12 bits. + * @note To be used with function @ref LL_ADC_ConfigAnalogWDThresholds() + * or @ref LL_ADC_SetAnalogWDThresholds(). + * Example, with a ADC resolution of 8 bits, to set the value of + * analog watchdog threshold high (on 8 bits): + * LL_ADC_SetAnalogWDThresholds + * (< ADCx param >, + * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, ) + * ); + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF + */ +#define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \ + ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_Pos - 1U ))) + +/** + * @brief Helper macro to get the value of ADC analog watchdog threshold high + * or low in function of ADC resolution, when ADC resolution is + * different of 12 bits. + * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds(). + * Example, with a ADC resolution of 8 bits, to get the value of + * analog watchdog threshold high (on 8 bits): + * < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION + * (LL_ADC_RESOLUTION_8B, + * LL_ADC_GetAnalogWDThresholds(, LL_ADC_AWD_THRESHOLD_HIGH) + * ); + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF + */ +#define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \ + ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_Pos - 1U ))) + +/** + * @brief Helper macro to get the ADC analog watchdog threshold high + * or low from raw value containing both thresholds concatenated. + * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds(). + * Example, to get analog watchdog threshold high from the register raw value: + * __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(LL_ADC_AWD_THRESHOLD_HIGH, ); + * @param __AWD_THRESHOLD_TYPE__ This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH + * @arg @ref LL_ADC_AWD_THRESHOLD_LOW + * @param __AWD_THRESHOLDS__ Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF + */ +#define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__) \ + (((__AWD_THRESHOLDS__) >> (((__AWD_THRESHOLD_TYPE__) & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)) \ + & LL_ADC_AWD_THRESHOLD_LOW) + +/** + * @brief Helper macro to select the ADC common instance + * to which is belonging the selected ADC instance. + * @note ADC common register instance can be used for: + * - Set parameters common to several ADC instances + * - Multimode (for devices with several ADC instances) + * Refer to functions having argument "ADCxy_COMMON" as parameter. + * @param __ADCx__ ADC instance + * @retval ADC common register instance + */ +#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \ + (ADC4_COMMON) + +/** + * @brief Helper macro to check if all ADC instances sharing the same + * ADC common instance are disabled. + * @note This check is required by functions with setting conditioned to + * ADC state: + * All ADC instances of the ADC common group must be disabled. + * Refer to functions having argument "ADCxy_COMMON" as parameter. + * @note On devices with only 1 ADC common instance, parameter of this macro + * is useless and can be ignored (parameter kept for compatibility + * with devices featuring several ADC common instances). + * @param __ADCXY_COMMON__ ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval Value "0" if all ADC instances sharing the same ADC common instance + * are disabled. + * Value "1" if at least one ADC instance sharing the same ADC common instance + * is enabled. + */ +#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ + LL_ADC_IsEnabled(ADC4) + +/** + * @brief Helper macro to define the ADC conversion data full-scale digital + * value corresponding to the selected ADC resolution. + * @note ADC conversion data full-scale corresponds to voltage range + * determined by analog voltage references Vref+ and Vref- + * (refer to reference manual). + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @retval ADC conversion data full-scale digital value (unit: digital value of ADC conversion data) + */ +#define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ + (0xFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_Pos - 1UL))) + +/** + * @brief Helper macro to convert the ADC conversion data from + * a resolution to another resolution. + * @param __DATA__ ADC conversion data to be converted + * @param __ADC_RESOLUTION_CURRENT__ Resolution of the data to be converted + * This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion + * This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @retval ADC conversion data to the requested resolution + */ +#define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\ + __ADC_RESOLUTION_CURRENT__,\ + __ADC_RESOLUTION_TARGET__) \ +(((__DATA__) \ + << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR1_RES_Pos - 1UL))) \ + >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR1_RES_Pos - 1UL)) \ +) + +/** + * @brief Helper macro to calculate the voltage (unit: mVolt) + * corresponding to a ADC conversion data (unit: digital value). + * @note Analog reference voltage (Vref+) must be either known from + * user board environment or can be calculated using ADC measurement + * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). + * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) + * @param __ADC_DATA__ ADC conversion data (resolution 12 bits) + * (unit: digital value). + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @retval ADC conversion data equivalent voltage value (unit: mVolt) + */ +#define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ + __ADC_DATA__,\ + __ADC_RESOLUTION__) \ +((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \ + / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ +) + +/** + * @brief Helper macro to calculate analog reference voltage (Vref+) + * (unit: mVolt) from ADC conversion data of internal voltage + * reference VrefInt. + * @note Computation is using VrefInt calibration value + * stored in system memory for each device during production. + * @note This voltage depends on user board environment: voltage level + * connected to pin Vref+. + * On devices with small package, the pin Vref+ is not present + * and internally bonded to pin Vdda. + * @note On this STM32 series, calibration data of internal voltage reference + * VrefInt corresponds to a resolution of 12 bits, + * this is the recommended ADC resolution to convert voltage of + * internal voltage reference VrefInt. + * Otherwise, this macro performs the processing to scale + * ADC conversion data to 12 bits. + * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits) + * of internal voltage reference VrefInt (unit: digital value). + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @retval Analog reference voltage (unit: mV) + */ +#define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\ + __ADC_RESOLUTION__) \ +(((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \ + / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \ + (__ADC_RESOLUTION__), \ + LL_ADC_RESOLUTION_12B) \ +) + +/** + * @brief Helper macro to calculate the temperature (unit: degree Celsius) + * from ADC conversion data of internal temperature sensor. + * @note Computation is using temperature sensor calibration values + * stored in system memory for each device during production. + * @note Calculation formula: + * Temperature = ((TS_ADC_DATA - TS_CAL1) + * * (TS_CAL2_TEMP - TS_CAL1_TEMP)) + * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP + * with TS_ADC_DATA = temperature sensor raw data measured by ADC + * Avg_Slope = (TS_CAL2 - TS_CAL1) + * / (TS_CAL2_TEMP - TS_CAL1_TEMP) + * TS_CAL1 = equivalent TS_ADC_DATA at temperature + * TEMP_DEGC_CAL1 (calibrated in factory) + * TS_CAL2 = equivalent TS_ADC_DATA at temperature + * TEMP_DEGC_CAL2 (calibrated in factory) + * Caution: Calculation relevancy under reserve that calibration + * parameters are correct (address and data). + * To calculate temperature using temperature sensor + * datasheet typical values (generic values less, therefore + * less accurate than calibrated values), + * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(). + * @note As calculation input, the analog reference voltage (Vref+) must be + * defined as it impacts the ADC LSB equivalent voltage. + * @note Analog reference voltage (Vref+) must be either known from + * user board environment or can be calculated using ADC measurement + * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). + * @note On this STM32 series, calibration data of temperature sensor + * corresponds to a resolution of 12 bits, + * this is the recommended ADC resolution to convert voltage of + * temperature sensor. + * Otherwise, this macro performs the processing to scale + * ADC conversion data to 12 bits. + * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) + * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal + * temperature sensor (unit: digital value). + * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature + * sensor voltage has been measured. + * This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @retval Temperature (unit: degree Celsius) + * In case or error, value LL_ADC_TEMPERATURE_CALC_ERROR is returned (inconsistent temperature value) + */ +#define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\ + __TEMPSENSOR_ADC_DATA__,\ + __ADC_RESOLUTION__)\ +((((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) != 0) ? \ + (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \ + (__ADC_RESOLUTION__), \ + LL_ADC_RESOLUTION_12B) \ + * (__VREFANALOG_VOLTAGE__)) \ + / TEMPSENSOR_CAL_VREFANALOG) \ + - (int32_t) *TEMPSENSOR_CAL1_ADDR) \ + ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \ + ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \ + ) + TEMPSENSOR_CAL1_TEMP \ + ) \ + : \ + ((int32_t)LL_ADC_TEMPERATURE_CALC_ERROR) \ +) + +/** + * @brief Helper macro to calculate the temperature (unit: degree Celsius) + * from ADC conversion data of internal temperature sensor. + * @note Computation is using temperature sensor typical values + * (refer to device datasheet). + * @note Calculation formula: + * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV) + * / Avg_Slope + CALx_TEMP + * with TS_ADC_DATA = temperature sensor raw data measured by ADC + * (unit: digital value) + * Avg_Slope = temperature sensor slope + * (unit: uV/Degree Celsius) + * TS_TYP_CALx_VOLT = temperature sensor digital value at + * temperature CALx_TEMP (unit: mV) + * Caution: Calculation relevancy under reserve the temperature sensor + * of the current device has characteristics in line with + * datasheet typical values. + * If temperature sensor calibration values are available on + * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()), + * temperature calculation will be more accurate using + * helper macro @ref __LL_ADC_CALC_TEMPERATURE(). + * @note As calculation input, the analog reference voltage (Vref+) must be + * defined as it impacts the ADC LSB equivalent voltage. + * @note Analog reference voltage (Vref+) must be either known from + * user board environment or can be calculated using ADC measurement + * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). + * @note ADC measurement data must correspond to a resolution of 12 bits + * (full scale digital value 4095). If not the case, the data must be + * preliminarily rescaled to an equivalent resolution of 12 bits. + * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value + (unit: uV/DegCelsius). + * On this STM32 series, refer to device datasheet parameter "Avg_Slope". + * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value + (at temperature and Vref+ defined in parameters below) (unit: mV). + * On this STM32 series, refer to datasheet parameter "V30" (corresponding + * to TS_CAL1). + * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage + (see parameter above) is corresponding (unit: mV) + * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) value (unit: mV) + * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value). + * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. + * This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @retval Temperature (unit: degree Celsius) + */ +#define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\ + __TEMPSENSOR_TYP_CALX_V__,\ + __TEMPSENSOR_CALX_TEMP__,\ + __VREFANALOG_VOLTAGE__,\ + __TEMPSENSOR_ADC_DATA__,\ + __ADC_RESOLUTION__) \ +(((((int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \ + / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \ + * 1000UL) \ + - \ + (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \ + * 1000UL) \ + ) \ + ) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__) \ + ) + (int32_t)(__TEMPSENSOR_CALX_TEMP__) \ +) + +/** + * @} + */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup ADC_LL_Exported_Functions ADC Exported Functions + * @{ + */ + +/** @defgroup ADC_LL_EF_DMA_Management ADC DMA management + * @{ + */ +/* Note: LL ADC functions to set DMA transfer are located into sections of */ +/* configuration of ADC instance, groups and multimode (if available): */ +/* @ref LL_ADC_REG_SetDMATransfer(), ... */ + +/** + * @brief Function to help to configure DMA transfer from ADC: retrieve the + * ADC register address from ADC instance and a list of ADC registers + * intended to be used (most commonly) with DMA transfer. + * @note These ADC registers are data registers: + * when ADC conversion data is available in ADC data registers, + * ADC generates a DMA transfer request. + * @note This macro is intended to be used with LL DMA driver, refer to + * function "LL_DMA_ConfigAddresses()". + * Example: + * LL_DMA_ConfigAddresses(DMA1, + * LL_DMA_CHANNEL_1, + * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA), + * (uint32_t)&< array or variable >, + * LL_DMA_DIRECTION_PERIPH_TO_MEMORY); + * @note For devices with several ADC: in multimode, some devices + * use a different data register outside of ADC instance scope + * (common data register). This macro manages this register difference, + * only ADC instance has to be set as parameter. + * @rmtoll DR DATA LL_ADC_DMA_GetRegAddr + * @param ADCx ADC instance + * @param Register This parameter can be one of the following values: + * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA + * @retval ADC register address + */ +__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(const ADC_TypeDef *ADCx, uint32_t Register) +{ + /* Prevent unused argument(s) compilation warning */ + (void)(Register); + + /* Retrieve address of register DR */ + return (uint32_t) &(ADCx->DR); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several + * ADC instances + * @{ + */ + +/** + * @brief Set parameter common to several ADC: Clock source and prescaler. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * All ADC instances of the ADC common group must be disabled. + * This check can be done with function @ref LL_ADC_IsEnabled() for each + * ADC instance or by using helper macro helper macro + * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(). + * @rmtoll CCR PRESC LL_ADC_SetCommonClock + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @param CommonClock This parameter can be one of the following values: + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1 (1) + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2 (1) + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4 (1) + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6 (1) + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8 (1) + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10 (1) + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12 (1) + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16 (1) + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32 (1) + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64 (1) + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128 (1) + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256 (1) + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock) +{ + MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_PRESC, CommonClock); +} + +/** + * @brief Get parameter common to several ADC: Clock source and prescaler. + * @rmtoll CCR PRESC LL_ADC_GetCommonClock + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1 (1) + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2 (1) + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4 (1) + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6 (1) + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8 (1) + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10 (1) + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12 (1) + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16 (1) + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32 (1) + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64 (1) + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128 (1) + * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256 (1) + */ +__STATIC_INLINE uint32_t LL_ADC_GetCommonClock(const ADC_Common_TypeDef *ADCxy_COMMON) +{ + return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_PRESC)); +} + +/** + * @brief Set parameter common to several ADC: measurement path to + * internal channels (VrefInt, temperature sensor, ...). + * Configure all paths (overwrite current configuration). + * @note One or several values can be selected. + * Example: (LL_ADC_PATH_INTERNAL_VREFINT | + * LL_ADC_PATH_INTERNAL_TEMPSENSOR) + * The values not selected are removed from configuration. + * @note Stabilization time of measurement path to internal channel: + * After enabling internal paths, before starting ADC conversion, + * a delay is required for internal voltage reference and + * temperature sensor stabilization time. + * Refer to device datasheet. + * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US. + * Refer to literals @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US, + * @ref LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US. + * @note ADC internal channel sampling time constraint: + * For ADC conversion of internal channels, + * a sampling time minimum value is required. + * Refer to device datasheet. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * All ADC instances of the ADC common group must be disabled. + * This check can be done with function @ref LL_ADC_IsEnabled() for each + * ADC instance or by using helper macro helper macro + * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(). + * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalCh\n + * CCR TSEN LL_ADC_SetCommonPathInternalCh + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @param PathInternal This parameter can be a combination of the following values: + * @arg @ref LL_ADC_PATH_INTERNAL_NONE + * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT + * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal) +{ + MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN, PathInternal); +} + +/** + * @brief Set parameter common to several ADC: measurement path to + * internal channels (VrefInt, temperature sensor, ...). + * Add paths to the current configuration. + * @note One or several values can be selected. + * Example: (LL_ADC_PATH_INTERNAL_VREFINT | + * LL_ADC_PATH_INTERNAL_TEMPSENSOR) + * @note Stabilization time of measurement path to internal channel: + * After enabling internal paths, before starting ADC conversion, + * a delay is required for internal voltage reference and + * temperature sensor stabilization time. + * Refer to device datasheet. + * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US. + * Refer to literals @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US, + * @ref LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US. + * @note ADC internal channel sampling time constraint: + * For ADC conversion of internal channels, + * a sampling time minimum value is required. + * Refer to device datasheet. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * All ADC instances of the ADC common group must be disabled. + * This check can be done with function @ref LL_ADC_IsEnabled() for each + * ADC instance or by using helper macro helper macro + * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(). + * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalCh\n + * CCR TSEN LL_ADC_SetCommonPathInternalCh + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @param PathInternal This parameter can be a combination of the following values: + * @arg @ref LL_ADC_PATH_INTERNAL_NONE + * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT + * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal) +{ + SET_BIT(ADCxy_COMMON->CCR, PathInternal); +} + +/** + * @brief Set parameter common to several ADC: measurement path to + * internal channels (VrefInt, temperature sensor, ...). + * Remove paths to the current configuration. + * @note One or several values can be selected. + * Example: (LL_ADC_PATH_INTERNAL_VREFINT | + * LL_ADC_PATH_INTERNAL_TEMPSENSOR) + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * All ADC instances of the ADC common group must be disabled. + * This check can be done with function @ref LL_ADC_IsEnabled() for each + * ADC instance or by using helper macro helper macro + * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(). + * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChRem\n + * CCR TSEN LL_ADC_SetCommonPathInternalChRem + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @param PathInternal This parameter can be a combination of the following values: + * @arg @ref LL_ADC_PATH_INTERNAL_NONE + * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT + * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal) +{ + CLEAR_BIT(ADCxy_COMMON->CCR, PathInternal); +} + +/** + * @brief Get parameter common to several ADC: measurement path to internal + * channels (VrefInt, temperature sensor, ...). + * @note One or several values can be selected. + * Example: (LL_ADC_PATH_INTERNAL_VREFINT | + * LL_ADC_PATH_INTERNAL_TEMPSENSOR) + * @rmtoll CCR VREFEN LL_ADC_GetCommonPathInternalCh\n + * CCR TSEN LL_ADC_GetCommonPathInternalCh + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval Returned value can be a combination of the following values: + * @arg @ref LL_ADC_PATH_INTERNAL_NONE + * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT + * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR + */ +__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(const ADC_Common_TypeDef *ADCxy_COMMON) +{ + return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN)); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance + * @{ + */ + +/** + * @brief Set ADC calibration factor in the mode single-ended + * or differential (for devices with differential mode available). + * @note This function is intended to set calibration parameters + * without having to perform a new calibration using + * @ref LL_ADC_StartCalibration(). + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be enabled, without calibration on going, without conversion + * on going on group regular. + * @rmtoll CALFACT CALFACT LL_ADC_SetCalibrationFactor + * @param ADCx ADC instance + * @param CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t CalibrationFactor) +{ + MODIFY_REG(ADCx->CALFACT, + ADC_CALFACT_CALFACT, + CalibrationFactor); +} + +/** + * @brief Get ADC calibration factor in the mode single-ended + * or differential (for devices with differential mode available). + * @note Calibration factors are set by hardware after performing + * a calibration run using function @ref LL_ADC_StartCalibration(). + * @rmtoll CALFACT CALFACT LL_ADC_GetCalibrationFactor + * @param ADCx ADC instance + * @retval Value between Min_Data=0x00 and Max_Data=0x7F + */ +__STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(const ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT)); +} + +/** + * @brief Set ADC resolution. + * Refer to reference manual for alignments formats + * dependencies to ADC resolutions. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @rmtoll CFGR1 RES LL_ADC_SetResolution + * @param ADCx ADC instance + * @param Resolution This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution) +{ + MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_RES, Resolution); +} + +/** + * @brief Get ADC resolution. + * Refer to reference manual for alignments formats + * dependencies to ADC resolutions. + * @rmtoll CFGR1 RES LL_ADC_GetResolution + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + */ +__STATIC_INLINE uint32_t LL_ADC_GetResolution(const ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_RES)); +} + +/** + * @brief Set ADC conversion data alignment. + * @note Refer to reference manual for alignments formats + * dependencies to ADC resolutions. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @rmtoll CFGR1 ALIGN LL_ADC_SetDataAlignment + * @param ADCx ADC instance + * @param DataAlignment This parameter can be one of the following values: + * @arg @ref LL_ADC_DATA_ALIGN_RIGHT + * @arg @ref LL_ADC_DATA_ALIGN_LEFT + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment) +{ + MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_ALIGN, DataAlignment); +} + +/** + * @brief Get ADC conversion data alignment. + * @note Refer to reference manual for alignments formats + * dependencies to ADC resolutions. + * @rmtoll CFGR1 ALIGN LL_ADC_GetDataAlignment + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_DATA_ALIGN_RIGHT + * @arg @ref LL_ADC_DATA_ALIGN_LEFT + */ +__STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(const ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_ALIGN)); +} + +/** + * @brief Set ADC low power mode. + * @note Description of ADC low power modes: + * - ADC low power mode "auto wait": Dynamic low power mode, + * ADC conversions occurrences are limited to the minimum necessary + * in order to reduce power consumption. + * New ADC conversion starts only when the previous + * unitary conversion data (for ADC group regular) + * has been retrieved by user software. + * In the meantime, ADC remains idle: does not performs any + * other conversion. + * This mode allows to automatically adapt the ADC conversions + * triggers to the speed of the software that reads the data. + * Moreover, this avoids risk of overrun for low frequency + * applications. + * How to use this low power mode: + * - It is not recommended to use with interruption or DMA + * since these modes have to clear immediately the EOC flag + * (by CPU to free the IRQ pending event or by DMA). + * Auto wait will work but fort a very short time, discarding + * its intended benefit (except specific case of high load of CPU + * or DMA transfers which can justify usage of auto wait). + * - Do use with polling: 1. Start conversion, + * 2. Later on, when conversion data is needed: poll for end of + * conversion to ensure that conversion is completed and + * retrieve ADC conversion data. This will trig another + * ADC conversion start. + * @note With ADC low power mode "auto wait", the ADC conversion data read + * is corresponding to previous ADC conversion start, independently + * of delay during which ADC was idle. + * Therefore, the ADC conversion data may be outdated: does not + * correspond to the current voltage level on the selected + * ADC channel. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @rmtoll CFGR WAIT LL_ADC_SetLPModeAutoWait + * @param ADCx ADC instance + * @param LowPowerMode This parameter can be one of the following values: + * @arg @ref LL_ADC_LP_AUTOWAIT_DISABLE + * @arg @ref LL_ADC_LP_AUTOWAIT_ENABLE + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetLPModeAutoWait(ADC_TypeDef *ADCx, uint32_t LowPowerMode) +{ + MODIFY_REG(ADCx->CFGR1, (ADC_CFGR1_WAIT), LowPowerMode); +} + +/** + * @brief Get ADC low power mode: + * @note Description of ADC low power modes: + * - ADC low power mode "auto wait": Dynamic low power mode, + * ADC conversions occurrences are limited to the minimum necessary + * in order to reduce power consumption. + * New ADC conversion starts only when the previous + * unitary conversion data (for ADC group regular) + * has been retrieved by user software. + * In the meantime, ADC remains idle: does not performs any + * other conversion. + * This mode allows to automatically adapt the ADC conversions + * triggers to the speed of the software that reads the data. + * Moreover, this avoids risk of overrun for low frequency + * applications. + * How to use this low power mode: + * - It is not recommended to use with interruption or DMA + * since these modes have to clear immediately the EOC flag + * (by CPU to free the IRQ pending event or by DMA). + * Auto wait will work but fort a very short time, discarding + * its intended benefit (except specific case of high load of CPU + * or DMA transfers which can justify usage of auto wait). + * - Do use with polling: 1. Start conversion, + * 2. Later on, when conversion data is needed: poll for end of + * conversion to ensure that conversion is completed and + * retrieve ADC conversion data. This will trig another + * ADC conversion start. + * @note With ADC low power mode "auto wait", the ADC conversion data read + * is corresponding to previous ADC conversion start, independently + * of delay during which ADC was idle. + * Therefore, the ADC conversion data may be outdated: does not + * correspond to the current voltage level on the selected + * ADC channel. + * @rmtoll CFGR WAIT LL_ADC_GetLPModeAutoWait + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_LP_AUTOWAIT_DISABLE + * @arg @ref LL_ADC_LP_AUTOWAIT_ENABLE + */ +__STATIC_INLINE uint32_t LL_ADC_GetLPModeAutoWait(const ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_WAIT)); +} + +/* Definitions for backward compatibility with legacy STM32 series */ +#define LL_ADC_SetLowPowerMode LL_ADC_SetLPModeAutoWait /* Redefinition for legacy purpose */ +#define LL_ADC_GetLowPowerMode LL_ADC_GetLPModeAutoWait /* Redefinition for legacy purpose */ + +/** + * @brief Set ADC low power mode: auto power off. + * @note Description of ADC low power mode: + * - ADC low power mode "auto power-off": + * the ADC automatically powers-off after a conversion and + * automatically wakes up when a new conversion is triggered + * (with startup time between trigger and start of sampling). + * This feature can be combined with low power mode "auto wait". + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled. + * @rmtoll PWRR AUTOFF LL_ADC_SetLPModeAutoPowerOff + * @param ADCx ADC instance + * @param LowPowerMode This parameter can be one of the following values: + * @arg @ref LL_ADC_LP_AUTOPOWEROFF_DISABLE + * @arg @ref LL_ADC_LP_AUTOPOWEROFF_ENABLE + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetLPModeAutoPowerOff(ADC_TypeDef *ADCx, uint32_t LowPowerMode) +{ + MODIFY_REG(ADCx->PWRR, ADC_PWRR_AUTOFF, LowPowerMode); +} + +/** + * @brief Get ADC low power mode: auto power off. + * @note Description of ADC low power mode: + * - ADC low power mode "auto power-off": + * the ADC automatically powers-off after a conversion and + * automatically wakes up when a new conversion is triggered + * (with startup time between trigger and start of sampling). + * This feature can be combined with low power mode "auto wait". + * @rmtoll PWRR AUTOFF LL_ADC_GetLPModeAutoPowerOff + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_LP_AUTOPOWEROFF_DISABLE + * @arg @ref LL_ADC_LP_AUTOPOWEROFF_ENABLE + */ +__STATIC_INLINE uint32_t LL_ADC_GetLPModeAutoPowerOff(const ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->PWRR, ADC_PWRR_AUTOFF)); +} + +/** + * @brief Set ADC low power mode: deep power down in autonomous mode + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled. + * @rmtoll PWRR DPD LL_ADC_SetLPModeAutonomousDPD + * @param ADCx ADC instance + * @param LowPowerMode This parameter can be one of the following values: + * @arg @ref LL_ADC_LP_AUTONOMOUS_DPD_DISABLE + * @arg @ref LL_ADC_LP_AUTONOMOUS_DPD_ENABLE + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetLPModeAutonomousDPD(ADC_TypeDef *ADCx, uint32_t LowPowerMode) +{ + MODIFY_REG(ADCx->PWRR, ADC_PWRR_DPD, LowPowerMode); +} + +/** + * @brief Get ADC low power mode: deep power down in autonomous mode + * @rmtoll PWRR DPD LL_ADC_GetLPModeAutonomousDPD + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_LP_AUTONOMOUS_DPD_DISABLE + * @arg @ref LL_ADC_LP_AUTONOMOUS_DPD_ENABLE + */ +__STATIC_INLINE uint32_t LL_ADC_GetLPModeAutonomousDPD(const ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->PWRR, ADC_PWRR_DPD)); +} + + +/** + * @brief Set ADC trigger frequency mode. + * @note ADC trigger frequency mode must be set to low frequency when + * a duration is exceeded before ADC conversion start trigger event + * (between ADC enable and ADC conversion start trigger event + * or between two ADC conversion start trigger event). + * Duration value: Refer to device datasheet, parameter "tIdle". + * @note When ADC trigger frequency mode is set to low frequency, + * some rearm cycles are inserted before performing ADC conversion + * start, inducing a delay of 2 ADC clock cycles. + * @note Usage of ADC trigger frequency mode with ADC low power mode: + * - Low power mode auto wait: Only the first ADC conversion + * start trigger inserts the rearm delay. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled. + * @rmtoll CFGR2 LFTRIG LL_ADC_SetTriggerFrequencyMode + * @param ADCx ADC instance + * @param TriggerFrequencyMode This parameter can be one of the following values: + * @arg @ref LL_ADC_TRIGGER_FREQ_HIGH + * @arg @ref LL_ADC_TRIGGER_FREQ_LOW + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetTriggerFrequencyMode(ADC_TypeDef *ADCx, uint32_t TriggerFrequencyMode) +{ + MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_LFTRIG, TriggerFrequencyMode); +} + +/** + * @brief Get ADC trigger frequency mode. + * @rmtoll CFGR2 LFTRIG LL_ADC_GetTriggerFrequencyMode + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_TRIGGER_FREQ_HIGH + * @arg @ref LL_ADC_TRIGGER_FREQ_LOW + */ +__STATIC_INLINE uint32_t LL_ADC_GetTriggerFrequencyMode(const ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_LFTRIG)); +} + +/** + * @brief Set sampling time common to a group of channels. + * @note Unit: ADC clock cycles. + * @note On this STM32 series, sampling time scope is on ADC instance: + * Sampling time common to all channels. + * (on some other STM32 series, sampling time is channel wise) + * @note In case of internal channel (VrefInt, TempSensor, ...) to be + * converted: + * sampling time constraints must be respected (sampling time can be + * adjusted in function of ADC clock frequency and sampling time + * setting). + * Refer to device datasheet for timings values (parameters TS_vrefint, + * TS_temp, ...). + * @note Conversion time is the addition of sampling time and processing time. + * On this STM32 series, ADC processing time is: + * - 12.5 ADC clock cycles at ADC resolution 12 bits + * - 10.5 ADC clock cycles at ADC resolution 10 bits + * - 8.5 ADC clock cycles at ADC resolution 8 bits + * - 6.5 ADC clock cycles at ADC resolution 6 bits + * @note In case of ADC conversion of internal channel (VrefInt, + * temperature sensor, ...), a sampling time minimum value + * is required. + * Refer to device datasheet. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @rmtoll SMPR SMP1 LL_ADC_SetSamplingTimeCommonChannels\n + * @rmtoll SMPR SMP2 LL_ADC_SetSamplingTimeCommonChannels + * @param ADCx ADC instance + * @param SamplingTimeY This parameter can be one of the following values: + * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1 + * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2 + * @param SamplingTime This parameter can be one of the following values: + * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5 + * @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_19CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_39CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_79CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_814CYCLES_5 + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetSamplingTimeCommonChannels(ADC_TypeDef *ADCx, uint32_t SamplingTimeY, + uint32_t SamplingTime) +{ + MODIFY_REG(ADCx->SMPR, + ADC_SMPR_SMP1 << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK), + SamplingTime << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK)); +} + +/** + * @brief Get sampling time common to a group of channels. + * @note Unit: ADC clock cycles. + * @note On this STM32 series, sampling time scope is on ADC instance: + * Sampling time common to all channels. + * (on some other STM32 series, sampling time is channel wise) + * @note Conversion time is the addition of sampling time and processing time. + * Refer to reference manual for ADC processing time of + * this STM32 series. + * @rmtoll SMPR SMP1 LL_ADC_GetSamplingTimeCommonChannels\n + * @rmtoll SMPR SMP2 LL_ADC_GetSamplingTimeCommonChannels + * @param ADCx ADC instance + * @param SamplingTimeY This parameter can be one of the following values: + * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1 + * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2 + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5 + * @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_19CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_39CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_79CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_814CYCLES_5 + */ +__STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonChannels(const ADC_TypeDef *ADCx, uint32_t SamplingTimeY) +{ + return (uint32_t)((READ_BIT(ADCx->SMPR, ADC_SMPR_SMP1 << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK))) + >> (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK)); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular + * @{ + */ + +/** + * @brief Set ADC group regular conversion trigger source: + * internal (SW start) or from external peripheral (timer event, + * external interrupt line). + * @note On this STM32 series, setting trigger source to external trigger + * also set trigger polarity to rising edge + * (default setting for compatibility with some ADC on other + * STM32 series having this setting set by HW default value). + * In case of need to modify trigger edge, use + * function @ref LL_ADC_REG_SetTriggerEdge(). + * @note On this STM32 series, ADC trigger frequency mode must be set + * in function of frequency of ADC group regular conversion trigger. + * Refer to description of function + * @ref LL_ADC_SetTriggerFrequencyMode(). + * @note Availability of parameters of trigger sources from timer + * depends on timers availability on the selected device. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @rmtoll CFGR1 EXTSEL LL_ADC_REG_SetTriggerSource\n + * CFGR1 EXTEN LL_ADC_REG_SetTriggerSource + * @param ADCx ADC instance + * @param TriggerSource This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_TRIG_SOFTWARE + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH4 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO + * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM1_CH1 + * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE15 + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource) +{ + MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL, TriggerSource); +} + +/** + * @brief Get ADC group regular conversion trigger source: + * internal (SW start) or from external peripheral (timer event, + * external interrupt line). + * @note To determine whether group regular trigger source is + * internal (SW start) or external, without detail + * of which peripheral is selected as external trigger, + * (equivalent to + * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)") + * use function @ref LL_ADC_REG_IsTriggerSourceSWStart. + * @note Availability of parameters of trigger sources from timer + * depends on timers availability on the selected device. + * @rmtoll CFGR1 EXTSEL LL_ADC_REG_GetTriggerSource\n + * CFGR1 EXTEN LL_ADC_REG_GetTriggerSource + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_TRIG_SOFTWARE + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH4 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO + * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM1_CH1 + * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE15 + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(const ADC_TypeDef *ADCx) +{ + __IO uint32_t trigger_source = READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTSEL | ADC_CFGR1_EXTEN); + + /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */ + /* corresponding to ADC_CFGR1_EXTEN {0; 1; 2; 3}. */ + uint32_t shift_exten = ((trigger_source & ADC_CFGR1_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL)); + + /* Set bitfield corresponding to ADC_CFGR1_EXTEN and ADC_CFGR1_EXTSEL */ + /* to match with triggers literals definition. */ + return ((trigger_source + & (ADC_REG_TRIG_SOURCE_MASK >> shift_exten) & ADC_CFGR1_EXTSEL) + | ((ADC_REG_TRIG_EDGE_MASK >> shift_exten) & ADC_CFGR1_EXTEN) + ); +} + +/** + * @brief Get ADC group regular conversion trigger source internal (SW start) + * or external. + * @note In case of group regular trigger source set to external trigger, + * to determine which peripheral is selected as external trigger, + * use function @ref LL_ADC_REG_GetTriggerSource(). + * @rmtoll CFGR1 EXTEN LL_ADC_REG_IsTriggerSourceSWStart + * @param ADCx ADC instance + * @retval Value "0" if trigger source external trigger + * Value "1" if trigger source SW start. + */ +__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN)) ? 1UL : 0UL); +} + +/** + * @brief Set ADC group regular conversion trigger polarity. + * @note Applicable only for trigger source set to external trigger. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @rmtoll CFGR1 EXTEN LL_ADC_REG_SetTriggerEdge + * @param ADCx ADC instance + * @param ExternalTriggerEdge This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_TRIG_EXT_RISING + * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING + * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge) +{ + MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN, ExternalTriggerEdge); +} + +/** + * @brief Get ADC group regular conversion trigger polarity. + * @note Applicable only for trigger source set to external trigger. + * @rmtoll CFGR1 EXTEN LL_ADC_REG_GetTriggerEdge + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_TRIG_EXT_RISING + * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING + * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(const ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN)); +} + +/** + * @brief Set ADC group regular sequencer configuration flexibility. + * @note On this STM32 series, ADC group regular sequencer both modes + * "fully configurable" or "not fully configurable" are + * available: + * - sequencer configured to fully configurable: + * sequencer length and each rank + * affectation to a channel are configurable. + * Refer to description of function + * @ref LL_ADC_REG_SetSequencerLength(). + * - sequencer configured to not fully configurable: + * sequencer length and each rank affectation to a channel + * are fixed by channel HW number. + * Refer to description of function + * @ref LL_ADC_REG_SetSequencerChannels(). + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @rmtoll CFGR CHSELRMOD LL_ADC_REG_SetSequencerConfigurable + * @param ADCx ADC instance + * @param Configurability This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_SEQ_FIXED + * @arg @ref LL_ADC_REG_SEQ_CONFIGURABLE + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetSequencerConfigurable(ADC_TypeDef *ADCx, uint32_t Configurability) +{ + MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_CHSELRMOD, Configurability); +} + +/** + * @brief Get ADC group regular sequencer configuration flexibility. + * @note On this STM32 series, ADC group regular sequencer both modes + * "fully configurable" or "not fully configurable" are + * available: + * - sequencer configured to fully configurable: + * sequencer length and each rank + * affectation to a channel are configurable. + * Refer to description of function + * @ref LL_ADC_REG_SetSequencerLength(). + * - sequencer configured to not fully configurable: + * sequencer length and each rank affectation to a channel + * are fixed by channel HW number. + * Refer to description of function + * @ref LL_ADC_REG_SetSequencerChannels(). + * @rmtoll CFGR CHSELRMOD LL_ADC_REG_SetSequencerConfigurable + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_SEQ_FIXED + * @arg @ref LL_ADC_REG_SEQ_CONFIGURABLE + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerConfigurable(const ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_CHSELRMOD)); +} + +/** + * @brief Set ADC group regular sequencer length and scan direction. + * @note Description of ADC group regular sequencer features: + * - For devices with sequencer fully configurable + * (function "LL_ADC_REG_SetSequencerRanks()" available): + * sequencer length and each rank affectation to a channel + * are configurable. + * This function performs configuration of: + * - Sequence length: Number of ranks in the scan sequence. + * - Sequence direction: Unless specified in parameters, sequencer + * scan direction is forward (from rank 1 to rank n). + * Sequencer ranks are selected using + * function "LL_ADC_REG_SetSequencerRanks()". + * - For devices with sequencer not fully configurable + * (function "LL_ADC_REG_SetSequencerChannels()" available): + * sequencer length and each rank affectation to a channel + * are defined by channel number. + * This function performs configuration of: + * - Sequence length: Number of ranks in the scan sequence is + * defined by number of channels set in the sequence, + * rank of each channel is fixed by channel HW number. + * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). + * - Sequence direction: Unless specified in parameters, sequencer + * scan direction is forward (from lowest channel number to + * highest channel number). + * Sequencer ranks are selected using + * function "LL_ADC_REG_SetSequencerChannels()". + * To set scan direction differently, refer to function + * @ref LL_ADC_REG_SetSequencerScanDirection(). + * @note On this STM32 series, ADC group regular sequencer both modes + * "fully configurable" or "not fully configurable" + * are available, they can be chosen using + * function @ref LL_ADC_REG_SetSequencerConfigurable(). + * @note Sequencer disabled is equivalent to sequencer of 1 rank: + * ADC conversion on only 1 channel. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @rmtoll CHSELR SQ1 LL_ADC_REG_SetSequencerLength\n + * CHSELR SQ2 LL_ADC_REG_SetSequencerLength\n + * CHSELR SQ3 LL_ADC_REG_SetSequencerLength\n + * CHSELR SQ4 LL_ADC_REG_SetSequencerLength\n + * CHSELR SQ5 LL_ADC_REG_SetSequencerLength\n + * CHSELR SQ6 LL_ADC_REG_SetSequencerLength\n + * CHSELR SQ7 LL_ADC_REG_SetSequencerLength\n + * CHSELR SQ8 LL_ADC_REG_SetSequencerLength + * @param ADCx ADC instance + * @param SequencerNbRanks This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks) +{ + SET_BIT(ADCx->CHSELR, SequencerNbRanks); +} + +/** + * @brief Get ADC group regular sequencer length and scan direction. + * @note Description of ADC group regular sequencer features: + * - For devices with sequencer fully configurable + * (function "LL_ADC_REG_SetSequencerRanks()" available): + * sequencer length and each rank affectation to a channel + * are configurable. + * This function retrieves: + * - Sequence length: Number of ranks in the scan sequence. + * - Sequence direction: Unless specified in parameters, sequencer + * scan direction is forward (from rank 1 to rank n). + * Sequencer ranks are selected using + * function "LL_ADC_REG_SetSequencerRanks()". + * - For devices with sequencer not fully configurable + * (function "LL_ADC_REG_SetSequencerChannels()" available): + * sequencer length and each rank affectation to a channel + * are defined by channel number. + * This function retrieves: + * - Sequence length: Number of ranks in the scan sequence is + * defined by number of channels set in the sequence, + * rank of each channel is fixed by channel HW number. + * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). + * - Sequence direction: Unless specified in parameters, sequencer + * scan direction is forward (from lowest channel number to + * highest channel number). + * Sequencer ranks are selected using + * function "LL_ADC_REG_SetSequencerChannels()". + * To set scan direction differently, refer to function + * @ref LL_ADC_REG_SetSequencerScanDirection(). + * @note On this STM32 series, ADC group regular sequencer both modes + * "fully configurable" or "not fully configurable" + * are available, they can be chosen using + * function @ref LL_ADC_REG_SetSequencerConfigurable(). + * @note Sequencer disabled is equivalent to sequencer of 1 rank: + * ADC conversion on only 1 channel. + * @rmtoll CHSELR SQ1 LL_ADC_REG_GetSequencerLength\n + * CHSELR SQ2 LL_ADC_REG_GetSequencerLength\n + * CHSELR SQ3 LL_ADC_REG_GetSequencerLength\n + * CHSELR SQ4 LL_ADC_REG_GetSequencerLength\n + * CHSELR SQ5 LL_ADC_REG_GetSequencerLength\n + * CHSELR SQ6 LL_ADC_REG_GetSequencerLength\n + * CHSELR SQ7 LL_ADC_REG_GetSequencerLength\n + * CHSELR SQ8 LL_ADC_REG_GetSequencerLength + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(const ADC_TypeDef *ADCx) +{ + __IO uint32_t channels_ranks = READ_BIT(ADCx->CHSELR, ADC_CHSELR_SQ_ALL); + uint32_t sequencer_length = LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS; + uint32_t rank_index; + uint32_t rank_shifted; + + /* Parse register for end of sequence identifier */ + /* Note: Value "0xF0UL" corresponds to bitfield of sequencer 2nd rank + (ADC_CHSELR_SQ2), value "4" to length of end of sequence + identifier (0xF) */ + for (rank_index = 0U; rank_index <= (28U - 4U); rank_index += 4U) + { + rank_shifted = (uint32_t)(0xF0UL << rank_index); + if ((channels_ranks & rank_shifted) == rank_shifted) + { + sequencer_length = rank_shifted; + break; + } + } + + return sequencer_length; +} + +/** + * @brief Set ADC group regular sequencer scan direction. + * @note On this STM32 series, parameter relevant only is sequencer is set + * to mode not fully configurable, + * refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). + * @note On some other STM32 series, this setting is not available and + * the default scan direction is forward. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @rmtoll CFGR1 SCANDIR LL_ADC_REG_SetSequencerScanDirection + * @param ADCx ADC instance + * @param ScanDirection This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_FORWARD + * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetSequencerScanDirection(ADC_TypeDef *ADCx, uint32_t ScanDirection) +{ + MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_SCANDIR, ScanDirection); +} + +/** + * @brief Get ADC group regular sequencer scan direction. + * @note On this STM32 series, parameter relevant only is sequencer is set + * to mode not fully configurable, + * refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). + * @note On some other STM32 series, this setting is not available and + * the default scan direction is forward. + * @rmtoll CFGR1 SCANDIR LL_ADC_REG_GetSequencerScanDirection + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_FORWARD + * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerScanDirection(const ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_SCANDIR)); +} + +/** + * @brief Set ADC group regular sequencer discontinuous mode: + * sequence subdivided and scan conversions interrupted every selected + * number of ranks. + * @note It is not possible to enable both ADC group regular + * continuous mode and sequencer discontinuous mode. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @rmtoll CFGR1 DISCEN LL_ADC_REG_SetSequencerDiscont\n + * @param ADCx ADC instance + * @param SeqDiscont This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE + * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont) +{ + MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DISCEN, SeqDiscont); +} + +/** + * @brief Get ADC group regular sequencer discontinuous mode: + * sequence subdivided and scan conversions interrupted every selected + * number of ranks. + * @rmtoll CFGR1 DISCEN LL_ADC_REG_GetSequencerDiscont\n + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE + * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(const ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DISCEN)); +} + +/** + * @brief Set ADC group regular sequence: channel on the selected + * scan sequence rank. + * @note This function performs configuration of: + * - Channels ordering into each rank of scan sequence: + * whatever channel can be placed into whatever rank. + * @note On this STM32 series, ADC group regular sequencer is + * fully configurable: sequencer length and each rank + * affectation to a channel are configurable. + * Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). + * @note Depending on devices and packages, some channels may not be available. + * Refer to device datasheet for channels availability. + * @note On this STM32 series, to measure internal channels (VrefInt, + * TempSensor, ...), measurement paths to internal channels must be + * enabled separately. + * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @rmtoll CHSELR SQ1 LL_ADC_REG_SetSequencerRanks\n + * CHSELR SQ2 LL_ADC_REG_SetSequencerRanks\n + * CHSELR SQ3 LL_ADC_REG_SetSequencerRanks\n + * CHSELR SQ4 LL_ADC_REG_SetSequencerRanks\n + * CHSELR SQ5 LL_ADC_REG_SetSequencerRanks\n + * CHSELR SQ6 LL_ADC_REG_SetSequencerRanks\n + * CHSELR SQ7 LL_ADC_REG_SetSequencerRanks\n + * CHSELR SQ8 LL_ADC_REG_SetSequencerRanks + * @param ADCx ADC instance + * @param Rank This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_RANK_1 + * @arg @ref LL_ADC_REG_RANK_2 + * @arg @ref LL_ADC_REG_RANK_3 + * @arg @ref LL_ADC_REG_RANK_4 + * @arg @ref LL_ADC_REG_RANK_5 + * @arg @ref LL_ADC_REG_RANK_6 + * @arg @ref LL_ADC_REG_RANK_7 + * @arg @ref LL_ADC_REG_RANK_8 + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_VREFINT + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR + * @arg @ref LL_ADC_CHANNEL_VCORE + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel) +{ + /* Set bits with content of parameter "Channel" with bits position */ + /* in register depending on parameter "Rank". */ + /* Parameters "Rank" and "Channel" are used with masks because containing */ + /* other bits reserved for other purpose. */ + MODIFY_REG(ADCx->CHSELR, + ADC_CHSELR_SQ1 << (Rank & ADC_REG_RANK_ID_SQRX_MASK), + ((Channel & ADC_CHANNEL_ID_NUMBER_MASK_SEQ) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) + << (Rank & ADC_REG_RANK_ID_SQRX_MASK)); +} + +/** + * @brief Get ADC group regular sequence: channel on the selected + * scan sequence rank. + * @note On this STM32 series, ADC group regular sequencer is + * fully configurable: sequencer length and each rank + * affectation to a channel are configurable. + * Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). + * @note Depending on devices and packages, some channels may not be available. + * Refer to device datasheet for channels availability. + * @note Usage of the returned channel number: + * - To reinject this channel into another function LL_ADC_xxx: + * the returned channel number is only partly formatted on definition + * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared + * with parts of literals LL_ADC_CHANNEL_x or using + * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). + * Then the selected literal LL_ADC_CHANNEL_x can be used + * as parameter for another function. + * - To get the channel number in decimal format: + * process the returned value with the helper macro + * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). + * @rmtoll CHSELR SQ1 LL_ADC_REG_GetSequencerRanks\n + * CHSELR SQ2 LL_ADC_REG_GetSequencerRanks\n + * CHSELR SQ3 LL_ADC_REG_GetSequencerRanks\n + * CHSELR SQ4 LL_ADC_REG_GetSequencerRanks\n + * CHSELR SQ5 LL_ADC_REG_GetSequencerRanks\n + * CHSELR SQ6 LL_ADC_REG_GetSequencerRanks\n + * CHSELR SQ7 LL_ADC_REG_GetSequencerRanks\n + * CHSELR SQ8 LL_ADC_REG_GetSequencerRanks + * @param ADCx ADC instance + * @param Rank This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_RANK_1 + * @arg @ref LL_ADC_REG_RANK_2 + * @arg @ref LL_ADC_REG_RANK_3 + * @arg @ref LL_ADC_REG_RANK_4 + * @arg @ref LL_ADC_REG_RANK_5 + * @arg @ref LL_ADC_REG_RANK_6 + * @arg @ref LL_ADC_REG_RANK_7 + * @arg @ref LL_ADC_REG_RANK_8 + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) + * @arg @ref LL_ADC_CHANNEL_VCORE (1) + * + * (1) For ADC channel read back from ADC register, + * comparison with internal channel parameter to be done + * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(const ADC_TypeDef *ADCx, uint32_t Rank) +{ + return (uint32_t)((READ_BIT(ADCx->CHSELR, + ADC_CHSELR_SQ1 << (Rank & ADC_REG_RANK_ID_SQRX_MASK)) + >> (Rank & ADC_REG_RANK_ID_SQRX_MASK) + ) << (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) + ); +} + +/** + * @brief Set ADC group regular sequence: channel on rank corresponding to + * channel number. + * @note This function performs: + * - Channels ordering into each rank of scan sequence: + * rank of each channel is fixed by channel HW number + * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). + * - Set channels selected by overwriting the current sequencer + * configuration. + * @note On this STM32 series, ADC group regular sequencer both modes + * "fully configurable" or "not fully configurable" + * are available, they can be chosen using + * function @ref LL_ADC_REG_SetSequencerConfigurable(). + * This function can be used with setting "not fully configurable". + * Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable() + * and @ref LL_ADC_REG_SetSequencerLength(). + * @note Depending on devices and packages, some channels may not be available. + * Refer to device datasheet for channels availability. + * @note On this STM32 series, to measure internal channels (VrefInt, + * TempSensor, ...), measurement paths to internal channels must be + * enabled separately. + * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @note One or several values can be selected. + * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...) + * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChannels + * @param ADCx ADC instance + * @param Channel This parameter can be a combination of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_VREFINT + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR + * @arg @ref LL_ADC_CHANNEL_VCORE + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetSequencerChannels(ADC_TypeDef *ADCx, uint32_t Channel) +{ + /* Parameter "Channel" is used with masks because containing */ + /* other bits reserved for other purpose. */ + WRITE_REG(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK)); +} + +/** + * @brief Add channel to ADC group regular sequence: channel on rank corresponding to + * channel number. + * @note This function performs: + * - Channels ordering into each rank of scan sequence: + * rank of each channel is fixed by channel HW number + * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). + * - Set channels selected by adding them to the current sequencer + * configuration. + * @note On this STM32 series, ADC group regular sequencer both modes + * "fully configurable" or "not fully configurable" + * are available, they can be chosen using + * function @ref LL_ADC_REG_SetSequencerConfigurable(). + * This function can be used with setting "not fully configurable". + * Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable() + * and @ref LL_ADC_REG_SetSequencerLength(). + * @note Depending on devices and packages, some channels may not be available. + * Refer to device datasheet for channels availability. + * @note On this STM32 series, to measure internal channels (VrefInt, + * TempSensor, ...), measurement paths to internal channels must be + * enabled separately. + * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @note One or several values can be selected. + * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...) + * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChAdd + * @param ADCx ADC instance + * @param Channel This parameter can be a combination of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_VREFINT + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR + * @arg @ref LL_ADC_CHANNEL_VCORE + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetSequencerChAdd(ADC_TypeDef *ADCx, uint32_t Channel) +{ + /* Parameter "Channel" is used with masks because containing */ + /* other bits reserved for other purpose. */ + SET_BIT(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK)); +} + +/** + * @brief Remove channel to ADC group regular sequence: channel on rank corresponding to + * channel number. + * @note This function performs: + * - Channels ordering into each rank of scan sequence: + * rank of each channel is fixed by channel HW number + * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). + * - Set channels selected by removing them to the current sequencer + * configuration. + * @note On this STM32 series, ADC group regular sequencer both modes + * "fully configurable" or "not fully configurable" + * are available, they can be chosen using + * function @ref LL_ADC_REG_SetSequencerConfigurable(). + * This function can be used with setting "not fully configurable". + * Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable() + * and @ref LL_ADC_REG_SetSequencerLength(). + * @note Depending on devices and packages, some channels may not be available. + * Refer to device datasheet for channels availability. + * @note On this STM32 series, to measure internal channels (VrefInt, + * TempSensor, ...), measurement paths to internal channels must be + * enabled separately. + * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @note One or several values can be selected. + * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...) + * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChRem + * @param ADCx ADC instance + * @param Channel This parameter can be a combination of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_VREFINT + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR + * @arg @ref LL_ADC_CHANNEL_VCORE + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetSequencerChRem(ADC_TypeDef *ADCx, uint32_t Channel) +{ + /* Parameter "Channel" is used with masks because containing */ + /* other bits reserved for other purpose. */ + CLEAR_BIT(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK)); +} + +/** + * @brief Get ADC group regular sequence: channel on rank corresponding to + * channel number. + * @note This function performs: + * - Channels order reading into each rank of scan sequence: + * rank of each channel is fixed by channel HW number + * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). + * @note On this STM32 series, ADC group regular sequencer both modes + * "fully configurable" or "not fully configurable" + * are available, they can be chosen using + * function @ref LL_ADC_REG_SetSequencerConfigurable(). + * This function can be used with setting "not fully configurable". + * Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable() + * and @ref LL_ADC_REG_SetSequencerLength(). + * @note Depending on devices and packages, some channels may not be available. + * Refer to device datasheet for channels availability. + * @note On this STM32 series, to measure internal channels (VrefInt, + * TempSensor, ...), measurement paths to internal channels must be + * enabled separately. + * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @note One or several values can be retrieved. + * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...) + * @rmtoll CHSELR CHSEL0 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL1 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL2 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL3 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL4 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL5 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL6 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL7 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL8 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL9 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL10 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL11 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL12 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL13 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL14 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL15 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL16 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL17 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL18 LL_ADC_REG_GetSequencerChannels + * @param ADCx ADC instance + * @retval Returned value can be a combination of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_VREFINT + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR + * @arg @ref LL_ADC_CHANNEL_VCORE + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerChannels(const ADC_TypeDef *ADCx) +{ + uint32_t channels_bitfield = (uint32_t)READ_BIT(ADCx->CHSELR, ADC_CHSELR_CHSEL); + + return ((((channels_bitfield & ADC_CHSELR_CHSEL0) >> ADC_CHSELR_CHSEL0_BITOFFSET_POS) * LL_ADC_CHANNEL_0) + | (((channels_bitfield & ADC_CHSELR_CHSEL1) >> ADC_CHSELR_CHSEL1_BITOFFSET_POS) * LL_ADC_CHANNEL_1) + | (((channels_bitfield & ADC_CHSELR_CHSEL2) >> ADC_CHSELR_CHSEL2_BITOFFSET_POS) * LL_ADC_CHANNEL_2) + | (((channels_bitfield & ADC_CHSELR_CHSEL3) >> ADC_CHSELR_CHSEL3_BITOFFSET_POS) * LL_ADC_CHANNEL_3) + | (((channels_bitfield & ADC_CHSELR_CHSEL4) >> ADC_CHSELR_CHSEL4_BITOFFSET_POS) * LL_ADC_CHANNEL_4) + | (((channels_bitfield & ADC_CHSELR_CHSEL5) >> ADC_CHSELR_CHSEL5_BITOFFSET_POS) * LL_ADC_CHANNEL_5) + | (((channels_bitfield & ADC_CHSELR_CHSEL6) >> ADC_CHSELR_CHSEL6_BITOFFSET_POS) * LL_ADC_CHANNEL_6) + | (((channels_bitfield & ADC_CHSELR_CHSEL7) >> ADC_CHSELR_CHSEL7_BITOFFSET_POS) * LL_ADC_CHANNEL_7) + | (((channels_bitfield & ADC_CHSELR_CHSEL10) >> ADC_CHSELR_CHSEL10_BITOFFSET_POS) * LL_ADC_CHANNEL_10) + | (((channels_bitfield & ADC_CHSELR_CHSEL11) >> ADC_CHSELR_CHSEL11_BITOFFSET_POS) * LL_ADC_CHANNEL_11) + | (((channels_bitfield & ADC_CHSELR_CHSEL12) >> ADC_CHSELR_CHSEL12_BITOFFSET_POS) * LL_ADC_CHANNEL_12) + | (((channels_bitfield & ADC_CHSELR_CHSEL13) >> ADC_CHSELR_CHSEL13_BITOFFSET_POS) * LL_ADC_CHANNEL_13) + ); +} + +/** + * @brief Set ADC continuous conversion mode on ADC group regular. + * @note Description of ADC continuous conversion mode: + * - single mode: one conversion per trigger + * - continuous mode: after the first trigger, following + * conversions launched successively automatically. + * @note It is not possible to enable both ADC group regular + * continuous mode and sequencer discontinuous mode. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @rmtoll CFGR1 CONT LL_ADC_REG_SetContinuousMode + * @param ADCx ADC instance + * @param Continuous This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_CONV_SINGLE + * @arg @ref LL_ADC_REG_CONV_CONTINUOUS + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous) +{ + MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_CONT, Continuous); +} + +/** + * @brief Get ADC continuous conversion mode on ADC group regular. + * @note Description of ADC continuous conversion mode: + * - single mode: one conversion per trigger + * - continuous mode: after the first trigger, following + * conversions launched successively automatically. + * @rmtoll CFGR1 CONT LL_ADC_REG_GetContinuousMode + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_CONV_SINGLE + * @arg @ref LL_ADC_REG_CONV_CONTINUOUS + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(const ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_CONT)); +} + +/** + * @brief Set ADC group regular conversion data transfer: no transfer or + * transfer by DMA, and DMA requests mode. + * @note If transfer by DMA selected, specifies the DMA requests + * mode: + * - Limited mode (One shot mode): DMA transfer requests are stopped + * when number of DMA data transfers (number of + * ADC conversions) is reached. + * This ADC mode is intended to be used with DMA mode non-circular. + * - Unlimited mode: DMA transfer requests are unlimited, + * whatever number of DMA data transfers (number of + * ADC conversions). + * This ADC mode is intended to be used with DMA mode circular. + * @note If ADC DMA requests mode is set to unlimited and DMA is set to + * mode non-circular: + * when DMA transfers size will be reached, DMA will stop transfers of + * ADC conversions data ADC will raise an overrun error + * (overrun flag and interruption if enabled). + * @note To configure DMA source address (peripheral address), + * use function @ref LL_ADC_DMA_GetRegAddr(). + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @rmtoll CFGR1 DMAEN LL_ADC_REG_SetDMATransfer\n + * CFGR1 DMACFG LL_ADC_REG_SetDMATransfer + * @param ADCx ADC instance + * @param DMATransfer This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE + * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED + * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer) +{ + MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG, DMATransfer); +} + +/** + * @brief Get ADC group regular conversion data transfer: no transfer or + * transfer by DMA, and DMA requests mode. + * @note If transfer by DMA selected, specifies the DMA requests + * mode: + * - Limited mode (One shot mode): DMA transfer requests are stopped + * when number of DMA data transfers (number of + * ADC conversions) is reached. + * This ADC mode is intended to be used with DMA mode non-circular. + * - Unlimited mode: DMA transfer requests are unlimited, + * whatever number of DMA data transfers (number of + * ADC conversions). + * This ADC mode is intended to be used with DMA mode circular. + * @note If ADC DMA requests mode is set to unlimited and DMA is set to + * mode non-circular: + * when DMA transfers size will be reached, DMA will stop transfers of + * ADC conversions data ADC will raise an overrun error + * (overrun flag and interruption if enabled). + * @note To configure DMA source address (peripheral address), + * use function @ref LL_ADC_DMA_GetRegAddr(). + * @rmtoll CFGR1 DMAEN LL_ADC_REG_GetDMATransfer\n + * CFGR1 DMACFG LL_ADC_REG_GetDMATransfer + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE + * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED + * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(const ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG)); +} + +/** + * @brief Set ADC group regular behavior in case of overrun: + * data preserved or overwritten. + * @note Compatibility with devices without feature overrun: + * other devices without this feature have a behavior + * equivalent to data overwritten. + * The default setting of overrun is data preserved. + * Therefore, for compatibility with all devices, parameter + * overrun should be set to data overwritten. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @rmtoll CFGR1 OVRMOD LL_ADC_REG_SetOverrun + * @param ADCx ADC instance + * @param Overrun This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED + * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun) +{ + MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_OVRMOD, Overrun); +} + +/** + * @brief Get ADC group regular behavior in case of overrun: + * data preserved or overwritten. + * @rmtoll CFGR1 OVRMOD LL_ADC_REG_GetOverrun + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED + * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(const ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_OVRMOD)); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels + * @{ + */ + +/** + * @brief Set sampling time of the selected ADC channel + * Unit: ADC clock cycles. + * @note On this device, sampling time is on channel scope: independently + * of channel mapped on ADC group regular or injected. + * @note In case of internal channel (VrefInt, TempSensor, ...) to be + * converted: + * sampling time constraints must be respected (sampling time can be + * adjusted in function of ADC clock frequency and sampling time + * setting). + * Refer to device datasheet for timings values (parameters TS_vrefint, + * TS_temp, ...). + * @note Conversion time is the addition of sampling time and processing time. + * Refer to reference manual for ADC processing time of + * this STM32 series. + * @note In case of ADC conversion of internal channel (VrefInt, + * temperature sensor, ...), a sampling time minimum value + * is required. + * Refer to device datasheet. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @rmtoll SMPR SMPSEL0 LL_ADC_SetChannelSamplingTime\n + * SMPR SMPSEL1 LL_ADC_SetChannelSamplingTime\n + * SMPR SMPSEL2 LL_ADC_SetChannelSamplingTime\n + * SMPR SMPSEL3 LL_ADC_SetChannelSamplingTime\n + * SMPR SMPSEL4 LL_ADC_SetChannelSamplingTime\n + * SMPR SMPSEL5 LL_ADC_SetChannelSamplingTime\n + * SMPR SMPSEL6 LL_ADC_SetChannelSamplingTime\n + * SMPR SMPSEL7 LL_ADC_SetChannelSamplingTime\n + * SMPR SMPSEL8 LL_ADC_SetChannelSamplingTime\n + * SMPR SMPSEL9 LL_ADC_SetChannelSamplingTime\n + * SMPR SMPSEL10 LL_ADC_SetChannelSamplingTime\n + * SMPR SMPSEL11 LL_ADC_SetChannelSamplingTime\n + * SMPR SMPSEL12 LL_ADC_SetChannelSamplingTime\n + * SMPR SMPSEL13 LL_ADC_SetChannelSamplingTime\n + * SMPR SMPSEL14 LL_ADC_SetChannelSamplingTime\n + * SMPR SMPSEL15 LL_ADC_SetChannelSamplingTime\n + * SMPR SMPSEL16 LL_ADC_SetChannelSamplingTime\n + * SMPR SMPSEL17 LL_ADC_SetChannelSamplingTime\n + * SMPR SMPSEL18 LL_ADC_SetChannelSamplingTime + * @param ADCx ADC instance + * @param Channel This parameter can be a combination of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_VREFINT + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR + * @arg @ref LL_ADC_CHANNEL_VCORE + * @param SamplingTimeY This parameter can be one of the following values: + * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1 + * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2 + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTimeY) +{ + /* Parameter "Channel" is used with masks because containing */ + /* other bits reserved for other purpose. */ + MODIFY_REG(ADCx->SMPR, + (Channel << ADC_SMPR_SMPSEL0_BITOFFSET_POS), + (Channel << ADC_SMPR_SMPSEL0_BITOFFSET_POS) & (SamplingTimeY & ADC_SAMPLING_TIME_CH_MASK) + ); +} + +/** + * @brief Get sampling time of the selected ADC channel + * Unit: ADC clock cycles. + * @note On this device, sampling time is on channel scope: independently + * of channel mapped on ADC group regular or injected. + * @note Conversion time is the addition of sampling time and processing time. + * Refer to reference manual for ADC processing time of + * this STM32 series. + * @rmtoll SMPR SMPSEL0 LL_ADC_GetChannelSamplingTime\n + * SMPR SMPSEL1 LL_ADC_GetChannelSamplingTime\n + * SMPR SMPSEL2 LL_ADC_GetChannelSamplingTime\n + * SMPR SMPSEL3 LL_ADC_GetChannelSamplingTime\n + * SMPR SMPSEL4 LL_ADC_GetChannelSamplingTime\n + * SMPR SMPSEL5 LL_ADC_GetChannelSamplingTime\n + * SMPR SMPSEL6 LL_ADC_GetChannelSamplingTime\n + * SMPR SMPSEL7 LL_ADC_GetChannelSamplingTime\n + * SMPR SMPSEL8 LL_ADC_GetChannelSamplingTime\n + * SMPR SMPSEL9 LL_ADC_GetChannelSamplingTime\n + * SMPR SMPSEL10 LL_ADC_GetChannelSamplingTime\n + * SMPR SMPSEL11 LL_ADC_GetChannelSamplingTime\n + * SMPR SMPSEL12 LL_ADC_GetChannelSamplingTime\n + * SMPR SMPSEL13 LL_ADC_GetChannelSamplingTime\n + * SMPR SMPSEL14 LL_ADC_GetChannelSamplingTime\n + * SMPR SMPSEL15 LL_ADC_GetChannelSamplingTime\n + * SMPR SMPSEL16 LL_ADC_GetChannelSamplingTime\n + * SMPR SMPSEL17 LL_ADC_GetChannelSamplingTime\n + * SMPR SMPSEL18 LL_ADC_GetChannelSamplingTime + * @param ADCx ADC instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_VREFINT + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR + * @arg @ref LL_ADC_CHANNEL_VCORE + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1 + * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2 + */ +__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(const ADC_TypeDef *ADCx, uint32_t Channel) +{ + __IO uint32_t smpr = READ_REG(ADCx->SMPR); + + /* Retrieve sampling time bit corresponding to the selected channel */ + /* and shift it to position 0. */ + uint32_t smp_channel_posbit0 = ((smpr & ADC_SAMPLING_TIME_CH_MASK) + >> ((((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) + + ADC_SMPR_SMPSEL0_BITOFFSET_POS) + & 0x1FUL)); + + /* Select sampling time bitfield depending on sampling time bit value 0 or 1. */ + return ((~(smp_channel_posbit0) * LL_ADC_SAMPLINGTIME_COMMON_1) + | (smp_channel_posbit0 * LL_ADC_SAMPLINGTIME_COMMON_2)); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog + * @{ + */ + +/** + * @brief Set ADC analog watchdog monitored channels: + * a single channel, multiple channels or all channels, + * on ADC group regular. + * @note Once monitored channels are selected, analog watchdog + * is enabled. + * @note In case of need to define a single channel to monitor + * with analog watchdog from sequencer channel definition, + * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP(). + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @rmtoll CFGR1 AWD1CH LL_ADC_SetAnalogWDMonitChannels\n + * CFGR1 AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n + * CFGR1 AWD1EN LL_ADC_SetAnalogWDMonitChannels\n + * AWD2CR AWD2CH LL_ADC_SetAnalogWDMonitChannels\n + * AWD3CR AWD3CH LL_ADC_SetAnalogWDMonitChannels + * @param ADCx ADC instance + * @param AWDy This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD1 + * @arg @ref LL_ADC_AWD2 + * @arg @ref LL_ADC_AWD3 + * @param AWDChannelGroup This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD_DISABLE + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG + * @arg @ref LL_ADC_AWD_CHANNEL_0_REG + * @arg @ref LL_ADC_AWD_CHANNEL_1_REG + * @arg @ref LL_ADC_AWD_CHANNEL_2_REG + * @arg @ref LL_ADC_AWD_CHANNEL_3_REG + * @arg @ref LL_ADC_AWD_CHANNEL_4_REG + * @arg @ref LL_ADC_AWD_CHANNEL_5_REG + * @arg @ref LL_ADC_AWD_CHANNEL_6_REG + * @arg @ref LL_ADC_AWD_CHANNEL_7_REG + * @arg @ref LL_ADC_AWD_CHANNEL_10_REG + * @arg @ref LL_ADC_AWD_CHANNEL_11_REG + * @arg @ref LL_ADC_AWD_CHANNEL_12_REG + * @arg @ref LL_ADC_AWD_CHANNEL_13_REG + * @arg @ref LL_ADC_AWD_CH_VREFINT_REG + * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG + * @arg @ref LL_ADC_AWD_CH_VCORE_REG + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup) +{ + /* Set bits with content of parameter "AWDChannelGroup" with bits position */ + /* in register and register position depending on parameter "AWDy". */ + /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */ + /* containing other bits reserved for other purpose. */ + __IO uint32_t *preg; + + if (AWDy == LL_ADC_AWD1) + { + preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR1, 0UL); + } + else + { + preg = __ADC_PTR_REG_OFFSET(ADCx->AWD2CR, + ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK)) >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL)); + } + + MODIFY_REG(*preg, + (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK), + AWDChannelGroup & AWDy); +} + +/** + * @brief Get ADC analog watchdog monitored channel. + * @note Usage of the returned channel number: + * - To reinject this channel into another function LL_ADC_xxx: + * the returned channel number is only partly formatted on definition + * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared + * with parts of literals LL_ADC_CHANNEL_x or using + * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). + * Then the selected literal LL_ADC_CHANNEL_x can be used + * as parameter for another function. + * - To get the channel number in decimal format: + * process the returned value with the helper macro + * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). + * Applicable only when the analog watchdog is set to monitor + * one channel. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @rmtoll CFGR1 AWD1CH LL_ADC_GetAnalogWDMonitChannels\n + * CFGR1 AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n + * CFGR1 AWD1EN LL_ADC_GetAnalogWDMonitChannels\n + * AWD2CR AWD2CH LL_ADC_GetAnalogWDMonitChannels\n + * AWD3CR AWD3CH LL_ADC_GetAnalogWDMonitChannels + * @param ADCx ADC instance + * @param AWDy This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD1 + * @arg @ref LL_ADC_AWD2 (1) + * @arg @ref LL_ADC_AWD3 (1) + * + * (1) On this AWD number, monitored channel can be retrieved + * if only 1 channel is programmed (or none or all channels). + * This function cannot retrieve monitored channel if + * multiple channels are programmed simultaneously + * by bitfield. + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_AWD_DISABLE + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG + * @arg @ref LL_ADC_AWD_CHANNEL_0_REG + * @arg @ref LL_ADC_AWD_CHANNEL_1_REG + * @arg @ref LL_ADC_AWD_CHANNEL_2_REG + * @arg @ref LL_ADC_AWD_CHANNEL_3_REG + * @arg @ref LL_ADC_AWD_CHANNEL_4_REG + * @arg @ref LL_ADC_AWD_CHANNEL_5_REG + * @arg @ref LL_ADC_AWD_CHANNEL_6_REG + * @arg @ref LL_ADC_AWD_CHANNEL_7_REG + * @arg @ref LL_ADC_AWD_CHANNEL_10_REG + * @arg @ref LL_ADC_AWD_CHANNEL_11_REG + * @arg @ref LL_ADC_AWD_CHANNEL_12_REG + * @arg @ref LL_ADC_AWD_CHANNEL_13_REG + */ +__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(const ADC_TypeDef *ADCx, uint32_t AWDy) +{ + __IO const uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR1, + ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) + + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) + * ADC_AWD_CR12_REGOFFSETGAP_VAL)); + + uint32_t analog_wd_monit_channels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK); + + /* If "analog_wd_monit_channels" == 0, then the selected AWD is disabled */ + /* (parameter value LL_ADC_AWD_DISABLE). */ + /* Else, the selected AWD is enabled and is monitoring a group of channels */ + /* or a single channel. */ + if (analog_wd_monit_channels != 0UL) + { + if (AWDy == LL_ADC_AWD1) + { + if ((analog_wd_monit_channels & ADC_CFGR1_AWD1SGL) == 0UL) + { + /* AWD monitoring a group of channels */ + analog_wd_monit_channels = ((analog_wd_monit_channels + | (ADC_AWD_CR23_CHANNEL_MASK) + ) + & (~(ADC_CFGR1_AWD1CH)) + ); + } + else + { + /* AWD monitoring a single channel */ + analog_wd_monit_channels = (analog_wd_monit_channels + | (ADC_AWD2CR_AWD2CH_0 << (analog_wd_monit_channels >> ADC_CFGR1_AWD1CH_Pos)) + ); + } + } + else + { + if ((analog_wd_monit_channels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK) + { + /* AWD monitoring a group of channels */ + analog_wd_monit_channels = (ADC_AWD_CR23_CHANNEL_MASK + | (ADC_CFGR1_AWD1EN) + ); + } + else + { + /* AWD monitoring a single channel */ + /* AWD monitoring a group of channels */ + analog_wd_monit_channels = (analog_wd_monit_channels + | (ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) + | (__LL_ADC_CHANNEL_TO_DECIMAL_NB(analog_wd_monit_channels) << ADC_CFGR1_AWD1CH_Pos) + ); + } + } + } + + return analog_wd_monit_channels; +} + +/** + * @brief Set ADC analog watchdog thresholds value of both thresholds + * high and low. + * @note If value of only one threshold high or low must be set, + * use function @ref LL_ADC_SetAnalogWDThresholds(). + * @note In case of ADC resolution different of 12 bits, + * analog watchdog thresholds data require a specific shift. + * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(). + * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are + * impacted: the comparison of analog watchdog thresholds is done on + * oversampling final computation (after ratio and shift application): + * ADC data register bitfield [15:4] (12 most significant bits). + * Examples: + * - Oversampling ratio and shift selected to have ADC conversion data + * on 12 bits (ratio 16 and shift 4, or ratio 32 and shift 5, ...): + * ADC analog watchdog thresholds must be divided by 16. + * - Oversampling ratio and shift selected to have ADC conversion data + * on 14 bits (ratio 16 and shift 2, or ratio 32 and shift 3, ...): + * ADC analog watchdog thresholds must be divided by 4. + * - Oversampling ratio and shift selected to have ADC conversion data + * on 16 bits (ratio 16 and shift none, or ratio 32 and shift 1, ...): + * ADC analog watchdog thresholds match directly to ADC data register. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @rmtoll AWD1TR HT1 LL_ADC_ConfigAnalogWDThresholds\n + * AWD2TR HT2 LL_ADC_ConfigAnalogWDThresholds\n + * AWD3TR HT3 LL_ADC_ConfigAnalogWDThresholds\n + * AWD1TR LT1 LL_ADC_ConfigAnalogWDThresholds\n + * AWD2TR LT2 LL_ADC_ConfigAnalogWDThresholds\n + * AWD3TR LT3 LL_ADC_ConfigAnalogWDThresholds + * @param ADCx ADC instance + * @param AWDy This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD1 + * @arg @ref LL_ADC_AWD2 + * @arg @ref LL_ADC_AWD3 + * @param AWDThresholdHighValue Value between Min_Data=0x000 and Max_Data=0xFFF + * @param AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF + * @retval None + */ +__STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue, + uint32_t AWDThresholdLowValue) +{ + /* Set bits with content of parameter "AWDThresholdxxxValue" with bits */ + /* position in register and register position depending on parameter */ + /* "AWDy". */ + /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */ + /* containing other bits reserved for other purpose. */ + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR, + (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK)) + >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS)) + + ((ADC_AWD_CR3_REGOFFSET & AWDy) + >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL)) + ); + + MODIFY_REG(*preg, + ADC_AWD1TR_HT1 | ADC_AWD1TR_LT1, + (AWDThresholdHighValue << ADC_AWD1TR_HT1_Pos) | AWDThresholdLowValue); +} + +/** + * @brief Set ADC analog watchdog threshold value of threshold + * high or low. + * @note If values of both thresholds high or low must be set, + * use function @ref LL_ADC_ConfigAnalogWDThresholds(). + * @note In case of ADC resolution different of 12 bits, + * analog watchdog thresholds data require a specific shift. + * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(). + * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are + * impacted: the comparison of analog watchdog thresholds is done on + * oversampling final computation (after ratio and shift application): + * ADC data register bitfield [15:4] (12 most significant bits). + * Examples: + * - Oversampling ratio and shift selected to have ADC conversion data + * on 12 bits (ratio 16 and shift 4, or ratio 32 and shift 5, ...): + * ADC analog watchdog thresholds must be divided by 16. + * - Oversampling ratio and shift selected to have ADC conversion data + * on 14 bits (ratio 16 and shift 2, or ratio 32 and shift 3, ...): + * ADC analog watchdog thresholds must be divided by 4. + * - Oversampling ratio and shift selected to have ADC conversion data + * on 16 bits (ratio 16 and shift none, or ratio 32 and shift 1, ...): + * ADC analog watchdog thresholds match directly to ADC data register. + * @note On this STM32 series, setting of this feature is not conditioned to + * ADC state: + * ADC can be disabled, enabled with or without conversion on going + * on ADC group regular. + * @rmtoll AWD1TR HT1 LL_ADC_SetAnalogWDThresholds\n + * AWD2TR HT2 LL_ADC_SetAnalogWDThresholds\n + * AWD3TR HT3 LL_ADC_SetAnalogWDThresholds\n + * AWD1TR LT1 LL_ADC_SetAnalogWDThresholds\n + * AWD2TR LT2 LL_ADC_SetAnalogWDThresholds\n + * AWD3TR LT3 LL_ADC_SetAnalogWDThresholds + * @param ADCx ADC instance + * @param AWDy This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD1 + * @arg @ref LL_ADC_AWD2 + * @arg @ref LL_ADC_AWD3 + * @param AWDThresholdsHighLow This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH + * @arg @ref LL_ADC_AWD_THRESHOLD_LOW + * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow, + uint32_t AWDThresholdValue) +{ + /* Set bits with content of parameter "AWDThresholdValue" with bits */ + /* position in register and register position depending on parameters */ + /* "AWDThresholdsHighLow" and "AWDy". */ + /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */ + /* containing other bits reserved for other purpose. */ + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR, + (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK)) + >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS)) + + ((ADC_AWD_CR3_REGOFFSET & AWDy) + >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL))); + + MODIFY_REG(*preg, + AWDThresholdsHighLow, + AWDThresholdValue << ((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)); +} + +/** + * @brief Get ADC analog watchdog threshold value of threshold high, + * threshold low or raw data with ADC thresholds high and low + * concatenated. + * @note If raw data with ADC thresholds high and low is retrieved, + * the data of each threshold high or low can be isolated + * using helper macro: + * @ref __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(). + * @note In case of ADC resolution different of 12 bits, + * analog watchdog thresholds data require a specific shift. + * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(). + * @rmtoll AWD1TR HT1 LL_ADC_GetAnalogWDThresholds\n + * AWD2TR HT2 LL_ADC_GetAnalogWDThresholds\n + * AWD3TR HT3 LL_ADC_GetAnalogWDThresholds\n + * AWD1TR LT1 LL_ADC_GetAnalogWDThresholds\n + * AWD2TR LT2 LL_ADC_GetAnalogWDThresholds\n + * AWD3TR LT3 LL_ADC_GetAnalogWDThresholds + * @param ADCx ADC instance + * @param AWDy This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD1 + * @arg @ref LL_ADC_AWD2 + * @arg @ref LL_ADC_AWD3 + * @param AWDThresholdsHighLow This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH + * @arg @ref LL_ADC_AWD_THRESHOLD_LOW + * @arg @ref LL_ADC_AWD_THRESHOLDS_HIGH_LOW + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF + */ +__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(const ADC_TypeDef *ADCx, + uint32_t AWDy, uint32_t AWDThresholdsHighLow) +{ + /* Set bits with content of parameter "AWDThresholdValue" with bits */ + /* position in register and register position depending on parameters */ + /* "AWDThresholdsHighLow" and "AWDy". */ + /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */ + /* containing other bits reserved for other purpose. */ + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR, + (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK)) + >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS)) + + ((ADC_AWD_CR3_REGOFFSET & AWDy) + >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL))); + + return (uint32_t)(READ_BIT(*preg, + (AWDThresholdsHighLow | ADC_AWD1TR_LT1)) + >> (((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4) + & ~(AWDThresholdsHighLow & ADC_AWD1TR_LT1))); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_ADC_oversampling Configuration of ADC transversal scope: oversampling + * @{ + */ + +/** + * @brief Set ADC oversampling scope. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled. + * @rmtoll CFGR2 OVSE LL_ADC_SetOverSamplingScope + * @param ADCx ADC instance + * @param OvsScope This parameter can be one of the following values: + * @arg @ref LL_ADC_OVS_DISABLE + * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope) +{ + MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_OVSE, OvsScope); +} + +/** + * @brief Get ADC oversampling scope. + * @rmtoll CFGR2 OVSE LL_ADC_GetOverSamplingScope + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_OVS_DISABLE + * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED + */ +__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(const ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSE)); +} + +/** + * @brief Set ADC oversampling discontinuous mode (triggered mode) + * on the selected ADC group. + * @note Number of oversampled conversions are done either in: + * - continuous mode (all conversions of oversampling ratio + * are done from 1 trigger) + * - discontinuous mode (each conversion of oversampling ratio + * needs a trigger) + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @rmtoll CFGR2 TOVS LL_ADC_SetOverSamplingDiscont + * @param ADCx ADC instance + * @param OverSamplingDiscont This parameter can be one of the following values: + * @arg @ref LL_ADC_OVS_REG_CONT + * @arg @ref LL_ADC_OVS_REG_DISCONT + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont) +{ + MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TOVS, OverSamplingDiscont); +} + +/** + * @brief Get ADC oversampling discontinuous mode (triggered mode) + * on the selected ADC group. + * @note Number of oversampled conversions are done either in: + * - continuous mode (all conversions of oversampling ratio + * are done from 1 trigger) + * - discontinuous mode (each conversion of oversampling ratio + * needs a trigger) + * @rmtoll CFGR2 TOVS LL_ADC_GetOverSamplingDiscont + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_OVS_REG_CONT + * @arg @ref LL_ADC_OVS_REG_DISCONT + */ +__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(const ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TOVS)); +} + +/** + * @brief Set ADC oversampling + * @note This function set the 2 items of oversampling configuration: + * - ratio + * - shift + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled. + * @rmtoll CFGR2 OVSS LL_ADC_ConfigOverSamplingRatioShift\n + * CFGR2 OVSR LL_ADC_ConfigOverSamplingRatioShift + * @param ADCx ADC instance + * @param Ratio This parameter can be one of the following values: + * @arg @ref LL_ADC_OVS_RATIO_2 + * @arg @ref LL_ADC_OVS_RATIO_4 + * @arg @ref LL_ADC_OVS_RATIO_8 + * @arg @ref LL_ADC_OVS_RATIO_16 + * @arg @ref LL_ADC_OVS_RATIO_32 + * @arg @ref LL_ADC_OVS_RATIO_64 + * @arg @ref LL_ADC_OVS_RATIO_128 + * @arg @ref LL_ADC_OVS_RATIO_256 + * @param Shift This parameter can be one of the following values: + * @arg @ref LL_ADC_OVS_SHIFT_NONE + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8 + * @retval None + */ +__STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift) +{ + MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | Ratio)); +} + +/** + * @brief Get ADC oversampling ratio + * @rmtoll CFGR2 OVSR LL_ADC_GetOverSamplingRatio + * @param ADCx ADC instance + * @retval Ratio This parameter can be one of the following values: + * @arg @ref LL_ADC_OVS_RATIO_2 + * @arg @ref LL_ADC_OVS_RATIO_4 + * @arg @ref LL_ADC_OVS_RATIO_8 + * @arg @ref LL_ADC_OVS_RATIO_16 + * @arg @ref LL_ADC_OVS_RATIO_32 + * @arg @ref LL_ADC_OVS_RATIO_64 + * @arg @ref LL_ADC_OVS_RATIO_128 + * @arg @ref LL_ADC_OVS_RATIO_256 + */ +__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(const ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR)); +} + +/** + * @brief Get ADC oversampling shift + * @rmtoll CFGR2 OVSS LL_ADC_GetOverSamplingShift + * @param ADCx ADC instance + * @retval Shift This parameter can be one of the following values: + * @arg @ref LL_ADC_OVS_SHIFT_NONE + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7 + * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8 + */ +__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(const ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS)); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance + * @{ + */ + +/** + * @brief Enable ADC instance internal voltage regulator. + * @note On this STM32 series, there are three possibilities to enable + * the voltage regulator: + * - by enabling it manually + * using function @ref LL_ADC_EnableInternalRegulator(). + * - by launching a calibration + * using function @ref LL_ADC_StartCalibration(). + * - by enabling the ADC + * using function @ref LL_ADC_Enable(). + * @note On this STM32 series, after ADC internal voltage regulator enable, + * a delay for ADC internal voltage regulator stabilization + * is required before performing a ADC calibration or ADC enable. + * Refer to device datasheet, parameter "tADCVREG_STUP". + * Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be ADC disabled. + * @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx) +{ + /* Note: Write register with some additional bits forced to state reset */ + /* instead of modifying only the selected bit for this function, */ + /* to not interfere with bits with HW property "rs". */ + MODIFY_REG(ADCx->CR, + ADC_CR_BITS_PROPERTY_RS, + ADC_CR_ADVREGEN); +} + +/** + * @brief Disable ADC internal voltage regulator. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be ADC disabled. + * @rmtoll CR ADVREGEN LL_ADC_DisableInternalRegulator + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN | ADC_CR_BITS_PROPERTY_RS)); +} + +/** + * @brief Get the selected ADC instance internal voltage regulator state. + * @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled + * @param ADCx ADC instance + * @retval 0: internal regulator is disabled, 1: internal regulator is enabled. + */ +__STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable the selected ADC instance. + * @note On this STM32 series, after ADC enable, a delay for + * ADC internal analog stabilization is required before performing a + * ADC conversion start. + * Refer to device datasheet, parameter tSTAB. + * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC + * is enabled and when conversion clock is active. + * (not only core clock: this ADC has a dual clock domain) + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be ADC disabled and ADC internal voltage regulator enabled. + * @rmtoll CR ADEN LL_ADC_Enable + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx) +{ + /* Note: Write register with some additional bits forced to state reset */ + /* instead of modifying only the selected bit for this function, */ + /* to not interfere with bits with HW property "rs". */ + MODIFY_REG(ADCx->CR, + ADC_CR_BITS_PROPERTY_RS, + ADC_CR_ADEN); +} + +/** + * @brief Disable the selected ADC instance. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be not disabled. Must be enabled without conversion on going + * on group regular. + * @rmtoll CR ADDIS LL_ADC_Disable + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx) +{ + /* Note: Write register with some additional bits forced to state reset */ + /* instead of modifying only the selected bit for this function, */ + /* to not interfere with bits with HW property "rs". */ + MODIFY_REG(ADCx->CR, + ADC_CR_BITS_PROPERTY_RS, + ADC_CR_ADDIS); +} + +/** + * @brief Get the selected ADC instance enable state. + * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC + * is enabled and when conversion clock is active. + * (not only core clock: this ADC has a dual clock domain) + * @rmtoll CR ADEN LL_ADC_IsEnabled + * @param ADCx ADC instance + * @retval 0: ADC is disabled, 1: ADC is enabled. + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabled(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); +} + +/** + * @brief Get the selected ADC instance disable state. + * @rmtoll CR ADDIS LL_ADC_IsDisableOngoing + * @param ADCx ADC instance + * @retval 0: no ADC disable command on going. + */ +__STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL); +} + +/** + * @brief Start ADC calibration in the mode single-ended + * or differential (for devices with differential mode available). + * @note On this STM32 series, a minimum number of ADC clock cycles + * are required between ADC end of calibration and ADC enable. + * Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES. + * @note In case of usage of ADC with DMA transfer: + * On this STM32 series, ADC DMA transfer request should be disabled + * during calibration: + * Calibration factor is available in data register + * and also transferred by DMA. + * To not insert ADC calibration factor among ADC conversion data + * in array variable, DMA transfer must be disabled during + * calibration. + * (DMA transfer setting backup and disable before calibration, + * DMA transfer setting restore after calibration. + * Refer to functions @ref LL_ADC_REG_GetDMATransfer(), + * @ref LL_ADC_REG_SetDMATransfer() ). + * @note In case of usage of feature auto power-off: + * This mode must be disabled during calibration + * Refer to function @ref LL_ADC_SetLowPowerMode(). + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be ADC disabled. + * @rmtoll CR ADCAL LL_ADC_StartCalibration + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx) +{ + /* Note: Write register with some additional bits forced to state reset */ + /* instead of modifying only the selected bit for this function, */ + /* to not interfere with bits with HW property "rs". */ + MODIFY_REG(ADCx->CR, + ADC_CR_BITS_PROPERTY_RS, + ADC_CR_ADCAL); +} + +/** + * @brief Get ADC calibration state. + * @rmtoll CR ADCAL LL_ADC_IsCalibrationOnGoing + * @param ADCx ADC instance + * @retval 0: calibration complete, 1: calibration in progress. + */ +__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular + * @{ + */ + +/** + * @brief Start ADC group regular conversion. + * @note On this STM32 series, this function is relevant for both + * internal trigger (SW start) and external trigger: + * - If ADC trigger has been set to software start, ADC conversion + * starts immediately. + * - If ADC trigger has been set to external trigger, ADC conversion + * will start at next trigger event (on the selected trigger edge) + * following the ADC start conversion command. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be enabled without conversion on going on group regular, + * without conversion stop command on going on group regular, + * without ADC disable command on going. + * @rmtoll CR ADSTART LL_ADC_REG_StartConversion + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx) +{ + /* Note: Write register with some additional bits forced to state reset */ + /* instead of modifying only the selected bit for this function, */ + /* to not interfere with bits with HW property "rs". */ + MODIFY_REG(ADCx->CR, + ADC_CR_BITS_PROPERTY_RS, + ADC_CR_ADSTART); +} + +/** + * @brief Stop ADC group regular conversion. + * @note On this STM32 series, setting of this feature is conditioned to + * ADC state: + * ADC must be enabled (potentially with conversion on going on group regular), + * without ADC disable command on going. + * @rmtoll CR ADSTP LL_ADC_REG_StopConversion + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx) +{ + /* Note: Write register with some additional bits forced to state reset */ + /* instead of modifying only the selected bit for this function, */ + /* to not interfere with bits with HW property "rs". */ + MODIFY_REG(ADCx->CR, + ADC_CR_BITS_PROPERTY_RS, + ADC_CR_ADSTP); +} + +/** + * @brief Get ADC group regular conversion state. + * @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing + * @param ADCx ADC instance + * @retval 0: no conversion is on going on ADC group regular. + */ +__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); +} + +/** + * @brief Get ADC group regular command of conversion stop state + * @rmtoll CR ADSTP LL_ADC_REG_IsStopConversionOngoing + * @param ADCx ADC instance + * @retval 0: no command of conversion stop is on going on ADC group regular. + */ +__STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)) ? 1UL : 0UL); +} + +/** + * @brief Get ADC group regular conversion data, range fit for + * all ADC configurations: all ADC resolutions and + * all oversampling increased data width (for devices + * with feature oversampling). + * @rmtoll DR DATA LL_ADC_REG_ReadConversionData32 + * @param ADCx ADC instance + * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(const ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); +} + +/** + * @brief Get ADC group regular conversion data, range fit for + * ADC resolution 12 bits. + * @note For devices with feature oversampling: Oversampling + * can increase data width, function for extended range + * may be needed: @ref LL_ADC_REG_ReadConversionData32. + * @rmtoll DR DATA LL_ADC_REG_ReadConversionData12 + * @param ADCx ADC instance + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF + */ +__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(const ADC_TypeDef *ADCx) +{ + return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA) & 0x00000FFFUL); +} + +/** + * @brief Get ADC group regular conversion data, range fit for + * ADC resolution 10 bits. + * @note For devices with feature oversampling: Oversampling + * can increase data width, function for extended range + * may be needed: @ref LL_ADC_REG_ReadConversionData32. + * @rmtoll DR DATA LL_ADC_REG_ReadConversionData10 + * @param ADCx ADC instance + * @retval Value between Min_Data=0x000 and Max_Data=0x3FF + */ +__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(const ADC_TypeDef *ADCx) +{ + return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA) & 0x000003FFUL); +} + +/** + * @brief Get ADC group regular conversion data, range fit for + * ADC resolution 8 bits. + * @note For devices with feature oversampling: Oversampling + * can increase data width, function for extended range + * may be needed: @ref LL_ADC_REG_ReadConversionData32. + * @rmtoll DR DATA LL_ADC_REG_ReadConversionData8 + * @param ADCx ADC instance + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(const ADC_TypeDef *ADCx) +{ + return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA) & 0x000000FFUL); +} + +/** + * @brief Get ADC group regular conversion data, range fit for + * ADC resolution 6 bits. + * @note For devices with feature oversampling: Oversampling + * can increase data width, function for extended range + * may be needed: @ref LL_ADC_REG_ReadConversionData32. + * @rmtoll DR DATA LL_ADC_REG_ReadConversionData6 + * @param ADCx ADC instance + * @retval Value between Min_Data=0x00 and Max_Data=0x3F + */ +__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(const ADC_TypeDef *ADCx) +{ + return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA) & 0x0000003FUL); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_FLAG_Management ADC flag management + * @{ + */ + +/** + * @brief Get flag ADC ready. + * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC + * is enabled and when conversion clock is active. + * (not only core clock: this ADC has a dual clock domain) + * @rmtoll ISR ADRDY LL_ADC_IsActiveFlag_ADRDY + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)) ? 1UL : 0UL); +} + +/** + * @brief Get flag ADC internal voltage regulator ready. + * @rmtoll ISR LDORDY LL_ADC_IsActiveFlag_LDORDY + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_LDORDY(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_LDORDY) == (LL_ADC_FLAG_LDORDY)) ? 1UL : 0UL); +} + +/** + * @brief Get flag ADC group regular end of unitary conversion. + * @rmtoll ISR EOC LL_ADC_IsActiveFlag_EOC + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)) ? 1UL : 0UL); +} + +/** + * @brief Get flag ADC group regular end of sequence conversions. + * @rmtoll ISR EOS LL_ADC_IsActiveFlag_EOS + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)) ? 1UL : 0UL); +} + +/** + * @brief Get flag ADC group regular overrun. + * @rmtoll ISR OVR LL_ADC_IsActiveFlag_OVR + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)) ? 1UL : 0UL); +} + +/** + * @brief Get flag ADC group regular end of sampling phase. + * @rmtoll ISR EOSMP LL_ADC_IsActiveFlag_EOSMP + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)) ? 1UL : 0UL); +} + +/** + * @brief Get flag ADC analog watchdog 1 flag + * @rmtoll ISR AWD1 LL_ADC_IsActiveFlag_AWD1 + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)) ? 1UL : 0UL); +} + +/** + * @brief Get flag ADC analog watchdog 2. + * @rmtoll ISR AWD2 LL_ADC_IsActiveFlag_AWD2 + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)) ? 1UL : 0UL); +} + +/** + * @brief Get flag ADC analog watchdog 3. + * @rmtoll ISR AWD3 LL_ADC_IsActiveFlag_AWD3 + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL : 0UL); +} + +/** + * @brief Get flag ADC end of calibration. + * @rmtoll ISR EOCAL LL_ADC_IsActiveFlag_EOCAL + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOCAL(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOCAL) == (LL_ADC_FLAG_EOCAL)) ? 1UL : 0UL); +} + +/** + * @brief Clear flag ADC ready. + * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC + * is enabled and when conversion clock is active. + * (not only core clock: this ADC has a dual clock domain) + * @rmtoll ISR ADRDY LL_ADC_ClearFlag_ADRDY + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx) +{ + WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY); +} + +/** + * @brief Clear flag ADC internal voltage regulator ready. + * @rmtoll ISR LDORDY LL_ADC_ClearFlag_LDORDY + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void LL_ADC_ClearFlag_LDORDY(ADC_TypeDef *ADCx) +{ + WRITE_REG(ADCx->ISR, LL_ADC_FLAG_LDORDY); +} + +/** + * @brief Clear flag ADC group regular end of unitary conversion. + * @rmtoll ISR EOC LL_ADC_ClearFlag_EOC + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx) +{ + WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC); +} + +/** + * @brief Clear flag ADC group regular end of sequence conversions. + * @rmtoll ISR EOS LL_ADC_ClearFlag_EOS + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx) +{ + WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS); +} + +/** + * @brief Clear flag ADC group regular overrun. + * @rmtoll ISR OVR LL_ADC_ClearFlag_OVR + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx) +{ + WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR); +} + +/** + * @brief Clear flag ADC group regular end of sampling phase. + * @rmtoll ISR EOSMP LL_ADC_ClearFlag_EOSMP + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx) +{ + WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP); +} + +/** + * @brief Clear flag ADC analog watchdog 1. + * @rmtoll ISR AWD1 LL_ADC_ClearFlag_AWD1 + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx) +{ + WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1); +} + +/** + * @brief Clear flag ADC analog watchdog 2. + * @rmtoll ISR AWD2 LL_ADC_ClearFlag_AWD2 + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_ClearFlag_AWD2(ADC_TypeDef *ADCx) +{ + WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD2); +} + +/** + * @brief Clear flag ADC analog watchdog 3. + * @rmtoll ISR AWD3 LL_ADC_ClearFlag_AWD3 + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx) +{ + WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD3); +} + +/** + * @brief Clear flag ADC end of calibration. + * @rmtoll ISR EOCAL LL_ADC_ClearFlag_EOCAL + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_ClearFlag_EOCAL(ADC_TypeDef *ADCx) +{ + WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOCAL); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_IT_Management ADC IT management + * @{ + */ + +/** + * @brief Enable ADC ready. + * @rmtoll IER ADRDYIE LL_ADC_EnableIT_ADRDY + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY); +} + +/** + * @brief Enable interruption ADC internal voltage regulator ready. + * @rmtoll IER LDORDYIE LL_ADC_EnableIT_LDORDY + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void LL_ADC_EnableIT_LDORDY(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IER, LL_ADC_FLAG_LDORDY); +} + +/** + * @brief Enable interruption ADC group regular end of unitary conversion. + * @rmtoll IER EOCIE LL_ADC_EnableIT_EOC + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IER, LL_ADC_IT_EOC); +} + +/** + * @brief Enable interruption ADC group regular end of sequence conversions. + * @rmtoll IER EOSIE LL_ADC_EnableIT_EOS + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IER, LL_ADC_IT_EOS); +} + +/** + * @brief Enable ADC group regular interruption overrun. + * @rmtoll IER OVRIE LL_ADC_EnableIT_OVR + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IER, LL_ADC_IT_OVR); +} + +/** + * @brief Enable interruption ADC group regular end of sampling. + * @rmtoll IER EOSMPIE LL_ADC_EnableIT_EOSMP + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP); +} + +/** + * @brief Enable interruption ADC analog watchdog 1. + * @rmtoll IER AWD1IE LL_ADC_EnableIT_AWD1 + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IER, LL_ADC_IT_AWD1); +} + +/** + * @brief Enable interruption ADC analog watchdog 2. + * @rmtoll IER AWD2IE LL_ADC_EnableIT_AWD2 + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_EnableIT_AWD2(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IER, LL_ADC_IT_AWD2); +} + +/** + * @brief Enable interruption ADC analog watchdog 3. + * @rmtoll IER AWD3IE LL_ADC_EnableIT_AWD3 + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_EnableIT_AWD3(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IER, LL_ADC_IT_AWD3); +} + +/** + * @brief Enable interruption ADC end of calibration. + * @rmtoll IER EOCALIE LL_ADC_EnableIT_EOCAL + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_EnableIT_EOCAL(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IER, LL_ADC_IT_EOCAL); +} + +/** + * @brief Disable interruption ADC ready. + * @rmtoll IER ADRDYIE LL_ADC_DisableIT_ADRDY + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY); +} + +/** + * @brief Disable interruption ADC internal voltage regulator ready. + * @rmtoll IER LDORDYIE LL_ADC_DisableIT_LDORDY + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE void LL_ADC_DisableIT_LDORDY(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->IER, LL_ADC_FLAG_LDORDY); +} + +/** + * @brief Disable interruption ADC group regular end of unitary conversion. + * @rmtoll IER EOCIE LL_ADC_DisableIT_EOC + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC); +} + +/** + * @brief Disable interruption ADC group regular end of sequence conversions. + * @rmtoll IER EOSIE LL_ADC_DisableIT_EOS + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS); +} + +/** + * @brief Disable interruption ADC group regular overrun. + * @rmtoll IER OVRIE LL_ADC_DisableIT_OVR + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR); +} + +/** + * @brief Disable interruption ADC group regular end of sampling. + * @rmtoll IER EOSMPIE LL_ADC_DisableIT_EOSMP + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP); +} + +/** + * @brief Disable interruption ADC analog watchdog 1. + * @rmtoll IER AWD1IE LL_ADC_DisableIT_AWD1 + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1); +} + +/** + * @brief Disable interruption ADC analog watchdog 2. + * @rmtoll IER AWD2IE LL_ADC_DisableIT_AWD2 + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_DisableIT_AWD2(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD2); +} + +/** + * @brief Disable interruption ADC analog watchdog 3. + * @rmtoll IER AWD3IE LL_ADC_DisableIT_AWD3 + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD3); +} + +/** + * @brief Disable interruption ADC end of calibration. + * @rmtoll IER EOCALIE LL_ADC_DisableIT_EOCAL + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_DisableIT_EOCAL(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOCAL); +} + +/** + * @brief Get state of interruption ADC ready + * (0: interrupt disabled, 1: interrupt enabled). + * @rmtoll IER ADRDYIE LL_ADC_IsEnabledIT_ADRDY + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)) ? 1UL : 0UL); +} + +/** + * @brief Get state of interruption ADC internal voltage regulator ready. + * @rmtoll IER LDORDYIE LL_ADC_IsEnabledIT_LDORDY + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_LDORDY(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->IER, LL_ADC_FLAG_LDORDY) == (LL_ADC_FLAG_LDORDY)) ? 1UL : 0UL); +} + +/** + * @brief Get state of interruption ADC group regular end of unitary conversion + * (0: interrupt disabled, 1: interrupt enabled). + * @rmtoll IER EOCIE LL_ADC_IsEnabledIT_EOC + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)) ? 1UL : 0UL); +} + +/** + * @brief Get state of interruption ADC group regular end of sequence conversions + * (0: interrupt disabled, 1: interrupt enabled). + * @rmtoll IER EOSIE LL_ADC_IsEnabledIT_EOS + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)) ? 1UL : 0UL); +} + +/** + * @brief Get state of interruption ADC group regular overrun + * (0: interrupt disabled, 1: interrupt enabled). + * @rmtoll IER OVRIE LL_ADC_IsEnabledIT_OVR + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)) ? 1UL : 0UL); +} + +/** + * @brief Get state of interruption ADC group regular end of sampling + * (0: interrupt disabled, 1: interrupt enabled). + * @rmtoll IER EOSMPIE LL_ADC_IsEnabledIT_EOSMP + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)) ? 1UL : 0UL); +} + +/** + * @brief Get state of interruption ADC analog watchdog 1 + * (0: interrupt disabled, 1: interrupt enabled). + * @rmtoll IER AWD1IE LL_ADC_IsEnabledIT_AWD1 + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)) ? 1UL : 0UL); +} + +/** + * @brief Get state of interruption Get ADC analog watchdog 2 + * (0: interrupt disabled, 1: interrupt enabled). + * @rmtoll IER AWD2IE LL_ADC_IsEnabledIT_AWD2 + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)) ? 1UL : 0UL); +} + +/** + * @brief Get state of interruption Get ADC analog watchdog 3 + * (0: interrupt disabled, 1: interrupt enabled). + * @rmtoll IER AWD3IE LL_ADC_IsEnabledIT_AWD3 + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)) ? 1UL : 0UL); +} + +/** + * @brief Get state of interruption ADC end of calibration + * (0: interrupt disabled, 1: interrupt enabled). + * @rmtoll IER EOCALIE LL_ADC_IsEnabledIT_EOCAL + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOCAL(const ADC_TypeDef *ADCx) +{ + return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOCAL) == (LL_ADC_IT_EOCAL)) ? 1UL : 0UL); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +/* Initialization of some features of ADC common parameters and multimode */ +ErrorStatus LL_ADC_CommonDeInit(const ADC_Common_TypeDef *ADCxy_COMMON); +ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, const LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct); +void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct); + +/* De-initialization of ADC instance */ +ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx); + +/* Initialization of some features of ADC instance */ +ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, const LL_ADC_InitTypeDef *pADC_InitStruct); +void LL_ADC_StructInit(LL_ADC_InitTypeDef *pADC_InitStruct); + +/* Initialization of some features of ADC instance and ADC group regular */ +ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, const LL_ADC_REG_InitTypeDef *pADC_RegInitStruct); +void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *pADC_RegInitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* ADC4 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WBAxx_LL_ADC_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_bus.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_bus.h new file mode 100644 index 0000000000..50ffd2534f --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_bus.h @@ -0,0 +1,1757 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_ll_bus.h + * @author MCD Application Team + * @brief Header file of BUS LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### RCC Limitations ##### + ============================================================================== + [..] + A delay between an RCC peripheral clock enable and the effective peripheral + enabling should be taken into account in order to manage the peripheral read/write + from/to registers. + (+) This delay depends on the peripheral mapping. + (++) AHB , APB peripherals, 1 dummy read is necessary + + [..] + Workarounds: + (#) For AHB , APB peripherals, a dummy read to the peripheral register has been + inserted in each LL_{BUS}_GRP{x}_EnableClock() function. + + @endverbatim + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_LL_BUS_H +#define STM32WBAxx_LL_BUS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx.h" + +/** @addtogroup STM32WBAxx_LL_Driver + * @{ + */ + +#if defined(RCC) + +/** @defgroup BUS_LL BUS + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants + * @{ + */ + +/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH + * @{ + */ +#define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU +#define LL_AHB1_GRP1_PERIPH_GPDMA1 RCC_AHB1ENR_GPDMA1EN +#define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHB1ENR_FLASHEN +#define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN +#define LL_AHB1_GRP1_PERIPH_TSC RCC_AHB1ENR_TSCEN +#define LL_AHB1_GRP1_PERIPH_RAMCFG RCC_AHB1ENR_RAMCFGEN +#if defined(GTZC_TZSC) +#define LL_AHB1_GRP1_PERIPH_GTZC1 RCC_AHB1ENR_GTZC1EN +#endif /* GTZC_TZSC */ +#define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1ENR_SRAM1EN +/** + * @} + */ + +/** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH + * @{ + */ +#define LL_AHB2_GRP1_PERIPH_ALL 0xFFFFFFFFU +#define LL_AHB2_GRP1_PERIPH_GPIOA RCC_AHB2ENR_GPIOAEN +#define LL_AHB2_GRP1_PERIPH_GPIOB RCC_AHB2ENR_GPIOBEN +#define LL_AHB2_GRP1_PERIPH_GPIOC RCC_AHB2ENR_GPIOCEN +#define LL_AHB2_GRP1_PERIPH_GPIOH RCC_AHB2ENR_GPIOHEN +#define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN +#define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR_HASHEN +#define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN +#if defined(SAES) +#define LL_AHB2_GRP1_PERIPH_SAES RCC_AHB2ENR_SAESEN +#endif /* SAES */ +#define LL_AHB2_GRP1_PERIPH_HSEM RCC_AHB2ENR_HSEMEN +#define LL_AHB2_GRP1_PERIPH_PKA RCC_AHB2ENR_PKAEN +#define LL_AHB2_GRP1_PERIPH_SRAM2 RCC_AHB2ENR_SRAM2EN +/** + * @} + */ + +/** @defgroup BUS_LL_EC_AHB4_GRP1_PERIPH AHB4 GRP1 PERIPH + * @{ + */ +#define LL_AHB4_GRP1_PERIPH_ALL 0xFFFFFFFFU +#define LL_AHB4_GRP1_PERIPH_PWR RCC_AHB4ENR_PWREN +#define LL_AHB4_GRP1_PERIPH_ADC4 RCC_AHB4ENR_ADC4EN +/** + * @} + */ + +/** @defgroup BUS_LL_EC_AHB5_GRP1_PERIPH AHB5 GRP1 PERIPH + * @{ + */ +#define LL_AHB5_GRP1_PERIPH_ALL 0xFFFFFFFFU +#if defined(PTACONV) +#define LL_AHB5_GRP1_PERIPH_PTACONV RCC_AHB5ENR_PTACONVEN +#endif /* PTACONV */ +#define LL_AHB5_GRP1_PERIPH_RADIO RCC_AHB5ENR_RADIOEN +/** + * @} + */ + +/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH + * @{ + */ +#define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU +#define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR1_TIM2EN +#if defined(TIM3) +#define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR1_TIM3EN +#endif /* TIM3 */ +#define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR1_WWDGEN +#define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR1_USART2EN +#if defined(I2C1) +#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR1_I2C1EN +#endif /* I2C1 */ +/** + * @} + */ + + +/** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH + * @{ + */ +#define LL_APB1_GRP2_PERIPH_ALL 0xFFFFFFFFU +#if defined(LPTIM2) +#define LL_APB1_GRP2_PERIPH_LPTIM2 RCC_APB1ENR2_LPTIM2EN +#endif /* LPTIM2 */ +/** + * @} + */ + +/** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH + * @{ + */ +#define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU +#define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN +#if defined(SPI1) +#define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN +#endif /* SPI1 */ +#define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN +#define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN +#if defined(TIM17) +#define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN +#endif /* TIM17 */ +#if defined(SAI1) +#define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN +#endif /* SAI1 */ +/** + * @} + */ + +/** @defgroup BUS_LL_EC_APB7_GRP1_PERIPH APB7 GRP1 PERIPH + * @{ + */ +#define LL_APB7_GRP1_PERIPH_ALL 0xFFFFFFFFU +#define LL_APB7_GRP1_PERIPH_SYSCFG RCC_APB7ENR_SYSCFGEN +#define LL_APB7_GRP1_PERIPH_SPI3 RCC_APB7ENR_SPI3EN +#define LL_APB7_GRP1_PERIPH_LPUART1 RCC_APB7ENR_LPUART1EN +#define LL_APB7_GRP1_PERIPH_I2C3 RCC_APB7ENR_I2C3EN +#define LL_APB7_GRP1_PERIPH_LPTIM1 RCC_APB7ENR_LPTIM1EN +#if defined(COMP1) +#define LL_APB7_GRP1_PERIPH_COMP RCC_APB7ENR_COMPEN +#endif /* COMP1 */ +#define LL_APB7_GRP1_PERIPH_RTCAPB RCC_APB7ENR_RTCAPBEN +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions + * @{ + */ + +/** @defgroup BUS_LL_EF_AHB1 AHB1 + * @{ + */ +/** + * @brief Enable AHB1 peripherals clock. + * @rmtoll AHB1ENR GPDMA1EN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR FLASHEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR TSCEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR RAMCFGEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR GTZC1EN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR SRAM1EN LL_AHB1_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_TSC + * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG + * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB1ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB1ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB1 peripheral clock is enabled or not + * @rmtoll AHB1ENR GPDMA1EN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR FLASHEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR TSCEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR RAMCFGEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR GTZC1EN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR SRAM1EN LL_AHB1_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_TSC + * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG + * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable AHB1 peripherals clock. + * @rmtoll AHB1ENR GPDMA1EN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR FLASHEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR TSCEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR RAMCFGEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR GTZC1EN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR SRAM1EN LL_AHB1_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_TSC + * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG + * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB1ENR, Periphs); +} + +/** + * @brief Force AHB1 peripherals reset. + * @rmtoll AHB1RSTR GPDMA1RSTR LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR CRCRSTR LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR TSCRSTR LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR RAMCFGRSTR LL_AHB1_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_TSC + * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG + * @retval None + */ +__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->AHB1RSTR, Periphs); +} + +/** + * @brief Release AHB1 peripherals reset. + * @rmtoll AHB1RSTR GPDMA1RSTR LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR CRCRSTR LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR TSCRSTR LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR RAMCFGRSTR LL_AHB1_GRP1_ReleaseReset\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_TSC + * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG + * @retval None + */ +__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB1RSTR, Periphs); +} + +/** + * @brief Enable AHB1 peripheral clocks in Sleep and Stop modes + * @rmtoll AHB1SMENR GPDMA1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n + * AHB1SMENR FLASHSMEN LL_AHB1_GRP1_EnableClockStopSleep\n + * AHB1SMENR CRCSMEN LL_AHB1_GRP1_EnableClockStopSleep\n + * AHB1SMENR TSCSMEN LL_AHB1_GRP1_EnableClockStopSleep\n + * AHB1SMENR RAMCFGSMEN LL_AHB1_GRP1_EnableClockStopSleep\n + * AHB1SMENR GTZC1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n + * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_EnableClockStopSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_TSC + * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG + * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB1SMENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB1SMENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB1 peripheral clocks in Sleep and Stop modes is enabled or not + * @rmtoll AHB1SMENR GPDMA1SMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n + * AHB1SMENR FLASHSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n + * AHB1SMENR CRCSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n + * AHB1SMENR TSCSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n + * AHB1SMENR RAMCFGSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n + * AHB1SMENR GTZC1SMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n + * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_IsEnabledClockStopSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_TSC + * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG + * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClockStopSleep(uint32_t Periphs) +{ + return ((READ_BIT(RCC->AHB1SMENR, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable AHB1 peripheral clocks in Sleep and Stop modes + * @rmtoll AHB1SMENR GPDMA1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n + * AHB1SMENR FLASHSMEN LL_AHB1_GRP1_DisableClockStopSleep\n + * AHB1SMENR CRCSMEN LL_AHB1_GRP1_DisableClockStopSleep\n + * AHB1SMENR TSCSMEN LL_AHB1_GRP1_DisableClockStopSleep\n + * AHB1SMENR RAMCFGSMEN LL_AHB1_GRP1_DisableClockStopSleep\n + * AHB1SMENR GTZC1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n + * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_DisableClockStopSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_TSC + * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG + * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1 (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB1SMENR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH + * @{ + */ +/** + * @brief Enable AHB2 peripherals clock. + * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR GPIOBEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR GPIOCEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR GPIOHEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR AESEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR SAESEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR HSEMEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR PKAEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR SRAM2EN LL_AHB2_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_ALL + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB2_GRP1_PERIPH_AES + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM + * @arg @ref LL_AHB2_GRP1_PERIPH_PKA + * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2 + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB2ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB2 peripheral clock is enabled or not + * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR GPIOBEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR GPIOCEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR GPIOHEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR AESEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR HASHEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR SAESEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR HSEMEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR PKAEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR SRAM2EN LL_AHB2_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_ALL + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB2_GRP1_PERIPH_AES + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM + * @arg @ref LL_AHB2_GRP1_PERIPH_PKA + * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2 + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->AHB2ENR, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable AHB2 peripherals clock. + * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR GPIOBEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR GPIOCEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR GPIOHEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR AESEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR HASHEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR SAESEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR HSEMEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR PKAEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR SRAM2EN LL_AHB2_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_ALL + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB2_GRP1_PERIPH_AES + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM + * @arg @ref LL_AHB2_GRP1_PERIPH_PKA + * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2 + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB2ENR, Periphs); +} + +/** + * @brief Force AHB2 peripherals reset. + * @rmtoll AHB2RSTR GPIOARST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR GPIOBRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR GPIOCRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR GPIOHRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR AESRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR HASHRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR SAESRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR HSEMRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR PKARST LL_AHB2_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_ALL + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB2_GRP1_PERIPH_AES + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM + * @arg @ref LL_AHB2_GRP1_PERIPH_PKA + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->AHB2RSTR, Periphs); +} + +/** + * @brief Release AHB2 peripherals reset. + * @rmtoll AHB2RSTR GPIOARST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR GPIOBRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR GPIOCRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR GPIOHRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR AESRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR HASHRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR SAESRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR HSEMRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR PKARST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR SRAM1RST LL_AHB2_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_ALL + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB2_GRP1_PERIPH_AES + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HSEM + * @arg @ref LL_AHB2_GRP1_PERIPH_PKA + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB2RSTR, Periphs); +} + +/** + * @brief Enable AHB2 peripheral clocks in Sleep and Stop modes + * @rmtoll AHB2SMENR GPIOASMEN LL_AHB2_GRP1_EnableClockStopSleep\n + * AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_EnableClockStopSleep\n + * AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_EnableClockStopSleep\n + * AHB2SMENR GPIOHSMEN LL_AHB2_GRP1_EnableClockStopSleep\n + * AHB2SMENR AESSMEN LL_AHB2_GRP1_EnableClockStopSleep\n + * AHB2SMENR HASHSMEN LL_AHB2_GRP1_EnableClockStopSleep\n + * AHB2SMENR RNGSMEN LL_AHB2_GRP1_EnableClockStopSleep\n + * AHB2SMENR SAESSMEN LL_AHB2_GRP1_EnableClockStopSleep\n + * AHB2SMENR PKASMEN LL_AHB2_GRP1_EnableClockStopSleep\n + * AHB2SMENR SRAM2SMEN LL_AHB2_GRP1_EnableClockStopSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB2_GRP1_PERIPH_AES + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_PKA + * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2 + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP1_EnableClockStopSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB2SMENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB2SMENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB2 peripheral clocks in Sleep and Stop modes is enabled or not + * @rmtoll AHB2SMENR GPIOASMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n + * AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n + * AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n + * AHB2SMENR GPIOHSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n + * AHB2SMENR AESSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n + * AHB2SMENR HASHSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n + * AHB2SMENR RNGSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n + * AHB2SMENR SAESSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n + * AHB2SMENR PKASMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n + * AHB2SMENR SRAM2SMEN LL_AHB2_GRP1_IsEnabledClockStopSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB2_GRP1_PERIPH_AES + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_PKA + * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2 + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClockStopSleep(uint32_t Periphs) +{ + return ((READ_BIT(RCC->AHB2SMENR, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable AHB2 peripheral clocks in Sleep and Stop modes + * @rmtoll AHB2SMENR GPIOASMEN LL_AHB2_GRP1_DisableClockStopSleep\n + * AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_DisableClockStopSleep\n + * AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_DisableClockStopSleep\n + * AHB2SMENR GPIOHSMEN LL_AHB2_GRP1_DisableClockStopSleep\n + * AHB2SMENR AESSMEN LL_AHB2_GRP1_DisableClockStopSleep\n + * AHB2SMENR HASHSMEN LL_AHB2_GRP1_DisableClockStopSleep\n + * AHB2SMENR RNGSMEN LL_AHB2_GRP1_DisableClockStopSleep\n + * AHB2SMENR SAESSMEN LL_AHB2_GRP1_DisableClockStopSleep\n + * AHB2SMENR PKASMEN LL_AHB2_GRP1_DisableClockStopSleep\n + * AHB2SMENR SRAM2SMEN LL_AHB2_GRP1_DisableClockStopSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB2_GRP1_PERIPH_AES + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_PKA + * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2 + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP1_DisableClockStopSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB2SMENR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_AHB4 AHB4 + * @{ + */ +/** + * @brief Enable AHB4 peripherals clock. + * @rmtoll AHB4ENR PWREN LL_AHB4_GRP1_EnableClock\n + * AHB4ENR ADC4EN LL_AHB4_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_ALL + * @arg @ref LL_AHB4_GRP1_PERIPH_PWR + * @arg @ref LL_AHB4_GRP1_PERIPH_ADC4 + * @retval None + */ +__STATIC_INLINE void LL_AHB4_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB4ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB4ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB4 peripheral clock is enabled or not + * @rmtoll AHB4ENR PWREN LL_AHB4_GRP1_IsEnabledClock\n + * AHB4ENR ADC4EN LL_AHB4_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_ALL + * @arg @ref LL_AHB4_GRP1_PERIPH_PWR + * @arg @ref LL_AHB4_GRP1_PERIPH_ADC4 + * @retval State of Periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_AHB4_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->AHB4ENR, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable AHB4 peripherals clock. + * @rmtoll AHB4ENR PWREN LL_AHB4_GRP1_DisableClock\n + * AHB4ENR ADC4EN LL_AHB4_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_ALL + * @arg @ref LL_AHB4_GRP1_PERIPH_PWR + * @arg @ref LL_AHB4_GRP1_PERIPH_ADC4 + * @retval None + */ +__STATIC_INLINE void LL_AHB4_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB4ENR, Periphs); +} + +/** + * @brief Force AHB4 peripherals reset. + * @rmtoll AHB4RSTR ADC4RST LL_AHB4_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_ALL + * @arg @ref LL_AHB4_GRP1_PERIPH_ADC4 + * @retval None + */ +__STATIC_INLINE void LL_AHB4_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->AHB4RSTR, Periphs); +} + +/** + * @brief Release AHB4 peripherals reset. + * @rmtoll AHB4RSTR ADC4RST LL_AHB4_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_ALL + * @arg @ref LL_AHB4_GRP1_PERIPH_ADC4 + * @retval None + */ +__STATIC_INLINE void LL_AHB4_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB4RSTR, Periphs); +} + +/** + * @brief Enable AHB4 peripheral clocks in Sleep and Stop modes + * @rmtoll AHB4SMENR PWRSMEN LL_AHB4_GRP1_EnableClockStopSleep\n + * AHB4SMENR ADC4SMEN LL_AHB4_GRP1_EnableClockStopSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_ALL + * @arg @ref LL_AHB4_GRP1_PERIPH_PWR + * @arg @ref LL_AHB4_GRP1_PERIPH_ADC4 + * @retval None + */ +__STATIC_INLINE void LL_AHB4_GRP1_EnableClockStopSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB4SMENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB4SMENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB4 peripheral clocks in Sleep and Stop modes is enabled or not + * @rmtoll AHB4SMENR PWRSMEN LL_AHB4_GRP1_IsEnabledClockStopSleep\n + * AHB4SMENR ADC4SMEN LL_AHB4_GRP1_IsEnabledClockStopSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_ALL + * @arg @ref LL_AHB4_GRP1_PERIPH_PWR + * @arg @ref LL_AHB4_GRP1_PERIPH_ADC4 + * @retval State of Periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_AHB4_GRP1_IsEnabledClockStopSleep(uint32_t Periphs) +{ + return ((READ_BIT(RCC->AHB4SMENR, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable AHB4 peripheral clocks in Sleep and Stop modes + * @rmtoll AHB4SMENR PWRSMEN LL_AHB4_GRP1_DisableClockStopSleep\n + * AHB4SMENR ADC4SMEN LL_AHB4_GRP1_DisableClockStopSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB4_GRP1_PERIPH_ALL + * @arg @ref LL_AHB4_GRP1_PERIPH_PWR + * @arg @ref LL_AHB4_GRP1_PERIPH_ADC4 + * @retval None + */ +__STATIC_INLINE void LL_AHB4_GRP1_DisableClockStopSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB4SMENR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_AHB5 AHB5 + * @{ + */ +/** + * @brief Enable AHB5 peripherals clock. + * @rmtoll AHB5ENR RADIOEN LL_AHB5_GRP1_EnableClock\n + * AHB5ENR PTACONVEN LL_AHB5_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB5_GRP1_PERIPH_ALL + * @arg @ref LL_AHB5_GRP1_PERIPH_RADIO + * @arg @ref LL_AHB5_GRP1_PERIPH_PTACONV (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB5_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB5ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB5ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB5 peripheral clock is enabled or not + * @rmtoll AHB5ENR RADIOEN LL_AHB5_GRP1_IsEnabledClock\n + * AHB5ENR PTACONVEN LL_AHB5_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB5_GRP1_PERIPH_ALL + * @arg @ref LL_AHB5_GRP1_PERIPH_RADIO + * @arg @ref LL_AHB5_GRP1_PERIPH_PTACONV (*) + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_AHB5_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->AHB5ENR, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable AHB5 peripherals clock. + * @rmtoll AHB5ENR RADIOEN LL_AHB5_GRP1_DisableClock\n + * AHB5ENR PTACONVEN LL_AHB5_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB5_GRP1_PERIPH_ALL + * @arg @ref LL_AHB5_GRP1_PERIPH_RADIO + * @arg @ref LL_AHB5_GRP1_PERIPH_PTACONV (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB5_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB5ENR, Periphs); +} + +/** + * @brief Force AHB5 peripherals reset. + * @rmtoll AHB5RSTR RADIORST LL_AHB5_GRP1_ForceReset\n + * AHB5RSTR PTACONVRST LL_AHB5_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB5_GRP1_PERIPH_ALL + * @arg @ref LL_AHB5_GRP1_PERIPH_RADIO + * @arg @ref LL_AHB5_GRP1_PERIPH_PTACONV (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB5_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->AHB5RSTR, Periphs); +} + +/** + * @brief Release AHB5 peripherals reset. + * @rmtoll AHB5RSTR RADIORST LL_AHB5_GRP1_ReleaseReset\n + * AHB5RSTR PTACONVRST LL_AHB5_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB5_GRP1_PERIPH_ALL + * @arg @ref LL_AHB5_GRP1_PERIPH_RADIO + * @arg @ref LL_AHB5_GRP1_PERIPH_PTACONV (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB5_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB5RSTR, Periphs); +} + +/** + * @brief Enable AHB5 peripheral clocks in Sleep and Stop modes + * @rmtoll AHB5SMENR RADIOSMEN LL_AHB5_GRP1_EnableClockStopSleep\n + * AHB5SMENR PTACONVSMEN LL_AHB5_GRP1_EnableClockStopSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB5_GRP1_PERIPH_ALL + * @arg @ref LL_AHB5_GRP1_PERIPH_RADIO + * @arg @ref LL_AHB5_GRP1_PERIPH_PTACONV (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB5_GRP1_EnableClockStopSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB5SMENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB5SMENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB5 peripheral clocks in Sleep and Stop modes is enabled or not + * @rmtoll AHB5SMENR RADIOSMEN LL_AHB5_GRP1_IsEnabledClockStopSleep\n + * AHB5SMENR PTACONVSMEN LL_AHB5_GRP1_IsEnabledClockStopSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB5_GRP1_PERIPH_ALL + * @arg @ref LL_AHB5_GRP1_PERIPH_RADIO + * @arg @ref LL_AHB5_GRP1_PERIPH_PTACONV (*) + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_AHB5_GRP1_IsEnabledClockStopSleep(uint32_t Periphs) +{ + return ((READ_BIT(RCC->AHB5SMENR, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable AHB5 peripheral clocks in Sleep and Stop modes + * @rmtoll AHB5SMENR RADIOSMEN LL_AHB5_GRP1_DisableClockStopSleep\n + * AHB5SMENR PTACONVSMEN LL_AHB5_GRP1_DisableClockStopSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB5_GRP1_PERIPH_ALL + * @arg @ref LL_AHB5_GRP1_PERIPH_RADIO + * @arg @ref LL_AHB5_GRP1_PERIPH_PTACONV (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_AHB5_GRP1_DisableClockStopSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB5SMENR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_APB1 APB1 + * @{ + */ + +/** + * @brief Enable APB1 peripherals clock. + * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 TIM3EN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 WWDGEN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 USART2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR1 I2C1EN LL_APB1_GRP1_EnableClock\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_ALL + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB1ENR1, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB1ENR1, Periphs); + (void)tmpreg; +} + +/** + * @brief Enable APB1 peripherals clock. + * APB1ENR2 LPTIM2EN LL_APB1_GRP2_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_ALL + * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB1ENR2, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB1ENR2, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB1 peripheral clock is enabled or not + * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 TIM3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 WWDGEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 USART2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR1 I2C1EN LL_APB1_GRP1_IsEnabledClock\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_ALL + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 (*) + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APB1ENR1, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Check if APB1 peripheral clock is enabled or not + * APB1ENR2 LPTIM2EN LL_APB1_GRP2_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_ALL + * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 + * @retval State of Periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APB1ENR2, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable APB1 peripherals clock. + * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 TIM3EN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 WWDGEN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 USART2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR1 I2C1EN LL_APB1_GRP1_DisableClock\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_ALL + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1ENR1, Periphs); +} + +/** + * @brief Disable APB1 peripherals clock. + * APB1ENR2 LPTIM2EN LL_APB1_GRP2_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_ALL + * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1ENR2, Periphs); +} + +/** + * @brief Force APB1 peripherals reset. + * @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 TIM3RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 USART2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR1 I2C1RST LL_APB1_GRP1_ForceReset\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_ALL + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->APB1RSTR1, Periphs); +} + +/** + * @brief Force APB1 peripherals reset. + * APB1RSTR2 LPTIM2RST LL_APB1_GRP2_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_ALL + * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->APB1RSTR2, Periphs); +} + +/** + * @brief Release APB1 peripherals reset. + * @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 TIM3RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 USART2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR1 I2C1RST LL_APB1_GRP1_ReleaseReset\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_ALL + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1RSTR1, Periphs); +} + +/** + * @brief Release APB1 peripherals reset. + * APB1RSTR2 LPTIM2RST LL_APB1_GRP2_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_ALL + * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1RSTR2, Periphs); +} + +/** + * @brief Enable APB1 peripheral clocks in Sleep and Stop modes + * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_EnableClockStopSleep\n + * APB1SMENR1 TIM3SMEN LL_APB1_GRP1_EnableClockStopSleep\n + * APB1SMENR1 WWDGSMEN LL_APB1_GRP1_EnableClockStopSleep\n + * APB1SMENR1 USART2SMEN LL_APB1_GRP1_EnableClockStopSleep\n + * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_EnableClockStopSleep\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_ALL + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_EnableClockStopSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB1SMENR1, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB1SMENR1, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB1 peripheral clocks in Sleep and Stop modes is enabled or not + * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n + * APB1SMENR1 TIM3SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n + * APB1SMENR1 WWDGSMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n + * APB1SMENR1 USART2SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n + * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_ALL + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 (*) + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClockStopSleep(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APB1SMENR1, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable APB1 peripheral clocks in Sleep and Stop modes + * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_DisableClockStopSleep\n + * APB1SMENR1 TIM3SMEN LL_APB1_GRP1_DisableClockStopSleep\n + * APB1SMENR1 WWDGSMEN LL_APB1_GRP1_DisableClockStopSleep\n + * APB1SMENR1 USART2SMEN LL_APB1_GRP1_DisableClockStopSleep\n + * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_DisableClockStopSleep\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_ALL + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_DisableClockStopSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1SMENR1, Periphs); +} + +/** + * @brief Enable APB1 peripheral clocks in Sleep and Stop modes + * APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_EnableClockStopSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_ALL + * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP2_EnableClockStopSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB1SMENR2, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB1SMENR2, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB1 peripheral clocks in Sleep and Stop modes is enabled or not + * APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_IsEnabledClockStopSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_ALL + * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 + * @retval State of Periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClockStopSleep(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APB1SMENR2, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable APB1 peripheral clocks in Sleep and Stop modes + * APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_DisableClockStopSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_ALL + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP2_DisableClockStopSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1SMENR2, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_APB2 APB2 + * @{ + */ + +/** + * @brief Enable APB2 peripherals clock. + * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SAI1EN LL_APB2_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ALL + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB2ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB2ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB2 peripheral clock is enabled or not + * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ALL + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APB2ENR, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable APB2 peripherals clock. + * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SAI1EN LL_APB2_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ALL + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB2ENR, Periphs); +} + +/** + * @brief Force APB2 peripherals reset. + * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ALL + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->APB2RSTR, Periphs); +} + +/** + * @brief Release APB2 peripherals reset. + * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ALL + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB2RSTR, Periphs); +} + +/** + * @brief Enable APB2 peripheral clocks in Sleep and Stop modes + * @rmtoll APB2SMENR TIM1SMEN LL_APB2_GRP1_EnableClockStopSleep\n + * APB2SMENR SPI1SMEN LL_APB2_GRP1_EnableClockStopSleep\n + * APB2SMENR USART1SMEN LL_APB2_GRP1_EnableClockStopSleep\n + * APB2SMENR TIM16SMEN LL_APB2_GRP1_EnableClockStopSleep\n + * APB2SMENR TIM17SMEN LL_APB2_GRP1_EnableClockStopSleep\n + * APB2SMENR SAI1SMEN LL_APB2_GRP1_EnableClockStopSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ALL + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB2_GRP1_EnableClockStopSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB2SMENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB2SMENR, Periphs); + (void)tmpreg; +} + + +/** + * @brief Check if APB2 peripheral clocks in Sleep and Stop modes is enabled or not + * @rmtoll APB2SMENR TIM1SMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n + * APB2SMENR SPI1SMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n + * APB2SMENR USART1SMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n + * APB2SMENR TIM16SMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n + * APB2SMENR TIM17SMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n + * APB2SMENR SAI1SMEN LL_APB2_GRP1_IsEnabledClockStopSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ALL + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClockStopSleep(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APB2SMENR, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable APB2 peripheral clocks in Sleep and Stop modes + * @rmtoll APB2SMENR TIM1SMEN LL_APB2_GRP1_DisableClockStopSleep\n + * APB2SMENR SPI1SMEN LL_APB2_GRP1_DisableClockStopSleep\n + * APB2SMENR USART1SMEN LL_APB2_GRP1_DisableClockStopSleep\n + * APB2SMENR TIM16SMEN LL_APB2_GRP1_DisableClockStopSleep\n + * APB2SMENR TIM17SMEN LL_APB2_GRP1_DisableClockStopSleep\n + * APB2SMENR SAI1SMEN LL_APB2_GRP1_DisableClockStopSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ALL + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB2_GRP1_DisableClockStopSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB2SMENR, Periphs); +} + +/** + * @} + */ + + +/** @defgroup BUS_LL_EF_APB7 APB7 + * @{ + */ + +/** + * @brief Enable APB7 peripherals clock. + * @rmtoll APB7ENR SYSCFGEN LL_APB7_GRP1_EnableClock\n + * APB7ENR SPI3EN LL_APB7_GRP1_EnableClock\n + * APB7ENR LPUART1EN LL_APB7_GRP1_EnableClock\n + * APB7ENR I2C3EN LL_APB7_GRP1_EnableClock\n + * APB7ENR LPTIM1EN LL_APB7_GRP1_EnableClock\n + * APB7ENR COMPEN LL_APB7_GRP1_EnableClock\n + * APB7ENR RTCAPBEN LL_APB7_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB7_GRP1_PERIPH_ALL + * @arg @ref LL_APB7_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB7_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB7_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB7_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB7_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB7_GRP1_PERIPH_COMP (*) + * @arg @ref LL_APB7_GRP1_PERIPH_RTCAPB + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB7_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB7ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB7ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB7 peripheral clock is enabled or not + * @rmtoll APB7ENR SYSCFGEN LL_APB7_GRP1_IsEnabledClock\n + * APB7ENR SPI3EN LL_APB7_GRP1_IsEnabledClock\n + * APB7ENR LPUART1EN LL_APB7_GRP1_IsEnabledClock\n + * APB7ENR I2C3EN LL_APB7_GRP1_IsEnabledClock\n + * APB7ENR LPTIM1EN LL_APB7_GRP1_IsEnabledClock\n + * APB7ENR COMPEN LL_APB7_GRP1_IsEnabledClock\n + * APB7ENR RTCAPBEN LL_APB7_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB7_GRP1_PERIPH_ALL + * @arg @ref LL_APB7_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB7_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB7_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB7_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB7_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB7_GRP1_PERIPH_COMP (*) + * @arg @ref LL_APB7_GRP1_PERIPH_RTCAPB + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_APB7_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APB7ENR, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable APB2 peripherals clock. + * @rmtoll APB7ENR SYSCFGEN LL_APB7_GRP1_DisableClock\n + * APB7ENR SPI3EN LL_APB7_GRP1_DisableClock\n + * APB7ENR LPUART1EN LL_APB7_GRP1_DisableClock\n + * APB7ENR I2C3EN LL_APB7_GRP1_DisableClock\n + * APB7ENR LPTIM1EN LL_APB7_GRP1_DisableClock\n + * APB7ENR COMPEN LL_APB7_GRP1_DisableClock\n + * APB7ENR RTCAPBEN LL_APB7_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB7_GRP1_PERIPH_ALL + * @arg @ref LL_APB7_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB7_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB7_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB7_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB7_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB7_GRP1_PERIPH_COMP (*) + * @arg @ref LL_APB7_GRP1_PERIPH_RTCAPB + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB7_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB7ENR, Periphs); +} + +/** + * @brief Force APB7 peripherals reset. + * @rmtoll APB7RSTR SYSCFGRST LL_APB7_GRP1_ForceReset\n + * APB7RSTR SPI3RST LL_APB7_GRP1_ForceReset\n + * APB7RSTR LPUART1RST LL_APB7_GRP1_ForceReset\n + * APB7RSTR I2C3RST LL_APB7_GRP1_ForceReset\n + * APB7RSTR LPTIM1RST LL_APB7_GRP1_ForceReset\n + * APB7RSTR COMPRST LL_APB7_GRP1_ForceReset\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB7_GRP1_PERIPH_ALL + * @arg @ref LL_APB7_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB7_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB7_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB7_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB7_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB7_GRP1_PERIPH_COMP (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB7_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->APB7RSTR, Periphs); +} + +/** + * @brief Release APB7 peripherals reset. + * @rmtoll APB7RSTR SYSCFGRST LL_APB7_GRP1_ReleaseReset\n + * APB7RSTR SPI3RST LL_APB7_GRP1_ReleaseReset\n + * APB7RSTR LPUART1RST LL_APB7_GRP1_ReleaseReset\n + * APB7RSTR I2C3RST LL_APB7_GRP1_ReleaseReset\n + * APB7RSTR LPTIM1RST LL_APB7_GRP1_ReleaseReset\n + * APB7RSTR COMPRST LL_APB7_GRP1_ReleaseReset\n + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB7_GRP1_PERIPH_ALL + * @arg @ref LL_APB7_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB7_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB7_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB7_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB7_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB7_GRP1_PERIPH_COMP (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB7_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB7RSTR, Periphs); +} + +/** + * @brief Enable APB7 peripheral clocks in Sleep and Stop modes + * @rmtoll APB7SMENR SYSCFGSMEN LL_APB7_GRP1_EnableClockStopSleep\n + * APB7SMENR SPI3SMEN LL_APB7_GRP1_EnableClockStopSleep\n + * APB7SMENR LPUART1SMEN LL_APB7_GRP1_EnableClockStopSleep\n + * APB7SMENR I2C3SMEN LL_APB7_GRP1_EnableClockStopSleep\n + * APB7SMENR LPTIM1SMEN LL_APB7_GRP1_EnableClockStopSleep\n + * APB7SMENR COMPSMEN LL_APB7_GRP1_EnableClockStopSleep\n + * APB7SMENR RTCAPBSMEN LL_APB7_GRP1_EnableClockStopSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB7_GRP1_PERIPH_ALL + * @arg @ref LL_APB7_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB7_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB7_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB7_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB7_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB7_GRP1_PERIPH_COMP (*) + * @arg @ref LL_APB7_GRP1_PERIPH_RTCAPB + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB7_GRP1_EnableClockStopSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB7SMENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB7SMENR, Periphs); + (void)tmpreg; +} + + +/** + * @brief Check if APB7 peripheral clocks in Sleep and Stop modes is enabled or not + * @rmtoll APB7SMENR SYSCFGSMEN LL_APB7_GRP1_IsEnabledClockStopSleep\n + * APB7SMENR SPI3SMEN LL_APB7_GRP1_IsEnabledClockStopSleep\n + * APB7SMENR LPUART1SMEN LL_APB7_GRP1_IsEnabledClockStopSleep\n + * APB7SMENR I2C3SMEN LL_APB7_GRP1_IsEnabledClockStopSleep\n + * APB7SMENR LPTIM1SMEN LL_APB7_GRP1_IsEnabledClockStopSleep\n + * APB7SMENR COMPSMEN LL_APB7_GRP1_IsEnabledClockStopSleep\n + * APB7SMENR RTCAPBSMEN LL_APB7_GRP1_IsEnabledClockStopSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB7_GRP1_PERIPH_ALL + * @arg @ref LL_APB7_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB7_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB7_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB7_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB7_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB7_GRP1_PERIPH_COMP (*) + * @arg @ref LL_APB7_GRP1_PERIPH_RTCAPB + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_APB7_GRP1_IsEnabledClockStopSleep(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APB7SMENR, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable APB7 peripheral clocks in Sleep and Stop modes + * @rmtoll APB7SMENR SYSCFGSMEN LL_APB7_GRP1_DisableClockStopSleep\n + * APB7SMENR SPI3SMEN LL_APB7_GRP1_DisableClockStopSleep\n + * APB7SMENR LPUART1SMEN LL_APB7_GRP1_DisableClockStopSleep\n + * APB7SMENR I2C3SMEN LL_APB7_GRP1_DisableClockStopSleep\n + * APB7SMENR LPTIM1SMEN LL_APB7_GRP1_DisableClockStopSleep\n + * APB7SMENR COMPSMEN LL_APB7_GRP1_DisableClockStopSleep\n + * APB7SMENR RTCAPBSMEN LL_APB7_GRP1_DisableClockStopSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB7_GRP1_PERIPH_ALL + * @arg @ref LL_APB7_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB7_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB7_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB7_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB7_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB7_GRP1_PERIPH_COMP (*) + * @arg @ref LL_APB7_GRP1_PERIPH_RTCAPB + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_APB7_GRP1_DisableClockStopSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB7SMENR, Periphs); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(RCC) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WBAxx_LL_BUS_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_comp.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_comp.h new file mode 100644 index 0000000000..8124b00ac6 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_comp.h @@ -0,0 +1,849 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_ll_comp.h + * @author MCD Application Team + * @brief Header file of COMP LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_LL_COMP_H +#define STM32WBAxx_LL_COMP_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx.h" + +/** @addtogroup STM32WBAxx_LL_Driver + * @{ + */ + +#if defined (COMP1) || defined (COMP2) + +/** @defgroup COMP_LL COMP + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup COMP_LL_Private_Constants COMP Private Constants + * @{ + */ + +/* Internal mask for pair of comparators instances window mode: */ +/* To select into literals LL_COMP_WINDOWMODE_COMPx_INPUT_PLUS_COMMON */ +/* the relevant bits for: */ +/* (concatenation of multiple bits used in different registers) */ +/* - Comparator instance selected as master for window mode : register offset */ +/* - Window mode enable or disable: bit value */ +#define LL_COMP_WINDOWMODE_COMP_ODD_REGOFFSET_MASK (0x00000000UL) /* Register of COMP instance odd (COMP1_CSR, ...) + defined as reference register */ +#define LL_COMP_WINDOWMODE_COMP_EVEN_REGOFFSET_MASK (0x00000001UL) /* Register of COMP instance even (COMP2_CSR, ...) + offset vs register of COMP instance odd */ +#define LL_COMP_WINDOWMODE_COMPX_REGOFFSET_MASK (LL_COMP_WINDOWMODE_COMP_ODD_REGOFFSET_MASK \ + | LL_COMP_WINDOWMODE_COMP_EVEN_REGOFFSET_MASK) +#define LL_COMP_WINDOWMODE_COMPX_SETTING_MASK (COMP_CSR_WINMODE) +#define LL_COMP_WINDOWOUTPUT_COMPX_SETTING_MASK (COMP_CSR_WINOUT) +#define LL_COMP_WINDOWOUTPUT_BOTH_SETTING_MASK (COMP_CSR_WINOUT << 1UL) +#define LL_COMP_WINDOWOUTPUT_BOTH_POS_VS_WINDOW (1UL) + +/* COMP registers bits positions */ +#define LL_COMP_WINDOWMODE_BITOFFSET_POS (11UL) /* Value equivalent to POSITION_VAL(COMP_CSR_WINMODE) */ +#define LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS (30UL) /* Value equivalent to POSITION_VAL(COMP_CSR_VALUE) */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup COMP_LL_Private_Macros COMP Private Macros + * @{ + */ + +/** + * @brief Driver macro reserved for internal use: set a pointer to + * a register from a register basis from which an offset + * is applied. + * @param __REG__ Register basis from which the offset is applied. + * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers). + * @retval Pointer to register address + */ +#define __COMP_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \ + ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL)))) + +/** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup COMP_LL_ES_INIT COMP Exported Init structure + * @{ + */ + +/** + * @brief Structure definition of some features of COMP instance. + */ +typedef struct +{ + uint32_t PowerMode; /*!< Set comparator operating mode to adjust power and speed. + This parameter can be a value of @ref COMP_LL_EC_POWERMODE + This feature can be modified afterwards using unitary + function @ref LL_COMP_SetPowerMode(). */ + + uint32_t InputPlus; /*!< Set comparator input plus (non-inverting input). + This parameter can be a value of @ref COMP_LL_EC_INPUT_PLUS + This feature can be modified afterwards using unitary function + @ref LL_COMP_SetInputPlus(). */ + + uint32_t InputMinus; /*!< Set comparator input minus (inverting input). + This parameter can be a value of @ref COMP_LL_EC_INPUT_MINUS + This feature can be modified afterwards using unitary function + @ref LL_COMP_SetInputMinus(). */ + + uint32_t InputHysteresis; /*!< Set comparator hysteresis mode of the input minus. + This parameter can be a value of @ref COMP_LL_EC_INPUT_HYSTERESIS + This feature can be modified afterwards using unitary function + @ref LL_COMP_SetInputHysteresis(). */ + + uint32_t OutputPolarity; /*!< Set comparator output polarity. + This parameter can be a value of @ref COMP_LL_EC_OUTPUT_POLARITY + This feature can be modified afterwards using unitary function + @ref LL_COMP_SetOutputPolarity(). */ + + uint32_t OutputBlankingSource; /*!< Set comparator blanking source. + This parameter can be a value of @ref COMP_LL_EC_OUTPUT_BLANKING_SOURCE + This feature can be modified afterwards using unitary function + @ref LL_COMP_SetOutputBlankingSource(). */ + +} LL_COMP_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup COMP_LL_Exported_Constants COMP Exported Constants + * @{ + */ + + +/** @defgroup COMP_LL_EC_COMMON_WINDOWMODE Comparator common modes - Window mode + * @{ + */ +#define LL_COMP_WINDOWMODE_DISABLE (0x00000000UL) /*!< Window mode disable: Comparators 1 and 2 are independent */ +#define LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_WINMODE | LL_COMP_WINDOWMODE_COMP_EVEN_REGOFFSET_MASK) /*!< Window mode enable: Comparators instances pair COMP1 and COMP2 have their input plus connected together. The common input is COMP1 input plus (COMP2 input plus is no more accessible). */ +#define LL_COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON (COMP_CSR_WINMODE | LL_COMP_WINDOWMODE_COMP_ODD_REGOFFSET_MASK) /*!< Window mode enable: if used from COMP1 or COMP2 instance, comparators instances pair COMP1 and COMP2 have their input plus connected together, the common input is COMP2 input plus (COMP1 input plus is no more accessible). */ +/** + * @} + */ + +/** @defgroup COMP_LL_EC_COMMON_WINDOWOUTPUT Comparator common modes - Window output + * @{ + */ +#define LL_COMP_WINDOWOUTPUT_EACH_COMP (0x00000000UL) /*!< Window output default mode: Comparators output are indicating each their own state. To know window mode state: each comparator output must be read, if "((COMPx exclusive or COMPy) == 1)" then monitored signal is within comparators window. The same way, if both comparators output are high, then monitored signal is below window. */ +#define LL_COMP_WINDOWOUTPUT_COMP1 (COMP_CSR_WINOUT | LL_COMP_WINDOWMODE_COMP_ODD_REGOFFSET_MASK) /*!< Window output synthesized on COMP1 output: COMP1 output is no more indicating its own state, but global window mode state (logical high means monitored signal is within comparators window). Note: impacts only comparator output signal level (COMPx_OUT propagated to GPIO, EXTI lines, timers, ...), does not impact output digital state of comparator (COMPx_VALUE) always reflecting each comparator output state.*/ +#define LL_COMP_WINDOWOUTPUT_COMP2 (COMP_CSR_WINOUT | LL_COMP_WINDOWMODE_COMP_EVEN_REGOFFSET_MASK) /*!< Window output synthesized on COMP2 output: COMP2 output is no more indicating its own state, but global window mode state (logical high means monitored signal is within comparators window). Note: impacts only comparator output signal level (COMPx_OUT propagated to GPIO, EXTI lines, timers, ...), does not impact output digital state of comparator (COMPx_VALUE) always reflecting each comparator output state.*/ +#define LL_COMP_WINDOWOUTPUT_BOTH (COMP_CSR_WINOUT | LL_COMP_WINDOWMODE_COMP_EVEN_REGOFFSET_MASK | LL_COMP_WINDOWOUTPUT_BOTH_SETTING_MASK) /*!< Window output synthesized on both comparators output of pair of comparator selected (COMP1 and COMP2): both comparators outputs are no more indicating their own state, but global window mode state (logical high means monitored signal is within comparators window). This is a specific configuration (technically possible but not relevant from application point of view: 2 comparators output used for the same signal level), standard configuration for window mode is one of the settings above. */ +/** + * @} + */ + + +/** @defgroup COMP_LL_EC_POWERMODE Comparator modes - Power mode + * @{ + */ +#define LL_COMP_POWERMODE_HIGHSPEED (0x00000000UL) /*!< COMP power mode to high speed */ +#define LL_COMP_POWERMODE_MEDIUMSPEED (COMP_CSR_PWRMODE_0) /*!< COMP power mode to medium speed */ +/** + * @} + */ + +/** @defgroup COMP_LL_EC_INPUT_PLUS Comparator inputs - Input plus (input non-inverting) selection + * @{ + */ +#define LL_COMP_INPUT_PLUS_IO1 (0x00000000UL) /*!< Comparator input plus connected to IO1 (pin PA2 for COMP1, pin PA0 for COMP2) */ +/** + * @} + */ + +/** @defgroup COMP_LL_EC_INPUT_MINUS Comparator inputs - Input minus (input inverting) selection + * @{ + */ +#define LL_COMP_INPUT_MINUS_1_4VREFINT (0x00000000UL) /*!< Comparator input minus connected to 1/4 VrefInt */ +#define LL_COMP_INPUT_MINUS_1_2VREFINT ( COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to 1/2 VrefInt */ +#define LL_COMP_INPUT_MINUS_3_4VREFINT ( COMP_CSR_INMSEL_1 ) /*!< Comparator input minus connected to 3/4 VrefInt */ +#define LL_COMP_INPUT_MINUS_VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to VrefInt */ +#define LL_COMP_INPUT_MINUS_DAC1_CH1 ( COMP_CSR_INMSEL_2 ) /*!< Comparator input minus connected to DAC1 channel 1 (DAC_OUT1) */ +#define LL_COMP_INPUT_MINUS_DAC1_CH2 ( COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to DAC1 channel 2 (DAC_OUT2) */ +#define LL_COMP_INPUT_MINUS_IO1 ( COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 ) /*!< Comparator input minus connected to IO1 (pin PA1 for COMP1, pin PB9 for COMP2) */ +/** + * @} + */ + +/** @defgroup COMP_LL_EC_INPUT_HYSTERESIS Comparator input - Hysteresis + * @{ + */ +#define LL_COMP_HYSTERESIS_NONE (0x00000000UL) /*!< No hysteresis */ +#define LL_COMP_HYSTERESIS_LOW ( COMP_CSR_HYST_0) /*!< Hysteresis level low */ +#define LL_COMP_HYSTERESIS_MEDIUM (COMP_CSR_HYST_1 ) /*!< Hysteresis level medium */ +#define LL_COMP_HYSTERESIS_HIGH (COMP_CSR_HYST_1 | COMP_CSR_HYST_0) /*!< Hysteresis level high */ +/** + * @} + */ + +/** @defgroup COMP_LL_EC_OUTPUT_POLARITY Comparator output - Output polarity + * @{ + */ +#define LL_COMP_OUTPUTPOL_NONINVERTED (0x00000000UL) /*!< COMP output polarity is not inverted: comparator output is high when the plus (non-inverting) input is at a higher voltage than the minus (inverting) input */ +#define LL_COMP_OUTPUTPOL_INVERTED (COMP_CSR_POLARITY) /*!< COMP output polarity is inverted: comparator output is low when the plus (non-inverting) input is at a lower voltage than the minus (inverting) input */ +/** + * @} + */ + +/** @defgroup COMP_LL_EC_OUTPUT_BLANKING_SOURCE Comparator output - Blanking source + * @{ + */ +#define LL_COMP_BLANKINGSRC_NONE (0x00000000UL) /*!__REG__, (__VALUE__)) + +/** + * @brief Read a value in COMP register + * @param __INSTANCE__ comparator instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_COMP_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__) +/** + * @} + */ + +/** @defgroup COMP_LL_EM_HELPER_MACRO COMP helper macro + * @{ + */ + +/** + * @brief Helper macro to select the COMP common instance + * to which is belonging the selected COMP instance. + * @note COMP common register instance can be used to + * set parameters common to several COMP instances. + * Refer to functions having argument "COMPxy_COMMON" as parameter. + * @param __COMPx__ COMP instance + * @retval COMP common instance or value "0" if there is no COMP common instance. + */ +#define __LL_COMP_COMMON_INSTANCE(__COMPx__) (COMP12_COMMON) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup COMP_LL_Exported_Functions COMP Exported Functions + * @{ + */ + +/** @defgroup COMP_LL_EF_Configuration_comparator_common Configuration of COMP hierarchical scope: + * common to several COMP instances + * @{ + */ + + +/** + * @brief Set window mode of a pair of comparators instances + * (2 consecutive COMP instances COMP and COMP). + * @rmtoll CSR WINMODE LL_COMP_SetCommonWindowMode + * @param COMPxy_COMMON Comparator common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_COMP_COMMON_INSTANCE() ) + * @param WindowMode This parameter can be one of the following values: + * @arg @ref LL_COMP_WINDOWMODE_DISABLE + * @arg @ref LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON + * @arg @ref LL_COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON + * @retval None + */ +__STATIC_INLINE void LL_COMP_SetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COMMON, uint32_t WindowMode) +{ + /* Note: On this STM32 series, window mode can be set from any instance */ + /* of the pair of comparator instances. */ + register __IO uint32_t *preg = __COMP_PTR_REG_OFFSET(COMPxy_COMMON->CSR_ODD, + (WindowMode & LL_COMP_WINDOWMODE_COMPX_REGOFFSET_MASK)); + + /* Clear the potential previous setting of window mode */ + register __IO uint32_t *preg_clear = __COMP_PTR_REG_OFFSET(COMPxy_COMMON->CSR_ODD, + (~(WindowMode & LL_COMP_WINDOWMODE_COMPX_REGOFFSET_MASK) + & 0x1UL)); + CLEAR_BIT(*preg_clear, + COMP_CSR_WINMODE + ); + + /* Set window mode */ + MODIFY_REG(*preg, + COMP_CSR_WINMODE, + (WindowMode & LL_COMP_WINDOWMODE_COMPX_SETTING_MASK) + ); +} + +/** + * @brief Get window mode of a pair of comparators instances + * (2 consecutive COMP instances COMP and COMP). + * @rmtoll CSR WINMODE LL_COMP_GetCommonWindowMode + * @param COMPxy_COMMON Comparator common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_COMP_COMMON_INSTANCE() ) + * @retval Returned value can be one of the following values: + * @arg @ref LL_COMP_WINDOWMODE_DISABLE + * @arg @ref LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON + * @arg @ref LL_COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON + */ +__STATIC_INLINE uint32_t LL_COMP_GetCommonWindowMode(const COMP_Common_TypeDef *COMPxy_COMMON) +{ + /* Note: On this STM32 series, window mode can be set from any instance */ + /* of the pair of comparator instances. */ + register const uint32_t window_mode_comp_odd = (uint32_t)READ_BIT(COMPxy_COMMON->CSR_ODD, COMP_CSR_WINMODE); + register const uint32_t window_mode_comp_even = (uint32_t)READ_BIT(COMPxy_COMMON->CSR_EVEN, COMP_CSR_WINMODE); + + return (uint32_t)(window_mode_comp_odd + | window_mode_comp_even + | ((window_mode_comp_even >> LL_COMP_WINDOWMODE_BITOFFSET_POS) + * LL_COMP_WINDOWMODE_COMP_EVEN_REGOFFSET_MASK) + ); +} + +/** + * @brief Set window output of a pair of comparators instances + * (2 consecutive COMP instances COMP and COMP). + * @rmtoll CSR WINOUT LL_COMP_SetCommonWindowOutput + * @param COMPxy_COMMON Comparator common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_COMP_COMMON_INSTANCE() ) + * @param WindowOutput This parameter can be one of the following values: + * @arg @ref LL_COMP_WINDOWOUTPUT_EACH_COMP + * @arg @ref LL_COMP_WINDOWOUTPUT_COMP1 + * @arg @ref LL_COMP_WINDOWOUTPUT_COMP2 + * @retval None + */ +__STATIC_INLINE void LL_COMP_SetCommonWindowOutput(COMP_Common_TypeDef *COMPxy_COMMON, uint32_t WindowOutput) +{ + register __IO uint32_t *preg = __COMP_PTR_REG_OFFSET(COMPxy_COMMON->CSR_ODD, + (WindowOutput & LL_COMP_WINDOWMODE_COMPX_REGOFFSET_MASK)); + + /* Clear the potential previous setting of window output on the relevant comparator instance */ + /* (clear bit of window output unless specific case of setting of comparator both output selected) */ + register __IO uint32_t *preg_clear = __COMP_PTR_REG_OFFSET(COMPxy_COMMON->CSR_ODD, + (~(WindowOutput & LL_COMP_WINDOWMODE_COMPX_REGOFFSET_MASK) + & 0x1UL)); + MODIFY_REG(*preg_clear, + COMP_CSR_WINOUT, + ((WindowOutput & LL_COMP_WINDOWOUTPUT_BOTH_SETTING_MASK) >> LL_COMP_WINDOWOUTPUT_BOTH_POS_VS_WINDOW) + ); + + /* Set window output */ + MODIFY_REG(*preg, + COMP_CSR_WINOUT, + (WindowOutput & LL_COMP_WINDOWOUTPUT_COMPX_SETTING_MASK) + ); +} + +/** + * @brief Get window output of a pair of comparators instances + * (2 consecutive COMP instances COMP and COMP). + * @rmtoll CSR WINMODE LL_COMP_GetCommonWindowOutput + * @param COMPxy_COMMON Comparator common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_COMP_COMMON_INSTANCE() ) + * @retval Returned value can be one of the following values: + * @arg @ref LL_COMP_WINDOWOUTPUT_EACH_COMP + * @arg @ref LL_COMP_WINDOWOUTPUT_COMP1 + * @arg @ref LL_COMP_WINDOWOUTPUT_COMP2 + */ +__STATIC_INLINE uint32_t LL_COMP_GetCommonWindowOutput(const COMP_Common_TypeDef *COMPxy_COMMON) +{ + register const uint32_t window_output_comp_odd = (uint32_t)READ_BIT(COMPxy_COMMON->CSR_ODD, COMP_CSR_WINOUT); + register const uint32_t window_output_comp_even = (uint32_t)READ_BIT(COMPxy_COMMON->CSR_EVEN, COMP_CSR_WINOUT); + + /* Construct value corresponding to LL_COMP_WINDOWOUTPUT_xxx */ + return (uint32_t)(window_output_comp_odd + | window_output_comp_even + | ((window_output_comp_even >> COMP_CSR_WINOUT_Pos) * LL_COMP_WINDOWMODE_COMP_EVEN_REGOFFSET_MASK) + | (window_output_comp_odd + window_output_comp_even)); +} + + +/** + * @} + */ + +/** @defgroup COMP_LL_EF_Configuration_comparator_modes Configuration of comparator modes + * @{ + */ + +/** + * @brief Set comparator instance operating mode to adjust power and speed. + * @rmtoll CSR PWRMODE LL_COMP_SetPowerMode + * @param COMPx Comparator instance + * @param PowerMode This parameter can be one of the following values: + * @arg @ref LL_COMP_POWERMODE_HIGHSPEED + * @arg @ref LL_COMP_POWERMODE_MEDIUMSPEED + * @retval None + */ +__STATIC_INLINE void LL_COMP_SetPowerMode(COMP_TypeDef *COMPx, uint32_t PowerMode) +{ + MODIFY_REG(COMPx->CSR, COMP_CSR_PWRMODE, PowerMode); +} + +/** + * @brief Get comparator instance operating mode to adjust power and speed. + * @rmtoll CSR PWRMODE LL_COMP_GetPowerMode + * @param COMPx Comparator instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_COMP_POWERMODE_HIGHSPEED + * @arg @ref LL_COMP_POWERMODE_MEDIUMSPEED + */ +__STATIC_INLINE uint32_t LL_COMP_GetPowerMode(const COMP_TypeDef *COMPx) +{ + return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_PWRMODE)); +} + +/** + * @} + */ + +/** @defgroup COMP_LL_EF_Configuration_comparator_inputs Configuration of comparator inputs + * @{ + */ + +/** + * @brief Set comparator inputs minus (inverting) and plus (non-inverting). + * @note In case of comparator input selected to be connected to IO: + * GPIO pins are specific to each comparator instance. + * Refer to description of parameters or to reference manual. + * @note On this STM32 series, a voltage scaler is used + * when COMP input is based on VrefInt (VrefInt or subdivision + * of VrefInt): + * Voltage scaler requires a delay for voltage stabilization. + * Refer to device datasheet, parameter "tSTART_SCALER". + * @rmtoll CSR INMSEL LL_COMP_ConfigInputs\n + * CSR INPSEL LL_COMP_ConfigInputs\n + * @param COMPx Comparator instance + * @param InputMinus This parameter can be one of the following values: + * @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT + * @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT + * @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT + * @arg @ref LL_COMP_INPUT_MINUS_VREFINT + * @arg @ref LL_COMP_INPUT_MINUS_IO1 + * @param InputPlus This parameter can be one of the following values: + * @arg @ref LL_COMP_INPUT_PLUS_IO1 + * @retval None + */ +__STATIC_INLINE void LL_COMP_ConfigInputs(COMP_TypeDef *COMPx, uint32_t InputMinus, uint32_t InputPlus) +{ + MODIFY_REG(COMPx->CSR, + COMP_CSR_INMSEL | COMP_CSR_INPSEL, + InputMinus | InputPlus); +} + +/** + * @brief Set comparator input plus (non-inverting). + * @note In case of comparator input selected to be connected to IO: + * GPIO pins are specific to each comparator instance. + * Refer to description of parameters or to reference manual. + * @rmtoll CSR INPSEL LL_COMP_SetInputPlus + * @param COMPx Comparator instance + * @param InputPlus This parameter can be one of the following values: + * @arg @ref LL_COMP_INPUT_PLUS_IO1 + * @retval None + */ +__STATIC_INLINE void LL_COMP_SetInputPlus(COMP_TypeDef *COMPx, uint32_t InputPlus) +{ + MODIFY_REG(COMPx->CSR, COMP_CSR_INPSEL, InputPlus); +} + +/** + * @brief Get comparator input plus (non-inverting). + * @note In case of comparator input selected to be connected to IO: + * GPIO pins are specific to each comparator instance. + * Refer to description of parameters or to reference manual. + * @rmtoll CSR INPSEL LL_COMP_GetInputPlus + * @param COMPx Comparator instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_COMP_INPUT_PLUS_IO1 + */ +__STATIC_INLINE uint32_t LL_COMP_GetInputPlus(const COMP_TypeDef *COMPx) +{ + return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_INPSEL)); +} + +/** + * @brief Set comparator input minus (inverting). + * @note In case of comparator input selected to be connected to IO: + * GPIO pins are specific to each comparator instance. + * Refer to description of parameters or to reference manual. + * @note On this STM32 series, a voltage scaler is used + * when COMP input is based on VrefInt (VrefInt or subdivision + * of VrefInt): + * Voltage scaler requires a delay for voltage stabilization. + * Refer to device datasheet, parameter "tSTART_SCALER". + * @rmtoll CSR INMSEL LL_COMP_SetInputMinus + * @param COMPx Comparator instance + * @param InputMinus This parameter can be one of the following values: + * @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT + * @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT + * @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT + * @arg @ref LL_COMP_INPUT_MINUS_VREFINT + * @arg @ref LL_COMP_INPUT_MINUS_IO1 + * @retval None + */ +__STATIC_INLINE void LL_COMP_SetInputMinus(COMP_TypeDef *COMPx, uint32_t InputMinus) +{ + MODIFY_REG(COMPx->CSR, COMP_CSR_INMSEL, InputMinus); +} + +/** + * @brief Get comparator input minus (inverting). + * @note In case of comparator input selected to be connected to IO: + * GPIO pins are specific to each comparator instance. + * Refer to description of parameters or to reference manual. + * @rmtoll CSR INMSEL LL_COMP_GetInputMinus + * @param COMPx Comparator instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT + * @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT + * @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT + * @arg @ref LL_COMP_INPUT_MINUS_VREFINT + * @arg @ref LL_COMP_INPUT_MINUS_IO1 + */ +__STATIC_INLINE uint32_t LL_COMP_GetInputMinus(const COMP_TypeDef *COMPx) +{ + return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_INMSEL)); +} + +/** + * @brief Set comparator instance hysteresis mode of the input minus (inverting input). + * @rmtoll CSR HYST LL_COMP_SetInputHysteresis + * @param COMPx Comparator instance + * @param InputHysteresis This parameter can be one of the following values: + * @arg @ref LL_COMP_HYSTERESIS_NONE + * @arg @ref LL_COMP_HYSTERESIS_LOW + * @arg @ref LL_COMP_HYSTERESIS_MEDIUM + * @arg @ref LL_COMP_HYSTERESIS_HIGH + * @retval None + */ +__STATIC_INLINE void LL_COMP_SetInputHysteresis(COMP_TypeDef *COMPx, uint32_t InputHysteresis) +{ + MODIFY_REG(COMPx->CSR, COMP_CSR_HYST, InputHysteresis); +} + +/** + * @brief Get comparator instance hysteresis mode of the minus (inverting) input. + * @rmtoll CSR HYST LL_COMP_GetInputHysteresis + * @param COMPx Comparator instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_COMP_HYSTERESIS_NONE + * @arg @ref LL_COMP_HYSTERESIS_LOW + * @arg @ref LL_COMP_HYSTERESIS_MEDIUM + * @arg @ref LL_COMP_HYSTERESIS_HIGH + */ +__STATIC_INLINE uint32_t LL_COMP_GetInputHysteresis(const COMP_TypeDef *COMPx) +{ + return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_HYST)); +} + +/** + * @} + */ + +/** @defgroup COMP_LL_EF_Configuration_comparator_output Configuration of comparator output + * @{ + */ + +/** + * @brief Set comparator instance output polarity. + * @rmtoll CSR POLARITY LL_COMP_SetOutputPolarity + * @param COMPx Comparator instance + * @param OutputPolarity This parameter can be one of the following values: + * @arg @ref LL_COMP_OUTPUTPOL_NONINVERTED + * @arg @ref LL_COMP_OUTPUTPOL_INVERTED + * @retval None + */ +__STATIC_INLINE void LL_COMP_SetOutputPolarity(COMP_TypeDef *COMPx, uint32_t OutputPolarity) +{ + MODIFY_REG(COMPx->CSR, COMP_CSR_POLARITY, OutputPolarity); +} + +/** + * @brief Get comparator instance output polarity. + * @rmtoll CSR POLARITY LL_COMP_GetOutputPolarity + * @param COMPx Comparator instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_COMP_OUTPUTPOL_NONINVERTED + * @arg @ref LL_COMP_OUTPUTPOL_INVERTED + */ +__STATIC_INLINE uint32_t LL_COMP_GetOutputPolarity(const COMP_TypeDef *COMPx) +{ + return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_POLARITY)); +} + +/** + * @brief Set comparator instance blanking source. + * @note Blanking source may be specific to each comparator instance. + * Refer to description of parameters or to reference manual. + * @note Availability of parameters of blanking source from timer + * depends on timers availability on the selected device. + * @rmtoll CSR BLANKSEL LL_COMP_SetOutputBlankingSource + * @param COMPx Comparator instance + * @param BlankingSource This parameter can be one of the following values: + * @arg @ref LL_COMP_BLANKINGSRC_NONE + * @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1 (1) + * @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1 (1) + * @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1 (1) + * @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC4_COMP2 (2) + * + * (1) Parameter available only on comparator instance: COMP1. + * (2) Parameter available only on comparator instance: COMP2. + * @retval None + */ +__STATIC_INLINE void LL_COMP_SetOutputBlankingSource(COMP_TypeDef *COMPx, uint32_t BlankingSource) +{ + MODIFY_REG(COMPx->CSR, COMP_CSR_BLANKSEL, BlankingSource); +} + +/** + * @brief Get comparator instance blanking source. + * @note Availability of parameters of blanking source from timer + * depends on timers availability on the selected device. + * @note Blanking source may be specific to each comparator instance. + * Refer to description of parameters or to reference manual. + * @rmtoll CSR BLANKSEL LL_COMP_GetOutputBlankingSource + * @param COMPx Comparator instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_COMP_BLANKINGSRC_NONE + * @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1 (1) + * @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1 (1) + * @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1 (1) + * @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC4_COMP2 (2) + * + * (1) Parameter available only on comparator instance: COMP1. + * (2) Parameter available only on comparator instance: COMP2. + */ +__STATIC_INLINE uint32_t LL_COMP_GetOutputBlankingSource(const COMP_TypeDef *COMPx) +{ + return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_BLANKSEL)); +} + +/** + * @} + */ + +/** @defgroup COMP_LL_EF_Operation Operation on comparator instance + * @{ + */ + +/** + * @brief Enable comparator instance. + * @note After enable from off state, comparator requires a delay + * to reach reach propagation delay specification. + * Refer to device datasheet, parameter "tSTART". + * @rmtoll CSR EN LL_COMP_Enable + * @param COMPx Comparator instance + * @retval None + */ +__STATIC_INLINE void LL_COMP_Enable(COMP_TypeDef *COMPx) +{ + SET_BIT(COMPx->CSR, COMP_CSR_EN); +} + +/** + * @brief Disable comparator instance. + * @rmtoll CSR EN LL_COMP_Disable + * @param COMPx Comparator instance + * @retval None + */ +__STATIC_INLINE void LL_COMP_Disable(COMP_TypeDef *COMPx) +{ + CLEAR_BIT(COMPx->CSR, COMP_CSR_EN); +} + +/** + * @brief Get comparator enable state + * (0: COMP is disabled, 1: COMP is enabled) + * @rmtoll CSR EN LL_COMP_IsEnabled + * @param COMPx Comparator instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_COMP_IsEnabled(const COMP_TypeDef *COMPx) +{ + return ((READ_BIT(COMPx->CSR, COMP_CSR_EN) == (COMP_CSR_EN)) ? 1UL : 0UL); +} + +/** + * @brief Lock comparator instance. + * @note Once locked, comparator configuration can be accessed in read-only. + * @note The only way to unlock the comparator is a device hardware reset. + * @rmtoll CSR LOCK LL_COMP_Lock + * @param COMPx Comparator instance + * @retval None + */ +__STATIC_INLINE void LL_COMP_Lock(COMP_TypeDef *COMPx) +{ + SET_BIT(COMPx->CSR, COMP_CSR_LOCK); +} + +/** + * @brief Get comparator lock state + * (0: COMP is unlocked, 1: COMP is locked). + * @note Once locked, comparator configuration can be accessed in read-only. + * @note The only way to unlock the comparator is a device hardware reset. + * @rmtoll CSR LOCK LL_COMP_IsLocked + * @param COMPx Comparator instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_COMP_IsLocked(const COMP_TypeDef *COMPx) +{ + return ((READ_BIT(COMPx->CSR, COMP_CSR_LOCK) == (COMP_CSR_LOCK)) ? 1UL : 0UL); +} + +/** + * @brief Read comparator instance output level. + * @note The comparator output level depends on the selected polarity + * (Refer to function @ref LL_COMP_SetOutputPolarity()). + * If the comparator polarity is not inverted: + * - Comparator output is low when the input plus + * is at a lower voltage than the input minus + * - Comparator output is high when the input plus + * is at a higher voltage than the input minus + * If the comparator polarity is inverted: + * - Comparator output is high when the input plus + * is at a lower voltage than the input minus + * - Comparator output is low when the input plus + * is at a higher voltage than the input minus + * @rmtoll CSR VALUE LL_COMP_ReadOutputLevel + * @param COMPx Comparator instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_COMP_OUTPUT_LEVEL_LOW + * @arg @ref LL_COMP_OUTPUT_LEVEL_HIGH + */ +__STATIC_INLINE uint32_t LL_COMP_ReadOutputLevel(const COMP_TypeDef *COMPx) +{ + return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_VALUE) + >> LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup COMP_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_COMP_DeInit(COMP_TypeDef *COMPx); +ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, const LL_COMP_InitTypeDef *COMP_InitStruct); +void LL_COMP_StructInit(LL_COMP_InitTypeDef *COMP_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* COMP1 || COMP2 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WBAxx_LL_COMP_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_cortex.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_cortex.h new file mode 100644 index 0000000000..7ba4a5f9c8 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_cortex.h @@ -0,0 +1,1316 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_ll_cortex.h + * @author MCD Application Team + * @brief Header file of CORTEX LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LL CORTEX driver contains a set of generic APIs that can be + used by user: + (+) SysTick configuration used by LL_mDelay and LL_Init1msTick with + HCLK source or LL_Init1msTick_HCLK_Div8 or LL_Init1msTick_LSI or + LL_Init1msTick_LSE with external source + (+) Low power mode configuration (SCB register of Cortex-MCU) + (+) API to access to MCU info (CPUID register) + (+) API to enable fault handler (SHCSR accesses) + (+) API to enable and disable the MPU secure and non-secure + (+) API to configure the region of MPU secure and non-secure + (+) API to configure the attributes region of MPU secure and non-secure + + @endverbatim + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_LL_CORTEX_H +#define STM32WBAxx_LL_CORTEX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx.h" + +/** @addtogroup STM32WBAxx_LL_Driver + * @{ + */ + +/** @defgroup CORTEX_LL CORTEX + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup CORTEX_LL_EC_REGION_ACCESS CORTEX LL MPU Region Access Attributes + * @{ + */ +/* Register MPU_RBAR (Cortex-M33) : bits [4:0] */ +#define MPU_ACCESS_MSK (MPU_RBAR_SH_Msk|MPU_RBAR_AP_Msk|MPU_RBAR_XN_Msk) +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CORTEX_LL_Exported_Constants CORTEX LL Exported Constants + * @{ + */ + +/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source + * @{ + */ +#define LL_SYSTICK_CLKSOURCE_EXTERNAL 0x00000000U /*!< External clock source selected as + SysTick clock source */ +#define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick + clock source */ + +/** Legacy definitions for compatibility purpose +@cond 0 +*/ +#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 LL_SYSTICK_CLKSOURCE_EXTERNAL +/** +@endcond +*/ + +/** @defgroup CORTEX_LL_EC_FAULT Handler Fault type + * @{ + */ +#define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */ +#define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */ +#define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */ +#define LL_HANDLER_FAULT_SECURE SCB_SHCSR_SECUREFAULTENA_Msk /*!< Secure fault */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_MPU_HFNMI_PRIVDEF_Control CORTEX LL MPU HFNMI and PRIVILEGED Access control + * @{ + */ +#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0U +#define LL_MPU_CTRL_HARDFAULT_NMI 2U +#define LL_MPU_CTRL_PRIVILEGED_DEFAULT 4U +#define LL_MPU_CTRL_HFNMI_PRIVDEF 6U +/** + * @} + */ + +/** @defgroup CORTEX_LL_MPU_Attributes CORTEX LL MPU Attributes + * @{ + */ +#define LL_MPU_DEVICE_nGnRnE 0x0U /* Device, noGather, noReorder, noEarly acknowledge. */ +#define LL_MPU_DEVICE_nGnRE 0x4U /* Device, noGather, noReorder, Early acknowledge. */ +#define LL_MPU_DEVICE_nGRE 0x8U /* Device, noGather, Reorder, Early acknowledge. */ +#define LL_MPU_DEVICE_GRE 0xCU /* Device, Gather, Reorder, Early acknowledge. */ + +#define LL_MPU_WRITE_THROUGH 0x0U /* Normal memory, write-through. */ +#define LL_MPU_NOT_CACHEABLE 0x4U /* Normal memory, non-cacheable. */ +#define LL_MPU_WRITE_BACK 0x4U /* Normal memory, write-back. */ + +#define LL_MPU_TRANSIENT 0x0U /* Normal memory, transient. */ +#define LL_MPU_NON_TRANSIENT 0x8U /* Normal memory, non-transient. */ + +#define LL_MPU_NO_ALLOCATE 0x0U /* Normal memory, no allocate. */ +#define LL_MPU_W_ALLOCATE 0x1U /* Normal memory, write allocate. */ +#define LL_MPU_R_ALLOCATE 0x2U /* Normal memory, read allocate. */ +#define LL_MPU_RW_ALLOCATE 0x3U /* Normal memory, read/write allocate. */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_MPU_Region_Enable CORTEX LL MPU Region Enable + * @{ + */ +#define LL_MPU_REGION_ENABLE 1U +#define LL_MPU_REGION_DISABLE 0U +/** + * @} + */ + +/** @defgroup CORTEX_LL_MPU_Instruction_Access CORTEX LL MPU Instruction Access + * @{ + */ +#define LL_MPU_INSTRUCTION_ACCESS_ENABLE (0U << MPU_RBAR_XN_Pos) +#define LL_MPU_INSTRUCTION_ACCESS_DISABLE (1U << MPU_RBAR_XN_Pos) +/** + * @} + */ + +/** @defgroup CORTEX_LL_MPU_Access_Shareable CORTEX LL MPU Instruction Access Shareable + * @{ + */ +#define LL_MPU_ACCESS_NOT_SHAREABLE (0U << MPU_RBAR_SH_Pos) +#define LL_MPU_ACCESS_OUTER_SHAREABLE (2U << MPU_RBAR_SH_Pos) +#define LL_MPU_ACCESS_INNER_SHAREABLE (3U << MPU_RBAR_SH_Pos) +/** + * @} + */ + +/** @defgroup CORTEX_LL_MPU_Region_Permission_Attributes CORTEX LL MPU Region Permission Attributes + * @{ + */ +#define LL_MPU_REGION_PRIV_RW (0U << MPU_RBAR_AP_Pos) +#define LL_MPU_REGION_ALL_RW (1U << MPU_RBAR_AP_Pos) +#define LL_MPU_REGION_PRIV_RO (2U << MPU_RBAR_AP_Pos) +#define LL_MPU_REGION_ALL_RO (3U << MPU_RBAR_AP_Pos) +/** + * @} + */ + +/** @defgroup CORTEX_LL_MPU_Region_Index CORTEX LL MPU Region Index + * @{ + */ +#define LL_MPU_REGION_NUMBER0 0U +#define LL_MPU_REGION_NUMBER1 1U +#define LL_MPU_REGION_NUMBER2 2U +#define LL_MPU_REGION_NUMBER3 3U +#define LL_MPU_REGION_NUMBER4 4U +#define LL_MPU_REGION_NUMBER5 5U +#define LL_MPU_REGION_NUMBER6 6U +#define LL_MPU_REGION_NUMBER7 7U +/** + * @} + */ + +/** @defgroup CORTEX_LL_MPU_Attributes_Index CORTEX LL MPU Memory Attributes Index + * @{ + */ +#define LL_MPU_ATTRIBUTES_NUMBER0 0U +#define LL_MPU_ATTRIBUTES_NUMBER1 1U +#define LL_MPU_ATTRIBUTES_NUMBER2 2U +#define LL_MPU_ATTRIBUTES_NUMBER3 3U +#define LL_MPU_ATTRIBUTES_NUMBER4 4U +#define LL_MPU_ATTRIBUTES_NUMBER5 5U +#define LL_MPU_ATTRIBUTES_NUMBER6 6U +#define LL_MPU_ATTRIBUTES_NUMBER7 7U +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup CORTEX_LL_Exported_Functions CORTEX LL Exported Functions + * @{ + */ + +/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK + * @brief CORTEX SYSTICK LL module driver + * @{ + */ + +/** + * @brief This function checks if the Systick counter flag is active or not. + * @note It can be used in timeout function on application side. + * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void) +{ + return (((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)) ? 1UL : 0UL); +} + +/** + * @brief Configures the SysTick clock source + * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_SYSTICK_CLKSOURCE_EXTERNAL + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source) +{ + if (Source == LL_SYSTICK_CLKSOURCE_HCLK) + { + SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); + } + else + { + CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); + } +} + +/** + * @brief Get the SysTick clock source + * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSTICK_CLKSOURCE_EXTERNAL + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK + */ +__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void) +{ + return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); +} + +/** + * @brief Enable SysTick exception request + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_EnableIT(void) +{ + SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Disable SysTick exception request + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_DisableIT(void) +{ + CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Checks if the SYSTICK interrupt is enabled or disabled. + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void) +{ + return ((READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE CORTEX LL LOW POWER MODE + * @{ + */ + +/** + * @brief Processor uses sleep as its low power mode + * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableSleep(void) +{ + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); +} + +/** + * @brief Processor uses deep sleep as its low power mode + * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableDeepSleep(void) +{ + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); +} + +/** + * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode. + * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an + * empty main application. + * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void) +{ + /* Set SLEEPONEXIT bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + +/** + * @brief Do not sleep when returning to Thread mode. + * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit + * @retval None + */ +__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void) +{ + /* Clear SLEEPONEXIT bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + +/** + * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the + * processor. + * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableEventOnPend(void) +{ + /* Set SEVEONPEND bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + +/** + * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are + * excluded + * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend + * @retval None + */ +__STATIC_INLINE void LL_LPM_DisableEventOnPend(void) +{ + /* Clear SEVEONPEND bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + +/** + * @} + */ + +/** @defgroup CORTEX_LL_EF_HANDLER CORTEX LL HANDLER + * @{ + */ + +/** + * @brief Enable a fault in System handler control register (SHCSR) + * @rmtoll SCB_SHCSR USGFAULTENA LL_HANDLER_EnableFault\n + * SCB_SHCSR BUSFAULTENA LL_HANDLER_EnableFault\n + * SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault\n + * SCB_SHCSR SECUREFAULTENA LL_HANDLER_EnableFault + * @param Fault This parameter can be a combination of the following values: + * @arg @ref LL_HANDLER_FAULT_USG + * @arg @ref LL_HANDLER_FAULT_BUS + * @arg @ref LL_HANDLER_FAULT_MEM + * @arg @ref LL_HANDLER_FAULT_SECURE (*) + * + * (*) value applicable in secure when the system implements the security. + * @retval None + */ +__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault) +{ + /* Enable the system handler fault */ + SET_BIT(SCB->SHCSR, Fault); +} + +/** + * @brief Disable a fault in System handler control register (SHCSR) + * @rmtoll SCB_SHCSR USGFAULTENA LL_HANDLER_DisableFault\n + * SCB_SHCSR BUSFAULTENA LL_HANDLER_DisableFault\n + * SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault\n + * SCB_SHCSR SECUREFAULTENA LL_HANDLER_DisableFault + * @param Fault This parameter can be a combination of the following values: + * @arg @ref LL_HANDLER_FAULT_USG + * @arg @ref LL_HANDLER_FAULT_BUS + * @arg @ref LL_HANDLER_FAULT_MEM + * @arg @ref LL_HANDLER_FAULT_SECURE (*) + * + * (*) value applicable in secure when the system implements the security. + * @retval None + */ +__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault) +{ + /* Disable the system handler fault */ + CLEAR_BIT(SCB->SHCSR, Fault); +} + +/** + * @} + */ + +/** @defgroup CORTEX_LL_EF_MCU_INFO CORTEX LL MCU INFO + * @{ + */ + +/** + * @brief Get Implementer code + * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer + * @retval Value should be equal to 0x41 for ARM + */ +__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos); +} + +/** + * @brief Get Variant number (The r value in the rnpn product revision identifier) + * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant + * @retval Value between 0 and 255 (0x0: revision 0) + */ +__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos); +} + +/** + * @brief Get Architecture version + * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetArchitecture + * @retval Value should be equal to 0xF for Cortex-M33 ("ARMv8-M with Main Extension") + */ +__STATIC_INLINE uint32_t LL_CPUID_GetArchitecture(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos); +} + +/** + * @brief Get Part number + * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo + * @retval Value should be equal to 0xD21 for Cortex-M33 + */ +__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos); +} + +/** + * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release) + * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision + * @retval Value between 0 and 255 (0x1: patch 1) + */ +__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos); +} + +/** + * @} + */ + +/** @defgroup CORTEX_LL_EF_MPU CORTEX LL MPU + * @{ + */ + +/** + * @brief Enable MPU with input options + * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable + * @param MPU_Control This parameter can be one of the following values: + * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE + * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI + * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT + * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF + * @retval None + */ +__STATIC_INLINE void LL_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before enabling the MPU */ + + /* Enable the MPU*/ + MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_Control; + + /* Follow ARM recommendation with */ + /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */ + __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */ + __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Enable non-secure MPU with input options + * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable + * @param MPU_Control This parameter can be one of the following values: + * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE + * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI + * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT + * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF + * @retval None + */ +__STATIC_INLINE void LL_MPU_Enable_NS(uint32_t MPU_Control) +{ + __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before enabling the MPU */ + + /* Enable the MPU*/ + MPU_NS->CTRL = MPU_CTRL_ENABLE_Msk | MPU_Control; + + /* Follow ARM recommendation with */ + /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */ + __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */ + __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */ +} +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @brief Disable MPU + * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable + * @retval None + */ +__STATIC_INLINE void LL_MPU_Disable(void) +{ + __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before disabling the MPU */ + + /* Disable MPU*/ + WRITE_REG(MPU->CTRL, 0U); + + /* Follow ARM recommendation with */ + /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */ + __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */ + __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Disable the non-secure MPU + * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable_NS + * @retval None + */ +__STATIC_INLINE void LL_MPU_Disable_NS(void) +{ + __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before disabling the MPU */ + + /* Disable MPU*/ + WRITE_REG(MPU_NS->CTRL, 0U); + + /* Follow ARM recommendation with */ + /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */ + __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */ + __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */ +} +#endif /* __ARM_FEATURE_CMSE */ + + +/** + * @brief Check if MPU is enabled or not + * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void) +{ + return ((READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)) ? 1UL : 0UL); +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Check if non-secure MPU is enabled or not + * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled_NS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_MPU_IsEnabled_NS(void) +{ + return ((READ_BIT(MPU_NS->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)) ? 1UL : 0UL); +} +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @brief Enable a MPU region + * @rmtoll MPU_RLAR ENABLE LL_MPU_EnableRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @note cortex-M33 supports 8 secure and 8 non secure regions. + * @retval None + */ +__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + + /* Enable the MPU region */ + SET_BIT(MPU->RLAR, MPU_RLAR_EN_Msk); +} + +/** + * @brief Check if MPU region is enabled or not + * @rmtoll MPU_RNR ENABLE LL_MPU_IsEnabled_Region + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @note cortex-M33 supports 8 secure and 8 non secure regions. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_MPU_IsEnabled_Region(uint32_t Region) +{ + /* Set region index */ + WRITE_REG(MPU->RNR, Region); + + /* Return MPU region status */ + return ((READ_BIT(MPU->RLAR, MPU_RLAR_EN_Msk) == (MPU_RLAR_EN_Msk)) ? 1UL : 0UL); +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Enable a non-secure MPU region + * @rmtoll MPU_RLAR ENABLE LL_MPU_EnableRegion_NS + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @note cortex-M33 supports 8 secure and 8 non secure regions. + * @retval None + */ +__STATIC_INLINE void LL_MPU_EnableRegion_NS(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU_NS->RNR, Region); + + /* Enable the MPU region */ + SET_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk); +} + +/** + * @brief Check if non-secure MPU region is enabled or not + * @rmtoll MPU_RNR ENABLE LL_MPU_IsEnabled_Region_NS + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @note cortex-M33 supports 8 secure and 8 non secure regions. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_MPU_IsEnabled_Region_NS(uint32_t Region) +{ + /* Set region index */ + WRITE_REG(MPU_NS->RNR, Region); + + /* Return non-secure MPU region status */ + return ((READ_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk) == (MPU_RLAR_EN_Msk)) ? 1UL : 0UL); +} +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @brief Disable a MPU region + * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n + * MPU_RLAR ENABLE LL_MPU_DisableRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @note cortex-M33 supports 8 secure and 8 non secure regions. + * @retval None + */ +__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + + /* Disable the MPU region */ + CLEAR_BIT(MPU->RLAR, MPU_RLAR_EN_Msk); +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Disable a non-secure MPU region + * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion_NS\n + * MPU_RLAR ENABLE LL_MPU_DisableRegion_NS\n + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @note cortex-M33 supports 8 secure and 8 non secure regions. + * @retval None + */ +__STATIC_INLINE void LL_MPU_DisableRegion_NS(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU_NS->RNR, Region); + + /* Disable the MPU region */ + CLEAR_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk); +} +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @brief Configure and enable a MPU region + * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n + * MPU_RBAR ADDR LL_MPU_ConfigRegion\n + * MPU_RLAR ADDR LL_MPU_ConfigRegion\n + * MPU_RBAR XN LL_MPU_ConfigRegion\n + * MPU_RBAR AP LL_MPU_ConfigRegion\n + * MPU_RBAR SH LL_MPU_ConfigRegion\n + * MPU_RLAR EN LL_MPU_ConfigRegion\n + * MPU_RLAR AttrIndx LL_MPU_ConfigRegion\n + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @param Attributes This parameter can be a combination of the following values: + * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE + * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE + * or @ref LL_MPU_ACCESS_INNER_SHAREABLE + * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO + * or @ref LL_MPU_REGION_ALL_RO + * @param AttrIndx This parameter can be one of the following values: + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7 + * @param BaseAddress Value of region base address + * @param LimitAddress Value of region limit address + * @note cortex-M33 supports 8 secure and 8 non secure regions. + * @retval None + */ +__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t Attributes, uint32_t AttrIndx, uint32_t BaseAddress, + uint32_t LimitAddress) +{ + /* Set region index */ + WRITE_REG(MPU->RNR, Region); + + /* Set base address */ + MPU->RBAR |= Attributes; + + /* Set region base address and region access attributes */ + WRITE_REG(MPU->RBAR, ((BaseAddress & MPU_RBAR_BASE_Msk) | Attributes)); + + /* Set region limit address, memory attributes index and enable region */ + WRITE_REG(MPU->RLAR, ((LimitAddress & MPU_RLAR_LIMIT_Msk) | AttrIndx | MPU_RLAR_EN_Msk)); +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Configure and enable a non-secure MPU region + * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion_NS\n + * MPU_RBAR ADDR LL_MPU_ConfigRegion_NS\n + * MPU_RLAR ADDR LL_MPU_ConfigRegion_NS\n + * MPU_RBAR XN LL_MPU_ConfigRegion_NS\n + * MPU_RBAR AP LL_MPU_ConfigRegion_NS\n + * MPU_RBAR SH LL_MPU_ConfigRegion_NS\n + * MPU_RLAR EN LL_MPU_ConfigRegion_NS\n + * MPU_RLAR AttrIndx LL_MPU_ConfigRegion_NS\n + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @param Attributes This parameter can be a combination of the following values: + * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE + * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE + * or @ref LL_MPU_ACCESS_INNER_SHAREABLE + * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO + * or @ref LL_MPU_REGION_ALL_RO + * @param AttrIndx This parameter can be one of the following values: + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7 + * @param BaseAddress Value of region base address + * @param LimitAddress Value of region limit address + * @note cortex-M33 supports 8 secure and 8 non secure regions. + * @retval None + */ +__STATIC_INLINE void LL_MPU_ConfigRegion_NS(uint32_t Region, uint32_t Attributes, uint32_t AttrIndx, + uint32_t BaseAddress, uint32_t LimitAddress) +{ + /* Set Region number */ + WRITE_REG(MPU_NS->RNR, Region); + + /* Set region base address and region access attributes */ + WRITE_REG(MPU_NS->RBAR, ((BaseAddress & MPU_RBAR_BASE_Msk) | Attributes)); + + /* Set region limit address, memory attributes index and enable region */ + WRITE_REG(MPU_NS->RLAR, ((LimitAddress & MPU_RLAR_LIMIT_Msk) | AttrIndx | MPU_RLAR_EN_Msk)); +} +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @brief Configure a MPU region address range + * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegionAddress\n + * MPU_RBAR ADDR LL_MPU_ConfigRegionAddress\n + * MPU_RLAR ADDR LL_MPU_ConfigRegionAddress\n + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @param BaseAddress Value of region base address + * @param LimitAddress Value of region limit address + * @note cortex-M33 supports 8 secure and 8 non secure regions. + * @retval None + */ +__STATIC_INLINE void LL_MPU_ConfigRegionAddress(uint32_t Region, uint32_t BaseAddress, uint32_t LimitAddress) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + + /* Modify region base address */ + MODIFY_REG(MPU->RBAR, MPU_RBAR_BASE_Msk, (BaseAddress & MPU_RBAR_BASE_Msk)); + + /* Modify region limit address */ + MODIFY_REG(MPU->RLAR, MPU_RLAR_LIMIT_Msk, (LimitAddress & MPU_RLAR_LIMIT_Msk)); +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Configure a non-secure MPU region address range + * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegionAddress_NS\n + * MPU_RBAR ADDR LL_MPU_ConfigRegionAddress_NS\n + * MPU_RLAR ADDR LL_MPU_ConfigRegionAddress_NS\n + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @param BaseAddress Value of region base address + * @param LimitAddress Value of region limit address + * @note cortex-M33 supports 8 secure and 8 non secure regions. + * @retval None + */ +__STATIC_INLINE void LL_MPU_ConfigRegionAddress_NS(uint32_t Region, uint32_t BaseAddress, uint32_t LimitAddress) +{ + /* Set Region number */ + WRITE_REG(MPU_NS->RNR, Region); + + /* Set base address */ + MODIFY_REG(MPU_NS->RBAR, MPU_RBAR_BASE_Msk, (BaseAddress & MPU_RBAR_BASE_Msk)); + + /* Set limit address */ + MODIFY_REG(MPU_NS->RLAR, MPU_RLAR_LIMIT_Msk, (LimitAddress & MPU_RLAR_LIMIT_Msk)); +} +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @brief Configure a MPU attributes index + * @rmtoll MPU_MAIR0 Attribute LL_MPU_ConfigAttributes\n + * MPU_MAIR1 Attribute LL_MPU_ConfigAttributes\n + * @param AttIndex This parameter can be one of the following values: + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7 + * @param Attributes This parameter can be a combination of @ref CORTEX_LL_MPU_Attributes + * @retval None + */ +__STATIC_INLINE void LL_MPU_ConfigAttributes(uint32_t AttIndex, uint32_t Attributes) +{ + /* When selected index is in range [0;3] */ + if (AttIndex < LL_MPU_ATTRIBUTES_NUMBER4) + { + /* Modify Attr field of MPU_MAIR0 accordingly */ + MODIFY_REG(MPU->MAIR0, (0xFFU << (AttIndex * 8U)), (Attributes << (AttIndex * 8U))); + } + /* When selected index is in range [4;7] */ + else + { + /* Modify Attr field of MPU_MAIR1 accordingly */ + MODIFY_REG(MPU->MAIR1, (0xFFU << ((AttIndex - 4U) * 8U)), (Attributes << ((AttIndex - 4U) * 8U))); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Configure a non-secure MPU attributes index + * @rmtoll MPU_MAIR0 Attribute LL_MPU_ConfigAttributes_NS\n + * MPU_MAIR1 Attribute LL_MPU_ConfigAttributes_NS\n + * @param AttIndex This parameter can be one of the following values: + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7 + * @param Attributes This parameter can be a combination of @ref CORTEX_LL_MPU_Attributes + * @retval None + */ +__STATIC_INLINE void LL_MPU_ConfigAttributes_NS(uint32_t AttIndex, uint32_t Attributes) +{ + /* When selected index is in range [0;3] */ + if (AttIndex < LL_MPU_ATTRIBUTES_NUMBER4) + { + /* Modify Attr field of MPU_MAIR0_NS accordingly */ + MODIFY_REG(MPU_NS->MAIR0, (0xFFU << (AttIndex * 8U)), (Attributes << (AttIndex * 8U))); + } + /* When selected index is in range [4;7] */ + else + { + /* Modify Attr field of MPU_MAIR1_NS accordingly */ + MODIFY_REG(MPU_NS->MAIR1, (0xFFU << ((AttIndex - 4U) * 8U)), (Attributes << ((AttIndex - 4U) * 8U))); + } +} +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @brief Configure a MPU region limit address + * @rmtoll MPU_RNR REGION LL_MPU_SetRegionLimitAddress\n + * MPU_RLAR ADDR LL_MPU_SetRegionLimitAddress\n + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @param LimitAddress Value of region limit address + * @note cortex-M33 supports 8 secure and 8 non secure regions. + * @retval None + */ +__STATIC_INLINE void LL_MPU_SetRegionLimitAddress(uint32_t Region, uint32_t LimitAddress) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + + /* Set limit address */ + MODIFY_REG(MPU->RLAR, MPU_RLAR_LIMIT_Msk, (LimitAddress & MPU_RLAR_LIMIT_Msk)); +} + +/** + * @brief Get a MPU region limit address + * @rmtoll MPU_RNR REGION LL_MPU_GetRegionLimitAddress\n + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @retval None + */ +__STATIC_INLINE uint32_t LL_MPU_GetRegionLimitAddress(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + + return (READ_REG(MPU->RLAR & MPU_RLAR_LIMIT_Msk)); +} + +/** + * @brief Configure a MPU region base address + * @rmtoll MPU_RNR REGION LL_MPU_SetRegionBaseAddress\n + * MPU_RBAR ADDR LL_MPU_SetRegionBaseAddress\n + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @param BaseAddress Value of region base address + * @note cortex-M33 supports 8 secure and 8 non secure regions. + * @retval None + */ +__STATIC_INLINE void LL_MPU_SetRegionBaseAddress(uint32_t Region, uint32_t BaseAddress) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + + /* Set base address */ + MODIFY_REG(MPU->RBAR, MPU_RBAR_BASE_Msk, (BaseAddress & MPU_RBAR_BASE_Msk)); +} + +/** + * @brief Get a MPU region base address + * @rmtoll MPU_RNR REGION LL_MPU_GetRegionBaseAddress\n + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @retval None + */ +__STATIC_INLINE uint32_t LL_MPU_GetRegionBaseAddress(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + + return (READ_REG(MPU->RBAR & MPU_RBAR_BASE_Msk)); +} + +/** + * @brief Configure a MPU region access attributes and enable a region + * @rmtoll MPU_RNR REGION LL_MPU_SetRegionAccess\n + * MPU_RBAR XN LL_MPU_SetRegionAccess\n + * MPU_RBAR AP LL_MPU_SetRegionAccess\n + * MPU_RBAR SH LL_MPU_SetRegionAccess\n + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @param Attributes This parameter can be a combination of the following values: + * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE + * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE + * or @ref LL_MPU_ACCESS_INNER_SHAREABLE + * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO + * or @ref LL_MPU_REGION_ALL_RO + * @note cortex-M33 supports 8 secure and 8 non secure regions. + * @retval None + */ +__STATIC_INLINE void LL_MPU_SetRegionAccess(uint32_t Region, uint32_t Attributes) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + + /* Set base address */ + MODIFY_REG(MPU->RBAR, MPU_ACCESS_MSK, (Attributes & MPU_ACCESS_MSK)); +} + +/** + * @brief Get a MPU region access attributes + * @rmtoll MPU_RNR REGION LL_MPU_GetRegionAccess\n + * MPU_RBAR XN LL_MPU_GetRegionAccess\n + * MPU_RBAR AP LL_MPU_GetRegionAccess\n + * MPU_RBAR SH LL_MPU_GetRegionAccess\n + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @retval None + */ +__STATIC_INLINE uint32_t LL_MPU_GetRegionAccess(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + + return (READ_REG(MPU->RBAR & (MPU_RBAR_XN_Msk | MPU_RBAR_AP_Msk | MPU_RBAR_SH_Msk))); +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Configure a non-secure MPU region limit address + * @rmtoll MPU_RNR REGION LL_MPU_SetRegionLimitAddress_NS\n + * MPU_RLAR ADDR LL_MPU_SetRegionLimitAddress_NS\n + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @param LimitAddress Value of region limit address + * @note cortex-M33 supports 8 secure and 8 non secure regions. + * @retval None + */ +__STATIC_INLINE void LL_MPU_SetRegionLimitAddress_NS(uint32_t Region, uint32_t LimitAddress) +{ + /* Set Region number */ + WRITE_REG(MPU_NS->RNR, Region); + + /* Set limit address */ + MODIFY_REG(MPU_NS->RLAR, MPU_RLAR_LIMIT_Msk, (LimitAddress & MPU_RLAR_LIMIT_Msk)); +} + +/** + * @brief Get a non-secure MPU region limit address + * @rmtoll MPU_RNR REGION LL_MPU_GetRegionLimitAddress_NS\n + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @retval None + */ +__STATIC_INLINE uint32_t LL_MPU_GetRegionLimitAddress_NS(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU_NS->RNR, Region); + + return (READ_REG(MPU_NS->RLAR & MPU_RLAR_LIMIT_Msk)); +} + +/** + * @brief Configure a non-secure MPU region base address + * @rmtoll MPU_RNR REGION LL_MPU_SetRegionBaseAddress_NS\n + * MPU_RBAR ADDR LL_MPU_SetRegionBaseAddress_NS\n + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @param BaseAddress Value of region base address + * @note cortex-M33 supports 8 secure and 8 non secure regions. + * @retval None + */ +__STATIC_INLINE void LL_MPU_SetRegionBaseAddress_NS(uint32_t Region, uint32_t BaseAddress) +{ + /* Set Region number */ + WRITE_REG(MPU_NS->RNR, Region); + + /* Set base address */ + MODIFY_REG(MPU_NS->RBAR, MPU_RBAR_BASE_Msk, (BaseAddress & MPU_RBAR_BASE_Msk)); +} + +/** + * @brief Get a non-secure MPU region base address + * @rmtoll MPU_RNR REGION LL_MPU_GetRegionBaseAddress_NS\n + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @retval None + */ +__STATIC_INLINE uint32_t LL_MPU_GetRegionBaseAddress_NS(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU_NS->RNR, Region); + + return (READ_REG(MPU_NS->RBAR & MPU_RBAR_BASE_Msk)); +} + +/** + * @brief Configure a non-secure MPU region access attributes and enable a region + * @rmtoll MPU_RNR REGION LL_MPU_SetRegionAccess_NS\n + * MPU_RBAR XN LL_MPU_SetRegionAccess_NS\n + * MPU_RBAR AP LL_MPU_SetRegionAccess_NS\n + * MPU_RBAR SH LL_MPU_SetRegionAccess_NS\n + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @param Attributes This parameter can be a combination of the following values: + * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE + * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE + * or @ref LL_MPU_ACCESS_INNER_SHAREABLE + * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO + * or @ref LL_MPU_REGION_ALL_RO + * @note cortex-M33 supports 8 secure and 8 non secure regions. + * @retval None + */ +__STATIC_INLINE void LL_MPU_SetRegionAccess_NS(uint32_t Region, uint32_t Attributes) +{ + /* Set Region number */ + WRITE_REG(MPU_NS->RNR, Region); + + /* Set base address Attributes */ + MODIFY_REG(MPU_NS->RBAR, MPU_ACCESS_MSK, (Attributes & MPU_ACCESS_MSK)); +} + +/** + * @brief Get a non-secure MPU region access attributes + * @rmtoll MPU_RNR REGION LL_MPU_GetRegionAccess_NS\n + * MPU_RBAR XN LL_MPU_GetRegionAccess_NS\n + * MPU_RBAR AP LL_MPU_GetRegionAccess_NS\n + * MPU_RBAR SH LL_MPU_GetRegionAccess_NS\n + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @retval None + */ +__STATIC_INLINE uint32_t LL_MPU_GetRegionAccess_NS(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU_NS->RNR, Region); + + return (READ_REG(MPU_NS->RBAR & (MPU_RBAR_XN_Msk | MPU_RBAR_AP_Msk | MPU_RBAR_SH_Msk))); +} +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WBAxx_LL_CORTEX_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_crc.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_crc.h new file mode 100644 index 0000000000..ad2e2a87d7 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_crc.h @@ -0,0 +1,461 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_ll_crc.h + * @author MCD Application Team + * @brief Header file of CRC LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_LL_CRC_H +#define STM32WBAxx_LL_CRC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx.h" + +/** @addtogroup STM32WBAxx_LL_Driver + * @{ + */ + +#if defined(CRC) + +/** @defgroup CRC_LL CRC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CRC_LL_Exported_Constants CRC Exported Constants + * @{ + */ + +/** @defgroup CRC_LL_EC_POLYLENGTH Polynomial length + * @{ + */ +#define LL_CRC_POLYLENGTH_32B 0x00000000U /*!< 32 bits Polynomial size */ +#define LL_CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0 /*!< 16 bits Polynomial size */ +#define LL_CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1 /*!< 8 bits Polynomial size */ +#define LL_CRC_POLYLENGTH_7B (CRC_CR_POLYSIZE_1 | CRC_CR_POLYSIZE_0) /*!< 7 bits Polynomial size */ +/** + * @} + */ + +/** @defgroup CRC_LL_EC_INDATA_REVERSE Input Data Reverse + * @{ + */ +#define LL_CRC_INDATA_REVERSE_NONE 0x00000000U /*!< Input Data bit order not affected */ +#define LL_CRC_INDATA_REVERSE_BYTE CRC_CR_REV_IN_0 /*!< Input Data bit reversal done by byte */ +#define LL_CRC_INDATA_REVERSE_HALFWORD CRC_CR_REV_IN_1 /*!< Input Data bit reversal done by half-word */ +#define LL_CRC_INDATA_REVERSE_WORD (CRC_CR_REV_IN_1 | CRC_CR_REV_IN_0) /*!< Input Data bit reversal done by word */ +/** + * @} + */ + +/** @defgroup CRC_LL_EC_OUTDATA_REVERSE Output Data Reverse + * @{ + */ +#define LL_CRC_OUTDATA_REVERSE_NONE 0x00000000U /*!< Output Data bit order not affected */ +#define LL_CRC_OUTDATA_REVERSE_BIT CRC_CR_REV_OUT /*!< Output Data bit reversal done by bit */ +/** + * @} + */ + +/** @defgroup CRC_LL_EC_Default_Polynomial_Value Default CRC generating polynomial value + * @brief Normal representation of this polynomial value is + * X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2 + X + 1 . + * @{ + */ +#define LL_CRC_DEFAULT_CRC32_POLY 0x04C11DB7U /*!< Default CRC generating polynomial value */ +/** + * @} + */ + +/** @defgroup CRC_LL_EC_Default_InitValue Default CRC computation initialization value + * @{ + */ +#define LL_CRC_DEFAULT_CRC_INITVALUE 0xFFFFFFFFU /*!< Default CRC computation initialization value */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup CRC_LL_Exported_Macros CRC Exported Macros + * @{ + */ + +/** @defgroup CRC_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in CRC register + * @param __INSTANCE__ CRC Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, __VALUE__) + +/** + * @brief Read a value in CRC register + * @param __INSTANCE__ CRC Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_CRC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup CRC_LL_Exported_Functions CRC Exported Functions + * @{ + */ + +/** @defgroup CRC_LL_EF_Configuration CRC Configuration functions + * @{ + */ + +/** + * @brief Reset the CRC calculation unit. + * @note If Programmable Initial CRC value feature + * is available, also set the Data Register to the value stored in the + * CRC_INIT register, otherwise, reset Data Register to its default value. + * @rmtoll CR RESET LL_CRC_ResetCRCCalculationUnit + * @param CRCx CRC Instance + * @retval None + */ +__STATIC_INLINE void LL_CRC_ResetCRCCalculationUnit(CRC_TypeDef *CRCx) +{ + SET_BIT(CRCx->CR, CRC_CR_RESET); +} + +/** + * @brief Configure size of the polynomial. + * @rmtoll CR POLYSIZE LL_CRC_SetPolynomialSize + * @param CRCx CRC Instance + * @param PolySize This parameter can be one of the following values: + * @arg @ref LL_CRC_POLYLENGTH_32B + * @arg @ref LL_CRC_POLYLENGTH_16B + * @arg @ref LL_CRC_POLYLENGTH_8B + * @arg @ref LL_CRC_POLYLENGTH_7B + * @retval None + */ +__STATIC_INLINE void LL_CRC_SetPolynomialSize(CRC_TypeDef *CRCx, uint32_t PolySize) +{ + MODIFY_REG(CRCx->CR, CRC_CR_POLYSIZE, PolySize); +} + +/** + * @brief Return size of the polynomial. + * @rmtoll CR POLYSIZE LL_CRC_GetPolynomialSize + * @param CRCx CRC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_CRC_POLYLENGTH_32B + * @arg @ref LL_CRC_POLYLENGTH_16B + * @arg @ref LL_CRC_POLYLENGTH_8B + * @arg @ref LL_CRC_POLYLENGTH_7B + */ +__STATIC_INLINE uint32_t LL_CRC_GetPolynomialSize(const CRC_TypeDef *CRCx) +{ + return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_POLYSIZE)); +} + +/** + * @brief Configure the reversal of the bit order of the input data + * @rmtoll CR REV_IN LL_CRC_SetInputDataReverseMode + * @param CRCx CRC Instance + * @param ReverseMode This parameter can be one of the following values: + * @arg @ref LL_CRC_INDATA_REVERSE_NONE + * @arg @ref LL_CRC_INDATA_REVERSE_BYTE + * @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD + * @arg @ref LL_CRC_INDATA_REVERSE_WORD + * @retval None + */ +__STATIC_INLINE void LL_CRC_SetInputDataReverseMode(CRC_TypeDef *CRCx, uint32_t ReverseMode) +{ + MODIFY_REG(CRCx->CR, CRC_CR_REV_IN, ReverseMode); +} + +/** + * @brief Return type of reversal for input data bit order + * @rmtoll CR REV_IN LL_CRC_GetInputDataReverseMode + * @param CRCx CRC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_CRC_INDATA_REVERSE_NONE + * @arg @ref LL_CRC_INDATA_REVERSE_BYTE + * @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD + * @arg @ref LL_CRC_INDATA_REVERSE_WORD + */ +__STATIC_INLINE uint32_t LL_CRC_GetInputDataReverseMode(const CRC_TypeDef *CRCx) +{ + return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_IN)); +} + +/** + * @brief Configure the reversal of the bit order of the Output data + * @rmtoll CR REV_OUT LL_CRC_SetOutputDataReverseMode + * @param CRCx CRC Instance + * @param ReverseMode This parameter can be one of the following values: + * @arg @ref LL_CRC_OUTDATA_REVERSE_NONE + * @arg @ref LL_CRC_OUTDATA_REVERSE_BIT + * @retval None + */ +__STATIC_INLINE void LL_CRC_SetOutputDataReverseMode(CRC_TypeDef *CRCx, uint32_t ReverseMode) +{ + MODIFY_REG(CRCx->CR, CRC_CR_REV_OUT, ReverseMode); +} + +/** + * @brief Return type of reversal of the bit order of the Output data + * @rmtoll CR REV_OUT LL_CRC_GetOutputDataReverseMode + * @param CRCx CRC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_CRC_OUTDATA_REVERSE_NONE + * @arg @ref LL_CRC_OUTDATA_REVERSE_BIT + */ +__STATIC_INLINE uint32_t LL_CRC_GetOutputDataReverseMode(const CRC_TypeDef *CRCx) +{ + return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_OUT)); +} + +/** + * @brief Initialize the Programmable initial CRC value. + * @note If the CRC size is less than 32 bits, the least significant bits + * are used to write the correct value + * @note LL_CRC_DEFAULT_CRC_INITVALUE could be used as value for InitCrc parameter. + * @rmtoll INIT INIT LL_CRC_SetInitialData + * @param CRCx CRC Instance + * @param InitCrc Value to be programmed in Programmable initial CRC value register + * @retval None + */ +__STATIC_INLINE void LL_CRC_SetInitialData(CRC_TypeDef *CRCx, uint32_t InitCrc) +{ + WRITE_REG(CRCx->INIT, InitCrc); +} + +/** + * @brief Return current Initial CRC value. + * @note If the CRC size is less than 32 bits, the least significant bits + * are used to read the correct value + * @rmtoll INIT INIT LL_CRC_GetInitialData + * @param CRCx CRC Instance + * @retval Value programmed in Programmable initial CRC value register + */ +__STATIC_INLINE uint32_t LL_CRC_GetInitialData(const CRC_TypeDef *CRCx) +{ + return (uint32_t)(READ_REG(CRCx->INIT)); +} + +/** + * @brief Initialize the Programmable polynomial value + * (coefficients of the polynomial to be used for CRC calculation). + * @note LL_CRC_DEFAULT_CRC32_POLY could be used as value for PolynomCoef parameter. + * @note Please check Reference Manual and existing Errata Sheets, + * regarding possible limitations for Polynomial values usage. + * For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65 + * @rmtoll POL POL LL_CRC_SetPolynomialCoef + * @param CRCx CRC Instance + * @param PolynomCoef Value to be programmed in Programmable Polynomial value register + * @retval None + */ +__STATIC_INLINE void LL_CRC_SetPolynomialCoef(CRC_TypeDef *CRCx, uint32_t PolynomCoef) +{ + WRITE_REG(CRCx->POL, PolynomCoef); +} + +/** + * @brief Return current Programmable polynomial value + * @note Please check Reference Manual and existing Errata Sheets, + * regarding possible limitations for Polynomial values usage. + * For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65 + * @rmtoll POL POL LL_CRC_GetPolynomialCoef + * @param CRCx CRC Instance + * @retval Value programmed in Programmable Polynomial value register + */ +__STATIC_INLINE uint32_t LL_CRC_GetPolynomialCoef(const CRC_TypeDef *CRCx) +{ + return (uint32_t)(READ_REG(CRCx->POL)); +} + +/** + * @} + */ + +/** @defgroup CRC_LL_EF_Data_Management Data_Management + * @{ + */ + +/** + * @brief Write given 32-bit data to the CRC calculator + * @rmtoll DR DR LL_CRC_FeedData32 + * @param CRCx CRC Instance + * @param InData value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_CRC_FeedData32(CRC_TypeDef *CRCx, uint32_t InData) +{ + WRITE_REG(CRCx->DR, InData); +} + +/** + * @brief Write given 16-bit data to the CRC calculator + * @rmtoll DR DR LL_CRC_FeedData16 + * @param CRCx CRC Instance + * @param InData 16 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_CRC_FeedData16(CRC_TypeDef *CRCx, uint16_t InData) +{ + __IO uint16_t *pReg; + + pReg = (__IO uint16_t *)(__IO void *)(&CRCx->DR); /* Derogation MisraC2012 R.11.5 */ + *pReg = InData; +} + +/** + * @brief Write given 8-bit data to the CRC calculator + * @rmtoll DR DR LL_CRC_FeedData8 + * @param CRCx CRC Instance + * @param InData 8 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_CRC_FeedData8(CRC_TypeDef *CRCx, uint8_t InData) +{ + *(uint8_t __IO *)(&CRCx->DR) = (uint8_t) InData; +} + +/** + * @brief Return current CRC calculation result. 32 bits value is returned. + * @rmtoll DR DR LL_CRC_ReadData32 + * @param CRCx CRC Instance + * @retval Current CRC calculation result as stored in CRC_DR register (32 bits). + */ +__STATIC_INLINE uint32_t LL_CRC_ReadData32(const CRC_TypeDef *CRCx) +{ + return (uint32_t)(READ_REG(CRCx->DR)); +} + +/** + * @brief Return current CRC calculation result. 16 bits value is returned. + * @note This function is expected to be used in a 16 bits CRC polynomial size context. + * @rmtoll DR DR LL_CRC_ReadData16 + * @param CRCx CRC Instance + * @retval Current CRC calculation result as stored in CRC_DR register (16 bits). + */ +__STATIC_INLINE uint16_t LL_CRC_ReadData16(const CRC_TypeDef *CRCx) +{ + return (uint16_t)READ_REG(CRCx->DR); +} + +/** + * @brief Return current CRC calculation result. 8 bits value is returned. + * @note This function is expected to be used in a 8 bits CRC polynomial size context. + * @rmtoll DR DR LL_CRC_ReadData8 + * @param CRCx CRC Instance + * @retval Current CRC calculation result as stored in CRC_DR register (8 bits). + */ +__STATIC_INLINE uint8_t LL_CRC_ReadData8(const CRC_TypeDef *CRCx) +{ + return (uint8_t)READ_REG(CRCx->DR); +} + +/** + * @brief Return current CRC calculation result. 7 bits value is returned. + * @note This function is expected to be used in a 7 bits CRC polynomial size context. + * @rmtoll DR DR LL_CRC_ReadData7 + * @param CRCx CRC Instance + * @retval Current CRC calculation result as stored in CRC_DR register (7 bits). + */ +__STATIC_INLINE uint8_t LL_CRC_ReadData7(const CRC_TypeDef *CRCx) +{ + return (uint8_t)(READ_REG(CRCx->DR) & 0x7FU); +} + +/** + * @brief Return data stored in the Independent Data(IDR) register. + * @note This register can be used as a temporary storage location for one 32-bit long data. + * @rmtoll IDR IDR LL_CRC_Read_IDR + * @param CRCx CRC Instance + * @retval Value stored in CRC_IDR register (General-purpose 32-bit data register). + */ +__STATIC_INLINE uint32_t LL_CRC_Read_IDR(const CRC_TypeDef *CRCx) +{ + return (uint32_t)(READ_REG(CRCx->IDR)); +} + +/** + * @brief Store data in the Independent Data(IDR) register. + * @note This register can be used as a temporary storage location for one 32-bit long data. + * @rmtoll IDR IDR LL_CRC_Write_IDR + * @param CRCx CRC Instance + * @param InData value to be stored in CRC_IDR register (32-bit) between Min_Data=0 and Max_Data=0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_CRC_Write_IDR(CRC_TypeDef *CRCx, uint32_t InData) +{ + *((uint32_t __IO *)(&CRCx->IDR)) = (uint32_t) InData; +} +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup CRC_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_CRC_DeInit(const CRC_TypeDef *CRCx); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(CRC) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WBAxx_LL_CRC_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_dma.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_dma.h new file mode 100644 index 0000000000..03654564ea --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_dma.h @@ -0,0 +1,4561 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_ll_dma.h + * @author MCD Application Team + * @brief Header file of DMA LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### LL DMA driver acronyms ##### + ============================================================================== + [..] Acronyms table : + ========================================= + || Acronym || || + ========================================= + || SRC || Source || + || DEST || Destination || + || ADDR || Address || + || ADDRS || Addresses || + || INC || Increment / Incremented || + || DEC || Decrement / Decremented || + || BLK || Block || + || RPT || Repeat / Repeated || + || TRIG || Trigger || + ========================================= + @endverbatim + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_LL_DMA_H +#define STM32WBAxx_LL_DMA_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx.h" + +/** @addtogroup STM32WBAxx_LL_Driver + * @{ + */ + +#if defined (GPDMA1) + +/** @defgroup DMA_LL DMA + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/** @defgroup DMA_LL_Private_Variables DMA Private Variables + * @{ + */ +#define DMA_CHANNEL0_OFFSET (0x00000050UL) +#define DMA_CHANNEL1_OFFSET (0x000000D0UL) +#define DMA_CHANNEL2_OFFSET (0x00000150UL) +#define DMA_CHANNEL3_OFFSET (0x000001D0UL) +#define DMA_CHANNEL4_OFFSET (0x00000250UL) +#define DMA_CHANNEL5_OFFSET (0x000002D0UL) +#define DMA_CHANNEL6_OFFSET (0x00000350UL) +#define DMA_CHANNEL7_OFFSET (0x000003D0UL) + +/* Array used to get the DMA Channel register offset versus Channel index LL_DMA_CHANNEL_x */ +static const uint32_t LL_DMA_CH_OFFSET_TAB[] = +{ + DMA_CHANNEL0_OFFSET, DMA_CHANNEL1_OFFSET, DMA_CHANNEL2_OFFSET, DMA_CHANNEL3_OFFSET, + DMA_CHANNEL4_OFFSET, DMA_CHANNEL5_OFFSET, DMA_CHANNEL6_OFFSET, DMA_CHANNEL7_OFFSET, +}; + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ + +#if defined (USE_FULL_LL_DRIVER) +/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure + * @{ + */ + +/** + * @brief LL DMA init structure definition. + */ +typedef struct +{ + uint32_t SrcAddress; /*!< This field specify the data transfer source address. + Programming this field is mandatory for all available DMA channels. + This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetSrcAddress(). */ + + uint32_t DestAddress; /*!< This field specify the data transfer destination address. + Programming this field is mandatory for all available DMA channels. + This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetDestAddress(). */ + + uint32_t Direction; /*!< This field specify the data transfer direction. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_TRANSFER_DIRECTION. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetDataTransferDirection(). */ + + uint32_t BlkHWRequest; /*!< This field specify the hardware request unity. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_BLKHW_REQUEST. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetBlkHWRequest(). */ + + uint32_t DataAlignment; /*!< This field specify the transfer data alignment. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_DATA_ALIGNMENT. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetDataAlignment(). */ + + uint32_t SrcBurstLength; /*!< This field specify the source burst length of transfer in bytes. + Programming this field is mandatory for all available DMA channels. + This parameter must be a value between Min_Data = 1 and Max_Data = 64. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetSrcBurstLength(). */ + + uint32_t DestBurstLength; /*!< This field specify the destination burst length of transfer in bytes. + Programming this field is mandatory for all available DMA channels. + This parameter must be a value between Min_Data = 1 and Max_Data = 64. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetDestBurstLength(). */ + + uint32_t SrcDataWidth; /*!< This field specify the source data width. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_SOURCE_DATA_WIDTH. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetSrcDataWidth(). */ + + uint32_t DestDataWidth; /*!< This field specify the destination data width. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_DESTINATION_DATA_WIDTH. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetDestDataWidth(). */ + + uint32_t SrcIncMode; /*!< This field specify the source burst increment mode. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_SOURCE_INCREMENT_MODE. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetSrcIncMode(). */ + + uint32_t DestIncMode; /*!< This field specify the destination burst increment mode. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_DESTINATION_INCREMENT_MODE. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetDestIncMode(). */ + + uint32_t Priority; /*!< This field specify the channel priority level. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_PRIORITY_LEVEL. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetChannelPriorityLevel(). */ + + uint32_t BlkDataLength; /*!< This field specify the length of a block transfer in bytes. + Programming this field is mandatory for all available DMA channels. + This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetBlkDataLength(). */ + + uint32_t TriggerMode; /*!< This field specify the trigger mode. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_TRIGGER_MODE. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetTriggerMode(). */ + + uint32_t TriggerPolarity; /*!< This field specify the trigger event polarity. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_TRIGGER_POLARITY. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetTriggerPolarity(). */ + + uint32_t TriggerSelection; /*!< This field specify the trigger event selection. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_TRIGGER_SELECTION. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetHWTrigger(). */ + + uint32_t Request; /*!< This field specify the peripheral request selection. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_REQUEST_SELECTION. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetPeriphRequest(). */ + + uint32_t TransferEventMode; /*!< This field specify the transfer event mode. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_TRANSFER_EVENT_MODE. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetTransferEventMode(). */ + + uint32_t DestHWordExchange; /*!< This field specify the destination half word exchange. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_DEST_HALFWORD_EXCHANGE. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetDestHWordExchange(). */ + + uint32_t DestByteExchange; /*!< This field specify the destination byte exchange. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_DEST_BYTE_EXCHANGE. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetDestByteExchange(). */ + + uint32_t SrcByteExchange; /*!< This field specify the source byte exchange. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_SRC_BYTE_EXCHANGE. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetSrcByteExchange(). */ + + uint32_t SrcAllocatedPort; /*!< This field specify the source allocated port. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_SOURCE_ALLOCATED_PORT. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetSrcAllocatedPort(). */ + + uint32_t DestAllocatedPort; /*!< This field specify the destination allocated port. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_DESTINATION_ALLOCATED_PORT. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetDestAllocatedPort(). */ + + uint32_t LinkAllocatedPort; /*!< This field specify the linked-list allocated port. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_LINKED_LIST_ALLOCATED_PORT. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetLinkAllocatedPort(). */ + + uint32_t LinkStepMode; /*!< This field specify the link step mode. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_LINK_STEP_MODE. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetLinkStepMode(). */ + + uint32_t LinkedListBaseAddr; /*!< This field specify the linked list base address. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value Between 0 to 0xFFFF0000 (where the 4 first + bytes are always forced to 0). + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetLinkedListBaseAddr(). */ + + uint32_t LinkedListAddrOffset; /*!< Specifies the linked list address offset. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value Between 0 to 0x0000FFFC. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetLinkedListAddrOffset(). */ + +} LL_DMA_InitTypeDef; + + +/** + * @brief LL DMA init linked list structure definition. + */ +typedef struct +{ + uint32_t Priority; /*!< This field specify the channel priority level. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_PRIORITY_LEVEL. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetChannelPriorityLevel(). */ + + uint32_t LinkStepMode; /*!< This field specify the link step mode. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_LINK_STEP_MODE. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetLinkStepMode(). */ + + uint32_t LinkAllocatedPort; /*!< This field specify the linked-list allocated port. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_LINKED_LIST_ALLOCATED_PORT. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetLinkAllocatedPort(). */ + + uint32_t TransferEventMode; /*!< This field specify the transfer event mode. + Programming this field is mandatory for all available DMA channels. + This parameter can be a value of @ref DMA_LL_EC_TRANSFER_EVENT_MODE. + This feature can be modified afterwards using unitary function + @ref LL_DMA_SetTransferEventMode(). */ +} LL_DMA_InitLinkedListTypeDef; + + +/** + * @brief LL DMA node init structure definition. + */ +typedef struct +{ + /* CTR1 register fields ****************************************************** + If any CTR1 fields need to be updated comparing to previous node, it is + mandatory to update the new value in CTR1 register fields and enable update + CTR1 register in UpdateRegisters fields if it is not enabled in the + previous node. + + */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + uint32_t DestSecure; /*!< This field specify the destination secure. + This parameter can be a value of @ref DMA_LL_EC_DESTINATION_SECURITY_ATTRIBUTE. */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + uint32_t DestAllocatedPort; /*!< This field specify the destination allocated port. + This parameter can be a value of @ref DMA_LL_EC_DESTINATION_ALLOCATED_PORT. */ + + uint32_t DestHWordExchange; /*!< This field specify the destination half word exchange. + This parameter can be a value of @ref DMA_LL_EC_DEST_HALFWORD_EXCHANGE. */ + + uint32_t DestByteExchange; /*!< This field specify the destination byte exchange. + This parameter can be a value of @ref DMA_LL_EC_DEST_BYTE_EXCHANGE. */ + + uint32_t DestBurstLength; /*!< This field specify the destination burst length of transfer in bytes. + This parameter must be a value between Min_Data = 1 and Max_Data = 64. */ + + uint32_t DestIncMode; /*!< This field specify the destination increment mode. + This parameter can be a value of @ref DMA_LL_EC_DESTINATION_INCREMENT_MODE. */ + + uint32_t DestDataWidth; /*!< This field specify the destination data width. + This parameter can be a value of @ref DMA_LL_EC_DESTINATION_DATA_WIDTH. */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + uint32_t SrcSecure; /*!< This field specify the source secure. + This parameter can be a value of @ref DMA_LL_EC_SOURCE_SECURITY_ATTRIBUTE. */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + uint32_t SrcAllocatedPort; /*!< This field specify the source allocated port. + This parameter can be a value of @ref DMA_LL_EC_SOURCE_ALLOCATED_PORT. */ + + uint32_t SrcByteExchange; /*!< This field specify the source byte exchange. + This parameter can be a value of @ref DMA_LL_EC_SRC_BYTE_EXCHANGE. */ + + uint32_t DataAlignment; /*!< This field specify the transfer data alignment. + This parameter can be a value of @ref DMA_LL_EC_DATA_ALIGNMENT. */ + + uint32_t SrcBurstLength; /*!< This field specify the source burst length of transfer in bytes. + This parameter must be a value between Min_Data = 1 and Max_Data = 64. */ + + uint32_t SrcIncMode; /*!< This field specify the source increment mode. + This parameter can be a value of @ref DMA_LL_EC_SOURCE_INCREMENT_MODE. */ + + uint32_t SrcDataWidth; /*!< This field specify the source data width. + This parameter can be a value of @ref DMA_LL_EC_SOURCE_DATA_WIDTH. */ + + + /* CTR2 register fields ****************************************************** + If any CTR2 fields need to be updated comparing to previous node, it is + mandatory to update the new value in CTR2 register fields and enable update + CTR2 register in UpdateRegisters fields if it is not enabled in the + previous node. + + For all node created, filling all fields is mandatory. + */ + uint32_t TransferEventMode; /*!< This field specify the transfer event mode. + This parameter can be a value of @ref DMA_LL_EC_TRANSFER_EVENT_MODE. */ + + uint32_t TriggerPolarity; /*!< This field specify the trigger event polarity. + This parameter can be a value of @ref DMA_LL_EC_TRIGGER_POLARITY. */ + + uint32_t TriggerSelection; /*!< This field specify the trigger event selection. + This parameter can be a value of @ref DMA_LL_EC_TRIGGER_SELECTION. */ + + uint32_t TriggerMode; /*!< This field specify the trigger mode. + This parameter can be a value of @ref DMA_LL_EC_TRIGGER_MODE. */ + + uint32_t BlkHWRequest; /*!< This field specify the hardware request unity. + This parameter can be a value of @ref DMA_LL_EC_BLKHW_REQUEST. */ + + uint32_t Direction; /*!< This field specify the transfer direction. + This parameter can be a value of @ref DMA_LL_EC_TRANSFER_DIRECTION. */ + + uint32_t Request; /*!< This field specify the peripheral request selection. + This parameter can be a value of @ref DMA_LL_EC_REQUEST_SELECTION. */ + + + /* CBR1 register fields ****************************************************** + If any CBR1 fields need to be updated comparing to previous node, it is + mandatory to update the new value in CBR1 register fields and enable update + CBR1 register in UpdateRegisters fields if it is not enabled in the + previous node. + */ + + uint32_t BlkDataLength; /*!< This field specify the length of a block transfer in bytes. + This parameter must be a value between Min_Data = 0 + and Max_Data = 0x0000FFFF. */ + + /* CSAR register fields ****************************************************** + If any CSAR fields need to be updated comparing to previous node, it is + mandatory to update the new value in CSAR register fields and enable update + CSAR register in UpdateRegisters fields if it is not enabled in the + previous node. + + For all node created, filling all fields is mandatory. + */ + uint32_t SrcAddress; /*!< This field specify the transfer source address. + This parameter must be a value between Min_Data = 0 + and Max_Data = 0xFFFFFFFF. */ + + + /* CDAR register fields ****************************************************** + If any CDAR fields need to be updated comparing to previous node, it is + mandatory to update the new value in CDAR register fields and enable update + CDAR register in UpdateRegisters fields if it is not enabled in the + previous node. + + For all node created, filling all fields is mandatory. + */ + uint32_t DestAddress; /*!< This field specify the transfer destination address. + This parameter must be a value between Min_Data = 0 + and Max_Data = 0xFFFFFFFF. */ + + /* CLLR register fields ****************************************************** + If any CLLR fields need to be updated comparing to previous node, it is + mandatory to update the new value in CLLR register fields and enable update + CLLR register in UpdateRegisters fields if it is not enabled in the + previous node. + */ + uint32_t UpdateRegisters; /*!< Specifies the linked list register update. + This parameter can be a value of @ref DMA_LL_EC_LINKEDLIST_REGISTER_UPDATE. */ + + /* DMA Node type field ******************************************************* + This parameter defines node types as node size and node content varies + between channels. + Thanks to this fields, linked list queue could be created independently + from channel selection. So, one queue could be executed by all DMA channels. + */ + uint32_t NodeType; /*!< Specifies the node type to be created. + This parameter can be a value of @ref DMA_LL_EC_LINKEDLIST_NODE_TYPE. */ +} LL_DMA_InitNodeTypeDef; + +/** + * @brief LL DMA linked list node structure definition. + * @note For GPDMA linear addressing channels, the maximum node size is : + * (4 Bytes * 6 registers = 24 Bytes). + */ +typedef struct +{ + __IO uint32_t LinkRegisters[6U]; + +} LL_DMA_LinkNodeTypeDef; +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants + * @{ + */ + +/** @defgroup DMA_LL_EC_CHANNEL Channel + * @{ + */ +#define LL_DMA_CHANNEL_0 (0x00U) +#define LL_DMA_CHANNEL_1 (0x01U) +#define LL_DMA_CHANNEL_2 (0x02U) +#define LL_DMA_CHANNEL_3 (0x03U) +#define LL_DMA_CHANNEL_4 (0x04U) +#define LL_DMA_CHANNEL_5 (0x05U) +#define LL_DMA_CHANNEL_6 (0x06U) +#define LL_DMA_CHANNEL_7 (0x07U) +#define LL_DMA_CHANNEL_8 (0x08U) +#define LL_DMA_CHANNEL_9 (0x09U) +#define LL_DMA_CHANNEL_10 (0x0AU) +#define LL_DMA_CHANNEL_11 (0x0BU) +#define LL_DMA_CHANNEL_12 (0x0CU) +#define LL_DMA_CHANNEL_13 (0x0DU) +#define LL_DMA_CHANNEL_14 (0x0EU) +#define LL_DMA_CHANNEL_15 (0x0FU) +#if defined (USE_FULL_LL_DRIVER) +#define LL_DMA_CHANNEL_ALL (0x10U) +#endif /* USE_FULL_LL_DRIVER */ +/** + * @} + */ + +#if defined (USE_FULL_LL_DRIVER) +/** @defgroup DMA_LL_EC_CLLR_OFFSET CLLR offset + * @{ + */ +#define LL_DMA_CLLR_OFFSET0 (0x00U) +#define LL_DMA_CLLR_OFFSET1 (0x01U) +#define LL_DMA_CLLR_OFFSET2 (0x02U) +#define LL_DMA_CLLR_OFFSET3 (0x03U) +#define LL_DMA_CLLR_OFFSET4 (0x04U) +#define LL_DMA_CLLR_OFFSET5 (0x05U) +#define LL_DMA_CLLR_OFFSET6 (0x06U) +#define LL_DMA_CLLR_OFFSET7 (0x07U) +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** @defgroup DMA_LL_EC_PRIORITY_LEVEL Priority Level + * @{ + */ +#define LL_DMA_LOW_PRIORITY_LOW_WEIGHT 0x00000000U /*!< Priority level : Low Priority, Low Weight */ +#define LL_DMA_LOW_PRIORITY_MID_WEIGHT DMA_CCR_PRIO_0 /*!< Priority level : Low Priority, Mid Weight */ +#define LL_DMA_LOW_PRIORITY_HIGH_WEIGHT DMA_CCR_PRIO_1 /*!< Priority level : Low Priority, High Weight */ +#define LL_DMA_HIGH_PRIORITY DMA_CCR_PRIO /*!< Priority level : High Priority */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_LINKED_LIST_ALLOCATED_PORT Linked List Allocated Port + * @{ + */ +#define LL_DMA_LINK_ALLOCATED_PORT0 0x00000000U /*!< Linked List Allocated Port 0 */ +#define LL_DMA_LINK_ALLOCATED_PORT1 DMA_CCR_LAP /*!< Linked List Allocated Port 1 */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_LINK_STEP_MODE Link Step Mode + * @{ + */ +#define LL_DMA_LSM_FULL_EXECUTION 0x00000000U /*!< Channel execute the full linked list */ +#define LL_DMA_LSM_1LINK_EXECUTION DMA_CCR_LSM /*!< Channel execute one node of the linked list */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_DEST_HALFWORD_EXCHANGE Destination Half-Word Exchange + * @{ + */ +#define LL_DMA_DEST_HALFWORD_PRESERVE 0x00000000U /*!< No destination Half-Word exchange when destination data width + is word */ +#define LL_DMA_DEST_HALFWORD_EXCHANGE DMA_CTR1_DHX /*!< Destination Half-Word exchange when destination data width + is word */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_DEST_BYTE_EXCHANGE Destination Byte Exchange + * @{ + */ +#define LL_DMA_DEST_BYTE_PRESERVE 0x00000000U /*!< No destination Byte exchange when destination data width > Byte */ +#define LL_DMA_DEST_BYTE_EXCHANGE DMA_CTR1_DBX /*!< Destination Byte exchange when destination data width > Byte */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_SRC_BYTE_EXCHANGE Source Byte Exchange + * @{ + */ +#define LL_DMA_SRC_BYTE_PRESERVE 0x00000000U /*!< No source Byte exchange when source data width is word */ +#define LL_DMA_SRC_BYTE_EXCHANGE DMA_CTR1_SBX /*!< Source Byte exchange when source data width is word */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_SOURCE_ALLOCATED_PORT Source Allocated Port + * @{ + */ +#define LL_DMA_SRC_ALLOCATED_PORT0 0x00000000U /*!< Source Allocated Port 0 */ +#define LL_DMA_SRC_ALLOCATED_PORT1 DMA_CTR1_SAP /*!< Source Allocated Port 1 */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_DESTINATION_ALLOCATED_PORT Destination Allocated Port + * @{ + */ +#define LL_DMA_DEST_ALLOCATED_PORT0 0x00000000U /*!< Destination Allocated Port 0 */ +#define LL_DMA_DEST_ALLOCATED_PORT1 DMA_CTR1_DAP /*!< Destination Allocated Port 1 */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_DESTINATION_INCREMENT_MODE Destination Increment Mode + * @{ + */ +#define LL_DMA_DEST_FIXED 0x00000000U /*!< Destination fixed single/burst */ +#define LL_DMA_DEST_INCREMENT DMA_CTR1_DINC /*!< Destination incremented single/burst */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_DESTINATION_DATA_WIDTH Destination Data Width + * @{ + */ +#define LL_DMA_DEST_DATAWIDTH_BYTE 0x00000000U /*!< Destination Data Width : Byte */ +#define LL_DMA_DEST_DATAWIDTH_HALFWORD DMA_CTR1_DDW_LOG2_0 /*!< Destination Data Width : HalfWord */ +#define LL_DMA_DEST_DATAWIDTH_WORD DMA_CTR1_DDW_LOG2_1 /*!< Destination Data Width : Word */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_DATA_ALIGNMENT Data Alignment + * @{ + */ +#define LL_DMA_DATA_ALIGN_ZEROPADD 0x00000000U /*!< If src data width < dest data width : + => Right Aligned padded with 0 up to destination + data width. + If src data width > dest data width : + => Right Aligned Left Truncated down to destination + data width. */ +#define LL_DMA_DATA_ALIGN_SIGNEXTPADD DMA_CTR1_PAM_0 /*!< If src data width < dest data width : + => Right Aligned padded with sign extended up to destination + data width. + If src data width > dest data width : + => Left Aligned Right Truncated down to the destination + data width */ +#define LL_DMA_DATA_PACK_UNPACK DMA_CTR1_PAM_1 /*!< If src data width < dest data width : + => Packed at the destination data width + If src data width > dest data width : + => Unpacked at the destination data width */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_SOURCE_INCREMENT_MODE Source Increment Mode + * @{ + */ +#define LL_DMA_SRC_FIXED 0x00000000U /*!< Source fixed single/burst */ +#define LL_DMA_SRC_INCREMENT DMA_CTR1_SINC /*!< Source incremented single/burst */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_SOURCE_DATA_WIDTH Source Data Width + * @{ + */ +#define LL_DMA_SRC_DATAWIDTH_BYTE 0x00000000U /*!< Source Data Width : Byte */ +#define LL_DMA_SRC_DATAWIDTH_HALFWORD DMA_CTR1_SDW_LOG2_0 /*!< Source Data Width : HalfWord */ +#define LL_DMA_SRC_DATAWIDTH_WORD DMA_CTR1_SDW_LOG2_1 /*!< Source Data Width : Word */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_BLKHW_REQUEST Block Hardware Request + * @{ + */ +#define LL_DMA_HWREQUEST_SINGLEBURST 0x00000000U /*!< Hardware request is driven by a peripheral with a hardware + request/acknowledge protocol at a burst level */ +#define LL_DMA_HWREQUEST_BLK DMA_CTR2_BREQ /*!< Hardware request is driven by a peripheral with a hardware + request/acknowledge protocol at a block level */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_TRANSFER_EVENT_MODE Transfer Event Mode + * @{ + */ +#define LL_DMA_TCEM_BLK_TRANSFER 0x00000000U /*!< The TC (and the HT) event is generated at the + (respectively half) end of each block */ +#define LL_DMA_TCEM_RPT_BLK_TRANSFER DMA_CTR2_TCEM_0 /*!< The TC (and the HT) event is generated at the + (respectively half) end of the repeated block */ +#define LL_DMA_TCEM_EACH_LLITEM_TRANSFER DMA_CTR2_TCEM_1 /*!< The TC (and the HT) event is generated at the + (respectively half) end of each linked-list item */ +#define LL_DMA_TCEM_LAST_LLITEM_TRANSFER DMA_CTR2_TCEM /*!< The TC (and the HT) event is generated at the + (respectively half) end of the last linked-list item */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_TRIGGER_POLARITY Trigger Polarity + * @{ + */ +#define LL_DMA_TRIG_POLARITY_MASKED 0x00000000U /*!< No trigger of the selected DMA request. + Masked trigger event */ +#define LL_DMA_TRIG_POLARITY_RISING DMA_CTR2_TRIGPOL_0 /*!< Trigger of the selected DMA request on the rising + edge of the selected trigger event input */ +#define LL_DMA_TRIG_POLARITY_FALLING DMA_CTR2_TRIGPOL_1 /*!< Trigger of the selected DMA request on the falling + edge of the selected trigger event input */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_TRIGGER_MODE Transfer Trigger Mode + * @{ + */ +#define LL_DMA_TRIGM_BLK_TRANSFER 0x00000000U /*!< A block transfer is conditioned by (at least) + one hit trigger */ +#define LL_DMA_TRIGM_RPT_BLK_TRANSFER DMA_CTR2_TRIGM_0 /*!< A repeated block transfer is conditioned by (at least) + one hit trigger */ +#define LL_DMA_TRIGM_LLI_LINK_TRANSFER DMA_CTR2_TRIGM_1 /*!< A LLI link transfer is conditioned by (at least) + one hit trigger */ +#define LL_DMA_TRIGM_SINGLBURST_TRANSFER DMA_CTR2_TRIGM /*!< A Single/Burst transfer is conditioned by (at least) + one hit trigger */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_TRANSFER_DIRECTION Transfer Direction + * @{ + */ +#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CTR2_SWREQ /*!< Memory to memory direction */ +#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ +#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CTR2_DREQ /*!< Memory to peripheral direction */ +/** + * @} + */ + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** @defgroup DMA_LL_EC_SOURCE_SECURITY_ATTRIBUTE Source Security Attribute + * @{ + */ +#define LL_DMA_CHANNEL_NSEC 0x00000000U /*!< NSecure channel */ +#define LL_DMA_CHANNEL_SEC 0x00000001U /*!< Secure channel */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_SOURCE_SECURITY_ATTRIBUTE Source Security Attribute + * @{ + */ +#define LL_DMA_CHANNEL_SRC_NSEC 0x00000000U /*!< NSecure transfer from the source */ +#define LL_DMA_CHANNEL_SRC_SEC DMA_CTR1_SSEC /*!< Secure transfer from the source */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_DESTINATION_SECURITY_ATTRIBUTE Destination Security Attribute + * @{ + */ +#define LL_DMA_CHANNEL_DEST_NSEC 0x00000000U /*!< NSecure transfer from the destination */ +#define LL_DMA_CHANNEL_DEST_SEC DMA_CTR1_DSEC /*!< Secure transfer from the destination */ +/** + * @} + */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/** @defgroup DMA_LL_EC_LINKEDLIST_NODE_TYPE Linked list node type + * @{ + */ +#define LL_DMA_GPDMA_LINEAR_NODE 0x01U /*!< GPDMA node : linear addressing node */ + +/** + * @} + */ + +/** @defgroup DMA_LL_EC_LINKEDLIST_REGISTER_UPDATE Linked list register update + * @{ + */ +#define LL_DMA_UPDATE_CTR1 DMA_CLLR_UT1 /*!< Update CTR1 register from memory : + available for all DMA channels */ +#define LL_DMA_UPDATE_CTR2 DMA_CLLR_UT2 /*!< Update CTR2 register from memory : + available for all DMA channels */ +#define LL_DMA_UPDATE_CBR1 DMA_CLLR_UB1 /*!< Update CBR1 register from memory : + available for all DMA channels */ +#define LL_DMA_UPDATE_CSAR DMA_CLLR_USA /*!< Update CSAR register from memory : + available for all DMA channels */ +#define LL_DMA_UPDATE_CDAR DMA_CLLR_UDA /*!< Update CDAR register from memory : + available for all DMA channels */ +#define LL_DMA_UPDATE_CLLR DMA_CLLR_ULL /*!< Update CLLR register from memory : + available for all DMA channels */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_REQUEST_SELECTION Request Selection + * @{ + */ +/* GPDMA1 Hardware Requests */ +#define LL_GPDMA1_REQUEST_ADC4 0U /*!< GPDMA1 HW request is ADC4 */ +#if defined (SPI1) +#define LL_GPDMA1_REQUEST_SPI1_RX 1U /*!< GPDMA1 HW request is SPI1_RX */ +#define LL_GPDMA1_REQUEST_SPI1_TX 2U /*!< GPDMA1 HW request is SPI1_TX */ +#endif /* SPI1 */ +#define LL_GPDMA1_REQUEST_SPI3_RX 3U /*!< GPDMA1 HW request is SPI3_RX */ +#define LL_GPDMA1_REQUEST_SPI3_TX 4U /*!< GPDMA1 HW request is SPI3_TX */ +#if defined (I2C1) +#define LL_GPDMA1_REQUEST_I2C1_RX 5U /*!< GPDMA1 HW request is I2C1_RX */ +#define LL_GPDMA1_REQUEST_I2C1_TX 6U /*!< GPDMA1 HW request is I2C1_TX */ +#define LL_GPDMA1_REQUEST_I2C1_EVC 7U /*!< GPDMA1 HW request is I2C1_EVC */ +#endif /* I2C1 */ +#define LL_GPDMA1_REQUEST_I2C3_RX 8U /*!< GPDMA1 HW request is I2C3_RX */ +#define LL_GPDMA1_REQUEST_I2C3_TX 9U /*!< GPDMA1 HW request is I2C3_TX */ +#define LL_GPDMA1_REQUEST_I2C3_EVC 10U /*!< GPDMA1 HW request is I2C3_EVC */ +#define LL_GPDMA1_REQUEST_USART1_RX 11U /*!< GPDMA1 HW request is USART1_RX */ +#define LL_GPDMA1_REQUEST_USART1_TX 12U /*!< GPDMA1 HW request is USART1_TX */ +#if defined (USART2) +#define LL_GPDMA1_REQUEST_USART2_RX 13U /*!< GPDMA1 HW request is USART2_RX */ +#define LL_GPDMA1_REQUEST_USART2_TX 14U /*!< GPDMA1 HW request is USART2_TX */ +#endif /* USART2 */ +#define LL_GPDMA1_REQUEST_LPUART1_RX 15U /*!< GPDMA1 HW request is LPUART1_RX */ +#define LL_GPDMA1_REQUEST_LPUART1_TX 16U /*!< GPDMA1 HW request is LPUART1_TX */ +#if defined (SAI1) +#define LL_GPDMA1_REQUEST_SAI1_A 17U /*!< GPDMA1 HW request is SAI1_A */ +#define LL_GPDMA1_REQUEST_SAI1_B 18U /*!< GPDMA1 HW request is SAI1_B */ +#endif /* SAI1 */ +#define LL_GPDMA1_REQUEST_TIM1_CH1 19U /*!< GPDMA1 HW request is TIM1_CH1 */ +#define LL_GPDMA1_REQUEST_TIM1_CH2 20U /*!< GPDMA1 HW request is TIM1_CH2 */ +#define LL_GPDMA1_REQUEST_TIM1_CH3 21U /*!< GPDMA1 HW request is TIM1_CH3 */ +#define LL_GPDMA1_REQUEST_TIM1_CH4 22U /*!< GPDMA1 HW request is TIM1_CH4 */ +#define LL_GPDMA1_REQUEST_TIM1_UP 23U /*!< GPDMA1 HW request is TIM1_UP */ +#define LL_GPDMA1_REQUEST_TIM1_TRIG 24U /*!< GPDMA1 HW request is TIM1_TRIG */ +#define LL_GPDMA1_REQUEST_TIM1_COM 25U /*!< GPDMA1 HW request is TIM1_COM */ +#define LL_GPDMA1_REQUEST_TIM2_CH1 26U /*!< GPDMA1 HW request is TIM2_CH1 */ +#define LL_GPDMA1_REQUEST_TIM2_CH2 27U /*!< GPDMA1 HW request is TIM2_CH2 */ +#define LL_GPDMA1_REQUEST_TIM2_CH3 28U /*!< GPDMA1 HW request is TIM2_CH3 */ +#define LL_GPDMA1_REQUEST_TIM2_CH4 29U /*!< GPDMA1 HW request is TIM2_CH4 */ +#define LL_GPDMA1_REQUEST_TIM2_UP 30U /*!< GPDMA1 HW request is TIM2_UP */ +#if defined (TIM3) +#define LL_GPDMA1_REQUEST_TIM3_CH1 31U /*!< GPDMA1 HW request is TIM3_CH1 */ +#define LL_GPDMA1_REQUEST_TIM3_CH2 32U /*!< GPDMA1 HW request is TIM3_CH2 */ +#define LL_GPDMA1_REQUEST_TIM3_CH3 33U /*!< GPDMA1 HW request is TIM3_CH3 */ +#define LL_GPDMA1_REQUEST_TIM3_CH4 34U /*!< GPDMA1 HW request is TIM3_CH4 */ +#define LL_GPDMA1_REQUEST_TIM3_UP 35U /*!< GPDMA1 HW request is TIM3_UP */ +#define LL_GPDMA1_REQUEST_TIM3_TRIG 36U /*!< GPDMA1 HW request is TIM3_TRIG */ +#endif /* TIM3 */ +#define LL_GPDMA1_REQUEST_TIM16_CH1 37U /*!< GPDMA1 HW request is TIM16_CH1 */ +#define LL_GPDMA1_REQUEST_TIM16_UP 38U /*!< GPDMA1 HW request is TIM16_UP */ +#if defined (TIM17) +#define LL_GPDMA1_REQUEST_TIM17_CH1 39U /*!< GPDMA1 HW request is TIM17_CH1 */ +#define LL_GPDMA1_REQUEST_TIM17_UP 40U /*!< GPDMA1 HW request is TIM17_UP */ +#endif /* TIM17 */ +#if defined (AES) +#define LL_GPDMA1_REQUEST_AES_IN 41U /*!< GPDMA1 HW request is AES_IN */ +#define LL_GPDMA1_REQUEST_AES_OUT 42U /*!< GPDMA1 HW request is AES_OUT */ +#endif /* AES */ +#define LL_GPDMA1_REQUEST_HASH_IN 43U /*!< GPDMA1 HW request is HASH_IN */ +#if defined (SAES) +#define LL_GPDMA1_REQUEST_SAES_IN 44U /*!< GPDMA1 HW request is SAES_IN */ +#define LL_GPDMA1_REQUEST_SAES_OUT 45U /*!< GPDMA1 HW request is SAES_OUT */ +#endif /* SAES */ +#define LL_GPDMA1_REQUEST_LPTIM1_IC1 46U /*!< GPDMA1 HW request is LPTIM1_IC1 */ +#define LL_GPDMA1_REQUEST_LPTIM1_IC2 47U /*!< GPDMA1 HW request is LPTIM1_IC2 */ +#define LL_GPDMA1_REQUEST_LPTIM1_UE 48U /*!< GPDMA1 HW request is LPTIM1_UE */ +#if defined (LPTIM2) +#define LL_GPDMA1_REQUEST_LPTIM2_IC1 49U /*!< GPDMA1 HW request is LPTIM2_IC1 */ +#define LL_GPDMA1_REQUEST_LPTIM2_IC2 50U /*!< GPDMA1 HW request is LPTIM2_IC2 */ +#define LL_GPDMA1_REQUEST_LPTIM2_UE 51U /*!< GPDMA1 HW request is LPTIM2_UE */ +#endif /* LPTIM2 */ + +/** + * @} + */ + +/** @defgroup DMA_LL_EC_TRIGGER_SELECTION Trigger Selection + * @{ + */ +/* GPDMA1 Hardware Triggers */ +#define LL_GPDMA1_TRIGGER_EXTI_LINE0 0U /*!< GPDMA1 HW Trigger signal is EXTI_LINE0 */ +#define LL_GPDMA1_TRIGGER_EXTI_LINE1 1U /*!< GPDMA1 HW Trigger signal is EXTI_LINE1 */ +#define LL_GPDMA1_TRIGGER_EXTI_LINE2 2U /*!< GPDMA1 HW Trigger signal is EXTI_LINE2 */ +#define LL_GPDMA1_TRIGGER_EXTI_LINE3 3U /*!< GPDMA1 HW Trigger signal is EXTI_LINE3 */ +#define LL_GPDMA1_TRIGGER_EXTI_LINE4 4U /*!< GPDMA1 HW Trigger signal is EXTI_LINE4 */ +#define LL_GPDMA1_TRIGGER_EXTI_LINE5 5U /*!< GPDMA1 HW Trigger signal is EXTI_LINE5 */ +#define LL_GPDMA1_TRIGGER_EXTI_LINE6 6U /*!< GPDMA1 HW Trigger signal is EXTI_LINE6 */ +#define LL_GPDMA1_TRIGGER_EXTI_LINE7 7U /*!< GPDMA1 HW Trigger signal is EXTI_LINE7 */ +#define LL_GPDMA1_TRIGGER_TAMP_TRG1 8U /*!< GPDMA1 HW Trigger signal is TAMP_TRG1 */ +#define LL_GPDMA1_TRIGGER_TAMP_TRG2 9U /*!< GPDMA1 HW Trigger signal is TAMP_TRG2 */ +#define LL_GPDMA1_TRIGGER_TAMP_TRG3 10U /*!< GPDMA1 HW Trigger signal is TAMP_TRG3 */ +#define LL_GPDMA1_TRIGGER_LPTIM1_CH1 11U /*!< GPDMA1 HW Trigger signal is LPTIM1_CH1 */ +#define LL_GPDMA1_TRIGGER_LPTIM1_CH2 12U /*!< GPDMA1 HW Trigger signal is LPTIM1_CH2 */ +#if defined (LPTIM2) +#define LL_GPDMA1_TRIGGER_LPTIM2_CH1 13U /*!< GPDMA1 HW Trigger signal is LPTIM2_CH1 */ +#define LL_GPDMA1_TRIGGER_LPTIM2_CH2 14U /*!< GPDMA1 HW Trigger signal is LPTIM2_CH2 */ +#endif /* LPTIM2 */ +#if defined (COMP1) +#define LL_GPDMA1_TRIGGER_COMP1_OUT 15U /*!< GPDMA1 HW Trigger signal is COMP1_OUT */ +#endif /* COMP1 */ +#if defined (COMP2) +#define LL_GPDMA1_TRIGGER_COMP2_OUT 16U /*!< GPDMA1 HW Trigger signal is COMP2_OUT */ +#endif /* COMP2 */ +#define LL_GPDMA1_TRIGGER_RTC_ALRA_TRG 17U /*!< GPDMA1 HW Trigger signal is RTC_ALRA_TRG */ +#define LL_GPDMA1_TRIGGER_RTC_ALRB_TRG 18U /*!< GPDMA1 HW Trigger signal is RTC_ALRB_TRG */ +#define LL_GPDMA1_TRIGGER_RTC_WUT_TRG 19U /*!< GPDMA1 HW Trigger signal is RTC_WUT_TRG */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH0_TCF 20U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH0_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH1_TCF 21U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH1_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH2_TCF 22U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH2_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH3_TCF 23U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH3_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH4_TCF 24U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH4_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH5_TCF 25U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH5_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH6_TCF 26U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH6_TCF */ +#define LL_GPDMA1_TRIGGER_GPDMA1_CH7_TCF 27U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH7_TCF */ +#define LL_GPDMA1_TRIGGER_TIM2_TRGO 28U /*!< GPDMA1 HW Trigger signal is TIM2_TRGO */ +#define LL_GPDMA1_TRIGGER_ADC4_AWD1 29U /*!< GPDMA1 HW Trigger signal is ADC4_ADW1 */ +#if defined (TIM3) +#define LL_GPDMA1_TRIGGER_TIM3_TRGO 30U /*!< GPDMA1 HW Trigger signal is TIM3_TRGO */ +#endif /* TIM3 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros + * @{ + */ + +/** @defgroup DMA_LL_EM_COMMON_WRITE_READ_REGISTERS Common Write and Read Registers macros + * @{ + */ +/** + * @brief Write a value in DMA register. + * @param __INSTANCE__ DMA Instance. + * @param __REG__ Register to be written. + * @param __VALUE__ Value to be written in the register. + * @retval None. + */ +#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__)) + +/** + * @brief Read a value in DMA register. + * @param __INSTANCE__ DMA Instance. + * @param __REG__ Register to be read. + * @retval Register value. + */ +#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely + * @{ + */ +/** + * @brief Convert DMAx_Channely into DMAx. + * @param __CHANNEL_INSTANCE__ DMAx_Channely. + * @retval DMAx. + */ +#define LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \ + (GPDMA1) + +/** + * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y. + * @param __CHANNEL_INSTANCE__ DMAx_Channely. + * @retval LL_DMA_CHANNEL_y. + */ +#define LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ + (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel0)) ? LL_DMA_CHANNEL_0 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ + LL_DMA_CHANNEL_7) + +/** + * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely. + * @param __DMA_INSTANCE__ DMAx. + * @param __CHANNEL__ LL_DMA_CHANNEL_y. + * @retval DMAx_Channely. + */ +#define LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ + ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_0))) \ + ? GPDMA1_Channel0 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) \ + ? GPDMA1_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) \ + ? GPDMA1_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) \ + ? GPDMA1_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) \ + ? GPDMA1_Channel4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) \ + ? GPDMA1_Channel5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) \ + ? GPDMA1_Channel6 : GPDMA1_Channel7) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions + * @{ + */ + +/** @defgroup DMA_LL_EF_Configuration Configuration + * @{ + */ +/** + * @brief Enable channel. + * @note This API is used for all available DMA channels. + * @rmtoll CCR EN LL_DMA_EnableChannel + * @param DMAx DMAx Instance. + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableChannel(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN); +} + +/** + * @brief Disable channel. + * @note This API is used for all available DMA channels. + * @rmtoll CCR EN LL_DMA_DisableChannel + * @param DMAx DMAx Instance. + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableChannel(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, + (DMA_CCR_SUSP | DMA_CCR_RESET)); +} + +/** + * @brief Check if channel is enabled or disabled. + * @note This API is used for all available DMA channels. + * @rmtoll CCR EN LL_DMA_IsEnabledChannel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN) + == (DMA_CCR_EN)) ? 1UL : 0UL); +} + +/** + * @brief Reset channel. + * @note This API is used for all available DMA channels. + * @rmtoll CCR RESET LL_DMA_ResetChannel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ResetChannel(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_RESET); +} + +/** + * @brief Suspend channel. + * @note This API is used for all available DMA channels. + * @rmtoll CCR SUSP LL_DMA_SuspendChannel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SuspendChannel(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSP); +} + +/** + * @brief Resume channel. + * @note This API is used for all available DMA channels. + * @rmtoll CCR SUSP LL_DMA_ResumeChannel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ResumeChannel(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSP); +} + +/** + * @brief Check if channel is suspended. + * @note This API is used for all available DMA channels. + * @rmtoll CCR SUSP LL_DMA_IsSuspendedChannel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsSuspendedChannel(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSP) + == (DMA_CCR_SUSP)) ? 1UL : 0UL); +} + +/** + * @brief Set linked-list base address. + * @note This API is used for all available DMA channels. + * @rmtoll CLBAR LBA LL_DMA_SetLinkedListBaseAddr + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param LinkedListBaseAddr Between 0 to 0xFFFF0000 (where the 4 LSB bytes + * are always 0) + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetLinkedListBaseAddr(const DMA_TypeDef *DMAx, uint32_t Channel, + uint32_t LinkedListBaseAddr) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLBAR, DMA_CLBAR_LBA, + (LinkedListBaseAddr & DMA_CLBAR_LBA)); +} + +/** + * @brief Get linked-list base address. + * @note This API is used for all available DMA channels. + * @rmtoll CLBAR LBA LL_DMA_GetLinkedListBaseAddr + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Value between 0 to 0xFFFF0000 (where the 4 LSB bytes are always 0) + */ +__STATIC_INLINE uint32_t LL_DMA_GetLinkedListBaseAddr(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLBAR, DMA_CLBAR_LBA)); +} + +/** + * @brief Configure all parameters linked to channel control. + * @note This API is used for all available DMA channels. + * @rmtoll CCR PRIO LL_DMA_ConfigControl\n + * CCR LAP LL_DMA_ConfigControl\n + * CCR LSM LL_DMA_ConfigControl + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_DMA_LOW_PRIORITY_LOW_WEIGHT or @ref LL_DMA_LOW_PRIORITY_MID_WEIGHT or + * @ref LL_DMA_LOW_PRIORITY_HIGH_WEIGHT or @ref LL_DMA_HIGH_PRIORITY + * @arg @ref LL_DMA_LINK_ALLOCATED_PORT0 or @ref LL_DMA_LINK_ALLOCATED_PORT1 + * @arg @ref LL_DMA_LSM_FULL_EXECUTION or @ref LL_DMA_LSM_1LINK_EXECUTION + *@retval None. + */ +__STATIC_INLINE void LL_DMA_ConfigControl(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, + (DMA_CCR_PRIO | DMA_CCR_LAP | DMA_CCR_LSM), Configuration); +} + +/** + * @brief Set priority level. + * @note This API is used for all available DMA channels. + * @rmtoll CCR PRIO LL_DMA_SetChannelPriorityLevel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param Priority This parameter can be one of the following values: + * @arg @ref LL_DMA_LOW_PRIORITY_LOW_WEIGHT + * @arg @ref LL_DMA_LOW_PRIORITY_MID_WEIGHT + * @arg @ref LL_DMA_LOW_PRIORITY_HIGH_WEIGHT + * @arg @ref LL_DMA_HIGH_PRIORITY + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PRIO, Priority); +} + +/** + * @brief Get Channel priority level. + * @note This API is used for all available DMA channels. + * @rmtoll CCR PRIO LL_DMA_GetChannelPriorityLevel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_LOW_PRIORITY_LOW_WEIGHT + * @arg @ref LL_DMA_LOW_PRIORITY_MID_WEIGHT + * @arg @ref LL_DMA_LOW_PRIORITY_HIGH_WEIGHT + * @arg @ref LL_DMA_HIGH_PRIORITY + */ +__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PRIO)); +} + +/** + * @brief Set linked-list allocated port. + * @rmtoll CCR LAP LL_DMA_SetLinkAllocatedPort + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param LinkAllocatedPort This parameter can be one of the following values: + * @arg @ref LL_DMA_LINK_ALLOCATED_PORT0 + * @arg @ref LL_DMA_LINK_ALLOCATED_PORT1 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetLinkAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t LinkAllocatedPort) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, + DMA_CCR_LAP, LinkAllocatedPort); +} + +/** + * @brief Get linked-list allocated port. + * @rmtoll CCR LAP LL_DMA_GetLinkAllocatedPort + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_LINK_ALLOCATED_PORT0 + * @arg @ref LL_DMA_LINK_ALLOCATED_PORT1 + */ +__STATIC_INLINE uint32_t LL_DMA_GetLinkAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_LAP)); +} + +/** + * @brief Set link step mode. + * @note This API is used for all available DMA channels. + * @rmtoll CCR LSM LL_DMA_SetLinkStepMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param LinkStepMode This parameter can be one of the following values: + * @arg @ref LL_DMA_LSM_FULL_EXECUTION + * @arg @ref LL_DMA_LSM_1LINK_EXECUTION + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetLinkStepMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t LinkStepMode) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_LSM, LinkStepMode); +} + +/** + * @brief Get Link step mode. + * @note This API is used for all available DMA channels. + * @rmtoll CCR LSM LL_DMA_GetLinkStepMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_LSM_FULL_EXECUTION + * @arg @ref LL_DMA_LSM_1LINK_EXECUTION + */ +__STATIC_INLINE uint32_t LL_DMA_GetLinkStepMode(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_LSM)); +} + +/** + * @brief Configure data transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CTR1 DAP LL_DMA_ConfigTransfer\n + * CTR1 DHX LL_DMA_ConfigTransfer\n + * CTR1 DBX LL_DMA_ConfigTransfer\n + * CTR1 DINC LL_DMA_ConfigTransfer\n + * CTR1 SAP LL_DMA_ConfigTransfer\n + * CTR1 SBX LL_DMA_ConfigTransfer\n + * CTR1 PAM LL_DMA_ConfigTransfer\n + * CTR1 SINC LL_DMA_ConfigTransfer + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_DMA_DEST_ALLOCATED_PORT0 or @ref LL_DMA_DEST_ALLOCATED_PORT1 + * @arg @ref LL_DMA_DEST_HALFWORD_PRESERVE or @ref LL_DMA_DEST_HALFWORD_EXCHANGE + * @arg @ref LL_DMA_DEST_BYTE_PRESERVE or @ref LL_DMA_DEST_BYTE_EXCHANGE + * @arg @ref LL_DMA_SRC_BYTE_PRESERVE or @ref LL_DMA_SRC_BYTE_EXCHANGE + * @arg @ref LL_DMA_DEST_FIXED or @ref LL_DMA_DEST_INCREMENT + * @arg @ref LL_DMA_DEST_DATAWIDTH_BYTE or @ref LL_DMA_DEST_DATAWIDTH_HALFWORD or + * @ref LL_DMA_DEST_DATAWIDTH_WORD + * @arg @ref LL_DMA_SRC_ALLOCATED_PORT0 or @ref LL_DMA_SRC_ALLOCATED_PORT1 + * @arg @ref LL_DMA_DATA_ALIGN_ZEROPADD or @ref LL_DMA_DATA_ALIGN_SIGNEXTPADD or + * @ref LL_DMA_DATA_PACK_UNPACK + * @arg @ref LL_DMA_SRC_FIXED or @ref LL_DMA_SRC_INCREMENT + * @arg @ref LL_DMA_SRC_DATAWIDTH_BYTE or @ref LL_DMA_SRC_DATAWIDTH_HALFWORD or + * @ref LL_DMA_SRC_DATAWIDTH_WORD + *@retval None. + */ +__STATIC_INLINE void LL_DMA_ConfigTransfer(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, + DMA_CTR1_DAP | DMA_CTR1_DHX | DMA_CTR1_DBX | DMA_CTR1_SBX | DMA_CTR1_DINC | DMA_CTR1_SINC | \ + DMA_CTR1_SAP | DMA_CTR1_PAM | DMA_CTR1_DDW_LOG2 | DMA_CTR1_SDW_LOG2, Configuration); +} + +/** + * @brief Configure source and destination burst length. + * @rmtoll CTR1 DBL_1 LL_DMA_SetDestBurstLength\n + * @rmtoll CTR1 SBL_1 LL_DMA_SetDestBurstLength + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param SrcBurstLength Between 1 to 64 + * @param DestBurstLength Between 1 to 64 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ConfigBurstLength(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcBurstLength, + uint32_t DestBurstLength) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, + (DMA_CTR1_SBL_1 | DMA_CTR1_DBL_1), (((SrcBurstLength - 1U) << DMA_CTR1_SBL_1_Pos) & DMA_CTR1_SBL_1) | \ + (((DestBurstLength - 1U) << DMA_CTR1_DBL_1_Pos) & DMA_CTR1_DBL_1)); +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Configure all secure parameters linked to DMA channel. + * @note This API is used for all available DMA channels. + * @rmtoll SECCFGR SEC LL_DMA_ConfigChannelSecure\n + * @rmtoll CTR1 SSEC LL_DMA_ConfigChannelSecure\n + * @rmtoll CTR1 DSEC LL_DMA_ConfigChannelSecure + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_DMA_CHANNEL_NSEC or @ref LL_DMA_CHANNEL_SEC + * @arg @ref LL_DMA_CHANNEL_SRC_NSEC or @ref LL_DMA_CHANNEL_SRC_SEC + * @arg @ref LL_DMA_CHANNEL_DEST_NSEC or @ref LL_DMA_CHANNEL_DEST_SEC + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ConfigChannelSecure(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(DMAx->SECCFGR, (DMA_SECCFGR_SEC0 << Channel), ((Configuration & LL_DMA_CHANNEL_SEC) << Channel)); + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, + (DMA_CTR1_SSEC | DMA_CTR1_DSEC), (Configuration & (~LL_DMA_CHANNEL_SEC))); +} + +/** + * @brief Enable security attribute of the DMA transfer to the destination. + * @note This API is used for all available DMA channels. + * @rmtoll CTR1 DSEC LL_DMA_EnableChannelDestSecure + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableChannelDestSecure(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DSEC); +} + +/** + * @brief Disable security attribute of the DMA transfer to the destination. + * @note This API is used for all available DMA channels. + * @rmtoll CTR1 DSEC LL_DMA_DisableChannelDestSecure + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableChannelDestSecure(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DSEC); +} +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#if defined (DMA_SECCFGR_SEC0) +/** + * @brief Check security attribute of the DMA transfer to the destination. + * @note This API is used for all available DMA channels. + * @rmtoll CTR1 DSEC LL_DMA_IsEnabledChannelDestSecure + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelDestSecure(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DSEC) + == (DMA_CTR1_DSEC)) ? 1UL : 0UL); +} +#endif /* DMA_SECCFGR_SEC0 */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Enable security attribute of the DMA transfer from the source. + * @note This API is used for all available DMA channels. + * @rmtoll CTR1 SSEC LL_DMA_EnableChannelSrcSecure + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableChannelSrcSecure(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SSEC); +} + +/** + * @brief Disable security attribute of the DMA transfer from the source. + * @note This API is used for all available DMA channels. + * @rmtoll CTR1 SSEC LL_DMA_DisableChannelSrcSecure + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableChannelSrcSecure(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SSEC); +} +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#if defined (DMA_SECCFGR_SEC0) +/** + * @brief Check security attribute of the DMA transfer from the source. + * @note This API is used for all available DMA channels. + * @rmtoll CTR1 SSEC LL_DMA_IsEnabledChannelSrcSecure + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelSrcSecure(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SSEC) + == (DMA_CTR1_SSEC)) ? 1UL : 0UL); +} +#endif /* DMA_SECCFGR_SEC0 */ + +/** + * @brief Set destination allocated port. + * @rmtoll CTR1 DAP LL_DMA_SetDestAllocatedPort + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param DestAllocatedPort This parameter can be one of the following values: + * @arg @ref LL_DMA_DEST_ALLOCATED_PORT0 + * @arg @ref LL_DMA_DEST_ALLOCATED_PORT1 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetDestAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestAllocatedPort) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DAP, + DestAllocatedPort); +} + +/** + * @brief Get destination allocated port. + * @rmtoll CTR1 DAP LL_DMA_GetDestAllocatedPort + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_DEST_ALLOCATED_PORT0 + * @arg @ref LL_DMA_DEST_ALLOCATED_PORT1 + */ +__STATIC_INLINE uint32_t LL_DMA_GetDestAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DAP)); +} + +/** + * @brief Set destination half-word exchange. + * @rmtoll CTR1 DHX LL_DMA_SetDestHWordExchange + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param DestHWordExchange This parameter can be one of the following values: + * @arg @ref LL_DMA_DEST_HALFWORD_PRESERVE + * @arg @ref LL_DMA_DEST_HALFWORD_EXCHANGE + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetDestHWordExchange(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestHWordExchange) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DHX, + DestHWordExchange); +} + +/** + * @brief Get destination half-word exchange. + * @rmtoll CTR1 DHX LL_DMA_GetDestHWordExchange + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_DEST_HALFWORD_PRESERVE + * @arg @ref LL_DMA_DEST_HALFWORD_EXCHANGE + */ +__STATIC_INLINE uint32_t LL_DMA_GetDestHWordExchange(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DHX)); +} + +/** + * @brief Set destination byte exchange. + * @rmtoll CTR1 DBX LL_DMA_SetDestByteExchange + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param DestByteExchange This parameter can be one of the following values: + * @arg @ref LL_DMA_DEST_BYTE_PRESERVE + * @arg @ref LL_DMA_DEST_BYTE_EXCHANGE + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetDestByteExchange(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestByteExchange) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DBX, + DestByteExchange); +} + +/** + * @brief Get destination byte exchange. + * @rmtoll CTR1 DBX LL_DMA_GetDestByteExchange + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_DEST_BYTE_PRESERVE + * @arg @ref LL_DMA_DEST_BYTE_EXCHANGE + */ +__STATIC_INLINE uint32_t LL_DMA_GetDestByteExchange(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DBX)); +} + +/** + * @brief Set source byte exchange. + * @rmtoll CTR1 SBX LL_DMA_SetSrcByteExchange + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param SrcByteExchange This parameter can be one of the following values: + * @arg @ref LL_DMA_SRC_BYTE_PRESERVE + * @arg @ref LL_DMA_SRC_BYTE_EXCHANGE + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetSrcByteExchange(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcByteExchange) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SBX, + SrcByteExchange); +} + +/** + * @brief Get source byte exchange. + * @rmtoll CTR1 SBX LL_DMA_GetSrcByteExchange + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_SRC_BYTE_PRESERVE + * @arg @ref LL_DMA_SRC_BYTE_EXCHANGE + */ +__STATIC_INLINE uint32_t LL_DMA_GetSrcByteExchange(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SBX)); +} + +/** + * @brief Set destination burst length. + * @rmtoll CTR1 DBL_1 LL_DMA_SetDestBurstLength + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param DestBurstLength Between 1 to 64 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetDestBurstLength(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestBurstLength) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DBL_1, + ((DestBurstLength - 1U) << DMA_CTR1_DBL_1_Pos) & DMA_CTR1_DBL_1); +} + +/** + * @brief Get destination burst length. + * @rmtoll CTR1 DBL_1 LL_DMA_GetDestBurstLength + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Between 1 to 64. + */ +__STATIC_INLINE uint32_t LL_DMA_GetDestBurstLength(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, + DMA_CTR1_DBL_1) >> DMA_CTR1_DBL_1_Pos) + 1U); +} + +/** + * @brief Set destination increment mode. + * @rmtoll CTR1 DINC LL_DMA_SetDestIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param DestInc This parameter can be one of the following values: + * @arg @ref LL_DMA_DEST_FIXED + * @arg @ref LL_DMA_DEST_INCREMENT + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetDestIncMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestInc) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DINC, DestInc); +} + +/** + * @brief Get destination increment mode. + * @note This API is used for all available DMA channels. + * @rmtoll CTR1 DINC LL_DMA_GetDestIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_DEST_FIXED + * @arg @ref LL_DMA_DEST_INCREMENT + */ +__STATIC_INLINE uint32_t LL_DMA_GetDestIncMode(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DINC)); +} + +/** + * @brief Set destination data width. + * @note This API is used for all available DMA channels. + * @rmtoll CTR1 DDW_LOG2 LL_DMA_SetDestDataWidth + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param DestDataWidth This parameter can be one of the following values: + * @arg @ref LL_DMA_DEST_DATAWIDTH_BYTE + * @arg @ref LL_DMA_DEST_DATAWIDTH_HALFWORD + * @arg @ref LL_DMA_DEST_DATAWIDTH_WORD + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetDestDataWidth(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestDataWidth) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DDW_LOG2, + DestDataWidth); +} + +/** + * @brief Get destination data width. + * @note This API is used for all available DMA channels. + * @rmtoll CTR1 DDW_LOG2 LL_DMA_GetDestDataWidth + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_DEST_DATAWIDTH_BYTE + * @arg @ref LL_DMA_DEST_DATAWIDTH_HALFWORD + * @arg @ref LL_DMA_DEST_DATAWIDTH_WORD + */ +__STATIC_INLINE uint32_t LL_DMA_GetDestDataWidth(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DDW_LOG2)); +} + +/** + * @brief Set source allocated port. + * @rmtoll CTR1 SAP LL_DMA_SetSrcAllocatedPort + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param SrcAllocatedPort This parameter can be one of the following values: + * @arg @ref LL_DMA_SRC_ALLOCATED_PORT0 + * @arg @ref LL_DMA_SRC_ALLOCATED_PORT1 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetSrcAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAllocatedPort) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SAP, + SrcAllocatedPort); +} + +/** + * @brief Get source allocated port. + * @rmtoll CTR1 SAP LL_DMA_GetSrcAllocatedPort + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_SRC_ALLOCATED_PORT0 + * @arg @ref LL_DMA_SRC_ALLOCATED_PORT1 + */ +__STATIC_INLINE uint32_t LL_DMA_GetSrcAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SAP)); +} + +/** + * @brief Set data alignment mode. + * @note This API is used for all available DMA channels. + * @rmtoll CTR1 PAM LL_DMA_SetDataAlignment + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param DataAlignment This parameter can be one of the following values: + * @arg @ref LL_DMA_DATA_ALIGN_ZEROPADD + * @arg @ref LL_DMA_DATA_ALIGN_SIGNEXTPADD + * @arg @ref LL_DMA_DATA_PACK_UNPACK + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetDataAlignment(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DataAlignment) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_PAM, + DataAlignment); +} + +/** + * @brief Get data alignment mode. + * @note This API is used for all available DMA channels. + * @rmtoll CTR1 PAM LL_DMA_GetDataAlignment + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_DATA_ALIGN_ZEROPADD + * @arg @ref LL_DMA_DATA_ALIGN_SIGNEXTPADD + * @arg @ref LL_DMA_DATA_PACK_UNPACK + */ +__STATIC_INLINE uint32_t LL_DMA_GetDataAlignment(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_PAM)); +} + +/** + * @brief Set source burst length. + * @rmtoll CTR1 SBL_1 LL_DMA_SetSrcBurstLength + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param SrcBurstLength Between 1 to 64 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetSrcBurstLength(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcBurstLength) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SBL_1, + ((SrcBurstLength - 1U) << DMA_CTR1_SBL_1_Pos) & DMA_CTR1_SBL_1); +} + +/** + * @brief Get source burst length. + * @rmtoll CTR1 SBL_1 LL_DMA_GetSrcBurstLength + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Between 1 to 64 + * @retval None. + */ +__STATIC_INLINE uint32_t LL_DMA_GetSrcBurstLength(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, + DMA_CTR1_SBL_1) >> DMA_CTR1_SBL_1_Pos) + 1U); +} + +/** + * @brief Set source increment mode. + * @note This API is used for all available DMA channels. + * @rmtoll CTR1 SINC LL_DMA_SetSrcIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param SrcInc This parameter can be one of the following values: + * @arg @ref LL_DMA_SRC_FIXED + * @arg @ref LL_DMA_SRC_INCREMENT + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetSrcIncMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcInc) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SINC, SrcInc); +} + +/** + * @brief Get source increment mode. + * @note This API is used for all available DMA channels. + * @rmtoll CTR1 SINC LL_DMA_GetSrcIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_SRC_FIXED + * @arg @ref LL_DMA_SRC_INCREMENT + */ +__STATIC_INLINE uint32_t LL_DMA_GetSrcIncMode(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SINC)); +} + +/** + * @brief Set source data width. + * @note This API is used for all available DMA channels. + * @rmtoll CTR1 SDW_LOG2 LL_DMA_SetSrcDataWidth + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param SrcDataWidth This parameter can be one of the following values: + * @arg @ref LL_DMA_SRC_DATAWIDTH_BYTE + * @arg @ref LL_DMA_SRC_DATAWIDTH_HALFWORD + * @arg @ref LL_DMA_SRC_DATAWIDTH_WORD + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetSrcDataWidth(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcDataWidth) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SDW_LOG2, + SrcDataWidth); +} + +/** + * @brief Get Source Data width. + * @note This API is used for all available DMA channels. + * @rmtoll CTR1 SDW_LOG2 LL_DMA_GetSrcDataWidth + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_SRC_DATAWIDTH_BYTE + * @arg @ref LL_DMA_SRC_DATAWIDTH_HALFWORD + * @arg @ref LL_DMA_SRC_DATAWIDTH_WORD + */ +__STATIC_INLINE uint32_t LL_DMA_GetSrcDataWidth(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SDW_LOG2)); +} + +/** + * @brief Configure channel transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 TCEM LL_DMA_ConfigChannelTransfer\n + * CTR2 TRIGPOL LL_DMA_ConfigChannelTransfer\n + * CTR2 TRIGM LL_DMA_ConfigChannelTransfer\n + * CTR2 BREQ LL_DMA_ConfigChannelTransfer\n + * CTR2 DREQ LL_DMA_ConfigChannelTransfer\n + * CTR2 SWREQ LL_DMA_ConfigChannelTransfer + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_DMA_TCEM_BLK_TRANSFER or @ref LL_DMA_TCEM_RPT_BLK_TRANSFER or + * @ref LL_DMA_TCEM_EACH_LLITEM_TRANSFER or @ref LL_DMA_TCEM_LAST_LLITEM_TRANSFER + * @arg @ref LL_DMA_HWREQUEST_SINGLEBURST or @ref LL_DMA_HWREQUEST_BLK + * @arg @ref LL_DMA_TRIG_POLARITY_MASKED or @ref LL_DMA_TRIG_POLARITY_RISING or + * @ref LL_DMA_TRIG_POLARITY_FALLING + * @arg @ref LL_DMA_TRIGM_BLK_TRANSFER or @ref LL_DMA_TRIGM_RPT_BLK_TRANSFER or + * @ref LL_DMA_TRIGM_LLI_LINK_TRANSFER or @ref LL_DMA_TRIGM_SINGLBURST_TRANSFER + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or + * @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + *@retval None. + */ +__STATIC_INLINE void LL_DMA_ConfigChannelTransfer(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, + (DMA_CTR2_TCEM | DMA_CTR2_TRIGPOL | DMA_CTR2_TRIGM | DMA_CTR2_DREQ | DMA_CTR2_SWREQ | DMA_CTR2_BREQ), + Configuration); +} + +/** + * @brief Set transfer event mode. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 TCEM LL_DMA_SetTransferEventMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param TransferEventMode This parameter can be one of the following values: + * @arg @ref LL_DMA_TCEM_BLK_TRANSFER + * @arg @ref LL_DMA_TCEM_RPT_BLK_TRANSFER + * @arg @ref LL_DMA_TCEM_EACH_LLITEM_TRANSFER + * @arg @ref LL_DMA_TCEM_LAST_LLITEM_TRANSFER + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetTransferEventMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t TransferEventMode) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TCEM, + TransferEventMode); +} + +/** + * @brief Get transfer event mode. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 TCEM LL_DMA_GetTransferEventMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_TCEM_BLK_TRANSFER + * @arg @ref LL_DMA_TCEM_RPT_BLK_TRANSFER + * @arg @ref LL_DMA_TCEM_EACH_LLITEM_TRANSFER + * @arg @ref LL_DMA_TCEM_LAST_LLITEM_TRANSFER + */ +__STATIC_INLINE uint32_t LL_DMA_GetTransferEventMode(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TCEM)); +} + +/** + * @brief Set trigger polarity. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 TRIGPOL LL_DMA_SetTriggerPolarity + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param TriggerPolarity This parameter can be one of the following values: + * @arg @ref LL_DMA_TRIG_POLARITY_MASKED + * @arg @ref LL_DMA_TRIG_POLARITY_RISING + * @arg @ref LL_DMA_TRIG_POLARITY_FALLING + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetTriggerPolarity(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t TriggerPolarity) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGPOL, + TriggerPolarity); +} + +/** + * @brief Get trigger polarity. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 TRIGPOL LL_DMA_GetTriggerPolarity + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_TRIG_POLARITY_MASKED + * @arg @ref LL_DMA_TRIG_POLARITY_RISING + * @arg @ref LL_DMA_TRIG_POLARITY_FALLING + */ +__STATIC_INLINE uint32_t LL_DMA_GetTriggerPolarity(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGPOL)); +} + +/** + * @brief Set trigger Mode. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 TRIGM LL_DMA_SetTriggerMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param TriggerMode This parameter can be one of the following values: + * @arg @ref LL_DMA_TRIGM_BLK_TRANSFER + * @arg @ref LL_DMA_TRIGM_LLI_LINK_TRANSFER + * @arg @ref LL_DMA_TRIGM_SINGLBURST_TRANSFER + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetTriggerMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t TriggerMode) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGM, + TriggerMode); +} + +/** + * @brief Get trigger Mode. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 TRIGM LL_DMA_GetTriggerMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_TRIGM_BLK_TRANSFER + * @arg @ref LL_DMA_TRIGM_LLI_LINK_TRANSFER + * @arg @ref LL_DMA_TRIGM_SINGLBURST_TRANSFER + */ +__STATIC_INLINE uint32_t LL_DMA_GetTriggerMode(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGM)); +} + +/** + * @brief Set destination hardware and software transfer request. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 DREQ LL_DMA_SetDataTransferDirection\n + * @rmtoll CTR2 SWREQ LL_DMA_SetDataTransferDirection + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetDataTransferDirection(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, + DMA_CTR2_DREQ | DMA_CTR2_SWREQ, Direction); +} + +/** + * @brief Get destination hardware and software transfer request. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 DREQ LL_DMA_GetDataTransferDirection\n + * @rmtoll CTR2 SWREQ LL_DMA_GetDataTransferDirection + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + */ +__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, + DMA_CTR2_DREQ | DMA_CTR2_SWREQ)); +} + +/** + * @brief Set block hardware request. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 BREQ LL_DMA_SetBlkHWRequest\n + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param BlkHWRequest This parameter can be one of the following values: + * @arg @ref LL_DMA_HWREQUEST_SINGLEBURST + * @arg @ref LL_DMA_HWREQUEST_BLK + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetBlkHWRequest(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkHWRequest) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_BREQ, + BlkHWRequest); +} + +/** + * @brief Get block hardware request. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 BREQ LL_DMA_GetBlkHWRequest\n + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_HWREQUEST_SINGLEBURST + * @arg @ref LL_DMA_HWREQUEST_BLK + */ +__STATIC_INLINE uint32_t LL_DMA_GetBlkHWRequest(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_BREQ)); +} + +/** + * @brief Set hardware request. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 REQSEL LL_DMA_SetPeriphRequest + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param Request This parameter can be one of the following values: + * @arg @ref LL_GPDMA1_REQUEST_ADC4 + * @arg @ref LL_GPDMA1_REQUEST_SPI1_RX (*) + * @arg @ref LL_GPDMA1_REQUEST_SPI1_TX (*) + * @arg @ref LL_GPDMA1_REQUEST_SPI3_RX + * @arg @ref LL_GPDMA1_REQUEST_SPI3_TX + * @arg @ref LL_GPDMA1_REQUEST_I2C1_RX (*) + * @arg @ref LL_GPDMA1_REQUEST_I2C1_TX (*) + * @arg @ref LL_GPDMA1_REQUEST_I2C1_EVC (*) + * @arg @ref LL_GPDMA1_REQUEST_I2C3_RX + * @arg @ref LL_GPDMA1_REQUEST_I2C3_TX + * @arg @ref LL_GPDMA1_REQUEST_I2C3_EVC + * @arg @ref LL_GPDMA1_REQUEST_USART1_RX + * @arg @ref LL_GPDMA1_REQUEST_USART1_TX + * @arg @ref LL_GPDMA1_REQUEST_USART2_RX (*) + * @arg @ref LL_GPDMA1_REQUEST_USART2_TX (*) + * @arg @ref LL_GPDMA1_REQUEST_LPUART1_RX + * @arg @ref LL_GPDMA1_REQUEST_LPUART1_TX + * @arg @ref LL_GPDMA1_REQUEST_SAI1_A (*) + * @arg @ref LL_GPDMA1_REQUEST_SAI1_B (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH1 + * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH2 + * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH3 + * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH4 + * @arg @ref LL_GPDMA1_REQUEST_TIM1_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM1_TRIG + * @arg @ref LL_GPDMA1_REQUEST_TIM1_COM + * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH1 + * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH2 + * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH3 + * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH4 + * @arg @ref LL_GPDMA1_REQUEST_TIM2_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH1 (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH2 (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH3 (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH4 (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM3_UP (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM3_TRIG (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM16_CH1 + * @arg @ref LL_GPDMA1_REQUEST_TIM16_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM17_CH1 (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM17_UP (*) + * @arg @ref LL_GPDMA1_REQUEST_AES_IN (*) + * @arg @ref LL_GPDMA1_REQUEST_AES_OUT (*) + * @arg @ref LL_GPDMA1_REQUEST_HASH_IN + * @arg @ref LL_GPDMA1_REQUEST_SAES_IN (*) + * @arg @ref LL_GPDMA1_REQUEST_SAES_OUT (*) + * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_IC1 + * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_IC2 + * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_UE + * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_IC1 (*) + * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_IC2 (*) + * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_UE (*) + * @arg @ref LL_GPDMA1_REQUEST_SPI2_RX (*) + * @arg @ref LL_GPDMA1_REQUEST_SPI2_TX (*) + * @arg @ref LL_GPDMA1_REQUEST_I2C2_RX (*) + * @arg @ref LL_GPDMA1_REQUEST_I2C2_TX (*) + * @arg @ref LL_GPDMA1_REQUEST_I2C2_EVC (*) + * @arg @ref LL_GPDMA1_REQUEST_I2C4_RX (*) + * @arg @ref LL_GPDMA1_REQUEST_I2C4_TX (*) + * @arg @ref LL_GPDMA1_REQUEST_I2C4_EVC (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH1 (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH2 (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH3 (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH4 (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM4_UP (*) + * @arg @ref LL_GPDMA1_REQUEST_USART3_RX (*) + * @arg @ref LL_GPDMA1_REQUEST_USART3_TX (*) + * @note (*) Availability depends on devices. + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetPeriphRequest(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_REQSEL, Request); +} + +/** + * @brief Get hardware request. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 REQSEL LL_DMA_GetPeriphRequest + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPDMA1_REQUEST_ADC4 + * @arg @ref LL_GPDMA1_REQUEST_SPI1_RX (*) + * @arg @ref LL_GPDMA1_REQUEST_SPI1_TX (*) + * @arg @ref LL_GPDMA1_REQUEST_SPI3_RX + * @arg @ref LL_GPDMA1_REQUEST_SPI3_TX + * @arg @ref LL_GPDMA1_REQUEST_I2C1_RX (*) + * @arg @ref LL_GPDMA1_REQUEST_I2C1_TX (*) + * @arg @ref LL_GPDMA1_REQUEST_I2C1_EVC (*) + * @arg @ref LL_GPDMA1_REQUEST_I2C3_RX + * @arg @ref LL_GPDMA1_REQUEST_I2C3_TX + * @arg @ref LL_GPDMA1_REQUEST_I2C3_EVC + * @arg @ref LL_GPDMA1_REQUEST_USART1_RX + * @arg @ref LL_GPDMA1_REQUEST_USART1_TX + * @arg @ref LL_GPDMA1_REQUEST_USART2_RX (*) + * @arg @ref LL_GPDMA1_REQUEST_USART2_TX (*) + * @arg @ref LL_GPDMA1_REQUEST_LPUART1_RX + * @arg @ref LL_GPDMA1_REQUEST_LPUART1_TX + * @arg @ref LL_GPDMA1_REQUEST_SAI1_A (*) + * @arg @ref LL_GPDMA1_REQUEST_SAI1_B (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH1 + * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH2 + * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH3 + * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH4 + * @arg @ref LL_GPDMA1_REQUEST_TIM1_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM1_TRIG + * @arg @ref LL_GPDMA1_REQUEST_TIM1_COM + * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH1 + * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH2 + * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH3 + * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH4 + * @arg @ref LL_GPDMA1_REQUEST_TIM2_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH1 (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH2 (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH3 (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH4 (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM3_UP (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM3_TRIG (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM16_CH1 + * @arg @ref LL_GPDMA1_REQUEST_TIM16_UP + * @arg @ref LL_GPDMA1_REQUEST_TIM17_CH1 (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM17_UP (*) + * @arg @ref LL_GPDMA1_REQUEST_AES_IN (*) + * @arg @ref LL_GPDMA1_REQUEST_AES_OUT (*) + * @arg @ref LL_GPDMA1_REQUEST_HASH_IN + * @arg @ref LL_GPDMA1_REQUEST_SAES_IN (*) + * @arg @ref LL_GPDMA1_REQUEST_SAES_OUT (*) + * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_IC1 + * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_IC2 + * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_UE + * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_IC1 (*) + * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_IC2 (*) + * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_UE (*) + * @arg @ref LL_GPDMA1_REQUEST_SPI2_RX (*) + * @arg @ref LL_GPDMA1_REQUEST_SPI2_TX (*) + * @arg @ref LL_GPDMA1_REQUEST_I2C2_RX (*) + * @arg @ref LL_GPDMA1_REQUEST_I2C2_TX (*) + * @arg @ref LL_GPDMA1_REQUEST_I2C2_EVC (*) + * @arg @ref LL_GPDMA1_REQUEST_I2C4_RX (*) + * @arg @ref LL_GPDMA1_REQUEST_I2C4_TX (*) + * @arg @ref LL_GPDMA1_REQUEST_I2C4_EVC (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH1 (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH2 (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH3 (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH4 (*) + * @arg @ref LL_GPDMA1_REQUEST_TIM4_UP (*) + * @arg @ref LL_GPDMA1_REQUEST_USART3_RX (*) + * @arg @ref LL_GPDMA1_REQUEST_USART3_TX (*) + * @note (*) Availability depends on devices. + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_REQSEL)); +} + +/** + * @brief Set hardware trigger. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 TRIGSEL LL_DMA_SetHWTrigger + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param Trigger This parameter can be one of the following values: + * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE0 + * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE1 + * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE2 + * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE3 + * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE4 + * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE5 + * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE6 + * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE7 + * @arg @ref LL_GPDMA1_TRIGGER_TAMP_TRG1 + * @arg @ref LL_GPDMA1_TRIGGER_TAMP_TRG2 + * @arg @ref LL_GPDMA1_TRIGGER_TAMP_TRG3 + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM1_CH1 + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM1_CH2 + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM2_CH1 (*) + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM2_CH2 (*) + * @arg @ref LL_GPDMA1_TRIGGER_COMP1_OUT (*) + * @arg @ref LL_GPDMA1_TRIGGER_COMP2_OUT (*) + * @arg @ref LL_GPDMA1_TRIGGER_RTC_ALRA_TRG + * @arg @ref LL_GPDMA1_TRIGGER_RTC_ALRB_TRG + * @arg @ref LL_GPDMA1_TRIGGER_RTC_WUT_TRG + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH0_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH1_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH2_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH3_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH4_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH5_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH6_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH7_TCF + * @arg @ref LL_GPDMA1_TRIGGER_TIM2_TRGO + * @arg @ref LL_GPDMA1_TRIGGER_ADC4_AWD1 + * @arg @ref LL_GPDMA1_TRIGGER_TIM3_TRGO (*) + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetHWTrigger(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Trigger) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGSEL, + (Trigger << DMA_CTR2_TRIGSEL_Pos) & DMA_CTR2_TRIGSEL); +} + +/** + * @brief Get hardware triggers. + * @note This API is used for all available DMA channels. + * @rmtoll CTR2 TRIGSEL LL_DMA_GetHWTrigger + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE0 + * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE1 + * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE2 + * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE3 + * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE4 + * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE5 + * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE6 + * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE7 + * @arg @ref LL_GPDMA1_TRIGGER_TAMP_TRG1 + * @arg @ref LL_GPDMA1_TRIGGER_TAMP_TRG2 + * @arg @ref LL_GPDMA1_TRIGGER_TAMP_TRG3 + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM1_CH1 + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM1_CH2 + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM2_CH1 (*) + * @arg @ref LL_GPDMA1_TRIGGER_LPTIM2_CH2 (*) + * @arg @ref LL_GPDMA1_TRIGGER_COMP1_OUT (*) + * @arg @ref LL_GPDMA1_TRIGGER_COMP2_OUT (*) + * @arg @ref LL_GPDMA1_TRIGGER_RTC_ALRA_TRG + * @arg @ref LL_GPDMA1_TRIGGER_RTC_ALRB_TRG + * @arg @ref LL_GPDMA1_TRIGGER_RTC_WUT_TRG + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH0_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH1_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH2_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH3_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH4_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH5_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH6_TCF + * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH7_TCF + * @arg @ref LL_GPDMA1_TRIGGER_TIM2_TRGO + * @arg @ref LL_GPDMA1_TRIGGER_ADC4_AWD1 + * @arg @ref LL_GPDMA1_TRIGGER_TIM3_TRGO (*) + */ +__STATIC_INLINE uint32_t LL_DMA_GetHWTrigger(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, + DMA_CTR2_TRIGSEL) >> DMA_CTR2_TRIGSEL_Pos); +} + +/** + * @brief Set block data length in bytes to transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CBR1 BNDT LL_DMA_SetBlkDataLength + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param BlkDataLength Between 0 to 0x0000FFFF + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetBlkDataLength(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkDataLength) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BNDT, + BlkDataLength); +} + +/** + * @brief Get block data length in bytes to transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CBR1 BNDT LL_DMA_GetBlkDataLength + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Between 0 to 0x0000FFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetBlkDataLength(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BNDT)); +} + +/** + * @brief Configure the source and destination addresses. + * @note This API is used for all available DMA channels. + * @note This API must not be called when the DMA Channel is enabled. + * @rmtoll CSAR SA LL_DMA_ConfigAddresses\n + * CDAR DA LL_DMA_ConfigAddresses + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param SrcAddress Between 0 to 0xFFFFFFFF + * @param DestAddress Between 0 to 0xFFFFFFFF + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ConfigAddresses(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress, uint32_t + DestAddress) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSAR, SrcAddress); + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CDAR, DestAddress); +} + +/** + * @brief Set source address. + * @note This API is used for all available DMA channels. + * @rmtoll CSAR SA LL_DMA_SetSrcAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param SrcAddress Between 0 to 0xFFFFFFFF + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetSrcAddress(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSAR, SrcAddress); +} + +/** + * @brief Get source address. + * @note This API is used for all available DMA channels. + * @rmtoll CSAR SA LL_DMA_GetSrcAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Between 0 to 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetSrcAddress(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSAR)); +} + +/** + * @brief Set destination address. + * @note This API is used for all available DMA channels. + * @rmtoll CDAR DA LL_DMA_SetDestAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param DestAddress Between 0 to 0xFFFFFFFF + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetDestAddress(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestAddress) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CDAR, DestAddress); +} + +/** + * @brief Get destination address. + * @note This API is used for all available DMA channels. + * @rmtoll CDAR DA LL_DMA_GetDestAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Between 0 to 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetDestAddress(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CDAR)); +} + + +/** + * @brief Configure registers update and node address offset during the link transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR UT1 LL_DMA_ConfigLinkUpdate\n + * @rmtoll CLLR UT2 LL_DMA_ConfigLinkUpdate\n + * @rmtoll CLLR UB1 LL_DMA_ConfigLinkUpdate\n + * @rmtoll CLLR USA LL_DMA_ConfigLinkUpdate\n + * @rmtoll CLLR UDA LL_DMA_ConfigLinkUpdate\n + * @rmtoll CLLR ULL LL_DMA_ConfigLinkUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param RegistersUpdate This parameter must be a combination of all the following values: + * @arg @ref LL_DMA_UPDATE_CTR1 + * @arg @ref LL_DMA_UPDATE_CTR2 + * @arg @ref LL_DMA_UPDATE_CBR1 + * @arg @ref LL_DMA_UPDATE_CSAR + * @arg @ref LL_DMA_UPDATE_CDAR + * @arg @ref LL_DMA_UPDATE_CLLR + * @param LinkedListAddrOffset Between 0 to 0x0000FFFC by increment of 4 Bytes. + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ConfigLinkUpdate(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t RegistersUpdate, + uint32_t LinkedListAddrOffset) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, + (DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | \ + DMA_CLLR_ULL | DMA_CLLR_LA), (RegistersUpdate | (LinkedListAddrOffset & DMA_CLLR_LA))); +} + +/** + * @brief Enable CTR1 update during the link transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR UT1 LL_DMA_EnableCTR1Update + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableCTR1Update(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT1); +} + +/** + * @brief Disable CTR1 update during the link transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR UT1 LL_DMA_DisableCTR1Update + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableCTR1Update(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT1); +} + +/** + * @brief Check if CTR1 update during the link transfer is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR UT1 LL_DMA_IsEnabledCTR1Update + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledCTR1Update(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT1) + == (DMA_CLLR_UT1)) ? 1UL : 0UL); +} + +/** + * @brief Enable CTR2 update during the link transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR UT2 LL_DMA_EnableCTR2Update + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableCTR2Update(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT2); +} + +/** + * @brief Disable CTR2 update during the link transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR UT2 LL_DMA_DisableCTR2Update + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableCTR2Update(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT2); +} + +/** + * @brief Check if CTR2 update during the link transfer is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR UT2 LL_DMA_IsEnabledCTR2Update + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledCTR2Update(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT2) + == (DMA_CLLR_UT2)) ? 1UL : 0UL); +} + +/** + * @brief Enable CBR1 update during the link transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR UB1 LL_DMA_EnableCBR1Update + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableCBR1Update(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB1); +} + +/** + * @brief Disable CBR1 update during the link transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR UB1 LL_DMA_DisableCBR1Update + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableCBR1Update(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB1); +} + +/** + * @brief Check if CBR1 update during the link transfer is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR UB1 LL_DMA_IsEnabledCBR1Update + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledCBR1Update(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB1) + == (DMA_CLLR_UB1)) ? 1UL : 0UL); +} + +/** + * @brief Enable CSAR update during the link transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR USA LL_DMA_EnableCSARUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableCSARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA); +} + +/** + * @brief Disable CSAR update during the link transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR USA LL_DMA_DisableCSARUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableCSARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA); +} + +/** + * @brief Check if CSAR update during the link transfer is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR USA LL_DMA_IsEnabledCSARUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledCSARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA) + == (DMA_CLLR_USA)) ? 1UL : 0UL); +} + +/** + * @brief Enable CDAR update during the link transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR UDA LL_DMA_EnableCDARUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableCDARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UDA); +} + +/** + * @brief Disable CDAR update during the link transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR UDA LL_DMA_DisableCDARUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableCDARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UDA); +} + +/** + * @brief Check if CDAR update during the link transfer is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR UDA LL_DMA_IsEnabledCDARUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledCDARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UDA) + == (DMA_CLLR_UDA)) ? 1UL : 0UL); +} + + +/** + * @brief Enable CLLR update during the link transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR ULL LL_DMA_EnableCLLRUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableCLLRUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL); +} + +/** + * @brief Disable CLLR update during the link transfer. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR ULL LL_DMA_DisableCLLRUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableCLLRUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL); +} + +/** + * @brief Check if CLLR update during the link transfer is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR ULL LL_DMA_IsEnabledCLLRUpdate + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledCLLRUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL) + == (DMA_CLLR_ULL)) ? 1UL : 0UL); +} + +/** + * @brief Set linked list address offset. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR LA LL_DMA_SetLinkedListAddrOffset + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param LinkedListAddrOffset Between 0 to 0x0000FFFC by increment of 4 Bytes. + * @retval None. + */ +__STATIC_INLINE void LL_DMA_SetLinkedListAddrOffset(const DMA_TypeDef *DMAx, uint32_t Channel, + uint32_t LinkedListAddrOffset) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_LA, + (LinkedListAddrOffset & DMA_CLLR_LA)); +} + +/** + * @brief Get linked list address offset. + * @note This API is used for all available DMA channels. + * @rmtoll CLLR LA LL_DMA_GetLinkedListAddrOffset + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Between 0 to 0x0000FFFC. + */ +__STATIC_INLINE uint32_t LL_DMA_GetLinkedListAddrOffset(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, + DMA_CLLR_LA) >> DMA_CLLR_LA_Pos); +} + +/** + * @brief Get FIFO level. + * @rmtoll CSR FIFOL LL_DMA_GetFIFOLevel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Between 0 to 0x000000FF. + */ +__STATIC_INLINE uint32_t LL_DMA_GetFIFOLevel(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, + DMA_CSR_FIFOL) >> DMA_CSR_FIFOL_Pos); +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Enable the DMA channel secure attribute. + * @note This API is used for all available DMA channels. + * @rmtoll SECCFGR SECx LL_DMA_EnableChannelSecure + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableChannelSecure(DMA_TypeDef *DMAx, uint32_t Channel) +{ + SET_BIT(DMAx->SECCFGR, (DMA_SECCFGR_SEC0 << (Channel & 0x0000000FU))); +} + +/** + * @brief Disable the DMA channel secure attribute. + * @note This API is used for all available DMA channels. + * @rmtoll SECCFGR SECx LL_DMA_DisableChannelSecure + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableChannelSecure(DMA_TypeDef *DMAx, uint32_t Channel) +{ + CLEAR_BIT(DMAx->SECCFGR, (DMA_SECCFGR_SEC0 << (Channel & 0x0000000FU))); +} +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#if defined (DMA_SECCFGR_SEC0) +/** + * @brief Check if DMA channel secure is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll SECCFGR SECx LL_DMA_IsEnabledChannelSecure + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelSecure(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + return ((READ_BIT(DMAx->SECCFGR, (DMA_SECCFGR_SEC0 << (Channel & 0x0000000FU))) + == (DMA_SECCFGR_SEC0 << (Channel & 0x0000000FU))) ? 1UL : 0UL); +} +#endif /* DMA_SECCFGR_SEC0 */ +#if defined (DMA_PRIVCFGR_PRIV0) +/** + * @brief Enable the DMA channel privilege attribute. + * @note This API is used for all available DMA channels. + * @rmtoll PRIVCFGR PRIVx LL_DMA_EnableChannelPrivilege + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableChannelPrivilege(DMA_TypeDef *DMAx, uint32_t Channel) +{ + SET_BIT(DMAx->PRIVCFGR, (DMA_PRIVCFGR_PRIV0 << (Channel & 0x0000000FU))); +} + +/** + * @brief Disable the DMA channel privilege attribute. + * @note This API is used for all available DMA channels. + * @rmtoll PRIVCFGR PRIVx LL_DMA_DisableChannelPrivilege + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableChannelPrivilege(DMA_TypeDef *DMAx, uint32_t Channel) +{ + CLEAR_BIT(DMAx->PRIVCFGR, (DMA_PRIVCFGR_PRIV0 << (Channel & 0x0000000FU))); +} + +/** + * @brief Check if DMA Channel privilege is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll PRIVCFGR PRIVx LL_DMA_IsEnabledChannelPrivilege + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelPrivilege(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + return ((READ_BIT(DMAx->PRIVCFGR, (DMA_PRIVCFGR_PRIV0 << (Channel & 0x0000000FU))) + == (DMA_PRIVCFGR_PRIV0 << (Channel & 0x0000000FU))) ? 1UL : 0UL); +} +#endif /* DMA_PRIVCFGR_PRIV0 */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Enable the DMA channel lock attributes. + * @note This API is used for all available DMA channels. + * @rmtoll RCFGLOCKR LOCKx LL_DMA_EnableChannelLockAttribute + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableChannelLockAttribute(DMA_TypeDef *DMAx, uint32_t Channel) +{ + SET_BIT(DMAx->RCFGLOCKR, (DMA_RCFGLOCKR_LOCK0 << (Channel & 0x0000000FU))); +} +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#if defined (DMA_RCFGLOCKR_LOCK0) +/** + * @brief Check if DMA channel attributes are locked. + * @note This API is used for all available DMA channels. + * @rmtoll SECCFGR LOCKx LL_DMA_IsEnabledChannelLockAttribute + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelLockAttribute(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + return ((READ_BIT(DMAx->RCFGLOCKR, (DMA_RCFGLOCKR_LOCK0 << (Channel & 0x0000000FU))) + == (DMA_RCFGLOCKR_LOCK0 << (Channel & 0x0000000FU))) ? 1UL : 0UL); +} + +#endif /* DMA_RCFGLOCKR_LOCK0 */ +/** + * @} + */ + +/** @defgroup DMA_LL_EF_FLAG_Management Flag Management + * @{ + */ + +/** + * @brief Clear trigger overrun flag. + * @note This API is used for all available DMA channels. + * @rmtoll CFCR TOF LL_DMA_ClearFlag_TO + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TO(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_TOF); +} + +/** + * @brief Clear suspension flag. + * @note This API is used for all available DMA channels. + * @rmtoll CFCR SUSPF LL_DMA_ClearFlag_SUSP + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ClearFlag_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_SUSPF); +} + +/** + * @brief Clear user setting error flag. + * @note This API is used for all available DMA channels. + * @rmtoll CFCR USEF LL_DMA_ClearFlag_USE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ClearFlag_USE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_USEF); +} + +/** + * @brief Clear link transfer error flag. + * @note This API is used for all available DMA channels. + * @rmtoll CFCR ULEF LL_DMA_ClearFlag_ULE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ClearFlag_ULE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_ULEF); +} + +/** + * @brief Clear data transfer error flag. + * @note This API is used for all available DMA channels. + * @rmtoll CFCR DTEF LL_DMA_ClearFlag_DTE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ClearFlag_DTE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_DTEF); +} + +/** + * @brief Clear half transfer flag. + * @note This API is used for all available DMA channels. + * @rmtoll CFCR HTF LL_DMA_ClearFlag_HT + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_HTF); +} + +/** + * @brief Clear transfer complete flag. + * @note This API is used for all available DMA channels. + * @rmtoll CFCR TCF LL_DMA_ClearFlag_TC + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_TCF); +} + +/** + * @brief Get trigger overrun flag. + * @note This API is used for all available DMA channels. + * @rmtoll CSR TOF LL_DMA_IsActiveFlag_TO + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TO(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_TOF) + == (DMA_CSR_TOF)) ? 1UL : 0UL); +} + +/** + * @brief Get suspension flag. + * @note This API is used for all available DMA channels. + * @rmtoll CSR SUSPF LL_DMA_IsActiveFlag_SUSP + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_SUSPF) + == (DMA_CSR_SUSPF)) ? 1UL : 0UL); +} + +/** + * @brief Get user setting error flag. + * @note This API is used for all available DMA channels. + * @rmtoll CSR USEF LL_DMA_IsActiveFlag_USE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_USE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_USEF) + == (DMA_CSR_USEF)) ? 1UL : 0UL); +} + +/** + * @brief Get user setting error flag. + * @note This API is used for all available DMA channels. + * @rmtoll CSR ULEF LL_DMA_IsActiveFlag_ULE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_ULE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_ULEF) + == (DMA_CSR_ULEF)) ? 1UL : 0UL); +} + +/** + * @brief Get data transfer error flag. + * @note This API is used for all available DMA channels. + * @rmtoll CSR DTEF LL_DMA_IsActiveFlag_DTE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DTE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_DTEF) + == (DMA_CSR_DTEF)) ? 1UL : 0UL); +} + +/** + * @brief Get half transfer flag. + * @note This API is used for all available DMA channels. + * @rmtoll CSR HTF LL_DMA_IsActiveFlag_HT + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_HTF) + == (DMA_CSR_HTF)) ? 1UL : 0UL); +} + +/** + * @brief Get transfer complete flag. + * @note This API is used for all available DMA channels. + * @rmtoll CSR TCF LL_DMA_IsActiveFlag_TC + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_TCF) + == (DMA_CSR_TCF)) ? 1UL : 0UL); +} + +/** + * @brief Get idle flag. + * @note This API is used for all available DMA channels. + * @rmtoll CSR IDLEF LL_DMA_IsActiveFlag_IDLE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_IDLE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_IDLEF) + == (DMA_CSR_IDLEF)) ? 1UL : 0UL); +} + +/** + * @brief Check if nsecure masked interrupt is active. + * @note This API is used for all available DMA channels. + * @rmtoll MISR MISx LL_DMA_IsActiveFlag_MIS + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_MIS(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + return ((READ_BIT(DMAx->MISR, (DMA_MISR_MIS0 << (Channel & 0x0FU))) + == (DMA_MISR_MIS0 << (Channel & 0x0FU))) ? 1UL : 0UL); +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Check if secure masked interrupt is active. + * @note This API is used for all available DMA channels. + * @rmtoll SMISR MISx LL_DMA_IsActiveFlag_SMIS + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_SMIS(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + return ((READ_BIT(DMAx->SMISR, (DMA_SMISR_MIS0 << (Channel & 0x0000000FU))) + == (DMA_SMISR_MIS0 << (Channel & 0x0000000FU))) ? 1UL : 0UL); +} +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/** + * @} + */ + +/** @defgroup DMA_LL_EF_IT_Management Interrupt Management + * @{ + */ + +/** + * @brief Enable trigger overrun interrupt. + * @note This API is used for all available DMA channels. + * @rmtoll CCR TOIE LL_DMA_EnableIT_TO + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableIT_TO(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TOIE); +} + +/** + * @brief Enable suspension interrupt. + * @note This API is used for all available DMA channels. + * @rmtoll CCR SUSPIE LL_DMA_EnableIT_SUSP + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableIT_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSPIE); +} + +/** + * @brief Enable user setting error interrupt. + * @note This API is used for all available DMA channels. + * @rmtoll CCR USEIE LL_DMA_EnableIT_USE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableIT_USE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_USEIE); +} + +/** + * @brief Enable update link transfer error interrupt. + * @note This API is used for all available DMA channels. + * @rmtoll CCR ULEIE LL_DMA_EnableIT_ULE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableIT_ULE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_ULEIE); +} + +/** + * @brief Enable data transfer error interrupt. + * @note This API is used for all available DMA channels. + * @rmtoll CCR DTEIE LL_DMA_EnableIT_DTE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableIT_DTE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_DTEIE); +} + +/** + * @brief Enable half transfer complete interrupt. + * @note This API is used for all available DMA channels. + * @rmtoll CCR HTIE LL_DMA_EnableIT_HT + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableIT_HT(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE); +} + +/** + * @brief Enable transfer complete interrupt. + * @note This API is used for all available DMA channels. + * @rmtoll CCR TCIE LL_DMA_EnableIT_TC + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_EnableIT_TC(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE); +} + +/** + * @brief Disable trigger overrun interrupt. + * @note This API is used for all available DMA channels. + * @rmtoll CCR TOIE LL_DMA_DisableIT_TO + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableIT_TO(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TOIE); +} + +/** + * @brief Disable suspension interrupt. + * @note This API is used for all available DMA channels. + * @rmtoll CCR SUSPIE LL_DMA_DisableIT_SUSP + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableIT_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSPIE); +} + +/** + * @brief Disable user setting error interrupt. + * @note This API is used for all available DMA channels. + * @rmtoll CCR USEIE LL_DMA_DisableIT_USE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableIT_USE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_USEIE); +} + +/** + * @brief Disable update link transfer error interrupt. + * @note This API is used for all available DMA channels. + * @rmtoll CCR ULEIE LL_DMA_DisableIT_ULE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableIT_ULE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_ULEIE); +} + +/** + * @brief Disable data transfer error interrupt. + * @note This API is used for all available DMA channels. + * @rmtoll CCR DTEIE LL_DMA_DisableIT_DTE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableIT_DTE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_DTEIE); +} + +/** + * @brief Disable half transfer complete interrupt. + * @note This API is used for all available DMA channels. + * @rmtoll CCR HTIE LL_DMA_DisableIT_HT + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableIT_HT(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE); +} + +/** + * @brief Disable transfer complete interrupt. + * @note This API is used for all available DMA channels. + * @rmtoll CCR TCIE LL_DMA_DisableIT_TC + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None. + */ +__STATIC_INLINE void LL_DMA_DisableIT_TC(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE); +} + +/** + * @brief Check if trigger overrun interrupt is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll CCR TOIE LL_DMA_IsEnabledIT_TO + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TO(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TOIE) + == DMA_CCR_TOIE) ? 1UL : 0UL); +} + +/** + * @brief Check if suspension interrupt is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll CCR SUSPIE LL_DMA_IsEnabledIT_SUSP + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSPIE) + == DMA_CCR_SUSPIE) ? 1UL : 0UL); +} + +/** + * @brief Check if user setting error interrupt is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll CCR USEIE LL_DMA_IsEnabledIT_USE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_USE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_USEIE) + == DMA_CCR_USEIE) ? 1UL : 0UL); +} + +/** + * @brief Check if update link transfer error interrupt is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll CCR ULEIE LL_DMA_IsEnabledIT_ULE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_ULE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_ULEIE) + == DMA_CCR_ULEIE) ? 1UL : 0UL); +} + +/** + * @brief Check if data transfer error interrupt is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll CCR DTEIE LL_DMA_IsEnabledIT_DTE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DTE(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_DTEIE) + == DMA_CCR_DTEIE) ? 1UL : 0UL); +} + +/** + * @brief Check if half transfer complete interrupt is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE) + == DMA_CCR_HTIE) ? 1UL : 0UL); +} + +/** + * @brief Check if transfer complete interrupt is enabled. + * @note This API is used for all available DMA channels. + * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(const DMA_TypeDef *DMAx, uint32_t Channel) +{ + uint32_t dma_base_addr = (uint32_t)DMAx; + return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE) + == DMA_CCR_TCIE) ? 1UL : 0UL); +} +/** + * @} + */ + +#if defined (USE_FULL_LL_DRIVER) +/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions + * @{ + */ +uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct); +uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel); + +void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct); +void LL_DMA_ListStructInit(LL_DMA_InitLinkedListTypeDef *DMA_InitLinkedListStruct); +void LL_DMA_NodeStructInit(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct); + +uint32_t LL_DMA_List_Init(DMA_TypeDef *DMAx, uint32_t Channel, + LL_DMA_InitLinkedListTypeDef *DMA_InitLinkedListStruct); +uint32_t LL_DMA_List_DeInit(DMA_TypeDef *DMAx, uint32_t Channel); + +uint32_t LL_DMA_CreateLinkNode(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct, LL_DMA_LinkNodeTypeDef *pNode); +void LL_DMA_ConnectLinkNode(LL_DMA_LinkNodeTypeDef *pPrevLinkNode, uint32_t PrevNodeCLLRIdx, + LL_DMA_LinkNodeTypeDef *pNewLinkNode, uint32_t NewNodeCLLRIdx); +void LL_DMA_DisconnectNextLinkNode(LL_DMA_LinkNodeTypeDef *pLinkNode, uint32_t LinkNodeCLLRIdx); +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* GPDMA1 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STM32WBAxx_LL_DMA_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_exti.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_exti.h new file mode 100644 index 0000000000..005670cd90 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_exti.h @@ -0,0 +1,1295 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_ll_exti.h + * @author MCD Application Team + * @brief Header file of EXTI LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_LL_EXTI_H +#define STM32WBAxx_LL_EXTI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx.h" + +/** @addtogroup STM32WBAxx_LL_Driver + * @{ + */ + +#if defined (EXTI) + +/** @defgroup EXTI_LL EXTI + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +#define LL_EXTI_REGISTER_PINPOS_SHFT 16U /*!< Define used to shift pin position in EXTICR register */ + +/* Private Macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure + * @{ + */ +typedef struct +{ + + uint32_t Line_0_31; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31 + This parameter can be any combination of @ref EXTI_LL_EC_LINE */ + + FunctionalState LineCommand; /*!< Specifies the new state of the selected EXTI lines. + This parameter can be set either to ENABLE or DISABLE */ + + uint8_t Mode; /*!< Specifies the mode for the EXTI lines. + This parameter can be a value of @ref EXTI_LL_EC_MODE. */ + + uint8_t Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. + This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */ +} LL_EXTI_InitTypeDef; + +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants + * @{ + */ + +/** @defgroup EXTI_LL_EC_LINE LINE + * @{ + */ +#define LL_EXTI_LINE_0 EXTI_IMR1_IM0 /*!< Extended line 0 */ +#define LL_EXTI_LINE_1 EXTI_IMR1_IM1 /*!< Extended line 1 */ +#define LL_EXTI_LINE_2 EXTI_IMR1_IM2 /*!< Extended line 2 */ +#define LL_EXTI_LINE_3 EXTI_IMR1_IM3 /*!< Extended line 3 */ +#define LL_EXTI_LINE_4 EXTI_IMR1_IM4 /*!< Extended line 4 */ +#define LL_EXTI_LINE_5 EXTI_IMR1_IM5 /*!< Extended line 5 */ +#define LL_EXTI_LINE_6 EXTI_IMR1_IM6 /*!< Extended line 6 */ +#define LL_EXTI_LINE_7 EXTI_IMR1_IM7 /*!< Extended line 7 */ +#define LL_EXTI_LINE_8 EXTI_IMR1_IM8 /*!< Extended line 8 */ +#define LL_EXTI_LINE_9 EXTI_IMR1_IM9 /*!< Extended line 9 */ +#define LL_EXTI_LINE_10 EXTI_IMR1_IM10 /*!< Extended line 10 */ +#define LL_EXTI_LINE_11 EXTI_IMR1_IM11 /*!< Extended line 11 */ +#define LL_EXTI_LINE_12 EXTI_IMR1_IM12 /*!< Extended line 12 */ +#define LL_EXTI_LINE_13 EXTI_IMR1_IM13 /*!< Extended line 13 */ +#define LL_EXTI_LINE_14 EXTI_IMR1_IM14 /*!< Extended line 14 */ +#define LL_EXTI_LINE_15 EXTI_IMR1_IM15 /*!< Extended line 15 */ +#if defined(EXTI_IMR1_IM16) +#define LL_EXTI_LINE_16 EXTI_IMR1_IM16 /*!< Extended line 16 */ +#if defined(EXTI_IMR1_IM17) +#endif /* EXTI_IMR_IM17 */ +#define LL_EXTI_LINE_17 EXTI_IMR1_IM17 /*!< Extended line 17 */ +#endif /* LL_EXTI_LINE_17 */ +#if defined(EXTI_IMR1_IM18) +#define LL_EXTI_LINE_18 EXTI_IMR1_IM18 /*!< Extended line 18 */ +#endif /* LL_EXTI_LINE_18 */ +#define LL_EXTI_LINE_ALL_0_31 0x007FFFFFU /*!< ALL Extended line */ + +#if defined(USE_FULL_LL_DRIVER) +#define LL_EXTI_LINE_NONE 0x00000000U /*!< None Extended line */ +#endif /*USE_FULL_LL_DRIVER*/ + +/** @defgroup SYSTEM_LL_EC_EXTI_PORT EXTI EXTI PORT + * @{ + */ +#define LL_EXTI_CONFIG_PORTA 0U /*!< EXTI PORT A */ +#define LL_EXTI_CONFIG_PORTB EXTI_EXTICR1_EXTI0_0 /*!< EXTI PORT B */ +#define LL_EXTI_CONFIG_PORTC EXTI_EXTICR1_EXTI0_1 /*!< EXTI PORT C */ +#define LL_EXTI_CONFIG_PORTH (EXTI_EXTICR1_EXTI0_2|EXTI_EXTICR1_EXTI0_1|EXTI_EXTICR1_EXTI0_0) /*!< EXTI PORT H */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_EXTI_LINE EXTI EXTI LINE + * @{ + */ +#define LL_EXTI_CONFIG_LINE0 (0U << LL_EXTI_REGISTER_PINPOS_SHFT | 0U) /*!< EXTI_POSITION_0 | EXTICR[0] */ +#define LL_EXTI_CONFIG_LINE1 (8U << LL_EXTI_REGISTER_PINPOS_SHFT | 0U) /*!< EXTI_POSITION_8 | EXTICR[0] */ +#define LL_EXTI_CONFIG_LINE2 (16U << LL_EXTI_REGISTER_PINPOS_SHFT | 0U) /*!< EXTI_POSITION_16 | EXTICR[0] */ +#define LL_EXTI_CONFIG_LINE3 (24U << LL_EXTI_REGISTER_PINPOS_SHFT | 0U) /*!< EXTI_POSITION_24 | EXTICR[0] */ +#define LL_EXTI_CONFIG_LINE4 (0U << LL_EXTI_REGISTER_PINPOS_SHFT | 1U) /*!< EXTI_POSITION_0 | EXTICR[1] */ +#define LL_EXTI_CONFIG_LINE5 (8U << LL_EXTI_REGISTER_PINPOS_SHFT | 1U) /*!< EXTI_POSITION_8 | EXTICR[1] */ +#define LL_EXTI_CONFIG_LINE6 (16U << LL_EXTI_REGISTER_PINPOS_SHFT | 1U) /*!< EXTI_POSITION_16 | EXTICR[1] */ +#define LL_EXTI_CONFIG_LINE7 (24U << LL_EXTI_REGISTER_PINPOS_SHFT | 1U) /*!< EXTI_POSITION_24 | EXTICR[1] */ +#define LL_EXTI_CONFIG_LINE8 (0U << LL_EXTI_REGISTER_PINPOS_SHFT | 2U) /*!< EXTI_POSITION_0 | EXTICR[2] */ +#define LL_EXTI_CONFIG_LINE9 (8U << LL_EXTI_REGISTER_PINPOS_SHFT | 2U) /*!< EXTI_POSITION_8 | EXTICR[2] */ +#define LL_EXTI_CONFIG_LINE10 (16U << LL_EXTI_REGISTER_PINPOS_SHFT | 2U) /*!< EXTI_POSITION_16 | EXTICR[2] */ +#define LL_EXTI_CONFIG_LINE11 (24U << LL_EXTI_REGISTER_PINPOS_SHFT | 2U) /*!< EXTI_POSITION_24 | EXTICR[2] */ +#define LL_EXTI_CONFIG_LINE12 (0U << LL_EXTI_REGISTER_PINPOS_SHFT | 3U) /*!< EXTI_POSITION_0 | EXTICR[3] */ +#define LL_EXTI_CONFIG_LINE13 (8U << LL_EXTI_REGISTER_PINPOS_SHFT | 3U) /*!< EXTI_POSITION_8 | EXTICR[3] */ +#define LL_EXTI_CONFIG_LINE14 (16U << LL_EXTI_REGISTER_PINPOS_SHFT | 3U) /*!< EXTI_POSITION_16 | EXTICR[3] */ +#define LL_EXTI_CONFIG_LINE15 (24U << LL_EXTI_REGISTER_PINPOS_SHFT | 3U) /*!< EXTI_POSITION_24 | EXTICR[3] */ +/** + * @} + */ +/** + * @} + */ +#if defined(USE_FULL_LL_DRIVER) + +/** @defgroup EXTI_LL_EC_MODE Mode + * @{ + */ +#define LL_EXTI_MODE_IT ((uint8_t)0x00U) /*!< Interrupt Mode */ +#define LL_EXTI_MODE_EVENT ((uint8_t)0x01U) /*!< Event Mode */ +#define LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02U) /*!< Interrupt & Event Mode */ +/** + * @} + */ + +/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger + * @{ + */ +#define LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U) /*!< No Trigger Mode */ +#define LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U) /*!< Trigger Rising Mode */ +#define LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U) /*!< Trigger Falling Mode */ +#define LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */ + +/** + * @} + */ + + +#endif /*USE_FULL_LL_DRIVER*/ + + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros + * @{ + */ + +/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in EXTI register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__)) + +/** + * @brief Read a value in EXTI register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__) +/** + * @} + */ + + +/** + * @} + */ + + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions + * @{ + */ +/** @defgroup EXTI_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Interrupt request for Lines in range 0 to 31 + * @note The reset value for the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR1 IMx LL_EXTI_EnableIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->IMR1, ExtiLine); +} + +/** + * @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31 + * @note The reset value for the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR1 IMx LL_EXTI_DisableIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->IMR1, ExtiLine); +} + +/** + * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31 + * @note The reset value for the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR1 IMx LL_EXTI_IsEnabledIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->IMR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Event_Management Event_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Event request for Lines in range 0 to 31 + * @rmtoll EMR1 EMx LL_EXTI_EnableEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->EMR1, ExtiLine); + +} + +/** + * @brief Disable ExtiLine Event request for Lines in range 0 to 31 + * @rmtoll EMR1 EMx LL_EXTI_DisableEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->EMR1, ExtiLine); +} + +/** + * @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31 + * @rmtoll EMR1 EMx LL_EXTI_IsEnabledEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->EMR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); + +} + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR1 RTx LL_EXTI_EnableRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->RTSR1, ExtiLine); +} + +/** + * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR1 RTx LL_EXTI_DisableRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->RTSR1, ExtiLine); + +} + +/** + * @brief Check if rising edge trigger is enabled for Lines in range 0 to 31 + * @rmtoll RTSR1 RTx LL_EXTI_IsEnabledRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->RTSR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll FTSR1 FTx LL_EXTI_EnableFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->FTSR1, ExtiLine); +} + +/** + * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a Falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for the same interrupt line. + * In this case, both generate a trigger condition. + * @rmtoll FTSR1 FTx LL_EXTI_DisableFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->FTSR1, ExtiLine); +} + +/** + * @brief Check if falling edge trigger is enabled for Lines in range 0 to 31 + * @rmtoll FTSR1 FTx LL_EXTI_IsEnabledFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->FTSR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management + * @{ + */ + +/** + * @brief Generate a software Interrupt Event for Lines in range 0 to 31 + * @note If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to + * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR + * resulting in an interrupt request generation. + * This bit is cleared by clearing the corresponding bit in the EXTI_PR + * register (by writing a 1 into the bit) + * @rmtoll SWIER1 SWIx LL_EXTI_GenerateSWI_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->SWIER1, ExtiLine); +} + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management + * @{ + */ + +/** + * @brief Check if the ExtLine Falling Flag is set or not for Lines in range 0 to 31 + * @note This bit is set when the falling edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll FPR1 FPIFx LL_EXTI_IsActiveFallingFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsActiveFallingFlag_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->FPR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +/** + * @brief Read ExtLine Combination Falling Flag for Lines in range 0 to 31 + * @note This bit is set when the falling edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll FPR1 FPIFx LL_EXTI_ReadFallingFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @note Please check each device line mapping for EXTI Line availability + * @retval @note This bit is set when the selected edge event arrives on the interrupt + */ +__STATIC_INLINE uint32_t LL_EXTI_ReadFallingFlag_0_31(uint32_t ExtiLine) +{ + return (uint32_t)(READ_BIT(EXTI->FPR1, ExtiLine)); +} + +/** + * @brief Clear ExtLine Falling Flags for Lines in range 0 to 31 + * @note This bit is set when the falling edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll FPR1 FPIFx LL_EXTI_ClearFallingFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_ClearFallingFlag_0_31(uint32_t ExtiLine) +{ + WRITE_REG(EXTI->FPR1, ExtiLine); +} + +/** + * @brief Check if the ExtLine Rising Flag is set or not for Lines in range 0 to 31 + * @note This bit is set when the Rising edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll RPR1 RPIFx LL_EXTI_IsActiveRisingFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsActiveRisingFlag_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->RPR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} + +/** + * @brief Read ExtLine Combination Rising Flag for Lines in range 0 to 31 + * @note This bit is set when the Rising edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll RPR1 RPIFx LL_EXTI_ReadRisingFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @note Please check each device line mapping for EXTI Line availability + * @retval @note This bit is set when the selected edge event arrives on the interrupt + */ +__STATIC_INLINE uint32_t LL_EXTI_ReadRisingFlag_0_31(uint32_t ExtiLine) +{ + return (uint32_t)(READ_BIT(EXTI->RPR1, ExtiLine)); +} + +/** + * @brief Clear ExtLine Rising Flags for Lines in range 0 to 31 + * @note This bit is set when the Rising edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll RPR1 RPIFx LL_EXTI_ClearRisingFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_ClearRisingFlag_0_31(uint32_t ExtiLine) +{ + WRITE_REG(EXTI->RPR1, ExtiLine); +} + +/** + * @} + */ +/** @defgroup EXTI_LL_EF_Config EF configuration functions + * @{ + */ + +/** + * @brief Configure source input for the EXTI external interrupt. + * @rmtoll EXTI_EXTICR1 EXTI0 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR1 EXTI1 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR1 EXTI2 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR1 EXTI3 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR2 EXTI4 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR2 EXTI5 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR2 EXTI6 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR2 EXTI7 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR3 EXTI8 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR3 EXTI9 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR3 EXTI10 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR3 EXTI11 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR4 EXTI12 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR4 EXTI13 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR4 EXTI14 LL_EXTI_SetEXTISource\n + * EXTI_EXTICR4 EXTI15 LL_EXTI_SetEXTISource + * @param Port This parameter can be one of the following values: + * @arg @ref LL_EXTI_CONFIG_PORTA + * @arg @ref LL_EXTI_CONFIG_PORTB + * @arg @ref LL_EXTI_CONFIG_PORTC + * @arg @ref LL_EXTI_CONFIG_PORTH + * + * (*) value not defined in all devices + * @param Line This parameter can be one of the following values: + * @arg @ref LL_EXTI_CONFIG_LINE0 + * @arg @ref LL_EXTI_CONFIG_LINE1 + * @arg @ref LL_EXTI_CONFIG_LINE2 + * @arg @ref LL_EXTI_CONFIG_LINE3 + * @arg @ref LL_EXTI_CONFIG_LINE4 + * @arg @ref LL_EXTI_CONFIG_LINE5 + * @arg @ref LL_EXTI_CONFIG_LINE6 + * @arg @ref LL_EXTI_CONFIG_LINE7 + * @arg @ref LL_EXTI_CONFIG_LINE8 + * @arg @ref LL_EXTI_CONFIG_LINE9 + * @arg @ref LL_EXTI_CONFIG_LINE10 + * @arg @ref LL_EXTI_CONFIG_LINE11 + * @arg @ref LL_EXTI_CONFIG_LINE12 + * @arg @ref LL_EXTI_CONFIG_LINE13 + * @arg @ref LL_EXTI_CONFIG_LINE14 + * @arg @ref LL_EXTI_CONFIG_LINE15 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_SetEXTISource(uint32_t Port, uint32_t Line) +{ + MODIFY_REG(EXTI->EXTICR[Line & 0x03U], EXTI_EXTICR1_EXTI0 << (Line >> LL_EXTI_REGISTER_PINPOS_SHFT), Port << (Line >> LL_EXTI_REGISTER_PINPOS_SHFT)); +} + +/** + * @brief Get the configured defined for specific EXTI Line + * @rmtoll EXTI_EXTICR1 EXTI0 LL_EXTI_GetEXTISource\n + * EXTI_EXTICR1 EXTI1 LL_EXTI_GetEXTISource\n + * EXTI_EXTICR1 EXTI2 LL_EXTI_GetEXTISource\n + * EXTI_EXTICR1 EXTI3 LL_EXTI_GetEXTISource\n + * EXTI_EXTICR2 EXTI4 LL_EXTI_GetEXTISource\n + * EXTI_EXTICR2 EXTI5 LL_EXTI_GetEXTISource\n + * EXTI_EXTICR2 EXTI6 LL_EXTI_GetEXTISource\n + * EXTI_EXTICR2 EXTI7 LL_EXTI_GetEXTISource\n + * EXTI_EXTICR3 EXTI8 LL_EXTI_GetEXTISource\n + * EXTI_EXTICR3 EXTI9 LL_EXTI_GetEXTISource\n + * EXTI_EXTICR3 EXTI10 LL_EXTI_GetEXTISource\n + * EXTI_EXTICR3 EXTI11 LL_EXTI_GetEXTISource\n + * EXTI_EXTICR4 EXTI12 LL_EXTI_GetEXTISource\n + * EXTI_EXTICR4 EXTI13 LL_EXTI_GetEXTISource\n + * EXTI_EXTICR4 EXTI14 LL_EXTI_GetEXTISource\n + * EXTI_EXTICR4 EXTI15 LL_EXTI_GetEXTISource + * @param Line This parameter can be one of the following values: + * @arg @ref LL_EXTI_CONFIG_LINE0 + * @arg @ref LL_EXTI_CONFIG_LINE1 + * @arg @ref LL_EXTI_CONFIG_LINE2 + * @arg @ref LL_EXTI_CONFIG_LINE3 + * @arg @ref LL_EXTI_CONFIG_LINE4 + * @arg @ref LL_EXTI_CONFIG_LINE5 + * @arg @ref LL_EXTI_CONFIG_LINE6 + * @arg @ref LL_EXTI_CONFIG_LINE7 + * @arg @ref LL_EXTI_CONFIG_LINE8 + * @arg @ref LL_EXTI_CONFIG_LINE9 + * @arg @ref LL_EXTI_CONFIG_LINE10 + * @arg @ref LL_EXTI_CONFIG_LINE11 + * @arg @ref LL_EXTI_CONFIG_LINE12 + * @arg @ref LL_EXTI_CONFIG_LINE13 + * @arg @ref LL_EXTI_CONFIG_LINE14 + * @arg @ref LL_EXTI_CONFIG_LINE15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_EXTI_CONFIG_PORTA + * @arg @ref LL_EXTI_CONFIG_PORTB + * @arg @ref LL_EXTI_CONFIG_PORTC + * @arg @ref LL_EXTI_CONFIG_PORTH + */ +__STATIC_INLINE uint32_t LL_EXTI_GetEXTISource(uint32_t Line) +{ + return (uint32_t)(READ_BIT(EXTI->EXTICR[Line & 0x03U], (EXTI_EXTICR1_EXTI0 << (Line >> LL_EXTI_REGISTER_PINPOS_SHFT))) >> (Line >> LL_EXTI_REGISTER_PINPOS_SHFT)); +} +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Secure_Management Secure_Management + * @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + * @brief Enable ExtiLine Secure attribute for Lines in range 0 to 31 + * @rmtoll SECCFGR1 SECx LL_EXTI_EnableSecure_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableSecure_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->SECCFGR1, ExtiLine); +} + +/** + * @brief Disable ExtiLine Secure attribute for Lines in range 0 to 31 + * @rmtoll SECCFGR1 SECx LL_EXTI_DisableSecure_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableSecure_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->SECCFGR1, ExtiLine); +} + +/** + * @brief Indicate if ExtiLine Secure attribute is enabled for Lines in range 0 to 31 + * @rmtoll SECCFGR1 SECx LL_EXTI_IsEnabledSecure_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledSecure_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->SECCFGR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Privilege_Management Privilege_Management + * @{ + */ + +#if defined(EXTI_PRIVCFGR1_PRIV0) +/** + * @brief Enable ExtiLine Privilege attribute for Lines in range 0 to 31 + * @rmtoll PRIVCFGR1 PRIVx LL_EXTI_EnablePrivilege_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnablePrivilege_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->PRIVCFGR1, ExtiLine); +} + +/** + * @brief Disable ExtiLine Privilege attribute for Lines in range 0 to 31 + * @rmtoll PRIVCFGR1 PRIVx LL_EXTI_DisablePrivilege_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisablePrivilege_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->PRIVCFGR1, ExtiLine); +} + +/** + * @brief Indicate if ExtiLine Privilege attribute is enabled for Lines in range 0 to 31 + * @rmtoll PRIVCFGR1 PRIVx LL_EXTI_IsEnabledPrivilege_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledPrivilege_0_31(uint32_t ExtiLine) +{ + return ((READ_BIT(EXTI->PRIVCFGR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); +} +#endif /* EXTI_PRIVCFGR1_PRIV0 */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Lock the secure and privilege configuration registers. + * @rmtoll LOCKR LOCK LL_EXTI_LockAttributes + * @retval None + */ +__STATIC_INLINE void LL_EXTI_LockAttributes(void) +{ + SET_BIT(EXTI->LOCKR, EXTI_LOCKR_LOCK); +} + +/** + * @brief Return the secure and privilege configuration registers LOCK status + * @rmtoll LOCKR LOCK LL_EXTI_GetLockAttributes + * @retval 1 if the secure and privilege configuration registers have been locked else 0. + */ +__STATIC_INLINE uint32_t LL_EXTI_GetLockAttributes(void) +{ + return READ_BIT(EXTI->LOCKR, EXTI_LOCKR_LOCK); +} +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @} + */ + + + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct); +ErrorStatus LL_EXTI_DeInit(void); +void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct); + + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* EXTI */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WBAxx_LL_EXTI_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_gpio.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_gpio.h new file mode 100644 index 0000000000..ad2afbee3c --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_gpio.h @@ -0,0 +1,1086 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_ll_gpio.h + * @author MCD Application Team + * @brief Header file of GPIO LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32WBAxx_LL_GPIO_H +#define __STM32WBAxx_LL_GPIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx.h" + +/** @addtogroup STM32WBAxx_LL_Driver + * @{ + */ + +#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOH) + +/** @defgroup GPIO_LL GPIO + * @{ + */ +/** MISRA C:2012 deviation rule has been granted for following rules: + * Rule-18.1_d - Medium: Array pointer `GPIOx' is accessed with index [..,..] + * which may be out of array bounds [..,UNKNOWN] in following APIs: + * LL_GPIO_GetAFPin_0_7 + * LL_GPIO_SetAFPin_0_7 + * LL_GPIO_SetAFPin_8_15 + * LL_GPIO_GetAFPin_8_15 + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros + * @{ + */ + +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures + * @{ + */ + +/** + * @brief LL GPIO Init Structure definition + */ +typedef struct +{ + uint32_t Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_LL_EC_PIN */ + + uint32_t Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_MODE. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/ + + uint32_t Speed; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_SPEED. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/ + + uint32_t OutputType; /*!< Specifies the operating output type for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_OUTPUT. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/ + + uint32_t Pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_PULL. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/ + + uint32_t Alternate; /*!< Specifies the Peripheral to be connected to the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_AF. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().*/ +} LL_GPIO_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants + * @{ + */ + +/** @defgroup GPIO_LL_EC_PIN PIN + * @{ + */ +#define LL_GPIO_PIN_0 GPIO_BSRR_BS0 /*!< Select pin 0 */ +#define LL_GPIO_PIN_1 GPIO_BSRR_BS1 /*!< Select pin 1 */ +#define LL_GPIO_PIN_2 GPIO_BSRR_BS2 /*!< Select pin 2 */ +#define LL_GPIO_PIN_3 GPIO_BSRR_BS3 /*!< Select pin 3 */ +#define LL_GPIO_PIN_4 GPIO_BSRR_BS4 /*!< Select pin 4 */ +#define LL_GPIO_PIN_5 GPIO_BSRR_BS5 /*!< Select pin 5 */ +#define LL_GPIO_PIN_6 GPIO_BSRR_BS6 /*!< Select pin 6 */ +#define LL_GPIO_PIN_7 GPIO_BSRR_BS7 /*!< Select pin 7 */ +#define LL_GPIO_PIN_8 GPIO_BSRR_BS8 /*!< Select pin 8 */ +#define LL_GPIO_PIN_9 GPIO_BSRR_BS9 /*!< Select pin 9 */ +#define LL_GPIO_PIN_10 GPIO_BSRR_BS10 /*!< Select pin 10 */ +#define LL_GPIO_PIN_11 GPIO_BSRR_BS11 /*!< Select pin 11 */ +#define LL_GPIO_PIN_12 GPIO_BSRR_BS12 /*!< Select pin 12 */ +#define LL_GPIO_PIN_13 GPIO_BSRR_BS13 /*!< Select pin 13 */ +#define LL_GPIO_PIN_14 GPIO_BSRR_BS14 /*!< Select pin 14 */ +#define LL_GPIO_PIN_15 GPIO_BSRR_BS15 /*!< Select pin 15 */ +#define LL_GPIO_PIN_ALL (GPIO_BSRR_BS0 | GPIO_BSRR_BS1 | GPIO_BSRR_BS2 | \ + GPIO_BSRR_BS3 | GPIO_BSRR_BS4 | GPIO_BSRR_BS5 | \ + GPIO_BSRR_BS6 | GPIO_BSRR_BS7 | GPIO_BSRR_BS8 | \ + GPIO_BSRR_BS9 | GPIO_BSRR_BS10 | GPIO_BSRR_BS11 | \ + GPIO_BSRR_BS12 | GPIO_BSRR_BS13 | GPIO_BSRR_BS14 | \ + GPIO_BSRR_BS15) /*!< Select all pins */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_MODE Mode + * @{ + */ +#define LL_GPIO_MODE_INPUT (0x00000000U) /*!< Select input mode */ +#define LL_GPIO_MODE_OUTPUT GPIO_MODER_MODE0_0 /*!< Select output mode */ +#define LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODE0_1 /*!< Select alternate function mode */ +#define LL_GPIO_MODE_ANALOG GPIO_MODER_MODE0 /*!< Select analog mode */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_OUTPUT Output Type + * @{ + */ +#define LL_GPIO_OUTPUT_PUSHPULL (0x00000000U) /*!< Select push-pull as output type */ +#define LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT0 /*!< Select open-drain as output type */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_SPEED Output Speed + * @{ + */ +#define LL_GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< Select I/O low output speed */ +#define LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDR_OSPEED0_0 /*!< Select I/O medium output speed */ +#define LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDR_OSPEED0_1 /*!< Select I/O fast output speed */ +/** + * @} + */ +#define LL_GPIO_SPEED_LOW LL_GPIO_SPEED_FREQ_LOW +#define LL_GPIO_SPEED_MEDIUM LL_GPIO_SPEED_FREQ_MEDIUM +#define LL_GPIO_SPEED_FAST LL_GPIO_SPEED_FREQ_HIGH + + +/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down + * @{ + */ +#define LL_GPIO_PULL_NO (0x00000000U) /*!< Select I/O no pull */ +#define LL_GPIO_PULL_UP GPIO_PUPDR_PUPD0_0 /*!< Select I/O pull up */ +#define LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPD0_1 /*!< Select I/O pull down */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_AF Alternate Function + * @{ + */ +#define LL_GPIO_AF_0 (0x0000000U) /*!< Select alternate function 0 */ +#define LL_GPIO_AF_1 (0x0000001U) /*!< Select alternate function 1 */ +#define LL_GPIO_AF_2 (0x0000002U) /*!< Select alternate function 2 */ +#define LL_GPIO_AF_3 (0x0000003U) /*!< Select alternate function 3 */ +#define LL_GPIO_AF_4 (0x0000004U) /*!< Select alternate function 4 */ +#define LL_GPIO_AF_5 (0x0000005U) /*!< Select alternate function 5 */ +#define LL_GPIO_AF_6 (0x0000006U) /*!< Select alternate function 6 */ +#define LL_GPIO_AF_7 (0x0000007U) /*!< Select alternate function 7 */ +#define LL_GPIO_AF_8 (0x0000008U) /*!< Select alternate function 8 */ +#define LL_GPIO_AF_9 (0x0000009U) /*!< Select alternate function 9 */ +#define LL_GPIO_AF_10 (0x000000AU) /*!< Select alternate function 10 */ +#define LL_GPIO_AF_11 (0x000000BU) /*!< Select alternate function 11 */ +#define LL_GPIO_AF_12 (0x000000CU) /*!< Select alternate function 12 */ +#define LL_GPIO_AF_13 (0x000000DU) /*!< Select alternate function 13 */ +#define LL_GPIO_AF_14 (0x000000EU) /*!< Select alternate function 14 */ +#define LL_GPIO_AF_15 (0x000000FU) /*!< Select alternate function 15 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros + * @{ + */ + +/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in GPIO register + * @param __INSTANCE__ GPIO Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in GPIO register + * @param __INSTANCE__ GPIO Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions + * @{ + */ + +/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration + * @{ + */ + +/** + * @brief Configure gpio mode for a dedicated pin on dedicated port. + * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll MODER MODEy LL_GPIO_SetPinMode + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_GPIO_MODE_INPUT + * @arg @ref LL_GPIO_MODE_OUTPUT + * @arg @ref LL_GPIO_MODE_ALTERNATE + * @arg @ref LL_GPIO_MODE_ANALOG + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode) +{ + MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * GPIO_MODER_MODE1_Pos)), + (Mode << (POSITION_VAL(Pin) * GPIO_MODER_MODE1_Pos))); +} + +/** + * @brief Return gpio mode for a dedicated pin on dedicated port. + * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll MODER MODEy LL_GPIO_GetPinMode + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_MODE_INPUT + * @arg @ref LL_GPIO_MODE_OUTPUT + * @arg @ref LL_GPIO_MODE_ALTERNATE + * @arg @ref LL_GPIO_MODE_ANALOG + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(const GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->MODER, (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * GPIO_MODER_MODE1_Pos))) + >> (POSITION_VAL(Pin) * GPIO_MODER_MODE1_Pos)); +} + +/** + * @brief Configure gpio output type for several pins on dedicated port. + * @note Output type as to be set when gpio pin is in output or + * alternate modes. Possible type are Push-pull or Open-drain. + * @rmtoll OTYPER OTy LL_GPIO_SetPinOutputType + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @param OutputType This parameter can be one of the following values: + * @arg @ref LL_GPIO_OUTPUT_PUSHPULL + * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType) +{ + MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType)); +} + +/** + * @brief Return gpio output type for several pins on dedicated port. + * @note Output type as to be set when gpio pin is in output or + * alternate modes. Possible type are Push-pull or Open-drain. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll OTYPER OTy LL_GPIO_GetPinOutputType + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_OUTPUT_PUSHPULL + * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(const GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) >> POSITION_VAL(Pin)); +} + +/** + * @brief Configure gpio speed for a dedicated pin on dedicated port. + * @note I/O speed can be Low, Medium, Fast or High speed. + * @note Warning: only one pin can be passed as parameter. + * @note Refer to datasheet for frequency specifications and the power + * supply and load conditions for each speed. + * @rmtoll OSPEEDR OSPEEDy LL_GPIO_SetPinSpeed + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Speed This parameter can be one of the following values: + * @arg @ref LL_GPIO_SPEED_FREQ_LOW + * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM + * @arg @ref LL_GPIO_SPEED_FREQ_HIGH + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed) +{ + MODIFY_REG(GPIOx->OSPEEDR, (GPIO_OSPEEDR_OSPEED0 << (POSITION_VAL(Pin) * GPIO_OSPEEDR_OSPEED1_Pos)), + (Speed << (POSITION_VAL(Pin) * GPIO_OSPEEDR_OSPEED1_Pos))); +} + +/** + * @brief Return gpio speed for a dedicated pin on dedicated port. + * @note I/O speed can be Low, Medium, Fast or High speed. + * @note Warning: only one pin can be passed as parameter. + * @note Refer to datasheet for frequency specifications and the power + * supply and load conditions for each speed. + * @rmtoll OSPEEDR OSPEEDy LL_GPIO_GetPinSpeed + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_SPEED_FREQ_LOW + * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM + * @arg @ref LL_GPIO_SPEED_FREQ_HIGH + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(const GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->OSPEEDR, (GPIO_OSPEEDR_OSPEED0 << (POSITION_VAL(Pin) * GPIO_OSPEEDR_OSPEED1_Pos))) + >> (POSITION_VAL(Pin) * GPIO_OSPEEDR_OSPEED1_Pos)); +} + +/** + * @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll PUPDR PUPDy LL_GPIO_SetPinPull + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Pull This parameter can be one of the following values: + * @arg @ref LL_GPIO_PULL_NO + * @arg @ref LL_GPIO_PULL_UP + * @arg @ref LL_GPIO_PULL_DOWN + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull) +{ + MODIFY_REG(GPIOx->PUPDR, (GPIO_PUPDR_PUPD0 << (POSITION_VAL(Pin) * GPIO_PUPDR_PUPD1_Pos)), + (Pull << (POSITION_VAL(Pin) * GPIO_PUPDR_PUPD1_Pos))); +} + +/** + * @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port + * @note Warning: only one pin can be passed as parameter. + * @rmtoll PUPDR PUPDy LL_GPIO_GetPinPull + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_PULL_NO + * @arg @ref LL_GPIO_PULL_UP + * @arg @ref LL_GPIO_PULL_DOWN + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(const GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->PUPDR, (GPIO_PUPDR_PUPD0 << (POSITION_VAL(Pin) * GPIO_PUPDR_PUPD1_Pos))) + >> (POSITION_VAL(Pin) * GPIO_PUPDR_PUPD1_Pos)); +} + +/** + * @brief Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. + * @note Possible values are from AF0 to AF15 depending on target. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll AFRL AFSELy LL_GPIO_SetAFPin_0_7 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @param Alternate This parameter can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) +{ + MODIFY_REG(GPIOx->AFR[0], (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * GPIO_AFRL_AFSEL1_Pos)), + (Alternate << (POSITION_VAL(Pin) * GPIO_AFRL_AFSEL1_Pos))); +} + +/** + * @brief Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. + * @rmtoll AFRL AFSELy LL_GPIO_GetAFPin_0_7 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + */ +__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(const GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->AFR[0], (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * GPIO_AFRL_AFSEL1_Pos))) + >> (POSITION_VAL(Pin) * GPIO_AFRL_AFSEL1_Pos)); +} + +/** + * @brief Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port. + * @note Possible values are from AF0 to AF15 depending on target. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll AFRH AFSELy LL_GPIO_SetAFPin_8_15 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Alternate This parameter can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) +{ + MODIFY_REG(GPIOx->AFR[1], (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * GPIO_AFRH_AFSEL9_Pos)), + (Alternate << (POSITION_VAL(Pin >> 8U) * GPIO_AFRH_AFSEL9_Pos))); +} + +/** + * @brief Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port. + * @note Possible values are from AF0 to AF15 depending on target. + * @rmtoll AFRH AFSELy LL_GPIO_GetAFPin_8_15 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + */ +__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(const GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->AFR[1], (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * GPIO_AFRH_AFSEL9_Pos))) + >> (POSITION_VAL(Pin >> 8U) * GPIO_AFRH_AFSEL9_Pos)); +} + + +/** + * @brief Lock configuration of several pins for a dedicated port. + * @note When the lock sequence has been applied on a port bit, the + * value of this port bit can no longer be modified until the + * next reset. + * @note Each lock bit freezes a specific configuration register + * (control and alternate function registers). + * @rmtoll LCKR LCKK LL_GPIO_LockPin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + __IO uint32_t temp; + WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); + WRITE_REG(GPIOx->LCKR, PinMask); + WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); + /* Read LCKK register. This read is mandatory to complete key lock sequence */ + temp = READ_REG(GPIOx->LCKR); + (void) temp; +} + +/** + * @brief Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0. + * @rmtoll LCKR LCKy LL_GPIO_IsPinLocked + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(const GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return ((READ_BIT(GPIOx->LCKR, PinMask) == (PinMask)) ? 1UL : 0UL); +} + +/** + * @brief Return 1 if one of the pin of a dedicated port is locked. else return 0. + * @rmtoll LCKR LCKK LL_GPIO_IsAnyPinLocked + * @param GPIOx GPIO Port + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(const GPIO_TypeDef *GPIOx) +{ + return ((READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup GPIO_LL_EF_Data_Access Data Access + * @{ + */ + +/** + * @brief Return full input data register value for a dedicated port. + * @rmtoll IDR IDy LL_GPIO_ReadInputPort + * @param GPIOx GPIO Port + * @retval Input data register value of port + */ +__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(const GPIO_TypeDef *GPIOx) +{ + return (uint32_t)(READ_REG(GPIOx->IDR)); +} + +/** + * @brief Return if input data level for several pins of dedicated port is high or low. + * @rmtoll IDR IDy LL_GPIO_IsInputPinSet + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(const GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return ((READ_BIT(GPIOx->IDR, PinMask) == (PinMask)) ? 1UL : 0UL); +} + +/** + * @brief Write output data register for the port. + * @rmtoll ODR ODy LL_GPIO_WriteOutputPort + * @param GPIOx GPIO Port + * @param PortValue Level value for each pin of the port + * @retval None + */ +__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue) +{ + WRITE_REG(GPIOx->ODR, PortValue); +} + +/** + * @brief Return full output data register value for a dedicated port. + * @rmtoll ODR ODy LL_GPIO_ReadOutputPort + * @param GPIOx GPIO Port + * @retval Output data register value of port + */ +__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(const GPIO_TypeDef *GPIOx) +{ + return (uint32_t)(READ_REG(GPIOx->ODR)); +} + +/** + * @brief Return if input data level for several pins of dedicated port is high or low. + * @rmtoll ODR ODy LL_GPIO_IsOutputPinSet + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(const GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return ((READ_BIT(GPIOx->ODR, PinMask) == (PinMask)) ? 1UL : 0UL); +} + +/** + * @brief Set several pins to high level on dedicated gpio port. + * @rmtoll BSRR BSy LL_GPIO_SetOutputPin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + WRITE_REG(GPIOx->BSRR, PinMask); +} + +/** + * @brief Set several pins to low level on dedicated gpio port. + * @rmtoll BRR BRy LL_GPIO_ResetOutputPin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + WRITE_REG(GPIOx->BRR, PinMask); +} + +/** + * @brief Toggle data value for several pin of dedicated port. + * @rmtoll ODR ODy LL_GPIO_TogglePin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + uint32_t odr = READ_REG(GPIOx->ODR); + WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask)); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + * @brief Enable secure write only access for several pin of dedicated port. + * @rmtoll SECCFGR SECy LL_GPIO_EnablePinSecure + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_EnablePinSecure(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + SET_BIT(GPIOx->SECCFGR, PinMask); +} + + +/** + * @brief Disable secure write only access for several pin of dedicated port. + * @rmtoll SECCFGR SECy LL_GPIO_DisablePinSecure + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_DisablePinSecure(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + CLEAR_BIT(GPIOx->SECCFGR, PinMask); +} + + +/** + * @brief Return if secure write only access for several pin of dedicated port is enabled or not. + * @rmtoll SECCFGR SECy LL_GPIO_IsEnabledPinSecure + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsEnabledPinSecure(const GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return ((READ_BIT(GPIOx->SECCFGR, PinMask) == (PinMask)) ? 1UL : 0UL); +} + +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_GPIO_DeInit(const GPIO_TypeDef *GPIOx); +ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct); +void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOH) */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WBAxx_LL_GPIO_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_hsem.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_hsem.h new file mode 100644 index 0000000000..9f61e76eda --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_hsem.h @@ -0,0 +1,819 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_ll_hsem.h + * @author MCD Application Team + * @brief Header file of HSEM LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_LL_HSEM_H +#define STM32WBAxx_LL_HSEM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx.h" + +/** @addtogroup STM32WBAxx_LL_Driver + * @{ + */ + +#if defined(HSEM) + +/** @defgroup HSEM_LL HSEM + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup HSEM_LL_Exported_Constants HSEM Exported Constants + * @{ + */ + +/** @defgroup HSEM_LL_EC_LOCKID LOCKID Defines + * @{ + */ +#define LL_HSEM_LOCKID_NONE 0U +#define LL_HSEM_LOCKID_CPU1 HSEM_CR_LOCKID_CPU1 +#define LL_HSEM_LOCKID HSEM_CR_LOCKID_CURRENT +/** + * @} + */ + +/** @defgroup HSEM_LL_EC_ATTRIBUTES Attributes Defines + * @brief HSEM Privilege/NPrivilege and Secure/NSecure Attributes + * @{ + */ +#define LL_HSEM_NSEC_PRIV HSEM_R_PRIV /*!< NSecure and Privileged attribute */ +#define LL_HSEM_NSEC_NPRIV 0x0U /*!< NSecure and NPrivileged attribute */ +#define LL_HSEM_SEC_PRIV (HSEM_R_SEC | HSEM_R_PRIV) /*!< Secure and Privileged attribute */ +#define LL_HSEM_SEC_NPRIV HSEM_R_SEC /*!< Secure and NPrivileged attribute */ +/** + * @} + */ + +/** @defgroup HSEM_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_HSEM_ReadReg function + * @{ + */ + +#define LL_HSEM_SEMAPHORE_0 HSEM_IER_ISE0 +#define LL_HSEM_SEMAPHORE_1 HSEM_IER_ISE1 +#define LL_HSEM_SEMAPHORE_2 HSEM_IER_ISE2 +#define LL_HSEM_SEMAPHORE_3 HSEM_IER_ISE3 +#define LL_HSEM_SEMAPHORE_4 HSEM_IER_ISE4 +#define LL_HSEM_SEMAPHORE_5 HSEM_IER_ISE5 +#define LL_HSEM_SEMAPHORE_6 HSEM_IER_ISE6 +#define LL_HSEM_SEMAPHORE_7 HSEM_IER_ISE7 +#define LL_HSEM_SEMAPHORE_8 HSEM_IER_ISE8 +#define LL_HSEM_SEMAPHORE_9 HSEM_IER_ISE9 +#define LL_HSEM_SEMAPHORE_10 HSEM_IER_ISE10 +#define LL_HSEM_SEMAPHORE_11 HSEM_IER_ISE11 +#define LL_HSEM_SEMAPHORE_12 HSEM_IER_ISE12 +#define LL_HSEM_SEMAPHORE_13 HSEM_IER_ISE13 +#define LL_HSEM_SEMAPHORE_14 HSEM_IER_ISE14 +#define LL_HSEM_SEMAPHORE_15 HSEM_IER_ISE15 +#define LL_HSEM_SEMAPHORE_16 HSEM_IER_ISE16 +#define LL_HSEM_SEMAPHORE_17 HSEM_IER_ISE17 +#define LL_HSEM_SEMAPHORE_18 HSEM_IER_ISE18 +#define LL_HSEM_SEMAPHORE_19 HSEM_IER_ISE19 +#define LL_HSEM_SEMAPHORE_20 HSEM_IER_ISE20 +#define LL_HSEM_SEMAPHORE_21 HSEM_IER_ISE21 +#define LL_HSEM_SEMAPHORE_22 HSEM_IER_ISE22 +#define LL_HSEM_SEMAPHORE_23 HSEM_IER_ISE23 +#define LL_HSEM_SEMAPHORE_24 HSEM_IER_ISE24 +#define LL_HSEM_SEMAPHORE_25 HSEM_IER_ISE25 +#define LL_HSEM_SEMAPHORE_26 HSEM_IER_ISE26 +#define LL_HSEM_SEMAPHORE_27 HSEM_IER_ISE27 +#define LL_HSEM_SEMAPHORE_28 HSEM_IER_ISE28 +#define LL_HSEM_SEMAPHORE_29 HSEM_IER_ISE29 +#define LL_HSEM_SEMAPHORE_30 HSEM_IER_ISE30 +#define LL_HSEM_SEMAPHORE_31 HSEM_IER_ISE31 +#define LL_HSEM_SEMAPHORE_ALL 0xFFFFFFFFU +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup HSEM_LL_Exported_Macros HSEM Exported Macros + * @{ + */ + +/** @defgroup HSEM_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in HSEM register + * @param __INSTANCE__ HSEM Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_HSEM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in HSEM register + * @param __INSTANCE__ HSEM Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_HSEM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup HSEM_LL_Exported_Functions HSEM Exported Functions + * @{ + */ + +/** @defgroup HSEM_LL_EF_Data_Management Data_Management + * @{ + */ + + +/** + * @brief Return 1 if the semaphore is locked, else return 0. + * @rmtoll R LOCK LL_HSEM_IsSemaphoreLocked + * @param HSEMx HSEM Instance. + * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_HSEM_IsSemaphoreLocked(const HSEM_TypeDef *HSEMx, uint32_t Semaphore) +{ + return ((READ_BIT(HSEMx->R[Semaphore], HSEM_R_LOCK) == (HSEM_R_LOCK_Msk)) ? 1UL : 0UL); +} + +/** + * @brief Get core id. + * @rmtoll R LOCKID LL_HSEM_GetCoreId + * @param HSEMx HSEM Instance. + * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 + * @retval Returned value can be one of the following values: + * @arg @ref LL_HSEM_LOCKID_NONE + * @arg @ref LL_HSEM_LOCKID_CPU1 + */ +__STATIC_INLINE uint32_t LL_HSEM_GetCoreId(const HSEM_TypeDef *HSEMx, uint32_t Semaphore) +{ + return (uint32_t)(READ_BIT(HSEMx->R[Semaphore], HSEM_R_LOCKID_Msk)); +} + +/** + * @brief Get process id. + * @rmtoll R PROCID LL_HSEM_GetProcessId + * @param HSEMx HSEM Instance. + * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 + * @retval Process number. Value between Min_Data=0 and Max_Data=255 + */ +__STATIC_INLINE uint32_t LL_HSEM_GetProcessId(const HSEM_TypeDef *HSEMx, uint32_t Semaphore) +{ + return (uint32_t)(READ_BIT(HSEMx->R[Semaphore], HSEM_R_PROCID_Msk)); +} + +/** + * @brief Get the lock by writing in R register. + * @note The R register has to be read to determined if the lock is taken. + * @rmtoll R LOCK LL_HSEM_SetLock + * @rmtoll R LOCKID LL_HSEM_SetLock + * @rmtoll R PROCID LL_HSEM_SetLock + * @rmtoll R SEC LL_HSEM_SetLock + * @rmtoll R PRIV LL_HSEM_SetLock + * @param HSEMx HSEM Instance. + * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 + * @param process Process id. Value between Min_Data=0 and Max_Data=255 + * @param attribute Security and privilege attributes. Value can be one of the following: + * @arg @ref LL_HSEM_NSEC_PRIV + * @arg @ref LL_HSEM_NSEC_NPRIV + * @arg @ref LL_HSEM_SEC_PRIV + * @arg @ref LL_HSEM_SEC_NPRIV + * @retval None + */ +__STATIC_INLINE void LL_HSEM_SetLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t process, uint32_t attribute) +{ + WRITE_REG(HSEMx->R[Semaphore], (HSEM_R_LOCK | LL_HSEM_LOCKID | process | attribute)); +} + +/** + * @brief Get the lock with 2-step lock. + * @rmtoll R LOCK LL_HSEM_2StepLock + * @rmtoll R LOCKID LL_HSEM_2StepLock + * @rmtoll R PROCID LL_HSEM_2StepLock + * @rmtoll R SEC LL_HSEM_2StepLock + * @rmtoll R PRIV LL_HSEM_2StepLock + * @param HSEMx HSEM Instance. + * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 + * @param process Process id. Value between Min_Data=0 and Max_Data=255 + * @param attribute Security and privilege attributes. Value can be one of the following: + * @arg @ref LL_HSEM_NSEC_PRIV + * @arg @ref LL_HSEM_NSEC_NPRIV + * @arg @ref LL_HSEM_SEC_PRIV + * @arg @ref LL_HSEM_SEC_NPRIV + * @retval 1 lock fail, 0 lock successful or already locked by same process and core + */ +__STATIC_INLINE uint32_t LL_HSEM_2StepLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t process, uint32_t attribute) +{ + WRITE_REG(HSEMx->R[Semaphore], (HSEM_R_LOCK | LL_HSEM_LOCKID | process | attribute)); + return ((HSEMx->R[Semaphore] != (HSEM_R_LOCK | LL_HSEM_LOCKID | process | attribute)) ? 1UL : 0UL); +} + +/** + * @brief Get the lock with 1-step lock. + * @rmtoll RLR LOCK LL_HSEM_1StepLock + * @rmtoll RLR LOCKID LL_HSEM_1StepLock + * @rmtoll RLR PROCID LL_HSEM_1StepLock + * @rmtoll RLR SEC LL_HSEM_1StepLock + * @rmtoll RLR PRIV LL_HSEM_1StepLock + * @param HSEMx HSEM Instance. + * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 + * @param attribute Security and privilege attributes. Value can be one of the following: + * @arg @ref LL_HSEM_NSEC_PRIV + * @arg @ref LL_HSEM_NSEC_NPRIV + * @arg @ref LL_HSEM_SEC_PRIV + * @arg @ref LL_HSEM_SEC_NPRIV + * @retval 1 lock fail, 0 lock successful or already locked by same core + */ +__STATIC_INLINE uint32_t LL_HSEM_1StepLock(const HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t attribute) +{ + return ((HSEMx->RLR[Semaphore] != (HSEM_RLR_LOCK | LL_HSEM_LOCKID | attribute)) ? 1UL : 0UL); +} + +/** + * @brief Release the lock of the semaphore. + * @note In case of LL_HSEM_1StepLock usage to lock a semaphore, the process is 0. + * @rmtoll R LOCK LL_HSEM_ReleaseLock + * @rmtoll R SEC LL_HSEM_ReleaseLock + * @rmtoll R PRIV LL_HSEM_ReleaseLock + * @param HSEMx HSEM Instance. + * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 + * @param process Process number. Value between Min_Data=0 and Max_Data=255 + * @param attribute Security and privilege attributes. Value can be one of the following: + * @arg @ref LL_HSEM_NSEC_PRIV + * @arg @ref LL_HSEM_NSEC_NPRIV + * @arg @ref LL_HSEM_SEC_PRIV + * @arg @ref LL_HSEM_SEC_NPRIV + * @retval None + */ +__STATIC_INLINE void LL_HSEM_ReleaseLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t process, uint32_t attribute) +{ + WRITE_REG(HSEMx->R[Semaphore], (LL_HSEM_LOCKID | process | attribute)); +} + +/** + * @brief Get the lock status of the semaphore. + * @rmtoll R LOCK LL_HSEM_GetStatus + * @param HSEMx HSEM Instance. + * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 + * @retval 0 semaphore is free, 1 semaphore is locked */ +__STATIC_INLINE uint32_t LL_HSEM_GetStatus(const HSEM_TypeDef *HSEMx, uint32_t Semaphore) +{ + return ((HSEMx->R[Semaphore] != 0U) ? 1UL : 0UL); +} + +/** + * @brief Set the key. + * @rmtoll KEYR KEY LL_HSEM_SetKey + * @param HSEMx HSEM Instance. + * @param key Key value. + * @retval None + */ +__STATIC_INLINE void LL_HSEM_SetKey(HSEM_TypeDef *HSEMx, uint32_t key) +{ + WRITE_REG(HSEMx->KEYR, key << HSEM_KEYR_KEY_Pos); +} + +/** + * @brief Get the key. + * @rmtoll KEYR KEY LL_HSEM_GetKey + * @param HSEMx HSEM Instance. + * @retval key to unlock all semaphore from the same core + */ +__STATIC_INLINE uint32_t LL_HSEM_GetKey(const HSEM_TypeDef *HSEMx) +{ + return (uint32_t)(READ_BIT(HSEMx->KEYR, HSEM_KEYR_KEY) >> HSEM_KEYR_KEY_Pos); +} + +/** + * @brief Release all semaphore with the same core id. + * @rmtoll CR KEY LL_HSEM_ResetAllLock + * @param HSEMx HSEM Instance. + * @param key Key value. + * @param core This parameter can be one of the following values: + * @arg @ref LL_HSEM_LOCKID_CPU1 + * @param attribute Security and privilege attributes. Value can be one of the following: + * @arg @ref LL_HSEM_NSEC_PRIV + * @arg @ref LL_HSEM_NSEC_NPRIV + * @arg @ref LL_HSEM_SEC_PRIV + * @arg @ref LL_HSEM_SEC_NPRIV + * @retval None + */ +__STATIC_INLINE void LL_HSEM_ResetAllLock(HSEM_TypeDef *HSEMx, uint32_t key, uint32_t core, uint32_t attribute) +{ + WRITE_REG(HSEMx->CR, (key << HSEM_CR_KEY_Pos) | core | attribute); +} + +#if defined(HSEM_SECCFGR_SEC0) +/** + * @brief Set semaphore accessible by secure only. + * @rmtoll SECCFGR SEC LL_HSEM_SetSemaphoreSecure + * @param HSEMx HSEM Instance. + * @param SemMask This parameter can be a combination of the following values: + * @arg @ref LL_HSEM_SEMAPHORE_0 + * @arg @ref LL_HSEM_SEMAPHORE_1 + * @arg @ref LL_HSEM_SEMAPHORE_2 + * @arg @ref LL_HSEM_SEMAPHORE_3 + * @arg @ref LL_HSEM_SEMAPHORE_4 + * @arg @ref LL_HSEM_SEMAPHORE_5 + * @arg @ref LL_HSEM_SEMAPHORE_6 + * @arg @ref LL_HSEM_SEMAPHORE_7 + * @arg @ref LL_HSEM_SEMAPHORE_8 + * @arg @ref LL_HSEM_SEMAPHORE_9 + * @arg @ref LL_HSEM_SEMAPHORE_10 + * @arg @ref LL_HSEM_SEMAPHORE_11 + * @arg @ref LL_HSEM_SEMAPHORE_12 + * @arg @ref LL_HSEM_SEMAPHORE_13 + * @arg @ref LL_HSEM_SEMAPHORE_14 + * @arg @ref LL_HSEM_SEMAPHORE_15 + * @arg @ref LL_HSEM_SEMAPHORE_16 + * @arg @ref LL_HSEM_SEMAPHORE_ALL + * @retval None + */ +__STATIC_INLINE void LL_HSEM_SetSemaphoreSecure(HSEM_TypeDef *HSEMx, uint32_t SemMask) +{ + SET_BIT(HSEMx->SECCFGR, SemMask); +} + +/** + * @brief Set semaphore accessible by secure and non-secure. + * @rmtoll SECCFGR SEC LL_HSEM_SetSemaphoreNonSecure + * @param HSEMx HSEM Instance. + * @param SemMask This parameter can be a combination of the following values: + * @arg @ref LL_HSEM_SEMAPHORE_0 + * @arg @ref LL_HSEM_SEMAPHORE_1 + * @arg @ref LL_HSEM_SEMAPHORE_2 + * @arg @ref LL_HSEM_SEMAPHORE_3 + * @arg @ref LL_HSEM_SEMAPHORE_4 + * @arg @ref LL_HSEM_SEMAPHORE_5 + * @arg @ref LL_HSEM_SEMAPHORE_6 + * @arg @ref LL_HSEM_SEMAPHORE_7 + * @arg @ref LL_HSEM_SEMAPHORE_8 + * @arg @ref LL_HSEM_SEMAPHORE_9 + * @arg @ref LL_HSEM_SEMAPHORE_10 + * @arg @ref LL_HSEM_SEMAPHORE_11 + * @arg @ref LL_HSEM_SEMAPHORE_12 + * @arg @ref LL_HSEM_SEMAPHORE_13 + * @arg @ref LL_HSEM_SEMAPHORE_14 + * @arg @ref LL_HSEM_SEMAPHORE_15 + * @arg @ref LL_HSEM_SEMAPHORE_16 + * @arg @ref LL_HSEM_SEMAPHORE_ALL + * @retval None + */ +__STATIC_INLINE void LL_HSEM_SetSemaphoreNonSecure(HSEM_TypeDef *HSEMx, uint32_t SemMask) +{ + CLEAR_BIT(HSEMx->SECCFGR, SemMask); +} + +/** + * @brief Get security attribute of semaphore. + * @rmtoll SECCFGR SEC LL_HSEM_GetSemaphoreSecure + * @param HSEMx HSEM Instance. + * @retval Security attribute of semaphores + */ +__STATIC_INLINE uint32_t LL_HSEM_GetSemaphoreSecure(const HSEM_TypeDef *HSEMx) +{ + return HSEMx->SECCFGR; +} + +/** + * @brief Set semaphore accessible by privilege only. + * @rmtoll PRIVCFGR PRIV LL_HSEM_SetSemaphorePrivilege + * @param HSEMx HSEM Instance. + * @param SemMask This parameter can be a combination of the following values: + * @arg @ref LL_HSEM_SEMAPHORE_0 + * @arg @ref LL_HSEM_SEMAPHORE_1 + * @arg @ref LL_HSEM_SEMAPHORE_2 + * @arg @ref LL_HSEM_SEMAPHORE_3 + * @arg @ref LL_HSEM_SEMAPHORE_4 + * @arg @ref LL_HSEM_SEMAPHORE_5 + * @arg @ref LL_HSEM_SEMAPHORE_6 + * @arg @ref LL_HSEM_SEMAPHORE_7 + * @arg @ref LL_HSEM_SEMAPHORE_8 + * @arg @ref LL_HSEM_SEMAPHORE_9 + * @arg @ref LL_HSEM_SEMAPHORE_10 + * @arg @ref LL_HSEM_SEMAPHORE_11 + * @arg @ref LL_HSEM_SEMAPHORE_12 + * @arg @ref LL_HSEM_SEMAPHORE_13 + * @arg @ref LL_HSEM_SEMAPHORE_14 + * @arg @ref LL_HSEM_SEMAPHORE_15 + * @arg @ref LL_HSEM_SEMAPHORE_16 + * @arg @ref LL_HSEM_SEMAPHORE_ALL + * @retval None + */ +__STATIC_INLINE void LL_HSEM_SetSemaphorePrivilege(HSEM_TypeDef *HSEMx, uint32_t SemMask) +{ + SET_BIT(HSEMx->PRIVCFGR, SemMask); +} + +/** + * @brief Set semaphore accessible by privilege and non-privilege. + * @rmtoll PRIVCFGR PRIV LL_HSEM_SetSemaphoreNonPrivilege + * @param HSEMx HSEM Instance. + * @param SemMask This parameter can be a combination of the following values: + * @arg @ref LL_HSEM_SEMAPHORE_0 + * @arg @ref LL_HSEM_SEMAPHORE_1 + * @arg @ref LL_HSEM_SEMAPHORE_2 + * @arg @ref LL_HSEM_SEMAPHORE_3 + * @arg @ref LL_HSEM_SEMAPHORE_4 + * @arg @ref LL_HSEM_SEMAPHORE_5 + * @arg @ref LL_HSEM_SEMAPHORE_6 + * @arg @ref LL_HSEM_SEMAPHORE_7 + * @arg @ref LL_HSEM_SEMAPHORE_8 + * @arg @ref LL_HSEM_SEMAPHORE_9 + * @arg @ref LL_HSEM_SEMAPHORE_10 + * @arg @ref LL_HSEM_SEMAPHORE_11 + * @arg @ref LL_HSEM_SEMAPHORE_12 + * @arg @ref LL_HSEM_SEMAPHORE_13 + * @arg @ref LL_HSEM_SEMAPHORE_14 + * @arg @ref LL_HSEM_SEMAPHORE_15 + * @arg @ref LL_HSEM_SEMAPHORE_16 + * @arg @ref LL_HSEM_SEMAPHORE_ALL + * @retval None + */ +__STATIC_INLINE void LL_HSEM_SetSemaphoreNonPrivilege(HSEM_TypeDef *HSEMx, uint32_t SemMask) +{ + CLEAR_BIT(HSEMx->PRIVCFGR, SemMask); +} + +/** + * @brief Get privilege attribute of semaphore. + * @rmtoll PRIVCFGR PRIV LL_HSEM_GetSemaphorePrivilege + * @param HSEMx HSEM Instance. + * @retval Privilege attribute of semaphores + */ +__STATIC_INLINE uint32_t LL_HSEM_GetSemaphorePrivilege(const HSEM_TypeDef *HSEMx) +{ + return HSEMx->PRIVCFGR; +} + +#endif +/** + * @} + */ + +/** @defgroup HSEM_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable interrupt. + * @rmtoll IER ISEM LL_HSEM_EnableIT_IER + * @param HSEMx HSEM Instance. + * @param SemaphoreMask This parameter can be a combination of the following values: + * @arg @ref LL_HSEM_SEMAPHORE_0 + * @arg @ref LL_HSEM_SEMAPHORE_1 + * @arg @ref LL_HSEM_SEMAPHORE_2 + * @arg @ref LL_HSEM_SEMAPHORE_3 + * @arg @ref LL_HSEM_SEMAPHORE_4 + * @arg @ref LL_HSEM_SEMAPHORE_5 + * @arg @ref LL_HSEM_SEMAPHORE_6 + * @arg @ref LL_HSEM_SEMAPHORE_7 + * @arg @ref LL_HSEM_SEMAPHORE_8 + * @arg @ref LL_HSEM_SEMAPHORE_9 + * @arg @ref LL_HSEM_SEMAPHORE_10 + * @arg @ref LL_HSEM_SEMAPHORE_11 + * @arg @ref LL_HSEM_SEMAPHORE_12 + * @arg @ref LL_HSEM_SEMAPHORE_13 + * @arg @ref LL_HSEM_SEMAPHORE_14 + * @arg @ref LL_HSEM_SEMAPHORE_15 + * @arg @ref LL_HSEM_SEMAPHORE_16 + * @arg @ref LL_HSEM_SEMAPHORE_17 + * @arg @ref LL_HSEM_SEMAPHORE_18 + * @arg @ref LL_HSEM_SEMAPHORE_19 + * @arg @ref LL_HSEM_SEMAPHORE_20 + * @arg @ref LL_HSEM_SEMAPHORE_21 + * @arg @ref LL_HSEM_SEMAPHORE_22 + * @arg @ref LL_HSEM_SEMAPHORE_23 + * @arg @ref LL_HSEM_SEMAPHORE_24 + * @arg @ref LL_HSEM_SEMAPHORE_25 + * @arg @ref LL_HSEM_SEMAPHORE_26 + * @arg @ref LL_HSEM_SEMAPHORE_27 + * @arg @ref LL_HSEM_SEMAPHORE_28 + * @arg @ref LL_HSEM_SEMAPHORE_29 + * @arg @ref LL_HSEM_SEMAPHORE_30 + * @arg @ref LL_HSEM_SEMAPHORE_31 + * @arg @ref LL_HSEM_SEMAPHORE_ALL + * @retval None + */ +__STATIC_INLINE void LL_HSEM_EnableIT_IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +{ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SET_BIT(HSEMx->SIER, SemaphoreMask); +#else + SET_BIT(HSEMx->IER, SemaphoreMask); +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +} + +/** + * @brief Disable interrupt. + * @rmtoll IER ISEM LL_HSEM_DisableIT_IER + * @param HSEMx HSEM Instance. + * @param SemaphoreMask This parameter can be a combination of the following values: + * @arg @ref LL_HSEM_SEMAPHORE_0 + * @arg @ref LL_HSEM_SEMAPHORE_1 + * @arg @ref LL_HSEM_SEMAPHORE_2 + * @arg @ref LL_HSEM_SEMAPHORE_3 + * @arg @ref LL_HSEM_SEMAPHORE_4 + * @arg @ref LL_HSEM_SEMAPHORE_5 + * @arg @ref LL_HSEM_SEMAPHORE_6 + * @arg @ref LL_HSEM_SEMAPHORE_7 + * @arg @ref LL_HSEM_SEMAPHORE_8 + * @arg @ref LL_HSEM_SEMAPHORE_9 + * @arg @ref LL_HSEM_SEMAPHORE_10 + * @arg @ref LL_HSEM_SEMAPHORE_11 + * @arg @ref LL_HSEM_SEMAPHORE_12 + * @arg @ref LL_HSEM_SEMAPHORE_13 + * @arg @ref LL_HSEM_SEMAPHORE_14 + * @arg @ref LL_HSEM_SEMAPHORE_15 + * @arg @ref LL_HSEM_SEMAPHORE_16 + * @arg @ref LL_HSEM_SEMAPHORE_17 + * @arg @ref LL_HSEM_SEMAPHORE_18 + * @arg @ref LL_HSEM_SEMAPHORE_19 + * @arg @ref LL_HSEM_SEMAPHORE_20 + * @arg @ref LL_HSEM_SEMAPHORE_21 + * @arg @ref LL_HSEM_SEMAPHORE_22 + * @arg @ref LL_HSEM_SEMAPHORE_23 + * @arg @ref LL_HSEM_SEMAPHORE_24 + * @arg @ref LL_HSEM_SEMAPHORE_25 + * @arg @ref LL_HSEM_SEMAPHORE_26 + * @arg @ref LL_HSEM_SEMAPHORE_27 + * @arg @ref LL_HSEM_SEMAPHORE_28 + * @arg @ref LL_HSEM_SEMAPHORE_29 + * @arg @ref LL_HSEM_SEMAPHORE_30 + * @arg @ref LL_HSEM_SEMAPHORE_31 + * @arg @ref LL_HSEM_SEMAPHORE_ALL + * @retval None + */ +__STATIC_INLINE void LL_HSEM_DisableIT_IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +{ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + CLEAR_BIT(HSEMx->SIER, SemaphoreMask); +#else + CLEAR_BIT(HSEMx->IER, SemaphoreMask); +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +} + +/** + * @brief Check if interrupt is enabled. + * @rmtoll IER ISEM LL_HSEM_IsEnabledIT_IER + * @param HSEMx HSEM Instance. + * @param SemaphoreMask This parameter can be a combination of the following values: + * @arg @ref LL_HSEM_SEMAPHORE_0 + * @arg @ref LL_HSEM_SEMAPHORE_1 + * @arg @ref LL_HSEM_SEMAPHORE_2 + * @arg @ref LL_HSEM_SEMAPHORE_3 + * @arg @ref LL_HSEM_SEMAPHORE_4 + * @arg @ref LL_HSEM_SEMAPHORE_5 + * @arg @ref LL_HSEM_SEMAPHORE_6 + * @arg @ref LL_HSEM_SEMAPHORE_7 + * @arg @ref LL_HSEM_SEMAPHORE_8 + * @arg @ref LL_HSEM_SEMAPHORE_9 + * @arg @ref LL_HSEM_SEMAPHORE_10 + * @arg @ref LL_HSEM_SEMAPHORE_11 + * @arg @ref LL_HSEM_SEMAPHORE_12 + * @arg @ref LL_HSEM_SEMAPHORE_13 + * @arg @ref LL_HSEM_SEMAPHORE_14 + * @arg @ref LL_HSEM_SEMAPHORE_15 + * @arg @ref LL_HSEM_SEMAPHORE_16 + * @arg @ref LL_HSEM_SEMAPHORE_17 + * @arg @ref LL_HSEM_SEMAPHORE_18 + * @arg @ref LL_HSEM_SEMAPHORE_19 + * @arg @ref LL_HSEM_SEMAPHORE_20 + * @arg @ref LL_HSEM_SEMAPHORE_21 + * @arg @ref LL_HSEM_SEMAPHORE_22 + * @arg @ref LL_HSEM_SEMAPHORE_23 + * @arg @ref LL_HSEM_SEMAPHORE_24 + * @arg @ref LL_HSEM_SEMAPHORE_25 + * @arg @ref LL_HSEM_SEMAPHORE_26 + * @arg @ref LL_HSEM_SEMAPHORE_27 + * @arg @ref LL_HSEM_SEMAPHORE_28 + * @arg @ref LL_HSEM_SEMAPHORE_29 + * @arg @ref LL_HSEM_SEMAPHORE_30 + * @arg @ref LL_HSEM_SEMAPHORE_31 + * @arg @ref LL_HSEM_SEMAPHORE_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_HSEM_IsEnabledIT_IER(const HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +{ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + return ((READ_BIT(HSEMx->SIER, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); +#else + return ((READ_BIT(HSEMx->IER, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +} + + +/** + * @} + */ + +/** @defgroup HSEM_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Clear interrupt status. + * @rmtoll ICR ISEM LL_HSEM_ClearFlag_ICR + * @param HSEMx HSEM Instance. + * @param SemaphoreMask This parameter can be a combination of the following values: + * @arg @ref LL_HSEM_SEMAPHORE_0 + * @arg @ref LL_HSEM_SEMAPHORE_1 + * @arg @ref LL_HSEM_SEMAPHORE_2 + * @arg @ref LL_HSEM_SEMAPHORE_3 + * @arg @ref LL_HSEM_SEMAPHORE_4 + * @arg @ref LL_HSEM_SEMAPHORE_5 + * @arg @ref LL_HSEM_SEMAPHORE_6 + * @arg @ref LL_HSEM_SEMAPHORE_7 + * @arg @ref LL_HSEM_SEMAPHORE_8 + * @arg @ref LL_HSEM_SEMAPHORE_9 + * @arg @ref LL_HSEM_SEMAPHORE_10 + * @arg @ref LL_HSEM_SEMAPHORE_11 + * @arg @ref LL_HSEM_SEMAPHORE_12 + * @arg @ref LL_HSEM_SEMAPHORE_13 + * @arg @ref LL_HSEM_SEMAPHORE_14 + * @arg @ref LL_HSEM_SEMAPHORE_15 + * @arg @ref LL_HSEM_SEMAPHORE_16 + * @arg @ref LL_HSEM_SEMAPHORE_17 + * @arg @ref LL_HSEM_SEMAPHORE_18 + * @arg @ref LL_HSEM_SEMAPHORE_19 + * @arg @ref LL_HSEM_SEMAPHORE_20 + * @arg @ref LL_HSEM_SEMAPHORE_21 + * @arg @ref LL_HSEM_SEMAPHORE_22 + * @arg @ref LL_HSEM_SEMAPHORE_23 + * @arg @ref LL_HSEM_SEMAPHORE_24 + * @arg @ref LL_HSEM_SEMAPHORE_25 + * @arg @ref LL_HSEM_SEMAPHORE_26 + * @arg @ref LL_HSEM_SEMAPHORE_27 + * @arg @ref LL_HSEM_SEMAPHORE_28 + * @arg @ref LL_HSEM_SEMAPHORE_29 + * @arg @ref LL_HSEM_SEMAPHORE_30 + * @arg @ref LL_HSEM_SEMAPHORE_31 + * @arg @ref LL_HSEM_SEMAPHORE_ALL + * @retval None + */ +__STATIC_INLINE void LL_HSEM_ClearFlag_ICR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +{ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + WRITE_REG(HSEMx->SICR, SemaphoreMask); +#else + WRITE_REG(HSEMx->ICR, SemaphoreMask); +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +} + +/** + * @brief Get interrupt status from ISR register. + * @rmtoll ISR ISEM LL_HSEM_IsActiveFlag_ISR + * @param HSEMx HSEM Instance. + * @param SemaphoreMask This parameter can be a combination of the following values: + * @arg @ref LL_HSEM_SEMAPHORE_0 + * @arg @ref LL_HSEM_SEMAPHORE_1 + * @arg @ref LL_HSEM_SEMAPHORE_2 + * @arg @ref LL_HSEM_SEMAPHORE_3 + * @arg @ref LL_HSEM_SEMAPHORE_4 + * @arg @ref LL_HSEM_SEMAPHORE_5 + * @arg @ref LL_HSEM_SEMAPHORE_6 + * @arg @ref LL_HSEM_SEMAPHORE_7 + * @arg @ref LL_HSEM_SEMAPHORE_8 + * @arg @ref LL_HSEM_SEMAPHORE_9 + * @arg @ref LL_HSEM_SEMAPHORE_10 + * @arg @ref LL_HSEM_SEMAPHORE_11 + * @arg @ref LL_HSEM_SEMAPHORE_12 + * @arg @ref LL_HSEM_SEMAPHORE_13 + * @arg @ref LL_HSEM_SEMAPHORE_14 + * @arg @ref LL_HSEM_SEMAPHORE_15 + * @arg @ref LL_HSEM_SEMAPHORE_16 + * @arg @ref LL_HSEM_SEMAPHORE_17 + * @arg @ref LL_HSEM_SEMAPHORE_18 + * @arg @ref LL_HSEM_SEMAPHORE_19 + * @arg @ref LL_HSEM_SEMAPHORE_20 + * @arg @ref LL_HSEM_SEMAPHORE_21 + * @arg @ref LL_HSEM_SEMAPHORE_22 + * @arg @ref LL_HSEM_SEMAPHORE_23 + * @arg @ref LL_HSEM_SEMAPHORE_24 + * @arg @ref LL_HSEM_SEMAPHORE_25 + * @arg @ref LL_HSEM_SEMAPHORE_26 + * @arg @ref LL_HSEM_SEMAPHORE_27 + * @arg @ref LL_HSEM_SEMAPHORE_28 + * @arg @ref LL_HSEM_SEMAPHORE_29 + * @arg @ref LL_HSEM_SEMAPHORE_30 + * @arg @ref LL_HSEM_SEMAPHORE_31 + * @arg @ref LL_HSEM_SEMAPHORE_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_ISR(const HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +{ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + return ((READ_BIT(HSEMx->SISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); +#else + return ((READ_BIT(HSEMx->ISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +} + +/** + * @brief Get interrupt status from MISR register. + * @rmtoll MISR ISEM LL_HSEM_IsActiveFlag_MISR + * @param HSEMx HSEM Instance. + * @param SemaphoreMask This parameter can be a combination of the following values: + * @arg @ref LL_HSEM_SEMAPHORE_0 + * @arg @ref LL_HSEM_SEMAPHORE_1 + * @arg @ref LL_HSEM_SEMAPHORE_2 + * @arg @ref LL_HSEM_SEMAPHORE_3 + * @arg @ref LL_HSEM_SEMAPHORE_4 + * @arg @ref LL_HSEM_SEMAPHORE_5 + * @arg @ref LL_HSEM_SEMAPHORE_6 + * @arg @ref LL_HSEM_SEMAPHORE_7 + * @arg @ref LL_HSEM_SEMAPHORE_8 + * @arg @ref LL_HSEM_SEMAPHORE_9 + * @arg @ref LL_HSEM_SEMAPHORE_10 + * @arg @ref LL_HSEM_SEMAPHORE_11 + * @arg @ref LL_HSEM_SEMAPHORE_12 + * @arg @ref LL_HSEM_SEMAPHORE_13 + * @arg @ref LL_HSEM_SEMAPHORE_14 + * @arg @ref LL_HSEM_SEMAPHORE_15 + * @arg @ref LL_HSEM_SEMAPHORE_16 + * @arg @ref LL_HSEM_SEMAPHORE_17 + * @arg @ref LL_HSEM_SEMAPHORE_18 + * @arg @ref LL_HSEM_SEMAPHORE_19 + * @arg @ref LL_HSEM_SEMAPHORE_20 + * @arg @ref LL_HSEM_SEMAPHORE_21 + * @arg @ref LL_HSEM_SEMAPHORE_22 + * @arg @ref LL_HSEM_SEMAPHORE_23 + * @arg @ref LL_HSEM_SEMAPHORE_24 + * @arg @ref LL_HSEM_SEMAPHORE_25 + * @arg @ref LL_HSEM_SEMAPHORE_26 + * @arg @ref LL_HSEM_SEMAPHORE_27 + * @arg @ref LL_HSEM_SEMAPHORE_28 + * @arg @ref LL_HSEM_SEMAPHORE_29 + * @arg @ref LL_HSEM_SEMAPHORE_30 + * @arg @ref LL_HSEM_SEMAPHORE_31 + * @arg @ref LL_HSEM_SEMAPHORE_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_MISR(const HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +{ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + return ((READ_BIT(HSEMx->SMISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); +#else + return ((READ_BIT(HSEMx->MISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(HSEM) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32WBAxx_LL_HSEM_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_i2c.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_i2c.h new file mode 100644 index 0000000000..fec55e8434 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_i2c.h @@ -0,0 +1,2611 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_ll_i2c.h + * @author MCD Application Team + * @brief Header file of I2C LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_LL_I2C_H +#define STM32WBAxx_LL_I2C_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx.h" + +/** @addtogroup STM32WBAxx_LL_Driver + * @{ + */ + +#if defined (I2C1) || defined (I2C3) + +/** @defgroup I2C_LL I2C + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup I2C_LL_Private_Constants I2C Private Constants + * @{ + */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup I2C_LL_Private_Macros I2C Private Macros + * @{ + */ +#if defined(I2C_TRIG_GRP1) +#define IS_LL_I2C_GRP1_INSTANCE(__INSTANCE__) IS_I2C_GRP1_INSTANCE(__INSTANCE__) +#endif /* I2C_TRIG_GRP1 */ + +#define IS_LL_I2C_GRP2_INSTANCE(__INSTANCE__) IS_I2C_GRP2_INSTANCE(__INSTANCE__) +/** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup I2C_LL_ES_INIT I2C Exported Init structure + * @{ + */ +typedef struct +{ + uint32_t PeripheralMode; /*!< Specifies the peripheral mode. + This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE. + + This feature can be modified afterwards using unitary function + @ref LL_I2C_SetMode(). */ + + uint32_t Timing; /*!< Specifies the SDA setup, hold time and the SCL high, low period values. + This parameter must be set by referring to the STM32CubeMX Tool and + the helper macro @ref __LL_I2C_CONVERT_TIMINGS(). + + This feature can be modified afterwards using unitary function + @ref LL_I2C_SetTiming(). */ + + uint32_t AnalogFilter; /*!< Enables or disables analog noise filter. + This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION. + + This feature can be modified afterwards using unitary functions + @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */ + + uint32_t DigitalFilter; /*!< Configures the digital noise filter. + This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F. + + This feature can be modified afterwards using unitary function + @ref LL_I2C_SetDigitalFilter(). */ + + uint32_t OwnAddress1; /*!< Specifies the device own address 1. + This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF. + + This feature can be modified afterwards using unitary function + @ref LL_I2C_SetOwnAddress1(). */ + + uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive + match code or next received byte. + This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE. + + This feature can be modified afterwards using unitary function + @ref LL_I2C_AcknowledgeNextData(). */ + + uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit). + This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1. + + This feature can be modified afterwards using unitary function + @ref LL_I2C_SetOwnAddress1(). */ +} LL_I2C_InitTypeDef; +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup I2C_LL_Exported_Constants I2C Exported Constants + * @{ + */ + +/** @defgroup I2C_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_I2C_WriteReg function + * @{ + */ +#define LL_I2C_ICR_ADDRCF I2C_ICR_ADDRCF /*!< Address Matched flag */ +#define LL_I2C_ICR_NACKCF I2C_ICR_NACKCF /*!< Not Acknowledge flag */ +#define LL_I2C_ICR_STOPCF I2C_ICR_STOPCF /*!< Stop detection flag */ +#define LL_I2C_ICR_BERRCF I2C_ICR_BERRCF /*!< Bus error flag */ +#define LL_I2C_ICR_ARLOCF I2C_ICR_ARLOCF /*!< Arbitration Lost flag */ +#define LL_I2C_ICR_OVRCF I2C_ICR_OVRCF /*!< Overrun/Underrun flag */ +#define LL_I2C_ICR_PECCF I2C_ICR_PECCF /*!< PEC error flag */ +#define LL_I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF /*!< Timeout detection flag */ +#define LL_I2C_ICR_ALERTCF I2C_ICR_ALERTCF /*!< Alert flag */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_I2C_ReadReg function + * @{ + */ +#define LL_I2C_ISR_TXE I2C_ISR_TXE /*!< Transmit data register empty */ +#define LL_I2C_ISR_TXIS I2C_ISR_TXIS /*!< Transmit interrupt status */ +#define LL_I2C_ISR_RXNE I2C_ISR_RXNE /*!< Receive data register not empty */ +#define LL_I2C_ISR_ADDR I2C_ISR_ADDR /*!< Address matched (slave mode) */ +#define LL_I2C_ISR_NACKF I2C_ISR_NACKF /*!< Not Acknowledge received flag */ +#define LL_I2C_ISR_STOPF I2C_ISR_STOPF /*!< Stop detection flag */ +#define LL_I2C_ISR_TC I2C_ISR_TC /*!< Transfer Complete (master mode) */ +#define LL_I2C_ISR_TCR I2C_ISR_TCR /*!< Transfer Complete Reload */ +#define LL_I2C_ISR_BERR I2C_ISR_BERR /*!< Bus error */ +#define LL_I2C_ISR_ARLO I2C_ISR_ARLO /*!< Arbitration lost */ +#define LL_I2C_ISR_OVR I2C_ISR_OVR /*!< Overrun/Underrun (slave mode) */ +#define LL_I2C_ISR_PECERR I2C_ISR_PECERR /*!< PEC Error in reception (SMBus mode) */ +#define LL_I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT /*!< Timeout detection flag (SMBus mode) */ +#define LL_I2C_ISR_ALERT I2C_ISR_ALERT /*!< SMBus alert (SMBus mode) */ +#define LL_I2C_ISR_BUSY I2C_ISR_BUSY /*!< Bus busy */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions + * @{ + */ +#define LL_I2C_CR1_TXIE I2C_CR1_TXIE /*!< TX Interrupt enable */ +#define LL_I2C_CR1_RXIE I2C_CR1_RXIE /*!< RX Interrupt enable */ +#define LL_I2C_CR1_ADDRIE I2C_CR1_ADDRIE /*!< Address match Interrupt enable (slave only) */ +#define LL_I2C_CR1_NACKIE I2C_CR1_NACKIE /*!< Not acknowledge received Interrupt enable */ +#define LL_I2C_CR1_STOPIE I2C_CR1_STOPIE /*!< STOP detection Interrupt enable */ +#define LL_I2C_CR1_TCIE I2C_CR1_TCIE /*!< Transfer Complete interrupt enable */ +#define LL_I2C_CR1_ERRIE I2C_CR1_ERRIE /*!< Error interrupts enable */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode + * @{ + */ +#define LL_I2C_MODE_I2C 0x00000000U /*!< I2C Master or Slave mode */ +#define LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN /*!< SMBus Host address acknowledge */ +#define LL_I2C_MODE_SMBUS_DEVICE 0x00000000U /*!< SMBus Device default mode + (Default address not acknowledge) */ +#define LL_I2C_MODE_SMBUS_DEVICE_ARP I2C_CR1_SMBDEN /*!< SMBus Device Default address acknowledge */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection + * @{ + */ +#define LL_I2C_ANALOGFILTER_ENABLE 0x00000000U /*!< Analog filter is enabled. */ +#define LL_I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF /*!< Analog filter is disabled. */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_ADDRESSING_MODE Master Addressing Mode + * @{ + */ +#define LL_I2C_ADDRESSING_MODE_7BIT 0x00000000U /*!< Master operates in 7-bit addressing mode. */ +#define LL_I2C_ADDRESSING_MODE_10BIT I2C_CR2_ADD10 /*!< Master operates in 10-bit addressing mode.*/ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length + * @{ + */ +#define LL_I2C_OWNADDRESS1_7BIT 0x00000000U /*!< Own address 1 is a 7-bit address. */ +#define LL_I2C_OWNADDRESS1_10BIT I2C_OAR1_OA1MODE /*!< Own address 1 is a 10-bit address.*/ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_OWNADDRESS2 Own Address 2 Masks + * @{ + */ +#define LL_I2C_OWNADDRESS2_NOMASK I2C_OAR2_OA2NOMASK /*!< Own Address2 No mask. */ +#define LL_I2C_OWNADDRESS2_MASK01 I2C_OAR2_OA2MASK01 /*!< Only Address2 bits[7:2] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK02 I2C_OAR2_OA2MASK02 /*!< Only Address2 bits[7:3] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK03 I2C_OAR2_OA2MASK03 /*!< Only Address2 bits[7:4] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK04 I2C_OAR2_OA2MASK04 /*!< Only Address2 bits[7:5] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK05 I2C_OAR2_OA2MASK05 /*!< Only Address2 bits[7:6] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK06 I2C_OAR2_OA2MASK06 /*!< Only Address2 bits[7] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK07 I2C_OAR2_OA2MASK07 /*!< No comparison is done. + All Address2 are acknowledged. */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation + * @{ + */ +#define LL_I2C_ACK 0x00000000U /*!< ACK is sent after current received byte. */ +#define LL_I2C_NACK I2C_CR2_NACK /*!< NACK is sent after current received byte.*/ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_ADDRSLAVE Slave Address Length + * @{ + */ +#define LL_I2C_ADDRSLAVE_7BIT 0x00000000U /*!< Slave Address in 7-bit. */ +#define LL_I2C_ADDRSLAVE_10BIT I2C_CR2_ADD10 /*!< Slave Address in 10-bit.*/ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_REQUEST Transfer Request Direction + * @{ + */ +#define LL_I2C_REQUEST_WRITE 0x00000000U /*!< Master request a write transfer. */ +#define LL_I2C_REQUEST_READ I2C_CR2_RD_WRN /*!< Master request a read transfer. */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_MODE Transfer End Mode + * @{ + */ +#define LL_I2C_MODE_RELOAD I2C_CR2_RELOAD /*!< Enable I2C Reload mode. */ +#define LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND /*!< Enable I2C Automatic end mode + with no HW PEC comparison. */ +#define LL_I2C_MODE_SOFTEND 0x00000000U /*!< Enable I2C Software end mode + with no HW PEC comparison. */ +#define LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD /*!< Enable SMBUS Automatic end mode + with HW PEC comparison. */ +#define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND /*!< Enable SMBUS Automatic end mode + with HW PEC comparison. */ +#define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND /*!< Enable SMBUS Software end mode + with HW PEC comparison. */ +#define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE) +/*!< Enable SMBUS Automatic end mode with HW PEC comparison. */ +#define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE) +/*!< Enable SMBUS Software end mode with HW PEC comparison. */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation + * @{ + */ +#define LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U +/*!< Don't Generate Stop and Start condition. */ +#define LL_I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) +/*!< Generate Stop condition (Size should be set to 0). */ +#define LL_I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) +/*!< Generate Start for read request. */ +#define LL_I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) +/*!< Generate Start for write request. */ +#define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) +/*!< Generate Restart for read request, slave 7Bit address. */ +#define LL_I2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) +/*!< Generate Restart for write request, slave 7Bit address. */ +#define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | \ + I2C_CR2_RD_WRN | I2C_CR2_HEAD10R) +/*!< Generate Restart for read request, slave 10Bit address. */ +#define LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) +/*!< Generate Restart for write request, slave 10Bit address.*/ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_DIRECTION Read Write Direction + * @{ + */ +#define LL_I2C_DIRECTION_WRITE 0x00000000U /*!< Write transfer request by master, + slave enters receiver mode. */ +#define LL_I2C_DIRECTION_READ I2C_ISR_DIR /*!< Read transfer request by master, + slave enters transmitter mode.*/ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_DMA_REG_DATA DMA Register Data + * @{ + */ +#define LL_I2C_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for + transmission */ +#define LL_I2C_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for + reception */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout + * @{ + */ +#define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U /*!< TimeoutA is used to detect + SCL low level timeout. */ +#define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE /*!< TimeoutA is used to detect + both SCL and SDA high level timeout.*/ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection + * @{ + */ +#define LL_I2C_SMBUS_TIMEOUTA I2C_TIMEOUTR_TIMOUTEN /*!< TimeoutA enable bit */ +#define LL_I2C_SMBUS_TIMEOUTB I2C_TIMEOUTR_TEXTEN /*!< TimeoutB (extended clock) + enable bit */ +#define LL_I2C_SMBUS_ALL_TIMEOUT (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | \ + I2C_TIMEOUTR_TEXTEN) /*!< TimeoutA and TimeoutB +(extended clock) enable bits */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_AUTOCR_TRIGSEL Autonomous Trigger selection + * @brief I2C Autonomous Trigger selection + * @{ + */ +#if defined(I2C1) +#define LL_I2C_TRIG_GRP1 (0x10000000U) /*!< Trigger Group for I2C1 */ +#endif /* I2C1 */ +#define LL_I2C_TRIG_GRP2 (0x20000000U) /*!< Trigger Group for I2C3 */ + +#if defined(I2C_TRIG_GRP1) +#define LL_I2C_GRP1_GPDMA_CH0_TCF_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x00000000U)) +/*!< HW Trigger signal is GPDMA_CH0_TRG */ +#define LL_I2C_GRP1_GPDMA_CH1_TCF_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x1U << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is GPDMA_CH1_TRG */ +#define LL_I2C_GRP1_GPDMA_CH2_TCF_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x2U << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is GPDMA_CH2_TRG */ +#define LL_I2C_GRP1_GPDMA_CH3_TCF_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x3U << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is GPDMA_CH3_TRG */ +#define LL_I2C_GRP1_EXTI5_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x4U << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is EXTI5_TRG */ +#define LL_I2C_GRP1_EXTI9_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x5U << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is EXTI9_TRG */ +#define LL_I2C_GRP1_LPTIM1_CH1_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x6U << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is LPTIM1_CH1_TRG */ +#define LL_I2C_GRP1_LPTIM2_CH1_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x7U << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is LPTIM2_CH1_TRG */ +#if defined(COMP1) +#define LL_I2C_GRP1_COMP1_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x8U << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is COMP1_TRG */ +#endif /* COMP1 */ +#if defined(COMP2) +#define LL_I2C_GRP1_COMP2_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x9U << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is COMP2_TRG */ +#endif /* COMP2 */ +#define LL_I2C_GRP1_RTC_ALRA_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0xAU << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is RTC_ALRA_TRG */ +#define LL_I2C_GRP1_RTC_WUT_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0xBU << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is RTC_WUT_TRG */ +#endif /* I2C_TRIG_GRP1 */ + +#define LL_I2C_GRP2_GPDMA_CH0_TCF_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0x00000000U)) +/*!< HW Trigger signal is GPDMA_CH0_TRG */ +#define LL_I2C_GRP2_GPDMA_CH1_TCF_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0x1U << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is GPDMA_CH1_TRG */ +#define LL_I2C_GRP2_GPDMA_CH2_TCF_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0x2U << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is GPDMA_CH2_TRG */ +#define LL_I2C_GRP2_GPDMA_CH3_TCF_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0x3U << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is GPDMA_CH3_TRG */ +#define LL_I2C_GRP2_EXTI5_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0x4U << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is EXTI5_TRG */ +#define LL_I2C_GRP2_EXTI8_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0x5U << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is EXTI8_TRG */ +#define LL_I2C_GRP2_LPTIM1_CH1_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0x6U << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is LPTIM1_CH1_TRG */ +#if defined(COMP1) +#define LL_I2C_GRP2_COMP1_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0x8U << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is COMP1_TRG */ +#endif /* COMP1 */ +#if defined(COMP2) +#define LL_I2C_GRP2_COMP2_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0x9U << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is COMP2_TRG */ +#endif /* COMP2 */ +#define LL_I2C_GRP2_RTC_ALRA_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0xAU << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is RTC_ALRA_TRG */ +#define LL_I2C_GRP2_RTC_WUT_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0xBU << I2C_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is RTC_WUT_TRG */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_AUTOCR_TRIGPOL Autonomous Trigger Polarity + * @brief I2C Autonomous Trigger Polarity + * @{ + */ +#define LL_I2C_TRIG_POLARITY_RISING 0x00000000U /*!< I2C triggered on rising edge */ +#define LL_I2C_TRIG_POLARITY_FALLING I2C_AUTOCR_TRIGPOL /*!< I2C triggered on falling edge */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup I2C_LL_Exported_Macros I2C Exported Macros + * @{ + */ + +/** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in I2C register + * @param __INSTANCE__ I2C Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in I2C register + * @param __INSTANCE__ I2C Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup I2C_LL_EM_CONVERT_TIMINGS Convert SDA SCL timings + * @{ + */ +/** + * @brief Configure the SDA setup, hold time and the SCL high, low period. + * @param __PRESCALER__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. + * @param __SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. + (tscldel = (SCLDEL+1)xtpresc) + * @param __HOLD_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. + (tsdadel = SDADELxtpresc) + * @param __SCLH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. + (tsclh = (SCLH+1)xtpresc) + * @param __SCLL_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. + (tscll = (SCLL+1)xtpresc) + * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF + */ +#define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __SETUP_TIME__, __HOLD_TIME__, __SCLH_PERIOD__, __SCLL_PERIOD__) \ + ((((uint32_t)(__PRESCALER__) << I2C_TIMINGR_PRESC_Pos) & I2C_TIMINGR_PRESC) | \ + (((uint32_t)(__SETUP_TIME__) << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL) | \ + (((uint32_t)(__HOLD_TIME__) << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL) | \ + (((uint32_t)(__SCLH_PERIOD__) << I2C_TIMINGR_SCLH_Pos) & I2C_TIMINGR_SCLH) | \ + (((uint32_t)(__SCLL_PERIOD__) << I2C_TIMINGR_SCLL_Pos) & I2C_TIMINGR_SCLL)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup I2C_LL_Exported_Functions I2C Exported Functions + * @{ + */ + +/** @defgroup I2C_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Enable I2C peripheral (PE = 1). + * @rmtoll CR1 PE LL_I2C_Enable + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_PE); +} + +/** + * @brief Disable I2C peripheral (PE = 0). + * @note When PE = 0, the I2C SCL and SDA lines are released. + * Internal state machines and status bits are put back to their reset value. + * When cleared, PE must be kept low for at least 3 APB clock cycles. + * @rmtoll CR1 PE LL_I2C_Disable + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE); +} + +/** + * @brief Check if the I2C peripheral is enabled or disabled. + * @rmtoll CR1 PE LL_I2C_IsEnabled + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabled(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE)) ? 1UL : 0UL); +} + +/** + * @brief Configure Noise Filters (Analog and Digital). + * @note If the analog filter is also enabled, the digital filter is added to analog filter. + * The filters can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll CR1 ANFOFF LL_I2C_ConfigFilters\n + * CR1 DNF LL_I2C_ConfigFilters + * @param I2Cx I2C Instance. + * @param AnalogFilter This parameter can be one of the following values: + * @arg @ref LL_I2C_ANALOGFILTER_ENABLE + * @arg @ref LL_I2C_ANALOGFILTER_DISABLE + * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) + and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk). + * This parameter is used to configure the digital noise filter on SDA and SCL input. + * The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter) +{ + MODIFY_REG(I2Cx->CR1, I2C_CR1_ANFOFF | I2C_CR1_DNF, AnalogFilter | (DigitalFilter << I2C_CR1_DNF_Pos)); +} + +/** + * @brief Configure Digital Noise Filter. + * @note If the analog filter is also enabled, the digital filter is added to analog filter. + * This filter can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll CR1 DNF LL_I2C_SetDigitalFilter + * @param I2Cx I2C Instance. + * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) + and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk). + * This parameter is used to configure the digital noise filter on SDA and SCL input. + * The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk. + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter) +{ + MODIFY_REG(I2Cx->CR1, I2C_CR1_DNF, DigitalFilter << I2C_CR1_DNF_Pos); +} + +/** + * @brief Get the current Digital Noise Filter configuration. + * @rmtoll CR1 DNF LL_I2C_GetDigitalFilter + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x0 and Max_Data=0xF + */ +__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(const I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos); +} + +/** + * @brief Enable Analog Noise Filter. + * @note This filter can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll CR1 ANFOFF LL_I2C_EnableAnalogFilter + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableAnalogFilter(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_ANFOFF); +} + +/** + * @brief Disable Analog Noise Filter. + * @note This filter can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll CR1 ANFOFF LL_I2C_DisableAnalogFilter + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_ANFOFF); +} + +/** + * @brief Check if Analog Noise Filter is enabled or disabled. + * @rmtoll CR1 ANFOFF LL_I2C_IsEnabledAnalogFilter + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF)) ? 1UL : 0UL); +} + +/** + * @brief Enable DMA transmission requests. + * @rmtoll CR1 TXDMAEN LL_I2C_EnableDMAReq_TX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN); +} + +/** + * @brief Disable DMA transmission requests. + * @rmtoll CR1 TXDMAEN LL_I2C_DisableDMAReq_TX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN); +} + +/** + * @brief Check if DMA transmission requests are enabled or disabled. + * @rmtoll CR1 TXDMAEN LL_I2C_IsEnabledDMAReq_TX + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable DMA reception requests. + * @rmtoll CR1 RXDMAEN LL_I2C_EnableDMAReq_RX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN); +} + +/** + * @brief Disable DMA reception requests. + * @rmtoll CR1 RXDMAEN LL_I2C_DisableDMAReq_RX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN); +} + +/** + * @brief Check if DMA reception requests are enabled or disabled. + * @rmtoll CR1 RXDMAEN LL_I2C_IsEnabledDMAReq_RX + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN)) ? 1UL : 0UL); +} + +/** + * @brief Get the data register address used for DMA transfer + * @rmtoll TXDR TXDATA LL_I2C_DMA_GetRegAddr\n + * RXDR RXDATA LL_I2C_DMA_GetRegAddr + * @param I2Cx I2C Instance + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_I2C_DMA_REG_DATA_TRANSMIT + * @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE + * @retval Address of data register + */ +__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(const I2C_TypeDef *I2Cx, uint32_t Direction) +{ + uint32_t data_reg_addr; + + if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT) + { + /* return address of TXDR register */ + data_reg_addr = (uint32_t) &(I2Cx->TXDR); + } + else + { + /* return address of RXDR register */ + data_reg_addr = (uint32_t) &(I2Cx->RXDR); + } + + return data_reg_addr; +} + +/** + * @brief Enable Clock stretching. + * @note This bit can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll CR1 NOSTRETCH LL_I2C_EnableClockStretching + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH); +} + +/** + * @brief Disable Clock stretching. + * @note This bit can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll CR1 NOSTRETCH LL_I2C_DisableClockStretching + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH); +} + +/** + * @brief Check if Clock stretching is enabled or disabled. + * @rmtoll CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH)) ? 1UL : 0UL); +} + +/** + * @brief Enable hardware byte control in slave mode. + * @rmtoll CR1 SBC LL_I2C_EnableSlaveByteControl + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableSlaveByteControl(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_SBC); +} + +/** + * @brief Disable hardware byte control in slave mode. + * @rmtoll CR1 SBC LL_I2C_DisableSlaveByteControl + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableSlaveByteControl(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_SBC); +} + +/** + * @brief Check if hardware byte control in slave mode is enabled or disabled. + * @rmtoll CR1 SBC LL_I2C_IsEnabledSlaveByteControl + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC)) ? 1UL : 0UL); +} + +/** + * @brief Enable Wakeup from STOP. + * @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not + * WakeUpFromStop feature is supported by the I2Cx Instance. + * @note This bit can only be programmed when Digital Filter is disabled. + * @rmtoll CR1 WUPEN LL_I2C_EnableWakeUpFromStop + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableWakeUpFromStop(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_WUPEN); +} + +/** + * @brief Disable Wakeup from STOP. + * @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not + * WakeUpFromStop feature is supported by the I2Cx Instance. + * @rmtoll CR1 WUPEN LL_I2C_DisableWakeUpFromStop + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableWakeUpFromStop(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_WUPEN); +} + +/** + * @brief Check if Wakeup from STOP is enabled or disabled. + * @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not + * WakeUpFromStop feature is supported by the I2Cx Instance. + * @rmtoll CR1 WUPEN LL_I2C_IsEnabledWakeUpFromStop + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_WUPEN) == (I2C_CR1_WUPEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable General Call. + * @note When enabled the Address 0x00 is ACKed. + * @rmtoll CR1 GCEN LL_I2C_EnableGeneralCall + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_GCEN); +} + +/** + * @brief Disable General Call. + * @note When disabled the Address 0x00 is NACKed. + * @rmtoll CR1 GCEN LL_I2C_DisableGeneralCall + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_GCEN); +} + +/** + * @brief Check if General Call is enabled or disabled. + * @rmtoll CR1 GCEN LL_I2C_IsEnabledGeneralCall + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable I2C Fast Mode Plus (FMP = 1). + * @note 20mA I/O drive enable + * @rmtoll CR1 FMP LL_I2C_EnableFastModePlus + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableFastModePlus(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_FMP); +} + +/** + * @brief Disable I2C Fast Mode Plus (FMP = 0). + * @note 20mA I/O drive disable + * @rmtoll CR1 FMP LL_I2C_DisableFastModePlus + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableFastModePlus(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_FMP); +} + +/** + * @brief Check if the I2C Fast Mode Plus is enabled or disabled. + * @rmtoll CR1 FMP LL_I2C_IsEnabledFastModePlus + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledFastModePlus(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_FMP) == (I2C_CR1_FMP)) ? 1UL : 0UL); +} + +/** + * @brief Enable automatic clear of ADDR flag. + * @rmtoll CR1 ADDRACLR LL_I2C_EnableAutoClearFlag_ADDR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableAutoClearFlag_ADDR(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_ADDRACLR); +} + +/** + * @brief Disable automatic clear of ADDR flag. + * @rmtoll CR1 ADDRACLR LL_I2C_DisableAutoClearFlag_ADDR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableAutoClearFlag_ADDR(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_ADDRACLR); +} + +/** + * @brief Check if the automatic clear of ADDR flag is enabled or disabled. + * @rmtoll CR1 ADDRACLR LL_I2C_IsEnabledAutoClearFlag_ADDR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoClearFlag_ADDR(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_ADDRACLR) == (I2C_CR1_ADDRACLR)) ? 1UL : 0UL); +} + +/** + * @brief Enable automatic clear of STOP flag. + * @rmtoll CR1 STOPFACLR LL_I2C_EnableAutoClearFlag_STOP + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableAutoClearFlag_STOP(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_STOPFACLR); +} + +/** + * @brief Disable automatic clear of STOP flag. + * @rmtoll CR1 STOPFACLR LL_I2C_DisableAutoClearFlag_STOP + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableAutoClearFlag_STOP(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_STOPFACLR); +} + +/** + * @brief Check if the automatic clear of STOP flag is enabled or disabled. + * @rmtoll CR1 STOPFACLR LL_I2C_IsEnabledAutoClearFlag_STOP + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoClearFlag_STOP(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_STOPFACLR) == (I2C_CR1_STOPFACLR)) ? 1UL : 0UL); +} + +/** + * @brief Configure the Master to operate in 7-bit or 10-bit addressing mode. + * @note Changing this bit is not allowed, when the START bit is set. + * @rmtoll CR2 ADD10 LL_I2C_SetMasterAddressingMode + * @param I2Cx I2C Instance. + * @param AddressingMode This parameter can be one of the following values: + * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT + * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetMasterAddressingMode(I2C_TypeDef *I2Cx, uint32_t AddressingMode) +{ + MODIFY_REG(I2Cx->CR2, I2C_CR2_ADD10, AddressingMode); +} + +/** + * @brief Get the Master addressing mode. + * @rmtoll CR2 ADD10 LL_I2C_GetMasterAddressingMode + * @param I2Cx I2C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT + * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT + */ +__STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(const I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10)); +} + +/** + * @brief Set the Own Address1. + * @rmtoll OAR1 OA1 LL_I2C_SetOwnAddress1\n + * OAR1 OA1MODE LL_I2C_SetOwnAddress1 + * @param I2Cx I2C Instance. + * @param OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF. + * @param OwnAddrSize This parameter can be one of the following values: + * @arg @ref LL_I2C_OWNADDRESS1_7BIT + * @arg @ref LL_I2C_OWNADDRESS1_10BIT + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize) +{ + MODIFY_REG(I2Cx->OAR1, I2C_OAR1_OA1 | I2C_OAR1_OA1MODE, OwnAddress1 | OwnAddrSize); +} + +/** + * @brief Enable acknowledge on Own Address1 match address. + * @rmtoll OAR1 OA1EN LL_I2C_EnableOwnAddress1 + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableOwnAddress1(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN); +} + +/** + * @brief Disable acknowledge on Own Address1 match address. + * @rmtoll OAR1 OA1EN LL_I2C_DisableOwnAddress1 + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN); +} + +/** + * @brief Check if Own Address1 acknowledge is enabled or disabled. + * @rmtoll OAR1 OA1EN LL_I2C_IsEnabledOwnAddress1 + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN)) ? 1UL : 0UL); +} + +/** + * @brief Set the 7bits Own Address2. + * @note This action has no effect if own address2 is enabled. + * @rmtoll OAR2 OA2 LL_I2C_SetOwnAddress2\n + * OAR2 OA2MSK LL_I2C_SetOwnAddress2 + * @param I2Cx I2C Instance. + * @param OwnAddress2 Value between Min_Data=0 and Max_Data=0x7F. + * @param OwnAddrMask This parameter can be one of the following values: + * @arg @ref LL_I2C_OWNADDRESS2_NOMASK + * @arg @ref LL_I2C_OWNADDRESS2_MASK01 + * @arg @ref LL_I2C_OWNADDRESS2_MASK02 + * @arg @ref LL_I2C_OWNADDRESS2_MASK03 + * @arg @ref LL_I2C_OWNADDRESS2_MASK04 + * @arg @ref LL_I2C_OWNADDRESS2_MASK05 + * @arg @ref LL_I2C_OWNADDRESS2_MASK06 + * @arg @ref LL_I2C_OWNADDRESS2_MASK07 + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask) +{ + MODIFY_REG(I2Cx->OAR2, I2C_OAR2_OA2 | I2C_OAR2_OA2MSK, OwnAddress2 | OwnAddrMask); +} + +/** + * @brief Enable acknowledge on Own Address2 match address. + * @rmtoll OAR2 OA2EN LL_I2C_EnableOwnAddress2 + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN); +} + +/** + * @brief Disable acknowledge on Own Address2 match address. + * @rmtoll OAR2 OA2EN LL_I2C_DisableOwnAddress2 + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN); +} + +/** + * @brief Check if Own Address1 acknowledge is enabled or disabled. + * @rmtoll OAR2 OA2EN LL_I2C_IsEnabledOwnAddress2 + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN)) ? 1UL : 0UL); +} + +/** + * @brief Configure the SDA setup, hold time and the SCL high, low period. + * @note This bit can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll TIMINGR TIMINGR LL_I2C_SetTiming + * @param I2Cx I2C Instance. + * @param Timing This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF. + * @note This parameter is computed with the STM32CubeMX Tool. + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing) +{ + WRITE_REG(I2Cx->TIMINGR, Timing); +} + +/** + * @brief Get the Timing Prescaler setting. + * @rmtoll TIMINGR PRESC LL_I2C_GetTimingPrescaler + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x0 and Max_Data=0xF + */ +__STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(const I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos); +} + +/** + * @brief Get the SCL low period setting. + * @rmtoll TIMINGR SCLL LL_I2C_GetClockLowPeriod + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(const I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos); +} + +/** + * @brief Get the SCL high period setting. + * @rmtoll TIMINGR SCLH LL_I2C_GetClockHighPeriod + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(const I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos); +} + +/** + * @brief Get the SDA hold time. + * @rmtoll TIMINGR SDADEL LL_I2C_GetDataHoldTime + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x0 and Max_Data=0xF + */ +__STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(const I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos); +} + +/** + * @brief Get the SDA setup time. + * @rmtoll TIMINGR SCLDEL LL_I2C_GetDataSetupTime + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x0 and Max_Data=0xF + */ +__STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(const I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos); +} + +/** + * @brief Configure peripheral mode. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 SMBHEN LL_I2C_SetMode\n + * CR1 SMBDEN LL_I2C_SetMode + * @param I2Cx I2C Instance. + * @param PeripheralMode This parameter can be one of the following values: + * @arg @ref LL_I2C_MODE_I2C + * @arg @ref LL_I2C_MODE_SMBUS_HOST + * @arg @ref LL_I2C_MODE_SMBUS_DEVICE + * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode) +{ + MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN, PeripheralMode); +} + +/** + * @brief Get peripheral mode. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 SMBHEN LL_I2C_GetMode\n + * CR1 SMBDEN LL_I2C_GetMode + * @param I2Cx I2C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2C_MODE_I2C + * @arg @ref LL_I2C_MODE_SMBUS_HOST + * @arg @ref LL_I2C_MODE_SMBUS_DEVICE + * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP + */ +__STATIC_INLINE uint32_t LL_I2C_GetMode(const I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN)); +} + +/** + * @brief Enable SMBus alert (Host or Device mode) + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note SMBus Device mode: + * - SMBus Alert pin is drived low and + * Alert Response Address Header acknowledge is enabled. + * SMBus Host mode: + * - SMBus Alert pin management is supported. + * @rmtoll CR1 ALERTEN LL_I2C_EnableSMBusAlert + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_ALERTEN); +} + +/** + * @brief Disable SMBus alert (Host or Device mode) + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note SMBus Device mode: + * - SMBus Alert pin is not drived (can be used as a standard GPIO) and + * Alert Response Address Header acknowledge is disabled. + * SMBus Host mode: + * - SMBus Alert pin management is not supported. + * @rmtoll CR1 ALERTEN LL_I2C_DisableSMBusAlert + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERTEN); +} + +/** + * @brief Check if SMBus alert (Host or Device mode) is enabled or disabled. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 ALERTEN LL_I2C_IsEnabledSMBusAlert + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable SMBus Packet Error Calculation (PEC). + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 PECEN LL_I2C_EnableSMBusPEC + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_PECEN); +} + +/** + * @brief Disable SMBus Packet Error Calculation (PEC). + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 PECEN LL_I2C_DisableSMBusPEC + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_PECEN); +} + +/** + * @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 PECEN LL_I2C_IsEnabledSMBusPEC + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN)) ? 1UL : 0UL); +} + +/** + * @brief Configure the SMBus Clock Timeout. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB). + * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_ConfigSMBusTimeout\n + * TIMEOUTR TIDLE LL_I2C_ConfigSMBusTimeout\n + * TIMEOUTR TIMEOUTB LL_I2C_ConfigSMBusTimeout + * @param I2Cx I2C Instance. + * @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF. + * @param TimeoutAMode This parameter can be one of the following values: + * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW + * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH + * @param TimeoutB + * @retval None + */ +__STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode, + uint32_t TimeoutB) +{ + MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA | I2C_TIMEOUTR_TIDLE | I2C_TIMEOUTR_TIMEOUTB, + TimeoutA | TimeoutAMode | (TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos)); +} + +/** + * @brief Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode). + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note These bits can only be programmed when TimeoutA is disabled. + * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_SetSMBusTimeoutA + * @param I2Cx I2C Instance. + * @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF. + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t TimeoutA) +{ + WRITE_REG(I2Cx->TIMEOUTR, TimeoutA); +} + +/** + * @brief Get the SMBus Clock TimeoutA setting. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_GetSMBusTimeoutA + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0 and Max_Data=0xFFF + */ +__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(const I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA)); +} + +/** + * @brief Set the SMBus Clock TimeoutA mode. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note This bit can only be programmed when TimeoutA is disabled. + * @rmtoll TIMEOUTR TIDLE LL_I2C_SetSMBusTimeoutAMode + * @param I2Cx I2C Instance. + * @param TimeoutAMode This parameter can be one of the following values: + * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW + * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t TimeoutAMode) +{ + WRITE_REG(I2Cx->TIMEOUTR, TimeoutAMode); +} + +/** + * @brief Get the SMBus Clock TimeoutA mode. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll TIMEOUTR TIDLE LL_I2C_GetSMBusTimeoutAMode + * @param I2Cx I2C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW + * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH + */ +__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(const I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE)); +} + +/** + * @brief Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode). + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note These bits can only be programmed when TimeoutB is disabled. + * @rmtoll TIMEOUTR TIMEOUTB LL_I2C_SetSMBusTimeoutB + * @param I2Cx I2C Instance. + * @param TimeoutB This parameter must be a value between Min_Data=0 and Max_Data=0xFFF. + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t TimeoutB) +{ + WRITE_REG(I2Cx->TIMEOUTR, TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos); +} + +/** + * @brief Get the SMBus Extended Cumulative Clock TimeoutB setting. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll TIMEOUTR TIMEOUTB LL_I2C_GetSMBusTimeoutB + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0 and Max_Data=0xFFF + */ +__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(const I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos); +} + +/** + * @brief Enable the SMBus Clock Timeout. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_EnableSMBusTimeout\n + * TIMEOUTR TEXTEN LL_I2C_EnableSMBusTimeout + * @param I2Cx I2C Instance. + * @param ClockTimeout This parameter can be one of the following values: + * @arg @ref LL_I2C_SMBUS_TIMEOUTA + * @arg @ref LL_I2C_SMBUS_TIMEOUTB + * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout) +{ + SET_BIT(I2Cx->TIMEOUTR, ClockTimeout); +} + +/** + * @brief Disable the SMBus Clock Timeout. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_DisableSMBusTimeout\n + * TIMEOUTR TEXTEN LL_I2C_DisableSMBusTimeout + * @param I2Cx I2C Instance. + * @param ClockTimeout This parameter can be one of the following values: + * @arg @ref LL_I2C_SMBUS_TIMEOUTA + * @arg @ref LL_I2C_SMBUS_TIMEOUTB + * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout) +{ + CLEAR_BIT(I2Cx->TIMEOUTR, ClockTimeout); +} + +/** + * @brief Check if the SMBus Clock Timeout is enabled or disabled. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_IsEnabledSMBusTimeout\n + * TIMEOUTR TEXTEN LL_I2C_IsEnabledSMBusTimeout + * @param I2Cx I2C Instance. + * @param ClockTimeout This parameter can be one of the following values: + * @arg @ref LL_I2C_SMBUS_TIMEOUTA + * @arg @ref LL_I2C_SMBUS_TIMEOUTB + * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(const I2C_TypeDef *I2Cx, uint32_t ClockTimeout) +{ + return ((READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == \ + (ClockTimeout)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup I2C_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable TXIS interrupt. + * @rmtoll CR1 TXIE LL_I2C_EnableIT_TX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_TXIE); +} + +/** + * @brief Disable TXIS interrupt. + * @rmtoll CR1 TXIE LL_I2C_DisableIT_TX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE); +} + +/** + * @brief Check if the TXIS Interrupt is enabled or disabled. + * @rmtoll CR1 TXIE LL_I2C_IsEnabledIT_TX + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable RXNE interrupt. + * @rmtoll CR1 RXIE LL_I2C_EnableIT_RX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_RXIE); +} + +/** + * @brief Disable RXNE interrupt. + * @rmtoll CR1 RXIE LL_I2C_DisableIT_RX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXIE); +} + +/** + * @brief Check if the RXNE Interrupt is enabled or disabled. + * @rmtoll CR1 RXIE LL_I2C_IsEnabledIT_RX + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable Address match interrupt (slave mode only). + * @rmtoll CR1 ADDRIE LL_I2C_EnableIT_ADDR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_ADDR(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_ADDRIE); +} + +/** + * @brief Disable Address match interrupt (slave mode only). + * @rmtoll CR1 ADDRIE LL_I2C_DisableIT_ADDR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_ADDRIE); +} + +/** + * @brief Check if Address match interrupt is enabled or disabled. + * @rmtoll CR1 ADDRIE LL_I2C_IsEnabledIT_ADDR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable Not acknowledge received interrupt. + * @rmtoll CR1 NACKIE LL_I2C_EnableIT_NACK + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_NACK(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_NACKIE); +} + +/** + * @brief Disable Not acknowledge received interrupt. + * @rmtoll CR1 NACKIE LL_I2C_DisableIT_NACK + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_NACKIE); +} + +/** + * @brief Check if Not acknowledge received interrupt is enabled or disabled. + * @rmtoll CR1 NACKIE LL_I2C_IsEnabledIT_NACK + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable STOP detection interrupt. + * @rmtoll CR1 STOPIE LL_I2C_EnableIT_STOP + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_STOP(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_STOPIE); +} + +/** + * @brief Disable STOP detection interrupt. + * @rmtoll CR1 STOPIE LL_I2C_DisableIT_STOP + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_STOPIE); +} + +/** + * @brief Check if STOP detection interrupt is enabled or disabled. + * @rmtoll CR1 STOPIE LL_I2C_IsEnabledIT_STOP + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable Transfer Complete interrupt. + * @note Any of these events will generate interrupt : + * Transfer Complete (TC) + * Transfer Complete Reload (TCR) + * @rmtoll CR1 TCIE LL_I2C_EnableIT_TC + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_TC(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_TCIE); +} + +/** + * @brief Disable Transfer Complete interrupt. + * @note Any of these events will generate interrupt : + * Transfer Complete (TC) + * Transfer Complete Reload (TCR) + * @rmtoll CR1 TCIE LL_I2C_DisableIT_TC + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_TCIE); +} + +/** + * @brief Check if Transfer Complete interrupt is enabled or disabled. + * @rmtoll CR1 TCIE LL_I2C_IsEnabledIT_TC + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable Error interrupts. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note Any of these errors will generate interrupt : + * Arbitration Loss (ARLO) + * Bus Error detection (BERR) + * Overrun/Underrun (OVR) + * SMBus Timeout detection (TIMEOUT) + * SMBus PEC error detection (PECERR) + * SMBus Alert pin event detection (ALERT) + * @rmtoll CR1 ERRIE LL_I2C_EnableIT_ERR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE); +} + +/** + * @brief Disable Error interrupts. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note Any of these errors will generate interrupt : + * Arbitration Loss (ARLO) + * Bus Error detection (BERR) + * Overrun/Underrun (OVR) + * SMBus Timeout detection (TIMEOUT) + * SMBus PEC error detection (PECERR) + * SMBus Alert pin event detection (ALERT) + * @rmtoll CR1 ERRIE LL_I2C_DisableIT_ERR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE); +} + +/** + * @brief Check if Error interrupts are enabled or disabled. + * @rmtoll CR1 ERRIE LL_I2C_IsEnabledIT_ERR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup I2C_LL_EF_FLAG_management FLAG_management + * @{ + */ + +/** + * @brief Indicate the status of Transmit data register empty flag. + * @note RESET: When next data is written in Transmit data register. + * SET: When Transmit data register is empty. + * @rmtoll ISR TXE LL_I2C_IsActiveFlag_TXE + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Transmit interrupt flag. + * @note RESET: When next data is written in Transmit data register. + * SET: When Transmit data register is empty. + * @rmtoll ISR TXIS LL_I2C_IsActiveFlag_TXIS + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Receive data register not empty flag. + * @note RESET: When Receive data register is read. + * SET: When the received data is copied in Receive data register. + * @rmtoll ISR RXNE LL_I2C_IsActiveFlag_RXNE + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Address matched flag (slave mode). + * @note RESET: Clear default value. + * SET: When the received slave address matched with one of the enabled slave address. + * @rmtoll ISR ADDR LL_I2C_IsActiveFlag_ADDR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Not Acknowledge received flag. + * @note RESET: Clear default value. + * SET: When a NACK is received after a byte transmission. + * @rmtoll ISR NACKF LL_I2C_IsActiveFlag_NACK + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Stop detection flag. + * @note RESET: Clear default value. + * SET: When a Stop condition is detected. + * @rmtoll ISR STOPF LL_I2C_IsActiveFlag_STOP + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Transfer complete flag (master mode). + * @note RESET: Clear default value. + * SET: When RELOAD=0, AUTOEND=0 and NBYTES date have been transferred. + * @rmtoll ISR TC LL_I2C_IsActiveFlag_TC + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Transfer complete flag (master mode). + * @note RESET: Clear default value. + * SET: When RELOAD=1 and NBYTES date have been transferred. + * @rmtoll ISR TCR LL_I2C_IsActiveFlag_TCR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Bus error flag. + * @note RESET: Clear default value. + * SET: When a misplaced Start or Stop condition is detected. + * @rmtoll ISR BERR LL_I2C_IsActiveFlag_BERR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Arbitration lost flag. + * @note RESET: Clear default value. + * SET: When arbitration lost. + * @rmtoll ISR ARLO LL_I2C_IsActiveFlag_ARLO + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Overrun/Underrun flag (slave mode). + * @note RESET: Clear default value. + * SET: When an overrun/underrun error occurs (Clock Stretching Disabled). + * @rmtoll ISR OVR LL_I2C_IsActiveFlag_OVR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of SMBus PEC error flag in reception. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note RESET: Clear default value. + * SET: When the received PEC does not match with the PEC register content. + * @rmtoll ISR PECERR LL_I2C_IsActiveSMBusFlag_PECERR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of SMBus Timeout detection flag. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note RESET: Clear default value. + * SET: When a timeout or extended clock timeout occurs. + * @rmtoll ISR TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of SMBus alert flag. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note RESET: Clear default value. + * SET: When SMBus host configuration, SMBus alert enabled and + * a falling edge event occurs on SMBA pin. + * @rmtoll ISR ALERT LL_I2C_IsActiveSMBusFlag_ALERT + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Bus Busy flag. + * @note RESET: Clear default value. + * SET: When a Start condition is detected. + * @rmtoll ISR BUSY LL_I2C_IsActiveFlag_BUSY + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY)) ? 1UL : 0UL); +} + +/** + * @brief Clear Address Matched flag. + * @rmtoll ICR ADDRCF LL_I2C_ClearFlag_ADDR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_ADDRCF); +} + +/** + * @brief Clear Not Acknowledge flag. + * @rmtoll ICR NACKCF LL_I2C_ClearFlag_NACK + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_NACK(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_NACKCF); +} + +/** + * @brief Clear Stop detection flag. + * @rmtoll ICR STOPCF LL_I2C_ClearFlag_STOP + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_STOPCF); +} + +/** + * @brief Clear Transmit data register empty flag (TXE). + * @note This bit can be clear by software in order to flush the transmit data register (TXDR). + * @rmtoll ISR TXE LL_I2C_ClearFlag_TXE + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_TXE(I2C_TypeDef *I2Cx) +{ + WRITE_REG(I2Cx->ISR, I2C_ISR_TXE); +} + +/** + * @brief Clear Bus error flag. + * @rmtoll ICR BERRCF LL_I2C_ClearFlag_BERR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_BERRCF); +} + +/** + * @brief Clear Arbitration lost flag. + * @rmtoll ICR ARLOCF LL_I2C_ClearFlag_ARLO + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_ARLOCF); +} + +/** + * @brief Clear Overrun/Underrun flag. + * @rmtoll ICR OVRCF LL_I2C_ClearFlag_OVR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_OVRCF); +} + +/** + * @brief Clear SMBus PEC error flag. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll ICR PECCF LL_I2C_ClearSMBusFlag_PECERR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_PECCF); +} + +/** + * @brief Clear SMBus Timeout detection flag. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll ICR TIMOUTCF LL_I2C_ClearSMBusFlag_TIMEOUT + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_TIMOUTCF); +} + +/** + * @brief Clear SMBus Alert flag. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll ICR ALERTCF LL_I2C_ClearSMBusFlag_ALERT + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_ALERTCF); +} + +/** + * @} + */ + +/** @defgroup I2C_LL_EF_Data_Management Data_Management + * @{ + */ + +/** + * @brief Enable automatic STOP condition generation (master mode). + * @note Automatic end mode : a STOP condition is automatically sent when NBYTES data are transferred. + * This bit has no effect in slave mode or when RELOAD bit is set. + * @rmtoll CR2 AUTOEND LL_I2C_EnableAutoEndMode + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableAutoEndMode(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_AUTOEND); +} + +/** + * @brief Disable automatic STOP condition generation (master mode). + * @note Software end mode : TC flag is set when NBYTES data are transferre, stretching SCL low. + * @rmtoll CR2 AUTOEND LL_I2C_DisableAutoEndMode + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR2, I2C_CR2_AUTOEND); +} + +/** + * @brief Check if automatic STOP condition is enabled or disabled. + * @rmtoll CR2 AUTOEND LL_I2C_IsEnabledAutoEndMode + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND)) ? 1UL : 0UL); +} + +/** + * @brief Enable reload mode (master mode). + * @note The transfer is not completed after the NBYTES data transfer, NBYTES will be reloaded when TCR flag is set. + * @rmtoll CR2 RELOAD LL_I2C_EnableReloadMode + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableReloadMode(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_RELOAD); +} + +/** + * @brief Disable reload mode (master mode). + * @note The transfer is completed after the NBYTES data transfer(STOP or RESTART will follow). + * @rmtoll CR2 RELOAD LL_I2C_DisableReloadMode + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR2, I2C_CR2_RELOAD); +} + +/** + * @brief Check if reload mode is enabled or disabled. + * @rmtoll CR2 RELOAD LL_I2C_IsEnabledReloadMode + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD)) ? 1UL : 0UL); +} + +/** + * @brief Configure the number of bytes for transfer. + * @note Changing these bits when START bit is set is not allowed. + * @rmtoll CR2 NBYTES LL_I2C_SetTransferSize + * @param I2Cx I2C Instance. + * @param TransferSize This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF. + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t TransferSize) +{ + MODIFY_REG(I2Cx->CR2, I2C_CR2_NBYTES, TransferSize << I2C_CR2_NBYTES_Pos); +} + +/** + * @brief Get the number of bytes configured for transfer. + * @rmtoll CR2 NBYTES LL_I2C_GetTransferSize + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x0 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_I2C_GetTransferSize(const I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos); +} + +/** + * @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code + or next received byte. + * @note Usage in Slave mode only. + * @rmtoll CR2 NACK LL_I2C_AcknowledgeNextData + * @param I2Cx I2C Instance. + * @param TypeAcknowledge This parameter can be one of the following values: + * @arg @ref LL_I2C_ACK + * @arg @ref LL_I2C_NACK + * @retval None + */ +__STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge) +{ + MODIFY_REG(I2Cx->CR2, I2C_CR2_NACK, TypeAcknowledge); +} + +/** + * @brief Generate a START or RESTART condition + * @note The START bit can be set even if bus is BUSY or I2C is in slave mode. + * This action has no effect when RELOAD is set. + * @rmtoll CR2 START LL_I2C_GenerateStartCondition + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_START); +} + +/** + * @brief Generate a STOP condition after the current byte transfer (master mode). + * @rmtoll CR2 STOP LL_I2C_GenerateStopCondition + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_STOP); +} + +/** + * @brief Enable automatic RESTART Read request condition for 10bit address header (master mode). + * @note The master sends the complete 10bit slave address read sequence : + * Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address + in Read direction. + * @rmtoll CR2 HEAD10R LL_I2C_EnableAuto10BitRead + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableAuto10BitRead(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR2, I2C_CR2_HEAD10R); +} + +/** + * @brief Disable automatic RESTART Read request condition for 10bit address header (master mode). + * @note The master only sends the first 7 bits of 10bit address in Read direction. + * @rmtoll CR2 HEAD10R LL_I2C_DisableAuto10BitRead + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableAuto10BitRead(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_HEAD10R); +} + +/** + * @brief Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled. + * @rmtoll CR2 HEAD10R LL_I2C_IsEnabledAuto10BitRead + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R)) ? 1UL : 0UL); +} + +/** + * @brief Configure the transfer direction (master mode). + * @note Changing these bits when START bit is set is not allowed. + * @rmtoll CR2 RD_WRN LL_I2C_SetTransferRequest + * @param I2Cx I2C Instance. + * @param TransferRequest This parameter can be one of the following values: + * @arg @ref LL_I2C_REQUEST_WRITE + * @arg @ref LL_I2C_REQUEST_READ + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetTransferRequest(I2C_TypeDef *I2Cx, uint32_t TransferRequest) +{ + MODIFY_REG(I2Cx->CR2, I2C_CR2_RD_WRN, TransferRequest); +} + +/** + * @brief Get the transfer direction requested (master mode). + * @rmtoll CR2 RD_WRN LL_I2C_GetTransferRequest + * @param I2Cx I2C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2C_REQUEST_WRITE + * @arg @ref LL_I2C_REQUEST_READ + */ +__STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(const I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_RD_WRN)); +} + +/** + * @brief Configure the slave address for transfer (master mode). + * @note Changing these bits when START bit is set is not allowed. + * @rmtoll CR2 SADD LL_I2C_SetSlaveAddr + * @param I2Cx I2C Instance. + * @param SlaveAddr This parameter must be a value between Min_Data=0x00 and Max_Data=0x3F. + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetSlaveAddr(I2C_TypeDef *I2Cx, uint32_t SlaveAddr) +{ + MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD, SlaveAddr); +} + +/** + * @brief Get the slave address programmed for transfer. + * @rmtoll CR2 SADD LL_I2C_GetSlaveAddr + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x0 and Max_Data=0x3F + */ +__STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(const I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_SADD)); +} + +/** + * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set). + * @rmtoll CR2 SADD LL_I2C_HandleTransfer\n + * CR2 ADD10 LL_I2C_HandleTransfer\n + * CR2 RD_WRN LL_I2C_HandleTransfer\n + * CR2 START LL_I2C_HandleTransfer\n + * CR2 STOP LL_I2C_HandleTransfer\n + * CR2 RELOAD LL_I2C_HandleTransfer\n + * CR2 NBYTES LL_I2C_HandleTransfer\n + * CR2 AUTOEND LL_I2C_HandleTransfer\n + * CR2 HEAD10R LL_I2C_HandleTransfer + * @param I2Cx I2C Instance. + * @param SlaveAddr Specifies the slave address to be programmed. + * @param SlaveAddrSize This parameter can be one of the following values: + * @arg @ref LL_I2C_ADDRSLAVE_7BIT + * @arg @ref LL_I2C_ADDRSLAVE_10BIT + * @param TransferSize Specifies the number of bytes to be programmed. + * This parameter must be a value between Min_Data=0 and Max_Data=255. + * @param EndMode This parameter can be one of the following values: + * @arg @ref LL_I2C_MODE_RELOAD + * @arg @ref LL_I2C_MODE_AUTOEND + * @arg @ref LL_I2C_MODE_SOFTEND + * @arg @ref LL_I2C_MODE_SMBUS_RELOAD + * @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC + * @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC + * @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC + * @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC + * @param Request This parameter can be one of the following values: + * @arg @ref LL_I2C_GENERATE_NOSTARTSTOP + * @arg @ref LL_I2C_GENERATE_STOP + * @arg @ref LL_I2C_GENERATE_START_READ + * @arg @ref LL_I2C_GENERATE_START_WRITE + * @arg @ref LL_I2C_GENERATE_RESTART_7BIT_READ + * @arg @ref LL_I2C_GENERATE_RESTART_7BIT_WRITE + * @arg @ref LL_I2C_GENERATE_RESTART_10BIT_READ + * @arg @ref LL_I2C_GENERATE_RESTART_10BIT_WRITE + * @retval None + */ +__STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize, + uint32_t TransferSize, uint32_t EndMode, uint32_t Request) +{ + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + uint32_t tmp = ((uint32_t)(((uint32_t)SlaveAddr & I2C_CR2_SADD) | \ + ((uint32_t)SlaveAddrSize & I2C_CR2_ADD10) | \ + (((uint32_t)TransferSize << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ + (uint32_t)EndMode | (uint32_t)Request) & (~0x80000000U)); + + /* update CR2 register */ + MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | + (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | + I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD | + I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R, + tmp); +} + +/** + * @brief Indicate the value of transfer direction (slave mode). + * @note RESET: Write transfer, Slave enters in receiver mode. + * SET: Read transfer, Slave enters in transmitter mode. + * @rmtoll ISR DIR LL_I2C_GetTransferDirection + * @param I2Cx I2C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2C_DIRECTION_WRITE + * @arg @ref LL_I2C_DIRECTION_READ + */ +__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(const I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_DIR)); +} + +/** + * @brief Return the slave matched address. + * @rmtoll ISR ADDCODE LL_I2C_GetAddressMatchCode + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x00 and Max_Data=0x3F + */ +__STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(const I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos << 1); +} + +/** + * @brief Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode). + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition + or an Address Matched is received. + * This bit has no effect when RELOAD bit is set. + * This bit has no effect in device mode when SBC bit is not set. + * @rmtoll CR2 PECBYTE LL_I2C_EnableSMBusPECCompare + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_PECBYTE); +} + +/** + * @brief Check if the SMBus Packet Error byte internal comparison is requested or not. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR2 PECBYTE LL_I2C_IsEnabledSMBusPECCompare + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE)) ? 1UL : 0UL); +} + +/** + * @brief Get the SMBus Packet Error byte calculated. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll PECR PEC LL_I2C_GetSMBusPEC + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(const I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC)); +} + +/** + * @brief Read Receive Data register. + * @rmtoll RXDR RXDATA LL_I2C_ReceiveData8 + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(const I2C_TypeDef *I2Cx) +{ + return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA)); +} + +/** + * @brief Write in Transmit Data Register . + * @rmtoll TXDR TXDATA LL_I2C_TransmitData8 + * @param I2Cx I2C Instance. + * @param Data Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data) +{ + WRITE_REG(I2Cx->TXDR, Data); +} + +/** + * @} + */ + +/** @defgroup I2C_LL_EF_AutonomousMode Configuration functions related to Autonomous mode feature + * @{ + */ + +/** + * @brief Enable Selected Trigger + * @rmtoll AUTOCR TRIGEN LL_I2C_Enable_SelectedTrigger + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_Enable_SelectedTrigger(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->AUTOCR, I2C_AUTOCR_TRIGEN); +} + +/** + * @brief Disable Selected Trigger + * @rmtoll AUTOCR TRIGEN LL_I2C_Disable_SelectedTrigger + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_Disable_SelectedTrigger(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->AUTOCR, I2C_AUTOCR_TRIGEN); +} + +/** + * @brief Indicate if selected Trigger is disabled or enabled + * @rmtoll AUTOCR TRIGEN LL_I2C_IsEnabled_SelectedTrigger + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabled_SelectedTrigger(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->AUTOCR, I2C_AUTOCR_TRIGEN) == (I2C_AUTOCR_TRIGEN)) ? 1UL : 0UL); +} + +/** + * @brief Set the trigger polarity + * @rmtoll AUTOCR TRIGPOL LL_I2C_SetTriggerPolarity + * @param I2Cx I2C Instance. + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_I2C_TRIG_POLARITY_RISING + * @arg @ref LL_I2C_TRIG_POLARITY_FALLING + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetTriggerPolarity(I2C_TypeDef *I2Cx, uint32_t Polarity) +{ + MODIFY_REG(I2Cx->AUTOCR, I2C_AUTOCR_TRIGPOL, Polarity); +} + +/** + * @brief Get the trigger polarity + * @rmtoll AUTOCR TRIGPOL LL_I2C_GetTriggerPolarity + * @param I2Cx I2C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2C_TRIG_POLARITY_RISING + * @arg @ref LL_I2C_TRIG_POLARITY_FALLING + */ +__STATIC_INLINE uint32_t LL_I2C_GetTriggerPolarity(const I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->AUTOCR, I2C_AUTOCR_TRIGPOL)); +} + +/** + * @brief Set the selected trigger + * @rmtoll AUTOCR TRIGSEL LL_I2C_SetSelectedTrigger + * @param I2Cx I2C Instance. + * @param Trigger This parameter can be one of the following values: + * @arg @ref LL_I2C_GRP1_GPDMA_CH0_TCF_TRG + * @arg @ref LL_I2C_GRP1_GPDMA_CH1_TCF_TRG + * @arg @ref LL_I2C_GRP1_GPDMA_CH2_TCF_TRG + * @arg @ref LL_I2C_GRP1_GPDMA_CH3_TCF_TRG + * @arg @ref LL_I2C_GRP1_EXTI5_TRG + * @arg @ref LL_I2C_GRP1_EXTI9_TRG + * @arg @ref LL_I2C_GRP1_LPTIM1_CH1_TRG + * @arg @ref LL_I2C_GRP1_LPTIM2_CH1_TRG + * @arg @ref LL_I2C_GRP1_COMP1_TRG + * @arg @ref LL_I2C_GRP1_COMP2_TRG + * @arg @ref LL_I2C_GRP1_RTC_ALRA_TRG + * @arg @ref LL_I2C_GRP1_RTC_WUT_TRG + * @arg @ref LL_I2C_GRP2_GPDMA_CH0_TCF_TRG + * @arg @ref LL_I2C_GRP2_GPDMA_CH1_TCF_TRG + * @arg @ref LL_I2C_GRP2_GPDMA_CH2_TCF_TRG + * @arg @ref LL_I2C_GRP2_GPDMA_CH3_TCF_TRG + * @arg @ref LL_I2C_GRP2_EXTI5_TRG + * @arg @ref LL_I2C_GRP2_EXTI8_TRG + * @arg @ref LL_I2C_GRP2_LPTIM1_CH1_TRG + * @arg @ref LL_I2C_GRP2_COMP1_TRG + * @arg @ref LL_I2C_GRP2_COMP2_TRG + * @arg @ref LL_I2C_GRP2_RTC_ALRA_TRG + * @arg @ref LL_I2C_GRP2_RTC_WUT_TRG + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetSelectedTrigger(I2C_TypeDef *I2Cx, uint32_t Trigger) +{ + MODIFY_REG(I2Cx->AUTOCR, I2C_AUTOCR_TRIGSEL, (Trigger & I2C_AUTOCR_TRIGSEL_Msk)); +} + +/** + * @brief Get the selected trigger + * @rmtoll AUTOCR TRIGSEL LL_I2C_GetSelectedTrigger + * @param I2Cx I2C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2C_GRP1_GPDMA_CH0_TCF_TRG + * @arg @ref LL_I2C_GRP1_GPDMA_CH1_TCF_TRG + * @arg @ref LL_I2C_GRP1_GPDMA_CH2_TCF_TRG + * @arg @ref LL_I2C_GRP1_GPDMA_CH3_TCF_TRG + * @arg @ref LL_I2C_GRP1_EXTI5_TRG + * @arg @ref LL_I2C_GRP1_EXTI9_TRG + * @arg @ref LL_I2C_GRP1_LPTIM1_CH1_TRG + * @arg @ref LL_I2C_GRP1_LPTIM2_CH1_TRG + * @arg @ref LL_I2C_GRP1_COMP1_TRG + * @arg @ref LL_I2C_GRP1_COMP2_TRG + * @arg @ref LL_I2C_GRP1_RTC_ALRA_TRG + * @arg @ref LL_I2C_GRP1_RTC_WUT_TRG + * @arg @ref LL_I2C_GRP2_GPDMA_CH0_TCF_TRG + * @arg @ref LL_I2C_GRP2_GPDMA_CH1_TCF_TRG + * @arg @ref LL_I2C_GRP2_GPDMA_CH2_TCF_TRG + * @arg @ref LL_I2C_GRP2_GPDMA_CH3_TCF_TRG + * @arg @ref LL_I2C_GRP2_EXTI5_TRG + * @arg @ref LL_I2C_GRP2_EXTI8_TRG + * @arg @ref LL_I2C_GRP2_LPTIM1_CH1_TRG + * @arg @ref LL_I2C_GRP2_COMP1_TRG + * @arg @ref LL_I2C_GRP2_COMP2_TRG + * @arg @ref LL_I2C_GRP2_RTC_ALRA_TRG + * @arg @ref LL_I2C_GRP2_RTC_WUT_TRG + */ +__STATIC_INLINE uint32_t LL_I2C_GetSelectedTrigger(const I2C_TypeDef *I2Cx) +{ +#if defined(LL_I2C_TRIG_GRP1) + if (IS_LL_I2C_GRP2_INSTANCE(I2Cx)) + { + return (uint32_t)((READ_BIT(I2Cx->AUTOCR, I2C_AUTOCR_TRIGSEL) | LL_I2C_TRIG_GRP2)); + } + else + { + return (uint32_t)((READ_BIT(I2Cx->AUTOCR, I2C_AUTOCR_TRIGSEL) | LL_I2C_TRIG_GRP1)); + } +#else + return (uint32_t)((READ_BIT(I2Cx->AUTOCR, I2C_AUTOCR_TRIGSEL) | LL_I2C_TRIG_GRP2)); +#endif /* LL_I2C_TRIG_GRP1 */ +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, const LL_I2C_InitTypeDef *I2C_InitStruct); +ErrorStatus LL_I2C_DeInit(const I2C_TypeDef *I2Cx); +void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct); + + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* I2C1 || I2C3 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WBAxx_LL_I2C_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_icache.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_icache.h new file mode 100644 index 0000000000..1083c3d4d7 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_icache.h @@ -0,0 +1,782 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_ll_icache.h + * @author MCD Application Team + * @brief Header file of ICACHE LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion ------------------------------------*/ +#ifndef STM32WBAxx_LL_ICACHE_H +#define STM32WBAxx_LL_ICACHE_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes -----------------------------------------------------------------*/ +#include "stm32wbaxx.h" + +/** @addtogroup STM32WBAxx_LL_Driver + * @{ + */ + +#if defined(ICACHE) + +/** @defgroup ICACHE_LL ICACHE + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/** @defgroup ICACHE_LL_REGION_CONFIG ICACHE Exported Configuration structure + * @{ + */ + +/** + * @brief LL ICACHE region configuration structure definition + */ +typedef struct +{ + uint32_t BaseAddress; /*!< Configures the C-AHB base address to be remapped */ + + uint32_t RemapAddress; /*!< Configures the remap address to be remapped */ + + uint32_t Size; /*!< Configures the region size. + This parameter can be a value of @ref ICACHE_LL_EC_Region_Size */ + + uint32_t TrafficRoute; /*!< Selects the traffic route. + This parameter can be a value of @ref ICACHE_LL_EC_Traffic_Route */ + + uint32_t OutputBurstType; /*!< Selects the output burst type. + This parameter can be a value of @ref ICACHE_LL_EC_Output_Burst_Type */ +} LL_ICACHE_RegionTypeDef; + +/** + * @} + */ + +/* Exported constants -------------------------------------------------------*/ +/** @defgroup ICACHE_LL_Exported_Constants ICACHE Exported Constants + * @{ + */ + +/** @defgroup ICACHE_LL_EC_WaysSelection Ways selection + * @{ + */ +#define LL_ICACHE_1WAY 0U /*!< 1-way cache (direct mapped cache) */ +#define LL_ICACHE_2WAYS ICACHE_CR_WAYSEL /*!< 2-ways set associative cache (default) */ +/** + * @} + */ + +/** @defgroup ICACHE_LL_EC_Monitor_Type Monitor type + * @{ + */ +#define LL_ICACHE_MONITOR_HIT ICACHE_CR_HITMEN /*!< Hit monitor counter */ +#define LL_ICACHE_MONITOR_MISS ICACHE_CR_MISSMEN /*!< Miss monitor counter */ +#define LL_ICACHE_MONITOR_ALL (ICACHE_CR_HITMEN | ICACHE_CR_MISSMEN) /*!< All monitors counters */ +/** + * @} + */ + +/** @defgroup ICACHE_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_ICACHE_ReadReg function + * @{ + */ +#define LL_ICACHE_SR_BUSYF ICACHE_SR_BUSYF /*!< Busy flag */ +#define LL_ICACHE_SR_BSYENDF ICACHE_SR_BSYENDF /*!< Busy end flag */ +#define LL_ICACHE_SR_ERRF ICACHE_SR_ERRF /*!< Cache error flag */ +/** + * @} + */ + +/** @defgroup ICACHE_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_ICACHE_WriteReg function + * @{ + */ +#define LL_ICACHE_FCR_CBSYENDF ICACHE_FCR_CBSYENDF /*!< Busy end flag */ +#define LL_ICACHE_FCR_CERRF ICACHE_FCR_CERRF /*!< Cache error flag */ +/** + * @} + */ + +/** @defgroup ICACHE_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_ICACHE_ReadReg and LL_ICACHE_WriteReg functions + * @{ + */ +#define LL_ICACHE_IER_BSYENDIE ICACHE_IER_BSYENDIE /*!< Busy end interrupt */ +#define LL_ICACHE_IER_ERRIE ICACHE_IER_ERRIE /*!< Cache error interrupt */ +/** + * @} + */ + +/** @defgroup ICACHE_LL_EC_Region Remapped Region number + * @{ + */ +#define LL_ICACHE_REGION_0 0U /*!< Region 0 */ +#define LL_ICACHE_REGION_1 1U /*!< Region 1 */ +#define LL_ICACHE_REGION_2 2U /*!< Region 2 */ +#define LL_ICACHE_REGION_3 3U /*!< Region 3 */ +/** + * @} + */ + +/** @defgroup ICACHE_LL_EC_Region_Size Remapped Region size + * @{ + */ +#define LL_ICACHE_REGIONSIZE_2MB 1U /*!< Region size 2MB */ +#define LL_ICACHE_REGIONSIZE_4MB 2U /*!< Region size 4MB */ +#define LL_ICACHE_REGIONSIZE_8MB 3U /*!< Region size 8MB */ +#define LL_ICACHE_REGIONSIZE_16MB 4U /*!< Region size 16MB */ +#define LL_ICACHE_REGIONSIZE_32MB 5U /*!< Region size 32MB */ +#define LL_ICACHE_REGIONSIZE_64MB 6U /*!< Region size 64MB */ +#define LL_ICACHE_REGIONSIZE_128MB 7U /*!< Region size 128MB */ +/** + * @} + */ + +/** @defgroup ICACHE_LL_EC_Traffic_Route Remapped Traffic route + * @{ + */ +#define LL_ICACHE_MASTER1_PORT 0U /*!< Master1 port */ +#define LL_ICACHE_MASTER2_PORT ICACHE_CRRx_MSTSEL /*!< Master2 port */ +/** + * @} + */ + +/** @defgroup ICACHE_LL_EC_Output_Burst_Type Remapped Output burst type + * @{ + */ +#define LL_ICACHE_OUTPUT_BURST_WRAP 0U /*!< WRAP */ +#define LL_ICACHE_OUTPUT_BURST_INCR ICACHE_CRRx_HBURST /*!< INCR */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros ----------------------------------------------------------*/ +/** @defgroup ICACHE_LL_Exported_Macros ICACHE Exported Macros + * @{ + */ + +/** @defgroup ICACHE_LL_EM_WRITE_READ Common write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in ICACHE register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_ICACHE_WriteReg(__REG__, __VALUE__) WRITE_REG(ICACHE->__REG__, (__VALUE__)) + +/** + * @brief Read a value in ICACHE register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_ICACHE_ReadReg(__REG__) READ_REG(ICACHE->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup ICACHE_LL_Exported_Functions ICACHE Exported Functions + * @{ + */ + +/** @defgroup ICACHE_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Enable the ICACHE. + * @rmtoll CR EN LL_ICACHE_Enable + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_Enable(void) +{ + SET_BIT(ICACHE->CR, ICACHE_CR_EN); +} + +/** + * @brief Disable the ICACHE. + * @rmtoll CR EN LL_ICACHE_Disable + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_Disable(void) +{ + CLEAR_BIT(ICACHE->CR, ICACHE_CR_EN); +} + +/** + * @brief Return if ICACHE is enabled or not. + * @rmtoll CR EN LL_ICACHE_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ICACHE_IsEnabled(void) +{ + return ((READ_BIT(ICACHE->CR, ICACHE_CR_EN) == (ICACHE_CR_EN)) ? 1UL : 0UL); +} + +/** + * @brief Select the ICACHE operating mode. + * @rmtoll CR WAYSEL LL_ICACHE_SetMode + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_ICACHE_1WAY + * @arg @ref LL_ICACHE_2WAYS + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_SetMode(uint32_t Mode) +{ + MODIFY_REG(ICACHE->CR, ICACHE_CR_WAYSEL, Mode); +} + +/** + * @brief Get the selected ICACHE operating mode. + * @rmtoll CR WAYSEL LL_ICACHE_GetMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_ICACHE_1WAY + * @arg @ref LL_ICACHE_2WAYS + */ +__STATIC_INLINE uint32_t LL_ICACHE_GetMode(void) +{ + return (READ_BIT(ICACHE->CR, ICACHE_CR_WAYSEL)); +} + +/** + * @brief Invalidate the ICACHE. + * @note Until the BSYEND flag is set, the cache is bypassed. + * @rmtoll CR CACHEINV LL_ICACHE_Invalidate + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_Invalidate(void) +{ + SET_BIT(ICACHE->CR, ICACHE_CR_CACHEINV); +} + +/** + * @} + */ + +/** @defgroup ICACHE_LL_EF_Monitors Monitors + * @{ + */ + +/** + * @brief Enable the hit/miss monitor(s). + * @rmtoll CR HITMEN LL_ICACHE_EnableMonitors + * @rmtoll CR MISSMEN LL_ICACHE_EnableMonitors + * @param Monitors This parameter can be one or a combination of the following values: + * @arg @ref LL_ICACHE_MONITOR_HIT + * @arg @ref LL_ICACHE_MONITOR_MISS + * @arg @ref LL_ICACHE_MONITOR_ALL + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_EnableMonitors(uint32_t Monitors) +{ + SET_BIT(ICACHE->CR, Monitors); +} + +/** + * @brief Disable the hit/miss monitor(s). + * @rmtoll CR HITMEN LL_ICACHE_DisableMonitors + * @rmtoll CR MISSMEN LL_ICACHE_DisableMonitors + * @param Monitors This parameter can be one or a combination of the following values: + * @arg @ref LL_ICACHE_MONITOR_HIT + * @arg @ref LL_ICACHE_MONITOR_MISS + * @arg @ref LL_ICACHE_MONITOR_ALL + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_DisableMonitors(uint32_t Monitors) +{ + CLEAR_BIT(ICACHE->CR, Monitors); +} + +/** + * @brief Check if the monitor(s) is(are) enabled or disabled. + * @rmtoll CR HITMEN LL_ICACHE_IsEnabledMonitors + * @rmtoll CR MISSMEN LL_ICACHE_IsEnabledMonitors + * @param Monitors This parameter can be one or a combination of the following values: + * @arg @ref LL_ICACHE_MONITOR_HIT + * @arg @ref LL_ICACHE_MONITOR_MISS + * @arg @ref LL_ICACHE_MONITOR_ALL + * @retval State of parameter value (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ICACHE_IsEnabledMonitors(uint32_t Monitors) +{ + return ((READ_BIT(ICACHE->CR, Monitors) == (Monitors)) ? 1UL : 0UL); +} + +/** + * @brief Reset the hit/miss monitor(s). + * @rmtoll CR HITMRST LL_ICACHE_ResetMonitors + * @rmtoll CR MISSMRST LL_ICACHE_ResetMonitors + * @param Monitors This parameter can be one or a combination of the following values: + * @arg @ref LL_ICACHE_MONITOR_HIT + * @arg @ref LL_ICACHE_MONITOR_MISS + * @arg @ref LL_ICACHE_MONITOR_ALL + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_ResetMonitors(uint32_t Monitors) +{ + /* Reset */ + SET_BIT(ICACHE->CR, (Monitors << 2U)); + /* Release reset */ + CLEAR_BIT(ICACHE->CR, (Monitors << 2U)); +} + +/** + * @brief Get the Hit monitor. + * @note Upon reaching the 32-bit maximum value, hit monitor does not wrap. + * @rmtoll HMONR HITMON LL_ICACHE_GetHitMonitor + * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_ICACHE_GetHitMonitor(void) +{ + return (ICACHE->HMONR); +} + +/** + * @brief Get the Miss monitor. + * @note Upon reaching the 16-bit maximum value, miss monitor does not wrap. + * @rmtoll MMONR MISSMON LL_ICACHE_GetMissMonitor + * @retval Value between Min_Data=0 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint32_t LL_ICACHE_GetMissMonitor(void) +{ + return (ICACHE->MMONR); +} + +/** + * @} + */ + +/** @defgroup ICACHE_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable BSYEND interrupt. + * @rmtoll IER BSYENDIE LL_ICACHE_EnableIT_BSYEND + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_EnableIT_BSYEND(void) +{ + SET_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE); +} + +/** + * @brief Disable BSYEND interrupt. + * @rmtoll IER BSYENDIE LL_ICACHE_DisableIT_BSYEND + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_DisableIT_BSYEND(void) +{ + CLEAR_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE); +} + +/** + * @brief Check if the BSYEND Interrupt is enabled or disabled. + * @rmtoll IER BSYENDIE LL_ICACHE_IsEnabledIT_BSYEND + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ICACHE_IsEnabledIT_BSYEND(void) +{ + return ((READ_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE) == (ICACHE_IER_BSYENDIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable ERR interrupt. + * @rmtoll IER ERRIE LL_ICACHE_EnableIT_ERR + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_EnableIT_ERR(void) +{ + SET_BIT(ICACHE->IER, ICACHE_IER_ERRIE); +} + +/** + * @brief Disable ERR interrupt. + * @rmtoll IER ERRIE LL_ICACHE_DisableIT_ERR + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_DisableIT_ERR(void) +{ + CLEAR_BIT(ICACHE->IER, ICACHE_IER_ERRIE); +} + +/** + * @brief Check if the ERR Interrupt is enabled or disabled. + * @rmtoll IER ERRIE LL_ICACHE_IsEnabledIT_ERR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ICACHE_IsEnabledIT_ERR(void) +{ + return ((READ_BIT(ICACHE->IER, ICACHE_IER_ERRIE) == (ICACHE_IER_ERRIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup ICACHE_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Indicate the status of an ongoing operation flag. + * @rmtoll SR BUSYF LL_ICACHE_IsActiveFlag_BUSY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ICACHE_IsActiveFlag_BUSY(void) +{ + return ((READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) == (ICACHE_SR_BUSYF)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of an operation end flag. + * @rmtoll SR BSYEND LL_ICACHE_IsActiveFlag_BSYEND + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ICACHE_IsActiveFlag_BSYEND(void) +{ + return ((READ_BIT(ICACHE->SR, ICACHE_SR_BSYENDF) == (ICACHE_SR_BSYENDF)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of an error flag. + * @rmtoll SR ERRF LL_ICACHE_IsActiveFlag_ERR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ICACHE_IsActiveFlag_ERR(void) +{ + return ((READ_BIT(ICACHE->SR, ICACHE_SR_ERRF) == (ICACHE_SR_ERRF)) ? 1UL : 0UL); +} + +/** + * @brief Clear busy end of operation flag. + * @rmtoll FCR CBSYENDF LL_ICACHE_ClearFlag_BSYEND + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_ClearFlag_BSYEND(void) +{ + WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); +} + +/** + * @brief Clear error flag. + * @rmtoll FCR ERRF LL_ICACHE_ClearFlag_ERR + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_ClearFlag_ERR(void) +{ + WRITE_REG(ICACHE->FCR, ICACHE_FCR_CERRF); +} + +/** + * @} + */ + +/** @defgroup ICACHE_LL_EF_REGION_Management REGION_Management + * @{ + */ + +/** + * @brief Enable the remapped memory region. + * @note The region must have been already configured. + * @rmtoll CRRx REN LL_ICACHE_EnableRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGION_0 + * @arg @ref LL_ICACHE_REGION_1 + * @arg @ref LL_ICACHE_REGION_2 + * @arg @ref LL_ICACHE_REGION_3 + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_EnableRegion(uint32_t Region) +{ + SET_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ + ICACHE_CRRx_REN); +} + +/** + * @brief Disable the remapped memory region. + * @rmtoll CRRx REN LL_ICACHE_DisableRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGION_0 + * @arg @ref LL_ICACHE_REGION_1 + * @arg @ref LL_ICACHE_REGION_2 + * @arg @ref LL_ICACHE_REGION_3 + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_DisableRegion(uint32_t Region) +{ + CLEAR_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ + ICACHE_CRRx_REN); +} + +/** + * @brief Return if remapped memory region is enabled or not. + * @rmtoll CRRx REN LL_ICACHE_IsEnabledRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGION_0 + * @arg @ref LL_ICACHE_REGION_1 + * @arg @ref LL_ICACHE_REGION_2 + * @arg @ref LL_ICACHE_REGION_3 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ICACHE_IsEnabledRegion(uint32_t Region) +{ + return ((READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ + ICACHE_CRRx_REN) == (ICACHE_CRRx_REN)) ? 1UL : 0UL); +} + +/** + * @brief Select the memory remapped region base address. + * @note The useful bits depends on RSIZE as described in the Reference Manual. + * @rmtoll CRRx BASEADDR LL_ICACHE_SetRegionBaseAddress + * @param Region This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGION_0 + * @arg @ref LL_ICACHE_REGION_1 + * @arg @ref LL_ICACHE_REGION_2 + * @arg @ref LL_ICACHE_REGION_3 + * @param Address Alias address in the Code region + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_SetRegionBaseAddress(uint32_t Region, uint32_t Address) +{ + MODIFY_REG(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ + ICACHE_CRRx_BASEADDR, ((Address & 0x1FFFFFFFU) >> 21U)); +} + +/** + * @brief Get the memory remapped region base address. + * @note The base address is the alias in the Code region. + * @note The useful bits depends on RSIZE as described in the Reference Manual. + * @rmtoll CRRx BASEADDR LL_ICACHE_GetRegionBaseAddress + * @param Region This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGION_0 + * @arg @ref LL_ICACHE_REGION_1 + * @arg @ref LL_ICACHE_REGION_2 + * @arg @ref LL_ICACHE_REGION_3 + * @retval Address Alias address in the Code region + */ +__STATIC_INLINE uint32_t LL_ICACHE_GetRegionBaseAddress(uint32_t Region) +{ + return (READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ + ICACHE_CRRx_BASEADDR) << 21U); +} + +/** + * @brief Select the memory remapped region address. + * @note The useful bits depends on RSIZE as described in the Reference Manual. + * @rmtoll CRRx REMAPADDR LL_ICACHE_SetRegionRemapAddress + * @param Region This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGION_0 + * @arg @ref LL_ICACHE_REGION_1 + * @arg @ref LL_ICACHE_REGION_2 + * @arg @ref LL_ICACHE_REGION_3 + * @param Address Memory address to remap + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_SetRegionRemapAddress(uint32_t Region, uint32_t Address) +{ + MODIFY_REG(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ + ICACHE_CRRx_REMAPADDR, ((Address >> 21U) << ICACHE_CRRx_REMAPADDR_Pos)); +} + +/** + * @brief Get the memory remapped region address. + * @note The useful bits depends on RSIZE as described in the Reference Manual. + * @rmtoll CRRx REMAPADDR LL_ICACHE_GetRegionRemapAddress + * @param Region This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGION_0 + * @arg @ref LL_ICACHE_REGION_1 + * @arg @ref LL_ICACHE_REGION_2 + * @arg @ref LL_ICACHE_REGION_3 + * @retval Address Remapped memory address + */ +__STATIC_INLINE uint32_t LL_ICACHE_GetRegionRemapAddress(uint32_t Region) +{ + return ((READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ + ICACHE_CRRx_REMAPADDR) >> ICACHE_CRRx_REMAPADDR_Pos) << 21U); +} + +/** + * @brief Select the memory remapped region size. + * @rmtoll CRRx RSIZE LL_ICACHE_SetRegionSize + * @param Region This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGION_0 + * @arg @ref LL_ICACHE_REGION_1 + * @arg @ref LL_ICACHE_REGION_2 + * @arg @ref LL_ICACHE_REGION_3 + * @param Size This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGIONSIZE_2MB + * @arg @ref LL_ICACHE_REGIONSIZE_4MB + * @arg @ref LL_ICACHE_REGIONSIZE_8MB + * @arg @ref LL_ICACHE_REGIONSIZE_16MB + * @arg @ref LL_ICACHE_REGIONSIZE_32MB + * @arg @ref LL_ICACHE_REGIONSIZE_64MB + * @arg @ref LL_ICACHE_REGIONSIZE_128MB + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_SetRegionSize(uint32_t Region, uint32_t Size) +{ + MODIFY_REG(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ + ICACHE_CRRx_RSIZE, (Size << ICACHE_CRRx_RSIZE_Pos)); +} + +/** + * @brief Get the selected the memory remapped region size. + * @rmtoll CRRx RSIZE LL_ICACHE_GetRegionSize + * @param Region This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGION_0 + * @arg @ref LL_ICACHE_REGION_1 + * @arg @ref LL_ICACHE_REGION_2 + * @arg @ref LL_ICACHE_REGION_3 + * @retval Returned value can be one of the following values: + * @arg @ref LL_ICACHE_REGIONSIZE_2MB + * @arg @ref LL_ICACHE_REGIONSIZE_4MB + * @arg @ref LL_ICACHE_REGIONSIZE_8MB + * @arg @ref LL_ICACHE_REGIONSIZE_16MB + * @arg @ref LL_ICACHE_REGIONSIZE_32MB + * @arg @ref LL_ICACHE_REGIONSIZE_64MB + * @arg @ref LL_ICACHE_REGIONSIZE_128MB + */ +__STATIC_INLINE uint32_t LL_ICACHE_GetRegionSize(uint32_t Region) +{ + return (READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ + ICACHE_CRRx_RSIZE) >> ICACHE_CRRx_RSIZE_Pos); +} + +/** + * @brief Select the memory remapped region output burst type. + * @rmtoll CRRx HBURST LL_ICACHE_SetRegionOutputBurstType + * @param Region This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGION_0 + * @arg @ref LL_ICACHE_REGION_1 + * @arg @ref LL_ICACHE_REGION_2 + * @arg @ref LL_ICACHE_REGION_3 + * @param Type This parameter can be one of the following values: + * @arg @ref LL_ICACHE_OUTPUT_BURST_WRAP + * @arg @ref LL_ICACHE_OUTPUT_BURST_INCR + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_SetRegionOutputBurstType(uint32_t Region, uint32_t Type) +{ + MODIFY_REG(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ + ICACHE_CRRx_HBURST, Type); +} + +/** + * @brief Get the selected the memory remapped region output burst type. + * @rmtoll CRRx HBURST LL_ICACHE_GetRegionOutputBurstType + * @param Region This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGION_0 + * @arg @ref LL_ICACHE_REGION_1 + * @arg @ref LL_ICACHE_REGION_2 + * @arg @ref LL_ICACHE_REGION_3 + * @retval Returned value can be one of the following values: + * @arg @ref LL_ICACHE_OUTPUT_BURST_WRAP + * @arg @ref LL_ICACHE_OUTPUT_BURST_INCR + */ +__STATIC_INLINE uint32_t LL_ICACHE_GetRegionOutputBurstType(uint32_t Region) +{ + return (READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ + ICACHE_CRRx_HBURST)); +} + +/** + * @brief Select the memory remapped region cache master port. + * @rmtoll CRRx MSTSEL LL_ICACHE_SetRegionMasterPort + * @param Region This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGION_0 + * @arg @ref LL_ICACHE_REGION_1 + * @arg @ref LL_ICACHE_REGION_2 + * @arg @ref LL_ICACHE_REGION_3 + * @param Port This parameter can be one of the following values: + * @arg @ref LL_ICACHE_MASTER1_PORT + * @arg @ref LL_ICACHE_MASTER2_PORT + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_SetRegionMasterPort(uint32_t Region, uint32_t Port) +{ + MODIFY_REG(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ + ICACHE_CRRx_MSTSEL, Port); +} + +/** + * @brief Get the selected the memory remapped region cache master port. + * @rmtoll CRRx MSTSEL LL_ICACHE_GetRegionMasterPort + * @param Region This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGION_0 + * @arg @ref LL_ICACHE_REGION_1 + * @arg @ref LL_ICACHE_REGION_2 + * @arg @ref LL_ICACHE_REGION_3 + * @retval Returned value can be one of the following values: + * @arg @ref LL_ICACHE_MASTER1_PORT + * @arg @ref LL_ICACHE_MASTER2_PORT + */ +__STATIC_INLINE uint32_t LL_ICACHE_GetRegionMasterPort(uint32_t Region) +{ + return (READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ + ICACHE_CRRx_MSTSEL)); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup ICACHE_LL_EF_REGION_Init Region Initialization functions + * @{ + */ + +void LL_ICACHE_ConfigRegion(uint32_t Region, const LL_ICACHE_RegionTypeDef *const pICACHE_RegionStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* ICACHE */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WBAxx_LL_ICACHE_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_iwdg.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_iwdg.h new file mode 100644 index 0000000000..e0df90d961 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_iwdg.h @@ -0,0 +1,453 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_ll_iwdg.h + * @author MCD Application Team + * @brief Header file of IWDG LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_LL_IWDG_H +#define STM32WBAxx_LL_IWDG_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx.h" + +/** @addtogroup STM32WBAxx_LL_Driver + * @{ + */ + +#if defined(IWDG) + +/** @defgroup IWDG_LL IWDG + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup IWDG_LL_Private_Constants IWDG Private Constants + * @{ + */ +#define LL_IWDG_KEY_RELOAD 0x0000AAAAU /*!< IWDG Reload Counter Enable */ +#define LL_IWDG_KEY_ENABLE 0x0000CCCCU /*!< IWDG Peripheral Enable */ +#define LL_IWDG_KEY_WR_ACCESS_ENABLE 0x00005555U /*!< IWDG KR Write Access Enable */ +#define LL_IWDG_KEY_WR_ACCESS_DISABLE 0x00000000U /*!< IWDG KR Write Access Disable */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup IWDG_LL_Exported_Constants IWDG Exported Constants + * @{ + */ + +/** @defgroup IWDG_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_IWDG_ReadReg function + * @{ + */ +#define LL_IWDG_SR_PVU IWDG_SR_PVU /*!< Watchdog prescaler value update */ +#define LL_IWDG_SR_RVU IWDG_SR_RVU /*!< Watchdog counter reload value update */ +#define LL_IWDG_SR_WVU IWDG_SR_WVU /*!< Watchdog counter window value update */ +/** + * @} + */ + +/** @defgroup IWDG_LL_EC_PRESCALER Prescaler Divider + * @{ + */ +#define LL_IWDG_PRESCALER_4 0x00000000U /*!< Divider by 4 */ +#define LL_IWDG_PRESCALER_8 (IWDG_PR_PR_0) /*!< Divider by 8 */ +#define LL_IWDG_PRESCALER_16 (IWDG_PR_PR_1) /*!< Divider by 16 */ +#define LL_IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< Divider by 32 */ +#define LL_IWDG_PRESCALER_64 (IWDG_PR_PR_2) /*!< Divider by 64 */ +#define LL_IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< Divider by 128 */ +#define LL_IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< Divider by 256 */ +#define LL_IWDG_PRESCALER_512 (IWDG_PR_PR_2 | IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< Divider by 512 */ +#define LL_IWDG_PRESCALER_1024 IWDG_PR_PR_3 /*!< Divider by 1024 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup IWDG_LL_Exported_Macros IWDG Exported Macros + * @{ + */ + +/** @defgroup IWDG_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in IWDG register + * @param __INSTANCE__ IWDG Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_IWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in IWDG register + * @param __INSTANCE__ IWDG Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_IWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup IWDG_LL_Exported_Functions IWDG Exported Functions + * @{ + */ +/** @defgroup IWDG_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Start the Independent Watchdog + * @note Except if the hardware watchdog option is selected + * @rmtoll KR KEY LL_IWDG_Enable + * @param IWDGx IWDG Instance + * @retval None + */ +__STATIC_INLINE void LL_IWDG_Enable(IWDG_TypeDef *IWDGx) +{ + WRITE_REG(IWDGx->KR, LL_IWDG_KEY_ENABLE); +} + +/** + * @brief Reloads IWDG counter with value defined in the reload register + * @rmtoll KR KEY LL_IWDG_ReloadCounter + * @param IWDGx IWDG Instance + * @retval None + */ +__STATIC_INLINE void LL_IWDG_ReloadCounter(IWDG_TypeDef *IWDGx) +{ + WRITE_REG(IWDGx->KR, LL_IWDG_KEY_RELOAD); +} + +/** + * @brief Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers + * @rmtoll KR KEY LL_IWDG_EnableWriteAccess + * @param IWDGx IWDG Instance + * @retval None + */ +__STATIC_INLINE void LL_IWDG_EnableWriteAccess(IWDG_TypeDef *IWDGx) +{ + WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE); +} + +/** + * @brief Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers + * @rmtoll KR KEY LL_IWDG_DisableWriteAccess + * @param IWDGx IWDG Instance + * @retval None + */ +__STATIC_INLINE void LL_IWDG_DisableWriteAccess(IWDG_TypeDef *IWDGx) +{ + WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE); +} + +/** + * @brief Select the prescaler of the IWDG + * @rmtoll PR PR LL_IWDG_SetPrescaler + * @param IWDGx IWDG Instance + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_IWDG_PRESCALER_4 + * @arg @ref LL_IWDG_PRESCALER_8 + * @arg @ref LL_IWDG_PRESCALER_16 + * @arg @ref LL_IWDG_PRESCALER_32 + * @arg @ref LL_IWDG_PRESCALER_64 + * @arg @ref LL_IWDG_PRESCALER_128 + * @arg @ref LL_IWDG_PRESCALER_256 + * @arg @ref LL_IWDG_PRESCALER_512 + * @arg @ref LL_IWDG_PRESCALER_1024 + * @retval None + */ +__STATIC_INLINE void LL_IWDG_SetPrescaler(IWDG_TypeDef *IWDGx, uint32_t Prescaler) +{ + WRITE_REG(IWDGx->PR, IWDG_PR_PR & Prescaler); +} + +/** + * @brief Get the selected prescaler of the IWDG + * @rmtoll PR PR LL_IWDG_GetPrescaler + * @param IWDGx IWDG Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_IWDG_PRESCALER_4 + * @arg @ref LL_IWDG_PRESCALER_8 + * @arg @ref LL_IWDG_PRESCALER_16 + * @arg @ref LL_IWDG_PRESCALER_32 + * @arg @ref LL_IWDG_PRESCALER_64 + * @arg @ref LL_IWDG_PRESCALER_128 + * @arg @ref LL_IWDG_PRESCALER_256 + * @arg @ref LL_IWDG_PRESCALER_512 + * @arg @ref LL_IWDG_PRESCALER_1024 + */ +__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(const IWDG_TypeDef *IWDGx) +{ + return (READ_REG(IWDGx->PR)); +} + +/** + * @brief Specify the IWDG down-counter reload value + * @rmtoll RLR RL LL_IWDG_SetReloadCounter + * @param IWDGx IWDG Instance + * @param Counter Value between Min_Data=0 and Max_Data=0x0FFF + * @retval None + */ +__STATIC_INLINE void LL_IWDG_SetReloadCounter(IWDG_TypeDef *IWDGx, uint32_t Counter) +{ + WRITE_REG(IWDGx->RLR, IWDG_RLR_RL & Counter); +} + +/** + * @brief Get the specified IWDG down-counter reload value + * @rmtoll RLR RL LL_IWDG_GetReloadCounter + * @param IWDGx IWDG Instance + * @retval Value between Min_Data=0 and Max_Data=0x0FFF + */ +__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(const IWDG_TypeDef *IWDGx) +{ + return (READ_REG(IWDGx->RLR)); +} + +/** + * @brief Specify high limit of the window value to be compared to the down-counter. + * @rmtoll WINR WIN LL_IWDG_SetWindow + * @param IWDGx IWDG Instance + * @param Window Value between Min_Data=0 and Max_Data=0x0FFF + * @retval None + */ +__STATIC_INLINE void LL_IWDG_SetWindow(IWDG_TypeDef *IWDGx, uint32_t Window) +{ + WRITE_REG(IWDGx->WINR, IWDG_WINR_WIN & Window); +} + +/** + * @brief Get the high limit of the window value specified. + * @rmtoll WINR WIN LL_IWDG_GetWindow + * @param IWDGx IWDG Instance + * @retval Value between Min_Data=0 and Max_Data=0x0FFF + */ +__STATIC_INLINE uint32_t LL_IWDG_GetWindow(const IWDG_TypeDef *IWDGx) +{ + return (READ_REG(IWDGx->WINR)); +} + +/** + * @} + */ + +/** @defgroup IWDG_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Specify comparator value that will be used to trig Early Wakeup interrupt + * @rmtoll EWCR EWIT LL_IWDG_SetEwiTime + * @param IWDGx IWDG Instance + * @param Time Value between Min_Data=0 and Max_Data=0x0FFF + * @retval None + */ +__STATIC_INLINE void LL_IWDG_SetEwiTime(IWDG_TypeDef *IWDGx, uint32_t Time) +{ + MODIFY_REG(IWDGx->EWCR, IWDG_EWCR_EWIT, Time); +} + +/** + * @brief Get the Early Wakeup interrupt comparator value + * @rmtoll EWCR EWIT LL_IWDG_GetEwiTime + * @param IWDGx IWDG Instance + * @retval Value between Min_Data=0 and Max_Data=0x0FFF + */ +__STATIC_INLINE uint32_t LL_IWDG_GetEwiTime(const IWDG_TypeDef *IWDGx) +{ + return (READ_BIT(IWDGx->EWCR, IWDG_EWCR_EWIT)); +} + +/** + * @brief Enable Early wakeup interrupt + * @rmtoll EWCR EWIE LL_IWDG_EnableIT_EWI + * @param IWDGx IWDG Instance + * @retval None + */ +__STATIC_INLINE void LL_IWDG_EnableIT_EWI(IWDG_TypeDef *IWDGx) +{ + SET_BIT(IWDGx->EWCR, IWDG_EWCR_EWIE); +} + +/** + * @brief Disable Early wakeup interrupt + * @rmtoll EWCR EWIE LL_IWDG_DisableIT_EWI + * @param IWDGx IWDG Instance + * @retval None + */ +__STATIC_INLINE void LL_IWDG_DisableIT_EWI(IWDG_TypeDef *IWDGx) +{ + CLEAR_BIT(IWDGx->EWCR, IWDG_EWCR_EWIE); +} + +/** + * @brief Indicates whether Early wakeup interrupt is enable + * @rmtoll EWCR EWIE LL_IWDG_IsEnabledIT_EWI + * @param IWDGx IWDG Instance + * @retval None + */ +__STATIC_INLINE uint32_t LL_IWDG_IsEnabledIT_EWI(const IWDG_TypeDef *IWDGx) +{ + return ((READ_BIT(IWDGx->EWCR, IWDG_EWCR_EWIE) == (IWDG_EWCR_EWIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup IWDG_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Check if flag Prescaler Value Update is set or not + * @rmtoll SR PVU LL_IWDG_IsActiveFlag_PVU + * @param IWDGx IWDG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(const IWDG_TypeDef *IWDGx) +{ + return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU)) ? 1UL : 0UL); +} + +/** + * @brief Check if flag Reload Value Update is set or not + * @rmtoll SR RVU LL_IWDG_IsActiveFlag_RVU + * @param IWDGx IWDG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(const IWDG_TypeDef *IWDGx) +{ + return ((READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU)) ? 1UL : 0UL); +} + +/** + * @brief Check if flag Window Value Update is set or not + * @rmtoll SR WVU LL_IWDG_IsActiveFlag_WVU + * @param IWDGx IWDG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(const IWDG_TypeDef *IWDGx) +{ + return ((READ_BIT(IWDGx->SR, IWDG_SR_WVU) == (IWDG_SR_WVU)) ? 1UL : 0UL); +} + +/** + * @brief Check if flag EWI Value Update is set or not + * @rmtoll SR EVU LL_IWDG_IsActiveFlag_EWU + * @param IWDGx IWDG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_EWU(const IWDG_TypeDef *IWDGx) +{ + return ((READ_BIT(IWDGx->SR, IWDG_SR_EWU) == (IWDG_SR_EWU)) ? 1UL : 0UL); +} + +/** + * @brief Check if all flags Prescaler, Reload, Window & Early Interrupt Value Update are reset or not + * @rmtoll SR PVU LL_IWDG_IsReady\n + * SR RVU LL_IWDG_IsReady\n + * SR WVU LL_IWDG_IsReady\n + * SR EWU LL_IWDG_IsReady + * @param IWDGx IWDG Instance + * @retval State of bits (1 or 0). + */ +__STATIC_INLINE uint32_t LL_IWDG_IsReady(const IWDG_TypeDef *IWDGx) +{ + return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU | IWDG_SR_WVU | IWDG_SR_EWU) == 0U) ? 1UL : 0UL); +} + +/** + * @brief Check if IWDG has been started or not + * @rmtoll SR ONF LL_IWDG_IsActiveFlag_ONF + * @param IWDGx IWDG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_ONF(const IWDG_TypeDef *IWDGx) +{ + return ((READ_BIT(IWDGx->SR, IWDG_SR_ONF) == (IWDG_SR_ONF)) ? 1UL : 0UL); +} + +/** + * @brief Check if Early Wakeup interrupt flag is set or not + * @rmtoll SR EWIF LL_IWDG_IsActiveFlag_EWIF + * @param IWDGx IWDG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_EWIF(const IWDG_TypeDef *IWDGx) +{ + return ((READ_BIT(IWDGx->SR, IWDG_SR_EWIF) == (IWDG_SR_EWIF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Early Wakeup interrupt flag + * @rmtoll EWCR EWIC LL_IWDG_ClearFlag_EWIF + * @param IWDGx IWDG Instance + * @retval None + */ +__STATIC_INLINE void LL_IWDG_ClearFlag_EWIF(IWDG_TypeDef *IWDGx) +{ + SET_BIT(IWDGx->EWCR, IWDG_EWCR_EWIC); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* IWDG */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WBAxx_LL_IWDG_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_lptim.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_lptim.h new file mode 100644 index 0000000000..fbe0291005 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_lptim.h @@ -0,0 +1,2426 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_ll_lptim.h + * @author MCD Application Team + * @brief Header file of LPTIM LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_LL_LPTIM_H +#define STM32WBAxx_LL_LPTIM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx.h" + +/** @addtogroup STM32WBAxx_LL_Driver + * @{ + */ + +#if defined (LPTIM1) || defined (LPTIM2) + +/** @defgroup LPTIM_LL LPTIM + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup LPTIM_LL_Private_variables LPTIM Private variables + * @{ + */ + +static const uint8_t LL_LPTIM_SHIFT_TAB_CCxP[] = +{ + 0U, /* CC1P */ + 16U /* CC2P */ +}; + +static const uint8_t LL_LPTIM_SHIFT_TAB_ICxF[] = +{ + 0U, /* IC1F */ + 16U /* IC2F */ +}; + +static const uint8_t LL_LPTIM_SHIFT_TAB_ICxPSC[] = +{ + 0U, /* IC1PSC */ + 16U /* IC2PSC */ +}; + +static const uint8_t LL_LPTIM_SHIFT_TAB_CCxSEL[] = +{ + 0U, /* CC1SEL */ + 16U /* CC2SEL */ +}; + +static const uint8_t LL_LPTIM_SHIFT_TAB_CCxE[] = +{ + LPTIM_CCMR1_CC1E_Pos, /* CC1E */ + LPTIM_CCMR1_CC2E_Pos /* CC2E */ +}; + +static const uint8_t LL_LPTIM_OFFSET_TAB_ICx[8][4] = +{ + {2, 7, 9, 13}, + {3, 5, 6, 8}, + {2, 3, 4, 5}, + {2, 2, 3, 3}, + {2, 2, 2, 2}, + {2, 2, 2, 2}, + {2, 2, 2, 2}, + {2, 2, 2, 2} + +}; + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup LPTIM_LL_Private_Macros LPTIM Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup LPTIM_LL_ES_INIT LPTIM Exported Init structure + * @{ + */ + +/** + * @brief LPTIM Init structure definition + */ +typedef struct +{ + uint32_t ClockSource; /*!< Specifies the source of the clock used by the LPTIM instance. + This parameter can be a value of @ref LPTIM_LL_EC_CLK_SOURCE. + + This feature can be modified afterwards using unitary + function @ref LL_LPTIM_SetClockSource().*/ + + uint32_t Prescaler; /*!< Specifies the prescaler division ratio. + This parameter can be a value of @ref LPTIM_LL_EC_PRESCALER. + + This feature can be modified afterwards using using unitary + function @ref LL_LPTIM_SetPrescaler().*/ + + uint32_t Waveform; /*!< Specifies the waveform shape. + This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_WAVEFORM. + + This feature can be modified afterwards using unitary + function @ref LL_LPTIM_SetWaveform().*/ +} LL_LPTIM_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup LPTIM_LL_Exported_Constants LPTIM Exported Constants + * @{ + */ + +/** @defgroup LPTIM_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_LPTIM_ReadReg function + * @{ + */ +#define LL_LPTIM_ISR_CMP1OK LPTIM_ISR_CMP1OK /*!< Compare register 1 update OK */ +#define LL_LPTIM_ISR_CMP2OK LPTIM_ISR_CMP2OK /*!< Compare register 2 update OK */ +#define LL_LPTIM_ISR_CC1IF LPTIM_ISR_CC1IF /*!< Capture/Compare 1 interrupt flag */ +#define LL_LPTIM_ISR_CC2IF LPTIM_ISR_CC2IF /*!< Capture/Compare 2 interrupt flag */ +#define LL_LPTIM_ISR_CC1OF LPTIM_ISR_CC1OF /*!< Capture/Compare 1 over-capture flag */ +#define LL_LPTIM_ISR_CC2OF LPTIM_ISR_CC2OF /*!< Capture/Compare 2 over-capture flag */ +#define LL_LPTIM_ISR_DIEROK LPTIM_ISR_DIEROK /*!< Interrupt enable register update OK */ +#define LL_LPTIM_ISR_ARRM LPTIM_ISR_ARRM /*!< Autoreload match */ +#define LL_LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG /*!< External trigger edge event */ +#define LL_LPTIM_ISR_ARROK LPTIM_ISR_ARROK /*!< Autoreload register update OK */ +#define LL_LPTIM_ISR_UP LPTIM_ISR_UP /*!< Counter direction change down to up */ +#define LL_LPTIM_ISR_DOWN LPTIM_ISR_DOWN /*!< Counter direction change up to down */ +#define LL_LPTIM_ISR_UE LPTIM_ISR_UE /*!< Update event */ +#define LL_LPTIM_ISR_REPOK LPTIM_ISR_REPOK /*!< Repetition register update OK */ +/** + * @} + */ + +/** @defgroup LPTIM_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_LPTIM_ReadReg and LL_LPTIM_WriteReg functions + * @{ + */ +#define LL_LPTIM_DIER_CMP1OKIE LPTIM_DIER_CMP1OKIE /*!< Compare register 1 update OK */ +#define LL_LPTIM_DIER_CMP2OKIE LPTIM_DIER_CMP2OKIE /*!< Compare register 2 update OK */ +#define LL_LPTIM_DIER_CC1IFIE LPTIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt flag */ +#define LL_LPTIM_DIER_CC2IFIE LPTIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt flag */ +#define LL_LPTIM_DIER_CC1OFIE LPTIM_DIER_CC1OIE /*!< Capture/Compare 1 over-capture flag */ +#define LL_LPTIM_DIER_CC2OFIE LPTIM_DIER_CC2OIE /*!< Capture/Compare 2 over-capture flag */ +#define LL_LPTIM_DIER_ARRMIE LPTIM_DIER_ARRMIE /*!< Autoreload match */ +#define LL_LPTIM_DIER_EXTTRIGIE LPTIM_DIER_EXTTRIGIE /*!< External trigger edge event */ +#define LL_LPTIM_DIER_ARROKIE LPTIM_DIER_ARROKIE /*!< Autoreload register update OK */ +#define LL_LPTIM_DIER_UPIE LPTIM_DIER_UPIE /*!< Counter direction change down to up */ +#define LL_LPTIM_DIER_DOWNIE LPTIM_DIER_DOWNIE /*!< Counter direction change up to down */ +#define LL_LPTIM_DIER_UEIE LPTIM_DIER_UEIE /*!< Update event */ +#define LL_LPTIM_DIER_REPOKIE LPTIM_DIER_REPOKIE /*!< Repetition register update OK */ +/** + * @} + */ + +/** @defgroup LPTIM_LL_EC_OPERATING_MODE Operating Mode + * @{ + */ +#define LL_LPTIM_OPERATING_MODE_CONTINUOUS LPTIM_CR_CNTSTRT /*!__REG__, (__VALUE__)) + +/** + * @brief Read a value in LPTIM register + * @param __INSTANCE__ LPTIM Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__) + +/** + * @brief LPTimer Input Capture Get Offset(in counter step unit) + * @note The real capture value corresponding to the input capture trigger can be calculated using + * the formula hereafter : Real capture value = captured(LPTIM_CCRx) - offset + * The Offset value is depending on the glitch filter value for the channel + * and the value of the prescaler for the kernel clock. + * Please check Errata Sheet V1_8 for more details under "variable latency + * on input capture channel" section. + * @param __PSC__ This parameter can be one of the following values: + * @arg @ref LL_LPTIM_PRESCALER_DIV1 + * @arg @ref LL_LPTIM_PRESCALER_DIV2 + * @arg @ref LL_LPTIM_PRESCALER_DIV4 + * @arg @ref LL_LPTIM_PRESCALER_DIV8 + * @arg @ref LL_LPTIM_PRESCALER_DIV16 + * @arg @ref LL_LPTIM_PRESCALER_DIV32 + * @arg @ref LL_LPTIM_PRESCALER_DIV64 + * @arg @ref LL_LPTIM_PRESCALER_DIV128 + * @param __FLT__ This parameter can be one of the following values: + * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV1 + * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV2 + * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV4 + * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV8 + * @retval offset value + */ +#define LL_LPTIM_IC_GET_OFFSET(__PSC__, __FLT__) LL_LPTIM_OFFSET_TAB_ICx\ + [((__PSC__) & LPTIM_CFGR_PRESC_Msk) >> LPTIM_CFGR_PRESC_Pos]\ + [((__FLT__) & LPTIM_CCMR1_IC1F_Msk) >> LPTIM_CCMR1_IC1F_Pos] +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup LPTIM_LL_Exported_Functions LPTIM Exported Functions + * @{ + */ + +/** Legacy definitions for compatibility purpose +@cond 0 + */ +#define LL_LPTIM_ClearFLAG_CMPM LL_LPTIM_ClearFlag_CMPM +#define LL_LPTIM_ClearFLAG_CC1 LL_LPTIM_ClearFlag_CC1 +#define LL_LPTIM_ClearFLAG_CC2 LL_LPTIM_ClearFlag_CC2 +#define LL_LPTIM_ClearFLAG_CC1O LL_LPTIM_ClearFlag_CC1O +#define LL_LPTIM_ClearFLAG_CC2O LL_LPTIM_ClearFlag_CC2O +#define LL_LPTIM_ClearFLAG_ARRM LL_LPTIM_ClearFlag_ARRM +/** +@endcond + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup LPTIM_LL_EF_Init Initialisation and deinitialisation functions + * @{ + */ + +ErrorStatus LL_LPTIM_DeInit(const LPTIM_TypeDef *LPTIMx); +void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct); +ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, const LL_LPTIM_InitTypeDef *LPTIM_InitStruct); +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** @defgroup LPTIM_LL_EF_LPTIM_Configuration LPTIM Configuration + * @{ + */ + +/** + * @brief Enable the LPTIM instance + * @note After setting the ENABLE bit, a delay of two counter clock is needed + * before the LPTIM instance is actually enabled. + * @rmtoll CR ENABLE LL_LPTIM_Enable + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_Enable(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->CR, LPTIM_CR_ENABLE); +} + +/** + * @brief Disable the LPTIM instance + * @rmtoll CR ENABLE LL_LPTIM_Disable + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx) +{ + CLEAR_BIT(LPTIMx->CR, LPTIM_CR_ENABLE); +} + +/** + * @brief Indicates whether the LPTIM instance is enabled. + * @rmtoll CR ENABLE LL_LPTIM_IsEnabled + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(const LPTIM_TypeDef *LPTIMx) +{ + return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE) ? 1UL : 0UL)); +} + +/** + * @brief Starts the LPTIM counter in the desired mode. + * @note LPTIM instance must be enabled before starting the counter. + * @note It is possible to change on the fly from One Shot mode to + * Continuous mode. + * @rmtoll CR CNTSTRT LL_LPTIM_StartCounter\n + * CR SNGSTRT LL_LPTIM_StartCounter + * @param LPTIMx Low-Power Timer instance + * @param OperatingMode This parameter can be one of the following values: + * @arg @ref LL_LPTIM_OPERATING_MODE_CONTINUOUS + * @arg @ref LL_LPTIM_OPERATING_MODE_ONESHOT + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_StartCounter(LPTIM_TypeDef *LPTIMx, uint32_t OperatingMode) +{ + MODIFY_REG(LPTIMx->CR, LPTIM_CR_CNTSTRT | LPTIM_CR_SNGSTRT, OperatingMode); +} + +/** + * @brief Enable reset after read. + * @note After calling this function any read access to LPTIM_CNT + * register will asynchronously reset the LPTIM_CNT register content. + * @rmtoll CR RSTARE LL_LPTIM_EnableResetAfterRead + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_EnableResetAfterRead(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->CR, LPTIM_CR_RSTARE); +} + +/** + * @brief Disable reset after read. + * @rmtoll CR RSTARE LL_LPTIM_DisableResetAfterRead + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_DisableResetAfterRead(LPTIM_TypeDef *LPTIMx) +{ + CLEAR_BIT(LPTIMx->CR, LPTIM_CR_RSTARE); +} + +/** + * @brief Indicate whether the reset after read feature is enabled. + * @rmtoll CR RSTARE LL_LPTIM_IsEnabledResetAfterRead + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledResetAfterRead(const LPTIM_TypeDef *LPTIMx) +{ + return (((READ_BIT(LPTIMx->CR, LPTIM_CR_RSTARE) == LPTIM_CR_RSTARE) ? 1UL : 0UL)); +} + +/** + * @brief Reset of the LPTIM_CNT counter register (synchronous). + * @note Due to the synchronous nature of this reset, it only takes + * place after a synchronization delay of 3 LPTIM core clock cycles + * (LPTIM core clock may be different from APB clock). + * @note COUNTRST is automatically cleared by hardware + * @rmtoll CR COUNTRST LL_LPTIM_ResetCounter\n + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_ResetCounter(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->CR, LPTIM_CR_COUNTRST); +} + +/** + * @brief Set the LPTIM registers update mode (enable/disable register preload) + * @note This function must be called when the LPTIM instance is disabled. + * @rmtoll CFGR PRELOAD LL_LPTIM_SetUpdateMode + * @param LPTIMx Low-Power Timer instance + * @param UpdateMode This parameter can be one of the following values: + * @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE + * @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_SetUpdateMode(LPTIM_TypeDef *LPTIMx, uint32_t UpdateMode) +{ + MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD, UpdateMode); +} + +/** + * @brief Get the LPTIM registers update mode + * @rmtoll CFGR PRELOAD LL_LPTIM_GetUpdateMode + * @param LPTIMx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE + * @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD + */ +__STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(const LPTIM_TypeDef *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD)); +} + +/** + * @brief Set the auto reload value + * @note The LPTIMx_ARR register content must only be modified when the LPTIM is enabled + * @note After a write to the LPTIMx_ARR register a new write operation to the + * same register can only be performed when the previous write operation + * is completed. Any successive write before the ARROK flag is set, will + * lead to unpredictable results. + * @note autoreload value be strictly greater than the compare value. + * @rmtoll ARR ARR LL_LPTIM_SetAutoReload + * @param LPTIMx Low-Power Timer instance + * @param AutoReload Value between Min_Data=0x0001 and Max_Data=0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_SetAutoReload(LPTIM_TypeDef *LPTIMx, uint32_t AutoReload) +{ + MODIFY_REG(LPTIMx->ARR, LPTIM_ARR_ARR, AutoReload); +} + +/** + * @brief Get actual auto reload value + * @rmtoll ARR ARR LL_LPTIM_GetAutoReload + * @param LPTIMx Low-Power Timer instance + * @retval AutoReload Value between Min_Data=0x0001 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(const LPTIM_TypeDef *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->ARR, LPTIM_ARR_ARR)); +} + +/** + * @brief Set the repetition value + * @note The LPTIMx_RCR register content must only be modified when the LPTIM is enabled + * @rmtoll RCR REP LL_LPTIM_SetRepetition + * @param LPTIMx Low-Power Timer instance + * @param Repetition Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_SetRepetition(LPTIM_TypeDef *LPTIMx, uint32_t Repetition) +{ + MODIFY_REG(LPTIMx->RCR, LPTIM_RCR_REP, Repetition); +} + +/** + * @brief Get the repetition value + * @rmtoll RCR REP LL_LPTIM_GetRepetition + * @param LPTIMx Low-Power Timer instance + * @retval Repetition Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_LPTIM_GetRepetition(const LPTIM_TypeDef *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->RCR, LPTIM_RCR_REP)); +} + +/** + * @brief Enable capture/compare channel. + * @rmtoll CCMR1 CC1E LL_LPTIM_CC_EnableChannel\n + * CCMR1 CC2E LL_LPTIM_CC_EnableChannel + * @param LPTIMx LPTimer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_LPTIM_CHANNEL_CH1 + * @arg @ref LL_LPTIM_CHANNEL_CH2 + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_CC_EnableChannel(LPTIM_TypeDef *LPTIMx, uint32_t Channel) +{ + SET_BIT(LPTIMx->CCMR1, 0x1UL << LL_LPTIM_SHIFT_TAB_CCxE[Channel]); +} + +/** + * @brief Disable capture/compare channel. + * @rmtoll CCMR1 CC1E LL_LPTIM_CC_DisableChannel\n + * CCMR1 CC2E LL_LPTIM_CC_DisableChannel + * @param LPTIMx LPTimer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_LPTIM_CHANNEL_CH1 + * @arg @ref LL_LPTIM_CHANNEL_CH2 + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_CC_DisableChannel(LPTIM_TypeDef *LPTIMx, uint32_t Channel) +{ + CLEAR_BIT(LPTIMx->CCMR1, 0x1UL << LL_LPTIM_SHIFT_TAB_CCxE[Channel]); +} + +/** + * @brief Indicate whether channel is enabled. + * @rmtoll CCMR1 CC1E LL_LPTIM_CC_IsEnabledChannel\n + * CCMR1 CC2E LL_LPTIM_CC_IsEnabledChannel + * @param LPTIMx LPTimer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_LPTIM_CHANNEL_CH1 + * @arg @ref LL_LPTIM_CHANNEL_CH2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_CC_IsEnabledChannel(const LPTIM_TypeDef *LPTIMx, uint32_t Channel) +{ + return ((READ_BIT(LPTIMx->CCMR1, 0x1UL << LL_LPTIM_SHIFT_TAB_CCxE[Channel]) == \ + (0x1UL << LL_LPTIM_SHIFT_TAB_CCxE[Channel])) ? 1UL : 0UL); + +} + +/** + * @brief Set the compare value + * @note After a write to the LPTIMx_CCR1 register a new write operation to the + * same register can only be performed when the previous write operation + * is completed. Any successive write before the CMP1OK flag is set, will + * lead to unpredictable results. + * @rmtoll CCR1 CCR1 LL_LPTIM_OC_SetCompareCH1 + * @param LPTIMx Low-Power Timer instance + * @param CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_OC_SetCompareCH1(LPTIM_TypeDef *LPTIMx, uint32_t CompareValue) +{ + MODIFY_REG(LPTIMx->CCR1, LPTIM_CCR1_CCR1, CompareValue); +} + +/** + * @brief Get actual compare value + * @rmtoll CCR1 CCR1 LL_LPTIM_OC_GetCompareCH1 + * @param LPTIMx Low-Power Timer instance + * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint32_t LL_LPTIM_OC_GetCompareCH1(const LPTIM_TypeDef *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CCR1, LPTIM_CCR1_CCR1)); +} + +/** + * @brief Set the compare value + * @note After a write to the LPTIMx_CCR2 register a new write operation to the + * same register can only be performed when the previous write operation + * is completed. Any successive write before the CMP2OK flag is set, will + * lead to unpredictable results. + * @rmtoll CCR2 CCR2 LL_LPTIM_OC_SetCompareCH2 + * @param LPTIMx Low-Power Timer instance + * @param CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_OC_SetCompareCH2(LPTIM_TypeDef *LPTIMx, uint32_t CompareValue) +{ + MODIFY_REG(LPTIMx->CCR2, LPTIM_CCR2_CCR2, CompareValue); +} + +/** + * @brief Get actual compare value + * @rmtoll CCR2 CCR2 LL_LPTIM_OC_GetCompareCH2 + * @param LPTIMx Low-Power Timer instance + * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint32_t LL_LPTIM_OC_GetCompareCH2(const LPTIM_TypeDef *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CCR2, LPTIM_CCR2_CCR2)); +} + +/** + * @brief Get actual counter value + * @note When the LPTIM instance is running with an asynchronous clock, reading + * the LPTIMx_CNT register may return unreliable values. So in this case + * it is necessary to perform two consecutive read accesses and verify + * that the two returned values are identical. + * @rmtoll CNT CNT LL_LPTIM_GetCounter + * @param LPTIMx Low-Power Timer instance + * @retval Counter value + */ +__STATIC_INLINE uint32_t LL_LPTIM_GetCounter(const LPTIM_TypeDef *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CNT, LPTIM_CNT_CNT)); +} + +/** + * @brief Set the counter mode (selection of the LPTIM counter clock source). + * @note The counter mode can be set only when the LPTIM instance is disabled. + * @rmtoll CFGR COUNTMODE LL_LPTIM_SetCounterMode + * @param LPTIMx Low-Power Timer instance + * @param CounterMode This parameter can be one of the following values: + * @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL + * @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_SetCounterMode(LPTIM_TypeDef *LPTIMx, uint32_t CounterMode) +{ + MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE, CounterMode); +} + +/** + * @brief Get the counter mode + * @rmtoll CFGR COUNTMODE LL_LPTIM_GetCounterMode + * @param LPTIMx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL + * @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL + */ +__STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode(const LPTIM_TypeDef *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE)); +} + +/** + * @brief Set waveform shape + * @rmtoll CFGR WAVE LL_LPTIM_SetWaveform + * @param LPTIMx Low-Power Timer instance + * @param Waveform This parameter can be one of the following values: + * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM + * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_SetWaveform(LPTIM_TypeDef *LPTIMx, uint32_t Waveform) +{ + MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE, Waveform); +} + +/** + * @brief Get actual waveform shape + * @rmtoll CFGR WAVE LL_LPTIM_GetWaveform + * @param LPTIMx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM + * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE + */ +__STATIC_INLINE uint32_t LL_LPTIM_GetWaveform(const LPTIM_TypeDef *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVE)); +} + +/** + * @brief Set the polarity of an output channel. + * @rmtoll CCMR1 CC1P LL_LPTIM_OC_SetPolarity\n + * @rmtoll CCMR1 CC2P LL_LPTIM_OC_SetPolarity\n + * @param LPTIMx Low-Power Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_LPTIM_CHANNEL_CH1 + * @arg @ref LL_LPTIM_CHANNEL_CH2 + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR + * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_OC_SetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t Polarity) +{ + MODIFY_REG(LPTIMx->CCMR1, (LPTIM_CCMR1_CC1P << LL_LPTIM_SHIFT_TAB_CCxP[Channel]), + (Polarity << LL_LPTIM_SHIFT_TAB_CCxP[Channel])); +} + +/** + * @brief Get the polarity of an output channel. + * @rmtoll CCMR1 CC1P LL_LPTIM_OC_GetPolarity\n + * @rmtoll CCMR1 CC2P LL_LPTIM_OC_GetPolarity\n + * @param LPTIMx Low-Power Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_LPTIM_CHANNEL_CH1 + * @arg @ref LL_LPTIM_CHANNEL_CH2 + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR + * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE + */ +__STATIC_INLINE uint32_t LL_LPTIM_OC_GetPolarity(const LPTIM_TypeDef *LPTIMx, uint32_t Channel) +{ + return (uint32_t)((READ_BIT(LPTIMx->CCMR1, (LPTIM_CCMR1_CC1P << LL_LPTIM_SHIFT_TAB_CCxP[Channel]))) >> \ + LL_LPTIM_SHIFT_TAB_CCxP[Channel]); +} + +/** + * @brief Set actual prescaler division ratio. + * @note This function must be called when the LPTIM instance is disabled. + * @note When the LPTIM is configured to be clocked by an internal clock source + * and the LPTIM counter is configured to be updated by active edges + * detected on the LPTIM external Input1, the internal clock provided to + * the LPTIM must be not be prescaled. + * @rmtoll CFGR PRESC LL_LPTIM_SetPrescaler + * @param LPTIMx Low-Power Timer instance + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_LPTIM_PRESCALER_DIV1 + * @arg @ref LL_LPTIM_PRESCALER_DIV2 + * @arg @ref LL_LPTIM_PRESCALER_DIV4 + * @arg @ref LL_LPTIM_PRESCALER_DIV8 + * @arg @ref LL_LPTIM_PRESCALER_DIV16 + * @arg @ref LL_LPTIM_PRESCALER_DIV32 + * @arg @ref LL_LPTIM_PRESCALER_DIV64 + * @arg @ref LL_LPTIM_PRESCALER_DIV128 + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_SetPrescaler(LPTIM_TypeDef *LPTIMx, uint32_t Prescaler) +{ + MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRESC, Prescaler); +} + +/** + * @brief Get actual prescaler division ratio. + * @rmtoll CFGR PRESC LL_LPTIM_GetPrescaler + * @param LPTIMx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPTIM_PRESCALER_DIV1 + * @arg @ref LL_LPTIM_PRESCALER_DIV2 + * @arg @ref LL_LPTIM_PRESCALER_DIV4 + * @arg @ref LL_LPTIM_PRESCALER_DIV8 + * @arg @ref LL_LPTIM_PRESCALER_DIV16 + * @arg @ref LL_LPTIM_PRESCALER_DIV32 + * @arg @ref LL_LPTIM_PRESCALER_DIV64 + * @arg @ref LL_LPTIM_PRESCALER_DIV128 + */ +__STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(const LPTIM_TypeDef *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRESC)); +} + +/** + * @brief Set LPTIM input 1 source (default GPIO). + * @rmtoll CFGR2 IN1SEL LL_LPTIM_SetInput1Src + * @param LPTIMx Low-Power Timer instance + * @param Src This parameter can be one of the following values: + * @arg @ref LL_LPTIM_INPUT1_SRC_GPIO + * @arg @ref LL_LPTIM_INPUT1_SRC_COMP1 (*) + * (*) Value not defined for all devices + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_SetInput1Src(LPTIM_TypeDef *LPTIMx, uint32_t Src) +{ + MODIFY_REG(LPTIMx->CFGR2, LPTIM_CFGR2_IN1SEL, Src); +} + +/** + * @brief Set LPTIM input 2 source (default GPIO). + * @rmtoll CFGR2 IN2SEL LL_LPTIM_SetInput2Src + * @param LPTIMx Low-Power Timer instance + * @param Src This parameter can be one of the following values: + * @arg @ref LL_LPTIM_INPUT2_SRC_GPIO + * @arg @ref LL_LPTIM_INPUT2_SRC_COMP2 (*) + * (*) Value not defined for all devices + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_SetInput2Src(LPTIM_TypeDef *LPTIMx, uint32_t Src) +{ + MODIFY_REG(LPTIMx->CFGR2, LPTIM_CFGR2_IN2SEL, Src); +} + +/** + * @brief Set LPTIM input source (default GPIO). + * @rmtoll CFGR2 IC1SEL LL_LPTIM_SetRemap + * @rmtoll CFGR2 IC2SEL LL_LPTIM_SetRemap + * @param LPTIMx Low-Power Timer instance + * @param Src This parameter can be one of the following values: + * @arg @ref LL_LPTIM_LPTIM1_IC1_RMP_GPIO + * @arg @ref LL_LPTIM_LPTIM1_IC1_RMP_COMP1 (*) + * @arg @ref LL_LPTIM_LPTIM1_IC1_RMP_COMP2 (*) + * @arg @ref LL_LPTIM_LPTIM1_IC2_RMP_GPIO + * @arg @ref LL_LPTIM_LPTIM1_IC2_RMP_LSI + * @arg @ref LL_LPTIM_LPTIM1_IC2_RMP_LSE + * @arg @ref LL_LPTIM_LPTIM2_IC1_RMP_GPIO + * @arg @ref LL_LPTIM_LPTIM2_IC1_RMP_COMP1 (*) + * @arg @ref LL_LPTIM_LPTIM2_IC1_RMP_COMP2 (*) + * @arg @ref LL_LPTIM_LPTIM2_IC2_RMP_GPIO + * @arg @ref LL_LPTIM_LPTIM2_IC2_RMP_HSI_256 + * + * (*) Value not defined in all devices. \n + * + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_SetRemap(LPTIM_TypeDef *LPTIMx, uint32_t Src) +{ + MODIFY_REG(LPTIMx->CFGR2, LPTIM_CFGR2_IC1SEL | LPTIM_CFGR2_IC2SEL, Src); +} + +/** + * @brief Set the polarity of IC channel 1. + * @rmtoll CCMR1 CC1P LL_LPTIM_IC_SetPolarity\n + * @rmtoll CCMR1 CC2P LL_LPTIM_IC_SetPolarity\n + * @param LPTIMx Low-Power Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_LPTIM_CHANNEL_CH1 + * @arg @ref LL_LPTIM_CHANNEL_CH2 + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_LPTIM_ICPOLARITY_RISING + * @arg @ref LL_LPTIM_ICPOLARITY_FALLING + * @arg @ref LL_LPTIM_ICPOLARITY_RISING_FALLING + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_IC_SetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t Polarity) +{ + MODIFY_REG(LPTIMx->CCMR1, LPTIM_CCMR1_CC1P << LL_LPTIM_SHIFT_TAB_CCxP[Channel], + Polarity << LL_LPTIM_SHIFT_TAB_CCxP[Channel]); +} + +/** + * @brief Get the polarity of IC channels. + * @rmtoll CCMR1 CC1P LL_LPTIM_IC_GetPolarity\n + * @rmtoll CCMR1 CC2P LL_LPTIM_IC_GetPolarity\n + * @param LPTIMx Low-Power Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_LPTIM_CHANNEL_CH1 + * @arg @ref LL_LPTIM_CHANNEL_CH2 + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPTIM_ICPOLARITY_RISING + * @arg @ref LL_LPTIM_ICPOLARITY_FALLING + * @arg @ref LL_LPTIM_ICPOLARITY_RISING_FALLING + */ +__STATIC_INLINE uint32_t LL_LPTIM_IC_GetPolarity(const LPTIM_TypeDef *LPTIMx, uint32_t Channel) +{ + return (uint32_t)((READ_BIT(LPTIMx->CCMR1, LPTIM_CCMR1_CC1P << LL_LPTIM_SHIFT_TAB_CCxP[Channel])) >> \ + LL_LPTIM_SHIFT_TAB_CCxP[Channel]); + +} + +/** + * @brief Set the filter of IC channels. + * @rmtoll CCMR1 IC1F LL_LPTIM_IC_SetFilter\n + * @rmtoll CCMR1 IC2F LL_LPTIM_IC_SetFilter\n + * @param LPTIMx Low-Power Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_LPTIM_CHANNEL_CH1 + * @arg @ref LL_LPTIM_CHANNEL_CH2 + * @param Filter This parameter can be one of the following values: + * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV1 + * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV2 + * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV4 + * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV8 + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_IC_SetFilter(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t Filter) +{ + MODIFY_REG(LPTIMx->CCMR1, LPTIM_CCMR1_IC1F << LL_LPTIM_SHIFT_TAB_ICxF[Channel], + Filter << LL_LPTIM_SHIFT_TAB_ICxF[Channel]); +} + +/** + * @brief Get the filter of IC channels. + * @rmtoll CCMR1 IC1F LL_LPTIM_IC_GetFilter\n + * @rmtoll CCMR1 IC2F LL_LPTIM_IC_GetFilter\n + * @param LPTIMx Low-Power Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_LPTIM_CHANNEL_CH1 + * @arg @ref LL_LPTIM_CHANNEL_CH2 + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV1 + * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV2 + * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV4 + * @arg @ref LL_LPTIM_ICFLT_CLOCK_DIV8 + */ +__STATIC_INLINE uint32_t LL_LPTIM_IC_GetFilter(const LPTIM_TypeDef *LPTIMx, uint32_t Channel) +{ + return (uint32_t)((READ_BIT(LPTIMx->CCMR1, LPTIM_CCMR1_IC1F << LL_LPTIM_SHIFT_TAB_ICxF[Channel])) >> \ + LL_LPTIM_SHIFT_TAB_ICxF[Channel]); +} + +/** + * @brief Set the prescaler of IC channels. + * @rmtoll CCMR1 IC1PSC LL_LPTIM_IC_SetPrescaler\n + * @rmtoll CCMR1 IC2PSC LL_LPTIM_IC_SetPrescaler\n + * @param LPTIMx Low-Power Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_LPTIM_CHANNEL_CH1 + * @arg @ref LL_LPTIM_CHANNEL_CH2 + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_LPTIM_ICPSC_DIV1 + * @arg @ref LL_LPTIM_ICPSC_DIV2 + * @arg @ref LL_LPTIM_ICPSC_DIV4 + * @arg @ref LL_LPTIM_ICPSC_DIV8 + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_IC_SetPrescaler(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t Prescaler) +{ + MODIFY_REG(LPTIMx->CCMR1, LPTIM_CCMR1_IC1PSC << LL_LPTIM_SHIFT_TAB_ICxPSC[Channel], + Prescaler << LL_LPTIM_SHIFT_TAB_ICxPSC[Channel]); +} + +/** + * @brief Get the prescaler of IC channels. + * @rmtoll CCMR1 IC1PSC LL_LPTIM_IC_GetPrescaler\n + * @rmtoll CCMR1 IC2PSC LL_LPTIM_IC_GetPrescaler\n + * @param LPTIMx Low-Power Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_LPTIM_CHANNEL_CH1 + * @arg @ref LL_LPTIM_CHANNEL_CH2 + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPTIM_ICPSC_DIV1 + * @arg @ref LL_LPTIM_ICPSC_DIV2 + * @arg @ref LL_LPTIM_ICPSC_DIV4 + * @arg @ref LL_LPTIM_ICPSC_DIV8 + */ +__STATIC_INLINE uint32_t LL_LPTIM_IC_GetPrescaler(const LPTIM_TypeDef *LPTIMx, uint32_t Channel) +{ + return (uint32_t)((READ_BIT(LPTIMx->CCMR1, LPTIM_CCMR1_IC1PSC << LL_LPTIM_SHIFT_TAB_ICxPSC[Channel])) >> \ + LL_LPTIM_SHIFT_TAB_ICxPSC[Channel]); +} + +/** + * @brief Set the Channel Mode. + * @rmtoll CCMR1 CC1SEL LL_LPTIM_CC_SetChannelMode\n + * CCMR1 CC2SEL LL_LPTIM_CC_SetChannelMode + * @param LPTIMx Low-Power Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_LPTIM_CHANNEL_CH1 + * @arg @ref LL_LPTIM_CHANNEL_CH2 + * @param CCMode This parameter can be one of the following values: + * @arg @ref LL_LPTIM_CCMODE_OUTPUT_PWM + * @arg @ref LL_LPTIM_CCMODE_INPUTCAPTURE + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_CC_SetChannelMode(LPTIM_TypeDef *LPTIMx, uint32_t Channel, uint32_t CCMode) +{ + SET_BIT(LPTIMx->CCMR1, CCMode << LL_LPTIM_SHIFT_TAB_CCxSEL[Channel]); +} + +/** + * @brief Get the Channel Mode. + * @rmtoll CCMR1 CC1SEL LL_LPTIM_CC_GetChannelMode\n + * CCMR1 CC2SEL LL_LPTIM_CC_GetChannelMode + * @param LPTIMx Low-Power Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_LPTIM_CHANNEL_CH1 + * @arg @ref LL_LPTIM_CHANNEL_CH2 + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPTIM_CCMODE_OUTPUT_PWM + * @arg @ref LL_LPTIM_CCMODE_INPUTCAPTURE + */ +__STATIC_INLINE uint32_t LL_LPTIM_CC_GetChannelMode(const LPTIM_TypeDef *LPTIMx, uint32_t Channel) +{ + return (uint32_t)((READ_BIT(LPTIMx->CCMR1, LPTIM_CCMR1_CC1SEL << LL_LPTIM_SHIFT_TAB_CCxSEL[Channel])) >> \ + LL_LPTIM_SHIFT_TAB_CCxSEL[Channel]); +} + +/** + * @brief Get captured value for input channel 1. + * @rmtoll CCR1 CCR1 LL_LPTIM_IC_GetCaptureCH1 + * @note The real capture value corresponding to the input capture trigger can be calculated using + * the formula hereafter : Real capture value = captured(LPTIM_CCRx) - offset + * where offset can be retrieved by calling @ref LL_LPTIM_IC_GET_OFFSET + * @param LPTIMx Low-Power Timer instance + * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_LPTIM_IC_GetCaptureCH1(const LPTIM_TypeDef *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CCR1, LPTIM_CCR1_CCR1)); +} + +/** + * @brief Get captured value for input channel 2. + * @rmtoll CCR2 CCR2 LL_LPTIM_IC_GetCaptureCH2 + * @note The real capture value corresponding to the input capture trigger can be calculated using + * the formula hereafter : Real capture value = captured(LPTIM_CCRx) - offset + * where offset can be retrieved by calling @ref LL_LPTIM_IC_GET_OFFSET + * @param LPTIMx Low-Power Timer instance + * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_LPTIM_IC_GetCaptureCH2(const LPTIM_TypeDef *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CCR2, LPTIM_CCR2_CCR2)); +} + +/** + * @} + */ + +/** @defgroup LPTIM_LL_EF_Trigger_Configuration Trigger Configuration + * @{ + */ + +/** + * @brief Enable the timeout function + * @note This function must be called when the LPTIM instance is disabled. + * @note The first trigger event will start the timer, any successive trigger + * event will reset the counter and the timer will restart. + * @note The timeout value corresponds to the compare value; if no trigger + * occurs within the expected time frame, the MCU is waked-up by the + * compare match event. + * @rmtoll CFGR TIMOUT LL_LPTIM_EnableTimeout + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_EnableTimeout(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT); +} + +/** + * @brief Disable the timeout function + * @note This function must be called when the LPTIM instance is disabled. + * @note A trigger event arriving when the timer is already started will be + * ignored. + * @rmtoll CFGR TIMOUT LL_LPTIM_DisableTimeout + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_DisableTimeout(LPTIM_TypeDef *LPTIMx) +{ + CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT); +} + +/** + * @brief Indicate whether the timeout function is enabled. + * @rmtoll CFGR TIMOUT LL_LPTIM_IsEnabledTimeout + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(const LPTIM_TypeDef *LPTIMx) +{ + return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT) ? 1UL : 0UL)); +} + +/** + * @brief Start the LPTIM counter + * @note This function must be called when the LPTIM instance is disabled. + * @rmtoll CFGR TRIGEN LL_LPTIM_TrigSw + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_TrigSw(LPTIM_TypeDef *LPTIMx) +{ + CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN); +} + +/** + * @brief Configure the external trigger used as a trigger event for the LPTIM. + * @note This function must be called when the LPTIM instance is disabled. + * @note An internal clock source must be present when a digital filter is + * required for the trigger. + * @rmtoll CFGR TRIGSEL LL_LPTIM_ConfigTrigger\n + * CFGR TRGFLT LL_LPTIM_ConfigTrigger\n + * CFGR TRIGEN LL_LPTIM_ConfigTrigger + * @param LPTIMx Low-Power Timer instance + * @param Source This parameter can be one of the following values: + * @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO + * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA + * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB + * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1 + * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2 + * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1 (*) + * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2 (*) + * + * (*) Value not defined in all devices. \n + * + * @param Filter This parameter can be one of the following values: + * @arg @ref LL_LPTIM_TRIG_FILTER_NONE + * @arg @ref LL_LPTIM_TRIG_FILTER_2 + * @arg @ref LL_LPTIM_TRIG_FILTER_4 + * @arg @ref LL_LPTIM_TRIG_FILTER_8 + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING + * @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING + * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_ConfigTrigger(LPTIM_TypeDef *LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity) +{ + MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL | LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGEN, Source | Filter | Polarity); +} + +/** + * @brief Get actual external trigger source. + * @rmtoll CFGR TRIGSEL LL_LPTIM_GetTriggerSource + * @param LPTIMx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO + * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA + * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB + * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1 + * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2 + * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1 (*) + * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2 (*) + * + * (*) Value not defined in all devices. \n + * + */ +__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(const LPTIM_TypeDef *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL)); +} + +/** + * @brief Get actual external trigger filter. + * @rmtoll CFGR TRGFLT LL_LPTIM_GetTriggerFilter + * @param LPTIMx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPTIM_TRIG_FILTER_NONE + * @arg @ref LL_LPTIM_TRIG_FILTER_2 + * @arg @ref LL_LPTIM_TRIG_FILTER_4 + * @arg @ref LL_LPTIM_TRIG_FILTER_8 + */ +__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(const LPTIM_TypeDef *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRGFLT)); +} + +/** + * @brief Get actual external trigger polarity. + * @rmtoll CFGR TRIGEN LL_LPTIM_GetTriggerPolarity + * @param LPTIMx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING + * @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING + * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING + */ +__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerPolarity(const LPTIM_TypeDef *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN)); +} + +/** + * @} + */ + +/** @defgroup LPTIM_LL_EF_Clock_Configuration Clock Configuration + * @{ + */ + +/** + * @brief Set the source of the clock used by the LPTIM instance. + * @note This function must be called when the LPTIM instance is disabled. + * @rmtoll CFGR CKSEL LL_LPTIM_SetClockSource + * @param LPTIMx Low-Power Timer instance + * @param ClockSource This parameter can be one of the following values: + * @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL + * @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_SetClockSource(LPTIM_TypeDef *LPTIMx, uint32_t ClockSource) +{ + MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKSEL, ClockSource); +} + +/** + * @brief Get actual LPTIM instance clock source. + * @rmtoll CFGR CKSEL LL_LPTIM_GetClockSource + * @param LPTIMx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL + * @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL + */ +__STATIC_INLINE uint32_t LL_LPTIM_GetClockSource(const LPTIM_TypeDef *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKSEL)); +} + +/** + * @brief Configure the active edge or edges used by the counter when + the LPTIM is clocked by an external clock source. + * @note This function must be called when the LPTIM instance is disabled. + * @note When both external clock signal edges are considered active ones, + * the LPTIM must also be clocked by an internal clock source with a + * frequency equal to at least four times the external clock frequency. + * @note An internal clock source must be present when a digital filter is + * required for external clock. + * @rmtoll CFGR CKFLT LL_LPTIM_ConfigClock\n + * CFGR CKPOL LL_LPTIM_ConfigClock + * @param LPTIMx Low-Power Timer instance + * @param ClockFilter This parameter can be one of the following values: + * @arg @ref LL_LPTIM_CLK_FILTER_NONE + * @arg @ref LL_LPTIM_CLK_FILTER_2 + * @arg @ref LL_LPTIM_CLK_FILTER_4 + * @arg @ref LL_LPTIM_CLK_FILTER_8 + * @param ClockPolarity This parameter can be one of the following values: + * @arg @ref LL_LPTIM_CLK_POLARITY_RISING + * @arg @ref LL_LPTIM_CLK_POLARITY_FALLING + * @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_ConfigClock(LPTIM_TypeDef *LPTIMx, uint32_t ClockFilter, uint32_t ClockPolarity) +{ + MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKFLT | LPTIM_CFGR_CKPOL, ClockFilter | ClockPolarity); +} + +/** + * @brief Get actual clock polarity + * @rmtoll CFGR CKPOL LL_LPTIM_GetClockPolarity + * @param LPTIMx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPTIM_CLK_POLARITY_RISING + * @arg @ref LL_LPTIM_CLK_POLARITY_FALLING + * @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING + */ +__STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(const LPTIM_TypeDef *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL)); +} + +/** + * @brief Get actual clock digital filter + * @rmtoll CFGR CKFLT LL_LPTIM_GetClockFilter + * @param LPTIMx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPTIM_CLK_FILTER_NONE + * @arg @ref LL_LPTIM_CLK_FILTER_2 + * @arg @ref LL_LPTIM_CLK_FILTER_4 + * @arg @ref LL_LPTIM_CLK_FILTER_8 + */ +__STATIC_INLINE uint32_t LL_LPTIM_GetClockFilter(const LPTIM_TypeDef *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKFLT)); +} + +/** + * @} + */ + +/** @defgroup LPTIM_LL_EF_Encoder_Mode Encoder Mode + * @{ + */ + +/** + * @brief Configure the encoder mode. + * @note This function must be called when the LPTIM instance is disabled. + * @rmtoll CFGR CKPOL LL_LPTIM_SetEncoderMode + * @param LPTIMx Low-Power Timer instance + * @param EncoderMode This parameter can be one of the following values: + * @arg @ref LL_LPTIM_ENCODER_MODE_RISING + * @arg @ref LL_LPTIM_ENCODER_MODE_FALLING + * @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_SetEncoderMode(LPTIM_TypeDef *LPTIMx, uint32_t EncoderMode) +{ + MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKPOL, EncoderMode); +} + +/** + * @brief Get actual encoder mode. + * @rmtoll CFGR CKPOL LL_LPTIM_GetEncoderMode + * @param LPTIMx Low-Power Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPTIM_ENCODER_MODE_RISING + * @arg @ref LL_LPTIM_ENCODER_MODE_FALLING + * @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING + */ +__STATIC_INLINE uint32_t LL_LPTIM_GetEncoderMode(const LPTIM_TypeDef *LPTIMx) +{ + return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL)); +} + +/** + * @brief Enable the encoder mode + * @note This function must be called when the LPTIM instance is disabled. + * @note In this mode the LPTIM instance must be clocked by an internal clock + * source. Also, the prescaler division ratio must be equal to 1. + * @note LPTIM instance must be configured in continuous mode prior enabling + * the encoder mode. + * @rmtoll CFGR ENC LL_LPTIM_EnableEncoderMode + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_EnableEncoderMode(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC); +} + +/** + * @brief Disable the encoder mode + * @note This function must be called when the LPTIM instance is disabled. + * @rmtoll CFGR ENC LL_LPTIM_DisableEncoderMode + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef *LPTIMx) +{ + CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC); +} + +/** + * @brief Indicates whether the LPTIM operates in encoder mode. + * @rmtoll CFGR ENC LL_LPTIM_IsEnabledEncoderMode + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(const LPTIM_TypeDef *LPTIMx) +{ + return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC) ? 1UL : 0UL)); +} + +/** + * @} + */ + +/** @defgroup LPTIM_LL_EF_FLAG_Management FLAG Management + * @{ + */ + +/** + * @brief Clear the compare match flag for channel 1 (CC1CF) + * @rmtoll ICR CC1CF LL_LPTIM_ClearFlag_CC1 + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_ClearFlag_CC1(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->ICR, LPTIM_ICR_CC1CF); +} + +/** + * @brief Inform application whether a capture/compare interrupt has occurred for channel 1. + * @rmtoll ISR CC1IF LL_LPTIM_IsActiveFlag_CC1 + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC1(const LPTIM_TypeDef *LPTIMx) +{ + return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CC1IF) == LPTIM_ISR_CC1IF) ? 1UL : 0UL)); +} + +/** + * @brief Clear the compare match flag for channel 2 (CC2CF) + * @rmtoll ICR CC2CF LL_LPTIM_ClearFlag_CC2 + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_ClearFlag_CC2(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->ICR, LPTIM_ICR_CC2CF); +} + +/** + * @brief Inform application whether a capture/compare interrupt has occurred for channel 2. + * @rmtoll ISR CC2IF LL_LPTIM_IsActiveFlag_CC2 + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC2(const LPTIM_TypeDef *LPTIMx) +{ + return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CC2IF) == LPTIM_ISR_CC2IF) ? 1UL : 0UL)); +} + +/** + * @brief Clear the Capture/Compare 1 over-capture flag for channel 1 (CC1OCF) + * @rmtoll ICR CC1OCF LL_LPTIM_ClearFlag_CC1O + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_ClearFlag_CC1O(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->ICR, LPTIM_ICR_CC1OCF); +} + +/** + * @brief Inform application whether a Capture/Compare 1 over-capture has occurred for channel 1. + * @rmtoll ISR CC1OF LL_LPTIM_IsActiveFlag_CC1O + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC1O(const LPTIM_TypeDef *LPTIMx) +{ + return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CC1OF) == LPTIM_ISR_CC1OF) ? 1UL : 0UL)); +} + +/** + * @brief Clear the Capture/Compare 2 over-capture flag for channel 2 (CC2OCF) + * @rmtoll ICR CC2OCF LL_LPTIM_ClearFlag_CC2O + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_ClearFlag_CC2O(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->ICR, LPTIM_ICR_CC2OCF); +} + +/** + * @brief Inform application whether a Capture/Compare 2 over-capture has occurred for channel 2. + * @rmtoll ISR CC2OF LL_LPTIM_IsActiveFlag_CC2O + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CC2O(const LPTIM_TypeDef *LPTIMx) +{ + return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CC2OF) == LPTIM_ISR_CC2OF) ? 1UL : 0UL)); +} +/** + * @brief Clear the autoreload match flag (ARRMCF) + * @rmtoll ICR ARRMCF LL_LPTIM_ClearFlag_ARRM + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_ClearFlag_ARRM(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARRMCF); +} + +/** + * @brief Inform application whether a autoreload match interrupt has occurred. + * @rmtoll ISR ARRM LL_LPTIM_IsActiveFlag_ARRM + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(const LPTIM_TypeDef *LPTIMx) +{ + return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM) ? 1UL : 0UL)); +} + +/** + * @brief Clear the external trigger valid edge flag(EXTTRIGCF). + * @rmtoll ICR EXTTRIGCF LL_LPTIM_ClearFlag_EXTTRIG + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->ICR, LPTIM_ICR_EXTTRIGCF); +} + +/** + * @brief Inform application whether a valid edge on the selected external trigger input has occurred. + * @rmtoll ISR EXTTRIG LL_LPTIM_IsActiveFlag_EXTTRIG + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(const LPTIM_TypeDef *LPTIMx) +{ + return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG) ? 1UL : 0UL)); +} + +/** + * @brief Clear the compare register update interrupt flag (CMP1OKCF). + * @rmtoll ICR CMP1OKCF LL_LPTIM_ClearFlag_CMP1OK + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_ClearFlag_CMP1OK(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMP1OKCF); +} + +/** + * @brief Informs application whether the APB bus write operation to the LPTIMx_CCR1 register has been successfully + completed. If so, a new one can be initiated. + * @rmtoll ISR CMP1OK LL_LPTIM_IsActiveFlag_CMP1OK + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMP1OK(const LPTIM_TypeDef *LPTIMx) +{ + return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMP1OK) == LPTIM_ISR_CMP1OK) ? 1UL : 0UL)); +} + +/** + * @brief Clear the compare register update interrupt flag (CMP2OKCF). + * @rmtoll ICR CMP2OKCF LL_LPTIM_ClearFlag_CMP2OK + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_ClearFlag_CMP2OK(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMP2OKCF); +} + +/** + * @brief Informs application whether the APB bus write operation to the LPTIMx_CCR2 register has been successfully + completed. If so, a new one can be initiated. + * @rmtoll ISR CMP2OK LL_LPTIM_IsActiveFlag_CMP2OK + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMP2OK(const LPTIM_TypeDef *LPTIMx) +{ + return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMP2OK) == LPTIM_ISR_CMP2OK) ? 1UL : 0UL)); +} + +/** + * @brief Clear the interrupt register update interrupt flag (DIEROKCF). + * @rmtoll ICR DIEROKCF LL_LPTIM_ClearFlag_DIEROK + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_ClearFlag_DIEROK(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->ICR, LPTIM_ICR_DIEROKCF); +} + +/** + * @brief Informs application whether the APB bus write operation to the LPTIMx_DIER register has been successfully + completed. If so, a new one can be initiated. + * @rmtoll ISR DIEROK LL_LPTIM_IsActiveFlag_DIEROK + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DIEROK(const LPTIM_TypeDef *LPTIMx) +{ + return ((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DIEROK) == (LPTIM_ISR_DIEROK)) ? 1UL : 0UL); +} + +/** + * @brief Clear the autoreload register update interrupt flag (ARROKCF). + * @rmtoll ICR ARROKCF LL_LPTIM_ClearFlag_ARROK + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARROKCF); +} + +/** + * @brief Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully + completed. If so, a new one can be initiated. + * @rmtoll ISR ARROK LL_LPTIM_IsActiveFlag_ARROK + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(const LPTIM_TypeDef *LPTIMx) +{ + return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK) ? 1UL : 0UL)); +} + +/** + * @brief Clear the counter direction change to up interrupt flag (UPCF). + * @rmtoll ICR UPCF LL_LPTIM_ClearFlag_UP + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->ICR, LPTIM_ICR_UPCF); +} + +/** + * @brief Informs the application whether the counter direction has changed from down to up (when the LPTIM instance + operates in encoder mode). + * @rmtoll ISR UP LL_LPTIM_IsActiveFlag_UP + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(const LPTIM_TypeDef *LPTIMx) +{ + return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP) ? 1UL : 0UL)); +} + +/** + * @brief Clear the counter direction change to down interrupt flag (DOWNCF). + * @rmtoll ICR DOWNCF LL_LPTIM_ClearFlag_DOWN + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->ICR, LPTIM_ICR_DOWNCF); +} + +/** + * @brief Informs the application whether the counter direction has changed from up to down (when the LPTIM instance + operates in encoder mode). + * @rmtoll ISR DOWN LL_LPTIM_IsActiveFlag_DOWN + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(const LPTIM_TypeDef *LPTIMx) +{ + return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN) ? 1UL : 0UL)); +} + +/** + * @brief Clear the repetition register update interrupt flag (REPOKCF). + * @rmtoll ICR REPOKCF LL_LPTIM_ClearFlag_REPOK + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_ClearFlag_REPOK(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->ICR, LPTIM_ICR_REPOKCF); +} + +/** + * @brief Informs application whether the APB bus write operation to the LPTIMx_RCR register has been successfully + completed; If so, a new one can be initiated. + * @rmtoll ISR REPOK LL_LPTIM_IsActiveFlag_REPOK + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_REPOK(const LPTIM_TypeDef *LPTIMx) +{ + return ((READ_BIT(LPTIMx->ISR, LPTIM_ISR_REPOK) == (LPTIM_ISR_REPOK)) ? 1UL : 0UL); +} + +/** + * @brief Clear the update event flag (UECF). + * @rmtoll ICR UECF LL_LPTIM_ClearFlag_UE + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_ClearFlag_UE(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->ICR, LPTIM_ICR_UECF); +} + +/** + * @brief Informs application whether the LPTIMx update event has occurred. + * @rmtoll ISR UE LL_LPTIM_IsActiveFlag_UE + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UE(const LPTIM_TypeDef *LPTIMx) +{ + return ((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UE) == (LPTIM_ISR_UE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup LPTIM_LL_EF_IT_Management Interrupt Management + * @{ + */ +/** + * @brief Enable capture/compare 1 interrupt (CC1IE). + * @rmtoll DIER CC1IE LL_LPTIM_EnableIT_CC1 + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_EnableIT_CC1(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC1IE); +} + +/** + * @brief Disable capture/compare 1 interrupt (CC1IE). + * @rmtoll DIER CC1IE LL_LPTIM_DisableIT_CC1 + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_DisableIT_CC1(LPTIM_TypeDef *LPTIMx) +{ + CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC1IE); +} + +/** + * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled. + * @rmtoll DIER CC1IE LL_LPTIM_IsEnabledIT_CC1 + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC1(const LPTIM_TypeDef *LPTIMx) +{ + return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC1IE) == LPTIM_DIER_CC1IE) ? 1UL : 0UL)); +} + +/** + * @brief Enable capture/compare 1 interrupt (CC2IE). + * @rmtoll DIER CC2IE LL_LPTIM_EnableIT_CC2 + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_EnableIT_CC2(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC2IE); +} + +/** + * @brief Disable capture/compare 2 interrupt (CC2IE). + * @rmtoll DIER CC2IE LL_LPTIM_DisableIT_CC2 + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_DisableIT_CC2(LPTIM_TypeDef *LPTIMx) +{ + CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC2IE); +} + +/** + * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled. + * @rmtoll DIER CC2IE LL_LPTIM_IsEnabledIT_CC2 + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC2(const LPTIM_TypeDef *LPTIMx) +{ + return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC2IE) == LPTIM_DIER_CC2IE) ? 1UL : 0UL)); +} + +/** + * @brief Enable capture/compare 1 over-capture interrupt (CC1OIE). + * @rmtoll DIER CC1OIE LL_LPTIM_EnableIT_CC1O + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_EnableIT_CC1O(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC1OIE); +} + +/** + * @brief Disable capture/compare 1 over-capture interrupt (CC1OIE). + * @rmtoll DIER CC1OIE LL_LPTIM_DisableIT_CC1O + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_DisableIT_CC1O(LPTIM_TypeDef *LPTIMx) +{ + CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC1OIE); +} + +/** + * @brief Indicates whether the capture/compare 1 over-capture interrupt (CC1OIE) is enabled. + * @rmtoll DIER CC1OIE LL_LPTIM_IsEnabledIT_CC1O + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC1O(const LPTIM_TypeDef *LPTIMx) +{ + return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC1OIE) == LPTIM_DIER_CC1OIE) ? 1UL : 0UL)); +} + +/** + * @brief Enable capture/compare 1 over-capture interrupt (CC2OIE). + * @rmtoll DIER CC2OIE LL_LPTIM_EnableIT_CC2O + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_EnableIT_CC2O(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC2OIE); +} + +/** + * @brief Disable capture/compare 1 over-capture interrupt (CC2OIE). + * @rmtoll DIER CC2OIE LL_LPTIM_DisableIT_CC2O + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_DisableIT_CC2O(LPTIM_TypeDef *LPTIMx) +{ + CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC2OIE); +} + +/** + * @brief Indicates whether the capture/compare 2 over-capture interrupt (CC2OIE) is enabled. + * @rmtoll DIER CC2OIE LL_LPTIM_IsEnabledIT_CC2O + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CC2O(const LPTIM_TypeDef *LPTIMx) +{ + return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC2OIE) == LPTIM_DIER_CC2OIE) ? 1UL : 0UL)); +} + +/** + * @brief Enable autoreload match interrupt (ARRMIE). + * @rmtoll DIER ARRMIE LL_LPTIM_EnableIT_ARRM + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_EnableIT_ARRM(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->DIER, LPTIM_DIER_ARRMIE); +} + +/** + * @brief Disable autoreload match interrupt (ARRMIE). + * @rmtoll DIER ARRMIE LL_LPTIM_DisableIT_ARRM + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef *LPTIMx) +{ + CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_ARRMIE); +} + +/** + * @brief Indicates whether the autoreload match interrupt (ARRMIE) is enabled. + * @rmtoll DIER ARRMIE LL_LPTIM_IsEnabledIT_ARRM + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(const LPTIM_TypeDef *LPTIMx) +{ + return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_ARRMIE) == LPTIM_DIER_ARRMIE) ? 1UL : 0UL)); +} + +/** + * @brief Enable external trigger valid edge interrupt (EXTTRIGIE). + * @rmtoll DIER EXTTRIGIE LL_LPTIM_EnableIT_EXTTRIG + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_EnableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->DIER, LPTIM_DIER_EXTTRIGIE); +} + +/** + * @brief Disable external trigger valid edge interrupt (EXTTRIGIE). + * @rmtoll DIER EXTTRIGIE LL_LPTIM_DisableIT_EXTTRIG + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx) +{ + CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_EXTTRIGIE); +} + +/** + * @brief Indicates external trigger valid edge interrupt (EXTTRIGIE) is enabled. + * @rmtoll DIER EXTTRIGIE LL_LPTIM_IsEnabledIT_EXTTRIG + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(const LPTIM_TypeDef *LPTIMx) +{ + return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_EXTTRIGIE) == LPTIM_DIER_EXTTRIGIE) ? 1UL : 0UL)); +} + +/** + * @brief Enable compare register write completed interrupt (CMP1OKIE). + * @rmtoll IER CMP1OKIE LL_LPTIM_EnableIT_CMP1OK + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_EnableIT_CMP1OK(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->DIER, LPTIM_DIER_CMP1OKIE); +} + +/** + * @brief Disable compare register write completed interrupt (CMP1OKIE). + * @rmtoll IER CMPO1KIE LL_LPTIM_DisableIT_CMP1OK + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_DisableIT_CMP1OK(LPTIM_TypeDef *LPTIMx) +{ + CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CMP1OKIE); +} + +/** + * @brief Indicates whether the compare register write completed interrupt (CMP1OKIE) is enabled. + * @rmtoll IER CMP1OKIE LL_LPTIM_IsEnabledIT_CMP1OK + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMP1OK(const LPTIM_TypeDef *LPTIMx) +{ + return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CMP1OKIE) == LPTIM_DIER_CMP1OKIE) ? 1UL : 0UL)); +} + +/** + * @brief Enable compare register write completed interrupt (CMP2OKIE). + * @rmtoll IER CMP2OKIE LL_LPTIM_EnableIT_CMP2OK + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_EnableIT_CMP2OK(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->DIER, LPTIM_DIER_CMP2OKIE); +} + +/** + * @brief Disable compare register write completed interrupt (CMP2OKIE). + * @rmtoll IER CMP2OKIE LL_LPTIM_DisableIT_CMP2OK + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_DisableIT_CMP2OK(LPTIM_TypeDef *LPTIMx) +{ + CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CMP2OKIE); +} + +/** + * @brief Indicates whether the compare register write completed interrupt (CMP2OKIE) is enabled. + * @rmtoll IER CMP2OKIE LL_LPTIM_IsEnabledIT_CMP2OK + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMP2OK(const LPTIM_TypeDef *LPTIMx) +{ + return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CMP2OKIE) == LPTIM_DIER_CMP2OKIE) ? 1UL : 0UL)); +} + +/** + * @brief Enable autoreload register write completed interrupt (ARROKIE). + * @rmtoll DIER ARROKIE LL_LPTIM_EnableIT_ARROK + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_EnableIT_ARROK(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->DIER, LPTIM_DIER_ARROKIE); +} + +/** + * @brief Disable autoreload register write completed interrupt (ARROKIE). + * @rmtoll DIER ARROKIE LL_LPTIM_DisableIT_ARROK + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef *LPTIMx) +{ + CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_ARROKIE); +} + +/** + * @brief Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled. + * @rmtoll DIER ARROKIE LL_LPTIM_IsEnabledIT_ARROK + * @param LPTIMx Low-Power Timer instance + * @retval State of bit(1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(const LPTIM_TypeDef *LPTIMx) +{ + return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_ARROKIE) == LPTIM_DIER_ARROKIE) ? 1UL : 0UL)); +} + +/** + * @brief Enable direction change to up interrupt (UPIE). + * @rmtoll DIER UPIE LL_LPTIM_EnableIT_UP + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_EnableIT_UP(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->DIER, LPTIM_DIER_UPIE); +} + +/** + * @brief Disable direction change to up interrupt (UPIE). + * @rmtoll DIER UPIE LL_LPTIM_DisableIT_UP + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_DisableIT_UP(LPTIM_TypeDef *LPTIMx) +{ + CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_UPIE); +} + +/** + * @brief Indicates whether the direction change to up interrupt (UPIE) is enabled. + * @rmtoll DIER UPIE LL_LPTIM_IsEnabledIT_UP + * @param LPTIMx Low-Power Timer instance + * @retval State of bit(1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(const LPTIM_TypeDef *LPTIMx) +{ + return (((READ_BIT(LPTIMx->DIER, LPTIM_DIER_UPIE) == LPTIM_DIER_UPIE) ? 1UL : 0UL)); +} + +/** + * @brief Enable direction change to down interrupt (DOWNIE). + * @rmtoll DIER DOWNIE LL_LPTIM_EnableIT_DOWN + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_EnableIT_DOWN(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->DIER, LPTIM_DIER_DOWNIE); +} + +/** + * @brief Disable direction change to down interrupt (DOWNIE). + * @rmtoll DIER DOWNIE LL_LPTIM_DisableIT_DOWN + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef *LPTIMx) +{ + CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_DOWNIE); +} + +/** + * @brief Indicates whether the direction change to down interrupt (DOWNIE) is enabled. + * @rmtoll DIER DOWNIE LL_LPTIM_IsEnabledIT_DOWN + * @param LPTIMx Low-Power Timer instance + * @retval State of bit(1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(const LPTIM_TypeDef *LPTIMx) +{ + return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_DOWNIE) == LPTIM_DIER_DOWNIE) ? 1UL : 0UL); +} + +/** + * @brief Enable repetition register update successfully completed interrupt (REPOKIE). + * @rmtoll DIER REPOKIE LL_LPTIM_EnableIT_REPOK + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_EnableIT_REPOK(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->DIER, LPTIM_DIER_REPOKIE); +} + +/** + * @brief Disable repetition register update successfully completed interrupt (REPOKIE). + * @rmtoll DIER REPOKIE LL_LPTIM_DisableIT_REPOK + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_DisableIT_REPOK(LPTIM_TypeDef *LPTIMx) +{ + CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_REPOKIE); +} + +/** + * @brief Indicates whether the repetition register update successfully completed interrupt (REPOKIE) is enabled. + * @rmtoll DIER REPOKIE LL_LPTIM_IsEnabledIT_REPOK + * @param LPTIMx Low-Power Timer instance + * @retval State of bit(1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_REPOK(const LPTIM_TypeDef *LPTIMx) +{ + return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_REPOKIE) == (LPTIM_DIER_REPOKIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable update event interrupt (UEIE). + * @rmtoll DIER UEIE LL_LPTIM_EnableIT_UE + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_EnableIT_UE(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->DIER, LPTIM_DIER_UEIE); +} + +/** + * @brief Disable update event interrupt (UEIE). + * @rmtoll DIER UEIE LL_LPTIM_DisableIT_UE + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_DisableIT_UE(LPTIM_TypeDef *LPTIMx) +{ + CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_UEIE); +} + +/** + * @brief Indicates whether the update event interrupt (UEIE) is enabled. + * @rmtoll DIER UEIE LL_LPTIM_IsEnabledIT_UE + * @param LPTIMx Low-Power Timer instance + *@ retval State of bit(1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UE(const LPTIM_TypeDef *LPTIMx) +{ + return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_UEIE) == (LPTIM_DIER_UEIE)) ? 1UL : 0UL); +} +/** + * @} + */ + + +/** @defgroup TIM_LL_EF_DMA_Management DMA Management + * @{ + */ +/** + * @brief Enable update DMA request. + * @rmtoll DIER UEDE LL_LPTIM_EnableDMAReq_UPDATE + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_EnableDMAReq_UPDATE(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->DIER, LPTIM_DIER_UEDE); +} + +/** + * @brief Disable update DMA request. + * @rmtoll DIER UEDE LL_LPTIM_DisableDMAReq_UPDATE + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_DisableDMAReq_UPDATE(LPTIM_TypeDef *LPTIMx) +{ + CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_UEDE); +} + +/** + * @brief Indicates whether the update DMA request is enabled. + * @rmtoll DIER UEDE LL_LPTIM_IsEnabledDMAReq_UPDATE + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledDMAReq_UPDATE(const LPTIM_TypeDef *LPTIMx) +{ + return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_UEDE) == (LPTIM_DIER_UEDE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 1 DMA request (CC1DE). + * @rmtoll DIER CC1DE LL_LPTIM_EnableDMAReq_CC1 + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_EnableDMAReq_CC1(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC1DE); +} + +/** + * @brief Disable capture/compare 1 DMA request (CC1DE). + * @rmtoll DIER CC1DE LL_LPTIM_DisableDMAReq_CC1 + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_DisableDMAReq_CC1(LPTIM_TypeDef *LPTIMx) +{ + CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC1DE); +} + +/** + * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled. + * @rmtoll DIER CC1DE LL_LPTIM_IsEnabledDMAReq_CC1 + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledDMAReq_CC1(const LPTIM_TypeDef *LPTIMx) +{ + return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC1DE) == (LPTIM_DIER_CC1DE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 2 DMA request (CC2DE). + * @rmtoll DIER CC2DE LL_LPTIM_EnableDMAReq_CC2 + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_EnableDMAReq_CC2(LPTIM_TypeDef *LPTIMx) +{ + SET_BIT(LPTIMx->DIER, LPTIM_DIER_CC2DE); +} + +/** + * @brief Disable capture/compare 2 DMA request (CC2DE). + * @rmtoll DIER CC2DE LL_LPTIM_DisableDMAReq_CC2 + * @param LPTIMx Low-Power Timer instance + * @retval None + */ +__STATIC_INLINE void LL_LPTIM_DisableDMAReq_CC2(LPTIM_TypeDef *LPTIMx) +{ + CLEAR_BIT(LPTIMx->DIER, LPTIM_DIER_CC2DE); +} + +/** + * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled. + * @rmtoll DIER CC2DE LL_LPTIM_IsEnabledDMAReq_CC2 + * @param LPTIMx Low-Power Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledDMAReq_CC2(const LPTIM_TypeDef *LPTIMx) +{ + return ((READ_BIT(LPTIMx->DIER, LPTIM_DIER_CC2DE) == (LPTIM_DIER_CC2DE)) ? 1UL : 0UL); +} + +/** + * @} + */ +/** + * @} + */ + +/** + * @} + */ + +#endif /* LPTIM1 || LPTIM2 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WBAxx_LL_LPTIM_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_lpuart.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_lpuart.h new file mode 100644 index 0000000000..e0985dafb6 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_lpuart.h @@ -0,0 +1,2744 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_ll_lpuart.h + * @author MCD Application Team + * @brief Header file of LPUART LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_LL_LPUART_H +#define STM32WBAxx_LL_LPUART_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx.h" + +/** @addtogroup STM32WBAxx_LL_Driver + * @{ + */ + +#if defined (LPUART1) + +/** @defgroup LPUART_LL LPUART + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup LPUART_LL_Private_Variables LPUART Private Variables + * @{ + */ +/* Array used to get the LPUART prescaler division decimal values versus @ref LPUART_LL_EC_PRESCALER values */ +static const uint16_t LPUART_PRESCALER_TAB[] = +{ + (uint16_t)1, + (uint16_t)2, + (uint16_t)4, + (uint16_t)6, + (uint16_t)8, + (uint16_t)10, + (uint16_t)12, + (uint16_t)16, + (uint16_t)32, + (uint16_t)64, + (uint16_t)128, + (uint16_t)256 +}; +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup LPUART_LL_Private_Constants LPUART Private Constants + * @{ + */ +/* Defines used in Baud Rate related macros and corresponding register setting computation */ +#define LPUART_LPUARTDIV_FREQ_MUL 256U +#define LPUART_BRR_MASK 0x000FFFFFU +#define LPUART_BRR_MIN_VALUE 0x00000300U +/** + * @} + */ + + +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup LPUART_LL_Private_Macros LPUART Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup LPUART_LL_ES_INIT LPUART Exported Init structures + * @{ + */ + +/** + * @brief LL LPUART Init Structure definition + */ +typedef struct +{ + uint32_t PrescalerValue; /*!< Specifies the Prescaler to compute the communication baud rate. + This parameter can be a value of @ref LPUART_LL_EC_PRESCALER. + + This feature can be modified afterwards using unitary + function @ref LL_LPUART_SetPrescaler().*/ + + uint32_t BaudRate; /*!< This field defines expected LPUART communication baud rate. + + This feature can be modified afterwards using unitary + function @ref LL_LPUART_SetBaudRate().*/ + + uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref LPUART_LL_EC_DATAWIDTH. + + This feature can be modified afterwards using unitary + function @ref LL_LPUART_SetDataWidth().*/ + + uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref LPUART_LL_EC_STOPBITS. + + This feature can be modified afterwards using unitary + function @ref LL_LPUART_SetStopBitsLength().*/ + + uint32_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref LPUART_LL_EC_PARITY. + + This feature can be modified afterwards using unitary + function @ref LL_LPUART_SetParity().*/ + + uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled. + This parameter can be a value of @ref LPUART_LL_EC_DIRECTION. + + This feature can be modified afterwards using unitary + function @ref LL_LPUART_SetTransferDirection().*/ + + uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled. + This parameter can be a value of @ref LPUART_LL_EC_HWCONTROL. + + This feature can be modified afterwards using unitary + function @ref LL_LPUART_SetHWFlowCtrl().*/ + +} LL_LPUART_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup LPUART_LL_Exported_Constants LPUART Exported Constants + * @{ + */ + +/** @defgroup LPUART_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_LPUART_WriteReg function + * @{ + */ +#define LL_LPUART_ICR_PECF USART_ICR_PECF /*!< Parity error clear flag */ +#define LL_LPUART_ICR_FECF USART_ICR_FECF /*!< Framing error clear flag */ +#define LL_LPUART_ICR_NCF USART_ICR_NECF /*!< Noise error detected clear flag */ +#define LL_LPUART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error clear flag */ +#define LL_LPUART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected clear flag */ +#define LL_LPUART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete clear flag */ +#define LL_LPUART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS clear flag */ +#define LL_LPUART_ICR_CMCF USART_ICR_CMCF /*!< Character match clear flag */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_LPUART_ReadReg function + * @{ + */ +#define LL_LPUART_ISR_PE USART_ISR_PE /*!< Parity error flag */ +#define LL_LPUART_ISR_FE USART_ISR_FE /*!< Framing error flag */ +#define LL_LPUART_ISR_NE USART_ISR_NE /*!< Noise detected flag */ +#define LL_LPUART_ISR_ORE USART_ISR_ORE /*!< Overrun error flag */ +#define LL_LPUART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detected flag */ +#define LL_LPUART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE /*!< Read data register or RX FIFO not empty flag */ +#define LL_LPUART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */ +#define LL_LPUART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF /*!< Transmit data register empty or TX FIFO Not Full flag*/ +#define LL_LPUART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */ +#define LL_LPUART_ISR_CTS USART_ISR_CTS /*!< CTS flag */ +#define LL_LPUART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */ +#define LL_LPUART_ISR_CMF USART_ISR_CMF /*!< Character match flag */ +#define LL_LPUART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */ +#define LL_LPUART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup from Mute mode flag */ +#define LL_LPUART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable acknowledge flag */ +#define LL_LPUART_ISR_REACK USART_ISR_REACK /*!< Receive enable acknowledge flag */ +#define LL_LPUART_ISR_TXFE USART_ISR_TXFE /*!< TX FIFO empty flag */ +#define LL_LPUART_ISR_RXFF USART_ISR_RXFF /*!< RX FIFO full flag */ +#define LL_LPUART_ISR_RXFT USART_ISR_RXFT /*!< RX FIFO threshold flag */ +#define LL_LPUART_ISR_TXFT USART_ISR_TXFT /*!< TX FIFO threshold flag */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_LPUART_ReadReg and LL_LPUART_WriteReg functions + * @{ + */ +#define LL_LPUART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */ +#define LL_LPUART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE /*!< Read data register and RXFIFO not empty + interrupt enable */ +#define LL_LPUART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */ +#define LL_LPUART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE /*!< Transmit data register empty and TX FIFO + not full interrupt enable */ +#define LL_LPUART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */ +#define LL_LPUART_CR1_CMIE USART_CR1_CMIE /*!< Character match interrupt enable */ +#define LL_LPUART_CR1_TXFEIE USART_CR1_TXFEIE /*!< TX FIFO empty interrupt enable */ +#define LL_LPUART_CR1_RXFFIE USART_CR1_RXFFIE /*!< RX FIFO full interrupt enable */ +#define LL_LPUART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */ +#define LL_LPUART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */ +#define LL_LPUART_CR3_TXFTIE USART_CR3_TXFTIE /*!< TX FIFO threshold interrupt enable */ +#define LL_LPUART_CR3_RXFTIE USART_CR3_RXFTIE /*!< RX FIFO threshold interrupt enable */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_FIFOTHRESHOLD FIFO Threshold + * @{ + */ +#define LL_LPUART_FIFOTHRESHOLD_1_8 0x00000000U /*!< FIFO reaches 1/8 of its depth */ +#define LL_LPUART_FIFOTHRESHOLD_1_4 0x00000001U /*!< FIFO reaches 1/4 of its depth */ +#define LL_LPUART_FIFOTHRESHOLD_1_2 0x00000002U /*!< FIFO reaches 1/2 of its depth */ +#define LL_LPUART_FIFOTHRESHOLD_3_4 0x00000003U /*!< FIFO reaches 3/4 of its depth */ +#define LL_LPUART_FIFOTHRESHOLD_7_8 0x00000004U /*!< FIFO reaches 7/8 of its depth */ +#define LL_LPUART_FIFOTHRESHOLD_8_8 0x00000005U /*!< FIFO becomes empty for TX and full for RX */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_DIRECTION Direction + * @{ + */ +#define LL_LPUART_DIRECTION_NONE 0x00000000U /*!< Transmitter and Receiver are disabled */ +#define LL_LPUART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */ +#define LL_LPUART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */ +#define LL_LPUART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_PARITY Parity Control + * @{ + */ +#define LL_LPUART_PARITY_NONE 0x00000000U /*!< Parity control disabled */ +#define LL_LPUART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */ +#define LL_LPUART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_WAKEUP Wakeup + * @{ + */ +#define LL_LPUART_WAKEUP_IDLELINE 0x00000000U /*!< LPUART wake up from Mute mode on Idle Line */ +#define LL_LPUART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< LPUART wake up from Mute mode on Address Mark */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_DATAWIDTH Datawidth + * @{ + */ +#define LL_LPUART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */ +#define LL_LPUART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */ +#define LL_LPUART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_PRESCALER Clock Source Prescaler + * @{ + */ +#define LL_LPUART_PRESCALER_DIV1 0x00000000U /*!< Input clock not divided */ +#define LL_LPUART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock divided by 2 */ +#define LL_LPUART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock divided by 4 */ +#define LL_LPUART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 |\ + USART_PRESC_PRESCALER_0) /*!< Input clock divided by 6 */ +#define LL_LPUART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock divided by 8 */ +#define LL_LPUART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 |\ + USART_PRESC_PRESCALER_0) /*!< Input clock divided by 10 */ +#define LL_LPUART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 |\ + USART_PRESC_PRESCALER_1) /*!< Input clock divided by 12 */ +#define LL_LPUART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 |\ + USART_PRESC_PRESCALER_1 |\ + USART_PRESC_PRESCALER_0) /*!< Input clock divided by 16 */ +#define LL_LPUART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock divided by 32 */ +#define LL_LPUART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 |\ + USART_PRESC_PRESCALER_0) /*!< Input clock divided by 64 */ +#define LL_LPUART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 |\ + USART_PRESC_PRESCALER_1) /*!< Input clock divided by 128 */ +#define LL_LPUART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 |\ + USART_PRESC_PRESCALER_1 |\ + USART_PRESC_PRESCALER_0) /*!< Input clock divided by 256 */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_STOPBITS Stop Bits + * @{ + */ +#define LL_LPUART_STOPBITS_1 0x00000000U /*!< 1 stop bit */ +#define LL_LPUART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_TXRX TX RX Pins Swap + * @{ + */ +#define LL_LPUART_TXRX_STANDARD 0x00000000U /*!< TX/RX pins are used as defined in standard pinout */ +#define LL_LPUART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< TX and RX pins functions are swapped. */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion + * @{ + */ +#define LL_LPUART_RXPIN_LEVEL_STANDARD 0x00000000U /*!< RX pin signal works using the standard logic levels */ +#define LL_LPUART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal values are inverted. */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion + * @{ + */ +#define LL_LPUART_TXPIN_LEVEL_STANDARD 0x00000000U /*!< TX pin signal works using the standard logic levels */ +#define LL_LPUART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal values are inverted. */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_BINARY_LOGIC Binary Data Inversion + * @{ + */ +#define LL_LPUART_BINARY_LOGIC_POSITIVE 0x00000000U /*!< Logical data from the data register are send/received + in positive/direct logic. (1=H, 0=L) */ +#define LL_LPUART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are send/received + in negative/inverse logic. (1=L, 0=H). + The parity bit is also inverted. */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_BITORDER Bit Order + * @{ + */ +#define LL_LPUART_BITORDER_LSBFIRST 0x00000000U /*!< data is transmitted/received with data bit 0 first, + following the start bit */ +#define LL_LPUART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first, + following the start bit */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_ADDRESS_DETECT Address Length Detection + * @{ + */ +#define LL_LPUART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit address detection method selected */ +#define LL_LPUART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_HWCONTROL Hardware Control + * @{ + */ +#define LL_LPUART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */ +#define LL_LPUART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested + when there is space in the receive buffer */ +#define LL_LPUART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted + when the nCTS input is asserted (tied to 0)*/ +#define LL_LPUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_DE_POLARITY Driver Enable Polarity + * @{ + */ +#define LL_LPUART_DE_POLARITY_HIGH 0x00000000U /*!< DE signal is active high */ +#define LL_LPUART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_DMA_REG_DATA DMA Register Data + * @{ + */ +#define LL_LPUART_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */ +#define LL_LPUART_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_AUTOCR_TRIGSEL Autonomous Trigger selection + * @brief LPUART Autonomous Trigger selection + * @{ + */ +#define LL_LPUART_GPDMA1_CH0_TCF_TRG 0U /*!< LPUART GPDMA1 channel0 Internal Trigger */ +#define LL_LPUART_GPDMA1_CH1_TCF_TRG 1U /*!< LPUART GPDMA1 channel1 Internal Trigger */ +#define LL_LPUART_GPDMA1_CH2_TCF_TRG 2U /*!< LPUART GPDMA1 channel2 Internal Trigger */ +#define LL_LPUART_GPDMA1_CH3_TCF_TRG 3U /*!< LPUART GPDMA1 channel3 Internal Trigger */ +#define LL_LPUART_EXTI_LINE6_TRG 4U /*!< LPUART EXTI line 6 Internal Trigger */ +#define LL_LPUART_EXTI_LINE8_TRG 5U /*!< LPUART EXTI line 8 Internal Trigger */ +#define LL_LPUART_LPTIM1_OUT_TRG 6U /*!< LPUART LPTIM1 out Internal Trigger */ +#if defined(COMP12_COMMON) +#define LL_LPUART_COMP1_OUT_TRG 8U /*!< LPUART COMP1 out Internal Trigger */ +#define LL_LPUART_COMP2_OUT_TRG 9U /*!< LPUART COMP2 out Internal Trigger */ +#endif /* COMP12_COMMON */ +#define LL_LPUART_RTC_ALRA_TRG 10U /*!< LPUART RTC alarm Internal Trigger */ +#define LL_LPUART_RTC_WUT_TRG 11U /*!< LPUART RTC wakeup Internal Trigger */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_AUTOCR_TRIGPOL Autonomous Trigger Polarity + * @brief LPUART Autonomous Trigger Polarity + * @{ + */ +#define LL_LPUART_TRIG_POLARITY_RISING 0x00000000U /*!< LPUART triggered on rising edge */ +#define LL_LPUART_TRIG_POLARITY_FALLING USART_AUTOCR_TRIGPOL /*!< LPUART triggered on falling edge */ +/** + * @} + */ +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup LPUART_LL_Exported_Macros LPUART Exported Macros + * @{ + */ + +/** @defgroup LPUART_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in LPUART register + * @param __INSTANCE__ LPUART Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_LPUART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in LPUART register + * @param __INSTANCE__ LPUART Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_LPUART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup LPUART_LL_EM_Exported_Macros_Helper Helper Macros + * @{ + */ + +/** + * @brief Compute LPUARTDIV value according to Peripheral Clock and + * expected Baud Rate (20-bit value of LPUARTDIV is returned) + * @param __PERIPHCLK__ Peripheral Clock frequency used for LPUART Instance + * @param __PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_LPUART_PRESCALER_DIV1 + * @arg @ref LL_LPUART_PRESCALER_DIV2 + * @arg @ref LL_LPUART_PRESCALER_DIV4 + * @arg @ref LL_LPUART_PRESCALER_DIV6 + * @arg @ref LL_LPUART_PRESCALER_DIV8 + * @arg @ref LL_LPUART_PRESCALER_DIV10 + * @arg @ref LL_LPUART_PRESCALER_DIV12 + * @arg @ref LL_LPUART_PRESCALER_DIV16 + * @arg @ref LL_LPUART_PRESCALER_DIV32 + * @arg @ref LL_LPUART_PRESCALER_DIV64 + * @arg @ref LL_LPUART_PRESCALER_DIV128 + * @arg @ref LL_LPUART_PRESCALER_DIV256 + * @param __BAUDRATE__ Baud Rate value to achieve + * @retval LPUARTDIV value to be used for BRR register filling + */ +#define __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (uint32_t)\ + ((((((uint64_t)(__PERIPHCLK__)/(uint64_t)(LPUART_PRESCALER_TAB[(uint16_t)(__PRESCALER__)]))\ + * LPUART_LPUARTDIV_FREQ_MUL) + (uint32_t)((__BAUDRATE__)/2U))/(__BAUDRATE__)) & LPUART_BRR_MASK) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup LPUART_LL_Exported_Functions LPUART Exported Functions + * @{ + */ + +/** @defgroup LPUART_LL_EF_Configuration Configuration functions + * @{ + */ + +/** + * @brief LPUART Enable + * @rmtoll CR1 UE LL_LPUART_Enable + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_Enable(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR1, USART_CR1_UE); +} + +/** + * @brief LPUART Disable + * @note When LPUART is disabled, LPUART prescalers and outputs are stopped immediately, + * and current operations are discarded. The configuration of the LPUART is kept, but all the status + * flags, in the LPUARTx_ISR are set to their default values. + * @note In order to go into low-power mode without generating errors on the line, + * the TE bit must be reset before and the software must wait + * for the TC bit in the LPUART_ISR to be set before resetting the UE bit. + * The DMA requests are also reset when UE = 0 so the DMA channel must + * be disabled before resetting the UE bit. + * @rmtoll CR1 UE LL_LPUART_Disable + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_Disable(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR1, USART_CR1_UE); +} + +/** + * @brief Indicate if LPUART is enabled + * @rmtoll CR1 UE LL_LPUART_IsEnabled + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabled(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL); +} + +/** + * @brief FIFO Mode Enable + * @rmtoll CR1 FIFOEN LL_LPUART_EnableFIFO + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableFIFO(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR1, USART_CR1_FIFOEN); +} + +/** + * @brief FIFO Mode Disable + * @rmtoll CR1 FIFOEN LL_LPUART_DisableFIFO + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableFIFO(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR1, USART_CR1_FIFOEN); +} + +/** + * @brief Indicate if FIFO Mode is enabled + * @rmtoll CR1 FIFOEN LL_LPUART_IsEnabledFIFO + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledFIFO(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL); +} + +/** + * @brief Configure TX FIFO Threshold + * @rmtoll CR3 TXFTCFG LL_LPUART_SetTXFIFOThreshold + * @param LPUARTx LPUART Instance + * @param Threshold This parameter can be one of the following values: + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetTXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold) +{ + ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos); +} + +/** + * @brief Return TX FIFO Threshold Configuration + * @rmtoll CR3 TXFTCFG LL_LPUART_GetTXFIFOThreshold + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 + */ +__STATIC_INLINE uint32_t LL_LPUART_GetTXFIFOThreshold(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); +} + +/** + * @brief Configure RX FIFO Threshold + * @rmtoll CR3 RXFTCFG LL_LPUART_SetRXFIFOThreshold + * @param LPUARTx LPUART Instance + * @param Threshold This parameter can be one of the following values: + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetRXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold) +{ + ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos); +} + +/** + * @brief Return RX FIFO Threshold Configuration + * @rmtoll CR3 RXFTCFG LL_LPUART_GetRXFIFOThreshold + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 + */ +__STATIC_INLINE uint32_t LL_LPUART_GetRXFIFOThreshold(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); +} + +/** + * @brief Configure TX and RX FIFOs Threshold + * @rmtoll CR3 TXFTCFG LL_LPUART_ConfigFIFOsThreshold\n + * CR3 RXFTCFG LL_LPUART_ConfigFIFOsThreshold + * @param LPUARTx LPUART Instance + * @param TXThreshold This parameter can be one of the following values: + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 + * @param RXThreshold This parameter can be one of the following values: + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ConfigFIFOsThreshold(USART_TypeDef *LPUARTx, uint32_t TXThreshold, uint32_t RXThreshold) +{ + ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | \ + (RXThreshold << USART_CR3_RXFTCFG_Pos)); +} + +/** + * @brief LPUART enabled in STOP Mode + * @note When this function is enabled, LPUART is able to wake up the MCU from Stop mode, provided that + * LPUART clock selection is HSI or LSE in RCC. + * @rmtoll CR1 UESM LL_LPUART_EnableInStopMode + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableInStopMode(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_UESM); +} + +/** + * @brief LPUART disabled in STOP Mode + * @note When this function is disabled, LPUART is not able to wake up the MCU from Stop mode + * @rmtoll CR1 UESM LL_LPUART_DisableInStopMode + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableInStopMode(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_UESM); +} + +/** + * @brief Indicate if LPUART is enabled in STOP Mode + * (able to wake up MCU from Stop mode or not) + * @rmtoll CR1 UESM LL_LPUART_IsEnabledInStopMode + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL); +} + +/** + * @brief Receiver Enable (Receiver is enabled and begins searching for a start bit) + * @rmtoll CR1 RE LL_LPUART_EnableDirectionRx + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableDirectionRx(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RE); +} + +/** + * @brief Receiver Disable + * @rmtoll CR1 RE LL_LPUART_DisableDirectionRx + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableDirectionRx(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RE); +} + +/** + * @brief Transmitter Enable + * @rmtoll CR1 TE LL_LPUART_EnableDirectionTx + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableDirectionTx(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TE); +} + +/** + * @brief Transmitter Disable + * @rmtoll CR1 TE LL_LPUART_DisableDirectionTx + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableDirectionTx(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TE); +} + +/** + * @brief Configure simultaneously enabled/disabled states + * of Transmitter and Receiver + * @rmtoll CR1 RE LL_LPUART_SetTransferDirection\n + * CR1 TE LL_LPUART_SetTransferDirection + * @param LPUARTx LPUART Instance + * @param TransferDirection This parameter can be one of the following values: + * @arg @ref LL_LPUART_DIRECTION_NONE + * @arg @ref LL_LPUART_DIRECTION_RX + * @arg @ref LL_LPUART_DIRECTION_TX + * @arg @ref LL_LPUART_DIRECTION_TX_RX + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetTransferDirection(USART_TypeDef *LPUARTx, uint32_t TransferDirection) +{ + ATOMIC_MODIFY_REG(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection); +} + +/** + * @brief Return enabled/disabled states of Transmitter and Receiver + * @rmtoll CR1 RE LL_LPUART_GetTransferDirection\n + * CR1 TE LL_LPUART_GetTransferDirection + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_DIRECTION_NONE + * @arg @ref LL_LPUART_DIRECTION_RX + * @arg @ref LL_LPUART_DIRECTION_TX + * @arg @ref LL_LPUART_DIRECTION_TX_RX + */ +__STATIC_INLINE uint32_t LL_LPUART_GetTransferDirection(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE)); +} + +/** + * @brief Configure Parity (enabled/disabled and parity mode if enabled) + * @note This function selects if hardware parity control (generation and detection) is enabled or disabled. + * When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position + * (depending on data width) and parity is checked on the received data. + * @rmtoll CR1 PS LL_LPUART_SetParity\n + * CR1 PCE LL_LPUART_SetParity + * @param LPUARTx LPUART Instance + * @param Parity This parameter can be one of the following values: + * @arg @ref LL_LPUART_PARITY_NONE + * @arg @ref LL_LPUART_PARITY_EVEN + * @arg @ref LL_LPUART_PARITY_ODD + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetParity(USART_TypeDef *LPUARTx, uint32_t Parity) +{ + MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity); +} + +/** + * @brief Return Parity configuration (enabled/disabled and parity mode if enabled) + * @rmtoll CR1 PS LL_LPUART_GetParity\n + * CR1 PCE LL_LPUART_GetParity + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_PARITY_NONE + * @arg @ref LL_LPUART_PARITY_EVEN + * @arg @ref LL_LPUART_PARITY_ODD + */ +__STATIC_INLINE uint32_t LL_LPUART_GetParity(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE)); +} + +/** + * @brief Set Receiver Wake Up method from Mute mode. + * @rmtoll CR1 WAKE LL_LPUART_SetWakeUpMethod + * @param LPUARTx LPUART Instance + * @param Method This parameter can be one of the following values: + * @arg @ref LL_LPUART_WAKEUP_IDLELINE + * @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetWakeUpMethod(USART_TypeDef *LPUARTx, uint32_t Method) +{ + MODIFY_REG(LPUARTx->CR1, USART_CR1_WAKE, Method); +} + +/** + * @brief Return Receiver Wake Up method from Mute mode + * @rmtoll CR1 WAKE LL_LPUART_GetWakeUpMethod + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_WAKEUP_IDLELINE + * @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK + */ +__STATIC_INLINE uint32_t LL_LPUART_GetWakeUpMethod(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_WAKE)); +} + +/** + * @brief Set Word length (nb of data bits, excluding start and stop bits) + * @rmtoll CR1 M LL_LPUART_SetDataWidth + * @param LPUARTx LPUART Instance + * @param DataWidth This parameter can be one of the following values: + * @arg @ref LL_LPUART_DATAWIDTH_7B + * @arg @ref LL_LPUART_DATAWIDTH_8B + * @arg @ref LL_LPUART_DATAWIDTH_9B + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetDataWidth(USART_TypeDef *LPUARTx, uint32_t DataWidth) +{ + MODIFY_REG(LPUARTx->CR1, USART_CR1_M, DataWidth); +} + +/** + * @brief Return Word length (i.e. nb of data bits, excluding start and stop bits) + * @rmtoll CR1 M LL_LPUART_GetDataWidth + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_DATAWIDTH_7B + * @arg @ref LL_LPUART_DATAWIDTH_8B + * @arg @ref LL_LPUART_DATAWIDTH_9B + */ +__STATIC_INLINE uint32_t LL_LPUART_GetDataWidth(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_M)); +} + +/** + * @brief Allow switch between Mute Mode and Active mode + * @rmtoll CR1 MME LL_LPUART_EnableMuteMode + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableMuteMode(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_MME); +} + +/** + * @brief Prevent Mute Mode use. Set Receiver in active mode permanently. + * @rmtoll CR1 MME LL_LPUART_DisableMuteMode + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableMuteMode(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_MME); +} + +/** + * @brief Indicate if switch between Mute Mode and Active mode is allowed + * @rmtoll CR1 MME LL_LPUART_IsEnabledMuteMode + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL); +} + +/** + * @brief Configure Clock source prescaler for baudrate generator and oversampling + * @rmtoll PRESC PRESCALER LL_LPUART_SetPrescaler + * @param LPUARTx LPUART Instance + * @param PrescalerValue This parameter can be one of the following values: + * @arg @ref LL_LPUART_PRESCALER_DIV1 + * @arg @ref LL_LPUART_PRESCALER_DIV2 + * @arg @ref LL_LPUART_PRESCALER_DIV4 + * @arg @ref LL_LPUART_PRESCALER_DIV6 + * @arg @ref LL_LPUART_PRESCALER_DIV8 + * @arg @ref LL_LPUART_PRESCALER_DIV10 + * @arg @ref LL_LPUART_PRESCALER_DIV12 + * @arg @ref LL_LPUART_PRESCALER_DIV16 + * @arg @ref LL_LPUART_PRESCALER_DIV32 + * @arg @ref LL_LPUART_PRESCALER_DIV64 + * @arg @ref LL_LPUART_PRESCALER_DIV128 + * @arg @ref LL_LPUART_PRESCALER_DIV256 + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetPrescaler(USART_TypeDef *LPUARTx, uint32_t PrescalerValue) +{ + MODIFY_REG(LPUARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue); +} + +/** + * @brief Retrieve the Clock source prescaler for baudrate generator and oversampling + * @rmtoll PRESC PRESCALER LL_LPUART_GetPrescaler + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_PRESCALER_DIV1 + * @arg @ref LL_LPUART_PRESCALER_DIV2 + * @arg @ref LL_LPUART_PRESCALER_DIV4 + * @arg @ref LL_LPUART_PRESCALER_DIV6 + * @arg @ref LL_LPUART_PRESCALER_DIV8 + * @arg @ref LL_LPUART_PRESCALER_DIV10 + * @arg @ref LL_LPUART_PRESCALER_DIV12 + * @arg @ref LL_LPUART_PRESCALER_DIV16 + * @arg @ref LL_LPUART_PRESCALER_DIV32 + * @arg @ref LL_LPUART_PRESCALER_DIV64 + * @arg @ref LL_LPUART_PRESCALER_DIV128 + * @arg @ref LL_LPUART_PRESCALER_DIV256 + */ +__STATIC_INLINE uint32_t LL_LPUART_GetPrescaler(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->PRESC, USART_PRESC_PRESCALER)); +} + +/** + * @brief Set the length of the stop bits + * @rmtoll CR2 STOP LL_LPUART_SetStopBitsLength + * @param LPUARTx LPUART Instance + * @param StopBits This parameter can be one of the following values: + * @arg @ref LL_LPUART_STOPBITS_1 + * @arg @ref LL_LPUART_STOPBITS_2 + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetStopBitsLength(USART_TypeDef *LPUARTx, uint32_t StopBits) +{ + MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits); +} + +/** + * @brief Retrieve the length of the stop bits + * @rmtoll CR2 STOP LL_LPUART_GetStopBitsLength + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_STOPBITS_1 + * @arg @ref LL_LPUART_STOPBITS_2 + */ +__STATIC_INLINE uint32_t LL_LPUART_GetStopBitsLength(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_STOP)); +} + +/** + * @brief Configure Character frame format (Datawidth, Parity control, Stop Bits) + * @note Call of this function is equivalent to following function call sequence : + * - Data Width configuration using @ref LL_LPUART_SetDataWidth() function + * - Parity Control and mode configuration using @ref LL_LPUART_SetParity() function + * - Stop bits configuration using @ref LL_LPUART_SetStopBitsLength() function + * @rmtoll CR1 PS LL_LPUART_ConfigCharacter\n + * CR1 PCE LL_LPUART_ConfigCharacter\n + * CR1 M LL_LPUART_ConfigCharacter\n + * CR2 STOP LL_LPUART_ConfigCharacter + * @param LPUARTx LPUART Instance + * @param DataWidth This parameter can be one of the following values: + * @arg @ref LL_LPUART_DATAWIDTH_7B + * @arg @ref LL_LPUART_DATAWIDTH_8B + * @arg @ref LL_LPUART_DATAWIDTH_9B + * @param Parity This parameter can be one of the following values: + * @arg @ref LL_LPUART_PARITY_NONE + * @arg @ref LL_LPUART_PARITY_EVEN + * @arg @ref LL_LPUART_PARITY_ODD + * @param StopBits This parameter can be one of the following values: + * @arg @ref LL_LPUART_STOPBITS_1 + * @arg @ref LL_LPUART_STOPBITS_2 + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ConfigCharacter(USART_TypeDef *LPUARTx, uint32_t DataWidth, uint32_t Parity, + uint32_t StopBits) +{ + MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth); + MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits); +} + +/** + * @brief Configure TX/RX pins swapping setting. + * @rmtoll CR2 SWAP LL_LPUART_SetTXRXSwap + * @param LPUARTx LPUART Instance + * @param SwapConfig This parameter can be one of the following values: + * @arg @ref LL_LPUART_TXRX_STANDARD + * @arg @ref LL_LPUART_TXRX_SWAPPED + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetTXRXSwap(USART_TypeDef *LPUARTx, uint32_t SwapConfig) +{ + MODIFY_REG(LPUARTx->CR2, USART_CR2_SWAP, SwapConfig); +} + +/** + * @brief Retrieve TX/RX pins swapping configuration. + * @rmtoll CR2 SWAP LL_LPUART_GetTXRXSwap + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_TXRX_STANDARD + * @arg @ref LL_LPUART_TXRX_SWAPPED + */ +__STATIC_INLINE uint32_t LL_LPUART_GetTXRXSwap(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_SWAP)); +} + +/** + * @brief Configure RX pin active level logic + * @rmtoll CR2 RXINV LL_LPUART_SetRXPinLevel + * @param LPUARTx LPUART Instance + * @param PinInvMethod This parameter can be one of the following values: + * @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD + * @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetRXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod) +{ + MODIFY_REG(LPUARTx->CR2, USART_CR2_RXINV, PinInvMethod); +} + +/** + * @brief Retrieve RX pin active level logic configuration + * @rmtoll CR2 RXINV LL_LPUART_GetRXPinLevel + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD + * @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED + */ +__STATIC_INLINE uint32_t LL_LPUART_GetRXPinLevel(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_RXINV)); +} + +/** + * @brief Configure TX pin active level logic + * @rmtoll CR2 TXINV LL_LPUART_SetTXPinLevel + * @param LPUARTx LPUART Instance + * @param PinInvMethod This parameter can be one of the following values: + * @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD + * @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetTXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod) +{ + MODIFY_REG(LPUARTx->CR2, USART_CR2_TXINV, PinInvMethod); +} + +/** + * @brief Retrieve TX pin active level logic configuration + * @rmtoll CR2 TXINV LL_LPUART_GetTXPinLevel + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD + * @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED + */ +__STATIC_INLINE uint32_t LL_LPUART_GetTXPinLevel(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_TXINV)); +} + +/** + * @brief Configure Binary data logic. + * + * @note Allow to define how Logical data from the data register are send/received : + * either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H) + * @rmtoll CR2 DATAINV LL_LPUART_SetBinaryDataLogic + * @param LPUARTx LPUART Instance + * @param DataLogic This parameter can be one of the following values: + * @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE + * @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetBinaryDataLogic(USART_TypeDef *LPUARTx, uint32_t DataLogic) +{ + MODIFY_REG(LPUARTx->CR2, USART_CR2_DATAINV, DataLogic); +} + +/** + * @brief Retrieve Binary data configuration + * @rmtoll CR2 DATAINV LL_LPUART_GetBinaryDataLogic + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE + * @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE + */ +__STATIC_INLINE uint32_t LL_LPUART_GetBinaryDataLogic(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_DATAINV)); +} + +/** + * @brief Configure transfer bit order (either Less or Most Significant Bit First) + * @note MSB First means data is transmitted/received with the MSB first, following the start bit. + * LSB First means data is transmitted/received with data bit 0 first, following the start bit. + * @rmtoll CR2 MSBFIRST LL_LPUART_SetTransferBitOrder + * @param LPUARTx LPUART Instance + * @param BitOrder This parameter can be one of the following values: + * @arg @ref LL_LPUART_BITORDER_LSBFIRST + * @arg @ref LL_LPUART_BITORDER_MSBFIRST + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetTransferBitOrder(USART_TypeDef *LPUARTx, uint32_t BitOrder) +{ + MODIFY_REG(LPUARTx->CR2, USART_CR2_MSBFIRST, BitOrder); +} + +/** + * @brief Return transfer bit order (either Less or Most Significant Bit First) + * @note MSB First means data is transmitted/received with the MSB first, following the start bit. + * LSB First means data is transmitted/received with data bit 0 first, following the start bit. + * @rmtoll CR2 MSBFIRST LL_LPUART_GetTransferBitOrder + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_BITORDER_LSBFIRST + * @arg @ref LL_LPUART_BITORDER_MSBFIRST + */ +__STATIC_INLINE uint32_t LL_LPUART_GetTransferBitOrder(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_MSBFIRST)); +} + +/** + * @brief Set Address of the LPUART node. + * @note This is used in multiprocessor communication during Mute mode or Stop mode, + * for wake up with address mark detection. + * @note 4bits address node is used when 4-bit Address Detection is selected in ADDM7. + * (b7-b4 should be set to 0) + * 8bits address node is used when 7-bit Address Detection is selected in ADDM7. + * (This is used in multiprocessor communication during Mute mode or Stop mode, + * for wake up with 7-bit address mark detection. + * The MSB of the character sent by the transmitter should be equal to 1. + * It may also be used for character detection during normal reception, + * Mute mode inactive (for example, end of block detection in ModBus protocol). + * In this case, the whole received character (8-bit) is compared to the ADD[7:0] + * value and CMF flag is set on match) + * @rmtoll CR2 ADD LL_LPUART_ConfigNodeAddress\n + * CR2 ADDM7 LL_LPUART_ConfigNodeAddress + * @param LPUARTx LPUART Instance + * @param AddressLen This parameter can be one of the following values: + * @arg @ref LL_LPUART_ADDRESS_DETECT_4B + * @arg @ref LL_LPUART_ADDRESS_DETECT_7B + * @param NodeAddress 4 or 7 bit Address of the LPUART node. + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ConfigNodeAddress(USART_TypeDef *LPUARTx, uint32_t AddressLen, uint32_t NodeAddress) +{ + MODIFY_REG(LPUARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7, + (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos))); +} + +/** + * @brief Return 8 bit Address of the LPUART node as set in ADD field of CR2. + * @note If 4-bit Address Detection is selected in ADDM7, + * only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant) + * If 7-bit Address Detection is selected in ADDM7, + * only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant) + * @rmtoll CR2 ADD LL_LPUART_GetNodeAddress + * @param LPUARTx LPUART Instance + * @retval Address of the LPUART node (Value between Min_Data=0 and Max_Data=255) + */ +__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos); +} + +/** + * @brief Return Length of Node Address used in Address Detection mode (7-bit or 4-bit) + * @rmtoll CR2 ADDM7 LL_LPUART_GetNodeAddressLen + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_ADDRESS_DETECT_4B + * @arg @ref LL_LPUART_ADDRESS_DETECT_7B + */ +__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddressLen(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADDM7)); +} + +/** + * @brief Enable RTS HW Flow Control + * @rmtoll CR3 RTSE LL_LPUART_EnableRTSHWFlowCtrl + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableRTSHWFlowCtrl(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR3, USART_CR3_RTSE); +} + +/** + * @brief Disable RTS HW Flow Control + * @rmtoll CR3 RTSE LL_LPUART_DisableRTSHWFlowCtrl + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableRTSHWFlowCtrl(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR3, USART_CR3_RTSE); +} + +/** + * @brief Enable CTS HW Flow Control + * @rmtoll CR3 CTSE LL_LPUART_EnableCTSHWFlowCtrl + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableCTSHWFlowCtrl(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR3, USART_CR3_CTSE); +} + +/** + * @brief Disable CTS HW Flow Control + * @rmtoll CR3 CTSE LL_LPUART_DisableCTSHWFlowCtrl + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableCTSHWFlowCtrl(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSE); +} + +/** + * @brief Configure HW Flow Control mode (both CTS and RTS) + * @rmtoll CR3 RTSE LL_LPUART_SetHWFlowCtrl\n + * CR3 CTSE LL_LPUART_SetHWFlowCtrl + * @param LPUARTx LPUART Instance + * @param HardwareFlowControl This parameter can be one of the following values: + * @arg @ref LL_LPUART_HWCONTROL_NONE + * @arg @ref LL_LPUART_HWCONTROL_RTS + * @arg @ref LL_LPUART_HWCONTROL_CTS + * @arg @ref LL_LPUART_HWCONTROL_RTS_CTS + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetHWFlowCtrl(USART_TypeDef *LPUARTx, uint32_t HardwareFlowControl) +{ + MODIFY_REG(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl); +} + +/** + * @brief Return HW Flow Control configuration (both CTS and RTS) + * @rmtoll CR3 RTSE LL_LPUART_GetHWFlowCtrl\n + * CR3 CTSE LL_LPUART_GetHWFlowCtrl + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_HWCONTROL_NONE + * @arg @ref LL_LPUART_HWCONTROL_RTS + * @arg @ref LL_LPUART_HWCONTROL_CTS + * @arg @ref LL_LPUART_HWCONTROL_RTS_CTS + */ +__STATIC_INLINE uint32_t LL_LPUART_GetHWFlowCtrl(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE)); +} + +/** + * @brief Enable Overrun detection + * @rmtoll CR3 OVRDIS LL_LPUART_EnableOverrunDetect + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableOverrunDetect(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR3, USART_CR3_OVRDIS); +} + +/** + * @brief Disable Overrun detection + * @rmtoll CR3 OVRDIS LL_LPUART_DisableOverrunDetect + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableOverrunDetect(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR3, USART_CR3_OVRDIS); +} + +/** + * @brief Indicate if Overrun detection is enabled + * @rmtoll CR3 OVRDIS LL_LPUART_IsEnabledOverrunDetect + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledOverrunDetect(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL); +} + +/** + * @brief Configure LPUART BRR register for achieving expected Baud Rate value. + * + * @note Compute and set LPUARTDIV value in BRR Register (full BRR content) + * according to used Peripheral Clock and expected Baud Rate values + * @note Peripheral clock and Baud Rate values provided as function parameters should be valid + * (Baud rate value != 0). + * @note Provided that LPUARTx_BRR must be > = 0x300 and LPUART_BRR is 20-bit, + * a care should be taken when generating high baud rates using high PeriphClk + * values. PeriphClk must be in the range [3 x BaudRate, 4096 x BaudRate]. + * @rmtoll BRR BRR LL_LPUART_SetBaudRate + * @param LPUARTx LPUART Instance + * @param PeriphClk Peripheral Clock + * @param PrescalerValue This parameter can be one of the following values: + * @arg @ref LL_LPUART_PRESCALER_DIV1 + * @arg @ref LL_LPUART_PRESCALER_DIV2 + * @arg @ref LL_LPUART_PRESCALER_DIV4 + * @arg @ref LL_LPUART_PRESCALER_DIV6 + * @arg @ref LL_LPUART_PRESCALER_DIV8 + * @arg @ref LL_LPUART_PRESCALER_DIV10 + * @arg @ref LL_LPUART_PRESCALER_DIV12 + * @arg @ref LL_LPUART_PRESCALER_DIV16 + * @arg @ref LL_LPUART_PRESCALER_DIV32 + * @arg @ref LL_LPUART_PRESCALER_DIV64 + * @arg @ref LL_LPUART_PRESCALER_DIV128 + * @arg @ref LL_LPUART_PRESCALER_DIV256 + * @param BaudRate Baud Rate + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue, + uint32_t BaudRate) +{ + if (BaudRate != 0U) + { + LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, PrescalerValue, BaudRate); + } +} + +/** + * @brief Return current Baud Rate value, according to LPUARTDIV present in BRR register + * (full BRR content), and to used Peripheral Clock values + * @note In case of non-initialized or invalid value stored in BRR register, value 0 will be returned. + * @rmtoll BRR BRR LL_LPUART_GetBaudRate + * @param LPUARTx LPUART Instance + * @param PeriphClk Peripheral Clock + * @param PrescalerValue This parameter can be one of the following values: + * @arg @ref LL_LPUART_PRESCALER_DIV1 + * @arg @ref LL_LPUART_PRESCALER_DIV2 + * @arg @ref LL_LPUART_PRESCALER_DIV4 + * @arg @ref LL_LPUART_PRESCALER_DIV6 + * @arg @ref LL_LPUART_PRESCALER_DIV8 + * @arg @ref LL_LPUART_PRESCALER_DIV10 + * @arg @ref LL_LPUART_PRESCALER_DIV12 + * @arg @ref LL_LPUART_PRESCALER_DIV16 + * @arg @ref LL_LPUART_PRESCALER_DIV32 + * @arg @ref LL_LPUART_PRESCALER_DIV64 + * @arg @ref LL_LPUART_PRESCALER_DIV128 + * @arg @ref LL_LPUART_PRESCALER_DIV256 + * @retval Baud Rate + */ +__STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(const USART_TypeDef *LPUARTx, uint32_t PeriphClk, + uint32_t PrescalerValue) +{ + uint32_t lpuartdiv; + uint32_t brrresult; + uint32_t periphclkpresc = (uint32_t)(PeriphClk / (LPUART_PRESCALER_TAB[(uint16_t)PrescalerValue])); + + lpuartdiv = LPUARTx->BRR & LPUART_BRR_MASK; + + if (lpuartdiv >= LPUART_BRR_MIN_VALUE) + { + brrresult = (uint32_t)(((uint64_t)(periphclkpresc) * LPUART_LPUARTDIV_FREQ_MUL) / lpuartdiv); + } + else + { + brrresult = 0x0UL; + } + + return (brrresult); +} + +/** + * @} + */ + +/** @defgroup LPUART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature + * @{ + */ + +/** + * @brief Enable Single Wire Half-Duplex mode + * @rmtoll CR3 HDSEL LL_LPUART_EnableHalfDuplex + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableHalfDuplex(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR3, USART_CR3_HDSEL); +} + +/** + * @brief Disable Single Wire Half-Duplex mode + * @rmtoll CR3 HDSEL LL_LPUART_DisableHalfDuplex + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableHalfDuplex(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR3, USART_CR3_HDSEL); +} + +/** + * @brief Indicate if Single Wire Half-Duplex mode is enabled + * @rmtoll CR3 HDSEL LL_LPUART_IsEnabledHalfDuplex + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledHalfDuplex(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup LPUART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature + * @{ + */ + +/** + * @brief Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits). + * @rmtoll CR1 DEDT LL_LPUART_SetDEDeassertionTime + * @param LPUARTx LPUART Instance + * @param Time Value between Min_Data=0 and Max_Data=31 + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetDEDeassertionTime(USART_TypeDef *LPUARTx, uint32_t Time) +{ + MODIFY_REG(LPUARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos); +} + +/** + * @brief Return DEDT (Driver Enable De-Assertion Time) + * @rmtoll CR1 DEDT LL_LPUART_GetDEDeassertionTime + * @param LPUARTx LPUART Instance + * @retval Time value expressed on 5 bits ([4:0] bits) : c + */ +__STATIC_INLINE uint32_t LL_LPUART_GetDEDeassertionTime(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos); +} + +/** + * @brief Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits). + * @rmtoll CR1 DEAT LL_LPUART_SetDEAssertionTime + * @param LPUARTx LPUART Instance + * @param Time Value between Min_Data=0 and Max_Data=31 + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetDEAssertionTime(USART_TypeDef *LPUARTx, uint32_t Time) +{ + MODIFY_REG(LPUARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos); +} + +/** + * @brief Return DEAT (Driver Enable Assertion Time) + * @rmtoll CR1 DEAT LL_LPUART_GetDEAssertionTime + * @param LPUARTx LPUART Instance + * @retval Time value expressed on 5 bits ([4:0] bits) : Time Value between Min_Data=0 and Max_Data=31 + */ +__STATIC_INLINE uint32_t LL_LPUART_GetDEAssertionTime(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos); +} + +/** + * @brief Enable Driver Enable (DE) Mode + * @rmtoll CR3 DEM LL_LPUART_EnableDEMode + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableDEMode(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR3, USART_CR3_DEM); +} + +/** + * @brief Disable Driver Enable (DE) Mode + * @rmtoll CR3 DEM LL_LPUART_DisableDEMode + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableDEMode(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR3, USART_CR3_DEM); +} + +/** + * @brief Indicate if Driver Enable (DE) Mode is enabled + * @rmtoll CR3 DEM LL_LPUART_IsEnabledDEMode + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDEMode(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL); +} + +/** + * @brief Select Driver Enable Polarity + * @rmtoll CR3 DEP LL_LPUART_SetDESignalPolarity + * @param LPUARTx LPUART Instance + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_LPUART_DE_POLARITY_HIGH + * @arg @ref LL_LPUART_DE_POLARITY_LOW + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetDESignalPolarity(USART_TypeDef *LPUARTx, uint32_t Polarity) +{ + MODIFY_REG(LPUARTx->CR3, USART_CR3_DEP, Polarity); +} + +/** + * @brief Return Driver Enable Polarity + * @rmtoll CR3 DEP LL_LPUART_GetDESignalPolarity + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_DE_POLARITY_HIGH + * @arg @ref LL_LPUART_DE_POLARITY_LOW + */ +__STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_DEP)); +} + +/** + * @} + */ + +/** @defgroup LPUART_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Check if the LPUART Parity Error Flag is set or not + * @rmtoll ISR PE LL_LPUART_IsActiveFlag_PE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Framing Error Flag is set or not + * @rmtoll ISR FE LL_LPUART_IsActiveFlag_FE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Noise error detected Flag is set or not + * @rmtoll ISR NE LL_LPUART_IsActiveFlag_NE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART OverRun Error Flag is set or not + * @rmtoll ISR ORE LL_LPUART_IsActiveFlag_ORE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART IDLE line detected Flag is set or not + * @rmtoll ISR IDLE LL_LPUART_IsActiveFlag_IDLE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL); +} + +#define LL_LPUART_IsActiveFlag_RXNE LL_LPUART_IsActiveFlag_RXNE_RXFNE /* Redefinition for legacy purpose */ + +/** + * @brief Check if the LPUART Read Data Register or LPUART RX FIFO Not Empty Flag is set or not + * @rmtoll ISR RXNE_RXFNE LL_LPUART_IsActiveFlag_RXNE_RXFNE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE_RXFNE(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Transmission Complete Flag is set or not + * @rmtoll ISR TC LL_LPUART_IsActiveFlag_TC + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL); +} + +#define LL_LPUART_IsActiveFlag_TXE LL_LPUART_IsActiveFlag_TXE_TXFNF /* Redefinition for legacy purpose */ + +/** + * @brief Check if the LPUART Transmit Data Register Empty or LPUART TX FIFO Not Full Flag is set or not + * @rmtoll ISR TXE_TXFNF LL_LPUART_IsActiveFlag_TXE_TXFNF + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE_TXFNF(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART CTS interrupt Flag is set or not + * @rmtoll ISR CTSIF LL_LPUART_IsActiveFlag_nCTS + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART CTS Flag is set or not + * @rmtoll ISR CTS LL_LPUART_IsActiveFlag_CTS + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Busy Flag is set or not + * @rmtoll ISR BUSY LL_LPUART_IsActiveFlag_BUSY + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Character Match Flag is set or not + * @rmtoll ISR CMF LL_LPUART_IsActiveFlag_CM + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Send Break Flag is set or not + * @rmtoll ISR SBKF LL_LPUART_IsActiveFlag_SBK + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Receive Wake Up from mute mode Flag is set or not + * @rmtoll ISR RWU LL_LPUART_IsActiveFlag_RWU + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Transmit Enable Acknowledge Flag is set or not + * @rmtoll ISR TEACK LL_LPUART_IsActiveFlag_TEACK + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Receive Enable Acknowledge Flag is set or not + * @rmtoll ISR REACK LL_LPUART_IsActiveFlag_REACK + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART TX FIFO Empty Flag is set or not + * @rmtoll ISR TXFE LL_LPUART_IsActiveFlag_TXFE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFE(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART RX FIFO Full Flag is set or not + * @rmtoll ISR RXFF LL_LPUART_IsActiveFlag_RXFF + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFF(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART TX FIFO Threshold Flag is set or not + * @rmtoll ISR TXFT LL_LPUART_IsActiveFlag_TXFT + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFT(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART RX FIFO Threshold Flag is set or not + * @rmtoll ISR RXFT LL_LPUART_IsActiveFlag_RXFT + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFT(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL); +} + +/** + * @brief Clear Parity Error Flag + * @rmtoll ICR PECF LL_LPUART_ClearFlag_PE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_PE(USART_TypeDef *LPUARTx) +{ + WRITE_REG(LPUARTx->ICR, USART_ICR_PECF); +} + +/** + * @brief Clear Framing Error Flag + * @rmtoll ICR FECF LL_LPUART_ClearFlag_FE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_FE(USART_TypeDef *LPUARTx) +{ + WRITE_REG(LPUARTx->ICR, USART_ICR_FECF); +} + +/** + * @brief Clear Noise detected Flag + * @rmtoll ICR NECF LL_LPUART_ClearFlag_NE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_NE(USART_TypeDef *LPUARTx) +{ + WRITE_REG(LPUARTx->ICR, USART_ICR_NECF); +} + +/** + * @brief Clear OverRun Error Flag + * @rmtoll ICR ORECF LL_LPUART_ClearFlag_ORE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_ORE(USART_TypeDef *LPUARTx) +{ + WRITE_REG(LPUARTx->ICR, USART_ICR_ORECF); +} + +/** + * @brief Clear IDLE line detected Flag + * @rmtoll ICR IDLECF LL_LPUART_ClearFlag_IDLE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_IDLE(USART_TypeDef *LPUARTx) +{ + WRITE_REG(LPUARTx->ICR, USART_ICR_IDLECF); +} + +/** + * @brief Clear Transmission Complete Flag + * @rmtoll ICR TCCF LL_LPUART_ClearFlag_TC + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_TC(USART_TypeDef *LPUARTx) +{ + WRITE_REG(LPUARTx->ICR, USART_ICR_TCCF); +} + +/** + * @brief Clear CTS Interrupt Flag + * @rmtoll ICR CTSCF LL_LPUART_ClearFlag_nCTS + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_nCTS(USART_TypeDef *LPUARTx) +{ + WRITE_REG(LPUARTx->ICR, USART_ICR_CTSCF); +} + +/** + * @brief Clear Character Match Flag + * @rmtoll ICR CMCF LL_LPUART_ClearFlag_CM + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_CM(USART_TypeDef *LPUARTx) +{ + WRITE_REG(LPUARTx->ICR, USART_ICR_CMCF); +} + +/** + * @} + */ + +/** @defgroup LPUART_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable IDLE Interrupt + * @rmtoll CR1 IDLEIE LL_LPUART_EnableIT_IDLE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_IDLE(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_IDLEIE); +} + +#define LL_LPUART_EnableIT_RXNE LL_LPUART_EnableIT_RXNE_RXFNE /* Redefinition for legacy purpose */ + +/** + * @brief Enable RX Not Empty and RX FIFO Not Empty Interrupt + * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_EnableIT_RXNE_RXFNE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE); +} + +/** + * @brief Enable Transmission Complete Interrupt + * @rmtoll CR1 TCIE LL_LPUART_EnableIT_TC + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_TC(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TCIE); +} + +#define LL_LPUART_EnableIT_TXE LL_LPUART_EnableIT_TXE_TXFNF /* Redefinition for legacy purpose */ + +/** + * @brief Enable TX Empty and TX FIFO Not Full Interrupt + * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_EnableIT_TXE_TXFNF + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_TXE_TXFNF(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE); +} + +/** + * @brief Enable Parity Error Interrupt + * @rmtoll CR1 PEIE LL_LPUART_EnableIT_PE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_PE(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_PEIE); +} + +/** + * @brief Enable Character Match Interrupt + * @rmtoll CR1 CMIE LL_LPUART_EnableIT_CM + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_CM(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_CMIE); +} + +/** + * @brief Enable TX FIFO Empty Interrupt + * @rmtoll CR1 TXFEIE LL_LPUART_EnableIT_TXFE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_TXFE(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXFEIE); +} + +/** + * @brief Enable RX FIFO Full Interrupt + * @rmtoll CR1 RXFFIE LL_LPUART_EnableIT_RXFF + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_RXFF(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXFFIE); +} + +/** + * @brief Enable Error Interrupt + * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing + * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register). + * - 0: Interrupt is inhibited + * - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register. + * @rmtoll CR3 EIE LL_LPUART_EnableIT_ERROR + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_ERROR(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_EIE); +} + +/** + * @brief Enable CTS Interrupt + * @rmtoll CR3 CTSIE LL_LPUART_EnableIT_CTS + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_CTS(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_CTSIE); +} + +/** + * @brief Enable TX FIFO Threshold Interrupt + * @rmtoll CR3 TXFTIE LL_LPUART_EnableIT_TXFT + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_TXFT(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_TXFTIE); +} + +/** + * @brief Enable RX FIFO Threshold Interrupt + * @rmtoll CR3 RXFTIE LL_LPUART_EnableIT_RXFT + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_RXFT(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_RXFTIE); +} + +/** + * @brief Disable IDLE Interrupt + * @rmtoll CR1 IDLEIE LL_LPUART_DisableIT_IDLE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_IDLE(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_IDLEIE); +} + +#define LL_LPUART_DisableIT_RXNE LL_LPUART_DisableIT_RXNE_RXFNE /* Redefinition for legacy purpose */ + +/** + * @brief Disable RX Not Empty and RX FIFO Not Empty Interrupt + * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_DisableIT_RXNE_RXFNE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE); +} + +/** + * @brief Disable Transmission Complete Interrupt + * @rmtoll CR1 TCIE LL_LPUART_DisableIT_TC + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_TC(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TCIE); +} + +#define LL_LPUART_DisableIT_TXE LL_LPUART_DisableIT_TXE_TXFNF /* Redefinition for legacy purpose */ + +/** + * @brief Disable TX Empty and TX FIFO Not Full Interrupt + * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_DisableIT_TXE_TXFNF + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_TXE_TXFNF(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE); +} + +/** + * @brief Disable Parity Error Interrupt + * @rmtoll CR1 PEIE LL_LPUART_DisableIT_PE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_PE(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_PEIE); +} + +/** + * @brief Disable Character Match Interrupt + * @rmtoll CR1 CMIE LL_LPUART_DisableIT_CM + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_CM(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_CMIE); +} + +/** + * @brief Disable TX FIFO Empty Interrupt + * @rmtoll CR1 TXFEIE LL_LPUART_DisableIT_TXFE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_TXFE(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXFEIE); +} + +/** + * @brief Disable RX FIFO Full Interrupt + * @rmtoll CR1 RXFFIE LL_LPUART_DisableIT_RXFF + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_RXFF(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXFFIE); +} + +/** + * @brief Disable Error Interrupt + * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing + * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register). + * - 0: Interrupt is inhibited + * - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register. + * @rmtoll CR3 EIE LL_LPUART_DisableIT_ERROR + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_ERROR(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_EIE); +} + +/** + * @brief Disable CTS Interrupt + * @rmtoll CR3 CTSIE LL_LPUART_DisableIT_CTS + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_CTS(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSIE); +} + +/** + * @brief Disable TX FIFO Threshold Interrupt + * @rmtoll CR3 TXFTIE LL_LPUART_DisableIT_TXFT + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_TXFT(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_TXFTIE); +} + +/** + * @brief Disable RX FIFO Threshold Interrupt + * @rmtoll CR3 RXFTIE LL_LPUART_DisableIT_RXFT + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_RXFT(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_RXFTIE); +} + +/** + * @brief Check if the LPUART IDLE Interrupt source is enabled or disabled. + * @rmtoll CR1 IDLEIE LL_LPUART_IsEnabledIT_IDLE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL); +} + +#define LL_LPUART_IsEnabledIT_RXNE LL_LPUART_IsEnabledIT_RXNE_RXFNE /* Redefinition for legacy purpose */ + +/** + * @brief Check if the LPUART RX Not Empty and LPUART RX FIFO Not Empty Interrupt is enabled or disabled. + * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_IsEnabledIT_RXNE_RXFNE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE_RXFNE(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Transmission Complete Interrupt is enabled or disabled. + * @rmtoll CR1 TCIE LL_LPUART_IsEnabledIT_TC + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL); +} + +#define LL_LPUART_IsEnabledIT_TXE LL_LPUART_IsEnabledIT_TXE_TXFNF /* Redefinition for legacy purpose */ + +/** + * @brief Check if the LPUART TX Empty and LPUART TX FIFO Not Full Interrupt is enabled or disabled + * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_IsEnabledIT_TXE_TXFNF + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE_TXFNF(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Parity Error Interrupt is enabled or disabled. + * @rmtoll CR1 PEIE LL_LPUART_IsEnabledIT_PE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Character Match Interrupt is enabled or disabled. + * @rmtoll CR1 CMIE LL_LPUART_IsEnabledIT_CM + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART TX FIFO Empty Interrupt is enabled or disabled + * @rmtoll CR1 TXFEIE LL_LPUART_IsEnabledIT_TXFE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFE(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART RX FIFO Full Interrupt is enabled or disabled + * @rmtoll CR1 RXFFIE LL_LPUART_IsEnabledIT_RXFF + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFF(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Error Interrupt is enabled or disabled. + * @rmtoll CR3 EIE LL_LPUART_IsEnabledIT_ERROR + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART CTS Interrupt is enabled or disabled. + * @rmtoll CR3 CTSIE LL_LPUART_IsEnabledIT_CTS + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if LPUART TX FIFO Threshold Interrupt is enabled or disabled + * @rmtoll CR3 TXFTIE LL_LPUART_IsEnabledIT_TXFT + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFT(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if LPUART RX FIFO Threshold Interrupt is enabled or disabled + * @rmtoll CR3 RXFTIE LL_LPUART_IsEnabledIT_RXFT + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFT(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup LPUART_LL_EF_DMA_Management DMA_Management + * @{ + */ + +/** + * @brief Enable DMA Mode for reception + * @rmtoll CR3 DMAR LL_LPUART_EnableDMAReq_RX + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableDMAReq_RX(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAR); +} + +/** + * @brief Disable DMA Mode for reception + * @rmtoll CR3 DMAR LL_LPUART_DisableDMAReq_RX + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableDMAReq_RX(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAR); +} + +/** + * @brief Check if DMA Mode is enabled for reception + * @rmtoll CR3 DMAR LL_LPUART_IsEnabledDMAReq_RX + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_RX(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL); +} + +/** + * @brief Enable DMA Mode for transmission + * @rmtoll CR3 DMAT LL_LPUART_EnableDMAReq_TX + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableDMAReq_TX(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAT); +} + +/** + * @brief Disable DMA Mode for transmission + * @rmtoll CR3 DMAT LL_LPUART_DisableDMAReq_TX + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableDMAReq_TX(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAT); +} + +/** + * @brief Check if DMA Mode is enabled for transmission + * @rmtoll CR3 DMAT LL_LPUART_IsEnabledDMAReq_TX + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_TX(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL); +} + +/** + * @brief Enable DMA Disabling on Reception Error + * @rmtoll CR3 DDRE LL_LPUART_EnableDMADeactOnRxErr + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableDMADeactOnRxErr(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR3, USART_CR3_DDRE); +} + +/** + * @brief Disable DMA Disabling on Reception Error + * @rmtoll CR3 DDRE LL_LPUART_DisableDMADeactOnRxErr + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableDMADeactOnRxErr(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR3, USART_CR3_DDRE); +} + +/** + * @brief Indicate if DMA Disabling on Reception Error is disabled + * @rmtoll CR3 DDRE LL_LPUART_IsEnabledDMADeactOnRxErr + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL); +} + +/** + * @brief Get the LPUART data register address used for DMA transfer + * @rmtoll RDR RDR LL_LPUART_DMA_GetRegAddr\n + * @rmtoll TDR TDR LL_LPUART_DMA_GetRegAddr + * @param LPUARTx LPUART Instance + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_LPUART_DMA_REG_DATA_TRANSMIT + * @arg @ref LL_LPUART_DMA_REG_DATA_RECEIVE + * @retval Address of data register + */ +__STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(const USART_TypeDef *LPUARTx, uint32_t Direction) +{ + uint32_t data_reg_addr; + + if (Direction == LL_LPUART_DMA_REG_DATA_TRANSMIT) + { + /* return address of TDR register */ + data_reg_addr = (uint32_t) &(LPUARTx->TDR); + } + else + { + /* return address of RDR register */ + data_reg_addr = (uint32_t) &(LPUARTx->RDR); + } + + return data_reg_addr; +} + +/** + * @} + */ + +/** @defgroup LPUART_LL_EF_Data_Management Data_Management + * @{ + */ + +/** + * @brief Read Receiver Data register (Receive Data value, 8 bits) + * @rmtoll RDR RDR LL_LPUART_ReceiveData8 + * @param LPUARTx LPUART Instance + * @retval Time Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(const USART_TypeDef *LPUARTx) +{ + return (uint8_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR) & 0xFFU); +} + +/** + * @brief Read Receiver Data register (Receive Data value, 9 bits) + * @rmtoll RDR RDR LL_LPUART_ReceiveData9 + * @param LPUARTx LPUART Instance + * @retval Time Value between Min_Data=0x00 and Max_Data=0x1FF + */ +__STATIC_INLINE uint16_t LL_LPUART_ReceiveData9(const USART_TypeDef *LPUARTx) +{ + return (uint16_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR)); +} + +/** + * @brief Write in Transmitter Data Register (Transmit Data value, 8 bits) + * @rmtoll TDR TDR LL_LPUART_TransmitData8 + * @param LPUARTx LPUART Instance + * @param Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_LPUART_TransmitData8(USART_TypeDef *LPUARTx, uint8_t Value) +{ + LPUARTx->TDR = Value; +} + +/** + * @brief Write in Transmitter Data Register (Transmit Data value, 9 bits) + * @rmtoll TDR TDR LL_LPUART_TransmitData9 + * @param LPUARTx LPUART Instance + * @param Value between Min_Data=0x00 and Max_Data=0x1FF + * @retval None + */ +__STATIC_INLINE void LL_LPUART_TransmitData9(USART_TypeDef *LPUARTx, uint16_t Value) +{ + LPUARTx->TDR = Value & 0x1FFUL; +} + +/** + * @} + */ + +/** @defgroup LPUART_LL_EF_Execution Execution + * @{ + */ + +/** + * @brief Request Break sending + * @rmtoll RQR SBKRQ LL_LPUART_RequestBreakSending + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_RequestBreakSending(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_SBKRQ); +} + +/** + * @brief Put LPUART in mute mode and set the RWU flag + * @rmtoll RQR MMRQ LL_LPUART_RequestEnterMuteMode + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_RequestEnterMuteMode(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_MMRQ); +} + +/** + * @brief Request a Receive Data and FIFO flush + * @note Allows to discard the received data without reading them, and avoid an overrun + * condition. + * @rmtoll RQR RXFRQ LL_LPUART_RequestRxDataFlush + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_RequestRxDataFlush(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_RXFRQ); +} + +/** + * @} + */ + +/** @defgroup LPUART_LL_EF_AutonomousMode Configuration functions related to Autonomous mode feature + * @{ + */ + +/** + * @brief Enable Selected Trigger + * @rmtoll AUTOCR TRIGEN LL_LPUART_Enable_SelectedTrigger + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_Enable_SelectedTrigger(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->AUTOCR, USART_AUTOCR_TRIGEN); +} + +/** + * @brief Disable Selected Trigger + * @rmtoll AUTOCR TRIGEN LL_LPUART_Disable_SelectedTrigger + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_Disable_SelectedTrigger(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->AUTOCR, USART_AUTOCR_TRIGEN); +} + +/** + * @brief Indicate if selected Trigger is disabled or enabled + * @rmtoll AUTOCR TRIGEN LL_LPUART_IsEnabled_SelectedTrigger + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabled_SelectedTrigger(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->AUTOCR, USART_AUTOCR_TRIGEN) == (USART_AUTOCR_TRIGEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable Autonomous Send Idle Frame feature + * @rmtoll AUTOCR IDLEDIS LL_LPUART_Enable_AutonomousSendIdleFrame + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_Enable_AutonomousSendIdleFrame(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->AUTOCR, USART_AUTOCR_IDLEDIS); +} + +/** + * @brief Disable Autonomous Send Idle Frame feature + * @rmtoll AUTOCR IDLEDIS LL_LPUART_Disable_AutonomousSendIdleFrame + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_Disable_AutonomousSendIdleFrame(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->AUTOCR, USART_AUTOCR_IDLEDIS); +} + +/** + * @brief Indicate if Autonomous send Idle Frame feature is disabled or enabled + * @rmtoll AUTOCR IDLEDIS LL_LPUART_IsEnabled_AutonomousSendIdleFrame + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabled_AutonomousSendIdleFrame(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->AUTOCR, USART_AUTOCR_IDLEDIS) == (USART_AUTOCR_IDLEDIS)) ? 0UL : 1UL); +} + +/** + * @brief Configure the Number of transferred data in bytes + * @rmtoll AUTOCR TDN LL_LPUART_SetNbTxData + * @param LPUARTx LPUART Instance + * @param Nbdata This parameter can be a value between 0 and 0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetNbTxData(USART_TypeDef *LPUARTx, uint32_t Nbdata) +{ + MODIFY_REG(LPUARTx->AUTOCR, USART_AUTOCR_TDN, (uint16_t)Nbdata); +} + +/** + * @brief Retrieve the Number of transferred data in bytes + * @rmtoll AUTOCR TDN LL_LPUART_GetNbTxData + * @param LPUARTx LPUART Instance + * @retval Returned value can be a value between 0 and 0xFFFF + */ +__STATIC_INLINE uint32_t LL_LPUART_GetNbTxData(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->AUTOCR, USART_AUTOCR_TDN)); +} + +/** + * @brief Set the trigger polarity + * @rmtoll AUTOCR TRIGPOL LL_LPUART_SetTriggerPolarity + * @param LPUARTx LPUART Instance + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_LPUART_TRIG_POLARITY_RISING + * @arg @ref LL_LPUART_TRIG_POLARITY_FALLING + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetTriggerPolarity(USART_TypeDef *LPUARTx, uint32_t Polarity) +{ + MODIFY_REG(LPUARTx->AUTOCR, USART_AUTOCR_TRIGPOL, Polarity); +} + +/** + * @brief Get the trigger polarity + * @rmtoll AUTOCR TRIGPOL LL_LPUART_GetTriggerPolarity + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_TRIG_POLARITY_RISING + * @arg @ref LL_LPUART_TRIG_POLARITY_FALLING + */ +__STATIC_INLINE uint32_t LL_LPUART_GetTriggerPolarity(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->AUTOCR, USART_AUTOCR_TRIGPOL)); +} + +/** + * @brief Set the selected trigger + * @rmtoll AUTOCR TRIGSEL LL_LPUART_SetSelectedTrigger + * @param LPUARTx LPUART Instance + * @param Trigger This parameter can be one of the following values: + * @arg @ref LL_LPUART_GPDMA1_CH0_TCF_TRG + * @arg @ref LL_LPUART_GPDMA1_CH1_TCF_TRG + * @arg @ref LL_LPUART_GPDMA1_CH2_TCF_TRG + * @arg @ref LL_LPUART_GPDMA1_CH3_TCF_TRG + * @arg @ref LL_LPUART_EXTI_LINE6_TRG + * @arg @ref LL_LPUART_EXTI_LINE8_TRG + * @arg @ref LL_LPUART_LPTIM1_OUT_TRG + * @arg @ref LL_LPUART_COMP1_OUT_TRG (only available of STM32WBA54xx and STM32WBA55xx) + * @arg @ref LL_LPUART_COMP2_OUT_TRG (only available of STM32WBA54xx and STM32WBA55xx) + * @arg @ref LL_LPUART_RTC_ALRA_TRG + * @arg @ref LL_LPUART_RTC_WUT_TRG + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetSelectedTrigger(USART_TypeDef *LPUARTx, uint32_t Trigger) +{ + MODIFY_REG(LPUARTx->AUTOCR, USART_AUTOCR_TRIGSEL, (Trigger << USART_AUTOCR_TRIGSEL_Pos)); +} + +/** + * @brief Get the selected trigger + * @rmtoll AUTOCR TRIGSEL LL_LPUART_GetSelectedTrigger + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_GPDMA1_CH0_TCF_TRG + * @arg @ref LL_LPUART_GPDMA1_CH1_TCF_TRG + * @arg @ref LL_LPUART_GPDMA1_CH2_TCF_TRG + * @arg @ref LL_LPUART_GPDMA1_CH3_TCF_TRG + * @arg @ref LL_LPUART_EXTI_LINE6_TRG + * @arg @ref LL_LPUART_EXTI_LINE8_TRG + * @arg @ref LL_LPUART_LPTIM1_OUT_TRG + * @arg @ref LL_LPUART_COMP1_OUT_TRG (only available of STM32WBA54xx and STM32WBA55xx) + * @arg @ref LL_LPUART_COMP2_OUT_TRG (only available of STM32WBA54xx and STM32WBA55xx) + * @arg @ref LL_LPUART_RTC_ALRA_TRG + * @arg @ref LL_LPUART_RTC_WUT_TRG + */ +__STATIC_INLINE uint32_t LL_LPUART_GetSelectedTrigger(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)((READ_BIT(LPUARTx->AUTOCR, USART_AUTOCR_TRIGSEL) >> USART_AUTOCR_TRIGSEL_Pos)); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup LPUART_LL_EF_Init Initialization and de-initialization functions + * @{ + */ +ErrorStatus LL_LPUART_DeInit(const USART_TypeDef *LPUARTx); +ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, const LL_LPUART_InitTypeDef *LPUART_InitStruct); +void LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct); +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* LPUART1 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WBAxx_LL_LPUART_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_pka.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_pka.h new file mode 100644 index 0000000000..df2c0669d0 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_pka.h @@ -0,0 +1,601 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_ll_pka.h + * @author MCD Application Team + * @brief Header file of PKA LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_LL_PKA_H +#define STM32WBAxx_LL_PKA_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx.h" + +/** @addtogroup STM32WBAxx_LL_Driver + * @{ + */ + +#if defined(PKA) + +/** @defgroup PKA_LL PKA + * @{ + */ + +/* Private variables ---------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup PKA_LL_ES_INIT PKA Exported Init structure + * @{ + */ + +/** + * @brief PKA Init structures definition + */ +typedef struct +{ + uint32_t Mode; /*!< Specifies the PKA operation mode. + This parameter can be a value of @ref PKA_LL_EC_MODE. + + This feature can be modified afterwards using unitary function @ref LL_PKA_SetMode(). */ +} LL_PKA_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup PKA_LL_Exported_Constants PKA Exported Constants + * @{ + */ + +/** @defgroup PKA_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_PKA_ReadReg function + * @{ + */ +#define LL_PKA_SR_ADDRERRF PKA_SR_ADDRERRF +#define LL_PKA_SR_RAMERRF PKA_SR_RAMERRF +#define LL_PKA_SR_PROCENDF PKA_SR_PROCENDF +#define LL_PKA_SR_BUSY PKA_SR_BUSY +#define LL_PKA_SR_INITOK PKA_SR_INITOK +#define LL_PKA_SR_OPERRF PKA_SR_OPERRF +/** + * @} + */ + +/** @defgroup PKA_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_PKA_ReadReg and LL_PKA_WriteReg functions + * @{ + */ +#define LL_PKA_CR_ADDRERRIE PKA_CR_ADDRERRIE +#define LL_PKA_CR_RAMERRIE PKA_CR_RAMERRIE +#define LL_PKA_CR_PROCENDIE PKA_CR_PROCENDIE +#define LL_PKA_CLRFR_PROCENDFC PKA_CLRFR_PROCENDFC +#define LL_PKA_CLRFR_RAMERRFC PKA_CLRFR_RAMERRFC +#define LL_PKA_CLRFR_ADDRERRFC PKA_CLRFR_ADDRERRFC +#define LL_PKA_CR_OPERRIE PKA_CR_OPERRIE +#define LL_PKA_CLRFR_OPERRFC PKA_CLRFR_OPERRFC +/** + * @} + */ + +/** @defgroup PKA_LL_EC_MODE Operation Mode + * @brief List of operation mode. + * @{ + */ +#define LL_PKA_MODE_MODULAR_EXP ((uint32_t)0x00000000U) /*!< modular exponentiation */ +#define LL_PKA_MODE_MONTGOMERY_PARAM ((uint32_t)0x00000001U) /*!< Compute Montgomery parameter only */ +#define LL_PKA_MODE_MODULAR_EXP_FAST ((uint32_t)0x00000002U) /*!< modular exponentiation fast mode */ +#define LL_PKA_MODE_MODULAR_EXP_PROTECT ((uint32_t)0x00000003U) /*!< modular exponentiation protect mode */ +#define LL_PKA_MODE_ECC_MUL ((uint32_t)0x00000020U) /*!< compute ECC kP operation */ +#define LL_PKA_MODE_ECC_COMPLETE_ADD ((uint32_t)0x00000023U) /*!< ECC complete addition */ +#define LL_PKA_MODE_ECDSA_SIGNATURE ((uint32_t)0x00000024U) /*!< ECDSA signature */ +#define LL_PKA_MODE_ECDSA_VERIFICATION ((uint32_t)0x00000026U) /*!< ECDSA verification */ +#define LL_PKA_MODE_POINT_CHECK ((uint32_t)0x00000028U) /*!< Point check */ +#define LL_PKA_MODE_RSA_CRT_EXP ((uint32_t)0x00000007U) /*!< RSA CRT exponentiation */ +#define LL_PKA_MODE_MODULAR_INV ((uint32_t)0x00000008U) /*!< Modular inversion */ +#define LL_PKA_MODE_ARITHMETIC_ADD ((uint32_t)0x00000009U) /*!< Arithmetic addition */ +#define LL_PKA_MODE_ARITHMETIC_SUB ((uint32_t)0x0000000AU) /*!< Arithmetic subtraction */ +#define LL_PKA_MODE_ARITHMETIC_MUL ((uint32_t)0x0000000BU) /*!< Arithmetic multiplication */ +#define LL_PKA_MODE_COMPARISON ((uint32_t)0x0000000CU) /*!< Comparison */ +#define LL_PKA_MODE_MODULAR_REDUC ((uint32_t)0x0000000DU) /*!< Modular reduction */ +#define LL_PKA_MODE_MODULAR_ADD ((uint32_t)0x0000000EU) /*!< Modular addition */ +#define LL_PKA_MODE_MODULAR_SUB ((uint32_t)0x0000000FU) /*!< Modular subtraction */ +#define LL_PKA_MODE_MONTGOMERY_MUL ((uint32_t)0x00000010U) /*!< Montgomery multiplication */ +#define LL_PKA_MODE_DOUBLE_BASE_LADDER ((uint32_t)0x00000027U) /*!< Double base ladder */ +#define LL_PKA_MODE_ECC_PROJECTIVE_AFF ((uint32_t)0x0000002FU) /*!< ECC projective to affine */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup PKA_LL_Exported_Macros PKA Exported Macros + * @{ + */ + +/** @defgroup PKA_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in PKA register + * @param __INSTANCE__ PKA Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_PKA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in PKA register + * @param __INSTANCE__ PKA Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_PKA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup PKA_LL_Exported_Functions PKA Exported Functions + * @{ + */ + +/** @defgroup PKA_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Configure PKA peripheral. + * @brief Set PKA operating mode. + * @rmtoll CR MODE LL_PKA_Config + * @param PKAx PKA Instance. + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_PKA_MODE_MONTGOMERY_PARAM + * @arg @ref LL_PKA_MODE_MODULAR_EXP + * @arg @ref LL_PKA_MODE_ECDSA_SIGNATURE + * @arg @ref LL_PKA_MODE_ECDSA_VERIFICATION + * @arg @ref LL_PKA_MODE_POINT_CHECK + * @arg @ref LL_PKA_MODE_RSA_CRT_EXP + * @arg @ref LL_PKA_MODE_MODULAR_INV + * @arg @ref LL_PKA_MODE_ARITHMETIC_ADD + * @arg @ref LL_PKA_MODE_ARITHMETIC_SUB + * @arg @ref LL_PKA_MODE_ARITHMETIC_MUL + * @arg @ref LL_PKA_MODE_COMPARISON + * @arg @ref LL_PKA_MODE_MODULAR_REDUC + * @arg @ref LL_PKA_MODE_MODULAR_ADD + * @arg @ref LL_PKA_MODE_MODULAR_SUB + * @arg @ref LL_PKA_MODE_MONTGOMERY_MUL + * @arg @ref LL_PKA_MODE_MODULAR_EXP_PROTECT + * @arg @ref LL_PKA_MODE_DOUBLE_BASE_LADDER + * @arg @ref LL_PKA_MODE_ECC_PROJECTIVE_AFF + * @arg @ref LL_PKA_MODE_ECC_COMPLETE_ADD + * @arg @ref LL_PKA_MODE_ECC_MUL + * @arg @ref LL_PKA_MODE_MODULAR_EXP_FAST + */ +__STATIC_INLINE void LL_PKA_Config(PKA_TypeDef *PKAx, uint32_t Mode) +{ + MODIFY_REG(PKAx->CR, (PKA_CR_MODE), (Mode << PKA_CR_MODE_Pos)); +} + +/** + * @brief Enable PKA peripheral. + * @rmtoll CR EN LL_PKA_Enable + * @param PKAx PKA Instance. + * @retval None + */ +__STATIC_INLINE void LL_PKA_Enable(PKA_TypeDef *PKAx) +{ + SET_BIT(PKAx->CR, PKA_CR_EN); +} + +/** + * @brief Disable PKA peripheral. + * @rmtoll CR EN LL_PKA_Disable + * @param PKAx PKA Instance. + * @retval None + */ +__STATIC_INLINE void LL_PKA_Disable(PKA_TypeDef *PKAx) +{ + CLEAR_BIT(PKAx->CR, PKA_CR_EN); +} + +/** + * @brief Check if the PKA peripheral is enabled or disabled. + * @rmtoll CR EN LL_PKA_IsEnabled + * @param PKAx PKA Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PKA_IsEnabled(const PKA_TypeDef *PKAx) +{ + return ((READ_BIT(PKAx->CR, PKA_CR_EN) == (PKA_CR_EN)) ? 1UL : 0UL); +} + +/** + * @brief Set PKA operating mode. + * @rmtoll CR MODE LL_PKA_SetMode + * @param PKAx PKA Instance. + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_PKA_MODE_MONTGOMERY_PARAM + * @arg @ref LL_PKA_MODE_MODULAR_EXP + * @arg @ref LL_PKA_MODE_ECDSA_SIGNATURE + * @arg @ref LL_PKA_MODE_ECDSA_VERIFICATION + * @arg @ref LL_PKA_MODE_POINT_CHECK + * @arg @ref LL_PKA_MODE_RSA_CRT_EXP + * @arg @ref LL_PKA_MODE_MODULAR_INV + * @arg @ref LL_PKA_MODE_ARITHMETIC_ADD + * @arg @ref LL_PKA_MODE_ARITHMETIC_SUB + * @arg @ref LL_PKA_MODE_ARITHMETIC_MUL + * @arg @ref LL_PKA_MODE_COMPARISON + * @arg @ref LL_PKA_MODE_MODULAR_REDUC + * @arg @ref LL_PKA_MODE_MODULAR_ADD + * @arg @ref LL_PKA_MODE_MODULAR_SUB + * @arg @ref LL_PKA_MODE_MONTGOMERY_MUL + * @arg @ref LL_PKA_MODE_MODULAR_EXP_PROTECT + * @arg @ref LL_PKA_MODE_DOUBLE_BASE_LADDER + * @arg @ref LL_PKA_MODE_ECC_PROJECTIVE_AFF + * @arg @ref LL_PKA_MODE_ECC_COMPLETE_ADD + * @arg @ref LL_PKA_MODE_ECC_MUL + * @arg @ref LL_PKA_MODE_MODULAR_EXP_FAST + * @retval None + */ +__STATIC_INLINE void LL_PKA_SetMode(PKA_TypeDef *PKAx, uint32_t Mode) +{ + MODIFY_REG(PKAx->CR, PKA_CR_MODE, Mode << PKA_CR_MODE_Pos); +} + +/** + * @brief Get PKA operating mode. + * @rmtoll CR MODE LL_PKA_GetMode + * @param PKAx PKA Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_PKA_MODE_MONTGOMERY_PARAM + * @arg @ref LL_PKA_MODE_MODULAR_EXP + * @arg @ref LL_PKA_MODE_ECDSA_SIGNATURE + * @arg @ref LL_PKA_MODE_ECDSA_VERIFICATION + * @arg @ref LL_PKA_MODE_POINT_CHECK + * @arg @ref LL_PKA_MODE_RSA_CRT_EXP + * @arg @ref LL_PKA_MODE_MODULAR_INV + * @arg @ref LL_PKA_MODE_ARITHMETIC_ADD + * @arg @ref LL_PKA_MODE_ARITHMETIC_SUB + * @arg @ref LL_PKA_MODE_ARITHMETIC_MUL + * @arg @ref LL_PKA_MODE_COMPARISON + * @arg @ref LL_PKA_MODE_MODULAR_REDUC + * @arg @ref LL_PKA_MODE_MODULAR_ADD + * @arg @ref LL_PKA_MODE_MODULAR_SUB + * @arg @ref LL_PKA_MODE_MONTGOMERY_MUL + * @arg @ref LL_PKA_MODE_MODULAR_EXP_PROTECT + * @arg @ref LL_PKA_MODE_DOUBLE_BASE_LADDER + * @arg @ref LL_PKA_MODE_ECC_PROJECTIVE_AFF + * @arg @ref LL_PKA_MODE_ECC_COMPLETE_ADD + * @arg @ref LL_PKA_MODE_ECC_MUL + * @arg @ref LL_PKA_MODE_MODULAR_EXP_FAST + */ +__STATIC_INLINE uint32_t LL_PKA_GetMode(const PKA_TypeDef *PKAx) +{ + return (uint32_t)(READ_BIT(PKAx->CR, PKA_CR_MODE) >> PKA_CR_MODE_Pos); +} + +/** + * @brief Start the operation selected using LL_PKA_SetMode. + * @rmtoll CR START LL_PKA_Start + * @param PKAx PKA Instance. + * @retval None + */ +__STATIC_INLINE void LL_PKA_Start(PKA_TypeDef *PKAx) +{ + SET_BIT(PKAx->CR, PKA_CR_START); +} + +/** + * @} + */ + +/** @defgroup PKA_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable address error interrupt. + * @rmtoll CR ADDRERRIE LL_PKA_EnableIT_ADDRERR + * @param PKAx PKA Instance. + * @retval None + */ +__STATIC_INLINE void LL_PKA_EnableIT_ADDRERR(PKA_TypeDef *PKAx) +{ + SET_BIT(PKAx->CR, PKA_CR_ADDRERRIE); +} + +/** + * @brief Enable RAM error interrupt. + * @rmtoll CR RAMERRIE LL_PKA_EnableIT_RAMERR + * @param PKAx PKA Instance. + * @retval None + */ +__STATIC_INLINE void LL_PKA_EnableIT_RAMERR(PKA_TypeDef *PKAx) +{ + SET_BIT(PKAx->CR, PKA_CR_RAMERRIE); +} + +/** + * @brief Enable OPERATION error interrupt. + * @rmtoll CR OPERRIE LL_PKA_EnableIT_OPERR + * @param PKAx PKA Instance. + * @retval None + */ +__STATIC_INLINE void LL_PKA_EnableIT_OPERR(PKA_TypeDef *PKAx) +{ + SET_BIT(PKAx->CR, PKA_CR_OPERRIE); +} + +/** + * @brief Enable end of operation interrupt. + * @rmtoll CR PROCENDIE LL_PKA_EnableIT_PROCEND + * @param PKAx PKA Instance. + * @retval None + */ +__STATIC_INLINE void LL_PKA_EnableIT_PROCEND(PKA_TypeDef *PKAx) +{ + SET_BIT(PKAx->CR, PKA_CR_PROCENDIE); +} + +/** + * @brief Disable address error interrupt. + * @rmtoll CR ADDRERRIE LL_PKA_DisableIT_ADDERR + * @param PKAx PKA Instance. + * @retval None + */ +__STATIC_INLINE void LL_PKA_DisableIT_ADDERR(PKA_TypeDef *PKAx) +{ + CLEAR_BIT(PKAx->CR, PKA_CR_ADDRERRIE); +} + +/** + * @brief Disable RAM error interrupt. + * @rmtoll CR RAMERRIE LL_PKA_DisableIT_RAMERR + * @param PKAx PKA Instance. + * @retval None + */ +__STATIC_INLINE void LL_PKA_DisableIT_RAMERR(PKA_TypeDef *PKAx) +{ + CLEAR_BIT(PKAx->CR, PKA_CR_RAMERRIE); +} + +/** + * @brief Disable End of operation interrupt. + * @rmtoll CR PROCENDIE LL_PKA_DisableIT_PROCEND + * @param PKAx PKA Instance. + * @retval None + */ +__STATIC_INLINE void LL_PKA_DisableIT_PROCEND(PKA_TypeDef *PKAx) +{ + CLEAR_BIT(PKAx->CR, PKA_CR_PROCENDIE); +} + +/** + * @brief Disable OPERATION error interrupt. + * @rmtoll CR OPERRIE LL_PKA_EnableIT_OPERR + * @param PKAx PKA Instance. + * @retval None + */ +__STATIC_INLINE void LL_PKA_DisableIT_OPERR(PKA_TypeDef *PKAx) +{ + CLEAR_BIT(PKAx->CR, PKA_CR_OPERRIE); +} + +/** + * @brief Check if address error interrupt is enabled. + * @rmtoll CR ADDRERRIE LL_PKA_IsEnabledIT_ADDRERR + * @param PKAx PKA Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PKA_IsEnabledIT_ADDRERR(const PKA_TypeDef *PKAx) +{ + return ((READ_BIT(PKAx->CR, PKA_CR_ADDRERRIE) == (PKA_CR_ADDRERRIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if RAM error interrupt is enabled. + * @rmtoll CR RAMERRIE LL_PKA_IsEnabledIT_RAMERR + * @param PKAx PKA Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PKA_IsEnabledIT_RAMERR(const PKA_TypeDef *PKAx) +{ + return ((READ_BIT(PKAx->CR, PKA_CR_RAMERRIE) == (PKA_CR_RAMERRIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if OPERATION error interrupt is enabled. + * @rmtoll CR OPERRIE LL_PKA_IsEnabledIT_OPERR + * @param PKAx PKA Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PKA_IsEnabledIT_OPERR(const PKA_TypeDef *PKAx) +{ + return ((READ_BIT(PKAx->CR, PKA_CR_OPERRIE) == (PKA_CR_OPERRIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if end of operation interrupt is enabled. + * @rmtoll CR PROCENDIE LL_PKA_IsEnabledIT_PROCEND + * @param PKAx PKA Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PKA_IsEnabledIT_PROCEND(const PKA_TypeDef *PKAx) +{ + return ((READ_BIT(PKAx->CR, PKA_CR_PROCENDIE) == (PKA_CR_PROCENDIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup PKA_LL_EF_FLAG_Management PKA flag management + * @{ + */ + +/** + * @brief Get PKA address error flag. + * @rmtoll SR ADDRERRF LL_PKA_IsActiveFlag_ADDRERR + * @param PKAx PKA Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_ADDRERR(const PKA_TypeDef *PKAx) +{ + return ((READ_BIT(PKAx->SR, PKA_SR_ADDRERRF) == (PKA_SR_ADDRERRF)) ? 1UL : 0UL); +} + +/** + * @brief Get PKA RAM error flag. + * @rmtoll SR RAMERRF LL_PKA_IsActiveFlag_RAMERR + * @param PKAx PKA Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_RAMERR(const PKA_TypeDef *PKAx) +{ + return ((READ_BIT(PKAx->SR, PKA_SR_RAMERRF) == (PKA_SR_RAMERRF)) ? 1UL : 0UL); +} + +/** + * @brief Get PKA OPERATION error flag. + * @rmtoll SR OPERRF LL_PKA_IsActiveFlag_OPERR + * @param PKAx PKA Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_OPERR(const PKA_TypeDef *PKAx) +{ + return ((READ_BIT(PKAx->SR, PKA_SR_OPERRF) == (PKA_SR_OPERRF)) ? 1UL : 0UL); +} + +/** + * @brief Get PKA end of operation flag. + * @rmtoll SR PROCENDF LL_PKA_IsActiveFlag_PROCEND + * @param PKAx PKA Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_PROCEND(const PKA_TypeDef *PKAx) +{ + return ((READ_BIT(PKAx->SR, PKA_SR_PROCENDF) == (PKA_SR_PROCENDF)) ? 1UL : 0UL); +} + +/** + * @brief Get PKA busy flag. + * @rmtoll SR BUSY LL_PKA_IsActiveFlag_BUSY + * @param PKAx PKA Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_BUSY(const PKA_TypeDef *PKAx) +{ + return ((READ_BIT(PKAx->SR, PKA_SR_BUSY) == (PKA_SR_BUSY)) ? 1UL : 0UL); +} + +/** + * @brief Clear PKA address error flag. + * @rmtoll CLRFR ADDRERRFC LL_PKA_ClearFlag_ADDERR + * @param PKAx PKA Instance. + * @retval None + */ +__STATIC_INLINE void LL_PKA_ClearFlag_ADDERR(PKA_TypeDef *PKAx) +{ + SET_BIT(PKAx->CLRFR, PKA_CLRFR_ADDRERRFC); +} + +/** + * @brief Clear PKA RAM error flag. + * @rmtoll CLRFR RAMERRFC LL_PKA_ClearFlag_RAMERR + * @param PKAx PKA Instance. + * @retval None + */ +__STATIC_INLINE void LL_PKA_ClearFlag_RAMERR(PKA_TypeDef *PKAx) +{ + SET_BIT(PKAx->CLRFR, PKA_CLRFR_RAMERRFC); +} + +/** + * @brief Clear PKA OPERATION error flag. + * @rmtoll CLRFR OPERRFC LL_PKA_ClearFlag_OPERR + * @param PKAx PKA Instance. + * @retval None + */ +__STATIC_INLINE void LL_PKA_ClearFlag_OPERR(PKA_TypeDef *PKAx) +{ + SET_BIT(PKAx->CLRFR, PKA_CLRFR_OPERRFC); +} + +/** + * @brief Clear PKA end of operation flag. + * @rmtoll CLRFR PROCENDFC LL_PKA_ClearFlag_PROCEND + * @param PKAx PKA Instance. + * @retval None + */ +__STATIC_INLINE void LL_PKA_ClearFlag_PROCEND(PKA_TypeDef *PKAx) +{ + SET_BIT(PKAx->CLRFR, PKA_CLRFR_PROCENDFC); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) + +/** @defgroup PKA_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_PKA_DeInit(const PKA_TypeDef *PKAx); +ErrorStatus LL_PKA_Init(PKA_TypeDef *PKAx, LL_PKA_InitTypeDef *PKA_InitStruct); +void LL_PKA_StructInit(LL_PKA_InitTypeDef *PKA_InitStruct); + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(PKA) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WBAxx_LL_PKA_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_pwr.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_pwr.h new file mode 100644 index 0000000000..23eac9fdda --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_pwr.h @@ -0,0 +1,1802 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_ll_pwr.h + * @author MCD Application Team + * @brief Header file of PWR LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_LL_PWR_H +#define STM32WBAxx_LL_PWR_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx.h" + +/** @addtogroup STM32WBAxx_LL_Driver + * @{ + */ + +#if defined (PWR) + +/** @defgroup PWR_LL PWR + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants + * @{ + */ + +/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_PWR_WriteReg function + * @{ + */ +#define LL_PWR_SR_CSSF PWR_SR_CSSF /*!< Clear Stop and Standby flags */ +#define LL_PWR_WUSCR_CWUF1 PWR_WUSCR_CWUF1 /*!< Clear Wakeup flag 1 */ +#define LL_PWR_WUSCR_CWUF2 PWR_WUSCR_CWUF2 /*!< Clear Wakeup flag 2 */ +#define LL_PWR_WUSCR_CWUF3 PWR_WUSCR_CWUF3 /*!< Clear Wakeup flag 3 */ +#define LL_PWR_WUSCR_CWUF4 PWR_WUSCR_CWUF4 /*!< Clear Wakeup flag 4 */ +#define LL_PWR_WUSCR_CWUF5 PWR_WUSCR_CWUF5 /*!< Clear Wakeup flag 5 */ +#define LL_PWR_WUSCR_CWUF6 PWR_WUSCR_CWUF6 /*!< Clear Wakeup flag 6 */ +#define LL_PWR_WUSCR_CWUF7 PWR_WUSCR_CWUF7 /*!< Clear Wakeup flag 7 */ +#define LL_PWR_WUSCR_CWUF8 PWR_WUSCR_CWUF8 /*!< Clear Wakeup flag 8 */ +#define LL_PWR_WUSCR_CWUF_ALL PWR_WUSCR_CWUF /*!< Clear all Wakeup flags */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_PWR_ReadReg function + * @{ + */ +#define LL_PWR_FLAG_VOSRDY PWR_VOSR_VOSRDY /*!< Voltage scaling ready flag */ +#define LL_PWR_FLAG_STOPF PWR_SR_STOPF /*!< Stop flag */ +#define LL_PWR_FLAG_SBF PWR_SR_SBF /*!< Standby flag */ +#define LL_PWR_FLAG_ACTVOSRDY PWR_SVMSR_ACTVOSRDY /*!< Currently applied VOS ready flag */ +#define LL_PWR_FLAG_PVDO PWR_SVMSR_PVDO /*!< VDD voltage detector output flag */ +#define LL_PWR_FLAG_REGS PWR_SVMSR_REGS /*!< Regulator selection flag */ + +#define LL_PWR_WAKEUP_FLAG1 PWR_WUSR_WUF1 /*!< Wakeup flag 1 */ +#define LL_PWR_WAKEUP_FLAG2 PWR_WUSR_WUF2 /*!< Wakeup flag 2 */ +#define LL_PWR_WAKEUP_FLAG3 PWR_WUSR_WUF3 /*!< Wakeup flag 3 */ +#define LL_PWR_WAKEUP_FLAG4 PWR_WUSR_WUF4 /*!< Wakeup flag 4 */ +#define LL_PWR_WAKEUP_FLAG5 PWR_WUSR_WUF5 /*!< Wakeup flag 5 */ +#define LL_PWR_WAKEUP_FLAG6 PWR_WUSR_WUF6 /*!< Wakeup flag 6 */ +#define LL_PWR_WAKEUP_FLAG7 PWR_WUSR_WUF7 /*!< Wakeup flag 7 */ +#define LL_PWR_WAKEUP_FLAG8 PWR_WUSR_WUF8 /*!< Wakeup flag 8 */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_LOW_POWER_MODE_SELECTION Low Power Mode Selection + * @{ + */ +#define LL_PWR_MODE_STOP0 0U /*!< Stop 0 mode */ +#define LL_PWR_MODE_STOP1 PWR_CR1_LPMS_0 /*!< Stop 1 mode */ +#define LL_PWR_MODE_STANDBY PWR_CR1_LPMS_2 /*!< Standby mode */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_SRAM1_SB_RETENTION PWR SRAM1 Retention in Standby Mode + * @{ + */ +#define LL_PWR_SRAM1_SB_NO_RETENTION 0U /*!< SRAM1 no retention in Standby mode */ +#define LL_PWR_SRAM1_SB_FULL_RETENTION PWR_CR1_R1RSB1 /*!< SRAM1 all pages retention in Standby mode */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_SRAM2_SB_RETENTION PWR SRAM2 Retention in Standby Mode + * @{ + */ +#define LL_PWR_SRAM2_SB_NO_RETENTION 0U /*!< SRAM2 no retention in Standby mode */ +#define LL_PWR_SRAM2_SB_FULL_RETENTION PWR_CR1_R2RSB1 /*!< SRAM2 all pages retention in Standby mode */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_RADIO_SB_RETENTION PWR RADIO SRAMs and Sleep Clock Retention in Standby Mode + * @{ + */ +#define LL_PWR_RADIO_SB_NO_RETENTION 0U /*!< 2.4 GHz RADIO SRAMs and sleep timer content not retained in Standby mode */ +#define LL_PWR_RADIO_SB_FULL_RETENTION PWR_CR1_RADIORSB /*!< 2.4 GHz RADIO SRAMs and sleep timer content retained in Standby mode */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_SRAM1_STOP_RETENTION PWR SRAM1 Retention in Stop Mode + * @{ + */ +#define LL_PWR_SRAM1_STOP_NO_RETENTION 0U /*!< SRAM1 no retention in Stop mode */ +#define LL_PWR_SRAM1_STOP_FULL_RETENTION PWR_CR2_SRAM1PDS1 /*!< SRAM1 all pages retention in Stop mode */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_SRAM2_STOP_RETENTION PWR SRAM2 Retention in Stop Mode + * @{ + */ +#define LL_PWR_SRAM2_STOP_NO_RETENTION 0U /*!< SRAM2 no retention in Stop mode */ +#define LL_PWR_SRAM2_STOP_FULL_RETENTION PWR_CR2_SRAM2PDS1 /*!< SRAM2 all pages retention in Stop mode */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_ICACHERAM_STOP_RETENTION PWR ICACHE SRAM Retention in Stop Mode + * @{ + */ +#define LL_PWR_ICACHERAM_STOP_NO_RETENTION 0U /*!< ICACHE SRAM no retention in Stop mode */ +#define LL_PWR_ICACHERAM_STOP_FULL_RETENTION PWR_CR2_ICRAMPDS /*!< ICACHE SRAM full retention in Stop mode */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_SMPS_PWM_MODE PWR SMPS PWM mode + * @{ + */ +#define LL_PWR_SMPS_NO_PWM_MODE 0U /*!< SMPS PWM mode disabled (high-efficiency mode) */ +#define LL_PWR_SMPS_PWM_MODE PWR_CR2_FPWM /*!< SMPS PWM mode enabled (harmonic reduction) */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_REGULATOR_SUPPLY_SELECTION PWR Regulator Supply Selection + * @{ + */ +#define LL_PWR_LDO_SUPPLY 0U /*!< LDO regulator supply */ +#define LL_PWR_SMPS_SUPPLY PWR_CR3_REGSEL /*!< SMPS regulator supply */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_REGULATOR_VDDHPA_SUPPLY_SELECTION PWR Regulator REG_VDDHPA input supply selection + * @{ + */ +#define LL_PWR_REG_VDDHPA_VDDRFPA_PIN 0U /*!< VDDRFPA pin selected as regulator REG_VDDHPA input supply */ +#define LL_PWR_REG_VDDHPA_VDDRFPA_VDD11 PWR_RADIOSCR_REGPASEL /*!< Regulator REG_VDDHPA input supply selection between VDDRFPA and VDD11 dependent on requested regulated output voltage */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_RADIO_PHY_MODE PWR 2.4 GHz RADIO PHY operating mode + * @{ + */ +#define LL_PWR_RADIO_PHY_SLEEP_MODE 0U /*!< 2.4 GHz RADIO Sleep mode */ +#define LL_PWR_RADIO_PHY_STANDBY_MODE PWR_RADIOSCR_PHYMODE /*!< 2.4 GHz RADIO Standby mode */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_RADIO_OPERATING_MODE PWR 2.4 GHz RADIO operating mode + * @{ + */ +#define LL_PWR_RADIO_DEEP_SLEEP_MODE 0U /*!< 2.4 GHz RADIO Deep Sleep mode */ +#define LL_PWR_RADIO_SLEEP_MODE PWR_RADIOSCR_MODE_0 /*!< 2.4 GHz RADIO Sleep mode */ +#define LL_PWR_RADIO_ACTIVE_MODE PWR_RADIOSCR_MODE_1 /*!< 2.4 GHz RADIO Active mode */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_VOLTAGE_SCALING_RANGE_SELECTION PWR Voltage scaling range selection + * @{ + */ +#define LL_PWR_REGU_VOLTAGE_SCALE1 PWR_VOSR_VOS /*!< Voltage scaling range 1 (highest frequency) */ +#define LL_PWR_REGU_VOLTAGE_SCALE2 0U /*!< Voltage scaling range 2 (lowest power) */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_PVD_LEVEL_SELECTION PWR Power Voltage Detector Level Selection + * @{ + */ +#define LL_PWR_PVDLEVEL_0 0U /*!< Voltage threshold detected by PVD 2.0 V */ +#define LL_PWR_PVDLEVEL_1 PWR_SVMCR_PVDLS_0 /*!< Voltage threshold detected by PVD 2.2 V */ +#define LL_PWR_PVDLEVEL_2 PWR_SVMCR_PVDLS_1 /*!< Voltage threshold detected by PVD 2.4 V */ +#define LL_PWR_PVDLEVEL_3 (PWR_SVMCR_PVDLS_0 | PWR_SVMCR_PVDLS_1) /*!< Voltage threshold detected by PVD 2.5 V */ +#define LL_PWR_PVDLEVEL_4 PWR_SVMCR_PVDLS_2 /*!< Voltage threshold detected by PVD 2.6 V */ +#define LL_PWR_PVDLEVEL_5 (PWR_SVMCR_PVDLS_0 | PWR_SVMCR_PVDLS_2) /*!< Voltage threshold detected by PVD 2.8 V */ +#define LL_PWR_PVDLEVEL_6 (PWR_SVMCR_PVDLS_1 | PWR_SVMCR_PVDLS_2) /*!< Voltage threshold detected by PVD 2.9 V */ +#define LL_PWR_PVDLEVEL_7 PWR_SVMCR_PVDLS /*!< External input analog voltage on PVD_IN + pin, compared to internal VREFINT level */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_WAKEUP_PIN PWR Wake Up Pin + * @{ + */ +#define LL_PWR_WAKEUP_PIN1 PWR_WUCR1_WUPEN1 /*!< Wakeup pin 1 enable */ +#define LL_PWR_WAKEUP_PIN2 PWR_WUCR1_WUPEN2 /*!< Wakeup pin 2 enable */ +#define LL_PWR_WAKEUP_PIN3 PWR_WUCR1_WUPEN3 /*!< Wakeup pin 3 enable */ +#define LL_PWR_WAKEUP_PIN4 PWR_WUCR1_WUPEN4 /*!< Wakeup pin 4 enable */ +#define LL_PWR_WAKEUP_PIN5 PWR_WUCR1_WUPEN5 /*!< Wakeup pin 5 enable */ +#define LL_PWR_WAKEUP_PIN6 PWR_WUCR1_WUPEN6 /*!< Wakeup pin 6 enable */ +#define LL_PWR_WAKEUP_PIN7 PWR_WUCR1_WUPEN7 /*!< Wakeup pin 7 enable */ +#define LL_PWR_WAKEUP_PIN8 PWR_WUCR1_WUPEN8 /*!< Wakeup pin 8 enable */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_WAKEUP_PIN_SELECTION PWR Wakeup Pin Selection + * @{ + */ +#define LL_PWR_WAKEUP_PIN_SELECTION_0 0UL /*!< Wakeup pin selection 0 */ +#define LL_PWR_WAKEUP_PIN_SELECTION_1 PWR_WUCR3_WUSEL1_0 /*!< Wakeup pin selection 1 */ +#define LL_PWR_WAKEUP_PIN_SELECTION_2 PWR_WUCR3_WUSEL1_1 /*!< Wakeup pin selection 2 */ +#define LL_PWR_WAKEUP_PIN_SELECTION_3 PWR_WUCR3_WUSEL1 /*!< Wakeup pin selection 3 */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_GPIO_STATE_RETENTION_ENABLE_SELECTION PWR GPIO State Retention Enable Port Selection + * @{ + */ +#define LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTA (uint32_t)(&(PWR->IORETENRA)) /*!< GPIO port A */ +#define LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTB (uint32_t)(&(PWR->IORETENRB)) /*!< GPIO port B */ +#define LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTC (uint32_t)(&(PWR->IORETENRC)) /*!< GPIO port C */ +#define LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTH (uint32_t)(&(PWR->IORETENRH)) /*!< GPIO port H */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_GPIO_STATE_RETENTION_STATUS_SELECTION PWR GPIO State Retention Status Port Selection + * @{ + */ +#define LL_PWR_GPIO_STATE_RETENTION_STATUS_PORTA (uint32_t)(&(PWR->IORETRA)) /*!< GPIO port A */ +#define LL_PWR_GPIO_STATE_RETENTION_STATUS_PORTB (uint32_t)(&(PWR->IORETRB)) /*!< GPIO port B */ +#define LL_PWR_GPIO_STATE_RETENTION_STATUS_PORTC (uint32_t)(&(PWR->IORETRC)) /*!< GPIO port C */ +#define LL_PWR_GPIO_STATE_RETENTION_STATUS_PORTH (uint32_t)(&(PWR->IORETRH)) /*!< GPIO port H */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_GPIO_PIN_MASK PWR GPIO Pin Mask + * @{ + */ +#define LL_PWR_GPIO_PIN_0 (0x0001U) /*!< GPIO port I/O pin 0 */ +#define LL_PWR_GPIO_PIN_1 (0x0002U) /*!< GPIO port I/O pin 1 */ +#define LL_PWR_GPIO_PIN_2 (0x0004U) /*!< GPIO port I/O pin 2 */ +#define LL_PWR_GPIO_PIN_3 (0x0008U) /*!< GPIO port I/O pin 3 */ +#define LL_PWR_GPIO_PIN_4 (0x0010U) /*!< GPIO port I/O pin 4 */ +#define LL_PWR_GPIO_PIN_5 (0x0020U) /*!< GPIO port I/O pin 5 */ +#define LL_PWR_GPIO_PIN_6 (0x0040U) /*!< GPIO port I/O pin 6 */ +#define LL_PWR_GPIO_PIN_7 (0x0080U) /*!< GPIO port I/O pin 7 */ +#define LL_PWR_GPIO_PIN_8 (0x0100U) /*!< GPIO port I/O pin 8 */ +#define LL_PWR_GPIO_PIN_9 (0x0200U) /*!< GPIO port I/O pin 9 */ +#define LL_PWR_GPIO_PIN_10 (0x0400U) /*!< GPIO port I/O pin 10 */ +#define LL_PWR_GPIO_PIN_11 (0x0800U) /*!< GPIO port I/O pin 11 */ +#define LL_PWR_GPIO_PIN_12 (0x1000U) /*!< GPIO port I/O pin 12 */ +#define LL_PWR_GPIO_PIN_13 (0x2000U) /*!< GPIO port I/O pin 13 */ +#define LL_PWR_GPIO_PIN_14 (0x4000U) /*!< GPIO port I/O pin 14 */ +#define LL_PWR_GPIO_PIN_15 (0x8000U) /*!< GPIO port I/O pin 15 */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_ITEMS_SECURE_ATTRIBUTE PWR Items Secure Attribute + * @{ + */ +#define LL_PWR_WAKEUP_PIN1_NSEC 0U /*!< Wake up pin 1 nsecure mode */ +#define LL_PWR_WAKEUP_PIN1_SEC PWR_SECCFGR_WUP1SEC /*!< Wake up pin 1 secure mode */ +#define LL_PWR_WAKEUP_PIN2_NSEC 0U /*!< Wake up pin 2 nsecure mode */ +#define LL_PWR_WAKEUP_PIN2_SEC PWR_SECCFGR_WUP2SEC /*!< Wake up pin 2 secure mode */ +#define LL_PWR_WAKEUP_PIN3_NSEC 0U /*!< Wake up pin 3 nsecure mode */ +#define LL_PWR_WAKEUP_PIN3_SEC PWR_SECCFGR_WUP3SEC /*!< Wake up pin 3 secure mode */ +#define LL_PWR_WAKEUP_PIN4_NSEC 0U /*!< Wake up pin 4 nsecure mode */ +#define LL_PWR_WAKEUP_PIN4_SEC PWR_SECCFGR_WUP4SEC /*!< Wake up pin 4 secure mode */ +#define LL_PWR_WAKEUP_PIN5_NSEC 0U /*!< Wake up pin 5 nsecure mode */ +#define LL_PWR_WAKEUP_PIN5_SEC PWR_SECCFGR_WUP5SEC /*!< Wake up pin 5 secure mode */ +#define LL_PWR_WAKEUP_PIN6_NSEC 0U /*!< Wake up pin 6 nsecure mode */ +#define LL_PWR_WAKEUP_PIN6_SEC PWR_SECCFGR_WUP6SEC /*!< Wake up pin 6 secure mode */ +#define LL_PWR_WAKEUP_PIN7_NSEC 0U /*!< Wake up pin 7 nsecure mode */ +#define LL_PWR_WAKEUP_PIN7_SEC PWR_SECCFGR_WUP7SEC /*!< Wake up pin 7 secure mode */ +#define LL_PWR_WAKEUP_PIN8_NSEC 0U /*!< Wake up pin 8 nsecure mode */ +#define LL_PWR_WAKEUP_PIN8_SEC PWR_SECCFGR_WUP8SEC /*!< Wake up pin 8 secure mode */ + +#define LL_PWR_LPM_NSEC 0U /*!< Low-power modes nsecure mode */ +#define LL_PWR_LPM_SEC PWR_SECCFGR_LPMSEC /*!< Low-power modes secure mode */ +#define LL_PWR_VDM_NSEC 0U /*!< Voltage detection and monitoring nsecure mode */ +#define LL_PWR_VDM_SEC PWR_SECCFGR_VDMSEC /*!< Voltage detection and monitoring secure mode */ +#define LL_PWR_VB_NSEC 0U /*!< Backup domain nsecure mode */ +#define LL_PWR_VB_SEC PWR_SECCFGR_VBSEC /*!< Backup domain secure mode */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros + * @{ + */ + +/** @defgroup PWR_LL_EM_WRITE_READ Common Write and Read Registers Macros + * @{ + */ + +/** + * @brief Write a value in PWR register. + * @param __REG__ Register to be written. + * @param __VALUE__ Value to be written in the register. + * @retval None. + */ +#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__)) + +/** + * @brief Read a value in PWR register. + * @param __REG__ Register to be read. + * @retval Register value. + */ +#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @defgroup PWR_LL_EF_CONFIGURATION PWR Configuration + * @{ + */ + +/** + * @brief Set system power mode. + * @rmtoll CR1 LPMS LL_PWR_SetPowerMode + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_PWR_MODE_STOP0 + * @arg @ref LL_PWR_MODE_STOP1 + * @arg @ref LL_PWR_MODE_STANDBY + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t Mode) +{ + MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, Mode); +} + +/** + * @brief Get system power mode. + * @rmtoll CR1 LPMS LL_PWR_GetPowerMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_MODE_STOP0 + * @arg @ref LL_PWR_MODE_STOP1 + * @arg @ref LL_PWR_MODE_STANDBY + */ +__STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void) +{ + return (READ_BIT(PWR->CR1, PWR_CR1_LPMS)); +} + +/** + * @brief Set the SRAM2 page(s) retention in Standby mode. + * @rmtoll CR1 R2RSB1 LL_PWR_SetSRAM2SBRetention + * @param SRAM2PageRetention This parameter can be one of the following values: + * @arg @ref LL_PWR_SRAM2_SB_NO_RETENTION + * @arg @ref LL_PWR_SRAM2_SB_FULL_RETENTION + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetSRAM2SBRetention(uint32_t SRAM2PageRetention) +{ + MODIFY_REG(PWR->CR1, PWR_CR1_R2RSB1, SRAM2PageRetention); +} + +/** + * @brief Get the SRAM2 page(s) retention in Standby mode. + * @rmtoll CR1 R2RSB1 LL_PWR_GetSRAM2SBRetention + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_SRAM2_SB_NO_RETENTION + * @arg @ref LL_PWR_SRAM2_SB_FULL_RETENTION + */ +__STATIC_INLINE uint32_t LL_PWR_GetSRAM2SBRetention(void) +{ + return (READ_BIT(PWR->CR1, PWR_CR1_R2RSB1)); +} + +/** + * @brief Set the SRAM1 page(s) retention in Standby mode. + * @rmtoll CR1 R1RSB1 LL_PWR_SetSRAM1SBRetention + * @param SRAM1PageRetention This parameter can be one of the following values: + * @arg @ref LL_PWR_SRAM1_SB_NO_RETENTION + * @arg @ref LL_PWR_SRAM1_SB_FULL_RETENTION + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetSRAM1SBRetention(uint32_t SRAM1PageRetention) +{ + MODIFY_REG(PWR->CR1, PWR_CR1_R1RSB1, SRAM1PageRetention); +} + +/** + * @brief Get the SRAM1 page(s) retention in Standby mode. + * @rmtoll CR1 R1RSB1 LL_PWR_GetSRAM1SBRetention + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_SRAM1_SB_NO_RETENTION + * @arg @ref LL_PWR_SRAM1_SB_FULL_RETENTION + */ +__STATIC_INLINE uint32_t LL_PWR_GetSRAM1SBRetention(void) +{ + return (READ_BIT(PWR->CR1, PWR_CR1_R1RSB1)); +} + +/** + * @brief Set the Radio retention in Standby mode. + * @rmtoll CR1 RADIORSB LL_PWR_SetRadioSBRetention + * @param RadioRetention This parameter can be one of the following values: + * @arg @ref LL_PWR_RADIO_SB_NO_RETENTION + * @arg @ref LL_PWR_RADIO_SB_FULL_RETENTION + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetRadioSBRetention(uint32_t RadioRetention) +{ + MODIFY_REG(PWR->CR1, PWR_CR1_RADIORSB, RadioRetention); +} + +/** + * @brief Get the Radio retention in Standby mode. + * @rmtoll CR1 RADIORSB LL_PWR_GetRadioSBRetention + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_RADIO_SB_NO_RETENTION + * @arg @ref LL_PWR_RADIO_SB_FULL_RETENTION + */ +__STATIC_INLINE uint32_t LL_PWR_GetRadioSBRetention(void) +{ + return (READ_BIT(PWR->CR1, PWR_CR1_RADIORSB)); +} + +/** + * @brief Enable BOR ultra low power mode. + * @rmtoll CR1 UPLMEN LL_PWR_EnableUltraLowPowerMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableUltraLowPowerMode(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_ULPMEN); +} + +/** + * @brief Disable BOR ultra low-power mode. + * @rmtoll CR1 UPLMEN LL_PWR_DisableUltraLowPowerMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableUltraLowPowerMode(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_ULPMEN); +} + +/** + * @brief Check if BOR ultra low power mode is enabled. + * @rmtoll CR1 UPLMEN LL_PWR_IsEnabledUltraLowPowerMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledUltraLowPowerMode(void) +{ + return ((READ_BIT(PWR->CR1, PWR_CR1_ULPMEN) == (PWR_CR1_ULPMEN)) ? 1UL : 0UL); +} + + +/** + * @brief Set the SRAM1 page(s) retention in Stop mode. + * @rmtoll CR2 SRAM1PDS1 LL_PWR_SetSRAM1StopRetention + * @param SRAM1PageRetention This parameter can be one of the following values: + * @arg @ref LL_PWR_SRAM1_STOP_NO_RETENTION + * @arg @ref LL_PWR_SRAM1_STOP_FULL_RETENTION + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetSRAM1StopRetention(uint32_t SRAM1PageRetention) +{ + MODIFY_REG(PWR->CR2, PWR_CR2_SRAM1PDS1, ((~SRAM1PageRetention) & PWR_CR2_SRAM1PDS1)); +} + +/** + * @brief Get the SRAM1 page(s) retention in Stop mode. + * @rmtoll CR2 SRAM1PDS1 LL_PWR_GetSRAM1StopRetention + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_SRAM1_STOP_NO_RETENTION + * @arg @ref LL_PWR_SRAM1_STOP_FULL_RETENTION + */ +__STATIC_INLINE uint32_t LL_PWR_GetSRAM1StopRetention(void) +{ + return ((~(READ_BIT(PWR->CR2, PWR_CR2_SRAM1PDS1))) & PWR_CR2_SRAM1PDS1); +} + +/** + * @brief Set the SRAM2 page(s) retention in Stop mode. + * @rmtoll CR2 SRAM2PDS1 LL_PWR_SetSRAM2StopRetention + * @param SRAM2PageRetention This parameter can be one of the following values: + * @arg @ref LL_PWR_SRAM2_STOP_NO_RETENTION + * @arg @ref LL_PWR_SRAM2_STOP_FULL_RETENTION + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetSRAM2StopRetention(uint32_t SRAM2PageRetention) +{ + MODIFY_REG(PWR->CR2, PWR_CR2_SRAM2PDS1, ((~SRAM2PageRetention) & PWR_CR2_SRAM2PDS1)); +} + +/** + * @brief Get the SRAM2 page(s) retention in Stop mode. + * @rmtoll CR2 SRAM2PDS1 LL_PWR_GetSRAM2StopRetention + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_SRAM2_STOP_NO_RETENTION + * @arg @ref LL_PWR_SRAM2_STOP_FULL_RETENTION + */ +__STATIC_INLINE uint32_t LL_PWR_GetSRAM2StopRetention(void) +{ + return ((~(READ_BIT(PWR->CR2, PWR_CR2_SRAM2PDS1))) & PWR_CR2_SRAM2PDS1); +} + +/** + * @brief Set the ICACHE SRAM page(s) retention in Stop mode. + * @rmtoll CR2 ICRAMPDS LL_PWR_SetICacheRAMStopRetention +#if defined(STM32WBAXX_SI_CUT1_0) + * @note On Silicon Cut 1.0, it is mandatory to disable the ICACHE before going into + * stop modes otherwise an hard fault may occur when waking up from stop modes. +#endif + * @param ICRAMPageRetention This parameter can be one of the following values: + * @arg @ref LL_PWR_ICACHERAM_STOP_NO_RETENTION + * @arg @ref LL_PWR_ICACHERAM_STOP_FULL_RETENTION + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetICacheRAMStopRetention(uint32_t ICRAMPageRetention) +{ + MODIFY_REG(PWR->CR2, PWR_CR2_ICRAMPDS, + ((~ICRAMPageRetention) & PWR_CR2_ICRAMPDS)); +} + +/** + * @brief Get the ICACHE SRAM page(s) retention in Stop mode. + * @rmtoll CR2 ICRAMPDS LL_PWR_GetICacheRAMStopRetention + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_ICACHERAM_STOP_NO_RETENTION + * @arg @ref LL_PWR_ICACHERAM_STOP_FULL_RETENTION + */ +__STATIC_INLINE uint32_t LL_PWR_GetICacheRAMStopRetention(void) +{ + return ((~(READ_BIT(PWR->CR2, PWR_CR2_ICRAMPDS))) & PWR_CR2_ICRAMPDS); +} + +/** + * @brief Enable the flash memory fast wakeup from Stop mode (Stop 0, 1). + * @rmtoll CR2 FLASHFWU LL_PWR_EnableFlashFastWakeUp + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableFlashFastWakeUp(void) +{ + SET_BIT(PWR->CR2, PWR_CR2_FLASHFWU); +} + +/** + * @brief Disable the flash memory fast wakeup from Stop mode (Stop 0, 1). + * @rmtoll CR2 FLASHFWU LL_PWR_DisableFlashFastWakeUp + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableFlashFastWakeUp(void) +{ + CLEAR_BIT(PWR->CR2, PWR_CR2_FLASHFWU); +} + +/** + * @brief Check if the flash memory fast wakeup from Stop mode (Stop 0, 1) is enabled. + * @rmtoll CR2 FLASHFWU LL_PWR_IsEnabledFlashFastWakeUp + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledFlashFastWakeUp(void) +{ + return ((READ_BIT(PWR->CR2, PWR_CR2_FLASHFWU) == (PWR_CR2_FLASHFWU)) ? 1UL : 0UL); +} + +#if defined(PWR_CR3_REGSEL) +/** + * @brief Set the VCore regulator supply. + * @rmtoll CR3 REGSEL LL_PWR_SetRegulatorSupply + * @param RegulatorSupply This parameter can be one of the following values: + * @arg @ref LL_PWR_LDO_SUPPLY + * @arg @ref LL_PWR_SMPS_SUPPLY + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetRegulatorSupply(uint32_t RegulatorSupply) +{ + MODIFY_REG(PWR->CR3, PWR_CR3_REGSEL, RegulatorSupply); +} + +/** + * @brief Get the VCore regulator supply. + * @rmtoll CR3 REGSEL LL_PWR_GetRegulatorSupply + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_LDO_SUPPLY + * @arg @ref LL_PWR_SMPS_SUPPLY + */ +__STATIC_INLINE uint32_t LL_PWR_GetRegulatorSupply(void) +{ + return (READ_BIT(PWR->CR3, PWR_CR3_REGSEL)); +} +#endif /* PWR_CR3_REGSEL */ + +#if defined(PWR_CR2_FPWM) +/** + * @brief Enable the SMPS PWM mode. + * @rmtoll CR2 FPWM LL_PWR_EnableSMPSPWMMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableSMPSPWMMode(void) +{ + SET_BIT(PWR->CR2, PWR_CR2_FPWM); +} + +/** + * @brief Disable the SMPS PWM mode. + * @rmtoll CR2 FPWM LL_PWR_DisableSMPSPWMMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableSMPSPWMMode(void) +{ + CLEAR_BIT(PWR->CR2, PWR_CR2_FPWM); +} + +/** + * @brief Check if the SMPS PWM mode is enabled. + * @rmtoll CR2 FPWM LL_PWR_IsEnabledSMPSPWMMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledSMPSPWMMode(void) +{ + return ((READ_BIT(PWR->CR2, PWR_CR2_FPWM) == (PWR_CR2_FPWM)) ? 1UL : 0UL); +} +#endif /* PWR_CR2_FPWM */ + +/** + * @brief Enable the fast soft start for selected regulator. + * @rmtoll CR3 FSTEN LL_PWR_EnableFastSoftStart + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableFastSoftStart(void) +{ + SET_BIT(PWR->CR3, PWR_CR3_FSTEN); +} + +/** + * @brief Disable the fast soft start for selected regulator. + * @rmtoll CR3 FSTEN LL_PWR_DisableFastSoftStart + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableFastSoftStart(void) +{ + CLEAR_BIT(PWR->CR3, PWR_CR3_FSTEN); +} + +/** + * @brief Check if the fast soft start for selected regulator is enabled. + * @rmtoll CR3 FSTEN LL_PWR_IsEnabledFastSoftStart + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledFastSoftStart(void) +{ + return ((READ_BIT(PWR->CR3, PWR_CR3_FSTEN) == (PWR_CR3_FSTEN)) ? 1UL : 0UL); +} + +/** + * @brief Set the regulator supply output voltage. + * @rmtoll VOSR VOS LL_PWR_SetRegulVoltageScaling + * @param VoltageScaling This parameter can be one of the following values: + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling) +{ + MODIFY_REG(PWR->VOSR, PWR_VOSR_VOS, VoltageScaling); +} + +/** + * @brief Get the regulator supply output voltage. + * @rmtoll VOSR VOS LL_PWR_GetRegulVoltageScaling + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2 + */ +__STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void) +{ + return (uint32_t)(READ_BIT(PWR->VOSR, PWR_VOSR_VOS)); +} + +/** + * @brief Set the Power voltage detector level. + * @rmtoll SVMCR PVDLS LL_PWR_SetPVDLevel + * @param PVDLevel This parameter can be one of the following values: + * @arg @ref LL_PWR_PVDLEVEL_0 + * @arg @ref LL_PWR_PVDLEVEL_1 + * @arg @ref LL_PWR_PVDLEVEL_2 + * @arg @ref LL_PWR_PVDLEVEL_3 + * @arg @ref LL_PWR_PVDLEVEL_4 + * @arg @ref LL_PWR_PVDLEVEL_5 + * @arg @ref LL_PWR_PVDLEVEL_6 + * @arg @ref LL_PWR_PVDLEVEL_7 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel) +{ + MODIFY_REG(PWR->SVMCR, PWR_SVMCR_PVDLS, PVDLevel); +} + +/** + * @brief Get the Power voltage detector level. + * @rmtoll SVMCR PVDLS LL_PWR_GetPVDLevel + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_PVDLEVEL_0 + * @arg @ref LL_PWR_PVDLEVEL_1 + * @arg @ref LL_PWR_PVDLEVEL_2 + * @arg @ref LL_PWR_PVDLEVEL_3 + * @arg @ref LL_PWR_PVDLEVEL_4 + * @arg @ref LL_PWR_PVDLEVEL_5 + * @arg @ref LL_PWR_PVDLEVEL_6 + * @arg @ref LL_PWR_PVDLEVEL_7 + */ +__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void) +{ + return (READ_BIT(PWR->SVMCR, PWR_SVMCR_PVDLS)); +} + +/** + * @brief Enable the power voltage detector. + * @rmtoll SVMCR PVDE LL_PWR_EnablePVD + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnablePVD(void) +{ + SET_BIT(PWR->SVMCR, PWR_SVMCR_PVDE); +} + +/** + * @brief Disable the power voltage detector. + * @rmtoll SVMCR PVDE LL_PWR_DisablePVD + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisablePVD(void) +{ + CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_PVDE); +} + +/** + * @brief Check if the power voltage detector is enabled. + * @rmtoll SVMCR PVDE LL_PWR_IsEnabledPVD + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void) +{ + return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_PVDE) == (PWR_SVMCR_PVDE)) ? 1UL : 0UL); +} + +/** + * @brief Enable the wake up pin_x. + * @rmtoll WUCR1 WUPENx LL_PWR_EnableWakeUpPin + * @param WakeUpPin This parameter can be a combination of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 + * @arg @ref LL_PWR_WAKEUP_PIN6 + * @arg @ref LL_PWR_WAKEUP_PIN7 + * @arg @ref LL_PWR_WAKEUP_PIN8 + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin) +{ + SET_BIT(PWR->WUCR1, WakeUpPin); +} + +/** + * @brief Disable the wake up pin_x. + * @rmtoll WUCR1 WUPENx LL_PWR_DisableWakeUpPin + * @param WakeUpPin This parameter can be a combination of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 + * @arg @ref LL_PWR_WAKEUP_PIN6 + * @arg @ref LL_PWR_WAKEUP_PIN7 + * @arg @ref LL_PWR_WAKEUP_PIN8 + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin) +{ + CLEAR_BIT(PWR->WUCR1, WakeUpPin); +} + +/** + * @brief Check if the wake up pin_x is enabled. + * @rmtoll WUCR1 WUPENx LL_PWR_IsEnabledWakeUpPin + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 + * @arg @ref LL_PWR_WAKEUP_PIN6 + * @arg @ref LL_PWR_WAKEUP_PIN7 + * @arg @ref LL_PWR_WAKEUP_PIN8 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin) +{ + return ((READ_BIT(PWR->WUCR1, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL); +} + +/** + * @brief Set the wake up pin polarity low for the event detection. + * @rmtoll WUCR2 WUPPx LL_PWR_SetWakeUpPinPolarityLow + * @param WakeUpPin This parameter can be a combination of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 + * @arg @ref LL_PWR_WAKEUP_PIN6 + * @arg @ref LL_PWR_WAKEUP_PIN7 + * @arg @ref LL_PWR_WAKEUP_PIN8 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin) +{ + SET_BIT(PWR->WUCR2, WakeUpPin); +} + +/** + * @brief Set the wake up pin polarity high for the event detection. + * @rmtoll WUCR2 WUPPx LL_PWR_SetWakeUpPinPolarityHigh + * @param WakeUpPin This parameter can be a combination of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 + * @arg @ref LL_PWR_WAKEUP_PIN6 + * @arg @ref LL_PWR_WAKEUP_PIN7 + * @arg @ref LL_PWR_WAKEUP_PIN8 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin) +{ + CLEAR_BIT(PWR->WUCR2, WakeUpPin); +} + +/** + * @brief Get the wake up pin polarity for the event detection. + * @rmtoll WUCR2 WUPPx LL_PWR_GetWakeUpPinPolarity + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 + * @arg @ref LL_PWR_WAKEUP_PIN6 + * @arg @ref LL_PWR_WAKEUP_PIN7 + * @arg @ref LL_PWR_WAKEUP_PIN8 + * @retval State of bit (1 : polarity or 0 : polarity high). + */ +__STATIC_INLINE uint32_t LL_PWR_GetWakeUpPinPolarity(uint32_t WakeUpPin) +{ + return ((READ_BIT(PWR->WUCR2, WakeUpPin) == WakeUpPin) ? 1UL : 0UL); +} + +/** + * @brief Set the wakeup pin_x selection 0. + * @rmtoll WUCR3 WUSELx LL_PWR_SetWakeUpPinSignal0Selection + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 + * @arg @ref LL_PWR_WAKEUP_PIN6 + * @arg @ref LL_PWR_WAKEUP_PIN7 + * @arg @ref LL_PWR_WAKEUP_PIN8 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPinSignal0Selection(uint32_t WakeUpPin) +{ + MODIFY_REG(PWR->WUCR3, (3UL << (POSITION_VAL(WakeUpPin) * 2U)), + (LL_PWR_WAKEUP_PIN_SELECTION_0 << (POSITION_VAL(WakeUpPin) * 2U))); +} + +/** + * @brief Set the wakeup pin_x selection 1. + * @rmtoll WUCR3 WUSELx LL_PWR_SetWakeUpPinSignal1Selection + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 + * @arg @ref LL_PWR_WAKEUP_PIN6 + * @arg @ref LL_PWR_WAKEUP_PIN7 + * @arg @ref LL_PWR_WAKEUP_PIN8 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPinSignal1Selection(uint32_t WakeUpPin) +{ + MODIFY_REG(PWR->WUCR3, (3UL << (POSITION_VAL(WakeUpPin) * 2U)), + (LL_PWR_WAKEUP_PIN_SELECTION_1 << (POSITION_VAL(WakeUpPin) * 2U))); +} + +/** + * @brief Set the wakeup pin_x selection 2. + * @rmtoll WUCR3 WUSELx LL_PWR_SetWakeUpPinSignal2Selection + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 + * @arg @ref LL_PWR_WAKEUP_PIN6 + * @arg @ref LL_PWR_WAKEUP_PIN7 + * @arg @ref LL_PWR_WAKEUP_PIN8 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPinSignal2Selection(uint32_t WakeUpPin) +{ + MODIFY_REG(PWR->WUCR3, (3UL << (POSITION_VAL(WakeUpPin) * 2U)), + (LL_PWR_WAKEUP_PIN_SELECTION_2 << (POSITION_VAL(WakeUpPin) * 2U))); +} + +/** + * @brief Set the wakeup pin_x selection 3. + * @rmtoll WUCR3 WUSELx LL_PWR_SetWakeUpPinSignal3Selection + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 + * @arg @ref LL_PWR_WAKEUP_PIN6 + * @arg @ref LL_PWR_WAKEUP_PIN7 + * @arg @ref LL_PWR_WAKEUP_PIN8 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPinSignal3Selection(uint32_t WakeUpPin) +{ + MODIFY_REG(PWR->WUCR3, (3UL << (POSITION_VAL(WakeUpPin) * 2U)), + (LL_PWR_WAKEUP_PIN_SELECTION_3 << (POSITION_VAL(WakeUpPin) * 2U))); +} + +/** + * @brief Get the wakeup pin_x selection. + * @rmtoll WUCR3 WUSELx LL_PWR_GetWakeUpPinSignalSelection + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 + * @arg @ref LL_PWR_WAKEUP_PIN6 + * @arg @ref LL_PWR_WAKEUP_PIN7 + * @arg @ref LL_PWR_WAKEUP_PIN8 + */ +__STATIC_INLINE uint32_t LL_PWR_GetWakeUpPinSignalSelection(uint32_t WakeUpPin) +{ + return (READ_BIT(PWR->WUCR3, (3UL << (POSITION_VAL(WakeUpPin) * 2U)))); +} + +/** + * @brief Enable access to the backup domain. + * @rmtoll DBPR DBP LL_PWR_EnableBkUpAccess + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void) +{ + SET_BIT(PWR->DBPR, PWR_DBPR_DBP); +} + +/** + * @brief Disable access to the backup domain. + * @rmtoll DBPR DBP LL_PWR_DisableBkUpAccess + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void) +{ + CLEAR_BIT(PWR->DBPR, PWR_DBPR_DBP); +} + +/** + * @brief Check if the access to backup domain is enabled. + * @rmtoll DBPR DBP LL_PWR_IsEnabledBkUpAccess + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void) +{ + return ((READ_BIT(PWR->DBPR, PWR_DBPR_DBP) == (PWR_DBPR_DBP)) ? 1UL : 0UL); +} + +/** + * @brief Enable GPIO retention in Standby mode + * @rmtoll IORETENRx ENx LL_PWR_EnableGPIOStandbyRetention + * @param GPIOPort This parameter can be one of the following values: + * @arg @ref LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTA + * @arg @ref LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTB + * @arg @ref LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTC + * @arg @ref LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTH + * @param GPIOPin This parameter can be a combination of the following values: + * @arg @ref LL_PWR_GPIO_PIN_0 + * @arg @ref LL_PWR_GPIO_PIN_1 + * @arg @ref LL_PWR_GPIO_PIN_2 + * @arg @ref LL_PWR_GPIO_PIN_3 + * @arg @ref LL_PWR_GPIO_PIN_4 + * @arg @ref LL_PWR_GPIO_PIN_5 + * @arg @ref LL_PWR_GPIO_PIN_6 + * @arg @ref LL_PWR_GPIO_PIN_7 + * @arg @ref LL_PWR_GPIO_PIN_8 + * @arg @ref LL_PWR_GPIO_PIN_9 + * @arg @ref LL_PWR_GPIO_PIN_10 + * @arg @ref LL_PWR_GPIO_PIN_11 + * @arg @ref LL_PWR_GPIO_PIN_12 + * @arg @ref LL_PWR_GPIO_PIN_13 + * @arg @ref LL_PWR_GPIO_PIN_14 + * @arg @ref LL_PWR_GPIO_PIN_15 + * @retval None. + */ +__STATIC_INLINE void LL_PWR_EnableGPIOStandbyRetention(uint32_t GPIOPort, uint32_t GPIOPin) +{ + SET_BIT(*((__IO uint32_t *)GPIOPort), GPIOPin); +} + +/** + * @brief Disable GPIO retention in Standby mode + * @rmtoll IORETENRx ENx LL_PWR_DisableGPIOStandbyRetention + * @param GPIOPort This parameter can be one of the following values: + * @arg @ref LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTA + * @arg @ref LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTB + * @arg @ref LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTC + * @arg @ref LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTH + * @param GPIOPin This parameter can be a combinat+ion of the following values: + * @arg @ref LL_PWR_GPIO_PIN_0 + * @arg @ref LL_PWR_GPIO_PIN_1 + * @arg @ref LL_PWR_GPIO_PIN_2 + * @arg @ref LL_PWR_GPIO_PIN_3 + * @arg @ref LL_PWR_GPIO_PIN_4 + * @arg @ref LL_PWR_GPIO_PIN_5 + * @arg @ref LL_PWR_GPIO_PIN_6 + * @arg @ref LL_PWR_GPIO_PIN_7 + * @arg @ref LL_PWR_GPIO_PIN_8 + * @arg @ref LL_PWR_GPIO_PIN_9 + * @arg @ref LL_PWR_GPIO_PIN_10 + * @arg @ref LL_PWR_GPIO_PIN_11 + * @arg @ref LL_PWR_GPIO_PIN_12 + * @arg @ref LL_PWR_GPIO_PIN_13 + * @arg @ref LL_PWR_GPIO_PIN_14 + * @arg @ref LL_PWR_GPIO_PIN_15 + * @retval None. + */ +__STATIC_INLINE void LL_PWR_DisableGPIOStandbyRetention(uint32_t GPIOPort, uint32_t GPIOPin) +{ + CLEAR_BIT(*((__IO uint32_t *)GPIOPort), GPIOPin); +} + +/** + * @brief Check if GPIO retention is enabled in Standby mode + * @rmtoll IORETENRx ENx LL_PWR_IsEnabledGPIOStandbyRetention + * @param GPIOPort This parameter can be one of the following values: + * @arg @ref LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTA + * @arg @ref LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTB + * @arg @ref LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTC + * @arg @ref LL_PWR_GPIO_STATE_RETENTION_ENABLE_PORTH + * @param GPIOPin This parameter can be one of the following values: + * @arg @ref LL_PWR_GPIO_PIN_0 + * @arg @ref LL_PWR_GPIO_PIN_1 + * @arg @ref LL_PWR_GPIO_PIN_2 + * @arg @ref LL_PWR_GPIO_PIN_3 + * @arg @ref LL_PWR_GPIO_PIN_4 + * @arg @ref LL_PWR_GPIO_PIN_5 + * @arg @ref LL_PWR_GPIO_PIN_6 + * @arg @ref LL_PWR_GPIO_PIN_7 + * @arg @ref LL_PWR_GPIO_PIN_8 + * @arg @ref LL_PWR_GPIO_PIN_9 + * @arg @ref LL_PWR_GPIO_PIN_10 + * @arg @ref LL_PWR_GPIO_PIN_11 + * @arg @ref LL_PWR_GPIO_PIN_12 + * @arg @ref LL_PWR_GPIO_PIN_13 + * @arg @ref LL_PWR_GPIO_PIN_14 + * @arg @ref LL_PWR_GPIO_PIN_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOStandbyRetention(uint32_t GPIOPort, uint32_t GPIOPin) +{ + return ((READ_BIT(*((__IO uint32_t *)(GPIOPort)), GPIOPin) == (GPIOPin)) ? 1UL : 0UL); +} + +/** + * @brief Check if GPIO state was retained after Standby mode entry + * @rmtoll IORETRx RETx LL_PWR_IsGPIOStandbyStateRetained + * @param GPIOPort This parameter can be one of the following values: + * @arg @ref LL_PWR_GPIO_STATE_RETENTION_STATUS_PORTA + * @arg @ref LL_PWR_GPIO_STATE_RETENTION_STATUS_PORTB + * @arg @ref LL_PWR_GPIO_STATE_RETENTION_STATUS_PORTC + * @arg @ref LL_PWR_GPIO_STATE_RETENTION_STATUS_PORTH + * @param GPIOPin This parameter can be one of the following values: + * @arg @ref LL_PWR_GPIO_PIN_0 + * @arg @ref LL_PWR_GPIO_PIN_1 + * @arg @ref LL_PWR_GPIO_PIN_2 + * @arg @ref LL_PWR_GPIO_PIN_3 + * @arg @ref LL_PWR_GPIO_PIN_4 + * @arg @ref LL_PWR_GPIO_PIN_5 + * @arg @ref LL_PWR_GPIO_PIN_6 + * @arg @ref LL_PWR_GPIO_PIN_7 + * @arg @ref LL_PWR_GPIO_PIN_8 + * @arg @ref LL_PWR_GPIO_PIN_9 + * @arg @ref LL_PWR_GPIO_PIN_10 + * @arg @ref LL_PWR_GPIO_PIN_11 + * @arg @ref LL_PWR_GPIO_PIN_12 + * @arg @ref LL_PWR_GPIO_PIN_13 + * @arg @ref LL_PWR_GPIO_PIN_14 + * @arg @ref LL_PWR_GPIO_PIN_15 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsGPIOStandbyStateRetained(uint32_t GPIOPort, uint32_t GPIOPin) +{ + return ((READ_BIT(*((__IO uint32_t *)(GPIOPort)), GPIOPin) == (GPIOPin)) ? 1UL : 0UL); +} + +/** + * @brief Clear GPIO state retention status after Standby mode entry + * @rmtoll IORETRx RETx LL_PWR_ClearGPIOStandbyRetentionStatus + * @param GPIOPort This parameter can be one of the following values: + * @arg @ref LL_PWR_GPIO_STATE_RETENTION_STATUS_PORTA + * @arg @ref LL_PWR_GPIO_STATE_RETENTION_STATUS_PORTB + * @arg @ref LL_PWR_GPIO_STATE_RETENTION_STATUS_PORTC + * @arg @ref LL_PWR_GPIO_STATE_RETENTION_STATUS_PORTH + * @param GPIOPin This parameter can be one of the following values: + * @arg @ref LL_PWR_GPIO_PIN_0 + * @arg @ref LL_PWR_GPIO_PIN_1 + * @arg @ref LL_PWR_GPIO_PIN_2 + * @arg @ref LL_PWR_GPIO_PIN_3 + * @arg @ref LL_PWR_GPIO_PIN_4 + * @arg @ref LL_PWR_GPIO_PIN_5 + * @arg @ref LL_PWR_GPIO_PIN_6 + * @arg @ref LL_PWR_GPIO_PIN_7 + * @arg @ref LL_PWR_GPIO_PIN_8 + * @arg @ref LL_PWR_GPIO_PIN_9 + * @arg @ref LL_PWR_GPIO_PIN_10 + * @arg @ref LL_PWR_GPIO_PIN_11 + * @arg @ref LL_PWR_GPIO_PIN_12 + * @arg @ref LL_PWR_GPIO_PIN_13 + * @arg @ref LL_PWR_GPIO_PIN_14 + * @arg @ref LL_PWR_GPIO_PIN_15 + * @retval None. + */ +__STATIC_INLINE void LL_PWR_ClearGPIOStandbyRetentionStatus(uint32_t GPIOPort, uint32_t GPIOPin) +{ + CLEAR_BIT(*((__IO uint32_t *)GPIOPort), GPIOPin); +} + +/** + * @brief Get currently voltage scaling applied to VCORE. + * @rmtoll SVMSR ACTVOS LL_PWR_GetRegulCurrentVOS + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2 + */ +__STATIC_INLINE uint32_t LL_PWR_GetRegulCurrentVOS(void) +{ + return (READ_BIT(PWR->SVMSR, PWR_SVMSR_ACTVOS)); +} +/** + * @} + */ + + +/** @defgroup PWR_LL_EF_RADIO_MANAGEMENT PWR RADIO Management + * @{ + */ + +#if defined(PWR_RADIOSCR_REGPABYPEN) +/** + * @brief Enable regulator REG_VDDHPA bypass. + * @rmtoll RADIOSCR REGPABYPEN LL_PWR_EnableREGVDDHPABypass + * @note This bit shall only be written when the VDDHPA regulator is not used (When REGPASEL = 0) + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableREGVDDHPABypass(void) +{ + SET_BIT(PWR->RADIOSCR, PWR_RADIOSCR_REGPABYPEN); +} + +/** + * @brief Disable regulator REG_VDDHPA bypass. + * @rmtoll RADIOSCR REGPABYPEN LL_PWR_DisableREGVDDHPABypass + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableREGVDDHPABypass(void) +{ + CLEAR_BIT(PWR->RADIOSCR, PWR_RADIOSCR_REGPABYPEN); +} + +/** + * @brief Check if regulator REG_VDDHPA bypass is enabled. + * @rmtoll RADIOSCR REGPABYPEN LL_PWR_IsEnabledREGVDDHPABypass + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledREGVDDHPABypass(void) +{ + return ((READ_BIT(PWR->RADIOSCR, PWR_RADIOSCR_REGPABYPEN) == (PWR_RADIOSCR_REGPABYPEN)) ? 1UL : 0UL); +} +#endif /* PWR_RADIOSCR_REGPABYPEN */ + +#if defined(PWR_RADIOSCR_REGPASEL) +/** + * @brief Set regulator REG_VDDHPA input supply. + * @rmtoll RADIOSCR REGPASEL LL_PWR_SetREGVDDHPAInputSupply + * @note This bit shall only be written when the VDDHPA regulator is not used (When REGPASEL = 0) + * @arg @ref LL_PWR_REG_VDDHPA_VDDRFPA_PIN + * @arg @ref LL_PWR_REG_VDDHPA_VDDRFPA_VDD11 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetREGVDDHPAInputSupply(uint32_t InputSupply) +{ + MODIFY_REG(PWR->RADIOSCR, PWR_RADIOSCR_REGPASEL, InputSupply); +} + +/** + * @brief Get regulator REG_VDDHPA input supply. + * @rmtoll RADIOSCR REGPASEL LL_PWR_GetREGVDDHPAInputSupply + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_REG_VDDHPA_VDDRFPA_PIN + * @arg @ref LL_PWR_REG_VDDHPA_VDDRFPA_VDD11 + */ +__STATIC_INLINE uint32_t LL_PWR_GetREGVDDHPAInputSupply(void) +{ + return (READ_BIT(PWR->RADIOSCR, PWR_RADIOSCR_REGPASEL)); +} +#endif /* PWR_RADIOSCR_REGPASEL */ + +/** + * @brief Indicate whether the VDDHPA voltage output is ready when selecting VDDRFPA input. + * @rmtoll RADIOSCR REGPARDYVDDRFPA LL_PWR_IsActiveFlag_REGPARDYVDDRFPA + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGPARDYVDDRFPA(void) +{ + return ((READ_BIT(PWR->RADIOSCR, PWR_RADIOSCR_REGPARDYVDDRFPA) == (PWR_RADIOSCR_REGPARDYVDDRFPA)) ? 1UL : 0UL); +} + +#if defined(PWR_RADIOSCR_REGPARDYV11) +/** + * @brief Indicate whether the VDDHPA voltage output is ready when selecting VDD11 input. + * @rmtoll RADIOSCR REGPARDYV11 LL_PWR_IsActiveFlag_REGPARDYV11 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGPARDYV11(void) +{ + return ((READ_BIT(PWR->RADIOSCR, PWR_RADIOSCR_REGPARDYV11) == (PWR_RADIOSCR_REGPARDYV11)) ? 1UL : 0UL); +} +#endif /* PWR_RADIOSCR_REGPARDYV11 */ + +/** + * @brief Get 2.4 GHz RADIO VDDHPA control word. + * @rmtoll RADIOSCR RFVDDHPA LL_PWR_GetRadioVDDHPAControlWord + * @retval 4-bit control word. + */ +__STATIC_INLINE uint32_t LL_PWR_GetRadioVDDHPAControlWord(void) +{ + return (READ_BIT(PWR->RADIOSCR, PWR_RADIOSCR_RFVDDHPA)); +} + +/** + * @brief Indicate whether the 2.4 GHz RADIO encryption function is enabled + * @rmtoll RADIOSCR ENCMODE LL_PWR_IsEnabledRadioEncryption + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledRadioEncryption(void) +{ + return ((READ_BIT(PWR->RADIOSCR, PWR_RADIOSCR_ENCMODE) == (PWR_RADIOSCR_ENCMODE)) ? 1UL : 0UL); +} + +/** + * @brief Get 2.4 GHz RADIO PHY operating mode. + * @rmtoll RADIOSCR PHYMODE LL_PWR_GetRadioPhyMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_RADIO_PHY_SLEEP_MODE + * @arg @ref LL_PWR_RADIO_PHY_STANDBY_MODE + */ +__STATIC_INLINE uint32_t LL_PWR_GetRadioPhyMode(void) +{ + return (READ_BIT(PWR->RADIOSCR, PWR_RADIOSCR_PHYMODE)); +} + +/** + * @brief Get 2.4 GHz RADIO operating mode. + * @rmtoll RADIOSCR MODE LL_PWR_GetRadioMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_RADIO_DEEP_SLEEP_MODE + * @arg @ref LL_PWR_RADIO_SLEEP_MODE + * @arg @ref LL_PWR_RADIO_ACTIVE_MODE + */ +__STATIC_INLINE uint32_t LL_PWR_GetRadioMode(void) +{ + if (READ_BIT(PWR->RADIOSCR, PWR_RADIOSCR_MODE_1) != 0UL) + { + return LL_PWR_RADIO_ACTIVE_MODE; + } + else + { + return (READ_BIT(PWR->RADIOSCR, PWR_RADIOSCR_MODE_0)); + } +} +/** + * @} + */ + + +/** @defgroup PWR_LL_EF_FLAG_MANAGEMENT PWR FLAG Management + * @{ + */ + +/** + * @brief Indicate whether the regulator voltage output is above voltage + * scaling range or not. + * @rmtoll VOSR VOSRDY LL_PWR_IsActiveFlag_VOS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void) +{ + return ((READ_BIT(PWR->VOSR, PWR_VOSR_VOSRDY) == (PWR_VOSR_VOSRDY)) ? 1UL : 0UL); +} + + +/** + * @brief Indicate whether the system was in standby mode or not. + * @rmtoll SR SBF LL_PWR_IsActiveFlag_SB + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void) +{ + return ((READ_BIT(PWR->SR, PWR_SR_SBF) == (PWR_SR_SBF)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether the system was in stop mode or not. + * @rmtoll SR STOPF LL_PWR_IsActiveFlag_STOP + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_STOP(void) +{ + return ((READ_BIT(PWR->SR, PWR_SR_STOPF) == (PWR_SR_STOPF)) ? 1UL : 0UL); +} + + +#if defined(PWR_SVMSR_REGS) +/** + * @brief Indicate whether the regulator supply is LDO or SMPS. + * @rmtoll SVMSR REGS LL_PWR_IsActiveFlag_REGULATOR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGULATOR(void) +{ + return ((READ_BIT(PWR->SVMSR, PWR_SVMSR_REGS) == (PWR_SVMSR_REGS)) ? 1UL : 0UL); +} +#endif /* PWR_SVMSR_REGS */ + +/** + * @brief Indicate whether the VDD voltage is below the threshold or not. + * @rmtoll SVMSR PVDO LL_PWR_IsActiveFlag_PVDO + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void) +{ + return ((READ_BIT(PWR->SVMSR, PWR_SVMSR_PVDO) == (PWR_SVMSR_PVDO)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether the regulator voltage output is equal to current + * used voltage scaling range or not. + * @rmtoll SVMSR ACTVOSRDY LL_PWR_IsActiveFlag_ACTVOS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ACTVOS(void) +{ + return ((READ_BIT(PWR->SVMSR, PWR_SVMSR_ACTVOSRDY) == (PWR_SVMSR_ACTVOSRDY)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether a wakeup event is detected on wake up pin 1. + * @rmtoll WUSR WUF1 LL_PWR_IsActiveFlag_WU1 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void) +{ + return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF1) == (PWR_WUSR_WUF1)) ? 1UL : 0UL); +} + +#if defined(PWR_WUSR_WUF2) +/** + * @brief Indicate whether a wakeup event is detected on wake up pin 2. + * @rmtoll WUSR WUF2 LL_PWR_IsActiveFlag_WU2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void) +{ + return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF2) == (PWR_WUSR_WUF2)) ? 1UL : 0UL); +} +#endif /* PWR_WUSR_WUF2 */ + +/** + * @brief Indicate whether a wakeup event is detected on wake up pin 3. + * @rmtoll WUSR WUF3 LL_PWR_IsActiveFlag_WU3 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void) +{ + return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF3) == (PWR_WUSR_WUF3)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether a wakeup event is detected on wake up pin 4. + * @rmtoll WUSR WUF4 LL_PWR_IsActiveFlag_WU4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void) +{ + return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF4) == (PWR_WUSR_WUF4)) ? 1UL : 0UL); +} + +#if defined(PWR_WUSR_WUF5) +/** + * @brief Indicate whether a wakeup event is detected on wake up pin 5. + * @rmtoll WUSR WUF5 LL_PWR_IsActiveFlag_WU5 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void) +{ + return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF5) == (PWR_WUSR_WUF5)) ? 1UL : 0UL); +} +#endif /* PWR_WUSR_WUF5 */ + +/** + * @brief Indicate whether a wakeup event is detected on wake up pin 6. + * @rmtoll WUSR WUF6 LL_PWR_IsActiveFlag_WU6 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU6(void) +{ + return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF6) == (PWR_WUSR_WUF6)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether a wakeup event is detected on wake up pin 7. + * @rmtoll WUSR WUF7 LL_PWR_IsActiveFlag_WU7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU7(void) +{ + return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF7) == (PWR_WUSR_WUF7)) ? 1UL : 0UL); +} + +/** + * @brief Indicate whether a wakeup event is detected on wake up pin 8. + * @rmtoll WUSR WUF8 LL_PWR_IsActiveFlag_WU8 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU8(void) +{ + return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF8) == (PWR_WUSR_WUF8)) ? 1UL : 0UL); +} + + +/** + * @brief Clear stop flag. + * @rmtoll SR CSSF LL_PWR_ClearFlag_STOP + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_STOP(void) +{ + WRITE_REG(PWR->SR, PWR_SR_CSSF); +} + + +/** + * @brief Clear standby flag. + * @rmtoll SR CSSF LL_PWR_ClearFlag_SB + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_SB(void) +{ + WRITE_REG(PWR->SR, PWR_SR_CSSF); +} + +/** + * @brief Clear wake up flag 1. + * @rmtoll WUSCR CWUF1 LL_PWR_ClearFlag_WU1 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU1(void) +{ + WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF1); +} + +#if defined(PWR_WUSCR_CWUF2) +/** + * @brief Clear wake up flag 2. + * @rmtoll WUSCR CWUF2 LL_PWR_ClearFlag_WU2 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU2(void) +{ + WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF2); +} +#endif /* PWR_WUSCR_CWUF2 */ + +/** + * @brief Clear wake up flag 3. + * @rmtoll WUSCR CWUF3 LL_PWR_ClearFlag_WU3 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU3(void) +{ + WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF3); +} + +/** + * @brief Clear wake up flag 4. + * @rmtoll WUSCR CWUF4 LL_PWR_ClearFlag_WU4 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU4(void) +{ + WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF4); +} + +#if defined(PWR_WUSCR_CWUF5) +/** + * @brief Clear wake up flag 5. + * @rmtoll WUSCR CWUF5 LL_PWR_ClearFlag_WU5 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU5(void) +{ + WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF5); +} +#endif /* PWR_WUSCR_CWUF5 */ + +/** + * @brief Clear wake up flag 6. + * @rmtoll WUSCR CWUF6 LL_PWR_ClearFlag_WU6 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU6(void) +{ + WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF6); +} + +/** + * @brief Clear wake up flag 7. + * @rmtoll WUSCR CWUF7 LL_PWR_ClearFlag_WU7 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU7(void) +{ + WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF7); +} + +/** + * @brief Clear wake up flag 8. + * @rmtoll WUSCR CWUF8 LL_PWR_ClearFlag_WU8 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU8(void) +{ + WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF8); +} + +/** + * @brief Clear all wake up flags. + * @rmtoll WUSCR CWUF LL_PWR_ClearFlag_WU + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU(void) +{ + WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF); +} + +/** + * @} + */ + +/** @defgroup PWR_LL_EF_ATTRIBUTE_MANAGEMENT PWR Attribute Management + * @{ + */ + +#if defined(PWR_PRIVCFGR_NSPRIV) +/** + * @brief Enable privileged mode for nsecure items. + * @rmtoll PRIVCFGR NSPRIV LL_PWR_EnableNSecurePrivilege + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableNSecurePrivilege(void) +{ + SET_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV); +} + +/** + * @brief Disable privileged mode for nsecure items. + * @rmtoll PRIVCFGR NSPRIV LL_PWR_DisableNSecurePrivilege + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableNSecurePrivilege(void) +{ + CLEAR_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV); +} + +/** + * @brief Check if privileged mode for nsecure items is enabled. + * @rmtoll PRIVCFGR NSPRIV LL_PWR_IsEnabledNSecurePrivilege + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledNSecurePrivilege(void) +{ + return ((READ_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV) == PWR_PRIVCFGR_NSPRIV) ? 1UL : 0UL); +} +#endif /* PWR_PRIVCFGR_NSPRIV */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Enable privileged mode for secure items. + * @rmtoll PRIVCFGR SPRIV LL_PWR_EnableSecurePrivilege + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableSecurePrivilege(void) +{ + SET_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_SPRIV); +} + +/** + * @brief Disable privileged mode for secure items. + * @rmtoll PRIVCFGR SPRIV LL_PWR_DisableSecurePrivilege + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableSecurePrivilege(void) +{ + CLEAR_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_SPRIV); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#if defined(PWR_PRIVCFGR_NSPRIV) +/** + * @brief Check if privileged mode for secure items is enabled. + * @rmtoll PRIVCFGR SPRIV LL_PWR_IsEnabledSecurePrivilege + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledSecurePrivilege(void) +{ + return ((READ_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_SPRIV) == PWR_PRIVCFGR_SPRIV) ? 1UL : 0UL); +} +#endif /* PWR_PRIVCFGR_NSPRIV */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Configure secure attribute mode. + * @note This API can be executed only by CPU in secure mode. + * @rmtoll SECCFGR WUP1SEC LL_PWR_ConfigSecure\n + * SECCFGR WUP2SEC LL_PWR_ConfigSecure\n + * SECCFGR WUP3SEC LL_PWR_ConfigSecure\n + * SECCFGR WUP4SEC LL_PWR_ConfigSecure\n + * SECCFGR WUP5SEC LL_PWR_ConfigSecure\n + * SECCFGR WUP6SEC LL_PWR_ConfigSecure\n + * SECCFGR WUP7SEC LL_PWR_ConfigSecure\n + * SECCFGR WUP8SEC LL_PWR_ConfigSecure\n + * SECCFGR LPMSEC LL_PWR_ConfigSecure\n + * SECCFGR VDMSEC LL_PWR_ConfigSecure\n + * SECCFGR VBSEC LL_PWR_ConfigSecure + * @param SecureConfig This parameter can be the full combination + * of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1_NSEC or LL_PWR_WAKEUP_PIN1_SEC + * @arg @ref LL_PWR_WAKEUP_PIN2_NSEC or LL_PWR_WAKEUP_PIN2_SEC + * @arg @ref LL_PWR_WAKEUP_PIN3_NSEC or LL_PWR_WAKEUP_PIN3_SEC + * @arg @ref LL_PWR_WAKEUP_PIN4_NSEC or LL_PWR_WAKEUP_PIN4_SEC + * @arg @ref LL_PWR_WAKEUP_PIN5_NSEC or LL_PWR_WAKEUP_PIN5_SEC + * @arg @ref LL_PWR_WAKEUP_PIN6_NSEC or LL_PWR_WAKEUP_PIN6_SEC + * @arg @ref LL_PWR_WAKEUP_PIN7_NSEC or LL_PWR_WAKEUP_PIN7_SEC + * @arg @ref LL_PWR_WAKEUP_PIN8_NSEC or LL_PWR_WAKEUP_PIN8_SEC + * @arg @ref LL_PWR_LPM_NSEC or LL_PWR_LPM_SEC + * @arg @ref LL_PWR_VDM_NSEC or LL_PWR_VDM_SEC + * @arg @ref LL_PWR_VB_NSEC or LL_PWR_VB_SEC + * @retval None. + */ +__STATIC_INLINE void LL_PWR_ConfigSecure(uint32_t SecureConfig) +{ + WRITE_REG(PWR->SECCFGR, SecureConfig); +} + +/** + * @brief Get secure attribute configuration. + * @note This API can be executed only by CPU in secure mode. + * @rmtoll SECCFGR WUP1SEC LL_PWR_GetConfigSecure\n + * SECCFGR WUP2SEC LL_PWR_GetConfigSecure\n + * SECCFGR WUP3SEC LL_PWR_GetConfigSecure\n + * SECCFGR WUP4SEC LL_PWR_GetConfigSecure\n + * SECCFGR WUP5SEC LL_PWR_GetConfigSecure\n + * SECCFGR WUP6SEC LL_PWR_GetConfigSecure\n + * SECCFGR WUP7SEC LL_PWR_GetConfigSecure\n + * SECCFGR WUP8SEC LL_PWR_GetConfigSecure\n + * SECCFGR LPMSEC LL_PWR_GetConfigSecure\n + * SECCFGR VDMSEC LL_PWR_GetConfigSecure\n + * SECCFGR VBSEC LL_PWR_GetConfigSecure + * @retval Returned value is the combination of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1_NSEC or LL_PWR_WAKEUP_PIN1_SEC + * @arg @ref LL_PWR_WAKEUP_PIN2_NSEC or LL_PWR_WAKEUP_PIN2_SEC + * @arg @ref LL_PWR_WAKEUP_PIN3_NSEC or LL_PWR_WAKEUP_PIN3_SEC + * @arg @ref LL_PWR_WAKEUP_PIN4_NSEC or LL_PWR_WAKEUP_PIN4_SEC + * @arg @ref LL_PWR_WAKEUP_PIN5_NSEC or LL_PWR_WAKEUP_PIN5_SEC + * @arg @ref LL_PWR_WAKEUP_PIN6_NSEC or LL_PWR_WAKEUP_PIN6_SEC + * @arg @ref LL_PWR_WAKEUP_PIN7_NSEC or LL_PWR_WAKEUP_PIN7_SEC + * @arg @ref LL_PWR_WAKEUP_PIN8_NSEC or LL_PWR_WAKEUP_PIN8_SEC + * @arg @ref LL_PWR_LPM_NSEC or LL_PWR_LPM_SEC + * @arg @ref LL_PWR_VDM_NSEC or LL_PWR_VDM_SEC + * @arg @ref LL_PWR_VB_NSEC or LL_PWR_VB_SEC + */ +__STATIC_INLINE uint32_t LL_PWR_GetConfigSecure(void) +{ + return (READ_REG(PWR->SECCFGR)); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/** + * @} + */ + +#if defined (USE_FULL_LL_DRIVER) +/** @defgroup PWR_LL_EF_Init De-initialization function + * @{ + */ +ErrorStatus LL_PWR_DeInit(void); +/** + * @} + */ +#endif /* defined (USE_FULL_LL_DRIVER) */ + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (PWR) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STM32WBAxx_LL_PWR_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_rcc.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_rcc.h new file mode 100644 index 0000000000..97e4f31033 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_rcc.h @@ -0,0 +1,3273 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_ll_rcc.h + * @author MCD Application Team + * @brief Header file of RCC LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_LL_RCC_H +#define STM32WBAxx_LL_RCC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx.h" + +/** @addtogroup STM32WBAxx_LL_Driver + * @{ + */ + +#if defined(RCC) + +/** @defgroup RCC_LL RCC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup RCC_LL_Private_Constants RCC Private Constants + * @{ + */ +/* Defines used to perform offsets*/ +/* Offset used to access to RCC_CCIPR1, RCC_CCIPR2 and RCC_CCIPR3 registers */ +#define RCC_OFFSET_CCIPR1 0U +#define RCC_OFFSET_CCIPR2 0x04U +#define RCC_OFFSET_CCIPR3 0x08U + +/* Defines used for security configuration extension */ +#define RCC_SECURE_MASK 0x10FBU +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_Exported_Types RCC Exported Types + * @{ + */ + +/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure + * @{ + */ + +/** + * @brief RCC Clocks Frequency Structure + */ +typedef struct +{ + uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */ + uint32_t HCLK_Frequency; /*!< HCLK clock frequency */ + uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */ + uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */ + uint32_t PCLK7_Frequency; /*!< PCLK7 clock frequency */ +} LL_RCC_ClocksTypeDef; + +/** + * @} + */ + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants + * @{ + */ + +/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation + * @brief Defines used to adapt values of different oscillators + * @note These values could be modified in the user environment according to + * HW set-up. + * @{ + */ +#if !defined (HSE_VALUE) +#define HSE_VALUE 32000000U /*!< Value of the HSE oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) +#define HSI_VALUE 16000000U /*!< Value of the HSI oscillator in Hz */ +#endif /* HSI_VALUE */ + +#if !defined (LSE_VALUE) +#define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSI_VALUE) +#define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */ +#endif /* LSI_VALUE */ + +#if defined (RCC_LSI2_SUPPORT) +#if !defined (LSI2_VALUE) +#define LSI2_VALUE 32000U /*!< Value of the LSI2 oscillator in Hz */ +#endif /* LSI_VALUE */ +#endif + +#if !defined (EXTERNAL_SAI1_CLOCK_VALUE) +#define EXTERNAL_SAI1_CLOCK_VALUE 48000U /*!< Value of the SAI1_EXTCLK external oscillator in Hz */ +#endif /* EXTERNAL_SAI1_CLOCK_VALUE */ + +/** + * @} + */ + +/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_RCC_WriteReg function + * @{ + */ +#define LL_RCC_CICR_LSI1RDYC RCC_CICR_LSI1RDYC /*!< LSI1 Ready Interrupt Clear */ +#define LL_RCC_CICR_LSERDYC RCC_CICR_LSERDYC /*!< LSE Ready Interrupt Clear */ +#define LL_RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC /*!< HSI Ready Interrupt Clear */ +#define LL_RCC_CICR_HSERDYC RCC_CICR_HSERDYC /*!< HSE Ready Interrupt Clear */ +#define LL_RCC_CICR_PLL1RDYC RCC_CICR_PLL1RDYC /*!< PLL1 Ready Interrupt Clear */ +#define LL_RCC_CICR_HSECSSC RCC_CICR_HSECSSC /*!< HSE Clock Security System Interrupt Clear */ +#define LL_RCC_CICR_LSI2RDYC RCC_CICR_LSI2RDYC /*!< LSI2 Ready Interrupt Clear */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_RCC_ReadReg function + * @{ + */ +#define LL_RCC_CIFR_LSI1RDYF RCC_CIFR_LSI1RDYF /*!< LSI1 Ready Interrupt flag */ +#define LL_RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */ +#define LL_RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF /*!< HSI Ready Interrupt flag */ +#define LL_RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */ +#define LL_RCC_CIFR_PLL1RDYF RCC_CIFR_PLL1RDYF /*!< PLL1 Ready Interrupt flag */ +#define LL_RCC_CIFR_HSECSSF RCC_CIFR_HSECSSF /*!< HSE Clock Security System Interrupt flag */ +#define LL_RCC_CIFR_LSI2RDYF RCC_CIFR_LSI2RDYF /*!< LSI2 Ready Interrupt flag */ +#define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /*!< Option byte loader reset flag */ +#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< NRST pin reset flag */ +#define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF /*!< BOR reset flag */ +#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software reset flag */ +#define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent watchdog reset flag */ +#define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */ +#define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-power reset flag */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions + * @{ + */ +#define LL_RCC_CIER_LSI1RDYIE RCC_CIER_LSI1RDYIE /*!< LSI1 Ready Interrupt Enable */ +#define LL_RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE /*!< LSE Ready Interrupt Enable */ +#define LL_RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE /*!< HSI Ready Interrupt Enable */ +#define LL_RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE /*!< HSE Ready Interrupt Enable */ +#define LL_RCC_CIER_PLL1RDYIE RCC_CIER_PLL1RDYIE /*!< PLL1 Ready Interrupt Enable */ +#define LL_RCC_CIER_LSI2RDYIE RCC_CIER_LSI2RDYIE /*!< LSI2 Ready Interrupt Enable */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LSIPRE LSI prescaler + * @{ + */ +#define LL_RCC_LSI_DIV_1 0U /*!< LSI1 divided by 1 */ +#define LL_RCC_LSI_DIV_128 RCC_BDCR1_LSI1PREDIV /*!< LSI1 divided by 128 */ +/** + * @} + */ + +#if defined(RCC_BDCR2_LSI2CFG) +/** @defgroup RCC_LL_EC_LSI2CFG LSI2 oscillator temperature sensitivity configuration + * @{ + */ +#define LL_RCC_LSI2_TEMP_SENSITIVITY_80 0U /*!< LSI2 frequency temperature sensitivity is close to zero at +80 degrees C */ +#define LL_RCC_LSI2_TEMP_SENSITIVITY_50 RCC_BDCR2_LSI2CFG_0 /*!< LSI2 frequency temperature sensitivity is close to zero at +50 degrees C */ +#define LL_RCC_LSI2_TEMP_SENSITIVITY_20 RCC_BDCR2_LSI2CFG_1 /*!< LSI2 frequency temperature sensitivity is close to zero at +20 degrees C */ +/** + * @} + */ +#endif /* RCC_BDCR2_LSI2CFG */ + +#if defined(RCC_BDCR2_LSI2MODE) +/** @defgroup RCC_LL_EC_LSI2MODE LSI2 oscillator operating mode configuration + * @{ + */ +#define LL_RCC_LSI2_NOMINAL_MODE 0U /*!< LSI2 nominal power, high accuracy */ +#define LL_RCC_LSI2_LOWPOWER_MODE RCC_BDCR2_LSI2MODE_0 /*!< LSI2 low power, medium accuracy */ +#define LL_RCC_LSI2_ULTRALOWPOWER_MODE RCC_BDCR2_LSI2MODE_1 /*!< LSI2 ultra low power, low accuracy */ +/** + * @} + */ +#endif /* RCC_BDCR2_LSI2MODE */ + +/** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability + * @{ + */ +#define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR1_LSEDRV_0 /*!< Xtal mode medium low driving capability */ +#define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR1_LSEDRV_1 /*!< Xtal mode medium high driving capability */ +#define LL_RCC_LSEDRIVE_HIGH RCC_BDCR1_LSEDRV /*!< Xtal mode higher driving capability */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LSCO_CLKSOURCE LSCO Selection + * @{ + */ +#define LL_RCC_LSCO_CLKSOURCE_LSI 0U /*!< LSI selection for low speed clock */ +#define LL_RCC_LSCO_CLKSOURCE_LSE RCC_BDCR1_LSCOSEL /*!< LSE selection for low speed clock */ +/** + * @} + */ + + +/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch + * @{ + */ +#define LL_RCC_SYS_CLKSOURCE_HSI 0U /*!< HSI selection as system clock */ +#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR1_SW_1 /*!< HSE selection as system clock */ +#define LL_RCC_SYS_CLKSOURCE_PLL1R (RCC_CFGR1_SW_1 | RCC_CFGR1_SW_0) /*!< PLL1R selection as system clock */ +/** + * @} + */ + + +/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status + * @{ + */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI 0U /*!< HSI used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR1_SWS_1 /*!< HSE used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL1R (RCC_CFGR1_SWS_1 | RCC_CFGR1_SWS_0) /*!< PLL1R used as system clock */ +/** + * @} + */ + + +/** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler + * @{ + */ +#define LL_RCC_SYSCLK_DIV_1 0U /*!< SYSCLK not divided */ +#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR2_HPRE_2 /*!< SYSCLK divided by 2 */ +#define LL_RCC_SYSCLK_DIV_4 (RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_0) /*!< SYSCLK divided by 4 */ +#define LL_RCC_SYSCLK_DIV_8 (RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_1) /*!< SYSCLK divided by 8 */ +#define LL_RCC_SYSCLK_DIV_16 (RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_0) /*!< SYSCLK divided by 16 */ +/** + * @} + */ + + +/** @defgroup RCC_LL_EC_SYSTICK_CLKSOURCE SYSTICK clock source selection + * @{ + */ +#define LL_RCC_SYSTICK_CLKSOURCE_HCLKDIV8 0U /*!< HCLKDIV8 clock used as SYSTICK clock source */ +#define LL_RCC_SYSTICK_CLKSOURCE_LSI RCC_CCIPR1_SYSTICKSEL_0 /*!< LSI clock used as SYSTICK clock source */ +#define LL_RCC_SYSTICK_CLKSOURCE_LSE RCC_CCIPR1_SYSTICKSEL_1 /*!< LSE clock used as SYSTICK clock source */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_APB1_DIV APB1 prescaler + * @{ + */ +#define LL_RCC_APB1_DIV_1 0U /*!< HCLK not divided */ +#define LL_RCC_APB1_DIV_2 RCC_CFGR2_PPRE1_2 /*!< HCLK divided by 2 */ +#define LL_RCC_APB1_DIV_4 (RCC_CFGR2_PPRE1_2 | RCC_CFGR2_PPRE1_0) /*!< HCLK divided by 4 */ +#define LL_RCC_APB1_DIV_8 (RCC_CFGR2_PPRE1_2 | RCC_CFGR2_PPRE1_1) /*!< HCLK divided by 8 */ +#define LL_RCC_APB1_DIV_16 (RCC_CFGR2_PPRE1_2 | RCC_CFGR2_PPRE1_1 | RCC_CFGR2_PPRE1_0) /*!< HCLK divided by 16 */ +/** + * @} + */ + + +/** @defgroup RCC_LL_EC_APB2_DIV APB2 prescaler + * @{ + */ +#define LL_RCC_APB2_DIV_1 0U /*!< HCLK not divided */ +#define LL_RCC_APB2_DIV_2 RCC_CFGR2_PPRE2_2 /*!< HCLK divided by 2 */ +#define LL_RCC_APB2_DIV_4 (RCC_CFGR2_PPRE2_2 | RCC_CFGR2_PPRE2_0) /*!< HCLK divided by 4 */ +#define LL_RCC_APB2_DIV_8 (RCC_CFGR2_PPRE2_2 | RCC_CFGR2_PPRE2_1) /*!< HCLK divided by 8 */ +#define LL_RCC_APB2_DIV_16 (RCC_CFGR2_PPRE2_2 | RCC_CFGR2_PPRE2_1 | RCC_CFGR2_PPRE2_0) /*!< HCLK divided by 16 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_APB7_DIV APB7 prescaler + * @{ + */ +#define LL_RCC_APB7_DIV_1 0U /*!< HCLK not divided */ +#define LL_RCC_APB7_DIV_2 RCC_CFGR3_PPRE7_2 /*!< HCLK divided by 2 */ +#define LL_RCC_APB7_DIV_4 (RCC_CFGR3_PPRE7_2 | RCC_CFGR3_PPRE7_0) /*!< HCLK divided by 4 */ +#define LL_RCC_APB7_DIV_8 (RCC_CFGR3_PPRE7_2 | RCC_CFGR3_PPRE7_1) /*!< HCLK divided by 8 */ +#define LL_RCC_APB7_DIV_16 (RCC_CFGR3_PPRE7_2 | RCC_CFGR3_PPRE7_1 | RCC_CFGR3_PPRE7_0) /*!< HCLK divided by 16 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_AHB5_DIV AHB5 prescaler when SYSCLK is PLL1R + * @{ + */ +#define LL_RCC_AHB5_DIV_1 0U /*!< SYSCLK not divided */ +#define LL_RCC_AHB5_DIV_2 RCC_CFGR4_HPRE5_2 /*!< SYSCLK divided by 2 */ +#define LL_RCC_AHB5_DIV_3 (RCC_CFGR4_HPRE5_2 | RCC_CFGR4_HPRE5_0) /*!< SYSCLK divided by 3 */ +#define LL_RCC_AHB5_DIV_4 (RCC_CFGR4_HPRE5_2 | RCC_CFGR4_HPRE5_1) /*!< SYSCLK divided by 4 */ +#define LL_RCC_AHB5_DIV_6 (RCC_CFGR4_HPRE5_2 | RCC_CFGR4_HPRE5_1 | RCC_CFGR4_HPRE5_0) /*!< SYSCLK divided by 6 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_AHB5_DIVIDER AHB5 divider when SYSCLK is HSI or HSE + * @{ + */ +#define LL_RCC_AHB5_DIVIDER_1 0U /*!< SYSCLK not divided */ +#define LL_RCC_AHB5_DIVIDER_2 RCC_CFGR4_HDIV5 /*!< SYSCLK divided by 2 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection + * @{ + */ +#define LL_RCC_MCO1SOURCE_NOCLOCK 0U /*!< MCO output disabled, no clock on MCO */ +#define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR1_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_HSI (RCC_CFGR1_MCOSEL_0 | RCC_CFGR1_MCOSEL_1) /*!< HSI selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_HSE RCC_CFGR1_MCOSEL_2 /*!< HSE selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_PLL1R (RCC_CFGR1_MCOSEL_0 | RCC_CFGR1_MCOSEL_2) /*!< PLL1RCLK selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_LSI (RCC_CFGR1_MCOSEL_1 | RCC_CFGR1_MCOSEL_2) /*!< LSI selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_LSE (RCC_CFGR1_MCOSEL_0 | RCC_CFGR1_MCOSEL_1| RCC_CFGR1_MCOSEL_2)/*!< LSE selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_PLL1P RCC_CFGR1_MCOSEL_3 /*!< PLL1PCLK selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_PLL1Q (RCC_CFGR1_MCOSEL_0 | RCC_CFGR1_MCOSEL_3) /*!< PLL1QCLK selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_HCLK5 (RCC_CFGR1_MCOSEL_1 | RCC_CFGR1_MCOSEL_3) /*!< HCLK5 selection as MCO1 source */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler + * @{ + */ +#define LL_RCC_MCO1_DIV_1 0U /*!< MCO not divided */ +#define LL_RCC_MCO1_DIV_2 RCC_CFGR1_MCOPRE_0 /*!< MCO divided by 2 */ +#define LL_RCC_MCO1_DIV_4 RCC_CFGR1_MCOPRE_1 /*!< MCO divided by 4 */ +#define LL_RCC_MCO1_DIV_8 (RCC_CFGR1_MCOPRE_1 | RCC_CFGR1_MCOPRE_0) /*!< MCO divided by 8 */ +#define LL_RCC_MCO1_DIV_16 RCC_CFGR1_MCOPRE_2 /*!< MCO divided by 16 */ +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency + * @{ + */ +#define LL_RCC_PERIPH_FREQUENCY_NO 0U /*!< No clock enabled for the peripheral */ +#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection + * @{ + */ +#define LL_RCC_RTC_CLKSOURCE_NONE 0U /*!< No clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR1_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR1_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR1_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_RADIO_SLEEPTIMER_CLKSOURCE RADIO Sleep Timer Clock source + * @{ + */ +#define LL_RCC_RADIOSLEEPSOURCE_NONE 0U /*!< No clock selected, 2.4 GHz RADIO sleep timer kernel clock disabled */ +#define LL_RCC_RADIOSLEEPSOURCE_LSE RCC_BDCR1_RADIOSTSEL_0 /*!< LSE oscillator clock selected */ +#define LL_RCC_RADIOSLEEPSOURCE_LSI RCC_BDCR1_RADIOSTSEL_1 /*!< LSI oscillator clock selected */ +#define LL_RCC_RADIOSLEEPSOURCE_HSE_DIV1000 RCC_BDCR1_RADIOSTSEL /*!< HSE oscillator clock divided by 1000 selected */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_USART_CLKSOURCE Peripheral USARTx clock source selection + * @{ + */ +#define LL_RCC_USART1_CLKSOURCE_PCLK2 (RCC_CCIPR1_USART1SEL << 16U) /*!< PCLK2 clock used as USART1 clock source */ +#define LL_RCC_USART1_CLKSOURCE_SYSCLK ((RCC_CCIPR1_USART1SEL << 16U) | RCC_CCIPR1_USART1SEL_0) /*!< SYSCLK clock used as USART1 clock source */ +#define LL_RCC_USART1_CLKSOURCE_HSI ((RCC_CCIPR1_USART1SEL << 16U) | RCC_CCIPR1_USART1SEL_1) /*!< HSI clock used as USART1 clock source */ +#define LL_RCC_USART1_CLKSOURCE_LSE ((RCC_CCIPR1_USART1SEL << 16U) | RCC_CCIPR1_USART1SEL) /*!< LSE clock used as USART1 clock source */ +#if defined(USART2) +#define LL_RCC_USART2_CLKSOURCE_PCLK1 (RCC_CCIPR1_USART2SEL << 16U) /*!< PCLK1 clock used as USART2 clock source */ +#define LL_RCC_USART2_CLKSOURCE_SYSCLK ((RCC_CCIPR1_USART2SEL << 16U) | RCC_CCIPR1_USART2SEL_0) /*!< SYSCLK clock used as USART2 clock source */ +#define LL_RCC_USART2_CLKSOURCE_HSI ((RCC_CCIPR1_USART2SEL << 16U) | RCC_CCIPR1_USART2SEL_1) /*!< HSI clock used as USART2 clock source */ +#define LL_RCC_USART2_CLKSOURCE_LSE ((RCC_CCIPR1_USART2SEL << 16U) | RCC_CCIPR1_USART2SEL) /*!< LSE clock used as USART2 clock source */ +#endif /* USART2 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LPUART_CLKSOURCE Peripheral LPUARTx clock source selection + * @{ + */ +#define LL_RCC_LPUART1_CLKSOURCE_PCLK7 0U /*!< PCLK3 clock used as LPUART1 clock source */ +#define LL_RCC_LPUART1_CLKSOURCE_SYSCLK RCC_CCIPR3_LPUART1SEL_0 /*!< SYSCLK clock used as LPUART1 clock source */ +#define LL_RCC_LPUART1_CLKSOURCE_HSI RCC_CCIPR3_LPUART1SEL_1 /*!< HSI clock used as LPUART1 clock source */ +#define LL_RCC_LPUART1_CLKSOURCE_LSE (RCC_CCIPR3_LPUART1SEL_0 | RCC_CCIPR3_LPUART1SEL_1) /*!< LSE clock used as LPUART1 clock source */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_I2C_CLKSOURCE Peripheral I2Cx clock source selection + * @{ + */ +#define LL_RCC_I2C1_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C1SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C1 clock source */ +#define LL_RCC_I2C1_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C1SEL_Pos << 16U) | (RCC_CCIPR1_I2C1SEL_0 >> RCC_CCIPR1_I2C1SEL_Pos)) /*!< SYSCLK clock used as I2C1 clock source */ +#define LL_RCC_I2C1_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C1SEL_Pos << 16U) | (RCC_CCIPR1_I2C1SEL_1 >> RCC_CCIPR1_I2C1SEL_Pos)) /*!< HSI clock used as I2C1 clock source */ +#define LL_RCC_I2C3_CLKSOURCE_PCLK7 ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_I2C3SEL_Pos << 16U)) /*!< PCLK7 clock used as I2C3 clock source */ +#define LL_RCC_I2C3_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_I2C3SEL_Pos << 16U) | (RCC_CCIPR3_I2C3SEL_0 >> RCC_CCIPR3_I2C3SEL_Pos)) /*!< SYSCLK clock used as I2C3 clock source */ +#define LL_RCC_I2C3_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_I2C3SEL_Pos << 16U) | (RCC_CCIPR3_I2C3SEL_1 >> RCC_CCIPR3_I2C3SEL_Pos)) /*!< HSI clock used as I2C3 clock source */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SPI_CLKSOURCE Peripheral SPIx clock source selection + * @{ + */ +#if defined(SPI1) +#define LL_RCC_SPI1_CLKSOURCE_PCLK2 ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI1SEL_Pos << 16U)) /*!< PCLK2 clock used as SPI1 clock source */ +#define LL_RCC_SPI1_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI1SEL_Pos << 16U) | (RCC_CCIPR1_SPI1SEL_0 >> RCC_CCIPR1_SPI1SEL_Pos)) /*!< SYSCLK clock used as SPI1 clock source */ +#define LL_RCC_SPI1_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI1SEL_Pos << 16U) | (RCC_CCIPR1_SPI1SEL_1 >> RCC_CCIPR1_SPI1SEL_Pos)) /*!< HSI clock used as SPI1 clock source */ +#endif /* SPI1 */ +#define LL_RCC_SPI3_CLKSOURCE_PCLK7 ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_SPI3SEL_Pos << 16U)) /*!< PCLK7 clock used as SPI3 clock source */ +#define LL_RCC_SPI3_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_SPI3SEL_Pos << 16U) | (RCC_CCIPR3_SPI3SEL_0 >> RCC_CCIPR3_SPI3SEL_Pos)) /*!< SYSCLK clock used as SPI3 clock source */ +#define LL_RCC_SPI3_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_SPI3SEL_Pos << 16U) | (RCC_CCIPR3_SPI3SEL_1 >> RCC_CCIPR3_SPI3SEL_Pos)) /*!< HSI clock used as SPI3 clock source */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LPTIM_CLKSOURCE Peripheral LPTIMx clock source selection + * @{ + */ +#define LL_RCC_LPTIM1_CLKSOURCE_PCLK7 ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM1SEL_Pos << 16U)) /*!< PCLK7 clock used as LPTIM1 clock source */ +#define LL_RCC_LPTIM1_CLKSOURCE_LSI ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM1SEL_Pos << 16U) | (RCC_CCIPR3_LPTIM1SEL_0 >> RCC_CCIPR3_LPTIM1SEL_Pos)) /*!< LSI clock used as LPTIM1 clock source */ +#define LL_RCC_LPTIM1_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM1SEL_Pos << 16U) | (RCC_CCIPR3_LPTIM1SEL_1 >> RCC_CCIPR3_LPTIM1SEL_Pos)) /*!< HSI clock used as LPTIM1 clock source */ +#define LL_RCC_LPTIM1_CLKSOURCE_LSE ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM1SEL_Pos << 16U) | (RCC_CCIPR3_LPTIM1SEL >> RCC_CCIPR3_LPTIM1SEL_Pos)) /*!< LSE clock used as LPTIM1 clock source */ +#if defined(LPTIM2) +#define LL_RCC_LPTIM2_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_LPTIM2SEL_Pos << 16U)) /*!< PCLK1 clock used as LPTIM2 clock source */ +#define LL_RCC_LPTIM2_CLKSOURCE_LSI ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_LPTIM2SEL_Pos << 16U) | (RCC_CCIPR1_LPTIM2SEL_0 >> RCC_CCIPR1_LPTIM2SEL_Pos)) /*!< LSI clock used as LPTIM2 clock source */ +#define LL_RCC_LPTIM2_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_LPTIM2SEL_Pos << 16U) | (RCC_CCIPR1_LPTIM2SEL_1 >> RCC_CCIPR1_LPTIM2SEL_Pos)) /*!< HSI clock used as LPTIM2 clock source */ +#define LL_RCC_LPTIM2_CLKSOURCE_LSE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_LPTIM2SEL_Pos << 16U) | (RCC_CCIPR1_LPTIM2SEL >> RCC_CCIPR1_LPTIM2SEL_Pos)) /*!< LSE clock used as LPTIM2 clock source */ +#endif /* LPTIM2 */ +/** + * @} + */ + +#if defined(SAI1) +/** @defgroup RCC_LL_EC_SAI_CLKSOURCE Peripheral SAIx clock source selection + * @{ + */ +#define LL_RCC_SAI1_CLKSOURCE_PLL1P (RCC_CCIPR2_SAI1SEL << 16U) /*!< PLL1P clock used as SAI1 clock source */ +#define LL_RCC_SAI1_CLKSOURCE_PLL1Q ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_0) /*!< PLL1Q clock used as SAI1 clock source */ +#define LL_RCC_SAI1_CLKSOURCE_SYSCLK ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_1) /*!< System clock used as SAI1 clock source */ +#define LL_RCC_SAI1_CLKSOURCE_PIN ((RCC_CCIPR2_SAI1SEL << 16U) | (RCC_CCIPR2_SAI1SEL_1 | RCC_CCIPR2_SAI1SEL_0)) /*!< External input clock used as SAI1 clock source */ +#define LL_RCC_SAI1_CLKSOURCE_HSI ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_2) /*!< HSI clock used as SAI1 clock source */ +/** + * @} + */ +#endif /* SAI1 */ + + +/** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection + * @{ + */ +#define LL_RCC_RNG_CLKSOURCE_LSE 0U /*!< LSE clock used as RNG clock source */ +#define LL_RCC_RNG_CLKSOURCE_LSI RCC_CCIPR2_RNGSEL_0 /*!< LSI clock used as RNG clock source */ +#define LL_RCC_RNG_CLKSOURCE_HSI RCC_CCIPR2_RNGSEL_1 /*!< HSI clock used as RNG clock source */ +#define LL_RCC_RNG_CLKSOURCE_PLL1Q_DIV2 (RCC_CCIPR2_RNGSEL_1 | RCC_CCIPR2_RNGSEL_0) /*!< PLL1Q/2 clock used as RNG clock source */ +/** + * @} + */ +/** Legacy definitions for compatibility purpose +@cond 0 + */ +#define LL_RCC_RNG_CLKSOURCE_PLL1Q LL_RCC_RNG_CLKSOURCE_PLL1Q_DIV2 +/** +@endcond + */ + +/** @defgroup RCC_LL_EC_ADC_CLKSOURCE Peripheral ADC4 clock source selection + * @{ + */ +#define LL_RCC_ADC_CLKSOURCE_HCLK 0U /*!< HCLK1 clock used as ADC4 clock source */ +#define LL_RCC_ADC_CLKSOURCE_SYSCLK RCC_CCIPR3_ADCSEL_0 /*!< SYSCLK clock used as ADC4 clock source */ +#define LL_RCC_ADC_CLKSOURCE_PLL1P RCC_CCIPR3_ADCSEL_1 /*!< PLL1P clock used as ADC4 clock source */ +#define LL_RCC_ADC_CLKSOURCE_HSI RCC_CCIPR3_ADCSEL_2 /*!< HSI clock used as ADC4 clock source */ +#define LL_RCC_ADC_CLKSOURCE_HSE (RCC_CCIPR3_ADCSEL_1 | RCC_CCIPR3_ADCSEL_0) /*!< HSE clock used as ADC4 clock source */ +/** + * @} + */ + + + +/** @defgroup RCC_LL_EC_TIM_INPUT_CAPTURE_CLOCKSource TIM Input capture clock source selection + * @{ + */ +#define LL_RCC_TIMIC_CLKSOURCE_NONE 0U /*!< No clock available for TIM16/TIM17 and LPTIM2 input capture */ +#define LL_RCC_TIMIC_CLKSOURCE_HSI_DIV256 RCC_CCIPR1_TIMICSEL /*!< HSI/256 selected for TIM16/TIM17 and LPTIM2 input capture */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_USART Peripheral USARTx get clock source + * @{ + */ +#define LL_RCC_USART1_CLKSOURCE RCC_CCIPR1_USART1SEL /*!< USART1 Clock source selection */ +#if defined(USART2) +#define LL_RCC_USART2_CLKSOURCE RCC_CCIPR1_USART2SEL /*!< USART2 Clock source selection */ +#endif /* USART2 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SPI Peripheral SPIx get clock source + * @{ + */ +#if defined(SPI1) +#define LL_RCC_SPI1_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI1SEL_Pos << 16U) | (RCC_CCIPR1_SPI1SEL >> RCC_CCIPR1_SPI1SEL_Pos)) /*!< SPI1 Clock source selection */ +#endif /* SPI1 */ +#define LL_RCC_SPI3_CLKSOURCE ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_SPI3SEL_Pos << 16U) | (RCC_CCIPR3_SPI3SEL >> RCC_CCIPR3_SPI3SEL_Pos)) /*!< SPI3 Clock source selection */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LPUART Peripheral LPUARTx get clock source + * @{ + */ +#define LL_RCC_LPUART1_CLKSOURCE RCC_CCIPR3_LPUART1SEL /*!< LPUART1 Clock source selection */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_I2C Peripheral I2Cx get clock source + * @{ + */ +#if defined(I2C1) +#define LL_RCC_I2C1_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C1SEL_Pos << 16U) | (RCC_CCIPR1_I2C1SEL >> RCC_CCIPR1_I2C1SEL_Pos)) /*!< I2C1 Clock source selection */ +#endif /* I2C1 */ +#define LL_RCC_I2C3_CLKSOURCE ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_I2C3SEL_Pos << 16U) | (RCC_CCIPR3_I2C3SEL >> RCC_CCIPR3_I2C3SEL_Pos)) /*!< I2C3 Clock source selection */ + +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LPTIM Peripheral LPTIMx get clock source + * @{ + */ +#define LL_RCC_LPTIM1_CLKSOURCE ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM1SEL_Pos << 16U) | (RCC_CCIPR3_LPTIM1SEL >> RCC_CCIPR3_LPTIM1SEL_Pos)) /*!< LPTIM1 Clock source selection */ +#if defined(LPTIM2) +#define LL_RCC_LPTIM2_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_LPTIM2SEL_Pos << 16U) | (RCC_CCIPR1_LPTIM2SEL >> RCC_CCIPR1_LPTIM2SEL_Pos)) /*!< LPTIM2 Clock source selection */ +#endif /* LPTIM2 */ +/** + * @} + */ + +#if defined(SAI1) +/** @defgroup RCC_LL_EC_SAI Peripheral SAIx get clock source + * @{ + */ +#define LL_RCC_SAI1_CLKSOURCE RCC_CCIPR2_SAI1SEL /*!< SAI1 Clock source selection */ +/** + * @} + */ +#endif /* SAI1 */ + +/** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source + * @{ + */ +#define LL_RCC_RNG_CLKSOURCE RCC_CCIPR2_RNGSEL /*!< RNG Clock source selection */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source + * @{ + */ +#define LL_RCC_ADC_CLKSOURCE RCC_CCIPR3_ADCSEL /*!< ADCs Clock source selection */ +/** + * @} + */ + + +/** @defgroup RCC_LL_EC_PLL1SOURCE PLL1 entry clock source + * @{ + */ +#define LL_RCC_PLL1SOURCE_NONE 0U /*!< No clock selected as PLL1 entry clock source */ +#define LL_RCC_PLL1SOURCE_HSI RCC_PLL1CFGR_PLL1SRC_1 /*!< HSI clock selected as PLL1 entry clock source */ +#define LL_RCC_PLL1SOURCE_HSE (RCC_PLL1CFGR_PLL1SRC_0 | RCC_PLL1CFGR_PLL1SRC_1) /*!< HSE clock selected as PLL1 entry clock source */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLLINPUTRANGE All PLLs input ranges + * @{ + */ +#define LL_RCC_PLLINPUTRANGE_4_8 2U /*!< VCO input range: 4 to 8 MHz */ +#define LL_RCC_PLLINPUTRANGE_8_16 3U /*!< VCO input range: 8 to 16 MHz */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLL1RCLKPRESTEP PLL1RCLK prescaler steps division + * @{ + */ +#define LL_RCC_PLL1RCLK_2_STEP_DIV 0U /*!< PLL1RCLK 2-step division */ +#define LL_RCC_PLL1RCLK_3_STEP_DIV RCC_PLL1CFGR_PLL1RCLKPRESTEP /*!< PLL1RCLK 3-step division */ +/** + * @} + */ + +/** @defgroup RCC_LSE_Trimming LSE Trimming + * @{ + */ +#define LL_RCC_LSETRIMMING_R 0U /*!< Current source resistance R */ +#define LL_RCC_LSETRIMMING_3_4_R RCC_BDCR1_LSETRIM_0 /*!< Current source resistance 3/4 * R */ +#define LL_RCC_LSETRIMMING_2_3_R RCC_BDCR1_LSETRIM_1 /*!< Current source resistance 2/3 * R */ +#define LL_RCC_LSETRIMMING_1_2_R RCC_BDCR1_LSETRIM /*!< Current source resistance 1/2 * R */ +/** + * @} + */ + +/** @defgroup RCC_LL_EF_Security_Services Security Services + * @note Only available when system implements security (TZEN=1) + * @{ + */ +#define LL_RCC_ALL_NSEC 0U /*!< No security on RCC resources (default) */ +#define LL_RCC_ALL_SEC RCC_SECURE_MASK /*!< Security on all RCC resources */ + +#define LL_RCC_HSI_SEC RCC_SECCFGR_HSISEC /*!< HSI clock configuration secure-only access */ +#define LL_RCC_HSI_NSEC 0U /*!< HSI clock configuration secure/non-secure access */ +#define LL_RCC_HSE_SEC RCC_SECCFGR_HSESEC /*!< HSE clock configuration secure-only access */ +#define LL_RCC_HSE_NSEC 0U /*!< HSE clock configuration secure/non-secure access */ +#define LL_RCC_LSE_SEC RCC_SECCFGR_LSESEC /*!< LSE clock configuration secure-only access */ +#define LL_RCC_LSE_NSEC 0U /*!< LSE clock configuration secure/non-secure access */ +#define LL_RCC_LSI_SEC RCC_SECCFGR_LSISEC /*!< LSI clock configuration secure-only access */ +#define LL_RCC_LSI_NSEC 0U /*!< LSI clock configuration secure/non-secure access */ +#define LL_RCC_SYSCLK_SEC RCC_SECCFGR_SYSCLKSEC /*!< SYSCLK clock; STOPWUCK and MCO output configuration secure-only access */ +#define LL_RCC_SYSCLK_NSEC 0U /*!< SYSCLK clock; STOPWUCK and MCO output configuration secure/non-secure access */ +#define LL_RCC_PRESCALERS_SEC RCC_SECCFGR_PRESCSEC /*!< AHBx/APBx prescaler configuration secure-only access */ +#define LL_RCC_PRESCALERS_NSEC 0U /*!< AHBx/APBx prescaler configuration secure/non-secure access */ +#define LL_RCC_PLL1_SEC RCC_SECCFGR_PLL1SEC /*!< PLL1 clock configuration secure-only access */ +#define LL_RCC_PLL1_NSEC 0U /*!< PLL1 clock configuration secure/non-secure access */ +#define LL_RCC_RESET_FLAGS_SEC RCC_SECCFGR_RMVFSEC /*!< Remove reset flag secure-only access */ +#define LL_RCC_RESET_FLAGS_NSEC 0U /*!< Remove reset flag secure/non-secure access */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros + * @{ + */ + +/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in RCC register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__)) + +/** + * @brief Read a value in RCC register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__) +/** + * @} + */ + +/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies + * @{ + */ + +/** + * @brief Helper macro to calculate the PLL1RCLK frequency on system domain + * @note ex: @ref __LL_RCC_CALC_PLL1RCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL1_GetDivider (), + * @ref LL_RCC_PLL1_GetN (), @ref LL_RCC_PLL1_GetR ()); + * @param __INPUTFREQ__ PLL1 Input frequency (based on HSE/HSI) + * @param __PLL1M__ parameter can be a value between 1 and 16 + * @param __PLL1N__ parameter can be a value between 4 and 512 + * @param __PLL1R__ parameter can be a value between 1 and 128 + * @retval PLL1R clock frequency (in Hz) + */ + +#define __LL_RCC_CALC_PLL1RCLK_FREQ(__INPUTFREQ__, __PLL1M__, __PLL1N__, __PLL1R__) ((((__INPUTFREQ__) /(__PLL1M__)) * (__PLL1N__)) / (__PLL1R__)) + +/** + * @brief Helper macro to calculate the PLL1PCLK frequency + * @note ex: @ref __LL_RCC_CALC_PLL1PCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL1_GetDivider (), + * @ref LL_RCC_PLL1_GetN (), @ref LL_RCC_PLL1_GetP ()); + * @param __INPUTFREQ__ PLL1 Input frequency (based on HSE/HSI) + * @param __PLL1M__ parameter can be a value between 1 and 16 + * @param __PLL1N__ parameter can be a value between 4 and 512 + * @param __PLL1P__ parameter can be a value between 2 and 128 + * @retval PLL1P clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLL1PCLK_FREQ(__INPUTFREQ__, __PLL1M__, __PLL1N__, __PLL1P__) ((((__INPUTFREQ__) /(__PLL1M__)) * (__PLL1N__)) / (__PLL1P__)) + +/** + * @brief Helper macro to calculate the PLL1QCLK frequency + * @note ex: @ref __LL_RCC_CALC_PLL1QCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL1_GetDivider (), + * @ref LL_RCC_PLL1_GetN (), @ref LL_RCC_PLL1_GetQ ()); + * @param __INPUTFREQ__ PLL1 Input frequency (based on HSE/HSI) + * @param __PLL1M__ parameter can be a value between 1 and 16 + * @param __PLL1N__ parameter can be a value between 4 and 512 + * @param __PLL1Q__ parameter can be a value between 1 and 128 + * @retval PLL1 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLL1QCLK_FREQ(__INPUTFREQ__, __PLL1M__, __PLL1N__, __PLL1Q__) ((((__INPUTFREQ__) /(__PLL1M__)) * (__PLL1N__)) / (__PLL1Q__)) + +/** + * @brief Helper macro to calculate the HCLK frequency + * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK) + * @param __AHBPRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @retval HCLK clock frequency (in Hz) + */ +#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos]) + +/** + * @brief Helper macro to calculate the PCLK1 frequency (ABP1) + * @param __HCLKFREQ__ HCLK frequency + * @param __APB1PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + * @retval PCLK1 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> (APBPrescTable[((__APB1PRESCALER__) & RCC_CFGR2_PPRE1) >> RCC_CFGR2_PPRE1_Pos])) + +/** + * @brief Helper macro to calculate the PCLK2 frequency (ABP2) + * @param __HCLKFREQ__ HCLK frequency + * @param __APB2PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_APB2_DIV_1 + * @arg @ref LL_RCC_APB2_DIV_2 + * @arg @ref LL_RCC_APB2_DIV_4 + * @arg @ref LL_RCC_APB2_DIV_8 + * @arg @ref LL_RCC_APB2_DIV_16 + * @retval PCLK2 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR2_PPRE2_Pos]) + + +/** + * @brief Helper macro to calculate the PCLK7 frequency (ABP7) + * @param __HCLKFREQ__ HCLK frequency + * @param __APB7PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_APB7_DIV_1 + * @arg @ref LL_RCC_APB7_DIV_2 + * @arg @ref LL_RCC_APB7_DIV_4 + * @arg @ref LL_RCC_APB7_DIV_8 + * @arg @ref LL_RCC_APB7_DIV_16 + * @retval PCLK3 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PCLK7_FREQ(__HCLKFREQ__, __APB7PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB7PRESCALER__) >> RCC_CFGR3_PPRE7_Pos]) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions + * @{ + */ + +/** @defgroup RCC_LL_EF_HSE HSE + * @{ + */ + +/** + * @brief Enable HSE crystal oscillator (HSE ON) + * @rmtoll CR HSEON LL_RCC_HSE_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSEON); +} + +/** + * @brief Disable HSE crystal oscillator (HSE ON) + * @rmtoll CR HSEON LL_RCC_HSE_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); +} + +/** + * @brief Check if HSE oscillator Ready + * @rmtoll CR HSERDY LL_RCC_HSE_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == RCC_CR_HSERDY) ? 1UL : 0UL); +} + +/** + * @brief Enable HSE clock prescaler for sysclk + * @rmtoll CR HSEPRE LL_RCC_HSE_EnablePrescaler + * @note Control the division factor of the HSE32 clock for sysclk + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_EnablePrescaler(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSEPRE); +} + +/** + * @brief Check if HSE clock prescaler for sysclk is enabled + * @rmtoll CR HSEPRE LL_RCC_HSE_IsEnabledPrescaler + * @note Check if the HSE32 clock for sysclk is divided by 2 or not + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSE_IsEnabledPrescaler(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_HSEPRE) == RCC_CR_HSEPRE) ? 1UL : 0UL); +} + +/** + * @brief Disable HSE clock prescaler for sysclk + * @rmtoll CR HSEPRE LL_RCC_HSE_DisablePrescaler + * @note Control the division factor of the HSE32 clock for sysclk + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_DisablePrescaler(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSEPRE); +} + +/** + * @brief Enable the Clock Security System. + * @rmtoll CR HSECSSON LL_RCC_HSE_EnableCSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSECSSON); +} + +/** + * @brief Set HSE clock trimming + * @note user-programmable capacitor trimming value. + * @rmtoll ECSCR1 HSETRIM LL_RCC_HSE_SetClockTrimming + * @param Value Between Min_Data = 0 and Max_Data = 63 + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_SetClockTrimming(uint32_t Value) +{ + MODIFY_REG(RCC->ECSCR1, RCC_ECSCR1_HSETRIM, Value << RCC_ECSCR1_HSETRIM_Pos); +} + +/** + * @brief Get HSE clock trimming + * @rmtoll ECSCR1 HSETRIM LL_RCC_HSE_GetClockTrimming + * @retval Between Min_Data = 0 and Max_Data = 63 + */ +__STATIC_INLINE uint32_t LL_RCC_HSE_GetClockTrimming(void) +{ + return (uint32_t)(READ_BIT(RCC->ECSCR1, RCC_ECSCR1_HSETRIM) >> RCC_ECSCR1_HSETRIM_Pos); +} +/** + * @} + */ + +/** @defgroup RCC_LL_EF_HSI HSI + * @{ + */ + +/** + * @brief Enable HSI even in stop mode + * @note HSI oscillator is forced ON even in Stop mode + * @rmtoll CR HSIKERON LL_RCC_HSI_EnableInStopMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_EnableInStopMode(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSIKERON); +} + +/** + * @brief Disable HSI in stop mode + * @rmtoll CR HSIKERON LL_RCC_HSI_DisableInStopMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON); +} + +/** + * @brief Check if HSI is enabled in stop mode + * @rmtoll CR HSIKERON LL_RCC_HSI_IsEnabledInStopMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_IsEnabledInStopMode(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_HSIKERON) == RCC_CR_HSIKERON) ? 1UL : 0UL); +} + +/** + * @brief Enable HSI oscillator + * @rmtoll CR HSION LL_RCC_HSI_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSION); +} + +/** + * @brief Disable HSI oscillator + * @rmtoll CR HSION LL_RCC_HSI_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSION); +} + +/** + * @brief Check if HSI clock is ready + * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RCC_CR_HSIRDY) ? 1UL : 0UL); +} + +/** + * @brief Get HSI Calibration value + * @note When HSITRIM is written, HSICAL is updated with the sum of + * HSITRIM and the factory trim value + * @rmtoll ICSCR3 HSICAL LL_RCC_HSI_GetCalibration + * @retval Between Min_Data = 0 and Max_Data = 4095 + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void) +{ + return (uint32_t)(READ_BIT(RCC->ICSCR3, RCC_ICSCR3_HSICAL) >> RCC_ICSCR3_HSICAL_Pos); +} + +/** + * @brief Set HSI Calibration trimming + * @note user-programmable trimming value that is added to the HSICAL + * @note Default value is 16, which, when added to the HSICAL value, + * should trim the HSI to 16 MHz +/- 1 % + * @rmtoll ICSCR3 HSITRIM LL_RCC_HSI_SetCalibTrimming + * @param Value Between Min_Data = 0 and Max_Data = 31 + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value) +{ + MODIFY_REG(RCC->ICSCR3, RCC_ICSCR3_HSITRIM, Value << RCC_ICSCR3_HSITRIM_Pos); +} + +/** + * @brief Get HSI Calibration trimming + * @rmtoll ICSCR3 HSITRIM LL_RCC_HSI_GetCalibTrimming + * @retval Between Min_Data = 0 and Max_Data = 31 + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void) +{ + return (uint32_t)(READ_BIT(RCC->ICSCR3, RCC_ICSCR3_HSITRIM) >> RCC_ICSCR3_HSITRIM_Pos); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_LSE LSE + * @{ + */ + +/** + * @brief Enable Low Speed External (LSE) crystal. + * @rmtoll BDCR1 LSEON LL_RCC_LSE_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_Enable(void) +{ + SET_BIT(RCC->BDCR1, RCC_BDCR1_LSEON); +} + +/** + * @brief Disable Low Speed External (LSE) crystal. + * @rmtoll BDCR1 LSEON LL_RCC_LSE_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_Disable(void) +{ + CLEAR_BIT(RCC->BDCR1, RCC_BDCR1_LSEON); +} + +/** + * @brief Enable external clock source (LSE bypass). + * @rmtoll BDCR1 LSEBYP LL_RCC_LSE_EnableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void) +{ + SET_BIT(RCC->BDCR1, RCC_BDCR1_LSEBYP); +} + +/** + * @brief Disable external clock source (LSE bypass). + * @rmtoll BDCR1 LSEBYP LL_RCC_LSE_DisableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void) +{ + CLEAR_BIT(RCC->BDCR1, RCC_BDCR1_LSEBYP); +} + +/** + * @brief Enable LSE clock glitch filter. + * @rmtoll BDCR1 LSEGFON LL_RCC_LSE_EnableGlitchFilter + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_EnableGlitchFilter(void) +{ + SET_BIT(RCC->BDCR1, RCC_BDCR1_LSEGFON); +} + +/** + * @brief Disable LSE clock glitch filter. + * @rmtoll BDCR1 LSEGFON LL_RCC_LSE_DisableGlitchFilter + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_DisableGlitchFilter(void) +{ + CLEAR_BIT(RCC->BDCR1, RCC_BDCR1_LSEGFON); +} + +/** + * @brief Set LSE trimming + * @rmtoll BDCR1 LSETRIM LL_RCC_LSE_SetClockTrimming + * @param LSETrim This parameter can be one of the following values: + * @arg @ref LL_RCC_LSETRIMMING_R + * @arg @ref LL_RCC_LSETRIMMING_3_4_R + * @arg @ref LL_RCC_LSETRIMMING_2_3_R + * @arg @ref LL_RCC_LSETRIMMING_1_2_R + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_SetClockTrimming(uint32_t LSETrim) +{ + MODIFY_REG(RCC->BDCR1, RCC_BDCR1_LSETRIM, LSETrim); +} + +/** + * @brief Get LSE trimming + * @rmtoll BDCR1 LSETRIM LL_RCC_LSE_GetClockTrimming + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LSETRIMMING_R + * @arg @ref LL_RCC_LSETRIMMING_3_4_R + * @arg @ref LL_RCC_LSETRIMMING_2_3_R + * @arg @ref LL_RCC_LSETRIMMING_1_2_R + * @retval None + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_GetClockTrimming(void) +{ + return (uint32_t)(READ_BIT(RCC->BDCR1, RCC_BDCR1_LSETRIM)); +} + +/** + * @brief Set LSE oscillator drive capability + * @note The oscillator is in Xtal mode when it is not in bypass mode. + * @rmtoll BDCR1 LSEDRV LL_RCC_LSE_SetDriveCapability + * @param LSEDrive This parameter can be one of the following values: + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH + * @arg @ref LL_RCC_LSEDRIVE_HIGH + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive) +{ + MODIFY_REG(RCC->BDCR1, RCC_BDCR1_LSEDRV, LSEDrive); +} + +/** + * @brief Get LSE oscillator drive capability + * @rmtoll BDCR1 LSEDRV LL_RCC_LSE_GetDriveCapability + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH + * @arg @ref LL_RCC_LSEDRIVE_HIGH + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void) +{ + return (uint32_t)(READ_BIT(RCC->BDCR1, RCC_BDCR1_LSEDRV)); +} + +/** + * @brief Enable Clock security system on LSE. + * @rmtoll BDCR1 LSECSSON LL_RCC_LSE_EnableCSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_EnableCSS(void) +{ + SET_BIT(RCC->BDCR1, RCC_BDCR1_LSECSSON); +} + +/** + * @brief Disable Clock security system on LSE. + * @note Clock security system can be disabled only after a LSE + * failure detection. In that case it MUST be disabled by software. + * @rmtoll BDCR1 LSECSSON LL_RCC_LSE_DisableCSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_DisableCSS(void) +{ + CLEAR_BIT(RCC->BDCR1, RCC_BDCR1_LSECSSON); +} + +/** + * @brief Check if LSE oscillator Ready + * @rmtoll BDCR1 LSERDY LL_RCC_LSE_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void) +{ + return ((READ_BIT(RCC->BDCR1, RCC_BDCR1_LSERDY) == RCC_BDCR1_LSERDY) ? 1UL : 0UL); +} + +/** + * @brief Enable LSE oscillator propagation for system clock + * @rmtoll BDCR1 LSESYSEN LL_RCC_LSE_EnablePropagation + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_EnablePropagation(void) +{ + SET_BIT(RCC->BDCR1, RCC_BDCR1_LSESYSEN); +} + +/** + * @brief Disable LSE oscillator propagation for system clock + * @rmtoll BDCR1 LSESYSEN LL_RCC_LSE_DisablePropagation + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_DisablePropagation(void) +{ + CLEAR_BIT(RCC->BDCR1, RCC_BDCR1_LSESYSEN); +} + +/** + * @brief Check if LSE oscillator propagation for system clock Ready + * @rmtoll BDCR1 LSESYSRDY LL_RCC_LSE_IsPropagationReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_IsPropagationReady(void) +{ + return ((READ_BIT(RCC->BDCR1, RCC_BDCR1_LSESYSRDY) == RCC_BDCR1_LSESYSRDY) ? 1UL : 0UL); +} + +/** + * @brief Check if CSS on LSE failure Detection + * @rmtoll BDCR1 LSECSSD LL_RCC_LSE_IsCSSDetected + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void) +{ + return ((READ_BIT(RCC->BDCR1, RCC_BDCR1_LSECSSD) == RCC_BDCR1_LSECSSD) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_LSI1 LSI1 + * @{ + */ + +/** + * @brief Enable LSI1 Oscillator + * @rmtoll BDCR1 LSI1ON LL_RCC_LSI1_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSI1_Enable(void) +{ + SET_BIT(RCC->BDCR1, RCC_BDCR1_LSI1ON); +} + +/** + * @brief Disable LSI1 Oscillator + * @rmtoll BDCR1 LSI1ON LL_RCC_LSI1_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSI1_Disable(void) +{ + CLEAR_BIT(RCC->BDCR1, RCC_BDCR1_LSI1ON); +} + +/** + * @brief Check if LSI1 is Ready + * @rmtoll BDCR1 LSI1RDY LL_RCC_LSI1_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSI1_IsReady(void) +{ + return ((READ_BIT(RCC->BDCR1, RCC_BDCR1_LSI1RDY) == RCC_BDCR1_LSI1RDY) ? 1UL : 0UL); +} + +/** + * @brief Set LSI1 prescaler + * @rmtoll BDCR1 LSI1PREDIV LL_RCC_LSI1_SetPrescaler + * @param LSI1Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_LSI_DIV_1 + * @arg @ref LL_RCC_LSI_DIV_128 + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSI1_SetPrescaler(uint32_t LSI1Prescaler) +{ + MODIFY_REG(RCC->BDCR1, RCC_BDCR1_LSI1PREDIV, LSI1Prescaler); +} + +/** + * @brief Get LSI1 prescaler + * @rmtoll BDCR1 LSI1PREDIV LL_RCC_LSI1_GetPrescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LSI_DIV_1 + * @arg @ref LL_RCC_LSI_DIV_128 + */ +__STATIC_INLINE uint32_t LL_RCC_LSI1_GetPrescaler(void) +{ + return (READ_BIT(RCC->BDCR1, RCC_BDCR1_LSI1PREDIV)); +} + +/** + * @} + */ + +#if defined(RCC_LSI2_SUPPORT) +/** @defgroup RCC_LL_EF_LSI2 LSI2 + * @{ + */ + +/** + * @brief Enable LSI2 Oscillator + * @rmtoll BDCR1 LSI2ON LL_RCC_LSI2_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSI2_Enable(void) +{ + SET_BIT(RCC->BDCR1, RCC_BDCR1_LSI2ON); +} + +/** + * @brief Disable LSI2 Oscillator + * @rmtoll BDCR1 LSI2ON LL_RCC_LSI2_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSI2_Disable(void) +{ + CLEAR_BIT(RCC->BDCR1, RCC_BDCR1_LSI2ON); +} + +/** + * @brief Check if LSI2 is Ready + * @rmtoll BDCR1 LSI2RDY LL_RCC_LSI2_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSI2_IsReady(void) +{ + return ((READ_BIT(RCC->BDCR1, RCC_BDCR1_LSI2RDY) == RCC_BDCR1_LSI2RDY) ? 1UL : 0UL); +} + +/** + * @brief Configure LSI2 oscillator temperature sensitivity + * @rmtoll BDCR2 LSI2CFG LL_RCC_LSI2_SetTempSensitivity + * @param Sensitivity This parameter can be one of the following values: + * @arg @ref LL_RCC_LSI2_TEMP_SENSITIVITY_80 + * @arg @ref LL_RCC_LSI2_TEMP_SENSITIVITY_50 + * @arg @ref LL_RCC_LSI2_TEMP_SENSITIVITY_20 + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSI2_SetTempSensitivity(uint32_t Sensitivity) +{ + MODIFY_REG(RCC->BDCR2, RCC_BDCR2_LSI2CFG, Sensitivity); +} + +/** + * @brief Get LSI2 oscillator temperature sensitivity + * @rmtoll BDCR2 LSI2CFG LL_RCC_LSI2_GetTempSensitivity + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LSI2_TEMP_SENSITIVITY_80 + * @arg @ref LL_RCC_LSI2_TEMP_SENSITIVITY_50 + * @arg @ref LL_RCC_LSI2_TEMP_SENSITIVITY_20 + */ +__STATIC_INLINE uint32_t LL_RCC_LSI2_GetTempSensitivity(void) +{ + return (uint32_t)(READ_BIT(RCC->BDCR2, RCC_BDCR2_LSI2CFG)); +} + +/** + * @brief Configure LSI2 operating mode configuration + * @rmtoll BDCR2 LSI2MODE LL_RCC_LSI2_SetOperatingMode + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_RCC_LSI2_NOMINAL_MODE + * @arg @ref LL_RCC_LSI2_LOWPOWER_MODE + * @arg @ref LL_RCC_LSI2_ULTRALOWPOWER_MODE + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSI2_SetOperatingMode(uint32_t Mode) +{ + MODIFY_REG(RCC->BDCR2, RCC_BDCR2_LSI2MODE, Mode); +} + +/** + * @brief Get LSI2 oscillator operating mode + * @rmtoll BDCR2 LSI2MODE LL_RCC_LSI2_GetOperatingMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LSI2_NOMINAL_MODE + * @arg @ref LL_RCC_LSI2_LOWPOWER_MODE + * @arg @ref LL_RCC_LSI2_ULTRALOWPOWER_MODE + */ +__STATIC_INLINE uint32_t LL_RCC_LSI2_GetOperatingMode(void) +{ + return (uint32_t)(READ_BIT(RCC->BDCR2, RCC_BDCR2_LSI2MODE)); +} + +/** + * @} + */ +#endif /* LSI2 */ + +/** @defgroup RCC_LL_EF_LSCO LSCO + * @{ + */ + +/** + * @brief Enable Low speed clock + * @rmtoll BDCR1 LSCOEN LL_RCC_LSCO_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSCO_Enable(void) +{ + SET_BIT(RCC->BDCR1, RCC_BDCR1_LSCOEN); +} + +/** + * @brief Disable Low speed clock + * @rmtoll BDCR1 LSCOEN LL_RCC_LSCO_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSCO_Disable(void) +{ + CLEAR_BIT(RCC->BDCR1, RCC_BDCR1_LSCOEN); +} + +/** + * @brief Configure Low speed clock selection + * @rmtoll BDCR1 LSCOSEL LL_RCC_LSCO_SetSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI + * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSCO_SetSource(uint32_t Source) +{ + MODIFY_REG(RCC->BDCR1, RCC_BDCR1_LSCOSEL, Source); +} + +/** + * @brief Get Low speed clock selection + * @rmtoll BDCR1 LSCOSEL LL_RCC_LSCO_GetSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI + * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE + */ +__STATIC_INLINE uint32_t LL_RCC_LSCO_GetSource(void) +{ + return (uint32_t)(READ_BIT(RCC->BDCR1, RCC_BDCR1_LSCOSEL)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_System System + * @{ + */ + +/** + * @brief Configure the system clock source + * @rmtoll CFGR1 SW LL_RCC_SetSysClkSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE + * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL1R + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source) +{ + MODIFY_REG(RCC->CFGR1, RCC_CFGR1_SW, Source); +} + +/** + * @brief Get the system clock source + * @rmtoll CFGR1 SWS LL_RCC_GetSysClkSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL1R + */ +__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR1, RCC_CFGR1_SWS)); +} + +/** + * @brief Set AHB prescaler + * @rmtoll CFGR2 HPRE LL_RCC_SetAHBPrescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_HPRE, Prescaler); +} + +/** + * @brief Set Systick clock source + * @rmtoll CCIPR1 SYSTICKSEL LL_RCC_SetSystickClockSource + * @param SystickSource This parameter can be one of the following values: + * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_LSI + * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_LSE + * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_HCLKDIV8 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSystickClockSource(uint32_t SystickSource) +{ + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_SYSTICKSEL, SystickSource); +} + +/** + * @brief Set APB1 prescaler + * @rmtoll CFGR2 PPRE1 LL_RCC_SetAPB1Prescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE1, Prescaler); +} + +/** + * @brief Set APB2 prescaler + * @rmtoll CFGR2 PPRE2 LL_RCC_SetAPB2Prescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_APB2_DIV_1 + * @arg @ref LL_RCC_APB2_DIV_2 + * @arg @ref LL_RCC_APB2_DIV_4 + * @arg @ref LL_RCC_APB2_DIV_8 + * @arg @ref LL_RCC_APB2_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE2, Prescaler); +} + +/** + * @brief Set APB7 prescaler + * @rmtoll CFGR3 PPRE7 LL_RCC_SetAPB7Prescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_APB7_DIV_1 + * @arg @ref LL_RCC_APB7_DIV_2 + * @arg @ref LL_RCC_APB7_DIV_4 + * @arg @ref LL_RCC_APB7_DIV_8 + * @arg @ref LL_RCC_APB7_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAPB7Prescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR3, RCC_CFGR3_PPRE7, Prescaler); +} + +/** + * @brief Set AHB5 prescaler when SYSCLK is PLL1R + * @rmtoll CFGR4 HPRE5 LL_RCC_SetAHB5Prescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_AHB5_DIV_1 + * @arg @ref LL_RCC_AHB5_DIV_2 + * @arg @ref LL_RCC_AHB5_DIV_3 + * @arg @ref LL_RCC_AHB5_DIV_4 + * @arg @ref LL_RCC_AHB5_DIV_6 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAHB5Prescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR4, RCC_CFGR4_HPRE5, Prescaler); +} + +/** + * @brief Set AHB5 divider when SYSCLK is HSI or HSE + * @rmtoll CFGR4 HDIV5 LL_RCC_SetAHB5Divider + * @param Divider This parameter can be one of the following values: + * @arg @ref LL_RCC_AHB5_DIVIDER_1 + * @arg @ref LL_RCC_AHB5_DIVIDER_2 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAHB5Divider(uint32_t Divider) +{ + MODIFY_REG(RCC->CFGR4, RCC_CFGR4_HDIV5, Divider); +} + +/** + * @brief Get AHB prescaler + * @rmtoll CFGR2 HPRE LL_RCC_GetAHBPrescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_HPRE)); +} + +/** + * @brief Get Sysctick clock source + * @rmtoll CCIPR1 SYSTICKSEL LL_RCC_SetSystickClockSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_LSI + * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_LSE + * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_HCLKDIV8 + */ +__STATIC_INLINE uint32_t LL_RCC_GetSystickClockSource(void) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_SYSTICKSEL)); +} + +/** + * @brief Get APB1 prescaler + * @rmtoll CFGR2 PPRE1 LL_RCC_GetAPB1Prescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PPRE1)); +} + +/** + * @brief Get APB2 prescaler + * @rmtoll CFGR2 PPRE2 LL_RCC_GetAPB2Prescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_APB2_DIV_1 + * @arg @ref LL_RCC_APB2_DIV_2 + * @arg @ref LL_RCC_APB2_DIV_4 + * @arg @ref LL_RCC_APB2_DIV_8 + * @arg @ref LL_RCC_APB2_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PPRE2)); +} + +/** + * @brief Get APB7 prescaler + * @rmtoll CFGR3 PPRE7 LL_RCC_GetAPB7Prescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_APB7_DIV_1 + * @arg @ref LL_RCC_APB7_DIV_2 + * @arg @ref LL_RCC_APB7_DIV_4 + * @arg @ref LL_RCC_APB7_DIV_8 + * @arg @ref LL_RCC_APB7_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAPB7Prescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_PPRE7)); +} + +/** + * @brief Get AHB5 prescaler when SYSCLK is PLL1R + * @rmtoll CFGR4 HPRE5 LL_RCC_GetAHB5Prescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_AHB5_DIV_1 + * @arg @ref LL_RCC_AHB5_DIV_2 + * @arg @ref LL_RCC_AHB5_DIV_3 + * @arg @ref LL_RCC_AHB5_DIV_4 + * @arg @ref LL_RCC_AHB5_DIV_6 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAHB5Prescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR4, RCC_CFGR4_HPRE5)); +} + +/** + * @brief Get AHB5 divider when SYSCLK is HSI or HSE + * @rmtoll CFGR4 HDIV5 LL_RCC_GetAHB5Divider + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_AHB5_DIVIDER_1 + * @arg @ref LL_RCC_AHB5_DIVIDER_2 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAHB5Divider(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR4, RCC_CFGR4_HDIV5)); +} +/** + * @} + */ + +/** @defgroup RCC_LL_EF_RADIO RADIO + * @{ + */ + +/** + * @brief Enable the 2.4 GHz RADIO baseband clock + * @rmtoll RADIOENR BBCLKEN LL_RCC_RADIO_EnableBasebandClock + * @retval None + */ +__STATIC_INLINE void LL_RCC_RADIO_EnableBasebandClock(void) +{ + SET_BIT(RCC->RADIOENR, RCC_RADIOENR_BBCLKEN); +} + +/** + * @brief Disable the 2.4 GHz RADIO baseband clock + * @rmtoll RADIOENR BBCLKEN LL_RCC_RADIO_DisableBasebandClock + * @retval None + */ +__STATIC_INLINE void LL_RCC_RADIO_DisableBasebandClock(void) +{ + CLEAR_BIT(RCC->RADIOENR, RCC_RADIOENR_BBCLKEN); +} + +/** + * @brief Check if 2.4 GHz RADIO baseband clock is enabled + * @rmtoll RADIOENR BBCLKEN LL_RCC_RADIO_IsEnabledBasebandClock + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_RADIO_IsEnabledBasebandClock(void) +{ + return ((READ_BIT(RCC->RADIOENR, RCC_RADIOENR_BBCLKEN) == RCC_RADIOENR_BBCLKEN) ? 1UL : 0UL); +} + +/** + * @brief Disable the 2.4 GHz RADIO bus clock and HSE32 oscillator by 2.4 GHz RADIO sleep timer wakeup event + * @rmtoll RADIOENR STRADIOCLKON LL_RCC_RADIO_DisableSleepTimerClock + * @retval None + */ +__STATIC_INLINE void LL_RCC_RADIO_DisableSleepTimerClock(void) +{ + CLEAR_BIT(RCC->RADIOENR, RCC_RADIOENR_STRADIOCLKON); +} + +/** + * @brief Check if 2.4 GHz RADIO bus clock and HSE32 oscillator are enabled by 2.4 GHz RADIO sleep timer wakeup event + * @rmtoll RADIOENR STRADIOCLKON LL_RCC_RADIO_IsEnabledSleepTimerClock + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_RADIO_IsEnabledSleepTimerClock(void) +{ + return ((READ_BIT(RCC->RADIOENR, RCC_RADIOENR_STRADIOCLKON) == RCC_RADIOENR_STRADIOCLKON) ? 1UL : 0UL); +} + +/** + * @brief Check if 2.4 GHz RADIO bus clock is ready + * @rmtoll RADIOENR RADIOCLKRDY LL_RCC_RADIO_IsBusClockReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_RADIO_IsBusClockReady(void) +{ + return ((READ_BIT(RCC->RADIOENR, RCC_RADIOENR_RADIOCLKRDY) == RCC_RADIOENR_RADIOCLKRDY) ? 1UL : 0UL); +} + +/** + * @brief Set the 2.4 GHz RADIO sleep timer kernel clock + * @rmtoll BDCR1 RADIOSTSEL LL_RCC_RADIO_SetSleepTimerClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_RADIOSLEEPSOURCE_NONE + * @arg @ref LL_RCC_RADIOSLEEPSOURCE_LSE + * @arg @ref LL_RCC_RADIOSLEEPSOURCE_LSI (*) + * @arg @ref LL_RCC_RADIOSLEEPSOURCE_HSE_DIV1000 + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RCC_RADIO_SetSleepTimerClockSource(uint32_t Source) +{ + MODIFY_REG(RCC->BDCR1, RCC_BDCR1_RADIOSTSEL, Source); +} + +/** + * @brief Get the 2.4 GHz RADIO sleep timer kernel clock + * @rmtoll BDCR1 RADIOSTSEL LL_RCC_RADIO_GetSleepTimerClockSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_RADIOSLEEPSOURCE_NONE + * @arg @ref LL_RCC_RADIOSLEEPSOURCE_LSE + * @arg @ref LL_RCC_RADIOSLEEPSOURCE_LSI (*) + * @arg @ref LL_RCC_RADIOSLEEPSOURCE_HSE_DIV1000 + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_RCC_RADIO_GetSleepTimerClockSource(void) +{ + return (uint32_t)(READ_BIT(RCC->BDCR1, RCC_BDCR1_RADIOSTSEL)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_MCO MCO + * @{ + */ + +/** + * @brief Configure MCOx + * @rmtoll CFGR1 MCOSEL LL_RCC_ConfigMCO\n + * CFGR1 MCOPRE LL_RCC_ConfigMCO + * @param MCOxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK + * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK + * @arg @ref LL_RCC_MCO1SOURCE_HSI + * @arg @ref LL_RCC_MCO1SOURCE_HSE + * @arg @ref LL_RCC_MCO1SOURCE_PLL1R + * @arg @ref LL_RCC_MCO1SOURCE_PLL1Q + * @arg @ref LL_RCC_MCO1SOURCE_PLL1P + * @arg @ref LL_RCC_MCO1SOURCE_LSI + * @arg @ref LL_RCC_MCO1SOURCE_LSE + * @arg @ref LL_RCC_MCO1SOURCE_HCLK5 + * @param MCOxPrescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_MCO1_DIV_1 + * @arg @ref LL_RCC_MCO1_DIV_2 + * @arg @ref LL_RCC_MCO1_DIV_4 + * @arg @ref LL_RCC_MCO1_DIV_8 + * @arg @ref LL_RCC_MCO1_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler) +{ + MODIFY_REG(RCC->CFGR1, RCC_CFGR1_MCOSEL | RCC_CFGR1_MCOPRE, MCOxSource | MCOxPrescaler); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source + * @{ + */ + +/** + * @brief Configure USARTx clock source + * @rmtoll CCIPR1 USART1SEL LL_RCC_SetUSARTClockSource\n + * CCIPR1 USART2SEL LL_RCC_SetUSARTClockSource\n + * @param USARTxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource) +{ + MODIFY_REG(RCC->CCIPR1, USARTxSource >> 16U, (USARTxSource & 0x0000FFFFU)); +} + +/** + * @brief Configure LPUARTx clock source + * @rmtoll CCIPR3 LPUART1SEL LL_RCC_SetLPUARTClockSource + * @param LPUARTxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK7 + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource) +{ + MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_LPUART1SEL, LPUARTxSource); +} + +/** + * @brief Configure I2Cx clock source + * @rmtoll CCIPR1 I2C1SEL LL_RCC_SetI2CClockSource\n + * CCIPR3 I2C3SEL LL_RCC_SetI2CClockSource\n + * @param I2CxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK7 + * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource) +{ + __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (I2CxSource >> 24U)); + MODIFY_REG(*reg, 3U << (((I2CxSource & 0x00FF0000U) >> 16U) & 0x1FU), ((I2CxSource & 0x000000FFU) << (((I2CxSource & 0x00FF0000U) >> 16U) & 0x1FU))); +} + +/** + * @brief Configure SPIx clock source + * @rmtoll CCIPR1 SPI1SEL LL_RCC_SetSPIClockSource\n + * CCIPR3 SPI3SEL LL_RCC_SetSPIClockSource\n + * @param SPIxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_SPI1_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_SPI1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_SPI1_CLKSOURCE_HSI + * @arg @ref LL_RCC_SPI3_CLKSOURCE_PCLK7 + * @arg @ref LL_RCC_SPI3_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_SPI3_CLKSOURCE_HSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSPIClockSource(uint32_t SPIxSource) +{ + __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (SPIxSource >> 24U)); + MODIFY_REG(*reg, 3U << (((SPIxSource & 0x00FF0000U) >> 16U) & 0x1FU), ((SPIxSource & 0x000000FFU) << (((SPIxSource & 0x00FF0000U) >> 16U) & 0x1FU))); +} + +/** + * @brief Configure LPTIMx clock source + * @rmtoll CCIPR3 LPTIM1SEL LL_RCC_SetLPTIMClockSource\n + * CCIPR1 LPTIM2SEL LL_RCC_SetLPTIMClockSource\n + * @param LPTIMxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK7 + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource) +{ + __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (LPTIMxSource >> 24U)); + MODIFY_REG(*reg, 3U << (((LPTIMxSource & 0x00FF0000U) >> 16U) & 0x1FU), ((LPTIMxSource & 0x000000FFU) << (((LPTIMxSource & 0x00FF0000U) >> 16U) & 0x1FU))); +} + + +/** + * @brief Configure SAIx clock source + * @rmtoll CCIPR2 SAI1SEL LL_RCC_SetSAIClockSource\n + * @param SAIxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1P(*) + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q(*) + * @arg @ref LL_RCC_SAI1_CLKSOURCE_SYSCLK(*) + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN(*) + * @arg @ref LL_RCC_SAI1_CLKSOURCE_HSI(*) + * (*) Feature not available on all devices of the family + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource) +{ + MODIFY_REG(RCC->CCIPR2, (SAIxSource >> 16U), (SAIxSource & 0x0000FFFFU)); +} + +/** + * @brief Configure RNG clock source + * @rmtoll CCIPR2 RNGSEL LL_RCC_SetRNGClockSource + * @param RNGxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_RNG_CLKSOURCE_LSE + * @arg @ref LL_RCC_RNG_CLKSOURCE_LSI + * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI + * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL1Q_DIV2 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource) +{ + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_RNGSEL, RNGxSource); +} + +/** + * @brief Configure ADC clock source + * @rmtoll CCIPR3 ADCSEL LL_RCC_SetADCClockSource + * @param ADC4Source This parameter can be one of the following values: + * @arg @ref LL_RCC_ADC_CLKSOURCE_HCLK + * @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_ADC_CLKSOURCE_PLL1P + * @arg @ref LL_RCC_ADC_CLKSOURCE_HSE + * @arg @ref LL_RCC_ADC_CLKSOURCE_HSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADC4Source) +{ + MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_ADCSEL, ADC4Source); +} + + +/** + * @brief Get USARTx clock source + * @rmtoll CCIPR1 USART1SEL LL_RCC_GetUSARTClockSource\n + * CCIPR1 USART2SEL LL_RCC_GetUSARTClockSource\n + * @param USARTx This parameter can be one of the following values: + * @arg @ref LL_RCC_USART1_CLKSOURCE + * @arg @ref LL_RCC_USART2_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE + */ +__STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR1, USARTx) | (USARTx << 16U)); +} + +/** + * @brief Get LPUARTx clock source + * @rmtoll CCIPR3 LPUART1SEL LL_RCC_GetLPUARTClockSource + * @param LPUARTx This parameter can be one of the following values: + * @arg @ref LL_RCC_LPUART1_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK7 + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE + */ +__STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR3, LPUARTx)); +} + +/** + * @brief Get I2Cx clock source + * @rmtoll CCIPR1 I2C1SEL LL_RCC_GetI2CClockSource\n + * CCIPR3 I2C3SEL LL_RCC_GetI2CClockSource\n + * @param I2Cx This parameter can be one of the following values: + * @arg @ref LL_RCC_I2C1_CLKSOURCE + * @arg @ref LL_RCC_I2C3_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK7 + * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI + */ +__STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx) +{ + __IO const uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (I2Cx >> 24U)); + return (uint32_t)((READ_BIT(*reg, (3UL << (((I2Cx & 0x00FF0000UL) >> 16U) & 0x1FUL))) >> (((I2Cx & 0x00FF0000UL) >> 16U) & 0x1FUL)) | (I2Cx & 0xFFFF0000UL)); +} + +/** + * @brief Get SPIx clock source + * @rmtoll CCIPR1 SPI1SEL LL_RCC_GetSPIClockSource\n + * CCIPR3 SPI3SEL LL_RCC_GetSPIClockSource + * @param SPIx This parameter can be one of the following values: + * @arg @ref LL_RCC_SPI1_CLKSOURCE + * @arg @ref LL_RCC_SPI3_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SPI1_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_SPI1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_SPI1_CLKSOURCE_HSI + * @arg @ref LL_RCC_SPI3_CLKSOURCE_PCLK7 + * @arg @ref LL_RCC_SPI3_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_SPI3_CLKSOURCE_HSI + */ +__STATIC_INLINE uint32_t LL_RCC_GetSPIClockSource(uint32_t SPIx) +{ + __IO const uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (SPIx >> 24U)); + return (uint32_t)((READ_BIT(*reg, (3UL << (((SPIx & 0x00FF0000UL) >> 16U) & 0x1FUL))) >> (((SPIx & 0x00FF0000UL) >> 16U) & 0x1FUL)) | (SPIx & 0xFFFF0000UL)); +} + +/** + * @brief Get LPTIMx clock source + * @rmtoll CCIPR3 LPTIM1SEL LL_RCC_GetLPTIMClockSource\n + * CCIPR1 LPTIM2SEL LL_RCC_GetLPTIMClockSource\n + * @param LPTIMx This parameter can be one of the following values: + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK7 + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE + */ +__STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx) +{ + __IO const uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (LPTIMx >> 24U)); + return (uint32_t)((READ_BIT(*reg, (3UL << (((LPTIMx & 0x00FF0000UL) >> 16U) & 0x1FUL))) >> (((LPTIMx & 0x00FF0000UL) >> 16U) & 0x1FUL)) | (LPTIMx & 0xFFFF0000UL)); +} + +/** + * @brief Set Tim Input capture clock source + * @rmtoll CCIPR1 TIMICSEL LL_RCC_SetTIMICClockSource + * @param TIMICSource This parameter can be one of the following combined values: + * @arg @ref LL_RCC_TIMIC_CLKSOURCE_NONE + * @arg @ref LL_RCC_TIMIC_CLKSOURCE_HSI_DIV256 + * @note HSI clock without division is also available when TIMICSEL[2] is 1. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetTIMICClockSource(uint32_t TIMICSource) +{ + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_TIMICSEL, TIMICSource); +} + +/** + * @brief Get Tim Input capture clock source + * @rmtoll CCIPR1 TIMICSEL LL_RCC_GetTIMICClockSource + * @retval Returned value can be one of the following combined values: + * @arg @ref LL_RCC_TIMIC_CLKSOURCE_NONE + * @arg @ref LL_RCC_TIMIC_CLKSOURCE_HSI_DIV256 + */ +__STATIC_INLINE uint32_t LL_RCC_GetTIMICClockSource(void) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_TIMICSEL)); +} + +/** + * @brief Get SAIx clock source + * @rmtoll CCIPR2 SAI1SEL LL_RCC_GetSAIClockSource\n + * @param SAIx This parameter can be one of the following values: + * @arg @ref LL_RCC_SAI1_CLKSOURCE(*) + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1P(*) + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q(*) + * @arg @ref LL_RCC_SAI1_CLKSOURCE_SYSCLK(*) + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN(*) + * @arg @ref LL_RCC_SAI1_CLKSOURCE_HSI(*) + * (*) Feature not available on all devices of the family + */ +__STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR2, SAIx) | (SAIx << 16U)); +} + +/** + * @brief Get RNGx clock source + * @rmtoll CCIPR2 RNGSEL LL_RCC_GetRNGClockSource + * @param RNGx This parameter can be one of the following values: + * @arg @ref LL_RCC_RNG_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_RNG_CLKSOURCE_LSE + * @arg @ref LL_RCC_RNG_CLKSOURCE_LSI + * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI + * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL1Q_DIV2 + */ +__STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR2, RNGx)); +} + +/** + * @brief Get ADCx clock source + * @rmtoll CCIPR3 ADCSEL LL_RCC_GetADCClockSource + * @param ADCx This parameter can be one of the following values: + * @arg @ref LL_RCC_ADC_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_ADC_CLKSOURCE_HCLK + * @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_ADC_CLKSOURCE_PLL1P + * @arg @ref LL_RCC_ADC_CLKSOURCE_HSE + * @arg @ref LL_RCC_ADC_CLKSOURCE_HSI + */ +__STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR3, ADCx)); +} + + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_RTC RTC + * @{ + */ + +/** + * @brief Set RTC Clock Source + * @note Once the RTC clock source has been selected, it cannot be changed anymore unless + * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is + * set). The BDRST bit can be used to reset them. + * @rmtoll BDCR1 RTCSEL LL_RCC_SetRTCClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI + * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source) +{ + MODIFY_REG(RCC->BDCR1, RCC_BDCR1_RTCSEL, Source); +} + +/** + * @brief Get RTC Clock Source + * @rmtoll BDCR1 RTCSEL LL_RCC_GetRTCClockSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI + * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32 + */ +__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void) +{ + return (uint32_t)(READ_BIT(RCC->BDCR1, RCC_BDCR1_RTCSEL)); +} + +/** + * @brief Force the Backup domain reset + * @rmtoll BDCR1 BDRST LL_RCC_ForceBackupDomainReset + * @retval None + */ +__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void) +{ + SET_BIT(RCC->BDCR1, RCC_BDCR1_BDRST); +} + +/** + * @brief Release the Backup domain reset + * @rmtoll BDCR1 BDRST LL_RCC_ReleaseBackupDomainReset + * @retval None + */ +__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void) +{ + CLEAR_BIT(RCC->BDCR1, RCC_BDCR1_BDRST); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_PLL1 PLL1 + * @{ + */ + +/** + * @brief Enable PLL1 + * @rmtoll CR PLL1ON LL_RCC_PLL1_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_PLL1ON); +} + +/** + * @brief Disable PLL1 + * @note Cannot be disabled if the PLL1 clock is used as the system clock + * @rmtoll CR PLL1ON LL_RCC_PLL1_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON); +} + +/** + * @brief Check if PLL1 Ready + * @rmtoll CR PLL1RDY LL_RCC_PLL1_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_PLL1RDY) == RCC_CR_PLL1RDY) ? 1UL : 0UL); +} + +/** + * @brief Enable prescaler division on PLL1RCLK for SYSCLK + * @rmtoll PLL1CFGR PLL1RCLKPRE LL_RCC_PLL1_EnablePLL1RCLKDivision + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1_EnablePLL1RCLKDivision(void) +{ + SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1RCLKPRE); +} + +/** + * @brief Disable PLL1RCLK for SYSCLK prescaler division + * @rmtoll PLL1CFGR PLL1RCLKPRE LL_RCC_PLL1_DisablePLL1RCLKDivision + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1_DisablePLL1RCLKDivision(void) +{ + CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1RCLKPRE); +} + +/** + * @brief Set the division step of PLL1RCLK clock for SYSCLK + * @rmtoll PLL1CFGR PLL1RCLKPRESTEP LL_RCC_PLL1_SetPLL1RCLKDivisionStep + * @param Step This parameter can be one of the following values: + * @arg @ref LL_RCC_PLL1RCLK_2_STEP_DIV + * @arg @ref LL_RCC_PLL1RCLK_3_STEP_DIV + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1_SetPLL1RCLKDivisionStep(uint32_t Step) +{ + MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1RCLKPRESTEP, Step); +} + +/** + * @brief Get the division step of PLL1RCLK clock for SYSCLK + * @rmtoll PLL1CFGR PLL1RCLKPRESTEP LL_RCC_PLL1_GetPLL1RCLKDivisionStep + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLL1RCLK_2_STEP_DIV + * @arg @ref LL_RCC_PLL1RCLK_3_STEP_DIV + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_GetPLL1RCLKDivisionStep(void) +{ + return (uint32_t)(READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1RCLKPRESTEP)); +} + +/** + * @brief Check if prescaler division on PLL1RCLK for SYSCLK is ready + * @rmtoll PLL1CFGR PLL1RCLKPRERDY LL_RCC_PLL1_IsPLL1RCLKDivisionReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_IsPLL1RCLKDivisionReady(void) +{ + return ((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1RCLKPRERDY) == RCC_PLL1CFGR_PLL1RCLKPRERDY) ? 1UL : 0UL); +} + +/** + * @brief Configure PLL1R used for SYSCLK Domain + * @note PLL1 Source, PLLM, PLLN and PLLR can be written only when PLL1 is disabled. + * @note PLLN/PLLR can be written only when PLL1 is disabled. + * @rmtoll PLL1CFGR PLL1SRC LL_RCC_PLL1_ConfigDomain_PLL1R\n + * PLL1CFGR PLL1M LL_RCC_PLL1_ConfigDomain_PLL1R\n + * PLL1DIVR PLL1N LL_RCC_PLL1_ConfigDomain_PLL1R\n + * PLL1DIVR PLL1R LL_RCC_PLL1_ConfigDomain_PLL1R + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLL1SOURCE_NONE + * @arg @ref LL_RCC_PLL1SOURCE_HSI + * @arg @ref LL_RCC_PLL1SOURCE_HSE + * @param PLLM parameter can be a value between 1 and 16 + * @param PLLR parameter can be a value between 1 and 128 + * @param PLLN parameter can be a value between 4 and 512 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1_ConfigDomain_PLL1R(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) +{ + MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1M, Source | ((PLLM - 1UL) << RCC_PLL1CFGR_PLL1M_Pos)); + MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1N | RCC_PLL1DIVR_PLL1R, ((PLLN - 1UL) << RCC_PLL1DIVR_PLL1N_Pos) | ((PLLR - 1UL) << RCC_PLL1DIVR_PLL1R_Pos)); +} + +/** + * @brief Configure PLL1P + * @note PLL1 Source, PLLM, PLLN and PLLPDIV can be written only when PLL1 is disabled. + * @note This can be selected for ADC and SAI + * @rmtoll PLL1CFGR PLL1SRC LL_RCC_PLL1_ConfigDomain_PLL1P\n + * PLL1CFGR PLL1M LL_RCC_PLL1_ConfigDomain_PLL1P\n + * PLL1DIVR PLL1N LL_RCC_PLL1_ConfigDomain_PLL1P\n + * PLL1DIVR PLL1P LL_RCC_PLL1_ConfigDomain_PLL1P + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLL1SOURCE_NONE + * @arg @ref LL_RCC_PLL1SOURCE_HSI + * @arg @ref LL_RCC_PLL1SOURCE_HSE + * @param PLLM parameter can be a value between 1 and 16 + * @param PLLN parameter can be a value between 4 and 512 + * @param PLLP parameter can be a value between 2 and 128 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1_ConfigDomain_PLL1P(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) +{ + MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1M, Source | ((PLLM - 1UL) << RCC_PLL1CFGR_PLL1M_Pos)); + MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1N | RCC_PLL1DIVR_PLL1P, ((PLLN - 1UL) << RCC_PLL1DIVR_PLL1N_Pos) | ((PLLP - 1UL) << RCC_PLL1DIVR_PLL1P_Pos)); +} + +/** + * @brief Configure PLL1Q + * @note PLL1 Source, PLLM, PLLN and PLLQ can be written only when PLL1 is disabled. + * @note This can be selected for RNG and SAI + * @rmtoll PLL1CFGR PLL1SRC LL_RCC_PLL1_ConfigDomain_PLL1Q\n + * PLL1CFGR PLL1M LL_RCC_PLL1_ConfigDomain_PLL1Q\n + * PLL1DIVR PLL1N LL_RCC_PLL1_ConfigDomain_PLL1Q\n + * PLL1DIVR PLL1Q LL_RCC_PLL1_ConfigDomain_PLL1Q + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLL1SOURCE_NONE + * @arg @ref LL_RCC_PLL1SOURCE_HSI + * @arg @ref LL_RCC_PLL1SOURCE_HSE + * @param PLLM parameter can be a value between 1 and 16 + * @param PLLN parameter can be a value between 4 and 512 + * @param PLLQ parameter can be a value between 1 and 128 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1_ConfigDomain_PLL1Q(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ) +{ + MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1M, Source | ((PLLM - 1UL) << RCC_PLL1CFGR_PLL1M_Pos)); + MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1N | RCC_PLL1DIVR_PLL1Q, ((PLLN - 1UL) << RCC_PLL1DIVR_PLL1N_Pos) | ((PLLQ - 1UL) << RCC_PLL1DIVR_PLL1Q_Pos)); +} + +/** + * @brief Configure PLL1 clock source + * @rmtoll PLL1CFGR PLL1SRC LL_RCC_PLL1_SetMainSource + * @param PLL1Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLL1SOURCE_NONE + * @arg @ref LL_RCC_PLL1SOURCE_HSI + * @arg @ref LL_RCC_PLL1SOURCE_HSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1_SetMainSource(uint32_t PLL1Source) +{ + MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC, PLL1Source); +} + +/** + * @brief Get the oscillator used as PLL1 clock source. + * @rmtoll PLL1CFGR PLL1SRC LL_RCC_PLL1_GetMainSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLL1SOURCE_NONE + * @arg @ref LL_RCC_PLL1SOURCE_HSI + * @arg @ref LL_RCC_PLL1SOURCE_HSE + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_GetMainSource(void) +{ + return (uint32_t)(READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC)); +} + +/** + * @brief Set PLL1 multiplication factor for VCO + * @rmtoll PLL1DIVR PLL1N LL_RCC_PLL1_SetN + * @param PLL1N parameter can be a value between 4 and 512 + */ +__STATIC_INLINE void LL_RCC_PLL1_SetN(uint32_t PLL1N) +{ + MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1N, (PLL1N - 1UL) << RCC_PLL1DIVR_PLL1N_Pos); +} + +/** + * @brief Get PLL1 multiplication factor for VCO + * @rmtoll PLL1DIVR PLL1N LL_RCC_PLL1_GetN + * @retval Between 4 and 512 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_GetN(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1N) >> RCC_PLL1DIVR_PLL1N_Pos) + 1UL); +} + + +/** + * @brief Set PLL1 division factor for PLL1P + * @note Used for PLL1PCLK selected ADC and SAI + * @rmtoll PLL1DIVR PLL1P LL_RCC_PLL1_SetP + * @param PLL1P parameter can be a value between 2 and 128 + */ +__STATIC_INLINE void LL_RCC_PLL1_SetP(uint32_t PLL1P) +{ + MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1P, (PLL1P - 1UL) << RCC_PLL1DIVR_PLL1P_Pos); +} + +/** + * @brief Get PLL1 division factor for PLL1P + * @note Used for PLL1PCLK selected ADC and SAI + * @rmtoll PLL1DIVR PLL1P LL_RCC_PLL1_GetP + * @retval Between 2 and 128 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_GetP(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1P) >> RCC_PLL1DIVR_PLL1P_Pos) + 1UL); +} + + +/** + * @brief Set PLL1 division factor for PLL1Q + * @note Used for PLL1QCLK selected for RNG and SAI + * @rmtoll PLL1DIVR PLL1Q LL_RCC_PLL1_SetQ + * @param PLL1Q parameter can be a value between 1 and 128 + */ +__STATIC_INLINE void LL_RCC_PLL1_SetQ(uint32_t PLL1Q) +{ + MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1Q, (PLL1Q - 1UL) << RCC_PLL1DIVR_PLL1Q_Pos); +} + +/** + * @brief Get PLL1 division factor for PLL1Q + * @note Used for PLL1QCLK selected for RNG and SAI + * @rmtoll PLL1DIVR PLL1Q LL_RCC_PLL1_GetQ + * @retval Between 1 and 128 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_GetQ(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1Q) >> RCC_PLL1DIVR_PLL1Q_Pos) + 1UL); +} + +/** + * @brief Set PLL1 division factor for PLL1R + * @note Used for PLL1RCLK selected for system clock + * @rmtoll PLL1DIVR PLL1R LL_RCC_PLL1_SetR + * @param PLL1R parameter can be a value between 1 and 128 + */ +__STATIC_INLINE void LL_RCC_PLL1_SetR(uint32_t PLL1R) +{ + MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1R, (PLL1R - 1UL) << RCC_PLL1DIVR_PLL1R_Pos); +} + +/** + * @brief Get PLL1 division factor for PLL1R + * @note Used for PLL1RCLK selected for system clock + * @rmtoll PLL1DIVR PLL1R LL_RCC_PLL1_GetR + * @retval Between 1 and 128 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_GetR(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1UL); +} + +/** + * @brief Set Division factor for PLL1 + * @rmtoll PLL1CFGR PLL1M LL_RCC_PLL1_SetDivider + * @param PLL1M parameter can be a value between 1 and 8 + */ +__STATIC_INLINE void LL_RCC_PLL1_SetDivider(uint32_t PLL1M) +{ + MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1M, (PLL1M - 1UL) << RCC_PLL1CFGR_PLL1M_Pos); +} + +/** + * @brief Get Division factor for PLL1 + * @rmtoll PLL1CFGR PLL1M LL_RCC_PLL1_GetDivider + * @retval Between 1 and 8 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_GetDivider(void) +{ + return (uint32_t)((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos) + 1UL); +} + +/** + * @brief Enable PLL1P output + * @rmtoll PLL1CFGR PLL1PEN LL_RCC_PLL1_EnableDomain_PLL1P + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1_EnableDomain_PLL1P(void) +{ + SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1PEN); +} + +/** + * @brief Disable PLL1P output + * @note In order to save power, when the PLL1PCLK of the PLL1 is + * not used, should be 0 + * @rmtoll PLL1CFGR PLL1PEN LL_RCC_PLL1_DisableDomain_PLL1P + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1_DisableDomain_PLL1P(void) +{ + CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1PEN); +} + +/** + * @brief Check if PLL1P output is enabled + * @rmtoll PLL1CFGR PLL1PEN LL_RCC_PLL1_IsEnabledDomain_PLL1P + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_IsEnabledDomain_PLL1P(void) +{ + return ((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1PEN) == RCC_PLL1CFGR_PLL1PEN) ? 1UL : 0UL); +} + +/** + * @brief Enable PLL1Q output + * @rmtoll PLL1CFGR PLL1QEN LL_RCC_PLL1_EnableDomain_PLL1Q + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1_EnableDomain_PLL1Q(void) +{ + SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1QEN); +} + +/** + * @brief Disable PLL1Q output + * @note In order to save power, when the PLL1QCLK of the PLL1 is + * not used, should be 0 + * @rmtoll PLL1CFGR PLL1QEN LL_RCC_PLL1_DisableDomain_PLL1Q + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1_DisableDomain_PLL1Q(void) +{ + CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1QEN); +} + +/** + * @brief Check if PLL1Q output is enabled + * @rmtoll PLL1CFGR PLL1QEN LL_RCC_PLL1_IsEnabledDomain_PLL1Q + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_IsEnabledDomain_PLL1Q(void) +{ + return ((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1QEN) == RCC_PLL1CFGR_PLL1QEN) ? 1UL : 0UL); +} + +/** + * @brief Enable PLL1R output mapped on SYSCLK domain + * @rmtoll PLL1CFGR PLL1REN LL_RCC_PLL1_EnableDomain_PLL1R + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1_EnableDomain_PLL1R(void) +{ + SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1REN); +} + +/** + * @brief Disable PLL1 output mapped on SYSCLK domain + * @note Cannot be disabled if the PLL1 clock is used as the system + * clock + * @note In order to save power, when the PLL1RCLK of the PLL1 is + * not used, PLL1 should be 0 + * @rmtoll PLL1CFGR PLL1REN LL_RCC_PLL1_DisableDomain_PLL1R + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1_DisableDomain_PLL1R(void) +{ + CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1REN); +} + +/** + * @brief Check if PLL1R output mapped on SYSCLK domain clock is enabled + * @rmtoll PLL1CFGR PLL1REN LL_RCC_PLL1_IsEnabledDomain_PLL1R + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_IsEnabledDomain_PLL1R(void) +{ + return ((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1REN) == RCC_PLL1CFGR_PLL1REN) ? 1UL : 0UL); +} + +/** + * @brief Enable PLL1 FRACN + * @rmtoll PLL1CFGR PLL1FRACEN LL_RCC_PLL1FRACN_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1FRACN_Enable(void) +{ + SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN); +} + +/** + * @brief Check if PLL1 FRACN is enabled + * @rmtoll PLL1CFGR PLL1FRACEN LL_RCC_PLL1FRACN_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1FRACN_IsEnabled(void) +{ + return ((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN) == RCC_PLL1CFGR_PLL1FRACEN) ? 1UL : 0UL); +} + +/** + * @brief Disable PLL1 FRACN + * @rmtoll PLL1CFGR PLL1FRACEN LL_RCC_PLL1FRACN_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1FRACN_Disable(void) +{ + CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN); +} + +/** + * @brief Set PLL1 FRACN Coefficient + * @rmtoll PLL1FRACR PLL1FRACN LL_RCC_PLL1_SetFRACN + * @param FRACN parameter can be a value between 0 and 8191 (0x1FFF) + */ +__STATIC_INLINE void LL_RCC_PLL1_SetFRACN(uint32_t FRACN) +{ + MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_PLL1FRACN, FRACN << RCC_PLL1FRACR_PLL1FRACN_Pos); +} + +/** + * @brief Get PLL1 FRACN Coefficient + * @rmtoll PLL1FRACR PLL1FRACN LL_RCC_PLL1_GetFRACN + * @retval A value between 0 and 8191 (0x1FFF) + */ +__STATIC_INLINE uint32_t LL_RCC_PLL1_GetFRACN(void) +{ + return (uint32_t)(READ_BIT(RCC->PLL1FRACR, RCC_PLL1FRACR_PLL1FRACN) >> RCC_PLL1FRACR_PLL1FRACN_Pos); +} + +/** + * @brief Set PLL1 VCO Input Range + * @note This API shall be called only when PLL1 is disabled. + * @rmtoll PLL1CFGR PLL1RGE LL_RCC_PLL1_SetVCOInputRange + * @param InputRange This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLINPUTRANGE_4_8 + * @arg @ref LL_RCC_PLLINPUTRANGE_8_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL1_SetVCOInputRange(uint32_t InputRange) +{ + MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1RGE, InputRange << RCC_PLL1CFGR_PLL1RGE_Pos); +} + +/** + * @} + */ + +#if defined(RCC_PRIVCFGR_NSPRIV) +/** @defgroup RCC_LL_EF_PRIV Privileged mode + * @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Enable Secure Privileged mode + * @rmtoll PRIVCFGR SPRIV LL_RCC_EnableSecPrivilegedMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableSecPrivilegedMode(void) +{ + SET_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_SPRIV); +} + +/** + * @brief Disable Secure Privileged mode + * @rmtoll PRIVCFGR SPRIV LL_RCC_DisableSecPrivilegedMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableSecPrivilegedMode(void) +{ + CLEAR_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_SPRIV); +} + +/** + * @brief Check if Secure Privileged mode has been enabled or not + * @rmtoll PRIVCFGR SPRIV LL_RCC_IsEnabledSecPrivilegedMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledSecPrivilegedMode(void) +{ + return ((READ_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_SPRIV) == RCC_PRIVCFGR_SPRIV) ? 1UL : 0UL); +} +#endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */ + +/** + * @brief Enable Non Secure Privileged mode + * @rmtoll PRIVCFGR NSPRIV LL_RCC_EnableNSecPrivilegedMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableNSecPrivilegedMode(void) +{ + SET_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV); +} + +/** + * @brief Disable Non Secure Privileged mode + * @rmtoll PRIVCFGR NSPRIV LL_RCC_DisableNSecPrivilegedMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableNSecPrivilegedMode(void) +{ + CLEAR_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV); +} + +/** + * @brief Check if Non Secure Privileged mode has been enabled or not + * @rmtoll PRIVCFGR NSPRIV LL_RCC_IsEnabledNSecPrivilegedMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledNSecPrivilegedMode(void) +{ + return ((READ_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV) == RCC_PRIVCFGR_NSPRIV) ? 1UL : 0UL); +} + +/** + * @} + */ +#endif /* RCC_PRIVCFGR_NSPRIV */ + +/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management + * @{ + */ + +/** + * @brief Clear LSI1 ready interrupt flag + * @rmtoll CICR LSI1RDYC LL_RCC_ClearFlag_LSI1RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_LSI1RDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_LSI1RDYC); +} + +#if defined(RCC_LSI2_SUPPORT) +/** + * @brief Clear LSI2 ready interrupt flag + * @rmtoll CICR LSI2RDYC LL_RCC_ClearFlag_LSI2RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_LSI2RDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_LSI2RDYC); +} +#endif /* RCC_BDCR1_LSI2ON */ + +/** + * @brief Clear LSE ready interrupt flag + * @rmtoll CICR LSERDYC LL_RCC_ClearFlag_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_LSERDYC); +} + +/** + * @brief Clear HSI ready interrupt flag + * @rmtoll CICR HSIRDYC LL_RCC_ClearFlag_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC); +} + +/** + * @brief Clear HSE ready interrupt flag + * @rmtoll CICR HSERDYC LL_RCC_ClearFlag_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_HSERDYC); +} + +/** + * @brief Clear PLL1 ready interrupt flag + * @rmtoll CICR PLL1RDYC LL_RCC_ClearFlag_PLL1RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_PLL1RDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_PLL1RDYC); +} + +/** + * @brief Clear Clock security system interrupt flag + * @rmtoll CICR CSSC LL_RCC_ClearFlag_HSECSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_HSECSSC); +} + + +/** + * @brief Check if LSI1 ready interrupt occurred or not + * @rmtoll CIFR LSI1RDYF LL_RCC_IsActiveFlag_LSI1RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSI1RDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSI1RDYF) == RCC_CIFR_LSI1RDYF) ? 1UL : 0UL); +} + +#if defined(RCC_LSI2_SUPPORT) +/** + * @brief Check if LSI2 ready interrupt occurred or not + * @rmtoll CIFR LSI2RDYF LL_RCC_IsActiveFlag_LSI2RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSI2RDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSI2RDYF) == RCC_CIFR_LSI2RDYF) ? 1UL : 0UL); +} +#endif /* RCC_BDCR1_LSI2ON */ + +/** + * @brief Check if LSE ready interrupt occurred or not + * @rmtoll CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == RCC_CIFR_LSERDYF) ? 1UL : 0UL); +} + +/** + * @brief Check if HSI ready interrupt occurred or not + * @rmtoll CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == RCC_CIFR_HSIRDYF) ? 1UL : 0UL); +} + +/** + * @brief Check if HSE ready interrupt occurred or not + * @rmtoll CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == RCC_CIFR_HSERDYF) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL1 ready interrupt occurred or not + * @rmtoll CIFR PLL1RDYF LL_RCC_IsActiveFlag_PLL1RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL1RDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL1RDYF) == RCC_CIFR_PLL1RDYF) ? 1UL : 0UL); +} + +/** + * @brief Check if Clock security system interrupt occurred or not + * @rmtoll CIFR CSSF LL_RCC_IsActiveFlag_HSECSS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSECSSF) == RCC_CIFR_HSECSSF) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Independent Watchdog reset is set or not. + * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == RCC_CSR_IWDGRSTF) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Low Power reset is set or not. + * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == RCC_CSR_LPWRRSTF) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag is set or not. + * @rmtoll CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == RCC_CSR_OBLRSTF) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Pin reset is set or not. + * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == RCC_CSR_PINRSTF) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Software reset is set or not. + * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == RCC_CSR_SFTRSTF) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Window Watchdog reset is set or not. + * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == RCC_CSR_WWDGRSTF) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag BOR reset is set or not. + * @rmtoll CSR BORRSTF LL_RCC_IsActiveFlag_BORRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == RCC_CSR_BORRSTF) ? 1UL : 0UL); +} + +/** + * @brief Set RMVF bit to clear the reset flags. + * @rmtoll CSR RMVF LL_RCC_ClearResetFlags + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearResetFlags(void) +{ + SET_BIT(RCC->CSR, RCC_CSR_RMVF); +} + +/* Alias for portability */ +#define LL_RCC_PLL1_ConfigDomain_SYS LL_RCC_PLL1_ConfigDomain_PLL1R + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_IT_Management IT Management + * @{ + */ + +/** + * @brief Enable LSI1 ready interrupt + * @rmtoll CIER LSI1RDYIE LL_RCC_EnableIT_LSI1RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_LSI1RDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_LSI1RDYIE); +} + +#if defined(RCC_LSI2_SUPPORT) +/** + * @brief Enable LSI2 ready interrupt + * @rmtoll CIER LSI2RDYIE LL_RCC_EnableIT_LSI2RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_LSI2RDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_LSI2RDYIE); +} +#endif /* RCC_BDCR1_LSI2ON */ + +/** + * @brief Enable LSE ready interrupt + * @rmtoll CIER LSERDYIE LL_RCC_EnableIT_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE); +} + +/** + * @brief Enable HSI ready interrupt + * @rmtoll CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE); +} + +/** + * @brief Enable HSE ready interrupt + * @rmtoll CIER HSERDYIE LL_RCC_EnableIT_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE); +} + +/** + * @brief Enable PLL1 ready interrupt + * @rmtoll CIER PLL1RDYIE LL_RCC_EnableIT_PLL1RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_PLL1RDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE); +} + +/** + * @brief Disable LSI1 ready interrupt + * @rmtoll CIER LSI1RDYIE LL_RCC_DisableIT_LSI1RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_LSI1RDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_LSI1RDYIE); +} + +#if defined(RCC_LSI2_SUPPORT) +/** + * @brief Disable LSI2 ready interrupt + * @rmtoll CIER LSI2RDYIE LL_RCC_DisableIT_LSI2RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_LSI2RDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_LSI2RDYIE); +} +#endif /* RCC_BDCR1_LSI2ON */ + +/** + * @brief Disable LSE ready interrupt + * @rmtoll CIER LSERDYIE LL_RCC_DisableIT_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE); +} + +/** + * @brief Disable HSI ready interrupt + * @rmtoll CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE); +} + +/** + * @brief Disable HSE ready interrupt + * @rmtoll CIER HSERDYIE LL_RCC_DisableIT_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE); +} + +/** + * @brief Disable PLL1 ready interrupt + * @rmtoll CIER PLL1RDYIE LL_RCC_DisableIT_PLL1RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_PLL1RDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE); +} + +/** + * @brief Checks if LSI1 ready interrupt source is enabled or disabled. + * @rmtoll CIER LSI1RDYIE LL_RCC_IsEnabledIT_LSI1RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSI1RDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_LSI1RDYIE) == RCC_CIER_LSI1RDYIE) ? 1UL : 0UL); +} + +#if defined(RCC_LSI2_SUPPORT) +/** + * @brief Checks if LSI2 ready interrupt source is enabled or disabled. + * @rmtoll CIER LSI2RDYIE LL_RCC_IsEnabledIT_LSI2RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSI2RDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_LSI2RDYIE) == RCC_CIER_LSI2RDYIE) ? 1UL : 0UL); +} +#endif /* RCC_BDCR1_LSI2ON */ + +/** + * @brief Checks if LSE ready interrupt source is enabled or disabled. + * @rmtoll CIER LSERDYIE LL_RCC_IsEnabledIT_LSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == RCC_CIER_LSERDYIE) ? 1UL : 0UL); +} + + +/** + * @brief Checks if HSI ready interrupt source is enabled or disabled. + * @rmtoll CIER HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == RCC_CIER_HSIRDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if HSE ready interrupt source is enabled or disabled. + * @rmtoll CIER HSERDYIE LL_RCC_IsEnabledIT_HSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == RCC_CIER_HSERDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if PLL1 ready interrupt source is enabled or disabled. + * @rmtoll CIER PLL1RDYIE LL_RCC_IsEnabledIT_PLL1RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLL1RDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE) == RCC_CIER_PLL1RDYIE) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_Security_Services Security Services + * @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Configure RCC resources security + * @note Only available from secure state when system implements security (TZEN=1) + * @rmtoll SECCFGR HSISEC LL_RCC_ConfigSecure\n + * SECCFGR HSESEC LL_RCC_ConfigSecure\n + * SECCFGR LSISEC LL_RCC_ConfigSecure\n + * SECCFGR LSESEC LL_RCC_ConfigSecure\n + * SECCFGR SYSCLKSEC LL_RCC_ConfigSecure\n + * SECCFGR PRESCSEC LL_RCC_ConfigSecure\n + * SECCFGR PLL1SEC LL_RCC_ConfigSecure\n + * SECCFGR RMVFSEC LL_RCC_ConfigSecure + * @param SecureConfig This parameter can be one or a combination of the following values: + * @arg @ref LL_RCC_ALL_NSEC & LL_RCC_ALL_SEC + * @arg @ref LL_RCC_HSI_SEC & LL_RCC_HSI_NSEC + * @arg @ref LL_RCC_HSE_SEC & LL_RCC_HSE_NSEC + * @arg @ref LL_RCC_LSE_SEC & LL_RCC_LSE_NSEC + * @arg @ref LL_RCC_LSI_SEC & LL_RCC_LSI_NSEC + * @arg @ref LL_RCC_SYSCLK_SEC & LL_RCC_SYSCLK_NSEC + * @arg @ref LL_RCC_PRESCALERS_SEC & LL_RCC_PRESCALERS_NSEC + * @arg @ref LL_RCC_PLL1_SEC & LL_RCC_PLL1_NSEC + * @arg @ref LL_RCC_RESET_FLAGS_SEC & LL_RCC_RESET_FLAGS_NSEC + * @retval None + */ +__STATIC_INLINE void LL_RCC_ConfigSecure(uint32_t SecureConfig) +{ + WRITE_REG(RCC->SECCFGR, SecureConfig); +} +#endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */ + +/** + * @brief Get RCC resources security status + * @note Only available from secure state when system implements security (TZEN=1) + * @rmtoll SECCFGR HSISEC LL_RCC_GetConfigSecure\n + * SECCFGR HSESEC LL_RCC_GetConfigSecure\n + * SECCFGR LSISEC LL_RCC_GetConfigSecure\n + * SECCFGR LSESEC LL_RCC_GetConfigSecure\n + * SECCFGR SYSCLKSEC LL_RCC_GetConfigSecure\n + * SECCFGR PRESCSEC LL_RCC_GetConfigSecure\n + * SECCFGR PLL1SEC LL_RCC_GetConfigSecure\n + * SECCFGR RMVFSEC LL_RCC_GetConfigSecure + * @retval Returned value can be one or a combination of the following values: + * @arg @ref LL_RCC_ALL_NSEC & LL_RCC_ALL_SEC + * @arg @ref LL_RCC_HSI_SEC & LL_RCC_HSI_NSEC + * @arg @ref LL_RCC_HSE_SEC & LL_RCC_HSE_NSEC + * @arg @ref LL_RCC_LSE_SEC & LL_RCC_LSE_NSEC + * @arg @ref LL_RCC_LSI_SEC & LL_RCC_LSI_NSEC + * @arg @ref LL_RCC_SYSCLK_SEC & LL_RCC_SYSCLK_NSEC + * @arg @ref LL_RCC_PRESCALERS_SEC & LL_RCC_PRESCALERS_NSEC + * @arg @ref LL_RCC_PLL1_SEC & LL_RCC_PLL1_NSEC + * @arg @ref LL_RCC_RESET_FLAGS_SEC & LL_RCC_RESET_FLAGS_NSEC + * @retval None + */ +__STATIC_INLINE uint32_t LL_RCC_GetConfigSecure(void) +{ + return (uint32_t)(READ_BIT(RCC->SECCFGR, RCC_SECURE_MASK)); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_EF_Init De-initialization function + * @{ + */ +ErrorStatus LL_RCC_DeInit(void); +/** + * @} + */ + +/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions + * @{ + */ +void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks); +uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource); +uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource); +uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource); +uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource); +uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource); +uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource); +uint32_t LL_RCC_GetSPIClockFreq(uint32_t SPIxSource); +uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource); +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(RCC) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WBAxx_LL_RCC_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_rng.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_rng.h new file mode 100644 index 0000000000..efeec7000b --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_rng.h @@ -0,0 +1,723 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_ll_rng.h + * @author MCD Application Team + * @brief Header file of RNG LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_LL_RNG_H +#define STM32WBAxx_LL_RNG_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx.h" + +/** @addtogroup STM32WBAxx_LL_Driver + * @{ + */ + +#if defined (RNG) + +/** @defgroup RNG_LL RNG + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RNG_LL_ES_Init_Struct RNG Exported Init structures + * @{ + */ + + +/** + * @brief LL RNG Init Structure Definition + */ +typedef struct +{ + uint32_t ClockErrorDetection; /*!< Clock error detection. + This parameter can be one value of @ref RNG_LL_CED. + This parameter can be modified using unitary + functions @ref LL_RNG_EnableClkErrorDetect(). */ +} LL_RNG_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RNG_LL_Exported_Constants RNG Exported Constants + * @{ + */ + +/** @defgroup RNG_LL_CED Clock Error Detection + * @{ + */ +#define LL_RNG_CED_ENABLE 0x00000000U /*!< Clock error detection enabled */ +#define LL_RNG_CED_DISABLE RNG_CR_CED /*!< Clock error detection disabled */ +/** + * @} + */ +/** @defgroup RNG_LL_ARDIS Auto reset disable + * @{ + */ +#define LL_RNG_ARDIS_ENABLE 0x00000000U /*!< ARDIS enabled automatic reset to clear SECS bit*/ +#define LL_RNG_ARDIS_DISABLE RNG_CR_ARDIS /*!< ARDIS disabled no automatic reset to clear SECS bit*/ +/** + * @} + */ + +/** @defgroup RNG_LL_Clock_Divider_Factor Value used to configure an internal + * programmable divider acting on the incoming RNG clock + * @{ + */ +#define LL_RNG_CLKDIV_BY_1 (0x00000000UL) /*!< No clock division */ +#define LL_RNG_CLKDIV_BY_2 (RNG_CR_CLKDIV_0) /*!< 2 RNG clock cycles per internal RNG clock */ +#define LL_RNG_CLKDIV_BY_4 (RNG_CR_CLKDIV_1) /*!< 4 RNG clock cycles per internal RNG clock */ +#define LL_RNG_CLKDIV_BY_8 (RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0) /*!< 8 RNG clock cycles per internal RNG clock */ +#define LL_RNG_CLKDIV_BY_16 (RNG_CR_CLKDIV_2) /*!< 16 RNG clock cycles per internal RNG clock */ +#define LL_RNG_CLKDIV_BY_32 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0) /*!< 32 RNG clock cycles per internal RNG clock */ +#define LL_RNG_CLKDIV_BY_64 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1) /*!< 64 RNG clock cycles per internal RNG clock */ +#define LL_RNG_CLKDIV_BY_128 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0) /*!< 128 RNG clock cycles per internal RNG clock */ +#define LL_RNG_CLKDIV_BY_256 (RNG_CR_CLKDIV_3) /*!< 256 RNG clock cycles per internal RNG clock */ +#define LL_RNG_CLKDIV_BY_512 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_0) /*!< 512 RNG clock cycles per internal RNG clock */ +#define LL_RNG_CLKDIV_BY_1024 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1) /*!< 1024 RNG clock cycles per internal RNG clock */ +#define LL_RNG_CLKDIV_BY_2048 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0) /*!< 2048 RNG clock cycles per internal RNG clock */ +#define LL_RNG_CLKDIV_BY_4096 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2) /*!< 4096 RNG clock cycles per internal RNG clock */ +#define LL_RNG_CLKDIV_BY_8192 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0) /*!< 8192 RNG clock cycles per internal RNG clock */ +#define LL_RNG_CLKDIV_BY_16384 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1) /*!< 16384 RNG clock cycles per internal RNG clock */ +#define LL_RNG_CLKDIV_BY_32768 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0) /*!< 32768 RNG clock cycles per internal RNG clock */ +/** + * @} + */ + +/** @defgroup RNG_LL_NIST_Compliance NIST Compliance configuration + * @{ + */ +#define LL_RNG_NIST_COMPLIANT (0x00000000UL) /*!< Default NIST compliant configuration*/ +#define LL_RNG_CUSTOM_NIST (RNG_CR_NISTC) /*!< Custom NIST configuration */ + +/** + * @} + */ + +/** @defgroup RNG_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_RNG_ReadReg function + * @{ + */ +#define LL_RNG_SR_DRDY RNG_SR_DRDY /*!< Register contains valid random data */ +#define LL_RNG_SR_CECS RNG_SR_CECS /*!< Clock error current status */ +#define LL_RNG_SR_SECS RNG_SR_SECS /*!< Seed error current status */ +#define LL_RNG_SR_CEIS RNG_SR_CEIS /*!< Clock error interrupt status */ +#define LL_RNG_SR_SEIS RNG_SR_SEIS /*!< Seed error interrupt status */ +/** + * @} + */ + +/** @defgroup RNG_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_RNG_ReadReg and LL_RNG_WriteReg macros + * @{ + */ +#define LL_RNG_CR_IE RNG_CR_IE /*!< RNG Interrupt enable */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup RNG_LL_Exported_Macros RNG Exported Macros + * @{ + */ + +/** @defgroup RNG_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in RNG register + * @param __INSTANCE__ RNG Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_RNG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in RNG register + * @param __INSTANCE__ RNG Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_RNG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup RNG_LL_Exported_Functions RNG Exported Functions + * @{ + */ +/** @defgroup RNG_LL_EF_Configuration RNG Configuration functions + * @{ + */ + +/** + * @brief Enable Random Number Generation + * @rmtoll CR RNGEN LL_RNG_Enable + * @param RNGx RNG Instance + * @retval None + */ +__STATIC_INLINE void LL_RNG_Enable(RNG_TypeDef *RNGx) +{ + SET_BIT(RNGx->CR, RNG_CR_RNGEN); +} + +/** + * @brief Disable Random Number Generation + * @rmtoll CR RNGEN LL_RNG_Disable + * @param RNGx RNG Instance + * @retval None + */ +__STATIC_INLINE void LL_RNG_Disable(RNG_TypeDef *RNGx) +{ + CLEAR_BIT(RNGx->CR, RNG_CR_RNGEN); +} + +/** + * @brief Check if Random Number Generator is enabled + * @rmtoll CR RNGEN LL_RNG_IsEnabled + * @param RNGx RNG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RNG_IsEnabled(const RNG_TypeDef *RNGx) +{ + return ((READ_BIT(RNGx->CR, RNG_CR_RNGEN) == (RNG_CR_RNGEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable Clock Error Detection + * @rmtoll CR CED LL_RNG_EnableClkErrorDetect + * @param RNGx RNG Instance + * @retval None + */ +__STATIC_INLINE void LL_RNG_EnableClkErrorDetect(RNG_TypeDef *RNGx) +{ + CLEAR_BIT(RNGx->CR, RNG_CR_CED); +} + +/** + * @brief Disable RNG Clock Error Detection + * @rmtoll CR CED LL_RNG_DisableClkErrorDetect + * @param RNGx RNG Instance + * @retval None + */ +__STATIC_INLINE void LL_RNG_DisableClkErrorDetect(RNG_TypeDef *RNGx) +{ + SET_BIT(RNGx->CR, RNG_CR_CED); +} + +/** + * @brief Check if RNG Clock Error Detection is enabled + * @rmtoll CR CED LL_RNG_IsEnabledClkErrorDetect + * @param RNGx RNG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RNG_IsEnabledClkErrorDetect(const RNG_TypeDef *RNGx) +{ + return ((READ_BIT(RNGx->CR, RNG_CR_CED) != (RNG_CR_CED)) ? 1UL : 0UL); +} + +/** + * @brief Set RNG Conditioning Soft Reset bit + * @rmtoll CR CONDRST LL_RNG_EnableCondReset + * @param RNGx RNG Instance + * @retval None + */ +__STATIC_INLINE void LL_RNG_EnableCondReset(RNG_TypeDef *RNGx) +{ + SET_BIT(RNGx->CR, RNG_CR_CONDRST); +} + +/** + * @brief Reset RNG Conditioning Soft Reset bit + * @rmtoll CR CONDRST LL_RNG_DisableCondReset + * @param RNGx RNG Instance + * @retval None + */ +__STATIC_INLINE void LL_RNG_DisableCondReset(RNG_TypeDef *RNGx) +{ + CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); +} + +/** + * @brief Check if RNG Conditioning Soft Reset bit is set + * @rmtoll CR CONDRST LL_RNG_IsEnabledCondReset + * @param RNGx RNG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RNG_IsEnabledCondReset(const RNG_TypeDef *RNGx) +{ + return ((READ_BIT(RNGx->CR, RNG_CR_CONDRST) == (RNG_CR_CONDRST)) ? 1UL : 0UL); +} + +/** + * @brief Enable RNG Config Lock + * @rmtoll CR CONFIGLOCK LL_RNG_ConfigLock + * @param RNGx RNG Instance + * @retval None + */ +__STATIC_INLINE void LL_RNG_ConfigLock(RNG_TypeDef *RNGx) +{ + SET_BIT(RNGx->CR, RNG_CR_CONFIGLOCK); +} + +/** + * @brief Check if RNG Config Lock is enabled + * @rmtoll CR CONFIGLOCK LL_RNG_IsConfigLocked + * @param RNGx RNG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RNG_IsConfigLocked(const RNG_TypeDef *RNGx) +{ + return ((READ_BIT(RNGx->CR, RNG_CR_CONFIGLOCK) == (RNG_CR_CONFIGLOCK)) ? 1UL : 0UL); +} + +/** + * @brief Enable NIST Compliance + * @rmtoll CR NISTC LL_RNG_EnableNistCompliance + * @param RNGx RNG Instance + * @retval None + */ +__STATIC_INLINE void LL_RNG_EnableNistCompliance(RNG_TypeDef *RNGx) +{ + MODIFY_REG(RNGx->CR, RNG_CR_NISTC | RNG_CR_CONDRST, LL_RNG_NIST_COMPLIANT | RNG_CR_CONDRST); + CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); +} + +/** + * @brief Disable NIST Compliance + * @rmtoll CR NISTC LL_RNG_DisableNistCompliance + * @param RNGx RNG Instance + * @retval None + */ +__STATIC_INLINE void LL_RNG_DisableNistCompliance(RNG_TypeDef *RNGx) +{ + MODIFY_REG(RNGx->CR, RNG_CR_NISTC | RNG_CR_CONDRST, LL_RNG_CUSTOM_NIST | RNG_CR_CONDRST); + CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);; +} + +/** + * @brief Check if NIST Compliance is enabled + * @rmtoll CR NISTC LL_RNG_IsEnabledNistCompliance + * @param RNGx RNG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RNG_IsEnabledNistCompliance(const RNG_TypeDef *RNGx) +{ + return ((READ_BIT(RNGx->CR, RNG_CR_NISTC) != (RNG_CR_NISTC)) ? 1UL : 0UL); +} + +/** + * @brief Set RNG Config1 Configuration field value + * @rmtoll CR RNG_CONFIG1 LL_RNG_SetConfig1 + * @param RNGx RNG Instance + * @param Config1 Value between 0 and 0x3F + * @retval None + */ +__STATIC_INLINE void LL_RNG_SetConfig1(RNG_TypeDef *RNGx, uint32_t Config1) +{ + MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG1 | RNG_CR_CONDRST, (Config1 << RNG_CR_RNG_CONFIG1_Pos) | RNG_CR_CONDRST); + CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); +} + +/** + * @brief Get RNG Config1 Configuration field value + * @rmtoll CR RNG_CONFIG1 LL_RNG_GetConfig1 + * @param RNGx RNG Instance + * @retval Returned Value expressed on 6 bits : Value between 0 and 0x3F + */ +__STATIC_INLINE uint32_t LL_RNG_GetConfig1(const RNG_TypeDef *RNGx) +{ + return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG1) >> RNG_CR_RNG_CONFIG1_Pos); +} + +/** + * @brief Set RNG Config2 Configuration field value + * @rmtoll CR RNG_CONFIG2 LL_RNG_SetConfig2 + * @param RNGx RNG Instance + * @param Config2 Value between 0 and 0x7 + * @retval None + */ +__STATIC_INLINE void LL_RNG_SetConfig2(RNG_TypeDef *RNGx, uint32_t Config2) +{ + MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG2 | RNG_CR_CONDRST, (Config2 << RNG_CR_RNG_CONFIG2_Pos) | RNG_CR_CONDRST); + CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); +} + +/** + * @brief Get RNG Config2 Configuration field value + * @rmtoll CR RNG_CONFIG2 LL_RNG_GetConfig2 + * @param RNGx RNG Instance + * @retval Returned Value expressed on 3 bits : Value between 0 and 0x7 + */ +__STATIC_INLINE uint32_t LL_RNG_GetConfig2(const RNG_TypeDef *RNGx) +{ + return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG2) >> RNG_CR_RNG_CONFIG2_Pos); +} + +/** + * @brief Set RNG Config3 Configuration field value + * @rmtoll CR RNG_CONFIG3 LL_RNG_SetConfig3 + * @param RNGx RNG Instance + * @param Config3 Value between 0 and 0xF + * @retval None + */ +__STATIC_INLINE void LL_RNG_SetConfig3(RNG_TypeDef *RNGx, uint32_t Config3) +{ + MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG3 | RNG_CR_CONDRST, (Config3 << RNG_CR_RNG_CONFIG3_Pos) | RNG_CR_CONDRST); + CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); +} + +/** + * @brief Get RNG Config3 Configuration field value + * @rmtoll CR RNG_CONFIG3 LL_RNG_GetConfig3 + * @param RNGx RNG Instance + * @retval Returned Value expressed on 4 bits : Value between 0 and 0xF + */ +__STATIC_INLINE uint32_t LL_RNG_GetConfig3(const RNG_TypeDef *RNGx) +{ + return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG3) >> RNG_CR_RNG_CONFIG3_Pos); +} + +/** + * @brief Set RNG Clock divider factor + * @rmtoll CR CLKDIV LL_RNG_SetClockDivider + * @param RNGx RNG Instance + * @param Divider can be one of the following values: + * @arg @ref LL_RNG_CLKDIV_BY_1 + * @arg @ref LL_RNG_CLKDIV_BY_2 + * @arg @ref LL_RNG_CLKDIV_BY_4 + * @arg @ref LL_RNG_CLKDIV_BY_8 + * @arg @ref LL_RNG_CLKDIV_BY_16 + * @arg @ref LL_RNG_CLKDIV_BY_32 + * @arg @ref LL_RNG_CLKDIV_BY_64 + * @arg @ref LL_RNG_CLKDIV_BY_128 + * @arg @ref LL_RNG_CLKDIV_BY_256 + * @arg @ref LL_RNG_CLKDIV_BY_512 + * @arg @ref LL_RNG_CLKDIV_BY_1024 + * @arg @ref LL_RNG_CLKDIV_BY_2048 + * @arg @ref LL_RNG_CLKDIV_BY_4096 + * @arg @ref LL_RNG_CLKDIV_BY_8192 + * @arg @ref LL_RNG_CLKDIV_BY_16384 + * @arg @ref LL_RNG_CLKDIV_BY_32768 + * @retval None + */ +__STATIC_INLINE void LL_RNG_SetClockDivider(RNG_TypeDef *RNGx, uint32_t Divider) +{ + MODIFY_REG(RNGx->CR, RNG_CR_CLKDIV | RNG_CR_CONDRST, (Divider << RNG_CR_CLKDIV_Pos) | RNG_CR_CONDRST); + CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); +} + +/** + * @brief Get RNG Clock divider factor + * @rmtoll CR CLKDIV LL_RNG_GetClockDivider + * @param RNGx RNG Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RNG_CLKDIV_BY_1 + * @arg @ref LL_RNG_CLKDIV_BY_2 + * @arg @ref LL_RNG_CLKDIV_BY_4 + * @arg @ref LL_RNG_CLKDIV_BY_8 + * @arg @ref LL_RNG_CLKDIV_BY_16 + * @arg @ref LL_RNG_CLKDIV_BY_32 + * @arg @ref LL_RNG_CLKDIV_BY_64 + * @arg @ref LL_RNG_CLKDIV_BY_128 + * @arg @ref LL_RNG_CLKDIV_BY_256 + * @arg @ref LL_RNG_CLKDIV_BY_512 + * @arg @ref LL_RNG_CLKDIV_BY_1024 + * @arg @ref LL_RNG_CLKDIV_BY_2048 + * @arg @ref LL_RNG_CLKDIV_BY_4096 + * @arg @ref LL_RNG_CLKDIV_BY_8192 + * @arg @ref LL_RNG_CLKDIV_BY_16384 + * @arg @ref LL_RNG_CLKDIV_BY_32768 + */ +__STATIC_INLINE uint32_t LL_RNG_GetClockDivider(const RNG_TypeDef *RNGx) +{ + return (uint32_t)READ_BIT(RNGx->CR, RNG_CR_CLKDIV); +} +/** + * @} + */ + +/** @defgroup RNG_LL_EF_FLAG_Management FLAG Management + * @{ + */ + +/** + * @brief Indicate if the RNG Data ready Flag is set or not + * @rmtoll SR DRDY LL_RNG_IsActiveFlag_DRDY + * @param RNGx RNG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(const RNG_TypeDef *RNGx) +{ + return ((READ_BIT(RNGx->SR, RNG_SR_DRDY) == (RNG_SR_DRDY)) ? 1UL : 0UL); +} + +/** + * @brief Indicate if the Clock Error Current Status Flag is set or not + * @rmtoll SR CECS LL_RNG_IsActiveFlag_CECS + * @param RNGx RNG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(const RNG_TypeDef *RNGx) +{ + return ((READ_BIT(RNGx->SR, RNG_SR_CECS) == (RNG_SR_CECS)) ? 1UL : 0UL); +} + +/** + * @brief Indicate if the Seed Error Current Status Flag is set or not + * @rmtoll SR SECS LL_RNG_IsActiveFlag_SECS + * @param RNGx RNG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(const RNG_TypeDef *RNGx) +{ + return ((READ_BIT(RNGx->SR, RNG_SR_SECS) == (RNG_SR_SECS)) ? 1UL : 0UL); +} + +/** + * @brief Indicate if the Clock Error Interrupt Status Flag is set or not + * @rmtoll SR CEIS LL_RNG_IsActiveFlag_CEIS + * @param RNGx RNG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(const RNG_TypeDef *RNGx) +{ + return ((READ_BIT(RNGx->SR, RNG_SR_CEIS) == (RNG_SR_CEIS)) ? 1UL : 0UL); +} + +/** + * @brief Indicate if the Seed Error Interrupt Status Flag is set or not + * @rmtoll SR SEIS LL_RNG_IsActiveFlag_SEIS + * @param RNGx RNG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS(const RNG_TypeDef *RNGx) +{ + return ((READ_BIT(RNGx->SR, RNG_SR_SEIS) == (RNG_SR_SEIS)) ? 1UL : 0UL); +} + +/** + * @brief Clear Clock Error interrupt Status (CEIS) Flag + * @rmtoll SR CEIS LL_RNG_ClearFlag_CEIS + * @param RNGx RNG Instance + * @retval None + */ +__STATIC_INLINE void LL_RNG_ClearFlag_CEIS(RNG_TypeDef *RNGx) +{ + WRITE_REG(RNGx->SR, ~RNG_SR_CEIS); +} + +/** + * @brief Clear Seed Error interrupt Status (SEIS) Flag + * @rmtoll SR SEIS LL_RNG_ClearFlag_SEIS + * @param RNGx RNG Instance + * @retval None + */ +__STATIC_INLINE void LL_RNG_ClearFlag_SEIS(RNG_TypeDef *RNGx) +{ + WRITE_REG(RNGx->SR, ~RNG_SR_SEIS); +} + +/** + * @} + */ + +/** @defgroup RNG_LL_EF_IT_Management IT Management + * @{ + */ + +/** + * @brief Enable Random Number Generator Interrupt + * (applies for either Seed error, Clock Error or Data ready interrupts) + * @rmtoll CR IE LL_RNG_EnableIT + * @param RNGx RNG Instance + * @retval None + */ +__STATIC_INLINE void LL_RNG_EnableIT(RNG_TypeDef *RNGx) +{ + SET_BIT(RNGx->CR, RNG_CR_IE); +} + +/** + * @brief Disable Random Number Generator Interrupt + * (applies for either Seed error, Clock Error or Data ready interrupts) + * @rmtoll CR IE LL_RNG_DisableIT + * @param RNGx RNG Instance + * @retval None + */ +__STATIC_INLINE void LL_RNG_DisableIT(RNG_TypeDef *RNGx) +{ + CLEAR_BIT(RNGx->CR, RNG_CR_IE); +} + +/** + * @brief Check if Random Number Generator Interrupt is enabled + * (applies for either Seed error, Clock Error or Data ready interrupts) + * @rmtoll CR IE LL_RNG_IsEnabledIT + * @param RNGx RNG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(const RNG_TypeDef *RNGx) +{ + return ((READ_BIT(RNGx->CR, RNG_CR_IE) == (RNG_CR_IE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup RNG_LL_EF_Data_Management Data Management + * @{ + */ + +/** + * @brief Return32-bit Random Number value + * @rmtoll DR RNDATA LL_RNG_ReadRandData32 + * @param RNGx RNG Instance + * @retval Generated 32-bit random value + */ +__STATIC_INLINE uint32_t LL_RNG_ReadRandData32(const RNG_TypeDef *RNGx) +{ + return (uint32_t)(READ_REG(RNGx->DR)); +} + +/** + * @} + */ + +/** + * @brief Enable Auto reset + * @rmtoll CR ARDIS LL_RNG_EnableArdis + * @param RNGx RNG Instance + * @retval None + */ +__STATIC_INLINE void LL_RNG_EnableArdis(RNG_TypeDef *RNGx) +{ + MODIFY_REG(RNGx->CR, RNG_CR_ARDIS | RNG_CR_CONDRST, LL_RNG_ARDIS_ENABLE | RNG_CR_CONDRST); + CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); +} + +/** + * @brief Disable Auto reset + * @rmtoll CR ARDIS LL_RNG_DisableArdis + * @param RNGx RNG Instance + * @retval None + */ +__STATIC_INLINE void LL_RNG_DisableArdis(RNG_TypeDef *RNGx) +{ + MODIFY_REG(RNGx->CR, RNG_CR_ARDIS | RNG_CR_CONDRST, LL_RNG_ARDIS_DISABLE | RNG_CR_CONDRST); + CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); +} + +/** + * @brief Check if RNG Auto reset is enabled + * @rmtoll CR ARDIS LL_RNG_IsEnabledArdis + * @param RNGx RNG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RNG_IsEnabledArdis(const RNG_TypeDef *RNGx) +{ + return ((READ_BIT(RNGx->CR, RNG_CR_ARDIS) != (RNG_CR_ARDIS)) ? 1UL : 0UL); +} + +/** @defgroup RNG_LL_EF_Health_Test_Control Health Test Control + * @{ + */ + +/** + * @brief Set RNG Health Test Control + * @rmtoll HTCR HTCFG LL_RNG_SetHealthConfig + * @param RNGx RNG Instance + * @param HTCFG can be values of 32 bits + * @retval None + */ +__STATIC_INLINE void LL_RNG_SetHealthConfig(RNG_TypeDef *RNGx, uint32_t HTCFG) +{ + WRITE_REG(RNGx->HTCR, HTCFG); +} + +/** + * @brief Get RNG Health Test Control + * @rmtoll HTCR HTCFG LL_RNG_GetHealthConfig + * @param RNGx RNG Instance + * @retval Return 32-bit RNG Health Test configuration + */ +__STATIC_INLINE uint32_t LL_RNG_GetHealthConfig(const RNG_TypeDef *RNGx) +{ + return (uint32_t)READ_REG(RNGx->HTCR); +} + +/** + * @} + */ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RNG_LL_EF_Init Initialization and de-initialization functions + * @{ + */ +ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct); +void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct); +ErrorStatus LL_RNG_DeInit(const RNG_TypeDef *RNGx); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* RNG */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32WBAxx_LL_RNG_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_rtc.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_rtc.h new file mode 100644 index 0000000000..48fe01b278 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_rtc.h @@ -0,0 +1,5888 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_ll_rtc.h + * @author MCD Application Team + * @brief Header file of RTC LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_LL_RTC_H +#define STM32WBAxx_LL_RTC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx.h" + +/** @addtogroup STM32WBAxx_LL_Driver + * @{ + */ + +#if defined(RTC) + +/** @defgroup RTC_LL RTC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup RTC_LL_Private_Constants RTC Private Constants + * @{ + */ +/* Masks Definition */ +#define RTC_LL_INIT_MASK 0xFFFFFFFFU +#define RTC_LL_RSF_MASK 0xFFFFFF5FU + +/* Write protection defines */ +#define RTC_WRITE_PROTECTION_DISABLE (uint8_t)0xFF +#define RTC_WRITE_PROTECTION_ENABLE_1 (uint8_t)0xCA +#define RTC_WRITE_PROTECTION_ENABLE_2 (uint8_t)0x53 + +/* Defines used to combine date & time */ +#define RTC_OFFSET_WEEKDAY 24U +#define RTC_OFFSET_DAY 16U +#define RTC_OFFSET_MONTH 8U +#define RTC_OFFSET_HOUR 16U +#define RTC_OFFSET_MINUTE 8U + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RTC_LL_Private_Macros RTC Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +#if !defined (UNUSED) +#define UNUSED(x) ((void)(x)) +#endif /* !defined (UNUSED) */ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RTC_LL_ES_INIT RTC Exported Init structure + * @{ + */ + +/** + * @brief RTC Init structures definition + */ +typedef struct +{ + uint32_t HourFormat; /*!< Specifies the RTC Hours Format. + This parameter can be a value of @ref RTC_LL_EC_HOURFORMAT + + This feature can be modified afterwards using unitary function + @ref LL_RTC_SetHourFormat(). */ + + uint32_t AsynchPrescaler; /*!< Specifies the RTC Asynchronous Predivider value. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F + + This feature can be modified afterwards using unitary function + @ref LL_RTC_SetAsynchPrescaler(). */ + + uint32_t SynchPrescaler; /*!< Specifies the RTC Synchronous Predivider value. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF + + This feature can be modified afterwards using unitary function + @ref LL_RTC_SetSynchPrescaler(). */ +} LL_RTC_InitTypeDef; + +/** + * @brief RTC Time structure definition + */ +typedef struct +{ + uint32_t TimeFormat; /*!< Specifies the RTC AM/PM Time. + This parameter can be a value of @ref RTC_LL_EC_TIME_FORMAT + + This feature can be modified afterwards using unitary function + @ref LL_RTC_TIME_SetFormat(). */ + + uint8_t Hours; /*!< Specifies the RTC Time Hours. + This parameter must be a number between Min_Data = 0 and Max_Data = 12 + if the @ref LL_RTC_TIME_FORMAT_PM is selected. + + This parameter must be a number between Min_Data = 0 and Max_Data = 23 + if the @ref LL_RTC_TIME_FORMAT_AM_OR_24 is selected. + + This feature can be modified afterwards using unitary function + @ref LL_RTC_TIME_SetHour(). */ + + uint8_t Minutes; /*!< Specifies the RTC Time Minutes. + This parameter must be a number between Min_Data = 0 and Max_Data = 59 + + This feature can be modified afterwards using unitary function + @ref LL_RTC_TIME_SetMinute(). */ + + uint8_t Seconds; /*!< Specifies the RTC Time Seconds. + This parameter must be a number between Min_Data = 0 and Max_Data = 59 + + This feature can be modified afterwards using unitary function + @ref LL_RTC_TIME_SetSecond(). */ +} LL_RTC_TimeTypeDef; + +/** + * @brief RTC Date structure definition + */ +typedef struct +{ + uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay. + This parameter can be a value of @ref RTC_LL_EC_WEEKDAY + + This feature can be modified afterwards using unitary function + @ref LL_RTC_DATE_SetWeekDay(). */ + + uint8_t Month; /*!< Specifies the RTC Date Month. + This parameter can be a value of @ref RTC_LL_EC_MONTH + + This feature can be modified afterwards using unitary function + @ref LL_RTC_DATE_SetMonth(). */ + + uint8_t Day; /*!< Specifies the RTC Date Day. + This parameter must be a number between Min_Data = 1 and Max_Data = 31 + + This feature can be modified afterwards using unitary function + @ref LL_RTC_DATE_SetDay(). */ + + uint8_t Year; /*!< Specifies the RTC Date Year. + This parameter must be a number between Min_Data = 0 and Max_Data = 99 + + This feature can be modified afterwards using unitary function + @ref LL_RTC_DATE_SetYear(). */ +} LL_RTC_DateTypeDef; + +/** + * @brief RTC Alarm structure definition + */ +typedef struct +{ + LL_RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members. */ + + uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks. + This parameter can be a value of @ref RTC_LL_EC_ALMA_MASK for ALARM A or + @ref RTC_LL_EC_ALMB_MASK for ALARM B. + + This feature can be modified afterwards using unitary function + @ref LL_RTC_ALMA_SetMask() for ALARM A or @ref LL_RTC_ALMB_SetMask() for ALARM B. + */ + + uint32_t AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on day or WeekDay. + This parameter can be a value of @ref RTC_LL_EC_ALMA_WEEKDAY_SELECTION + for ALARM A or @ref RTC_LL_EC_ALMB_WEEKDAY_SELECTION for ALARM B. + + This feature can be modified afterwards using unitary function + @ref LL_RTC_ALMA_EnableWeekday() or @ref LL_RTC_ALMA_DisableWeekday() for ALARM A + or @ref LL_RTC_ALMB_EnableWeekday() or @ref LL_RTC_ALMB_DisableWeekday() + for ALARM B. + */ + + uint8_t AlarmDateWeekDay; /*!< Specifies the RTC Alarm Day/WeekDay. + If AlarmDateWeekDaySel set to day, this parameter must be a number + between Min_Data = 1 and Max_Data = 31. + + This feature can be modified afterwards using unitary function + @ref LL_RTC_ALMA_SetDay() for ALARM A or @ref LL_RTC_ALMB_SetDay() for ALARM B. + + If AlarmDateWeekDaySel set to Weekday, this parameter can be a value of + @ref RTC_LL_EC_WEEKDAY. + + This feature can be modified afterwards using unitary function + @ref LL_RTC_ALMA_SetWeekDay() for ALARM A or + @ref LL_RTC_ALMB_SetWeekDay() for ALARM B. + */ +} LL_RTC_AlarmTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RTC_LL_Exported_Constants RTC Exported Constants + * @{ + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RTC_LL_EC_FORMAT FORMAT + * @{ + */ +#define LL_RTC_FORMAT_BIN 0U /*!< Binary data format */ +#define LL_RTC_FORMAT_BCD 1U /*!< BCD data format */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ALMA_WEEKDAY_SELECTION RTC Alarm A Date WeekDay + * @{ + */ +#define LL_RTC_ALMA_DATEWEEKDAYSEL_DATE 0U /*!< Alarm A Date is selected */ +#define LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL /*!< Alarm A WeekDay is selected */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ALMB_WEEKDAY_SELECTION RTC Alarm B Date WeekDay + * @{ + */ +#define LL_RTC_ALMB_DATEWEEKDAYSEL_DATE 0U /*!< Alarm B Date is selected */ +#define LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMBR_WDSEL /*!< Alarm B WeekDay is selected */ +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/** @defgroup RTC_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_RTC_ReadReg function + * @{ + */ +#define LL_RTC_SCR_SSRUF RTC_SCR_CSSRUF +#define LL_RTC_SCR_TSOVF RTC_SCR_CTSOVF +#define LL_RTC_SCR_TSF RTC_SCR_CTSF +#define LL_RTC_SCR_WUTF RTC_SCR_CWUTF +#define LL_RTC_SCR_ALRBF RTC_SCR_CALRBF +#define LL_RTC_SCR_ALRAF RTC_SCR_CALRAF + +#define LL_RTC_ICSR_RECALPF RTC_ICSR_RECALPF +#define LL_RTC_ICSR_BCDU_2 RTC_ICSR_BCDU_2 +#define LL_RTC_ICSR_BCDU_1 RTC_ICSR_BCDU_1 +#define LL_RTC_ICSR_BCDU_0 RTC_ICSR_BCDU_0 +#define LL_RTC_ICSR_BIN_1 RTC_ICSR_BIN_1 +#define LL_RTC_ICSR_BIN_0 RTC_ICSR_BIN_0 +#define LL_RTC_ICSR_INITF RTC_ICSR_INITF +#define LL_RTC_ICSR_RSF RTC_ICSR_RSF +#define LL_RTC_ICSR_INITS RTC_ICSR_INITS +#define LL_RTC_ICSR_SHPF RTC_ICSR_SHPF +#define LL_RTC_ICSR_WUTWF RTC_ICSR_WUTWF +/** + * @} + */ + +/** @defgroup RTC_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_RTC_ReadReg and LL_RTC_WriteReg functions + * @{ + */ +#define LL_RTC_CR_TSIE RTC_CR_TSIE +#define LL_RTC_CR_WUTIE RTC_CR_WUTIE +#define LL_RTC_CR_ALRBIE RTC_CR_ALRBIE +#define LL_RTC_CR_ALRAIE RTC_CR_ALRAIE +/** + * @} + */ + +/** @defgroup RTC_LL_EC_WEEKDAY WEEK DAY + * @{ + */ +#define LL_RTC_WEEKDAY_MONDAY (uint8_t)0x01 /*!< Monday */ +#define LL_RTC_WEEKDAY_TUESDAY (uint8_t)0x02 /*!< Tuesday */ +#define LL_RTC_WEEKDAY_WEDNESDAY (uint8_t)0x03 /*!< Wednesday */ +#define LL_RTC_WEEKDAY_THURSDAY (uint8_t)0x04 /*!< Thrusday */ +#define LL_RTC_WEEKDAY_FRIDAY (uint8_t)0x05 /*!< Friday */ +#define LL_RTC_WEEKDAY_SATURDAY (uint8_t)0x06 /*!< Saturday */ +#define LL_RTC_WEEKDAY_SUNDAY (uint8_t)0x07 /*!< Sunday */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_MONTH MONTH + * @{ + */ +#define LL_RTC_MONTH_JANUARY (uint8_t)0x01 /*!< January */ +#define LL_RTC_MONTH_FEBRUARY (uint8_t)0x02 /*!< February */ +#define LL_RTC_MONTH_MARCH (uint8_t)0x03 /*!< March */ +#define LL_RTC_MONTH_APRIL (uint8_t)0x04 /*!< April */ +#define LL_RTC_MONTH_MAY (uint8_t)0x05 /*!< May */ +#define LL_RTC_MONTH_JUNE (uint8_t)0x06 /*!< June */ +#define LL_RTC_MONTH_JULY (uint8_t)0x07 /*!< July */ +#define LL_RTC_MONTH_AUGUST (uint8_t)0x08 /*!< August */ +#define LL_RTC_MONTH_SEPTEMBER (uint8_t)0x09 /*!< September */ +#define LL_RTC_MONTH_OCTOBER (uint8_t)0x10 /*!< October */ +#define LL_RTC_MONTH_NOVEMBER (uint8_t)0x11 /*!< November */ +#define LL_RTC_MONTH_DECEMBER (uint8_t)0x12 /*!< December */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_HOURFORMAT HOUR FORMAT + * @{ + */ +#define LL_RTC_HOURFORMAT_24HOUR 0U /*!< 24 hour/day format */ +#define LL_RTC_HOURFORMAT_AMPM RTC_CR_FMT /*!< AM/PM hour format */ +/** + * @} + */ + +#if defined(RTC_CR_OSEL) +/** @defgroup RTC_LL_EC_ALARMOUT ALARM OUTPUT + * @{ + */ +#define LL_RTC_ALARMOUT_DISABLE 0U /*!< Output disabled */ +#define LL_RTC_ALARMOUT_ALMA RTC_CR_OSEL_0 /*!< Alarm A output enabled */ +#define LL_RTC_ALARMOUT_ALMB RTC_CR_OSEL_1 /*!< Alarm B output enabled */ +#define LL_RTC_ALARMOUT_WAKEUP RTC_CR_OSEL /*!< Wakeup output enabled */ +/** + * @} + */ +#endif /* RTC_CR_OSEL */ + +/** @defgroup RTC_LL_EC_ALARM_OUTPUTTYPE ALARM OUTPUT TYPE + * @{ + */ +#define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN RTC_CR_TAMPALRM_TYPE /*!< RTC_ALARM is open-drain output */ +#define LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL 0U /*!< RTC_ALARM is push-pull output */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_OUTPUTPOLARITY_PIN OUTPUT POLARITY PIN + * @{ + */ +#define LL_RTC_OUTPUTPOLARITY_PIN_HIGH 0U /*!< Pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL) */ +#define LL_RTC_OUTPUTPOLARITY_PIN_LOW RTC_CR_POL /*!< Pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL) */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TIME_FORMAT TIME FORMAT + * @{ + */ +#define LL_RTC_TIME_FORMAT_AM_OR_24 0U /*!< AM or 24-hour format */ +#define LL_RTC_TIME_FORMAT_PM RTC_TR_PM /*!< PM */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_SHIFT_SECOND SHIFT SECOND + * @{ + */ +#define LL_RTC_SHIFT_SECOND_DELAY 0U /*!< Delay (seconds) = SUBFS / (PREDIV_S + 1) */ +#define LL_RTC_SHIFT_SECOND_ADVANCE RTC_SHIFTR_ADD1S /*!< Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))) */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ALMA_MASK ALARMA MASK + * @{ + */ +#define LL_RTC_ALMA_MASK_NONE 0U /*!< No masks applied on Alarm A */ +#define LL_RTC_ALMA_MASK_DATEWEEKDAY RTC_ALRMAR_MSK4 /*!< Date/day do not care in Alarm A comparison */ +#define LL_RTC_ALMA_MASK_HOURS RTC_ALRMAR_MSK3 /*!< Hours do not care in Alarm A comparison */ +#define LL_RTC_ALMA_MASK_MINUTES RTC_ALRMAR_MSK2 /*!< Minutes do not care in Alarm A comparison */ +#define LL_RTC_ALMA_MASK_SECONDS RTC_ALRMAR_MSK1 /*!< Seconds do not care in Alarm A comparison */ +#define LL_RTC_ALMA_MASK_ALL (RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1) /*!< Masks all */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ALMA_TIME_FORMAT ALARMA TIME FORMAT + * @{ + */ +#define LL_RTC_ALMA_TIME_FORMAT_AM 0U /*!< AM or 24-hour format */ +#define LL_RTC_ALMA_TIME_FORMAT_PM RTC_ALRMAR_PM /*!< PM */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ALMA_SUBSECONDBIN_AUTOCLR RTC Alarm Sub Seconds with binary mode auto clear Definitions + * @{ + */ +#define LL_RTC_ALMA_SUBSECONDBIN_AUTOCLR_NO 0UL +/*!< The synchronous binary counter (SS[31:0] in RTC_SSR) is free-running. */ + +#define LL_RTC_ALMA_SUBSECONDBIN_AUTOCLR_YES RTC_ALRMASSR_SSCLR +/*!< The synchronous binary counter (SS[31:0] in RTC_SSR) is running from 0xFFFF FFFF to RTC_ALRMABINR -> SS[31:0] + value and is automatically reloaded with 0xFFFF FFFF when reaching RTC_ALRMABINR -> SS[31:0]. */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ALMB_MASK ALARMB MASK + * @{ + */ +#define LL_RTC_ALMB_MASK_NONE 0U /*!< No masks applied on Alarm B */ +#define LL_RTC_ALMB_MASK_DATEWEEKDAY RTC_ALRMBR_MSK4 /*!< Date/day do not care in Alarm B comparison */ +#define LL_RTC_ALMB_MASK_HOURS RTC_ALRMBR_MSK3 /*!< Hours do not care in Alarm B comparison */ +#define LL_RTC_ALMB_MASK_MINUTES RTC_ALRMBR_MSK2 /*!< Minutes do not care in Alarm B comparison */ +#define LL_RTC_ALMB_MASK_SECONDS RTC_ALRMBR_MSK1 /*!< Seconds do not care in Alarm B comparison */ +#define LL_RTC_ALMB_MASK_ALL (RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1) /*!< Masks all */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ALMB_TIME_FORMAT ALARMB TIME FORMAT + * @{ + */ +#define LL_RTC_ALMB_TIME_FORMAT_AM 0U /*!< AM or 24-hour format */ +#define LL_RTC_ALMB_TIME_FORMAT_PM RTC_ALRMBR_PM /*!< PM */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ALMB_SUBSECONDBIN_AUTOCLR Alarm Sub Seconds with binary mode auto clear Definitions + * @{ + */ +#define LL_RTC_ALMB_SUBSECONDBIN_AUTOCLR_NO 0UL +/*!< The synchronous binary counter (SS[31:0] in RTC_SSR) is free-running. */ + +#define LL_RTC_ALMB_SUBSECONDBIN_AUTOCLR_YES RTC_ALRMBSSR_SSCLR +/*!< The synchronous binary counter (SS[31:0] in RTC_SSR) is running from 0xFFFF FFFF to RTC_ALRMBBINR -> SS[31:0] + value and is automatically reloaded with 0xFFFF FFFF when reaching RTC_ALRMBBINR -> SS[31:0]. */ +/** + * @} + */ + +#if defined(RTC_CR_TSEDGE) +/** @defgroup RTC_LL_EC_TIMESTAMP_EDGE TIMESTAMP EDGE + * @{ + */ +#define LL_RTC_TIMESTAMP_EDGE_RISING 0U /*!< RTC_TS input rising edge generates a time-stamp event */ +#define LL_RTC_TIMESTAMP_EDGE_FALLING RTC_CR_TSEDGE /*!< RTC_TS input falling edge generates a time-stamp even */ +/** + * @} + */ +#endif /* RTC_CR_TSEDGE */ + +/** @defgroup RTC_LL_EC_TS_TIME_FORMAT TIMESTAMP TIME FORMAT + * @{ + */ +#define LL_RTC_TS_TIME_FORMAT_AM 0U /*!< AM or 24-hour format */ +#define LL_RTC_TS_TIME_FORMAT_PM RTC_TSTR_PM /*!< PM */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TAMPER TAMPER + * @{ + */ +#define LL_RTC_TAMPER_1 TAMP_CR1_TAMP1E /*!< Tamper 1 input detection */ +#define LL_RTC_TAMPER_2 TAMP_CR1_TAMP2E /*!< Tamper 2 input detection */ +#define LL_RTC_TAMPER_3 TAMP_CR1_TAMP3E /*!< Tamper 3 input detection */ +#ifdef TAMP_CR1_TAMP4E +#define LL_RTC_TAMPER_4 TAMP_CR1_TAMP4E /*!< Tamper 4 input detection */ +#define LL_RTC_TAMPER_5 TAMP_CR1_TAMP5E /*!< Tamper 5 input detection */ +#define LL_RTC_TAMPER_6 TAMP_CR1_TAMP6E /*!< Tamper 6 input detection */ +#endif /* TAMP_CR1_TAMP4E */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TAMPER_MASK TAMPER MASK + * @{ + */ +#define LL_RTC_TAMPER_MASK_TAMPER1 TAMP_CR2_TAMP1MSK /*!< Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by hardware. The backup registers are not erased */ +#define LL_RTC_TAMPER_MASK_TAMPER2 TAMP_CR2_TAMP2MSK /*!< Tamper 2 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased */ +#define LL_RTC_TAMPER_MASK_TAMPER3 TAMP_CR2_TAMP3MSK /*!< Tamper 3 event generates a trigger event. TAMP3F is masked and internally cleared by hardware. The backup registers are not erased */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TAMPER_NOERASE TAMPER NO ERASE + * @{ + */ +#define LL_RTC_TAMPER_NOERASE_TAMPER1 TAMP_CR2_TAMP1POM /*!< Tamper 1 event does not erase the backup registers */ +#define LL_RTC_TAMPER_NOERASE_TAMPER2 TAMP_CR2_TAMP2POM /*!< Tamper 2 event does not erase the backup registers */ +#define LL_RTC_TAMPER_NOERASE_TAMPER3 TAMP_CR2_TAMP3POM /*!< Tamper 3 event does not erase the backup registers */ +#ifdef TAMP_CR2_TAMP4POM +#define LL_RTC_TAMPER_NOERASE_TAMPER4 TAMP_CR2_TAMP4POM /*!< Tamper 4 event does not erase the backup registers */ +#define LL_RTC_TAMPER_NOERASE_TAMPER5 TAMP_CR2_TAMP5POM /*!< Tamper 5 event does not erase the backup registers */ +#define LL_RTC_TAMPER_NOERASE_TAMPER6 TAMP_CR2_TAMP6POM /*!< Tamper 6 event does not erase the backup registers */ +#endif /* TAMP_CR2_TAMP4POM */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TAMPER_DURATION TAMPER DURATION + * @{ + */ +#define LL_RTC_TAMPER_DURATION_1RTCCLK 0U /*!< Tamper pins are pre-charged before sampling during 1 RTCCLK cycle */ +#define LL_RTC_TAMPER_DURATION_2RTCCLK TAMP_FLTCR_TAMPPRCH_0 /*!< Tamper pins are pre-charged before sampling during 2 RTCCLK cycles */ +#define LL_RTC_TAMPER_DURATION_4RTCCLK TAMP_FLTCR_TAMPPRCH_1 /*!< Tamper pins are pre-charged before sampling during 4 RTCCLK cycles */ +#define LL_RTC_TAMPER_DURATION_8RTCCLK TAMP_FLTCR_TAMPPRCH /*!< Tamper pins are pre-charged before sampling during 8 RTCCLK cycles */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TAMPER_FILTER TAMPER FILTER + * @{ + */ +#define LL_RTC_TAMPER_FILTER_DISABLE 0U /*!< Tamper filter is disabled */ +#define LL_RTC_TAMPER_FILTER_2SAMPLE TAMP_FLTCR_TAMPFLT_0 /*!< Tamper is activated after 2 consecutive samples at the active level */ +#define LL_RTC_TAMPER_FILTER_4SAMPLE TAMP_FLTCR_TAMPFLT_1 /*!< Tamper is activated after 4 consecutive samples at the active level */ +#define LL_RTC_TAMPER_FILTER_8SAMPLE TAMP_FLTCR_TAMPFLT /*!< Tamper is activated after 8 consecutive samples at the active level */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TAMPER_SAMPLFREQDIV TAMPER SAMPLING FREQUENCY DIVIDER + * @{ + */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_32768 0U /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 32768 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_16384 TAMP_FLTCR_TAMPFREQ_0 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 16384 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_8192 TAMP_FLTCR_TAMPFREQ_1 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 8192 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_4096 (TAMP_FLTCR_TAMPFREQ_1 | TAMP_FLTCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 4096 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_2048 TAMP_FLTCR_TAMPFREQ_2 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 2048 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_1024 (TAMP_FLTCR_TAMPFREQ_2 | TAMP_FLTCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 1024 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_512 (TAMP_FLTCR_TAMPFREQ_2 | TAMP_FLTCR_TAMPFREQ_1) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 512 */ +#define LL_RTC_TAMPER_SAMPLFREQDIV_256 TAMP_FLTCR_TAMPFREQ /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 256 */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_TAMPER_ACTIVELEVEL TAMPER ACTIVE LEVEL + * @{ + */ +#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 TAMP_CR2_TAMP1TRG /*!< Tamper 1 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */ +#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 TAMP_CR2_TAMP2TRG /*!< Tamper 2 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */ +#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 TAMP_CR2_TAMP3TRG /*!< Tamper 3 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */ +#ifdef TAMP_CR2_TAMP4TRG +#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP4 TAMP_CR2_TAMP4TRG /*!< Tamper 4 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */ +#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP5 TAMP_CR2_TAMP5TRG /*!< Tamper 5 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */ +#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP6 TAMP_CR2_TAMP6TRG /*!< Tamper 6 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */ +#endif /* TAMP_CR2_TAMP4TRG */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_INTERNAL INTERNAL TAMPER + * @{ + */ +#define LL_RTC_TAMPER_ITAMP3 TAMP_CR1_ITAMP3E /*!< Internal tamper 3: LSE monitoring */ +#define LL_RTC_TAMPER_ITAMP5 TAMP_CR1_ITAMP5E /*!< Internal tamper 5: RTC calendar overflow */ +#define LL_RTC_TAMPER_ITAMP6 TAMP_CR1_ITAMP6E /*!< Internal tamper 6: JTAG/SWD access when RDP > 0 */ +#define LL_RTC_TAMPER_ITAMP7 TAMP_CR1_ITAMP7E /*!< Internal tamper 7: ADC4 analog watchdog monitoring 1 */ +#define LL_RTC_TAMPER_ITAMP8 TAMP_CR1_ITAMP8E /*!< Internal tamper 8: Monotonic counter overflow */ +#define LL_RTC_TAMPER_ITAMP9 TAMP_CR1_ITAMP9E /*!< Internal tamper 9: Cryptographic IPs fault */ +#define LL_RTC_TAMPER_ITAMP11 TAMP_CR1_ITAMP11E /*!< Internal tamper 11: IWDG reset when tamper flag is set */ +#define LL_RTC_TAMPER_ITAMP12 TAMP_CR1_ITAMP12E /*!< Internal tamper 12: ADC4 analog watchdog monitoring 2 */ +#define LL_RTC_TAMPER_ITAMP13 TAMP_CR1_ITAMP13E /*!< Internal tamper 13: ADC4 analog watchdog monitoring 3 */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ITAMPER_NOERASE INTERNAL TAMPER NO ERASE + * @{ + */ +#define LL_RTC_TAMPER_NOERASE_ITAMPER3 TAMP_CR3_ITAMP3POM /*!< Internal tamper 3 event does not erase the backup registers */ +#define LL_RTC_TAMPER_NOERASE_ITAMPER5 TAMP_CR3_ITAMP5POM /*!< Internal tamper 5 event does not erase the backup registers */ +#define LL_RTC_TAMPER_NOERASE_ITAMPER6 TAMP_CR3_ITAMP6POM /*!< Internal tamper 6 event does not erase the backup registers */ +#define LL_RTC_TAMPER_NOERASE_ITAMPER7 TAMP_CR3_ITAMP7POM /*!< Internal tamper 7 event does not erase the backup registers */ +#define LL_RTC_TAMPER_NOERASE_ITAMPER8 TAMP_CR3_ITAMP8POM /*!< Internal tamper 8 event does not erase the backup registers */ +#define LL_RTC_TAMPER_NOERASE_ITAMPER9 TAMP_CR3_ITAMP9POM /*!< Internal tamper 9 event does not erase the backup registers */ +#define LL_RTC_TAMPER_NOERASE_ITAMPER11 TAMP_CR3_ITAMP11POM /*!< Internal tamper 11 event does not erase the backup registers */ +#define LL_RTC_TAMPER_NOERASE_ITAMPER12 TAMP_CR3_ITAMP12POM /*!< Internal tamper 12 event does not erase the backup registers */ +#define LL_RTC_TAMPER_NOERASE_ITAMPER13 TAMP_CR3_ITAMP13POM /*!< Internal tamper 13 event does not erase the backup registers */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ACTIVE_MODE ACTIVE TAMPER MODE + * @{ + */ +#define LL_RTC_TAMPER_ATAMP_TAMP1AM TAMP_ATCR1_TAMP1AM /*!< Tamper 1 is active */ +#define LL_RTC_TAMPER_ATAMP_TAMP2AM TAMP_ATCR1_TAMP2AM /*!< Tamper 2 is active */ +#define LL_RTC_TAMPER_ATAMP_TAMP3AM TAMP_ATCR1_TAMP3AM /*!< Tamper 3 is active */ +#ifdef TAMP_ATCR1_TAMP4AM +#define LL_RTC_TAMPER_ATAMP_TAMP4AM TAMP_ATCR1_TAMP4AM /*!< Tamper 4 is active */ +#define LL_RTC_TAMPER_ATAMP_TAMP5AM TAMP_ATCR1_TAMP5AM /*!< Tamper 5 is active */ +#define LL_RTC_TAMPER_ATAMP_TAMP6AM TAMP_ATCR1_TAMP6AM /*!< Tamper 6 is active */ +#endif /* TAMP_ATCR1_TAMP4AM */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ACTIVE_ASYNC_PRESCALER ACTIVE TAMPER ASYNCHRONOUS PRESCALER CLOCK + * @{ + */ +#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK 0U /*!< RTCCLK */ +#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_2 TAMP_ATCR1_ATCKSEL_0 /*!< RTCCLK/2 */ +#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_4 TAMP_ATCR1_ATCKSEL_1 /*!< RTCCLK/4 */ +#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_8 (TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/8 */ +#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_16 TAMP_ATCR1_ATCKSEL_2 /*!< RTCCLK/16 */ +#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_32 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/32 */ +#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_64 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1) /*!< RTCCLK/64 */ +#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_128 (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0) /*!< RTCCLK/128 */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_ACTIVE_OUTPUT_SELECTION ACTIVE TAMPER OUTPUT SELECTION + * @{ + */ +#define LL_RTC_TAMPER_ATAMP1IN_ATAMP1OUT (0U << TAMP_ATCR2_ATOSEL1_Pos) +#define LL_RTC_TAMPER_ATAMP1IN_ATAMP2OUT (1U << TAMP_ATCR2_ATOSEL1_Pos) +#define LL_RTC_TAMPER_ATAMP1IN_ATAMP3OUT (2U << TAMP_ATCR2_ATOSEL1_Pos) +#define LL_RTC_TAMPER_ATAMP1IN_ATAMP4OUT (3U << TAMP_ATCR2_ATOSEL1_Pos) +#define LL_RTC_TAMPER_ATAMP1IN_ATAMP5OUT (4U << TAMP_ATCR2_ATOSEL1_Pos) +#define LL_RTC_TAMPER_ATAMP1IN_ATAMP6OUT (5U << TAMP_ATCR2_ATOSEL1_Pos) + +#define LL_RTC_TAMPER_ATAMP2IN_ATAMP1OUT (0U << TAMP_ATCR2_ATOSEL2_Pos) +#define LL_RTC_TAMPER_ATAMP2IN_ATAMP2OUT (1U << TAMP_ATCR2_ATOSEL2_Pos) +#define LL_RTC_TAMPER_ATAMP2IN_ATAMP3OUT (2U << TAMP_ATCR2_ATOSEL2_Pos) +#define LL_RTC_TAMPER_ATAMP2IN_ATAMP4OUT (3U << TAMP_ATCR2_ATOSEL2_Pos) +#define LL_RTC_TAMPER_ATAMP2IN_ATAMP5OUT (4U << TAMP_ATCR2_ATOSEL2_Pos) +#define LL_RTC_TAMPER_ATAMP2IN_ATAMP6OUT (5U << TAMP_ATCR2_ATOSEL2_Pos) + +#define LL_RTC_TAMPER_ATAMP3IN_ATAMP1OUT (0U << TAMP_ATCR2_ATOSEL3_Pos) +#define LL_RTC_TAMPER_ATAMP3IN_ATAMP2OUT (1U << TAMP_ATCR2_ATOSEL3_Pos) +#define LL_RTC_TAMPER_ATAMP3IN_ATAMP3OUT (2U << TAMP_ATCR2_ATOSEL3_Pos) +#define LL_RTC_TAMPER_ATAMP3IN_ATAMP4OUT (3U << TAMP_ATCR2_ATOSEL3_Pos) +#define LL_RTC_TAMPER_ATAMP3IN_ATAMP5OUT (4U << TAMP_ATCR2_ATOSEL3_Pos) +#define LL_RTC_TAMPER_ATAMP3IN_ATAMP6OUT (5U << TAMP_ATCR2_ATOSEL3_Pos) + +#define LL_RTC_TAMPER_ATAMP4IN_ATAMP1OUT (0U << TAMP_ATCR2_ATOSEL4_Pos) +#define LL_RTC_TAMPER_ATAMP4IN_ATAMP2OUT (1U << TAMP_ATCR2_ATOSEL4_Pos) +#define LL_RTC_TAMPER_ATAMP4IN_ATAMP3OUT (2U << TAMP_ATCR2_ATOSEL4_Pos) +#define LL_RTC_TAMPER_ATAMP4IN_ATAMP4OUT (3U << TAMP_ATCR2_ATOSEL4_Pos) +#define LL_RTC_TAMPER_ATAMP4IN_ATAMP5OUT (4U << TAMP_ATCR2_ATOSEL4_Pos) +#define LL_RTC_TAMPER_ATAMP4IN_ATAMP6OUT (5U << TAMP_ATCR2_ATOSEL4_Pos) + +#define LL_RTC_TAMPER_ATAMP5IN_ATAMP1OUT (0U << TAMP_ATCR2_ATOSEL5_Pos) +#define LL_RTC_TAMPER_ATAMP5IN_ATAMP2OUT (1U << TAMP_ATCR2_ATOSEL5_Pos) +#define LL_RTC_TAMPER_ATAMP5IN_ATAMP3OUT (2U << TAMP_ATCR2_ATOSEL5_Pos) +#define LL_RTC_TAMPER_ATAMP5IN_ATAMP4OUT (3U << TAMP_ATCR2_ATOSEL5_Pos) +#define LL_RTC_TAMPER_ATAMP5IN_ATAMP5OUT (4U << TAMP_ATCR2_ATOSEL5_Pos) +#define LL_RTC_TAMPER_ATAMP5IN_ATAMP6OUT (5U << TAMP_ATCR2_ATOSEL5_Pos) + +#define LL_RTC_TAMPER_ATAMP6IN_ATAMP1OUT (0U << TAMP_ATCR2_ATOSEL6_Pos) +#define LL_RTC_TAMPER_ATAMP6IN_ATAMP2OUT (1U << TAMP_ATCR2_ATOSEL6_Pos) +#define LL_RTC_TAMPER_ATAMP6IN_ATAMP3OUT (2U << TAMP_ATCR2_ATOSEL6_Pos) +#define LL_RTC_TAMPER_ATAMP6IN_ATAMP4OUT (3U << TAMP_ATCR2_ATOSEL6_Pos) +#define LL_RTC_TAMPER_ATAMP6IN_ATAMP5OUT (4U << TAMP_ATCR2_ATOSEL6_Pos) +#define LL_RTC_TAMPER_ATAMP6IN_ATAMP6OUT (5U << TAMP_ATCR2_ATOSEL6_Pos) +/** + * @} + */ + +/** @defgroup RTC_LL_EC_BKP BACKUP + * @{ + */ +#define LL_RTC_BKP_NUMBER RTC_BACKUP_NB +#define LL_RTC_BKP_DR0 0U +#define LL_RTC_BKP_DR1 1U +#define LL_RTC_BKP_DR2 2U +#define LL_RTC_BKP_DR3 3U +#define LL_RTC_BKP_DR4 4U +#define LL_RTC_BKP_DR5 5U +#define LL_RTC_BKP_DR6 6U +#define LL_RTC_BKP_DR7 7U +#define LL_RTC_BKP_DR8 8U +#define LL_RTC_BKP_DR9 9U +#define LL_RTC_BKP_DR10 10U +#define LL_RTC_BKP_DR11 11U +#define LL_RTC_BKP_DR12 12U +#define LL_RTC_BKP_DR13 13U +#define LL_RTC_BKP_DR14 14U +#define LL_RTC_BKP_DR15 15U +#define LL_RTC_BKP_DR16 16U +#define LL_RTC_BKP_DR17 17U +#define LL_RTC_BKP_DR18 18U +#define LL_RTC_BKP_DR19 19U +#define LL_RTC_BKP_DR20 20U +#define LL_RTC_BKP_DR21 21U +#define LL_RTC_BKP_DR22 22U +#define LL_RTC_BKP_DR23 23U +#define LL_RTC_BKP_DR24 24U +#define LL_RTC_BKP_DR25 25U +#define LL_RTC_BKP_DR26 26U +#define LL_RTC_BKP_DR27 27U +#define LL_RTC_BKP_DR28 28U +#define LL_RTC_BKP_DR29 29U +#define LL_RTC_BKP_DR30 30U +#define LL_RTC_BKP_DR31 31U +/** + * @} + */ + +/** @defgroup RTC_LL_EC_WAKEUPCLOCK_DIV WAKEUP CLOCK DIV + * @{ + */ +#define LL_RTC_WAKEUPCLOCK_DIV_16 0U /*!< RTC/16 clock is selected */ +#define LL_RTC_WAKEUPCLOCK_DIV_8 RTC_CR_WUCKSEL_0 /*!< RTC/8 clock is selected */ +#define LL_RTC_WAKEUPCLOCK_DIV_4 RTC_CR_WUCKSEL_1 /*!< RTC/4 clock is selected */ +#define LL_RTC_WAKEUPCLOCK_DIV_2 (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_0) /*!< RTC/2 clock is selected */ +#define LL_RTC_WAKEUPCLOCK_CKSPRE RTC_CR_WUCKSEL_2 /*!< ck_spre (usually 1 Hz) clock is selected */ +#define LL_RTC_WAKEUPCLOCK_CKSPRE_WUT (RTC_CR_WUCKSEL_2 | RTC_CR_WUCKSEL_1) /*!< ck_spre (usually 1 Hz) clock is selected and 2exp16 is added to the WUT counter value */ +/** + * @} + */ + +#if defined(RTC_CR_COE) +/** @defgroup RTC_LL_EC_CALIB_OUTPUT Calibration output + * @{ + */ +#define LL_RTC_CALIB_OUTPUT_NONE 0U /*!< Calibration output disabled */ +#define LL_RTC_CALIB_OUTPUT_1HZ (RTC_CR_COE | RTC_CR_COSEL) /*!< Calibration output is 1 Hz */ +#define LL_RTC_CALIB_OUTPUT_512HZ RTC_CR_COE /*!< Calibration output is 512 Hz */ +/** + * @} + */ +#endif /* RTC_CR_COE */ + +/** @defgroup RTC_LL_EC_CALIB_INSERTPULSE Calibration pulse insertion + * @{ + */ +#define LL_RTC_CALIB_INSERTPULSE_NONE 0U /*!< No RTCCLK pulses are added */ +#define LL_RTC_CALIB_INSERTPULSE_SET RTC_CALR_CALP /*!< One RTCCLK pulse is effectively inserted every 2exp11 pulses (frequency increased by 488.5 ppm) */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_CALIB_PERIOD Calibration period + * @{ + */ +#define LL_RTC_CALIB_PERIOD_32SEC 0U /*!< Use a 32-second calibration cycle period */ +#define LL_RTC_CALIB_PERIOD_16SEC RTC_CALR_CALW16 /*!< Use a 16-second calibration cycle period */ +#define LL_RTC_CALIB_PERIOD_8SEC RTC_CALR_CALW8 /*!< Use a 8-second calibration cycle period */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_CALIB_LOWPOWER Calibration low power + * @{ + */ +#define LL_RTC_CALIB_LOWPOWER_NONE 0U /*!< High conso mode */ +#define LL_RTC_CALIB_LOWPOWER_SET RTC_CALR_LPCAL /*!< Low power mode */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_BINARY_MODE Binary mode (Sub Second Register) + * @{ + */ +#define LL_RTC_BINARY_NONE 0U /*!< Free running BCD calendar mode (Binary mode disabled) */ +#define LL_RTC_BINARY_ONLY RTC_ICSR_BIN_0 /*!< Free running Binary mode (BCD mode disabled) */ +#define LL_RTC_BINARY_MIX RTC_ICSR_BIN_1 /*!< Free running BCD calendar and Binary mode enable */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_BINARY_MIX_BCDU Calendar second incrementation in Binary mix mode + * @{ + */ +#define LL_RTC_BINARY_MIX_BCDU_0 0U /*!< 1s calendar increment is generated each time SS[7:0] = 0 */ +#define LL_RTC_BINARY_MIX_BCDU_1 (0x1UL << RTC_ICSR_BCDU_Pos) /*!< 1s calendar increment is generated each time SS[8:0] = 0 */ +#define LL_RTC_BINARY_MIX_BCDU_2 (0x2UL << RTC_ICSR_BCDU_Pos) /*!< 1s calendar increment is generated each time SS[9:0] = 0 */ +#define LL_RTC_BINARY_MIX_BCDU_3 (0x3UL << RTC_ICSR_BCDU_Pos) /*!< 1s calendar increment is generated each time SS[10:0] = 0 */ +#define LL_RTC_BINARY_MIX_BCDU_4 (0x4UL << RTC_ICSR_BCDU_Pos) /*!< 1s calendar increment is generated each time SS[11:0] = 0 */ +#define LL_RTC_BINARY_MIX_BCDU_5 (0x5UL << RTC_ICSR_BCDU_Pos) /*!< 1s calendar increment is generated each time SS[12:0] = 0 */ +#define LL_RTC_BINARY_MIX_BCDU_6 (0x6UL << RTC_ICSR_BCDU_Pos) /*!< 1s calendar increment is generated each time SS[13:0] = 0 */ +#define LL_RTC_BINARY_MIX_BCDU_7 (0x7UL << RTC_ICSR_BCDU_Pos) /*!< 1s calendar increment is generated each time SS[14:0] = 0 */ +/** + * @} + */ + +#if defined(RTC_SECCFGR_SEC) +/** @defgroup RTC_LL_EC_SECURE_RTC_FULL Secure full rtc + * @{ + */ +#define LL_RTC_SECURE_FULL_YES RTC_SECCFGR_SEC /*!< RTC full secure */ +#define LL_RTC_SECURE_FULL_NO 0U /*!< RTC is not full secure, features can be secure. See RTC_LL_EC_SECURE_RTC_FEATURE */ +/** + * @} + */ +#endif /* RTC_SECCFGR_SEC */ + +/** @defgroup RTC_LL_EC_SECURE_RTC_FEATURE Secure features rtc in case of LL_RTC_SECURE_FULL_NO. + * @{ + */ +#define LL_RTC_SECURE_FEATURE_INIT RTC_SECCFGR_INITSEC /*!< Initialization feature is secure */ +#define LL_RTC_SECURE_FEATURE_CAL RTC_SECCFGR_CALSEC /*!< Calibration feature is secure */ +#define LL_RTC_SECURE_FEATURE_TS RTC_SECCFGR_TSSEC /*!< Time stamp feature is secure */ +#define LL_RTC_SECURE_FEATURE_WUT RTC_SECCFGR_WUTSEC /*!< Wake up timer feature is secure */ +#define LL_RTC_SECURE_FEATURE_ALRA RTC_SECCFGR_ALRASEC /*!< Alarm A feature is secure */ +#define LL_RTC_SECURE_FEATURE_ALRB RTC_SECCFGR_ALRBSEC /*!< Alarm B feature is secure */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_SECURE_TAMP Secure tamp + * @{ + */ +#define LL_TAMP_SECURE_FULL_YES TAMP_SECCFGR_TAMPSEC /*!< TAMP full secure */ +#define LL_TAMP_SECURE_FULL_NO 0U /*!< TAMP is not secure */ +/** + * @} + */ + +#if defined(RTC_PRIVCFGR_PRIV) +/** @defgroup RTC_LL_EC_PRIVILEGE_RTC_FULL Privilege full rtc + * @{ + */ +#define LL_RTC_PRIVILEGE_FULL_YES RTC_PRIVCFGR_PRIV /*!< RTC full privilege */ +#define LL_RTC_PRIVILEGE_FULL_NO 0U /*!< RTC is not full privilege, features can be unprivilege. See RTC_LL_EC_PRIVILEGE_RTC_FEATURE */ +/** + * @} + */ +#endif /* RTC_PRIVCFGR_PRIV */ + +/** @defgroup RTC_LL_EC_PRIVILEGE_RTC_FEATURE Privilege rtc features in case of LL_RTC_PRIVILEGE_FULL_NO. + * @{ + */ +#define LL_RTC_PRIVILEGE_FEATURE_INIT RTC_PRIVCFGR_INITPRIV /*!< Initialization feature is privilege */ +#define LL_RTC_PRIVILEGE_FEATURE_CAL RTC_PRIVCFGR_CALPRIV /*!< Calibration feature is privilege */ +#define LL_RTC_PRIVILEGE_FEATURE_TS RTC_PRIVCFGR_TSPRIV /*!< Time stamp feature is privilege */ +#define LL_RTC_PRIVILEGE_FEATURE_WUT RTC_PRIVCFGR_WUTPRIV /*!< Wake up timer feature is privilege */ +#define LL_RTC_PRIVILEGE_FEATURE_ALRA RTC_PRIVCFGR_ALRAPRIV /*!< Alarm A feature is privilege */ +#define LL_RTC_PRIVILEGE_FEATURE_ALRB RTC_PRIVCFGR_ALRBPRIV /*!< Alarm B feature is privilege */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_PRIVILEGE_TAMP_FULL Privilege full tamp + * @{ + */ +#define LL_TAMP_PRIVILEGE_FULL_YES TAMP_PRIVCFGR_TAMPPRIV /*!< TAMP full privilege */ +#define LL_TAMP_PRIVILEGE_FULL_NO 0U /*!< TAMP is not privilege */ +/** + * @} + */ + +/** @defgroup RTC_LL_EC_PRIVILEGE_BACKUP_REG_ZONE Privilege Backup register privilege zone + * @{ + */ +#define LL_RTC_PRIVILEGE_BKUP_ZONE_NONE 0U +#define LL_RTC_PRIVILEGE_BKUP_ZONE_1 TAMP_PRIVCFGR_BKPRWPRIV +#define LL_RTC_PRIVILEGE_BKUP_ZONE_2 TAMP_PRIVCFGR_BKPWPRIV +#define LL_RTC_PRIVILEGE_BKUP_ZONE_ALL (LL_RTC_PRIVILEGE_BKUP_ZONE_1 | LL_RTC_PRIVILEGE_BKUP_ZONE_2) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup RTC_LL_Exported_Macros RTC Exported Macros + * @{ + */ + +/** @defgroup RTC_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in RTC register + * @param __INSTANCE__ RTC Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_RTC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in RTC register + * @param __INSTANCE__ RTC Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_RTC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup RTC_LL_EM_Convert Convert helper Macros + * @{ + */ + +/** + * @brief Helper macro to convert a value from 2 digit decimal format to BCD format + * @param __VALUE__ Byte to be converted + * @retval Converted byte + */ +#define __LL_RTC_CONVERT_BIN2BCD(__VALUE__) ((uint8_t)((((__VALUE__) / 10U) << 4U) | ((__VALUE__) % 10U))) + +/** + * @brief Helper macro to convert a value from BCD format to 2 digit decimal format + * @param __VALUE__ BCD value to be converted + * @retval Converted byte + */ +#define __LL_RTC_CONVERT_BCD2BIN(__VALUE__) \ + ((uint8_t)((((uint8_t)((__VALUE__) & (uint8_t)0xF0U) >> (uint8_t)0x4U) * 10U) + ((__VALUE__) & (uint8_t)0x0FU))) + +/** + * @} + */ + +/** @defgroup RTC_LL_EM_Date Date helper Macros + * @{ + */ + +/** + * @brief Helper macro to retrieve weekday. + * @param __RTC_DATE__ Date returned by @ref LL_RTC_DATE_Get function. + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_WEEKDAY_MONDAY + * @arg @ref LL_RTC_WEEKDAY_TUESDAY + * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY + * @arg @ref LL_RTC_WEEKDAY_THURSDAY + * @arg @ref LL_RTC_WEEKDAY_FRIDAY + * @arg @ref LL_RTC_WEEKDAY_SATURDAY + * @arg @ref LL_RTC_WEEKDAY_SUNDAY + */ +#define __LL_RTC_GET_WEEKDAY(__RTC_DATE__) (((__RTC_DATE__) >> RTC_OFFSET_WEEKDAY) & 0x000000FFU) + +/** + * @brief Helper macro to retrieve Year in BCD format + * @param __RTC_DATE__ Value returned by @ref LL_RTC_DATE_Get + * @retval Year in BCD format (0x00 . . . 0x99) + */ +#define __LL_RTC_GET_YEAR(__RTC_DATE__) ((__RTC_DATE__) & 0x000000FFU) + +/** + * @brief Helper macro to retrieve Month in BCD format + * @param __RTC_DATE__ Value returned by @ref LL_RTC_DATE_Get + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_MONTH_JANUARY + * @arg @ref LL_RTC_MONTH_FEBRUARY + * @arg @ref LL_RTC_MONTH_MARCH + * @arg @ref LL_RTC_MONTH_APRIL + * @arg @ref LL_RTC_MONTH_MAY + * @arg @ref LL_RTC_MONTH_JUNE + * @arg @ref LL_RTC_MONTH_JULY + * @arg @ref LL_RTC_MONTH_AUGUST + * @arg @ref LL_RTC_MONTH_SEPTEMBER + * @arg @ref LL_RTC_MONTH_OCTOBER + * @arg @ref LL_RTC_MONTH_NOVEMBER + * @arg @ref LL_RTC_MONTH_DECEMBER + */ +#define __LL_RTC_GET_MONTH(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_MONTH) & 0x000000FFU) + +/** + * @brief Helper macro to retrieve Day in BCD format + * @param __RTC_DATE__ Value returned by @ref LL_RTC_DATE_Get + * @retval Day in BCD format (0x01 . . . 0x31) + */ +#define __LL_RTC_GET_DAY(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_DAY) & 0x000000FFU) + +/** + * @} + */ + +/** @defgroup RTC_LL_EM_Time Time helper Macros + * @{ + */ + +/** + * @brief Helper macro to retrieve hour in BCD format + * @param __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function + * @retval Hours in BCD format (0x01. . .0x12 or between Min_Data=0x00 and Max_Data=0x23) + */ +#define __LL_RTC_GET_HOUR(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_HOUR) & 0x000000FFU) + +/** + * @brief Helper macro to retrieve minute in BCD format + * @param __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function + * @retval Minutes in BCD format (0x00. . .0x59) + */ +#define __LL_RTC_GET_MINUTE(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_MINUTE) & 0x000000FFU) + +/** + * @brief Helper macro to retrieve second in BCD format + * @param __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function + * @retval Seconds in format (0x00. . .0x59) + */ +#define __LL_RTC_GET_SECOND(__RTC_TIME__) ((__RTC_TIME__) & 0x000000FFU) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup RTC_LL_Exported_Functions RTC Exported Functions + * @{ + */ + +/** @defgroup RTC_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Set Hours format (24 hour/day or AM/PM hour format) + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) + * @rmtoll RTC_CR FMT LL_RTC_SetHourFormat + * @param RTCx RTC Instance + * @param HourFormat This parameter can be one of the following values: + * @arg @ref LL_RTC_HOURFORMAT_24HOUR + * @arg @ref LL_RTC_HOURFORMAT_AMPM + * @retval None + */ +__STATIC_INLINE void LL_RTC_SetHourFormat(RTC_TypeDef *RTCx, uint32_t HourFormat) +{ + MODIFY_REG(RTCx->CR, RTC_CR_FMT, HourFormat); +} + +/** + * @brief Get Hours format (24 hour/day or AM/PM hour format) + * @rmtoll RTC_CR FMT LL_RTC_GetHourFormat + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_HOURFORMAT_24HOUR + * @arg @ref LL_RTC_HOURFORMAT_AMPM + */ +__STATIC_INLINE uint32_t LL_RTC_GetHourFormat(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_FMT)); +} + +#if defined(RTC_CR_OSEL) +/** + * @brief Select the flag to be routed to RTC_ALARM output + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR OSEL LL_RTC_SetAlarmOutEvent + * @param RTCx RTC Instance + * @param AlarmOutput This parameter can be one of the following values: + * @arg @ref LL_RTC_ALARMOUT_DISABLE + * @arg @ref LL_RTC_ALARMOUT_ALMA + * @arg @ref LL_RTC_ALARMOUT_ALMB + * @arg @ref LL_RTC_ALARMOUT_WAKEUP + * @retval None + */ +__STATIC_INLINE void LL_RTC_SetAlarmOutEvent(RTC_TypeDef *RTCx, uint32_t AlarmOutput) +{ + MODIFY_REG(RTCx->CR, RTC_CR_OSEL, AlarmOutput); +} + +/** + * @brief Get the flag to be routed to RTC_ALARM output + * @rmtoll RTC_CR OSEL LL_RTC_GetAlarmOutEvent + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_ALARMOUT_DISABLE + * @arg @ref LL_RTC_ALARMOUT_ALMA + * @arg @ref LL_RTC_ALARMOUT_ALMB + * @arg @ref LL_RTC_ALARMOUT_WAKEUP + */ +__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutEvent(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_OSEL)); +} +#endif /* RTC_CR_OSEL */ + + +#ifdef RTC_CR_TAMPALRM_TYPE +/** + * @brief Set RTC_ALARM output type (ALARM in push-pull or open-drain output) + * @rmtoll RTC_CR TAMPALRM_TYPE LL_RTC_SetAlarmOutputType + * @param RTCx RTC Instance + * @param Output This parameter can be one of the following values: + * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN + * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL + * @retval None + */ +__STATIC_INLINE void LL_RTC_SetAlarmOutputType(RTC_TypeDef *RTCx, uint32_t Output) +{ + MODIFY_REG(RTCx->CR, RTC_CR_TAMPALRM_TYPE, Output); +} + +/** + * @brief Get RTC_ALARM output type (ALARM in push-pull or open-drain output) + * @rmtoll RTC_CR TAMPALRM_TYPE LL_RTC_GetAlarmOutputType + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN + * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL + */ +__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutputType(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_TAMPALRM_TYPE)); +} +#endif /* RTC_CR_TAMPALRM_TYPE */ + +/** + * @brief Enable initialization mode + * @note Initialization mode is used to program time and date register (RTC_TR and RTC_DR) + * and prescaler register (RTC_PRER). + * Counters are stopped and start counting from the new value when INIT is reset. + * @rmtoll RTC_ICSR INIT LL_RTC_EnableInitMode + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableInitMode(RTC_TypeDef *RTCx) +{ + /* Set the Initialization mode */ + SET_BIT(RTCx->ICSR, RTC_ICSR_INIT); +} + +/** + * @brief Disable initialization mode (Free running mode) + * @rmtoll RTC_ICSR INIT LL_RTC_DisableInitMode + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableInitMode(RTC_TypeDef *RTCx) +{ + /* Exit Initialization mode */ + CLEAR_BIT(RTCx->ICSR, RTC_ICSR_INIT); + +} + +/** + * @brief Set Binary mode (Sub Second Register) + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function). + * @rmtoll RTC_ICSR BIN LL_RTC_SetBinaryMode + * @param RTCx RTC Instance + * @param BinaryMode can be one of the following values: + * @arg @ref LL_RTC_BINARY_NONE + * @arg @ref LL_RTC_BINARY_ONLY + * @arg @ref LL_RTC_BINARY_MIX + * @retval None + */ +__STATIC_INLINE void LL_RTC_SetBinaryMode(RTC_TypeDef *RTCx, uint32_t BinaryMode) +{ + MODIFY_REG(RTCx->ICSR, RTC_ICSR_BIN, BinaryMode); +} + +/** + * @brief Get Binary mode (Sub Second Register) + * @rmtoll RTC_ICSR BIN LL_RTC_GetBinaryMode + * @param RTCx RTC Instance + * @retval This parameter can be one of the following values: + * @arg @ref LL_RTC_BINARY_NONE + * @arg @ref LL_RTC_BINARY_ONLY + * @arg @ref LL_RTC_BINARY_MIX + * @retval None + */ +__STATIC_INLINE uint32_t LL_RTC_GetBinaryMode(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ICSR, RTC_ICSR_BIN)); +} + +/** + * @brief Set Binary Mix mode BCDU + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function). + * @rmtoll RTC_ICSR BCDU LL_RTC_SetBinMixBCDU + * @param RTCx RTC Instance + * @param BinMixBcdU can be one of the following values: + * @arg @ref LL_RTC_BINARY_MIX_BCDU_0 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_1 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_2 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_3 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_4 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_5 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_6 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_7 + * @retval None + */ +__STATIC_INLINE void LL_RTC_SetBinMixBCDU(RTC_TypeDef *RTCx, uint32_t BinMixBcdU) +{ + MODIFY_REG(RTCx->ICSR, RTC_ICSR_BCDU, BinMixBcdU); +} + +/** + * @brief Get Binary Mix mode BCDU + * @rmtoll RTC_ICSR BCDU LL_RTC_GetBinMixBCDU + * @param RTCx RTC Instance + * @retval This parameter can be one of the following values: + * @arg @ref LL_RTC_BINARY_MIX_BCDU_0 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_1 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_2 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_3 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_4 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_5 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_6 + * @arg @ref LL_RTC_BINARY_MIX_BCDU_7 + * @retval None + */ +__STATIC_INLINE uint32_t LL_RTC_GetBinMixBCDU(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ICSR, RTC_ICSR_BCDU)); +} + + +#ifdef RTC_CR_POL +/** + * @brief Set Output polarity (pin is low when ALRAF/ALRBF/WUTF is asserted) + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR POL LL_RTC_SetOutputPolarity + * @param RTCx RTC Instance + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH + * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_LOW + * @retval None + */ +__STATIC_INLINE void LL_RTC_SetOutputPolarity(RTC_TypeDef *RTCx, uint32_t Polarity) +{ + MODIFY_REG(RTCx->CR, RTC_CR_POL, Polarity); +} + +/** + * @brief Get Output polarity + * @rmtoll RTC_CR POL LL_RTC_GetOutputPolarity + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH + * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_LOW + */ +__STATIC_INLINE uint32_t LL_RTC_GetOutputPolarity(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_POL)); +} +#endif /* RTC_CR_POL */ + +/** + * @brief Enable Bypass the shadow registers + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR BYPSHAD LL_RTC_EnableShadowRegBypass + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableShadowRegBypass(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_BYPSHAD); +} + +/** + * @brief Disable Bypass the shadow registers + * @rmtoll RTC_CR BYPSHAD LL_RTC_DisableShadowRegBypass + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableShadowRegBypass(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_BYPSHAD); +} + +/** + * @brief Check if Shadow registers bypass is enabled or not. + * @rmtoll RTC_CR BYPSHAD LL_RTC_IsShadowRegBypassEnabled + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsShadowRegBypassEnabled(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->CR, RTC_CR_BYPSHAD) == (RTC_CR_BYPSHAD)) ? 1U : 0U); +} + +#if defined(RTC_CR_REFCKON) +/** + * @brief Enable RTC_REFIN reference clock detection (50 or 60 Hz) + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) + * @rmtoll RTC_CR REFCKON LL_RTC_EnableRefClock + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableRefClock(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_REFCKON); +} + +/** + * @brief Disable RTC_REFIN reference clock detection (50 or 60 Hz) + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) + * @rmtoll RTC_CR REFCKON LL_RTC_DisableRefClock + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableRefClock(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_REFCKON); +} +#endif /* RTC_CR_REFCKON */ + +/** + * @brief Set Asynchronous prescaler factor + * @rmtoll RTC_PRER PREDIV_A LL_RTC_SetAsynchPrescaler + * @param RTCx RTC Instance + * @param AsynchPrescaler Value between Min_Data = 0 and Max_Data = 0x7F + * @retval None + */ +__STATIC_INLINE void LL_RTC_SetAsynchPrescaler(RTC_TypeDef *RTCx, uint32_t AsynchPrescaler) +{ + MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_A, AsynchPrescaler << RTC_PRER_PREDIV_A_Pos); +} + +/** + * @brief Set Synchronous prescaler factor + * @rmtoll RTC_PRER PREDIV_S LL_RTC_SetSynchPrescaler + * @param RTCx RTC Instance + * @param SynchPrescaler Value between Min_Data = 0 and Max_Data = 0x7FFF + * @retval None + */ +__STATIC_INLINE void LL_RTC_SetSynchPrescaler(RTC_TypeDef *RTCx, uint32_t SynchPrescaler) +{ + MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_S, SynchPrescaler); +} + +/** + * @brief Get Asynchronous prescaler factor + * @rmtoll RTC_PRER PREDIV_A LL_RTC_GetAsynchPrescaler + * @param RTCx RTC Instance + * @retval Value between Min_Data = 0 and Max_Data = 0x7F + */ +__STATIC_INLINE uint32_t LL_RTC_GetAsynchPrescaler(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_A) >> RTC_PRER_PREDIV_A_Pos); +} + +/** + * @brief Get Synchronous prescaler factor + * @rmtoll RTC_PRER PREDIV_S LL_RTC_GetSynchPrescaler + * @param RTCx RTC Instance + * @retval Value between Min_Data = 0 and Max_Data = 0x7FFF + */ +__STATIC_INLINE uint32_t LL_RTC_GetSynchPrescaler(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_S)); +} + +/** + * @brief Enable the write protection for RTC registers. + * @rmtoll RTC_WPR KEY LL_RTC_EnableWriteProtection + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableWriteProtection(RTC_TypeDef *RTCx) +{ + WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_DISABLE); +} + +/** + * @brief Disable the write protection for RTC registers. + * @rmtoll RTC_WPR KEY LL_RTC_DisableWriteProtection + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableWriteProtection(RTC_TypeDef *RTCx) +{ + WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_1); + WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_2); +} + +#ifdef RTC_CR_TAMPOE +/** + * @brief Enable tamper output. + * @note When the tamper output is enabled, all external and internal tamper flags + * are ORed and routed to the TAMPALRM output. + * @rmtoll RTC_CR TAMPOE LL_RTC_EnableTamperOutput + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableTamperOutput(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_TAMPOE); +} + +/** + * @brief Disable tamper output. + * @rmtoll RTC_CR TAMPOE LL_RTC_DisableTamperOutput + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableTamperOutput(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_TAMPOE); +} + +/** + * @brief Check if tamper output is enabled or not. + * @rmtoll RTC_CR TAMPOE LL_RTC_IsTamperOutputEnabled + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsTamperOutputEnabled(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->CR, RTC_CR_TAMPOE) == (RTC_CR_TAMPOE)) ? 1U : 0U); +} + +/** + * @brief Enable internal pull-up in output mode. + * @rmtoll RTC_CR TAMPALRM_PU LL_RTC_EnableAlarmPullUp + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableAlarmPullUp(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_TAMPALRM_PU); +} +#endif /* RTC_CR_TAMPOE */ + +#ifdef RTC_CR_TAMPALRM_PU +/** + * @brief Disable internal pull-up in output mode. + * @rmtoll RTC_CR TAMPALRM_PU LL_RTC_EnableAlarmPullUp + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableAlarmPullUp(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_TAMPALRM_PU); +} + +/** + * @brief Check if internal pull-up in output mode is enabled or not. + * @rmtoll RTC_CR TAMPALRM_PU LL_RTC_IsAlarmPullUpEnabled + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsAlarmPullUpEnabled(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->CR, RTC_CR_TAMPALRM_PU) == (RTC_CR_TAMPALRM_PU)) ? 1U : 0U); +} +#endif /* RTC_CR_TAMPALRM_PU */ + + +#if defined(RTC_CR_OUT2EN) +/** + * @brief Enable RTC_OUT2 output + * @note RTC_OUT2 mapping depends on both OSEL (@ref LL_RTC_SetAlarmOutEvent) + * and COE (@ref LL_RTC_CAL_SetOutputFreq) settings. + * @note RTC_OUT2 is not available ins VBAT mode. + * @rmtoll RTC_CR OUT2EN LL_RTC_EnableOutput2 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableOutput2(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_OUT2EN); +} + +/** + * @brief Disable RTC_OUT2 output + * @rmtoll RTC_CR OUT2EN LL_RTC_DisableOutput2 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableOutput2(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_OUT2EN); +} + +/** + * @brief Check if RTC_OUT2 output is enabled or not. + * @rmtoll RTC_CR OUT2EN LL_RTC_IsOutput2Enabled + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsOutput2Enabled(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->CR, RTC_CR_OUT2EN) == (RTC_CR_OUT2EN)) ? 1U : 0U); +} +#endif /* RTC_CR_OUT2EN */ + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_Time Time + * @{ + */ + +/** + * @brief Set time format (AM/24-hour or PM notation) + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) + * @rmtoll RTC_TR PM LL_RTC_TIME_SetFormat + * @param RTCx RTC Instance + * @param TimeFormat This parameter can be one of the following values: + * @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24 + * @arg @ref LL_RTC_TIME_FORMAT_PM + * @retval None + */ +__STATIC_INLINE void LL_RTC_TIME_SetFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat) +{ + MODIFY_REG(RTCx->TR, RTC_TR_PM, TimeFormat); +} + +/** + * @brief Get time format (AM or PM notation) + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set + * before reading this bit + * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar + * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). + * @rmtoll RTC_TR PM LL_RTC_TIME_GetFormat + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24 + * @arg @ref LL_RTC_TIME_FORMAT_PM + */ +__STATIC_INLINE uint32_t LL_RTC_TIME_GetFormat(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TR, RTC_TR_PM)); +} + +/** + * @brief Set Hours in BCD format + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert hour from binary to BCD format + * @rmtoll RTC_TR HT LL_RTC_TIME_SetHour\n + * RTC_TR HU LL_RTC_TIME_SetHour + * @param RTCx RTC Instance + * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 + * @retval None + */ +__STATIC_INLINE void LL_RTC_TIME_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) +{ + MODIFY_REG(RTCx->TR, (RTC_TR_HT | RTC_TR_HU), + (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos))); +} + +/** + * @brief Get Hours in BCD format + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set + * before reading this bit + * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar + * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert hour from BCD to + * Binary format + * @rmtoll RTC_TR HT LL_RTC_TIME_GetHour\n + * RTC_TR HU LL_RTC_TIME_GetHour + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 + */ +__STATIC_INLINE uint32_t LL_RTC_TIME_GetHour(const RTC_TypeDef *RTCx) +{ + return (uint32_t)((READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU))) >> RTC_TR_HU_Pos); +} + +/** + * @brief Set Minutes in BCD format + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format + * @rmtoll RTC_TR MNT LL_RTC_TIME_SetMinute\n + * RTC_TR MNU LL_RTC_TIME_SetMinute + * @param RTCx RTC Instance + * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59 + * @retval None + */ +__STATIC_INLINE void LL_RTC_TIME_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) +{ + MODIFY_REG(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU), + (((Minutes & 0xF0U) << (RTC_TR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_TR_MNU_Pos))); +} + +/** + * @brief Get Minutes in BCD format + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set + * before reading this bit + * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar + * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert minute from BCD + * to Binary format + * @rmtoll RTC_TR MNT LL_RTC_TIME_GetMinute\n + * RTC_TR MNU LL_RTC_TIME_GetMinute + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x59 + */ +__STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU)) >> RTC_TR_MNU_Pos); +} + +/** + * @brief Set Seconds in BCD format + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format + * @rmtoll RTC_TR ST LL_RTC_TIME_SetSecond\n + * RTC_TR SU LL_RTC_TIME_SetSecond + * @param RTCx RTC Instance + * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59 + * @retval None + */ +__STATIC_INLINE void LL_RTC_TIME_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) +{ + MODIFY_REG(RTCx->TR, (RTC_TR_ST | RTC_TR_SU), + (((Seconds & 0xF0U) << (RTC_TR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_TR_SU_Pos))); +} + +/** + * @brief Get Seconds in BCD format + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set + * before reading this bit + * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar + * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD + * to Binary format + * @rmtoll RTC_TR ST LL_RTC_TIME_GetSecond\n + * RTC_TR SU LL_RTC_TIME_GetSecond + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x59 + */ +__STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TR, (RTC_TR_ST | RTC_TR_SU)) >> RTC_TR_SU_Pos); +} + +/** + * @brief Set time (hour, minute and second) in BCD format + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) + * @note TimeFormat and Hours should follow the same format + * @rmtoll RTC_TR PM LL_RTC_TIME_Config\n + * RTC_TR HT LL_RTC_TIME_Config\n + * RTC_TR HU LL_RTC_TIME_Config\n + * RTC_TR MNT LL_RTC_TIME_Config\n + * RTC_TR MNU LL_RTC_TIME_Config\n + * RTC_TR ST LL_RTC_TIME_Config\n + * RTC_TR SU LL_RTC_TIME_Config + * @param RTCx RTC Instance + * @param Format12_24 This parameter can be one of the following values: + * @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24 + * @arg @ref LL_RTC_TIME_FORMAT_PM + * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 + * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59 + * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59 + * @retval None + */ +__STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, + uint32_t Format12_24, + uint32_t Hours, + uint32_t Minutes, + uint32_t Seconds) +{ + uint32_t temp; + + temp = Format12_24 | \ + (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos)) | \ + (((Minutes & 0xF0U) << (RTC_TR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_TR_MNU_Pos)) | \ + (((Seconds & 0xF0U) << (RTC_TR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_TR_SU_Pos)); + MODIFY_REG(RTCx->TR, (RTC_TR_PM | RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU), temp); +} + +/** + * @brief Get time (hour, minute and second) in BCD format + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set + * before reading this bit + * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar + * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). + * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND + * are available to get independently each parameter. + * @rmtoll RTC_TR HT LL_RTC_TIME_Get\n + * RTC_TR HU LL_RTC_TIME_Get\n + * RTC_TR MNT LL_RTC_TIME_Get\n + * RTC_TR MNU LL_RTC_TIME_Get\n + * RTC_TR ST LL_RTC_TIME_Get\n + * RTC_TR SU LL_RTC_TIME_Get + * @param RTCx RTC Instance + * @retval Combination of hours, minutes and seconds (Format: 0x00HHMMSS). + */ +__STATIC_INLINE uint32_t LL_RTC_TIME_Get(const RTC_TypeDef *RTCx) +{ + uint32_t temp; + + temp = READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU)); + return (uint32_t)((((((temp & RTC_TR_HT) >> RTC_TR_HT_Pos) << 4U) | \ + ((temp & RTC_TR_HU) >> RTC_TR_HU_Pos)) << RTC_OFFSET_HOUR) | \ + (((((temp & RTC_TR_MNT) >> RTC_TR_MNT_Pos) << 4U) | \ + ((temp & RTC_TR_MNU) >> RTC_TR_MNU_Pos)) << RTC_OFFSET_MINUTE) | \ + ((((temp & RTC_TR_ST) >> RTC_TR_ST_Pos) << 4U) | ((temp & RTC_TR_SU) >> RTC_TR_SU_Pos))); +} + +/** + * @brief Memorize whether the daylight saving time change has been performed + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR BKP LL_RTC_TIME_EnableDayLightStore + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TIME_EnableDayLightStore(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_BKP); +} + +/** + * @brief Disable memorization whether the daylight saving time change has been performed. + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR BKP LL_RTC_TIME_DisableDayLightStore + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TIME_DisableDayLightStore(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_BKP); +} + +/** + * @brief Check if RTC Day Light Saving stored operation has been enabled or not + * @rmtoll RTC_CR BKP LL_RTC_TIME_IsDayLightStoreEnabled + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_TIME_IsDayLightStoreEnabled(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->CR, RTC_CR_BKP) == (RTC_CR_BKP)) ? 1U : 0U); +} + +/** + * @brief Subtract 1 hour (winter time change) + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR SUB1H LL_RTC_TIME_DecHour + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TIME_DecHour(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_SUB1H); +} + +/** + * @brief Add 1 hour (summer time change) + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR ADD1H LL_RTC_TIME_IncHour + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TIME_IncHour(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_ADD1H); +} + +/** + * @brief Get Sub second value in the synchronous prescaler counter. + * @note You can use both SubSeconds value and SecondFraction (PREDIV_S through + * LL_RTC_GetSynchPrescaler function) terms returned to convert Calendar + * SubSeconds value in second fraction ratio with time unit following + * generic formula: + * ==> Seconds fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit + * This conversion can be performed only if no shift operation is pending + * (ie. SHFP=0) when PREDIV_S >= SS. + * @rmtoll RTC_SSR SS LL_RTC_TIME_GetSubSecond + * @param RTCx RTC Instance + * @retval If binary mode is none, Value between Min_Data=0x0 and Max_Data=0x7FFF + * else Value between Min_Data=0x0 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_RTC_TIME_GetSubSecond(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->SSR, RTC_SSR_SS)); +} + +/** + * @brief Synchronize to a remote clock with a high degree of precision. + * @note This operation effectively subtracts from (delays) or advance the clock of a fraction of a second. + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note When REFCKON is set, firmware must not write to Shift control register. + * @rmtoll RTC_SHIFTR ADD1S LL_RTC_TIME_Synchronize\n + * RTC_SHIFTR SUBFS LL_RTC_TIME_Synchronize + * @param RTCx RTC Instance + * @param ShiftSecond This parameter can be one of the following values: + * @arg @ref LL_RTC_SHIFT_SECOND_DELAY + * @arg @ref LL_RTC_SHIFT_SECOND_ADVANCE + * @param Fraction Number of Seconds Fractions (any value from 0 to 0x7FFF) + * @retval None + */ +__STATIC_INLINE void LL_RTC_TIME_Synchronize(RTC_TypeDef *RTCx, uint32_t ShiftSecond, uint32_t Fraction) +{ + WRITE_REG(RTCx->SHIFTR, ShiftSecond | Fraction); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_Date Date + * @{ + */ + +/** + * @brief Set Year in BCD format + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Year from binary to BCD format + * @rmtoll RTC_DR YT LL_RTC_DATE_SetYear\n + * RTC_DR YU LL_RTC_DATE_SetYear + * @param RTCx RTC Instance + * @param Year Value between Min_Data=0x00 and Max_Data=0x99 + * @retval None + */ +__STATIC_INLINE void LL_RTC_DATE_SetYear(RTC_TypeDef *RTCx, uint32_t Year) +{ + MODIFY_REG(RTCx->DR, (RTC_DR_YT | RTC_DR_YU), + (((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos))); +} + +/** + * @brief Get Year in BCD format + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set + * before reading this bit + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Year from BCD to Binary format + * @rmtoll RTC_DR YT LL_RTC_DATE_GetYear\n + * RTC_DR YU LL_RTC_DATE_GetYear + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x99 + */ +__STATIC_INLINE uint32_t LL_RTC_DATE_GetYear(const RTC_TypeDef *RTCx) +{ + return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_YT | RTC_DR_YU))) >> RTC_DR_YU_Pos); +} + +/** + * @brief Set Week day + * @rmtoll RTC_DR WDU LL_RTC_DATE_SetWeekDay + * @param RTCx RTC Instance + * @param WeekDay This parameter can be one of the following values: + * @arg @ref LL_RTC_WEEKDAY_MONDAY + * @arg @ref LL_RTC_WEEKDAY_TUESDAY + * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY + * @arg @ref LL_RTC_WEEKDAY_THURSDAY + * @arg @ref LL_RTC_WEEKDAY_FRIDAY + * @arg @ref LL_RTC_WEEKDAY_SATURDAY + * @arg @ref LL_RTC_WEEKDAY_SUNDAY + * @retval None + */ +__STATIC_INLINE void LL_RTC_DATE_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) +{ + MODIFY_REG(RTCx->DR, RTC_DR_WDU, WeekDay << RTC_DR_WDU_Pos); +} + +/** + * @brief Get Week day + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set + * before reading this bit + * @rmtoll RTC_DR WDU LL_RTC_DATE_GetWeekDay + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_WEEKDAY_MONDAY + * @arg @ref LL_RTC_WEEKDAY_TUESDAY + * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY + * @arg @ref LL_RTC_WEEKDAY_THURSDAY + * @arg @ref LL_RTC_WEEKDAY_FRIDAY + * @arg @ref LL_RTC_WEEKDAY_SATURDAY + * @arg @ref LL_RTC_WEEKDAY_SUNDAY + */ +__STATIC_INLINE uint32_t LL_RTC_DATE_GetWeekDay(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->DR, RTC_DR_WDU) >> RTC_DR_WDU_Pos); +} + +/** + * @brief Set Month in BCD format + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Month from binary to BCD format + * @rmtoll RTC_DR MT LL_RTC_DATE_SetMonth\n + * RTC_DR MU LL_RTC_DATE_SetMonth + * @param RTCx RTC Instance + * @param Month This parameter can be one of the following values: + * @arg @ref LL_RTC_MONTH_JANUARY + * @arg @ref LL_RTC_MONTH_FEBRUARY + * @arg @ref LL_RTC_MONTH_MARCH + * @arg @ref LL_RTC_MONTH_APRIL + * @arg @ref LL_RTC_MONTH_MAY + * @arg @ref LL_RTC_MONTH_JUNE + * @arg @ref LL_RTC_MONTH_JULY + * @arg @ref LL_RTC_MONTH_AUGUST + * @arg @ref LL_RTC_MONTH_SEPTEMBER + * @arg @ref LL_RTC_MONTH_OCTOBER + * @arg @ref LL_RTC_MONTH_NOVEMBER + * @arg @ref LL_RTC_MONTH_DECEMBER + * @retval None + */ +__STATIC_INLINE void LL_RTC_DATE_SetMonth(RTC_TypeDef *RTCx, uint32_t Month) +{ + MODIFY_REG(RTCx->DR, (RTC_DR_MT | RTC_DR_MU), + (((Month & 0xF0U) << (RTC_DR_MT_Pos - 4U)) | ((Month & 0x0FU) << RTC_DR_MU_Pos))); +} + +/** + * @brief Get Month in BCD format + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set + * before reading this bit + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format + * @rmtoll RTC_DR MT LL_RTC_DATE_GetMonth\n + * RTC_DR MU LL_RTC_DATE_GetMonth + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_MONTH_JANUARY + * @arg @ref LL_RTC_MONTH_FEBRUARY + * @arg @ref LL_RTC_MONTH_MARCH + * @arg @ref LL_RTC_MONTH_APRIL + * @arg @ref LL_RTC_MONTH_MAY + * @arg @ref LL_RTC_MONTH_JUNE + * @arg @ref LL_RTC_MONTH_JULY + * @arg @ref LL_RTC_MONTH_AUGUST + * @arg @ref LL_RTC_MONTH_SEPTEMBER + * @arg @ref LL_RTC_MONTH_OCTOBER + * @arg @ref LL_RTC_MONTH_NOVEMBER + * @arg @ref LL_RTC_MONTH_DECEMBER + */ +__STATIC_INLINE uint32_t LL_RTC_DATE_GetMonth(const RTC_TypeDef *RTCx) +{ + return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_MT | RTC_DR_MU))) >> RTC_DR_MU_Pos); +} + +/** + * @brief Set Day in BCD format + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format + * @rmtoll RTC_DR DT LL_RTC_DATE_SetDay\n + * RTC_DR DU LL_RTC_DATE_SetDay + * @param RTCx RTC Instance + * @param Day Value between Min_Data=0x01 and Max_Data=0x31 + * @retval None + */ +__STATIC_INLINE void LL_RTC_DATE_SetDay(RTC_TypeDef *RTCx, uint32_t Day) +{ + MODIFY_REG(RTCx->DR, (RTC_DR_DT | RTC_DR_DU), + (((Day & 0xF0U) << (RTC_DR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_DR_DU_Pos))); +} + +/** + * @brief Get Day in BCD format + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set + * before reading this bit + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format + * @rmtoll RTC_DR DT LL_RTC_DATE_GetDay\n + * RTC_DR DU LL_RTC_DATE_GetDay + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x01 and Max_Data=0x31 + */ +__STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(const RTC_TypeDef *RTCx) +{ + return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_DT | RTC_DR_DU))) >> RTC_DR_DU_Pos); +} + +/** + * @brief Set date (WeekDay, Day, Month and Year) in BCD format + * @rmtoll RTC_DR WDU LL_RTC_DATE_Config\n + * RTC_DR MT LL_RTC_DATE_Config\n + * RTC_DR MU LL_RTC_DATE_Config\n + * RTC_DR DT LL_RTC_DATE_Config\n + * RTC_DR DU LL_RTC_DATE_Config\n + * RTC_DR YT LL_RTC_DATE_Config\n + * RTC_DR YU LL_RTC_DATE_Config + * @param RTCx RTC Instance + * @param WeekDay This parameter can be one of the following values: + * @arg @ref LL_RTC_WEEKDAY_MONDAY + * @arg @ref LL_RTC_WEEKDAY_TUESDAY + * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY + * @arg @ref LL_RTC_WEEKDAY_THURSDAY + * @arg @ref LL_RTC_WEEKDAY_FRIDAY + * @arg @ref LL_RTC_WEEKDAY_SATURDAY + * @arg @ref LL_RTC_WEEKDAY_SUNDAY + * @param Day Value between Min_Data=0x01 and Max_Data=0x31 + * @param Month This parameter can be one of the following values: + * @arg @ref LL_RTC_MONTH_JANUARY + * @arg @ref LL_RTC_MONTH_FEBRUARY + * @arg @ref LL_RTC_MONTH_MARCH + * @arg @ref LL_RTC_MONTH_APRIL + * @arg @ref LL_RTC_MONTH_MAY + * @arg @ref LL_RTC_MONTH_JUNE + * @arg @ref LL_RTC_MONTH_JULY + * @arg @ref LL_RTC_MONTH_AUGUST + * @arg @ref LL_RTC_MONTH_SEPTEMBER + * @arg @ref LL_RTC_MONTH_OCTOBER + * @arg @ref LL_RTC_MONTH_NOVEMBER + * @arg @ref LL_RTC_MONTH_DECEMBER + * @param Year Value between Min_Data=0x00 and Max_Data=0x99 + * @retval None + */ +__STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, + uint32_t WeekDay, + uint32_t Day, + uint32_t Month, + uint32_t Year) +{ + uint32_t temp; + + temp = (WeekDay << RTC_DR_WDU_Pos) | \ + (((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos)) | \ + (((Month & 0xF0U) << (RTC_DR_MT_Pos - 4U)) | ((Month & 0x0FU) << RTC_DR_MU_Pos)) | \ + (((Day & 0xF0U) << (RTC_DR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_DR_DU_Pos)); + + MODIFY_REG(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU), temp); +} + +/** + * @brief Get date (WeekDay, Day, Month and Year) in BCD format + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set + * before reading this bit + * @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_YEAR, __LL_RTC_GET_MONTH, + * and __LL_RTC_GET_DAY are available to get independently each parameter. + * @rmtoll RTC_DR WDU LL_RTC_DATE_Get\n + * RTC_DR MT LL_RTC_DATE_Get\n + * RTC_DR MU LL_RTC_DATE_Get\n + * RTC_DR DT LL_RTC_DATE_Get\n + * RTC_DR DU LL_RTC_DATE_Get\n + * RTC_DR YT LL_RTC_DATE_Get\n + * RTC_DR YU LL_RTC_DATE_Get + * @param RTCx RTC Instance + * @retval Combination of WeekDay, Day, Month and Year (Format: 0xWWDDMMYY). + */ +__STATIC_INLINE uint32_t LL_RTC_DATE_Get(const RTC_TypeDef *RTCx) +{ + uint32_t temp; + + temp = READ_BIT(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU)); + return (uint32_t)((((temp & RTC_DR_WDU) >> RTC_DR_WDU_Pos) << RTC_OFFSET_WEEKDAY) | \ + (((((temp & RTC_DR_DT) >> RTC_DR_DT_Pos) << 4U) | \ + ((temp & RTC_DR_DU) >> RTC_DR_DU_Pos)) << RTC_OFFSET_DAY) | \ + (((((temp & RTC_DR_MT) >> RTC_DR_MT_Pos) << 4U) | \ + ((temp & RTC_DR_MU) >> RTC_DR_MU_Pos)) << RTC_OFFSET_MONTH) | \ + ((((temp & RTC_DR_YT) >> RTC_DR_YT_Pos) << 4U) | ((temp & RTC_DR_YU) >> RTC_DR_YU_Pos))); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_ALARMA ALARMA + * @{ + */ + +/** + * @brief Enable Alarm A + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR ALRAE LL_RTC_ALMA_Enable + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_Enable(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_ALRAE); +} + +/** + * @brief Disable Alarm A + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR ALRAE LL_RTC_ALMA_Disable + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_Disable(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_ALRAE); +} + +/** + * @brief Specify the Alarm A masks. + * @rmtoll RTC_ALRMAR MSK4 LL_RTC_ALMA_SetMask\n + * RTC_ALRMAR MSK3 LL_RTC_ALMA_SetMask\n + * RTC_ALRMAR MSK2 LL_RTC_ALMA_SetMask\n + * RTC_ALRMAR MSK1 LL_RTC_ALMA_SetMask + * @param RTCx RTC Instance + * @param Mask This parameter can be a combination of the following values: + * @arg @ref LL_RTC_ALMA_MASK_NONE + * @arg @ref LL_RTC_ALMA_MASK_DATEWEEKDAY + * @arg @ref LL_RTC_ALMA_MASK_HOURS + * @arg @ref LL_RTC_ALMA_MASK_MINUTES + * @arg @ref LL_RTC_ALMA_MASK_SECONDS + * @arg @ref LL_RTC_ALMA_MASK_ALL + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_SetMask(RTC_TypeDef *RTCx, uint32_t Mask) +{ + MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1, Mask); +} + +/** + * @brief Get the Alarm A masks. + * @rmtoll RTC_ALRMAR MSK4 LL_RTC_ALMA_GetMask\n + * RTC_ALRMAR MSK3 LL_RTC_ALMA_GetMask\n + * RTC_ALRMAR MSK2 LL_RTC_ALMA_GetMask\n + * RTC_ALRMAR MSK1 LL_RTC_ALMA_GetMask + * @param RTCx RTC Instance + * @retval Returned value can be can be a combination of the following values: + * @arg @ref LL_RTC_ALMA_MASK_NONE + * @arg @ref LL_RTC_ALMA_MASK_DATEWEEKDAY + * @arg @ref LL_RTC_ALMA_MASK_HOURS + * @arg @ref LL_RTC_ALMA_MASK_MINUTES + * @arg @ref LL_RTC_ALMA_MASK_SECONDS + * @arg @ref LL_RTC_ALMA_MASK_ALL + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMask(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1)); +} + +/** + * @brief Enable AlarmA Week day selection (DU[3:0] represents the week day. DT[1:0] is do not care) + * @rmtoll RTC_ALRMAR WDSEL LL_RTC_ALMA_EnableWeekday + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_EnableWeekday(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->ALRMAR, RTC_ALRMAR_WDSEL); +} + +/** + * @brief Disable AlarmA Week day selection (DU[3:0] represents the date ) + * @rmtoll RTC_ALRMAR WDSEL LL_RTC_ALMA_DisableWeekday + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_DisableWeekday(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->ALRMAR, RTC_ALRMAR_WDSEL); +} + +/** + * @brief Set ALARM A Day in BCD format + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format + * @rmtoll RTC_ALRMAR DT LL_RTC_ALMA_SetDay\n + * RTC_ALRMAR DU LL_RTC_ALMA_SetDay + * @param RTCx RTC Instance + * @param Day Value between Min_Data=0x01 and Max_Data=0x31 + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_SetDay(RTC_TypeDef *RTCx, uint32_t Day) +{ + MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU), + (((Day & 0xF0U) << (RTC_ALRMAR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_ALRMAR_DU_Pos))); +} + +/** + * @brief Get ALARM A Day in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format + * @rmtoll RTC_ALRMAR DT LL_RTC_ALMA_GetDay\n + * RTC_ALRMAR DU LL_RTC_ALMA_GetDay + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x01 and Max_Data=0x31 + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetDay(const RTC_TypeDef *RTCx) +{ + return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU))) >> RTC_ALRMAR_DU_Pos); +} + +/** + * @brief Set ALARM A Weekday + * @rmtoll RTC_ALRMAR DU LL_RTC_ALMA_SetWeekDay + * @param RTCx RTC Instance + * @param WeekDay This parameter can be one of the following values: + * @arg @ref LL_RTC_WEEKDAY_MONDAY + * @arg @ref LL_RTC_WEEKDAY_TUESDAY + * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY + * @arg @ref LL_RTC_WEEKDAY_THURSDAY + * @arg @ref LL_RTC_WEEKDAY_FRIDAY + * @arg @ref LL_RTC_WEEKDAY_SATURDAY + * @arg @ref LL_RTC_WEEKDAY_SUNDAY + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) +{ + MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_DU, WeekDay << RTC_ALRMAR_DU_Pos); +} + +/** + * @brief Get ALARM A Weekday + * @rmtoll RTC_ALRMAR DU LL_RTC_ALMA_GetWeekDay + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_WEEKDAY_MONDAY + * @arg @ref LL_RTC_WEEKDAY_TUESDAY + * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY + * @arg @ref LL_RTC_WEEKDAY_THURSDAY + * @arg @ref LL_RTC_WEEKDAY_FRIDAY + * @arg @ref LL_RTC_WEEKDAY_SATURDAY + * @arg @ref LL_RTC_WEEKDAY_SUNDAY + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetWeekDay(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_DU) >> RTC_ALRMAR_DU_Pos); +} + +/** + * @brief Set Alarm A time format (AM/24-hour or PM notation) + * @rmtoll RTC_ALRMAR PM LL_RTC_ALMA_SetTimeFormat + * @param RTCx RTC Instance + * @param TimeFormat This parameter can be one of the following values: + * @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM + * @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat) +{ + MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_PM, TimeFormat); +} + +/** + * @brief Get Alarm A time format (AM or PM notation) + * @rmtoll RTC_ALRMAR PM LL_RTC_ALMA_GetTimeFormat + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM + * @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTimeFormat(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_PM)); +} + +/** + * @brief Set ALARM A Hours in BCD format + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD format + * @rmtoll RTC_ALRMAR HT LL_RTC_ALMA_SetHour\n + * RTC_ALRMAR HU LL_RTC_ALMA_SetHour + * @param RTCx RTC Instance + * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) +{ + MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU), + (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos))); +} + +/** + * @brief Get ALARM A Hours in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format + * @rmtoll RTC_ALRMAR HT LL_RTC_ALMA_GetHour\n + * RTC_ALRMAR HU LL_RTC_ALMA_GetHour + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetHour(const RTC_TypeDef *RTCx) +{ + return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU))) >> RTC_ALRMAR_HU_Pos); +} + +/** + * @brief Set ALARM A Minutes in BCD format + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format + * @rmtoll RTC_ALRMAR MNT LL_RTC_ALMA_SetMinute\n + * RTC_ALRMAR MNU LL_RTC_ALMA_SetMinute + * @param RTCx RTC Instance + * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59 + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) +{ + MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU), + (((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos))); +} + +/** + * @brief Get ALARM A Minutes in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format + * @rmtoll RTC_ALRMAR MNT LL_RTC_ALMA_GetMinute\n + * RTC_ALRMAR MNU LL_RTC_ALMA_GetMinute + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x59 + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMinute(const RTC_TypeDef *RTCx) +{ + return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU))) >> RTC_ALRMAR_MNU_Pos); +} + +/** + * @brief Set ALARM A Seconds in BCD format + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format + * @rmtoll RTC_ALRMAR ST LL_RTC_ALMA_SetSecond\n + * RTC_ALRMAR SU LL_RTC_ALMA_SetSecond + * @param RTCx RTC Instance + * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59 + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) +{ + MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU), + (((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos))); +} + +/** + * @brief Get ALARM A Seconds in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format + * @rmtoll RTC_ALRMAR ST LL_RTC_ALMA_GetSecond\n + * RTC_ALRMAR SU LL_RTC_ALMA_GetSecond + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x59 + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(const RTC_TypeDef *RTCx) +{ + return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU))) >> RTC_ALRMAR_SU_Pos); +} + +/** + * @brief Set Alarm A Time (hour, minute and second) in BCD format + * @rmtoll RTC_ALRMAR PM LL_RTC_ALMA_ConfigTime\n + * RTC_ALRMAR HT LL_RTC_ALMA_ConfigTime\n + * RTC_ALRMAR HU LL_RTC_ALMA_ConfigTime\n + * RTC_ALRMAR MNT LL_RTC_ALMA_ConfigTime\n + * RTC_ALRMAR MNU LL_RTC_ALMA_ConfigTime\n + * RTC_ALRMAR ST LL_RTC_ALMA_ConfigTime\n + * RTC_ALRMAR SU LL_RTC_ALMA_ConfigTime + * @param RTCx RTC Instance + * @param Format12_24 This parameter can be one of the following values: + * @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM + * @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM + * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 + * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59 + * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59 + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_ConfigTime(RTC_TypeDef *RTCx, + uint32_t Format12_24, + uint32_t Hours, + uint32_t Minutes, + uint32_t Seconds) +{ + uint32_t temp; + + temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos)) | \ + (((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos)) | \ + (((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos)); + + MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_PM | RTC_ALRMAR_HT | RTC_ALRMAR_HU | RTC_ALRMAR_MNT | RTC_ALRMAR_MNU | \ + RTC_ALRMAR_ST | RTC_ALRMAR_SU, temp); +} + +/** + * @brief Get Alarm B Time (hour, minute and second) in BCD format + * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND + * are available to get independently each parameter. + * @rmtoll RTC_ALRMAR HT LL_RTC_ALMA_GetTime\n + * RTC_ALRMAR HU LL_RTC_ALMA_GetTime\n + * RTC_ALRMAR MNT LL_RTC_ALMA_GetTime\n + * RTC_ALRMAR MNU LL_RTC_ALMA_GetTime\n + * RTC_ALRMAR ST LL_RTC_ALMA_GetTime\n + * RTC_ALRMAR SU LL_RTC_ALMA_GetTime + * @param RTCx RTC Instance + * @retval Combination of hours, minutes and seconds. + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTime(const RTC_TypeDef *RTCx) +{ + return (uint32_t)((LL_RTC_ALMA_GetHour(RTCx) << RTC_OFFSET_HOUR) | + (LL_RTC_ALMA_GetMinute(RTCx) << RTC_OFFSET_MINUTE) | LL_RTC_ALMA_GetSecond(RTCx)); +} + +/** + * @brief Set Alarm A Mask the most-significant bits starting at this bit + * @note This register can be written only when ALRAE is reset in RTC_CR register, + * or in initialization mode. + * @rmtoll RTC_ALRMASSR MASKSS LL_RTC_ALMA_SetSubSecondMask + * @param RTCx RTC Instance + * @param Mask If binary mode is none, Value between Min_Data=0x0 and Max_Data=0xF + * else Value between Min_Data=0x0 and Max_Data=0x3F + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Mask) +{ + MODIFY_REG(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS, Mask << RTC_ALRMASSR_MASKSS_Pos); +} + +/** + * @brief Get Alarm A Mask the most-significant bits starting at this bit + * @rmtoll RTC_ALRMASSR MASKSS LL_RTC_ALMA_GetSubSecondMask + * @param RTCx RTC Instance + * @retval If binary mode is none, Value between Min_Data=0x0 and Max_Data=0xF + * else Value between Min_Data=0x0 and Max_Data=0x3F + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecondMask(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS) >> RTC_ALRMASSR_MASKSS_Pos); +} + +/** + * @brief Set Alarm A Binary mode auto clear + * @note This register can be written only when ALRAE is reset in RTC_CR register, + * or in initialization mode. + * @rmtoll RTC_ALRABINR SSCLR LL_RTC_ALMA_SetBinAutoClr + * @param RTCx RTC Instance + * @param BinaryAutoClr This parameter can be one of the following values: + * @arg @ref LL_RTC_ALMA_SUBSECONDBIN_AUTOCLR_NO + * @arg @ref LL_RTC_ALMA_SUBSECONDBIN_AUTOCLR_YES + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_SetBinAutoClr(RTC_TypeDef *RTCx, uint32_t BinaryAutoClr) +{ + MODIFY_REG(RTCx->ALRMASSR, RTC_ALRMASSR_SSCLR, BinaryAutoClr); +} + +/** + * @brief Get Alarm A Binary mode auto clear + * @rmtoll RTC_ALRABINR SSCLR LL_RTC_ALMA_GetBinAutoClr + * @param RTCx RTC Instance + * @retval It can be one of the following values: + * @arg @ref LL_RTC_ALMA_SUBSECONDBIN_AUTOCLR_NO + * @arg @ref LL_RTC_ALMA_SUBSECONDBIN_AUTOCLR_YES + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetBinAutoClr(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_SSCLR)); +} + +/** + * @brief Set Alarm A Sub seconds value + * @rmtoll RCT_ALRMASSR SS LL_RTC_ALMA_SetSubSecond + * @param RTCx RTC Instance + * @param Subsecond If binary mode is none, Value between Min_Data=0x0 and Max_Data=0x7FFF + * else Value between Min_Data=0x0 and Max_Data=0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMA_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsecond) +{ + MODIFY_REG(RTCx->ALRMASSR, RTC_ALRMASSR_SS, Subsecond); +} + +/** + * @brief Get Alarm A Sub seconds value + * @rmtoll RCT_ALRMASSR SS LL_RTC_ALMA_GetSubSecond + * @param RTCx RTC Instance + * @retval If binary mode is none, Value between Min_Data=0x0 and Max_Data=0x7FFF + * else Value between Min_Data=0x0 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecond(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_SS)); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_ALARMB ALARMB + * @{ + */ + +/** + * @brief Enable Alarm B + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR ALRBE LL_RTC_ALMB_Enable + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_Enable(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_ALRBE); +} + +/** + * @brief Disable Alarm B + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR ALRBE LL_RTC_ALMB_Disable + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_Disable(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_ALRBE); +} + +/** + * @brief Specify the Alarm B masks. + * @rmtoll RTC_ALRMBR MSK4 LL_RTC_ALMB_SetMask\n + * RTC_ALRMBR MSK3 LL_RTC_ALMB_SetMask\n + * RTC_ALRMBR MSK2 LL_RTC_ALMB_SetMask\n + * RTC_ALRMBR MSK1 LL_RTC_ALMB_SetMask + * @param RTCx RTC Instance + * @param Mask This parameter can be a combination of the following values: + * @arg @ref LL_RTC_ALMB_MASK_NONE + * @arg @ref LL_RTC_ALMB_MASK_DATEWEEKDAY + * @arg @ref LL_RTC_ALMB_MASK_HOURS + * @arg @ref LL_RTC_ALMB_MASK_MINUTES + * @arg @ref LL_RTC_ALMB_MASK_SECONDS + * @arg @ref LL_RTC_ALMB_MASK_ALL + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_SetMask(RTC_TypeDef *RTCx, uint32_t Mask) +{ + MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1, Mask); +} + +/** + * @brief Get the Alarm B masks. + * @rmtoll RTC_ALRMBR MSK4 LL_RTC_ALMB_GetMask\n + * RTC_ALRMBR MSK3 LL_RTC_ALMB_GetMask\n + * RTC_ALRMBR MSK2 LL_RTC_ALMB_GetMask\n + * RTC_ALRMBR MSK1 LL_RTC_ALMB_GetMask + * @param RTCx RTC Instance + * @retval Returned value can be can be a combination of the following values: + * @arg @ref LL_RTC_ALMB_MASK_NONE + * @arg @ref LL_RTC_ALMB_MASK_DATEWEEKDAY + * @arg @ref LL_RTC_ALMB_MASK_HOURS + * @arg @ref LL_RTC_ALMB_MASK_MINUTES + * @arg @ref LL_RTC_ALMB_MASK_SECONDS + * @arg @ref LL_RTC_ALMB_MASK_ALL + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMask(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1)); +} + +/** + * @brief Enable AlarmB Week day selection (DU[3:0] represents the week day. DT[1:0] is do not care) + * @rmtoll RTC_ALRMBR WDSEL LL_RTC_ALMB_EnableWeekday + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_EnableWeekday(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->ALRMBR, RTC_ALRMBR_WDSEL); +} + +/** + * @brief Disable AlarmB Week day selection (DU[3:0] represents the date ) + * @rmtoll RTC_ALRMBR WDSEL LL_RTC_ALMB_DisableWeekday + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_DisableWeekday(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->ALRMBR, RTC_ALRMBR_WDSEL); +} + +/** + * @brief Set ALARM B Day in BCD format + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format + * @rmtoll RTC_ALRMBR DT LL_RTC_ALMB_SetDay\n + * RTC_ALRMBR DU LL_RTC_ALMB_SetDay + * @param RTCx RTC Instance + * @param Day Value between Min_Data=0x01 and Max_Data=0x31 + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_SetDay(RTC_TypeDef *RTCx, uint32_t Day) +{ + MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU), + (((Day & 0xF0U) << (RTC_ALRMBR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_ALRMBR_DU_Pos))); +} + +/** + * @brief Get ALARM B Day in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format + * @rmtoll RTC_ALRMBR DT LL_RTC_ALMB_GetDay\n + * RTC_ALRMBR DU LL_RTC_ALMB_GetDay + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x01 and Max_Data=0x31 + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetDay(const RTC_TypeDef *RTCx) +{ + return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU))) >> RTC_ALRMBR_DU_Pos); +} + +/** + * @brief Set ALARM B Weekday + * @rmtoll RTC_ALRMBR DU LL_RTC_ALMB_SetWeekDay + * @param RTCx RTC Instance + * @param WeekDay This parameter can be one of the following values: + * @arg @ref LL_RTC_WEEKDAY_MONDAY + * @arg @ref LL_RTC_WEEKDAY_TUESDAY + * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY + * @arg @ref LL_RTC_WEEKDAY_THURSDAY + * @arg @ref LL_RTC_WEEKDAY_FRIDAY + * @arg @ref LL_RTC_WEEKDAY_SATURDAY + * @arg @ref LL_RTC_WEEKDAY_SUNDAY + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) +{ + MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_DU, WeekDay << RTC_ALRMBR_DU_Pos); +} + +/** + * @brief Get ALARM B Weekday + * @rmtoll RTC_ALRMBR DU LL_RTC_ALMB_GetWeekDay + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_WEEKDAY_MONDAY + * @arg @ref LL_RTC_WEEKDAY_TUESDAY + * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY + * @arg @ref LL_RTC_WEEKDAY_THURSDAY + * @arg @ref LL_RTC_WEEKDAY_FRIDAY + * @arg @ref LL_RTC_WEEKDAY_SATURDAY + * @arg @ref LL_RTC_WEEKDAY_SUNDAY + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetWeekDay(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_DU) >> RTC_ALRMBR_DU_Pos); +} + +/** + * @brief Set ALARM B time format (AM/24-hour or PM notation) + * @rmtoll RTC_ALRMBR PM LL_RTC_ALMB_SetTimeFormat + * @param RTCx RTC Instance + * @param TimeFormat This parameter can be one of the following values: + * @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM + * @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat) +{ + MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_PM, TimeFormat); +} + +/** + * @brief Get ALARM B time format (AM or PM notation) + * @rmtoll RTC_ALRMBR PM LL_RTC_ALMB_GetTimeFormat + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM + * @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTimeFormat(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_PM)); +} + +/** + * @brief Set ALARM B Hours in BCD format + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD format + * @rmtoll RTC_ALRMBR HT LL_RTC_ALMB_SetHour\n + * RTC_ALRMBR HU LL_RTC_ALMB_SetHour + * @param RTCx RTC Instance + * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) +{ + MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU), + (((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos))); +} + +/** + * @brief Get ALARM B Hours in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format + * @rmtoll RTC_ALRMBR HT LL_RTC_ALMB_GetHour\n + * RTC_ALRMBR HU LL_RTC_ALMB_GetHour + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetHour(const RTC_TypeDef *RTCx) +{ + return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU))) >> RTC_ALRMBR_HU_Pos); +} + +/** + * @brief Set ALARM B Minutes in BCD format + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format + * @rmtoll RTC_ALRMBR MNT LL_RTC_ALMB_SetMinute\n + * RTC_ALRMBR MNU LL_RTC_ALMB_SetMinute + * @param RTCx RTC Instance + * @param Minutes between Min_Data=0x00 and Max_Data=0x59 + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) +{ + MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU), + (((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos))); +} + +/** + * @brief Get ALARM B Minutes in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format + * @rmtoll RTC_ALRMBR MNT LL_RTC_ALMB_GetMinute\n + * RTC_ALRMBR MNU LL_RTC_ALMB_GetMinute + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x59 + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMinute(const RTC_TypeDef *RTCx) +{ + return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU))) >> RTC_ALRMBR_MNU_Pos); +} + +/** + * @brief Set ALARM B Seconds in BCD format + * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format + * @rmtoll RTC_ALRMBR ST LL_RTC_ALMB_SetSecond\n + * RTC_ALRMBR SU LL_RTC_ALMB_SetSecond + * @param RTCx RTC Instance + * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59 + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) +{ + MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU), + (((Seconds & 0xF0U) << (RTC_ALRMBR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMBR_SU_Pos))); +} + +/** + * @brief Get ALARM B Seconds in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format + * @rmtoll RTC_ALRMBR ST LL_RTC_ALMB_GetSecond\n + * RTC_ALRMBR SU LL_RTC_ALMB_GetSecond + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x59 + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond(const RTC_TypeDef *RTCx) +{ + return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU))) >> RTC_ALRMBR_SU_Pos); +} + +/** + * @brief Set Alarm B Time (hour, minute and second) in BCD format + * @rmtoll RTC_ALRMBR PM LL_RTC_ALMB_ConfigTime\n + * RTC_ALRMBR HT LL_RTC_ALMB_ConfigTime\n + * RTC_ALRMBR HU LL_RTC_ALMB_ConfigTime\n + * RTC_ALRMBR MNT LL_RTC_ALMB_ConfigTime\n + * RTC_ALRMBR MNU LL_RTC_ALMB_ConfigTime\n + * RTC_ALRMBR ST LL_RTC_ALMB_ConfigTime\n + * RTC_ALRMBR SU LL_RTC_ALMB_ConfigTime + * @param RTCx RTC Instance + * @param Format12_24 This parameter can be one of the following values: + * @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM + * @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM + * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 + * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59 + * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59 + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_ConfigTime(RTC_TypeDef *RTCx, + uint32_t Format12_24, + uint32_t Hours, + uint32_t Minutes, + uint32_t Seconds) +{ + uint32_t temp; + + temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos)) | \ + (((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos)) | \ + (((Seconds & 0xF0U) << (RTC_ALRMBR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMBR_SU_Pos)); + + MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_PM | RTC_ALRMBR_HT | RTC_ALRMBR_HU | RTC_ALRMBR_MNT | RTC_ALRMBR_MNU | \ + RTC_ALRMBR_ST | RTC_ALRMBR_SU, temp); +} + +/** + * @brief Get Alarm B Time (hour, minute and second) in BCD format + * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND + * are available to get independently each parameter. + * @rmtoll RTC_ALRMBR HT LL_RTC_ALMB_GetTime\n + * RTC_ALRMBR HU LL_RTC_ALMB_GetTime\n + * RTC_ALRMBR MNT LL_RTC_ALMB_GetTime\n + * RTC_ALRMBR MNU LL_RTC_ALMB_GetTime\n + * RTC_ALRMBR ST LL_RTC_ALMB_GetTime\n + * RTC_ALRMBR SU LL_RTC_ALMB_GetTime + * @param RTCx RTC Instance + * @retval Combination of hours, minutes and seconds. + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTime(const RTC_TypeDef *RTCx) +{ + return (uint32_t)((LL_RTC_ALMB_GetHour(RTCx) << RTC_OFFSET_HOUR) | \ + (LL_RTC_ALMB_GetMinute(RTCx) << RTC_OFFSET_MINUTE) | LL_RTC_ALMB_GetSecond(RTCx)); +} + +/** + * @brief Set Alarm B Mask the most-significant bits starting at this bit + * @note This register can be written only when ALRBE is reset in RTC_CR register, + * or in initialization mode. + * @rmtoll RTC_ALRMBSSR MASKSS LL_RTC_ALMB_SetSubSecondMask + * @param RTCx RTC Instance + * @param Mask If binary mode is none, Value between Min_Data=0x0 and Max_Data=0xF + * else Value between Min_Data=0x0 and Max_Data=0x3F + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Mask) +{ + MODIFY_REG(RTCx->ALRMBSSR, RTC_ALRMBSSR_MASKSS, Mask << RTC_ALRMBSSR_MASKSS_Pos); +} + +/** + * @brief Get Alarm B Mask the most-significant bits starting at this bit + * @rmtoll RTC_ALRMBSSR MASKSS LL_RTC_ALMB_GetSubSecondMask + * @param RTCx RTC Instance + * @retval If binary mode is none, Value between Min_Data=0x0 and Max_Data=0xF + * else Value between Min_Data=0x0 and Max_Data=0x3F + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecondMask(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_MASKSS) >> RTC_ALRMBSSR_MASKSS_Pos); +} + +/** + * @brief Set Alarm B Binary mode auto clear + * @note This register can be written only when ALRBE is reset in RTC_CR register, + * or in initialization mode. + * @rmtoll RTC_ALRBBINR SSCLR LL_RTC_ALMB_SetBinAutoClr + * @param RTCx RTC Instance + * @param BinaryAutoClr This parameter can be one of the following values: + * @arg @ref LL_RTC_ALMB_SUBSECONDBIN_AUTOCLR_NO + * @arg @ref LL_RTC_ALMB_SUBSECONDBIN_AUTOCLR_YES + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_SetBinAutoClr(RTC_TypeDef *RTCx, uint32_t BinaryAutoClr) +{ + MODIFY_REG(RTCx->ALRMBSSR, RTC_ALRMBSSR_SSCLR, BinaryAutoClr); +} + +/** + * @brief Get Alarm B Binary mode auto clear + * @rmtoll RTC_ALRBBINR SSCLR LL_RTC_ALMB_GetBinAutoClr + * @param RTCx RTC Instance + * @retval It can be one of the following values: + * @arg @ref LL_RTC_ALMB_SUBSECONDBIN_AUTOCLR_NO + * @arg @ref LL_RTC_ALMB_SUBSECONDBIN_AUTOCLR_YES + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetBinAutoClr(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_SSCLR)); +} + +/** + * @brief Set Alarm B Sub seconds value + * @rmtoll RTC_ALRMBSSR SS LL_RTC_ALMB_SetSubSecond + * @param RTCx RTC Instance + * @param Subsecond If binary mode is none, Value between Min_Data=0x0 and Max_Data=0x7FFF + * else Value between Min_Data=0x0 and Max_Data=0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALMB_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsecond) +{ + MODIFY_REG(RTCx->ALRMBSSR, RTC_ALRMBSSR_SS, Subsecond); +} + +/** + * @brief Get Alarm B Sub seconds value + * @rmtoll RTC_ALRMBSSR SS LL_RTC_ALMB_GetSubSecond + * @param RTCx RTC Instance + * @retval If binary mode is none, Value between Min_Data=0x0 and Max_Data=0x7FFF + * else Value between Min_Data=0x0 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecond(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_SS)); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_Timestamp Timestamp + * @{ + */ + +#ifdef RTC_CR_TSE +/** + * @brief Enable Timestamp + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR TSE LL_RTC_TS_Enable + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TS_Enable(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_TSE); +} + +/** + * @brief Disable Timestamp + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR TSE LL_RTC_TS_Disable + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TS_Disable(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_TSE); +} +#endif /* RTC_CR_TSE */ + +#if defined(RTC_CR_TSEDGE) +/** + * @brief Set Time-stamp event active edge + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting + * @rmtoll RTC_CR TSEDGE LL_RTC_TS_SetActiveEdge + * @param RTCx RTC Instance + * @param Edge This parameter can be one of the following values: + * @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING + * @arg @ref LL_RTC_TIMESTAMP_EDGE_FALLING + * @retval None + */ +__STATIC_INLINE void LL_RTC_TS_SetActiveEdge(RTC_TypeDef *RTCx, uint32_t Edge) +{ + MODIFY_REG(RTCx->CR, RTC_CR_TSEDGE, Edge); +} + +/** + * @brief Get Time-stamp event active edge + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR TSEDGE LL_RTC_TS_GetActiveEdge + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING + * @arg @ref LL_RTC_TIMESTAMP_EDGE_FALLING + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetActiveEdge(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_TSEDGE)); +} +#endif /* RTC_CR_TSEDGE */ + +/** + * @brief Get Timestamp AM/PM notation (AM or 24-hour format) + * @rmtoll RTC_TSTR PM LL_RTC_TS_GetTimeFormat + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_TS_TIME_FORMAT_AM + * @arg @ref LL_RTC_TS_TIME_FORMAT_PM + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetTimeFormat(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_PM)); +} + +/** + * @brief Get Timestamp Hours in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format + * @rmtoll RTC_TSTR HT LL_RTC_TS_GetHour\n + * RTC_TSTR HU LL_RTC_TS_GetHour + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetHour(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_HT | RTC_TSTR_HU) >> RTC_TSTR_HU_Pos); +} + +/** + * @brief Get Timestamp Minutes in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format + * @rmtoll RTC_TSTR MNT LL_RTC_TS_GetMinute\n + * RTC_TSTR MNU LL_RTC_TS_GetMinute + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x59 + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetMinute(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_MNT | RTC_TSTR_MNU) >> RTC_TSTR_MNU_Pos); +} + +/** + * @brief Get Timestamp Seconds in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format + * @rmtoll RTC_TSTR ST LL_RTC_TS_GetSecond\n + * RTC_TSTR SU LL_RTC_TS_GetSecond + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x59 + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetSecond(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_ST | RTC_TSTR_SU)); +} + +/** + * @brief Get Timestamp time (hour, minute and second) in BCD format + * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND + * are available to get independently each parameter. + * @rmtoll RTC_TSTR HT LL_RTC_TS_GetTime\n + * RTC_TSTR HU LL_RTC_TS_GetTime\n + * RTC_TSTR MNT LL_RTC_TS_GetTime\n + * RTC_TSTR MNU LL_RTC_TS_GetTime\n + * RTC_TSTR ST LL_RTC_TS_GetTime\n + * RTC_TSTR SU LL_RTC_TS_GetTime + * @param RTCx RTC Instance + * @retval Combination of hours, minutes and seconds. + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetTime(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TSTR, + RTC_TSTR_HT | RTC_TSTR_HU | RTC_TSTR_MNT | RTC_TSTR_MNU | RTC_TSTR_ST | RTC_TSTR_SU)); +} + +/** + * @brief Get Timestamp Week day + * @rmtoll RTC_TSDR WDU LL_RTC_TS_GetWeekDay + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_WEEKDAY_MONDAY + * @arg @ref LL_RTC_WEEKDAY_TUESDAY + * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY + * @arg @ref LL_RTC_WEEKDAY_THURSDAY + * @arg @ref LL_RTC_WEEKDAY_FRIDAY + * @arg @ref LL_RTC_WEEKDAY_SATURDAY + * @arg @ref LL_RTC_WEEKDAY_SUNDAY + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetWeekDay(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU) >> RTC_TSDR_WDU_Pos); +} + +/** + * @brief Get Timestamp Month in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format + * @rmtoll RTC_TSDR MT LL_RTC_TS_GetMonth\n + * RTC_TSDR MU LL_RTC_TS_GetMonth + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_MONTH_JANUARY + * @arg @ref LL_RTC_MONTH_FEBRUARY + * @arg @ref LL_RTC_MONTH_MARCH + * @arg @ref LL_RTC_MONTH_APRIL + * @arg @ref LL_RTC_MONTH_MAY + * @arg @ref LL_RTC_MONTH_JUNE + * @arg @ref LL_RTC_MONTH_JULY + * @arg @ref LL_RTC_MONTH_AUGUST + * @arg @ref LL_RTC_MONTH_SEPTEMBER + * @arg @ref LL_RTC_MONTH_OCTOBER + * @arg @ref LL_RTC_MONTH_NOVEMBER + * @arg @ref LL_RTC_MONTH_DECEMBER + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetMonth(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_MT | RTC_TSDR_MU) >> RTC_TSDR_MU_Pos); +} + +/** + * @brief Get Timestamp Day in BCD format + * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format + * @rmtoll RTC_TSDR DT LL_RTC_TS_GetDay\n + * RTC_TSDR DU LL_RTC_TS_GetDay + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x01 and Max_Data=0x31 + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetDay(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_DT | RTC_TSDR_DU)); +} + +/** + * @brief Get Timestamp date (WeekDay, Day and Month) in BCD format + * @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_MONTH, + * and __LL_RTC_GET_DAY are available to get independently each parameter. + * @rmtoll RTC_TSDR WDU LL_RTC_TS_GetDate\n + * RTC_TSDR MT LL_RTC_TS_GetDate\n + * RTC_TSDR MU LL_RTC_TS_GetDate\n + * RTC_TSDR DT LL_RTC_TS_GetDate\n + * RTC_TSDR DU LL_RTC_TS_GetDate + * @param RTCx RTC Instance + * @retval Combination of Weekday, Day and Month + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetDate(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU | RTC_TSDR_MT | RTC_TSDR_MU | RTC_TSDR_DT | RTC_TSDR_DU)); +} + +/** + * @brief Get time-stamp sub second value + * @rmtoll RTC_TSDR SS LL_RTC_TS_GetSubSecond + * @param RTCx RTC Instance + * @retval If binary mode is none, Value between Min_Data=0x0 and Max_Data=0x7FFF + * else Value between Min_Data=0x0 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_RTC_TS_GetSubSecond(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->TSSSR, RTC_TSSSR_SS)); +} + +/** + * @brief Activate timestamp on tamper detection event + * @rmtoll RTC_CR TAMPTS LL_RTC_TS_EnableOnTamper + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TS_EnableOnTamper(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_TAMPTS); +} + +/** + * @brief Disable timestamp on tamper detection event + * @rmtoll RTC_CR TAMPTS LL_RTC_TS_DisableOnTamper + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TS_DisableOnTamper(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_TAMPTS); +} + + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_Tamper Tamper + * @{ + */ + +/** + * @brief Enable TAMPx input detection + * @rmtoll TAMP_CR1 TAMP1E LL_RTC_TAMPER_Enable\n + * TAMP_CR1 TAMP2E... LL_RTC_TAMPER_Enable\n + * @param RTCx RTC Instance + * @param Tamper This parameter can be a combination of the following values: + * @arg @ref RTC_LL_EC_TAMPER + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_Enable(const RTC_TypeDef *RTCx, uint32_t Tamper) +{ + UNUSED(RTCx); + SET_BIT(TAMP->CR1, Tamper); +} + +/** + * @brief Clear TAMPx input detection + * @rmtoll TAMP_CR1 TAMP1E LL_RTC_TAMPER_Disable\n + * TAMP_CR1 TAMP2E... LL_RTC_TAMPER_Disable + * @param RTCx RTC Instance + * @param Tamper This parameter can be a combination of the following values: + * @arg @ref RTC_LL_EC_TAMPER + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_Disable(const RTC_TypeDef *RTCx, uint32_t Tamper) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->CR1, Tamper); +} + +/** + * @brief Enable Tamper mask flag + * @note Associated Tamper IT must not enabled when tamper mask is set. + * @rmtoll TAMP_CR2 TAMP1MF LL_RTC_TAMPER_EnableMask\n + * TAMP_CR2 TAMP2MF... LL_RTC_TAMPER_EnableMask + * @param RTCx RTC Instance + * @param Mask This parameter can be a combination of the following values: + * @arg @ref RTC_LL_EC_TAMPER_MASK + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_EnableMask(const RTC_TypeDef *RTCx, uint32_t Mask) +{ + UNUSED(RTCx); + SET_BIT(TAMP->CR2, Mask); +} + +/** + * @brief Disable Tamper mask flag + * @rmtoll TAMP_CR2 TAMP1MF LL_RTC_TAMPER_DisableMask\n + * TAMP_CR2 TAMP2MF... LL_RTC_TAMPER_DisableMask + * @param RTCx RTC Instance + * @param Mask This parameter can be a combination of the following values: + * @arg @ref RTC_LL_EC_TAMPER_MASK + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_DisableMask(const RTC_TypeDef *RTCx, uint32_t Mask) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->CR2, Mask); +} + +/** + * @brief Enable backup register erase after Tamper event detection + * @rmtoll TAMP_CR2 TAMP1POM LL_RTC_TAMPER_EnableEraseBKP\n + * TAMP_CR2 TAMP2POM... LL_RTC_TAMPER_EnableEraseBKP + * @param RTCx RTC Instance + * @param Tamper This parameter can be a combination of the following values: + * @arg @ref RTC_LL_EC_TAMPER_NOERASE + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_EnableEraseBKP(const RTC_TypeDef *RTCx, uint32_t Tamper) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->CR2, Tamper); +} + +/** + * @brief Disable backup register erase after Tamper event detection + * @rmtoll TAMP_CR2 TAMP1POM LL_RTC_TAMPER_DisableEraseBKP\n + * TAMP_CR2 TAMP2POM... LL_RTC_TAMPER_DisableEraseBKP + * @param RTCx RTC Instance + * @param Tamper This parameter can be a combination of the following values: + * @arg @ref RTC_LL_EC_TAMPER_NOERASE + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_DisableEraseBKP(const RTC_TypeDef *RTCx, uint32_t Tamper) +{ + UNUSED(RTCx); + SET_BIT(TAMP->CR2, Tamper); +} + +/** + * @brief Disable RTC_TAMPx pull-up disable (Disable precharge of RTC_TAMPx pins) + * @rmtoll TAMP_FLTCR TAMPPUDIS LL_RTC_TAMPER_DisablePullUp + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_DisablePullUp(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + SET_BIT(TAMP->FLTCR, TAMP_FLTCR_TAMPPUDIS); +} + +/** + * @brief Enable RTC_TAMPx pull-up disable ( Precharge RTC_TAMPx pins before sampling) + * @rmtoll TAMP_FLTCR TAMPPUDIS LL_RTC_TAMPER_EnablePullUp + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_EnablePullUp(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->FLTCR, TAMP_FLTCR_TAMPPUDIS); +} + +/** + * @brief Set RTC_TAMPx precharge duration + * @rmtoll TAMP_FLTCR TAMPPRCH LL_RTC_TAMPER_SetPrecharge + * @param RTCx RTC Instance + * @param Duration This parameter can be one of the following values: + * @arg @ref LL_RTC_TAMPER_DURATION_1RTCCLK + * @arg @ref LL_RTC_TAMPER_DURATION_2RTCCLK + * @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK + * @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_SetPrecharge(const RTC_TypeDef *RTCx, uint32_t Duration) +{ + UNUSED(RTCx); + MODIFY_REG(TAMP->FLTCR, TAMP_FLTCR_TAMPPRCH, Duration); +} + +/** + * @brief Get RTC_TAMPx precharge duration + * @rmtoll TAMP_FLTCR TAMPPRCH LL_RTC_TAMPER_GetPrecharge + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_TAMPER_DURATION_1RTCCLK + * @arg @ref LL_RTC_TAMPER_DURATION_2RTCCLK + * @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK + * @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK + */ +__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPrecharge(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return (uint32_t)(READ_BIT(TAMP->FLTCR, TAMP_FLTCR_TAMPPRCH)); +} + +/** + * @brief Set RTC_TAMPx filter count + * @rmtoll TAMP_FLTCR TAMPFLT LL_RTC_TAMPER_SetFilterCount + * @param RTCx RTC Instance + * @param FilterCount This parameter can be one of the following values: + * @arg @ref LL_RTC_TAMPER_FILTER_DISABLE + * @arg @ref LL_RTC_TAMPER_FILTER_2SAMPLE + * @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE + * @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_SetFilterCount(const RTC_TypeDef *RTCx, uint32_t FilterCount) +{ + UNUSED(RTCx); + MODIFY_REG(TAMP->FLTCR, TAMP_FLTCR_TAMPFLT, FilterCount); +} + +/** + * @brief Get RTC_TAMPx filter count + * @rmtoll TAMP_FLTCR TAMPFLT LL_RTC_TAMPER_GetFilterCount + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_TAMPER_FILTER_DISABLE + * @arg @ref LL_RTC_TAMPER_FILTER_2SAMPLE + * @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE + * @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE + */ +__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetFilterCount(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return (uint32_t)(READ_BIT(TAMP->FLTCR, TAMP_FLTCR_TAMPFLT)); +} + +/** + * @brief Set Tamper sampling frequency + * @rmtoll TAMP_FLTCR TAMPFREQ LL_RTC_TAMPER_SetSamplingFreq + * @param RTCx RTC Instance + * @param SamplingFreq This parameter can be one of the following values: + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_32768 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_16384 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_8192 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_4096 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_2048 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_1024 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256 + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_SetSamplingFreq(const RTC_TypeDef *RTCx, uint32_t SamplingFreq) +{ + UNUSED(RTCx); + MODIFY_REG(TAMP->FLTCR, TAMP_FLTCR_TAMPFREQ, SamplingFreq); +} + +/** + * @brief Get Tamper sampling frequency + * @rmtoll TAMP_FLTCR TAMPFREQ LL_RTC_TAMPER_GetSamplingFreq + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_32768 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_16384 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_8192 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_4096 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_2048 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_1024 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512 + * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256 + */ +__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return (uint32_t)(READ_BIT(TAMP->FLTCR, TAMP_FLTCR_TAMPFREQ)); +} + +/** + * @brief Enable Active level for Tamper input + * @rmtoll TAMP_CR2 TAMP1TRG LL_RTC_TAMPER_EnableActiveLevel\n + * TAMP_CR2 TAMP2TRG LL_RTC_TAMPER_EnableActiveLevel\n + * TAMP_CR2 TAMPxTRG LL_RTC_TAMPER_EnableActiveLevel\n + * @param RTCx RTC Instance + * @param Tamper This parameter can be a combination of the following values: + * @arg @ref RTC_LL_EC_TAMPER_ACTIVELEVEL + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_EnableActiveLevel(const RTC_TypeDef *RTCx, uint32_t Tamper) +{ + UNUSED(RTCx); + SET_BIT(TAMP->CR2, Tamper); +} + +/** + * @brief Disable Active level for Tamper input + * @rmtoll TAMP_CR2 TAMP1TRG LL_RTC_TAMPER_DisableActiveLevel\n + * TAMP_CR2 TAMP2TRG LL_RTC_TAMPER_DisableActiveLevel\n + * TAMP_CR2 TAMPxTRG LL_RTC_TAMPER_DisableActiveLevel\n + * @param RTCx RTC Instance + * @param Tamper This parameter can be a combination of the following values: + * @arg @ref RTC_LL_EC_TAMPER_ACTIVELEVEL + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_DisableActiveLevel(const RTC_TypeDef *RTCx, uint32_t Tamper) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->CR2, Tamper); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_Internal_Tamper Internal Tamper + * @{ + */ + +/** + * @brief Enable internal tamper detection. + * @rmtoll TAMP_CR1 ITAMP1E LL_RTC_TAMPER_ITAMP_Enable\n + * TAMP_CR1 ITAMP2E LL_RTC_TAMPER_ITAMP_Enable\n + * TAMP_CR1 ITAMPxE.. LL_RTC_TAMPER_ITAMP_Enable\n + * @param RTCx RTC Instance + * @param InternalTamper This parameter can be a combination of the following values: + * @arg @ref RTC_LL_EC_INTERNAL + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_ITAMP_Enable(const RTC_TypeDef *RTCx, uint32_t InternalTamper) +{ + UNUSED(RTCx); + SET_BIT(TAMP->CR1, InternalTamper); +} + +/** + * @brief Disable internal tamper detection. + * @rmtoll TAMP_CR1 ITAMP1E LL_RTC_TAMPER_ITAMP_Disable\n + * TAMP_CR1 ITAMP2E LL_RTC_TAMPER_ITAMP_Disable\n + * TAMP_CR1 ITAMPxE LL_RTC_TAMPER_ITAMP_Disable\n + * @param RTCx RTC Instance + * @param InternalTamper This parameter can be a combination of the following values: + * @arg @ref RTC_LL_EC_INTERNAL + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_ITAMP_Disable(const RTC_TypeDef *RTCx, uint32_t InternalTamper) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->CR1, InternalTamper); +} + +/** + * @brief Enable backup register erase after internal tamper event detection + * @rmtoll TAMP_CR3 ITAMP3POM LL_RTC_TAMPER_ITAMP_EnableEraseBKP + * TAMP_CR3 ITAMP5POM... LL_RTC_TAMPER_ITAMP_EnableEraseBKP + * @param RTCx RTC Instance + * @param InternalTamper This parameter can be a combination of the following values: + * @arg @ref RTC_LL_EC_ITAMPER_NOERASE + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_ITAMP_EnableEraseBKP(const RTC_TypeDef *RTCx, uint32_t InternalTamper) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->CR3, InternalTamper); +} + +/** + * @brief Disable backup register erase after internal tamper event detection + * @rmtoll TAMP_CR3 ITAMP3POM LL_RTC_TAMPER_ITAMP_DisableEraseBKP + * TAMP_CR3 ITAMP5POM... LL_RTC_TAMPER_ITAMP_DisableEraseBKP + * @param RTCx RTC Instance + * @param InternalTamper This parameter can be a combination of the following values: + * @arg @ref RTC_LL_EC_ITAMPER_NOERASE + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_ITAMP_DisableEraseBKP(const RTC_TypeDef *RTCx, uint32_t InternalTamper) +{ + UNUSED(RTCx); + SET_BIT(TAMP->CR3, InternalTamper); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_Active_Tamper Active Tamper + * @{ + */ +/** + * @brief Enable tamper active mode. + * @rmtoll TAMP_ATCR1 TAMP1AM LL_RTC_TAMPER_ATAMP_EnableActiveMode\n + * @rmtoll TAMP_ATCR1 TAMP2AM LL_RTC_TAMPER_ATAMP_EnableActiveMode\n + * @rmtoll TAMP_ATCR1 TAMPxAM LL_RTC_TAMPER_ATAMP_EnableActiveMode\n + * @param Tamper to configure as active. This parameter can be a combination of the following values: + * @arg @ref RTC_LL_EC_ACTIVE_MODE + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_EnableActiveMode(uint32_t Tamper) +{ + SET_BIT(TAMP->ATCR1, Tamper); +} + +/** + * @brief Disable tamper active mode. + * @rmtoll TAMP_ATCR1 TAMP1AM LL_RTC_TAMPER_ATAMP_DisableActiveMode\n + * @rmtoll TAMP_ATCR1 TAMP2AM LL_RTC_TAMPER_ATAMP_DisableActiveMode\n + * @rmtoll TAMP_ATCR1 TAMPxAM LL_RTC_TAMPER_ATAMP_DisableActiveMode\n + * @param Tamper to configure as active. This parameter can be a combination of the following values: + * @arg @ref RTC_LL_EC_ACTIVE_MODE + * + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_DisableActiveMode(uint32_t Tamper) +{ + CLEAR_BIT(TAMP->ATCR1, Tamper); +} + +/** + * @brief Enable active tamper filter. + * @rmtoll TAMP_ATCR1 FLTEN LL_RTC_TAMPER_ATAMP_EnableFilter\n + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_EnableFilter(void) +{ + SET_BIT(TAMP->ATCR1, TAMP_ATCR1_FLTEN); +} + +/** + * @brief Disable active tamper filter. + * @rmtoll TAMP_ATCR1 FLTEN LL_RTC_TAMPER_ATAMP_DisableFilter\n + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_DisableFilter(void) +{ + CLEAR_BIT(TAMP->ATCR1, TAMP_ATCR1_FLTEN); +} + +/** + * @brief Set Active tamper output change period. + * @rmtoll TAMP_ATCR1 ATPER LL_RTC_TAMPER_ATAMP_SetOutputChangePeriod\n + * @param ActiveOutputChangePeriod This parameter can be a value from 0 to 7 + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_SetOutputChangePeriod(uint32_t ActiveOutputChangePeriod) +{ + MODIFY_REG(TAMP->ATCR1, TAMP_ATCR1_ATPER, (ActiveOutputChangePeriod << TAMP_ATCR1_ATPER_Pos)); +} + +/** + * @brief Get Active tamper output change period. + * @rmtoll TAMP_ATCR1 ATPER LL_RTC_TAMPER_ATAMP_GetOutputChangePeriod\n + * @retval Output change period. This parameter can be a value from 0 to 7. + */ +__STATIC_INLINE uint32_t LL_RTC_TAMPER_ATAMP_GetOutputChangePeriod(void) +{ + return (READ_BIT(TAMP->ATCR1, TAMP_ATCR1_ATPER) >> TAMP_ATCR1_ATPER_Pos); +} + +/** + * @brief Set Active tamper asynchronous prescaler clock selection. + * @rmtoll TAMP_ATCR1 ATCKSEL LL_RTC_TAMPER_ATAMP_SetAsyncPrescaler\n + * @param ActiveAsynvPrescaler Specifies the Active Tamper asynchronous Prescaler clock. + This parameter can be a value of the following values: + * @arg @ref RTC_LL_EC_ACTIVE_ASYNC_PRESCALER + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_SetAsyncPrescaler(uint32_t ActiveAsynvPrescaler) +{ + MODIFY_REG(TAMP->ATCR1, TAMP_ATCR1_ATCKSEL, ActiveAsynvPrescaler); +} + +/** + * @brief Get Active tamper asynchronous prescaler clock selection. + * @rmtoll TAMP_ATCR1 ATCKSEL LL_RTC_TAMPER_ATAMP_GetAsyncPrescaler\n + * @retval One of @arg @ref RTC_LL_EC_ACTIVE_ASYNC_PRESCALER + */ +__STATIC_INLINE uint32_t LL_RTC_TAMPER_ATAMP_GetAsyncPrescaler(void) +{ + return (READ_BIT(TAMP->ATCR1, TAMP_ATCR1_ATCKSEL)); +} + +/** + * @brief Enable active tamper output sharing. + * @rmtoll TAMP_ATCR1 ATOSHARE LL_RTC_TAMPER_ATAMP_EnableOutputSharing\n + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_EnableOutputSharing(void) +{ + SET_BIT(TAMP->ATCR1, TAMP_ATCR1_ATOSHARE); +} + +/** + * @brief Disable active tamper output sharing. + * @rmtoll TAMP_ATCR1 ATOSHARE LL_RTC_TAMPER_ATAMP_DisableOutputSharing\n + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_DisableOutputSharing(void) +{ + CLEAR_BIT(TAMP->ATCR1, TAMP_ATCR1_ATOSHARE); +} + +/** + * @brief Set Active tamper shared output selection. + * @rmtoll TAMP_ATCR2 ATOSELx LL_RTC_TAMPER_ATAMP_SetSharedOuputSelection\n + * @param OutputSelection Specifies all the output selection of the Active Tamper. + This parameter is a combinasation of the following values: + * One of @arg @ref RTC_LL_EC_ACTIVE_OUTPUT_SELECTION + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_SetSharedOuputSelection(uint32_t OutputSelection) +{ +#if (RTC_TAMP_NB == 3U) + MODIFY_REG(TAMP->ATCR2, (TAMP_ATCR2_ATOSEL1 | TAMP_ATCR2_ATOSEL2 | TAMP_ATCR2_ATOSEL3), OutputSelection); +#else + MODIFY_REG(TAMP->ATCR2, (TAMP_ATCR2_ATOSEL1 | TAMP_ATCR2_ATOSEL2 | TAMP_ATCR2_ATOSEL3 | TAMP_ATCR2_ATOSEL4 | \ + TAMP_ATCR2_ATOSEL5 | TAMP_ATCR2_ATOSEL6), \ + OutputSelection); +#endif /* RTC_TAMP_NB */ + +} + +/** + * @brief Get Active tamper shared output selection. + * @rmtoll TAMP_ATCR2 ATOSELx LL_RTC_TAMPER_ATAMP_GetSharedOuputSelection\n + * @retval A combination of @arg @ref RTC_LL_EC_ACTIVE_OUTPUT_SELECTION + */ +__STATIC_INLINE uint32_t LL_RTC_TAMPER_ATAMP_GetSharedOuputSelection(void) +{ +#if (RTC_TAMP_NB == 3U) + return (READ_BIT(TAMP->ATCR2, (TAMP_ATCR2_ATOSEL1 | TAMP_ATCR2_ATOSEL2 | TAMP_ATCR2_ATOSEL3))); +#else + return (READ_BIT(TAMP->ATCR2, (TAMP_ATCR2_ATOSEL1 | TAMP_ATCR2_ATOSEL2 | TAMP_ATCR2_ATOSEL3 | TAMP_ATCR2_ATOSEL4 | \ + TAMP_ATCR2_ATOSEL5 | TAMP_ATCR2_ATOSEL6))); +#endif /* RTC_TAMP_NB */ +} + +/** + * @brief Write active tamper seed. + * @rmtoll TAMP_ATSEEDR SEED LL_RTC_TAMPER_ATAMP_WriteSeed\n + * @param Seed + * @retval None + */ +__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_WriteSeed(uint32_t Seed) +{ + WRITE_REG(TAMP->ATSEEDR, Seed); +} + +/** + * @brief Get active tamper initialization status flag. + * @rmtoll TAMP_ATOR INITS LL_RTC_IsActiveFlag_ATAMP_INITS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ATAMP_INITS(void) +{ + return ((READ_BIT(TAMP->ATOR, TAMP_ATOR_INITS) == (TAMP_ATOR_INITS)) ? 1U : 0U); +} + +/** + * @brief Get active tamper seed running status flag. + * @rmtoll TAMP_ATOR SEEDF LL_RTC_IsActiveFlag_ATAMP_SEEDF + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ATAMP_SEEDF(void) +{ + return ((READ_BIT(TAMP->ATOR, TAMP_ATOR_SEEDF) == (TAMP_ATOR_SEEDF)) ? 1U : 0U); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_Wakeup Wakeup + * @{ + */ + +/** + * @brief Enable Wakeup timer + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR WUTE LL_RTC_WAKEUP_Enable + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_WAKEUP_Enable(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_WUTE); +} + +/** + * @brief Disable Wakeup timer + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR WUTE LL_RTC_WAKEUP_Disable + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_WAKEUP_Disable(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_WUTE); +} + +/** + * @brief Check if Wakeup timer is enabled or not + * @rmtoll RTC_CR WUTE LL_RTC_WAKEUP_IsEnabled + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_WAKEUP_IsEnabled(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) ? 1U : 0U); +} + +/** + * @brief Select Wakeup clock + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note Bit can be written only when RTC_CR WUTE bit = 0 and RTC_ICSR WUTWF bit = 1 + * @rmtoll RTC_CR WUCKSEL LL_RTC_WAKEUP_SetClock + * @param RTCx RTC Instance + * @param WakeupClock This parameter can be one of the following values: + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_16 + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_8 + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_4 + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_2 + * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE + * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT + * @retval None + */ +__STATIC_INLINE void LL_RTC_WAKEUP_SetClock(RTC_TypeDef *RTCx, uint32_t WakeupClock) +{ + MODIFY_REG(RTCx->CR, RTC_CR_WUCKSEL, WakeupClock); +} + +/** + * @brief Get Wakeup clock + * @rmtoll RTC_CR WUCKSEL LL_RTC_WAKEUP_GetClock + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_16 + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_8 + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_4 + * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_2 + * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE + * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT + */ +__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetClock(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_WUCKSEL)); +} + +/** + * @brief Set Wakeup auto-reload value + * @note Bit can be written only when WUTWF is set to 1 in RTC_ICSR + * @rmtoll RTC_WUTR WUT LL_RTC_WAKEUP_SetAutoReload + * @param RTCx RTC Instance + * @param Value Value between Min_Data=0x00 and Max_Data=0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_RTC_WAKEUP_SetAutoReload(RTC_TypeDef *RTCx, uint32_t Value) +{ + MODIFY_REG(RTCx->WUTR, RTC_WUTR_WUT, Value); +} + +/** + * @brief Get Wakeup auto-reload value + * @rmtoll RTC_WUTR WUT LL_RTC_WAKEUP_GetAutoReload + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->WUTR, RTC_WUTR_WUT)); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_Backup_Registers Backup_Registers + * @{ + */ + +/** + * @brief Writes a data in a specified Backup data register. + * @rmtoll TAMP_BKPxR BKP LL_RTC_BKP_SetRegister + * @param RTCx RTC Instance + * @param BackupRegister This parameter can be one of the following values: + * @arg @ref LL_RTC_BKP_DR0 + * @arg @ref LL_RTC_BKP_DR1 + * @arg @ref LL_RTC_BKP_DR2 + * @arg @ref LL_RTC_BKP_DR3 + * @arg @ref LL_RTC_BKP_DR4 + * @arg LL_RTC_BKP_DRx ... + * @param Data Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_RTC_BKP_SetRegister(const RTC_TypeDef *RTCx, uint32_t BackupRegister, uint32_t Data) +{ + __IO uint32_t tmp; + + UNUSED(RTCx); + + tmp = (uint32_t)(&(TAMP->BKP0R)); + tmp += (BackupRegister * 4U); + + /* Write the specified register */ + *(__IO uint32_t *)tmp = (uint32_t)Data; +} + +/** + * @brief Reads data from the specified RTC Backup data Register. + * @rmtoll TAMP_BKPxR BKP LL_RTC_BKP_GetRegister + * @param RTCx RTC Instance + * @param BackupRegister This parameter can be one of the following values: + * @arg @ref LL_RTC_BKP_DR0 + * @arg @ref LL_RTC_BKP_DR1 + * @arg @ref LL_RTC_BKP_DR2 + * @arg @ref LL_RTC_BKP_DR3 + * @arg @ref LL_RTC_BKP_DR4 + * @arg LL_RTC_BKP_DRx ... + * @retval Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_RTC_BKP_GetRegister(const RTC_TypeDef *RTCx, uint32_t BackupRegister) +{ + uint32_t tmp; + + UNUSED(RTCx); + + tmp = (uint32_t)(&(TAMP->BKP0R)); + tmp += (BackupRegister * 4U); + + /* Read the specified register */ + return (*(__IO uint32_t *)tmp); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_Calibration Calibration + * @{ + */ + +#if defined(RTC_CR_COE) +/** + * @brief Set Calibration output frequency (1 Hz or 512 Hz) + * @note Bits are write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR COE LL_RTC_CAL_SetOutputFreq\n + * RTC_CR COSEL LL_RTC_CAL_SetOutputFreq + * @param RTCx RTC Instance + * @param Frequency This parameter can be one of the following values: + * @arg @ref LL_RTC_CALIB_OUTPUT_NONE + * @arg @ref LL_RTC_CALIB_OUTPUT_1HZ + * @arg @ref LL_RTC_CALIB_OUTPUT_512HZ + * @retval None + */ +__STATIC_INLINE void LL_RTC_CAL_SetOutputFreq(RTC_TypeDef *RTCx, uint32_t Frequency) +{ + MODIFY_REG(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL, Frequency); +} + +/** + * @brief Get Calibration output frequency (1 Hz or 512 Hz) + * @rmtoll RTC_CR COE LL_RTC_CAL_GetOutputFreq\n + * RTC_CR COSEL LL_RTC_CAL_GetOutputFreq + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_CALIB_OUTPUT_NONE + * @arg @ref LL_RTC_CALIB_OUTPUT_1HZ + * @arg @ref LL_RTC_CALIB_OUTPUT_512HZ + */ +__STATIC_INLINE uint32_t LL_RTC_CAL_GetOutputFreq(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL)); +} +#endif /* RTC_CR_COE */ + +/** + * @brief Insert or not One RTCCLK pulse every 2exp11 pulses (frequency increased by 488.5 ppm) + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note Bit can be written only when RECALPF is set to 0 in RTC_ICSR + * @rmtoll RTC_CALR CALP LL_RTC_CAL_SetPulse + * @param RTCx RTC Instance + * @param Pulse This parameter can be one of the following values: + * @arg @ref LL_RTC_CALIB_INSERTPULSE_NONE + * @arg @ref LL_RTC_CALIB_INSERTPULSE_SET + * @retval None + */ +__STATIC_INLINE void LL_RTC_CAL_SetPulse(RTC_TypeDef *RTCx, uint32_t Pulse) +{ + MODIFY_REG(RTCx->CALR, RTC_CALR_CALP, Pulse); +} + +/** + * @brief Check if one RTCCLK has been inserted or not every 2exp11 pulses (frequency increased by 488.5 ppm) + * @rmtoll RTC_CALR CALP LL_RTC_CAL_IsPulseInserted + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_CAL_IsPulseInserted(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->CALR, RTC_CALR_CALP) == (RTC_CALR_CALP)) ? 1U : 0U); +} + +/** + * @brief Set the calibration cycle period + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note Bit can be written only when RECALPF is set to 0 in RTC_ICSR + * @rmtoll RTC_CALR CALW8 LL_RTC_CAL_SetPeriod\n + * RTC_CALR CALW16 LL_RTC_CAL_SetPeriod + * @param RTCx RTC Instance + * @param Period This parameter can be one of the following values: + * @arg @ref LL_RTC_CALIB_PERIOD_32SEC + * @arg @ref LL_RTC_CALIB_PERIOD_16SEC + * @arg @ref LL_RTC_CALIB_PERIOD_8SEC + * @retval None + */ +__STATIC_INLINE void LL_RTC_CAL_SetPeriod(RTC_TypeDef *RTCx, uint32_t Period) +{ + MODIFY_REG(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16, Period); +} + +/** + * @brief Get the calibration cycle period + * @rmtoll RTC_CALR CALW8 LL_RTC_CAL_GetPeriod\n + * RTC_CALR CALW16 LL_RTC_CAL_GetPeriod + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_CALIB_PERIOD_32SEC + * @arg @ref LL_RTC_CALIB_PERIOD_16SEC + * @arg @ref LL_RTC_CALIB_PERIOD_8SEC + */ +__STATIC_INLINE uint32_t LL_RTC_CAL_GetPeriod(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16)); +} + +/** + * @brief Set Calibration minus + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note Bit can be written only when RECALPF is set to 0 in RTC_ICSR + * @rmtoll RTC_CALR CALM LL_RTC_CAL_SetMinus + * @param RTCx RTC Instance + * @param CalibMinus Value between Min_Data=0x00 and Max_Data=0x1FF + * @retval None + */ +__STATIC_INLINE void LL_RTC_CAL_SetMinus(RTC_TypeDef *RTCx, uint32_t CalibMinus) +{ + MODIFY_REG(RTCx->CALR, RTC_CALR_CALM, CalibMinus); +} + +/** + * @brief Get Calibration minus + * @rmtoll RTC_CALR CALM LL_RTC_CAL_GetMinus + * @param RTCx RTC Instance + * @retval Value between Min_Data=0x00 and Max_Data= 0x1FF + */ +__STATIC_INLINE uint32_t LL_RTC_CAL_GetMinus(const RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALM)); +} + +/** + * @brief Enable Calibration Low Power + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note Bit can be written only when RECALPF is set to 0 + * @rmtoll RTC_CALR LPCAL LL_RTC_CAL_LowPower_Enable + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_CAL_LowPower_Enable(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CALR, RTC_CALR_LPCAL); +} + +/** + * @brief Disable Calibration Low Power + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note Bit can be written only when RECALPF is set to 0 + * @rmtoll RTC_CALR LPCAL LL_RTC_CAL_LowPower_Disable + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_CAL_LowPower_Disable(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CALR, RTC_CALR_LPCAL); +} + +/** + * @brief Check if Calibration Low Power is enabled or not + * @rmtoll RTC_CALR LPCAL LL_RTC_CAL_LowPower_IsEnabled + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_CAL_LowPower_IsEnabled(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->CALR, RTC_CALR_LPCAL) == (RTC_CALR_LPCAL)) ? 1U : 0U); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Get Recalibration pending Flag + * @rmtoll RTC_ICSR RECALPF LL_RTC_IsActiveFlag_RECALP + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->ICSR, RTC_ICSR_RECALPF) == (RTC_ICSR_RECALPF)) ? 1U : 0U); +} + +/** + * @brief Get Time-stamp overflow flag + * @rmtoll RTC_SR TSOVF LL_RTC_IsActiveFlag_TSOV + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->SR, RTC_SR_TSOVF) == (RTC_SR_TSOVF)) ? 1U : 0U); +} + +/** + * @brief Get Time-stamp flag + * @rmtoll RTC_SR TSF LL_RTC_IsActiveFlag_TS + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->SR, RTC_SR_TSF) == (RTC_SR_TSF)) ? 1U : 0U); +} + +/** + * @brief Get Wakeup timer flag + * @rmtoll RTC_SR WUTF LL_RTC_IsActiveFlag_WUT + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->SR, RTC_SR_WUTF) == (RTC_SR_WUTF)) ? 1U : 0U); +} + +/** + * @brief Get Alarm B flag + * @rmtoll RTC_SR ALRBF LL_RTC_IsActiveFlag_ALRB + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->SR, RTC_SR_ALRBF) == (RTC_SR_ALRBF)) ? 1U : 0U); +} + +/** + * @brief Get Alarm A flag + * @rmtoll RTC_SR ALRAF LL_RTC_IsActiveFlag_ALRA + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRA(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->SR, RTC_SR_ALRAF) == (RTC_SR_ALRAF)) ? 1U : 0U); +} + +/** + * @brief Get SSR Underflow flag + * @rmtoll RTC_SR SSRUF LL_RTC_IsActiveFlag_SSRU + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SSRU(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->SR, RTC_SR_SSRUF) == (RTC_SR_SSRUF)) ? 1U : 0U); +} + +/** + * @brief Clear Time-stamp overflow flag + * @rmtoll RTC_SCR CTSOVF LL_RTC_ClearFlag_TSOV + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_TSOV(RTC_TypeDef *RTCx) +{ + WRITE_REG(RTCx->SCR, RTC_SCR_CTSOVF); +} + +/** + * @brief Clear Time-stamp flag + * @rmtoll RTC_SCR CTSF LL_RTC_ClearFlag_TS + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_TS(RTC_TypeDef *RTCx) +{ + WRITE_REG(RTCx->SCR, RTC_SCR_CTSF); +} + +/** + * @brief Clear Wakeup timer flag + * @rmtoll RTC_SCR CWUTF LL_RTC_ClearFlag_WUT + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_WUT(RTC_TypeDef *RTCx) +{ + WRITE_REG(RTCx->SCR, RTC_SCR_CWUTF); +} + +/** + * @brief Clear Alarm B flag + * @rmtoll RTC_SCR CALRBF LL_RTC_ClearFlag_ALRB + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_ALRB(RTC_TypeDef *RTCx) +{ + WRITE_REG(RTCx->SCR, RTC_SCR_CALRBF); +} + +/** + * @brief Clear Alarm A flag + * @rmtoll RTC_SCR CALRAF LL_RTC_ClearFlag_ALRA + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_ALRA(RTC_TypeDef *RTCx) +{ + WRITE_REG(RTCx->SCR, RTC_SCR_CALRAF); +} + +/** + * @brief Clear SSR Underflow flag + * @rmtoll RTC_SCR CSSRUF LL_RTC_ClearFlag_SSRU + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_SSRU(RTC_TypeDef *RTCx) +{ + WRITE_REG(RTCx->SCR, RTC_SCR_CSSRUF); +} + +/** + * @brief Get Initialization flag + * @rmtoll RTC_ICSR INITF LL_RTC_IsActiveFlag_INIT + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->ICSR, RTC_ICSR_INITF) == (RTC_ICSR_INITF)) ? 1U : 0U); +} + +/** + * @brief Get Registers synchronization flag + * @rmtoll RTC_ICSR RSF LL_RTC_IsActiveFlag_RS + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->ICSR, RTC_ICSR_RSF) == (RTC_ICSR_RSF)) ? 1U : 0U); +} + +/** + * @brief Clear Registers synchronization flag + * @rmtoll RTC_ICSR RSF LL_RTC_ClearFlag_RS + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_RS(RTC_TypeDef *RTCx) +{ + WRITE_REG(RTCx->ICSR, (~((RTC_ICSR_RSF | RTC_ICSR_INIT) & 0x000000FFU) | (RTCx->ICSR & RTC_ICSR_INIT))); +} + +/** + * @brief Get Initialization status flag + * @rmtoll RTC_ICSR INITS LL_RTC_IsActiveFlag_INITS + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->ICSR, RTC_ICSR_INITS) == (RTC_ICSR_INITS)) ? 1U : 0U); +} + +/** + * @brief Get Shift operation pending flag + * @rmtoll RTC_ICSR SHPF LL_RTC_IsActiveFlag_SHP + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->ICSR, RTC_ICSR_SHPF) == (RTC_ICSR_SHPF)) ? 1U : 0U); +} + +/** + * @brief Get Wakeup timer write flag + * @rmtoll RTC_ICSR WUTWF LL_RTC_IsActiveFlag_WUTW + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->ICSR, RTC_ICSR_WUTWF) == (RTC_ICSR_WUTWF)) ? 1U : 0U); +} + +/** + * @brief Get Alarm A masked flag. + * @rmtoll RTC_MISR ALRAMF LL_RTC_IsActiveFlag_ALRAM + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAM(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->MISR, RTC_MISR_ALRAMF) == (RTC_MISR_ALRAMF)) ? 1U : 0U); +} + +/** + * @brief Get SSR Underflow masked flag. + * @rmtoll RTC_MISR SSRUMF LL_RTC_IsActiveFlag_SSRUM + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SSRUM(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->MISR, RTC_MISR_SSRUMF) == (RTC_MISR_SSRUMF)) ? 1U : 0U); +} + +/** + * @brief Get Alarm B masked flag. + * @rmtoll RTC_MISR ALRBMF LL_RTC_IsActiveFlag_ALRBM + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBM(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->MISR, RTC_MISR_ALRBMF) == (RTC_MISR_ALRBMF)) ? 1U : 0U); +} + +/** + * @brief Get Wakeup timer masked flag. + * @rmtoll RTC_MISR WUTMF LL_RTC_IsActiveFlag_WUTM + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTM(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->MISR, RTC_MISR_WUTMF) == (RTC_MISR_WUTMF)) ? 1U : 0U); +} + +/** + * @brief Get Time-stamp masked flag. + * @rmtoll RTC_MISR TSMF LL_RTC_IsActiveFlag_TSM + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSM(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->MISR, RTC_MISR_TSMF) == (RTC_MISR_TSMF)) ? 1U : 0U); +} + +/** + * @brief Get Time-stamp overflow masked flag. + * @rmtoll RTC_MISR TSOVMF LL_RTC_IsActiveFlag_TSOVM + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOVM(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->MISR, RTC_MISR_TSOVMF) == (RTC_MISR_TSOVMF)) ? 1U : 0U); +} + +/** + * @brief Get tamper 1 detection flag. + * @rmtoll TAMP_SR TAMP1F LL_RTC_IsActiveFlag_TAMP1 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP1F) == (TAMP_SR_TAMP1F)) ? 1U : 0U); +} + +/** + * @brief Get tamper 2 detection flag. + * @rmtoll TAMP_SR TAMP2F LL_RTC_IsActiveFlag_TAMP2 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP2F) == (TAMP_SR_TAMP2F)) ? 1U : 0U); +} + +/** + * @brief Get tamper 3 detection flag. + * @rmtoll TAMP_SR TAMP3F LL_RTC_IsActiveFlag_TAMP3 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP3F) == (TAMP_SR_TAMP3F)) ? 1U : 0U); +} + +#ifdef TAMP_SR_TAMP4F +/** + * @brief Get tamper 4 detection flag. + * @rmtoll TAMP_SR TAMP4F LL_RTC_IsActiveFlag_TAMP4 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP4(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP4F) == (TAMP_SR_TAMP4F)) ? 1U : 0U); +} + +/** + * @brief Get tamper 5 detection flag. + * @rmtoll TAMP_SR TAMP5F LL_RTC_IsActiveFlag_TAMP5 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP5(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP5F) == (TAMP_SR_TAMP5F)) ? 1U : 0U); +} + +/** + * @brief Get tamper 6 detection flag. + * @rmtoll TAMP_SR TAMP6F LL_RTC_IsActiveFlag_TAMP6 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP6(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP6F) == (TAMP_SR_TAMP6F)) ? 1U : 0U); +} +#endif /* TAMP_SR_TAMP4F */ + +/** + * @brief Get internal tamper 3 detection flag. + * @rmtoll TAMP_SR ITAMP3F LL_RTC_IsActiveFlag_ITAMP3 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP3(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP3F) == (TAMP_SR_ITAMP3F)) ? 1U : 0U); +} + + +/** + * @brief Get internal tamper 5 detection flag. + * @rmtoll TAMP_SR ITAMP5F LL_RTC_IsActiveFlag_ITAMP5 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP5(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP5F) == (TAMP_SR_ITAMP5F)) ? 1U : 0U); +} + +/** + * @brief Get internal tamper 6 detection flag. + * @rmtoll TAMP_SR ITAMP6F LL_RTC_IsActiveFlag_ITAMP6 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP6(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP6F) == (TAMP_SR_ITAMP6F)) ? 1U : 0U); +} + +/** + * @brief Get internal tamper 7 detection flag. + * @rmtoll TAMP_SR ITAMP7F LL_RTC_IsActiveFlag_ITAMP7 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP7(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP7F) == (TAMP_SR_ITAMP7F)) ? 1U : 0U); +} + +/** + * @brief Get internal tamper 8 detection flag. + * @rmtoll TAMP_SR ITAMP8F LL_RTC_IsActiveFlag_ITAMP8 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP8(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP8F) == (TAMP_SR_ITAMP8F)) ? 1U : 0U); +} + +/** + * @brief Get internal tamper 9 detection flag. + * @rmtoll TAMP_SR ITAMP9F LL_RTC_IsActiveFlag_ITAMP9 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP9(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP9F) == (TAMP_SR_ITAMP9F)) ? 1U : 0U); +} + +/** + * @brief Get internal tamper 11 detection flag. + * @rmtoll TAMP_SR ITAMP11F LL_RTC_IsActiveFlag_ITAMP11 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP11(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP11F) == (TAMP_SR_ITAMP11F)) ? 1U : 0U); +} + +/** + * @brief Get internal tamper 12 detection flag. + * @rmtoll TAMP_SR ITAMP12F LL_RTC_IsActiveFlag_ITAMP12 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP12(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP12F) == (TAMP_SR_ITAMP12F)) ? 1U : 0U); +} + +/** + * @brief Get internal tamper 13 detection flag. + * @rmtoll TAMP_SR ITAMP13F LL_RTC_IsActiveFlag_ITAMP13 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP13(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP13F) == (TAMP_SR_ITAMP13F)) ? 1U : 0U); +} + +/** + * @brief Get tamper 1 interrupt masked flag. + * @rmtoll TAMP_MISR TAMP1MF LL_RTC_IsActiveFlag_TAMP1M + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1M(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP1MF) == (TAMP_MISR_TAMP1MF)) ? 1U : 0U); +} + +/** + * @brief Get tamper 2 interrupt masked flag. + * @rmtoll TAMP_MISR TAMP2MF LL_RTC_IsActiveFlag_TAMP2M + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2M(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP2MF) == (TAMP_MISR_TAMP2MF)) ? 1U : 0U); +} + +/** + * @brief Get tamper 3 interrupt masked flag. + * @rmtoll TAMP_MISR TAMP3MF LL_RTC_IsActiveFlag_TAMP3M + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3M(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP3MF) == (TAMP_MISR_TAMP3MF)) ? 1U : 0U); +} + +#ifdef TAMP_MISR_TAMP4MF +/** + * @brief Get tamper 4 interrupt masked flag. + * @rmtoll TAMP_MISR TAMP4MF LL_RTC_IsActiveFlag_TAMP4M + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP4M(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP4MF) == (TAMP_MISR_TAMP4MF)) ? 1U : 0U); +} + +/** + * @brief Get tamper 5 interrupt masked flag. + * @rmtoll TAMP_MISR TAMP5MF LL_RTC_IsActiveFlag_TAMP5M + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP5M(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP5MF) == (TAMP_MISR_TAMP5MF)) ? 1U : 0U); +} + +/** + * @brief Get tamper 6 interrupt masked flag. + * @rmtoll TAMP_MISR TAMP6MF LL_RTC_IsActiveFlag_TAMP6M + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP6M(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP6MF) == (TAMP_MISR_TAMP6MF)) ? 1U : 0U); +} +#endif /* TAMP_MISR_TAMP4MF */ + +/** + * @brief Get internal tamper 3 interrupt masked flag. + * @rmtoll TAMP_MISR ITAMP3MF LL_RTC_IsActiveFlag_ITAMP3M + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP3M(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP3MF) == (TAMP_MISR_ITAMP3MF)) ? 1U : 0U); +} + +/** + * @brief Get internal tamper 5 interrupt masked flag. + * @rmtoll TAMP_MISR ITAMP5MF LL_RTC_IsActiveFlag_ITAMP5M + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP5M(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP5MF) == (TAMP_MISR_ITAMP5MF)) ? 1U : 0U); +} + +/** + * @brief Get internal tamper 6 interrupt masked flag. + * @rmtoll TAMP_MISR ITAMP6MF LL_RTC_IsActiveFlag_ITAMP6M + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP6M(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP6MF) == (TAMP_MISR_ITAMP6MF)) ? 1U : 0U); +} + +/** + * @brief Get internal tamper 7 interrupt masked flag. + * @rmtoll TAMP_MISR ITAMP7MF LL_RTC_IsActiveFlag_ITAMP7M + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP7M(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP7MF) == (TAMP_MISR_ITAMP7MF)) ? 1U : 0U); +} + +/** + * @brief Get internal tamper 8 interrupt masked flag. + * @rmtoll TAMP_MISR ITAMP8MF LL_RTC_IsActiveFlag_ITAMP8M + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP8M(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP8MF) == (TAMP_MISR_ITAMP8MF)) ? 1U : 0U); +} + +/** + * @brief Get internal tamper 9 interrupt masked flag. + * @rmtoll TAMP_MISR ITAMP9MF LL_RTC_IsActiveFlag_ITAMP9M + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP9M(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP9MF) == (TAMP_MISR_ITAMP9MF)) ? 1U : 0U); +} + +/** + * @brief Get internal tamper 11 interrupt masked flag. + * @rmtoll TAMP_MISR ITAMP11MF LL_RTC_IsActiveFlag_ITAMP11M + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP11M(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP11MF) == (TAMP_MISR_ITAMP11MF)) ? 1U : 0U); +} + +/** + * @brief Get internal tamper 12 interrupt masked flag. + * @rmtoll TAMP_MISR ITAMP12MF LL_RTC_IsActiveFlag_ITAMP12M + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP12M(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP12MF) == (TAMP_MISR_ITAMP12MF)) ? 1U : 0U); +} + +/** + * @brief Get internal tamper 13 interrupt masked flag. + * @rmtoll TAMP_MISR ITAMP13MF LL_RTC_IsActiveFlag_ITAMP13M + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP13M(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP13MF) == (TAMP_MISR_ITAMP13MF)) ? 1U : 0U); +} + +/** + * @brief Clear tamper 1 detection flag. + * @rmtoll TAMP_SCR CTAMP1F LL_RTC_ClearFlag_TAMP1 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_TAMP1(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + WRITE_REG(TAMP->SCR, TAMP_SCR_CTAMP1F); +} + +/** + * @brief Clear tamper 2 detection flag. + * @rmtoll TAMP_SCR CTAMP2F LL_RTC_ClearFlag_TAMP2 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_TAMP2(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + WRITE_REG(TAMP->SCR, TAMP_SCR_CTAMP2F); +} + +/** + * @brief Clear tamper 3 detection flag. + * @rmtoll TAMP_SCR CTAMP3F LL_RTC_ClearFlag_TAMP3 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_TAMP3(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + WRITE_REG(TAMP->SCR, TAMP_SCR_CTAMP3F); +} + +#ifdef TAMP_SCR_CTAMP4F +/** + * @brief Clear tamper 4 detection flag. + * @rmtoll TAMP_SCR CTAMP4F LL_RTC_ClearFlag_TAMP4 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_TAMP4(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + WRITE_REG(TAMP->SCR, TAMP_SCR_CTAMP4F); +} + +/** + * @brief Clear tamper 5 detection flag. + * @rmtoll TAMP_SCR CTAMP5F LL_RTC_ClearFlag_TAMP5 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_TAMP5(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + WRITE_REG(TAMP->SCR, TAMP_SCR_CTAMP5F); +} + +/** + * @brief Clear tamper 6 detection flag. + * @rmtoll TAMP_SCR CTAMP6F LL_RTC_ClearFlag_TAMP6 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_TAMP6(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + WRITE_REG(TAMP->SCR, TAMP_SCR_CTAMP6F); +} +#endif /* TAMP_SCR_CTAMP4F */ + +/** + * @brief Clear internal tamper 3 detection flag. + * @rmtoll TAMP_SCR CITAMP3F LL_RTC_ClearFlag_ITAMP3 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP3(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + WRITE_REG(TAMP->SCR, TAMP_SCR_CITAMP3F); +} + +/** + * @brief Clear internal tamper 5 detection flag. + * @rmtoll TAMP_SCR CITAMP5F LL_RTC_ClearFlag_ITAMP5 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP5(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + WRITE_REG(TAMP->SCR, TAMP_SCR_CITAMP5F); +} + +/** + * @brief Clear internal tamper 6 detection flag. + * @rmtoll TAMP_SCR CITAMP6F LL_RTC_ClearFlag_ITAMP6 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP6(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + WRITE_REG(TAMP->SCR, TAMP_SCR_CITAMP6F); +} + +/** + * @brief Clear internal tamper 7 detection flag. + * @rmtoll TAMP_SCR CITAMP7F LL_RTC_ClearFlag_ITAMP7 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP7(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + WRITE_REG(TAMP->SCR, TAMP_SCR_CITAMP7F); +} + +/** + * @brief Clear internal tamper 8 detection flag. + * @rmtoll TAMP_SCR CITAMP8F LL_RTC_ClearFlag_ITAMP8 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP8(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + WRITE_REG(TAMP->SCR, TAMP_SCR_CITAMP8F); +} + +/** + * @brief Clear internal tamper 9 detection flag. + * @rmtoll TAMP_SCR CITAMP9F LL_RTC_ClearFlag_ITAMP9 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP9(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + WRITE_REG(TAMP->SCR, TAMP_SCR_CITAMP9F); +} + +/** + * @brief Clear internal tamper 11 detection flag. + * @rmtoll TAMP_SCR CITAMP11F LL_RTC_ClearFlag_ITAMP11 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP11(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + WRITE_REG(TAMP->SCR, TAMP_SCR_CITAMP11F); +} + +/** + * @brief Clear internal tamper 12 detection flag. + * @rmtoll TAMP_SCR CITAMP12F LL_RTC_ClearFlag_ITAMP12 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP12(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + WRITE_REG(TAMP->SCR, TAMP_SCR_CITAMP12F); +} + +/** + * @brief Clear internal tamper 13 detection flag. + * @rmtoll TAMP_SCR CITAMP13F LL_RTC_ClearFlag_ITAMP13 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP13(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + WRITE_REG(TAMP->SCR, TAMP_SCR_CITAMP13F); +} + +/** + * @} + */ + +#if defined(RTC_SECCFGR_SEC) +/** @defgroup RTC_LL_EF_SECURITY SECURITY_Management + * @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Set RTC secure level. + * @note secure features are relevant if LL_RTC_SECURE_FULL_NO. + * @rmtoll RTC_SECCFGR SEC LL_RTC_SetRtcSecure + * @rmtoll RTC_SECCFGR INITSEC LL_RTC_SetRtcSecure + * @rmtoll RTC_SECCFGR CALSEC LL_RTC_SetRtcSecure + * @rmtoll RTC_SECCFGR TSSEC LL_RTC_SetRtcSecure + * @rmtoll RTC_SECCFGR WUTSEC LL_RTC_SetRtcSecure + * @rmtoll RTC_SECCFGR ALRASEC LL_RTC_SetRtcSecure + * @rmtoll RTC_SECCFGR ALRBSEC LL_RTC_SetRtcSecure + * @param RTCx RTC Instance + * @param rtcSecure This parameter can be a combination of the following values: + * @arg @ref LL_RTC_SECURE_FULL_YES + * @arg @ref LL_RTC_SECURE_FULL_NO + * @arg @ref LL_RTC_SECURE_FEATURE_INIT + * @arg @ref LL_RTC_SECURE_FEATURE_CAL + * @arg @ref LL_RTC_SECURE_FEATURE_TS + * @arg @ref LL_RTC_SECURE_FEATURE_WUT + * @arg @ref LL_RTC_SECURE_FEATURE_ALRA + * @arg @ref LL_RTC_SECURE_FEATURE_ALRB + + * @retval None + */ +__STATIC_INLINE void LL_RTC_SetRtcSecure(RTC_TypeDef *RTCx, uint32_t rtcSecure) +{ + MODIFY_REG(RTCx->SECCFGR, RTC_SECCFGR_SEC | RTC_SECCFGR_INITSEC | RTC_SECCFGR_CALSEC | RTC_SECCFGR_TSSEC | \ + RTC_SECCFGR_WUTSEC | RTC_SECCFGR_ALRASEC | RTC_SECCFGR_ALRBSEC, rtcSecure); +} +#endif /* #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/** + * @brief Get RTC secure level. + * @note Secure features is relevant if LL_RTC_SECURE_FULL_NO. + * @rmtoll RTC_SECCFGR SEC LL_RTC_SetRtcSecure + * @rmtoll RTC_SECCFGR INISEC LL_RTC_SetRtcSecure + * @rmtoll RTC_SECCFGR CALSEC LL_RTC_SetRtcSecure + * @rmtoll RTC_SECCFGR TSSEC LL_RTC_SetRtcSecure + * @rmtoll RTC_SECCFGR WUTSEC LL_RTC_SetRtcSecure + * @rmtoll RTC_SECCFGR ALRASEC LL_RTC_SetRtcSecure + * @rmtoll RTC_SECCFGR ALRBSEC LL_RTC_SetRtcSecure + * @param RTCx RTC Instance + * @retval Combination of the following values: + * @arg @ref LL_RTC_SECURE_FULL_YES + * @arg @ref LL_RTC_SECURE_FULL_NO + * @arg @ref LL_RTC_SECURE_FEATURE_INIT + * @arg @ref LL_RTC_SECURE_FEATURE_CAL + * @arg @ref LL_RTC_SECURE_FEATURE_TS + * @arg @ref LL_RTC_SECURE_FEATURE_WUT + * @arg @ref LL_RTC_SECURE_FEATURE_ALRA + * @arg @ref LL_RTC_SECURE_FEATURE_ALRB + */ +__STATIC_INLINE uint32_t LL_RTC_GetRtcSecure(const RTC_TypeDef *RTCx) +{ + return READ_BIT(RTCx->SECCFGR, RTC_SECCFGR_SEC | RTC_SECCFGR_INITSEC | RTC_SECCFGR_CALSEC | RTC_SECCFGR_TSSEC | \ + RTC_SECCFGR_WUTSEC | RTC_SECCFGR_ALRASEC | RTC_SECCFGR_ALRBSEC); +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Set TAMPER secure level. + * @rmtoll TAMP_SECCFGR TAMPSEC LL_RTC_SetTampSecure + * @param RTCx RTC Instance + * @param tampSecure This parameter can be one of the following values: + * @arg @ref LL_TAMP_SECURE_FULL_YES + * @arg @ref LL_TAMP_SECURE_FULL_NO + * @retval None + */ +__STATIC_INLINE void LL_RTC_SetTampSecure(const RTC_TypeDef *RTCx, uint32_t tampSecure) +{ + UNUSED(RTCx); + MODIFY_REG(TAMP->SECCFGR, TAMP_SECCFGR_TAMPSEC, tampSecure); +} +#endif /* #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/** + * @brief Get TAMPER secure level. + * @rmtoll TAMP_SECCFGR TAMPSEC LL_RTC_GetTampSecure + * @param RTCx RTC Instance + * @retval This parameter can be one of the following values: + * @arg @ref LL_TAMP_SECURE_FULL_YES + * @arg @ref LL_TAMP_SECURE_FULL_NO + */ +__STATIC_INLINE uint32_t LL_RTC_GetTampSecure(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return READ_BIT(TAMP->SECCFGR, TAMP_SECCFGR_TAMPSEC); +} + +/** + * @} + */ +#endif /* RTC_SECCFGR_SEC */ + +#if defined(RTC_PRIVCFGR_PRIV) +/** @defgroup RTC_LL_EF_PRIVILEGE PRIVILEGE_Management + * @{ + */ + +/** + * @brief Set RTC privilege level. + * @note Privilege features are relevant if LL_RTC_PRIVILEGE_FULL_NO. + * @rmtoll RTC_PRIVCFGR PRIV LL_RTC_SetRtcPrivilege + * @rmtoll RTC_PRIVCFGR INITPRIV LL_RTC_SetRtcPrivilege + * @rmtoll RTC_PRIVCFGR CALPRIV LL_RTC_SetRtcPrivilege + * @rmtoll RTC_PRIVCFGR TSPRIV LL_RTC_SetRtcPrivilege + * @rmtoll RTC_PRIVCFGR WUTPRIV LL_RTC_SetRtcPrivilege + * @rmtoll RTC_PRIVCFGR ALRAPRIV LL_RTC_SetRtcPrivilege + * @rmtoll RTC_PRIVCFGR ALRBPRIV LL_RTC_SetRtcPrivilege + * @param RTCx RTC Instance + * @param rtcPrivilege This parameter can be a combination of the following values: + * @arg @ref LL_RTC_PRIVILEGE_FULL_YES + * @arg @ref LL_RTC_PRIVILEGE_FULL_NO + * @arg @ref LL_RTC_PRIVILEGE_FEATURE_INIT + * @arg @ref LL_RTC_PRIVILEGE_FEATURE_CAL + * @arg @ref LL_RTC_PRIVILEGE_FEATURE_TS + * @arg @ref LL_RTC_PRIVILEGE_FEATURE_WUT + * @arg @ref LL_RTC_PRIVILEGE_FEATURE_ALRA + * @arg @ref LL_RTC_PRIVILEGE_FEATURE_ALRB + * @retval None + */ +__STATIC_INLINE void LL_RTC_SetRtcPrivilege(RTC_TypeDef *RTCx, uint32_t rtcPrivilege) +{ + MODIFY_REG(RTCx->PRIVCFGR, RTC_PRIVCFGR_PRIV | RTC_PRIVCFGR_INITPRIV | RTC_PRIVCFGR_CALPRIV | RTC_PRIVCFGR_TSPRIV | \ + RTC_PRIVCFGR_WUTPRIV | RTC_PRIVCFGR_ALRAPRIV | RTC_PRIVCFGR_ALRBPRIV, rtcPrivilege); +} + +/** + * @brief Get RTC privilege level. + * @note Privilege features are relevant if LL_RTC_PRIVILEGE_FULL_NO. + * @rmtoll RTC_PRIVCFGR PRIV LL_RTC_SetRtcPrivilege + * @rmtoll RTC_PRIVCFGR INITPRIV LL_RTC_SetRtcPrivilege + * @rmtoll RTC_PRIVCFGR CALPRIV LL_RTC_SetRtcPrivilege + * @rmtoll RTC_PRIVCFGR TSPRIV LL_RTC_SetRtcPrivilege + * @rmtoll RTC_PRIVCFGR WUTPRIV LL_RTC_SetRtcPrivilege + * @rmtoll RTC_PRIVCFGR ALRAPRIV LL_RTC_SetRtcPrivilege + * @rmtoll RTC_PRIVCFGR ALRBPRIV LL_RTC_SetRtcPrivilege + * @param RTCx RTC Instance + * @retval Combination of the following values: + * @arg @ref LL_RTC_PRIVILEGE_FULL_YES + * @arg @ref LL_RTC_PRIVILEGE_FULL_NO + * @arg @ref LL_RTC_PRIVILEGE_FEATURE_INIT + * @arg @ref LL_RTC_PRIVILEGE_FEATURE_CAL + * @arg @ref LL_RTC_PRIVILEGE_FEATURE_TS + * @arg @ref LL_RTC_PRIVILEGE_FEATURE_WUT + * @arg @ref LL_RTC_PRIVILEGE_FEATURE_ALRA + * @arg @ref LL_RTC_PRIVILEGE_FEATURE_ALRB + */ +__STATIC_INLINE uint32_t LL_RTC_GetRtcPrivilege(const RTC_TypeDef *RTCx) +{ + return READ_BIT(RTCx->PRIVCFGR, RTC_PRIVCFGR_PRIV | RTC_PRIVCFGR_INITPRIV | RTC_PRIVCFGR_CALPRIV | \ + RTC_PRIVCFGR_TSPRIV | RTC_PRIVCFGR_WUTPRIV | RTC_PRIVCFGR_ALRAPRIV | \ + RTC_PRIVCFGR_ALRBPRIV); +} + +/** + * @brief Set TAMPER privilege level. + * @rmtoll TAMP_PRIVCFGR TAMPPRIV LL_RTC_SetTampPrivilege + * @param RTCx RTC Instance + * @param tampPrivilege This parameter can be one of the following values: + * @arg @ref LL_TAMP_PRIVILEGE_FULL_YES + * @arg @ref LL_TAMP_PRIVILEGE_FULL_NO + * @retval None + */ +__STATIC_INLINE void LL_RTC_SetTampPrivilege(const RTC_TypeDef *RTCx, uint32_t tampPrivilege) +{ + UNUSED(RTCx); + MODIFY_REG(TAMP->PRIVCFGR, TAMP_PRIVCFGR_TAMPPRIV, tampPrivilege); +} + +/** + * @brief Get TAMPER privilege level. + * @rmtoll TAMP_PRIVCFGR TAMPPRIV LL_RTC_GetTampPrivilege + * @param RTCx RTC Instance + * @retval This parameter can be one of the following values: + * @arg @ref LL_TAMP_PRIVILEGE_FULL_YES + * @arg @ref LL_TAMP_PRIVILEGE_FULL_NO + */ +__STATIC_INLINE uint32_t LL_RTC_GetTampPrivilege(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return READ_BIT(TAMP->PRIVCFGR, TAMP_PRIVCFGR_TAMPPRIV); +} + +/** + * @brief Set Backup Registers privilege level. + * @note bckupRegisterPrivilege is only writable in secure mode or if trustzone is disabled + * @rmtoll TAMP_PRIVCFGR BKPWPRIV LL_RTC_SetBackupRegisterPrivilege + * @rmtoll TAMP_PRIVCFGR BKPRWPRIV LL_RTC_SetBackupRegisterPrivilege + * @param RTCx RTC Instance + * @param bckupRegisterPrivilege This parameter can be one of the following values: + * @arg @ref LL_RTC_PRIVILEGE_BKUP_ZONE_NONE + * @arg @ref LL_RTC_PRIVILEGE_BKUP_ZONE_1 + * @arg @ref LL_RTC_PRIVILEGE_BKUP_ZONE_2 + * @arg @ref LL_RTC_PRIVILEGE_BKUP_ZONE_ALL + * @retval None + */ +__STATIC_INLINE void LL_RTC_SetBackupRegisterPrivilege(const RTC_TypeDef *RTCx, uint32_t bckupRegisterPrivilege) +{ + UNUSED(RTCx); + MODIFY_REG(TAMP->PRIVCFGR, (TAMP_PRIVCFGR_BKPWPRIV | TAMP_PRIVCFGR_BKPRWPRIV), bckupRegisterPrivilege); +} + +/** + * @brief Get Backup Registers privilege level. + * @rmtoll TAMP_PRIVCFGR BKPWPRIV LL_RTC_GetBackupRegisterPrivilege + * @rmtoll TAMP_PRIVCFGR BKPRWPRIV LL_RTC_GetBackupRegisterPrivilege + * @param RTCx RTC Instance + * @retval This parameter can be one of the following values: + * @arg @ref LL_RTC_PRIVILEGE_BKUP_ZONE_NONE + * @arg @ref LL_RTC_PRIVILEGE_BKUP_ZONE_1 + * @arg @ref LL_RTC_PRIVILEGE_BKUP_ZONE_2 + * @arg @ref LL_RTC_PRIVILEGE_BKUP_ZONE_ALL + */ +__STATIC_INLINE uint32_t LL_RTC_GetBackupRegisterPrivilege(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return READ_BIT(TAMP->PRIVCFGR, (TAMP_PRIVCFGR_BKPWPRIV | TAMP_PRIVCFGR_BKPRWPRIV)); +} +/** + * @} + */ +#endif /* RTC_PRIVCFGR_PRIV */ + +#if defined(TAMP_SECCFGR_TAMPSEC) +/** @defgroup RTC_LL_EF_BACKUP_REG_PROTECTION PROTECTION_BACKUP_REG_Management + * @brief Backup register protection is common to security and privilege. + * @{ + */ + +/** + * @brief Set Backup registers protection level. + * @note Zone 1 : read protection write protection + * @note Zone 2 : read non-protection write protection + * @note Zone 3 : read non-protection write non-protection + * @note zone 1 : start from 0 to startZone2 start value + * @note zone 2 : start from startZone2 start value to startZone3 start value + * @note zone 3 : start from to startZone3 to the end of BACKUPREG + * @note Warning : this parameter is only writable in secure mode or if trustzone is disabled + * @rmtoll TAMP_SECCFGR BKPWSEC LL_RTC_SetBackupRegProtection + * @rmtoll TAMP_SECCFGR BKPRWSEC LL_RTC_SetBackupRegProtection + * @param RTCx RTC Instance + * @param startZone2 This parameter can be one of the following values: + * @arg @ref LL_RTC_BKP_DR0 + * @arg @ref LL_RTC_BKP_DR1 + * @arg @ref LL_RTC_BKP_DR2 + * @arg @ref LL_RTC_BKP_DR3 + * @arg @ref LL_RTC_BKP_DR4 + * @arg LL_RTC_BKP_DRx ... + * @param startZone3 This parameter can be one of the following values: + * @arg @ref LL_RTC_BKP_DR0 + * @arg @ref LL_RTC_BKP_DR1 + * @arg @ref LL_RTC_BKP_DR2 + * @arg @ref LL_RTC_BKP_DR3 + * @arg @ref LL_RTC_BKP_DR4 + * @arg LL_RTC_BKP_DRx ... + * @retval None + */ +__STATIC_INLINE void LL_RTC_SetBackupRegProtection(const RTC_TypeDef *RTCx, uint32_t startZone2, uint32_t startZone3) +{ + UNUSED(RTCx); + MODIFY_REG(TAMP->SECCFGR, (TAMP_SECCFGR_BKPRWSEC_Msk | TAMP_SECCFGR_BKPWSEC_Msk), + (startZone2 << TAMP_SECCFGR_BKPRWSEC_Pos) | (startZone3 << TAMP_SECCFGR_BKPWSEC_Pos)); +} + +/** + * @brief Get Backup registers protection level start zone 2. + * @note Zone 1 : read protection write protection + * @note Zone 2 : read non-protection/non-privile write protection + * @note Zone 3 : read non-protection write non-protection + * @rmtoll TAMP_SECCFGR BKPRWSEC LL_RTC_GetBackupRegProtectionStartZone2 + * @param RTCx RTC Instance + * @retval Start zone 2 + */ +__STATIC_INLINE uint32_t LL_RTC_GetBackupRegProtectionStartZone2(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return READ_BIT(TAMP->SECCFGR, TAMP_SECCFGR_BKPRWSEC_Msk) >> TAMP_SECCFGR_BKPRWSEC_Pos; +} + +/** + * @brief Get Backup registers protection level start zone 3. + * @note Zone 1 : read protection write protection + * @note Zone 2 : read non-protection write protection + * @note Zone 3 : read non-protection write non-protection + * @rmtoll TAMP_SECCFGR BKPWSEC LL_RTC_GetBackupRegProtectionStartZone3 + * @param RTCx RTC Instance + * @retval Start zone 2 + */ +__STATIC_INLINE uint32_t LL_RTC_GetBackupRegProtectionStartZone3(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return READ_BIT(TAMP->SECCFGR, TAMP_SECCFGR_BKPWSEC_Msk) >> TAMP_SECCFGR_BKPWSEC_Pos; +} +/** + * @} + */ +#endif /* TAMP_SECCFGR_TAMPSEC */ + +/** @defgroup RTC_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable Time-stamp interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR TSIE LL_RTC_EnableIT_TS + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_TS(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_TSIE); +} + +/** + * @brief Disable Time-stamp interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR TSIE LL_RTC_DisableIT_TS + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_TS(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_TSIE); +} + +/** + * @brief Enable Wakeup timer interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR WUTIE LL_RTC_EnableIT_WUT + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_WUT(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_WUTIE); +} + +/** + * @brief Disable Wakeup timer interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR WUTIE LL_RTC_DisableIT_WUT + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_WUT(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_WUTIE); +} + +/** + * @brief Enable Alarm B interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR ALRBIE LL_RTC_EnableIT_ALRB + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_ALRB(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_ALRBIE); +} + +/** + * @brief Disable Alarm B interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR ALRBIE LL_RTC_DisableIT_ALRB + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_ALRB(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_ALRBIE); +} + +/** + * @brief Enable Alarm A interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR ALRAIE LL_RTC_EnableIT_ALRA + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_ALRA(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_ALRAIE); +} + +/** + * @brief Disable Alarm A interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR ALRAIE LL_RTC_DisableIT_ALRA + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_ALRA(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_ALRAIE); +} + +/** + * @brief Enable SSR Underflow interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR SSRUIE LL_RTC_EnableIT_SSRU + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_SSRU(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CR, RTC_CR_SSRUIE); +} + +/** + * @brief Disable SSR Underflow interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll RTC_CR SSRUIE LL_RTC_DisableIT_SSRU + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_SSRU(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CR, RTC_CR_SSRUIE); +} + +/** + * @brief Check if Time-stamp interrupt is enabled or not + * @rmtoll RTC_CR TSIE LL_RTC_IsEnabledIT_TS + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->CR, RTC_CR_TSIE) == (RTC_CR_TSIE)) ? 1U : 0U); +} + +/** + * @brief Check if Wakeup timer interrupt is enabled or not + * @rmtoll RTC_CR WUTIE LL_RTC_IsEnabledIT_WUT + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->CR, RTC_CR_WUTIE) == (RTC_CR_WUTIE)) ? 1U : 0U); +} + +/** + * @brief Check if Alarm B interrupt is enabled or not + * @rmtoll RTC_CR ALRBIE LL_RTC_IsEnabledIT_ALRB + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRB(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->CR, RTC_CR_ALRBIE) == (RTC_CR_ALRBIE)) ? 1U : 0U); +} + +/** + * @brief Check if Alarm A interrupt is enabled or not + * @rmtoll RTC_CR ALRAIE LL_RTC_IsEnabledIT_ALRA + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRA(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->CR, RTC_CR_ALRAIE) == (RTC_CR_ALRAIE)) ? 1U : 0U); +} + +/** + * @brief Check if SSR Underflow interrupt is enabled or not + * @rmtoll RTC_CR SSRUIE LL_RTC_IsEnabledIT_SSRU + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_SSRU(const RTC_TypeDef *RTCx) +{ + return ((READ_BIT(RTCx->CR, RTC_CR_SSRUIE) == (RTC_CR_SSRUIE)) ? 1U : 0U); +} + +/** + * @brief Enable tamper 1 interrupt. + * @rmtoll TAMP_IER TAMP1IE LL_RTC_EnableIT_TAMP1 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_TAMP1(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + SET_BIT(TAMP->IER, TAMP_IER_TAMP1IE); +} + +/** + * @brief Disable tamper 1 interrupt. + * @rmtoll TAMP_IER TAMP1IE LL_RTC_DisableIT_TAMP1 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_TAMP1(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP1IE); +} + +/** + * @brief Enable tamper 2 interrupt. + * @rmtoll TAMP_IER TAMP2IE LL_RTC_EnableIT_TAMP2 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_TAMP2(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + SET_BIT(TAMP->IER, TAMP_IER_TAMP2IE); +} + +/** + * @brief Disable tamper 2 interrupt. + * @rmtoll TAMP_IER TAMP2IE LL_RTC_DisableIT_TAMP2 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_TAMP2(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP2IE); +} + +/** + * @brief Enable tamper 3 interrupt. + * @rmtoll TAMP_IER TAMP3IE LL_RTC_EnableIT_TAMP3 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_TAMP3(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + SET_BIT(TAMP->IER, TAMP_IER_TAMP3IE); +} + +/** + * @brief Disable tamper 3 interrupt. + * @rmtoll TAMP_IER TAMP3IE LL_RTC_DisableIT_TAMP3 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_TAMP3(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP3IE); +} + +#ifdef TAMP_IER_TAMP4IE +/** + * @brief Enable tamper 4 interrupt. + * @rmtoll TAMP_IER TAMP4IE LL_RTC_EnableIT_TAMP4 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_TAMP4(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + SET_BIT(TAMP->IER, TAMP_IER_TAMP4IE); +} + +/** + * @brief Disable tamper 4 interrupt. + * @rmtoll TAMP_IER TAMP4IE LL_RTC_DisableIT_TAMP4 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_TAMP4(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP4IE); +} + +/** + * @brief Enable tamper 5 interrupt. + * @rmtoll TAMP_IER TAMP5IE LL_RTC_EnableIT_TAMP5 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_TAMP5(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + SET_BIT(TAMP->IER, TAMP_IER_TAMP5IE); +} + +/** + * @brief Disable tamper 5 interrupt. + * @rmtoll TAMP_IER TAMP5IE LL_RTC_DisableIT_TAMP5 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_TAMP5(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP5IE); +} + +/** + * @brief Enable tamper 6 interrupt. + * @rmtoll TAMP_IER TAMP6IE LL_RTC_EnableIT_TAMP6 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_TAMP6(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + SET_BIT(TAMP->IER, TAMP_IER_TAMP6IE); +} + +/** + * @brief Disable tamper 6 interrupt. + * @rmtoll TAMP_IER TAMP6IE LL_RTC_DisableIT_TAMP6 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_TAMP6(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP6IE); +} +#endif /* TAMP_IER_TAMP4IE */ + +/** + * @brief Enable internal tamper 3 interrupt. + * @rmtoll TAMP_IER ITAMP3IE LL_RTC_EnableIT_ITAMP3 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_ITAMP3(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + SET_BIT(TAMP->IER, TAMP_IER_ITAMP3IE); +} + +/** + * @brief Disable internal tamper 3 interrupt. + * @rmtoll TAMP_IER ITAMP3IE LL_RTC_DisableIT_ITAMP3 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_ITAMP3(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP3IE); +} + +/** + * @brief Enable internal tamper 5 interrupt. + * @rmtoll TAMP_IER ITAMP5IE LL_RTC_EnableIT_ITAMP5 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_ITAMP5(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + SET_BIT(TAMP->IER, TAMP_IER_ITAMP5IE); +} + +/** + * @brief Disable internal tamper 5 interrupt. + * @rmtoll TAMP_IER ITAMP5IE LL_RTC_DisableIT_ITAMP5 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_ITAMP5(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP5IE); +} + +/** + * @brief Enable internal tamper 6 interrupt. + * @rmtoll TAMP_IER ITAMP6IE LL_RTC_EnableIT_ITAMP6 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_ITAMP6(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + SET_BIT(TAMP->IER, TAMP_IER_ITAMP6IE); +} + +/** + * @brief Disable internal tamper 6 interrupt. + * @rmtoll TAMP_IER ITAMP6IE LL_RTC_DisableIT_ITAMP6 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_ITAMP6(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP6IE); +} + +/** + * @brief Enable internal tamper 7 interrupt. + * @rmtoll TAMP_IER ITAMP7IE LL_RTC_EnableIT_ITAMP7 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_ITAMP7(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + SET_BIT(TAMP->IER, TAMP_IER_ITAMP7IE); +} + +/** + * @brief Disable internal tamper 7 interrupt. + * @rmtoll TAMP_IER ITAMP7IE LL_RTC_DisableIT_ITAMP7 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_ITAMP7(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP7IE); +} + +/** + * @brief Enable internal tamper 8 interrupt. + * @rmtoll TAMP_IER ITAMP8IE LL_RTC_EnableIT_ITAMP8 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_ITAMP8(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + SET_BIT(TAMP->IER, TAMP_IER_ITAMP8IE); +} + +/** + * @brief Disable internal tamper 8 interrupt. + * @rmtoll TAMP_IER ITAMP8IE LL_RTC_DisableIT_ITAMP8 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_ITAMP8(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP8IE); +} + +/** + * @brief Enable internal tamper 9 interrupt. + * @rmtoll TAMP_IER ITAMP9IE LL_RTC_EnableIT_ITAMP9 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_ITAMP9(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + SET_BIT(TAMP->IER, TAMP_IER_ITAMP9IE); +} + +/** + * @brief Disable internal tamper 9 interrupt. + * @rmtoll TAMP_IER ITAMP9IE LL_RTC_DisableIT_ITAMP9 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_ITAMP9(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP9IE); +} + +/** + * @brief Enable internal tamper 11 interrupt. + * @rmtoll TAMP_IER ITAMP11IE LL_RTC_EnableIT_ITAMP11 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_ITAMP11(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + SET_BIT(TAMP->IER, TAMP_IER_ITAMP11IE); +} + +/** + * @brief Disable internal tamper 11 interrupt. + * @rmtoll TAMP_IER ITAMP11IE LL_RTC_DisableIT_ITAMP11 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_ITAMP11(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP11IE); +} + +/** + * @brief Enable internal tamper 12 interrupt. + * @rmtoll TAMP_IER ITAMP12IE LL_RTC_EnableIT_ITAMP12 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_ITAMP12(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + SET_BIT(TAMP->IER, TAMP_IER_ITAMP12IE); +} + +/** + * @brief Disable internal tamper 12 interrupt. + * @rmtoll TAMP_IER ITAMP12IE LL_RTC_DisableIT_ITAMP12 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_ITAMP12(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP12IE); +} + +/** + * @brief Enable internal tamper 13 interrupt. + * @rmtoll TAMP_IER ITAMP13IE LL_RTC_EnableIT_ITAMP13 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_ITAMP13(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + SET_BIT(TAMP->IER, TAMP_IER_ITAMP13IE); +} + +/** + * @brief Disable internal tamper 13 interrupt. + * @rmtoll TAMP_IER ITAMP13IE LL_RTC_DisableIT_ITAMP13 + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_ITAMP13(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP13IE); +} + +/** + * @brief Check if tamper 1 interrupt is enabled or not. + * @rmtoll TAMP_IER TAMP1IE LL_RTC_IsEnabledIT_TAMP1 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP1(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP1IE) == (TAMP_IER_TAMP1IE)) ? 1U : 0U); +} + +/** + * @brief Check if tamper 2 interrupt is enabled or not. + * @rmtoll TAMP_IER TAMP2IE LL_RTC_IsEnabledIT_TAMP2 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP2(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP2IE) == (TAMP_IER_TAMP2IE)) ? 1U : 0U); +} + +/** + * @brief Check if tamper 3 interrupt is enabled or not. + * @rmtoll TAMP_IER TAMP3IE LL_RTC_IsEnabledIT_TAMP3 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP3(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP3IE) == (TAMP_IER_TAMP3IE)) ? 1U : 0U); +} + +#ifdef TAMP_IER_TAMP4IE +/** + * @brief Check if tamper 4 interrupt is enabled or not. + * @rmtoll TAMP_IER TAMP4IE LL_RTC_IsEnabledIT_TAMP4 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP4(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP4IE) == (TAMP_IER_TAMP4IE)) ? 1U : 0U); +} + +/** + * @brief Check if tamper 5 interrupt is enabled or not. + * @rmtoll TAMP_IER TAMP5IE LL_RTC_IsEnabledIT_TAMP5 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP5(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP5IE) == (TAMP_IER_TAMP5IE)) ? 1U : 0U); +} + +/** + * @brief Check if tamper 6 interrupt is enabled or not. + * @rmtoll TAMP_IER TAMP6IE LL_RTC_IsEnabledIT_TAMP6 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP6(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP6IE) == (TAMP_IER_TAMP6IE)) ? 1U : 0U); +} +#endif /* TAMP_IER_TAMP4IE */ + +/** + * @brief Check if internal tamper 3 interrupt is enabled or not. + * @rmtoll TAMP_IER ITAMP3IE LL_RTC_IsEnabledIT_ITAMP3 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP3(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP3IE) == (TAMP_IER_ITAMP3IE)) ? 1U : 0U); +} + +/** + * @brief Check if internal tamper 5 interrupt is enabled or not. + * @rmtoll TAMP_IER ITAMP5IE LL_RTC_IsEnabledIT_ITAMP5 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP5(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP5IE) == (TAMP_IER_ITAMP5IE)) ? 1U : 0U); +} + +/** + * @brief Check if internal tamper 6 interrupt is enabled or not. + * @rmtoll TAMP_IER ITAMP6IE LL_RTC_IsEnabledIT_ITAMP6 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP6(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP6IE) == (TAMP_IER_ITAMP6IE)) ? 1U : 0U); +} + +/** + * @brief Check if internal tamper 7 interrupt is enabled or not. + * @rmtoll TAMP_IER ITAMP7IE LL_RTC_IsEnabledIT_ITAMP7 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP7(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP7IE) == (TAMP_IER_ITAMP7IE)) ? 1U : 0U); +} + +/** + * @brief Check if internal tamper 8 interrupt is enabled or not. + * @rmtoll TAMP_IER ITAMP8IE LL_RTC_IsEnabledIT_ITAMP8 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP8(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP8IE) == (TAMP_IER_ITAMP8IE)) ? 1U : 0U); +} + +/** + * @brief Check if internal tamper 9 interrupt is enabled or not. + * @rmtoll TAMP_IER ITAMP9IE LL_RTC_IsEnabledIT_ITAMP9 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP9(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP9IE) == (TAMP_IER_ITAMP9IE)) ? 1U : 0U); +} + +/** + * @brief Check if internal tamper 11 interrupt is enabled or not. + * @rmtoll TAMP_IER ITAMP11IE LL_RTC_IsEnabledIT_ITAMP11 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP11(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP11IE) == (TAMP_IER_ITAMP11IE)) ? 1U : 0U); +} + +/** + * @brief Check if internal tamper 12 interrupt is enabled or not. + * @rmtoll TAMP_IER ITAMP12IE LL_RTC_IsEnabledIT_ITAMP12 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP12(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP12IE) == (TAMP_IER_ITAMP12IE)) ? 1U : 0U); +} + +/** + * @brief Check if internal tamper 13 interrupt is enabled or not. + * @rmtoll TAMP_IER ITAMP13IE LL_RTC_IsEnabledIT_ITAMP13 + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP13(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP13IE) == (TAMP_IER_ITAMP13IE)) ? 1U : 0U); +} + +/** + * @brief Increment Monotonic counter. + * @rmtoll TAMP_COUNT1R COUNT LL_RTC_IncrementMonotonicCounter + * @param RTCx RTC Instance + * @retval None. + */ +__STATIC_INLINE void LL_RTC_IncrementMonotonicCounter(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + WRITE_REG(TAMP->COUNT1R, 0U); +} + +/** + * @brief Increment Monotonic counter. + * @rmtoll TAMP_COUNT1R COUNT LL_RTC_GetMonotonicCounter + * @param RTCx RTC Instance + * @retval Monotonic counter value. + */ +__STATIC_INLINE uint32_t LL_RTC_GetMonotonicCounter(const RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + return READ_REG(TAMP->COUNT1R); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RTC_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx); +ErrorStatus LL_RTC_Init(RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct); +void LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct); +ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct); +void LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct); +ErrorStatus LL_RTC_DATE_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct); +void LL_RTC_DATE_StructInit(LL_RTC_DateTypeDef *RTC_DateStruct); +ErrorStatus LL_RTC_ALMA_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct); +ErrorStatus LL_RTC_ALMB_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct); +void LL_RTC_ALMA_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct); +void LL_RTC_ALMB_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct); +ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx); +ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx); +ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(RTC) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WBAxx_LL_RTC_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_spi.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_spi.h new file mode 100644 index 0000000000..37db1561f3 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_spi.h @@ -0,0 +1,2735 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_ll_spi.h + * @author MCD Application Team + * @brief Header file of SPI LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_LL_SPI_H +#define STM32WBAxx_LL_SPI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx.h" + +/** @addtogroup STM32WBAxx_LL_Driver + * @{ + */ + +#if defined(SPI1) || defined(SPI3) + +/** @defgroup SPI_LL SPI + * @{ + */ + +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup SPI_LL_Private_Macros SPI Private Macros + * @{ + */ +#if defined(IS_SPI_GRP1_INSTANCE) +#define IS_LL_SPI_GRP1_INSTANCE(__INSTANCE__) IS_SPI_GRP1_INSTANCE(__INSTANCE__) +#endif /* SPI_TRIG_GRP1 */ +#define IS_LL_SPI_GRP2_INSTANCE(__INSTANCE__) IS_SPI_GRP2_INSTANCE(__INSTANCE__) +/** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup SPI_LL_Exported_Types SPI Exported Types + * @{ + */ + +/** + * @brief SPI Init structures definition + */ +typedef struct +{ + uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode. + This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE. + + This feature can be modified afterwards using unitary function + @ref LL_SPI_SetTransferDirection().*/ + + uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave). + This parameter can be a value of @ref SPI_LL_EC_MODE. + + This feature can be modified afterwards using unitary function + @ref LL_SPI_SetMode().*/ + + uint32_t DataWidth; /*!< Specifies the SPI data width. + This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH. + + This feature can be modified afterwards using unitary function + @ref LL_SPI_SetDataWidth().*/ + + uint32_t ClockPolarity; /*!< Specifies the serial clock steady state. + This parameter can be a value of @ref SPI_LL_EC_POLARITY. + + This feature can be modified afterwards using unitary function + @ref LL_SPI_SetClockPolarity().*/ + + uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture. + This parameter can be a value of @ref SPI_LL_EC_PHASE. + + This feature can be modified afterwards using unitary function + @ref LL_SPI_SetClockPhase().*/ + + uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) + or by software using the SSI bit. + + This parameter can be a value of @ref SPI_LL_EC_NSS_MODE. + + This feature can be modified afterwards using unitary function + @ref LL_SPI_SetNSSMode().*/ + + uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure + the transmit and receive SCK clock. + This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER. + @note The communication clock is derived from the master clock. + The slave clock does not need to be set. + + This feature can be modified afterwards using unitary function + @ref LL_SPI_SetBaudRatePrescaler().*/ + + uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit. + This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER. + + This feature can be modified afterwards using unitary function + @ref LL_SPI_SetTransferBitOrder().*/ + + uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. + This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION. + + This feature can be modified afterwards using unitary functions + @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/ + + uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation. + This parameter must be a number between Min_Data = 0x00 + and Max_Data = 0xFFFFFFFF. + + This feature can be modified afterwards using unitary function + @ref LL_SPI_SetCRCPolynomial().*/ + +} LL_SPI_InitTypeDef; + +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SPI_LL_Exported_Constants SPI Exported Constants + * @{ + */ + +/** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_SPI_ReadReg function + * @{ + */ +#define LL_SPI_SR_RXP (SPI_SR_RXP) +#define LL_SPI_SR_TXP (SPI_SR_TXP) +#define LL_SPI_SR_DXP (SPI_SR_DXP) +#define LL_SPI_SR_EOT (SPI_SR_EOT) +#define LL_SPI_SR_TXTF (SPI_SR_TXTF) +#define LL_SPI_SR_UDR (SPI_SR_UDR) +#define LL_SPI_SR_CRCE (SPI_SR_CRCE) +#define LL_SPI_SR_MODF (SPI_SR_MODF) +#define LL_SPI_SR_OVR (SPI_SR_OVR) +#define LL_SPI_SR_TIFRE (SPI_SR_TIFRE) +#define LL_SPI_SR_SUSP (SPI_SR_SUSP) +#define LL_SPI_SR_TXC (SPI_SR_TXC) +#define LL_SPI_SR_RXWNE (SPI_SR_RXWNE) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions + * @{ + */ +#define LL_SPI_IER_RXPIE (SPI_IER_RXPIE) +#define LL_SPI_IER_TXPIE (SPI_IER_TXPIE) +#define LL_SPI_IER_DXPIE (SPI_IER_DXPIE) +#define LL_SPI_IER_EOTIE (SPI_IER_EOTIE) +#define LL_SPI_IER_TXTFIE (SPI_IER_TXTFIE) +#define LL_SPI_IER_UDRIE (SPI_IER_UDRIE) +#define LL_SPI_IER_OVRIE (SPI_IER_OVRIE) +#define LL_SPI_IER_CRCEIE (SPI_IER_CRCEIE) +#define LL_SPI_IER_TIFREIE (SPI_IER_TIFREIE) +#define LL_SPI_IER_MODFIE (SPI_IER_MODFIE) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_MODE Mode + * @{ + */ +#define LL_SPI_MODE_MASTER (SPI_CFG2_MASTER) +#define LL_SPI_MODE_SLAVE (0x00000000UL) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_SS_LEVEL SS Level + * @{ + */ +#define LL_SPI_SS_LEVEL_HIGH (SPI_CR1_SSI) +#define LL_SPI_SS_LEVEL_LOW (0x00000000UL) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_SS_IDLENESS SS Idleness + * @{ + */ +#define LL_SPI_SS_IDLENESS_00CYCLE (0x00000000UL) +#define LL_SPI_SS_IDLENESS_01CYCLE (SPI_CFG2_MSSI_0) +#define LL_SPI_SS_IDLENESS_02CYCLE (SPI_CFG2_MSSI_1) +#define LL_SPI_SS_IDLENESS_03CYCLE (SPI_CFG2_MSSI_0 | SPI_CFG2_MSSI_1) +#define LL_SPI_SS_IDLENESS_04CYCLE (SPI_CFG2_MSSI_2) +#define LL_SPI_SS_IDLENESS_05CYCLE (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_0) +#define LL_SPI_SS_IDLENESS_06CYCLE (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1) +#define LL_SPI_SS_IDLENESS_07CYCLE (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0) +#define LL_SPI_SS_IDLENESS_08CYCLE (SPI_CFG2_MSSI_3) +#define LL_SPI_SS_IDLENESS_09CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_0) +#define LL_SPI_SS_IDLENESS_10CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_1) +#define LL_SPI_SS_IDLENESS_11CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0) +#define LL_SPI_SS_IDLENESS_12CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2) +#define LL_SPI_SS_IDLENESS_13CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_0) +#define LL_SPI_SS_IDLENESS_14CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1) +#define LL_SPI_SS_IDLENESS_15CYCLE (SPI_CFG2_MSSI_3\ + | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_ID_IDLENESS Master Inter-Data Idleness + * @{ + */ +#define LL_SPI_ID_IDLENESS_00CYCLE (0x00000000UL) +#define LL_SPI_ID_IDLENESS_01CYCLE (SPI_CFG2_MIDI_0) +#define LL_SPI_ID_IDLENESS_02CYCLE (SPI_CFG2_MIDI_1) +#define LL_SPI_ID_IDLENESS_03CYCLE (SPI_CFG2_MIDI_0 | SPI_CFG2_MIDI_1) +#define LL_SPI_ID_IDLENESS_04CYCLE (SPI_CFG2_MIDI_2) +#define LL_SPI_ID_IDLENESS_05CYCLE (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_0) +#define LL_SPI_ID_IDLENESS_06CYCLE (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1) +#define LL_SPI_ID_IDLENESS_07CYCLE (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0) +#define LL_SPI_ID_IDLENESS_08CYCLE (SPI_CFG2_MIDI_3) +#define LL_SPI_ID_IDLENESS_09CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_0) +#define LL_SPI_ID_IDLENESS_10CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_1) +#define LL_SPI_ID_IDLENESS_11CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0) +#define LL_SPI_ID_IDLENESS_12CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2) +#define LL_SPI_ID_IDLENESS_13CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_0) +#define LL_SPI_ID_IDLENESS_14CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1) +#define LL_SPI_ID_IDLENESS_15CYCLE (SPI_CFG2_MIDI_3\ + | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_TXCRCINIT_ALL TXCRC Init All + * @{ + */ +#define LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN (0x00000000UL) +#define LL_SPI_TXCRCINIT_ALL_ONES_PATTERN (SPI_CR1_TCRCINI) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_RXCRCINIT_ALL RXCRC Init All + * @{ + */ +#define LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN (0x00000000UL) +#define LL_SPI_RXCRCINIT_ALL_ONES_PATTERN (SPI_CR1_RCRCINI) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_UDR_CONFIG_REGISTER UDR Config Register + * @{ + */ +#define LL_SPI_UDR_CONFIG_REGISTER_PATTERN (0x00000000UL) +#define LL_SPI_UDR_CONFIG_LAST_RECEIVED (SPI_CFG1_UDRCFG) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_PROTOCOL Protocol + * @{ + */ +#define LL_SPI_PROTOCOL_MOTOROLA (0x00000000UL) +#define LL_SPI_PROTOCOL_TI (SPI_CFG2_SP_0) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_PHASE Phase + * @{ + */ +#define LL_SPI_PHASE_1EDGE (0x00000000UL) +#define LL_SPI_PHASE_2EDGE (SPI_CFG2_CPHA) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_POLARITY Polarity + * @{ + */ +#define LL_SPI_POLARITY_LOW (0x00000000UL) +#define LL_SPI_POLARITY_HIGH (SPI_CFG2_CPOL) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_NSS_POLARITY NSS Polarity + * @{ + */ +#define LL_SPI_NSS_POLARITY_LOW (0x00000000UL) +#define LL_SPI_NSS_POLARITY_HIGH (SPI_CFG2_SSIOP) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler + * @{ + */ +#define LL_SPI_BAUDRATEPRESCALER_BYPASS (SPI_CFG1_BPASS) +#define LL_SPI_BAUDRATEPRESCALER_DIV2 (0x00000000UL) +#define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CFG1_MBR_0) +#define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CFG1_MBR_1) +#define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CFG1_MBR_1 | SPI_CFG1_MBR_0) +#define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CFG1_MBR_2) +#define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_0) +#define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_1) +#define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_1 | SPI_CFG1_MBR_0) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_BIT_ORDER Bit Order + * @{ + */ +#define LL_SPI_LSB_FIRST (SPI_CFG2_LSBFRST) +#define LL_SPI_MSB_FIRST (0x00000000UL) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode + * @{ + */ +#define LL_SPI_FULL_DUPLEX (0x00000000UL) +#define LL_SPI_SIMPLEX_TX (SPI_CFG2_COMM_0) +#define LL_SPI_SIMPLEX_RX (SPI_CFG2_COMM_1) +#define LL_SPI_HALF_DUPLEX_RX (SPI_CFG2_COMM_0|SPI_CFG2_COMM_1) +#define LL_SPI_HALF_DUPLEX_TX (SPI_CFG2_COMM_0|SPI_CFG2_COMM_1|SPI_CR1_HDDIR) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_DATAWIDTH Data Width + * @{ + */ +#define LL_SPI_DATAWIDTH_4BIT (SPI_CFG1_DSIZE_0 | SPI_CFG1_DSIZE_1) +#define LL_SPI_DATAWIDTH_5BIT (SPI_CFG1_DSIZE_2) +#define LL_SPI_DATAWIDTH_6BIT (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0) +#define LL_SPI_DATAWIDTH_7BIT (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1) +#define LL_SPI_DATAWIDTH_8BIT (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0) +#define LL_SPI_DATAWIDTH_9BIT (SPI_CFG1_DSIZE_3) +#define LL_SPI_DATAWIDTH_10BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_0) +#define LL_SPI_DATAWIDTH_11BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1) +#define LL_SPI_DATAWIDTH_12BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0) +#define LL_SPI_DATAWIDTH_13BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2) +#define LL_SPI_DATAWIDTH_14BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0) +#define LL_SPI_DATAWIDTH_15BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1) +#define LL_SPI_DATAWIDTH_16BIT (SPI_CFG1_DSIZE_3\ + | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0) +#define LL_SPI_DATAWIDTH_17BIT (SPI_CFG1_DSIZE_4) +#define LL_SPI_DATAWIDTH_18BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_0) +#define LL_SPI_DATAWIDTH_19BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_1) +#define LL_SPI_DATAWIDTH_20BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_0 | SPI_CFG1_DSIZE_1) +#define LL_SPI_DATAWIDTH_21BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2) +#define LL_SPI_DATAWIDTH_22BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0) +#define LL_SPI_DATAWIDTH_23BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1) +#define LL_SPI_DATAWIDTH_24BIT (SPI_CFG1_DSIZE_4\ + | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0) +#define LL_SPI_DATAWIDTH_25BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3) +#define LL_SPI_DATAWIDTH_26BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_0) +#define LL_SPI_DATAWIDTH_27BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1) +#define LL_SPI_DATAWIDTH_28BIT (SPI_CFG1_DSIZE_4\ + | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0) +#define LL_SPI_DATAWIDTH_29BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2) +#define LL_SPI_DATAWIDTH_30BIT (SPI_CFG1_DSIZE_4\ + | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0) +#define LL_SPI_DATAWIDTH_31BIT (SPI_CFG1_DSIZE_4\ + | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1) +#define LL_SPI_DATAWIDTH_32BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3\ + | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_FIFO_TH FIFO Threshold + * @{ + */ +#define LL_SPI_FIFO_TH_01DATA (0x00000000UL) +#define LL_SPI_FIFO_TH_02DATA (SPI_CFG1_FTHLV_0) +#define LL_SPI_FIFO_TH_03DATA (SPI_CFG1_FTHLV_1) +#define LL_SPI_FIFO_TH_04DATA (SPI_CFG1_FTHLV_0 | SPI_CFG1_FTHLV_1) +#define LL_SPI_FIFO_TH_05DATA (SPI_CFG1_FTHLV_2) +#define LL_SPI_FIFO_TH_06DATA (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_0) +#define LL_SPI_FIFO_TH_07DATA (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1) +#define LL_SPI_FIFO_TH_08DATA (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0) +#define LL_SPI_FIFO_TH_09DATA (SPI_CFG1_FTHLV_3) +#define LL_SPI_FIFO_TH_10DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_0) +#define LL_SPI_FIFO_TH_11DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_1) +#define LL_SPI_FIFO_TH_12DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0) +#define LL_SPI_FIFO_TH_13DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2) +#define LL_SPI_FIFO_TH_14DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_0) +#define LL_SPI_FIFO_TH_15DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1) +#define LL_SPI_FIFO_TH_16DATA (SPI_CFG1_FTHLV_3\ + | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0) +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) + +/** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation + * @{ + */ +#define LL_SPI_CRCCALCULATION_DISABLE (0x00000000UL) /*!< CRC calculation disabled */ +#define LL_SPI_CRCCALCULATION_ENABLE (SPI_CFG1_CRCEN) /*!< CRC calculation enabled */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** @defgroup SPI_LL_EC_CRC CRC + * @{ + */ +#define LL_SPI_CRC_4BIT (SPI_CFG1_CRCSIZE_0 | SPI_CFG1_CRCSIZE_1) +#define LL_SPI_CRC_5BIT (SPI_CFG1_CRCSIZE_2) +#define LL_SPI_CRC_6BIT (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0) +#define LL_SPI_CRC_7BIT (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1) +#define LL_SPI_CRC_8BIT (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0) +#define LL_SPI_CRC_9BIT (SPI_CFG1_CRCSIZE_3) +#define LL_SPI_CRC_10BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_0) +#define LL_SPI_CRC_11BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1) +#define LL_SPI_CRC_12BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0) +#define LL_SPI_CRC_13BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2) +#define LL_SPI_CRC_14BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0) +#define LL_SPI_CRC_15BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1) +#define LL_SPI_CRC_16BIT (SPI_CFG1_CRCSIZE_3\ + | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0) +#define LL_SPI_CRC_17BIT (SPI_CFG1_CRCSIZE_4) +#define LL_SPI_CRC_18BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_0) +#define LL_SPI_CRC_19BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_1) +#define LL_SPI_CRC_20BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_0 | SPI_CFG1_CRCSIZE_1) +#define LL_SPI_CRC_21BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2) +#define LL_SPI_CRC_22BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0) +#define LL_SPI_CRC_23BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1) +#define LL_SPI_CRC_24BIT (SPI_CFG1_CRCSIZE_4\ + | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0) +#define LL_SPI_CRC_25BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3) +#define LL_SPI_CRC_26BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_0) +#define LL_SPI_CRC_27BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1) +#define LL_SPI_CRC_28BIT (SPI_CFG1_CRCSIZE_4\ + | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0) +#define LL_SPI_CRC_29BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2) +#define LL_SPI_CRC_30BIT (SPI_CFG1_CRCSIZE_4\ + | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0) +#define LL_SPI_CRC_31BIT (SPI_CFG1_CRCSIZE_4\ + | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1) +#define LL_SPI_CRC_32BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3\ + | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_NSS_MODE NSS Mode + * @{ + */ +#define LL_SPI_NSS_SOFT (SPI_CFG2_SSM) +#define LL_SPI_NSS_HARD_INPUT (0x00000000UL) +#define LL_SPI_NSS_HARD_OUTPUT (SPI_CFG2_SSOE) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_RX_FIFO RxFIFO Packing LeVel + * @{ + */ +#define LL_SPI_RX_FIFO_0PACKET (0x00000000UL) /* 0 or multiple of 4 packet available is the RxFIFO */ +#define LL_SPI_RX_FIFO_1PACKET (SPI_SR_RXPLVL_0) +#define LL_SPI_RX_FIFO_2PACKET (SPI_SR_RXPLVL_1) +#define LL_SPI_RX_FIFO_3PACKET (SPI_SR_RXPLVL_1 | SPI_SR_RXPLVL_0) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_AUTOCR_TRIGSEL Autonomous Trigger selection + * @brief SPI Autonomous Trigger selection + * @{ + */ +#if defined(SPI1) +#define LL_SPI_TRIG_GRP1 (0x10000000U) /*!< Trigger Group for SPI1 */ +#endif /* SPI1 */ +#define LL_SPI_TRIG_GRP2 (0x20000000U) /*!< Trigger Group for SPI3 */ + +#if defined(LL_SPI_TRIG_GRP1) +/*!< HW Trigger signal is GPDMA_CH0_TRG */ +#define LL_SPI_GRP1_GPDMA_CH0_TCF_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x00000000U)) +/*!< HW Trigger signal is GPDMA_CH1_TRG */ +#define LL_SPI_GRP1_GPDMA_CH1_TCF_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x1U << SPI_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is GPDMA_CH2_TRG */ +#define LL_SPI_GRP1_GPDMA_CH2_TCF_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x2U << SPI_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is GPDMA_CH3_TRG */ +#define LL_SPI_GRP1_GPDMA_CH3_TCF_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x3U << SPI_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is EXTI4_TRG */ +#define LL_SPI_GRP1_EXTI4_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x4U << SPI_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is EXTI9_TRG */ +#define LL_SPI_GRP1_EXTI9_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x5U << SPI_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is LPTIM1_CH1_TRG */ +#define LL_SPI_GRP1_LPTIM1_CH1_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x6U << SPI_AUTOCR_TRIGSEL_Pos)) +#if defined (LPTIM2) +/*!< HW Trigger signal is LPTIM2_CH1_TRG */ +#define LL_SPI_GRP1_LPTIM2_CH1_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x7U << SPI_AUTOCR_TRIGSEL_Pos)) +#endif /* LPTIM2 */ +#if defined (COMP1) +/*!< HW Trigger signal is COMP1_TRG */ +#define LL_SPI_GRP1_COMP1_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x8U << SPI_AUTOCR_TRIGSEL_Pos)) +#endif /* COMP1 */ +#if defined (COMP2) +/*!< HW Trigger signal is COMP2_TRG */ +#define LL_SPI_GRP1_COMP2_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x9U << SPI_AUTOCR_TRIGSEL_Pos)) +#endif /* COMP2 */ +/*!< HW Trigger signal is RTC_ALRA_TRG */ +#define LL_SPI_GRP1_RTC_ALRA_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0xAU << SPI_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is RTC_WUT_TRG */ +#define LL_SPI_GRP1_RTC_WUT_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0xBU << SPI_AUTOCR_TRIGSEL_Pos)) +#endif /* LL_SPI_TRIG_GRP1 */ + +/*!< HW Trigger signal is LPDMA_CH0_TRG */ +#define LL_SPI_GRP2_GPDMA_CH0_TCF_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x00000000U)) +/*!< HW Trigger signal is LPDMA_CH1_TRG */ +#define LL_SPI_GRP2_GPDMA_CH1_TCF_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x1U << SPI_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is LPDMA_CH2_TRG */ +#define LL_SPI_GRP2_GPDMA_CH2_TCF_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x2U << SPI_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is LPDMA_CH3_TRG */ +#define LL_SPI_GRP2_GPDMA_CH3_TCF_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x3U << SPI_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is EXTI4_TRG */ +#define LL_SPI_GRP2_EXTI4_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x4U << SPI_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is EXTI8_TRG */ +#define LL_SPI_GRP2_EXTI8_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x5U << SPI_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is LPTIM1_CH1_TRG */ +#define LL_SPI_GRP2_LPTIM1_CH1_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x6U << SPI_AUTOCR_TRIGSEL_Pos)) +#if defined (COMP1) +/*!< HW Trigger signal is COMP1_TRG */ +#define LL_SPI_GRP2_COMP1_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x8U << SPI_AUTOCR_TRIGSEL_Pos)) +#endif /* COMP1 */ +/*!< HW Trigger signal is RTC_ALRA_TRG */ +#define LL_SPI_GRP2_RTC_ALRA_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0xAU << SPI_AUTOCR_TRIGSEL_Pos)) +/*!< HW Trigger signal is RTC_WUT_TRG */ +#define LL_SPI_GRP2_RTC_WUT_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0xBU << SPI_AUTOCR_TRIGSEL_Pos)) +/** + * @} + */ + +/** @defgroup SPI_LL_EC_AUTOCR_TRIGPOL Autonomous Trigger Polarity + * @brief SPI Autonomous Trigger Polarity + * @{ + */ +#define LL_SPI_TRIG_POLARITY_RISING 0x00000000U /*!< SPI triggered on rising edge */ +#define LL_SPI_TRIG_POLARITY_FALLING SPI_AUTOCR_TRIGPOL /*!< SPI triggered on falling edge */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup SPI_LL_Exported_Macros SPI Exported Macros + * @{ + */ + +/** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in SPI register + * @param __INSTANCE__ SPI Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in SPI register + * @param __INSTANCE__ SPI Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup SPI_LL_Exported_Functions SPI Exported Functions + * @{ + */ + +/** @defgroup SPI_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Enable SPI peripheral + * @rmtoll CR1 SPE LL_SPI_Enable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR1, SPI_CR1_SPE); +} + +/** + * @brief Disable SPI peripheral + * @note When disabling the SPI, follow the procedure described in the Reference Manual. + * @rmtoll CR1 SPE LL_SPI_Disable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE); +} + +/** + * @brief Check if SPI peripheral is enabled + * @rmtoll CR1 SPE LL_SPI_IsEnabled + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabled(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL); +} + +/** + * @brief Swap the MOSI and MISO pin + * @note This configuration can not be changed when SPI is enabled. + * @rmtoll CFG2 IOSWP LL_SPI_EnableIOSwap + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIOSwap(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CFG2, SPI_CFG2_IOSWP); +} + +/** + * @brief Restore default function for MOSI and MISO pin + * @note This configuration can not be changed when SPI is enabled. + * @rmtoll CFG2 IOSWP LL_SPI_DisableIOSwap + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableIOSwap(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CFG2, SPI_CFG2_IOSWP); +} + +/** + * @brief Check if MOSI and MISO pin are swapped + * @rmtoll CFG2 IOSWP LL_SPI_IsEnabledIOSwap + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIOSwap(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CFG2, SPI_CFG2_IOSWP) == (SPI_CFG2_IOSWP)) ? 1UL : 0UL); +} + +/** + * @brief Enable GPIO control + * @note This configuration can not be changed when SPI is enabled. + * @rmtoll CFG2 AFCNTR LL_SPI_EnableGPIOControl + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableGPIOControl(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR); +} + +/** + * @brief Disable GPIO control + * @note This configuration can not be changed when SPI is enabled. + * @rmtoll CFG2 AFCNTR LL_SPI_DisableGPIOControl + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableGPIOControl(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR); +} + +/** + * @brief Check if GPIO control is active + * @rmtoll CFG2 AFCNTR LL_SPI_IsEnabledGPIOControl + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledGPIOControl(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR) == (SPI_CFG2_AFCNTR)) ? 1UL : 0UL); +} + +/** + * @brief Set SPI Mode to Master or Slave + * @note This configuration can not be changed when SPI is enabled. + * @rmtoll CFG2 MASTER LL_SPI_SetMode + * @param SPIx SPI Instance + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_SPI_MODE_MASTER + * @arg @ref LL_SPI_MODE_SLAVE + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode) +{ + MODIFY_REG(SPIx->CFG2, SPI_CFG2_MASTER, Mode); +} + +/** + * @brief Get SPI Mode (Master or Slave) + * @rmtoll CFG2 MASTER LL_SPI_GetMode + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_MODE_MASTER + * @arg @ref LL_SPI_MODE_SLAVE + */ +__STATIC_INLINE uint32_t LL_SPI_GetMode(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MASTER)); +} + +/** + * @brief Configure the Idleness applied by master between active edge of SS and first send data + * @rmtoll CFG2 MSSI LL_SPI_SetMasterSSIdleness + * @param SPIx SPI Instance + * @param MasterSSIdleness This parameter can be one of the following values: + * @arg @ref LL_SPI_SS_IDLENESS_00CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_01CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_02CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_03CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_04CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_05CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_06CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_07CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_08CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_09CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_10CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_11CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_12CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_13CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_14CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_15CYCLE + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetMasterSSIdleness(SPI_TypeDef *SPIx, uint32_t MasterSSIdleness) +{ + MODIFY_REG(SPIx->CFG2, SPI_CFG2_MSSI, MasterSSIdleness); +} + +/** + * @brief Get the configured Idleness applied by master + * @rmtoll CFG2 MSSI LL_SPI_GetMasterSSIdleness + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_SS_IDLENESS_00CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_01CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_02CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_03CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_04CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_05CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_06CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_07CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_08CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_09CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_10CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_11CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_12CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_13CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_14CYCLE + * @arg @ref LL_SPI_SS_IDLENESS_15CYCLE + */ +__STATIC_INLINE uint32_t LL_SPI_GetMasterSSIdleness(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MSSI)); +} + +/** + * @brief Configure the idleness applied by master between data frame + * @rmtoll CFG2 MIDI LL_SPI_SetInterDataIdleness + * @param SPIx SPI Instance + * @param MasterInterDataIdleness This parameter can be one of the following values: + * @arg @ref LL_SPI_ID_IDLENESS_00CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_01CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_02CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_03CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_04CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_05CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_06CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_07CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_08CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_09CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_10CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_11CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_12CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_13CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_14CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_15CYCLE + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetInterDataIdleness(SPI_TypeDef *SPIx, uint32_t MasterInterDataIdleness) +{ + MODIFY_REG(SPIx->CFG2, SPI_CFG2_MIDI, MasterInterDataIdleness); +} + +/** + * @brief Get the configured inter data idleness + * @rmtoll CFG2 MIDI LL_SPI_SetInterDataIdleness + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_ID_IDLENESS_00CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_01CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_02CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_03CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_04CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_05CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_06CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_07CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_08CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_09CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_10CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_11CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_12CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_13CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_14CYCLE + * @arg @ref LL_SPI_ID_IDLENESS_15CYCLE + */ +__STATIC_INLINE uint32_t LL_SPI_GetInterDataIdleness(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MIDI)); +} + +/** + * @brief Set transfer size + * @note Count is the number of frame to be transferred + * @rmtoll CR2 TSIZE LL_SPI_SetTransferSize + * @param SPIx SPI Instance + * @param Count 0..0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetTransferSize(SPI_TypeDef *SPIx, uint32_t Count) +{ + MODIFY_REG(SPIx->CR2, SPI_CR2_TSIZE, Count); +} + +/** + * @brief Get transfer size + * @note Count is the number of frame to be transferred + * @rmtoll CR2 TSIZE LL_SPI_GetTransferSize + * @param SPIx SPI Instance + * @retval 0..0xFFFF + */ +__STATIC_INLINE uint32_t LL_SPI_GetTransferSize(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_TSIZE)); +} + +/** + * @brief Lock the AF configuration of associated IOs + * @note Once this bit is set, the AF configuration remains locked until a hardware reset occurs. + * the reset of the IOLock bit is done by hardware. for that, LL_SPI_DisableIOLock can not exist. + * @rmtoll CR1 IOLOCK LL_SPI_EnableIOLock + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIOLock(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR1, SPI_CR1_IOLOCK); +} + +/** + * @brief Check if the AF configuration is locked. + * @rmtoll CR1 IOLOCK LL_SPI_IsEnabledIOLock + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIOLock(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CR1, SPI_CR1_IOLOCK) == (SPI_CR1_IOLOCK)) ? 1UL : 0UL); +} + +/** + * @brief Set Tx CRC Initialization Pattern + * @rmtoll CR1 TCRCINI LL_SPI_SetTxCRCInitPattern + * @param SPIx SPI Instance + * @param TXCRCInitAll This parameter can be one of the following values: + * @arg @ref LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN + * @arg @ref LL_SPI_TXCRCINIT_ALL_ONES_PATTERN + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetTxCRCInitPattern(SPI_TypeDef *SPIx, uint32_t TXCRCInitAll) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_RCRCINI, TXCRCInitAll); +} + +/** + * @brief Get Tx CRC Initialization Pattern + * @rmtoll CR1 TCRCINI LL_SPI_GetTxCRCInitPattern + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN + * @arg @ref LL_SPI_TXCRCINIT_ALL_ONES_PATTERN + */ +__STATIC_INLINE uint32_t LL_SPI_GetTxCRCInitPattern(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_TCRCINI)); +} + +/** + * @brief Set Rx CRC Initialization Pattern + * @rmtoll CR1 RCRCINI LL_SPI_SetRxCRCInitPattern + * @param SPIx SPI Instance + * @param RXCRCInitAll This parameter can be one of the following values: + * @arg @ref LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN + * @arg @ref LL_SPI_RXCRCINIT_ALL_ONES_PATTERN + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetRxCRCInitPattern(SPI_TypeDef *SPIx, uint32_t RXCRCInitAll) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_RCRCINI, RXCRCInitAll); +} + +/** + * @brief Get Rx CRC Initialization Pattern + * @rmtoll CR1 RCRCINI LL_SPI_GetRxCRCInitPattern + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN + * @arg @ref LL_SPI_RXCRCINIT_ALL_ONES_PATTERN + */ +__STATIC_INLINE uint32_t LL_SPI_GetRxCRCInitPattern(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RCRCINI)); +} + +/** + * @brief Set internal SS input level ignoring what comes from PIN. + * @note This configuration has effect only with config LL_SPI_NSS_SOFT + * @rmtoll CR1 SSI LL_SPI_SetInternalSSLevel + * @param SPIx SPI Instance + * @param SSLevel This parameter can be one of the following values: + * @arg @ref LL_SPI_SS_LEVEL_HIGH + * @arg @ref LL_SPI_SS_LEVEL_LOW + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetInternalSSLevel(SPI_TypeDef *SPIx, uint32_t SSLevel) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_SSI, SSLevel); +} + +/** + * @brief Get internal SS input level + * @rmtoll CR1 SSI LL_SPI_GetInternalSSLevel + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_SS_LEVEL_HIGH + * @arg @ref LL_SPI_SS_LEVEL_LOW + */ +__STATIC_INLINE uint32_t LL_SPI_GetInternalSSLevel(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_SSI)); +} + +/** + * @brief Enable CRC computation on 33/17 bits + * @rmtoll CR1 CRC33_17 LL_SPI_EnableFullSizeCRC + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableFullSizeCRC(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR1, SPI_CR1_CRC33_17); +} + +/** + * @brief Disable CRC computation on 33/17 bits + * @rmtoll CR1 CRC33_17 LL_SPI_DisableFullSizeCRC + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableFullSizeCRC(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR1, SPI_CR1_CRC33_17); +} + +/** + * @brief Check if Enable CRC computation on 33/17 bits is enabled + * @rmtoll CR1 CRC33_17 LL_SPI_IsEnabledFullSizeCRC + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledFullSizeCRC(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CR1, SPI_CR1_CRC33_17) == (SPI_CR1_CRC33_17)) ? 1UL : 0UL); +} + +/** + * @brief Suspend an ongoing transfer for Master configuration + * @rmtoll CR1 CSUSP LL_SPI_SuspendMasterTransfer + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_SuspendMasterTransfer(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR1, SPI_CR1_CSUSP); +} + +/** + * @brief Start effective transfer on wire for Master configuration + * @rmtoll CR1 CSTART LL_SPI_StartMasterTransfer + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_StartMasterTransfer(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR1, SPI_CR1_CSTART); +} + +/** + * @brief Check if there is an unfinished master transfer + * @rmtoll CR1 CSTART LL_SPI_IsActiveMasterTransfer + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveMasterTransfer(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CR1, SPI_CR1_CSTART) == (SPI_CR1_CSTART)) ? 1UL : 0UL); +} + +/** + * @brief Enable Master Rx auto suspend in case of overrun + * @rmtoll CR1 MASRX LL_SPI_EnableMasterRxAutoSuspend + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableMasterRxAutoSuspend(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR1, SPI_CR1_MASRX); +} + +/** + * @brief Disable Master Rx auto suspend in case of overrun + * @rmtoll CR1 MASRX LL_SPI_DisableMasterRxAutoSuspend + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableMasterRxAutoSuspend(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR1, SPI_CR1_MASRX); +} + +/** + * @brief Check if Master Rx auto suspend is activated + * @rmtoll CR1 MASRX LL_SPI_IsEnabledMasterRxAutoSuspend + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledMasterRxAutoSuspend(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CR1, SPI_CR1_MASRX) == (SPI_CR1_MASRX)) ? 1UL : 0UL); +} + +/** + * @brief Set Underrun behavior + * @note This configuration can not be changed when SPI is enabled. + * @rmtoll CFG1 UDRCFG LL_SPI_SetUDRConfiguration + * @param SPIx SPI Instance + * @param UDRConfig This parameter can be one of the following values: + * @arg @ref LL_SPI_UDR_CONFIG_REGISTER_PATTERN + * @arg @ref LL_SPI_UDR_CONFIG_LAST_RECEIVED + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetUDRConfiguration(SPI_TypeDef *SPIx, uint32_t UDRConfig) +{ + MODIFY_REG(SPIx->CFG1, SPI_CFG1_UDRCFG, UDRConfig); +} + +/** + * @brief Get Underrun behavior + * @rmtoll CFG1 UDRCFG LL_SPI_GetUDRConfiguration + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_UDR_CONFIG_REGISTER_PATTERN + * @arg @ref LL_SPI_UDR_CONFIG_LAST_RECEIVED + */ +__STATIC_INLINE uint32_t LL_SPI_GetUDRConfiguration(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_UDRCFG)); +} + + +/** + * @brief Set Serial protocol used + * @note This configuration can not be changed when SPI is enabled. + * @rmtoll CFG2 SP LL_SPI_SetStandard + * @param SPIx SPI Instance + * @param Standard This parameter can be one of the following values: + * @arg @ref LL_SPI_PROTOCOL_MOTOROLA + * @arg @ref LL_SPI_PROTOCOL_TI + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard) +{ + MODIFY_REG(SPIx->CFG2, SPI_CFG2_SP, Standard); +} + +/** + * @brief Get Serial protocol used + * @rmtoll CFG2 SP LL_SPI_GetStandard + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_PROTOCOL_MOTOROLA + * @arg @ref LL_SPI_PROTOCOL_TI + */ +__STATIC_INLINE uint32_t LL_SPI_GetStandard(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SP)); +} + +/** + * @brief Set Clock phase + * @note This configuration can not be changed when SPI is enabled. + * This bit is not used in SPI TI mode. + * @rmtoll CFG2 CPHA LL_SPI_SetClockPhase + * @param SPIx SPI Instance + * @param ClockPhase This parameter can be one of the following values: + * @arg @ref LL_SPI_PHASE_1EDGE + * @arg @ref LL_SPI_PHASE_2EDGE + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase) +{ + MODIFY_REG(SPIx->CFG2, SPI_CFG2_CPHA, ClockPhase); +} + +/** + * @brief Get Clock phase + * @rmtoll CFG2 CPHA LL_SPI_GetClockPhase + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_PHASE_1EDGE + * @arg @ref LL_SPI_PHASE_2EDGE + */ +__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_CPHA)); +} + +/** + * @brief Set Clock polarity + * @note This configuration can not be changed when SPI is enabled. + * This bit is not used in SPI TI mode. + * @rmtoll CFG2 CPOL LL_SPI_SetClockPolarity + * @param SPIx SPI Instance + * @param ClockPolarity This parameter can be one of the following values: + * @arg @ref LL_SPI_POLARITY_LOW + * @arg @ref LL_SPI_POLARITY_HIGH + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity) +{ + MODIFY_REG(SPIx->CFG2, SPI_CFG2_CPOL, ClockPolarity); +} + +/** + * @brief Get Clock polarity + * @rmtoll CFG2 CPOL LL_SPI_GetClockPolarity + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_POLARITY_LOW + * @arg @ref LL_SPI_POLARITY_HIGH + */ +__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_CPOL)); +} + +/** + * @brief Set NSS polarity + * @note This configuration can not be changed when SPI is enabled. + * This bit is not used in SPI TI mode. + * @rmtoll CFG2 SSIOP LL_SPI_SetNSSPolarity + * @param SPIx SPI Instance + * @param NSSPolarity This parameter can be one of the following values: + * @arg @ref LL_SPI_NSS_POLARITY_LOW + * @arg @ref LL_SPI_NSS_POLARITY_HIGH + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetNSSPolarity(SPI_TypeDef *SPIx, uint32_t NSSPolarity) +{ + MODIFY_REG(SPIx->CFG2, SPI_CFG2_SSIOP, NSSPolarity); +} + +/** + * @brief Get NSS polarity + * @rmtoll CFG2 SSIOP LL_SPI_GetNSSPolarity + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_NSS_POLARITY_LOW + * @arg @ref LL_SPI_NSS_POLARITY_HIGH + */ +__STATIC_INLINE uint32_t LL_SPI_GetNSSPolarity(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SSIOP)); +} + +/** + * @brief Set Baudrate Prescaler + * @note This configuration can not be changed when SPI is enabled. + * SPI BaudRate = fPCLK/Pescaler. + * @rmtoll CFG1 MBR LL_SPI_SetBaudRatePrescaler\n + * CFG1 BPASS LL_SPI_SetBaudRatePrescaler + * @param SPIx SPI Instance + * @param Baudrate This parameter can be one of the following values: + * @arg @ref LL_SPI_BAUDRATEPRESCALER_BYPASS + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256 + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t Baudrate) +{ + MODIFY_REG(SPIx->CFG1, (SPI_CFG1_MBR | SPI_CFG1_BPASS), Baudrate); +} + +/** + * @brief Get Baudrate Prescaler + * @rmtoll CFG1 MBR LL_SPI_GetBaudRatePrescaler\n + * CFG1 BPASS LL_SPI_GetBaudRatePrescaler + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_BAUDRATEPRESCALER_BYPASS + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256 + */ +__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CFG1, (SPI_CFG1_MBR | SPI_CFG1_BPASS))); +} + +/** + * @brief Set Transfer Bit Order + * @note This configuration can not be changed when SPI is enabled. + * This bit is not used in SPI TI mode. + * @rmtoll CFG2 LSBFRST LL_SPI_SetTransferBitOrder + * @param SPIx SPI Instance + * @param BitOrder This parameter can be one of the following values: + * @arg @ref LL_SPI_LSB_FIRST + * @arg @ref LL_SPI_MSB_FIRST + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder) +{ + MODIFY_REG(SPIx->CFG2, SPI_CFG2_LSBFRST, BitOrder); +} + +/** + * @brief Get Transfer Bit Order + * @rmtoll CFG2 LSBFRST LL_SPI_GetTransferBitOrder + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_LSB_FIRST + * @arg @ref LL_SPI_MSB_FIRST + */ +__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_LSBFRST)); +} + +/** + * @brief Set Transfer Mode + * @note This configuration can not be changed when SPI is enabled except for half duplex direction + * using LL_SPI_SetHalfDuplexDirection. + * @rmtoll CR1 HDDIR LL_SPI_SetTransferDirection\n + * CFG2 COMM LL_SPI_SetTransferDirection + * @param SPIx SPI Instance + * @param TransferDirection This parameter can be one of the following values: + * @arg @ref LL_SPI_FULL_DUPLEX + * @arg @ref LL_SPI_SIMPLEX_TX + * @arg @ref LL_SPI_SIMPLEX_RX + * @arg @ref LL_SPI_HALF_DUPLEX_RX + * @arg @ref LL_SPI_HALF_DUPLEX_TX + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_HDDIR, TransferDirection & SPI_CR1_HDDIR); + MODIFY_REG(SPIx->CFG2, SPI_CFG2_COMM, TransferDirection & SPI_CFG2_COMM); +} + +/** + * @brief Get Transfer Mode + * @rmtoll CR1 HDDIR LL_SPI_GetTransferDirection\n + * CFG2 COMM LL_SPI_GetTransferDirection + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_FULL_DUPLEX + * @arg @ref LL_SPI_SIMPLEX_TX + * @arg @ref LL_SPI_SIMPLEX_RX + * @arg @ref LL_SPI_HALF_DUPLEX_RX + * @arg @ref LL_SPI_HALF_DUPLEX_TX + */ +__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(const SPI_TypeDef *SPIx) +{ + uint32_t Hddir = READ_BIT(SPIx->CR1, SPI_CR1_HDDIR); + uint32_t Comm = READ_BIT(SPIx->CFG2, SPI_CFG2_COMM); + return (Hddir | Comm); +} + +/** + * @brief Set direction for Half-Duplex Mode + * @note In master mode the MOSI pin is used and in slave mode the MISO pin is used for Half-Duplex. + * @rmtoll CR1 HDDIR LL_SPI_SetHalfDuplexDirection + * @param SPIx SPI Instance + * @param HalfDuplexDirection This parameter can be one of the following values: + * @arg @ref LL_SPI_HALF_DUPLEX_RX + * @arg @ref LL_SPI_HALF_DUPLEX_TX + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetHalfDuplexDirection(SPI_TypeDef *SPIx, uint32_t HalfDuplexDirection) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_HDDIR, HalfDuplexDirection & SPI_CR1_HDDIR); +} + +/** + * @brief Get direction for Half-Duplex Mode + * @note In master mode the MOSI pin is used and in slave mode the MISO pin is used for Half-Duplex. + * @rmtoll CR1 HDDIR LL_SPI_GetHalfDuplexDirection + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_HALF_DUPLEX_RX + * @arg @ref LL_SPI_HALF_DUPLEX_TX + */ +__STATIC_INLINE uint32_t LL_SPI_GetHalfDuplexDirection(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_HDDIR) | SPI_CFG2_COMM); +} + +/** + * @brief Set Frame Data Size + * @note This configuration can not be changed when SPI is enabled. + * @rmtoll CFG1 DSIZE LL_SPI_SetDataWidth + * @param SPIx SPI Instance + * @param DataWidth This parameter can be one of the following values: + * @arg @ref LL_SPI_DATAWIDTH_4BIT + * @arg @ref LL_SPI_DATAWIDTH_5BIT + * @arg @ref LL_SPI_DATAWIDTH_6BIT + * @arg @ref LL_SPI_DATAWIDTH_7BIT + * @arg @ref LL_SPI_DATAWIDTH_8BIT + * @arg @ref LL_SPI_DATAWIDTH_9BIT + * @arg @ref LL_SPI_DATAWIDTH_10BIT + * @arg @ref LL_SPI_DATAWIDTH_11BIT + * @arg @ref LL_SPI_DATAWIDTH_12BIT + * @arg @ref LL_SPI_DATAWIDTH_13BIT + * @arg @ref LL_SPI_DATAWIDTH_14BIT + * @arg @ref LL_SPI_DATAWIDTH_15BIT + * @arg @ref LL_SPI_DATAWIDTH_16BIT + * @arg @ref LL_SPI_DATAWIDTH_17BIT + * @arg @ref LL_SPI_DATAWIDTH_18BIT + * @arg @ref LL_SPI_DATAWIDTH_19BIT + * @arg @ref LL_SPI_DATAWIDTH_20BIT + * @arg @ref LL_SPI_DATAWIDTH_21BIT + * @arg @ref LL_SPI_DATAWIDTH_22BIT + * @arg @ref LL_SPI_DATAWIDTH_23BIT + * @arg @ref LL_SPI_DATAWIDTH_24BIT + * @arg @ref LL_SPI_DATAWIDTH_25BIT + * @arg @ref LL_SPI_DATAWIDTH_26BIT + * @arg @ref LL_SPI_DATAWIDTH_27BIT + * @arg @ref LL_SPI_DATAWIDTH_28BIT + * @arg @ref LL_SPI_DATAWIDTH_29BIT + * @arg @ref LL_SPI_DATAWIDTH_30BIT + * @arg @ref LL_SPI_DATAWIDTH_31BIT + * @arg @ref LL_SPI_DATAWIDTH_32BIT + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth) +{ + MODIFY_REG(SPIx->CFG1, SPI_CFG1_DSIZE, DataWidth); +} + +/** + * @brief Get Frame Data Size + * @rmtoll CFG1 DSIZE LL_SPI_GetDataWidth + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_DATAWIDTH_4BIT + * @arg @ref LL_SPI_DATAWIDTH_5BIT + * @arg @ref LL_SPI_DATAWIDTH_6BIT + * @arg @ref LL_SPI_DATAWIDTH_7BIT + * @arg @ref LL_SPI_DATAWIDTH_8BIT + * @arg @ref LL_SPI_DATAWIDTH_9BIT + * @arg @ref LL_SPI_DATAWIDTH_10BIT + * @arg @ref LL_SPI_DATAWIDTH_11BIT + * @arg @ref LL_SPI_DATAWIDTH_12BIT + * @arg @ref LL_SPI_DATAWIDTH_13BIT + * @arg @ref LL_SPI_DATAWIDTH_14BIT + * @arg @ref LL_SPI_DATAWIDTH_15BIT + * @arg @ref LL_SPI_DATAWIDTH_16BIT + * @arg @ref LL_SPI_DATAWIDTH_17BIT + * @arg @ref LL_SPI_DATAWIDTH_18BIT + * @arg @ref LL_SPI_DATAWIDTH_19BIT + * @arg @ref LL_SPI_DATAWIDTH_20BIT + * @arg @ref LL_SPI_DATAWIDTH_21BIT + * @arg @ref LL_SPI_DATAWIDTH_22BIT + * @arg @ref LL_SPI_DATAWIDTH_23BIT + * @arg @ref LL_SPI_DATAWIDTH_24BIT + * @arg @ref LL_SPI_DATAWIDTH_25BIT + * @arg @ref LL_SPI_DATAWIDTH_26BIT + * @arg @ref LL_SPI_DATAWIDTH_27BIT + * @arg @ref LL_SPI_DATAWIDTH_28BIT + * @arg @ref LL_SPI_DATAWIDTH_29BIT + * @arg @ref LL_SPI_DATAWIDTH_30BIT + * @arg @ref LL_SPI_DATAWIDTH_31BIT + * @arg @ref LL_SPI_DATAWIDTH_32BIT + */ +__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_DSIZE)); +} + +/** + * @brief Set threshold of FIFO that triggers a transfer event + * @note This configuration can not be changed when SPI is enabled. + * @rmtoll CFG1 FTHLV LL_SPI_SetFIFOThreshold + * @param SPIx SPI Instance + * @param Threshold This parameter can be one of the following values: + * @arg @ref LL_SPI_FIFO_TH_01DATA + * @arg @ref LL_SPI_FIFO_TH_02DATA + * @arg @ref LL_SPI_FIFO_TH_03DATA + * @arg @ref LL_SPI_FIFO_TH_04DATA + * @arg @ref LL_SPI_FIFO_TH_05DATA + * @arg @ref LL_SPI_FIFO_TH_06DATA + * @arg @ref LL_SPI_FIFO_TH_07DATA + * @arg @ref LL_SPI_FIFO_TH_08DATA + * @arg @ref LL_SPI_FIFO_TH_09DATA + * @arg @ref LL_SPI_FIFO_TH_10DATA + * @arg @ref LL_SPI_FIFO_TH_11DATA + * @arg @ref LL_SPI_FIFO_TH_12DATA + * @arg @ref LL_SPI_FIFO_TH_13DATA + * @arg @ref LL_SPI_FIFO_TH_14DATA + * @arg @ref LL_SPI_FIFO_TH_15DATA + * @arg @ref LL_SPI_FIFO_TH_16DATA + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold) +{ + MODIFY_REG(SPIx->CFG1, SPI_CFG1_FTHLV, Threshold); +} + +/** + * @brief Get threshold of FIFO that triggers a transfer event + * @rmtoll CFG1 FTHLV LL_SPI_GetFIFOThreshold + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_FIFO_TH_01DATA + * @arg @ref LL_SPI_FIFO_TH_02DATA + * @arg @ref LL_SPI_FIFO_TH_03DATA + * @arg @ref LL_SPI_FIFO_TH_04DATA + * @arg @ref LL_SPI_FIFO_TH_05DATA + * @arg @ref LL_SPI_FIFO_TH_06DATA + * @arg @ref LL_SPI_FIFO_TH_07DATA + * @arg @ref LL_SPI_FIFO_TH_08DATA + * @arg @ref LL_SPI_FIFO_TH_09DATA + * @arg @ref LL_SPI_FIFO_TH_10DATA + * @arg @ref LL_SPI_FIFO_TH_11DATA + * @arg @ref LL_SPI_FIFO_TH_12DATA + * @arg @ref LL_SPI_FIFO_TH_13DATA + * @arg @ref LL_SPI_FIFO_TH_14DATA + * @arg @ref LL_SPI_FIFO_TH_15DATA + * @arg @ref LL_SPI_FIFO_TH_16DATA + */ +__STATIC_INLINE uint32_t LL_SPI_GetFIFOThreshold(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_FTHLV)); +} + +/** + * @brief Enable CRC + * @note This configuration can not be changed when SPI is enabled. + * @rmtoll CFG1 CRCEN LL_SPI_EnableCRC + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CFG1, SPI_CFG1_CRCEN); +} + +/** + * @brief Disable CRC + * @rmtoll CFG1 CRCEN LL_SPI_DisableCRC + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CFG1, SPI_CFG1_CRCEN); +} + +/** + * @brief Check if CRC is enabled + * @rmtoll CFG1 CRCEN LL_SPI_IsEnabledCRC + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CFG1, SPI_CFG1_CRCEN) == SPI_CFG1_CRCEN) ? 1UL : 0UL); +} + +/** + * @brief Set CRC Length + * @note This configuration can not be changed when SPI is enabled. + * @rmtoll CFG1 CRCSIZE LL_SPI_SetCRCWidth + * @param SPIx SPI Instance + * @param CRCLength This parameter can be one of the following values: + * @arg @ref LL_SPI_CRC_4BIT + * @arg @ref LL_SPI_CRC_5BIT + * @arg @ref LL_SPI_CRC_6BIT + * @arg @ref LL_SPI_CRC_7BIT + * @arg @ref LL_SPI_CRC_8BIT + * @arg @ref LL_SPI_CRC_9BIT + * @arg @ref LL_SPI_CRC_10BIT + * @arg @ref LL_SPI_CRC_11BIT + * @arg @ref LL_SPI_CRC_12BIT + * @arg @ref LL_SPI_CRC_13BIT + * @arg @ref LL_SPI_CRC_14BIT + * @arg @ref LL_SPI_CRC_15BIT + * @arg @ref LL_SPI_CRC_16BIT + * @arg @ref LL_SPI_CRC_17BIT + * @arg @ref LL_SPI_CRC_18BIT + * @arg @ref LL_SPI_CRC_19BIT + * @arg @ref LL_SPI_CRC_20BIT + * @arg @ref LL_SPI_CRC_21BIT + * @arg @ref LL_SPI_CRC_22BIT + * @arg @ref LL_SPI_CRC_23BIT + * @arg @ref LL_SPI_CRC_24BIT + * @arg @ref LL_SPI_CRC_25BIT + * @arg @ref LL_SPI_CRC_26BIT + * @arg @ref LL_SPI_CRC_27BIT + * @arg @ref LL_SPI_CRC_28BIT + * @arg @ref LL_SPI_CRC_29BIT + * @arg @ref LL_SPI_CRC_30BIT + * @arg @ref LL_SPI_CRC_31BIT + * @arg @ref LL_SPI_CRC_32BIT + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength) +{ + MODIFY_REG(SPIx->CFG1, SPI_CFG1_CRCSIZE, CRCLength); +} + +/** + * @brief Get CRC Length + * @rmtoll CFG1 CRCSIZE LL_SPI_GetCRCWidth + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_CRC_4BIT + * @arg @ref LL_SPI_CRC_5BIT + * @arg @ref LL_SPI_CRC_6BIT + * @arg @ref LL_SPI_CRC_7BIT + * @arg @ref LL_SPI_CRC_8BIT + * @arg @ref LL_SPI_CRC_9BIT + * @arg @ref LL_SPI_CRC_10BIT + * @arg @ref LL_SPI_CRC_11BIT + * @arg @ref LL_SPI_CRC_12BIT + * @arg @ref LL_SPI_CRC_13BIT + * @arg @ref LL_SPI_CRC_14BIT + * @arg @ref LL_SPI_CRC_15BIT + * @arg @ref LL_SPI_CRC_16BIT + * @arg @ref LL_SPI_CRC_17BIT + * @arg @ref LL_SPI_CRC_18BIT + * @arg @ref LL_SPI_CRC_19BIT + * @arg @ref LL_SPI_CRC_20BIT + * @arg @ref LL_SPI_CRC_21BIT + * @arg @ref LL_SPI_CRC_22BIT + * @arg @ref LL_SPI_CRC_23BIT + * @arg @ref LL_SPI_CRC_24BIT + * @arg @ref LL_SPI_CRC_25BIT + * @arg @ref LL_SPI_CRC_26BIT + * @arg @ref LL_SPI_CRC_27BIT + * @arg @ref LL_SPI_CRC_28BIT + * @arg @ref LL_SPI_CRC_29BIT + * @arg @ref LL_SPI_CRC_30BIT + * @arg @ref LL_SPI_CRC_31BIT + * @arg @ref LL_SPI_CRC_32BIT + */ +__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_CRCSIZE)); +} + +/** + * @brief Set NSS Mode + * @note This configuration can not be changed when SPI is enabled. + * This bit is not used in SPI TI mode. + * @rmtoll CFG2 SSM LL_SPI_SetNSSMode\n + * CFG2 SSOE LL_SPI_SetNSSMode + * @param SPIx SPI Instance + * @param NSS This parameter can be one of the following values: + * @arg @ref LL_SPI_NSS_SOFT + * @arg @ref LL_SPI_NSS_HARD_INPUT + * @arg @ref LL_SPI_NSS_HARD_OUTPUT + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS) +{ + MODIFY_REG(SPIx->CFG2, SPI_CFG2_SSM | SPI_CFG2_SSOE, NSS); +} + +/** + * @brief Set NSS Mode + * @rmtoll CFG2 SSM LL_SPI_GetNSSMode\n + * CFG2 SSOE LL_SPI_GetNSSMode + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_NSS_SOFT + * @arg @ref LL_SPI_NSS_HARD_INPUT + * @arg @ref LL_SPI_NSS_HARD_OUTPUT + */ +__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SSM | SPI_CFG2_SSOE)); +} + +/** + * @brief Enable NSS pulse mgt + * @note This configuration can not be changed when SPI is enabled. + * This bit is not used in SPI TI mode. + * @rmtoll CFG2 SSOM LL_SPI_EnableNSSPulseMgt + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CFG2, SPI_CFG2_SSOM); +} + +/** + * @brief Disable NSS pulse mgt + * @note This configuration can not be changed when SPI is enabled. + * This bit is not used in SPI TI mode. + * @rmtoll CFG2 SSOM LL_SPI_DisableNSSPulseMgt + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CFG2, SPI_CFG2_SSOM); +} + +/** + * @brief Check if NSS pulse is enabled + * @rmtoll CFG2 SSOM LL_SPI_IsEnabledNSSPulse + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CFG2, SPI_CFG2_SSOM) == SPI_CFG2_SSOM) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup SPI_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Check if there is enough data in FIFO to read a full packet + * @rmtoll SR RXP LL_SPI_IsActiveFlag_RXP + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXP(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_RXP) == (SPI_SR_RXP)) ? 1UL : 0UL); +} + +/** + * @brief Check if there is enough space in FIFO to hold a full packet + * @rmtoll SR TXP LL_SPI_IsActiveFlag_TXP + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXP(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_TXP) == (SPI_SR_TXP)) ? 1UL : 0UL); +} + +/** + * @brief Check if there enough space in FIFO to hold a full packet, AND enough data to read a full packet + * @rmtoll SR DXP LL_SPI_IsActiveFlag_DXP + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_DXP(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_DXP) == (SPI_SR_DXP)) ? 1UL : 0UL); +} + +/** + * @brief Check that end of transfer event occurred + * @rmtoll SR EOT LL_SPI_IsActiveFlag_EOT + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_EOT(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_EOT) == (SPI_SR_EOT)) ? 1UL : 0UL); +} + +/** + * @brief Check that all required data has been filled in the fifo according to transfer size + * @rmtoll SR TXTF LL_SPI_IsActiveFlag_TXTF + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXTF(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_TXTF) == (SPI_SR_TXTF)) ? 1UL : 0UL); +} + +/** + * @brief Get Underrun error flag + * @rmtoll SR UDR LL_SPI_IsActiveFlag_UDR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_UDR(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL); +} + +/** + * @brief Get CRC error flag + * @rmtoll SR CRCE LL_SPI_IsActiveFlag_CRCERR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_CRCE) == (SPI_SR_CRCE)) ? 1UL : 0UL); +} + +/** + * @brief Get Mode fault error flag + * @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL); +} + +/** + * @brief Get Overrun error flag + * @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL); +} + +/** + * @brief Get TI Frame format error flag + * @rmtoll SR TIFRE LL_SPI_IsActiveFlag_FRE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_TIFRE) == (SPI_SR_TIFRE)) ? 1UL : 0UL); +} + +/** + * @brief Check if a suspend operation is done + * @rmtoll SR SUSP LL_SPI_IsActiveFlag_SUSP + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_SUSP(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_SUSP) == (SPI_SR_SUSP)) ? 1UL : 0UL); +} + +/** + * @brief Check if last TxFIFO or CRC frame transmission is completed + * @rmtoll SR TXC LL_SPI_IsActiveFlag_TXC + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXC(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_TXC) == (SPI_SR_TXC)) ? 1UL : 0UL); +} + +/** + * @brief Check if at least one 32-bit data is available in RxFIFO + * @rmtoll SR RXWNE LL_SPI_IsActiveFlag_RXWNE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXWNE(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_RXWNE) == (SPI_SR_RXWNE)) ? 1UL : 0UL); +} + +/** + * @brief Get number of data framed remaining in current TSIZE + * @rmtoll SR CTSIZE LL_SPI_GetRemainingDataFrames + * @param SPIx SPI Instance + * @retval 0..0xFFFF + */ +__STATIC_INLINE uint32_t LL_SPI_GetRemainingDataFrames(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_CTSIZE) >> SPI_SR_CTSIZE_Pos); +} + +/** + * @brief Get RxFIFO packing Level + * @rmtoll SR RXPLVL LL_SPI_GetRxFIFOPackingLevel + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_RX_FIFO_0PACKET + * @arg @ref LL_SPI_RX_FIFO_1PACKET + * @arg @ref LL_SPI_RX_FIFO_2PACKET + * @arg @ref LL_SPI_RX_FIFO_3PACKET + */ +__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOPackingLevel(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_RXPLVL)); +} + +/** + * @brief Clear End Of Transfer flag + * @rmtoll IFCR EOTC LL_SPI_ClearFlag_EOT + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_ClearFlag_EOT(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IFCR, SPI_IFCR_EOTC); +} + +/** + * @brief Clear TXTF flag + * @rmtoll IFCR TXTFC LL_SPI_ClearFlag_TXTF + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_ClearFlag_TXTF(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IFCR, SPI_IFCR_TXTFC); +} + +/** + * @brief Clear Underrun error flag + * @rmtoll IFCR UDRC LL_SPI_ClearFlag_UDR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_ClearFlag_UDR(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IFCR, SPI_IFCR_UDRC); +} + +/** + * @brief Clear Overrun error flag + * @rmtoll IFCR OVRC LL_SPI_ClearFlag_OVR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IFCR, SPI_IFCR_OVRC); +} + +/** + * @brief Clear CRC error flag + * @rmtoll IFCR CRCEC LL_SPI_ClearFlag_CRCERR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IFCR, SPI_IFCR_CRCEC); +} + +/** + * @brief Clear Mode fault error flag + * @rmtoll IFCR MODFC LL_SPI_ClearFlag_MODF + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IFCR, SPI_IFCR_MODFC); +} + +/** + * @brief Clear Frame format error flag + * @rmtoll IFCR TIFREC LL_SPI_ClearFlag_FRE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IFCR, SPI_IFCR_TIFREC); +} + +/** + * @brief Clear SUSP flag + * @rmtoll IFCR SUSPC LL_SPI_ClearFlag_SUSP + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_ClearFlag_SUSP(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IFCR, SPI_IFCR_SUSPC); +} + +/** + * @} + */ + +/** @defgroup SPI_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable Rx Packet available IT + * @rmtoll IER RXPIE LL_SPI_EnableIT_RXP + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIT_RXP(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_RXPIE); +} + +/** + * @brief Enable Tx Packet space available IT + * @rmtoll IER TXPIE LL_SPI_EnableIT_TXP + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIT_TXP(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_TXPIE); +} + +/** + * @brief Enable Duplex Packet available IT + * @rmtoll IER DXPIE LL_SPI_EnableIT_DXP + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIT_DXP(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_DXPIE); +} + +/** + * @brief Enable End Of Transfer IT + * @rmtoll IER EOTIE LL_SPI_EnableIT_EOT + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIT_EOT(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_EOTIE); +} + +/** + * @brief Enable TXTF IT + * @rmtoll IER TXTFIE LL_SPI_EnableIT_TXTF + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIT_TXTF(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_TXTFIE); +} + +/** + * @brief Enable Underrun IT + * @rmtoll IER UDRIE LL_SPI_EnableIT_UDR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIT_UDR(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_UDRIE); +} + +/** + * @brief Enable Overrun IT + * @rmtoll IER OVRIE LL_SPI_EnableIT_OVR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIT_OVR(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_OVRIE); +} + +/** + * @brief Enable CRC Error IT + * @rmtoll IER CRCEIE LL_SPI_EnableIT_CRCERR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIT_CRCERR(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_CRCEIE); +} + +/** + * @brief Enable TI Frame Format Error IT + * @rmtoll IER TIFREIE LL_SPI_EnableIT_FRE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIT_FRE(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_TIFREIE); +} + +/** + * @brief Enable MODF IT + * @rmtoll IER MODFIE LL_SPI_EnableIT_MODF + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIT_MODF(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->IER, SPI_IER_MODFIE); +} + +/** + * @brief Disable Rx Packet available IT + * @rmtoll IER RXPIE LL_SPI_DisableIT_RXP + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableIT_RXP(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->IER, SPI_IER_RXPIE); +} + +/** + * @brief Disable Tx Packet space available IT + * @rmtoll IER TXPIE LL_SPI_DisableIT_TXP + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableIT_TXP(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->IER, SPI_IER_TXPIE); +} + +/** + * @brief Disable Duplex Packet available IT + * @rmtoll IER DXPIE LL_SPI_DisableIT_DXP + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableIT_DXP(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->IER, SPI_IER_DXPIE); +} + +/** + * @brief Disable End Of Transfer IT + * @rmtoll IER EOTIE LL_SPI_DisableIT_EOT + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableIT_EOT(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->IER, SPI_IER_EOTIE); +} + +/** + * @brief Disable TXTF IT + * @rmtoll IER TXTFIE LL_SPI_DisableIT_TXTF + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableIT_TXTF(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->IER, SPI_IER_TXTFIE); +} + +/** + * @brief Disable Underrun IT + * @rmtoll IER UDRIE LL_SPI_DisableIT_UDR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableIT_UDR(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->IER, SPI_IER_UDRIE); +} + +/** + * @brief Disable Overrun IT + * @rmtoll IER OVRIE LL_SPI_DisableIT_OVR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableIT_OVR(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->IER, SPI_IER_OVRIE); +} + +/** + * @brief Disable CRC Error IT + * @rmtoll IER CRCEIE LL_SPI_DisableIT_CRCERR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableIT_CRCERR(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->IER, SPI_IER_CRCEIE); +} + +/** + * @brief Disable TI Frame Format Error IT + * @rmtoll IER TIFREIE LL_SPI_DisableIT_FRE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableIT_FRE(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->IER, SPI_IER_TIFREIE); +} + +/** + * @brief Disable MODF IT + * @rmtoll IER MODFIE LL_SPI_DisableIT_MODF + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableIT_MODF(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->IER, SPI_IER_MODFIE); +} + +/** + * @brief Check if Rx Packet available IT is enabled + * @rmtoll IER RXPIE LL_SPI_IsEnabledIT_RXP + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXP(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->IER, SPI_IER_RXPIE) == (SPI_IER_RXPIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if Tx Packet space available IT is enabled + * @rmtoll IER TXPIE LL_SPI_IsEnabledIT_TXP + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXP(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->IER, SPI_IER_TXPIE) == (SPI_IER_TXPIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if Duplex Packet available IT is enabled + * @rmtoll IER DXPIE LL_SPI_IsEnabledIT_DXP + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_DXP(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->IER, SPI_IER_DXPIE) == (SPI_IER_DXPIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if End Of Transfer IT is enabled + * @rmtoll IER EOTIE LL_SPI_IsEnabledIT_EOT + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_EOT(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->IER, SPI_IER_EOTIE) == (SPI_IER_EOTIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if TXTF IT is enabled + * @rmtoll IER TXTFIE LL_SPI_IsEnabledIT_TXTF + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXTF(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->IER, SPI_IER_TXTFIE) == (SPI_IER_TXTFIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if Underrun IT is enabled + * @rmtoll IER UDRIE LL_SPI_IsEnabledIT_UDR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_UDR(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->IER, SPI_IER_UDRIE) == (SPI_IER_UDRIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if Overrun IT is enabled + * @rmtoll IER OVRIE LL_SPI_IsEnabledIT_OVR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_OVR(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->IER, SPI_IER_OVRIE) == (SPI_IER_OVRIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if CRC Error IT is enabled + * @rmtoll IER CRCEIE LL_SPI_IsEnabledIT_CRCERR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_CRCERR(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->IER, SPI_IER_CRCEIE) == (SPI_IER_CRCEIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if TI Frame Format Error IT is enabled + * @rmtoll IER TIFREIE LL_SPI_IsEnabledIT_FRE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_FRE(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->IER, SPI_IER_TIFREIE) == (SPI_IER_TIFREIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if MODF IT is enabled + * @rmtoll IER MODFIE LL_SPI_IsEnabledIT_MODF + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_MODF(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->IER, SPI_IER_MODFIE) == (SPI_IER_MODFIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup SPI_LL_EF_DMA_Management DMA Management + * @{ + */ + +/** + * @brief Enable DMA Rx + * @rmtoll CFG1 RXDMAEN LL_SPI_EnableDMAReq_RX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN); +} + +/** + * @brief Disable DMA Rx + * @rmtoll CFG1 RXDMAEN LL_SPI_DisableDMAReq_RX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN); +} + +/** + * @brief Check if DMA Rx is enabled + * @rmtoll CFG1 RXDMAEN LL_SPI_IsEnabledDMAReq_RX + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN) == (SPI_CFG1_RXDMAEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable DMA Tx + * @rmtoll CFG1 TXDMAEN LL_SPI_EnableDMAReq_TX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN); +} + +/** + * @brief Disable DMA Tx + * @rmtoll CFG1 TXDMAEN LL_SPI_DisableDMAReq_TX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN); +} + +/** + * @brief Check if DMA Tx is enabled + * @rmtoll CFG1 TXDMAEN LL_SPI_IsEnabledDMAReq_TX + * @param SPIx SPI Instance + * @retval State of bit (1 or 0) + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN) == (SPI_CFG1_TXDMAEN)) ? 1UL : 0UL); +} +/** + * @brief Get the data register address used for DMA transfer + * @rmtoll TXDR TXDR LL_SPI_DMA_GetTxRegAddr + * @param SPIx SPI Instance + * @retval Address of data register + */ +__STATIC_INLINE uint32_t LL_SPI_DMA_GetTxRegAddr(const SPI_TypeDef *SPIx) +{ + return (uint32_t) &(SPIx->TXDR); +} + +/** + * @brief Get the data register address used for DMA transfer + * @rmtoll RXDR RXDR LL_SPI_DMA_GetRxRegAddr + * @param SPIx SPI Instance + * @retval Address of data register + */ +__STATIC_INLINE uint32_t LL_SPI_DMA_GetRxRegAddr(const SPI_TypeDef *SPIx) +{ + return (uint32_t) &(SPIx->RXDR); +} +/** + * @} + */ + +/** @defgroup SPI_LL_EF_DATA_Management DATA_Management + * @{ + */ + +/** + * @brief Read Data Register + * @rmtoll RXDR . LL_SPI_ReceiveData8 + * @param SPIx SPI Instance + * @retval 0..0xFF + */ +__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx) /* Derogation MISRAC2012-Rule-8.13 */ +{ + return (*((__IO uint8_t *)&SPIx->RXDR)); +} + +/** + * @brief Read Data Register + * @rmtoll RXDR . LL_SPI_ReceiveData16 + * @param SPIx SPI Instance + * @retval 0..0xFFFF + */ +__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx) /* Derogation MISRAC2012-Rule-8.13 */ +{ +#if defined (__GNUC__) + __IO uint16_t *spirxdr = (__IO uint16_t *)(&(SPIx->RXDR)); + return (*spirxdr); +#else + return (*((__IO uint16_t *)&SPIx->RXDR)); +#endif /* __GNUC__ */ +} + +/** + * @brief Read Data Register + * @rmtoll RXDR . LL_SPI_ReceiveData32 + * @param SPIx SPI Instance + * @retval 0..0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_SPI_ReceiveData32(SPI_TypeDef *SPIx) /* Derogation MISRAC2012-Rule-8.13 */ +{ + return (*((__IO uint32_t *)&SPIx->RXDR)); +} + +/** + * @brief Write Data Register + * @rmtoll TXDR . LL_SPI_TransmitData8 + * @param SPIx SPI Instance + * @param TxData 0..0xFF + * @retval None + */ +__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData) +{ + *((__IO uint8_t *)&SPIx->TXDR) = TxData; +} + +/** + * @brief Write Data Register + * @rmtoll TXDR . LL_SPI_TransmitData16 + * @param SPIx SPI Instance + * @param TxData 0..0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) +{ +#if defined (__GNUC__) + __IO uint16_t *spitxdr = ((__IO uint16_t *)&SPIx->TXDR); + *spitxdr = TxData; +#else + *((__IO uint16_t *)&SPIx->TXDR) = TxData; +#endif /* __GNUC__ */ +} + +/** + * @brief Write Data Register + * @rmtoll TXDR . LL_SPI_TransmitData32 + * @param SPIx SPI Instance + * @param TxData 0..0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_SPI_TransmitData32(SPI_TypeDef *SPIx, uint32_t TxData) +{ + *((__IO uint32_t *)&SPIx->TXDR) = TxData; +} + +/** + * @brief Set polynomial for CRC calcul + * @rmtoll CRCPOLY CRCPOLY LL_SPI_SetCRCPolynomial + * @param SPIx SPI Instance + * @param CRCPoly 0..0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly) +{ + WRITE_REG(SPIx->CRCPOLY, CRCPoly); +} + +/** + * @brief Get polynomial for CRC calcul + * @rmtoll CRCPOLY CRCPOLY LL_SPI_GetCRCPolynomial + * @param SPIx SPI Instance + * @retval 0..0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_REG(SPIx->CRCPOLY)); +} + +/** + * @brief Set the underrun pattern + * @rmtoll UDRDR UDRDR LL_SPI_SetUDRPattern + * @param SPIx SPI Instance + * @param Pattern 0..0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetUDRPattern(SPI_TypeDef *SPIx, uint32_t Pattern) +{ + WRITE_REG(SPIx->UDRDR, Pattern); +} + +/** + * @brief Get the underrun pattern + * @rmtoll UDRDR UDRDR LL_SPI_GetUDRPattern + * @param SPIx SPI Instance + * @retval 0..0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_SPI_GetUDRPattern(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_REG(SPIx->UDRDR)); +} + +/** + * @brief Get Rx CRC + * @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC + * @param SPIx SPI Instance + * @retval 0..0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_REG(SPIx->RXCRC)); +} + +/** + * @brief Get Tx CRC + * @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC + * @param SPIx SPI Instance + * @retval 0..0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_REG(SPIx->TXCRC)); +} + +/** + * @} + */ + +/** @defgroup SPI_LL_AutonomousMode Configuration functions related to Autonomous mode feature + * @{ + */ + +/** + * @brief Enable Selected Trigger + * @rmtoll AUTOCR TRIGEN LL_SPI_Enable_SelectedTrigger + * @param SPIx SPI Instance. + * @retval None + */ +__STATIC_INLINE void LL_SPI_Enable_SelectedTrigger(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->AUTOCR, SPI_AUTOCR_TRIGEN); +} + +/** + * @brief Disable Selected Trigger + * @rmtoll AUTOCR TRIGEN LL_SPI_Disable_SelectedTrigger + * @param SPIx SPI Instance. + * @retval None + */ +__STATIC_INLINE void LL_SPI_Disable_SelectedTrigger(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->AUTOCR, SPI_AUTOCR_TRIGEN); +} + +/** + * @brief Indicate if selected Trigger is disabled or enabled + * @rmtoll AUTOCR TRIGEN LL_SPI_IsEnabled_SelectedTrigger + * @param SPIx SPI Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabled_SelectedTrigger(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->AUTOCR, SPI_AUTOCR_TRIGEN) == (SPI_AUTOCR_TRIGEN)) ? 1UL : 0UL); +} + +/** + * @brief Set the trigger polarity + * @rmtoll AUTOCR TRIGPOL LL_SPI_SetTriggerPolarity + * @param SPIx SPI Instance. + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_SPI_TRIG_POLARITY_RISING + * @arg @ref LL_SPI_TRIG_POLARITY_FALLING + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetTriggerPolarity(SPI_TypeDef *SPIx, uint32_t Polarity) +{ + MODIFY_REG(SPIx->AUTOCR, SPI_AUTOCR_TRIGPOL, Polarity); +} + +/** + * @brief Get the trigger polarity + * @rmtoll AUTOCR TRIGPOL LL_SPI_GetTriggerPolarity + * @param SPIx SPI Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_TRIG_POLARITY_RISING + * @arg @ref LL_SPI_TRIG_POLARITY_FALLING + */ +__STATIC_INLINE uint32_t LL_SPI_GetTriggerPolarity(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->AUTOCR, SPI_AUTOCR_TRIGPOL)); +} + +/** + * @brief Set the selected trigger + * @rmtoll AUTOCR TRIGSEL LL_SPI_SetSelectedTrigger + * @param SPIx SPI Instance. + * @param Trigger This parameter can be one of the following values: + * @arg @ref LL_SPI_GRP1_GPDMA_CH0_TCF_TRG + * @arg @ref LL_SPI_GRP1_GPDMA_CH1_TCF_TRG + * @arg @ref LL_SPI_GRP1_GPDMA_CH2_TCF_TRG + * @arg @ref LL_SPI_GRP1_GPDMA_CH3_TCF_TRG + * @arg @ref LL_SPI_GRP1_EXTI4_TRG + * @arg @ref LL_SPI_GRP1_EXTI9_TRG + * @arg @ref LL_SPI_GRP1_LPTIM1_CH1_TRG + * @arg @ref LL_SPI_GRP1_LPTIM2_CH1_TRG + * @arg @ref LL_SPI_GRP1_COMP1_TRG + * @arg @ref LL_SPI_GRP1_COMP2_TRG + * @arg @ref LL_SPI_GRP1_RTC_ALRA_TRG + * @arg @ref LL_SPI_GRP1_RTC_WUT_TRG + * @arg @ref LL_SPI_GRP2_GPDMA_CH0_TCF_TRG + * @arg @ref LL_SPI_GRP2_GPDMA_CH1_TCF_TRG + * @arg @ref LL_SPI_GRP2_GPDMA_CH2_TCF_TRG + * @arg @ref LL_SPI_GRP2_GPDMA_CH3_TCF_TRG + * @arg @ref LL_SPI_GRP2_EXTI4_TRG + * @arg @ref LL_SPI_GRP2_EXTI8_TRG + * @arg @ref LL_SPI_GRP2_LPTIM1_CH1_TRG + * @arg @ref LL_SPI_GRP2_COMP1_TRG + * @arg @ref LL_SPI_GRP2_RTC_ALRA_TRG + * @arg @ref LL_SPI_GRP2_RTC_WUT_TRG + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetSelectedTrigger(SPI_TypeDef *SPIx, uint32_t Trigger) +{ + MODIFY_REG(SPIx->AUTOCR, SPI_AUTOCR_TRIGSEL, (Trigger & SPI_AUTOCR_TRIGSEL_Msk)); +} + +/** + * @brief Get the selected trigger + * @rmtoll AUTOCR TRIGSEL LL_SPI_GetSelectedTrigger + * @param SPIx SPI Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_GRP1_GPDMA_CH0_TCF_TRG + * @arg @ref LL_SPI_GRP1_GPDMA_CH1_TCF_TRG + * @arg @ref LL_SPI_GRP1_GPDMA_CH2_TCF_TRG + * @arg @ref LL_SPI_GRP1_GPDMA_CH3_TCF_TRG + * @arg @ref LL_SPI_GRP1_EXTI4_TRG + * @arg @ref LL_SPI_GRP1_EXTI9_TRG + * @arg @ref LL_SPI_GRP1_LPTIM1_CH1_TRG + * @arg @ref LL_SPI_GRP1_LPTIM2_CH1_TRG + * @arg @ref LL_SPI_GRP1_COMP1_TRG + * @arg @ref LL_SPI_GRP1_COMP2_TRG + * @arg @ref LL_SPI_GRP1_RTC_ALRA_TRG + * @arg @ref LL_SPI_GRP1_RTC_WUT_TRG + * @arg @ref LL_SPI_GRP2_GPDMA_CH0_TCF_TRG + * @arg @ref LL_SPI_GRP2_GPDMA_CH1_TCF_TRG + * @arg @ref LL_SPI_GRP2_GPDMA_CH2_TCF_TRG + * @arg @ref LL_SPI_GRP2_GPDMA_CH3_TCF_TRG + * @arg @ref LL_SPI_GRP2_EXTI4_TRG + * @arg @ref LL_SPI_GRP2_EXTI8_TRG + * @arg @ref LL_SPI_GRP2_LPTIM1_CH1_TRG + * @arg @ref LL_SPI_GRP2_COMP1_TRG + * @arg @ref LL_SPI_GRP2_RTC_ALRA_TRG + * @arg @ref LL_SPI_GRP2_RTC_WUT_TRG + */ +__STATIC_INLINE uint32_t LL_SPI_GetSelectedTrigger(const SPI_TypeDef *SPIx) +{ +#if defined(LL_SPI_TRIG_GRP1) + if (IS_LL_SPI_GRP2_INSTANCE(SPIx)) + { + return (uint32_t)((READ_BIT(SPIx->AUTOCR, SPI_AUTOCR_TRIGSEL) | LL_SPI_TRIG_GRP2)); + } + else + { + return (uint32_t)((READ_BIT(SPIx->AUTOCR, SPI_AUTOCR_TRIGSEL) | LL_SPI_TRIG_GRP1)); + } +#else + return (uint32_t)((READ_BIT(SPIx->AUTOCR, SPI_AUTOCR_TRIGSEL) | LL_SPI_TRIG_GRP2)); +#endif /* LL_SPI_TRIG_GRP1 */ +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_SPI_DeInit(const SPI_TypeDef *SPIx); +ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct); +void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ +/** + * @} + */ +/** + * @} + */ + + +#endif /* defined(SPI1) || defined(SPI3) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WBAxx_LL_SPI_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_system.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_system.h new file mode 100644 index 0000000000..5ceb48622b --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_system.h @@ -0,0 +1,1102 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_ll_system.h + * @author MCD Application Team + * @brief Header file of SYSTEM LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LL SYSTEM driver contains a set of generic APIs that can be + used by user: + (+) Some of the FLASH features need to be handled in the SYSTEM file. + (+) Access to DBGCMU registers + (+) Access to SYSCFG registers + (+) Access to VREFBUF registers (not available on all devices) + @endverbatim + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_LL_SYSTEM_H +#define STM32WBAxx_LL_SYSTEM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx.h" + +/** @addtogroup STM32WBAxx_LL_Driver + * @{ + */ + +#if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) + +/** @defgroup SYSTEM_LL SYSTEM + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup SYSTEM_LL_Private_Constants SYSTEM LL Private Constants + * @{ + */ + +/** + * @brief Power-down in Run mode Flash key + */ +#define FLASH_PDKEY1_1 0x04152637U /*!< Flash power down key1 */ +#define FLASH_PDKEY1_2 0xFAFBFCFDU /*!< Flash power down key2: used with FLASH_PDKEYR + to unlock the PDREQ bit in FLASH_ACR */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants + * @{ + */ + +/** @defgroup SYSTEM_LL_EC_CS1 SYSCFG SYSCFG Vdd compensation cell Code selection + * @{ + */ +#define LL_SYSCFG_VDD_CELL_CODE 0U /*VDD I/Os code from the cell (available in the SYSCFG_CCVR)*/ +#define LL_SYSCFG_VDD_REGISTER_CODE SYSCFG_CCCSR_CS1 /*VDD I/Os code from the SYSCFG compensation cell code register (SYSCFG_CCCR)*/ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_ERASE_MEMORIES_STATUS SYSCFG MEMORIES ERASE + * @{ + */ +#define LL_SYSCFG_MEMORIES_ERASE_ON_GOING 0U /*Memory erase on going*/ +#define LL_SYSCFG_MEMORIES_ERASE_ENDED SYSCFG_MESR_MCLR /*Memory erase done */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS + * @{ + */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_PA6 SYSCFG_CFGR1_PA6_FMP /*!< Enable Fast Mode Plus on PA6 */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_PA7 SYSCFG_CFGR1_PA7_FMP /*!< Enable Fast Mode Plus on PA7 */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_PA15 SYSCFG_CFGR1_PA15_FMP /*!< Enable Fast Mode Plus on PA15 */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_PB3 SYSCFG_CFGR1_PB3_FMP /*!< Enable Fast Mode Plus on PB3 */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK + * @{ + */ +#define LL_SYSCFG_TIMBREAK_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal + with Break Input of TIM1/16/17 */ +#define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection + with TIM1/16/17 Break Input and also + the PVDE and PLS bits of the Power Control Interface */ +#define LL_SYSCFG_TIMBREAK_SRAM_ECC_LOCK SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM ECC double error signal + with Break Input of TIM1/16/17 */ +#define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM33 + with Break Input of TIM1/16/17 */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_SECURE_ATTRIBUTES Secure attributes + * @note Only available when system implements security (TZEN=1) + * @{ + */ +#define LL_SYSCFG_CLOCK_SEC SYSCFG_SECCFGR_SYSCFGSEC /*!< SYSCFG clock configuration secure-only access */ +#define LL_SYSCFG_CLOCK_NSEC 0U /*!< SYSCFG clock configuration secure/non-secure access */ +#define LL_SYSCFG_CLASSB_SEC SYSCFG_SECCFGR_CLASSBSEC /*!< Class B configuration secure-only access */ +#define LL_SYSCFG_CLASSB_NSEC 0U /*!< Class B configuration secure/non-secure access */ +#define LL_SYSCFG_FPU_SEC SYSCFG_SECCFGR_FPUSEC /*!< FPU configuration secure-only access */ +#define LL_SYSCFG_FPU_NSEC 0U /*!< FPU configuration secure/non-secure access */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP + * @{ + */ +#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1LFZR_DBG_TIM2_STOP /*!< The counter clock of TIM2 is stopped when the core is halted*/ +#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1LFZR_DBG_TIM3_STOP /*!< The counter clock of TIM3 is stopped when the core is halted*/ +#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1LFZR_DBG_WWDG_STOP /*!< The window watchdog counter clock is stopped when the core is halted*/ +#define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1LFZR_DBG_IWDG_STOP /*!< The independent watchdog counter clock is stopped when the core is halted*/ +#if defined(I2C1) +#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1LFZR_DBG_I2C1_STOP /*!< The I2C1 SMBus timeout is frozen*/ +#endif /* I2C1 */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_APB1_GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP + * @{ + */ +#if defined(LPTIM2) +#define LL_DBGMCU_APB1_GRP2_LPTIM2_STOP DBGMCU_APB1HFZR_DBG_LPTIM2_STOP /*!< The counter clock of LPTIM2 is stopped when the core is halted*/ +#endif /* LPTIM2 */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP + * @{ + */ +#define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2FZR_DBG_TIM1_STOP /*!< The counter clock of TIM1 is stopped when the core is halted*/ +#define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2FZR_DBG_TIM16_STOP /*!< The counter clock of TIM16 is stopped when the core is halted*/ +#define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2FZR_DBG_TIM17_STOP /*!< The counter clock of TIM17 is stopped when the core is halted*/ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_APB7_GRP1_STOP_IP DBGMCU APB7 GRP1 STOP IP + * @{ + */ +#define LL_DBGMCU_APB7_GRP1_I2C3_STOP DBGMCU_APB7FZR_DBG_I2C3_STOP /*!< The counter clock of I2C3 is stopped when the core is halted*/ +#define LL_DBGMCU_APB7_GRP1_LPTIM1_STOP DBGMCU_APB7FZR_DBG_LPTIM1_STOP /*!< The counter clock of LPTIM1 is stopped when the core is halted*/ +#define LL_DBGMCU_APB7_GRP1_RTC_STOP DBGMCU_APB7FZR_DBG_RTC_STOP /*!< The counter clock of RTC is stopped when the core is halted*/ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY + * @{ + */ +#define LL_FLASH_LATENCY_0 0 /*!< FLASH Zero wait state */ +#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One wait state */ +#define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two wait states */ +#define LL_FLASH_LATENCY_3 (FLASH_ACR_LATENCY_1 | FLASH_ACR_LATENCY_0) /*!< FLASH Three wait states */ +#define LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_2 /*!< FLASH Four wait states */ +#define LL_FLASH_LATENCY_5 (FLASH_ACR_LATENCY_2 | FLASH_ACR_LATENCY_0) /*!< FLASH Five wait state */ +#define LL_FLASH_LATENCY_6 (FLASH_ACR_LATENCY_2 | FLASH_ACR_LATENCY_1) /*!< FLASH Six wait state */ +#define LL_FLASH_LATENCY_7 (FLASH_ACR_LATENCY_2 | FLASH_ACR_LATENCY_1 | FLASH_ACR_LATENCY_0) /*!< FLASH Seven wait states */ +#define LL_FLASH_LATENCY_8 FLASH_ACR_LATENCY_3 /*!< FLASH Eight wait states */ +#define LL_FLASH_LATENCY_9 (FLASH_ACR_LATENCY_3 | FLASH_ACR_LATENCY_0) /*!< FLASH Nine wait states */ +#define LL_FLASH_LATENCY_10 (FLASH_ACR_LATENCY_3 | FLASH_ACR_LATENCY_1) /*!< FLASH Ten wait state */ +#define LL_FLASH_LATENCY_11 (FLASH_ACR_LATENCY_3 | FLASH_ACR_LATENCY_1 | FLASH_ACR_LATENCY_0) /*!< FLASH Eleven wait state */ +#define LL_FLASH_LATENCY_12 (FLASH_ACR_LATENCY_3 | FLASH_ACR_LATENCY_2) /*!< FLASH Twelve wait states */ +#define LL_FLASH_LATENCY_13 (FLASH_ACR_LATENCY_3 | FLASH_ACR_LATENCY_2 | FLASH_ACR_LATENCY_0) /*!< FLASH Thirteen wait states */ +#define LL_FLASH_LATENCY_14 (FLASH_ACR_LATENCY_3 | FLASH_ACR_LATENCY_2 | FLASH_ACR_LATENCY_1) /*!< FLASH Fourteen wait states */ +#define LL_FLASH_LATENCY_15 FLASH_ACR_LATENCY /*!< FLASH Fifteen wait states */ +/** + * @} + */ + + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions + * @{ + */ + +/** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG + * @{ + */ + +/** + * @brief Enable I/O analog switch voltage booster. + * @note When voltage booster is enabled, I/O analog switches are supplied + * by a dedicated voltage booster, from VDD power domain. This is + * the recommended configuration with low VDDA voltage operation. + * @note The I/O analog switch voltage booster is relevant for peripherals + * using I/O in analog input: ADC, COMP, OPAMP. + * However, COMP and OPAMP inputs have a high impedance and + * voltage booster do not impact performance significantly. + * Therefore, the voltage booster is mainly intended for + * usage with ADC. + * @rmtoll SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_EnableAnalogBooster + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableAnalogBooster(void) +{ + SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN); +} + +/** + * @brief Disable I/O analog switch voltage booster. + * @note When voltage booster is enabled, I/O analog switches are supplied + * by a dedicated voltage booster, from VDD power domain. This is + * the recommended configuration with low VDDA voltage operation. + * @note The I/O analog switch voltage booster is relevant for peripherals + * using I/O in analog input: ADC, COMP, OPAMP. + * However, COMP and OPAMP inputs have a high impedance and + * voltage booster do not impact performance significantly. + * Therefore, the voltage booster is mainly intended for + * usage with ADC. + * @rmtoll SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_DisableAnalogBooster + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableAnalogBooster(void) +{ + CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN); +} + +/** + * @brief Enable the I2C fast mode plus driving capability. + * @rmtoll SYSCFG_CFGR1 I2C_PABx_FMP LL_SYSCFG_EnableFastModePlus\n + * SYSCFG_CFGR1 I2Cx_FMP LL_SYSCFG_EnableFastModePlus + * @param ConfigFastModePlus This parameter can be a combination of the following values: + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA6 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA7 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA15 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB3 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus) +{ + SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus); +} + +/** + * @brief Disable the I2C fast mode plus driving capability. + * @rmtoll SYSCFG_CFGR1 I2C_PBx_FMP LL_SYSCFG_DisableFastModePlus\n + * SYSCFG_CFGR1 I2Cx_FMP LL_SYSCFG_DisableFastModePlus + * @param ConfigFastModePlus This parameter can be a combination of the following values: + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA6 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA7 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA15 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB3 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus) +{ + CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus); +} + +/** + * @brief Enable Floating Point Unit Invalid operation Interrupt + * @rmtoll SYSCFG_FPUIMR FPU_IE_0 LL_SYSCFG_EnableIT_FPU_IOC + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IOC(void) +{ + SET_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_0); +} + +/** + * @brief Enable Floating Point Unit Divide-by-zero Interrupt + * @rmtoll SYSCFG_FPUIMR FPU_IE_1 LL_SYSCFG_EnableIT_FPU_DZC + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_DZC(void) +{ + SET_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_1); +} + +/** + * @brief Enable Floating Point Unit Underflow Interrupt + * @rmtoll SYSCFG_FPUIMR FPU_IE_2 LL_SYSCFG_EnableIT_FPU_UFC + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_UFC(void) +{ + SET_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_2); +} + +/** + * @brief Enable Floating Point Unit Overflow Interrupt + * @rmtoll SYSCFG_FPUIMR FPU_IE_3 LL_SYSCFG_EnableIT_FPU_OFC + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_OFC(void) +{ + SET_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_3); +} + +/** + * @brief Enable Floating Point Unit Input denormal Interrupt + * @rmtoll SYSCFG_FPUIMR FPU_IE_4 LL_SYSCFG_EnableIT_FPU_IDC + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IDC(void) +{ + SET_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_4); +} + +/** + * @brief Enable Floating Point Unit Inexact Interrupt + * @rmtoll SYSCFG_FPUIMR FPU_IE_5 LL_SYSCFG_EnableIT_FPU_IXC + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IXC(void) +{ + SET_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_5); +} + +/** + * @brief Disable Floating Point Unit Invalid operation Interrupt + * @rmtoll SYSCFG_FPUIMR FPU_IE_0 LL_SYSCFG_DisableIT_FPU_IOC + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IOC(void) +{ + CLEAR_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_0); +} + +/** + * @brief Disable Floating Point Unit Divide-by-zero Interrupt + * @rmtoll SYSCFG_FPUIMR FPU_IE_1 LL_SYSCFG_DisableIT_FPU_DZC + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_DZC(void) +{ + CLEAR_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_1); +} + +/** + * @brief Disable Floating Point Unit Underflow Interrupt + * @rmtoll SYSCFG_FPUIMR FPU_IE_2 LL_SYSCFG_DisableIT_FPU_UFC + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_UFC(void) +{ + CLEAR_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_2); +} + +/** + * @brief Disable Floating Point Unit Overflow Interrupt + * @rmtoll SYSCFG_FPUIMR FPU_IE_3 LL_SYSCFG_DisableIT_FPU_OFC + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_OFC(void) +{ + CLEAR_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_3); +} + +/** + * @brief Disable Floating Point Unit Input denormal Interrupt + * @rmtoll SYSCFG_FPUIMR FPU_IE_4 LL_SYSCFG_DisableIT_FPU_IDC + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IDC(void) +{ + CLEAR_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_4); +} + +/** + * @brief Disable Floating Point Unit Inexact Interrupt + * @rmtoll SYSCFG_FPUIMR FPU_IE_5 LL_SYSCFG_DisableIT_FPU_IXC + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IXC(void) +{ + CLEAR_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_5); +} + +/** + * @brief Check if Floating Point Unit Invalid operation Interrupt source is enabled or disabled. + * @rmtoll SYSCFG_FPUIMR FPU_IE_0 LL_SYSCFG_IsEnabledIT_FPU_IOC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IOC(void) +{ + return ((READ_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_0) == SYSCFG_FPUIMR_FPU_IE_0) ? 1UL : 0UL); +} + +/** + * @brief Check if Floating Point Unit Divide-by-zero Interrupt source is enabled or disabled. + * @rmtoll SYSCFG_FPUIMR FPU_IE_1 LL_SYSCFG_IsEnabledIT_FPU_DZC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_DZC(void) +{ + return ((READ_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_1) == SYSCFG_FPUIMR_FPU_IE_1) ? 1UL : 0UL); +} + +/** + * @brief Check if Floating Point Unit Underflow Interrupt source is enabled or disabled. + * @rmtoll SYSCFG_FPUIMR FPU_IE_2 LL_SYSCFG_IsEnabledIT_FPU_UFC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_UFC(void) +{ + return ((READ_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_2) == SYSCFG_FPUIMR_FPU_IE_2) ? 1UL : 0UL); +} + +/** + * @brief Check if Floating Point Unit Overflow Interrupt source is enabled or disabled. + * @rmtoll SYSCFG_FPUIMR FPU_IE_3 LL_SYSCFG_IsEnabledIT_FPU_OFC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_OFC(void) +{ + return ((READ_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_3) == SYSCFG_FPUIMR_FPU_IE_3) ? 1UL : 0UL); +} + +/** + * @brief Check if Floating Point Unit Input denormal Interrupt source is enabled or disabled. + * @rmtoll SYSCFG_FPUIMR FPU_IE_4 LL_SYSCFG_IsEnabledIT_FPU_IDC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IDC(void) +{ + return ((READ_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_4) == SYSCFG_FPUIMR_FPU_IE_4) ? 1UL : 0UL); +} + +/** + * @brief Check if Floating Point Unit Inexact Interrupt source is enabled or disabled. + * @rmtoll SYSCFG_FPUIMR FPU_IE_5 LL_SYSCFG_IsEnabledIT_FPU_IXC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IXC(void) +{ + return ((READ_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_5) == SYSCFG_FPUIMR_FPU_IE_5) ? 1UL : 0UL); +} + +/** + * @brief Set connections to TIM1/8/15/16/17 Break inputs + * @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_SetTIMBreakInputs\n + * SYSCFG_CFGR2 SPL LL_SYSCFG_SetTIMBreakInputs\n + * SYSCFG_CFGR2 PVDL LL_SYSCFG_SetTIMBreakInputs\n + * SYSCFG_CFGR2 ECCL LL_SYSCFG_SetTIMBreakInputs + * @param Break This parameter can be a combination of the following values: + * @arg @ref LL_SYSCFG_TIMBREAK_ECC + * @arg @ref LL_SYSCFG_TIMBREAK_PVD + * @arg @ref LL_SYSCFG_TIMBREAK_SRAM_ECC_LOCK + * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break) +{ + MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL, Break); +} + +/** + * @brief Get connections to TIM1/8/15/16/17 Break inputs + * @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_GetTIMBreakInputs\n + * SYSCFG_CFGR2 SPL LL_SYSCFG_GetTIMBreakInputs\n + * SYSCFG_CFGR2 PVDL LL_SYSCFG_GetTIMBreakInputs\n + * SYSCFG_CFGR2 ECCL LL_SYSCFG_GetTIMBreakInputs + * @retval Returned value can be can be a combination of the following values: + * @arg @ref LL_SYSCFG_TIMBREAK_ECC + * @arg @ref LL_SYSCFG_TIMBREAK_PVD + * @arg @ref LL_SYSCFG_TIMBREAK_SRAM_ECC_LOCK + * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL)); +} + +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EF_SYSCFG_Secure_Management Secure Management + * @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + * @brief Configure Secure mode + * @note Only available from secure state when system implements security (TZEN=1) + * @rmtoll SECCFGR SYSCFGSEC LL_SYSCFG_ConfigSecure\n + * SECCFGR CLASSBSEC LL_SYSCFG_ConfigSecure\n + * SECCFGR FPUSEC LL_SYSCFG_ConfigSecure + * @param Configuration This parameter shall be the full combination + * of the following values: + * @arg @ref LL_SYSCFG_CLOCK_SEC or LL_SYSCFG_CLOCK_NSEC + * @arg @ref LL_SYSCFG_CLASSB_SEC or LL_SYSCFG_CLASSB_NSEC + * @arg @ref LL_SYSCFG_FPU_SEC or LL_SYSCFG_FPU_NSEC + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_ConfigSecure(uint32_t Configuration) +{ + WRITE_REG(SYSCFG->SECCFGR, Configuration); +} + +#endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */ + +/** + * @brief Get Secure mode configuration + * @note Only available when system implements security (TZEN=1) + * @rmtoll SECCFGR SYSCFGSEC LL_SYSCFG_ConfigSecure\n + * SECCFGR CLASSBSEC LL_SYSCFG_ConfigSecure\n + * SECCFGR FPUSEC LL_SYSCFG_ConfigSecure + * @retval Returned value is the combination of the following values: + * @arg @ref LL_SYSCFG_CLOCK_SEC or LL_SYSCFG_CLOCK_NSEC + * @arg @ref LL_SYSCFG_CLASSB_SEC or LL_SYSCFG_CLASSB_NSEC + * @arg @ref LL_SYSCFG_FPU_SEC or LL_SYSCFG_FPU_NSEC + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetConfigSecure(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->SECCFGR, 0xBU)); +} + +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EF_SYSCFG_ERASE_MEMORIE_STATUS SYSCFG ERASE MEMORIE STATUS + * @{ + */ + +/** + * @brief Clear Status of End of Erase for ICACHE and PKA RAMs + * @rmtoll MESR IPMEE LL_SYSCFG_ClearEraseEndStatus + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_ClearEraseEndStatus(void) +{ + SET_BIT(SYSCFG->MESR, SYSCFG_MESR_IPMEE); +} + +/** + * @brief Get Status of End of Erase for ICACHE and PKA RAMs + * @rmtoll MESR IPMEE LL_SYSCFG_GetEraseEndStatus + * @retval Returned value can be one of the following values: + * @arg LL_SYSCFG_MEMORIES_ERASE_ON_GOING : Erase of memories not yet done + * @arg LL_SYSCFG_MEMORIES_ERASE_ENDED: Erase of memories ended + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetEraseEndStatus(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->MESR, SYSCFG_MESR_IPMEE)); +} + + +/** + * @brief Clear Status of End of Erase after reset for SRAM2, BKPRAM, ICACHE, DCACHE,PKA rams + * @rmtoll MESR MCLR LL_SYSCFG_ClearEraseAfterResetStatus + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_ClearEraseAfterResetStatus(void) +{ + SET_BIT(SYSCFG->MESR, SYSCFG_MESR_MCLR); +} + +/** + * @brief Get Status of End of Erase after reset for SRAM2, BKPRAM, ICACHE, DCACHE,PKA rams + * @rmtoll MESR MCLR LL_SYSCFG_GetEraseAfterResetStatus + * @retval Returned value can be one of the following values: + * @arg LL_SYSCFG_MEMORIES_ERASE_ON_GOING : Erase of memories not yet done + * @arg LL_SYSCFG_MEMORIES_ERASE_ENDED: Erase of memories ended + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetEraseAfterResetStatus(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->MESR, SYSCFG_MESR_MCLR)); +} +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EF_SYSCFG_COMPENSATION SYSCFG COMPENSATION + * @{ + */ + +/** + * @brief Get the compensation cell value of the GPIO PMOS transistor supplied by VDD + * @rmtoll CCVR PCV1 LL_SYSCFG_GetPMOSVddCompensationValue + * @retval Returned value is the PMOS compensation cell + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSVddCompensationValue(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_PCV1)); +} + +/** + * @brief Get the compensation cell value of the GPIO NMOS transistor supplied by VDD + * @rmtoll CCVR NCV1 LL_SYSCFG_GetNMOSVddCompensationValue + * @retval Returned value is the NMOS compensation cell + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddCompensationValue(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_NCV1)); +} + + +/** + * @brief Set the compensation cell code of the GPIO PMOS transistor supplied by VDD + * @rmtoll CCCR PCC1 LL_SYSCFG_SetPMOSVddCompensationCode + * @param PMOSCode PMOS compensation code + * This code is applied to the PMOS compensation cell when the CS1 bit of the + * SYSCFG_CMPCR is set + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetPMOSVddCompensationCode(uint32_t PMOSCode) +{ + MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_PCC1, PMOSCode << SYSCFG_CCCR_PCC1_Pos); +} + +/** + * @brief Get the compensation cell code of the GPIO PMOS transistor supplied by VDD + * @rmtoll CCCR PCC1 LL_SYSCFG_GetPMOSVddCompensationCode + * @retval Returned value is the PMOS compensation cell + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSVddCompensationCode(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_PCC1)); +} + +/** + * @brief Set the compensation cell code of the GPIO NMOS transistor supplied by VDD + * @rmtoll CCCR PCC2 LL_SYSCFG_SetNMOSVddCompensationCode + * @param NMOSCode NMOS compensation code + * This code is applied to the NMOS compensation cell when the CS2 bit of the + * SYSCFG_CMPCR is set + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetNMOSVddCompensationCode(uint32_t NMOSCode) +{ + MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC1, NMOSCode << SYSCFG_CCCR_NCC1_Pos); +} + +/** + * @brief Get the compensation cell code of the GPIO NMOS transistor supplied by VDD + * @rmtoll CCCR NCC1 LL_SYSCFG_GetNMOSVddCompensationCode + * @retval Returned value is the Vdd compensation cell code for NMOS transistors + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddCompensationCode(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_NCC1)); +} + +/** + * @brief Enable the Compensation Cell of GPIO supplied by VDD + * @rmtoll CCCSR EN1 LL_SYSCFG_EnableVddCompensationCell + * @note The vdd compensation cell can be used only when the device supply + * voltage ranges from 1.71 to 3.6 V + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableVddCompensationCell(void) +{ + SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN1); +} + +/** + * @brief Disable the Compensation Cell of GPIO supplied by VDD + * @rmtoll CCCSR EN1 LL_SYSCFG_EnableVddCompensationCell + * @note The Vdd compensation cell can be used only when the device supply + * voltage ranges from 1.71 to 3.6 V + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableVddCompensationCell(void) +{ + CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN1); +} + +/** + * @brief Check if the Compensation Cell of GPIO supplied by VDD is enable + * @rmtoll CCCSR EN1 LL_SYSCFG_IsEnabled_VddCompensationCell + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabled_VddCompensationCell(void) +{ + return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN1) == SYSCFG_CCCSR_EN1) ? 1UL : 0UL); +} + +/** + * @brief Get Compensation Cell ready Flag of GPIO supplied by VDD + * @rmtoll CCCSR RDY1 LL_SYSCFG_IsActiveFlag_VddCMPCR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_VddCMPCR(void) +{ + return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_RDY1) == (SYSCFG_CCCSR_RDY1)) ? 1UL : 0UL); +} + +/** + * @brief Set the compensation cell code selection of GPIO supplied by VDD + * @rmtoll CCCSR CS1 LL_SYSCFG_SetVddCellCompensationCode + * @param CompCode: Selects the code to be applied for the Vdd compensation cell + * This parameter can be one of the following values: + * @arg LL_SYSCFG_VDD_CELL_CODE : Select Code from the cell (available in the SYSCFG_CCVR) + * @arg LL_SYSCFG_VDD_REGISTER_CODE: Select Code from the SYSCFG compensation cell code register (SYSCFG_CCCR) + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetVddCellCompensationCode(uint32_t CompCode) +{ + SET_BIT(SYSCFG->CCCSR, CompCode); +} + +/** + * @brief Get the compensation cell code selection of GPIO supplied by VDD + * @rmtoll CCCSR CS1 LL_SYSCFG_GetVddCellCompensationCode + * @retval Returned value can be one of the following values: + * @arg LL_SYSCFG_VDD_CELL_CODE : Selected Code is from the cell (available in the SYSCFG_CCVR) + * @arg LL_SYSCFG_VDD_REGISTER_CODE: Selected Code is from the SYSCFG compensation cell code register (SYSCFG_CCCR) + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetVddCellCompensationCode(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_CS1)); +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU + * @{ + */ + +/** + * @brief Return the device identifier + * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID + * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF (ex: device ID is 0x6415) + */ +__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void) +{ + return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID)); +} + +/** + * @brief Return the device revision identifier + * @note This field indicates the revision of the device. + * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID + * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void) +{ + return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos); +} + +/** + * @brief Enable the Debug Module during STOP mode + * @rmtoll DBGMCU_SCR DBG_STOP LL_DBGMCU_EnableDBGStopMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void) +{ + SET_BIT(DBGMCU->SCR, DBGMCU_SCR_DBG_STOP); +} + +/** + * @brief Disable the Debug Module during STOP mode + * @rmtoll DBGMCU_SCR DBG_STOP LL_DBGMCU_DisableDBGStopMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void) +{ + CLEAR_BIT(DBGMCU->SCR, DBGMCU_SCR_DBG_STOP); +} + +/** + * @brief Enable the Debug Module during STANDBY mode + * @rmtoll DBGMCU_SCR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void) +{ + SET_BIT(DBGMCU->SCR, DBGMCU_SCR_DBG_STANDBY); +} + +/** + * @brief Disable the Debug Module during STANDBY mode + * @rmtoll DBGMCU_SCR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void) +{ + CLEAR_BIT(DBGMCU->SCR, DBGMCU_SCR_DBG_STANDBY); +} + +/** + * @brief Freeze APB1 peripherals (group1 peripherals) + * @rmtoll DBGMCU_APB1LFZR DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->APB1LFZR, Periphs); +} + +/** + * @brief Freeze APB1 peripherals (group2 peripherals) + * @rmtoll DBGMCU_APB1HFZR DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP2_I2C4_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM2_STOP + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->APB1HFZR, Periphs); +} + +/** + * @brief Unfreeze APB1 peripherals (group1 peripherals) + * @rmtoll DBGMCU_APB1LFZR DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->APB1LFZR, Periphs); +} + +/** + * @brief Unfreeze APB1 peripherals (group2 peripherals) + * @rmtoll DBGMCU_APB1HFZR DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP2_I2C4_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM2_STOP + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->APB1HFZR, Periphs); +} + +/** + * @brief Freeze APB2 peripherals + * @rmtoll DBGMCU_APB2FZ DBG_TIMx_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->APB2FZR, Periphs); +} + +/** + * @brief Unfreeze APB2 peripherals + * @rmtoll DBGMCU_APB2FZR DBG_TIMx_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->APB2FZR, Periphs); +} + +/** + * @brief Freeze APB7 peripherals + * @rmtoll DBGMCU_APB7FZ DBG_TIMx_STOP LL_DBGMCU_APB7_GRP1_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB7_GRP1_I2C3_STOP + * @arg @ref LL_DBGMCU_APB7_GRP1_LPTIM1_STOP + * @arg @ref LL_DBGMCU_APB7_GRP1_RTC_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB7_GRP1_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->APB7FZR, Periphs); +} + +/** + * @brief Unfreeze APB7 peripherals + * @rmtoll DBGMCU_APB7FZR DBG_TIMx_STOP LL_DBGMCU_APB7_GRP1_UnFreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB7_GRP1_I2C3_STOP + * @arg @ref LL_DBGMCU_APB7_GRP1_LPTIM1_STOP + * @arg @ref LL_DBGMCU_APB7_GRP1_RTC_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB7_GRP1_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->APB7FZR, Periphs); +} + +/** + * @} + */ + + + +/** @defgroup SYSTEM_LL_EF_FLASH FLASH + * @{ + */ +/** + * @brief Set FLASH Latency + * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency + * @param Latency This parameter can be one of the following values: + * @arg @ref LL_FLASH_LATENCY_0 + * @arg @ref LL_FLASH_LATENCY_1 + * @arg @ref LL_FLASH_LATENCY_2 + * @arg @ref LL_FLASH_LATENCY_3 + * @arg @ref LL_FLASH_LATENCY_4 + * @arg @ref LL_FLASH_LATENCY_5 + * @arg @ref LL_FLASH_LATENCY_6 + * @arg @ref LL_FLASH_LATENCY_7 + * @arg @ref LL_FLASH_LATENCY_8 + * @arg @ref LL_FLASH_LATENCY_9 + * @arg @ref LL_FLASH_LATENCY_10 + * @arg @ref LL_FLASH_LATENCY_11 + * @arg @ref LL_FLASH_LATENCY_12 + * @arg @ref LL_FLASH_LATENCY_13 + * @arg @ref LL_FLASH_LATENCY_14 + * @arg @ref LL_FLASH_LATENCY_15 + * @retval None + */ +__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency) +{ + MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency); +} + +/** + * @brief Get FLASH Latency + * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency + * @retval Returned value can be one of the following values: + * @arg @ref LL_FLASH_LATENCY_0 + * @arg @ref LL_FLASH_LATENCY_1 + * @arg @ref LL_FLASH_LATENCY_2 + * @arg @ref LL_FLASH_LATENCY_3 + * @arg @ref LL_FLASH_LATENCY_4 + * @arg @ref LL_FLASH_LATENCY_5 + * @arg @ref LL_FLASH_LATENCY_6 + * @arg @ref LL_FLASH_LATENCY_7 + * @arg @ref LL_FLASH_LATENCY_8 + * @arg @ref LL_FLASH_LATENCY_9 + * @arg @ref LL_FLASH_LATENCY_10 + * @arg @ref LL_FLASH_LATENCY_11 + * @arg @ref LL_FLASH_LATENCY_12 + * @arg @ref LL_FLASH_LATENCY_13 + * @arg @ref LL_FLASH_LATENCY_14 + * @arg @ref LL_FLASH_LATENCY_15 + */ +__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void) +{ + return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)); +} + +/** + * @brief Enable Flash Power-down mode during run mode or Low-power run mode + * @note Flash memory can be put in power-down mode only when the code is executed + * from RAM + * @note Flash must not be accessed when power down is enabled + * @note Flash must not be put in power-down while a program or an erase operation + * is on-going + * @rmtoll FLASH_ACR PDREQ LL_FLASH_EnableRunPowerDown\n + * FLASH_PDKEYR PDKEY1_1 LL_FLASH_EnableRunPowerDown\n + * FLASH_PDKEYR PDKEY1_2 LL_FLASH_EnableRunPowerDown + * @retval None + */ +__STATIC_INLINE void LL_FLASH_EnableRunPowerDown(void) +{ + /* Following values must be written consecutively to unlock the PDREQ bit in + FLASH_ACR */ + WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1_1); + WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1_2); + + /*Request to enter flash in power mode */ + SET_BIT(FLASH->ACR, FLASH_ACR_PDREQ); +} + +/** + * @brief Enable Flash Power-down mode during Sleep or Low-power sleep mode + * @note Flash must not be put in power-down while a program or an erase operation + * is on-going + * @rmtoll FLASH_ACR SLEEP_PD LL_FLASH_EnableSleepPowerDown + * @retval None + */ +__STATIC_INLINE void LL_FLASH_EnableSleepPowerDown(void) +{ + SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD); +} + +/** + * @brief Disable Flash Power-down mode during Sleep or Low-power sleep mode + * @rmtoll FLASH_ACR SLEEP_PD LL_FLASH_DisableSleepPowerDown + * @retval None + */ +__STATIC_INLINE void LL_FLASH_DisableSleepPowerDown(void) +{ + CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD); +} + +/** + * @brief Return the Unique Device Number + * @retval Values between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_FLASH_GetUDN(void) +{ + return (READ_REG(*((uint32_t *)UID64_BASE))); +} + +/** + * @brief Return the Device ID + * For STM32WBA52xx devices, the device ID is 0x2A + * @retval Values between Min_Data=0x00 and Max_Data=0xFF (ex: Device ID is 0x2A) + */ +__STATIC_INLINE uint32_t LL_FLASH_GetDeviceID(void) +{ + return ((READ_REG(*((uint32_t *)UID64_BASE + 1U))) & 0x000000FFU); +} + +/** + * @brief Return the ST Company ID + * @note For STM32WBAxxxx devices, the ST Company ID is 0x0080E1 + * @retval Values between Min_Data=0x00 and Max_Data=0xFFFFFF (ex: ST Company ID is 0x0080E1) + */ +__STATIC_INLINE uint32_t LL_FLASH_GetSTCompanyID(void) +{ + return (((READ_REG(*((uint32_t *)UID64_BASE + 1U))) >> 8U) & 0x00FFFFFFU); +} +/** + * @} + */ + + + +/** + * @} + */ + +#endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WBAxx_LL_SYSTEM_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_tim.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_tim.h new file mode 100644 index 0000000000..033581374d --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_tim.h @@ -0,0 +1,6100 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_ll_tim.h + * @author MCD Application Team + * @brief Header file of TIM LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32WBAxx_LL_TIM_H +#define __STM32WBAxx_LL_TIM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx.h" + +/** @addtogroup STM32WBAxx_LL_Driver + * @{ + */ + +#if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM16) || defined (TIM17) + +/** @defgroup TIM_LL TIM + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup TIM_LL_Private_Variables TIM Private Variables + * @{ + */ +static const uint8_t OFFSET_TAB_CCMRx[] = +{ + 0x00U, /* 0: TIMx_CH1 */ + 0x00U, /* 1: TIMx_CH1N */ + 0x00U, /* 2: TIMx_CH2 */ + 0x00U, /* 3: TIMx_CH2N */ + 0x04U, /* 4: TIMx_CH3 */ + 0x04U, /* 5: TIMx_CH3N */ + 0x04U, /* 6: TIMx_CH4 */ + 0x04U, /* 7: TIMx_CH4N */ + 0x38U, /* 8: TIMx_CH5 */ + 0x38U /* 9: TIMx_CH6 */ + +}; + +static const uint8_t SHIFT_TAB_OCxx[] = +{ + 0U, /* 0: OC1M, OC1FE, OC1PE */ + 0U, /* 1: - NA */ + 8U, /* 2: OC2M, OC2FE, OC2PE */ + 0U, /* 3: - NA */ + 0U, /* 4: OC3M, OC3FE, OC3PE */ + 0U, /* 5: - NA */ + 8U, /* 6: OC4M, OC4FE, OC4PE */ + 0U, /* 7: - NA */ + 0U, /* 8: OC5M, OC5FE, OC5PE */ + 8U /* 9: OC6M, OC6FE, OC6PE */ +}; + +static const uint8_t SHIFT_TAB_ICxx[] = +{ + 0U, /* 0: CC1S, IC1PSC, IC1F */ + 0U, /* 1: - NA */ + 8U, /* 2: CC2S, IC2PSC, IC2F */ + 0U, /* 3: - NA */ + 0U, /* 4: CC3S, IC3PSC, IC3F */ + 0U, /* 5: - NA */ + 8U, /* 6: CC4S, IC4PSC, IC4F */ + 0U, /* 7: - NA */ + 0U, /* 8: - NA */ + 0U /* 9: - NA */ +}; + +static const uint8_t SHIFT_TAB_CCxP[] = +{ + 0U, /* 0: CC1P */ + 2U, /* 1: CC1NP */ + 4U, /* 2: CC2P */ + 6U, /* 3: CC2NP */ + 8U, /* 4: CC3P */ + 10U, /* 5: CC3NP */ + 12U, /* 6: CC4P */ + 14U, /* 7: CC4NP */ + 16U, /* 8: CC5P */ + 20U /* 9: CC6P */ +}; + +static const uint8_t SHIFT_TAB_OISx[] = +{ + 0U, /* 0: OIS1 */ + 1U, /* 1: OIS1N */ + 2U, /* 2: OIS2 */ + 3U, /* 3: OIS2N */ + 4U, /* 4: OIS3 */ + 5U, /* 5: OIS3N */ + 6U, /* 6: OIS4 */ + 7U, /* 7: OIS4N */ + 8U, /* 8: OIS5 */ + 10U /* 9: OIS6 */ +}; +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup TIM_LL_Private_Constants TIM Private Constants + * @{ + */ + +/* Defines used for the bit position in the register and perform offsets */ +#define TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FUL) + +/* Generic bit definitions for TIMx_AF1 register */ +#define TIMx_AF1_BKINP TIM_AF1_BKINP /*!< BRK BKIN input polarity */ +#define TIMx_AF1_ETRSEL TIM_AF1_ETRSEL /*!< TIMx ETR source selection */ + + +/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */ +#define DT_DELAY_1 ((uint8_t)0x7F) +#define DT_DELAY_2 ((uint8_t)0x3F) +#define DT_DELAY_3 ((uint8_t)0x1F) +#define DT_DELAY_4 ((uint8_t)0x1F) + +/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */ +#define DT_RANGE_1 ((uint8_t)0x00) +#define DT_RANGE_2 ((uint8_t)0x80) +#define DT_RANGE_3 ((uint8_t)0xC0) +#define DT_RANGE_4 ((uint8_t)0xE0) + +/** Legacy definitions for compatibility purpose +@cond 0 + */ +/** +@endcond + */ + +#define OCREF_CLEAR_SELECT_POS (28U) +#define OCREF_CLEAR_SELECT_MSK (0x1U << OCREF_CLEAR_SELECT_POS) /*!< 0x10000000 */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup TIM_LL_Private_Macros TIM Private Macros + * @{ + */ +/** @brief Convert channel id into channel index. + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH4N + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval none + */ +#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \ + (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH4N) ? 7U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 8U : 9U) + +/** @brief Calculate the deadtime sampling period(in ps). + * @param __TIMCLK__ timer input clock frequency (in Hz). + * @param __CKD__ This parameter can be one of the following values: + * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 + * @retval none + */ +#define TIM_CALC_DTS(__TIMCLK__, __CKD__) \ + (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \ + ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \ + ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U))) +/** + * @} + */ + + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure + * @{ + */ + +/** + * @brief TIM Time Base configuration structure definition. + */ +typedef struct +{ + uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetPrescaler().*/ + + uint32_t CounterMode; /*!< Specifies the counter mode. + This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetCounterMode().*/ + + uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF. + Some timer instances may support 32 bits counters. In that case this parameter must + be a number between 0x0000 and 0xFFFFFFFF. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetAutoReload().*/ + + uint32_t ClockDivision; /*!< Specifies the clock division. + This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetClockDivision().*/ + + uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter + reaches zero, an update event is generated and counting restarts + from the RCR value (N). + This means in PWM mode that (N+1) corresponds to: + - the number of PWM periods in edge-aligned mode + - the number of half PWM period in center-aligned mode + GP timers: this parameter must be a number between Min_Data = 0x00 and + Max_Data = 0xFF. + Advanced timers: this parameter must be a number between Min_Data = 0x0000 and + Max_Data = 0xFFFF. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetRepetitionCounter().*/ +} LL_TIM_InitTypeDef; + +/** + * @brief TIM Output Compare configuration structure definition. + */ +typedef struct +{ + uint32_t OCMode; /*!< Specifies the output mode. + This parameter can be a value of @ref TIM_LL_EC_OCMODE. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetMode().*/ + + uint32_t OCState; /*!< Specifies the TIM Output Compare state. + This parameter can be a value of @ref TIM_LL_EC_OCSTATE. + + This feature can be modified afterwards using unitary functions + @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ + + uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state. + This parameter can be a value of @ref TIM_LL_EC_OCSTATE. + + This feature can be modified afterwards using unitary functions + @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ + + uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. + + This feature can be modified afterwards using unitary function + LL_TIM_OC_SetCompareCHx (x=1..6).*/ + + uint32_t OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetPolarity().*/ + + uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetPolarity().*/ + + + uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetIdleState().*/ + + uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetIdleState().*/ +} LL_TIM_OC_InitTypeDef; + +/** + * @brief TIM Input Capture configuration structure definition. + */ + +typedef struct +{ + + uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPolarity().*/ + + uint32_t ICActiveInput; /*!< Specifies the input. + This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetActiveInput().*/ + + uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_LL_EC_ICPSC. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPrescaler().*/ + + uint32_t ICFilter; /*!< Specifies the input capture filter. + This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetFilter().*/ +} LL_TIM_IC_InitTypeDef; + + +/** + * @brief TIM Encoder interface configuration structure definition. + */ +typedef struct +{ + uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4). + This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetEncoderMode().*/ + + uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. + This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPolarity().*/ + + uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source + This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetActiveInput().*/ + + uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. + This parameter can be a value of @ref TIM_LL_EC_ICPSC. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPrescaler().*/ + + uint32_t IC1Filter; /*!< Specifies the TI1 input filter. + This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetFilter().*/ + + uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input. + This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPolarity().*/ + + uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source + This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetActiveInput().*/ + + uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value. + This parameter can be a value of @ref TIM_LL_EC_ICPSC. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPrescaler().*/ + + uint32_t IC2Filter; /*!< Specifies the TI2 input filter. + This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetFilter().*/ + +} LL_TIM_ENCODER_InitTypeDef; + +/** + * @brief TIM Hall sensor interface configuration structure definition. + */ +typedef struct +{ + + uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. + This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPolarity().*/ + + uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. + Prescaler must be set to get a maximum counter period longer than the + time interval between 2 consecutive changes on the Hall inputs. + This parameter can be a value of @ref TIM_LL_EC_ICPSC. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPrescaler().*/ + + uint32_t IC1Filter; /*!< Specifies the TI1 input filter. + This parameter can be a value of + @ref TIM_LL_EC_IC_FILTER. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetFilter().*/ + + uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register. + A positive pulse (TRGO event) is generated with a programmable delay every time + a change occurs on the Hall inputs. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetCompareCH2().*/ +} LL_TIM_HALLSENSOR_InitTypeDef; + +/** + * @brief BDTR (Break and Dead Time) structure definition + */ +typedef struct +{ + uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode. + This parameter can be a value of @ref TIM_LL_EC_OSSR + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetOffStates() + + @note This bit-field cannot be modified as long as LOCK level 2 has been + programmed. */ + + uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state. + This parameter can be a value of @ref TIM_LL_EC_OSSI + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetOffStates() + + @note This bit-field cannot be modified as long as LOCK level 2 has been + programmed. */ + + uint32_t LockLevel; /*!< Specifies the LOCK level parameters. + This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL + + @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR + register has been written, their content is frozen until the next reset.*/ + + uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the + switching-on of the outputs. + This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetDeadTime() + + @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been + programmed. */ + + uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not. + This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE + + This feature can be modified afterwards using unitary functions + @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK() + + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ + + uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. + This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY + + This feature can be modified afterwards using unitary function + @ref LL_TIM_ConfigBRK() + + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ + + uint32_t BreakFilter; /*!< Specifies the TIM Break Filter. + This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER + + This feature can be modified afterwards using unitary function + @ref LL_TIM_ConfigBRK() + + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ + + uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input. + This parameter can be a value of @ref TIM_LL_EC_BREAK_AFMODE + + This feature can be modified afterwards using unitary functions + @ref LL_TIM_ConfigBRK() + + @note Bidirectional break input is only supported by advanced timers instances. + + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ + + uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not. + This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE + + This feature can be modified afterwards using unitary functions + @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2() + + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ + + uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity. + This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY + + This feature can be modified afterwards using unitary function + @ref LL_TIM_ConfigBRK2() + + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ + + uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter. + This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER + + This feature can be modified afterwards using unitary function + @ref LL_TIM_ConfigBRK2() + + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ + + uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input. + This parameter can be a value of @ref TIM_LL_EC_BREAK2_AFMODE + + This feature can be modified afterwards using unitary functions + @ref LL_TIM_ConfigBRK2() + + @note Bidirectional break input is only supported by advanced timers instances. + + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ + + uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. + This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE + + This feature can be modified afterwards using unitary functions + @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput() + + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ +} LL_TIM_BDTR_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants + * @{ + */ + +/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_TIM_ReadReg function. + * @{ + */ +#define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */ +#define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */ +#define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */ +#define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */ +#define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */ +#define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrupt flag */ +#define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrupt flag */ +#define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */ +#define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */ +#define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */ +#define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt flag */ +#define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */ +#define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */ +#define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */ +#define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */ +#define LL_TIM_SR_SBIF TIM_SR_SBIF /*!< System Break interrupt flag */ +#define LL_TIM_SR_IDXF TIM_SR_IDXF /*!< Index interrupt flag */ +#define LL_TIM_SR_DIRF TIM_SR_DIRF /*!< Direction Change interrupt flag */ +#define LL_TIM_SR_IERRF TIM_SR_IERRF /*!< Index Error flag */ +#define LL_TIM_SR_TERRF TIM_SR_TERRF /*!< Transition Error flag */ +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable + * @{ + */ +#define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */ +#define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable + * @{ + */ +#define LL_TIM_BREAK2_DISABLE 0x00000000U /*!< Break2 function disabled */ +#define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable + * @{ + */ +#define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ +#define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** @defgroup TIM_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions. + * @{ + */ +#define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */ +#define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */ +#define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */ +#define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */ +#define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */ +#define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */ +#define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */ +#define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */ +#define LL_TIM_DIER_IDXIE TIM_DIER_IDXIE /*!< Index interrupt enable */ +#define LL_TIM_DIER_DIRIE TIM_DIER_DIRIE /*!< Direction Change interrupt enable */ +#define LL_TIM_DIER_IERRIE TIM_DIER_IERRIE /*!< Index Error interrupt enable */ +#define LL_TIM_DIER_TERRIE TIM_DIER_TERRIE /*!< Transition Error interrupt enable */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source + * @{ + */ +#define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */ +#define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode + * @{ + */ +#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ +#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode + * @{ + */ +#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as upcounter */ +#define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */ +#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */ +#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */ +#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division + * @{ + */ +#define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */ +#define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */ +#define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction + * @{ + */ +#define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */ +#define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source + * @{ + */ +#define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */ +#define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request + * @{ + */ +#define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */ +#define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level + * @{ + */ +#define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */ +#define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ +#define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ +#define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_CHANNEL Channel + * @{ + */ +#define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */ +#define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */ +#define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */ +#define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */ +#define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */ +#define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */ +#define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */ +#define LL_TIM_CHANNEL_CH4N TIM_CCER_CC4NE /*!< Timer complementary output channel 4 */ +#define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /*!< Timer output channel 5 */ +#define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /*!< Timer output channel 6 */ +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup TIM_LL_EC_OCSTATE Output Configuration State + * @{ + */ +#define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */ +#define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode + * @{ + */ +#define LL_TIM_OCMODE_FROZEN 0x00000000U /*!TIMx_CCRy else active.*/ +#define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!TIMx_CCRy else inactive*/ +#define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 /*!__REG__, (__VALUE__)) + +/** + * @brief Read a value in TIM register. + * @param __INSTANCE__ TIM Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__) +/** + * @} + */ + +/** + * @brief HELPER macro retrieving the UIFCPY flag from the counter value. + * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ()); + * @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied + * to TIMx_CNT register bit 31) + * @param __CNT__ Counter value + * @retval UIF status bit + */ +#define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \ + (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos) + +/** + * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration. + * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __CKD__ This parameter can be one of the following values: + * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 + * @param __DT__ deadtime duration (in ns) + * @retval DTG[0:7] + */ +#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \ + ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ + (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \ + (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ + (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \ + (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\ + (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ + (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \ + (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\ + (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ + (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \ + (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\ + 0U) + +/** + * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency. + * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __CNTCLK__ counter clock frequency (in Hz) + * @retval Prescaler value (between Min_Data=0 and Max_Data=65535) + */ +#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \ + (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U) + +/** + * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency. + * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __PSC__ prescaler + * @param __FREQ__ output signal frequency (in Hz) + * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) + */ +#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \ + ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U) + +/** + * @brief HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required + * output signal frequency. + * @note ex: @ref __LL_TIM_CALC_ARR_DITHER (1000000, @ref LL_TIM_GetPrescaler (), 10000); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __PSC__ prescaler + * @param __FREQ__ output signal frequency (in Hz) + * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) + */ +#define __LL_TIM_CALC_ARR_DITHER(__TIMCLK__, __PSC__, __FREQ__) \ + ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? \ + (uint32_t)((((uint64_t)(__TIMCLK__) * 16U/((__FREQ__) * ((__PSC__) + 1U))) - 16U)) : 0U) + +/** + * @brief HELPER macro calculating the compare value required to achieve the required timer output compare + * active/inactive delay. + * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __PSC__ prescaler + * @param __DELAY__ timer output compare active/inactive delay (in us) + * @retval Compare value (between Min_Data=0 and Max_Data=65535) + */ +#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \ + ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \ + / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U)))) + +/** + * @brief HELPER macro calculating the compare value, with dithering feature enabled, to achieve the required timer + * output compare active/inactive delay. + * @note ex: @ref __LL_TIM_CALC_DELAY_DITHER (1000000, @ref LL_TIM_GetPrescaler (), 10); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __PSC__ prescaler + * @param __DELAY__ timer output compare active/inactive delay (in us) + * @retval Compare value (between Min_Data=0 and Max_Data=65535) + */ +#define __LL_TIM_CALC_DELAY_DITHER(__TIMCLK__, __PSC__, __DELAY__) \ + ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__) * 16U) \ + / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U)))) + +/** + * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration + * (when the timer operates in one pulse mode). + * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __PSC__ prescaler + * @param __DELAY__ timer output compare active/inactive delay (in us) + * @param __PULSE__ pulse duration (in us) + * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) + */ +#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \ + ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \ + + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__)))) + +/** + * @brief HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required + * pulse duration (when the timer operates in one pulse mode). + * @note ex: @ref __LL_TIM_CALC_PULSE_DITHER (1000000, @ref LL_TIM_GetPrescaler (), 10, 20); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __PSC__ prescaler + * @param __DELAY__ timer output compare active/inactive delay (in us) + * @param __PULSE__ pulse duration (in us) + * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) + */ +#define __LL_TIM_CALC_PULSE_DITHER(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \ + ((uint32_t)(__LL_TIM_CALC_DELAY_DITHER((__TIMCLK__), (__PSC__), (__PULSE__)) \ + + __LL_TIM_CALC_DELAY_DITHER((__TIMCLK__), (__PSC__), (__DELAY__)))) + +/** + * @brief HELPER macro retrieving the ratio of the input capture prescaler + * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ()); + * @param __ICPSC__ This parameter can be one of the following values: + * @arg @ref LL_TIM_ICPSC_DIV1 + * @arg @ref LL_TIM_ICPSC_DIV2 + * @arg @ref LL_TIM_ICPSC_DIV4 + * @arg @ref LL_TIM_ICPSC_DIV8 + * @retval Input capture prescaler ratio (1, 2, 4 or 8) + */ +#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \ + ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos))) + + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions + * @{ + */ + +/** @defgroup TIM_LL_EF_Time_Base Time Base configuration + * @{ + */ +/** + * @brief Enable timer counter. + * @rmtoll CR1 CEN LL_TIM_EnableCounter + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR1, TIM_CR1_CEN); +} + +/** + * @brief Disable timer counter. + * @rmtoll CR1 CEN LL_TIM_DisableCounter + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN); +} + +/** + * @brief Indicates whether the timer counter is enabled. + * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable update event generation. + * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS); +} + +/** + * @brief Disable update event generation. + * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR1, TIM_CR1_UDIS); +} + +/** + * @brief Indicates whether update event generation is enabled. + * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent + * @param TIMx Timer instance + * @retval Inverted state of bit (0 or 1). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL); +} + +/** + * @brief Set update event source + * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events + * generate an update interrupt or DMA request if enabled: + * - Counter overflow/underflow + * - Setting the UG bit + * - Update generation through the slave mode controller + * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter + * overflow/underflow generates an update interrupt or DMA request if enabled. + * @rmtoll CR1 URS LL_TIM_SetUpdateSource + * @param TIMx Timer instance + * @param UpdateSource This parameter can be one of the following values: + * @arg @ref LL_TIM_UPDATESOURCE_REGULAR + * @arg @ref LL_TIM_UPDATESOURCE_COUNTER + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource) +{ + MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource); +} + +/** + * @brief Get actual event update source + * @rmtoll CR1 URS LL_TIM_GetUpdateSource + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_UPDATESOURCE_REGULAR + * @arg @ref LL_TIM_UPDATESOURCE_COUNTER + */ +__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS)); +} + +/** + * @brief Set one pulse mode (one shot v.s. repetitive). + * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode + * @param TIMx Timer instance + * @param OnePulseMode This parameter can be one of the following values: + * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE + * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode) +{ + MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode); +} + +/** + * @brief Get actual one pulse mode. + * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE + * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE + */ +__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM)); +} + +/** + * @brief Set the timer counter counting mode. + * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to + * check whether or not the counter mode selection feature is supported + * by a timer instance. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n + * CR1 CMS LL_TIM_SetCounterMode + * @param TIMx Timer instance + * @param CounterMode This parameter can be one of the following values: + * @arg @ref LL_TIM_COUNTERMODE_UP + * @arg @ref LL_TIM_COUNTERMODE_DOWN + * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP + * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN + * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode) +{ + MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode); +} + +/** + * @brief Get actual counter mode. + * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to + * check whether or not the counter mode selection feature is supported + * by a timer instance. + * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n + * CR1 CMS LL_TIM_GetCounterMode + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_COUNTERMODE_UP + * @arg @ref LL_TIM_COUNTERMODE_DOWN + * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP + * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN + * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN + */ +__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx) +{ + uint32_t counter_mode; + + counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS)); + + if (counter_mode == 0U) + { + counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); + } + + return counter_mode; +} + +/** + * @brief Enable auto-reload (ARR) preload. + * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR1, TIM_CR1_ARPE); +} + +/** + * @brief Disable auto-reload (ARR) preload. + * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE); +} + +/** + * @brief Indicates whether auto-reload (ARR) preload is enabled. + * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL); +} + +/** + * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators + * (when supported) and the digital filters. + * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check + * whether or not the clock division feature is supported by the timer + * instance. + * @rmtoll CR1 CKD LL_TIM_SetClockDivision + * @param TIMx Timer instance + * @param ClockDivision This parameter can be one of the following values: + * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision) +{ + MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision); +} + +/** + * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time + * generators (when supported) and the digital filters. + * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check + * whether or not the clock division feature is supported by the timer + * instance. + * @rmtoll CR1 CKD LL_TIM_GetClockDivision + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 + */ +__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD)); +} + +/** + * @brief Set the counter value. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note If dithering is activated, pay attention to the Counter value interpretation + * @rmtoll CNT CNT LL_TIM_SetCounter + * @param TIMx Timer instance + * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter) +{ + WRITE_REG(TIMx->CNT, Counter); +} + +/** + * @brief Get the counter value. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note If dithering is activated, pay attention to the Counter value interpretation + * @rmtoll CNT CNT LL_TIM_GetCounter + * @param TIMx Timer instance + * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) + */ +__STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CNT)); +} + +/** + * @brief Get the current direction of the counter + * @rmtoll CR1 DIR LL_TIM_GetDirection + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_COUNTERDIRECTION_UP + * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN + */ +__STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); +} + +/** + * @brief Set the prescaler value. + * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). + * @note The prescaler can be changed on the fly as this control register is buffered. The new + * prescaler ratio is taken into account at the next update event. + * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter + * @rmtoll PSC PSC LL_TIM_SetPrescaler + * @param TIMx Timer instance + * @param Prescaler between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler) +{ + WRITE_REG(TIMx->PSC, Prescaler); +} + +/** + * @brief Get the prescaler value. + * @rmtoll PSC PSC LL_TIM_GetPrescaler + * @param TIMx Timer instance + * @retval Prescaler value between Min_Data=0 and Max_Data=65535 + */ +__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->PSC)); +} + +/** + * @brief Set the auto-reload value. + * @note The counter is blocked while the auto-reload value is null. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter + * In case dithering is activated,macro __LL_TIM_CALC_ARR_DITHER can be used instead, to calculate the AutoReload + * parameter. + * @rmtoll ARR ARR LL_TIM_SetAutoReload + * @param TIMx Timer instance + * @param AutoReload between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload) +{ + WRITE_REG(TIMx->ARR, AutoReload); +} + +/** + * @brief Get the auto-reload value. + * @rmtoll ARR ARR LL_TIM_GetAutoReload + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note If dithering is activated, pay attention to the returned value interpretation + * @param TIMx Timer instance + * @retval Auto-reload value + */ +__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->ARR)); +} + +/** + * @brief Set the repetition counter value. + * @note For advanced timer instances RepetitionCounter can be up to 65535. + * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a repetition counter. + * @rmtoll RCR REP LL_TIM_SetRepetitionCounter + * @param TIMx Timer instance + * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer. + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter) +{ + WRITE_REG(TIMx->RCR, RepetitionCounter); +} + +/** + * @brief Get the repetition counter value. + * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a repetition counter. + * @rmtoll RCR REP LL_TIM_GetRepetitionCounter + * @param TIMx Timer instance + * @retval Repetition counter value + */ +__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->RCR)); +} + +/** + * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31). + * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read + * in an atomic way. + * @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP); +} + +/** + * @brief Disable update interrupt flag (UIF) remapping. + * @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP); +} + +/** + * @brief Indicate whether update interrupt flag (UIF) copy is set. + * @param Counter Counter value + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(const uint32_t Counter) +{ + return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL); +} + +/** + * @brief Enable dithering. + * @note Macro IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides dithering. + * @rmtoll CR1 DITHEN LL_TIM_EnableDithering + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDithering(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR1, TIM_CR1_DITHEN); +} + +/** + * @brief Disable dithering. + * @note Macro IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides dithering. + * @rmtoll CR1 DITHEN LL_TIM_DisableDithering + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDithering(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR1, TIM_CR1_DITHEN); +} + +/** + * @brief Indicates whether dithering is activated. + * @note Macro IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides dithering. + * @rmtoll CR1 DITHEN LL_TIM_IsEnabledDithering + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDithering(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->CR1, TIM_CR1_DITHEN) == (TIM_CR1_DITHEN)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration + * @{ + */ +/** + * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. + * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written, + * they are updated only when a commutation event (COM) occurs. + * @note Only on channels that have a complementary output. + * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check + * whether or not a timer instance is able to generate a commutation event. + * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR2, TIM_CR2_CCPC); +} + +/** + * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. + * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check + * whether or not a timer instance is able to generate a commutation event. + * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC); +} + +/** + * @brief Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is enabled. + * @rmtoll CR2 CCPC LL_TIM_CC_IsEnabledPreload + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL); +} + +/** + * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM). + * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check + * whether or not a timer instance is able to generate a commutation event. + * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate + * @param TIMx Timer instance + * @param CCUpdateSource This parameter can be one of the following values: + * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY + * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource) +{ + MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource); +} + +/** + * @brief Set the trigger of the capture/compare DMA request. + * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger + * @param TIMx Timer instance + * @param DMAReqTrigger This parameter can be one of the following values: + * @arg @ref LL_TIM_CCDMAREQUEST_CC + * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger) +{ + MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger); +} + +/** + * @brief Get actual trigger of the capture/compare DMA request. + * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_CCDMAREQUEST_CC + * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE + */ +__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS)); +} + +/** + * @brief Set the lock level to freeze the + * configuration of several capture/compare parameters. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * the lock mechanism is supported by a timer instance. + * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel + * @param TIMx Timer instance + * @param LockLevel This parameter can be one of the following values: + * @arg @ref LL_TIM_LOCKLEVEL_OFF + * @arg @ref LL_TIM_LOCKLEVEL_1 + * @arg @ref LL_TIM_LOCKLEVEL_2 + * @arg @ref LL_TIM_LOCKLEVEL_3 + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel) +{ + MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel); +} + +/** + * @brief Enable capture/compare channels. + * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n + * CCER CC1NE LL_TIM_CC_EnableChannel\n + * CCER CC2E LL_TIM_CC_EnableChannel\n + * CCER CC2NE LL_TIM_CC_EnableChannel\n + * CCER CC3E LL_TIM_CC_EnableChannel\n + * CCER CC3NE LL_TIM_CC_EnableChannel\n + * CCER CC4E LL_TIM_CC_EnableChannel\n + * CCER CC4NE LL_TIM_CC_EnableChannel\n + * CCER CC5E LL_TIM_CC_EnableChannel\n + * CCER CC6E LL_TIM_CC_EnableChannel + * @param TIMx Timer instance + * @param Channels This parameter can be a combination of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH4N + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels) +{ + SET_BIT(TIMx->CCER, Channels); +} + +/** + * @brief Disable capture/compare channels. + * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n + * CCER CC1NE LL_TIM_CC_DisableChannel\n + * CCER CC2E LL_TIM_CC_DisableChannel\n + * CCER CC2NE LL_TIM_CC_DisableChannel\n + * CCER CC3E LL_TIM_CC_DisableChannel\n + * CCER CC3NE LL_TIM_CC_DisableChannel\n + * CCER CC4E LL_TIM_CC_DisableChannel\n + * CCER CC4NE LL_TIM_CC_DisableChannel\n + * CCER CC5E LL_TIM_CC_DisableChannel\n + * CCER CC6E LL_TIM_CC_DisableChannel + * @param TIMx Timer instance + * @param Channels This parameter can be a combination of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH4N + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels) +{ + CLEAR_BIT(TIMx->CCER, Channels); +} + +/** + * @brief Indicate whether channel(s) is(are) enabled. + * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n + * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n + * CCER CC2E LL_TIM_CC_IsEnabledChannel\n + * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n + * CCER CC3E LL_TIM_CC_IsEnabledChannel\n + * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n + * CCER CC4E LL_TIM_CC_IsEnabledChannel\n + * CCER CC4NE LL_TIM_CC_IsEnabledChannel\n + * CCER CC5E LL_TIM_CC_IsEnabledChannel\n + * CCER CC6E LL_TIM_CC_IsEnabledChannel + * @param TIMx Timer instance + * @param Channels This parameter can be a combination of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH4N + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels) +{ + return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration + * @{ + */ +/** + * @brief Configure an output channel. + * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n + * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n + * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n + * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n + * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n + * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n + * CCER CC1P LL_TIM_OC_ConfigOutput\n + * CCER CC2P LL_TIM_OC_ConfigOutput\n + * CCER CC3P LL_TIM_OC_ConfigOutput\n + * CCER CC4P LL_TIM_OC_ConfigOutput\n + * CCER CC5P LL_TIM_OC_ConfigOutput\n + * CCER CC6P LL_TIM_OC_ConfigOutput\n + * CR2 OIS1 LL_TIM_OC_ConfigOutput\n + * CR2 OIS2 LL_TIM_OC_ConfigOutput\n + * CR2 OIS3 LL_TIM_OC_ConfigOutput\n + * CR2 OIS4 LL_TIM_OC_ConfigOutput\n + * CR2 OIS5 LL_TIM_OC_ConfigOutput\n + * CR2 OIS6 LL_TIM_OC_ConfigOutput + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW + * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel])); + MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), + (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]); + MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), + (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]); +} + +/** + * @brief Define the behavior of the output reference signal OCxREF from which + * OCx and OCxN (when relevant) are derived. + * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n + * CCMR1 OC2M LL_TIM_OC_SetMode\n + * CCMR2 OC3M LL_TIM_OC_SetMode\n + * CCMR2 OC4M LL_TIM_OC_SetMode\n + * CCMR3 OC5M LL_TIM_OC_SetMode\n + * CCMR3 OC6M LL_TIM_OC_SetMode + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_TIM_OCMODE_FROZEN + * @arg @ref LL_TIM_OCMODE_ACTIVE + * @arg @ref LL_TIM_OCMODE_INACTIVE + * @arg @ref LL_TIM_OCMODE_TOGGLE + * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE + * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE + * @arg @ref LL_TIM_OCMODE_PWM1 + * @arg @ref LL_TIM_OCMODE_PWM2 + * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1 + * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2 + * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1 + * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2 + * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1 + * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2 + * @arg @ref LL_TIM_OCMODE_PULSE_ON_COMPARE (for channel 3 or channel 4 only) + * @arg @ref LL_TIM_OCMODE_DIRECTION_OUTPUT (for channel 3 or channel 4 only) + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]); +} + +/** + * @brief Get the output compare mode of an output channel. + * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n + * CCMR1 OC2M LL_TIM_OC_GetMode\n + * CCMR2 OC3M LL_TIM_OC_GetMode\n + * CCMR2 OC4M LL_TIM_OC_GetMode\n + * CCMR3 OC5M LL_TIM_OC_GetMode\n + * CCMR3 OC6M LL_TIM_OC_GetMode + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_OCMODE_FROZEN + * @arg @ref LL_TIM_OCMODE_ACTIVE + * @arg @ref LL_TIM_OCMODE_INACTIVE + * @arg @ref LL_TIM_OCMODE_TOGGLE + * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE + * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE + * @arg @ref LL_TIM_OCMODE_PWM1 + * @arg @ref LL_TIM_OCMODE_PWM2 + * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1 + * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2 + * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1 + * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2 + * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1 + * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2 + * @arg @ref LL_TIM_OCMODE_PULSE_ON_COMPARE (for channel 3 or channel 4 only) + * @arg @ref LL_TIM_OCMODE_DIRECTION_OUTPUT (for channel 3 or channel 4 only) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]); +} + +/** + * @brief Set the polarity of an output channel. + * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n + * CCER CC1NP LL_TIM_OC_SetPolarity\n + * CCER CC2P LL_TIM_OC_SetPolarity\n + * CCER CC2NP LL_TIM_OC_SetPolarity\n + * CCER CC3P LL_TIM_OC_SetPolarity\n + * CCER CC3NP LL_TIM_OC_SetPolarity\n + * CCER CC4P LL_TIM_OC_SetPolarity\n + * CCER CC4NP LL_TIM_OC_SetPolarity\n + * CCER CC5P LL_TIM_OC_SetPolarity\n + * CCER CC6P LL_TIM_OC_SetPolarity + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH4N + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_TIM_OCPOLARITY_HIGH + * @arg @ref LL_TIM_OCPOLARITY_LOW + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]); +} + +/** + * @brief Get the polarity of an output channel. + * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n + * CCER CC1NP LL_TIM_OC_GetPolarity\n + * CCER CC2P LL_TIM_OC_GetPolarity\n + * CCER CC2NP LL_TIM_OC_GetPolarity\n + * CCER CC3P LL_TIM_OC_GetPolarity\n + * CCER CC3NP LL_TIM_OC_GetPolarity\n + * CCER CC4P LL_TIM_OC_GetPolarity\n + * CCER CC4NP LL_TIM_OC_GetPolarity\n + * CCER CC5P LL_TIM_OC_GetPolarity\n + * CCER CC6P LL_TIM_OC_GetPolarity + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH4N + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_OCPOLARITY_HIGH + * @arg @ref LL_TIM_OCPOLARITY_LOW + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]); +} + +/** + * @brief Set the IDLE state of an output channel + * @note This function is significant only for the timer instances + * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx) + * can be used to check whether or not a timer instance provides + * a break input. + * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n + * CR2 OIS2N LL_TIM_OC_SetIdleState\n + * CR2 OIS2 LL_TIM_OC_SetIdleState\n + * CR2 OIS2N LL_TIM_OC_SetIdleState\n + * CR2 OIS3 LL_TIM_OC_SetIdleState\n + * CR2 OIS3N LL_TIM_OC_SetIdleState\n + * CR2 OIS4 LL_TIM_OC_SetIdleState\n + * CR2 OIS4N LL_TIM_OC_SetIdleState\n + * CR2 OIS5 LL_TIM_OC_SetIdleState\n + * CR2 OIS6 LL_TIM_OC_SetIdleState + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH4N + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @param IdleState This parameter can be one of the following values: + * @arg @ref LL_TIM_OCIDLESTATE_LOW + * @arg @ref LL_TIM_OCIDLESTATE_HIGH + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]); +} + +/** + * @brief Get the IDLE state of an output channel + * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n + * CR2 OIS2N LL_TIM_OC_GetIdleState\n + * CR2 OIS2 LL_TIM_OC_GetIdleState\n + * CR2 OIS2N LL_TIM_OC_GetIdleState\n + * CR2 OIS3 LL_TIM_OC_GetIdleState\n + * CR2 OIS3N LL_TIM_OC_GetIdleState\n + * CR2 OIS4 LL_TIM_OC_GetIdleState\n + * CR2 OIS4N LL_TIM_OC_GetIdleState\n + * CR2 OIS5 LL_TIM_OC_GetIdleState\n + * CR2 OIS6 LL_TIM_OC_GetIdleState + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH4N + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_OCIDLESTATE_LOW + * @arg @ref LL_TIM_OCIDLESTATE_HIGH + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]); +} + +/** + * @brief Enable fast mode for the output channel. + * @note Acts only if the channel is configured in PWM1 or PWM2 mode. + * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n + * CCMR1 OC2FE LL_TIM_OC_EnableFast\n + * CCMR2 OC3FE LL_TIM_OC_EnableFast\n + * CCMR2 OC4FE LL_TIM_OC_EnableFast\n + * CCMR3 OC5FE LL_TIM_OC_EnableFast\n + * CCMR3 OC6FE LL_TIM_OC_EnableFast + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); + +} + +/** + * @brief Disable fast mode for the output channel. + * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n + * CCMR1 OC2FE LL_TIM_OC_DisableFast\n + * CCMR2 OC3FE LL_TIM_OC_DisableFast\n + * CCMR2 OC4FE LL_TIM_OC_DisableFast\n + * CCMR3 OC5FE LL_TIM_OC_DisableFast\n + * CCMR3 OC6FE LL_TIM_OC_DisableFast + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); + +} + +/** + * @brief Indicates whether fast mode is enabled for the output channel. + * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n + * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n + * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n + * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n + * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n + * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]; + return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); +} + +/** + * @brief Enable compare register (TIMx_CCRx) preload for the output channel. + * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n + * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n + * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n + * CCMR2 OC4PE LL_TIM_OC_EnablePreload\n + * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n + * CCMR3 OC6PE LL_TIM_OC_EnablePreload + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); +} + +/** + * @brief Disable compare register (TIMx_CCRx) preload for the output channel. + * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n + * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n + * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n + * CCMR2 OC4PE LL_TIM_OC_DisablePreload\n + * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n + * CCMR3 OC6PE LL_TIM_OC_DisablePreload + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); +} + +/** + * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel. + * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n + * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n + * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n + * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n + * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n + * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]; + return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); +} + +/** + * @brief Enable clearing the output channel on an external event. + * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. + * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether + * or not a timer instance can clear the OCxREF signal on an external event. + * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n + * CCMR1 OC2CE LL_TIM_OC_EnableClear\n + * CCMR2 OC3CE LL_TIM_OC_EnableClear\n + * CCMR2 OC4CE LL_TIM_OC_EnableClear\n + * CCMR3 OC5CE LL_TIM_OC_EnableClear\n + * CCMR3 OC6CE LL_TIM_OC_EnableClear + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); +} + +/** + * @brief Disable clearing the output channel on an external event. + * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether + * or not a timer instance can clear the OCxREF signal on an external event. + * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n + * CCMR1 OC2CE LL_TIM_OC_DisableClear\n + * CCMR2 OC3CE LL_TIM_OC_DisableClear\n + * CCMR2 OC4CE LL_TIM_OC_DisableClear\n + * CCMR3 OC5CE LL_TIM_OC_DisableClear\n + * CCMR3 OC6CE LL_TIM_OC_DisableClear + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); +} + +/** + * @brief Indicates clearing the output channel on an external event is enabled for the output channel. + * @note This function enables clearing the output channel on an external event. + * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. + * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether + * or not a timer instance can clear the OCxREF signal on an external event. + * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n + * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n + * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n + * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n + * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n + * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]; + return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); +} + +/** + * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of + * the Ocx and OCxN signals). + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * dead-time insertion feature is supported by a timer instance. + * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter + * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime + * @param TIMx Timer instance + * @param DeadTime between Min_Data=0 and Max_Data=255 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime) +{ + MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime); +} + +/** + * @brief Set compare value for output channel 1 (TIMx_CCR1). + * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not + * output channel 1 is supported by a timer instance. + * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER . + * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1 + * @param TIMx Timer instance + * @param CompareValue between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue) +{ + WRITE_REG(TIMx->CCR1, CompareValue); +} + +/** + * @brief Set compare value for output channel 2 (TIMx_CCR2). + * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not + * output channel 2 is supported by a timer instance. + * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER . + * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2 + * @param TIMx Timer instance + * @param CompareValue between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue) +{ + WRITE_REG(TIMx->CCR2, CompareValue); +} + +/** + * @brief Set compare value for output channel 3 (TIMx_CCR3). + * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not + * output channel is supported by a timer instance. + * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER . + * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3 + * @param TIMx Timer instance + * @param CompareValue between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue) +{ + WRITE_REG(TIMx->CCR3, CompareValue); +} + +/** + * @brief Set compare value for output channel 4 (TIMx_CCR4). + * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not + * output channel 4 is supported by a timer instance. + * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER . + * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4 + * @param TIMx Timer instance + * @param CompareValue between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue) +{ + WRITE_REG(TIMx->CCR4, CompareValue); +} + +/** + * @brief Set compare value for output channel 5 (TIMx_CCR5). + * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not + * output channel 5 is supported by a timer instance. + * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER . + * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5 + * @param TIMx Timer instance + * @param CompareValue between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue) +{ + MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue); +} + +/** + * @brief Set compare value for output channel 6 (TIMx_CCR6). + * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not + * output channel 6 is supported by a timer instance. + * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER . + * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6 + * @param TIMx Timer instance + * @param CompareValue between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue) +{ + WRITE_REG(TIMx->CCR6, CompareValue); +} + +/** + * @brief Get compare value (TIMx_CCR1) set for output channel 1. + * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not + * output channel 1 is supported by a timer instance. + * @note If dithering is activated, pay attention to the returned value interpretation. + * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1 + * @param TIMx Timer instance + * @retval CompareValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR1)); +} + +/** + * @brief Get compare value (TIMx_CCR2) set for output channel 2. + * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not + * output channel 2 is supported by a timer instance. + * @note If dithering is activated, pay attention to the returned value interpretation. + * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2 + * @param TIMx Timer instance + * @retval CompareValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR2)); +} + +/** + * @brief Get compare value (TIMx_CCR3) set for output channel 3. + * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not + * output channel 3 is supported by a timer instance. + * @note If dithering is activated, pay attention to the returned value interpretation. + * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3 + * @param TIMx Timer instance + * @retval CompareValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR3)); +} + +/** + * @brief Get compare value (TIMx_CCR4) set for output channel 4. + * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not + * output channel 4 is supported by a timer instance. + * @note If dithering is activated, pay attention to the returned value interpretation. + * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4 + * @param TIMx Timer instance + * @retval CompareValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR4)); +} + +/** + * @brief Get compare value (TIMx_CCR5) set for output channel 5. + * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not + * output channel 5 is supported by a timer instance. + * @note If dithering is activated, pay attention to the returned value interpretation. + * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5 + * @param TIMx Timer instance + * @retval CompareValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5)); +} + +/** + * @brief Get compare value (TIMx_CCR6) set for output channel 6. + * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not + * output channel 6 is supported by a timer instance. + * @note If dithering is activated, pay attention to the returned value interpretation. + * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6 + * @param TIMx Timer instance + * @retval CompareValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR6)); +} + +/** + * @brief Select on which reference signal the OC5REF is combined to. + * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports the combined 3-phase PWM mode. + * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n + * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n + * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels + * @param TIMx Timer instance + * @param GroupCH5 This parameter can be a combination of the following values: + * @arg @ref LL_TIM_GROUPCH5_NONE + * @arg @ref LL_TIM_GROUPCH5_OC1REFC + * @arg @ref LL_TIM_GROUPCH5_OC2REFC + * @arg @ref LL_TIM_GROUPCH5_OC3REFC + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5) +{ + MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5); +} + +/** + * @brief Set the pulse on compare pulse width prescaler. + * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check + * whether or not the pulse on compare feature is supported by the timer + * instance. + * @rmtoll ECR PWPRSC LL_TIM_OC_SetPulseWidthPrescaler + * @param TIMx Timer instance + * @param PulseWidthPrescaler This parameter can be one of the following values: + * @arg @ref LL_TIM_PWPRSC_X1 + * @arg @ref LL_TIM_PWPRSC_X2 + * @arg @ref LL_TIM_PWPRSC_X4 + * @arg @ref LL_TIM_PWPRSC_X8 + * @arg @ref LL_TIM_PWPRSC_X16 + * @arg @ref LL_TIM_PWPRSC_X32 + * @arg @ref LL_TIM_PWPRSC_X64 + * @arg @ref LL_TIM_PWPRSC_X128 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetPulseWidthPrescaler(TIM_TypeDef *TIMx, uint32_t PulseWidthPrescaler) +{ + MODIFY_REG(TIMx->ECR, TIM_ECR_PWPRSC, PulseWidthPrescaler); +} + +/** + * @brief Get the pulse on compare pulse width prescaler. + * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check + * whether or not the pulse on compare feature is supported by the timer + * instance. + * @rmtoll ECR PWPRSC LL_TIM_OC_GetPulseWidthPrescaler + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_PWPRSC_X1 + * @arg @ref LL_TIM_PWPRSC_X2 + * @arg @ref LL_TIM_PWPRSC_X4 + * @arg @ref LL_TIM_PWPRSC_X8 + * @arg @ref LL_TIM_PWPRSC_X16 + * @arg @ref LL_TIM_PWPRSC_X32 + * @arg @ref LL_TIM_PWPRSC_X64 + * @arg @ref LL_TIM_PWPRSC_X128 + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetPulseWidthPrescaler(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_PWPRSC)); +} + +/** + * @brief Set the pulse on compare pulse width duration. + * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check + * whether or not the pulse on compare feature is supported by the timer + * instance. + * @rmtoll ECR PW LL_TIM_OC_SetPulseWidth + * @param TIMx Timer instance + * @param PulseWidth This parameter can be between Min_Data=0 and Max_Data=255 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetPulseWidth(TIM_TypeDef *TIMx, uint32_t PulseWidth) +{ + MODIFY_REG(TIMx->ECR, TIM_ECR_PW, PulseWidth << TIM_ECR_PW_Pos); +} + +/** + * @brief Get the pulse on compare pulse width duration. + * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check + * whether or not the pulse on compare feature is supported by the timer + * instance. + * @rmtoll ECR PW LL_TIM_OC_GetPulseWidth + * @param TIMx Timer instance + * @retval Returned value can be between Min_Data=0 and Max_Data=255: + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetPulseWidth(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_PW)); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration + * @{ + */ +/** + * @brief Configure input channel. + * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n + * CCMR1 IC1PSC LL_TIM_IC_Config\n + * CCMR1 IC1F LL_TIM_IC_Config\n + * CCMR1 CC2S LL_TIM_IC_Config\n + * CCMR1 IC2PSC LL_TIM_IC_Config\n + * CCMR1 IC2F LL_TIM_IC_Config\n + * CCMR2 CC3S LL_TIM_IC_Config\n + * CCMR2 IC3PSC LL_TIM_IC_Config\n + * CCMR2 IC3F LL_TIM_IC_Config\n + * CCMR2 CC4S LL_TIM_IC_Config\n + * CCMR2 IC4PSC LL_TIM_IC_Config\n + * CCMR2 IC4F LL_TIM_IC_Config\n + * CCER CC1P LL_TIM_IC_Config\n + * CCER CC1NP LL_TIM_IC_Config\n + * CCER CC2P LL_TIM_IC_Config\n + * CCER CC2NP LL_TIM_IC_Config\n + * CCER CC3P LL_TIM_IC_Config\n + * CCER CC3NP LL_TIM_IC_Config\n + * CCER CC4P LL_TIM_IC_Config\n + * CCER CC4NP LL_TIM_IC_Config + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC + * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8 + * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8 + * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), + ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \ + << SHIFT_TAB_ICxx[iChannel]); + MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), + (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); +} + +/** + * @brief Set the active input. + * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n + * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n + * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n + * CCMR2 CC4S LL_TIM_IC_SetActiveInput + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param ICActiveInput This parameter can be one of the following values: + * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI + * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI + * @arg @ref LL_TIM_ACTIVEINPUT_TRC + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]); +} + +/** + * @brief Get the current active input. + * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n + * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n + * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n + * CCMR2 CC4S LL_TIM_IC_GetActiveInput + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI + * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI + * @arg @ref LL_TIM_ACTIVEINPUT_TRC + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); +} + +/** + * @brief Set the prescaler of input channel. + * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n + * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n + * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n + * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param ICPrescaler This parameter can be one of the following values: + * @arg @ref LL_TIM_ICPSC_DIV1 + * @arg @ref LL_TIM_ICPSC_DIV2 + * @arg @ref LL_TIM_ICPSC_DIV4 + * @arg @ref LL_TIM_ICPSC_DIV8 + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]); +} + +/** + * @brief Get the current prescaler value acting on an input channel. + * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n + * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n + * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n + * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_ICPSC_DIV1 + * @arg @ref LL_TIM_ICPSC_DIV2 + * @arg @ref LL_TIM_ICPSC_DIV4 + * @arg @ref LL_TIM_ICPSC_DIV8 + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); +} + +/** + * @brief Set the input filter duration. + * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n + * CCMR1 IC2F LL_TIM_IC_SetFilter\n + * CCMR2 IC3F LL_TIM_IC_SetFilter\n + * CCMR2 IC4F LL_TIM_IC_SetFilter + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param ICFilter This parameter can be one of the following values: + * @arg @ref LL_TIM_IC_FILTER_FDIV1 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]); +} + +/** + * @brief Get the input filter duration. + * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n + * CCMR1 IC2F LL_TIM_IC_GetFilter\n + * CCMR2 IC3F LL_TIM_IC_GetFilter\n + * CCMR2 IC4F LL_TIM_IC_GetFilter + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_IC_FILTER_FDIV1 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); +} + +/** + * @brief Set the input channel polarity. + * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n + * CCER CC1NP LL_TIM_IC_SetPolarity\n + * CCER CC2P LL_TIM_IC_SetPolarity\n + * CCER CC2NP LL_TIM_IC_SetPolarity\n + * CCER CC3P LL_TIM_IC_SetPolarity\n + * CCER CC3NP LL_TIM_IC_SetPolarity\n + * CCER CC4P LL_TIM_IC_SetPolarity\n + * CCER CC4NP LL_TIM_IC_SetPolarity + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param ICPolarity This parameter can be one of the following values: + * @arg @ref LL_TIM_IC_POLARITY_RISING + * @arg @ref LL_TIM_IC_POLARITY_FALLING + * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), + ICPolarity << SHIFT_TAB_CCxP[iChannel]); +} + +/** + * @brief Get the current input channel polarity. + * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n + * CCER CC1NP LL_TIM_IC_GetPolarity\n + * CCER CC2P LL_TIM_IC_GetPolarity\n + * CCER CC2NP LL_TIM_IC_GetPolarity\n + * CCER CC3P LL_TIM_IC_GetPolarity\n + * CCER CC3NP LL_TIM_IC_GetPolarity\n + * CCER CC4P LL_TIM_IC_GetPolarity\n + * CCER CC4NP LL_TIM_IC_GetPolarity + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_IC_POLARITY_RISING + * @arg @ref LL_TIM_IC_POLARITY_FALLING + * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> + SHIFT_TAB_CCxP[iChannel]); +} + +/** + * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination). + * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an XOR input. + * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR2, TIM_CR2_TI1S); +} + +/** + * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input. + * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an XOR input. + * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S); +} + +/** + * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input. + * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an XOR input. + * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL); +} + +/** + * @brief Get captured value for input channel 1. + * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not + * input channel 1 is supported by a timer instance. + * @note If dithering is activated, pay attention to the returned value interpretation. + * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1 + * @param TIMx Timer instance + * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR1)); +} + +/** + * @brief Get captured value for input channel 2. + * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not + * input channel 2 is supported by a timer instance. + * @note If dithering is activated, pay attention to the returned value interpretation. + * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2 + * @param TIMx Timer instance + * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR2)); +} + +/** + * @brief Get captured value for input channel 3. + * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not + * input channel 3 is supported by a timer instance. + * @note If dithering is activated, pay attention to the returned value interpretation. + * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3 + * @param TIMx Timer instance + * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR3)); +} + +/** + * @brief Get captured value for input channel 4. + * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not + * input channel 4 is supported by a timer instance. + * @note If dithering is activated, pay attention to the returned value interpretation. + * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4 + * @param TIMx Timer instance + * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR4)); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection + * @{ + */ +/** + * @brief Enable external clock mode 2. + * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal. + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports external clock mode2. + * @rmtoll SMCR ECE LL_TIM_EnableExternalClock + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->SMCR, TIM_SMCR_ECE); +} + +/** + * @brief Disable external clock mode 2. + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports external clock mode2. + * @rmtoll SMCR ECE LL_TIM_DisableExternalClock + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE); +} + +/** + * @brief Indicate whether external clock mode 2 is enabled. + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports external clock mode2. + * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL); +} + +/** + * @brief Set the clock source of the counter clock. + * @note when selected clock source is external clock mode 1, the timer input + * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput() + * function. This timer input must be configured by calling + * the @ref LL_TIM_IC_Config() function. + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports external clock mode1. + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports external clock mode2. + * @rmtoll SMCR SMS LL_TIM_SetClockSource\n + * SMCR ECE LL_TIM_SetClockSource + * @param TIMx Timer instance + * @param ClockSource This parameter can be one of the following values: + * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL + * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1 + * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource); +} + +/** + * @brief Set the encoder interface mode. + * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports the encoder mode. + * @rmtoll SMCR SMS LL_TIM_SetEncoderMode + * @param TIMx Timer instance + * @param EncoderMode This parameter can be one of the following values: + * @arg @ref LL_TIM_ENCODERMODE_X2_TI1 + * @arg @ref LL_TIM_ENCODERMODE_X2_TI2 + * @arg @ref LL_TIM_ENCODERMODE_X4_TI12 + * @arg @ref LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2 + * @arg @ref LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1 + * @arg @ref LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X2 + * @arg @ref LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12 + * @arg @ref LL_TIM_ENCODERMODE_X1_TI1 + * @arg @ref LL_TIM_ENCODERMODE_X1_TI2 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration + * @{ + */ +/** + * @brief Set the trigger output (TRGO) used for timer synchronization . + * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance can operate as a master timer. + * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput + * @param TIMx Timer instance + * @param TimerSynchronization This parameter can be one of the following values: + * @arg @ref LL_TIM_TRGO_RESET + * @arg @ref LL_TIM_TRGO_ENABLE + * @arg @ref LL_TIM_TRGO_UPDATE + * @arg @ref LL_TIM_TRGO_CC1IF + * @arg @ref LL_TIM_TRGO_OC1REF + * @arg @ref LL_TIM_TRGO_OC2REF + * @arg @ref LL_TIM_TRGO_OC3REF + * @arg @ref LL_TIM_TRGO_OC4REF + * @arg @ref LL_TIM_TRGO_ENCODERCLK + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization) +{ + MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization); +} + +/** + * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization . + * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check + * whether or not a timer instance can be used for ADC synchronization. + * @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2 + * @param TIMx Timer Instance + * @param ADCSynchronization This parameter can be one of the following values: + * @arg @ref LL_TIM_TRGO2_RESET + * @arg @ref LL_TIM_TRGO2_ENABLE + * @arg @ref LL_TIM_TRGO2_UPDATE + * @arg @ref LL_TIM_TRGO2_CC1F + * @arg @ref LL_TIM_TRGO2_OC1 + * @arg @ref LL_TIM_TRGO2_OC2 + * @arg @ref LL_TIM_TRGO2_OC3 + * @arg @ref LL_TIM_TRGO2_OC4 + * @arg @ref LL_TIM_TRGO2_OC5 + * @arg @ref LL_TIM_TRGO2_OC6 + * @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING + * @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING + * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING + * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING + * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING + * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization) +{ + MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization); +} + +/** + * @brief Set the synchronization mode of a slave timer. + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * a timer instance can operate as a slave timer. + * @rmtoll SMCR SMS LL_TIM_SetSlaveMode + * @param TIMx Timer instance + * @param SlaveMode This parameter can be one of the following values: + * @arg @ref LL_TIM_SLAVEMODE_DISABLED + * @arg @ref LL_TIM_SLAVEMODE_RESET + * @arg @ref LL_TIM_SLAVEMODE_GATED + * @arg @ref LL_TIM_SLAVEMODE_TRIGGER + * @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER + * @arg @ref LL_TIM_SLAVEMODE_COMBINED_GATEDRESET + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode); +} + +/** + * @brief Set the selects the trigger input to be used to synchronize the counter. + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * a timer instance can operate as a slave timer. + * @rmtoll SMCR TS LL_TIM_SetTriggerInput + * @param TIMx Timer instance + * @param TriggerInput This parameter can be one of the following values: + * @arg @ref LL_TIM_TS_ITR0 + * @arg @ref LL_TIM_TS_ITR1 + * @arg @ref LL_TIM_TS_ITR2 + * @arg @ref LL_TIM_TS_ITR7 + * @arg @ref LL_TIM_TS_ITR8 + * @arg @ref LL_TIM_TS_TI1F_ED + * @arg @ref LL_TIM_TS_TI1FP1 + * @arg @ref LL_TIM_TS_TI2FP2 + * @arg @ref LL_TIM_TS_ETRF + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput); +} + +/** + * @brief Enable the Master/Slave mode. + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * a timer instance can operate as a slave timer. + * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->SMCR, TIM_SMCR_MSM); +} + +/** + * @brief Disable the Master/Slave mode. + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * a timer instance can operate as a slave timer. + * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM); +} + +/** + * @brief Indicates whether the Master/Slave mode is enabled. + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * a timer instance can operate as a slave timer. + * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL); +} + +/** + * @brief Configure the external trigger (ETR) input. + * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an external trigger input. + * @rmtoll SMCR ETP LL_TIM_ConfigETR\n + * SMCR ETPS LL_TIM_ConfigETR\n + * SMCR ETF LL_TIM_ConfigETR + * @param TIMx Timer instance + * @param ETRPolarity This parameter can be one of the following values: + * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED + * @arg @ref LL_TIM_ETR_POLARITY_INVERTED + * @param ETRPrescaler This parameter can be one of the following values: + * @arg @ref LL_TIM_ETR_PRESCALER_DIV1 + * @arg @ref LL_TIM_ETR_PRESCALER_DIV2 + * @arg @ref LL_TIM_ETR_PRESCALER_DIV4 + * @arg @ref LL_TIM_ETR_PRESCALER_DIV8 + * @param ETRFilter This parameter can be one of the following values: + * @arg @ref LL_TIM_ETR_FILTER_FDIV1 + * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2 + * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4 + * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5 + * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5 + * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8 + * @retval None + */ +__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler, + uint32_t ETRFilter) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter); +} + +/** + * @brief Select the external trigger (ETR) input source. + * @note Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or + * not a timer instance supports ETR source selection. + * @rmtoll AF1 ETRSEL LL_TIM_SetETRSource + * @param TIMx Timer instance + * @param ETRSource This parameter can be one of the following values: + * + * For TIM1, the parameter is one of the following values: + * + * @arg @ref LL_TIM_TIM1_ETRSOURCE_GPIO + * @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP1 (*) + * @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP2 (*) + * @arg @ref LL_TIM_TIM1_ETRSOURCE_HSI + * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC4_AWD1 + * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC4_AWD2 + * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC4_AWD3 + * + * For TIM2, the parameter is one of the following values: + * + * @arg @ref LL_TIM_TIM2_ETRSOURCE_GPIO + * @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP1 (*) + * @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP2 (*) + * @arg @ref LL_TIM_TIM2_ETRSOURCE_HSI + * @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM3_ETR + * @arg @ref LL_TIM_TIM2_ETRSOURCE_LSE + * + * For TIM3, the parameter is one of the following values: + * + * @arg @ref LL_TIM_TIM3_ETRSOURCE_GPIO + * @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP1 (*) + * @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP2 (*) + * @arg @ref LL_TIM_TIM3_ETRSOURCE_HSI + * @arg @ref LL_TIM_TIM3_ETRSOURCE_TIM2_ETR + * @arg @ref LL_TIM_TIM3_ETRSOURCE_ADC4_AWD1 + * @arg @ref LL_TIM_TIM3_ETRSOURCE_ADC4_AWD2 + * @arg @ref LL_TIM_TIM3_ETRSOURCE_ADC4_AWD3 + * + * (*) Value not defined in all devices. \n + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource) +{ + MODIFY_REG(TIMx->AF1, TIMx_AF1_ETRSEL, ETRSource); +} + +/** + * @brief Enable SMS preload. + * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports the preload of SMS field in SMCR register. + * @rmtoll SMCR SMSPE LL_TIM_EnableSMSPreload + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableSMSPreload(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->SMCR, TIM_SMCR_SMSPE); +} + +/** + * @brief Disable SMS preload. + * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports the preload of SMS field in SMCR register. + * @rmtoll SMCR SMSPE LL_TIM_DisableSMSPreload + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableSMSPreload(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->SMCR, TIM_SMCR_SMSPE); +} + +/** + * @brief Indicate whether SMS preload is enabled. + * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports the preload of SMS field in SMCR register. + * @rmtoll SMCR SMSPE LL_TIM_IsEnabledSMSPreload + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledSMSPreload(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SMCR, TIM_SMCR_SMSPE) == (TIM_SMCR_SMSPE)) ? 1UL : 0UL); +} + +/** + * @brief Set the preload source of SMS. + * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports the preload of SMS field in SMCR register. + * @rmtoll SMCR SMSPS LL_TIM_SetSMSPreloadSource\n + * @param TIMx Timer instance + * @param PreloadSource This parameter can be one of the following values: + * @arg @ref LL_TIM_SMSPS_TIMUPDATE + * @arg @ref LL_TIM_SMSPS_INDEX + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetSMSPreloadSource(TIM_TypeDef *TIMx, uint32_t PreloadSource) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMSPS, PreloadSource); +} + +/** + * @brief Get the preload source of SMS. + * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports the preload of SMS field in SMCR register. + * @rmtoll SMCR SMSPS LL_TIM_GetSMSPreloadSource\n + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_SMSPS_TIMUPDATE + * @arg @ref LL_TIM_SMSPS_INDEX + */ +__STATIC_INLINE uint32_t LL_TIM_GetSMSPreloadSource(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->SMCR, TIM_SMCR_SMSPS)); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Break_Function Break function configuration + * @{ + */ +/** + * @brief Enable the break function. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR BKE LL_TIM_EnableBRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->BDTR, TIM_BDTR_BKE); +} + +/** + * @brief Disable the break function. + * @rmtoll BDTR BKE LL_TIM_DisableBRK + * @param TIMx Timer instance + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE); +} + +/** + * @brief Configure the break input. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @note Bidirectional mode is only supported by advanced timer instances. + * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not + * a timer instance is an advanced-control timer. + * @note In bidirectional mode (BKBID bit set), the Break input is configured both + * in input mode and in open drain output mode. Any active Break event will + * assert a low logic level on the Break input to indicate an internal break + * event to external devices. + * @note When bidirectional mode isn't supported, BreakAFMode must be set to + * LL_TIM_BREAK_AFMODE_INPUT. + * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n + * BDTR BKF LL_TIM_ConfigBRK\n + * BDTR BKBID LL_TIM_ConfigBRK + * @param TIMx Timer instance + * @param BreakPolarity This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_POLARITY_LOW + * @arg @ref LL_TIM_BREAK_POLARITY_HIGH + * @param BreakFilter This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_FILTER_FDIV1 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8 + * @param BreakAFMode This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_AFMODE_INPUT + * @arg @ref LL_TIM_BREAK_AFMODE_BIDIRECTIONAL + * @retval None + */ +__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter, + uint32_t BreakAFMode) +{ + MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF | TIM_BDTR_BKBID, BreakPolarity | BreakFilter | BreakAFMode); +} + +/** + * @brief Disarm the break input (when it operates in bidirectional mode). + * @note The break input can be disarmed only when it is configured in + * bidirectional mode and when when MOE is reset. + * @note Purpose is to be able to have the input voltage back to high-state, + * whatever the time constant on the output . + * @rmtoll BDTR BKDSRM LL_TIM_DisarmBRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisarmBRK(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM); +} + +/** + * @brief Enable the break 2 function. + * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a second break input. + * @rmtoll BDTR BK2E LL_TIM_EnableBRK2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E); +} + +/** + * @brief Disable the break 2 function. + * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a second break input. + * @rmtoll BDTR BK2E LL_TIM_DisableBRK2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E); +} + +/** + * @brief Configure the break 2 input. + * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a second break input. + * @note Bidirectional mode is only supported by advanced timer instances. + * Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not + * a timer instance is an advanced-control timer. + * @note In bidirectional mode (BK2BID bit set), the Break 2 input is configured both + * in input mode and in open drain output mode. Any active Break event will + * assert a low logic level on the Break 2 input to indicate an internal break + * event to external devices. + * @note When bidirectional mode isn't supported, Break2AFMode must be set to + * LL_TIM_BREAK2_AFMODE_INPUT. + * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n + * BDTR BK2F LL_TIM_ConfigBRK2\n + * BDTR BK2BID LL_TIM_ConfigBRK2 + * @param TIMx Timer instance + * @param Break2Polarity This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK2_POLARITY_LOW + * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH + * @param Break2Filter This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8 + * @param Break2AFMode This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK2_AFMODE_INPUT + * @arg @ref LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL + * @retval None + */ +__STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter, + uint32_t Break2AFMode) +{ + MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F | TIM_BDTR_BK2BID, Break2Polarity | Break2Filter | Break2AFMode); +} + +/** + * @brief Disarm the break 2 input (when it operates in bidirectional mode). + * @note The break 2 input can be disarmed only when it is configured in + * bidirectional mode and when when MOE is reset. + * @note Purpose is to be able to have the input voltage back to high-state, + * whatever the time constant on the output. + * @rmtoll BDTR BK2DSRM LL_TIM_DisarmBRK2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisarmBRK2(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM); +} + +/** + * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n + * BDTR OSSR LL_TIM_SetOffStates + * @param TIMx Timer instance + * @param OffStateIdle This parameter can be one of the following values: + * @arg @ref LL_TIM_OSSI_DISABLE + * @arg @ref LL_TIM_OSSI_ENABLE + * @param OffStateRun This parameter can be one of the following values: + * @arg @ref LL_TIM_OSSR_DISABLE + * @arg @ref LL_TIM_OSSR_ENABLE + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun) +{ + MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun); +} + +/** + * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active). + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->BDTR, TIM_BDTR_AOE); +} + +/** + * @brief Disable automatic output (MOE can be set only by software). + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE); +} + +/** + * @brief Indicate whether automatic output is enabled. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL); +} + +/** + * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register). + * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by + * software and is reset in case of break or break2 event + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->BDTR, TIM_BDTR_MOE); +} + +/** + * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register). + * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by + * software and is reset in case of break or break2 event. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE); +} + +/** + * @brief Indicates whether outputs are enabled. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL); +} + +/** + * @brief Enable the signals connected to the designated timer break input. + * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether + * or not a timer instance allows for break input selection. + * @rmtoll AF1 BKINE LL_TIM_EnableBreakInputSource\n + * AF1 BKCMP1E LL_TIM_EnableBreakInputSource\n + * AF1 BKCMP2E LL_TIM_EnableBreakInputSource\n + * AF2 BK2INE LL_TIM_EnableBreakInputSource\n + * AF2 BK2CMP1E LL_TIM_EnableBreakInputSource\n + * AF2 BK2CMP2E LL_TIM_EnableBreakInputSource\n + * @param TIMx Timer instance + * @param BreakInput This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_INPUT_BKIN + * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 + * @param Source This parameter can be one of the following values: + * @arg @ref LL_TIM_BKIN_SOURCE_BKIN + * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 + * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2 + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source) +{ + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); + SET_BIT(*pReg, Source); +} + +/** + * @brief Disable the signals connected to the designated timer break input. + * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether + * or not a timer instance allows for break input selection. + * @rmtoll AF1 BKINE LL_TIM_DisableBreakInputSource\n + * AF1 BKCMP1E LL_TIM_DisableBreakInputSource\n + * AF1 BKCMP2E LL_TIM_DisableBreakInputSource\n + * AF2 BK2INE LL_TIM_DisableBreakInputSource\n + * AF2 BK2CMP1E LL_TIM_DisableBreakInputSource\n + * AF2 BK2CMP2E LL_TIM_DisableBreakInputSource\n + * @param TIMx Timer instance + * @param BreakInput This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_INPUT_BKIN + * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 + * @param Source This parameter can be one of the following values: + * @arg @ref LL_TIM_BKIN_SOURCE_BKIN + * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 + * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2 + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source) +{ + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); + CLEAR_BIT(*pReg, Source); +} + +/** + * @brief Set the polarity of the break signal for the timer break input. + * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether + * or not a timer instance allows for break input selection. + * @rmtoll AF1 BKINP LL_TIM_SetBreakInputSourcePolarity\n + * AF1 BKCMP1P LL_TIM_SetBreakInputSourcePolarity\n + * AF1 BKCMP2P LL_TIM_SetBreakInputSourcePolarity\n + * AF2 BK2INP LL_TIM_SetBreakInputSourcePolarity\n + * AF2 BK2CMP1P LL_TIM_SetBreakInputSourcePolarity\n + * AF2 BK2CMP2P LL_TIM_SetBreakInputSourcePolarity + * @param TIMx Timer instance + * @param BreakInput This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_INPUT_BKIN + * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 + * @param Source This parameter can be one of the following values: + * @arg @ref LL_TIM_BKIN_SOURCE_BKIN + * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 + * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2 + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_TIM_BKIN_POLARITY_LOW + * @arg @ref LL_TIM_BKIN_POLARITY_HIGH + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source, + uint32_t Polarity) +{ + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); + MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE)); +} +/** + * @brief Enable asymmetrical deadtime. + * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides asymmetrical deadtime. + * @rmtoll DTR2 DTAE LL_TIM_EnableAsymmetricalDeadTime + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableAsymmetricalDeadTime(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DTR2, TIM_DTR2_DTAE); +} + +/** + * @brief Disable asymmetrical dead-time. + * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides asymmetrical deadtime. + * @rmtoll DTR2 DTAE LL_TIM_DisableAsymmetricalDeadTime + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableAsymmetricalDeadTime(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTAE); +} + +/** + * @brief Indicates whether asymmetrical deadtime is activated. + * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides asymmetrical deadtime. + * @rmtoll DTR2 DTAE LL_TIM_IsEnabledAsymmetricalDeadTime + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledAsymmetricalDeadTime(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTAE) == (TIM_DTR2_DTAE)) ? 1UL : 0UL); +} + +/** + * @brief Set the falling edge dead-time delay (delay inserted between the falling edge of the OCxREF signal and the + * rising edge of OCxN signals). + * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not + * asymmetrical dead-time insertion feature is supported by a timer instance. + * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter + * @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed + * (LOCK bits in TIMx_BDTR register). + * @rmtoll DTR2 DTGF LL_TIM_SetFallingDeadTime + * @param TIMx Timer instance + * @param DeadTime between Min_Data=0 and Max_Data=255 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetFallingDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime) +{ + MODIFY_REG(TIMx->DTR2, TIM_DTR2_DTGF, DeadTime); +} + +/** + * @brief Get the falling edge dead-time delay (delay inserted between the falling edge of the OCxREF signal and + * the rising edge of OCxN signals). + * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not + * asymmetrical dead-time insertion feature is supported by a timer instance. + * @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed + * (LOCK bits in TIMx_BDTR register). + * @rmtoll DTR2 DTGF LL_TIM_GetFallingDeadTime + * @param TIMx Timer instance + * @retval Returned value can be between Min_Data=0 and Max_Data=255: + */ +__STATIC_INLINE uint32_t LL_TIM_GetFallingDeadTime(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->DTR2, TIM_DTR2_DTGF)); +} + +/** + * @brief Enable deadtime preload. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides deadtime preload. + * @rmtoll DTR2 DTPE LL_TIM_EnableDeadTimePreload + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDeadTimePreload(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DTR2, TIM_DTR2_DTPE); +} + +/** + * @brief Disable dead-time preload. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides deadtime preload. + * @rmtoll DTR2 DTPE LL_TIM_DisableDeadTimePreload + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDeadTimePreload(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTPE); +} + +/** + * @brief Indicates whether deadtime preload is activated. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides deadtime preload. + * @rmtoll DTR2 DTPE LL_TIM_IsEnabledDeadTimePreload + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDeadTimePreload(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTPE) == (TIM_DTR2_DTPE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration + * @{ + */ +/** + * @brief Configures the timer DMA burst feature. + * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or + * not a timer instance supports the DMA burst mode. + * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n + * DCR DBA LL_TIM_ConfigDMABurst + * @param TIMx Timer instance + * @param DMABurstBaseAddress This parameter can be one of the following values: + * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2 + * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR + * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER + * @arg @ref LL_TIM_DMABURST_BASEADDR_SR + * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER + * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT + * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC + * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR + * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4 + * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3 + * @arg @ref LL_TIM_DMABURST_BASEADDR_DTR2 + * @arg @ref LL_TIM_DMABURST_BASEADDR_ECR + * @arg @ref LL_TIM_DMABURST_BASEADDR_TISEL + * @arg @ref LL_TIM_DMABURST_BASEADDR_AF1 + * @arg @ref LL_TIM_DMABURST_BASEADDR_AF2 + * @arg @ref LL_TIM_DMABURST_BASEADDR_OR + * @param DMABurstLength This parameter can be one of the following values: + * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER + * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_19TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_20TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_21TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_22TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_23TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_24TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_25TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_26TRANSFERS + * @param DMABurstSource This parameter can be one of the following values: + * @arg @ref LL_TIM_DMA_UPDATE + * @arg @ref LL_TIM_DMA_CC1 + * @arg @ref LL_TIM_DMA_CC2 + * @arg @ref LL_TIM_DMA_CC3 + * @arg @ref LL_TIM_DMA_CC4 + * @arg @ref LL_TIM_DMA_COM + * @arg @ref LL_TIM_DMA_TRIGGER + * @retval None + */ +__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength, + uint32_t DMABurstSource) +{ + MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA | TIM_DCR_DBSS), + (DMABurstBaseAddress | DMABurstLength | DMABurstSource)); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Encoder Encoder configuration + * @{ + */ + +/** + * @brief Enable encoder index. + * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an index input. + * @rmtoll ECR IE LL_TIM_EnableEncoderIndex + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableEncoderIndex(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->ECR, TIM_ECR_IE); +} + +/** + * @brief Disable encoder index. + * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an index input. + * @rmtoll ECR IE LL_TIM_DisableEncoderIndex + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableEncoderIndex(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->ECR, TIM_ECR_IE); +} + +/** + * @brief Indicate whether encoder index is enabled. + * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an index input. + * @rmtoll ECR IE LL_TIM_IsEnabledEncoderIndex + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledEncoderIndex(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->ECR, TIM_ECR_IE) == (TIM_ECR_IE)) ? 1U : 0U); +} + +/** + * @brief Set index direction + * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an index input. + * @rmtoll ECR IDIR LL_TIM_SetIndexDirection + * @param TIMx Timer instance + * @param IndexDirection This parameter can be one of the following values: + * @arg @ref LL_TIM_INDEX_UP_DOWN + * @arg @ref LL_TIM_INDEX_UP + * @arg @ref LL_TIM_INDEX_DOWN + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetIndexDirection(TIM_TypeDef *TIMx, uint32_t IndexDirection) +{ + MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR, IndexDirection); +} + +/** + * @brief Get actual index direction + * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an index input. + * @rmtoll ECR IDIR LL_TIM_GetIndexDirection + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_INDEX_UP_DOWN + * @arg @ref LL_TIM_INDEX_UP + * @arg @ref LL_TIM_INDEX_DOWN + */ +__STATIC_INLINE uint32_t LL_TIM_GetIndexDirection(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IDIR)); +} + +/** + * @brief Set index blanking + * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an index input. + * @rmtoll ECR IBLK LL_TIM_SetIndexblanking + * @param TIMx Timer instance + * @param Indexblanking This parameter can be one of the following values: + * @arg @ref LL_TIM_INDEX_BLANK_ALWAYS + * @arg @ref LL_TIM_INDEX_BLANK_TI3 + * @arg @ref LL_TIM_INDEX_BLANK_TI4 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetIndexblanking(TIM_TypeDef *TIMx, uint32_t Indexblanking) +{ + MODIFY_REG(TIMx->ECR, TIM_ECR_IBLK, Indexblanking); +} + +/** + * @brief Get actual index blanking + * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an index input. + * @rmtoll ECR IBLK LL_TIM_GetIndexblanking + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_INDEX_BLANK_ALWAYS + * @arg @ref LL_TIM_INDEX_BLANK_TI3 + * @arg @ref LL_TIM_INDEX_BLANK_TI4 + */ +__STATIC_INLINE uint32_t LL_TIM_GetIndexblanking(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IBLK)); +} + + +/** + * @brief Enable first index. + * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an index input. + * @rmtoll ECR FIDX LL_TIM_EnableFirstIndex + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableFirstIndex(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->ECR, TIM_ECR_FIDX); +} + +/** + * @brief Disable first index. + * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an index input. + * @rmtoll ECR FIDX LL_TIM_DisableFirstIndex + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableFirstIndex(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->ECR, TIM_ECR_FIDX); +} + +/** + * @brief Indicates whether first index is enabled. + * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an index input. + * @rmtoll ECR FIDX LL_TIM_IsEnabledFirstIndex + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledFirstIndex(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->ECR, TIM_ECR_FIDX) == (TIM_ECR_FIDX)) ? 1UL : 0UL); +} + +/** + * @brief Set index positioning + * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an index input. + * @rmtoll ECR IPOS LL_TIM_SetIndexPositionning + * @param TIMx Timer instance + * @param IndexPositionning This parameter can be one of the following values: + * @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN + * @arg @ref LL_TIM_INDEX_POSITION_DOWN_UP + * @arg @ref LL_TIM_INDEX_POSITION_UP_DOWN + * @arg @ref LL_TIM_INDEX_POSITION_UP_UP + * @arg @ref LL_TIM_INDEX_POSITION_DOWN + * @arg @ref LL_TIM_INDEX_POSITION_UP + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetIndexPositionning(TIM_TypeDef *TIMx, uint32_t IndexPositionning) +{ + MODIFY_REG(TIMx->ECR, TIM_ECR_IPOS, IndexPositionning); +} + +/** + * @brief Get actual index positioning + * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an index input. + * @rmtoll ECR IPOS LL_TIM_GetIndexPositionning + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN + * @arg @ref LL_TIM_INDEX_POSITION_DOWN_UP + * @arg @ref LL_TIM_INDEX_POSITION_UP_DOWN + * @arg @ref LL_TIM_INDEX_POSITION_UP_UP + * @arg @ref LL_TIM_INDEX_POSITION_DOWN + * @arg @ref LL_TIM_INDEX_POSITION_UP + */ +__STATIC_INLINE uint32_t LL_TIM_GetIndexPositionning(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IPOS)); +} + +/** + * @brief Configure encoder index. + * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an index input. + * @rmtoll ECR IDIR LL_TIM_ConfigIDX\n + * ECR IBLK LL_TIM_ConfigIDX\n + * ECR FIDX LL_TIM_ConfigIDX\n + * ECR IPOS LL_TIM_ConfigIDX + * @param TIMx Timer instance + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_TIM_INDEX_UP or @ref LL_TIM_INDEX_DOWN or @ref LL_TIM_INDEX_UP_DOWN + * @arg @ref LL_TIM_INDEX_BLANK_ALWAYS or @ref LL_TIM_INDEX_BLANK_TI3 or @ref LL_TIM_INDEX_BLANK_TI4 + * @arg @ref LL_TIM_INDEX_ALL or @ref LL_TIM_INDEX_FIRST_ONLY + * @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN or ... or @ref LL_TIM_INDEX_POSITION_UP + * @retval None + */ +__STATIC_INLINE void LL_TIM_ConfigIDX(TIM_TypeDef *TIMx, uint32_t Configuration) +{ + MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR | TIM_ECR_IBLK | TIM_ECR_FIDX | TIM_ECR_IPOS, Configuration); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping + * @{ + */ +/** + * @brief Remap TIM inputs (input channel, internal/external triggers). + * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not + * a some timer inputs can be remapped. + * @rmtoll TIM1_TISEL TI1SEL LL_TIM_SetRemap\n + * TIM2_TISEL TI1SEL LL_TIM_SetRemap\n + * TIM2_TISEL TI2SEL LL_TIM_SetRemap\n + * TIM2_TISEL TI4SEL LL_TIM_SetRemap\n + * TIM3_TISEL TI1SEL LL_TIM_SetRemap\n + * TIM3_TISEL TI2SEL LL_TIM_SetRemap\n + * TIM16_TISEL TI1SEL LL_TIM_SetRemap\n + * TIM17_TISEL TI1SEL LL_TIM_SetRemap + * @param TIMx Timer instance + * @param Remap Remap param depends on the TIMx. Description available only + * in CHM version of the User Manual (not in .pdf). + * Otherwise see Reference Manual description of TISEL registers. + * + * Below description summarizes "Timer Instance" and "Remap" param combinations: + * + * TIM1: one of the following values: + * @arg LL_TIM_TIM1_TI1_RMP_GPIO: TIM1 TI1 is connected to GPIO + * @arg LL_TIM_TIM1_TI1_RMP_COMP1: TIM1 TI1 is connected to COMP1 output (*) + * @arg LL_TIM_TIM1_TI1_RMP_COMP2: TIM1 TI1 is connected to COMP2 output (*) + * + * TIM2: one of the following values: + * @arg LL_TIM_TIM2_TI1_RMP_GPIO: TIM2 TI1 is connected to GPIO + * @arg LL_TIM_TIM2_TI1_RMP_COMP1: TIM2 TI1 is connected to COMP1 output (*) + * @arg LL_TIM_TIM2_TI1_RMP_COMP2: TIM2 TI1 is connected to COMP2 output (*) + * @arg LL_TIM_TIM2_TI2_RMP_GPIO: TIM2 TI2 is connected to GPIO + * @arg LL_TIM_TIM2_TI2_RMP_COMP1: TIM2 TI2 is connected to COMP1 output (*) + * @arg LL_TIM_TIM2_TI2_RMP_COMP2: TIM2 TI2 is connected to COMP2 output (*) + * @arg LL_TIM_TIM2_TI4_RMP_GPIO: TIM2 TI4 is connected to GPIO + * @arg LL_TIM_TIM2_TI4_RMP_COMP1: TIM2 TI4 is connected to COMP1 output (*) + * @arg LL_TIM_TIM2_TI4_RMP_COMP2: TIM2 TI4 is connected to COMP2 output (*) + * + * TIM3: one of the following values: + * @arg LL_TIM_TIM3_TI1_RMP_GPIO: TIM3 TI1 is connected to GPIO + * @arg LL_TIM_TIM3_TI1_RMP_COMP1: TIM3 TI1 is connected to COMP1 output (*) + * @arg LL_TIM_TIM3_TI1_RMP_COMP2: TIM3 TI1 is connected to COMP2 output (*) + * @arg LL_TIM_TIM3_TI2_RMP_GPIO: TIM3 TI2 is connected to GPIO + * @arg LL_TIM_TIM3_TI2_RMP_COMP1: TIM3 TI2 is connected to COMP1 output (*) + * @arg LL_TIM_TIM3_TI2_RMP_COMP2: TIM3 TI2 is connected to COMP2 output (*) + * + * TIM16: one of the following values: + * @arg LL_TIM_TIM16_TI1_RMP_GPIO: TIM16 TI1 is connected to GPIO + * @arg LL_TIM_TIM16_TI1_RMP_MCO: TIM16 TI1 is connected to MCO + * @arg LL_TIM_TIM16_TI1_RMP_HSE_DIV32: TIM16 TI1 is connected to HSE DIV32 + * @arg LL_TIM_TIM16_TI1_RMP_RTC: TIM16 TI1 is connected to RTC + * @arg LL_TIM_TIM16_TI1_RMP_LSE: TIM16 TI1 is connected to LSE + * @arg LL_TIM_TIM16_TI1_RMP_LSI: TIM16 TI1 is connected to LSI + * @arg LL_TIM_TIM16_TI1_RMP_HSI_256: TIM16 TI1 is connected to HSI/256 + * + * TIM17: one of the following values: + * @arg LL_TIM_TIM17_TI1_RMP_GPIO: TIM17 TI1 is connected to GPIO + * @arg LL_TIM_TIM17_TI1_RMP_MCO: TIM17 TI1 is connected to MCO + * @arg LL_TIM_TIM17_TI1_RMP_HSE_DIV32: TIM17 TI1 is connected to HSE DIV32 + * @arg LL_TIM_TIM17_TI1_RMP_RTC: TIM17 TI1 is connected to RTC + * @arg LL_TIM_TIM17_TI1_RMP_LSE: TIM17 TI1 is connected to LSE + * @arg LL_TIM_TIM17_TI1_RMP_LSI: TIM17 TI1 is connected to LSI + * @arg LL_TIM_TIM17_TI1_RMP_HSI_256: TIM17 TI1 is connected to HSI/256 + * + * (*) Value not defined in all devices. \n + + * + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap) +{ + MODIFY_REG(TIMx->TISEL, (TIM_TISEL_TI1SEL | TIM_TISEL_TI2SEL | TIM_TISEL_TI3SEL | TIM_TISEL_TI4SEL), Remap); +} + +/** + * @brief Enable request for HSE/32 clock used for TISEL remap. + * @note Only TIM16 and TIM17 support HSE/32 remap + * @rmtoll OR HSE32EN LL_TIM_EnableHSE32 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableHSE32(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->OR, TIM_OR_HSE32EN); +} + +/** + * @brief Disable request for HSE/32 clock used for TISEL remap. + * @note Only TIM16 and TIM17 support HSE/32 remap + * @rmtoll OR HSE32EN LL_TIM_DisableHSE32 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableHSE32(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->OR, TIM_OR_HSE32EN); +} + +/** + * @brief Indicate whether request for HSE/32 clock is enabled. + * @note Only TIM16 and TIM17 support HSE/32 remap + * @rmtoll OR HSE32EN LL_TIM_IsEnabledHSE32 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledHSE32(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->OR, TIM_OR_HSE32EN) == (TIM_OR_HSE32EN)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management + * @{ + */ +/** + * @brief Set the OCREF clear input source + * @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT + * @note This function can only be used in Output compare and PWM modes. + * @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource + * @rmtoll AF2 OCRSEL LL_TIM_SetOCRefClearInputSource + * @param TIMx Timer instance + * @param OCRefClearInputSource This parameter can be one of the following values: + * @arg @ref LL_TIM_OCREF_CLR_INT_ETR + * @arg @ref LL_TIM_OCREF_CLR_INT_COMP1 + * @arg @ref LL_TIM_OCREF_CLR_INT_COMP2 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS, + ((OCRefClearInputSource & OCREF_CLEAR_SELECT_MSK) >> OCREF_CLEAR_SELECT_POS) << TIM_SMCR_OCCS_Pos); + MODIFY_REG(TIMx->AF2, TIM_AF2_OCRSEL, OCRefClearInputSource); +} +/** + * @} + */ + +/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management + * @{ + */ +/** + * @brief Clear the update interrupt flag (UIF). + * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_UIF)); +} + +/** + * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending). + * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 1 interrupt flag (CC1F). + * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF)); +} + +/** + * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending). + * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 2 interrupt flag (CC2F). + * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF)); +} + +/** + * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending). + * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 3 interrupt flag (CC3F). + * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF)); +} + +/** + * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending). + * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 4 interrupt flag (CC4F). + * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF)); +} + +/** + * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending). + * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 5 interrupt flag (CC5F). + * @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF)); +} + +/** + * @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending). + * @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 6 interrupt flag (CC6F). + * @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF)); +} + +/** + * @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending). + * @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the commutation interrupt flag (COMIF). + * @rmtoll SR COMIF LL_TIM_ClearFlag_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF)); +} + +/** + * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending). + * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the trigger interrupt flag (TIF). + * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_TIF)); +} + +/** + * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending). + * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the break interrupt flag (BIF). + * @rmtoll SR BIF LL_TIM_ClearFlag_BRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_BIF)); +} + +/** + * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending). + * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the break 2 interrupt flag (B2IF). + * @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF)); +} + +/** + * @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending). + * @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF). + * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF)); +} + +/** + * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set + * (Capture/Compare 1 interrupt is pending). + * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF). + * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF)); +} + +/** + * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set + * (Capture/Compare 2 over-capture interrupt is pending). + * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF). + * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF)); +} + +/** + * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set + * (Capture/Compare 3 over-capture interrupt is pending). + * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF). + * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF)); +} + +/** + * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set + * (Capture/Compare 4 over-capture interrupt is pending). + * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the system break interrupt flag (SBIF). + * @rmtoll SR SBIF LL_TIM_ClearFlag_SYSBRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF)); +} + +/** + * @brief Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending). + * @rmtoll SR SBIF LL_TIM_IsActiveFlag_SYSBRK + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the transition error interrupt flag (TERRF). + * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides encoder error management. + * @rmtoll SR TERRF LL_TIM_ClearFlag_TERR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_TERR(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_TERRF)); +} + +/** + * @brief Indicate whether transition error interrupt flag (TERRF) is set (transition error interrupt is pending). + * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides encoder error management. + * @rmtoll SR TERRF LL_TIM_IsActiveFlag_TERR + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TERR(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_TERRF) == (TIM_SR_TERRF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the index error interrupt flag (IERRF). + * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides encoder error management. + * @rmtoll SR IERRF LL_TIM_ClearFlag_IERR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_IERR(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_IERRF)); +} + +/** + * @brief Indicate whether index error interrupt flag (IERRF) is set (index error interrupt is pending). + * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides encoder error management. + * @rmtoll SR IERRF LL_TIM_IsActiveFlag_IERR + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_IERR(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_IERRF) == (TIM_SR_IERRF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the direction change interrupt flag (DIRF). + * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides encoder interrupt management. + * @rmtoll SR DIRF LL_TIM_ClearFlag_DIR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_DIR(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_DIRF)); +} + +/** + * @brief Indicate whether direction change interrupt flag (DIRF) is set (direction change interrupt is pending). + * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides encoder interrupt management. + * @rmtoll SR DIRF LL_TIM_IsActiveFlag_DIR + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_DIR(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_DIRF) == (TIM_SR_DIRF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the index interrupt flag (IDXF). + * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides encoder interrupt management. + * @rmtoll SR IDXF LL_TIM_ClearFlag_IDX + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_IDX(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_IDXF)); +} + +/** + * @brief Indicate whether index interrupt flag (IDXF) is set (index interrupt is pending). + * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides encoder interrupt management. + * @rmtoll SR IDXF LL_TIM_IsActiveFlag_IDX + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_IDX(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_IDXF) == (TIM_SR_IDXF)) ? 1UL : 0UL); +} +/** + * @} + */ + +/** @defgroup TIM_LL_EF_IT_Management IT-Management + * @{ + */ +/** + * @brief Enable update interrupt (UIE). + * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_UIE); +} + +/** + * @brief Disable update interrupt (UIE). + * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE); +} + +/** + * @brief Indicates whether the update interrupt (UIE) is enabled. + * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 1 interrupt (CC1IE). + * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC1IE); +} + +/** + * @brief Disable capture/compare 1 interrupt (CC1IE). + * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE); +} + +/** + * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled. + * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 2 interrupt (CC2IE). + * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC2IE); +} + +/** + * @brief Disable capture/compare 2 interrupt (CC2IE). + * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE); +} + +/** + * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled. + * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 3 interrupt (CC3IE). + * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC3IE); +} + +/** + * @brief Disable capture/compare 3 interrupt (CC3IE). + * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE); +} + +/** + * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled. + * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 4 interrupt (CC4IE). + * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC4IE); +} + +/** + * @brief Disable capture/compare 4 interrupt (CC4IE). + * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE); +} + +/** + * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled. + * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL); +} + +/** + * @brief Enable commutation interrupt (COMIE). + * @rmtoll DIER COMIE LL_TIM_EnableIT_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_COMIE); +} + +/** + * @brief Disable commutation interrupt (COMIE). + * @rmtoll DIER COMIE LL_TIM_DisableIT_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE); +} + +/** + * @brief Indicates whether the commutation interrupt (COMIE) is enabled. + * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable trigger interrupt (TIE). + * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_TIE); +} + +/** + * @brief Disable trigger interrupt (TIE). + * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE); +} + +/** + * @brief Indicates whether the trigger interrupt (TIE) is enabled. + * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable break interrupt (BIE). + * @rmtoll DIER BIE LL_TIM_EnableIT_BRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_BIE); +} + +/** + * @brief Disable break interrupt (BIE). + * @rmtoll DIER BIE LL_TIM_DisableIT_BRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE); +} + +/** + * @brief Indicates whether the break interrupt (BIE) is enabled. + * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable transition error interrupt (TERRIE). + * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides encoder error management. + * @rmtoll DIER TERRIE LL_TIM_EnableIT_TERR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_TERR(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_TERRIE); +} + +/** + * @brief Disable transition error interrupt (TERRIE). + * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides encoder error management. + * @rmtoll DIER TERRIE LL_TIM_DisableIT_TERR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_TERR(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_TERRIE); +} + +/** + * @brief Indicates whether the transition error interrupt (TERRIE) is enabled. + * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides encoder error management. + * @rmtoll DIER TERRIE LL_TIM_IsEnabledIT_TERR + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TERR(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_TERRIE) == (TIM_DIER_TERRIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable index error interrupt (IERRIE). + * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides encoder error management. + * @rmtoll DIER IERRIE LL_TIM_EnableIT_IERR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_IERR(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_IERRIE); +} + +/** + * @brief Disable index error interrupt (IERRIE). + * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides encoder error management. + * @rmtoll DIER IERRIE LL_TIM_DisableIT_IERR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_IERR(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_IERRIE); +} + +/** + * @brief Indicates whether the index error interrupt (IERRIE) is enabled. + * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides encoder error management. + * @rmtoll DIER IERRIE LL_TIM_IsEnabledIT_IERR + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_IERR(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_IERRIE) == (TIM_DIER_IERRIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable direction change interrupt (DIRIE). + * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides encoder interrupt management. + * @rmtoll DIER DIRIE LL_TIM_EnableIT_DIR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_DIR(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_DIRIE); +} + +/** + * @brief Disable direction change interrupt (DIRIE). + * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides encoder interrupt management. + * @rmtoll DIER DIRIE LL_TIM_DisableIT_DIR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_DIR(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_DIRIE); +} + +/** + * @brief Indicates whether the direction change interrupt (DIRIE) is enabled. + * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides encoder interrupt management. + * @rmtoll DIER DIRIE LL_TIM_IsEnabledIT_DIR + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_DIR(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_DIRIE) == (TIM_DIER_DIRIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable index interrupt (IDXIE). + * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides encoder interrupt management. + * @rmtoll DIER IDXIE LL_TIM_EnableIT_IDX + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_IDX(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_IDXIE); +} + +/** + * @brief Disable index interrupt (IDXIE). + * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides encoder interrupt management. + * @rmtoll DIER IDXIE LL_TIM_DisableIT_IDX + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_IDX(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_IDXIE); +} + +/** + * @brief Indicates whether the index interrupt (IDXIE) is enabled. + * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides encoder interrupt management. + * @rmtoll DIER IDXIE LL_TIM_IsEnabledIT_IDX + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_IDX(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_IDXIE) == (TIM_DIER_IDXIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_DMA_Management DMA Management + * @{ + */ +/** + * @brief Enable update DMA request (UDE). + * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_UDE); +} + +/** + * @brief Disable update DMA request (UDE). + * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE); +} + +/** + * @brief Indicates whether the update DMA request (UDE) is enabled. + * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 1 DMA request (CC1DE). + * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC1DE); +} + +/** + * @brief Disable capture/compare 1 DMA request (CC1DE). + * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE); +} + +/** + * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled. + * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 2 DMA request (CC2DE). + * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC2DE); +} + +/** + * @brief Disable capture/compare 2 DMA request (CC2DE). + * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE); +} + +/** + * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled. + * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 3 DMA request (CC3DE). + * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC3DE); +} + +/** + * @brief Disable capture/compare 3 DMA request (CC3DE). + * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE); +} + +/** + * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled. + * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 4 DMA request (CC4DE). + * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC4DE); +} + +/** + * @brief Disable capture/compare 4 DMA request (CC4DE). + * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE); +} + +/** + * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled. + * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL); +} + +/** + * @brief Enable commutation DMA request (COMDE). + * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_COMDE); +} + +/** + * @brief Disable commutation DMA request (COMDE). + * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE); +} + +/** + * @brief Indicates whether the commutation DMA request (COMDE) is enabled. + * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL); +} + +/** + * @brief Enable trigger interrupt (TDE). + * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_TDE); +} + +/** + * @brief Disable trigger interrupt (TDE). + * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE); +} + +/** + * @brief Indicates whether the trigger interrupt (TDE) is enabled. + * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management + * @{ + */ +/** + * @brief Generate an update event. + * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_UG); +} + +/** + * @brief Generate Capture/Compare 1 event. + * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_CC1G); +} + +/** + * @brief Generate Capture/Compare 2 event. + * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_CC2G); +} + +/** + * @brief Generate Capture/Compare 3 event. + * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_CC3G); +} + +/** + * @brief Generate Capture/Compare 4 event. + * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_CC4G); +} + +/** + * @brief Generate commutation event. + * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_COMG); +} + +/** + * @brief Generate trigger event. + * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_TG); +} + +/** + * @brief Generate break event. + * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_BG); +} + +/** + * @brief Generate break 2 event. + * @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_B2G); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions + * @{ + */ + +ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx); +void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct); +ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct); +void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); +ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); +void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); +ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct); +void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); +ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); +void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); +ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); +void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); +ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* TIM1 || TIM2 || TIM3 || TIM6 || TIM7 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32WBAxx_LL_TIM_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_usart.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_usart.h new file mode 100644 index 0000000000..bfece693c4 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_usart.h @@ -0,0 +1,4491 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_ll_usart.h + * @author MCD Application Team + * @brief Header file of USART LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_LL_USART_H +#define STM32WBAxx_LL_USART_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx.h" + +/** @addtogroup STM32WBAxx_LL_Driver + * @{ + */ + +#if defined(USART1) || defined(USART2) + +/** @defgroup USART_LL USART + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup USART_LL_Private_Variables USART Private Variables + * @{ + */ +/* Array used to get the USART prescaler division decimal values versus @ref USART_LL_EC_PRESCALER values */ +static const uint32_t USART_PRESCALER_TAB[] = +{ + 1UL, + 2UL, + 4UL, + 6UL, + 8UL, + 10UL, + 12UL, + 16UL, + 32UL, + 64UL, + 128UL, + 256UL +}; +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup USART_LL_Private_Constants USART Private Constants + * @{ + */ +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup USART_LL_Private_Macros USART Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup USART_LL_ES_INIT USART Exported Init structures + * @{ + */ + +/** + * @brief LL USART Init Structure definition + */ +typedef struct +{ + uint32_t PrescalerValue; /*!< Specifies the Prescaler to compute the communication baud rate. + This parameter can be a value of @ref USART_LL_EC_PRESCALER. + + This feature can be modified afterwards using unitary + function @ref LL_USART_SetPrescaler().*/ + + uint32_t BaudRate; /*!< This field defines expected Usart communication baud rate. + + This feature can be modified afterwards using unitary + function @ref LL_USART_SetBaudRate().*/ + + uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref USART_LL_EC_DATAWIDTH. + + This feature can be modified afterwards using unitary + function @ref LL_USART_SetDataWidth().*/ + + uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref USART_LL_EC_STOPBITS. + + This feature can be modified afterwards using unitary + function @ref LL_USART_SetStopBitsLength().*/ + + uint32_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref USART_LL_EC_PARITY. + + This feature can be modified afterwards using unitary + function @ref LL_USART_SetParity().*/ + + uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled. + This parameter can be a value of @ref USART_LL_EC_DIRECTION. + + This feature can be modified afterwards using unitary + function @ref LL_USART_SetTransferDirection().*/ + + uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled. + This parameter can be a value of @ref USART_LL_EC_HWCONTROL. + + This feature can be modified afterwards using unitary + function @ref LL_USART_SetHWFlowCtrl().*/ + + uint32_t OverSampling; /*!< Specifies whether USART oversampling mode is 16 or 8. + This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING. + + This feature can be modified afterwards using unitary + function @ref LL_USART_SetOverSampling().*/ + +} LL_USART_InitTypeDef; + +/** + * @brief LL USART Clock Init Structure definition + */ +typedef struct +{ + uint32_t ClockOutput; /*!< Specifies whether the USART clock is enabled or disabled. + This parameter can be a value of @ref USART_LL_EC_CLOCK. + + USART HW configuration can be modified afterwards using unitary functions + @ref LL_USART_EnableSCLKOutput() or @ref LL_USART_DisableSCLKOutput(). + For more details, refer to description of this function. */ + + uint32_t ClockPolarity; /*!< Specifies the steady state of the serial clock. + This parameter can be a value of @ref USART_LL_EC_POLARITY. + + USART HW configuration can be modified afterwards using unitary + functions @ref LL_USART_SetClockPolarity(). + For more details, refer to description of this function. */ + + uint32_t ClockPhase; /*!< Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref USART_LL_EC_PHASE. + + USART HW configuration can be modified afterwards using unitary + functions @ref LL_USART_SetClockPhase(). + For more details, refer to description of this function. */ + + uint32_t LastBitClockPulse; /*!< Specifies whether the clock pulse corresponding to the last transmitted + data bit (MSB) has to be output on the SCLK pin in synchronous mode. + This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE. + + USART HW configuration can be modified afterwards using unitary + functions @ref LL_USART_SetLastClkPulseOutput(). + For more details, refer to description of this function. */ + +} LL_USART_ClockInitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup USART_LL_Exported_Constants USART Exported Constants + * @{ + */ + +/** @defgroup USART_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_USART_WriteReg function + * @{ + */ +#define LL_USART_ICR_PECF USART_ICR_PECF /*!< Parity error clear flag */ +#define LL_USART_ICR_FECF USART_ICR_FECF /*!< Framing error clear flag */ +#define LL_USART_ICR_NECF USART_ICR_NECF /*!< Noise error detected clear flag */ +#define LL_USART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error clear flag */ +#define LL_USART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected clear flag */ +#define LL_USART_ICR_TXFECF USART_ICR_TXFECF /*!< TX FIFO Empty clear flag */ +#define LL_USART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete clear flag */ +#define LL_USART_ICR_TCBGTCF USART_ICR_TCBGTCF /*!< Transmission completed before guard time clear flag */ +#define LL_USART_ICR_LBDCF USART_ICR_LBDCF /*!< LIN break detection clear flag */ +#define LL_USART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS clear flag */ +#define LL_USART_ICR_RTOCF USART_ICR_RTOCF /*!< Receiver timeout clear flag */ +#define LL_USART_ICR_EOBCF USART_ICR_EOBCF /*!< End of block clear flag */ +#define LL_USART_ICR_UDRCF USART_ICR_UDRCF /*!< SPI Slave Underrun clear flag */ +#define LL_USART_ICR_CMCF USART_ICR_CMCF /*!< Character match clear flag */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_USART_ReadReg function + * @{ + */ +#define LL_USART_ISR_PE USART_ISR_PE /*!< Parity error flag */ +#define LL_USART_ISR_FE USART_ISR_FE /*!< Framing error flag */ +#define LL_USART_ISR_NE USART_ISR_NE /*!< Noise detected flag */ +#define LL_USART_ISR_ORE USART_ISR_ORE /*!< Overrun error flag */ +#define LL_USART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detected flag */ +#define LL_USART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE /*!< Read data register or RX FIFO not empty flag */ +#define LL_USART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */ +#define LL_USART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF /*!< Transmit data register empty or TX FIFO Not Full flag*/ +#define LL_USART_ISR_LBDF USART_ISR_LBDF /*!< LIN break detection flag */ +#define LL_USART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */ +#define LL_USART_ISR_CTS USART_ISR_CTS /*!< CTS flag */ +#define LL_USART_ISR_RTOF USART_ISR_RTOF /*!< Receiver timeout flag */ +#define LL_USART_ISR_EOBF USART_ISR_EOBF /*!< End of block flag */ +#define LL_USART_ISR_UDR USART_ISR_UDR /*!< SPI Slave underrun error flag */ +#define LL_USART_ISR_ABRE USART_ISR_ABRE /*!< Auto baud rate error flag */ +#define LL_USART_ISR_ABRF USART_ISR_ABRF /*!< Auto baud rate flag */ +#define LL_USART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */ +#define LL_USART_ISR_CMF USART_ISR_CMF /*!< Character match flag */ +#define LL_USART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */ +#define LL_USART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup from Mute mode flag */ +#define LL_USART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable acknowledge flag */ +#define LL_USART_ISR_REACK USART_ISR_REACK /*!< Receive enable acknowledge flag */ +#define LL_USART_ISR_TXFE USART_ISR_TXFE /*!< TX FIFO empty flag */ +#define LL_USART_ISR_RXFF USART_ISR_RXFF /*!< RX FIFO full flag */ +#define LL_USART_ISR_TCBGT USART_ISR_TCBGT /*!< Transmission complete before guard time completion flag */ +#define LL_USART_ISR_RXFT USART_ISR_RXFT /*!< RX FIFO threshold flag */ +#define LL_USART_ISR_TXFT USART_ISR_TXFT /*!< TX FIFO threshold flag */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_USART_ReadReg and LL_USART_WriteReg functions + * @{ + */ +#define LL_USART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */ +#define LL_USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE /*!< Read data register and RXFIFO not empty interrupt enable */ +#define LL_USART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */ +#define LL_USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE /*!< Transmit data register empty and TX FIFO not full interrupt enable */ +#define LL_USART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */ +#define LL_USART_CR1_CMIE USART_CR1_CMIE /*!< Character match interrupt enable */ +#define LL_USART_CR1_RTOIE USART_CR1_RTOIE /*!< Receiver timeout interrupt enable */ +#define LL_USART_CR1_EOBIE USART_CR1_EOBIE /*!< End of Block interrupt enable */ +#define LL_USART_CR1_TXFEIE USART_CR1_TXFEIE /*!< TX FIFO empty interrupt enable */ +#define LL_USART_CR1_RXFFIE USART_CR1_RXFFIE /*!< RX FIFO full interrupt enable */ +#define LL_USART_CR2_LBDIE USART_CR2_LBDIE /*!< LIN break detection interrupt enable */ +#define LL_USART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */ +#define LL_USART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */ +#define LL_USART_CR3_TXFTIE USART_CR3_TXFTIE /*!< TX FIFO threshold interrupt enable */ +#define LL_USART_CR3_TCBGTIE USART_CR3_TCBGTIE /*!< Transmission complete before guard time interrupt enable */ +#define LL_USART_CR3_RXFTIE USART_CR3_RXFTIE /*!< RX FIFO threshold interrupt enable */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_FIFOTHRESHOLD FIFO Threshold + * @{ + */ +#define LL_USART_FIFOTHRESHOLD_1_8 0x00000000U /*!< FIFO reaches 1/8 of its depth */ +#define LL_USART_FIFOTHRESHOLD_1_4 0x00000001U /*!< FIFO reaches 1/4 of its depth */ +#define LL_USART_FIFOTHRESHOLD_1_2 0x00000002U /*!< FIFO reaches 1/2 of its depth */ +#define LL_USART_FIFOTHRESHOLD_3_4 0x00000003U /*!< FIFO reaches 3/4 of its depth */ +#define LL_USART_FIFOTHRESHOLD_7_8 0x00000004U /*!< FIFO reaches 7/8 of its depth */ +#define LL_USART_FIFOTHRESHOLD_8_8 0x00000005U /*!< FIFO becomes empty for TX and full for RX */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_DIRECTION Communication Direction + * @{ + */ +#define LL_USART_DIRECTION_NONE 0x00000000U /*!< Transmitter and Receiver are disabled */ +#define LL_USART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */ +#define LL_USART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */ +#define LL_USART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_PARITY Parity Control + * @{ + */ +#define LL_USART_PARITY_NONE 0x00000000U /*!< Parity control disabled */ +#define LL_USART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */ +#define LL_USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_WAKEUP Wakeup + * @{ + */ +#define LL_USART_WAKEUP_IDLELINE 0x00000000U /*!< USART wake up from Mute mode on Idle Line */ +#define LL_USART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< USART wake up from Mute mode on Address Mark */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_DATAWIDTH Datawidth + * @{ + */ +#define LL_USART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */ +#define LL_USART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */ +#define LL_USART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_OVERSAMPLING Oversampling + * @{ + */ +#define LL_USART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */ +#define LL_USART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */ +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup USART_LL_EC_CLOCK Clock Signal + * @{ + */ + +#define LL_USART_CLOCK_DISABLE 0x00000000U /*!< Clock signal not provided */ +#define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< Clock signal provided */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse + * @{ + */ +#define LL_USART_LASTCLKPULSE_NO_OUTPUT 0x00000000U /*!< The clock pulse of the last data bit is not output to the SCLK pin */ +#define LL_USART_LASTCLKPULSE_OUTPUT USART_CR2_LBCL /*!< The clock pulse of the last data bit is output to the SCLK pin */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_PHASE Clock Phase + * @{ + */ +#define LL_USART_PHASE_1EDGE 0x00000000U /*!< The first clock transition is the first data capture edge */ +#define LL_USART_PHASE_2EDGE USART_CR2_CPHA /*!< The second clock transition is the first data capture edge */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_POLARITY Clock Polarity + * @{ + */ +#define LL_USART_POLARITY_LOW 0x00000000U /*!< Steady low value on SCLK pin outside transmission window*/ +#define LL_USART_POLARITY_HIGH USART_CR2_CPOL /*!< Steady high value on SCLK pin outside transmission window */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_PRESCALER Clock Source Prescaler + * @{ + */ +#define LL_USART_PRESCALER_DIV1 0x00000000U /*!< Input clock not divided */ +#define LL_USART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock divided by 2 */ +#define LL_USART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock divided by 4 */ +#define LL_USART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 6 */ +#define LL_USART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock divided by 8 */ +#define LL_USART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 10 */ +#define LL_USART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1) /*!< Input clock divided by 12 */ +#define LL_USART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 16 */ +#define LL_USART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock divided by 32 */ +#define LL_USART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 64 */ +#define LL_USART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1) /*!< Input clock divided by 128 */ +#define LL_USART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 256 */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_STOPBITS Stop Bits + * @{ + */ +#define LL_USART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< 0.5 stop bit */ +#define LL_USART_STOPBITS_1 0x00000000U /*!< 1 stop bit */ +#define LL_USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< 1.5 stop bits */ +#define LL_USART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_TXRX TX RX Pins Swap + * @{ + */ +#define LL_USART_TXRX_STANDARD 0x00000000U /*!< TX/RX pins are used as defined in standard pinout */ +#define LL_USART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< TX and RX pins functions are swapped. */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion + * @{ + */ +#define LL_USART_RXPIN_LEVEL_STANDARD 0x00000000U /*!< RX pin signal works using the standard logic levels */ +#define LL_USART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal values are inverted. */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion + * @{ + */ +#define LL_USART_TXPIN_LEVEL_STANDARD 0x00000000U /*!< TX pin signal works using the standard logic levels */ +#define LL_USART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal values are inverted. */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_BINARY_LOGIC Binary Data Inversion + * @{ + */ +#define LL_USART_BINARY_LOGIC_POSITIVE 0x00000000U /*!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) */ +#define LL_USART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_BITORDER Bit Order + * @{ + */ +#define LL_USART_BITORDER_LSBFIRST 0x00000000U /*!< data is transmitted/received with data bit 0 first, following the start bit */ +#define LL_USART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first, following the start bit */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_AUTOBAUD_DETECT_ON Autobaud Detection + * @{ + */ +#define LL_USART_AUTOBAUD_DETECT_ON_STARTBIT 0x00000000U /*!< Measurement of the start bit is used to detect the baud rate */ +#define LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0 /*!< Falling edge to falling edge measurement. Received frame must start with a single bit = 1 -> Frame = Start10xxxxxx */ +#define LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME USART_CR2_ABRMODE_1 /*!< 0x7F frame detection */ +#define LL_USART_AUTOBAUD_DETECT_ON_55_FRAME (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0) /*!< 0x55 frame detection */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_ADDRESS_DETECT Address Length Detection + * @{ + */ +#define LL_USART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit address detection method selected */ +#define LL_USART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_HWCONTROL Hardware Control + * @{ + */ +#define LL_USART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */ +#define LL_USART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested when there is space in the receive buffer */ +#define LL_USART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */ +#define LL_USART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_IRDA_POWER IrDA Power + * @{ + */ +#define LL_USART_IRDA_POWER_NORMAL 0x00000000U /*!< IrDA normal power mode */ +#define LL_USART_IRDA_POWER_LOW USART_CR3_IRLP /*!< IrDA low power mode */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length + * @{ + */ +#define LL_USART_LINBREAK_DETECT_10B 0x00000000U /*!< 10-bit break detection method selected */ +#define LL_USART_LINBREAK_DETECT_11B USART_CR2_LBDL /*!< 11-bit break detection method selected */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_DE_POLARITY Driver Enable Polarity + * @{ + */ +#define LL_USART_DE_POLARITY_HIGH 0x00000000U /*!< DE signal is active high */ +#define LL_USART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_DMA_REG_DATA DMA Register Data + * @{ + */ +#define LL_USART_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */ +#define LL_USART_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_AUTOCR_TRIGSEL Autonomous Trigger Selection + * @brief USART Autonomous Trigger selection + * @{ + */ +#define LL_USART_GPDMA1_CH0_TCF_TRG 0U /*!< USART GPDMA1 channel0 Internal Trigger */ +#define LL_USART_GPDMA1_CH1_TCF_TRG 1U /*!< USART GPDMA1 channel1 Internal Trigger */ +#define LL_USART_GPDMA1_CH2_TCF_TRG 2U /*!< USART GPDMA1 channel2 Internal Trigger */ +#define LL_USART_GPDMA1_CH3_TCF_TRG 3U /*!< USART GPDMA1 channel3 Internal Trigger */ +#define LL_USART_EXTI_LINE6_TRG 4U /*!< USART EXTI line 6 Internal Trigger */ +#define LL_USART_EXTI_LINE9_TRG 5U /*!< USART EXTI line 9 Internal Trigger */ +#define LL_USART_LPTIM1_OUT_TRG 6U /*!< USART LPTIM1 out Internal Trigger */ +#if defined(LPTIM2) +#define LL_USART_LPTIM2_OUT_TRG 7U /*!< USART LPTIM2 out Internal Trigger */ +#endif /* LPTIM2 */ +#if defined(COMP12_COMMON) +#define LL_USART_COMP1_OUT_TRG 8U /*!< USART COMP1 out Internal Trigger */ +#define LL_USART_COMP2_OUT_TRG 9U /*!< USART COMP2 out Internal Trigger */ +#endif /* COMP12_COMMON */ +#define LL_USART_RTC_ALRA_TRG 10U /*!< USART RTC alarm Internal Trigger */ +#define LL_USART_RTC_WUT_TRG 11U /*!< USART RTC wakeup Internal Trigger */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_AUTOCR_TRIGPOL Autonomous Trigger Polarity + * @brief USART Autonomous Trigger Polarity + * @{ + */ +#define LL_USART_TRIG_POLARITY_RISING 0x00000000U /*!< USART triggered on rising edge */ +#define LL_USART_TRIG_POLARITY_FALLING USART_AUTOCR_TRIGPOL /*!< USART triggered on falling edge */ +/** + * @} + */ +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup USART_LL_Exported_Macros USART Exported Macros + * @{ + */ + +/** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in USART register + * @param __INSTANCE__ USART Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in USART register + * @param __INSTANCE__ USART Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper + * @{ + */ + +/** + * @brief Compute USARTDIV value according to Peripheral Clock and + * expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned) + * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance + * @param __PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_USART_PRESCALER_DIV1 + * @arg @ref LL_USART_PRESCALER_DIV2 + * @arg @ref LL_USART_PRESCALER_DIV4 + * @arg @ref LL_USART_PRESCALER_DIV6 + * @arg @ref LL_USART_PRESCALER_DIV8 + * @arg @ref LL_USART_PRESCALER_DIV10 + * @arg @ref LL_USART_PRESCALER_DIV12 + * @arg @ref LL_USART_PRESCALER_DIV16 + * @arg @ref LL_USART_PRESCALER_DIV32 + * @arg @ref LL_USART_PRESCALER_DIV64 + * @arg @ref LL_USART_PRESCALER_DIV128 + * @arg @ref LL_USART_PRESCALER_DIV256 + * @param __BAUDRATE__ Baud rate value to achieve + * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case + */ +#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) \ + (((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))*2U)\ + + ((__BAUDRATE__)/2U))/(__BAUDRATE__)) + +/** + * @brief Compute USARTDIV value according to Peripheral Clock and + * expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned) + * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance + * @param __PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_USART_PRESCALER_DIV1 + * @arg @ref LL_USART_PRESCALER_DIV2 + * @arg @ref LL_USART_PRESCALER_DIV4 + * @arg @ref LL_USART_PRESCALER_DIV6 + * @arg @ref LL_USART_PRESCALER_DIV8 + * @arg @ref LL_USART_PRESCALER_DIV10 + * @arg @ref LL_USART_PRESCALER_DIV12 + * @arg @ref LL_USART_PRESCALER_DIV16 + * @arg @ref LL_USART_PRESCALER_DIV32 + * @arg @ref LL_USART_PRESCALER_DIV64 + * @arg @ref LL_USART_PRESCALER_DIV128 + * @arg @ref LL_USART_PRESCALER_DIV256 + * @param __BAUDRATE__ Baud rate value to achieve + * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case + */ +#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) \ + ((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))\ + + ((__BAUDRATE__)/2U))/(__BAUDRATE__)) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup USART_LL_Exported_Functions USART Exported Functions + * @{ + */ + +/** @defgroup USART_LL_EF_Configuration Configuration functions + * @{ + */ + +/** + * @brief USART Enable + * @rmtoll CR1 UE LL_USART_Enable + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR1, USART_CR1_UE); +} + +/** + * @brief USART Disable (all USART prescalers and outputs are disabled) + * @note When USART is disabled, USART prescalers and outputs are stopped immediately, + * and current operations are discarded. The configuration of the USART is kept, but all the status + * flags, in the USARTx_ISR are set to their default values. + * @rmtoll CR1 UE LL_USART_Disable + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR1, USART_CR1_UE); +} + +/** + * @brief Indicate if USART is enabled + * @rmtoll CR1 UE LL_USART_IsEnabled + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabled(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL); +} + +/** + * @brief FIFO Mode Enable + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 FIFOEN LL_USART_EnableFIFO + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableFIFO(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR1, USART_CR1_FIFOEN); +} + +/** + * @brief FIFO Mode Disable + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 FIFOEN LL_USART_DisableFIFO + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableFIFO(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR1, USART_CR1_FIFOEN); +} + +/** + * @brief Indicate if FIFO Mode is enabled + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 FIFOEN LL_USART_IsEnabledFIFO + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledFIFO(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL); +} + +/** + * @brief Configure TX FIFO Threshold + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 TXFTCFG LL_USART_SetTXFIFOThreshold + * @param USARTx USART Instance + * @param Threshold This parameter can be one of the following values: + * @arg @ref LL_USART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_USART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_8_8 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetTXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold) +{ + ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos); +} + +/** + * @brief Return TX FIFO Threshold Configuration + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 TXFTCFG LL_USART_GetTXFIFOThreshold + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_USART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_8_8 + */ +__STATIC_INLINE uint32_t LL_USART_GetTXFIFOThreshold(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); +} + +/** + * @brief Configure RX FIFO Threshold + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 RXFTCFG LL_USART_SetRXFIFOThreshold + * @param USARTx USART Instance + * @param Threshold This parameter can be one of the following values: + * @arg @ref LL_USART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_USART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_8_8 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetRXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold) +{ + ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos); +} + +/** + * @brief Return RX FIFO Threshold Configuration + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 RXFTCFG LL_USART_GetRXFIFOThreshold + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_USART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_8_8 + */ +__STATIC_INLINE uint32_t LL_USART_GetRXFIFOThreshold(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); +} + +/** + * @brief Configure TX and RX FIFOs Threshold + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 TXFTCFG LL_USART_ConfigFIFOsThreshold\n + * CR3 RXFTCFG LL_USART_ConfigFIFOsThreshold + * @param USARTx USART Instance + * @param TXThreshold This parameter can be one of the following values: + * @arg @ref LL_USART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_USART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_8_8 + * @param RXThreshold This parameter can be one of the following values: + * @arg @ref LL_USART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_USART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_8_8 + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigFIFOsThreshold(USART_TypeDef *USARTx, uint32_t TXThreshold, uint32_t RXThreshold) +{ + ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | + (RXThreshold << USART_CR3_RXFTCFG_Pos)); +} + +/** + * @brief USART enabled in STOP Mode. + * @note When this function is enabled, USART is able to wake up the MCU from Stop mode, provided that + * USART clock selection is HSI or LSE in RCC. + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll CR1 UESM LL_USART_EnableInStopMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_UESM); +} + +/** + * @brief USART disabled in STOP Mode. + * @note When this function is disabled, USART is not able to wake up the MCU from Stop mode + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll CR1 UESM LL_USART_DisableInStopMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_UESM); +} + +/** + * @brief Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not) + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll CR1 UESM LL_USART_IsEnabledInStopMode + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL); +} + +/** + * @brief Receiver Enable (Receiver is enabled and begins searching for a start bit) + * @rmtoll CR1 RE LL_USART_EnableDirectionRx + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RE); +} + +/** + * @brief Receiver Disable + * @rmtoll CR1 RE LL_USART_DisableDirectionRx + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RE); +} + +/** + * @brief Transmitter Enable + * @rmtoll CR1 TE LL_USART_EnableDirectionTx + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TE); +} + +/** + * @brief Transmitter Disable + * @rmtoll CR1 TE LL_USART_DisableDirectionTx + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TE); +} + +/** + * @brief Configure simultaneously enabled/disabled states + * of Transmitter and Receiver + * @rmtoll CR1 RE LL_USART_SetTransferDirection\n + * CR1 TE LL_USART_SetTransferDirection + * @param USARTx USART Instance + * @param TransferDirection This parameter can be one of the following values: + * @arg @ref LL_USART_DIRECTION_NONE + * @arg @ref LL_USART_DIRECTION_RX + * @arg @ref LL_USART_DIRECTION_TX + * @arg @ref LL_USART_DIRECTION_TX_RX + * @retval None + */ +__STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirection) +{ + ATOMIC_MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection); +} + +/** + * @brief Return enabled/disabled states of Transmitter and Receiver + * @rmtoll CR1 RE LL_USART_GetTransferDirection\n + * CR1 TE LL_USART_GetTransferDirection + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_DIRECTION_NONE + * @arg @ref LL_USART_DIRECTION_RX + * @arg @ref LL_USART_DIRECTION_TX + * @arg @ref LL_USART_DIRECTION_TX_RX + */ +__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE)); +} + +/** + * @brief Configure Parity (enabled/disabled and parity mode if enabled). + * @note This function selects if hardware parity control (generation and detection) is enabled or disabled. + * When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position + * (9th or 8th bit depending on data width) and parity is checked on the received data. + * @rmtoll CR1 PS LL_USART_SetParity\n + * CR1 PCE LL_USART_SetParity + * @param USARTx USART Instance + * @param Parity This parameter can be one of the following values: + * @arg @ref LL_USART_PARITY_NONE + * @arg @ref LL_USART_PARITY_EVEN + * @arg @ref LL_USART_PARITY_ODD + * @retval None + */ +__STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity); +} + +/** + * @brief Return Parity configuration (enabled/disabled and parity mode if enabled) + * @rmtoll CR1 PS LL_USART_GetParity\n + * CR1 PCE LL_USART_GetParity + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_PARITY_NONE + * @arg @ref LL_USART_PARITY_EVEN + * @arg @ref LL_USART_PARITY_ODD + */ +__STATIC_INLINE uint32_t LL_USART_GetParity(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE)); +} + +/** + * @brief Set Receiver Wake Up method from Mute mode. + * @rmtoll CR1 WAKE LL_USART_SetWakeUpMethod + * @param USARTx USART Instance + * @param Method This parameter can be one of the following values: + * @arg @ref LL_USART_WAKEUP_IDLELINE + * @arg @ref LL_USART_WAKEUP_ADDRESSMARK + * @retval None + */ +__STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method); +} + +/** + * @brief Return Receiver Wake Up method from Mute mode + * @rmtoll CR1 WAKE LL_USART_GetWakeUpMethod + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_WAKEUP_IDLELINE + * @arg @ref LL_USART_WAKEUP_ADDRESSMARK + */ +__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE)); +} + +/** + * @brief Set Word length (i.e. nb of data bits, excluding start and stop bits) + * @rmtoll CR1 M0 LL_USART_SetDataWidth\n + * CR1 M1 LL_USART_SetDataWidth + * @param USARTx USART Instance + * @param DataWidth This parameter can be one of the following values: + * @arg @ref LL_USART_DATAWIDTH_7B + * @arg @ref LL_USART_DATAWIDTH_8B + * @arg @ref LL_USART_DATAWIDTH_9B + * @retval None + */ +__STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth); +} + +/** + * @brief Return Word length (i.e. nb of data bits, excluding start and stop bits) + * @rmtoll CR1 M0 LL_USART_GetDataWidth\n + * CR1 M1 LL_USART_GetDataWidth + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_DATAWIDTH_7B + * @arg @ref LL_USART_DATAWIDTH_8B + * @arg @ref LL_USART_DATAWIDTH_9B + */ +__STATIC_INLINE uint32_t LL_USART_GetDataWidth(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M)); +} + +/** + * @brief Allow switch between Mute Mode and Active mode + * @rmtoll CR1 MME LL_USART_EnableMuteMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableMuteMode(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_MME); +} + +/** + * @brief Prevent Mute Mode use. Set Receiver in active mode permanently. + * @rmtoll CR1 MME LL_USART_DisableMuteMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableMuteMode(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_MME); +} + +/** + * @brief Indicate if switch between Mute Mode and Active mode is allowed + * @rmtoll CR1 MME LL_USART_IsEnabledMuteMode + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL); +} + +/** + * @brief Set Oversampling to 8-bit or 16-bit mode + * @rmtoll CR1 OVER8 LL_USART_SetOverSampling + * @param USARTx USART Instance + * @param OverSampling This parameter can be one of the following values: + * @arg @ref LL_USART_OVERSAMPLING_16 + * @arg @ref LL_USART_OVERSAMPLING_8 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling); +} + +/** + * @brief Return Oversampling mode + * @rmtoll CR1 OVER8 LL_USART_GetOverSampling + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_OVERSAMPLING_16 + * @arg @ref LL_USART_OVERSAMPLING_8 + */ +__STATIC_INLINE uint32_t LL_USART_GetOverSampling(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8)); +} + +/** + * @brief Configure if Clock pulse of the last data bit is output to the SCLK pin or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 LBCL LL_USART_SetLastClkPulseOutput + * @param USARTx USART Instance + * @param LastBitClockPulse This parameter can be one of the following values: + * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT + * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT + * @retval None + */ +__STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPulse) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse); +} + +/** + * @brief Retrieve Clock pulse of the last data bit output configuration + * (Last bit Clock pulse output to the SCLK pin or not) + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 LBCL LL_USART_GetLastClkPulseOutput + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT + * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT + */ +__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL)); +} + +/** + * @brief Select the phase of the clock output on the SCLK pin in synchronous mode + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CPHA LL_USART_SetClockPhase + * @param USARTx USART Instance + * @param ClockPhase This parameter can be one of the following values: + * @arg @ref LL_USART_PHASE_1EDGE + * @arg @ref LL_USART_PHASE_2EDGE + * @retval None + */ +__STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase); +} + +/** + * @brief Return phase of the clock output on the SCLK pin in synchronous mode + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CPHA LL_USART_GetClockPhase + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_PHASE_1EDGE + * @arg @ref LL_USART_PHASE_2EDGE + */ +__STATIC_INLINE uint32_t LL_USART_GetClockPhase(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA)); +} + +/** + * @brief Select the polarity of the clock output on the SCLK pin in synchronous mode + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CPOL LL_USART_SetClockPolarity + * @param USARTx USART Instance + * @param ClockPolarity This parameter can be one of the following values: + * @arg @ref LL_USART_POLARITY_LOW + * @arg @ref LL_USART_POLARITY_HIGH + * @retval None + */ +__STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity); +} + +/** + * @brief Return polarity of the clock output on the SCLK pin in synchronous mode + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CPOL LL_USART_GetClockPolarity + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_POLARITY_LOW + * @arg @ref LL_USART_POLARITY_HIGH + */ +__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL)); +} + +/** + * @brief Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse) + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clock Phase configuration using @ref LL_USART_SetClockPhase() function + * - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function + * - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutput() function + * @rmtoll CR2 CPHA LL_USART_ConfigClock\n + * CR2 CPOL LL_USART_ConfigClock\n + * CR2 LBCL LL_USART_ConfigClock + * @param USARTx USART Instance + * @param Phase This parameter can be one of the following values: + * @arg @ref LL_USART_PHASE_1EDGE + * @arg @ref LL_USART_PHASE_2EDGE + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_USART_POLARITY_LOW + * @arg @ref LL_USART_POLARITY_HIGH + * @param LBCPOutput This parameter can be one of the following values: + * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT + * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCPOutput); +} + +/** + * @brief Configure Clock source prescaler for baudrate generator and oversampling + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll PRESC PRESCALER LL_USART_SetPrescaler + * @param USARTx USART Instance + * @param PrescalerValue This parameter can be one of the following values: + * @arg @ref LL_USART_PRESCALER_DIV1 + * @arg @ref LL_USART_PRESCALER_DIV2 + * @arg @ref LL_USART_PRESCALER_DIV4 + * @arg @ref LL_USART_PRESCALER_DIV6 + * @arg @ref LL_USART_PRESCALER_DIV8 + * @arg @ref LL_USART_PRESCALER_DIV10 + * @arg @ref LL_USART_PRESCALER_DIV12 + * @arg @ref LL_USART_PRESCALER_DIV16 + * @arg @ref LL_USART_PRESCALER_DIV32 + * @arg @ref LL_USART_PRESCALER_DIV64 + * @arg @ref LL_USART_PRESCALER_DIV128 + * @arg @ref LL_USART_PRESCALER_DIV256 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) +{ + MODIFY_REG(USARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue); +} + +/** + * @brief Retrieve the Clock source prescaler for baudrate generator and oversampling + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll PRESC PRESCALER LL_USART_GetPrescaler + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_PRESCALER_DIV1 + * @arg @ref LL_USART_PRESCALER_DIV2 + * @arg @ref LL_USART_PRESCALER_DIV4 + * @arg @ref LL_USART_PRESCALER_DIV6 + * @arg @ref LL_USART_PRESCALER_DIV8 + * @arg @ref LL_USART_PRESCALER_DIV10 + * @arg @ref LL_USART_PRESCALER_DIV12 + * @arg @ref LL_USART_PRESCALER_DIV16 + * @arg @ref LL_USART_PRESCALER_DIV32 + * @arg @ref LL_USART_PRESCALER_DIV64 + * @arg @ref LL_USART_PRESCALER_DIV128 + * @arg @ref LL_USART_PRESCALER_DIV256 + */ +__STATIC_INLINE uint32_t LL_USART_GetPrescaler(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->PRESC, USART_PRESC_PRESCALER)); +} + +/** + * @brief Enable Clock output on SCLK pin + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CLKEN LL_USART_EnableSCLKOutput + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_CLKEN); +} + +/** + * @brief Disable Clock output on SCLK pin + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CLKEN LL_USART_DisableSCLKOutput + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN); +} + +/** + * @brief Indicate if Clock output on SCLK pin is enabled + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CLKEN LL_USART_IsEnabledSCLKOutput + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL); +} + +/** + * @brief Set the length of the stop bits + * @rmtoll CR2 STOP LL_USART_SetStopBitsLength + * @param USARTx USART Instance + * @param StopBits This parameter can be one of the following values: + * @arg @ref LL_USART_STOPBITS_0_5 + * @arg @ref LL_USART_STOPBITS_1 + * @arg @ref LL_USART_STOPBITS_1_5 + * @arg @ref LL_USART_STOPBITS_2 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits); +} + +/** + * @brief Retrieve the length of the stop bits + * @rmtoll CR2 STOP LL_USART_GetStopBitsLength + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_STOPBITS_0_5 + * @arg @ref LL_USART_STOPBITS_1 + * @arg @ref LL_USART_STOPBITS_1_5 + * @arg @ref LL_USART_STOPBITS_2 + */ +__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP)); +} + +/** + * @brief Configure Character frame format (Datawidth, Parity control, Stop Bits) + * @note Call of this function is equivalent to following function call sequence : + * - Data Width configuration using @ref LL_USART_SetDataWidth() function + * - Parity Control and mode configuration using @ref LL_USART_SetParity() function + * - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function + * @rmtoll CR1 PS LL_USART_ConfigCharacter\n + * CR1 PCE LL_USART_ConfigCharacter\n + * CR1 M0 LL_USART_ConfigCharacter\n + * CR1 M1 LL_USART_ConfigCharacter\n + * CR2 STOP LL_USART_ConfigCharacter + * @param USARTx USART Instance + * @param DataWidth This parameter can be one of the following values: + * @arg @ref LL_USART_DATAWIDTH_7B + * @arg @ref LL_USART_DATAWIDTH_8B + * @arg @ref LL_USART_DATAWIDTH_9B + * @param Parity This parameter can be one of the following values: + * @arg @ref LL_USART_PARITY_NONE + * @arg @ref LL_USART_PARITY_EVEN + * @arg @ref LL_USART_PARITY_ODD + * @param StopBits This parameter can be one of the following values: + * @arg @ref LL_USART_STOPBITS_0_5 + * @arg @ref LL_USART_STOPBITS_1 + * @arg @ref LL_USART_STOPBITS_1_5 + * @arg @ref LL_USART_STOPBITS_2 + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity, + uint32_t StopBits) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth); + MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits); +} + +/** + * @brief Configure TX/RX pins swapping setting. + * @rmtoll CR2 SWAP LL_USART_SetTXRXSwap + * @param USARTx USART Instance + * @param SwapConfig This parameter can be one of the following values: + * @arg @ref LL_USART_TXRX_STANDARD + * @arg @ref LL_USART_TXRX_SWAPPED + * @retval None + */ +__STATIC_INLINE void LL_USART_SetTXRXSwap(USART_TypeDef *USARTx, uint32_t SwapConfig) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_SWAP, SwapConfig); +} + +/** + * @brief Retrieve TX/RX pins swapping configuration. + * @rmtoll CR2 SWAP LL_USART_GetTXRXSwap + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_TXRX_STANDARD + * @arg @ref LL_USART_TXRX_SWAPPED + */ +__STATIC_INLINE uint32_t LL_USART_GetTXRXSwap(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_SWAP)); +} + +/** + * @brief Configure RX pin active level logic + * @rmtoll CR2 RXINV LL_USART_SetRXPinLevel + * @param USARTx USART Instance + * @param PinInvMethod This parameter can be one of the following values: + * @arg @ref LL_USART_RXPIN_LEVEL_STANDARD + * @arg @ref LL_USART_RXPIN_LEVEL_INVERTED + * @retval None + */ +__STATIC_INLINE void LL_USART_SetRXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_RXINV, PinInvMethod); +} + +/** + * @brief Retrieve RX pin active level logic configuration + * @rmtoll CR2 RXINV LL_USART_GetRXPinLevel + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_RXPIN_LEVEL_STANDARD + * @arg @ref LL_USART_RXPIN_LEVEL_INVERTED + */ +__STATIC_INLINE uint32_t LL_USART_GetRXPinLevel(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_RXINV)); +} + +/** + * @brief Configure TX pin active level logic + * @rmtoll CR2 TXINV LL_USART_SetTXPinLevel + * @param USARTx USART Instance + * @param PinInvMethod This parameter can be one of the following values: + * @arg @ref LL_USART_TXPIN_LEVEL_STANDARD + * @arg @ref LL_USART_TXPIN_LEVEL_INVERTED + * @retval None + */ +__STATIC_INLINE void LL_USART_SetTXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_TXINV, PinInvMethod); +} + +/** + * @brief Retrieve TX pin active level logic configuration + * @rmtoll CR2 TXINV LL_USART_GetTXPinLevel + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_TXPIN_LEVEL_STANDARD + * @arg @ref LL_USART_TXPIN_LEVEL_INVERTED + */ +__STATIC_INLINE uint32_t LL_USART_GetTXPinLevel(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_TXINV)); +} + +/** + * @brief Configure Binary data logic. + * @note Allow to define how Logical data from the data register are send/received : + * either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H) + * @rmtoll CR2 DATAINV LL_USART_SetBinaryDataLogic + * @param USARTx USART Instance + * @param DataLogic This parameter can be one of the following values: + * @arg @ref LL_USART_BINARY_LOGIC_POSITIVE + * @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE + * @retval None + */ +__STATIC_INLINE void LL_USART_SetBinaryDataLogic(USART_TypeDef *USARTx, uint32_t DataLogic) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_DATAINV, DataLogic); +} + +/** + * @brief Retrieve Binary data configuration + * @rmtoll CR2 DATAINV LL_USART_GetBinaryDataLogic + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_BINARY_LOGIC_POSITIVE + * @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE + */ +__STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_DATAINV)); +} + +/** + * @brief Configure transfer bit order (either Less or Most Significant Bit First) + * @note MSB First means data is transmitted/received with the MSB first, following the start bit. + * LSB First means data is transmitted/received with data bit 0 first, following the start bit. + * @rmtoll CR2 MSBFIRST LL_USART_SetTransferBitOrder + * @param USARTx USART Instance + * @param BitOrder This parameter can be one of the following values: + * @arg @ref LL_USART_BITORDER_LSBFIRST + * @arg @ref LL_USART_BITORDER_MSBFIRST + * @retval None + */ +__STATIC_INLINE void LL_USART_SetTransferBitOrder(USART_TypeDef *USARTx, uint32_t BitOrder) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_MSBFIRST, BitOrder); +} + +/** + * @brief Return transfer bit order (either Less or Most Significant Bit First) + * @note MSB First means data is transmitted/received with the MSB first, following the start bit. + * LSB First means data is transmitted/received with data bit 0 first, following the start bit. + * @rmtoll CR2 MSBFIRST LL_USART_GetTransferBitOrder + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_BITORDER_LSBFIRST + * @arg @ref LL_USART_BITORDER_MSBFIRST + */ +__STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_MSBFIRST)); +} + +/** + * @brief Enable Auto Baud-Rate Detection + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll CR2 ABREN LL_USART_EnableAutoBaudRate + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableAutoBaudRate(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_ABREN); +} + +/** + * @brief Disable Auto Baud-Rate Detection + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll CR2 ABREN LL_USART_DisableAutoBaudRate + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_ABREN); +} + +/** + * @brief Indicate if Auto Baud-Rate Detection mechanism is enabled + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll CR2 ABREN LL_USART_IsEnabledAutoBaud + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN)) ? 1UL : 0UL); +} + +/** + * @brief Set Auto Baud-Rate mode bits + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll CR2 ABRMODE LL_USART_SetAutoBaudRateMode + * @param USARTx USART Instance + * @param AutoBaudRateMode This parameter can be one of the following values: + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME + * @retval None + */ +__STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx, uint32_t AutoBaudRateMode) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_ABRMODE, AutoBaudRateMode); +} + +/** + * @brief Return Auto Baud-Rate mode + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll CR2 ABRMODE LL_USART_GetAutoBaudRateMode + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME + */ +__STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ABRMODE)); +} + +/** + * @brief Enable Receiver Timeout + * @rmtoll CR2 RTOEN LL_USART_EnableRxTimeout + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableRxTimeout(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_RTOEN); +} + +/** + * @brief Disable Receiver Timeout + * @rmtoll CR2 RTOEN LL_USART_DisableRxTimeout + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableRxTimeout(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_RTOEN); +} + +/** + * @brief Indicate if Receiver Timeout feature is enabled + * @rmtoll CR2 RTOEN LL_USART_IsEnabledRxTimeout + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN)) ? 1UL : 0UL); +} + +/** + * @brief Set Address of the USART node. + * @note This is used in multiprocessor communication during Mute mode or Stop mode, + * for wake up with address mark detection. + * @note 4bits address node is used when 4-bit Address Detection is selected in ADDM7. + * (b7-b4 should be set to 0) + * 8bits address node is used when 7-bit Address Detection is selected in ADDM7. + * (This is used in multiprocessor communication during Mute mode or Stop mode, + * for wake up with 7-bit address mark detection. + * The MSB of the character sent by the transmitter should be equal to 1. + * It may also be used for character detection during normal reception, + * Mute mode inactive (for example, end of block detection in ModBus protocol). + * In this case, the whole received character (8-bit) is compared to the ADD[7:0] + * value and CMF flag is set on match) + * @rmtoll CR2 ADD LL_USART_ConfigNodeAddress\n + * CR2 ADDM7 LL_USART_ConfigNodeAddress + * @param USARTx USART Instance + * @param AddressLen This parameter can be one of the following values: + * @arg @ref LL_USART_ADDRESS_DETECT_4B + * @arg @ref LL_USART_ADDRESS_DETECT_7B + * @param NodeAddress 4 or 7 bit Address of the USART node. + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigNodeAddress(USART_TypeDef *USARTx, uint32_t AddressLen, uint32_t NodeAddress) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7, + (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos))); +} + +/** + * @brief Return 8 bit Address of the USART node as set in ADD field of CR2. + * @note If 4-bit Address Detection is selected in ADDM7, + * only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant) + * If 7-bit Address Detection is selected in ADDM7, + * only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant) + * @rmtoll CR2 ADD LL_USART_GetNodeAddress + * @param USARTx USART Instance + * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255) + */ +__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos); +} + +/** + * @brief Return Length of Node Address used in Address Detection mode (7-bit or 4-bit) + * @rmtoll CR2 ADDM7 LL_USART_GetNodeAddressLen + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_ADDRESS_DETECT_4B + * @arg @ref LL_USART_ADDRESS_DETECT_7B + */ +__STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADDM7)); +} + +/** + * @brief Enable RTS HW Flow Control + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 RTSE LL_USART_EnableRTSHWFlowCtrl + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_RTSE); +} + +/** + * @brief Disable RTS HW Flow Control + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 RTSE LL_USART_DisableRTSHWFlowCtrl + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE); +} + +/** + * @brief Enable CTS HW Flow Control + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 CTSE LL_USART_EnableCTSHWFlowCtrl + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_CTSE); +} + +/** + * @brief Disable CTS HW Flow Control + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 CTSE LL_USART_DisableCTSHWFlowCtrl + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE); +} + +/** + * @brief Configure HW Flow Control mode (both CTS and RTS) + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 RTSE LL_USART_SetHWFlowCtrl\n + * CR3 CTSE LL_USART_SetHWFlowCtrl + * @param USARTx USART Instance + * @param HardwareFlowControl This parameter can be one of the following values: + * @arg @ref LL_USART_HWCONTROL_NONE + * @arg @ref LL_USART_HWCONTROL_RTS + * @arg @ref LL_USART_HWCONTROL_CTS + * @arg @ref LL_USART_HWCONTROL_RTS_CTS + * @retval None + */ +__STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl) +{ + MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl); +} + +/** + * @brief Return HW Flow Control configuration (both CTS and RTS) + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 RTSE LL_USART_GetHWFlowCtrl\n + * CR3 CTSE LL_USART_GetHWFlowCtrl + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_HWCONTROL_NONE + * @arg @ref LL_USART_HWCONTROL_RTS + * @arg @ref LL_USART_HWCONTROL_CTS + * @arg @ref LL_USART_HWCONTROL_RTS_CTS + */ +__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE)); +} + +/** + * @brief Enable One bit sampling method + * @rmtoll CR3 ONEBIT LL_USART_EnableOneBitSamp + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_ONEBIT); +} + +/** + * @brief Disable One bit sampling method + * @rmtoll CR3 ONEBIT LL_USART_DisableOneBitSamp + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT); +} + +/** + * @brief Indicate if One bit sampling method is enabled + * @rmtoll CR3 ONEBIT LL_USART_IsEnabledOneBitSamp + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT)) ? 1UL : 0UL); +} + +/** + * @brief Enable Overrun detection + * @rmtoll CR3 OVRDIS LL_USART_EnableOverrunDetect + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableOverrunDetect(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_OVRDIS); +} + +/** + * @brief Disable Overrun detection + * @rmtoll CR3 OVRDIS LL_USART_DisableOverrunDetect + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableOverrunDetect(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_OVRDIS); +} + +/** + * @brief Indicate if Overrun detection is enabled + * @rmtoll CR3 OVRDIS LL_USART_IsEnabledOverrunDetect + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL); +} + +/** + * @brief Configure USART BRR register for achieving expected Baud Rate value. + * @note Compute and set USARTDIV value in BRR Register (full BRR content) + * according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values + * @note Peripheral clock and Baud rate values provided as function parameters should be valid + * (Baud rate value != 0) + * @note In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. + * @rmtoll BRR BRR LL_USART_SetBaudRate + * @param USARTx USART Instance + * @param PeriphClk Peripheral Clock + * @param PrescalerValue This parameter can be one of the following values: + * @arg @ref LL_USART_PRESCALER_DIV1 + * @arg @ref LL_USART_PRESCALER_DIV2 + * @arg @ref LL_USART_PRESCALER_DIV4 + * @arg @ref LL_USART_PRESCALER_DIV6 + * @arg @ref LL_USART_PRESCALER_DIV8 + * @arg @ref LL_USART_PRESCALER_DIV10 + * @arg @ref LL_USART_PRESCALER_DIV12 + * @arg @ref LL_USART_PRESCALER_DIV16 + * @arg @ref LL_USART_PRESCALER_DIV32 + * @arg @ref LL_USART_PRESCALER_DIV64 + * @arg @ref LL_USART_PRESCALER_DIV128 + * @arg @ref LL_USART_PRESCALER_DIV256 + * @param OverSampling This parameter can be one of the following values: + * @arg @ref LL_USART_OVERSAMPLING_16 + * @arg @ref LL_USART_OVERSAMPLING_8 + * @param BaudRate Baud Rate + * @retval None + */ +__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue, + uint32_t OverSampling, + uint32_t BaudRate) +{ + uint32_t usartdiv; + uint32_t brrtemp; + + if (PrescalerValue > LL_USART_PRESCALER_DIV256) + { + /* Do not overstep the size of USART_PRESCALER_TAB */ + } + else if (BaudRate == 0U) + { + /* Can Not divide per 0 */ + } + else if (OverSampling == LL_USART_OVERSAMPLING_8) + { + usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, (uint8_t)PrescalerValue, BaudRate)); + brrtemp = usartdiv & 0xFFF0U; + brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); + USARTx->BRR = brrtemp; + } + else + { + USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, (uint8_t)PrescalerValue, BaudRate)); + } +} + +/** + * @brief Return current Baud Rate value, according to USARTDIV present in BRR register + * (full BRR content), and to used Peripheral Clock and Oversampling mode values + * @note In case of non-initialized or invalid value stored in BRR register, value 0 will be returned. + * @note In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. + * @rmtoll BRR BRR LL_USART_GetBaudRate + * @param USARTx USART Instance + * @param PeriphClk Peripheral Clock + * @param PrescalerValue This parameter can be one of the following values: + * @arg @ref LL_USART_PRESCALER_DIV1 + * @arg @ref LL_USART_PRESCALER_DIV2 + * @arg @ref LL_USART_PRESCALER_DIV4 + * @arg @ref LL_USART_PRESCALER_DIV6 + * @arg @ref LL_USART_PRESCALER_DIV8 + * @arg @ref LL_USART_PRESCALER_DIV10 + * @arg @ref LL_USART_PRESCALER_DIV12 + * @arg @ref LL_USART_PRESCALER_DIV16 + * @arg @ref LL_USART_PRESCALER_DIV32 + * @arg @ref LL_USART_PRESCALER_DIV64 + * @arg @ref LL_USART_PRESCALER_DIV128 + * @arg @ref LL_USART_PRESCALER_DIV256 + * @param OverSampling This parameter can be one of the following values: + * @arg @ref LL_USART_OVERSAMPLING_16 + * @arg @ref LL_USART_OVERSAMPLING_8 + * @retval Baud Rate + */ +__STATIC_INLINE uint32_t LL_USART_GetBaudRate(const USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue, + uint32_t OverSampling) +{ + uint32_t usartdiv; + uint32_t brrresult = 0x0U; + uint32_t periphclkpresc = (uint32_t)(PeriphClk / (USART_PRESCALER_TAB[(uint8_t)PrescalerValue])); + + usartdiv = USARTx->BRR; + + if (usartdiv == 0U) + { + /* Do not perform a division by 0 */ + } + else if (OverSampling == LL_USART_OVERSAMPLING_8) + { + usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ; + if (usartdiv != 0U) + { + brrresult = (periphclkpresc * 2U) / usartdiv; + } + } + else + { + if ((usartdiv & 0xFFFFU) != 0U) + { + brrresult = periphclkpresc / usartdiv; + } + } + return (brrresult); +} + +/** + * @brief Set Receiver Time Out Value (expressed in nb of bits duration) + * @rmtoll RTOR RTO LL_USART_SetRxTimeout + * @param USARTx USART Instance + * @param Timeout Value between Min_Data=0x00 and Max_Data=0x00FFFFFF + * @retval None + */ +__STATIC_INLINE void LL_USART_SetRxTimeout(USART_TypeDef *USARTx, uint32_t Timeout) +{ + MODIFY_REG(USARTx->RTOR, USART_RTOR_RTO, Timeout); +} + +/** + * @brief Get Receiver Time Out Value (expressed in nb of bits duration) + * @rmtoll RTOR RTO LL_USART_GetRxTimeout + * @param USARTx USART Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x00FFFFFF + */ +__STATIC_INLINE uint32_t LL_USART_GetRxTimeout(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_RTO)); +} + +/** + * @brief Set Block Length value in reception + * @rmtoll RTOR BLEN LL_USART_SetBlockLength + * @param USARTx USART Instance + * @param BlockLength Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_USART_SetBlockLength(USART_TypeDef *USARTx, uint32_t BlockLength) +{ + MODIFY_REG(USARTx->RTOR, USART_RTOR_BLEN, BlockLength << USART_RTOR_BLEN_Pos); +} + +/** + * @brief Get Block Length value in reception + * @rmtoll RTOR BLEN LL_USART_GetBlockLength + * @param USARTx USART Instance + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_USART_GetBlockLength(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_BLEN) >> USART_RTOR_BLEN_Pos); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_IRDA Configuration functions related to Irda feature + * @{ + */ + +/** + * @brief Enable IrDA mode + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll CR3 IREN LL_USART_EnableIrda + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_IREN); +} + +/** + * @brief Disable IrDA mode + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll CR3 IREN LL_USART_DisableIrda + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_IREN); +} + +/** + * @brief Indicate if IrDA mode is enabled + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll CR3 IREN LL_USART_IsEnabledIrda + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN)) ? 1UL : 0UL); +} + +/** + * @brief Configure IrDA Power Mode (Normal or Low Power) + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll CR3 IRLP LL_USART_SetIrdaPowerMode + * @param USARTx USART Instance + * @param PowerMode This parameter can be one of the following values: + * @arg @ref LL_USART_IRDA_POWER_NORMAL + * @arg @ref LL_USART_IRDA_POWER_LOW + * @retval None + */ +__STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t PowerMode) +{ + MODIFY_REG(USARTx->CR3, USART_CR3_IRLP, PowerMode); +} + +/** + * @brief Retrieve IrDA Power Mode configuration (Normal or Low Power) + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll CR3 IRLP LL_USART_GetIrdaPowerMode + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_IRDA_POWER_NORMAL + * @arg @ref LL_USART_PHASE_2EDGE + */ +__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP)); +} + +/** + * @brief Set Irda prescaler value, used for dividing the USART clock source + * to achieve the Irda Low Power frequency (8 bits value) + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll GTPR PSC LL_USART_SetIrdaPrescaler + * @param USARTx USART Instance + * @param PrescalerValue Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) +{ + MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue); +} + +/** + * @brief Return Irda prescaler value, used for dividing the USART clock source + * to achieve the Irda Low Power frequency (8 bits value) + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll GTPR PSC LL_USART_GetIrdaPrescaler + * @param USARTx USART Instance + * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF) + */ +__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC)); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_Smartcard Configuration functions related to Smartcard feature + * @{ + */ + +/** + * @brief Enable Smartcard NACK transmission + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 NACK LL_USART_EnableSmartcardNACK + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_NACK); +} + +/** + * @brief Disable Smartcard NACK transmission + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 NACK LL_USART_DisableSmartcardNACK + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_NACK); +} + +/** + * @brief Indicate if Smartcard NACK transmission is enabled + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 NACK LL_USART_IsEnabledSmartcardNACK + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK)) ? 1UL : 0UL); +} + +/** + * @brief Enable Smartcard mode + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 SCEN LL_USART_EnableSmartcard + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_SCEN); +} + +/** + * @brief Disable Smartcard mode + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 SCEN LL_USART_DisableSmartcard + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_SCEN); +} + +/** + * @brief Indicate if Smartcard mode is enabled + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 SCEN LL_USART_IsEnabledSmartcard + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN)) ? 1UL : 0UL); +} + +/** + * @brief Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits) + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @note This bit-field specifies the number of retries in transmit and receive, in Smartcard mode. + * In transmission mode, it specifies the number of automatic retransmission retries, before + * generating a transmission error (FE bit set). + * In reception mode, it specifies the number or erroneous reception trials, before generating a + * reception error (RXNE and PE bits set) + * @rmtoll CR3 SCARCNT LL_USART_SetSmartcardAutoRetryCount + * @param USARTx USART Instance + * @param AutoRetryCount Value between Min_Data=0 and Max_Data=7 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount(USART_TypeDef *USARTx, uint32_t AutoRetryCount) +{ + MODIFY_REG(USARTx->CR3, USART_CR3_SCARCNT, AutoRetryCount << USART_CR3_SCARCNT_Pos); +} + +/** + * @brief Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits) + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 SCARCNT LL_USART_GetSmartcardAutoRetryCount + * @param USARTx USART Instance + * @retval Smartcard Auto-Retry Count value (Value between Min_Data=0 and Max_Data=7) + */ +__STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_SCARCNT) >> USART_CR3_SCARCNT_Pos); +} + +/** + * @brief Set Smartcard prescaler value, used for dividing the USART clock + * source to provide the SMARTCARD Clock (5 bits value) + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll GTPR PSC LL_USART_SetSmartcardPrescaler + * @param USARTx USART Instance + * @param PrescalerValue Value between Min_Data=0 and Max_Data=31 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) +{ + MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue); +} + +/** + * @brief Return Smartcard prescaler value, used for dividing the USART clock + * source to provide the SMARTCARD Clock (5 bits value) + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll GTPR PSC LL_USART_GetSmartcardPrescaler + * @param USARTx USART Instance + * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31) + */ +__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC)); +} + +/** + * @brief Set Smartcard Guard time value, expressed in nb of baud clocks periods + * (GT[7:0] bits : Guard time value) + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll GTPR GT LL_USART_SetSmartcardGuardTime + * @param USARTx USART Instance + * @param GuardTime Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime) +{ + MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, (uint16_t)(GuardTime << USART_GTPR_GT_Pos)); +} + +/** + * @brief Return Smartcard Guard time value, expressed in nb of baud clocks periods + * (GT[7:0] bits : Guard time value) + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll GTPR GT LL_USART_GetSmartcardGuardTime + * @param USARTx USART Instance + * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF) + */ +__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_GTPR_GT_Pos); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature + * @{ + */ + +/** + * @brief Enable Single Wire Half-Duplex mode + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * Half-Duplex mode is supported by the USARTx instance. + * @rmtoll CR3 HDSEL LL_USART_EnableHalfDuplex + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_HDSEL); +} + +/** + * @brief Disable Single Wire Half-Duplex mode + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * Half-Duplex mode is supported by the USARTx instance. + * @rmtoll CR3 HDSEL LL_USART_DisableHalfDuplex + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL); +} + +/** + * @brief Indicate if Single Wire Half-Duplex mode is enabled + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * Half-Duplex mode is supported by the USARTx instance. + * @rmtoll CR3 HDSEL LL_USART_IsEnabledHalfDuplex + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_SPI_SLAVE Configuration functions related to SPI Slave feature + * @{ + */ +/** + * @brief Enable SPI Synchronous Slave mode + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @rmtoll CR2 SLVEN LL_USART_EnableSPISlave + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableSPISlave(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_SLVEN); +} + +/** + * @brief Disable SPI Synchronous Slave mode + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @rmtoll CR2 SLVEN LL_USART_DisableSPISlave + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableSPISlave(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_SLVEN); +} + +/** + * @brief Indicate if SPI Synchronous Slave mode is enabled + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @rmtoll CR2 SLVEN LL_USART_IsEnabledSPISlave + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlave(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR2, USART_CR2_SLVEN) == (USART_CR2_SLVEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable SPI Slave Selection using NSS input pin + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @note SPI Slave Selection depends on NSS input pin + * (The slave is selected when NSS is low and deselected when NSS is high). + * @rmtoll CR2 DIS_NSS LL_USART_EnableSPISlaveSelect + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableSPISlaveSelect(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_DIS_NSS); +} + +/** + * @brief Disable SPI Slave Selection using NSS input pin + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @note SPI Slave will be always selected and NSS input pin will be ignored. + * @rmtoll CR2 DIS_NSS LL_USART_DisableSPISlaveSelect + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableSPISlaveSelect(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_DIS_NSS); +} + +/** + * @brief Indicate if SPI Slave Selection depends on NSS input pin + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @rmtoll CR2 DIS_NSS LL_USART_IsEnabledSPISlaveSelect + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlaveSelect(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR2, USART_CR2_DIS_NSS) != (USART_CR2_DIS_NSS)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to LIN feature + * @{ + */ + +/** + * @brief Set LIN Break Detection Length + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LBDL LL_USART_SetLINBrkDetectionLen + * @param USARTx USART Instance + * @param LINBDLength This parameter can be one of the following values: + * @arg @ref LL_USART_LINBREAK_DETECT_10B + * @arg @ref LL_USART_LINBREAK_DETECT_11B + * @retval None + */ +__STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint32_t LINBDLength) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_LBDL, LINBDLength); +} + +/** + * @brief Return LIN Break Detection Length + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LBDL LL_USART_GetLINBrkDetectionLen + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_LINBREAK_DETECT_10B + * @arg @ref LL_USART_LINBREAK_DETECT_11B + */ +__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL)); +} + +/** + * @brief Enable LIN mode + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LINEN LL_USART_EnableLIN + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_LINEN); +} + +/** + * @brief Disable LIN mode + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LINEN LL_USART_DisableLIN + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_LINEN); +} + +/** + * @brief Indicate if LIN mode is enabled + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LINEN LL_USART_IsEnabledLIN + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature + * @{ + */ + +/** + * @brief Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits). + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR1 DEDT LL_USART_SetDEDeassertionTime + * @param USARTx USART Instance + * @param Time Value between Min_Data=0 and Max_Data=31 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetDEDeassertionTime(USART_TypeDef *USARTx, uint32_t Time) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos); +} + +/** + * @brief Return DEDT (Driver Enable De-Assertion Time) + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR1 DEDT LL_USART_GetDEDeassertionTime + * @param USARTx USART Instance + * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31 + */ +__STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos); +} + +/** + * @brief Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits). + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR1 DEAT LL_USART_SetDEAssertionTime + * @param USARTx USART Instance + * @param Time Value between Min_Data=0 and Max_Data=31 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetDEAssertionTime(USART_TypeDef *USARTx, uint32_t Time) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos); +} + +/** + * @brief Return DEAT (Driver Enable Assertion Time) + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR1 DEAT LL_USART_GetDEAssertionTime + * @param USARTx USART Instance + * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31 + */ +__STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos); +} + +/** + * @brief Enable Driver Enable (DE) Mode + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR3 DEM LL_USART_EnableDEMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDEMode(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_DEM); +} + +/** + * @brief Disable Driver Enable (DE) Mode + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR3 DEM LL_USART_DisableDEMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDEMode(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_DEM); +} + +/** + * @brief Indicate if Driver Enable (DE) Mode is enabled + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR3 DEM LL_USART_IsEnabledDEMode + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL); +} + +/** + * @brief Select Driver Enable Polarity + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR3 DEP LL_USART_SetDESignalPolarity + * @param USARTx USART Instance + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_USART_DE_POLARITY_HIGH + * @arg @ref LL_USART_DE_POLARITY_LOW + * @retval None + */ +__STATIC_INLINE void LL_USART_SetDESignalPolarity(USART_TypeDef *USARTx, uint32_t Polarity) +{ + MODIFY_REG(USARTx->CR3, USART_CR3_DEP, Polarity); +} + +/** + * @brief Return Driver Enable Polarity + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR3 DEP LL_USART_GetDESignalPolarity + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_DE_POLARITY_HIGH + * @arg @ref LL_USART_DE_POLARITY_LOW + */ +__STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_DEP)); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_AdvancedConfiguration Advanced Configurations services + * @{ + */ + +/** + * @brief Perform basic configuration of USART for enabling use in Asynchronous Mode (UART) + * @note In UART mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - CLKEN bit in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - IREN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * @note Other remaining configurations items related to Asynchronous Mode + * (as Baud Rate, Word length, Parity, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigAsyncMode\n + * CR2 CLKEN LL_USART_ConfigAsyncMode\n + * CR3 SCEN LL_USART_ConfigAsyncMode\n + * CR3 IREN LL_USART_ConfigAsyncMode\n + * CR3 HDSEL LL_USART_ConfigAsyncMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx) +{ + /* In Asynchronous mode, the following bits must be kept cleared: + - LINEN, CLKEN bits in the USART_CR2 register, + - SCEN, IREN and HDSEL bits in the USART_CR3 register. + */ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL)); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Synchronous Mode + * @note In Synchronous mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - IREN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * This function also sets the USART in Synchronous mode. + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function + * @note Other remaining configurations items related to Synchronous Mode + * (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigSyncMode\n + * CR2 CLKEN LL_USART_ConfigSyncMode\n + * CR3 SCEN LL_USART_ConfigSyncMode\n + * CR3 IREN LL_USART_ConfigSyncMode\n + * CR3 HDSEL LL_USART_ConfigSyncMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx) +{ + /* In Synchronous mode, the following bits must be kept cleared: + - LINEN bit in the USART_CR2 register, + - SCEN, IREN and HDSEL bits in the USART_CR3 register. + */ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL)); + /* set the UART/USART in Synchronous mode */ + SET_BIT(USARTx->CR2, USART_CR2_CLKEN); +} + +/** + * @brief Perform basic configuration of USART for enabling use in LIN Mode + * @note In LIN mode, the following bits must be kept cleared: + * - STOP and CLKEN bits in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - IREN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * This function also set the UART/USART in LIN mode. + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear STOP in CR2 using @ref LL_USART_SetStopBitsLength() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * - Set LINEN in CR2 using @ref LL_USART_EnableLIN() function + * @note Other remaining configurations items related to LIN Mode + * (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using + * dedicated functions + * @rmtoll CR2 CLKEN LL_USART_ConfigLINMode\n + * CR2 STOP LL_USART_ConfigLINMode\n + * CR2 LINEN LL_USART_ConfigLINMode\n + * CR3 IREN LL_USART_ConfigLINMode\n + * CR3 SCEN LL_USART_ConfigLINMode\n + * CR3 HDSEL LL_USART_ConfigLINMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx) +{ + /* In LIN mode, the following bits must be kept cleared: + - STOP and CLKEN bits in the USART_CR2 register, + - IREN, SCEN and HDSEL bits in the USART_CR3 register. + */ + CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL)); + /* Set the UART/USART in LIN mode */ + SET_BIT(USARTx->CR2, USART_CR2_LINEN); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Half Duplex Mode + * @note In Half Duplex mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - CLKEN bit in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - IREN bit in the USART_CR3 register, + * This function also sets the UART/USART in Half Duplex mode. + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * Half-Duplex mode is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Set HDSEL in CR3 using @ref LL_USART_EnableHalfDuplex() function + * @note Other remaining configurations items related to Half Duplex Mode + * (as Baud Rate, Word length, Parity, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigHalfDuplexMode\n + * CR2 CLKEN LL_USART_ConfigHalfDuplexMode\n + * CR3 HDSEL LL_USART_ConfigHalfDuplexMode\n + * CR3 SCEN LL_USART_ConfigHalfDuplexMode\n + * CR3 IREN LL_USART_ConfigHalfDuplexMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx) +{ + /* In Half Duplex mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN and IREN bits in the USART_CR3 register. + */ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN)); + /* set the UART/USART in Half Duplex mode */ + SET_BIT(USARTx->CR3, USART_CR3_HDSEL); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Smartcard Mode + * @note In Smartcard mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - IREN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * This function also configures Stop bits to 1.5 bits and + * sets the USART in Smartcard mode (SCEN bit). + * Clock Output is also enabled (CLKEN). + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function + * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function + * - Set SCEN in CR3 using @ref LL_USART_EnableSmartcard() function + * @note Other remaining configurations items related to Smartcard Mode + * (as Baud Rate, Word length, Parity, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigSmartcardMode\n + * CR2 STOP LL_USART_ConfigSmartcardMode\n + * CR2 CLKEN LL_USART_ConfigSmartcardMode\n + * CR3 HDSEL LL_USART_ConfigSmartcardMode\n + * CR3 SCEN LL_USART_ConfigSmartcardMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx) +{ + /* In Smartcard mode, the following bits must be kept cleared: + - LINEN bit in the USART_CR2 register, + - IREN and HDSEL bits in the USART_CR3 register. + */ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL)); + /* Configure Stop bits to 1.5 bits */ + /* Synchronous mode is activated by default */ + SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN)); + /* set the UART/USART in Smartcard mode */ + SET_BIT(USARTx->CR3, USART_CR3_SCEN); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Irda Mode + * @note In IRDA mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - STOP and CLKEN bits in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * This function also sets the UART/USART in IRDA mode (IREN bit). + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function + * - Set IREN in CR3 using @ref LL_USART_EnableIrda() function + * @note Other remaining configurations items related to Irda Mode + * (as Baud Rate, Word length, Power mode, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigIrdaMode\n + * CR2 CLKEN LL_USART_ConfigIrdaMode\n + * CR2 STOP LL_USART_ConfigIrdaMode\n + * CR3 SCEN LL_USART_ConfigIrdaMode\n + * CR3 HDSEL LL_USART_ConfigIrdaMode\n + * CR3 IREN LL_USART_ConfigIrdaMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx) +{ + /* In IRDA mode, the following bits must be kept cleared: + - LINEN, STOP and CLKEN bits in the USART_CR2 register, + - SCEN and HDSEL bits in the USART_CR3 register. + */ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL)); + /* set the UART/USART in IRDA mode */ + SET_BIT(USARTx->CR3, USART_CR3_IREN); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Multi processor Mode + * (several USARTs connected in a network, one of the USARTs can be the master, + * its TX output connected to the RX inputs of the other slaves USARTs). + * @note In MultiProcessor mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - CLKEN bit in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - IREN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * @note Other remaining configurations items related to Multi processor Mode + * (as Baud Rate, Wake Up Method, Node address, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigMultiProcessMode\n + * CR2 CLKEN LL_USART_ConfigMultiProcessMode\n + * CR3 SCEN LL_USART_ConfigMultiProcessMode\n + * CR3 HDSEL LL_USART_ConfigMultiProcessMode\n + * CR3 IREN LL_USART_ConfigMultiProcessMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx) +{ + /* In Multi Processor mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - IREN, SCEN and HDSEL bits in the USART_CR3 register. + */ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Check if the USART Parity Error Flag is set or not + * @rmtoll ISR PE LL_USART_IsActiveFlag_PE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Framing Error Flag is set or not + * @rmtoll ISR FE LL_USART_IsActiveFlag_FE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Noise error detected Flag is set or not + * @rmtoll ISR NE LL_USART_IsActiveFlag_NE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART OverRun Error Flag is set or not + * @rmtoll ISR ORE LL_USART_IsActiveFlag_ORE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART IDLE line detected Flag is set or not + * @rmtoll ISR IDLE LL_USART_IsActiveFlag_IDLE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL); +} + +#define LL_USART_IsActiveFlag_RXNE LL_USART_IsActiveFlag_RXNE_RXFNE /* Redefinition for legacy purpose */ + +/** + * @brief Check if the USART Read Data Register or USART RX FIFO Not Empty Flag is set or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll ISR RXNE_RXFNE LL_USART_IsActiveFlag_RXNE_RXFNE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE_RXFNE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Transmission Complete Flag is set or not + * @rmtoll ISR TC LL_USART_IsActiveFlag_TC + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL); +} + +#define LL_USART_IsActiveFlag_TXE LL_USART_IsActiveFlag_TXE_TXFNF /* Redefinition for legacy purpose */ + +/** + * @brief Check if the USART Transmit Data Register Empty or USART TX FIFO Not Full Flag is set or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll ISR TXE_TXFNF LL_USART_IsActiveFlag_TXE_TXFNF + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE_TXFNF(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART LIN Break Detection Flag is set or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll ISR LBDF LL_USART_IsActiveFlag_LBD + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_LBDF) == (USART_ISR_LBDF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART CTS interrupt Flag is set or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll ISR CTSIF LL_USART_IsActiveFlag_nCTS + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART CTS Flag is set or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll ISR CTS LL_USART_IsActiveFlag_CTS + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Receiver Time Out Flag is set or not + * @rmtoll ISR RTOF LL_USART_IsActiveFlag_RTO + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_RTOF) == (USART_ISR_RTOF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART End Of Block Flag is set or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll ISR EOBF LL_USART_IsActiveFlag_EOB + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the SPI Slave Underrun error flag is set or not + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @rmtoll ISR UDR LL_USART_IsActiveFlag_UDR + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_UDR(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_UDR) == (USART_ISR_UDR)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Auto-Baud Rate Error Flag is set or not + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll ISR ABRE LL_USART_IsActiveFlag_ABRE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_ABRE) == (USART_ISR_ABRE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Auto-Baud Rate Flag is set or not + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll ISR ABRF LL_USART_IsActiveFlag_ABR + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_ABRF) == (USART_ISR_ABRF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Busy Flag is set or not + * @rmtoll ISR BUSY LL_USART_IsActiveFlag_BUSY + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Character Match Flag is set or not + * @rmtoll ISR CMF LL_USART_IsActiveFlag_CM + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Send Break Flag is set or not + * @rmtoll ISR SBKF LL_USART_IsActiveFlag_SBK + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Receive Wake Up from mute mode Flag is set or not + * @rmtoll ISR RWU LL_USART_IsActiveFlag_RWU + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Transmit Enable Acknowledge Flag is set or not + * @rmtoll ISR TEACK LL_USART_IsActiveFlag_TEACK + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Receive Enable Acknowledge Flag is set or not + * @rmtoll ISR REACK LL_USART_IsActiveFlag_REACK + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART TX FIFO Empty Flag is set or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll ISR TXFE LL_USART_IsActiveFlag_TXFE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART RX FIFO Full Flag is set or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll ISR RXFF LL_USART_IsActiveFlag_RXFF + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFF(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the Smartcard Transmission Complete Before Guard Time Flag is set or not + * @rmtoll ISR TCBGT LL_USART_IsActiveFlag_TCBGT + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_TCBGT) == (USART_ISR_TCBGT)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART TX FIFO Threshold Flag is set or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll ISR TXFT LL_USART_IsActiveFlag_TXFT + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFT(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART RX FIFO Threshold Flag is set or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll ISR RXFT LL_USART_IsActiveFlag_RXFT + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFT(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL); +} + +/** + * @brief Clear Parity Error Flag + * @rmtoll ICR PECF LL_USART_ClearFlag_PE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_PECF); +} + +/** + * @brief Clear Framing Error Flag + * @rmtoll ICR FECF LL_USART_ClearFlag_FE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_FECF); +} + +/** + * @brief Clear Noise Error detected Flag + * @rmtoll ICR NECF LL_USART_ClearFlag_NE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_NECF); +} + +/** + * @brief Clear OverRun Error Flag + * @rmtoll ICR ORECF LL_USART_ClearFlag_ORE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_ORECF); +} + +/** + * @brief Clear IDLE line detected Flag + * @rmtoll ICR IDLECF LL_USART_ClearFlag_IDLE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_IDLECF); +} + +/** + * @brief Clear TX FIFO Empty Flag + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll ICR TXFECF LL_USART_ClearFlag_TXFE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_TXFE(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_TXFECF); +} + +/** + * @brief Clear Transmission Complete Flag + * @rmtoll ICR TCCF LL_USART_ClearFlag_TC + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_TCCF); +} + +/** + * @brief Clear Smartcard Transmission Complete Before Guard Time Flag + * @rmtoll ICR TCBGTCF LL_USART_ClearFlag_TCBGT + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_TCBGT(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_TCBGTCF); +} + +/** + * @brief Clear LIN Break Detection Flag + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll ICR LBDCF LL_USART_ClearFlag_LBD + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_LBDCF); +} + +/** + * @brief Clear CTS Interrupt Flag + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll ICR CTSCF LL_USART_ClearFlag_nCTS + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_CTSCF); +} + +/** + * @brief Clear Receiver Time Out Flag + * @rmtoll ICR RTOCF LL_USART_ClearFlag_RTO + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_RTO(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_RTOCF); +} + +/** + * @brief Clear End Of Block Flag + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll ICR EOBCF LL_USART_ClearFlag_EOB + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_EOB(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_EOBCF); +} + +/** + * @brief Clear SPI Slave Underrun Flag + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @rmtoll ICR UDRCF LL_USART_ClearFlag_UDR + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_UDR(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_UDRCF); +} + +/** + * @brief Clear Character Match Flag + * @rmtoll ICR CMCF LL_USART_ClearFlag_CM + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_CM(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_CMCF); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable IDLE Interrupt + * @rmtoll CR1 IDLEIE LL_USART_EnableIT_IDLE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_IDLEIE); +} + +#define LL_USART_EnableIT_RXNE LL_USART_EnableIT_RXNE_RXFNE /* Redefinition for legacy purpose */ + +/** + * @brief Enable RX Not Empty and RX FIFO Not Empty Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 RXNEIE_RXFNEIE LL_USART_EnableIT_RXNE_RXFNE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_RXNE_RXFNE(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE); +} + +/** + * @brief Enable Transmission Complete Interrupt + * @rmtoll CR1 TCIE LL_USART_EnableIT_TC + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TCIE); +} + +#define LL_USART_EnableIT_TXE LL_USART_EnableIT_TXE_TXFNF /* Redefinition for legacy purpose */ + +/** + * @brief Enable TX Empty and TX FIFO Not Full Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 TXEIE_TXFNFIE LL_USART_EnableIT_TXE_TXFNF + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_TXE_TXFNF(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE); +} + +/** + * @brief Enable Parity Error Interrupt + * @rmtoll CR1 PEIE LL_USART_EnableIT_PE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_PEIE); +} + +/** + * @brief Enable Character Match Interrupt + * @rmtoll CR1 CMIE LL_USART_EnableIT_CM + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_CM(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_CMIE); +} + +/** + * @brief Enable Receiver Timeout Interrupt + * @rmtoll CR1 RTOIE LL_USART_EnableIT_RTO + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_RTO(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RTOIE); +} + +/** + * @brief Enable End Of Block Interrupt + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR1 EOBIE LL_USART_EnableIT_EOB + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_EOBIE); +} + +/** + * @brief Enable TX FIFO Empty Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 TXFEIE LL_USART_EnableIT_TXFE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_TXFE(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXFEIE); +} + +/** + * @brief Enable RX FIFO Full Interrupt + * @rmtoll CR1 RXFFIE LL_USART_EnableIT_RXFF + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_RXFF(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXFFIE); +} + +/** + * @brief Enable LIN Break Detection Interrupt + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LBDIE LL_USART_EnableIT_LBD + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_LBDIE); +} + +/** + * @brief Enable Error Interrupt + * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing + * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register). + * 0: Interrupt is inhibited + * 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register. + * @rmtoll CR3 EIE LL_USART_EnableIT_ERROR + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_EIE); +} + +/** + * @brief Enable CTS Interrupt + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 CTSIE LL_USART_EnableIT_CTS + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_CTSIE); +} + +/** + * @brief Enable TX FIFO Threshold Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 TXFTIE LL_USART_EnableIT_TXFT + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_TXFT(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_TXFTIE); +} + +/** + * @brief Enable Smartcard Transmission Complete Before Guard Time Interrupt + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 TCBGTIE LL_USART_EnableIT_TCBGT + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_TCBGT(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_TCBGTIE); +} + +/** + * @brief Enable RX FIFO Threshold Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 RXFTIE LL_USART_EnableIT_RXFT + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_RXFT(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_RXFTIE); +} + +/** + * @brief Disable IDLE Interrupt + * @rmtoll CR1 IDLEIE LL_USART_DisableIT_IDLE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE); +} + +#define LL_USART_DisableIT_RXNE LL_USART_DisableIT_RXNE_RXFNE /* Redefinition for legacy purpose */ + +/** + * @brief Disable RX Not Empty and RX FIFO Not Empty Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 RXNEIE_RXFNEIE LL_USART_DisableIT_RXNE_RXFNE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_RXNE_RXFNE(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE); +} + +/** + * @brief Disable Transmission Complete Interrupt + * @rmtoll CR1 TCIE LL_USART_DisableIT_TC + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE); +} + +#define LL_USART_DisableIT_TXE LL_USART_DisableIT_TXE_TXFNF /* Redefinition for legacy purpose */ + +/** + * @brief Disable TX Empty and TX FIFO Not Full Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 TXEIE_TXFNFIE LL_USART_DisableIT_TXE_TXFNF + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_TXE_TXFNF(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE); +} + +/** + * @brief Disable Parity Error Interrupt + * @rmtoll CR1 PEIE LL_USART_DisableIT_PE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE); +} + +/** + * @brief Disable Character Match Interrupt + * @rmtoll CR1 CMIE LL_USART_DisableIT_CM + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_CM(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_CMIE); +} + +/** + * @brief Disable Receiver Timeout Interrupt + * @rmtoll CR1 RTOIE LL_USART_DisableIT_RTO + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_RTO(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RTOIE); +} + +/** + * @brief Disable End Of Block Interrupt + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR1 EOBIE LL_USART_DisableIT_EOB + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_EOBIE); +} + +/** + * @brief Disable TX FIFO Empty Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 TXFEIE LL_USART_DisableIT_TXFE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_TXFE(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXFEIE); +} + +/** + * @brief Disable RX FIFO Full Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 RXFFIE LL_USART_DisableIT_RXFF + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_RXFF(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXFFIE); +} + +/** + * @brief Disable LIN Break Detection Interrupt + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LBDIE LL_USART_DisableIT_LBD + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_LBDIE); +} + +/** + * @brief Disable Error Interrupt + * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing + * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register). + * 0: Interrupt is inhibited + * 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register. + * @rmtoll CR3 EIE LL_USART_DisableIT_ERROR + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_EIE); +} + +/** + * @brief Disable CTS Interrupt + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 CTSIE LL_USART_DisableIT_CTS + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE); +} + +/** + * @brief Disable TX FIFO Threshold Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 TXFTIE LL_USART_DisableIT_TXFT + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_TXFT(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_TXFTIE); +} + +/** + * @brief Disable Smartcard Transmission Complete Before Guard Time Interrupt + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 TCBGTIE LL_USART_DisableIT_TCBGT + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_TCBGT(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_TCBGTIE); +} + +/** + * @brief Disable RX FIFO Threshold Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 RXFTIE LL_USART_DisableIT_RXFT + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_RXFT(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_RXFTIE); +} + +/** + * @brief Check if the USART IDLE Interrupt source is enabled or disabled. + * @rmtoll CR1 IDLEIE LL_USART_IsEnabledIT_IDLE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL); +} + +#define LL_USART_IsEnabledIT_RXNE LL_USART_IsEnabledIT_RXNE_RXFNE /* Redefinition for legacy purpose */ + +/** + * @brief Check if the USART RX Not Empty and USART RX FIFO Not Empty Interrupt is enabled or disabled. + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 RXNEIE_RXFNEIE LL_USART_IsEnabledIT_RXNE_RXFNE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE_RXFNE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Transmission Complete Interrupt is enabled or disabled. + * @rmtoll CR1 TCIE LL_USART_IsEnabledIT_TC + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL); +} + +#define LL_USART_IsEnabledIT_TXE LL_USART_IsEnabledIT_TXE_TXFNF /* Redefinition for legacy purpose */ + +/** + * @brief Check if the USART TX Empty and USART TX FIFO Not Full Interrupt is enabled or disabled + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 TXEIE_TXFNFIE LL_USART_IsEnabledIT_TXE_TXFNF + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE_TXFNF(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Parity Error Interrupt is enabled or disabled. + * @rmtoll CR1 PEIE LL_USART_IsEnabledIT_PE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Character Match Interrupt is enabled or disabled. + * @rmtoll CR1 CMIE LL_USART_IsEnabledIT_CM + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Receiver Timeout Interrupt is enabled or disabled. + * @rmtoll CR1 RTOIE LL_USART_IsEnabledIT_RTO + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_RTOIE) == (USART_CR1_RTOIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART End Of Block Interrupt is enabled or disabled. + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR1 EOBIE LL_USART_IsEnabledIT_EOB + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART TX FIFO Empty Interrupt is enabled or disabled + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 TXFEIE LL_USART_IsEnabledIT_TXFE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART RX FIFO Full Interrupt is enabled or disabled + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 RXFFIE LL_USART_IsEnabledIT_RXFF + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFF(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART LIN Break Detection Interrupt is enabled or disabled. + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LBDIE LL_USART_IsEnabledIT_LBD + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Error Interrupt is enabled or disabled. + * @rmtoll CR3 EIE LL_USART_IsEnabledIT_ERROR + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART CTS Interrupt is enabled or disabled. + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 CTSIE LL_USART_IsEnabledIT_CTS + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if USART TX FIFO Threshold Interrupt is enabled or disabled + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 TXFTIE LL_USART_IsEnabledIT_TXFT + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFT(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the Smartcard Transmission Complete Before Guard Time Interrupt is enabled or disabled. + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 TCBGTIE LL_USART_IsEnabledIT_TCBGT + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_TCBGTIE) == (USART_CR3_TCBGTIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if USART RX FIFO Threshold Interrupt is enabled or disabled + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 RXFTIE LL_USART_IsEnabledIT_RXFT + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFT(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_DMA_Management DMA_Management + * @{ + */ + +/** + * @brief Enable DMA Mode for reception + * @rmtoll CR3 DMAR LL_USART_EnableDMAReq_RX + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAR); +} + +/** + * @brief Disable DMA Mode for reception + * @rmtoll CR3 DMAR LL_USART_DisableDMAReq_RX + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR); +} + +/** + * @brief Check if DMA Mode is enabled for reception + * @rmtoll CR3 DMAR LL_USART_IsEnabledDMAReq_RX + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL); +} + +/** + * @brief Enable DMA Mode for transmission + * @rmtoll CR3 DMAT LL_USART_EnableDMAReq_TX + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAT); +} + +/** + * @brief Disable DMA Mode for transmission + * @rmtoll CR3 DMAT LL_USART_DisableDMAReq_TX + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT); +} + +/** + * @brief Check if DMA Mode is enabled for transmission + * @rmtoll CR3 DMAT LL_USART_IsEnabledDMAReq_TX + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL); +} + +/** + * @brief Enable DMA Disabling on Reception Error + * @rmtoll CR3 DDRE LL_USART_EnableDMADeactOnRxErr + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDMADeactOnRxErr(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_DDRE); +} + +/** + * @brief Disable DMA Disabling on Reception Error + * @rmtoll CR3 DDRE LL_USART_DisableDMADeactOnRxErr + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDMADeactOnRxErr(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_DDRE); +} + +/** + * @brief Indicate if DMA Disabling on Reception Error is disabled + * @rmtoll CR3 DDRE LL_USART_IsEnabledDMADeactOnRxErr + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL); +} + +/** + * @brief Get the data register address used for DMA transfer + * @rmtoll RDR RDR LL_USART_DMA_GetRegAddr\n + * @rmtoll TDR TDR LL_USART_DMA_GetRegAddr + * @param USARTx USART Instance + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_USART_DMA_REG_DATA_TRANSMIT + * @arg @ref LL_USART_DMA_REG_DATA_RECEIVE + * @retval Address of data register + */ +__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(const USART_TypeDef *USARTx, uint32_t Direction) +{ + uint32_t data_reg_addr; + + if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT) + { + /* return address of TDR register */ + data_reg_addr = (uint32_t) &(USARTx->TDR); + } + else + { + /* return address of RDR register */ + data_reg_addr = (uint32_t) &(USARTx->RDR); + } + + return data_reg_addr; +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Data_Management Data_Management + * @{ + */ + +/** + * @brief Read Receiver Data register (Receive Data value, 8 bits) + * @rmtoll RDR RDR LL_USART_ReceiveData8 + * @param USARTx USART Instance + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint8_t LL_USART_ReceiveData8(const USART_TypeDef *USARTx) +{ + return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR) & 0xFFU); +} + +/** + * @brief Read Receiver Data register (Receive Data value, 9 bits) + * @rmtoll RDR RDR LL_USART_ReceiveData9 + * @param USARTx USART Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x1FF + */ +__STATIC_INLINE uint16_t LL_USART_ReceiveData9(const USART_TypeDef *USARTx) +{ + return (uint16_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR)); +} + +/** + * @brief Write in Transmitter Data Register (Transmit Data value, 8 bits) + * @rmtoll TDR TDR LL_USART_TransmitData8 + * @param USARTx USART Instance + * @param Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value) +{ + USARTx->TDR = Value; +} + +/** + * @brief Write in Transmitter Data Register (Transmit Data value, 9 bits) + * @rmtoll TDR TDR LL_USART_TransmitData9 + * @param USARTx USART Instance + * @param Value between Min_Data=0x00 and Max_Data=0x1FF + * @retval None + */ +__STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Value) +{ + USARTx->TDR = (uint16_t)(Value & 0x1FFUL); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Execution Execution + * @{ + */ + +/** + * @brief Request an Automatic Baud Rate measurement on next received data frame + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll RQR ABRRQ LL_USART_RequestAutoBaudRate + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_RequestAutoBaudRate(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_ABRRQ); +} + +/** + * @brief Request Break sending + * @rmtoll RQR SBKRQ LL_USART_RequestBreakSending + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_SBKRQ); +} + +/** + * @brief Put USART in mute mode and set the RWU flag + * @rmtoll RQR MMRQ LL_USART_RequestEnterMuteMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_MMRQ); +} + +/** + * @brief Request a Receive Data and FIFO flush + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @note Allows to discard the received data without reading them, and avoid an overrun + * condition. + * @rmtoll RQR RXFRQ LL_USART_RequestRxDataFlush + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_RequestRxDataFlush(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_RXFRQ); +} + +/** + * @brief Request a Transmit data and FIFO flush + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll RQR TXFRQ LL_USART_RequestTxDataFlush + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_RequestTxDataFlush(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_TXFRQ); +} + +/** + * @} + */ + +/** @defgroup USART_LL_Autonomous_Mode Configuration functions related to Autonomous mode feature + * @{ + */ + +/** + * @brief Enable Selected Trigger + * @rmtoll AUTOCR TRIGEN LL_USART_Enable_SelectedTrigger + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_Enable_SelectedTrigger(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->AUTOCR, USART_AUTOCR_TRIGEN); +} + +/** + * @brief Disable Selected Trigger + * @rmtoll AUTOCR TRIGEN LL_USART_Disable_SelectedTrigger + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_Disable_SelectedTrigger(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->AUTOCR, USART_AUTOCR_TRIGEN); +} + +/** + * @brief Indicate if Selected Trigger is disabled or enabled + * @rmtoll AUTOCR TRIGEN LL_USART_IsEnabled_SelectedTrigger + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabled_SelectedTrigger(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->AUTOCR, USART_AUTOCR_TRIGEN) == (USART_AUTOCR_TRIGEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable Autonomous Send Idle Frame feature + * @rmtoll AUTOCR IDLEDIS LL_USART_Enable_AutonomousSendIdleFrame + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_Enable_AutonomousSendIdleFrame(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->AUTOCR, USART_AUTOCR_IDLEDIS); +} + +/** + * @brief Disable Autonomous Send Idle Frame feature + * @rmtoll AUTOCR IDLEDIS LL_USART_Disable_AutonomousSendIdleFrame + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_Disable_AutonomousSendIdleFrame(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->AUTOCR, USART_AUTOCR_IDLEDIS); +} + +/** + * @brief Indicate if Autonomous send Idle Frame feature is disabled or enabled + * @rmtoll AUTOCR IDLEDIS LL_USART_IsEnabled_AutonomousSendIdleFrame + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabled_AutonomousSendIdleFrame(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->AUTOCR, USART_AUTOCR_IDLEDIS) == (USART_AUTOCR_IDLEDIS)) ? 0UL : 1UL); +} + +/** + * @brief Configure the Number of transferred data in bytes + * @rmtoll AUTOCR TDN LL_USART_SetNbTxData + * @param USARTx USART Instance + * @param Nbdata This parameter can be a value between 0 and 0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_USART_SetNbTxData(USART_TypeDef *USARTx, uint32_t Nbdata) +{ + MODIFY_REG(USARTx->AUTOCR, USART_AUTOCR_TDN, (uint16_t)Nbdata); +} + +/** + * @brief Retrieve the Number of transferred data in bytes + * @rmtoll AUTOCR TDN LL_USART_GetNbTxData + * @param USARTx USART Instance + * @retval Returned value can be a value between 0 and 0xFFFF + */ +__STATIC_INLINE uint32_t LL_USART_GetNbTxData(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->AUTOCR, USART_AUTOCR_TDN)); +} + +/** + * @brief Set the trigger polarity + * @rmtoll AUTOCR TRIGPOL LL_USART_SetTriggerPolarity + * @param USARTx USART Instance + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_USART_TRIG_POLARITY_RISING + * @arg @ref LL_USART_TRIG_POLARITY_FALLING + * @retval None + */ +__STATIC_INLINE void LL_USART_SetTriggerPolarity(USART_TypeDef *USARTx, uint32_t Polarity) +{ + MODIFY_REG(USARTx->AUTOCR, USART_AUTOCR_TRIGPOL, Polarity); +} + +/** + * @brief Get the trigger polarity + * @rmtoll AUTOCR TRIGPOL LL_USART_GetTriggerPolarity + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_TRIG_POLARITY_RISING + * @arg @ref LL_USART_TRIG_POLARITY_FALLING + */ +__STATIC_INLINE uint32_t LL_USART_GetTriggerPolarity(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->AUTOCR, USART_AUTOCR_TRIGPOL)); +} + +/** + * @brief Set the selected trigger + * @rmtoll AUTOCR TRIGSEL LL_USART_SetSelectedTrigger + * @param USARTx USART Instance + * @param Trigger This parameter can be one of the following values: + * @arg @ref LL_USART_GPDMA1_CH0_TCF_TRG + * @arg @ref LL_USART_GPDMA1_CH1_TCF_TRG + * @arg @ref LL_USART_GPDMA1_CH2_TCF_TRG + * @arg @ref LL_USART_GPDMA1_CH3_TCF_TRG + * @arg @ref LL_USART_EXTI_LINE6_TRG + * @arg @ref LL_USART_EXTI_LINE9_TRG + * @arg @ref LL_USART_LPTIM1_OUT_TRG + * @arg @ref LL_USART_LPTIM2_OUT_TRG (only available of STM32WBA52xx, STM32WBA54xx and STM32WBA55xx) + * @arg @ref LL_USART_COMP1_OUT_TRG (only available of STM32WBA54xx and STM32WBA55xx) + * @arg @ref LL_USART_COMP2_OUT_TRG (only available of STM32WBA54xx and STM32WBA55xx) + * @arg @ref LL_USART_RTC_ALRA_TRG + * @arg @ref LL_USART_RTC_WUT_TRG + * @retval None + */ +__STATIC_INLINE void LL_USART_SetSelectedTrigger(USART_TypeDef *USARTx, uint32_t Trigger) +{ + MODIFY_REG(USARTx->AUTOCR, USART_AUTOCR_TRIGSEL, (Trigger << USART_AUTOCR_TRIGSEL_Pos)); +} + +/** + * @brief Get the selected trigger + * @rmtoll AUTOCR TRIGSEL LL_USART_GetSelectedTrigger + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_GPDMA1_CH0_TCF_TRG + * @arg @ref LL_USART_GPDMA1_CH1_TCF_TRG + * @arg @ref LL_USART_GPDMA1_CH2_TCF_TRG + * @arg @ref LL_USART_GPDMA1_CH3_TCF_TRG + * @arg @ref LL_USART_EXTI_LINE6_TRG + * @arg @ref LL_USART_EXTI_LINE9_TRG + * @arg @ref LL_USART_LPTIM1_OUT_TRG + * @arg @ref LL_USART_LPTIM2_OUT_TRG (only available of STM32WBA52xx, STM32WBA54xx and STM32WBA55xx) + * @arg @ref LL_USART_COMP1_OUT_TRG (only available of STM32WBA54xx and STM32WBA55xx) + * @arg @ref LL_USART_COMP2_OUT_TRG (only available of STM32WBA54xx and STM32WBA55xx) + * @arg @ref LL_USART_RTC_ALRA_TRG + * @arg @ref LL_USART_RTC_WUT_TRG + */ +__STATIC_INLINE uint32_t LL_USART_GetSelectedTrigger(const USART_TypeDef *USARTx) +{ + return (uint32_t)((READ_BIT(USARTx->AUTOCR, USART_AUTOCR_TRIGSEL) >> USART_AUTOCR_TRIGSEL_Pos)); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup USART_LL_EF_Init Initialization and de-initialization functions + * @{ + */ +ErrorStatus LL_USART_DeInit(const USART_TypeDef *USARTx); +ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, const LL_USART_InitTypeDef *USART_InitStruct); +void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct); +ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, const LL_USART_ClockInitTypeDef *USART_ClockInitStruct); +void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct); +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* USART1 || USART2 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WBAxx_LL_USART_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_utils.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_utils.h new file mode 100644 index 0000000000..c40d3eb39d --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_utils.h @@ -0,0 +1,304 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_ll_utils.h + * @author MCD Application Team + * @brief Header file of UTILS LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LL UTILS driver contains a set of generic APIs that can be + used by user: + (+) Device electronic signature + (+) Timing functions + (+) PLL configuration functions + + @endverbatim + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32WBAxx_LL_UTILS_H +#define __STM32WBAxx_LL_UTILS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx.h" + +/** @addtogroup STM32WBAxx_LL_Driver + * @{ + */ + +/** @defgroup UTILS_LL UTILS + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants + * @{ + */ + +/* Max delay can be used in LL_mDelay */ +#define LL_MAX_DELAY 0xFFFFFFFFU + +/** + * @brief Unique device ID register base address + */ +#define UID_BASE_ADDRESS UID_BASE + +/** + * @brief Flash size data register base address + */ +#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE + +/** + * @brief Package data register base address + */ +#define PACKAGE_BASE_ADDRESS PACKAGE_BASE + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros + * @{ + */ +/** + * @} + */ +/* Exported types ------------------------------------------------------------*/ +/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures + * @{ + */ + +/** + * @brief UTILS PLL structure definition + */ +typedef struct +{ + uint32_t PLLM; /*!< Division factor for PLL VCO input clock. + This parameter can be a number between Min_Data = 1 and Max_Data = 16 + + This feature can be modified afterwards using one of these functions + @ref LL_RCC_PLL1_ConfigDomain_PLL1P(), @ref LL_RCC_PLL1_ConfigDomain_PLL1R(), @ref LL_RCC_PLL1_ConfigDomain_PLL1Q(). */ + + uint32_t PLLN; /*!< Multiplication factor for PLL VCO output clock. + This parameter must be a number between Min_Data = 4 and Max_Data = 512 + + This feature can be modified afterwards using one of these functions + @ref LL_RCC_PLL1_ConfigDomain_PLL1P(), @ref LL_RCC_PLL1_ConfigDomain_PLL1R(), @ref LL_RCC_PLL1_ConfigDomain_PLL1Q(). */ + + uint32_t PLLR; /*!< Division for the main system clock. + This parameter can be a number between Min_Data = 1 and Max_Data = 128 + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL1_ConfigDomain_PLL1R(). */ +} LL_UTILS_PLLInitTypeDef; + +/** + * @brief UTILS System, AHB and APB buses clock configuration structure definition + */ +typedef struct +{ + uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). + This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAHBPrescaler(). */ + + uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_LL_EC_APB1_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAPB1Prescaler(). */ + + uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_LL_EC_APB2_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAPB2Prescaler(). */ + + uint32_t APB7CLKDivider; /*!< The APB7 clock (PCLK7) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_LL_EC_APB7_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAPB7Prescaler(). */ + +} LL_UTILS_ClkInitTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants + * @{ + */ + +/** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE + * @{ + */ +#define LL_UTILS_PACKAGETYPE_UQFN32 0x00000000U /*!< UQFN32 package type */ +#define LL_UTILS_PACKAGETYPE_UQFN48 0x00000001U /*!< UQFN48 package type */ +#define LL_UTILS_PACKAGETYPE_BGA59 0x00000002U /*!< BGA59 package type */ +#define LL_UTILS_PACKAGETYPE_UQFN32_SMPS 0x00000003U /*!< UQFN32 with internal SMPS package type */ +#define LL_UTILS_PACKAGETYPE_UQFN48_SMPS 0x00000004U /*!< UQFN48 with internal SMPS package type */ +#define LL_UTILS_PACKAGETYPE_BGA59_SMPS 0x00000005U /*!< BGA59 with internal SMPS package type */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions + * @{ + */ + +/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE + * @{ + */ + +/** + * @brief Get Word0 of the unique device identifier (UID based on 96 bits) + * @retval UID[31:0]: X and Y coordinates on the wafer expressed in BCD format + */ +__STATIC_INLINE uint32_t LL_GetUID_Word0(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS))); +} + +/** + * @brief Get Word1 of the unique device identifier (UID based on 96 bits) + * @retval UID[63:32]: Wafer number (UID[39:32]) & LOT_NUM[23:0] (UID[63:40]) + */ +__STATIC_INLINE uint32_t LL_GetUID_Word1(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U)))); +} + +/** + * @brief Get Word2 of the unique device identifier (UID based on 96 bits) + * @retval UID[95:64]: Lot number (ASCII encoded) - LOT_NUM[55:24] + */ +__STATIC_INLINE uint32_t LL_GetUID_Word2(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U)))); +} + +/** + * @brief Get Flash memory size + * @note This bitfield indicates the size of the device Flash memory expressed in + * Kbytes. As an example, 0x040 corresponds to 64 Kbytes. + * @retval FLASH_SIZE[15:0]: Flash memory size in Kbytes + */ +__STATIC_INLINE uint32_t LL_GetFlashSize(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)) & 0xFFFFU); +} + +/** + * @brief Get Package type + * @retval Returned value can be one of the following values: + * @arg @ref LL_UTILS_PACKAGETYPE_UQFN32 + * @arg @ref LL_UTILS_PACKAGETYPE_UQFN48 + * @arg @ref LL_UTILS_PACKAGETYPE_BGA59 + * @arg @ref LL_UTILS_PACKAGETYPE_UQFN32_SMPS + * @arg @ref LL_UTILS_PACKAGETYPE_UQFN48_SMPS + * @arg @ref LL_UTILS_PACKAGETYPE_BGA59_SMPS + */ +__STATIC_INLINE uint32_t LL_GetPackageType(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x1FU); +} + +/** + * @} + */ + +/** @defgroup UTILS_LL_EF_DELAY DELAY + * @{ + */ + +/** + * @brief This function configures the Cortex-M SysTick source of the time base. + * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro) + * @note When a RTOS is used, it is recommended to avoid changing the SysTick + * configuration by calling this function, for a delay use rather osDelay RTOS service. + * @param Ticks Number of ticks + * @retval None + */ +__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks) +{ + /* Configure the SysTick to have interrupt in 1ms time base */ + SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */ +} + +void LL_Init1msTick(uint32_t HCLKFrequency); +void LL_Init1msTick_HCLK_Div8(uint32_t HCLKFrequency); +void LL_Init1msTick_LSE(void); +void LL_Init1msTick_LSI(void); +void LL_mDelay(uint32_t Delay); + +/** + * @} + */ + +/** @defgroup UTILS_EF_SYSTEM SYSTEM + * @{ + */ + +void LL_SetSystemCoreClock(uint32_t HCLKFrequency); +ErrorStatus LL_PLL1_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, + LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); +ErrorStatus LL_PLL1_ConfigSystemClock_HSE(uint32_t HSEFrequency, + LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, + LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); +ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32WBAxx_LL_UTILS_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_wwdg.h b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_wwdg.h new file mode 100644 index 0000000000..13065f1455 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Inc/stm32wbaxx_ll_wwdg.h @@ -0,0 +1,328 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_ll_wwdg.h + * @author MCD Application Team + * @brief Header file of WWDG LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_LL_WWDG_H +#define STM32WBAxx_LL_WWDG_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx.h" + +/** @addtogroup STM32WBAxx_LL_Driver + * @{ + */ + +#if defined (WWDG) + +/** @defgroup WWDG_LL WWDG + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup WWDG_LL_Exported_Constants WWDG Exported Constants + * @{ + */ + +/** @defgroup WWDG_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_WWDG_ReadReg and LL_WWDG_WriteReg functions + * @{ + */ +#define LL_WWDG_CFR_EWI WWDG_CFR_EWI +/** + * @} + */ + +/** @defgroup WWDG_LL_EC_PRESCALER PRESCALER + * @{ + */ +#define LL_WWDG_PRESCALER_1 0x00000000u /*!< WWDG counter clock = (PCLK1/4096)/1 */ +#define LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */ +#define LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */ +#define LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1) /*!< WWDG counter clock = (PCLK1/4096)/8 */ +#define LL_WWDG_PRESCALER_16 WWDG_CFR_WDGTB_2 /*!< WWDG counter clock = (PCLK1/4096)/16 */ +#define LL_WWDG_PRESCALER_32 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_0) /*!< WWDG counter clock = (PCLK1/4096)/32 */ +#define LL_WWDG_PRESCALER_64 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1) /*!< WWDG counter clock = (PCLK1/4096)/64 */ +#define LL_WWDG_PRESCALER_128 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0) /*!< WWDG counter clock = (PCLK1/4096)/128 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup WWDG_LL_Exported_Macros WWDG Exported Macros + * @{ + */ +/** @defgroup WWDG_LL_EM_WRITE_READ Common Write and read registers macros + * @{ + */ +/** + * @brief Write a value in WWDG register + * @param __INSTANCE__ WWDG Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_WWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in WWDG register + * @param __INSTANCE__ WWDG Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_WWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup WWDG_LL_Exported_Functions WWDG Exported Functions + * @{ + */ + +/** @defgroup WWDG_LL_EF_Configuration Configuration + * @{ + */ +/** + * @brief Enable Window Watchdog. The watchdog is always disabled after a reset. + * @note It is enabled by setting the WDGA bit in the WWDG_CR register, + * then it cannot be disabled again except by a reset. + * This bit is set by software and only cleared by hardware after a reset. + * When WDGA = 1, the watchdog can generate a reset. + * @rmtoll CR WDGA LL_WWDG_Enable + * @param WWDGx WWDG Instance + * @retval None + */ +__STATIC_INLINE void LL_WWDG_Enable(WWDG_TypeDef *WWDGx) +{ + SET_BIT(WWDGx->CR, WWDG_CR_WDGA); +} + +/** + * @brief Checks if Window Watchdog is enabled + * @rmtoll CR WDGA LL_WWDG_IsEnabled + * @param WWDGx WWDG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_WWDG_IsEnabled(const WWDG_TypeDef *WWDGx) +{ + return ((READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA)) ? 1UL : 0UL); +} + +/** + * @brief Set the Watchdog counter value to provided value (7-bits T[6:0]) + * @note When writing to the WWDG_CR register, always write 1 in the MSB b6 to avoid generating an immediate reset + * This counter is decremented every (4096 x 2expWDGTB) PCLK cycles + * A reset is produced when it rolls over from 0x40 to 0x3F (bit T6 becomes cleared) + * Setting the counter lower then 0x40 causes an immediate reset (if WWDG enabled) + * @rmtoll CR T LL_WWDG_SetCounter + * @param WWDGx WWDG Instance + * @param Counter 0..0x7F (7 bit counter value) + * @retval None + */ +__STATIC_INLINE void LL_WWDG_SetCounter(WWDG_TypeDef *WWDGx, uint32_t Counter) +{ + MODIFY_REG(WWDGx->CR, WWDG_CR_T, Counter); +} + +/** + * @brief Return current Watchdog Counter Value (7 bits counter value) + * @rmtoll CR T LL_WWDG_GetCounter + * @param WWDGx WWDG Instance + * @retval 7 bit Watchdog Counter value + */ +__STATIC_INLINE uint32_t LL_WWDG_GetCounter(const WWDG_TypeDef *WWDGx) +{ + return (READ_BIT(WWDGx->CR, WWDG_CR_T)); +} + +/** + * @brief Set the time base of the prescaler (WDGTB). + * @note Prescaler is used to apply ratio on PCLK clock, so that Watchdog counter + * is decremented every (4096 x 2expWDGTB) PCLK cycles + * @rmtoll CFR WDGTB LL_WWDG_SetPrescaler + * @param WWDGx WWDG Instance + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_WWDG_PRESCALER_1 + * @arg @ref LL_WWDG_PRESCALER_2 + * @arg @ref LL_WWDG_PRESCALER_4 + * @arg @ref LL_WWDG_PRESCALER_8 + * @arg @ref LL_WWDG_PRESCALER_16 + * @arg @ref LL_WWDG_PRESCALER_32 + * @arg @ref LL_WWDG_PRESCALER_64 + * @arg @ref LL_WWDG_PRESCALER_128 + * @retval None + */ +__STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescaler) +{ + MODIFY_REG(WWDGx->CFR, WWDG_CFR_WDGTB, Prescaler); +} + +/** + * @brief Return current Watchdog Prescaler Value + * @rmtoll CFR WDGTB LL_WWDG_GetPrescaler + * @param WWDGx WWDG Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_WWDG_PRESCALER_1 + * @arg @ref LL_WWDG_PRESCALER_2 + * @arg @ref LL_WWDG_PRESCALER_4 + * @arg @ref LL_WWDG_PRESCALER_8 + * @arg @ref LL_WWDG_PRESCALER_16 + * @arg @ref LL_WWDG_PRESCALER_32 + * @arg @ref LL_WWDG_PRESCALER_64 + * @arg @ref LL_WWDG_PRESCALER_128 + */ +__STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(const WWDG_TypeDef *WWDGx) +{ + return (READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB)); +} + +/** + * @brief Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]). + * @note This window value defines when write in the WWDG_CR register + * to program Watchdog counter is allowed. + * Watchdog counter value update must occur only when the counter value + * is lower than the Watchdog window register value. + * Otherwise, a MCU reset is generated if the 7-bit Watchdog counter value + * (in the control register) is refreshed before the downcounter has reached + * the watchdog window register value. + * Physically is possible to set the Window lower then 0x40 but it is not recommended. + * To generate an immediate reset, it is possible to set the Counter lower than 0x40. + * @rmtoll CFR W LL_WWDG_SetWindow + * @param WWDGx WWDG Instance + * @param Window 0x00..0x7F (7 bit Window value) + * @retval None + */ +__STATIC_INLINE void LL_WWDG_SetWindow(WWDG_TypeDef *WWDGx, uint32_t Window) +{ + MODIFY_REG(WWDGx->CFR, WWDG_CFR_W, Window); +} + +/** + * @brief Return current Watchdog Window Value (7 bits value) + * @rmtoll CFR W LL_WWDG_GetWindow + * @param WWDGx WWDG Instance + * @retval 7 bit Watchdog Window value + */ +__STATIC_INLINE uint32_t LL_WWDG_GetWindow(const WWDG_TypeDef *WWDGx) +{ + return (READ_BIT(WWDGx->CFR, WWDG_CFR_W)); +} + +/** + * @} + */ + +/** @defgroup WWDG_LL_EF_FLAG_Management FLAG_Management + * @{ + */ +/** + * @brief Indicates if the WWDG Early Wakeup Interrupt Flag is set or not. + * @note This bit is set by hardware when the counter has reached the value 0x40. + * It must be cleared by software by writing 0. + * A write of 1 has no effect. This bit is also set if the interrupt is not enabled. + * @rmtoll SR EWIF LL_WWDG_IsActiveFlag_EWKUP + * @param WWDGx WWDG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(const WWDG_TypeDef *WWDGx) +{ + return ((READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF)) ? 1UL : 0UL); +} + +/** + * @brief Clear WWDG Early Wakeup Interrupt Flag (EWIF) + * @rmtoll SR EWIF LL_WWDG_ClearFlag_EWKUP + * @param WWDGx WWDG Instance + * @retval None + */ +__STATIC_INLINE void LL_WWDG_ClearFlag_EWKUP(WWDG_TypeDef *WWDGx) +{ + WRITE_REG(WWDGx->SR, ~WWDG_SR_EWIF); +} + +/** + * @} + */ + +/** @defgroup WWDG_LL_EF_IT_Management IT_Management + * @{ + */ +/** + * @brief Enable the Early Wakeup Interrupt. + * @note When set, an interrupt occurs whenever the counter reaches value 0x40. + * This interrupt is only cleared by hardware after a reset + * @rmtoll CFR EWI LL_WWDG_EnableIT_EWKUP + * @param WWDGx WWDG Instance + * @retval None + */ +__STATIC_INLINE void LL_WWDG_EnableIT_EWKUP(WWDG_TypeDef *WWDGx) +{ + SET_BIT(WWDGx->CFR, WWDG_CFR_EWI); +} + +/** + * @brief Check if Early Wakeup Interrupt is enabled + * @rmtoll CFR EWI LL_WWDG_IsEnabledIT_EWKUP + * @param WWDGx WWDG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(const WWDG_TypeDef *WWDGx) +{ + return ((READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* WWDG */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WBAxx_LL_WWDG_H */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/LICENSE.md b/system/Drivers/STM32WBAxx_HAL_Driver/LICENSE.md new file mode 100644 index 0000000000..4a464d09d0 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/LICENSE.md @@ -0,0 +1,27 @@ +Copyright 2022 STMicroelectronics. +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this +list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright notice, +this list of conditions and the following disclaimer in the documentation and/or +other materials provided with the distribution. + +3. Neither the name of the copyright holder nor the names of its contributors +may be used to endorse or promote products derived from this software without +specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/README.md b/system/Drivers/STM32WBAxx_HAL_Driver/README.md new file mode 100644 index 0000000000..b52ced71dd --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/README.md @@ -0,0 +1,36 @@ +# STM32CubeWBA HAL Driver MCU Component + +![latest tag](https://img.shields.io/github/v/tag/STMicroelectronics/stm32wbaxx_hal_driver.svg?color=brightgreen) + +## Overview + +**STM32Cube** is a STMicroelectronics original initiative aimed at making life easier for developers by reducing effort, time and cost. + +**STM32Cube** covers the overall STM32 products portfolio. It includes a comprehensive embedded software platform delivered for each STM32 series. + * The CMSIS modules (core and device) corresponding to the ARM(tm) core implemented in this STM32 product. + * The STM32 HAL-LL drivers, an abstraction layer offering a set of APIs ensuring maximized portability across the STM32 portfolio. + * The BSP drivers of each evaluation, demonstration, or nucleo board provided for this STM32 series. + * A consistent set of middleware libraries such as WPAN, ThreadX, FileX, USBX, NetDuoX, OpenBootloader, trustedfirmware, mbed-crypto... + * A full set of software projects (basic examples, applications, and demonstrations) for each board, each project developed in three flavors using three toolchains (EWARM, MDK-ARM, and STM32CubeIDE). + +Two models of publication are proposed for the STM32Cube embedded software: + * The monolithic **MCU Package**: all STM32Cube software modules of one STM32 series are present (Drivers, Middleware, Projects, Utilities) in the repository (usual name **STM32Cubexx**, xx corresponding to the STM32 series). + * The **MCU component**: each STM32Cube software module being part of the STM32Cube MCU Package, is delivered as an individual repository, allowing the user to select and get only the required software functions. + +## Description + +This **stm32wbaxx_hal_driver** MCU component repo is one element of the STM32CubeWBA MCU embedded software package, providing the **HAL-LL Drivers** part. + +## Release note + +Details about the content of this release are available in the release note [here](https://htmlpreview.github.io/?https://github.com/STMicroelectronics/stm32wbaxx_hal_driver/blob/main/Release_Notes.html). + +## Compatibility information + +It is **crucial** that you use a consistent set of versions for the CMSIS Core - CMSIS Device - HAL, as mentioned in [this](https://htmlpreview.github.io/?https://github.com/STMicroelectronics/STM32CubeWBA/blob/main/Release_Notes.html) release note. + +The full **STM32CubeWBA** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeWBA). + +## Troubleshooting + +Please refer to the [CONTRIBUTING.md](CONTRIBUTING.md) guide. diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Release_Notes.html b/system/Drivers/STM32WBAxx_HAL_Driver/Release_Notes.html new file mode 100644 index 0000000000..b901a2fd26 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Release_Notes.html @@ -0,0 +1,373 @@ + + + + + + + Release Notes for STM32WBAxx HAL Drivers + + + + + + +
+
+
+

Release Notes for

+

STM32WBAxx HAL Drivers

+

Copyright © 2022 STMicroelectronics

+ +
+

Purpose

+

The STM32Cube HAL and LL, an STM32 abstraction layer embedded software, ensure maximized portability across STM32 portfolio.

+

The portable APIs layer provides a generic, multi instanced and simple set of APIs to interact with the upper layer (application, libraries and stacks). It is composed of native and extended APIs set. It is directly built around a generic architecture and allows the build-upon layers, like the middleware layer, to implement its functions without knowing in-depth the used STM32 device. This improves the library code reusability and guarantees an easy portability on other devices and STM32 families.

+

The Low Layer (LL) drivers are part of the STM32Cube firmware HAL that provides a basic set of optimized and one shot services. The Low layer drivers, contrary to the HAL ones are not fully portable across the STM32 families; the availability of some functions depends on the physical availability of the relative features on the product. The Low Layer (LL) drivers are designed to offer the following features:

+
    +
  • New set of inline functions for direct and atomic register access
    • +
  • One-shot operations that can be used by the HAL drivers or from application level
    • +
  • Full independence from HAL and standalone usage (without HAL drivers)
    • +
  • Full features coverage of all the supported peripherals
    • +
+
+
+

Update History

+
+ +
+

Main Changes

+

Official Release of STM32CubeWBA Firmware package supporting STM32WBA52xx and STM32WBA55xx devices

+

Contents

+

Official Release of HAL/LL Drivers for STM32WBAxx serie

+
    +
  • HAL/LL Drivers are available for all peripherals: +
      +
    • HAL: ADC, CORTEX, CRC, CRYP, DMA, EXTI, FLASH, GPIO, GTZC, HASH, HSEM, I2C, ICACHE, IRDA, IWDG, LPTIM, PKA, PWR, RAMCFG, RCC, RNG, RTC, SMARTCARD, SMBUS, SPI, TIM, TSC, UART, USART, WWDG
      • +
    • LL: ADC, CRC, DMA, EXTI, GPIO, I2C, ICACHE, LPTIM, LPUART, PKA, PWR, RCC, RNG, RTC, SPI, TIM, USART, UTILS
      • +
    • +
  • Update SysTick clock source management to handle HCLK, HCLK/8, LSI and LSE sources +
      +
    • The SysTick clock source shall be configured with HAL_SYSTICK_CLKSourceConfig()
      • +
    • New implementation allowing to not re-initialize the SysTick in RCC after HCLK change if the SysTick source is LSI or LSE
      • +
    • Add support of HAL_SYSTICK_GetCLKSourceConfig() API to return the selected SYSTICK clock source set with HAL_SYSTICK_CLKSourceConfig()
      • +
    • +
+


+

+

HAL Drivers updates

+
    +
  • HAL CORTEX driver +
      +
    • Check preemption priority and subpriority versus current priority grouping
      • +
    • Remove check of __MPU_PRESENT flag in HAL CORTEX
      • +
    • Add support of HAL_SYSTICK_GetCLKSourceConfig() API to return the selected SYSTICK clock source set with HAL_SYSTICK_CLKSourceConfig()
      • +
    • +
  • HAL DMA driver +
      +
    • Update HAL_DMA_GetConfigChannelAttributes() to return DMA attributes even when TZEN=0
      • +
    • Update HAL_DMA_IRQHandler() to remove unnecessary hardware flag check upon suspend interrupt management
      • +
    • +
  • HAL FLASH driver +
      +
    • Update HAL FLASH API to support ECC management
      • +
    • +
  • HAL GPIO driver +
      +
    • Update HAL_GPIO_Init() using CMSIS definitions
      • +
    • Update GetConfigPinAttributes() to ensure it is used on a single pin
      • +
    • +
  • HAL I2C driver +
      +
    • Update HAL_I2C_Mem_Write_IT() to initialize XferSize at 0
      • +
    • Update HAL I2C driver to disable all interrupts after end of transaction
      • +
    • Update I2C_Slave_ISR_IT(), I2C_Slave_ISR_DMA() and I2C_ITSlaveCplt() to prevent the call of HAL_I2C_ListenCpltCallback() twice
      • +
    • Update I2C_WaitOnRXNEFlagUntilTimeout() to check I2C_FLAG_AF independently from I2C_FLAG_RXNE
      • +
    • Update HAL_I2C_IsDeviceReady() function to remove unusable code
      • +
    • +
  • HAL ICACHE driver +
      +
    • Update description of HAL_ICACHE_Enable() function
      • +
    • Update HAL_ICACHE_DeInit() to set registers to their reset value
      • +
    • Update HAL_ICACHE_Invalidate() to prevent launching an invalidation if one has already been launched
      • +
    • +
  • HAL PKA driver +
      +
    • Update HAL_PKA_IRQHandler() to fix MISRA C:2012-Rule-10.3, and Rule-10.4_a warnings
      • +
    • +
  • HAL RCC driver +
      +
    • Rename RCC_SYSTICKCLKSOURCE_HSI to RCC_SYSTICKCLKSOURCE_HSI_DIV4
      • +
    • Update HAL_RCC_NMI_IRQHandler() to clear flag before callback
      • +
    • +
  • HAL SAI driver +
      +
    • Improve audio quality (avoid potential glitch)
      • +
    • +
  • HAL SMARTCARD driver +
      +
    • Fix CONSTANT_EXPRESSION_RESULT coverity warning
      • +
    • +
  • HAL SMBUS driver +
      +
    • Remove default value to solve MISRA warning
      • +
    • +
  • HAL SPI driver +
      +
    • In Full Duplex mode, calling HAL_SPI_TransmitReceive_DMA() can generate a RX HDMA busy if HDMA TX is not well initialized. To avoid this, now a DMA abort is done on RX path to reset HDMA RX to ready state.
      • +
    • Add a check before send a Tx to not exceed RxFifo capacity
      • +
    • Update IT API to enable interrupts after process unlock
      • +
    • Remove HAL Lock/UnLock mechanism inside HAL_SPI_RegisterCallback and HAL_xxx_UnRegisterCallback functions
      • +
    • +
  • HAL SYSCFG driver +
      +
    • Update assert macro in HAL_SYSCFG_GetConfigAttributes() for accurate argument filtering
      • +
    • Allow HAL_SYSCFG_GetConfigAttributes() to be available in both secure and non-secure mode
      • +
    • +
  • HAL TIM driver +
      +
    • Fix MISRA warning in TIM_CCxNChannelCmd
      • +
    • Generalize bidirectional break input(s) configuration
      • +
    • Update HAL_TIM_IRQHandler() to clear System break interrupt flag
      • +
    • Update TIM_Base_SetConfig() to clear IUF flag after a software update triggered by HAL
      • +
    • Update HAL_TIMEx_OCN_Stop_IT() and HAL_TIMEx_PWMN_Stop_IT() using TIM_CCER_CCxNE_MASK definitions
      • +
    • Improve HAL_TIMEx_ConfigBreakDeadTime() function implementation
      • +
    • Update TIM_DMAErrorCCxN() to handle CH4N support
      • +
    • +
  • HAL UART driver +
      +
    • Fix incorrect gState check in HAL_UART_RegisterRxEventCallback()/HAL_UART_UnRegisterRxEventCallback() to allow user Rx Event Callback registration when a transmit is ongoing
      • +
    • Avoid RTOF flag to be cleared by a transmit process in polling mode
      • +
    • +
+


+

+

LL Drivers updates

+
    +
  • LL GPIO driver +
      +
    • Update LL_GPIO_SetPinMode() using CMSIS definitions
      • +
    • +
  • LL I2C driver +
      +
    • Update LL_I2C_HandleTranfer() function to prevent undefined behavior of volatile usage before updating the CR2 register
      • +
    • +
  • LL RTC driver +
      +
    • Update comments about RTC shadow registers
      • +
    • +
  • LL TIM driver +
      +
    • Remove support for LL_TIM_ReArmBRK() and LL_TIM_ReArmBRK2()
      • +
    • Add new function LL_TIM_CC_IsEnabledPreload()
      • +
    • Update LL_TIM_BDTR_Init() implementation
      • +
    • Update OCxConfig() functions to configure complementary channels only when supported
      • +
    • Remove LL_TIM_TIM3_ETRSOURCE_TIM4_ETR definition
      • +
    • +
+


+

+

Supported Devices and boards

+
    +
  • STM32WBA52xx and STM32WBA55xx devices
    • +
  • NUCLEO-WBA52CG, NUCLEO-WBA55CG and STM32WBA55G-DK1 boards
    • +
+

Backward compatibility

+
    +
  • Not applicable
    • +
+

Known Limitations

+
    +
  • None
    • +
+

Dependencies

+
    +
  • None
    • +
+

Notes

+
    +
  • None
    • +
+
+
+
+ +
+

Main Changes

+

Official Release of STM32CubeWBA Firmware package supporting STM32WBA52xx devices

+

Contents

+

Official Release of HAL/LL Drivers for STM32WBAxx serie

+
    +
  • HAL/LL Drivers are available for all peripherals: +
      +
    • HAL: ADC, CORTEX, CRC, CRYP, DMA, EXTI, FLASH, GPIO, GTZC, HASH, HSEM, I2C, ICACHE, IRDA, IWDG, LPTIM, PKA, PWR, RAMCFG, RCC, RNG, RTC, SMARTCARD, SMBUS, SPI, TIM, TSC, UART, USART, WWDG
      • +
    • LL: ADC, CRC, DMA, EXTI, GPIO, I2C, ICACHE, LPTIM, LPUART, PKA, PWR, RCC, RNG, RTC, SPI, TIM, USART, UTILS
      • +
    • +
+


+

+

HAL Drivers updates

+
    +
  • HAL CORTEX driver +
      +
    • Use synchronization barriers instead of memory barriers for MPU configuration (as recommended by ARM)
      • +
    • Update MPU_ACCESS_OUTER_SHAREABLE and LL_MPU_ACCESS_OUTER_SHAREABLE definitions
      • +
    • +
  • HAL CRYP driver +
      +
    • Update Crypt/Decrypt IT processes to avoid Computation Completed IRQ fires before DINR pointer increment
      • +
    • +
  • HAL DMA driver +
      +
    • Downsize LinkRegisters internal table from 8 to 6 for memory size optimization
      • +
    • Remove 2D addressing as not supported
      • +
    • Remove RepeatBlockConfig from DMA_NodeConfTypeDef structure and internal get function as not used
      • +
    • Update Assert checking the selected request. Assert can now also check in peripheral to memory case
      • +
    • Add missing TIM3 trigger and Request/trigger when I2C1, SAI1, AES, LPTIM2 feature available
      • +
    • +
  • HAL EXTI driver +
      +
    • Fix computation of pExtiConfig->GPIOSel in HAL_EXTI_GetConfigLine()
      • +
    • +
  • HAL Generic driver +
      +
    • Allow redefinition of macro UNUSED(x)
      • +
    • Move HAL version definition to HAL generic header file (stm32XXxx_hal.h)
      • +
    • +
  • HAL I2C driver +
      +
    • Update HAL_I2C_IsDeviceReady() to support 10-bit addressing mode
      • +
    • Update HAL I2C driver to disable all interrupts after end of transaction
      • +
    • Update HAL_I2C_Init() API to clear ADD10 bit in 7-bit addressing mode
      • +
    • +
  • HAL PWR driver +
      +
    • Remove __force_stores intrinsic keyword usage
      • +
    • +
  • HAL RTC driver +
      +
    • Remove useless polling of RTC_ICSR_WUTWF flag
      • +
    • Remove all useless RTC Write Protection Disable/Enable usage
      • +
    • Rework of HAL_RTC_GET_FLAG() macro implementation to return flag bit status
      • +
    • Rework of macro implementation to avoid confusion with parameters input
      • +
    • +
  • HAL TIM driver +
      +
    • Assert check for the right channels
      • +
    • Remove multiple volatile reads or writes in interrupt handler, for better performance
      • +
    • +
  • HAL TSC driver +
      +
    • Add parameter assertion depends on Duration time restriction link to product
      • +
    • +
  • HAL UART driver +
      +
    • Update initialisation sequence for TXINV, RXINV and TXRXSWAP settings
      • +
    • +
+


+

+

LL Drivers updates

+
    +
  • LL DMA driver +
      +
    • Clarifies that Linked List Address Offset can be chosen by steps of 4 bytes within 0 to 0xFFFC range
      • +
    • Fix inversion in LL_DMA_ConfigChannelTransfer description parameter
      • +
    • +
  • LL ICACHE driver +
      +
    • Update LL_ICACHE_GetRegionBaseAddress() to return the complete address
      • +
    • +
  • LL RCC driver +
      +
    • Add LL_RCC_HSE_IsEnabledPrescaler() to check HSE prescaler status
      • +
    • +
  • LL TIM driver +
      +
    • Remove unnecessary change of MOE bitfield in LL_TIM_BDTR_Init()
      • +
    • +
+


+

+

Supported Devices and boards

+
    +
  • STM32WBA52xx devices
    • +
  • NUCLEO-WBA52CG board
    • +
+

Backward compatibility

+
    +
  • Not applicable
    • +
+

Known Limitations

+
    +
  • None
    • +
+

Dependencies

+
    +
  • None
    • +
+

Notes

+
    +
  • None
    • +
+
+
+
+ +
+

Main Changes

+

First Official Release of STM32CubeWBA Firmware package supporting STM32WBA52xx devices

+

Contents

+

First Official Release of HAL/LL Drivers for STM32WBAxx serie

+
    +
  • HAL/LL Drivers are available for all peripherals: +
      +
    • HAL: ADC, CORTEX, CRC, CRYP, DMA, EXTI, FLASH, GPIO, GTZC, HASH, HSEM, I2C, ICACHE, IRDA, IWDG, LPTIM, PKA, PWR, RAMCFG, RCC, RNG, RTC, SMARTCARD, SMBUS, SPI, TIM, TSC, UART, USART, WWDG
      • +
    • LL: ADC, CRC, DMA, EXTI, GPIO, I2C, ICACHE, LPTIM, LPUART, PKA, PWR, RCC, RNG, RTC, SPI, TIM, USART, UTILS
      • +
    • +
+


+

+

Supported Devices and boards

+
    +
  • STM32WBA52xx devices
    • +
  • NUCLEO-WBA52CG board
    • +
+

Backward compatibility

+
    +
  • Not applicable
    • +
+

Known Limitations

+
    +
  • None
    • +
+

Dependencies

+
    +
  • None
    • +
+

Notes

+
    +
  • None
    • +
+
+
+
+
+
+
+
+

For complete documentation on STM32WBAxx, visit: www.st.com/stm32wba

+

This release note uses up to date web standards and, for this reason, should not be opened with Internet Explorer but preferably with popular browsers such as Google Chrome, Mozilla Firefox, Opera or Microsoft Edge.

+
+

Info

+
+
+
+ + diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal.c new file mode 100644 index 0000000000..7f4fb9582c --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal.c @@ -0,0 +1,756 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal.c + * @author MCD Application Team + * @brief HAL module driver. + * This is the common part of the HAL initialization + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The common HAL driver contains a set of generic and common APIs that can be + used by the PPP peripheral drivers and the user to start using the HAL. + [..] + The HAL contains two APIs' categories: + (+) Common HAL APIs + (+) Services HAL APIs + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @defgroup HAL HAL + * @brief HAL module driver + * @{ + */ + +#ifdef HAL_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Exported variables --------------------------------------------------------*/ + +/** @defgroup HAL_Exported_Variables HAL Exported Variables + * @{ + */ +__IO uint32_t uwTick; +uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */ +HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup HAL_Exported_Functions HAL Exported Functions + * @{ + */ + +/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions + * @brief Initialization and de-initialization functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initializes the Flash interface the NVIC allocation and initial clock + configuration. It initializes the systick also when timeout is needed + and the backup domain when enabled. + (+) De-Initializes common part of the HAL. + (+) Configure The time base source to have 1ms time base with a dedicated + Tick interrupt priority. + (++) SysTick timer is used by default as source of time base, but user + can eventually implement his proper time base source (a general purpose + timer for example or other time source), keeping in mind that Time base + duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and + handled in milliseconds basis. + (++) Time base configuration function (HAL_InitTick ()) is called automatically + at the beginning of the program after reset by HAL_Init() or at any time + when clock is configured, by HAL_RCC_ClockConfig(). + (++) Source of time base is configured to generate interrupts at regular + time intervals. Care must be taken if HAL_Delay() is called from a + peripheral ISR process, the Tick interrupt line must have higher priority + (numerically lower) than the peripheral interrupt. Otherwise the caller + ISR process will be blocked. + (++) functions affecting time base configurations are declared as __weak + to make override possible in case of other implementations in user file. +@endverbatim + * @{ + */ + +/** + * @brief Configure the Flash prefetch, the time base source, NVIC and any required global low + * level hardware by calling the HAL_MspInit() callback function to be optionally defined + * in user file stm32wbaxx_hal_msp.c. + * + * @note HAL_Init() function is called at the beginning of program after reset and before + * the clock configuration. + * + * @note In the default implementation the System Timer (SysTick) is used as source of time base. + * The SysTick configuration is based on HSI clock, as HSI is the clock + * used after a system Reset and the NVIC configuration is set to Priority group 4. + * Once done, time base tick starts incrementing: the tick variable counter is incremented + * each 1ms in the SysTick_Handler() interrupt handler. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_Init(void) +{ + /* Configure Flash prefetch */ +#if (PREFETCH_ENABLE != 0U) + __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); +#endif /* PREFETCH_ENABLE */ + + /* Set Interrupt Group Priority */ + HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); + + /* Ensure time base clock coherency */ + SystemCoreClockUpdate(); + + /* Select HCLK as SysTick clock source */ + HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK); + + /* Initialize 1ms tick time base (default SysTick based on HSI clock after Reset) */ + if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) + { + return HAL_ERROR; + } + + /* Init the low level hardware */ + HAL_MspInit(); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief This function de-Initializes common part of the HAL and stops the systick. + * This function is optional. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DeInit(void) +{ + /* Reset of all peripherals */ + __HAL_RCC_APB1_FORCE_RESET(); + __HAL_RCC_APB1_RELEASE_RESET(); + + __HAL_RCC_APB2_FORCE_RESET(); + __HAL_RCC_APB2_RELEASE_RESET(); + + __HAL_RCC_APB7_FORCE_RESET(); + __HAL_RCC_APB7_RELEASE_RESET(); + + __HAL_RCC_AHB1_FORCE_RESET(); + __HAL_RCC_AHB1_RELEASE_RESET(); + + __HAL_RCC_AHB2_FORCE_RESET(); + __HAL_RCC_AHB2_RELEASE_RESET(); + + __HAL_RCC_AHB4_FORCE_RESET(); + __HAL_RCC_AHB4_RELEASE_RESET(); + + __HAL_RCC_AHB5_FORCE_RESET(); + __HAL_RCC_AHB5_RELEASE_RESET(); + + /* De-Init the low level hardware */ + HAL_MspDeInit(); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initializes the MSP. + * @retval None + */ +__weak void HAL_MspInit(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes the MSP. + * @retval None + */ +__weak void HAL_MspDeInit(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief This function configures the source of the time base. + * The time source is configured to have 1ms time base with a dedicated + * Tick interrupt priority. + * @note This function is called automatically at the beginning of program after + * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig(). + * @note In the default implementation, SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals. + * Care must be taken if HAL_Delay() is called from a peripheral ISR process, + * The SysTick interrupt must have higher priority (numerically lower) + * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. + * The function is declared as __weak to be overwritten in case of other + * implementation in user file. + * @param TickPriority: Tick interrupt priority. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + uint32_t ticknumber = 0U; + uint32_t systicksel; + + /* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that don't take the value zero)*/ + if ((uint32_t)uwTickFreq == 0UL) + { + return HAL_ERROR; + } + + /* Check Clock source to calculate the tickNumber */ + if(READ_BIT(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk) == SysTick_CTRL_CLKSOURCE_Msk) + { + /* HCLK selected as SysTick clock source */ + ticknumber = SystemCoreClock / (1000UL / (uint32_t)uwTickFreq); + } + else + { + systicksel = __HAL_RCC_GET_SYSTICK_SOURCE(); + switch (systicksel) + { + /* HCLK_DIV8 selected as SysTick clock source */ + case RCC_SYSTICKCLKSOURCE_HCLK_DIV8: + /* Calculate tick value */ + ticknumber = (SystemCoreClock / (8000UL / (uint32_t)uwTickFreq)); + break; + + /* LSI selected as SysTick clock source */ + case RCC_SYSTICKCLKSOURCE_LSI: + /* Calculate tick value */ + ticknumber = (LSI_VALUE / (1000UL / (uint32_t)uwTickFreq)); + break; + + /* LSE selected as SysTick clock source */ + case RCC_SYSTICKCLKSOURCE_LSE: + /* Calculate tick value */ + ticknumber = (LSE_VALUE / (1000UL / (uint32_t)uwTickFreq)); + break; + + default: + /* Nothing to do */ + break; + } + } + + /* Configure the SysTick */ + if (HAL_SYSTICK_Config(ticknumber) > 0U) + { + return HAL_ERROR; + } + + /* Configure the SysTick IRQ priority */ + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); + uwTickPrio = TickPriority; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup HAL_Group2 HAL Control functions + * @brief HAL Control functions + * +@verbatim + =============================================================================== + ##### HAL Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Provide a tick value in millisecond + (+) Provide a blocking delay in millisecond + (+) Suspend the time base source interrupt + (+) Resume the time base source interrupt + (+) Get the HAL API driver version + (+) Get the device identifier + (+) Get the device revision identifier + (+) Enable/Disable Debug module during SLEEP mode + (+) Enable/Disable Debug module during STOP mode + (+) Enable/Disable Debug module during STANDBY mode + +@endverbatim + * @{ + */ + +/** + * @brief This function is called to increment a global variable "uwTick" + * used as application time base. + * @note In the default implementation, this variable is incremented each 1ms + * in SysTick ISR. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_IncTick(void) +{ + uwTick += (uint32_t)uwTickFreq; +} + +/** + * @brief Provides a tick value in millisecond. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval tick value + */ +__weak uint32_t HAL_GetTick(void) +{ + return uwTick; +} + +/** + * @brief This function returns a tick priority. + * @retval tick priority + */ +uint32_t HAL_GetTickPrio(void) +{ + return uwTickPrio; +} + +/** + * @brief Set new tick Freq. + * @retval Status + */ +HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq) +{ + HAL_StatusTypeDef status = HAL_OK; + assert_param(IS_TICKFREQ(Freq)); + + if (uwTickFreq != Freq) + { + /* Apply the new tick Freq */ + status = HAL_InitTick(uwTickPrio); + + if (status == HAL_OK) + { + uwTickFreq = Freq; + } + } + + return status; +} + +/** + * @brief Return tick frequency. + * @retval Tick frequency. + * Value of @ref HAL_TickFreqTypeDef. + */ +HAL_TickFreqTypeDef HAL_GetTickFreq(void) +{ + return uwTickFreq; +} + +/** + * @brief This function provides minimum delay (in milliseconds) based + * on variable incremented. + * @note In the default implementation , SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals where uwTick + * is incremented. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @param Delay specifies the delay time length, in milliseconds. + * @retval None + */ +__weak void HAL_Delay(uint32_t Delay) +{ + uint32_t tickstart = HAL_GetTick(); + uint32_t wait = Delay; + + /* Add a freq to guarantee minimum wait */ + if (wait < HAL_MAX_DELAY) + { + wait += (uint32_t)(uwTickFreq); + } + + while ((HAL_GetTick() - tickstart) < wait) + { + } +} + +/** + * @brief Suspend Tick increment. + * @note In the default implementation , SysTick timer is the source of time base. It is + * used to generate interrupts at regular time intervals. Once HAL_SuspendTick() + * is called, the SysTick interrupt will be disabled and so Tick increment + * is suspended. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_SuspendTick(void) +{ + /* Disable SysTick Interrupt */ + SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk; +} + +/** + * @brief Resume Tick increment. + * @note In the default implementation , SysTick timer is the source of time base. It is + * used to generate interrupts at regular time intervals. Once HAL_ResumeTick() + * is called, the SysTick interrupt will be enabled and so Tick increment + * is resumed. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_ResumeTick(void) +{ + /* Enable SysTick Interrupt */ + SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk; +} + +/** + * @brief Returns the HAL revision + * @retval version : 0xXYZR (8bits for each decimal, R for RC) + */ +uint32_t HAL_GetHalVersion(void) +{ + return __STM32WBAxx_HAL_VERSION; +} + +/** + * @brief Returns the device revision identifier. + * @retval Device revision identifier + */ +uint32_t HAL_GetREVID(void) +{ + return ((DBGMCU->IDCODE & DBGMCU_IDCODE_REV_ID) >> 16); +} + +/** + * @brief Returns the device identifier. + * @retval Device identifier + */ +uint32_t HAL_GetDEVID(void) +{ + return (DBGMCU->IDCODE & DBGMCU_IDCODE_DEV_ID); +} + +/** + * @brief Return the first word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw0(void) +{ + return (READ_REG(*((uint32_t *)UID_BASE))); +} + +/** + * @brief Return the second word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw1(void) +{ + return (READ_REG(*((uint32_t *)(UID_BASE + 4U)))); +} + +/** + * @brief Return the third word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw2(void) +{ + return (READ_REG(*((uint32_t *)(UID_BASE + 8U)))); +} +/** + * @} + */ + + +/** @defgroup HAL_Exported_Functions_Group3 HAL Debug functions + * @brief HAL Debug functions + * +@verbatim + =============================================================================== + ##### HAL Debug functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Enable/Disable Debug module during STOP0/STOP1/STOP2 modes + (+) Enable/Disable Debug module during STANDBY mode + +@endverbatim + * @{ + */ + +/** + * @brief Enable the Debug Module during STOP0/STOP1/STOP2 modes. + * @retval None + */ +void HAL_DBGMCU_EnableDBGStopMode(void) +{ + SET_BIT(DBGMCU->SCR, DBGMCU_SCR_DBG_STOP); +} + +/** + * @brief Disable the Debug Module during STOP0/STOP1/STOP2 modes. + * @retval None + */ +void HAL_DBGMCU_DisableDBGStopMode(void) +{ + CLEAR_BIT(DBGMCU->SCR, DBGMCU_SCR_DBG_STOP); +} + +/** + * @brief Enable the Debug Module during STANDBY mode. + * @retval None + */ +void HAL_DBGMCU_EnableDBGStandbyMode(void) +{ + SET_BIT(DBGMCU->SCR, DBGMCU_SCR_DBG_STANDBY); +} + +/** + * @brief Disable the Debug Module during STANDBY mode. + * @retval None + */ +void HAL_DBGMCU_DisableDBGStandbyMode(void) +{ + CLEAR_BIT(DBGMCU->SCR, DBGMCU_SCR_DBG_STANDBY); +} + +/** + * @} + */ + +/** @defgroup HAL_Exported_Functions_Group4 HAL SYSCFG configuration functions + * @brief HAL SYSCFG configuration functions + * +@verbatim + =============================================================================== + ##### HAL SYSCFG configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Enable/Disable the I/O analog switch voltage booster + +@endverbatim + * @{ + */ + +/** + * @brief Enable the I/O analog switch voltage booster + * + * @retval None + */ +void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void) +{ + SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN); +} + +/** + * @brief Disable the I/O analog switch voltage booster + * + * @retval None + */ +void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void) +{ + CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN); +} + +/** + * @} + */ + +/** @defgroup HAL_Exported_Functions_Group5 HAL SYSCFG lock management functions + * @brief SYSCFG lock management functions. + * +@verbatim + =============================================================================== + ##### SYSCFG lock functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Lock the SYSCFG item(s). + * @note Setting lock(s) depends on privilege mode in secure/non-secure code + * Lock(s) cleared only at system reset + * @param Item Item(s) to set lock on. + * This parameter can be a combination of @ref SYSCFG_Lock_items + * @retval None + */ +void HAL_SYSCFG_Lock(uint32_t Item) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_LOCK_ITEMS(Item)); + + /* Privilege secure/non-secure locks */ + SYSCFG->CNSLCKR = (0xFFFFU & Item); /* non-secure lock item in 16 lowest bits */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + /* Privilege secure only locks */ + SYSCFG->CSLCKR = ((0xFFFF0000U & Item) >> 16U); /* Secure-only lock item in 16 highest bits */ +#endif /* __ARM_FEATURE_CMSE */ +} + +/** + * @brief Get the lock state of SYSCFG item. + * @note Getting lock(s) depends on privilege mode in secure/non-secure code + * @param pItem pointer to return locked items + * the return value can be a combination of @ref SYSCFG_Lock_items + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SYSCFG_GetLock(uint32_t *pItem) +{ + uint32_t tmp_lock; + + /* Check null pointer */ + if (pItem == NULL) + { + return HAL_ERROR; + } + + /* Get the non-secure lock state */ + tmp_lock = SYSCFG->CNSLCKR; + + /* Get the secure lock state in secure code */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + tmp_lock |= (SYSCFG->CSLCKR << 16U); +#endif /* __ARM_FEATURE_CMSE */ + + /* Return overall lock status */ + *pItem = tmp_lock; + + return HAL_OK; +} + +/** + * @} + */ + + +#if defined(SYSCFG_SECCFGR_SYSCFGSEC) +/** @defgroup HAL_Exported_Functions_Group6 HAL SYSCFG attributes management functions + * @brief SYSCFG attributes management functions. + * +@verbatim + =============================================================================== + ##### SYSCFG attributes functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Configure the SYSCFG item attribute(s). + * @note Available attributes are to secure SYSCFG items, so this function is + * only available in secure + * @param Item Item(s) to set attributes on. + * This parameter can be a one or a combination of @ref SYSCFG_Attributes_items + * @param Attributes specifies the secure/non-secure attributes. + * @retval None + */ +void HAL_SYSCFG_ConfigAttributes(uint32_t Item, uint32_t Attributes) +{ + uint32_t tmp; + + /* Check the parameters */ + assert_param(IS_SYSCFG_ITEMS_ATTRIBUTES(Item)); + assert_param(IS_SYSCFG_ATTRIBUTES(Attributes)); + + tmp = SYSCFG_S->SECCFGR; + + /* Set or reset Item */ + if ((Attributes & SYSCFG_SEC) != 0x00U) + { + tmp |= Item; + } + else + { + tmp &= ~Item; + } + + /* Set secure attributes */ + SYSCFG_S->SECCFGR = tmp; +} + +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @brief Get the attribute of a SYSCFG item. + * @note Available attributes are to secure SYSCFG items, so this function is + * only available in secure + * @param Item Single item to get secure/non-secure attribute from. + * @param pAttributes pointer to return the attribute. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SYSCFG_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes) +{ + /* Check null pointer */ + if (pAttributes == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SYSCFG_SINGLE_ITEMS_ATTRIBUTES(Item)); + + /* Get the secure attribute state */ + if ((SYSCFG->SECCFGR & Item) != 0U) + { + *pAttributes = SYSCFG_SEC; + } + else + { + *pAttributes = SYSCFG_NSEC; + } + + return HAL_OK; +} + +/** + * @} + */ + +#endif /* SYSCFG_SECCFGR_SYSCFGSEC */ + +/** + * @} + */ + +#endif /* HAL_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_adc.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_adc.c new file mode 100644 index 0000000000..233cc3ffc7 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_adc.c @@ -0,0 +1,3005 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_adc.c + * @author MCD Application Team + * @brief This file provides firmware functions to manage the following + * functionalities of the Analog to Digital Converter (ADC) + * peripheral: + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + Peripheral State functions + * Other functions (extended functions) are available in file + * "stm32wbaxx_hal_adc_ex.c". + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### ADC peripheral features ##### + ============================================================================== + [..] + (+) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution. + + (+) Interrupt generation at the end of regular conversion and in case of + analog watchdog or overrun events. + + (+) Single and continuous conversion modes. + + (+) Scan mode for conversion of several channels sequentially. + + (+) Data alignment with in-built data coherency. + + (+) Programmable sampling time (common to group of channels) + + (+) External trigger (timer or EXTI) with configurable polarity + + (+) DMA request generation for transfer of conversions data of regular group. + + (+) ADC calibration + + (+) ADC conversion of regular group. + + (+) ADC supply requirements: 1.62 V to 3.6 V. + + (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to + Vdda or to an external voltage reference). + + + ##### How to use this driver ##### + ============================================================================== + [..] + + *** Configuration of top level parameters related to ADC *** + ============================================================ + [..] + + (#) Enable the ADC interface + (++) As prerequisite, ADC clock must be configured at RCC top level. + Caution: On this series, ADC clock frequency max is 35MHz (refer + to device datasheet). + Therefore, ADC clock source from RCC and ADC clock + prescaler must be configured to remain below + this maximum frequency. + + (++) Two clock settings are mandatory: + (+++) ADC clock (core clock, also possibly conversion clock). + + (+++) ADC clock (conversions clock). + Five possible clock sources from RCC level: HCLK1, SYSCLK, SYSCLK, HSE32, HSI16, PLL1PCLK. + + (+++) Example: + Into HAL_ADC_MspInit() (recommended code location) or with + other device clock parameters configuration: + (+++) __HAL_RCC_ADC_CLK_ENABLE(); (mandatory: core clock) + + (++) ADC clock source and clock prescaler are configured at ADC level with + parameter "ClockPrescaler" using function HAL_ADC_Init(). + + (#) ADC pins configuration + (++) Enable the clock for the ADC GPIOs + using macro __HAL_RCC_GPIOx_CLK_ENABLE() + (++) Configure these ADC pins in analog mode + using function HAL_GPIO_Init() + + (#) Optionally, in case of usage of ADC with interruptions: + (++) Configure the NVIC for ADC + using function HAL_NVIC_EnableIRQ(ADCx_IRQn) + (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() + into the function of corresponding ADC interruption vector + ADCx_IRQHandler(). + + (#) Optionally, in case of usage of DMA: + (++) Configure the DMA (DMA channel, mode normal or circular, ...) + using function HAL_DMA_Init(). + (++) Configure the NVIC for DMA + using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn) + (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() + into the function of corresponding DMA interruption vector + DMAx_Channelx_IRQHandler(). + + *** Configuration of ADC, group regular, channels parameters *** + ================================================================ + [..] + + (#) Configure the ADC parameters (resolution, data alignment, ...) + and regular group parameters (conversion trigger, sequencer, ...) + using function HAL_ADC_Init(). + + (#) Configure the channels for regular group parameters (channel number, + channel rank into sequencer, ..., into regular group) + using function HAL_ADC_ConfigChannel(). + + (#) Optionally, configure the analog watchdog parameters (channels + monitored, thresholds, ...) + using function HAL_ADC_AnalogWDGConfig(). + + *** Execution of ADC conversions *** + ==================================== + [..] + + (#) Optionally, perform an automatic ADC calibration to improve the + conversion accuracy + using function HAL_ADCEx_Calibration_Start(). + + (#) ADC driver can be used among three modes: polling, interruption, + transfer by DMA. + + (++) ADC conversion by polling: + (+++) Activate the ADC peripheral and start conversions + using function HAL_ADC_Start() + (+++) Wait for ADC conversion completion + using function HAL_ADC_PollForConversion() + (+++) Retrieve conversion results + using function HAL_ADC_GetValue() + (+++) Stop conversion and disable the ADC peripheral + using function HAL_ADC_Stop() + + (++) ADC conversion by interruption: + (+++) Activate the ADC peripheral and start conversions + using function HAL_ADC_Start_IT() + (+++) Wait for ADC conversion completion by call of function + HAL_ADC_ConvCpltCallback() + (this function must be implemented in user program) + (+++) Retrieve conversion results + using function HAL_ADC_GetValue() + (+++) Stop conversion and disable the ADC peripheral + using function HAL_ADC_Stop_IT() + + (++) ADC conversion with transfer by DMA: + (+++) Activate the ADC peripheral and start conversions + using function HAL_ADC_Start_DMA() + (+++) Wait for ADC conversion completion by call of function + HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback() + (these functions must be implemented in user program) + (+++) Conversion results are automatically transferred by DMA into + destination variable address. + (+++) Stop conversion and disable the ADC peripheral + using function HAL_ADC_Stop_DMA() + + [..] + + (@) Callback functions must be implemented in user program: + (+@) HAL_ADC_ErrorCallback() + (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog) + (+@) HAL_ADC_ConvCpltCallback() + (+@) HAL_ADC_ConvHalfCpltCallback + + *** Deinitialization of ADC *** + ============================================================ + [..] + + (#) Disable the ADC interface + (++) ADC clock can be hard reset and disabled at RCC top level. + (++) Hard reset of ADC peripherals + using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET(). + (++) ADC clock disable + using the equivalent macro/functions as configuration step. + (+++) Example: + Into HAL_ADC_MspDeInit() (recommended code location) or with + other device clock parameters configuration: + (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI14; + (+++) RCC_OscInitStructure.HSI14State = RCC_HSI14_OFF; (if not used for system clock) + (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure); + + (#) ADC pins configuration + (++) Disable the clock for the ADC GPIOs + using macro __HAL_RCC_GPIOx_CLK_DISABLE() + + (#) Optionally, in case of usage of ADC with interruptions: + (++) Disable the NVIC for ADC + using function HAL_NVIC_EnableIRQ(ADCx_IRQn) + + (#) Optionally, in case of usage of DMA: + (++) Deinitialize the DMA + using function HAL_DMA_Init(). + (++) Disable the NVIC for DMA + using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn) + + [..] + + *** Callback registration *** + ============================================= + [..] + + The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1, + allows the user to configure dynamically the driver callbacks. + Use Functions HAL_ADC_RegisterCallback() + to register an interrupt callback. + [..] + + Function HAL_ADC_RegisterCallback() allows to register following callbacks: + (+) ConvCpltCallback : ADC conversion complete callback + (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback + (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback + (+) ErrorCallback : ADC error callback + (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback + (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback + (+) EndOfSamplingCallback : ADC end of sampling callback + (+) MspInitCallback : ADC Msp Init callback + (+) MspDeInitCallback : ADC Msp DeInit callback + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + [..] + + Use function HAL_ADC_UnRegisterCallback to reset a callback to the default + weak function. + [..] + + HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) ConvCpltCallback : ADC conversion complete callback + (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback + (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback + (+) ErrorCallback : ADC error callback + (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback + (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback + (+) EndOfSamplingCallback : ADC end of sampling callback + (+) MspInitCallback : ADC Msp Init callback + (+) MspDeInitCallback : ADC Msp DeInit callback + [..] + + By default, after the HAL_ADC_Init() and when the state is HAL_ADC_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples HAL_ADC_ConvCpltCallback(), HAL_ADC_ErrorCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak functions in the HAL_ADC_Init()/ HAL_ADC_DeInit() only when + these callbacks are null (not registered beforehand). + [..] + + If MspInit or MspDeInit are not null, the HAL_ADC_Init()/ HAL_ADC_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + [..] + + Callbacks can be registered/unregistered in HAL_ADC_STATE_READY state only. + Exception done MspInit/MspDeInit functions that can be registered/unregistered + in HAL_ADC_STATE_READY or HAL_ADC_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + [..] + + Then, the user first registers the MspInit/MspDeInit user callbacks + using HAL_ADC_RegisterCallback() before calling HAL_ADC_DeInit() + or HAL_ADC_Init() function. + [..] + + When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @defgroup ADC ADC + * @brief ADC HAL module driver + * @{ + */ + +#ifdef HAL_ADC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/** @defgroup ADC_Private_Constants ADC Private Constants + * @{ + */ + +/* Fixed timeout values for ADC calibration, enable settling time, disable */ +/* settling time. */ +/* Values defined to be higher than worst cases: low clock frequency, */ +/* maximum prescaler. */ +/* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */ +/* prescaler 4, sampling time 7.5 ADC clock cycles, resolution 12 bits. */ +/* Unit: ms */ +#define ADC_ENABLE_TIMEOUT (2UL) +#define ADC_DISABLE_TIMEOUT (2UL) +#define ADC_STOP_CONVERSION_TIMEOUT (2UL) +#define ADC_LDO_RDY_TIMEOUT (1UL) /* Note: Timeout value independent of ADC clock frequency, for more + accurate value refer to LL_ADC_DELAY_INTERNAL_REGUL_STAB_US */ + +/* Register CHSELR bits corresponding to ranks 2 to 8 . */ +#define ADC_CHSELR_SQ2_TO_SQ8 (ADC_CHSELR_SQ2 | ADC_CHSELR_SQ3 | ADC_CHSELR_SQ4 | \ + ADC_CHSELR_SQ5 | ADC_CHSELR_SQ6 | ADC_CHSELR_SQ7 | ADC_CHSELR_SQ8) + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup ADC_Private_Functions ADC Private Functions + * @{ + */ +static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma); +static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); +static void ADC_DMAError(DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup ADC_Exported_Functions ADC Exported Functions + * @{ + */ + +/** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief ADC Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the ADC. + (+) De-initialize the ADC. +@endverbatim + * @{ + */ + +/** + * @brief Initialize the ADC peripheral and regular group according to + * parameters specified in structure "ADC_InitTypeDef". + * @note As prerequisite, ADC clock must be configured at RCC top level + * (refer to description of RCC configuration for ADC + * in header of this file). + * @note Possibility to update parameters on the fly: + * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when + * coming from ADC state reset. Following calls to this function can + * be used to reconfigure some parameters of ADC_InitTypeDef + * structure on the fly, without modifying MSP configuration. If ADC + * MSP has to be modified again, HAL_ADC_DeInit() must be called + * before HAL_ADC_Init(). + * The setting of these parameters is conditioned to ADC state. + * For parameters constraints, see comments of structure + * "ADC_InitTypeDef". + * @note This function configures the ADC within 2 scopes: scope of entire + * ADC and scope of regular group. For parameters details, see comments + * of structure "ADC_InitTypeDef". + * @param hadc ADC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) +{ + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + uint32_t tmp_cfgr1 = 0UL; + uint32_t tmp_cfgr2 = 0UL; + uint32_t tmp_adc_reg_is_conversion_on_going; + uint32_t tickstart; + + /* Check ADC handle */ + if (hadc == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler)); + assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution)); + assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); + assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); + assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); + assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests)); + assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); + assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoPowerOff)); + assert_param(IS_ADC_AUTONOMOUS_DPD(hadc->Init.LowPowerAutonomousDPD)); + assert_param(IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon1)); + assert_param(IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon2)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode)); + if (hadc->Init.OversamplingMode == ENABLE) + { + assert_param(IS_ADC_OVERSAMPLING_RATIO(hadc->Init.Oversampling.Ratio)); + assert_param(IS_ADC_RIGHT_BIT_SHIFT(hadc->Init.Oversampling.RightBitShift)); + assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(hadc->Init.Oversampling.TriggeredMode)); + } + assert_param(IS_ADC_TRIGGER_FREQ(hadc->Init.TriggerFrequencyMode)); + + if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) + { + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode)); + + if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE) + { + assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion)); + } + } + + /* ADC group regular discontinuous mode can be enabled only if */ + /* continuous mode is disabled. */ + assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE))); + + /* Actions performed only if ADC is coming from state reset: */ + /* - Initialization of ADC MSP */ + if (hadc->State == HAL_ADC_STATE_RESET) + { +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + /* Init the ADC Callback settings */ + hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; /* Legacy weak callback */ + hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; /* Legacy weak callback */ + hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; /* Legacy weak callback */ + hadc->ErrorCallback = HAL_ADC_ErrorCallback; /* Legacy weak callback */ + hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback; /* Legacy weak callback */ + hadc->LevelOutOfWindow3Callback = HAL_ADCEx_LevelOutOfWindow3Callback; /* Legacy weak callback */ + hadc->EndOfSamplingCallback = HAL_ADCEx_EndOfSamplingCallback; /* Legacy weak callback */ + + if (hadc->MspInitCallback == NULL) + { + hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware */ + hadc->MspInitCallback(hadc); +#else + /* Init the low level hardware */ + HAL_ADC_MspInit(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + + /* Set ADC error code to none */ + ADC_CLEAR_ERRORCODE(hadc); + + /* Initialize Lock */ + hadc->Lock = HAL_UNLOCKED; + } + + if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) + { + /* Clear flag ADC internal voltage regulator ready */ + LL_ADC_ClearFlag_LDORDY(hadc->Instance); + + /* Enable ADC internal voltage regulator */ + LL_ADC_EnableInternalRegulator(hadc->Instance); + + /* Get tick count */ + tickstart = HAL_GetTick(); + + /* Delay for ADC stabilization time */ + while (LL_ADC_IsActiveFlag_LDORDY(hadc->Instance) == 0UL) + { + if ((HAL_GetTick() - tickstart) > ADC_LDO_RDY_TIMEOUT) + { + /* New check to avoid false timeout detection in case of preemption */ + if (LL_ADC_IsActiveFlag_LDORDY(hadc->Instance) == 0UL) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + + return HAL_ERROR; + } + } + } + } + + /* Verification that ADC voltage regulator is correctly enabled, whether */ + /* or not ADC is coming from state reset (if any potential problem of */ + /* clocking, voltage regulator would not be enabled). */ + if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + + tmp_hal_status = HAL_ERROR; + } + + /* Configuration of ADC parameters if previous preliminary actions are */ + /* correctly completed and if there is no conversion on going on regular */ + /* group (ADC may already be enabled at this point if HAL_ADC_Init() is */ + /* called to update a parameter on the fly). */ + tmp_adc_reg_is_conversion_on_going = LL_ADC_REG_IsConversionOngoing(hadc->Instance); + + if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) + && (tmp_adc_reg_is_conversion_on_going == 0UL) + ) + { + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY, + HAL_ADC_STATE_BUSY_INTERNAL); + + /* Configuration of common ADC parameters */ + + /* Parameters update conditioned to ADC state: */ + /* Parameters that can be updated only when ADC is disabled: */ + /* - Internal voltage regulator (no parameter in HAL ADC init structure) */ + /* - Clock configuration */ + /* - ADC resolution */ + /* - Oversampling */ + /* - Trigger frequency mode */ + /* Note: If low power mode AutoPowerOff is enabled, ADC enable */ + /* and disable phases are performed automatically by hardware */ + /* (in this case, flag ADC_FLAG_RDY is not set). */ + if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) + { + /* Some parameters of this register are not reset, since they are set */ + /* by other functions and must be kept in case of usage of this */ + /* function on the fly (update of a parameter of ADC_InitTypeDef */ + /* without needing to reconfigure all other ADC groups/channels */ + /* parameters): */ + /* - internal measurement paths (VrefInt, ...) */ + /* (set into HAL_ADC_ConfigChannel() ) */ + + /* Configuration of ADC resolution */ + MODIFY_REG(hadc->Instance->CFGR1, + ADC_CFGR1_RES, + hadc->Init.Resolution); + + tmp_cfgr2 |= (hadc->Init.TriggerFrequencyMode); + + if (hadc->Init.OversamplingMode == ENABLE) + { + tmp_cfgr2 |= (ADC_CFGR2_OVSE | + hadc->Init.Oversampling.Ratio | + hadc->Init.Oversampling.RightBitShift | + hadc->Init.Oversampling.TriggeredMode + ); + } + + MODIFY_REG(hadc->Instance->CFGR2, + ADC_CFGR2_LFTRIG | + ADC_CFGR2_OVSE | + ADC_CFGR2_OVSR | + ADC_CFGR2_OVSS | + ADC_CFGR2_TOVS, + tmp_cfgr2); + + MODIFY_REG(ADC4_COMMON->CCR, + ADC_CCR_PRESC, + hadc->Init.ClockPrescaler & ADC_CCR_PRESC); + } + + /* Configuration of ADC: */ + /* - discontinuous mode */ + /* - LowPowerAutoWait mode */ + /* - LowPowerAutoPowerOff mode */ + /* - continuous conversion mode */ + /* - overrun */ + /* - external trigger to start conversion */ + /* - external trigger polarity */ + /* - data alignment */ + /* - resolution */ + /* - scan direction */ + /* - DMA continuous request */ + tmp_cfgr1 |= (ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | + ADC_CFGR1_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | + ADC_CFGR1_OVERRUN(hadc->Init.Overrun) | + hadc->Init.DataAlign | + ADC_SCAN_SEQ_MODE(hadc->Init.ScanConvMode) | + ADC_CFGR1_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests)); + + /* Update setting of discontinuous mode only if continuous mode is disabled */ + if (hadc->Init.DiscontinuousConvMode == ENABLE) + { + if (hadc->Init.ContinuousConvMode == DISABLE) + { + /* Enable the selected ADC group regular discontinuous mode */ + tmp_cfgr1 |= ADC_CFGR1_DISCEN; + } + else + { + /* ADC regular group discontinuous was intended to be enabled, */ + /* but ADC regular group modes continuous and sequencer discontinuous */ + /* cannot be enabled simultaneously. */ + + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + } + } + + /* Enable external trigger if trigger selection is different of software */ + /* start. */ + /* Note: This configuration keeps the hardware feature of parameter */ + /* ExternalTrigConvEdge "trigger edge none" equivalent to */ + /* software start. */ + if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) + { + tmp_cfgr1 |= ((hadc->Init.ExternalTrigConv & ADC_CFGR1_EXTSEL) | + hadc->Init.ExternalTrigConvEdge); + } + + /* Update ADC configuration register with previous settings */ + MODIFY_REG(hadc->Instance->CFGR1, + ADC_CFGR1_DISCEN | + ADC_CFGR1_CHSELRMOD | + ADC_CFGR1_WAIT | + ADC_CFGR1_CONT | + ADC_CFGR1_OVRMOD | + ADC_CFGR1_EXTSEL | + ADC_CFGR1_EXTEN | + ADC_CFGR1_ALIGN | + ADC_CFGR1_SCANDIR | + ADC_CFGR1_DMACFG, + tmp_cfgr1); + + MODIFY_REG(hadc->Instance->CFGR2, + ADC_CFGR2_LFTRIG | + ADC_CFGR2_OVSE | + ADC_CFGR2_OVSR | + ADC_CFGR2_OVSS | + ADC_CFGR2_TOVS, + tmp_cfgr2); + + /* Low power mode configuration */ + MODIFY_REG(hadc->Instance->PWRR, + ADC_PWRR_AUTOFF | + ADC_PWRR_DPD, + ((uint32_t) hadc->Init.LowPowerAutoPowerOff) | + hadc->Init.LowPowerAutonomousDPD); + + /* Channel sampling time configuration */ + LL_ADC_SetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_1, hadc->Init.SamplingTimeCommon1); + LL_ADC_SetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_2, hadc->Init.SamplingTimeCommon2); + + /* Configuration of regular group sequencer: */ + /* - if scan mode is disabled, regular channels sequence length is set to */ + /* 0x00: 1 channel converted (channel on regular rank 1) */ + /* Parameter "NbrOfConversion" is discarded. */ + /* Note: Scan mode is not present by hardware on this device, but */ + /* emulated by software for alignment over all STM32 devices. */ + /* - if scan mode is enabled, regular channels sequence length is set to */ + /* parameter "NbrOfConversion". */ + /* Channels must be configured into each rank using function */ + /* "HAL_ADC_ConfigChannel()". */ + if (hadc->Init.ScanConvMode == ADC_SCAN_DISABLE) + { + /* Set sequencer scan length by clearing ranks above rank 1 */ + /* and do not modify rank 1 value. */ + SET_BIT(hadc->Instance->CHSELR, + ADC_CHSELR_SQ2_TO_SQ8); + } + else if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE) + { + /* Set ADC group regular sequencer: */ + /* - Set ADC group regular sequencer to value memorized */ + /* in HAL ADC handle */ + /* Note: This value maybe be initialized at a unknown value, */ + /* therefore after the first call of "HAL_ADC_Init()", */ + /* each rank corresponding to parameter "NbrOfConversion" */ + /* must be set using "HAL_ADC_ConfigChannel()". */ + /* - Set sequencer scan length by clearing ranks above maximum rank */ + /* and do not modify other ranks value. */ + MODIFY_REG(hadc->Instance->CHSELR, + ADC_CHSELR_SQ_ALL, + (ADC_CHSELR_SQ2_TO_SQ8 << (((hadc->Init.NbrOfConversion - 1UL) * ADC_REGULAR_RANK_2) & 0x1FUL)) + | (hadc->ADCGroupRegularSequencerRanks) + ); + } + else + { + /* Nothing to do */ + } + + /* Check back that ADC registers have effectively been configured to */ + /* ensure of no potential problem of ADC core peripheral clocking. */ + /* Check through register CFGR1 (excluding analog watchdog configuration: */ + /* set into separate dedicated function, and bits of ADC resolution set */ + /* out of temporary variable 'tmp_cfgr1'). */ + if ((hadc->Instance->CFGR1 & ~(ADC_CFGR1_AWD1CH | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL | ADC_CFGR1_RES)) + == tmp_cfgr1) + { + /* Set ADC error code to none */ + ADC_CLEAR_ERRORCODE(hadc); + + /* Set the ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_BUSY_INTERNAL, + HAL_ADC_STATE_READY); + } + else + { + /* Update ADC state machine to error */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_BUSY_INTERNAL, + HAL_ADC_STATE_ERROR_INTERNAL); + + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + + tmp_hal_status = HAL_ERROR; + } + + } + else + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + + tmp_hal_status = HAL_ERROR; + } + + return tmp_hal_status; +} + +/** + * @brief Deinitialize the ADC peripheral registers to their default reset + * values, with deinitialization of the ADC MSP. + * @note For devices with several ADCs: reset of ADC common registers is done + * only if all ADCs sharing the same common group are disabled. + * (function "HAL_ADC_MspDeInit()" is also called under the same conditions: + * all ADC instances use the same core clock at RCC level, disabling + * the core clock reset all ADC instances). + * If this is not the case, reset of these common parameters reset is + * bypassed without error reporting: it can be the intended behavior in + * case of reset of a single ADC while the other ADCs sharing the same + * common group is still running. + * @note By default, HAL_ADC_DeInit() set ADC in mode deep power-down: + * this saves more power by reducing leakage currents + * and is particularly interesting before entering MCU low-power modes. + * @param hadc ADC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc) +{ + HAL_StatusTypeDef tmp_hal_status; + + /* Check ADC handle */ + if (hadc == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL); + + /* Stop potential conversion on going, on regular group */ + tmp_hal_status = ADC_ConversionStop(hadc); + + /* Disable ADC peripheral if conversions are effectively stopped */ + if (tmp_hal_status == HAL_OK) + { + /* Disable the ADC peripheral */ + tmp_hal_status = ADC_Disable(hadc); + + /* Check if ADC is effectively disabled */ + if (tmp_hal_status == HAL_OK) + { + /* Change ADC state */ + hadc->State = HAL_ADC_STATE_READY; + } + + /* Disable ADC internal voltage regulator */ + LL_ADC_DisableInternalRegulator(hadc->Instance); + } + + /* Note: HAL ADC deInit is done independently of ADC conversion stop */ + /* and disable return status. In case of status fail, attempt to */ + /* perform deinitialization anyway and it is up user code in */ + /* in HAL_ADC_MspDeInit() to reset the ADC peripheral using */ + /* system RCC hard reset. */ + + /* ========== Reset ADC registers ========== */ + /* Reset register IER */ + __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD3 | ADC_IT_AWD2 | + ADC_IT_AWD1 | ADC_IT_OVR | + ADC_IT_EOS | ADC_IT_EOC | + ADC_IT_EOSMP | ADC_IT_RDY)); + + /* Reset register ISR */ + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD3 | ADC_FLAG_AWD2 | + ADC_FLAG_AWD1 | ADC_FLAG_OVR | + ADC_FLAG_EOS | ADC_FLAG_EOC | + ADC_FLAG_EOSMP | ADC_FLAG_RDY)); + + /* Reset register CR */ + /* Bits ADC_CR_ADCAL, ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode */ + /* "read-set": no direct reset applicable. */ + + /* Reset register CFGR1 */ + hadc->Instance->CFGR1 &= ~(ADC_CFGR1_AWD1CH | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL | ADC_CFGR1_DISCEN | + ADC_CFGR1_CHSELRMOD | ADC_CFGR1_WAIT | ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD | + ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL | ADC_CFGR1_ALIGN | ADC_CFGR1_RES | + ADC_CFGR1_SCANDIR | ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN); + + /* Reset register SMPR */ + hadc->Instance->SMPR &= ~ADC_SMPR_SMP1; + + /* Reset registers AWDxTR */ + hadc->Instance->AWD1TR &= ~(ADC_AWD1TR_HT1 | ADC_AWD1TR_LT1); + hadc->Instance->AWD2TR &= ~(ADC_AWD2TR_HT2 | ADC_AWD2TR_LT2); + hadc->Instance->AWD3TR &= ~(ADC_AWD3TR_HT3 | ADC_AWD3TR_LT3); + + /* Reset register CHSELR */ + hadc->Instance->CHSELR &= ~(ADC_CHSELR_SQ_ALL); + + /* Reset register DR */ + /* bits in access mode read only, no direct reset applicable */ + + /* Reset register PWRR */ + /* Note: Bit of deep power down mode already updated previously */ + hadc->Instance->PWRR &= ~(ADC_PWRR_AUTOFF); + + /* Reset register CCR */ + ADC4_COMMON->CCR &= ~(ADC_CCR_TSEN | ADC_CCR_VREFEN | ADC_CCR_PRESC); + + /* ========== Hard reset ADC peripheral ========== */ + /* Performs a global reset of the entire ADC peripheral: ADC state is */ + /* forced to a similar state after device power-on. */ + /* Note: A possible implementation is to add RCC bus reset of ADC */ + /* (for example, using macro */ + /* __HAL_RCC_ADC..._FORCE_RESET()/..._RELEASE_RESET()/..._CLK_DISABLE()) */ + /* in function "void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc)": */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + if (hadc->MspDeInitCallback == NULL) + { + hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware */ + hadc->MspDeInitCallback(hadc); +#else + /* DeInit the low level hardware */ + HAL_ADC_MspDeInit(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + + /* Reset HAL ADC handle variable */ + hadc->ADCGroupRegularSequencerRanks = 0x00000000UL; + + /* Set ADC error code to none */ + ADC_CLEAR_ERRORCODE(hadc); + + /* Set ADC state */ + hadc->State = HAL_ADC_STATE_RESET; + + __HAL_UNLOCK(hadc); + + return tmp_hal_status; +} + +/** + * @brief Initialize the ADC MSP. + * @param hadc ADC handle + * @retval None + */ +__weak void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADC_MspInit must be implemented in the user file. + */ +} + +/** + * @brief DeInitialize the ADC MSP. + * @param hadc ADC handle + * @note All ADC instances use the same core clock at RCC level, disabling + * the core clock reset all ADC instances). + * @retval None + */ +__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADC_MspDeInit must be implemented in the user file. + */ +} + +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User ADC Callback + * To be used instead of the weak predefined callback + * @param hadc Pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID + * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID + * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID + * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID + * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID ADC analog watchdog 2 callback ID + * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID ADC analog watchdog 3 callback ID + * @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID ADC end of sampling callback ID + * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID + * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID + * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, + pADC_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if ((hadc->State & HAL_ADC_STATE_READY) != 0UL) + { + switch (CallbackID) + { + case HAL_ADC_CONVERSION_COMPLETE_CB_ID : + hadc->ConvCpltCallback = pCallback; + break; + + case HAL_ADC_CONVERSION_HALF_CB_ID : + hadc->ConvHalfCpltCallback = pCallback; + break; + + case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID : + hadc->LevelOutOfWindowCallback = pCallback; + break; + + case HAL_ADC_ERROR_CB_ID : + hadc->ErrorCallback = pCallback; + break; + + case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID : + hadc->LevelOutOfWindow2Callback = pCallback; + break; + + case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID : + hadc->LevelOutOfWindow3Callback = pCallback; + break; + + case HAL_ADC_END_OF_SAMPLING_CB_ID : + hadc->EndOfSamplingCallback = pCallback; + break; + + case HAL_ADC_MSPINIT_CB_ID : + hadc->MspInitCallback = pCallback; + break; + + case HAL_ADC_MSPDEINIT_CB_ID : + hadc->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_ADC_STATE_RESET == hadc->State) + { + switch (CallbackID) + { + case HAL_ADC_MSPINIT_CB_ID : + hadc->MspInitCallback = pCallback; + break; + + case HAL_ADC_MSPDEINIT_CB_ID : + hadc->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister a ADC Callback + * ADC callback is redirected to the weak predefined callback + * @param hadc Pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID + * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID + * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID + * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID + * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID ADC analog watchdog 2 callback ID + * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID ADC analog watchdog 3 callback ID + * @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID ADC end of sampling callback ID + * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID + * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID + * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if ((hadc->State & HAL_ADC_STATE_READY) != 0UL) + { + switch (CallbackID) + { + case HAL_ADC_CONVERSION_COMPLETE_CB_ID : + hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; + break; + + case HAL_ADC_CONVERSION_HALF_CB_ID : + hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; + break; + + case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID : + hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; + break; + + case HAL_ADC_ERROR_CB_ID : + hadc->ErrorCallback = HAL_ADC_ErrorCallback; + break; + + case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID : + hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback; + break; + + case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID : + hadc->LevelOutOfWindow3Callback = HAL_ADCEx_LevelOutOfWindow3Callback; + break; + + case HAL_ADC_END_OF_SAMPLING_CB_ID : + hadc->EndOfSamplingCallback = HAL_ADCEx_EndOfSamplingCallback; + break; + + case HAL_ADC_MSPINIT_CB_ID : + hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_ADC_MSPDEINIT_CB_ID : + hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_ADC_STATE_RESET == hadc->State) + { + switch (CallbackID) + { + case HAL_ADC_MSPINIT_CB_ID : + hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_ADC_MSPDEINIT_CB_ID : + hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup ADC_Exported_Functions_Group2 ADC Input and Output operation functions + * @brief ADC IO operation functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Start conversion of regular group. + (+) Stop conversion of regular group. + (+) Poll for conversion complete on regular group. + (+) Poll for conversion event. + (+) Get result of regular channel conversion. + (+) Start conversion of regular group and enable interruptions. + (+) Stop conversion of regular group and disable interruptions. + (+) Handle ADC interrupt request + (+) Start conversion of regular group and enable DMA transfer. + (+) Stop conversion of regular group and disable ADC DMA transfer. +@endverbatim + * @{ + */ + +/** + * @brief Enable ADC, start conversion of regular group. + * @note Interruptions enabled in this function: None. + * @param hadc ADC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc) +{ + HAL_StatusTypeDef tmp_hal_status; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Perform ADC enable and conversion start if no conversion is on going */ + if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) + { + __HAL_LOCK(hadc); + + /* Enable the ADC peripheral */ + tmp_hal_status = ADC_Enable(hadc); + + /* Start conversion if ADC is effectively enabled */ + if (tmp_hal_status == HAL_OK) + { + /* Set ADC state */ + /* - Clear state bitfield related to regular group conversion results */ + /* - Set state bitfield related to regular operation */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, + HAL_ADC_STATE_REG_BUSY); + + /* Set ADC error code */ + /* Reset all ADC error code fields */ + ADC_CLEAR_ERRORCODE(hadc); + + /* Clear ADC group regular conversion flag and overrun flag */ + /* (To ensure of no unknown state from potential previous ADC operations) */ + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); + + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); + + /* Enable conversion of regular group. */ + /* If software start has been selected, conversion starts immediately. */ + /* If external trigger has been selected, conversion will start at next */ + /* trigger event. */ + /* Start ADC group regular conversion */ + LL_ADC_REG_StartConversion(hadc->Instance); + } + else + { + __HAL_UNLOCK(hadc); + } + } + else + { + tmp_hal_status = HAL_BUSY; + } + + return tmp_hal_status; +} + +/** + * @brief Stop ADC conversion of regular group (and injected channels in + * case of auto_injection mode), disable ADC peripheral. + * @note: ADC peripheral disable is forcing stop of potential + * conversion on injected group. If injected group is under use, it + * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. + * @param hadc ADC handle + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc) +{ + HAL_StatusTypeDef tmp_hal_status; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + __HAL_LOCK(hadc); + + /* 1. Stop potential conversion on going, on ADC group regular */ + tmp_hal_status = ADC_ConversionStop(hadc); + + /* Disable ADC peripheral if conversions are effectively stopped */ + if (tmp_hal_status == HAL_OK) + { + /* 2. Disable the ADC peripheral */ + tmp_hal_status = ADC_Disable(hadc); + + /* Check if ADC is effectively disabled */ + if (tmp_hal_status == HAL_OK) + { + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY, + HAL_ADC_STATE_READY); + } + } + + __HAL_UNLOCK(hadc); + + return tmp_hal_status; +} + +/** + * @brief Wait for regular group conversion to be completed. + * @note ADC conversion flags EOS (end of sequence) and EOC (end of + * conversion) are cleared by this function, with an exception: + * if low power feature "LowPowerAutoWait" is enabled, flags are + * not cleared to not interfere with this feature until data register + * is read using function HAL_ADC_GetValue(). + * @note This function cannot be used in a particular setup: ADC configured + * in DMA mode and polling for end of each conversion (ADC init + * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV). + * In this case, DMA resets the flag EOC and polling cannot be + * performed on each conversion. Nevertheless, polling can still + * be performed on the complete sequence (ADC init + * parameter "EOCSelection" set to ADC_EOC_SEQ_CONV). + * @param hadc ADC handle + * @param Timeout Timeout value in millisecond. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout) +{ + uint32_t tickstart; + uint32_t tmp_flag_end; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* If end of conversion selected to end of sequence conversions */ + if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV) + { + tmp_flag_end = ADC_FLAG_EOS; + } + /* If end of conversion selected to end of unitary conversion */ + else /* ADC_EOC_SINGLE_CONV */ + { + /* Verification that ADC configuration is compliant with polling for */ + /* each conversion: */ + /* Particular case is ADC configured in DMA mode and ADC sequencer with */ + /* several ranks and polling for end of each conversion. */ + /* For code simplicity sake, this particular case is generalized to */ + /* ADC configured in DMA mode and and polling for end of each conversion. */ + if ((hadc->Instance->CFGR1 & ADC_CFGR1_DMAEN) != 0UL) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + + return HAL_ERROR; + } + else + { + tmp_flag_end = (ADC_FLAG_EOC); + } + } + + /* Get tick count */ + tickstart = HAL_GetTick(); + + /* Wait until End of unitary conversion or sequence conversions flag is raised */ + while ((hadc->Instance->ISR & tmp_flag_end) == 0UL) + { + /* Check if timeout is disabled (set to infinite wait) */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) + { + /* New check to avoid false timeout detection in case of preemption */ + if ((hadc->Instance->ISR & tmp_flag_end) == 0UL) + { + /* Update ADC state machine to timeout */ + SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); + + __HAL_UNLOCK(hadc); + + return HAL_TIMEOUT; + } + } + } + } + + /* Update ADC state machine */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); + + /* Determine whether any further conversion upcoming on group regular */ + /* by external trigger, continuous mode or scan sequence on going. */ + if ((LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL) + && (hadc->Init.ContinuousConvMode == DISABLE) + ) + { + /* Check whether end of sequence is reached */ + if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS)) + { + /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */ + /* ADSTART==0 (no conversion on going) */ + if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) + { + /* Disable ADC end of single conversion interrupt on group regular */ + /* Note: Overrun interrupt was enabled with EOC interrupt in */ + /* HAL_Start_IT(), but is not disabled here because can be used */ + /* by overrun IRQ process below. */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS); + + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY, + HAL_ADC_STATE_READY); + } + else + { + /* Change ADC state to error state */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + } + } + } + + /* Clear end of conversion flag of regular group if low power feature */ + /* "LowPowerAutoWait " is disabled, to not interfere with this feature */ + /* until data register is read using function HAL_ADC_GetValue(). */ + if (hadc->Init.LowPowerAutoWait == DISABLE) + { + /* Clear regular group conversion flag */ + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS)); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Poll for ADC event. + * @param hadc ADC handle + * @param EventType the ADC event type. + * This parameter can be one of the following values: + * @arg @ref ADC_EOSMP_EVENT ADC End of Sampling event + * @arg @ref ADC_AWD1_EVENT ADC Analog watchdog 1 event (main analog watchdog, present on + * all STM32 series) + * @arg @ref ADC_AWD2_EVENT ADC Analog watchdog 2 event (additional analog watchdog, not present on + * all STM32 series) + * @arg @ref ADC_AWD3_EVENT ADC Analog watchdog 3 event (additional analog watchdog, not present on + * all STM32 series) + * @arg @ref ADC_OVR_EVENT ADC Overrun event + * @param Timeout Timeout value in millisecond. + * @note The relevant flag is cleared if found to be set, except for ADC_FLAG_OVR. + * Indeed, the latter is reset only if hadc->Init.Overrun field is set + * to ADC_OVR_DATA_OVERWRITTEN. Otherwise, data register may be potentially overwritten + * by a new converted data as soon as OVR is cleared. + * To reset OVR flag once the preserved data is retrieved, the user can resort + * to macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + assert_param(IS_ADC_EVENT_TYPE(EventType)); + + /* Get tick count */ + tickstart = HAL_GetTick(); + + /* Check selected event flag */ + while (__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL) + { + /* Check if timeout is disabled (set to infinite wait) */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) + { + /* New check to avoid false timeout detection in case of preemption */ + if (__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL) + { + /* Update ADC state machine to timeout */ + SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); + + __HAL_UNLOCK(hadc); + + return HAL_TIMEOUT; + } + } + } + } + + switch (EventType) + { + /* End Of Sampling event */ + case ADC_EOSMP_EVENT: + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP); + + /* Clear the End Of Sampling flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP); + + break; + + /* Analog watchdog (level out of window) event */ + /* Note: In case of several analog watchdog enabled, if needed to know */ + /* which one triggered and on which ADCx, test ADC state of analog watchdog */ + /* flags HAL_ADC_STATE_AWD1/2/3 using function "HAL_ADC_GetState()". */ + /* For example: */ + /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " */ + /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD2) != 0UL) " */ + /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD3) != 0UL) " */ + + /* Check analog watchdog 1 flag */ + case ADC_AWD_EVENT: + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); + + /* Clear ADC analog watchdog flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1); + + break; + + /* Check analog watchdog 2 flag */ + case ADC_AWD2_EVENT: + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_AWD2); + + /* Clear ADC analog watchdog flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2); + + break; + + /* Check analog watchdog 3 flag */ + case ADC_AWD3_EVENT: + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_AWD3); + + /* Clear ADC analog watchdog flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3); + + break; + + /* Overrun event */ + default: /* Case ADC_OVR_EVENT */ + /* If overrun is set to overwrite previous data, overrun event is not */ + /* considered as an error. */ + /* (cf ref manual "Managing conversions without using the DMA and without */ + /* overrun ") */ + if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) + { + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR); + + /* Set ADC error code to overrun */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); + } + else + { + /* Clear ADC Overrun flag only if Overrun is set to ADC_OVR_DATA_OVERWRITTEN + otherwise, data register is potentially overwritten by new converted data as soon + as OVR is cleared. */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); + } + break; + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Enable ADC, start conversion of regular group with interruption. + * @note Interruptions enabled in this function according to initialization + * setting : EOC (end of conversion), EOS (end of sequence), + * OVR overrun. + * Each of these interruptions has its dedicated callback function. + * @note To guarantee a proper reset of all interruptions once all the needed + * conversions are obtained, HAL_ADC_Stop_IT() must be called to ensure + * a correct stop of the IT-based conversions. + * @note By default, HAL_ADC_Start_IT() does not enable the End Of Sampling + * interruption. If required (e.g. in case of oversampling with trigger + * mode), the user must: + * 1. first clear the EOSMP flag if set with macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP) + * 2. then enable the EOSMP interrupt with macro __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOSMP) + * before calling HAL_ADC_Start_IT(). + * @param hadc ADC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc) +{ + HAL_StatusTypeDef tmp_hal_status; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Perform ADC enable and conversion start if no conversion is on going */ + if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) + { + __HAL_LOCK(hadc); + + /* Enable the ADC peripheral */ + tmp_hal_status = ADC_Enable(hadc); + + /* Start conversion if ADC is effectively enabled */ + if (tmp_hal_status == HAL_OK) + { + /* Set ADC state */ + /* - Clear state bitfield related to regular group conversion results */ + /* - Set state bitfield related to regular operation */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, + HAL_ADC_STATE_REG_BUSY); + + + /* Set ADC error code */ + /* Reset all ADC error code fields */ + ADC_CLEAR_ERRORCODE(hadc); + + /* Clear ADC group regular conversion flag and overrun flag */ + /* (To ensure of no unknown state from potential previous ADC operations) */ + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); + + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); + + /* Disable all interruptions before enabling the desired ones */ + __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR)); + + /* Enable ADC end of conversion interrupt */ + switch (hadc->Init.EOCSelection) + { + case ADC_EOC_SEQ_CONV: + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOS); + break; + /* case ADC_EOC_SINGLE_CONV */ + default: + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC); + break; + } + + /* Enable ADC overrun interrupt */ + /* If hadc->Init.Overrun is set to ADC_OVR_DATA_PRESERVED, only then is + ADC_IT_OVR enabled; otherwise data overwrite is considered as normal + behavior and no CPU time is lost for a non-processed interruption */ + if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) + { + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); + } + + /* Enable conversion of regular group. */ + /* If software start has been selected, conversion starts immediately. */ + /* If external trigger has been selected, conversion will start at next */ + /* trigger event. */ + /* Start ADC group regular conversion */ + LL_ADC_REG_StartConversion(hadc->Instance); + } + else + { + __HAL_UNLOCK(hadc); + } + + } + else + { + tmp_hal_status = HAL_BUSY; + } + + return tmp_hal_status; +} + +/** + * @brief Stop ADC conversion of regular group (and injected group in + * case of auto_injection mode), disable interrution of + * end-of-conversion, disable ADC peripheral. + * @param hadc ADC handle + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc) +{ + HAL_StatusTypeDef tmp_hal_status; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + __HAL_LOCK(hadc); + + /* 1. Stop potential conversion on going, on ADC group regular */ + tmp_hal_status = ADC_ConversionStop(hadc); + + /* Disable ADC peripheral if conversions are effectively stopped */ + if (tmp_hal_status == HAL_OK) + { + /* Disable ADC end of conversion interrupt for regular group */ + /* Disable ADC overrun interrupt */ + __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR)); + + /* 2. Disable the ADC peripheral */ + tmp_hal_status = ADC_Disable(hadc); + + /* Check if ADC is effectively disabled */ + if (tmp_hal_status == HAL_OK) + { + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY, + HAL_ADC_STATE_READY); + } + } + + __HAL_UNLOCK(hadc); + + return tmp_hal_status; +} + +/** + * @brief Enable ADC, start conversion of regular group and transfer result through DMA. + * @note Interruptions enabled in this function: + * overrun (if applicable), DMA half transfer, DMA transfer complete. + * Each of these interruptions has its dedicated callback function. + * @param hadc ADC handle + * @param pData Destination Buffer address. + * @param Length Number of data to be transferred from ADC peripheral to memory + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length) +{ + HAL_StatusTypeDef tmp_hal_status; + uint32_t LengthInBytes; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Perform ADC enable and conversion start if no conversion is on going */ + if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) + { + __HAL_LOCK(hadc); + + /* Specific case for first call occurrence of this function (DMA transfer */ + /* not activated and ADC disabled), DMA transfer must be activated */ + /* with ADC disabled. */ + if ((hadc->Instance->CFGR1 & ADC_CFGR1_DMAEN) == 0UL) + { + if (LL_ADC_IsEnabled(hadc->Instance) != 0UL) + { + /* Disable ADC */ + LL_ADC_Disable(hadc->Instance); + } + + /* Enable ADC DMA mode */ + hadc->Instance->CFGR1 |= ADC_CFGR1_DMAEN; + } + + /* Enable the ADC peripheral */ + tmp_hal_status = ADC_Enable(hadc); + + /* Start conversion if ADC is effectively enabled */ + if (tmp_hal_status == HAL_OK) + { + /* Set ADC state */ + /* - Clear state bitfield related to regular group conversion results */ + /* - Set state bitfield related to regular operation */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, + HAL_ADC_STATE_REG_BUSY); + + /* Set ADC error code */ + /* Reset all ADC error code fields */ + ADC_CLEAR_ERRORCODE(hadc); + + /* Set the DMA transfer complete callback */ + hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; + + /* Set the DMA half transfer complete callback */ + hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; + + /* Set the DMA error callback */ + hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; + + + /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */ + /* start (in case of SW start): */ + + /* Clear regular group conversion flag and overrun flag */ + /* (To ensure of no unknown state from potential previous ADC */ + /* operations) */ + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); + + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); + + /* Enable ADC overrun interrupt */ + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); + + /* Length should be converted to number of bytes */ + LengthInBytes = Length * 4U; + + /* Start the DMA channel */ + if ((hadc->DMA_Handle->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if ((hadc->DMA_Handle->LinkedListQueue != NULL) && (hadc->DMA_Handle->LinkedListQueue->Head != NULL)) + { + hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = (uint32_t)LengthInBytes; + hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = \ + (uint32_t)&hadc->Instance->DR; + hadc->DMA_Handle->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData; + tmp_hal_status = HAL_DMAEx_List_Start_IT(hadc->DMA_Handle); + } + else + { + tmp_hal_status = HAL_ERROR; + } + } + else + { + tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, \ + LengthInBytes); + } + + /* Enable conversion of regular group. */ + /* If software start has been selected, conversion starts immediately. */ + /* If external trigger has been selected, conversion will start at next */ + /* trigger event. */ + /* Start ADC group regular conversion */ + LL_ADC_REG_StartConversion(hadc->Instance); + } + } + else + { + tmp_hal_status = HAL_BUSY; + } + + return tmp_hal_status; +} + +/** + * @brief Stop ADC conversion of regular group (and injected group in + * case of auto_injection mode), disable ADC DMA transfer, disable + * ADC peripheral. + * @param hadc ADC handle + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc) +{ + HAL_StatusTypeDef tmp_hal_status; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + __HAL_LOCK(hadc); + + /* 1. Stop potential ADC group regular conversion on going */ + tmp_hal_status = ADC_ConversionStop(hadc); + + /* Disable ADC peripheral if conversions are effectively stopped */ + if (tmp_hal_status == HAL_OK) + { + /* Disable the DMA channel (in case of DMA in circular mode or stop */ + /* while DMA transfer is on going) */ + if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY) + { + tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); + + /* Check if DMA channel effectively disabled */ + if (tmp_hal_status != HAL_OK) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); + } + } + + /* Disable ADC overrun interrupt */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); + + /* 2. Disable the ADC peripheral */ + /* Update "tmp_hal_status" only if DMA channel disabling passed, */ + /* to keep in memory a potential failing status. */ + if (tmp_hal_status == HAL_OK) + { + tmp_hal_status = ADC_Disable(hadc); + } + else + { + (void)ADC_Disable(hadc); + } + + /* Check if ADC is effectively disabled */ + if (tmp_hal_status == HAL_OK) + { + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY, + HAL_ADC_STATE_READY); + } + + /* Disable ADC DMA (ADC DMA configuration of continuous requests is kept) */ + CLEAR_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN); + } + + __HAL_UNLOCK(hadc); + + return tmp_hal_status; +} + +/** + * @brief Get ADC regular group conversion result. + * @note Reading register DR automatically clears ADC flag EOC + * (ADC group regular end of unitary conversion). + * @note This function does not clear ADC flag EOS + * (ADC group regular end of sequence conversion). + * Occurrence of flag EOS rising: + * - If sequencer is composed of 1 rank, flag EOS is equivalent + * to flag EOC. + * - If sequencer is composed of several ranks, during the scan + * sequence flag EOC only is raised, at the end of the scan sequence + * both flags EOC and EOS are raised. + * To clear this flag, either use function: + * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming + * model polling: @ref HAL_ADC_PollForConversion() + * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS). + * @param hadc ADC handle + * @retval ADC group regular conversion data + */ +uint32_t HAL_ADC_GetValue(const ADC_HandleTypeDef *hadc) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Note: EOC flag is not cleared here by software because automatically */ + /* cleared by hardware when reading register DR. */ + + /* Return ADC converted value */ + return hadc->Instance->DR; +} + +/** + * @brief Handle ADC interrupt request. + * @param hadc ADC handle + * @retval None + */ +void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc) +{ + uint32_t overrun_error = 0UL; /* flag set if overrun occurrence has to be considered as an error */ + uint32_t tmp_isr = hadc->Instance->ISR; + uint32_t tmp_ier = hadc->Instance->IER; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); + + /* ========== Check End of Sampling flag for ADC group regular ========== */ + if (((tmp_isr & ADC_FLAG_EOSMP) == ADC_FLAG_EOSMP) && ((tmp_ier & ADC_IT_EOSMP) == ADC_IT_EOSMP)) + { + /* Update state machine on end of sampling status if not in error state */ + if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) + { + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP); + } + + /* End Of Sampling callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->EndOfSamplingCallback(hadc); +#else + HAL_ADCEx_EndOfSamplingCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + + /* Clear regular group conversion flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP); + } + + /* ====== Check ADC group regular end of unitary conversion sequence conversions ===== */ + if ((((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) || + (((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS))) + { + /* Update state machine on conversion status if not in error state */ + if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) + { + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); + } + + /* Determine whether any further conversion upcoming on group regular */ + /* by external trigger, continuous mode or scan sequence on going */ + /* to disable interruption. */ + if ((LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL) + && (hadc->Init.ContinuousConvMode == DISABLE) + ) + { + /* If End of Sequence is reached, disable interrupts */ + if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS)) + { + /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */ + /* ADSTART==0 (no conversion on going) */ + if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) + { + /* Disable ADC end of single conversion interrupt on group regular */ + /* Note: Overrun interrupt was enabled with EOC interrupt in */ + /* HAL_Start_IT(), but is not disabled here because can be used */ + /* by overrun IRQ process below. */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS); + + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY, + HAL_ADC_STATE_READY); + } + else + { + /* Change ADC state to error state */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + } + } + } + + /* Conversion complete callback */ + /* Note: Into callback function "HAL_ADC_ConvCpltCallback()", */ + /* to determine if conversion has been triggered from EOC or EOS, */ + /* possibility to use: */ + /* " if ( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->ConvCpltCallback(hadc); +#else + HAL_ADC_ConvCpltCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + + /* Clear regular group conversion flag */ + /* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of */ + /* conversion flags clear induces the release of the preserved data.*/ + /* Therefore, if the preserved data value is needed, it must be */ + /* read preliminarily into HAL_ADC_ConvCpltCallback(). */ + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS)); + } + + /* ========== Check Analog watchdog 1 flag ========== */ + if (((tmp_isr & ADC_FLAG_AWD1) == ADC_FLAG_AWD1) && ((tmp_ier & ADC_IT_AWD1) == ADC_IT_AWD1)) + { + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); + + /* Level out of window 1 callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->LevelOutOfWindowCallback(hadc); +#else + HAL_ADC_LevelOutOfWindowCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + + /* Clear ADC analog watchdog flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1); + } + + /* ========== Check analog watchdog 2 flag ========== */ + if (((tmp_isr & ADC_FLAG_AWD2) == ADC_FLAG_AWD2) && ((tmp_ier & ADC_IT_AWD2) == ADC_IT_AWD2)) + { + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_AWD2); + + /* Level out of window 2 callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->LevelOutOfWindow2Callback(hadc); +#else + HAL_ADCEx_LevelOutOfWindow2Callback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + + /* Clear ADC analog watchdog flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2); + } + + /* ========== Check analog watchdog 3 flag ========== */ + if (((tmp_isr & ADC_FLAG_AWD3) == ADC_FLAG_AWD3) && ((tmp_ier & ADC_IT_AWD3) == ADC_IT_AWD3)) + { + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_AWD3); + + /* Level out of window 3 callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->LevelOutOfWindow3Callback(hadc); +#else + HAL_ADCEx_LevelOutOfWindow3Callback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + + /* Clear ADC analog watchdog flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3); + } + + /* ========== Check Overrun flag ========== */ + if (((tmp_isr & ADC_FLAG_OVR) == ADC_FLAG_OVR) && ((tmp_ier & ADC_IT_OVR) == ADC_IT_OVR)) + { + /* If overrun is set to overwrite previous data (default setting), */ + /* overrun event is not considered as an error. */ + /* (cf ref manual "Managing conversions without using the DMA and without */ + /* overrun ") */ + /* Exception for usage with DMA overrun event always considered as an */ + /* error. */ + if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) + { + overrun_error = 1UL; + } + else + { + /* Check DMA configuration */ + if (LL_ADC_REG_GetDMATransfer(hadc->Instance) != LL_ADC_REG_DMA_TRANSFER_NONE) + { + overrun_error = 1UL; + } + } + + if (overrun_error == 1UL) + { + /* Change ADC state to error state */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR); + + /* Set ADC error code to overrun */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); + + /* Error callback */ + /* Note: In case of overrun, ADC conversion data is preserved until */ + /* flag OVR is reset. */ + /* Therefore, old ADC conversion data can be retrieved in */ + /* function "HAL_ADC_ErrorCallback()". */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->ErrorCallback(hadc); +#else + HAL_ADC_ErrorCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + } + + /* Clear ADC overrun flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); + } + + /* ========== Check channel configuration ready flag ========== */ + if (((tmp_isr & ADC_FLAG_LDORDY) == ADC_FLAG_LDORDY) && ((tmp_ier & ADC_IT_LDORDY) == ADC_IT_LDORDY)) + { + /* Internal voltage regulator callback */ + HAL_ADCEx_LDOReadyCallback(hadc); + + /* Clear ADC analog watchdog flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_LDORDY); + } +} + +/** + * @brief Conversion complete callback in non-blocking mode. + * @param hadc ADC handle + * @retval None + */ +__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADC_ConvCpltCallback must be implemented in the user file. + */ +} + +/** + * @brief Conversion DMA half-transfer callback in non-blocking mode. + * @param hadc ADC handle + * @retval None + */ +__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file. + */ +} + +/** + * @brief Analog watchdog 1 callback in non-blocking mode. + * @param hadc ADC handle + * @retval None + */ +__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file. + */ +} + +/** + * @brief ADC error callback in non-blocking mode + * (ADC conversion with interruption or transfer by DMA). + * @note In case of error due to overrun when using ADC with DMA transfer + * (HAL ADC handle parameter "ErrorCode" to state "HAL_ADC_ERROR_OVR"): + * - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()". + * - If needed, restart a new ADC conversion using function + * "HAL_ADC_Start_DMA()" + * (this function is also clearing overrun flag) + * @param hadc ADC handle + * @retval None + */ +__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADC_ErrorCallback must be implemented in the user file. + */ +} + +/** + * @} + */ + +/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure channels on regular group + (+) Configure the analog watchdog + +@endverbatim + * @{ + */ + +/** + * @brief Configure a channel to be assigned to ADC group regular. + * @note In case of usage of internal measurement channels: + * Vbat/VrefInt/TempSensor. + * These internal paths can be disabled using function + * HAL_ADC_DeInit(). + * @note Possibility to update parameters on the fly: + * This function initializes channel into ADC group regular, + * following calls to this function can be used to reconfigure + * some parameters of structure "ADC_ChannelConfTypeDef" on the fly, + * without resetting the ADC. + * The setting of these parameters is conditioned to ADC state: + * Refer to comments of structure "ADC_ChannelConfTypeDef". + * @param hadc ADC handle + * @param pConfig Structure of ADC channel assigned to ADC group regular. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, const ADC_ChannelConfTypeDef *pConfig) +{ + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + uint32_t tmp_config_internal_channel; + __IO uint32_t wait_loop_index = 0UL; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + assert_param(IS_ADC_CHANNEL(pConfig->Channel)); + assert_param(IS_ADC_SAMPLING_TIME_COMMON(pConfig->SamplingTime)); + + if ((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED) || + (hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED_BACKWARD)) + { + assert_param(IS_ADC_REGULAR_RANK_SEQ_FIXED(pConfig->Rank)); + } + else + { + assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion)); + + assert_param(IS_ADC_REGULAR_RANK(pConfig->Rank)); + } + + __HAL_LOCK(hadc); + + /* Parameters update conditioned to ADC state: */ + /* Parameters that can be updated when ADC is disabled or enabled without */ + /* conversion on going on regular group: */ + /* - Channel number */ + /* - Channel sampling time */ + /* - Management of internal measurement channels: VrefInt/TempSensor/Vbat */ + if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) + { + /* Configure channel: depending on rank setting, add it or remove it from */ + /* ADC sequencer. */ + /* If sequencer set to not fully configurable with channel rank set to */ + /* none, remove the channel from the sequencer. */ + /* Otherwise (sequencer set to fully configurable or to to not fully */ + /* configurable with channel rank to be set), configure the selected */ + /* channel. */ + if (pConfig->Rank != ADC_RANK_NONE) + { + /* Regular sequence configuration */ + /* Note: ADC channel configuration requires few ADC clock cycles */ + /* to be ready. Processing of ADC settings in this function */ + /* induce that a specific wait time is not necessary. */ + /* For more details on ADC channel configuration ready, */ + /* refer to function "LL_ADC_IsActiveFlag_CCRDY()". */ + if ((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED) || + (hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED_BACKWARD)) + { + /* Sequencer set to not fully configurable: */ + /* Set the channel by enabling the corresponding bitfield. */ + LL_ADC_REG_SetSequencerChAdd(hadc->Instance, pConfig->Channel); + } + else + { + /* Sequencer set to fully configurable: */ + /* Set the channel by entering it into the selected rank. */ + + /* Memorize the channel set into variable in HAL ADC handle */ + MODIFY_REG(hadc->ADCGroupRegularSequencerRanks, + ADC_CHSELR_SQ1 << (pConfig->Rank & 0x1FUL), + __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel) << (pConfig->Rank & 0x1FUL)); + + /* If the selected rank is below ADC group regular sequencer length, */ + /* apply the configuration in ADC register. */ + /* Note: Otherwise, configuration is not applied. */ + /* To apply it, parameter'NbrOfConversion' must be increased. */ + if (((pConfig->Rank >> 2UL) + 1UL) <= hadc->Init.NbrOfConversion) + { + LL_ADC_REG_SetSequencerRanks(hadc->Instance, pConfig->Rank, pConfig->Channel); + } + } + + /* Set sampling time of the selected ADC channel */ + LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfig->Channel, pConfig->SamplingTime); + + /* Management of internal measurement channels: VrefInt/TempSensor/Vbat */ + /* internal measurement paths enable: If internal channel selected, */ + /* enable dedicated internal buffers and path. */ + /* Note: these internal measurement paths can be disabled using */ + /* HAL_ADC_DeInit() or removing the channel from sequencer with */ + /* channel configuration parameter "Rank". */ + if (__LL_ADC_IS_CHANNEL_INTERNAL(pConfig->Channel)) + { + tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); + + /* If the requested internal measurement path has already been enabled, */ + /* bypass the configuration processing. */ + if ((pConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && + ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL)) + { + LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), + LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel); + + /* Delay for temperature sensor stabilization time */ + /* Wait loop initialization and execution */ + /* Note: Variable divided by 2 to compensate partially */ + /* CPU processing cycles, scaling in us split to not */ + /* exceed 32 bits register capacity and handle low frequency. */ + wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); + while (wait_loop_index != 0UL) + { + wait_loop_index--; + } + } + else if ((pConfig->Channel == ADC_CHANNEL_VREFINT) && + ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL)) + { + LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), + LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel); + } + else + { + /* nothing to do */ + } + } + } + else + { + /* Regular sequencer configuration */ + /* Note: Case of sequencer set to fully configurable: */ + /* Sequencer rank cannot be disabled, only affected to */ + /* another channel. */ + /* To remove a rank, use parameter 'NbrOfConversion". */ + if ((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED) || + (hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED_BACKWARD)) + { + /* Sequencer set to not fully configurable: */ + /* Reset the channel by disabling the corresponding bitfield. */ + LL_ADC_REG_SetSequencerChRem(hadc->Instance, pConfig->Channel); + } + + /* Management of internal measurement channels: Vbat/VrefInt/TempSensor. */ + /* If internal channel selected, enable dedicated internal buffers and */ + /* paths. */ + if (__LL_ADC_IS_CHANNEL_INTERNAL(pConfig->Channel)) + { + tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); + + if (pConfig->Channel == ADC_CHANNEL_TEMPSENSOR) + { + LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), + ~LL_ADC_PATH_INTERNAL_TEMPSENSOR & tmp_config_internal_channel); + } + else if (pConfig->Channel == ADC_CHANNEL_VREFINT) + { + LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), + ~LL_ADC_PATH_INTERNAL_VREFINT & tmp_config_internal_channel); + } + else + { + /* nothing to do */ + } + } + } + } + + /* If a conversion is on going on regular group, no update on regular */ + /* channel could be done on neither of the channel configuration structure */ + /* parameters. */ + else + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + + tmp_hal_status = HAL_ERROR; + } + + __HAL_UNLOCK(hadc); + + return tmp_hal_status; +} + +/** + * @brief Configure the analog watchdog. + * @note Possibility to update parameters on the fly: + * This function initializes the selected analog watchdog, successive + * calls to this function can be used to reconfigure some parameters + * of structure "ADC_AnalogWDGConfTypeDef" on the fly, without resetting + * the ADC. + * The setting of these parameters is conditioned to ADC state. + * For parameters constraints, see comments of structure + * "ADC_AnalogWDGConfTypeDef". + * @note On this STM32 series, analog watchdog thresholds can be modified + * while ADC conversion is on going. + * In this case, some constraints must be taken into account: + * the programmed threshold values are effective from the next + * ADC EOC (end of unitary conversion). + * Considering that registers write delay may happen due to + * bus activity, this might cause an uncertainty on the + * effective timing of the new programmed threshold values. + * @param hadc ADC handle + * @param pAnalogWDGConfig Structure of ADC analog watchdog configuration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, const ADC_AnalogWDGConfTypeDef *pAnalogWDGConfig) +{ + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + uint32_t tmp_awd_high_threshold_shifted; + uint32_t tmp_awd_low_threshold_shifted; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(pAnalogWDGConfig->WatchdogNumber)); + assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(pAnalogWDGConfig->WatchdogMode)); + assert_param(IS_FUNCTIONAL_STATE(pAnalogWDGConfig->ITMode)); + + if (pAnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) + { + assert_param(IS_ADC_CHANNEL(pAnalogWDGConfig->Channel)); + } + + /* Verify thresholds range */ + if (hadc->Init.OversamplingMode == ENABLE) + { + /* Case of oversampling enabled: depending on ratio and shift configuration, + analog watchdog thresholds can be higher than ADC resolution. + Verify if thresholds are within maximum thresholds range. */ + assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, pAnalogWDGConfig->HighThreshold)); + assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, pAnalogWDGConfig->LowThreshold)); + } + else + { + /* Verify if thresholds are within the selected ADC resolution */ + assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pAnalogWDGConfig->HighThreshold)); + assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pAnalogWDGConfig->LowThreshold)); + } + + __HAL_LOCK(hadc); + + /* Parameters update conditioned to ADC state: */ + /* Parameters that can be updated when ADC is disabled or enabled without */ + /* conversion on going on ADC group regular: */ + /* - Analog watchdog channels */ + if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) + { + /* Analog watchdog configuration */ + if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1) + { + /* Configuration of analog watchdog: */ + /* - Set the analog watchdog enable mode: one or overall group of */ + /* channels. */ + switch (pAnalogWDGConfig->WatchdogMode) + { + case ADC_ANALOGWATCHDOG_SINGLE_REG: + LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, + __LL_ADC_ANALOGWD_CHANNEL_GROUP(pAnalogWDGConfig->Channel, + LL_ADC_GROUP_REGULAR)); + break; + + case ADC_ANALOGWATCHDOG_ALL_REG: + LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG); + break; + + default: /* ADC_ANALOGWATCHDOG_NONE */ + LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_DISABLE); + break; + } + + /* Update state, clear previous result related to AWD1 */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD1); + + /* Clear flag ADC analog watchdog */ + /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */ + /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */ + /* (in case left enabled by previous ADC operations). */ + LL_ADC_ClearFlag_AWD1(hadc->Instance); + + /* Configure ADC analog watchdog interrupt */ + if (pAnalogWDGConfig->ITMode == ENABLE) + { + LL_ADC_EnableIT_AWD1(hadc->Instance); + } + else + { + LL_ADC_DisableIT_AWD1(hadc->Instance); + } + } + /* Case of ADC_ANALOGWATCHDOG_2 or ADC_ANALOGWATCHDOG_3 */ + else + { + switch (pAnalogWDGConfig->WatchdogMode) + { + case ADC_ANALOGWATCHDOG_SINGLE_REG: + /* Update AWD by bitfield to keep the possibility to monitor */ + /* several channels by successive calls of this function. */ + if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2) + { + SET_BIT(hadc->Instance->AWD2CR, (1UL << __LL_ADC_CHANNEL_TO_DECIMAL_NB(pAnalogWDGConfig->Channel))); + } + else + { + SET_BIT(hadc->Instance->AWD3CR, (1UL << __LL_ADC_CHANNEL_TO_DECIMAL_NB(pAnalogWDGConfig->Channel))); + } + break; + + case ADC_ANALOGWATCHDOG_ALL_REG: + LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, + pAnalogWDGConfig->WatchdogNumber, + LL_ADC_AWD_ALL_CHANNELS_REG); + break; + + default: /* ADC_ANALOGWATCHDOG_NONE */ + LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, pAnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_DISABLE); + break; + } + + if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2) + { + /* Update state, clear previous result related to AWD2 */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD2); + + /* Clear flag ADC analog watchdog */ + /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */ + /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */ + /* (in case left enabled by previous ADC operations). */ + LL_ADC_ClearFlag_AWD2(hadc->Instance); + + /* Configure ADC analog watchdog interrupt */ + if (pAnalogWDGConfig->ITMode == ENABLE) + { + LL_ADC_EnableIT_AWD2(hadc->Instance); + } + else + { + LL_ADC_DisableIT_AWD2(hadc->Instance); + } + } + /* (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) */ + else + { + /* Update state, clear previous result related to AWD3 */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD3); + + /* Clear flag ADC analog watchdog */ + /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */ + /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */ + /* (in case left enabled by previous ADC operations). */ + LL_ADC_ClearFlag_AWD3(hadc->Instance); + + /* Configure ADC analog watchdog interrupt */ + if (pAnalogWDGConfig->ITMode == ENABLE) + { + LL_ADC_EnableIT_AWD3(hadc->Instance); + } + else + { + LL_ADC_DisableIT_AWD3(hadc->Instance); + } + } + } + + } + + /* Analog watchdog thresholds configuration */ + if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1) + { + /* Shift the offset with respect to the selected ADC resolution: */ + /* Thresholds have to be left-aligned on bit 11, the LSB (right bits) */ + /* are set to 0. */ + tmp_awd_high_threshold_shifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, pAnalogWDGConfig->HighThreshold); + tmp_awd_low_threshold_shifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, pAnalogWDGConfig->LowThreshold); + } + /* Case of ADC_ANALOGWATCHDOG_2 and ADC_ANALOGWATCHDOG_3 */ + else + { + /* No need to shift the offset with respect to the selected ADC resolution: */ + /* Thresholds have to be left-aligned on bit 11, the LSB (right bits) */ + /* are set to 0. */ + tmp_awd_high_threshold_shifted = pAnalogWDGConfig->HighThreshold; + tmp_awd_low_threshold_shifted = pAnalogWDGConfig->LowThreshold; + } + + /* Set ADC analog watchdog thresholds value of both thresholds high and low */ + LL_ADC_ConfigAnalogWDThresholds(hadc->Instance, pAnalogWDGConfig->WatchdogNumber, tmp_awd_high_threshold_shifted, + tmp_awd_low_threshold_shifted); + + __HAL_UNLOCK(hadc); + + return tmp_hal_status; +} + + +/** + * @} + */ + +/** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions + * @brief ADC Peripheral State functions + * +@verbatim + =============================================================================== + ##### Peripheral state and errors functions ##### + =============================================================================== + [..] + This subsection provides functions to get in run-time the status of the + peripheral. + (+) Check the ADC state + (+) Check the ADC error code + +@endverbatim + * @{ + */ + +/** + * @brief Return the ADC handle state. + * @note ADC state machine is managed by bitfields, ADC status must be + * compared with states bits. + * For example: + * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) " + * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " + * @param hadc ADC handle + * @retval ADC handle state (bitfield on 32 bits) + */ +uint32_t HAL_ADC_GetState(const ADC_HandleTypeDef *hadc) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Return ADC handle state */ + return hadc->State; +} + +/** + * @brief Return the ADC error code. + * @param hadc ADC handle + * @retval ADC error code (bitfield on 32 bits) + */ +uint32_t HAL_ADC_GetError(const ADC_HandleTypeDef *hadc) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + return hadc->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup ADC_Private_Functions ADC Private Functions + * @{ + */ + +/** + * @brief Stop ADC conversion. + * @note Prerequisite condition to use this function: ADC conversions must be + * stopped to disable the ADC. + * @param hadc ADC handle + * @retval HAL status. + */ +HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Verification if ADC is not already stopped on regular group to bypass */ + /* this function if not needed. */ + if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL) + { + /* Stop potential conversion on going on regular group */ + /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */ + if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL) + { + /* Stop ADC group regular conversion */ + LL_ADC_REG_StopConversion(hadc->Instance); + } + + /* Wait for conversion effectively stopped */ + /* Get tick count */ + tickstart = HAL_GetTick(); + + while ((hadc->Instance->CR & ADC_CR_ADSTART) != 0UL) + { + if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT) + { + /* New check to avoid false timeout detection in case of preemption */ + if ((hadc->Instance->CR & ADC_CR_ADSTART) != 0UL) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + + return HAL_ERROR; + } + } + } + + } + + /* Return HAL status */ + return HAL_OK; +} + +/** + * @brief Enable the selected ADC. + * @note Prerequisite condition to use this function: ADC must be disabled + * and voltage regulator must be enabled (done into HAL_ADC_Init()). + * @param hadc ADC handle + * @retval HAL status. + */ +HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc) +{ + uint32_t tickstart; + __IO uint32_t wait_loop_index = 0UL; + + /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ + /* enabling phase not yet completed: flag ADC ready not yet set). */ + /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ + /* causes: ADC clock not running, ...). */ + if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) + { + /* Check if conditions to enable the ADC are fulfilled */ + if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_ADSTP | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + + return HAL_ERROR; + } + + /* Enable the ADC peripheral */ + LL_ADC_Enable(hadc->Instance); + + if ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_TEMPSENSOR) + != 0UL) + { + /* Delay for temperature sensor buffer stabilization time */ + /* Wait loop initialization and execution */ + /* Note: Variable divided by 2 to compensate partially */ + /* CPU processing cycles, scaling in us split to not */ + /* exceed 32 bits register capacity and handle low frequency. */ + wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US / 10UL) + * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); + while (wait_loop_index != 0UL) + { + wait_loop_index--; + } + } + + /* If low power mode AutoPowerOff is enabled, power-on/off phases are */ + /* performed automatically by hardware and flag ADC ready is not set. */ + if (hadc->Init.LowPowerAutoPowerOff != ENABLE) + { + /* Wait for ADC effectively enabled */ + tickstart = HAL_GetTick(); + + while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) + { + /* If ADEN bit is set less than 4 ADC clock cycles after the ADCAL bit + has been cleared (after a calibration), ADEN bit is reset by the + calibration logic. + The workaround is to continue setting ADEN until ADRDY is becomes 1. + Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this + 4 ADC clock cycle duration */ + /* Note: Test of ADC enabled required due to hardware constraint to */ + /* not enable ADC if already enabled. */ + if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) + { + LL_ADC_Enable(hadc->Instance); + } + + if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) + { + /* New check to avoid false timeout detection in case of preemption */ + if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + + return HAL_ERROR; + } + } + } + } + } + + /* Return HAL status */ + return HAL_OK; +} + +/** + * @brief Disable the selected ADC. + * @note Prerequisite condition to use this function: ADC conversions must be + * stopped. + * @param hadc ADC handle + * @retval HAL status. + */ +HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc) +{ + uint32_t tickstart; + const uint32_t tmp_adc_is_disable_on_going = LL_ADC_IsDisableOngoing(hadc->Instance); + + /* Verification if ADC is not already disabled: */ + /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */ + /* disabled. */ + if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL) + && (tmp_adc_is_disable_on_going == 0UL) + ) + { + /* Check if conditions to disable the ADC are fulfilled */ + if ((hadc->Instance->CR & (ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN) + { + /* Disable the ADC peripheral */ + LL_ADC_Disable(hadc->Instance); + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); + } + else + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + + return HAL_ERROR; + } + + /* Wait for ADC effectively disabled */ + /* Get tick count */ + tickstart = HAL_GetTick(); + + while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) + { + if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) + { + /* New check to avoid false timeout detection in case of preemption */ + if ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + + return HAL_ERROR; + } + } + } + } + + /* Return HAL status */ + return HAL_OK; +} + +/** + * @brief DMA transfer complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) +{ + /* Retrieve ADC handle corresponding to current DMA handle */ + ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Update state machine on conversion status if not in error state */ + if ((hadc->State & (HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) == 0UL) + { + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); + + /* Determine whether any further conversion upcoming on group regular */ + /* by external trigger, continuous mode or scan sequence on going */ + /* to disable interruption. */ + if ((LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL) + && (hadc->Init.ContinuousConvMode == DISABLE) + ) + { + /* If End of Sequence is reached, disable interrupts */ + if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS)) + { + /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */ + /* ADSTART==0 (no conversion on going) */ + if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) + { + /* Disable ADC end of single conversion interrupt on group regular */ + /* Note: Overrun interrupt was enabled with EOC interrupt in */ + /* HAL_Start_IT(), but is not disabled here because can be used */ + /* by overrun IRQ process below. */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS); + + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY, + HAL_ADC_STATE_READY); + } + else + { + /* Change ADC state to error state */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + } + } + } + + /* Conversion complete callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->ConvCpltCallback(hadc); +#else + HAL_ADC_ConvCpltCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + } + else /* DMA and-or internal error occurred */ + { + if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) != 0UL) + { + /* Call HAL ADC Error Callback function */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->ErrorCallback(hadc); +#else + HAL_ADC_ErrorCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + } + else + { + /* Call ADC DMA error callback */ + hadc->DMA_Handle->XferErrorCallback(hdma); + } + } +} + +/** + * @brief DMA half transfer complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) +{ + /* Retrieve ADC handle corresponding to current DMA handle */ + ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Half conversion callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->ConvHalfCpltCallback(hadc); +#else + HAL_ADC_ConvHalfCpltCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA error callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void ADC_DMAError(DMA_HandleTypeDef *hdma) +{ + /* Retrieve ADC handle corresponding to current DMA handle */ + ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); + + /* Set ADC error code to DMA error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA); + + /* Error callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->ErrorCallback(hadc); +#else + HAL_ADC_ErrorCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ +} + +/** + * @} + */ + +#endif /* HAL_ADC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_adc_ex.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_adc_ex.c new file mode 100644 index 0000000000..dbc56e76f5 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_adc_ex.c @@ -0,0 +1,350 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_adc_ex.c + * @author MCD Application Team + * @brief This file provides firmware functions to manage the following + * functionalities of the Analog to Digital Converter (ADC) + * peripheral: + * + Peripheral Control functions + * Other functions (generic functions) are available in file + * "stm32wbaxx_hal_adc.c". + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + [..] + (@) Sections "ADC peripheral features" and "How to use this driver" are + available in file of generic functions "stm32wbaxx_hal_adc.c". + [..] + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @defgroup ADCEx ADCEx + * @brief ADC Extended HAL module driver + * @{ + */ + +#ifdef HAL_ADC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/** @defgroup ADCEx_Private_Constants ADC Extended Private Constants + * @{ + */ + +/* Fixed timeout value for ADC calibration. */ +/* Values defined to be higher than worst cases: maximum ratio between ADC */ +/* and CPU clock frequencies. */ +/* Example of profile low frequency : ADC frequency at 31.25kHz (ADC clock */ +/* source PLL 8MHz, ADC clock prescaler 256), CPU frequency 100MHz. */ +/* Calibration time max = 116 / fADC (refer to datasheet) */ +/* = 371 200 CPU cycles */ +#define ADC_CALIBRATION_TIMEOUT (178176UL) /*!< ADC calibration time-out value (unit: CPU cycles) */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup ADCEx_Exported_Functions ADC Extended Exported Functions + * @{ + */ + +/** @defgroup ADCEx_Exported_Functions_Group1 Extended Input and Output operation functions + * @brief Extended IO operation functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides functions allowing to: + + (+) Perform the ADC self-calibration. + (+) Get calibration factors. + (+) Set calibration factors. + +@endverbatim + * @{ + */ + +/** + * @brief Perform an ADC automatic self-calibration + * Calibration prerequisite: ADC must be disabled (execute this + * function before HAL_ADC_Start() or after HAL_ADC_Stop() ). + * @note Calibration factor can be read after calibration, using function + * HAL_ADC_GetValue() (value on 7 bits: from DR[6;0]). + * @param hadc ADC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc) +{ + HAL_StatusTypeDef tmp_hal_status; + __IO uint32_t wait_loop_index = 0UL; + uint32_t backup_setting_cfgr1; + uint32_t backup_setting_pwrr; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + __HAL_LOCK(hadc); + + /* Calibration prerequisite: ADC must be disabled. */ + + /* Disable the ADC (if not already disabled) */ + tmp_hal_status = ADC_Disable(hadc); + + /* Check if ADC is effectively disabled */ + if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) + { + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY, + HAL_ADC_STATE_BUSY_INTERNAL); + + /* Manage settings impacting calibration */ + /* - Disable ADC mode auto power-off */ + /* - Disable ADC DMA transfer request during calibration */ + /* Note: Specificity of this STM32 series: Calibration factor is */ + /* available in data register and also transferred by DMA. */ + /* To not insert ADC calibration factor among ADC conversion data */ + /* in array variable, DMA transfer must be disabled during */ + /* calibration. */ + backup_setting_pwrr = READ_BIT(hadc->Instance->PWRR, ADC_PWRR_AUTOFF); + backup_setting_cfgr1 = READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG); + CLEAR_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG); + CLEAR_BIT(hadc->Instance->PWRR, ADC_PWRR_AUTOFF); + + /* Start ADC calibration */ + SET_BIT(hadc->Instance->CR, ADC_CR_ADCAL); + + /* Wait for calibration completion */ + while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL) + { + wait_loop_index++; + if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT) + { + /* Update ADC state machine to error */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_BUSY_INTERNAL, + HAL_ADC_STATE_ERROR_INTERNAL); + + __HAL_UNLOCK(hadc); + + return HAL_ERROR; + } + } + + /* Restore configuration after calibration */ + SET_BIT(hadc->Instance->CFGR1, backup_setting_cfgr1); + SET_BIT(hadc->Instance->PWRR, backup_setting_pwrr); + + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_BUSY_INTERNAL, + HAL_ADC_STATE_READY); + } + else + { + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + + /* Note: No need to update variable "tmp_hal_status" here: already set */ + /* to state "HAL_ERROR" by function disabling the ADC. */ + } + + __HAL_UNLOCK(hadc); + + return tmp_hal_status; +} + +/** + * @brief Get the calibration factor. + * @param hadc ADC handle. + * @retval Calibration value. + */ +uint32_t HAL_ADCEx_Calibration_GetValue(const ADC_HandleTypeDef *hadc) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Return the selected ADC calibration value */ + return ((hadc->Instance->CALFACT) & 0x0000007FU); +} + +/** + * @brief Set the calibration factor to overwrite automatic conversion result. + * ADC must be enabled and no conversion is ongoing. + * @param hadc ADC handle + * @param CalibrationFactor Calibration factor (coded on 7 bits maximum) + * @retval HAL state + */ +HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t CalibrationFactor) +{ + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + uint32_t tmp_adc_is_conversion_on_going_regular; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + assert_param(IS_ADC_CALFACT(CalibrationFactor)); + + __HAL_LOCK(hadc); + + /* Verification of hardware constraints before modifying the calibration */ + /* factors register: ADC must be enabled, no conversion on going. */ + tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); + + if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL) + && (tmp_adc_is_conversion_on_going_regular == 0UL) + ) + { + hadc->Instance->CALFACT &= ~ADC_CALFACT_CALFACT; + hadc->Instance->CALFACT |= CalibrationFactor; + } + else + { + /* Update ADC state machine */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + /* Update ADC error code */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + + /* Update ADC state machine to error */ + tmp_hal_status = HAL_ERROR; + } + + __HAL_UNLOCK(hadc); + + return tmp_hal_status; +} + +/** + * @brief Analog watchdog 2 callback in non-blocking mode. + * @param hadc ADC handle + * @retval None + */ +__weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADCEx_LevelOutOfWindow2Callback must be implemented in the user file. + */ +} + +/** + * @brief Analog watchdog 3 callback in non-blocking mode. + * @param hadc ADC handle + * @retval None + */ +__weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADCEx_LevelOutOfWindow3Callback must be implemented in the user file. + */ +} + + +/** + * @brief End Of Sampling callback in non-blocking mode. + * @param hadc ADC handle + * @retval None + */ +__weak void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADCEx_EndOfSamplingCallback must be implemented in the user file. + */ +} + +/** + * @brief ADC internal voltage regulator ready callback in non-blocking mode. + * @param hadc ADC handle + * @retval None + */ +__weak void HAL_ADCEx_LDOReadyCallback(ADC_HandleTypeDef *hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_ADCEx_LDOReadyCallback must be implemented in the user file. + */ +} + +/** + * @} + */ + +/** + * @brief Disable ADC voltage regulator. + * @note Disabling voltage regulator allows to save power. This operation can + * be carried out only when ADC is disabled. + * @note To enable again the voltage regulator, the user is expected to + * resort to HAL_ADC_Init() API. + * @param hadc ADC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc) +{ + HAL_StatusTypeDef tmp_hal_status; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Setting of this feature is conditioned to ADC state: ADC must be ADC disabled */ + if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) + { + LL_ADC_DisableInternalRegulator(hadc->Instance); + tmp_hal_status = HAL_OK; + } + else + { + tmp_hal_status = HAL_ERROR; + } + + return tmp_hal_status; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_ADC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_comp.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_comp.c new file mode 100644 index 0000000000..03580ed09e --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_comp.c @@ -0,0 +1,1062 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_comp.c + * @author MCD Application Team + * @brief COMP HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the COMP peripheral: + * + Initialization and de-initialization functions + * + Peripheral control functions + * + Peripheral state functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### COMP Peripheral features ##### + ============================================================================== + + [..] + The STM32WBAxx device family integrates two analog comparators instances: + COMP1, COMP2. + (#) Comparators input minus (inverting input) and input plus (non inverting input) + can be set to internal references or to GPIO pins + (refer to GPIO list in reference manual). + + (#) Comparators output level is available using HAL_COMP_GetOutputLevel() + and can be redirected to other peripherals: GPIO pins (in mode + alternate functions for comparator), timers. + (refer to GPIO list in reference manual). + + (#) The comparators have interrupt capability through the EXTI controller + with wake-up from sleep and stop modes. + + (#) Pairs of comparators instances can be combined in window mode + (2 consecutive instances odd and even COMP and COMP). + + From the corresponding IRQ handler, the right interrupt source can be retrieved + using macro __HAL_COMP_COMPx_EXTI_GET_FLAG(). + + ##### How to use this driver ##### + ============================================================================== + [..] + This driver provides functions to configure and program the comparator instances + of STM32WBAxx devices. + + To use the comparator, perform the following steps: + + (#) Initialize the COMP low level resources by implementing the HAL_COMP_MspInit(): + (++) Configure the GPIO connected to comparator inputs plus and minus in analog mode + using HAL_GPIO_Init(). + (++) If needed, configure the GPIO connected to comparator output in alternate function mode + using HAL_GPIO_Init(). + (++) If required enable the COMP interrupt by configuring and enabling EXTI line in Interrupt mode and + selecting the desired sensitivity level using HAL_GPIO_Init() function. After that enable the comparator + interrupt vector using HAL_NVIC_EnableIRQ() function. + + (#) Configure the comparator using HAL_COMP_Init() function: + (++) Select the input minus (inverting input) + (++) Select the input plus (non-inverting input) + (++) Select the hysteresis + (++) Select the blanking source + (++) Select the output polarity + (++) Select the power mode + (++) Select the window mode + + -@@- HAL_COMP_Init() calls internally __HAL_RCC_SYSCFG_CLK_ENABLE() + to enable internal control clock of the comparators. + However, this is a legacy strategy. In future STM32 families, + COMP clock enable must be implemented by user in "HAL_COMP_MspInit()". + Therefore, for compatibility anticipation, it is recommended to + implement __HAL_RCC_SYSCFG_CLK_ENABLE() in "HAL_COMP_MspInit()". + + (#) Reconfiguration on-the-fly of comparator can be done by calling again + function HAL_COMP_Init() with new input structure parameters values. + + (#) Enable the comparator using HAL_COMP_Start() function. + + (#) Use HAL_COMP_TriggerCallback() or HAL_COMP_GetOutputLevel() functions + to manage comparator outputs (events and output level). + + (#) Disable the comparator using HAL_COMP_Stop() function. + + (#) De-initialize the comparator using HAL_COMP_DeInit() function. + + (#) For safety purpose, comparator configuration can be locked using HAL_COMP_Lock() function. + The only way to unlock the comparator is a device hardware reset. + + *** Callback registration *** + ============================================= + [..] + + The compilation flag USE_HAL_COMP_REGISTER_CALLBACKS, when set to 1, + allows the user to configure dynamically the driver callbacks. + Use Functions HAL_COMP_RegisterCallback() + to register an interrupt callback. + [..] + + Function HAL_COMP_RegisterCallback() allows to register following callbacks: + (+) TriggerCallback : callback for COMP trigger. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + [..] + + Use function HAL_COMP_UnRegisterCallback to reset a callback to the default + weak function. + [..] + + HAL_COMP_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) TriggerCallback : callback for COMP trigger. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + [..] + + By default, after the HAL_COMP_Init() and when the state is HAL_COMP_STATE_RESET + all callbacks are set to the corresponding weak functions: + example HAL_COMP_TriggerCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak functions in the HAL_COMP_Init()/ HAL_COMP_DeInit() only when + these callbacks are null (not registered beforehand). + [..] + + If MspInit or MspDeInit are not null, the HAL_COMP_Init()/ HAL_COMP_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + [..] + + Callbacks can be registered/unregistered in HAL_COMP_STATE_READY state only. + Exception done MspInit/MspDeInit functions that can be registered/unregistered + in HAL_COMP_STATE_READY or HAL_COMP_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + [..] + + Then, the user first registers the MspInit/MspDeInit user callbacks + using HAL_COMP_RegisterCallback() before calling HAL_COMP_DeInit() + or HAL_COMP_Init() function. + [..] + + When the compilation flag USE_HAL_COMP_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +#ifdef HAL_COMP_MODULE_ENABLED + +#if defined (COMP1) || defined (COMP2) + +/** @defgroup COMP COMP + * @brief COMP HAL module driver + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup COMP_Private_Constants + * @{ + */ + +/* Delay for COMP startup time. */ +/* Note: Delay required to reach propagation delay specification. */ +/* Literal set to maximum value (refer to device datasheet, */ +/* parameter "tSTART"). */ +/* Unit: us */ +#define COMP_DELAY_STARTUP_US (80UL) /*!< Delay for COMP startup time */ + +/* Delay for COMP voltage scaler stabilization time. */ +/* Literal set to maximum value (refer to device datasheet, */ +/* parameter "tSTART_SCALER"). */ +/* Unit: us */ +#define COMP_DELAY_VOLTAGE_SCALER_STAB_US (200UL) /*!< Delay for COMP voltage scaler stabilization time */ + +#define COMP_OUTPUT_LEVEL_BITOFFSET_POS (30UL) + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup COMP_Exported_Functions COMP Exported Functions + * @{ + */ + +/** @defgroup COMP_Exported_Functions_Group1 Initialization/de-initialization functions + * @brief Initialization and de-initialization functions. + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions to initialize and de-initialize comparators + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the COMP according to the specified + * parameters in the COMP_InitTypeDef and initialize the associated handle. + * @note If the selected comparator is locked, initialization can't be performed. + * To unlock the configuration, perform a system reset. + * @param hcomp COMP handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) +{ + uint32_t tmp_csr; + uint32_t exti_line; + uint32_t comp_voltage_scaler_initialized; /* Value "0" if comparator voltage scaler is not initialized */ + __IO uint32_t wait_loop_index = 0UL; + HAL_StatusTypeDef status = HAL_OK; + + /* Check the COMP handle allocation and lock status */ + if (hcomp == NULL) + { + status = HAL_ERROR; + } + else if (__HAL_COMP_IS_LOCKED(hcomp)) + { + status = HAL_ERROR; + } + else + { + /* Check the parameters */ + assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); + assert_param(IS_COMP_INPUT_PLUS(hcomp->Instance, hcomp->Init.InputPlus)); + assert_param(IS_COMP_INPUT_MINUS(hcomp->Instance, hcomp->Init.InputMinus)); + assert_param(IS_COMP_OUTPUTPOL(hcomp->Init.OutputPol)); + assert_param(IS_COMP_POWERMODE(hcomp->Init.Mode)); + assert_param(IS_COMP_HYSTERESIS(hcomp->Init.Hysteresis)); + assert_param(IS_COMP_BLANKINGSRC_INSTANCE(hcomp->Instance, hcomp->Init.BlankingSrce)); + assert_param(IS_COMP_TRIGGERMODE(hcomp->Init.TriggerMode)); + + assert_param(IS_COMP_WINDOWMODE(hcomp->Instance, hcomp->Init.WindowMode)); + if (hcomp->Init.WindowMode != COMP_WINDOWMODE_DISABLE) + { + assert_param(IS_COMP_WINDOWOUTPUT(hcomp->Init.WindowOutput)); + } + + + if (hcomp->State == HAL_COMP_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hcomp->Lock = HAL_UNLOCKED; + + /* Set COMP error code to none */ + COMP_CLEAR_ERRORCODE(hcomp); + +#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1) + /* Init the COMP Callback settings */ + hcomp->TriggerCallback = HAL_COMP_TriggerCallback; /* Legacy weak callback */ + + if (hcomp->MspInitCallback == NULL) + { + hcomp->MspInitCallback = HAL_COMP_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware */ + /* Note: Internal control clock of the comparators must */ + /* be enabled in "HAL_COMP_MspInit()" */ + /* using "__HAL_RCC_SYSCFG_CLK_ENABLE()". */ + hcomp->MspInitCallback(hcomp); +#else + /* Init the low level hardware */ + /* Note: Internal control clock of the comparators must */ + /* be enabled in "HAL_COMP_MspInit()" */ + /* using "__HAL_RCC_SYSCFG_CLK_ENABLE()". */ + HAL_COMP_MspInit(hcomp); +#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */ + } + + /* Memorize voltage scaler state before initialization */ + comp_voltage_scaler_initialized = READ_BIT(hcomp->Instance->CSR, (COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)); + + /* Set COMP parameters */ + tmp_csr = (hcomp->Init.InputMinus + | hcomp->Init.InputPlus + | hcomp->Init.BlankingSrce + | hcomp->Init.Hysteresis + | hcomp->Init.OutputPol + | hcomp->Init.Mode + ); + + /* Set parameters in COMP register */ + /* Note: Update all bits except read-only, lock and enable bits */ + MODIFY_REG(hcomp->Instance->CSR, + COMP_CSR_PWRMODE | COMP_CSR_INMSEL | COMP_CSR_INPSEL | + COMP_CSR_WINMODE | COMP_CSR_POLARITY | COMP_CSR_HYST | + COMP_CSR_BLANKSEL, + tmp_csr + ); + + + /* Set window mode */ + /* Note: Window mode bit is located into 1 out of the 2 pairs of COMP */ + /* instances. Therefore, this function can update another COMP */ + /* instance that the one currently selected. */ + + if (hcomp->Init.WindowMode == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON) + { + CLEAR_BIT(COMP12_COMMON->CSR_ODD, COMP_CSR_WINMODE); + SET_BIT(COMP12_COMMON->CSR_EVEN, COMP_CSR_WINMODE); + } + else if (hcomp->Init.WindowMode == COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON) + { + SET_BIT(COMP12_COMMON->CSR_ODD, COMP_CSR_WINMODE); + CLEAR_BIT(COMP12_COMMON->CSR_EVEN, COMP_CSR_WINMODE); + } + else + { + CLEAR_BIT(COMP12_COMMON->CSR_ODD, COMP_CSR_WINMODE); + CLEAR_BIT(COMP12_COMMON->CSR_EVEN, COMP_CSR_WINMODE); + } + + /* Set window mode output */ + /* Note: Window mode mode output can also be used when window mode */ + /* is disabled, to use comparators in independent mode with their */ + /* output connected through exclusive-or circuitry. */ + switch (hcomp->Init.WindowOutput) + { + case COMP_WINDOWOUTPUT_COMP1: + SET_BIT(COMP12_COMMON->CSR_ODD, COMP_CSR_WINOUT); + CLEAR_BIT(COMP12_COMMON->CSR_EVEN, COMP_CSR_WINOUT); + break; + + case COMP_WINDOWOUTPUT_COMP2: + CLEAR_BIT(COMP12_COMMON->CSR_ODD, COMP_CSR_WINOUT); + SET_BIT(COMP12_COMMON->CSR_EVEN, COMP_CSR_WINOUT); + break; + + case COMP_WINDOWOUTPUT_BOTH: + SET_BIT(COMP12_COMMON->CSR_ODD, COMP_CSR_WINOUT); + SET_BIT(COMP12_COMMON->CSR_EVEN, COMP_CSR_WINOUT); + break; + + default: /* COMP_WINDOWOUTPUT_EACH_COMP */ + CLEAR_BIT(COMP12_COMMON->CSR_ODD, COMP_CSR_WINOUT); + CLEAR_BIT(COMP12_COMMON->CSR_EVEN, COMP_CSR_WINOUT); + break; + } + + + /* Delay for COMP scaler bridge voltage stabilization */ + /* Apply the delay if voltage scaler bridge is required and not already enabled */ + if ((READ_BIT(hcomp->Instance->CSR, (COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)) != 0UL) && + (comp_voltage_scaler_initialized == 0UL)) + { + /* Wait loop initialization and execution */ + /* Note: Variable divided by 2 to compensate partially */ + /* CPU processing cycles, scaling in us split to not */ + /* exceed 32 bits register capacity and handle low frequency. */ + wait_loop_index = ((COMP_DELAY_VOLTAGE_SCALER_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); + while (wait_loop_index != 0UL) + { + wait_loop_index--; + } + } + + /* Get the EXTI line corresponding to the selected COMP instance */ + exti_line = COMP_GET_EXTI_LINE(hcomp->Instance); + + /* Manage EXTI settings */ + if ((hcomp->Init.TriggerMode & (COMP_EXTI_IT | COMP_EXTI_EVENT)) != 0UL) + { + /* Configure EXTI rising edge */ + if ((hcomp->Init.TriggerMode & COMP_EXTI_RISING) != 0UL) + { + LL_EXTI_EnableRisingTrig_0_31(exti_line); + } + else + { + LL_EXTI_DisableRisingTrig_0_31(exti_line); + } + + /* Configure EXTI falling edge */ + if ((hcomp->Init.TriggerMode & COMP_EXTI_FALLING) != 0UL) + { + LL_EXTI_EnableFallingTrig_0_31(exti_line); + } + else + { + LL_EXTI_DisableFallingTrig_0_31(exti_line); + } + + /* Clear COMP EXTI pending bit (if any) */ + LL_EXTI_ClearRisingFlag_0_31(exti_line); + LL_EXTI_ClearFallingFlag_0_31(exti_line); + + /* Configure EXTI event mode */ + if ((hcomp->Init.TriggerMode & COMP_EXTI_EVENT) != 0UL) + { + LL_EXTI_EnableEvent_0_31(exti_line); + } + else + { + LL_EXTI_DisableEvent_0_31(exti_line); + } + + /* Configure EXTI interrupt mode */ + if ((hcomp->Init.TriggerMode & COMP_EXTI_IT) != 0UL) + { + LL_EXTI_EnableIT_0_31(exti_line); + } + else + { + LL_EXTI_DisableIT_0_31(exti_line); + } + } + else + { + /* Disable EXTI event mode */ + LL_EXTI_DisableEvent_0_31(exti_line); + + /* Disable EXTI interrupt mode */ + LL_EXTI_DisableIT_0_31(exti_line); + } + + /* Set HAL COMP handle state */ + /* Note: Transition from state reset to state ready, */ + /* otherwise (coming from state ready or busy) no state update. */ + if (hcomp->State == HAL_COMP_STATE_RESET) + { + hcomp->State = HAL_COMP_STATE_READY; + } + } + + return status; +} + +/** + * @brief DeInitialize the COMP peripheral. + * @note Deinitialization cannot be performed if the COMP configuration is locked. + * To unlock the configuration, perform a system reset. + * @param hcomp COMP handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the COMP handle allocation and lock status */ + if (hcomp == NULL) + { + status = HAL_ERROR; + } + else if (__HAL_COMP_IS_LOCKED(hcomp)) + { + status = HAL_ERROR; + } + else + { + /* Check the parameter */ + assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); + + /* Set COMP_CSR register to reset value */ + WRITE_REG(hcomp->Instance->CSR, 0x00000000UL); + +#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1) + if (hcomp->MspDeInitCallback == NULL) + { + hcomp->MspDeInitCallback = HAL_COMP_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware: GPIO, RCC clock, NVIC */ + hcomp->MspDeInitCallback(hcomp); +#else + /* DeInit the low level hardware: GPIO, RCC clock, NVIC */ + HAL_COMP_MspDeInit(hcomp); +#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */ + + /* Set HAL COMP handle state */ + hcomp->State = HAL_COMP_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hcomp); + } + + return status; +} + +/** + * @brief Initialize the COMP MSP. + * @param hcomp COMP handle + * @retval None + */ +__weak void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcomp); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_COMP_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitialize the COMP MSP. + * @param hcomp COMP handle + * @retval None + */ +__weak void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcomp); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_COMP_MspDeInit could be implemented in the user file + */ +} + +#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User COMP Callback + * To be used instead of the weak predefined callback + * @param hcomp Pointer to a COMP_HandleTypeDef structure that contains + * the configuration information for the specified COMP. + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_COMP_TRIGGER_CB_ID Trigger callback ID + * @arg @ref HAL_COMP_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_COMP_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID, + pCOMP_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (HAL_COMP_STATE_READY == hcomp->State) + { + switch (CallbackID) + { + case HAL_COMP_TRIGGER_CB_ID : + hcomp->TriggerCallback = pCallback; + break; + + case HAL_COMP_MSPINIT_CB_ID : + hcomp->MspInitCallback = pCallback; + break; + + case HAL_COMP_MSPDEINIT_CB_ID : + hcomp->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_COMP_STATE_RESET == hcomp->State) + { + switch (CallbackID) + { + case HAL_COMP_MSPINIT_CB_ID : + hcomp->MspInitCallback = pCallback; + break; + + case HAL_COMP_MSPDEINIT_CB_ID : + hcomp->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister a COMP Callback + * COMP callback is redirected to the weak predefined callback + * @param hcomp Pointer to a COMP_HandleTypeDef structure that contains + * the configuration information for the specified COMP. + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_COMP_TRIGGER_CB_ID Trigger callback ID + * @arg @ref HAL_COMP_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_COMP_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_COMP_UnRegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (HAL_COMP_STATE_READY == hcomp->State) + { + switch (CallbackID) + { + case HAL_COMP_TRIGGER_CB_ID : + hcomp->TriggerCallback = HAL_COMP_TriggerCallback; /* Legacy weak callback */ + break; + + case HAL_COMP_MSPINIT_CB_ID : + hcomp->MspInitCallback = HAL_COMP_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_COMP_MSPDEINIT_CB_ID : + hcomp->MspDeInitCallback = HAL_COMP_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_COMP_STATE_RESET == hcomp->State) + { + switch (CallbackID) + { + case HAL_COMP_MSPINIT_CB_ID : + hcomp->MspInitCallback = HAL_COMP_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_COMP_MSPDEINIT_CB_ID : + hcomp->MspDeInitCallback = HAL_COMP_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup COMP_Exported_Functions_Group2 Start-Stop operation functions + * @brief Start-Stop operation functions. + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Start a comparator instance. + (+) Stop a comparator instance. + +@endverbatim + * @{ + */ + +/** + * @brief Start the comparator. + * @param hcomp COMP handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp) +{ + __IO uint32_t wait_loop_index = 0UL; + HAL_StatusTypeDef status = HAL_OK; + + /* Check the COMP handle allocation and lock status */ + if (hcomp == NULL) + { + status = HAL_ERROR; + } + else if (__HAL_COMP_IS_LOCKED(hcomp)) + { + status = HAL_ERROR; + } + else + { + /* Check the parameter */ + assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); + + if (hcomp->State == HAL_COMP_STATE_READY) + { + /* Enable the selected comparator */ + SET_BIT(hcomp->Instance->CSR, COMP_CSR_EN); + + /* Set HAL COMP handle state */ + hcomp->State = HAL_COMP_STATE_BUSY; + + /* Delay for COMP startup time */ + /* Wait loop initialization and execution */ + /* Note: Variable divided by 2 to compensate partially */ + /* CPU processing cycles, scaling in us split to not */ + /* exceed 32 bits register capacity and handle low frequency. */ + wait_loop_index = ((COMP_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); + while (wait_loop_index != 0UL) + { + wait_loop_index--; + } + } + else + { + status = HAL_ERROR; + } + } + + return status; +} + +/** + * @brief Stop the comparator. + * @param hcomp COMP handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the COMP handle allocation and lock status */ + if (hcomp == NULL) + { + status = HAL_ERROR; + } + else if (__HAL_COMP_IS_LOCKED(hcomp)) + { + status = HAL_ERROR; + } + else + { + /* Check the parameter */ + assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); + + /* Check compliant states: HAL_COMP_STATE_READY or HAL_COMP_STATE_BUSY */ + /* (all states except HAL_COMP_STATE_RESET and except locked status. */ + if (hcomp->State != HAL_COMP_STATE_RESET) + { + /* Disable the selected comparator */ + CLEAR_BIT(hcomp->Instance->CSR, COMP_CSR_EN); + + /* Set HAL COMP handle state */ + hcomp->State = HAL_COMP_STATE_READY; + } + else + { + status = HAL_ERROR; + } + } + + return status; +} + +/** + * @brief Comparator IRQ handler. + * @param hcomp COMP handle + * @retval None + */ +void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp) +{ + /* Get the EXTI line corresponding to the selected COMP instance */ + uint32_t exti_line = COMP_GET_EXTI_LINE(hcomp->Instance); + uint32_t comparator_window_mode; + + comparator_window_mode = READ_BIT(COMP12_COMMON->CSR_ODD, COMP_CSR_WINMODE); + comparator_window_mode |= READ_BIT(COMP12_COMMON->CSR_EVEN, COMP_CSR_WINMODE); + + /* Check COMP EXTI flag */ + if (LL_EXTI_IsActiveRisingFlag_0_31(exti_line) != 0UL) + { + /* Check whether comparator is in independent or window mode */ + if (comparator_window_mode != 0UL) + { + /* Clear COMP EXTI line pending bit of the pair of comparators */ + /* in window mode. */ + /* Note: Pair of comparators in window mode can both trig IRQ when */ + /* input voltage is changing from "out of window" area */ + /* (low or high ) to the other "out of window" area (high or low).*/ + /* Both flags must be cleared to call comparator trigger */ + /* callback is called once. */ + LL_EXTI_ClearRisingFlag_0_31((COMP_EXTI_LINE_COMP1 | COMP_EXTI_LINE_COMP2)); + } + else + { + /* Clear COMP EXTI line pending bit */ + LL_EXTI_ClearRisingFlag_0_31(exti_line); + } + + /* COMP trigger user callback */ +#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1) + hcomp->TriggerCallback(hcomp); +#else + HAL_COMP_TriggerCallback(hcomp); +#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */ + } + else if (LL_EXTI_IsActiveFallingFlag_0_31(exti_line) != 0UL) + { + /* Check whether comparator is in independent or window mode */ + if (comparator_window_mode != 0UL) + { + /* Clear COMP EXTI line pending bit of the pair of comparators */ + /* in window mode. */ + /* Note: Pair of comparators in window mode can both trig IRQ when */ + /* input voltage is changing from "out of window" area */ + /* (low or high ) to the other "out of window" area (high or low).*/ + /* Both flags must be cleared to call comparator trigger */ + /* callback is called once. */ + LL_EXTI_ClearFallingFlag_0_31((COMP_EXTI_LINE_COMP1 | COMP_EXTI_LINE_COMP2)); + } + else + { + /* Clear COMP EXTI line pending bit */ + LL_EXTI_ClearFallingFlag_0_31(exti_line); + } + + /* COMP trigger callback */ +#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1) + hcomp->TriggerCallback(hcomp); +#else + HAL_COMP_TriggerCallback(hcomp); +#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */ + } + else + { + /* nothing to do */ + } +} + +/** + * @} + */ + +/** @defgroup COMP_Exported_Functions_Group3 Peripheral Control functions + * @brief Management functions. + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the comparators. + +@endverbatim + * @{ + */ + +/** + * @brief Lock the selected comparator configuration. + * @note A system reset is required to unlock the comparator configuration. + * @note Locking the comparator from reset state is possible + * if __HAL_RCC_SYSCFG_CLK_ENABLE() is being called before. + * @param hcomp COMP handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the COMP handle allocation and lock status */ + if (hcomp == NULL) + { + status = HAL_ERROR; + } + else if (__HAL_COMP_IS_LOCKED(hcomp)) + { + status = HAL_ERROR; + } + else + { + /* Check the parameter */ + assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); + + /* Set HAL COMP handle state */ + switch (hcomp->State) + { + case HAL_COMP_STATE_RESET: + hcomp->State = HAL_COMP_STATE_RESET_LOCKED; + break; + case HAL_COMP_STATE_READY: + hcomp->State = HAL_COMP_STATE_READY_LOCKED; + break; + default: /* HAL_COMP_STATE_BUSY */ + hcomp->State = HAL_COMP_STATE_BUSY_LOCKED; + break; + } + + /* Set the lock bit corresponding to selected comparator */ + __HAL_COMP_LOCK(hcomp); + } + + return status; +} + +/** + * @brief Return the output level (high or low) of the selected comparator. + * The output level depends on the selected polarity. + * If the polarity is not inverted: + * - Comparator output is low when the input plus is at a lower + * voltage than the input minus + * - Comparator output is high when the input plus is at a higher + * voltage than the input minus + * If the polarity is inverted: + * - Comparator output is high when the input plus is at a lower + * voltage than the input minus + * - Comparator output is low when the input plus is at a higher + * voltage than the input minus + * @param hcomp COMP handle + * @retval Returns the selected comparator output level: + * @arg COMP_OUTPUT_LEVEL_LOW + * @arg COMP_OUTPUT_LEVEL_HIGH + * + */ +uint32_t HAL_COMP_GetOutputLevel(const COMP_HandleTypeDef *hcomp) +{ + /* Check the parameter */ + assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); + + return (uint32_t)(READ_BIT(hcomp->Instance->CSR, COMP_CSR_VALUE) + >> COMP_OUTPUT_LEVEL_BITOFFSET_POS); +} + +/** + * @brief Comparator trigger callback. + * @param hcomp COMP handle + * @retval None + */ +__weak void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcomp); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_COMP_TriggerCallback should be implemented in the user file + */ +} + + +/** + * @} + */ + +/** @defgroup COMP_Exported_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions. + * +@verbatim + =============================================================================== + ##### Peripheral State functions ##### + =============================================================================== + [..] + This subsection permit to get in run-time the status of the peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Return the COMP handle state. + * @param hcomp COMP handle + * @retval HAL state + */ +HAL_COMP_StateTypeDef HAL_COMP_GetState(const COMP_HandleTypeDef *hcomp) +{ + /* Check the COMP handle allocation */ + if (hcomp == NULL) + { + return HAL_COMP_STATE_RESET; + } + + /* Check the parameter */ + assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); + + /* Return HAL COMP handle state */ + return hcomp->State; +} + +/** + * @brief Return the COMP error code. + * @param hcomp COMP handle + * @retval COMP error code + */ +uint32_t HAL_COMP_GetError(const COMP_HandleTypeDef *hcomp) +{ + /* Check the parameters */ + assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); + + return hcomp->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* COMP1 || COMP2 */ + +#endif /* HAL_COMP_MODULE_ENABLED */ + +/** + * @} + */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_cortex.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_cortex.c new file mode 100644 index 0000000000..d0b3a681e4 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_cortex.c @@ -0,0 +1,702 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_cortex.c + * @author MCD Application Team + * @brief CORTEX HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the CORTEX: + * + Initialization and Configuration functions + * + Peripheral Control functions + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + + [..] + *** How to configure Interrupts using CORTEX HAL driver *** + =========================================================== + [..] + This section provides functions allowing to configure the NVIC interrupts (IRQ). + The Cortex-M33 exceptions are managed by CMSIS functions. + + (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function. + (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority(). + (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ(). + + -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible. + The pending IRQ priority will be managed only by the sub priority. + + -@- IRQ priority order (sorted by highest to lowest priority): + (+@) Lowest pre-emption priority + (+@) Lowest sub priority + (+@) Lowest hardware priority (IRQ number) + + [..] + *** How to configure SysTick using CORTEX HAL driver *** + ======================================================== + [..] + Setup SysTick Timer for time base. + + (+) The SysTick clock source shall be configured with HAL_SYSTICK_CLKSourceConfig(). + + (+) The SysTick IRQ priority shall be configured with HAL_NVIC_SetPriority(SysTick_IRQn,...). + The HAL_NVIC_SetPriority() calls the CMSIS NVIC_SetPriority() function. + + (+) The HAL_SYSTICK_Config() function: + (++) Configures the SysTick Reload register with the value passed as function parameter. + (++) Resets the SysTick Counter register. + (++) Enables the SysTick Interrupt. + (++) Starts the SysTick Counter. + + (+) To adjust the SysTick time base, use the following formula: + + Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) + (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function + (++) Reload Value should not exceed 0xFFFFFF + + (+) In case the HAL time base is the SysTick Timer, the HAL time base configuration must be completed + by calling the HAL_InitTick() function. + + @endverbatim + ****************************************************************************** + + The table below gives the allowed values of the pre-emption priority and subpriority according + to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function. + + ========================================================================================================================== + NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description + ========================================================================================================================== + NVIC_PRIORITYGROUP_0 | 0 | 0-15 | 0 bit for pre-emption priority + | | | 4 bits for subpriority + -------------------------------------------------------------------------------------------------------------------------- + NVIC_PRIORITYGROUP_1 | 0-1 | 0-7 | 1 bit for pre-emption priority + | | | 3 bits for subpriority + -------------------------------------------------------------------------------------------------------------------------- + NVIC_PRIORITYGROUP_2 | 0-3 | 0-3 | 2 bits for pre-emption priority + | | | 2 bits for subpriority + -------------------------------------------------------------------------------------------------------------------------- + NVIC_PRIORITYGROUP_3 | 0-7 | 0-1 | 3 bits for pre-emption priority + | | | 1 bit for subpriority + -------------------------------------------------------------------------------------------------------------------------- + NVIC_PRIORITYGROUP_4 | 0-15 | 0 | 4 bits for pre-emption priority + | | | 0 bit for subpriority + ========================================================================================================================== + + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @addtogroup CORTEX + * @{ + */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +static void MPU_ConfigRegion(MPU_Type *MPUx, MPU_Region_InitTypeDef *MPU_RegionInit); +static void MPU_ConfigMemoryAttributes(MPU_Type *MPUx, MPU_Attributes_InitTypeDef *MPU_AttributesInit); +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup CORTEX_Exported_Functions + * @{ + */ + + +/** @addtogroup CORTEX_Exported_Functions_Group1 + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and Configuration functions ##### + ============================================================================== + [..] + This section provides the CORTEX HAL driver functions allowing to configure Interrupts + SysTick functionalities + +@endverbatim + * @{ + */ + + +/** + * @brief Set the priority grouping field (pre-emption priority and subpriority) + * using the required unlock sequence. + * @param PriorityGroup: The priority grouping bits length. + * This parameter can be one of the following values: + * @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority, + * 4 bits for subpriority + * @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority, + * 3 bits for subpriority + * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority, + * 2 bits for subpriority + * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority, + * 1 bit for subpriority + * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority, + * 0 bit for subpriority + * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. + * The pending IRQ priority will be managed only by the subpriority. + * @retval None + */ +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + + /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ + NVIC_SetPriorityGrouping(PriorityGroup); +} + +/** + * @brief Set the priority of an interrupt. + * @param IRQn: External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbaxxxx.h)) + * @param PreemptPriority: The pre-emption priority for the IRQn channel. + * This parameter can be a value between 0 and 15 + * A lower priority value indicates a higher priority + * @param SubPriority: the subpriority level for the IRQ channel. + * This parameter can be a value between 0 and 15 + * A lower priority value indicates a higher priority. + * @retval None + */ +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t prioritygroup; + + prioritygroup = (NVIC_GetPriorityGrouping() & 0x7U); + + /* Check the parameters */ + assert_param(IS_NVIC_SUB_PRIORITY(SubPriority, prioritygroup)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority, prioritygroup)); + + NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); +} + +/** + * @brief Enable a device specific interrupt in the NVIC interrupt controller. + * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() + * function should be called before. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbaxxxx.h)) + * @retval None + */ +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Enable interrupt */ + NVIC_EnableIRQ(IRQn); +} + +/** + * @brief Disable a device specific interrupt in the NVIC interrupt controller. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbaxxxx.h)) + * @retval None + */ +void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Disable interrupt */ + NVIC_DisableIRQ(IRQn); +} + +/** + * @brief Initiate a system reset request to reset the MCU. + * @retval None + */ +void HAL_NVIC_SystemReset(void) +{ + /* System Reset */ + NVIC_SystemReset(); +} + +/** + * @brief Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick): + * Counter is in free running mode to generate periodic interrupts. + * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. + * @retval status: - 0 Function succeeded. + * - 1 Function failed. + */ +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) +{ + if ((TicksNumb - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + /* Reload value impossible */ + return (1UL); + } + + /* Set reload register */ + WRITE_REG(SysTick->LOAD, (uint32_t)(TicksNumb - 1UL)); + + /* Load the SysTick Counter Value */ + WRITE_REG(SysTick->VAL, 0UL); + + /* Enable SysTick IRQ and SysTick Timer */ + SET_BIT(SysTick->CTRL, (SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk)); + + /* Function successful */ + return (0UL); +} +/** + * @} + */ + +/** @addtogroup CORTEX_Exported_Functions_Group2 + * @brief Cortex control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control the CORTEX + (NVIC, SYSTICK, MPU) functionalities. + + +@endverbatim + * @{ + */ + +/** + * @brief Get the priority grouping field from the NVIC Interrupt Controller. + * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field) + */ +uint32_t HAL_NVIC_GetPriorityGrouping(void) +{ + /* Get the PRIGROUP[10:8] field value */ + return NVIC_GetPriorityGrouping(); +} + +/** + * @brief Get the priority of an interrupt. + * @param IRQn: External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbaxxxx.h)) + * @param PriorityGroup: the priority grouping bits length. + * This parameter can be one of the following values: + * @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority, + * 4 bits for subpriority + * @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority, + * 3 bits for subpriority + * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority, + * 2 bits for subpriority + * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority, + * 1 bit for subpriority + * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority, + * 0 bit for subpriority + * @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0). + * @param pSubPriority: Pointer on the Subpriority value (starting from 0). + * @retval None + */ +void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + /* Get priority for Cortex-M system or device specific interrupts */ + NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority); +} + +/** + * @brief Set Pending bit of an external interrupt. + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbaxxxx.h)) + * @retval None + */ +void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + /* Set interrupt pending */ + NVIC_SetPendingIRQ(IRQn); +} + +/** + * @brief Get Pending Interrupt (read the pending register in the NVIC + * and return the pending bit for the specified interrupt). + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbaxxxx.h)) + * @retval status: - 0 Interrupt status is not pending. + * - 1 Interrupt status is pending. + */ +uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + /* Return 1 if pending else 0 */ + return NVIC_GetPendingIRQ(IRQn); +} + +/** + * @brief Clear the pending bit of an external interrupt. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbaxxxx.h)) + * @retval None + */ +void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + /* Clear pending interrupt */ + NVIC_ClearPendingIRQ(IRQn); +} + +/** + * @brief Get active interrupt (read the active register in NVIC and return the active bit). + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbaxxxx.h)) + * @retval status: - 0 Interrupt status is not pending. + * - 1 Interrupt status is pending. + */ +uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) +{ + /* Return 1 if active else 0 */ + return NVIC_GetActive(IRQn); +} + +/** + * @brief Configure the SysTick clock source. + * @param CLKSource: specifies the SysTick clock source. + * This parameter can be one of the following values: + * @arg SYSTICK_CLKSOURCE_LSI: LSI clock selected as SysTick clock source. + * @arg SYSTICK_CLKSOURCE_LSE: LSE clock selected as SysTick clock source. + * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. + * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. + * @retval None + */ +void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) +{ + /* Check the parameters */ + assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource)); + switch (CLKSource) + { + /* Select HCLK as Systick clock source */ + case SYSTICK_CLKSOURCE_HCLK: + SET_BIT(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk); + break; + /* Select HCLK_DIV8 as Systick clock source */ + case SYSTICK_CLKSOURCE_HCLK_DIV8: + CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk); + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_SYSTICKSEL, (0x00000000U)); + break; + /* Select LSI as Systick clock source */ + case SYSTICK_CLKSOURCE_LSI: + CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk); + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_SYSTICKSEL, RCC_CCIPR1_SYSTICKSEL_0); + break; + /* Select LSE as Systick clock source */ + case SYSTICK_CLKSOURCE_LSE: + CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk); + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_SYSTICKSEL, RCC_CCIPR1_SYSTICKSEL_1); + break; + default: + /* Nothing to do */ + break; + } +} + +/** + * @brief Get the SysTick clock source configuration. + * @retval SysTick clock source that can be one of the following values: + * @arg SYSTICK_CLKSOURCE_LSI: LSI clock selected as SysTick clock source. + * @arg SYSTICK_CLKSOURCE_LSE: LSE clock selected as SysTick clock source. + * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. + * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. + */ +uint32_t HAL_SYSTICK_GetCLKSourceConfig(void) +{ + uint32_t systick_source; + + /* Read SysTick->CTRL register for internal or external clock source */ + if(READ_BIT(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk) != 0U) + { + /* Internal clock source */ + systick_source = SYSTICK_CLKSOURCE_HCLK; + } + else + { + /* External clock source, check the selected one in RCC */ + switch (__HAL_RCC_GET_SYSTICK_SOURCE()) + { + case RCC_SYSTICKCLKSOURCE_LSI: + systick_source = SYSTICK_CLKSOURCE_LSI; + break; + + case RCC_SYSTICKCLKSOURCE_LSE: + systick_source = SYSTICK_CLKSOURCE_LSE; + break; + + default: /* RCC_SYSTICKCLKSOURCE_HCLK_DIV8 */ + systick_source = SYSTICK_CLKSOURCE_HCLK_DIV8; + break; + } + } + return systick_source; +} + +/** + * @brief Handle SYSTICK interrupt request. + * @retval None + */ +void HAL_SYSTICK_IRQHandler(void) +{ + HAL_SYSTICK_Callback(); +} + +/** + * @brief SYSTICK callback. + * @retval None + */ +__weak void HAL_SYSTICK_Callback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SYSTICK_Callback could be implemented in the user file + */ +} + +/** + * @brief Enable the MPU. + * @param MPU_Control: Specifies the control mode of the MPU during hard fault, + * NMI, FAULTMASK and privileged accessto the default memory + * This parameter can be one of the following values: + * @arg MPU_HFNMI_PRIVDEF_NONE + * @arg MPU_HARDFAULT_NMI + * @arg MPU_PRIVILEGED_DEFAULT + * @arg MPU_HFNMI_PRIVDEF + * @retval None + */ +void HAL_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before enabling the MPU */ + + /* Enable the MPU */ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; + + /* Enable fault exceptions */ + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; + + /* Follow ARM recommendation with */ + /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */ + __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */ + __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Enable the non-secure MPU. + * @param MPU_Control: Specifies the control mode of the MPU during hard fault, + * NMI, FAULTMASK and privileged accessto the default memory + * This parameter can be one of the following values: + * @arg MPU_HFNMI_PRIVDEF_NONE + * @arg MPU_HARDFAULT_NMI + * @arg MPU_PRIVILEGED_DEFAULT + * @arg MPU_HFNMI_PRIVDEF + * @retval None + */ +void HAL_MPU_Enable_NS(uint32_t MPU_Control) +{ + __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before enabling the MPU */ + + /* Enable the MPU */ + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; + + /* Enable fault exceptions */ + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; + + /* Follow ARM recommendation with */ + /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */ + __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */ + __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */ +} +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @brief Disable the MPU. + * @retval None + */ +void HAL_MPU_Disable(void) +{ + __DMB(); /* Force any outstanding transfers to complete before disabling MPU */ + + /* Disable fault exceptions */ + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; + + /* Disable the MPU */ + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + + /* Follow ARM recommendation with */ + /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */ + __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */ + __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +void HAL_MPU_Disable_NS(void) +{ + __DMB(); /* Force any outstanding transfers to complete before disabling MPU */ + + /* Disable fault exceptions */ + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; + + /* Disable the MPU */ + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; + + /* Follow ARM recommendation with */ + /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */ + __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */ + __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */ +} +#endif /* __ARM_FEATURE_CMSE */ +/** + * @brief Initialize and configure the Region and the memory to be protected. + * @param MPU_RegionInit: Pointer to a MPU_Region_InitTypeDef structure that contains + * the initialization and configuration information. + * @retval None + */ +void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_RegionInit) +{ + MPU_ConfigRegion(MPU, MPU_RegionInit); +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Initialize and configure the Region and the memory to be protected for non-secure MPU. + * @param MPU_RegionInit: Pointer to a MPU_Region_InitTypeDef structure that contains + * the initialization and configuration information. + * @retval None + */ +void HAL_MPU_ConfigRegion_NS(MPU_Region_InitTypeDef *MPU_RegionInit) +{ + MPU_ConfigRegion(MPU_NS, MPU_RegionInit); +} +#endif /* __ARM_FEATURE_CMSE */ + +static void MPU_ConfigRegion(MPU_Type *MPUx, MPU_Region_InitTypeDef *MPU_RegionInit) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(MPU_RegionInit->Number)); + assert_param(IS_MPU_REGION_ENABLE(MPU_RegionInit->Enable)); + + /* Follow ARM recommendation with Data Memory Barrier prior to MPU configuration */ + __DMB(); + + /* Set the Region number */ + MPUx->RNR = MPU_RegionInit->Number; + + if (MPU_RegionInit->Enable != MPU_REGION_DISABLE) + { + /* Check the parameters */ + assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_RegionInit->DisableExec)); + assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_RegionInit->AccessPermission)); + assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_RegionInit->IsShareable)); + + MPUx->RBAR = (((uint32_t)MPU_RegionInit->BaseAddress & 0xFFFFFFE0U) | + ((uint32_t)MPU_RegionInit->IsShareable << MPU_RBAR_SH_Pos) | + ((uint32_t)MPU_RegionInit->AccessPermission << MPU_RBAR_AP_Pos) | + ((uint32_t)MPU_RegionInit->DisableExec << MPU_RBAR_XN_Pos)); + + MPUx->RLAR = (((uint32_t)MPU_RegionInit->LimitAddress & 0xFFFFFFE0U) | + ((uint32_t)MPU_RegionInit->AttributesIndex << MPU_RLAR_AttrIndx_Pos) | + ((uint32_t)MPU_RegionInit->Enable << MPU_RLAR_EN_Pos)); + } + else + { + MPUx->RBAR = 0U; + MPUx->RLAR = 0U; + } +} +/** + * @brief Initialize and configure the memory attributes. + * @param MPU_AttributesInit: Pointer to a MPU_Attributes_InitTypeDef structure that contains + * the initialization and configuration information. + * @retval None + */ +void HAL_MPU_ConfigMemoryAttributes(MPU_Attributes_InitTypeDef *MPU_AttributesInit) +{ + MPU_ConfigMemoryAttributes(MPU, MPU_AttributesInit); +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Initialize and configure the memory attributes for non-secure MPU. + * @param MPU_AttributesInit: Pointer to a MPU_Attributes_InitTypeDef structure that contains + * the initialization and configuration information. + * @retval None + */ +void HAL_MPU_ConfigMemoryAttributes_NS(MPU_Attributes_InitTypeDef *MPU_AttributesInit) +{ + MPU_ConfigMemoryAttributes(MPU_NS, MPU_AttributesInit); +} +#endif /* __ARM_FEATURE_CMSE */ + +static void MPU_ConfigMemoryAttributes(MPU_Type *MPUx, MPU_Attributes_InitTypeDef *MPU_AttributesInit) +{ + __IO uint32_t *mair; + uint32_t attr_values; + uint32_t attr_number; + + /* Check the parameters */ + assert_param(IS_MPU_ATTRIBUTES_NUMBER(MPU_AttributesInit->Number)); + /* No need to check Attributes value as all 0x0..0xFF possible */ + + /* Follow ARM recommendation with Data Memory Barrier prior to MPUx configuration */ + __DMB(); + + if (MPU_AttributesInit->Number < MPU_ATTRIBUTES_NUMBER4) + { + /* Program MPU_MAIR0 */ + mair = &(MPUx->MAIR0); + attr_number = MPU_AttributesInit->Number; + } + else + { + /* Program MPU_MAIR1 */ + mair = &(MPUx->MAIR1); + attr_number = (uint32_t)MPU_AttributesInit->Number - 4U; + } + + attr_values = *(mair); + attr_values &= ~(0xFFU << (attr_number * 8U)); + *(mair) = attr_values | ((uint32_t)MPU_AttributesInit->Attributes << (attr_number * 8U)); +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_CORTEX_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_crc.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_crc.c new file mode 100644 index 0000000000..f5c7641f69 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_crc.c @@ -0,0 +1,516 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_crc.c + * @author MCD Application Team + * @brief CRC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Cyclic Redundancy Check (CRC) peripheral: + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + Peripheral State functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + (+) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE(); + (+) Initialize CRC calculator + (++) specify generating polynomial (peripheral default or non-default one) + (++) specify initialization value (peripheral default or non-default one) + (++) specify input data format + (++) specify input or output data inversion mode if any + (+) Use HAL_CRC_Accumulate() function to compute the CRC value of the + input data buffer starting with the previously computed CRC as + initialization value + (+) Use HAL_CRC_Calculate() function to compute the CRC value of the + input data buffer starting with the defined initialization value + (default or non-default) to initiate CRC calculation + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @defgroup CRC CRC + * @brief CRC HAL module driver. + * @{ + */ + +#ifdef HAL_CRC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup CRC_Private_Functions CRC Private Functions + * @{ + */ +static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength); +static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup CRC_Exported_Functions CRC Exported Functions + * @{ + */ + +/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions. + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize the CRC according to the specified parameters + in the CRC_InitTypeDef and create the associated handle + (+) DeInitialize the CRC peripheral + (+) Initialize the CRC MSP (MCU Specific Package) + (+) DeInitialize the CRC MSP + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the CRC according to the specified + * parameters in the CRC_InitTypeDef and create the associated handle. + * @param hcrc CRC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) +{ + /* Check the CRC handle allocation */ + if (hcrc == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance)); + + if (hcrc->State == HAL_CRC_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hcrc->Lock = HAL_UNLOCKED; + /* Init the low level hardware */ + HAL_CRC_MspInit(hcrc); + } + + hcrc->State = HAL_CRC_STATE_BUSY; + + /* check whether or not non-default generating polynomial has been + * picked up by user */ + assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse)); + if (hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE) + { + /* initialize peripheral with default generating polynomial */ + WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY); + MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, CRC_POLYLENGTH_32B); + } + else + { + /* initialize CRC peripheral with generating polynomial defined by user */ + if (HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK) + { + return HAL_ERROR; + } + } + + /* check whether or not non-default CRC initial value has been + * picked up by user */ + assert_param(IS_DEFAULT_INIT_VALUE(hcrc->Init.DefaultInitValueUse)); + if (hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE) + { + WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE); + } + else + { + WRITE_REG(hcrc->Instance->INIT, hcrc->Init.InitValue); + } + + + /* set input data inversion mode */ + assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(hcrc->Init.InputDataInversionMode)); + MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode); + + /* set output data inversion mode */ + assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(hcrc->Init.OutputDataInversionMode)); + MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode); + + /* makes sure the input data format (bytes, halfwords or words stream) + * is properly specified by user */ + assert_param(IS_CRC_INPUTDATA_FORMAT(hcrc->InputDataFormat)); + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief DeInitialize the CRC peripheral. + * @param hcrc CRC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc) +{ + /* Check the CRC handle allocation */ + if (hcrc == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance)); + + /* Check the CRC peripheral state */ + if (hcrc->State == HAL_CRC_STATE_BUSY) + { + return HAL_BUSY; + } + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_BUSY; + + /* Reset CRC calculation unit */ + __HAL_CRC_DR_RESET(hcrc); + + /* Reset IDR register content */ + CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR); + + /* DeInit the low level hardware */ + HAL_CRC_MspDeInit(hcrc); + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_RESET; + + /* Process unlocked */ + __HAL_UNLOCK(hcrc); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initializes the CRC MSP. + * @param hcrc CRC handle + * @retval None + */ +__weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcrc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_CRC_MspInit can be implemented in the user file + */ +} + +/** + * @brief DeInitialize the CRC MSP. + * @param hcrc CRC handle + * @retval None + */ +__weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcrc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_CRC_MspDeInit can be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions + * @brief management functions. + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer + using combination of the previous CRC value and the new one. + + [..] or + + (+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer + independently of the previous CRC value. + +@endverbatim + * @{ + */ + +/** + * @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer + * starting with the previously computed CRC as initialization value. + * @param hcrc CRC handle + * @param pBuffer pointer to the input data buffer, exact input data format is + * provided by hcrc->InputDataFormat. + * @param BufferLength input data buffer length (number of bytes if pBuffer + * type is * uint8_t, number of half-words if pBuffer type is * uint16_t, + * number of words if pBuffer type is * uint32_t). + * @note By default, the API expects a uint32_t pointer as input buffer parameter. + * Input buffer pointers with other types simply need to be cast in uint32_t + * and the API will internally adjust its input data processing based on the + * handle field hcrc->InputDataFormat. + * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) + */ +uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength) +{ + uint32_t index; /* CRC input data buffer index */ + uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */ + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_BUSY; + + switch (hcrc->InputDataFormat) + { + case CRC_INPUTDATA_FORMAT_WORDS: + /* Enter Data to the CRC calculator */ + for (index = 0U; index < BufferLength; index++) + { + hcrc->Instance->DR = pBuffer[index]; + } + temp = hcrc->Instance->DR; + break; + + case CRC_INPUTDATA_FORMAT_BYTES: + temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength); + break; + + case CRC_INPUTDATA_FORMAT_HALFWORDS: + temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */ + break; + default: + break; + } + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_READY; + + /* Return the CRC computed value */ + return temp; +} + +/** + * @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer + * starting with hcrc->Instance->INIT as initialization value. + * @param hcrc CRC handle + * @param pBuffer pointer to the input data buffer, exact input data format is + * provided by hcrc->InputDataFormat. + * @param BufferLength input data buffer length (number of bytes if pBuffer + * type is * uint8_t, number of half-words if pBuffer type is * uint16_t, + * number of words if pBuffer type is * uint32_t). + * @note By default, the API expects a uint32_t pointer as input buffer parameter. + * Input buffer pointers with other types simply need to be cast in uint32_t + * and the API will internally adjust its input data processing based on the + * handle field hcrc->InputDataFormat. + * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) + */ +uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength) +{ + uint32_t index; /* CRC input data buffer index */ + uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */ + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_BUSY; + + /* Reset CRC Calculation Unit (hcrc->Instance->INIT is + * written in hcrc->Instance->DR) */ + __HAL_CRC_DR_RESET(hcrc); + + switch (hcrc->InputDataFormat) + { + case CRC_INPUTDATA_FORMAT_WORDS: + /* Enter 32-bit input data to the CRC calculator */ + for (index = 0U; index < BufferLength; index++) + { + hcrc->Instance->DR = pBuffer[index]; + } + temp = hcrc->Instance->DR; + break; + + case CRC_INPUTDATA_FORMAT_BYTES: + /* Specific 8-bit input data handling */ + temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength); + break; + + case CRC_INPUTDATA_FORMAT_HALFWORDS: + /* Specific 16-bit input data handling */ + temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */ + break; + + default: + break; + } + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_READY; + + /* Return the CRC computed value */ + return temp; +} + +/** + * @} + */ + +/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions + * @brief Peripheral State functions. + * +@verbatim + =============================================================================== + ##### Peripheral State functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Return the CRC handle state. + * @param hcrc CRC handle + * @retval HAL state + */ +HAL_CRC_StateTypeDef HAL_CRC_GetState(const CRC_HandleTypeDef *hcrc) +{ + /* Return CRC handle state */ + return hcrc->State; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup CRC_Private_Functions + * @{ + */ + +/** + * @brief Enter 8-bit input data to the CRC calculator. + * Specific data handling to optimize processing time. + * @param hcrc CRC handle + * @param pBuffer pointer to the input data buffer + * @param BufferLength input data buffer length + * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) + */ +static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength) +{ + uint32_t i; /* input data buffer index */ + uint16_t data; + __IO uint16_t *pReg; + + /* Processing time optimization: 4 bytes are entered in a row with a single word write, + * last bytes must be carefully fed to the CRC calculator to ensure a correct type + * handling by the peripheral */ + for (i = 0U; i < (BufferLength / 4U); i++) + { + hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \ + ((uint32_t)pBuffer[(4U * i) + 1U] << 16U) | \ + ((uint32_t)pBuffer[(4U * i) + 2U] << 8U) | \ + (uint32_t)pBuffer[(4U * i) + 3U]; + } + /* last bytes specific handling */ + if ((BufferLength % 4U) != 0U) + { + if ((BufferLength % 4U) == 1U) + { + *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[4U * i]; /* Derogation MisraC2012 R.11.5 */ + } + if ((BufferLength % 4U) == 2U) + { + data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U]; + pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */ + *pReg = data; + } + if ((BufferLength % 4U) == 3U) + { + data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U]; + pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */ + *pReg = data; + + *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[(4U * i) + 2U]; /* Derogation MisraC2012 R.11.5 */ + } + } + + /* Return the CRC computed value */ + return hcrc->Instance->DR; +} + +/** + * @brief Enter 16-bit input data to the CRC calculator. + * Specific data handling to optimize processing time. + * @param hcrc CRC handle + * @param pBuffer pointer to the input data buffer + * @param BufferLength input data buffer length + * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) + */ +static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength) +{ + uint32_t i; /* input data buffer index */ + __IO uint16_t *pReg; + + /* Processing time optimization: 2 HalfWords are entered in a row with a single word write, + * in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure + * a correct type handling by the peripheral */ + for (i = 0U; i < (BufferLength / 2U); i++) + { + hcrc->Instance->DR = ((uint32_t)pBuffer[2U * i] << 16U) | (uint32_t)pBuffer[(2U * i) + 1U]; + } + if ((BufferLength % 2U) != 0U) + { + pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */ + *pReg = pBuffer[2U * i]; + } + + /* Return the CRC computed value */ + return hcrc->Instance->DR; +} + +/** + * @} + */ + +#endif /* HAL_CRC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_crc_ex.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_crc_ex.c new file mode 100644 index 0000000000..3678b1b5ca --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_crc_ex.c @@ -0,0 +1,232 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_crc_ex.c + * @author MCD Application Team + * @brief Extended CRC HAL module driver. + * This file provides firmware functions to manage the extended + * functionalities of the CRC peripheral. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim +================================================================================ + ##### How to use this driver ##### +================================================================================ + [..] + (+) Set user-defined generating polynomial through HAL_CRCEx_Polynomial_Set() + (+) Configure Input or Output data inversion + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @defgroup CRCEx CRCEx + * @brief CRC Extended HAL module driver + * @{ + */ + +#ifdef HAL_CRC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup CRCEx_Exported_Functions CRC Extended Exported Functions + * @{ + */ + +/** @defgroup CRCEx_Exported_Functions_Group1 Extended Initialization/de-initialization functions + * @brief Extended Initialization and Configuration functions. + * +@verbatim + =============================================================================== + ##### Extended configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure the generating polynomial + (+) Configure the input data inversion + (+) Configure the output data inversion + +@endverbatim + * @{ + */ + + +/** + * @brief Initialize the CRC polynomial if different from default one. + * @param hcrc CRC handle + * @param Pol CRC generating polynomial (7, 8, 16 or 32-bit long). + * This parameter is written in normal representation, e.g. + * @arg for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65 + * @arg for a polynomial of degree 16, X^16 + X^12 + X^5 + 1 is written 0x1021 + * @param PolyLength CRC polynomial length. + * This parameter can be one of the following values: + * @arg @ref CRC_POLYLENGTH_7B 7-bit long CRC (generating polynomial of degree 7) + * @arg @ref CRC_POLYLENGTH_8B 8-bit long CRC (generating polynomial of degree 8) + * @arg @ref CRC_POLYLENGTH_16B 16-bit long CRC (generating polynomial of degree 16) + * @arg @ref CRC_POLYLENGTH_32B 32-bit long CRC (generating polynomial of degree 32) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t msb = 31U; /* polynomial degree is 32 at most, so msb is initialized to max value */ + + /* Check the parameters */ + assert_param(IS_CRC_POL_LENGTH(PolyLength)); + + /* Ensure that the generating polynomial is odd */ + if ((Pol & (uint32_t)(0x1U)) == 0U) + { + status = HAL_ERROR; + } + else + { + /* check polynomial definition vs polynomial size: + * polynomial length must be aligned with polynomial + * definition. HAL_ERROR is reported if Pol degree is + * larger than that indicated by PolyLength. + * Look for MSB position: msb will contain the degree of + * the second to the largest polynomial member. E.g., for + * X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */ + while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U)) + { + } + + switch (PolyLength) + { + + case CRC_POLYLENGTH_7B: + if (msb >= HAL_CRC_LENGTH_7B) + { + status = HAL_ERROR; + } + break; + case CRC_POLYLENGTH_8B: + if (msb >= HAL_CRC_LENGTH_8B) + { + status = HAL_ERROR; + } + break; + case CRC_POLYLENGTH_16B: + if (msb >= HAL_CRC_LENGTH_16B) + { + status = HAL_ERROR; + } + break; + + case CRC_POLYLENGTH_32B: + /* no polynomial definition vs. polynomial length issue possible */ + break; + default: + status = HAL_ERROR; + break; + } + } + if (status == HAL_OK) + { + /* set generating polynomial */ + WRITE_REG(hcrc->Instance->POL, Pol); + + /* set generating polynomial size */ + MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength); + } + /* Return function status */ + return status; +} + +/** + * @brief Set the Reverse Input data mode. + * @param hcrc CRC handle + * @param InputReverseMode Input Data inversion mode. + * This parameter can be one of the following values: + * @arg @ref CRC_INPUTDATA_INVERSION_NONE no change in bit order (default value) + * @arg @ref CRC_INPUTDATA_INVERSION_BYTE Byte-wise bit reversal + * @arg @ref CRC_INPUTDATA_INVERSION_HALFWORD HalfWord-wise bit reversal + * @arg @ref CRC_INPUTDATA_INVERSION_WORD Word-wise bit reversal + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode) +{ + /* Check the parameters */ + assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(InputReverseMode)); + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_BUSY; + + /* set input data inversion mode */ + MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, InputReverseMode); + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Set the Reverse Output data mode. + * @param hcrc CRC handle + * @param OutputReverseMode Output Data inversion mode. + * This parameter can be one of the following values: + * @arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion (default value) + * @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE bit-level inversion (e.g. for a 8-bit CRC: 0xB5 becomes 0xAD) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode) +{ + /* Check the parameters */ + assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(OutputReverseMode)); + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_BUSY; + + /* set output data inversion mode */ + MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, OutputReverseMode); + + /* Change CRC peripheral state */ + hcrc->State = HAL_CRC_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + + + + +/** + * @} + */ + + +/** + * @} + */ + + +#endif /* HAL_CRC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_cryp.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_cryp.c new file mode 100644 index 0000000000..76c12ba598 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_cryp.c @@ -0,0 +1,6498 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_cryp.c + * @author MCD Application Team + * @brief CRYP HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Cryptography (CRYP) peripheral: + * + Initialization, de-initialization, set config and get config functions + * + DMA callback functions + * + CRYP IRQ handler management + * + Peripheral State functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The CRYP HAL driver can be used as follows: + + (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit(): + (##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE()or __HAL_RCC_AES_CLK_ENABLE + (##) In case of using interrupts (e.g. HAL_CRYP_Encrypt_IT()) + (+++) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority() + (+++) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ() + (+++) In CRYP IRQ handler, call HAL_CRYP_IRQHandler() + (##) In case of using DMA to control data transfer (e.g. HAL_CRYP_Encrypt_DMA()) + (+++) Enable the DMAx interface clock using __RCC_DMAx_CLK_ENABLE() + (+++) Configure and enable two DMA channels one for managing data transfer from + memory to peripheral (input channel) and another channel for managing data + transfer from peripheral to memory (output channel) + (+++) Associate the initialized DMA handle to the CRYP DMA handle + using __HAL_LINKDMA() + (+++) Configure the priority and enable the NVIC for the transfer complete + interrupt on the two DMA channels. The output channel should have higher + priority than the input channel HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ() + + (#)Initialize the CRYP according to the specified parameters : + (##) The data type: 1-bit, 8-bit, 16-bit or 32-bit. + (##) The key size: 128, 192 or 256. + (##) The AES Algorithm ECB/CBC/CTR/GCM or CCM. + (##) The initialization vector (counter). It is not used in ECB mode. + (##) The key buffer used for encryption/decryption. + (+++) In some specific configurations, the key is written by the application + code out of the HAL scope. In that case, user can still resort to the + HAL APIs as usual but must make sure that pKey pointer is set to NULL. + (##) The DataWidthUnit field. It specifies whether the data length (or the payload + length for authentication algorithms) is in words or bytes. + (##) The Header used only in AES GCM and CCM Algorithm for authentication. + (##) The HeaderSize used to give size of header buffer in word or bytes, depending upon HeaderWidthUnit field. + (##) The HeaderWidthUnit field. It specifies whether the header length + (for authentication algorithms) is in words or bytes. + (##) The B0 block is the first authentication block used only in AES CCM mode. + (##) The KeyIVConfigSkip used to process several messages in a row. + (##) The KeyMode used to special key operation modes (for SAES : wrapped key, shared key with AES peripheral). + (##) The KeySelect, Only for SAES, used to select key from different key source. + (##) The KeyProtection, Only for SAES, used for security context enforcement. + + (#)Three processing (encryption/decryption) functions are available: + (##) Polling mode: encryption and decryption APIs are blocking functions + i.e. they process the data and wait till the processing is finished, + e.g. HAL_CRYP_Encrypt & HAL_CRYP_Decrypt + (##) Interrupt mode: encryption and decryption APIs are not blocking functions + i.e. they process the data under interrupt, + e.g. HAL_CRYP_Encrypt_IT & HAL_CRYP_Decrypt_IT + (##) DMA mode: encryption and decryption APIs are not blocking functions + i.e. the data transfer is ensured by DMA, + e.g. HAL_CRYP_Encrypt_DMA & HAL_CRYP_Decrypt_DMA + + (#)When the processing function is called at first time after HAL_CRYP_Init() + the CRYP peripheral is configured and processes the buffer in input. + At second call, no need to Initialize the CRYP, user have to get current configuration via + HAL_CRYP_GetConfig() API, then only HAL_CRYP_SetConfig() is requested to set + new parameters, finally user can start encryption/decryption. + + (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral. + + (#)To process a single message with consecutive calls to HAL_CRYP_Encrypt() or HAL_CRYP_Decrypt() + without having to configure again the Key or the Initialization Vector between each API call, + the field KeyIVConfigSkip of the initialization structure must be set to CRYP_KEYIVCONFIG_ONCE. + Same is true for consecutive calls of HAL_CRYP_Encrypt_IT(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt_DMA() + or HAL_CRYP_Decrypt_DMA(). + + [..] + The cryptographic processor supports following standards: + (#) The advanced encryption standard (AES) supported: + (##)128-bit data block processing + (##) chaining modes supported : + (+++) Electronic Code Book(ECB) + (+++) Cipher Block Chaining (CBC) + (+++) Counter mode (CTR) + (+++) Galois/counter mode (GCM/GMAC) + (+++) Counter with Cipher Block Chaining-Message(CCM) + (##) keys length Supported : 128-bit and 256-bit + + [..] + (@) Specific care must be taken to format the key and the Initialization Vector IV! + + [..] If the key is defined as a 128-bit long array key[127..0] = {b127 ... b0} where + b127 is the MSB and b0 the LSB, the key must be stored in MCU memory + (+) as a sequence of words where the MSB word comes first (occupies the + lowest memory address) + (++) address n+0 : 0b b127 .. b120 b119 .. b112 b111 .. b104 b103 .. b96 + (++) address n+4 : 0b b95 .. b88 b87 .. b80 b79 .. b72 b71 .. b64 + (++) address n+8 : 0b b63 .. b56 b55 .. b48 b47 .. b40 b39 .. b32 + (++) address n+C : 0b b31 .. b24 b23 .. b16 b15 .. b8 b7 .. b0 + [..] Hereafter, another illustration when considering a 128-bit long key made of 16 bytes {B15..B0}. + The 4 32-bit words that make the key must be stored as follows in MCU memory: + (+) address n+0 : 0x B15 B14 B13 B12 + (+) address n+4 : 0x B11 B10 B9 B8 + (+) address n+8 : 0x B7 B6 B5 B4 + (+) address n+C : 0x B3 B2 B1 B0 + [..] which leads to the expected setting + (+) AES_KEYR3 = 0x B15 B14 B13 B12 + (+) AES_KEYR2 = 0x B11 B10 B9 B8 + (+) AES_KEYR1 = 0x B7 B6 B5 B4 + (+) AES_KEYR0 = 0x B3 B2 B1 B0 + + [..] Same format must be applied for a 256-bit long key made of 32 bytes {B31..B0}. + The 8 32-bit words that make the key must be stored as follows in MCU memory: + (+) address n+00 : 0x B31 B30 B29 B28 + (+) address n+04 : 0x B27 B26 B25 B24 + (+) address n+08 : 0x B23 B22 B21 B20 + (+) address n+0C : 0x B19 B18 B17 B16 + (+) address n+10 : 0x B15 B14 B13 B12 + (+) address n+14 : 0x B11 B10 B9 B8 + (+) address n+18 : 0x B7 B6 B5 B4 + (+) address n+1C : 0x B3 B2 B1 B0 + [..] which leads to the expected setting + (+) AES_KEYR7 = 0x B31 B30 B29 B28 + (+) AES_KEYR6 = 0x B27 B26 B25 B24 + (+) AES_KEYR5 = 0x B23 B22 B21 B20 + (+) AES_KEYR4 = 0x B19 B18 B17 B16 + (+) AES_KEYR3 = 0x B15 B14 B13 B12 + (+) AES_KEYR2 = 0x B11 B10 B9 B8 + (+) AES_KEYR1 = 0x B7 B6 B5 B4 + (+) AES_KEYR0 = 0x B3 B2 B1 B0 + + [..] Initialization Vector IV (4 32-bit words) format must follow the same as + that of a 128-bit long key. + + [..] Note that key and IV registers are not sensitive to swap mode selection. + + [..] This section describes the AES Galois/counter mode (GCM) supported by the peripherals: + (#) Algorithm supported : + (##) Galois/counter mode (GCM) + (##) Galois message authentication code (GMAC) :is exactly the same as + GCM algorithm composed only by an header. + (#) Four phases are performed in GCM : + (##) Init phase: peripheral prepares the GCM hash subkey (H) and do the IV processing + (##) Header phase: peripheral processes the Additional Authenticated Data (AAD), with hash + computation only. + (##) Payload phase: peripheral processes the plaintext (P) with hash computation + keystream + encryption + data XORing. It works in a similar way for ciphertext (C). + (##) Final phase: peripheral generates the authenticated tag (T) using the last block of data. + HAL_CRYPEx_AESGCM_GenerateAuthTAG API used in this phase to generate 4 words which correspond + to the Tag. user should consider only part of this 4 words, if Tag length is less than 128 bits. + (#) structure of message construction in GCM is defined as below : + (##) 16 bytes Initial Counter Block (ICB)composed of IV and counter + (##) The authenticated header A (also knows as Additional Authentication Data AAD) + this part of the message is only authenticated, not encrypted. + (##) The plaintext message P is both authenticated and encrypted as ciphertext. + GCM standard specifies that ciphertext has same bit length as the plaintext. + (##) The last block is composed of the length of A (on 64 bits) and the length of ciphertext + (on 64 bits) + + [..] A more detailed description of the GCM message structure is available below. + + [..] This section describe The AES Counter with Cipher Block Chaining-Message + Authentication Code (CCM) supported by the peripheral: + (#) Specific parameters for CCM : + + (##) B0 block : follows NIST Special Publication 800-38C, + (##) B1 block (header) + (##) CTRx block : control blocks + + [..] A detailed description of the CCM message structure is available below. + + (#) CCM in peripheral: + (##) To perform message payload encryption or decryption AES is configured in CTR mode. + (##) For authentication two phases are performed : + - Header phase: peripheral processes the Additional Authenticated Data (AAD) first, then the cleartext message + only cleartext payload (not the ciphertext payload) is used and no output. + (##) Final phase: peripheral generates the authenticated tag (T) using the last block of data. + HAL_CRYPEx_AESCCM_GenerateAuthTAG API used in this phase to generate 4 words which correspond to the Tag. + user should consider only part of this 4 words, if Tag length is less than 128 bits + *** Callback registration *** + ============================= + + [..] + The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use Functions @ref HAL_CRYP_RegisterCallback() or HAL_CRYP_RegisterXXXCallback() + to register an interrupt callback. + + [..] + Function @ref HAL_CRYP_RegisterCallback() allows to register following callbacks: + (+) InCpltCallback : Input FIFO transfer completed callback. + (+) OutCpltCallback : Output FIFO transfer completed callback. + (+) ErrorCallback : callback for error detection. + (+) MspInitCallback : CRYP MspInit. + (+) MspDeInitCallback : CRYP MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + [..] + Use function @ref HAL_CRYP_UnRegisterCallback() to reset a callback to the default + weak function. + @ref HAL_CRYP_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) InCpltCallback : Input FIFO transfer completed callback. + (+) OutCpltCallback : Output FIFO transfer completed callback. + (+) ErrorCallback : callback for error detection. + (+) MspInitCallback : CRYP MspInit. + (+) MspDeInitCallback : CRYP MspDeInit. + + [..] + By default, after the @ref HAL_CRYP_Init() and when the state is HAL_CRYP_STATE_RESET + all callbacks are set to the corresponding weak functions : + examples @ref HAL_CRYP_InCpltCallback() , @ref HAL_CRYP_OutCpltCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak function in the @ref HAL_CRYP_Init()/ @ref HAL_CRYP_DeInit() only when + these callbacks are null (not registered beforehand). + if not, MspInit or MspDeInit are not null, the @ref HAL_CRYP_Init() / @ref HAL_CRYP_DeInit() + keep and use the user MspInit/MspDeInit functions (registered beforehand) + + [..] + Callbacks can be registered/unregistered in HAL_CRYP_STATE_READY state only. + Exception done MspInit/MspDeInit callbacks that can be registered/unregistered + in HAL_CRYP_STATE_READY or HAL_CRYP_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_CRYP_RegisterCallback() before calling @ref HAL_CRYP_DeInit() + or @ref HAL_CRYP_Init() function. + + [..] + When The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + + *** Suspend/Resume feature *** + ============================== + + [..] + The compilation define USE_HAL_CRYP_SUSPEND_RESUME when set to 1 + allows the user to resort to the suspend/resume feature. + A low priority block processing can be suspended to process a high priority block + instead. When the high priority block processing is over, the low priority block + processing can be resumed, restarting from the point where it was suspended. This + feature is applicable only in non-blocking interrupt mode. + + [..] User must resort to HAL_CRYP_Suspend() to suspend the low priority block + processing. This API manages the hardware block processing suspension and saves all the + internal data that will be needed to restart later on. Upon HAL_CRYP_Suspend() completion, + the user can launch the processing of any other block (high priority block processing). + + [..] When the high priority block processing is over, user must invoke HAL_CRYP_Resume() + to resume the low priority block processing. Ciphering (or deciphering) restarts from + the suspension point and ends as usual. + + [..] HAL_CRYP_Suspend() reports an error when the suspension request is sent too late + (i.e when the low priority block processing is about to end). There is no use to + suspend the tag generation processing for authentication algorithms. + + [..] + (@) If the key is written out of HAL scope (case pKey pointer set to NULL by the user), + the block processing suspension/resumption mechanism is NOT applicable. + + [..] + (@) If the Key and Initialization Vector are configured only once and configuration is + skipped for consecutive processings (case KeyIVConfigSkip set to CRYP_KEYIVCONFIG_ONCE), + the block processing suspension/resumption mechanism is NOT applicable. + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @addtogroup CRYP + * @{ + */ + +#if defined(AES) +#ifdef HAL_CRYP_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup CRYP_Private_Defines + * @{ + */ +#define CRYP_GENERAL_TIMEOUT 82U +#define CRYP_TIMEOUT_KEYPREPARATION 82U /*!< The latency of key preparation operation is 82 clock cycles.*/ +#define CRYP_TIMEOUT_GCMCCMINITPHASE 299U /*!< The latency of GCM/CCM init phase to prepare hash subkey + is 299 clock cycles.*/ +#define CRYP_TIMEOUT_GCMCCMHEADERPHASE 290U /*!< The latency of GCM/CCM header phase is 290 clock cycles.*/ + +#define CRYP_PHASE_READY 0x00000001U /*!< CRYP peripheral is ready for initialization. */ +#define CRYP_PHASE_PROCESS 0x00000002U /*!< CRYP peripheral is in processing phase */ +#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) +#define CRYP_PHASE_HEADER_SUSPENDED 0x00000004U /*!< GCM/GMAC/CCM header phase is suspended */ +#define CRYP_PHASE_PAYLOAD_SUSPENDED 0x00000005U /*!< GCM/CCM payload phase is suspended */ +#endif /* USE_HAL_CRYP_SUSPEND_RESUME */ +#define CRYP_PHASE_HEADER_DMA_FEED 0x00000006U /*!< GCM/GMAC/CCM header is fed to the peripheral in DMA mode */ + +#define CRYP_OPERATINGMODE_ENCRYPT 0x00000000U /*!< Encryption mode(Mode 1) */ +#define CRYP_OPERATINGMODE_KEYDERIVATION AES_CR_MODE_0 /*!< Key derivation mode only used when performing ECB and CBC decryptions (Mode 2) */ +#define CRYP_OPERATINGMODE_DECRYPT AES_CR_MODE_1 /*!< Decryption (Mode 3) */ +#define CRYP_PHASE_INIT 0x00000000U /*!< GCM/GMAC (or CCM) init phase */ +#define CRYP_PHASE_HEADER AES_CR_GCMPH_0 /*!< GCM/GMAC or CCM header phase */ +#define CRYP_PHASE_PAYLOAD AES_CR_GCMPH_1 /*!< GCM(/CCM) payload phase */ +#define CRYP_PHASE_FINAL AES_CR_GCMPH /*!< GCM/GMAC or CCM final phase */ + +/* CTR1 information to use in CCM algorithm */ +#define CRYP_CCM_CTR1_0 0x07FFFFFFU +#define CRYP_CCM_CTR1_1 0xFFFFFF00U +#define CRYP_CCM_CTR1_2 0x00000001U + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/** @addtogroup CRYP_Private_Macros + * @{ + */ + +#define CRYP_SET_PHASE(__HANDLE__, __PHASE__)\ + MODIFY_REG((__HANDLE__)->Instance->CR, AES_CR_GCMPH, (uint32_t)(__PHASE__)) + +/** + * @} + */ + +/* Private struct -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup CRYP_Private_Functions + * @{ + */ + +static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr); +static HAL_StatusTypeDef CRYP_SetHeaderDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size); +static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma); +static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma); +static void CRYP_DMAError(DMA_HandleTypeDef *hdma); +static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint32_t KeySize); +static void CRYP_SetIV(CRYP_HandleTypeDef *hcryp); +static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp); +static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); +static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp); +static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp); +static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcryp); +static HAL_StatusTypeDef CRYP_GCMCCM_SetPayloadPhase_DMA(CRYP_HandleTypeDef *hcryp); +static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp); +static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp); +static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); +static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); +static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp); +static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp); +static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcrypt, uint32_t Timeout); +static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); +static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); +static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp); +static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp); +static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp); +static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); +static void CRYP_ClearCCFlagWhenHigh(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); +#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) +static void CRYP_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, const uint32_t *Output); +static void CRYP_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, const uint32_t *Input); +static void CRYP_Read_SuspendRegisters(CRYP_HandleTypeDef *hcryp, const uint32_t *Output); +static void CRYP_Write_SuspendRegisters(CRYP_HandleTypeDef *hcryp, const uint32_t *Input); +static void CRYP_Read_KeyRegisters(CRYP_HandleTypeDef *hcryp, const uint32_t *Output, uint32_t KeySize); +static void CRYP_Write_KeyRegisters(CRYP_HandleTypeDef *hcryp, const uint32_t *Input, uint32_t KeySize); +static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp); +#endif /* USE_HAL_CRYP_SUSPEND_RESUME */ + + +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ + +/** @addtogroup CRYP_Exported_Functions + * @{ + */ + +/** @defgroup CRYP_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions. + * +@verbatim + ======================================================================================== + ##### Initialization, de-initialization and Set and Get configuration functions ##### + ======================================================================================== + [..] This section provides functions allowing to: + (+) Initialize the CRYP + (+) DeInitialize the CRYP + (+) Initialize the CRYP MSP + (+) DeInitialize the CRYP MSP + (+) configure CRYP (HAL_CRYP_SetConfig) with the specified parameters in the CRYP_ConfigTypeDef + Parameters which are configured in This section are : + (+) Key size + (+) Data Type : 32,16, 8 or 1bit + (+) AlgoMode : ECB,CBC,CTR,GCM/GMAC and CCM in AES Standard. + (+) Get CRYP configuration (HAL_CRYP_GetConfig) from the specified parameters in the CRYP_HandleTypeDef + (+) For interleave mode, API HAL_CRYP_SaveContext and HAL_CRYP_RestoreContext to be used to save then Restore CRYP + configuration and parameters. CRYP_IVCONFIG_ONCE should be selected for KeyIVConfigSkip parameter. + Only polling mode is supported, interleave mode should be used with HAL_CRYP_Encrypt and HAL_CRYP_Decrypt API. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the CRYP according to the specified + * parameters in the CRYP_ConfigTypeDef and creates the associated handle. + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp) +{ + uint32_t cr_value; +#if defined(SAES) + uint32_t tickstart; +#endif /* SAES */ + + /* Check the CRYP handle allocation */ + if (hcryp == NULL) + { + return HAL_ERROR; + } + + /* Check parameters */ + assert_param(IS_CRYP_KEYSIZE(hcryp->Init.KeySize)); + assert_param(IS_CRYP_DATATYPE(hcryp->Init.DataType)); + assert_param(IS_CRYP_ALGORITHM(hcryp->Init.Algorithm)); + assert_param(IS_CRYP_INIT(hcryp->Init.KeyIVConfigSkip)); + +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + if (hcryp->State == HAL_CRYP_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hcryp->Lock = HAL_UNLOCKED; + + hcryp->InCpltCallback = HAL_CRYP_InCpltCallback; /* Legacy weak InCpltCallback */ + hcryp->OutCpltCallback = HAL_CRYP_OutCpltCallback; /* Legacy weak OutCpltCallback */ + hcryp->ErrorCallback = HAL_CRYP_ErrorCallback; /* Legacy weak ErrorCallback */ + + if (hcryp->MspInitCallback == NULL) + { + hcryp->MspInitCallback = HAL_CRYP_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware */ + hcryp->MspInitCallback(hcryp); + } +#else + if (hcryp->State == HAL_CRYP_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hcryp->Lock = HAL_UNLOCKED; + + /* Init the low level hardware */ + HAL_CRYP_MspInit(hcryp); + } +#endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */ + +#if !defined(SAES) + /* Set the key size, data type and Algorithm */ + cr_value = (uint32_t)(hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm); + /* Set the key size, data type, algorithm and mode */ + MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD, cr_value); +#else + if (hcryp->Instance == AES) + { + /* Set the key size, data type and Algorithm */ + cr_value = (uint32_t)(hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm | hcryp->Init.KeyMode); + /* Set the key size, data type, algorithm and mode */ + MODIFY_REG(hcryp->Instance->CR, AES_CR_KMOD | AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD, cr_value); + } + else + { + /* SAES is initializing, fetching random number from the RNG */ + tickstart = HAL_GetTick(); + while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY)) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > CRYP_GENERAL_TIMEOUT) + { + __HAL_CRYP_DISABLE(hcryp); + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } + /* SAES is initializing, no random number fetching error flagged */ + tickstart = HAL_GetTick(); + while (HAL_IS_BIT_SET(hcryp->Instance->ISR, CRYP_FLAG_RNGEIF)) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > CRYP_GENERAL_TIMEOUT) + { + __HAL_CRYP_DISABLE(hcryp); + hcryp->ErrorCode |= HAL_CRYP_ERROR_RNG; + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } + cr_value = (uint32_t)(hcryp->Init.KeyMode | hcryp->Init.DataType | hcryp->Init.KeySize | \ + hcryp->Init.Algorithm | hcryp->Init.KeySelect | hcryp->Init.KeyProtection); + /* Set the key size, data type, algorithm, Key selection and key protection */ + MODIFY_REG(hcryp->Instance->CR, AES_CR_KMOD | AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD | AES_CR_KEYSEL | + AES_CR_KEYPROT, cr_value); + } +#endif /* !SAES */ + /* Reset Error Code field */ + hcryp->ErrorCode = HAL_CRYP_ERROR_NONE; + + /* Reset peripheral Key and IV configuration flag */ + hcryp->KeyIVConfig = 0U; + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_READY; + + /* Set the default CRYP phase */ + hcryp->Phase = CRYP_PHASE_READY; + + return HAL_OK; +} + +/** + * @brief De-Initializes the CRYP peripheral. + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp) +{ + /* Check the CRYP handle allocation */ + if (hcryp == NULL) + { + return HAL_ERROR; + } + + /* Set the default CRYP phase */ + hcryp->Phase = CRYP_PHASE_READY; + + /* Reset CrypInCount and CrypOutCount */ + hcryp->CrypInCount = 0; + hcryp->CrypOutCount = 0; + hcryp->CrypHeaderCount = 0; + + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Set IPRST for software reset */ + SET_BIT(hcryp->Instance->CR, AES_CR_IPRST); + + /* Clear IPRST to allow writing registers */ + CLEAR_BIT(hcryp->Instance->CR, AES_CR_IPRST); + +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + if (hcryp->MspDeInitCallback == NULL) + { + hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit; /* Legacy weak MspDeInit */ + } + /* DeInit the low level hardware */ + hcryp->MspDeInitCallback(hcryp); +#else + /* DeInit the low level hardware: CLOCK, NVIC.*/ + HAL_CRYP_MspDeInit(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_RESET; + __HAL_UNLOCK(hcryp); + + return HAL_OK; +} + +/** + * @brief Configure the CRYP according to the specified + * parameters in the CRYP_ConfigTypeDef + * @param hcryp pointer to a CRYP_HandleTypeDef structure + * @param pConf pointer to a CRYP_ConfigTypeDef structure that contains + * the configuration information for CRYP module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf) +{ + /* Check the CRYP handle allocation */ + if ((hcryp == NULL) || (pConf == NULL)) + { + return HAL_ERROR; + } + + /* Check parameters */ + assert_param(IS_CRYP_KEYSIZE(pConf->KeySize)); + assert_param(IS_CRYP_DATATYPE(pConf->DataType)); + assert_param(IS_CRYP_ALGORITHM(pConf->Algorithm)); + + if (hcryp->State == HAL_CRYP_STATE_READY) + { + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_BUSY; + __HAL_LOCK(hcryp); + + /* Set CRYP parameters */ + hcryp->Init.DataType = pConf->DataType; + hcryp->Init.pKey = pConf->pKey; + hcryp->Init.Algorithm = pConf->Algorithm; + hcryp->Init.KeySize = pConf->KeySize; + hcryp->Init.pInitVect = pConf->pInitVect; + hcryp->Init.Header = pConf->Header; + hcryp->Init.HeaderSize = pConf->HeaderSize; + hcryp->Init.B0 = pConf->B0; + hcryp->Init.DataWidthUnit = pConf->DataWidthUnit; + hcryp->Init.KeyMode = pConf->KeyMode; + hcryp->Init.HeaderWidthUnit = pConf->HeaderWidthUnit; + hcryp->Init.KeyIVConfigSkip = pConf->KeyIVConfigSkip; + +#if !defined(SAES) + /* Set the key size, data type, AlgoMode and operating mode */ + MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD, + hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm); +#else + if (hcryp->Instance == AES) + { + /* Set the key size, data type, AlgoMode and operating mode */ + MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD | AES_CR_KMOD, + hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm | hcryp->Init.KeyMode); + } + else + { + hcryp->Init.KeySelect = pConf->KeySelect; + hcryp->Init.KeyProtection = pConf->KeyProtection; + + /* In case of HSW, HW or SW key selection, we should specify Key mode selection (SAES_CR_KMOD) */ + if ((hcryp->Init.KeySelect != CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_WRAPPED)) + { + /* Disable AES to change key mode */ + __HAL_CRYP_DISABLE(hcryp); + /* Set key mode selection (Normal, Wrapped or Shared key )*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_KMOD, CRYP_KEYMODE_WRAPPED); + } + + /* Set the key size data type, AlgoMode and operating mode */ + MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD | \ + AES_CR_KEYSEL | AES_CR_KEYPROT | AES_CR_KMOD, hcryp->Init.DataType | hcryp->Init.KeySize | \ + hcryp->Init.Algorithm | hcryp->Init.KeySelect | hcryp->Init.KeyProtection | hcryp->Init.KeyMode); + /* Set to 0 the number of non-valid bytes using NPBLB field of CR register*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U); + } +#endif /* ! SAES*/ + /* Clear error flags */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_RWEIF); + __HAL_UNLOCK(hcryp); + + /* Reset Error Code field */ + hcryp->ErrorCode = HAL_CRYP_ERROR_NONE; + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_READY; + + /* Set the default CRYP phase */ + hcryp->Phase = CRYP_PHASE_READY; + + return HAL_OK; + } + else + { + /* Busy error code field */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY; + return HAL_ERROR; + } +} + +/** + * @brief Get CRYP Configuration parameters in associated handle. + * @param pConf pointer to a CRYP_ConfigTypeDef structure + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf) +{ + /* Check the CRYP handle allocation */ + if ((hcryp == NULL) || (pConf == NULL)) + { + return HAL_ERROR; + } + + if (hcryp->State == HAL_CRYP_STATE_READY) + { + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_BUSY; + __HAL_LOCK(hcryp); + + /* Get CRYP parameters */ + pConf->DataType = hcryp->Init.DataType; + pConf->pKey = hcryp->Init.pKey; + pConf->Algorithm = hcryp->Init.Algorithm; + pConf->KeySize = hcryp->Init.KeySize; + pConf->pInitVect = hcryp->Init.pInitVect; + pConf->Header = hcryp->Init.Header; + pConf->HeaderSize = hcryp->Init.HeaderSize; + pConf->B0 = hcryp->Init.B0; + pConf->DataWidthUnit = hcryp->Init.DataWidthUnit; + pConf->KeyMode = hcryp->Init.KeyMode; + pConf->KeySelect = hcryp->Init.KeySelect; + pConf->KeyProtection = hcryp->Init.KeyProtection; + pConf->KeyIVConfigSkip = hcryp->Init.KeyIVConfigSkip; + pConf->HeaderWidthUnit = hcryp->Init.HeaderWidthUnit; + + __HAL_UNLOCK(hcryp); + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_READY; + + return HAL_OK; + } + else + { + /* Busy error code field */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY; + return HAL_ERROR; + } +} +/** + * @brief Initializes the CRYP MSP. + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @retval None + */ +__weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcryp); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CRYP_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes CRYP MSP. + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @retval None + */ +__weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcryp); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CRYP_MspDeInit could be implemented in the user file + */ +} + +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) +/** + * @brief Register a User CRYP Callback + * To be used instead of the weak predefined callback + * @param hcryp cryp handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_CRYP_INPUT_COMPLETE_CB_ID Input FIFO transfer completed callback ID + * @arg @ref HAL_CRYP_OUTPUT_COMPLETE_CB_ID Output FIFO transfer completed callback ID + * @arg @ref HAL_CRYP_ERROR_CB_ID Error callback ID + * @arg @ref HAL_CRYP_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_CRYP_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, + pCRYP_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (hcryp->State == HAL_CRYP_STATE_READY) + { + switch (CallbackID) + { + case HAL_CRYP_INPUT_COMPLETE_CB_ID : + hcryp->InCpltCallback = pCallback; + break; + + case HAL_CRYP_OUTPUT_COMPLETE_CB_ID : + hcryp->OutCpltCallback = pCallback; + break; + + case HAL_CRYP_ERROR_CB_ID : + hcryp->ErrorCallback = pCallback; + break; + + case HAL_CRYP_MSPINIT_CB_ID : + hcryp->MspInitCallback = pCallback; + break; + + case HAL_CRYP_MSPDEINIT_CB_ID : + hcryp->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hcryp->State == HAL_CRYP_STATE_RESET) + { + switch (CallbackID) + { + case HAL_CRYP_MSPINIT_CB_ID : + hcryp->MspInitCallback = pCallback; + break; + + case HAL_CRYP_MSPDEINIT_CB_ID : + hcryp->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister an CRYP Callback + * CRYP callback is redirected to the weak predefined callback + * @param hcryp cryp handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_CRYP_INPUT_COMPLETE_CB_ID Input FIFO transfer completed callback ID + * @arg @ref HAL_CRYP_OUTPUT_COMPLETE_CB_ID Output FIFO transfer completed callback ID + * @arg @ref HAL_CRYP_ERROR_CB_ID Error callback ID + * @arg @ref HAL_CRYP_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_CRYP_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + + if (hcryp->State == HAL_CRYP_STATE_READY) + { + switch (CallbackID) + { + case HAL_CRYP_INPUT_COMPLETE_CB_ID : + hcryp->InCpltCallback = HAL_CRYP_InCpltCallback; /*!< Legacy weak InCpltCallback */ + break; + + case HAL_CRYP_OUTPUT_COMPLETE_CB_ID : + hcryp->OutCpltCallback = HAL_CRYP_OutCpltCallback; /*!< Legacy weak OutCpltCallback */ + break; + + case HAL_CRYP_ERROR_CB_ID : + hcryp->ErrorCallback = HAL_CRYP_ErrorCallback; /*!< Legacy weak ErrorCallback */ + break; + + case HAL_CRYP_MSPINIT_CB_ID : + hcryp->MspInitCallback = HAL_CRYP_MspInit; /*!< Legacy weak MspInit */ + break; + + case HAL_CRYP_MSPDEINIT_CB_ID : + hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit; /*!< Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;/*!< Legacy weak ERROR INVALID CALLBACK */ + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hcryp->State == HAL_CRYP_STATE_RESET) + { + switch (CallbackID) + { + case HAL_CRYP_MSPINIT_CB_ID : + hcryp->MspInitCallback = HAL_CRYP_MspInit; + break; + + case HAL_CRYP_MSPDEINIT_CB_ID : + hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit; + break; + + default : + /* Update the error code */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;; + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + +#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) +/** + * @brief Request CRYP processing suspension when in interruption mode. + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module. + * @note Set the handle field SuspendRequest to the appropriate value so that + * the on-going CRYP processing is suspended as soon as the required + * conditions are met. + * @note HAL_CRYP_ProcessSuspend() can only be invoked when the processing is done + * in non-blocking interrupt mode. + * @note It is advised not to suspend the CRYP processing when the DMA controller + * is managing the data transfer. + * @retval None + */ +void HAL_CRYP_ProcessSuspend(CRYP_HandleTypeDef *hcryp) +{ + /* Set Handle SuspendRequest field */ + hcryp->SuspendRequest = HAL_CRYP_SUSPEND; +} + +/** + * @brief CRYP processing suspension and peripheral internal parameters storage. + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @note peripheral internal parameters are stored to be readily available when + * suspended processing is resumed later on. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_Suspend(CRYP_HandleTypeDef *hcryp) +{ + HAL_CRYP_STATETypeDef state; + + /* Request suspension */ + HAL_CRYP_ProcessSuspend(hcryp); + + do + { + state = HAL_CRYP_GetState(hcryp); + } while ((state != HAL_CRYP_STATE_SUSPENDED) && (state != HAL_CRYP_STATE_READY)); + + if (HAL_CRYP_GetState(hcryp) == HAL_CRYP_STATE_READY) + { + /* Processing was already over or was about to end. No suspension done */ + return HAL_ERROR; + } + else + { + /* Suspend Processing */ + + /* If authentication algorithms on-going, carry out first saving steps + before disable the peripheral */ + if ((hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC) || \ + (hcryp->Init.Algorithm == CRYP_AES_CCM)) + { + /* Save Suspension registers */ + CRYP_Read_SuspendRegisters(hcryp, hcryp->SUSPxR_saved); + /* Save Key */ + CRYP_Read_KeyRegisters(hcryp, hcryp->Key_saved, hcryp->Init.KeySize); + /* Save IV */ + CRYP_Read_IVRegisters(hcryp, hcryp->IV_saved); + } + /* Disable AES */ + __HAL_CRYP_DISABLE(hcryp); + + /* Save low-priority block CRYP handle parameters */ + hcryp->Init_saved = hcryp->Init; + hcryp->pCrypInBuffPtr_saved = hcryp->pCrypInBuffPtr; + hcryp->pCrypOutBuffPtr_saved = hcryp->pCrypOutBuffPtr; + hcryp->CrypInCount_saved = hcryp->CrypInCount; + hcryp->CrypOutCount_saved = hcryp->CrypOutCount; + hcryp->Phase_saved = hcryp->Phase; + hcryp->State_saved = hcryp->State; + hcryp->Size_saved = ((hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)\ + ? (hcryp->Size / 4U) : hcryp->Size); + hcryp->SizesSum_saved = hcryp->SizesSum; + hcryp->CrypHeaderCount_saved = hcryp->CrypHeaderCount; + hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE; + + if ((hcryp->Init.Algorithm == CRYP_AES_CBC) || \ + (hcryp->Init.Algorithm == CRYP_AES_CTR)) + { + /* Save Initialisation Vector registers */ + CRYP_Read_IVRegisters(hcryp, hcryp->IV_saved); + } + + /* Save Control register */ + hcryp->CR_saved = hcryp->Instance->CR; + } + return HAL_OK; +} + +/** + * @brief CRYP processing resumption. + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @note Processing restarts at the exact point where it was suspended, based + * on the parameters saved at suspension time. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_Resume(CRYP_HandleTypeDef *hcryp) +{ + /* Check the CRYP handle allocation */ + if (hcryp == NULL) + { + return HAL_ERROR; + } + + if (hcryp->State_saved != HAL_CRYP_STATE_SUSPENDED) + { + /* CRYP was not suspended */ + return HAL_ERROR; + } + else + { + /* Restore low-priority block CRYP handle parameters */ + hcryp->Init = hcryp->Init_saved; + hcryp->State = hcryp->State_saved; + + /* Chaining algorithms case */ + if ((hcryp->Init_saved.Algorithm == CRYP_AES_ECB) || \ + (hcryp->Init_saved.Algorithm == CRYP_AES_CBC) || \ + (hcryp->Init_saved.Algorithm == CRYP_AES_CTR)) + { + /* Restore low-priority block CRYP handle parameters */ + if ((hcryp->Init.Algorithm == CRYP_AES_CBC) || \ + (hcryp->Init.Algorithm == CRYP_AES_CTR)) + { + hcryp->Init.pInitVect = hcryp->IV_saved; + } + __HAL_CRYP_DISABLE(hcryp); + + (void) HAL_CRYP_Init(hcryp); + } + else /* Authentication algorithms case */ + { + /* Restore low-priority block CRYP handle parameters */ + hcryp->Phase = hcryp->Phase_saved; + hcryp->CrypHeaderCount = hcryp->CrypHeaderCount_saved; + hcryp->SizesSum = hcryp->SizesSum_saved; + + /* Disable AES and write-back SUSPxR registers */; + __HAL_CRYP_DISABLE(hcryp); + /* Restore AES Suspend Registers */ + CRYP_Write_SuspendRegisters(hcryp, hcryp->SUSPxR_saved); + /* Restore Control, Key and IV Registers, then enable AES */ + hcryp->Instance->CR = hcryp->CR_saved; + CRYP_Write_KeyRegisters(hcryp, hcryp->Key_saved, hcryp->Init.KeySize); + CRYP_Write_IVRegisters(hcryp, hcryp->IV_saved); + __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE); + __HAL_CRYP_ENABLE(hcryp); + + /* At the same time, set handle state back to READY to be able to resume the AES calculations + without the processing APIs returning HAL_BUSY when called. */ + hcryp->State = HAL_CRYP_STATE_READY; + } + + /* Resume low-priority block processing under IT */ + hcryp->ResumingFlag = 1U; + if (READ_BIT(hcryp->CR_saved, AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT) + { + if (HAL_CRYP_Encrypt_IT(hcryp, hcryp->pCrypInBuffPtr_saved, hcryp->Size_saved, + hcryp->pCrypOutBuffPtr_saved) != HAL_OK) + { + return HAL_ERROR; + } + } + else + { + if (HAL_CRYP_Decrypt_IT(hcryp, hcryp->pCrypInBuffPtr_saved, hcryp->Size_saved, + hcryp->pCrypOutBuffPtr_saved) != HAL_OK) + { + return HAL_ERROR; + } + } + } + return HAL_OK; +} +#endif /* defined (USE_HAL_CRYP_SUSPEND_RESUME) */ + +/** + * @brief CRYP peripheral parameters storage when processing Interleaved mode . + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param pcont pointer to a CRYP_ContextTypeDef structure where CRYP parameters will be stored. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_SaveContext(CRYP_HandleTypeDef *hcryp, CRYP_ContextTypeDef *pcont) +{ + /* Check the CRYP handle allocation */ + if ((hcryp == NULL) || (pcont == NULL)) + { + return HAL_ERROR; + } + + if (hcryp->State == HAL_CRYP_STATE_READY) + { + /* Save CRYP handle parameters */ + pcont->DataType = (uint32_t)(hcryp->Init.DataType); + pcont->KeySize = (uint32_t)(hcryp->Init.KeySize); + pcont->pKey = hcryp->Init.pKey; + pcont->pInitVect = hcryp->Init.pInitVect; + pcont->Algorithm = (uint32_t)(hcryp->Init.Algorithm); + pcont->DataWidthUnit = (uint32_t)(hcryp->Init.DataWidthUnit); + pcont->KeyIVConfigSkip = (uint32_t)(hcryp->Init.KeyIVConfigSkip); + pcont->KeyMode = (uint32_t)(hcryp->Init.KeyMode); + pcont->Phase = (uint32_t)(hcryp->Phase); + pcont->KeyIVConfig = (uint32_t)(hcryp->KeyIVConfig); + + /* Save CRYP CR register content */ + pcont->CR_Reg = READ_REG(hcryp->Instance->CR); + + /* Save IER register content */ + pcont->IER_Reg = READ_BIT(hcryp->Instance->IER, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE); + + + if ((hcryp->Init.Algorithm == CRYP_AES_CBC) || \ + (hcryp->Init.Algorithm == CRYP_AES_CTR)) + { + /* Save Initialisation Vector registers */ + pcont->IVR0_Reg = READ_REG(hcryp->Instance->IVR0); + pcont->IVR1_Reg = READ_REG(hcryp->Instance->IVR1); + pcont->IVR2_Reg = READ_REG(hcryp->Instance->IVR2); + pcont->IVR3_Reg = READ_REG(hcryp->Instance->IVR3); + } + + /* To load Key for next piece of message */ + hcryp->KeyIVConfig = 0; + + return HAL_OK; + } + else + { + /* Busy error code field */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY; + return HAL_ERROR; + } + +} + +/** + * @brief Restore CRYP parameters needed for Interleaved mode. + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param pcont pointer to a CRYP_ContextTypeDef structure that contains CRYP parameters stored. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_RestoreContext(CRYP_HandleTypeDef *hcryp, CRYP_ContextTypeDef *pcont) +{ + /* Check the CRYP handle allocation */ + if ((hcryp == NULL) || (pcont == NULL)) + { + return HAL_ERROR; + } + + if (hcryp->State == HAL_CRYP_STATE_READY) + { + /* Restore CRYP handle parameters */ + hcryp->Init.DataType = pcont->DataType; + hcryp->Init.KeySize = pcont->KeySize; + hcryp->Init.pKey = pcont->pKey; + hcryp->Init.pInitVect = pcont->pInitVect; + hcryp->Init.Algorithm = pcont->Algorithm; + hcryp->Init.DataWidthUnit = pcont->DataWidthUnit; + hcryp->Init.KeyIVConfigSkip = pcont->KeyIVConfigSkip; + hcryp->Init.KeyMode = pcont->KeyMode; + hcryp->Phase = pcont->Phase; + hcryp->KeyIVConfig = pcont->KeyIVConfig; + + /* Restore CRYP CR register content */ + WRITE_REG(hcryp->Instance->CR, (uint32_t)(pcont->CR_Reg)); + + /* Restore CRYP IER register content */ + WRITE_REG(hcryp->Instance->IER, (uint32_t)(pcont->IER_Reg)); + + if ((hcryp->Init.Algorithm == CRYP_AES_CBC) || \ + (hcryp->Init.Algorithm == CRYP_AES_CTR)) + { + /* Restore Initialisation Vector registers */ + WRITE_REG(hcryp->Instance->IVR0, (uint32_t)(pcont->IVR0_Reg)); + WRITE_REG(hcryp->Instance->IVR1, (uint32_t)(pcont->IVR1_Reg)); + WRITE_REG(hcryp->Instance->IVR2, (uint32_t)(pcont->IVR2_Reg)); + WRITE_REG(hcryp->Instance->IVR3, (uint32_t)(pcont->IVR3_Reg)); + } + return HAL_OK; + } + else + { + /* Busy error code field */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY; + return HAL_ERROR; + } +} + +/** + * @} + */ + +/** @defgroup CRYP_Exported_Functions_Group2 Encryption Decryption functions + * @brief Encryption Decryption functions. + * +@verbatim + ============================================================================== + ##### Encrypt Decrypt functions ##### + ============================================================================== + [..] This section provides API allowing to Encrypt/Decrypt Data following + (+) Standard AES algorithms supported by the peripheral: + - Electronic Code Book(ECB) + - Cipher Block Chaining (CBC) + - Counter mode (CTR) + - Cipher Block Chaining (CBC) + - Counter mode (CTR) + - Galois/counter mode (GCM) + - Counter with Cipher Block Chaining-Message(CCM) + [..] Three processing functions are available: + (+) Polling mode : HAL_CRYP_Encrypt & HAL_CRYP_Decrypt + (+) Interrupt mode : HAL_CRYP_Encrypt_IT & HAL_CRYP_Decrypt_IT + (+) DMA mode : HAL_CRYP_Encrypt_DMA & HAL_CRYP_Decrypt_DMA + +@endverbatim + * @{ + */ + +/* GCM message structure additional details + + ICB + +-------------------------------------------------------+ + | Initialization vector (IV) | Counter | + |----------------|----------------|-----------|---------| + 127 95 63 31 0 + + + Bit Number Register Contents + ---------- --------------- ----------- + 127 ...96 CRYP_IV1R[31:0] ICB[127:96] + 95 ...64 CRYP_IV1L[31:0] B0[95:64] + 63 ... 32 CRYP_IV0R[31:0] ICB[63:32] + 31 ... 0 CRYP_IV0L[31:0] ICB[31:0], where 32-bit counter= 0x2 + + + GCM last block definition + +-------------------------------------------------------------------+ + | Bit[0] | Bit[32] | Bit[64] | Bit[96] | + |-----------|--------------------|-----------|----------------------| + | 0x0 | Header length[31:0]| 0x0 | Payload length[31:0] | + |-----------|--------------------|-----------|----------------------| +*/ + +/* CCM message blocks description + + (##) B0 block : According to NIST Special Publication 800-38C, + The first block B0 is formatted as follows, where l(m) is encoded in + most-significant-byte first order: + + Octet Number Contents + ------------ --------- + 0 Flags + 1 ... 15-q Nonce N + 16-q ... 15 Q + + the Flags field is formatted as follows: + + Bit Number Contents + ---------- ---------------------- + 7 Reserved (always zero) + 6 Adata + 5 ... 3 (t-2)/2 + 2 ... 0 [q-1]3 + + - Q: a bit string representation of the octet length of P (plaintext) + - q The octet length of the binary representation of the octet length of the payload + - A nonce (N), n The octet length of the where n+q=15. + - Flags: most significant octet containing four flags for control information, + - t The octet length of the MAC. + (##) B1 block (header) : associated data length(a) concatenated with Associated Data (A) + the associated data length expressed in bytes (a) defined as below: + - If 0 < a < 216-28, then it is encoded as [a]16, i.e. two octets + - If 216-28 < a < 232, then it is encoded as 0xff || 0xfe || [a]32, i.e. six octets + - If 232 < a < 264, then it is encoded as 0xff || 0xff || [a]64, i.e. ten octets + (##) CTRx block : control blocks + - Generation of CTR1 from first block B0 information : + equal to B0 with first 5 bits zeroed and most significant bits storing octet + length of P also zeroed, then incremented by one + + Bit Number Register Contents + ---------- --------------- ----------- + 127 ...96 CRYP_IV1R[31:0] B0[127:96], where Q length bits are set to 0, except for + bit 0 that is set to 1 + 95 ...64 CRYP_IV1L[31:0] B0[95:64] + 63 ... 32 CRYP_IV0R[31:0] B0[63:32] + 31 ... 0 CRYP_IV0L[31:0] B0[31:0], where flag bits set to 0 + + - Generation of CTR0: same as CTR1 with bit[0] set to zero. +*/ + +/** + * @brief Encryption mode. + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param pInput Pointer to the input buffer (plaintext) + * @param Size Length of the plaintext buffer either in word or in byte, according to DataWidthUnit + * @param pOutput Pointer to the output buffer(ciphertext) + * @param Timeout Specify Timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *pInput, uint16_t Size, uint32_t *pOutput, + uint32_t Timeout) +{ + uint32_t algo; + HAL_StatusTypeDef status; +#ifdef USE_FULL_ASSERT + uint32_t algo_assert = (hcryp->Instance->CR) & AES_CR_CHMOD; + + /* Check input buffer size */ + assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size)); +#endif /* USE_FULL_ASSERT */ + + if (hcryp->State == HAL_CRYP_STATE_READY) + { + /* Change state Busy */ + hcryp->State = HAL_CRYP_STATE_BUSY; + __HAL_LOCK(hcryp); + + /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters */ + hcryp->CrypInCount = 0U; + hcryp->CrypOutCount = 0U; + hcryp->pCrypInBuffPtr = pInput; + hcryp->pCrypOutBuffPtr = pOutput; + + /* Calculate Size parameter in Byte */ + if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD) + { + hcryp->Size = Size * 4U; + } + else + { + hcryp->Size = Size; + } + +#if !defined(SAES) + /* Set the operating mode */ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT); +#else + if (hcryp->Instance == AES) + { + /* Set the operating mode */ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT); + } + else + { + /* Set the operating mode and normal key selection */ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE | AES_CR_KMOD, CRYP_OPERATINGMODE_ENCRYPT | CRYP_KEYMODE_NORMAL); + } +#endif /* !SAES */ + /* Algo get algorithm selected */ + algo = hcryp->Instance->CR & AES_CR_CHMOD; + + switch (algo) + { + case CRYP_AES_ECB: + case CRYP_AES_CBC: + case CRYP_AES_CTR: + /* AES encryption */ + status = CRYP_AES_Encrypt(hcryp, Timeout); + break; + + case CRYP_AES_GCM_GMAC: + /* AES GCM encryption */ + status = CRYP_AESGCM_Process(hcryp, Timeout); + break; + + case CRYP_AES_CCM: + /* AES CCM encryption */ + status = CRYP_AESCCM_Process(hcryp, Timeout); + break; + + default: + hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Change the CRYP peripheral state */ + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + } + } + else + { + /* Busy error code field */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY; + status = HAL_ERROR; + } + return status; +} + +/** + * @brief Decryption mode. + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param pInput Pointer to the input buffer (ciphertext ) + * @param Size Length of the input buffer either in word or in byte, according to DataWidthUnit + * @param pOutput Pointer to the output buffer(plaintext) + * @param Timeout Specify Timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *pInput, uint16_t Size, uint32_t *pOutput, + uint32_t Timeout) +{ + HAL_StatusTypeDef status; + uint32_t algo; +#ifdef USE_FULL_ASSERT + uint32_t algo_assert = (hcryp->Instance->CR) & AES_CR_CHMOD; + + /* Check input buffer size */ + assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size)); +#endif /* USE_FULL_ASSERT */ + + if (hcryp->State == HAL_CRYP_STATE_READY) + { + /* Change state Busy */ + hcryp->State = HAL_CRYP_STATE_BUSY; + __HAL_LOCK(hcryp); + + /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/ + hcryp->CrypInCount = 0U; + hcryp->CrypOutCount = 0U; + hcryp->pCrypInBuffPtr = pInput; + hcryp->pCrypOutBuffPtr = pOutput; + + /* Calculate Size parameter in Byte*/ + if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD) + { + hcryp->Size = Size * 4U; + } + else + { + hcryp->Size = Size; + } + + /* Set Decryption operating mode*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); + + /* algo get algorithm selected */ + algo = hcryp->Instance->CR & AES_CR_CHMOD; + + switch (algo) + { + case CRYP_AES_ECB: + case CRYP_AES_CBC: + case CRYP_AES_CTR: + /* AES decryption */ + status = CRYP_AES_Decrypt(hcryp, Timeout); + break; + + case CRYP_AES_GCM_GMAC: + /* AES GCM decryption */ + status = CRYP_AESGCM_Process(hcryp, Timeout); + break; + + case CRYP_AES_CCM: + /* AES CCM decryption */ + status = CRYP_AESCCM_Process(hcryp, Timeout); + break; + + default: + hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Change the CRYP peripheral state */ + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + } + } + else + { + /* Busy error code field */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY; + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Encryption in interrupt mode. + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param pInput Pointer to the input buffer (plaintext) + * @param Size Length of the input buffer either in word or in byte, according to DataWidthUnit + * @param pOutput Pointer to the output buffer(ciphertext) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *pInput, uint16_t Size, uint32_t *pOutput) +{ + HAL_StatusTypeDef status; + uint32_t algo; +#ifdef USE_FULL_ASSERT + uint32_t algo_assert = (hcryp->Instance->CR) & AES_CR_CHMOD; + + /* Check input buffer size */ + assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size)); +#endif /* USE_FULL_ASSERT */ + + if (hcryp->State == HAL_CRYP_STATE_READY) + { + /* Change state Busy */ + hcryp->State = HAL_CRYP_STATE_BUSY; + __HAL_LOCK(hcryp); + + /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/ +#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) + if (hcryp->ResumingFlag == 1U) + { + hcryp->ResumingFlag = 0U; + if (hcryp->Phase != CRYP_PHASE_HEADER_SUSPENDED) + { + hcryp->CrypInCount = (uint16_t) hcryp->CrypInCount_saved; + hcryp->CrypOutCount = (uint16_t) hcryp->CrypOutCount_saved; + } + else + { + hcryp->CrypInCount = 0U; + hcryp->CrypOutCount = 0U; + } + } + else +#endif /* USE_HAL_CRYP_SUSPEND_RESUME */ + { + hcryp->CrypInCount = 0U; + hcryp->CrypOutCount = 0U; + } + + hcryp->pCrypInBuffPtr = pInput; + hcryp->pCrypOutBuffPtr = pOutput; + + /* Calculate Size parameter in Byte*/ + if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD) + { + hcryp->Size = Size * 4U; + } + else + { + hcryp->Size = Size; + } + + /* Set encryption operating mode*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT); + + /* algo get algorithm selected */ + algo = hcryp->Instance->CR & AES_CR_CHMOD; + + switch (algo) + { + + case CRYP_AES_ECB: + case CRYP_AES_CBC: + case CRYP_AES_CTR: + /* AES encryption */ + status = CRYP_AES_Encrypt_IT(hcryp); + break; + + case CRYP_AES_GCM_GMAC: + /* AES GCM encryption */ + status = CRYP_AESGCM_Process_IT(hcryp); + break; + + case CRYP_AES_CCM: + /* AES CCM encryption */ + status = CRYP_AESCCM_Process_IT(hcryp); + break; + + default: + hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; + status = HAL_ERROR; + break; + } + } + else + { + /* Busy error code field */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY; + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Decryption in interrupt mode. + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param pInput Pointer to the input buffer (ciphertext ) + * @param Size Length of the input buffer either in word or in byte, according to DataWidthUnit + * @param pOutput Pointer to the output buffer(plaintext) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *pInput, uint16_t Size, uint32_t *pOutput) +{ + HAL_StatusTypeDef status; + uint32_t algo; +#ifdef USE_FULL_ASSERT + uint32_t algo_assert = (hcryp->Instance->CR) & AES_CR_CHMOD; + + /* Check input buffer size */ + assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size)); +#endif /* USE_FULL_ASSERT */ + + if (hcryp->State == HAL_CRYP_STATE_READY) + { + /* Change state Busy */ + hcryp->State = HAL_CRYP_STATE_BUSY; + __HAL_LOCK(hcryp); + + /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/ +#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) + if (hcryp->ResumingFlag == 1U) + { + hcryp->ResumingFlag = 0U; + if (hcryp->Phase != CRYP_PHASE_HEADER_SUSPENDED) + { + hcryp->CrypInCount = (uint16_t) hcryp->CrypInCount_saved; + hcryp->CrypOutCount = (uint16_t) hcryp->CrypOutCount_saved; + } + else + { + hcryp->CrypInCount = 0U; + hcryp->CrypOutCount = 0U; + } + } + else +#endif /* USE_HAL_CRYP_SUSPEND_RESUME */ + { + hcryp->CrypInCount = 0U; + hcryp->CrypOutCount = 0U; + } + hcryp->pCrypInBuffPtr = pInput; + hcryp->pCrypOutBuffPtr = pOutput; + + /* Calculate Size parameter in Byte*/ + if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD) + { + hcryp->Size = Size * 4U; + } + else + { + hcryp->Size = Size; + } + + /* Set decryption operating mode*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); + + /* algo get algorithm selected */ + algo = hcryp->Instance->CR & AES_CR_CHMOD; + + switch (algo) + { + case CRYP_AES_ECB: + case CRYP_AES_CBC: + case CRYP_AES_CTR: + /* AES decryption */ + status = CRYP_AES_Decrypt_IT(hcryp); + break; + + case CRYP_AES_GCM_GMAC: + /* AES GCM decryption */ + status = CRYP_AESGCM_Process_IT(hcryp); + break; + + case CRYP_AES_CCM: + /* AES CCM decryption */ + status = CRYP_AESCCM_Process_IT(hcryp); + break; + + default: + hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; + status = HAL_ERROR; + break; + } + } + else + { + /* Busy error code field */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY; + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Encryption in DMA mode. + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param pInput Pointer to the input buffer (plaintext) + * @param Size Length of the input buffer either in word or in byte, according to DataWidthUnit + * @param pOutput Pointer to the output buffer(ciphertext) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *pInput, uint16_t Size, uint32_t *pOutput) +{ + HAL_StatusTypeDef status; +#if defined(SAES) + uint32_t count; +#endif /* SAES */ + uint32_t algo; + uint32_t dokeyivconfig = 1U; /* By default, carry out peripheral Key and IV configuration */ +#ifdef USE_FULL_ASSERT + uint32_t algo_assert = (hcryp->Instance->CR) & AES_CR_CHMOD; + + /* Check input buffer size */ + assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size)); +#endif /* USE_FULL_ASSERT */ + + if (hcryp->State == HAL_CRYP_STATE_READY) + { + /* Change state Busy */ + hcryp->State = HAL_CRYP_STATE_BUSY; + __HAL_LOCK(hcryp); + + /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/ + hcryp->CrypInCount = 0U; + hcryp->CrypOutCount = 0U; + hcryp->pCrypInBuffPtr = pInput; + hcryp->pCrypOutBuffPtr = pOutput; + + /* Calculate Size parameter in Byte*/ + if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD) + { + hcryp->Size = Size * 4U; + } + else + { + hcryp->Size = Size; + } + + /* Set encryption operating mode*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT); + + /* algo get algorithm selected */ + algo = hcryp->Instance->CR & AES_CR_CHMOD; + + switch (algo) + { + case CRYP_AES_ECB: + case CRYP_AES_CBC: + case CRYP_AES_CTR: + if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) + { + if (hcryp->KeyIVConfig == 1U) + { + /* If the Key and IV configuration has to be done only once + and if it has already been done, skip it */ + dokeyivconfig = 0U; + } + else + { + /* If the Key and IV configuration has to be done only once + and if it has not been done already, do it and set KeyIVConfig + to keep track it won't have to be done again next time */ + hcryp->KeyIVConfig = 1U; + } + } + + if ((dokeyivconfig == 1U) && (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)) + { +#if !defined(SAES) + CRYP_SetKey(hcryp, hcryp->Init.KeySize); +#else + if (hcryp->Instance == AES) + { + /* Set the Key */ + if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED) + { + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + else /* After sharing the key, AES should set KMOD[1:0] to 00.*/ + { + hcryp->Instance->CR &= ~CRYP_KEYMODE_SHARED; + } + } + else + { + /* We should re-write Key, in the case where we change key after first operation */ + if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL)) + { + /* Set the Key */ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + /* Wait for KEYVALID flag to be set */ + count = CRYP_TIMEOUT_KEYPREPARATION; + do + { + count--; + if (count == 0U) + { + /* Disable the SAES peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_KEYVALID)); + } +#endif /* SAES */ + /* Set the Initialization Vector */ + if (hcryp->Init.Algorithm != CRYP_AES_ECB) + { + CRYP_SetIV(hcryp); + } + } /* If (dokeyivconfig == 1U) */ + + /* Peripheral Key configuration to not do, IV to configure for CBC */ + if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYNOCONFIG) + { + if (hcryp->Init.Algorithm != CRYP_AES_ECB) + { + /* Set the Initialization Vector */ + CRYP_SetIV(hcryp); + } + } + + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; + + /* Start DMA process transfer for AES */ + CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size), (uint32_t)(hcryp->pCrypOutBuffPtr)); + status = HAL_OK; + break; + + case CRYP_AES_GCM_GMAC: + /* AES GCM encryption */ + status = CRYP_AESGCM_Process_DMA(hcryp); + break; + + case CRYP_AES_CCM: + /* AES CCM encryption */ + status = CRYP_AESCCM_Process_DMA(hcryp); + break; + + default: + hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; + status = HAL_ERROR; + break; + } + } + else + { + /* Busy error code field */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY; + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Decryption in DMA mode. + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param pInput Pointer to the input buffer (ciphertext ) + * @param Size Length of the input buffer either in word or in byte, according to DataWidthUnit + * @param pOutput Pointer to the output buffer(plaintext) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *pInput, uint16_t Size, uint32_t *pOutput) +{ + HAL_StatusTypeDef status; + uint32_t algo; +#ifdef USE_FULL_ASSERT + uint32_t algo_assert = (hcryp->Instance->CR) & AES_CR_CHMOD; + + /* Check input buffer size */ + assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size)); +#endif /* USE_FULL_ASSERT */ + + if (hcryp->State == HAL_CRYP_STATE_READY) + { + + /* Change state Busy */ + hcryp->State = HAL_CRYP_STATE_BUSY; + __HAL_LOCK(hcryp); + + /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/ + hcryp->CrypInCount = 0U; + hcryp->CrypOutCount = 0U; + hcryp->pCrypInBuffPtr = pInput; + hcryp->pCrypOutBuffPtr = pOutput; + + /* Calculate Size parameter in Byte*/ + if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD) + { + hcryp->Size = Size * 4U; + } + else + { + hcryp->Size = Size; + } + + /* Set decryption operating mode*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); + + /* algo get algorithm selected */ + algo = hcryp->Instance->CR & AES_CR_CHMOD; + + switch (algo) + { + case CRYP_AES_ECB: + case CRYP_AES_CBC: + case CRYP_AES_CTR: + /* AES decryption */ + status = CRYP_AES_Decrypt_DMA(hcryp); + break; + + case CRYP_AES_GCM_GMAC: + /* AES GCM decryption */ + status = CRYP_AESGCM_Process_DMA(hcryp); + break; + + case CRYP_AES_CCM: + /* AES CCM decryption */ + status = CRYP_AESCCM_Process_DMA(hcryp); + break; + + default: + hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; + status = HAL_ERROR; + break; + } + } + else + { + /* Busy error code field */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY; + status = HAL_ERROR; + } + return status; +} + +/** + * @} + */ + +/** @defgroup CRYP_Exported_Functions_Group3 CRYP IRQ handler management + * @brief CRYP IRQ handler. + * +@verbatim + ============================================================================== + ##### CRYP IRQ handler management ##### + ============================================================================== +[..] This section provides CRYP IRQ handler and callback functions. + (+) HAL_CRYP_IRQHandler CRYP interrupt request + (+) HAL_CRYP_InCpltCallback input data transfer complete callback + (+) HAL_CRYP_OutCpltCallback output data transfer complete callback + (+) HAL_CRYP_ErrorCallback CRYP error callback + (+) HAL_CRYP_GetState return the CRYP state + (+) HAL_CRYP_GetError return the CRYP error code +@endverbatim + * @{ + */ + +/** + * @brief This function handles cryptographic interrupt request. + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @retval None + */ +void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp) +{ + /* Check if Read or write error occurred */ + if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_RWEIE) != RESET) + { + /* If write Error occurred */ + if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_WRERR) != RESET) + { + hcryp->ErrorCode |= HAL_CRYP_ERROR_WRITE; + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_RWEIF); + } + /* If read Error occurred */ + if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_RDERR) != RESET) + { + hcryp->ErrorCode |= HAL_CRYP_ERROR_READ; + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_RWEIF); + } + } + /* Check if Key error occurred */ + if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_KEIE) != RESET) + { + if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_KEIF) != RESET) + { + hcryp->ErrorCode |= HAL_CRYP_ERROR_KEY; + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_KEIF); + /*Call weak error callback*/ + HAL_CRYP_ErrorCallback(hcryp); + } + } + + if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_CCF) != RESET) + { + if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_CCFIE) != RESET) + { + /* Clear computation complete flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + + if ((hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC) || (hcryp->Init.Algorithm == CRYP_AES_CCM)) + { + /* if header phase */ + if ((hcryp->Instance->CR & CRYP_PHASE_HEADER) == CRYP_PHASE_HEADER) + { + CRYP_GCMCCM_SetHeaderPhase_IT(hcryp); + } + else /* if payload phase */ + { + CRYP_GCMCCM_SetPayloadPhase_IT(hcryp); + } + } + else /* AES Algorithm ECB,CBC or CTR*/ + { + CRYP_AES_IT(hcryp); + } + } + } +} + +/** + * @brief Return the CRYP error code. + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for the CRYP peripheral + * @retval CRYP error code + */ +uint32_t HAL_CRYP_GetError(const CRYP_HandleTypeDef *hcryp) +{ + return hcryp->ErrorCode; +} + +/** + * @brief Returns the CRYP state. + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module. + * @retval HAL state + */ +HAL_CRYP_STATETypeDef HAL_CRYP_GetState(const CRYP_HandleTypeDef *hcryp) +{ + return hcryp->State; +} + +/** + * @brief Input FIFO transfer completed callback. + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module. + * @retval None + */ +__weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcryp); + + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_CRYP_InCpltCallback can be implemented in the user file + */ +} + +/** + * @brief Output FIFO transfer completed callback. + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module. + * @retval None + */ +__weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcryp); + + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_CRYP_OutCpltCallback can be implemented in the user file + */ +} + +/** + * @brief CRYP error callback. + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module. + * @retval None + */ +__weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcryp); + + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_CRYP_ErrorCallback can be implemented in the user file + */ +} +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @addtogroup CRYP_Private_Functions + * @{ + */ + +/** + * @brief Encryption in ECB/CBC & CTR Algorithm with AES Standard + * @param hcryp pointer to a CRYP_HandleTypeDef structure + * @param Timeout specify Timeout value + * @retval HAL status + */ +static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) +{ + uint16_t incount; /* Temporary CrypInCount Value */ + uint16_t outcount; /* Temporary CrypOutCount Value */ + uint32_t dokeyivconfig = 1U; /* By default, carry out peripheral Key and IV configuration */ +#if defined(SAES) + uint32_t tickstart; +#endif /* SEAS */ + + if ((hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) || (hcryp->Init.KeyIVConfigSkip == CRYP_IVCONFIG_ONCE)) + { + if (hcryp->KeyIVConfig == 1U) + { + /* If the Key and IV configuration has to be done only once + and if it has already been done, skip it */ + dokeyivconfig = 0U; + } + else + { + /* If the Key and IV configuration has to be done only once + and if it has not been done already, do it and set KeyIVConfig + to keep track it won't have to be done again next time */ + hcryp->KeyIVConfig = 1U; + } + } + + if (dokeyivconfig == 1U) + { + if ((hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) || \ + (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ALWAYS)) + { +#if !defined(SAES) + CRYP_SetKey(hcryp, hcryp->Init.KeySize); +#else + if (hcryp->Instance == AES) + { + /* Set the Key */ + if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED) + { + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + else /* After sharing the key, AES should set KMOD[1:0] to 00.*/ + { + hcryp->Instance->CR &= ~CRYP_KEYMODE_SHARED; + } + } + else + { + /* We should re-write Key, in the case where we change key after first operation */ + if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL)) + { + /* Set the Key */ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + /* Get tick */ + tickstart = HAL_GetTick(); + + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_KEYVALID)) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } + } + } +#endif /* SAES */ + if (hcryp->Init.Algorithm != CRYP_AES_ECB) + { + /* Set the Initialization Vector */ + CRYP_SetIV(hcryp); + } + } + /* key & IV configuration for CBC and CTR in interleave mode */ + if (hcryp->Init.KeyIVConfigSkip == CRYP_IVCONFIG_ONCE) + { + /* Set the Key */ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + if (hcryp->Init.Algorithm != CRYP_AES_ECB) + { + /* Set the Initialization Vector*/ + CRYP_SetIV(hcryp); + } + } + } /* If (dokeyivconfig == 1U) */ + else + { + /* interleave mode Key configuration */ + if (hcryp->Init.KeyIVConfigSkip == CRYP_IVCONFIG_ONCE) + { + /* Set the Key */ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + } + /* Peripheral Key configuration to not do, IV to configure for CBC */ + if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYNOCONFIG) + { + if (hcryp->Init.Algorithm != CRYP_AES_ECB) + { + /* Set the Initialization Vector*/ + CRYP_SetIV(hcryp); + } + } + + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; + + /* Enable CRYP */ + __HAL_CRYP_ENABLE(hcryp); + + incount = hcryp->CrypInCount; + outcount = hcryp->CrypOutCount; + while ((incount < (hcryp->Size / 4U)) && (outcount < (hcryp->Size / 4U))) + { + /* Write plain data and get cipher data */ + CRYP_AES_ProcessData(hcryp, Timeout); + incount = hcryp->CrypInCount; + outcount = hcryp->CrypOutCount; + } + + /* Disable CRYP */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Encryption in ECB/CBC & CTR mode with AES Standard using interrupt mode + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @retval HAL status + */ +static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp) +{ +#if defined(SAES) + uint32_t count; +#endif /* SAES */ + uint32_t dokeyivconfig = 1U; /* By default, carry out peripheral Key and IV configuration */ + + if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) + { + if (hcryp->KeyIVConfig == 1U) + { + /* If the Key and IV configuration has to be done only once + and if it has already been done, skip it */ + dokeyivconfig = 0U; + } + else + { + /* If the Key and IV configuration has to be done only once + and if it has not been done already, do it and set KeyIVConfig + to keep track it won't have to be done again next time */ + hcryp->KeyIVConfig = 1U; + } + } + + if ((dokeyivconfig == 1U) && (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG)) + { +#if !defined(SAES) + CRYP_SetKey(hcryp, hcryp->Init.KeySize); +#else + if (hcryp->Instance == AES) + { + /* Set the Key */ + if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED) + { + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + else /*after sharing the key, AES should set KMOD[1:0] to 00.*/ + { + hcryp->Instance->CR &= ~CRYP_KEYMODE_SHARED; + } + } + else + { + /* we should re-write Key, in the case where we change key after first operation*/ + if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL)) + { + /* Set the Key */ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + /* Wait for KEYVALID flag to be set */ + count = CRYP_TIMEOUT_KEYPREPARATION; + do + { + count--; + if (count == 0U) + { + /* Disable the SAES peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_KEYVALID)); + } +#endif /* SAES */ + if (hcryp->Init.Algorithm != CRYP_AES_ECB) + { + /* Set the Initialization Vector*/ + CRYP_SetIV(hcryp); + } + } /* if (dokeyivconfig == 1U) */ + /* Peripheral Key configuration to not do, IV to configure for CBC */ + if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYNOCONFIG) + { + if (hcryp->Init.Algorithm != CRYP_AES_ECB) + { + /* Set the Initialization Vector*/ + CRYP_SetIV(hcryp); + } + } + + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; + + if (hcryp->Size != 0U) + { + /* Enable CRYP */ + __HAL_CRYP_ENABLE(hcryp); + + /* Write the input block in the IN FIFO */ + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + + /* Enable computation complete flag and Key, Read and Write error interrupts */ + __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE); + } + else + { + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + } + + return HAL_OK; +} + +/** + * @brief Decryption in ECB/CBC & CTR mode with AES Standard + * @param hcryp pointer to a CRYP_HandleTypeDef structure + * @param Timeout Specify Timeout value + * @retval HAL status + */ +static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) +{ + uint16_t incount; /* Temporary CrypInCount Value */ + uint16_t outcount; /* Temporary CrypOutCount Value */ + uint32_t dokeyivconfig = 1U; /* By default, carry out peripheral Key and IV configuration */ + + if ((hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) || (hcryp->Init.KeyIVConfigSkip == CRYP_IVCONFIG_ONCE)) + { + if (hcryp->KeyIVConfig == 1U) + { + /* If the Key and IV configuration has to be done only once + and if it has already been done, skip it */ + dokeyivconfig = 0U; + } + else + { + /* If the Key and IV configuration has to be done only once + and if it has not been done already, do it and set KeyIVConfig + to keep track it won't have to be done again next time */ + hcryp->KeyIVConfig = 1U; + } + } + + if (dokeyivconfig == 1U) + { +#if !defined(SAES) + /* Key preparation for ECB/CBC */ + if (hcryp->Init.Algorithm != CRYP_AES_CTR) /*ECB or CBC*/ + { + /* key preparation for decryption, operating mode 2*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION); + + /* Set the Key */ + if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG) + { + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + + /* Enable CRYP */ + __HAL_CRYP_ENABLE(hcryp); + + /* Wait for CCF flag to be raised */ + if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + { + return HAL_ERROR; + } + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + + /* Return to decryption operating mode(Mode 3)*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); + } + else /*Algorithm CTR */ + { + /* Set the Key */ + if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG) + { + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + } +#else + if (hcryp->Instance == AES) + { + /* Key preparation for ECB/CBC */ + if (hcryp->Init.Algorithm != CRYP_AES_CTR) /*ECB or CBC*/ + { + /* key preparation for decryption, operating mode 2*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_KMOD, CRYP_KEYMODE_NORMAL); + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION); + + /* Set the Key */ + if ((hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) || \ + (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ALWAYS)) + { + if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED) + { + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + else /*after sharing the key, AES should set KMOD[1:0] to 00.*/ + { + hcryp->Instance->CR &= ~CRYP_KEYMODE_SHARED; + } + } + + /* interleave mode Key configuration */ + else if (hcryp->Init.KeyIVConfigSkip == CRYP_IVCONFIG_ONCE) + { + /* Set the Key */ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + else + { + /* Nothing to do */ + } + + /* Enable CRYP */ + __HAL_CRYP_ENABLE(hcryp); + + /* Wait for CCF flag to be raised */ + if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + { + return HAL_ERROR; + } + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + + /* Return to decryption operating mode(Mode 3)*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); + } + else /*Algorithm CTR */ + { + /* Set the Key */ + if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG) + { + if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED) + { + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + else /*after sharing the key, AES should set KMOD[1:0] to 00.*/ + { + hcryp->Instance->CR &= ~CRYP_KEYMODE_SHARED; + } + } + } + } + else /*SAES*/ + { + if (hcryp->Init.Algorithm != CRYP_AES_CTR) /*ECB or CBC*/ + { + /* key preparation for decryption, operating mode 2*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION); + + /* we should re-write Key, in the case where we change key after first operation*/ + if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL)) + { + if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG) + { + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + } + + /* Enable SAES */ + __HAL_CRYP_ENABLE(hcryp); + + /* Wait for CCF flag to be raised */ + if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + { + return HAL_ERROR; + } + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + + /* End of Key preparation for ECB/CBC */ + /* Return to decryption operating mode(Mode 3)*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); + } + else /*Algorithm CTR */ + { + /* we should re-write Key, in the case where we change key after first operation*/ + if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL)) + { + if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG) + { + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + } + } + } +#endif /* !defined(SAES) */ + /* Set IV */ + if (hcryp->Init.Algorithm != CRYP_AES_ECB) + { + /* Set the Initialization Vector*/ + CRYP_SetIV(hcryp); + } + } /* if (dokeyivconfig == 1U) */ + + else /* if (dokeyivconfig == 0U) */ + { + /* interleave mode Key configuration */ + if (hcryp->Init.KeyIVConfigSkip == CRYP_IVCONFIG_ONCE) + { + if (hcryp->Instance == AES) + { + /* Key preparation for ECB/CBC */ + if (hcryp->Init.Algorithm != CRYP_AES_CTR) /*ECB or CBC*/ + { + /* key preparation for decryption, operating mode 2*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_KMOD, CRYP_KEYMODE_NORMAL); + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION); + + /* Set the Key */ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + + /* Enable CRYP */ + __HAL_CRYP_ENABLE(hcryp); + + /* Wait for CCF flag to be raised */ + if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + { + return HAL_ERROR; + } + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + + /* Return to decryption operating mode(Mode 3)*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); + } + else /*Algorithm CTR */ + { + /* Set the Key */ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + + } + } + } + + } + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; + + /* Enable CRYP */ + __HAL_CRYP_ENABLE(hcryp); + + incount = hcryp->CrypInCount; + outcount = hcryp->CrypOutCount; + while ((incount < (hcryp->Size / 4U)) && (outcount < (hcryp->Size / 4U))) + { + /* Write plain data and get cipher data */ + CRYP_AES_ProcessData(hcryp, Timeout); + incount = hcryp->CrypInCount; + outcount = hcryp->CrypOutCount; + } + /* Disable CRYP */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_READY; + + return HAL_OK; +} +/** + * @brief Decryption in ECB/CBC & CTR mode with AES Standard using interrupt mode + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @retval HAL status + */ +static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp) +{ + uint32_t count; + uint32_t dokeyivconfig = 1U; /* By default, carry out peripheral Key and IV configuration */ + + if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) + { + if (hcryp->KeyIVConfig == 1U) + { + /* If the Key and IV configuration has to be done only once + and if it has already been done, skip it */ + dokeyivconfig = 0U; + } + else + { + /* If the Key and IV configuration has to be done only once + and if it has not been done already, do it and set KeyIVConfig + to keep track it won't have to be done again next time */ + hcryp->KeyIVConfig = 1U; + } + } + + if (dokeyivconfig == 1U) + { +#if !defined(SAES) + /* Key preparation for ECB/CBC */ + if (hcryp->Init.Algorithm != CRYP_AES_CTR) + { + /* key preparation for decryption, operating mode 2*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION); + + /* Set the Key */ + if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG) + { + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + + /* Enable CRYP */ + __HAL_CRYP_ENABLE(hcryp); + + /* Wait for CCF flag to be raised */ + count = CRYP_TIMEOUT_KEYPREPARATION; + do + { + count--; + if (count == 0U) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + + /* Return to decryption operating mode(Mode 3)*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); + } + else /*Algorithm CTR */ + { + if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG) + { + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + } +#else + if (hcryp->Instance == AES) + { + /* Key preparation for ECB/CBC */ + if (hcryp->Init.Algorithm != CRYP_AES_CTR) + { + /* key preparation for decryption, operating mode 2*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_KMOD, CRYP_KEYMODE_NORMAL); + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION); + + /* Set the Key */ + if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG) + { + if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED) + { + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + else /*after sharing the key, AES should set KMOD[1:0] to 00.*/ + { + hcryp->Instance->CR &= ~CRYP_KEYMODE_SHARED; + } + } + + /* Enable CRYP */ + __HAL_CRYP_ENABLE(hcryp); + + /* Wait for CCF flag to be raised */ + count = CRYP_TIMEOUT_KEYPREPARATION; + do + { + count--; + if (count == 0U) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } while (HAL_IS_BIT_CLR(hcryp->Instance->ISR, AES_ISR_CCF)); + + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + + /* Return to decryption operating mode(Mode 3)*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); + } + + else /*Algorithm CTR */ + { + if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG) + { + if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED) + { + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + else /*after sharing the key, AES should set KMOD[1:0] to 00.*/ + { + hcryp->Instance->CR &= ~CRYP_KEYMODE_SHARED; + } + } + } + } + else /*SAES*/ + { + /* Key preparation for ECB/CBC */ + if (hcryp->Init.Algorithm != CRYP_AES_CTR) + { + /* key preparation for decryption, operating mode 2*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION); + + /* we should re-write Key, in the case where we change key after first operation*/ + if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL)) + { + if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG) + { + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + } + /* Enable SAES */ + __HAL_CRYP_ENABLE(hcryp); + + /* Wait for CCF flag to be raised */ + count = CRYP_TIMEOUT_KEYPREPARATION; + do + { + count--; + if (count == 0U) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } while (HAL_IS_BIT_CLR(hcryp->Instance->ISR, AES_ISR_CCF)); + + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + + /* End of Key preparation for ECB/CBC */ + /* Return to decryption operating mode(Mode 3)*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); + } + else /*Algorithm CTR */ + { + /* we should re-write Key, in the case where we change key after first operation*/ + if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL)) + { + if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG) + { + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + } + } + } +#endif /* SAES */ + /* Set IV */ + if (hcryp->Init.Algorithm != CRYP_AES_ECB) + { + /* Set the Initialization Vector*/ + CRYP_SetIV(hcryp); + } + } /* if (dokeyivconfig == 1U) */ + + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; + if (hcryp->Size != 0U) + { + /* Enable CRYP */ + __HAL_CRYP_ENABLE(hcryp); + + /* Write the input block in the IN FIFO */ + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + + /* Enable computation complete flag and error interrupts */ + __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE); + } + else + { + __HAL_UNLOCK(hcryp); + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_READY; + } + + return HAL_OK; +} +/** + * @brief Decryption in ECB/CBC & CTR mode with AES Standard using DMA mode + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @retval HAL status + */ +static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp) +{ + uint32_t count; + uint32_t dokeyivconfig = 1U; /* By default, carry out peripheral Key and IV configuration */ + + if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) + { + if (hcryp->KeyIVConfig == 1U) + { + /* If the Key and IV configuration has to be done only once + and if it has already been done, skip it */ + dokeyivconfig = 0U; + } + else + { + /* If the Key and IV configuration has to be done only once + and if it has not been done already, do it and set KeyIVConfig + to keep track it won't have to be done again next time */ + hcryp->KeyIVConfig = 1U; + } + } + + if (dokeyivconfig == 1U) + { +#if !defined(SAES) + /* Key preparation for ECB/CBC */ + if (hcryp->Init.Algorithm != CRYP_AES_CTR) + { + /* key preparation for decryption, operating mode 2*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION); + + /* Set the Key */ + if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG) + { + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + + /* Enable CRYP */ + __HAL_CRYP_ENABLE(hcryp); + + /* Wait for CCF flag to be raised */ + count = CRYP_TIMEOUT_KEYPREPARATION; + do + { + count--; + if (count == 0U) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + + /* Return to decryption operating mode(Mode 3)*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); + } + else /*Algorithm CTR */ + { + /* Set the Key */ + if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG) + { + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + } +#else + if (hcryp->Instance == AES) + { + /* Key preparation for ECB/CBC */ + if (hcryp->Init.Algorithm != CRYP_AES_CTR) + { + /* key preparation for decryption, operating mode 2*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_KMOD, CRYP_KEYMODE_NORMAL); + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION); + + /* Set the Key */ + if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG) + { + if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED) + { + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + else /*after sharing the key, AES should set KMOD[1:0] to 00.*/ + { + hcryp->Instance->CR &= ~CRYP_KEYMODE_SHARED; + } + } + + /* Enable CRYP */ + __HAL_CRYP_ENABLE(hcryp); + + /* Wait for CCF flag to be raised */ + count = CRYP_TIMEOUT_KEYPREPARATION; + do + { + count--; + if (count == 0U) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } while (HAL_IS_BIT_CLR(hcryp->Instance->ISR, AES_ISR_CCF)); + + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + + /* Return to decryption operating mode(Mode 3)*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); + } + else /*Algorithm CTR */ + { + /* Set the Key */ + if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG) + { + if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED) + { + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + else /*after sharing the key, AES should set KMOD[1:0] to 00.*/ + { + hcryp->Instance->CR &= ~CRYP_KEYMODE_SHARED; + } + } + } + } + else /*SAES*/ + { + /* Key preparation for ECB/CBC */ + if (hcryp->Init.Algorithm != CRYP_AES_CTR) + { + /* key preparation for decryption, operating mode 2*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION); + + /* we should re-write Key, in the case where we change key after first operation*/ + if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL)) + { + if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG) + { + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + } + /* Enable SAES */ + __HAL_CRYP_ENABLE(hcryp); + + /* Wait for CCF flag to be raised */ + count = CRYP_TIMEOUT_KEYPREPARATION; + do + { + count--; + if (count == 0U) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } while (HAL_IS_BIT_CLR(hcryp->Instance->ISR, AES_ISR_CCF)); + + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + + /* End of Key preparation for ECB/CBC */ + /* Return to decryption operating mode(Mode 3)*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); + } + else /*Algorithm CTR */ + { + /* we should re-write Key, in the case where we change key after first operation*/ + if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL)) + { + if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG) + { + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + } + } + } +#endif /* SAES */ + + if (hcryp->Init.Algorithm != CRYP_AES_ECB) + { + /* Set the Initialization Vector*/ + CRYP_SetIV(hcryp); + } + } /* if (dokeyivconfig == 1U) */ + + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; + + if (hcryp->Size != 0U) + { + /* Set the input and output addresses and start DMA transfer */ + CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size), (uint32_t)(hcryp->pCrypOutBuffPtr)); + } + else + { + __HAL_UNLOCK(hcryp); + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_READY; + } + + return HAL_OK; +} + + +/** + * @brief DMA CRYP input data process complete callback. + * @param hdma DMA handle + * @retval None + */ +static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma) +{ + CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + uint32_t loopcounter; + uint32_t headersize_in_bytes; + uint32_t tmp; + const uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU + }; /* 8-bit data type */ + uint32_t algo; + + /* Disable the DMA transfer for input FIFO request by resetting the DIEN bit + in the DMACR register */ + CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAINEN); + + if (hcryp->Phase == CRYP_PHASE_HEADER_DMA_FEED) + { + /* DMA is disabled, CCF is meaningful. Wait for computation completion before moving forward */ + CRYP_ClearCCFlagWhenHigh(hcryp, CRYP_TIMEOUT_GCMCCMHEADERPHASE); + + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; + + if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD) + { + headersize_in_bytes = hcryp->Init.HeaderSize * 4U; + } + else + { + headersize_in_bytes = hcryp->Init.HeaderSize; + } + + if ((headersize_in_bytes % 16U) != 0U) + { + /* Write last words that couldn't be fed by DMA */ + hcryp->CrypHeaderCount = (uint16_t)((headersize_in_bytes / 16U) * 4U); + for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 4U) % 4U)); loopcounter++) + { + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + } + /* If the header size is a multiple of words */ + if ((headersize_in_bytes % 4U) == 0U) + { + /* Pad the data with zeros to have a complete block */ + while (loopcounter < 4U) + { + hcryp->Instance->DINR = 0x0U; + loopcounter++; + } + } + else + { + /* Enter last bytes, padded with zeros */ + tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)]; + hcryp->Instance->DINR = tmp; + loopcounter++; + /* Pad the data with zeros to have a complete block */ + while (loopcounter < 4U) + { + hcryp->Instance->DINR = 0x0U; + loopcounter++; + } + } + + /* Wait for computation completion before moving forward */ + CRYP_ClearCCFlagWhenHigh(hcryp, CRYP_TIMEOUT_GCMCCMHEADERPHASE); + } /* if ((headersize_in_bytes % 16U) != 0U) */ + + /* Set to 0 the number of non-valid bytes using NPBLB register*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U); + + /* Select payload phase once the header phase is performed */ + CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); + + /* Initiate payload DMA IN and processed data DMA OUT transfers */ + (void)CRYP_GCMCCM_SetPayloadPhase_DMA(hcryp); + } + else + { + + /* ECB, CBC or CTR end of input data feeding or + end of GCM/CCM payload data feeding through DMA */ + algo = hcryp->Instance->CR & AES_CR_CHMOD; + + /* Don't call input data transfer complete callback only if + it remains some input data to write to the peripheral. + This case can only occur for GCM and CCM with a payload length + not a multiple of 16 bytes */ + if (!(((algo == CRYP_AES_GCM_GMAC) || (algo == CRYP_AES_CCM)) && \ + (((hcryp->Size) % 16U) != 0U))) + { + /* Call input data transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + } /* if (hcryp->Phase == CRYP_PHASE_HEADER_DMA_FEED) */ +} + +/** + * @brief DMA CRYP output data process complete callback. + * @param hdma DMA handle + * @retval None + */ +static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma) +{ + uint32_t count; + uint32_t npblb; + uint32_t lastwordsize; + uint32_t temp[4]; /* Temporary CrypOutBuff */ + uint32_t mode; + + CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Disable the DMA transfer for output FIFO request by resetting + the DMAOUTEN bit in the CR register */ + + CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAOUTEN); + + /* Clear CCF flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + + /* Last block transfer in case of GCM or CCM with Size not %16*/ + if (((hcryp->Size) % 16U) != 0U) + { + /* set CrypInCount and CrypOutCount to exact number of word already computed via DMA */ + hcryp->CrypInCount = (hcryp->Size / 16U) * 4U; + hcryp->CrypOutCount = hcryp->CrypInCount; + + /* Compute the number of padding bytes in last block of payload */ + npblb = ((((uint32_t)hcryp->Size / 16U) + 1U) * 16U) - ((uint32_t)hcryp->Size); + + mode = hcryp->Instance->CR & AES_CR_MODE; + if (((mode == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)) || + ((mode == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM))) + { + /* Specify the number of non-valid bytes using NPBLB register*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U); + } + + /* Number of valid words (lastwordsize) in last block */ + if ((npblb % 4U) == 0U) + { + lastwordsize = (16U - npblb) / 4U; + } + else + { + lastwordsize = ((16U - npblb) / 4U) + 1U; + } + + /* Last block optionally pad the data with zeros*/ + for (count = 0U; count < lastwordsize; count++) + { + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + } + while (count < 4U) + { + /* Pad the data with zeros to have a complete block */ + hcryp->Instance->DINR = 0x0U; + count++; + } + /* Call input data transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + + /*Wait on CCF flag*/ + CRYP_ClearCCFlagWhenHigh(hcryp, CRYP_TIMEOUT_GCMCCMHEADERPHASE); + + /*Read the output block from the output FIFO */ + for (count = 0U; count < 4U; count++) + { + /* Read the output block from the output FIFO and put them in temporary buffer + then get CrypOutBuff from temporary buffer */ + temp[count] = hcryp->Instance->DOUTR; + } + + count = 0U; + while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (count < 4U)) + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[count]; + hcryp->CrypOutCount++; + count++; + } + } + + if (((hcryp->Init.Algorithm & CRYP_AES_GCM_GMAC) != CRYP_AES_GCM_GMAC) + && ((hcryp->Init.Algorithm & CRYP_AES_CCM) != CRYP_AES_CCM)) + { + /* Disable CRYP (not allowed in GCM)*/ + __HAL_CRYP_DISABLE(hcryp); + } + + /* Change the CRYP state to ready */ + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + + /* Call output data transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Output complete callback*/ + hcryp->OutCpltCallback(hcryp); +#else + /*Call legacy weak Output complete callback*/ + HAL_CRYP_OutCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA CRYP communication error callback. + * @param hdma DMA handle + * @retval None + */ +static void CRYP_DMAError(DMA_HandleTypeDef *hdma) +{ + CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Change the CRYP peripheral state */ + hcryp->State = HAL_CRYP_STATE_READY; + + /* DMA error code field */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA; + + /* Clear CCF flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + + /* Call error callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered error callback*/ + hcryp->ErrorCallback(hcryp); +#else + /*Call legacy weak error callback*/ + HAL_CRYP_ErrorCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ +} + +/** + * @brief Set the DMA configuration and start the DMA transfer + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param inputaddr address of the input buffer + * @param Size size of the input and output buffers in words, must be a multiple of 4. + * @param outputaddr address of the output buffer + * @retval None + */ +static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr) +{ + HAL_StatusTypeDef status; + + /* Set the CRYP DMA transfer complete callback */ + hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt; + + /* Set the DMA input error callback */ + hcryp->hdmain->XferErrorCallback = CRYP_DMAError; + + /* Set the CRYP DMA transfer complete callback */ + hcryp->hdmaout->XferCpltCallback = CRYP_DMAOutCplt; + + /* Set the DMA output error callback */ + hcryp->hdmaout->XferErrorCallback = CRYP_DMAError; + + if ((hcryp->Init.Algorithm & CRYP_AES_GCM_GMAC) != CRYP_AES_GCM_GMAC) + { + /* Enable CRYP (not allowed in GCM & CCM)*/ + __HAL_CRYP_ENABLE(hcryp); + } + + /* Enable the DMA input channel */ + if ((hcryp->hdmain->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if ((hcryp->hdmain->LinkedListQueue != NULL) && (hcryp->hdmain->LinkedListQueue->Head != NULL)) + { + /* Enable the DMA channel */ + hcryp->hdmain->LinkedListQueue->Head->\ + LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = Size; /* Set DMA data size */ + hcryp->hdmain->LinkedListQueue->Head->\ + LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = inputaddr; /* Set DMA source address */ + hcryp->hdmain->LinkedListQueue->Head->\ + LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)&hcryp->Instance->DINR; /* Set DMA destination address */ + + status = HAL_DMAEx_List_Start_IT(hcryp->hdmain); + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + } + else + { + status = HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DINR, Size); + } + + if (status != HAL_OK) + { + /* DMA error code field */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA; + + /*Call registered error callback*/ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + hcryp->ErrorCallback(hcryp); +#else + /*Call legacy weak error callback*/ + HAL_CRYP_ErrorCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + /* Enable the DMA output channel */ + if ((hcryp->hdmaout->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if ((hcryp->hdmaout->LinkedListQueue != NULL) && (hcryp->hdmaout->LinkedListQueue->Head != NULL)) + { + /* Enable the DMA channel */ + hcryp->hdmaout->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = \ + Size; /* Set DMA data size */ + hcryp->hdmaout->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = \ + (uint32_t)&hcryp->Instance->DOUTR; /* Set DMA source address */ + hcryp->hdmaout->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = \ + outputaddr; /* Set DMA destination address */ + + status = HAL_DMAEx_List_Start_IT(hcryp->hdmaout); + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + } + else + { + status = HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUTR, outputaddr, Size); + } + + if (status != HAL_OK) + { + /* DMA error code field */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA; + + /* Call error callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered error callback*/ + hcryp->ErrorCallback(hcryp); +#else + /*Call legacy weak error callback*/ + HAL_CRYP_ErrorCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + /* Enable In and Out DMA requests */ + SET_BIT(hcryp->Instance->CR, (AES_CR_DMAINEN | AES_CR_DMAOUTEN)); +} + +/** + * @brief Set the DMA configuration and start the header DMA transfer + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param inputaddr address of the input buffer + * @param Size size of the input buffer in words, must be a multiple of 4 + * @retval None + */ +static HAL_StatusTypeDef CRYP_SetHeaderDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size) +{ + HAL_StatusTypeDef status; + + /* Set the CRYP DMA transfer complete callback */ + hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt; + + /* Set the DMA input error callback */ + hcryp->hdmain->XferErrorCallback = CRYP_DMAError; + + /* Mark that header is fed to the peripheral in DMA mode */ + hcryp->Phase = CRYP_PHASE_HEADER_DMA_FEED; + + /* Enable the DMA input channel */ + if ((hcryp->hdmain->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if ((hcryp->hdmain->LinkedListQueue != NULL) && (hcryp->hdmain->LinkedListQueue->Head != NULL)) + { + /* Enable the DMA channel */ + hcryp->hdmain->LinkedListQueue->Head->\ + LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = Size; /* Set DMA data size */ + hcryp->hdmain->LinkedListQueue->Head->\ + LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = inputaddr; /* Set DMA source address */ + hcryp->hdmain->LinkedListQueue->Head->\ + LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)&hcryp->Instance->DINR; /* Set DMA destination address */ + + status = HAL_DMAEx_List_Start_IT(hcryp->hdmain); + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + } + else + { + status = HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DINR, Size); + } + if (status != HAL_OK) + { + /* DMA error code field */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA; + + /* Call error callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered error callback*/ + hcryp->ErrorCallback(hcryp); +#else + /*Call legacy weak error callback*/ + HAL_CRYP_ErrorCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + + /* Enable IN DMA requests */ + SET_BIT(hcryp->Instance->CR, AES_CR_DMAINEN); + + return status; +} + +/** + * @brief Process Data: Write Input data in polling mode and used in AES functions. + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param Timeout Specify Timeout value + * @retval None + */ +static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) +{ + + uint32_t temp[4]; /* Temporary CrypOutBuff */ + uint32_t i; + + /* Write the input block in the IN FIFO */ + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + + /* Wait for CCF flag to be raised */ + if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + { + /*Call registered error callback*/ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + hcryp->ErrorCallback(hcryp); +#else + /*Call legacy weak error callback*/ + HAL_CRYP_ErrorCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + + /* Read the output block from the output FIFO and put them in temporary buffer then + get CrypOutBuff from temporary buffer*/ + for (i = 0U; i < 4U; i++) + { + temp[i] = hcryp->Instance->DOUTR; + } + i = 0U; + while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U)) + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; + hcryp->CrypOutCount++; + i++; + } +} + +/** + * @brief Handle CRYP block input/output data handling under interruption. + * @note The function is called under interruption only, once + * interruptions have been enabled by HAL_CRYP_Encrypt_IT or HAL_CRYP_Decrypt_IT. + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module. + * @retval HAL status + */ +static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp) +{ + uint32_t temp[4]; /* Temporary CrypOutBuff */ + uint32_t i; + + if (hcryp->State == HAL_CRYP_STATE_BUSY) + { + /* Read the output block from the output FIFO and put them in temporary buffer then + get CrypOutBuff from temporary buffer*/ + for (i = 0U; i < 4U; i++) + { + temp[i] = hcryp->Instance->DOUTR; + } + i = 0U; + while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U)) + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; + hcryp->CrypOutCount++; + i++; + } + if (hcryp->CrypOutCount == (hcryp->Size / 4U)) + { + /* Disable Computation Complete flag and errors interrupts */ + __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE); + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_READY; + + /* Disable CRYP */ + __HAL_CRYP_DISABLE(hcryp); + __HAL_UNLOCK(hcryp); + + /* Call Output transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Output complete callback*/ + hcryp->OutCpltCallback(hcryp); +#else + /*Call legacy weak Output complete callback*/ + HAL_CRYP_OutCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + else + { +#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) + /* If suspension flag has been raised, suspend processing + only if not already at the end of the payload */ + if (hcryp->SuspendRequest == HAL_CRYP_SUSPEND) + { + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + + /* reset SuspendRequest */ + hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE; + /* Disable Computation Complete Flag and Errors Interrupts */ + __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE); + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_SUSPENDED; + /* Mark that the payload phase is suspended */ + hcryp->Phase = CRYP_PHASE_PAYLOAD_SUSPENDED; + __HAL_UNLOCK(hcryp); + } + else +#endif /* USE_HAL_CRYP_SUSPEND_RESUME */ + { + /* Write the input block in the IN FIFO */ + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + + if (hcryp->CrypInCount == (hcryp->Size / 4U)) + { + /* Call Input transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + } + } + } + else + { + /* Busy error code field */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY; +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered error callback*/ + hcryp->ErrorCallback(hcryp); +#else + /*Call legacy weak error callback*/ + HAL_CRYP_ErrorCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } +} + +/** + * @brief Writes Key in Key registers. + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param KeySize Size of Key + * @note If pKey is NULL, the Key registers are not written. + * @retval None + */ +static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint32_t KeySize) +{ + if (hcryp->Init.pKey != NULL) + { + switch (KeySize) + { + case CRYP_KEYSIZE_256B: + hcryp->Instance->KEYR7 = *(uint32_t *)(hcryp->Init.pKey); + hcryp->Instance->KEYR6 = *(uint32_t *)(hcryp->Init.pKey + 1U); + hcryp->Instance->KEYR5 = *(uint32_t *)(hcryp->Init.pKey + 2U); + hcryp->Instance->KEYR4 = *(uint32_t *)(hcryp->Init.pKey + 3U); + hcryp->Instance->KEYR3 = *(uint32_t *)(hcryp->Init.pKey + 4U); + hcryp->Instance->KEYR2 = *(uint32_t *)(hcryp->Init.pKey + 5U); + hcryp->Instance->KEYR1 = *(uint32_t *)(hcryp->Init.pKey + 6U); + hcryp->Instance->KEYR0 = *(uint32_t *)(hcryp->Init.pKey + 7U); + break; + case CRYP_KEYSIZE_128B: + hcryp->Instance->KEYR3 = *(uint32_t *)(hcryp->Init.pKey); + hcryp->Instance->KEYR2 = *(uint32_t *)(hcryp->Init.pKey + 1U); + hcryp->Instance->KEYR1 = *(uint32_t *)(hcryp->Init.pKey + 2U); + hcryp->Instance->KEYR0 = *(uint32_t *)(hcryp->Init.pKey + 3U); + break; + default: + break; + } + } +} + +/** + * @brief Writes initialization vector in IV registers. + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @note If IV is NULL, the IV registers are not written. + * @retval None + */ +static void CRYP_SetIV(CRYP_HandleTypeDef *hcryp) +{ + if (hcryp->Init.pInitVect != NULL) + { + /* Set the Initialization Vector*/ + hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect); + hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U); + hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U); + hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U); + } +} + +/** + * @brief Encryption/Decryption process in AES GCM mode and prepare the authentication TAG + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param Timeout Timeout duration + * @retval HAL status + */ +static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) +{ + uint32_t tickstart; + uint32_t wordsize = ((uint32_t)hcryp->Size / 4U); + uint32_t npblb; + uint32_t temp[4]; /* Temporary CrypOutBuff */ + uint32_t index; + uint32_t lastwordsize; + uint32_t incount; /* Temporary CrypInCount Value */ + uint32_t outcount; /* Temporary CrypOutCount Value */ + uint32_t dokeyivconfig = 1U; /* By default, carry out peripheral Key and IV configuration */ + + if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) + { + if (hcryp->KeyIVConfig == 1U) + { + /* If the Key and IV configuration has to be done only once + and if it has already been done, skip it */ + dokeyivconfig = 0U; + hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */ + } + else + { + /* If the Key and IV configuration has to be done only once + and if it has not been done already, do it and set KeyIVConfig + to keep track it won't have to be done again next time */ + hcryp->KeyIVConfig = 1U; + hcryp->SizesSum = hcryp->Size; /* Merely store payload length */ + } + } + else + { + hcryp->SizesSum = hcryp->Size; + } + + if (dokeyivconfig == 1U) + { + + /* Reset CrypHeaderCount */ + hcryp->CrypHeaderCount = 0U; + + /****************************** Init phase **********************************/ + + CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT); + /* Set the Key */ + if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG) + { +#if !defined(SAES) + CRYP_SetKey(hcryp, hcryp->Init.KeySize); +#else + if (hcryp->Instance == AES) + { + if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED) + { + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + else /*after sharing the key, AES should set KMOD[1:0] to 00.*/ + { + hcryp->Instance->CR &= ~CRYP_KEYMODE_SHARED; + } + } + else /*SAES*/ + { + /* We should re-write Key, in the case where we change key after first operation */ + if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL)) + { + /* Set the Key */ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + /* Get tick */ + tickstart = HAL_GetTick(); + + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_KEYVALID)) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } + } + } +#endif /* SAES */ + } + /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/ + CRYP_SetIV(hcryp); + + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); + + /* just wait for hash computation */ + if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + { + return HAL_ERROR; + } + /* Clear CCF flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + + /************************ Header phase *************************************/ + + if (CRYP_GCMCCM_SetHeaderPhase(hcryp, Timeout) != HAL_OK) + { + return HAL_ERROR; + } + + /*************************Payload phase ************************************/ + + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; + + /* Select payload phase once the header phase is performed */ + CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); + + /* Set to 0 the number of non-valid bytes using NPBLB register*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U); + + } /* if (dokeyivconfig == 1U) */ + + if ((hcryp->Size % 16U) != 0U) + { + /* recalculate wordsize */ + wordsize = ((wordsize / 4U) * 4U); + } + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Write input data and get output Data */ + incount = hcryp->CrypInCount; + outcount = hcryp->CrypOutCount; + while ((incount < wordsize) && (outcount < wordsize)) + { + /* Write plain data and get cipher data */ + CRYP_AES_ProcessData(hcryp, Timeout); + + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state & error code */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } + incount = hcryp->CrypInCount; + outcount = hcryp->CrypOutCount; + } + + if ((hcryp->Size % 16U) != 0U) + { + /* Compute the number of padding bytes in last block of payload */ + npblb = ((((uint32_t)hcryp->Size / 16U) + 1U) * 16U) - ((uint32_t)hcryp->Size); + + /* Set Npblb in case of AES GCM payload encryption to get right tag*/ + if ((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT) + { + /* Set to 0 the number of non-valid bytes using NPBLB register*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U); + } + /* Number of valid words (lastwordsize) in last block */ + if ((npblb % 4U) == 0U) + { + lastwordsize = (16U - npblb) / 4U; + } + else + { + lastwordsize = ((16U - npblb) / 4U) + 1U; + } + /* last block optionally pad the data with zeros*/ + for (index = 0U; index < lastwordsize; index ++) + { + /* Write the last Input block in the IN FIFO */ + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + } + while (index < 4U) + { + /* pad the data with zeros to have a complete block */ + hcryp->Instance->DINR = 0U; + index++; + } + /* Wait for CCF flag to be raised */ + if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + { +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered error callback*/ + hcryp->ErrorCallback(hcryp); +#else + /*Call legacy weak error callback*/ + HAL_CRYP_ErrorCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + + /*Read the output block from the output FIFO */ + for (index = 0U; index < 4U; index++) + { + /* Read the output block from the output FIFO and put them in temporary buffer then + get CrypOutBuff from temporary buffer */ + temp[index] = hcryp->Instance->DOUTR; + } + for (index = 0U; index < lastwordsize; index++) + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp[index]; + hcryp->CrypOutCount++; + } + } + + return HAL_OK; +} + +/** + * @brief Encryption/Decryption process in AES GCM mode and prepare the authentication TAG in interrupt mode + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @retval HAL status + */ +static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) +{ + uint32_t count; + uint32_t loopcounter; + uint32_t lastwordsize; + uint32_t npblb; + uint32_t dokeyivconfig = 1U; /* By default, carry out peripheral Key and IV configuration */ + uint32_t headersize_in_bytes; + uint32_t tmp; + const uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU + }; /* 8-bit data type */ + +#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) + if ((hcryp->Phase == CRYP_PHASE_HEADER_SUSPENDED) || (hcryp->Phase == CRYP_PHASE_PAYLOAD_SUSPENDED)) + { + CRYP_PhaseProcessingResume(hcryp); + return HAL_OK; + } +#endif /* USE_HAL_CRYP_SUSPEND_RESUME */ + + /* Manage header size given in bytes to handle cases where + header size is not a multiple of 4 bytes */ + if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD) + { + headersize_in_bytes = hcryp->Init.HeaderSize * 4U; + } + else + { + headersize_in_bytes = hcryp->Init.HeaderSize; + } + + if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) + { + if (hcryp->KeyIVConfig == 1U) + { + /* If the Key and IV configuration has to be done only once + and if it has already been done, skip it */ + dokeyivconfig = 0U; + hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */ + } + else + { + /* If the Key and IV configuration has to be done only once + and if it has not been done already, do it and set KeyIVConfig + to keep track it won't have to be done again next time */ + hcryp->KeyIVConfig = 1U; + hcryp->SizesSum = hcryp->Size; /* Merely store payload length */ + } + } + else + { + hcryp->SizesSum = hcryp->Size; + } + + /* Configure Key, IV and process message (header and payload) */ + if (dokeyivconfig == 1U) + { + /* Reset CrypHeaderCount */ + hcryp->CrypHeaderCount = 0U; + + /******************************* Init phase *********************************/ + + CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT); + /* Set the Key */ + if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG) + { +#if !defined(SAES) + CRYP_SetKey(hcryp, hcryp->Init.KeySize); +#else + if (hcryp->Instance == AES) + { + if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED) + { + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + else /*after sharing the key, AES should set KMOD[1:0] to 00.*/ + { + hcryp->Instance->CR &= ~CRYP_KEYMODE_SHARED; + } + } + else /*SAES*/ + { + /* We should re-write Key, in the case where we change key after first operation */ + if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL)) + { + /* Set the Key */ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + /* Wait for KEYVALID flag to be set */ + count = CRYP_TIMEOUT_KEYPREPARATION; + do + { + count--; + if (count == 0U) + { + /* Disable the SAES peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_KEYVALID)); + } +#endif /* SAES */ + } + /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/ + CRYP_SetIV(hcryp); + + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); + + /* just wait for hash computation */ + count = CRYP_TIMEOUT_GCMCCMINITPHASE; + do + { + count--; + if (count == 0U) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } while (HAL_IS_BIT_CLR(hcryp->Instance->ISR, AES_ISR_CCF)); + + /* Clear CCF flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + + /***************************** Header phase *********************************/ + + /* Select header phase */ + CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); + + /* Enable computation complete flag and error interrupts */ + __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE); + + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); + + if (hcryp->Init.HeaderSize == 0U) /*header phase is skipped*/ + { + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; + + /* Select payload phase once the header phase is performed */ + MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD); + + /* Set to 0 the number of non-valid bytes using NPBLB register*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U); + + /* Write the payload Input block in the IN FIFO */ + if (hcryp->Size == 0U) + { + /* Disable interrupts */ + __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE); + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + } + else if (hcryp->Size >= 16U) + { + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) + { + /* Call Input transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + } + else /* Size < 16Bytes : first block is the last block*/ + { + /* Size should be %4 otherwise Tag will be incorrectly generated for GCM Encryption: + Workaround is implemented in polling mode, so if last block of + payload <128bit do not use CRYP_Encrypt_IT otherwise TAG is incorrectly generated for GCM Encryption. */ + + + /* Compute the number of padding bytes in last block of payload */ + npblb = 16U - ((uint32_t)hcryp->Size); + + if ((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT) + { + /* Set to 0 the number of non-valid bytes using NPBLB register*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U); + } + + /* Number of valid words (lastwordsize) in last block */ + if ((npblb % 4U) == 0U) + { + lastwordsize = (16U - npblb) / 4U; + } + else + { + lastwordsize = ((16U - npblb) / 4U) + 1U; + } + + /* last block optionally pad the data with zeros*/ + for (loopcounter = 0U; loopcounter < lastwordsize ; loopcounter++) + { + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + } + while (loopcounter < 4U) + { + /* pad the data with zeros to have a complete block */ + hcryp->Instance->DINR = 0x0U; + loopcounter++; + } + /* Call Input transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + } + /* Enter header data */ + /* Cher first whether header length is small enough to enter the full header in one shot */ + else if (headersize_in_bytes <= 16U) + { + /* Write header data, padded with zeros if need be */ + for (loopcounter = 0U; (loopcounter < (headersize_in_bytes / 4U)); loopcounter++) + { + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + } + /* If the header size is a multiple of words */ + if ((headersize_in_bytes % 4U) == 0U) + { + /* Pad the data with zeros to have a complete block */ + while (loopcounter < 4U) + { + hcryp->Instance->DINR = 0x0U; + loopcounter++; + hcryp->CrypHeaderCount++; + } + } + else + { + /* Enter last bytes, padded with zeros */ + tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)]; + hcryp->Instance->DINR = tmp; + loopcounter++; + hcryp->CrypHeaderCount++ ; + /* Pad the data with zeros to have a complete block */ + while (loopcounter < 4U) + { + hcryp->Instance->DINR = 0x0U; + loopcounter++; + hcryp->CrypHeaderCount++; + } + } + /* Call Input transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + else + { + /* Write the first input header block in the Input FIFO, + the following header data will be fed after interrupt occurrence */ + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++; + } + + } /* end of if (dokeyivconfig == 1U) */ + else /* Key and IV have already been configured, + header has already been processed; + only process here message payload */ + { + + /* Enable computation complete flag and error interrupts */ + __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE); + + /* Set to 0 the number of non-valid bytes using NPBLB register*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U); + + /* Write the payload Input block in the IN FIFO */ + if (hcryp->Size == 0U) + { + /* Disable interrupts */ + __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE); + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + } + else if (hcryp->Size >= 16U) + { + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) + { + /* Call Input transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + } + else /* Size < 16Bytes : first block is the last block*/ + { + /* Size should be %4 otherwise Tag will be incorrectly generated for GCM Encryption: + Workaround is implemented in polling mode, so if last block of + payload <128bit do not use CRYP_Encrypt_IT otherwise TAG is incorrectly generated for GCM Encryption. */ + + + /* Compute the number of padding bytes in last block of payload */ + npblb = 16U - ((uint32_t)hcryp->Size); + + if ((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT) + { + /* Set to 0 the number of non-valid bytes using NPBLB register*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U); + } + + /* Number of valid words (lastwordsize) in last block */ + if ((npblb % 4U) == 0U) + { + lastwordsize = (16U - npblb) / 4U; + } + else + { + lastwordsize = ((16U - npblb) / 4U) + 1U; + } + + /* last block optionally pad the data with zeros*/ + for (loopcounter = 0U; loopcounter < lastwordsize ; loopcounter++) + { + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + } + while (loopcounter < 4U) + { + /* pad the data with zeros to have a complete block */ + hcryp->Instance->DINR = 0x0U; + loopcounter++; + } + /* Call Input transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + } + + return HAL_OK; +} + + +/** + * @brief Encryption/Decryption process in AES GCM mode and prepare the authentication TAG using DMA + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @retval HAL status + */ +static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp) +{ + uint32_t count; + uint32_t dokeyivconfig = 1U; /* By default, carry out peripheral Key and IV configuration */ + + if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) + { + if (hcryp->KeyIVConfig == 1U) + { + /* If the Key and IV configuration has to be done only once + and if it has already been done, skip it */ + dokeyivconfig = 0U; + hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */ + } + else + { + /* If the Key and IV configuration has to be done only once + and if it has not been done already, do it and set KeyIVConfig + to keep track it won't have to be done again next time */ + hcryp->KeyIVConfig = 1U; + hcryp->SizesSum = hcryp->Size; /* Merely store payload length */ + } + } + else + { + hcryp->SizesSum = hcryp->Size; + } + + if (dokeyivconfig == 1U) + { + + /* Reset CrypHeaderCount */ + hcryp->CrypHeaderCount = 0U; + + /*************************** Init phase ************************************/ + + CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT); + /* Set the Key */ + if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG) + { +#if !defined(SAES) + CRYP_SetKey(hcryp, hcryp->Init.KeySize); +#else + if (hcryp->Instance == AES) + { + if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED) + { + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + else /*after sharing the key, AES should set KMOD[1:0] to 00.*/ + { + hcryp->Instance->CR &= ~CRYP_KEYMODE_SHARED; + } + } + else /*SAES*/ + { + /* We should re-write Key, in the case where we change key after first operation */ + if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL)) + { + /* Set the Key */ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + /* Wait for KEYVALID flag to be set */ + count = CRYP_TIMEOUT_KEYPREPARATION; + do + { + count--; + if (count == 0U) + { + /* Disable the SAES peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_KEYVALID)); + } +#endif /* SAES */ + } + /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/ + CRYP_SetIV(hcryp); + + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); + + /* just wait for hash computation */ + count = CRYP_TIMEOUT_GCMCCMINITPHASE; + do + { + count--; + if (count == 0U) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } while (HAL_IS_BIT_CLR(hcryp->Instance->ISR, AES_ISR_CCF)); + + /* Clear CCF flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + + /************************ Header phase *************************************/ + + if (CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK) + { + return HAL_ERROR; + } + + } + else + { + /* Initialization and header phases already done, only do payload phase */ + if (CRYP_GCMCCM_SetPayloadPhase_DMA(hcryp) != HAL_OK) + { + return HAL_ERROR; + } + } /* if (DoKeyIVConfig == 1U) */ + + return HAL_OK; +} + + +/** + * @brief AES CCM encryption/decryption processing in polling mode + * encrypt/decrypt are performed with authentication preparation. + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param Timeout Timeout duration + * @retval HAL status + */ +static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) +{ + uint32_t tickstart; + uint32_t wordsize = ((uint32_t)hcryp->Size / 4U); + uint32_t loopcounter; + uint32_t npblb; + uint32_t lastwordsize; + uint32_t temp[4]; /* Temporary CrypOutBuff */ + uint32_t incount; /* Temporary CrypInCount Value */ + uint32_t outcount; /* Temporary CrypOutCount Value */ + uint32_t dokeyivconfig = 1U; /* By default, carry out peripheral Key and IV configuration */ + + if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) + { + if (hcryp->KeyIVConfig == 1U) + { + /* If the Key and IV configuration has to be done only once + and if it has already been done, skip it */ + dokeyivconfig = 0U; + hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */ + } + else + { + /* If the Key and IV configuration has to be done only once + and if it has not been done already, do it and set KeyIVConfig + to keep track it won't have to be done again next time */ + hcryp->KeyIVConfig = 1U; + hcryp->SizesSum = hcryp->Size; /* Merely store payload length */ + } + } + else + { + hcryp->SizesSum = hcryp->Size; + } + + if (dokeyivconfig == 1U) + { + /* Reset CrypHeaderCount */ + hcryp->CrypHeaderCount = 0U; + + /********************** Init phase ******************************************/ + + CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT); + /* Set the Key */ + if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG) + { +#if !defined(SAES) + CRYP_SetKey(hcryp, hcryp->Init.KeySize); +#else + if (hcryp->Instance == AES) + { + if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED) + { + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + else /*after sharing the key, AES should set KMOD[1:0] to 00.*/ + { + hcryp->Instance->CR &= ~CRYP_KEYMODE_SHARED; + } + } + else /*SAES*/ + { + /* We should re-write Key, in the case where we change key after first operation */ + if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL)) + { + /* Set the Key */ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + /* Get tick */ + tickstart = HAL_GetTick(); + + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_KEYVALID)) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } + } + } +#endif /* SAES */ + } + /* Set the initialization vector (IV) with B0 */ + hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.B0); + hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.B0 + 1U); + hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.B0 + 2U); + hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.B0 + 3U); + + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); + + /* just wait for hash computation */ + if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + { + return HAL_ERROR; + } + /* Clear CCF flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + + /************************ Header phase *************************************/ + /* Header block(B1) : associated data length expressed in bytes concatenated + with Associated Data (A)*/ + if (CRYP_GCMCCM_SetHeaderPhase(hcryp, Timeout) != HAL_OK) + { + return HAL_ERROR; + } + + /*************************Payload phase ************************************/ + + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; + + /* Select payload phase once the header phase is performed */ + MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD); + + /* Set to 0 the number of non-valid bytes using NPBLB register*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U); + + } /* if (dokeyivconfig == 1U) */ + + if ((hcryp->Size % 16U) != 0U) + { + /* recalculate wordsize */ + wordsize = ((wordsize / 4U) * 4U); + } + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Write input data and get output data */ + incount = hcryp->CrypInCount; + outcount = hcryp->CrypOutCount; + while ((incount < wordsize) && (outcount < wordsize)) + { + /* Write plain data and get cipher data */ + CRYP_AES_ProcessData(hcryp, Timeout); + + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } + incount = hcryp->CrypInCount; + outcount = hcryp->CrypOutCount; + } + + if ((hcryp->Size % 16U) != 0U) + { + /* Compute the number of padding bytes in last block of payload */ + npblb = ((((uint32_t)hcryp->Size / 16U) + 1U) * 16U) - ((uint32_t)hcryp->Size); + + if ((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_DECRYPT) + { + /* Set Npblb in case of AES CCM payload decryption to get right tag */ + MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20); + + } + /* Number of valid words (lastwordsize) in last block */ + if ((npblb % 4U) == 0U) + { + lastwordsize = (16U - npblb) / 4U; + } + else + { + lastwordsize = ((16U - npblb) / 4U) + 1U; + } + + /* Write the last input block in the IN FIFO */ + for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter ++) + { + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + } + + /* Pad the data with zeros to have a complete block */ + while (loopcounter < 4U) + { + hcryp->Instance->DINR = 0U; + loopcounter++; + } + /* just wait for hash computation */ + if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + { + return HAL_ERROR; + } + /* Clear CCF flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + + for (loopcounter = 0U; loopcounter < 4U; loopcounter++) + { + /* Read the output block from the output FIFO and put them in temporary buffer then + get CrypOutBuff from temporary buffer */ + temp[loopcounter] = hcryp->Instance->DOUTR; + } + for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++) + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[loopcounter]; + hcryp->CrypOutCount++; + } + } + + return HAL_OK; +} + +/** + * @brief AES CCM encryption/decryption process in interrupt mode + * encrypt/decrypt are performed with authentication preparation. + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @retval HAL status + */ +static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp) +{ + uint32_t count; + uint32_t loopcounter; + uint32_t lastwordsize; + uint32_t npblb; + uint32_t mode; + uint32_t dokeyivconfig = 1U; /* By default, carry out peripheral Key and IV configuration */ + uint32_t headersize_in_bytes; + uint32_t tmp; + const uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU + }; /* 8-bit data type */ + +#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) + if ((hcryp->Phase == CRYP_PHASE_HEADER_SUSPENDED) || (hcryp->Phase == CRYP_PHASE_PAYLOAD_SUSPENDED)) + { + CRYP_PhaseProcessingResume(hcryp); + return HAL_OK; + } +#endif /* USE_HAL_CRYP_SUSPEND_RESUME */ + + if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) + { + if (hcryp->KeyIVConfig == 1U) + { + /* If the Key and IV configuration has to be done only once + and if it has already been done, skip it */ + dokeyivconfig = 0U; + hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */ + } + else + { + /* If the Key and IV configuration has to be done only once + and if it has not been done already, do it and set KeyIVConfig + to keep track it won't have to be done again next time */ + hcryp->KeyIVConfig = 1U; + hcryp->SizesSum = hcryp->Size; /* Merely store payload length */ + } + } + else + { + hcryp->SizesSum = hcryp->Size; + } + + /* Configure Key, IV and process message (header and payload) */ + if (dokeyivconfig == 1U) + { + /* Reset CrypHeaderCount */ + hcryp->CrypHeaderCount = 0U; + + /********************** Init phase ******************************************/ + + CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT); + /* Set the Key */ + if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG) + { +#if !defined(SAES) + CRYP_SetKey(hcryp, hcryp->Init.KeySize); +#else + if (hcryp->Instance == AES) + { + if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED) + { + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + else /*after sharing the key, AES should set KMOD[1:0] to 00.*/ + { + hcryp->Instance->CR &= ~CRYP_KEYMODE_SHARED; + } + } + else /*SAES*/ + { + /* We should re-write Key, in the case where we change key after first operation */ + if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL)) + { + /* Set the Key */ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + /* Wait for KEYVALID flag to be set */ + count = CRYP_TIMEOUT_KEYPREPARATION; + do + { + count--; + if (count == 0U) + { + /* Disable the SAES peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_KEYVALID)); + } +#endif /* SAES */ + } + /* Set the initialization vector (IV) with B0 */ + hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.B0); + hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.B0 + 1U); + hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.B0 + 2U); + hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.B0 + 3U); + + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); + + /* just wait for hash computation */ + count = CRYP_TIMEOUT_GCMCCMINITPHASE; + do + { + count--; + if (count == 0U) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } while (HAL_IS_BIT_CLR(hcryp->Instance->ISR, AES_ISR_CCF)); + + /* Clear CCF flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + + /***************************** Header phase *********************************/ + + /* Select header phase */ + CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); + + /* Enable computation complete flag and error interrupts */ + __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE); + + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); + + if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD) + { + headersize_in_bytes = hcryp->Init.HeaderSize * 4U; + } + else + { + headersize_in_bytes = hcryp->Init.HeaderSize; + } + + if (headersize_in_bytes == 0U) /* Header phase is skipped */ + { + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; + /* Select payload phase once the header phase is performed */ + CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); + /* Set to 0 the number of non-valid bytes using NPBLB register*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U); + + if (hcryp->Init.Algorithm == CRYP_AES_CCM) + { + /* Increment CrypHeaderCount to pass in CRYP_GCMCCM_SetPayloadPhase_IT */ + hcryp->CrypHeaderCount++; + } + /* Write the payload Input block in the IN FIFO */ + if (hcryp->Size == 0U) + { + /* Disable interrupts */ + __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE); + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + } + else if (hcryp->Size >= 16U) + { + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + + if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) + { + /* Call Input transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + } + else /* Size < 4 words : first block is the last block*/ + { + /* Compute the number of padding bytes in last block of payload */ + npblb = 16U - (uint32_t)hcryp->Size; + + mode = hcryp->Instance->CR & AES_CR_MODE; + if (((mode == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)) || + ((mode == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM))) + { + /* Specify the number of non-valid bytes using NPBLB register*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U); + } + + /* Number of valid words (lastwordsize) in last block */ + if ((npblb % 4U) == 0U) + { + lastwordsize = (16U - npblb) / 4U; + } + else + { + lastwordsize = ((16U - npblb) / 4U) + 1U; + } + + /* Last block optionally pad the data with zeros*/ + for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++) + { + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + } + while (loopcounter < 4U) + { + /* Pad the data with zeros to have a complete block */ + hcryp->Instance->DINR = 0x0U; + loopcounter++; + } + /* Call Input transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + } + /* Enter header data */ + /* Check first whether header length is small enough to enter the full header in one shot */ + else if (headersize_in_bytes <= 16U) + { + /* Last block optionally pad the data with zeros*/ + for (loopcounter = 0U; (loopcounter < (headersize_in_bytes / 4U)); loopcounter++) + { + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++; + } + /* If the header size is a multiple of words */ + if ((headersize_in_bytes % 4U) == 0U) + { + /* Pad the data with zeros to have a complete block */ + while (loopcounter < 4U) + { + hcryp->Instance->DINR = 0x0U; + loopcounter++; + } + } + else + { + /* Enter last bytes, padded with zeros */ + tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)]; + hcryp->Instance->DINR = tmp; + hcryp->CrypHeaderCount++; + loopcounter++; + /* Pad the data with zeros to have a complete block */ + while (loopcounter < 4U) + { + /* pad the data with zeros to have a complete block */ + hcryp->Instance->DINR = 0x0U; + loopcounter++; + } + } + /* Call Input transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + else + { + /* Write the first input header block in the Input FIFO, + the following header data will be fed after interrupt occurrence */ + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++; + }/* if (hcryp->Init.HeaderSize == 0U) */ /* Header phase is skipped*/ + + } /* end of if (dokeyivconfig == 1U) */ + else /* Key and IV have already been configured, + header has already been processed; + only process here message payload */ + { + /* Write the payload Input block in the IN FIFO */ + if (hcryp->Size == 0U) + { + /* Disable interrupts */ + __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE); + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + } + else if (hcryp->Size >= 16U) + { + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + + if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) + { + /* Call Input transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + } + else /* Size < 4 words : first block is the last block*/ + { + /* Compute the number of padding bytes in last block of payload */ + npblb = 16U - (uint32_t)hcryp->Size; + + mode = hcryp->Instance->CR & AES_CR_MODE; + if (((mode == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)) || + ((mode == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM))) + { + /* Specify the number of non-valid bytes using NPBLB register*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U); + } + + /* Number of valid words (lastwordsize) in last block */ + if ((npblb % 4U) == 0U) + { + lastwordsize = (16U - npblb) / 4U; + } + else + { + lastwordsize = ((16U - npblb) / 4U) + 1U; + } + + /* Last block optionally pad the data with zeros*/ + for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++) + { + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + } + while (loopcounter < 4U) + { + /* Pad the data with zeros to have a complete block */ + hcryp->Instance->DINR = 0x0U; + loopcounter++; + } + /* Call Input transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + } + + return HAL_OK; +} + +/** + * @brief AES CCM encryption/decryption process in DMA mode + * encrypt/decrypt are performed with authentication preparation. + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @retval HAL status + */ +static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp) +{ + uint32_t count; + uint32_t dokeyivconfig = 1U; /* By default, carry out peripheral Key and IV configuration */ + + if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) + { + if (hcryp->KeyIVConfig == 1U) + { + /* If the Key and IV configuration has to be done only once + and if it has already been done, skip it */ + dokeyivconfig = 0U; + hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */ + } + else + { + /* If the Key and IV configuration has to be done only once + and if it has not been done already, do it and set KeyIVConfig + to keep track it won't have to be done again next time */ + hcryp->KeyIVConfig = 1U; + hcryp->SizesSum = hcryp->Size; /* Merely store payload length */ + } + } + else + { + hcryp->SizesSum = hcryp->Size; + } + + if (dokeyivconfig == 1U) + { + + /* Reset CrypHeaderCount */ + hcryp->CrypHeaderCount = 0U; + + + /********************** Init phase ******************************************/ + + CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT); + /* Set the Key */ + if (hcryp->Init.KeyIVConfigSkip != CRYP_KEYNOCONFIG) + { +#if !defined(SAES) + CRYP_SetKey(hcryp, hcryp->Init.KeySize); +#else + if (hcryp->Instance == AES) + { + if (hcryp->Init.KeyMode != CRYP_KEYMODE_SHARED) + { + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + else /*after sharing the key, AES should set KMOD[1:0] to 00.*/ + { + hcryp->Instance->CR &= ~CRYP_KEYMODE_SHARED; + } + } + else /*SAES*/ + { + /* We should re-write Key, in the case where we change key after first operation */ + if ((hcryp->Init.KeySelect == CRYP_KEYSEL_NORMAL) && (hcryp->Init.KeyMode == CRYP_KEYMODE_NORMAL)) + { + /* Set the Key */ + CRYP_SetKey(hcryp, hcryp->Init.KeySize); + } + /* Wait for KEYVALID flag to be set */ + count = CRYP_TIMEOUT_KEYPREPARATION; + do + { + count--; + if (count == 0U) + { + /* Disable the SAES peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_KEYVALID)); + } +#endif /* SAES*/ + } + /* Set the initialization vector (IV) with B0 */ + hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.B0); + hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.B0 + 1U); + hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.B0 + 2U); + hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.B0 + 3U); + + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); + + /* just wait for hash computation */ + count = CRYP_TIMEOUT_GCMCCMINITPHASE; + do + { + count--; + if (count == 0U) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } while (HAL_IS_BIT_CLR(hcryp->Instance->ISR, AES_ISR_CCF)); + + /* Clear CCF flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + + + /********************* Header phase *****************************************/ + + if (CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK) + { + return HAL_ERROR; + } + + } + else + { + /* Initialization and header phases already done, only do payload phase */ + if (CRYP_GCMCCM_SetPayloadPhase_DMA(hcryp) != HAL_OK) + { + return HAL_ERROR; + } + } /* if (DoKeyIVConfig == 1U) */ + + return HAL_OK; +} + +/** + * @brief Sets the payload phase in interrupt mode + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @retval state + */ +static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp) +{ + uint32_t loopcounter; + uint32_t temp[4]; /* Temporary CrypOutBuff */ + uint32_t lastwordsize; + uint32_t npblb; + uint32_t mode; + uint16_t incount; /* Temporary CrypInCount Value */ + uint16_t outcount; /* Temporary CrypOutCount Value */ + uint32_t i; + + /***************************** Payload phase *******************************/ + + /* Read the output block from the output FIFO and put them in temporary buffer then + get CrypOutBuff from temporary buffer*/ + for (i = 0U; i < 4U; i++) + { + temp[i] = hcryp->Instance->DOUTR; + } + i = 0U; + while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U)) + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; + hcryp->CrypOutCount++; + i++; + } + incount = hcryp->CrypInCount; + outcount = hcryp->CrypOutCount; + if ((outcount >= (hcryp->Size / 4U)) && ((incount * 4U) >= hcryp->Size)) + { + + /* When in CCM with Key and IV configuration skipped, don't disable interruptions */ + if (!((hcryp->Init.Algorithm == CRYP_AES_CCM) && (hcryp->KeyIVConfig == 1U))) + { + /* Disable computation complete flag and errors interrupts */ + __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE); + } + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + + /* Call output transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Output complete callback*/ + hcryp->OutCpltCallback(hcryp); +#else + /*Call legacy weak Output complete callback*/ + HAL_CRYP_OutCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + + else if (((hcryp->Size / 4U) - (hcryp->CrypInCount)) >= 4U) + { + +#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) + /* If suspension flag has been raised, suspend processing + only if not already at the end of the payload */ + if (hcryp->SuspendRequest == HAL_CRYP_SUSPEND) + { + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + + /* reset SuspendRequest */ + hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE; + /* Disable Computation Complete Flag and Errors Interrupts */ + __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE); + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_SUSPENDED; + /* Mark that the payload phase is suspended */ + hcryp->Phase = CRYP_PHASE_PAYLOAD_SUSPENDED; + __HAL_UNLOCK(hcryp); + } + else +#endif /* USE_HAL_CRYP_SUSPEND_RESUME */ + { + /* Write the input block in the IN FIFO */ + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) + { + /* Call output transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + } + } + else /* Last block of payload < 128bit*/ + { + /* Compute the number of padding bytes in last block of payload */ + npblb = ((((uint32_t)hcryp->Size / 16U) + 1U) * 16U) - ((uint32_t)hcryp->Size); + + mode = hcryp->Instance->CR & AES_CR_MODE; + if (((mode == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)) || + ((mode == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM))) + { + /* Specify the number of non-valid bytes using NPBLB register*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U); + } + + /* Number of valid words (lastwordsize) in last block */ + if ((npblb % 4U) == 0U) + { + lastwordsize = (16U - npblb) / 4U; + } + else + { + lastwordsize = ((16U - npblb) / 4U) + 1U; + } + + /* Last block optionally pad the data with zeros*/ + for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++) + { + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + } + while (loopcounter < 4U) + { + /* pad the data with zeros to have a complete block */ + hcryp->Instance->DINR = 0x0U; + loopcounter++; + } + } +} + +/** + * @brief Sets the payload phase in DMA mode + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @retval state + */ +static HAL_StatusTypeDef CRYP_GCMCCM_SetPayloadPhase_DMA(CRYP_HandleTypeDef *hcryp) +{ + uint32_t index; + uint32_t npblb; + uint32_t lastwordsize; + uint32_t temp[4]; /* Temporary CrypOutBuff */ + uint32_t count; + uint32_t reg; + + /************************ Payload phase ************************************/ + if (hcryp->Size == 0U) + { + /* Process unLocked */ + __HAL_UNLOCK(hcryp); + + /* Change the CRYP state and phase */ + hcryp->State = HAL_CRYP_STATE_READY; + } + else if (hcryp->Size >= 16U) + { + /*DMA transfer must not include the last block in case of Size is not %16 */ + CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (uint16_t)((hcryp->Size / 16U) * 16U), + (uint32_t)(hcryp->pCrypOutBuffPtr)); + } + else /* length of input data is < 16 */ + { + /* Compute the number of padding bytes in last block of payload */ + npblb = 16U - (uint32_t)hcryp->Size; + + /* Set Npblb in case of AES GCM payload encryption or AES CCM payload decryption to get right tag*/ + reg = hcryp->Instance->CR & (AES_CR_CHMOD | AES_CR_MODE); + if ((reg == (CRYP_AES_GCM_GMAC | CRYP_OPERATINGMODE_ENCRYPT)) || \ + (reg == (CRYP_AES_CCM | CRYP_OPERATINGMODE_DECRYPT))) + { + /* Specify the number of non-valid bytes using NPBLB register*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U); + } + + /* Number of valid words (lastwordsize) in last block */ + if ((npblb % 4U) == 0U) + { + lastwordsize = (16U - npblb) / 4U; + } + else + { + lastwordsize = ((16U - npblb) / 4U) + 1U; + } + + /* last block optionally pad the data with zeros*/ + for (index = 0U; index < lastwordsize; index ++) + { + /* Write the last Input block in the IN FIFO */ + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + } + while (index < 4U) + { + /* pad the data with zeros to have a complete block */ + hcryp->Instance->DINR = 0U; + index++; + } + /* Call the input data transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + /* Wait for CCF flag to be raised */ + count = CRYP_TIMEOUT_GCMCCMHEADERPHASE; + do + { + count-- ; + if (count == 0U) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } while (HAL_IS_BIT_CLR(hcryp->Instance->ISR, AES_ISR_CCF)); + + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + + /*Read the output block from the output FIFO */ + for (index = 0U; index < 4U; index++) + { + /* Read the output block from the output FIFO and put them in temporary + buffer then get CrypOutBuff from temporary buffer */ + temp[index] = hcryp->Instance->DOUTR; + } + for (index = 0U; index < lastwordsize; index++) + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[index]; + hcryp->CrypOutCount++; + } + + /* Change the CRYP state to ready */ + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + /* Call Output transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Output complete callback*/ + hcryp->OutCpltCallback(hcryp); +#else + /*Call legacy weak Output complete callback*/ + HAL_CRYP_OutCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} + +/** + * @brief Sets the header phase in polling mode + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module(Header & HeaderSize) + * @param Timeout Timeout value + * @retval state + */ +static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) +{ + uint32_t loopcounter; + uint32_t size_in_bytes; + uint32_t tmp; + const uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU + }; /* 8-bit data type */ + + /***************************** Header phase for GCM/GMAC or CCM *********************************/ + if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD) + { + size_in_bytes = hcryp->Init.HeaderSize * 4U; + } + else + { + size_in_bytes = hcryp->Init.HeaderSize; + } + + if ((size_in_bytes != 0U)) + { + /* Select header phase */ + CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); + + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); + + /* If size_in_bytes is a multiple of blocks (a multiple of four 32-bits words ) */ + if ((size_in_bytes % 16U) == 0U) + { + /* No padding */ + for (loopcounter = 0U; (loopcounter < (size_in_bytes / 4U)); loopcounter += 4U) + { + /* Write the input block in the data input register */ + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++; + + if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + { + return HAL_ERROR; + } + /* Clear CCF flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + } + } + else + { + /* Write header block in the IN FIFO without last block */ + for (loopcounter = 0U; (loopcounter < ((size_in_bytes / 16U) * 4U)); loopcounter += 4U) + { + /* Write the input block in the data input register */ + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++; + + if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + { + return HAL_ERROR; + } + /* Clear CCF flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + } + /* Write last complete words */ + for (loopcounter = 0U; (loopcounter < ((size_in_bytes / 4U) % 4U)); loopcounter++) + { + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++; + } + /* If the header size is a multiple of words */ + if ((size_in_bytes % 4U) == 0U) + { + /* Pad the data with zeros to have a complete block */ + while (loopcounter < 4U) + { + hcryp->Instance->DINR = 0x0U; + loopcounter++; + } + } + else + { + /* Enter last bytes, padded with zeros */ + tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + tmp &= mask[(hcryp->Init.DataType * 2U) + (size_in_bytes % 4U)]; + hcryp->Instance->DINR = tmp; + loopcounter++; + /* Pad the data with zeros to have a complete block */ + while (loopcounter < 4U) + { + hcryp->Instance->DINR = 0x0U; + loopcounter++; + } + } + + if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) + { + return HAL_ERROR; + } + /* Clear CCF flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + } + } + else + { + /*Workaround 1: only AES, before re-enabling the peripheral, datatype can be configured.*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType); + + /* Select header phase */ + CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); + + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); + } + + return HAL_OK; +} + +/** + * @brief Sets the header phase when using DMA in process + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module(Header & HeaderSize) + * @retval None + */ +static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcryp) +{ + uint32_t loopcounter; + uint32_t headersize_in_bytes; + uint32_t tmp; + const uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU + }; /* 8-bit data type */ + + /***************************** Header phase for GCM/GMAC or CCM *********************************/ + if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD) + { + headersize_in_bytes = hcryp->Init.HeaderSize * 4U; + } + else + { + headersize_in_bytes = hcryp->Init.HeaderSize; + } + + /* Select header phase */ + CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); + + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); + + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; + + /* If header size is at least equal to 16 bytes, feed the header through DMA. + If size_in_bytes is not a multiple of blocks (is not a multiple of four 32-bit words ), + last bytes feeding and padding will be done in CRYP_DMAInCplt() */ + if (headersize_in_bytes >= 16U) + { + /* Initiate header DMA transfer */ + if (CRYP_SetHeaderDMAConfig(hcryp, (uint32_t)(hcryp->Init.Header), + (uint16_t)((headersize_in_bytes / 16U) * 16U)) != HAL_OK) + { + return HAL_ERROR; + } + } + else + { + if (headersize_in_bytes != 0U) + { + /* Header length is larger than 0 and strictly less than 16 bytes */ + /* Write last complete words */ + for (loopcounter = 0U; (loopcounter < (headersize_in_bytes / 4U)); loopcounter++) + { + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + } + /* If the header size is a multiple of words */ + if ((headersize_in_bytes % 4U) == 0U) + { + /* Pad the data with zeros to have a complete block */ + while (loopcounter < 4U) + { + hcryp->Instance->DINR = 0x0U; + loopcounter++; + } + } + else + { + /* Enter last bytes, padded with zeros */ + tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)]; + hcryp->Instance->DINR = tmp; + loopcounter++; + /* Pad the data with zeros to have a complete block */ + while (loopcounter < 4U) + { + hcryp->Instance->DINR = 0x0U; + loopcounter++; + } + } + + if (CRYP_WaitOnCCFlag(hcryp, CRYP_TIMEOUT_GCMCCMHEADERPHASE) != HAL_OK) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + /* Clear CCF flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + } /* if (headersize_in_bytes != 0U) */ + + /* Move to payload phase if header length is null or + if the header length was less than 16 and header written by software instead of DMA */ + + /* Set to 0 the number of non-valid bytes using NPBLB register*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U); + + /* Select payload phase once the header phase is performed */ + CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); + + /* Initiate payload DMA IN and processed data DMA OUT transfers */ + if (CRYP_GCMCCM_SetPayloadPhase_DMA(hcryp) != HAL_OK) + { + return HAL_ERROR; + } + } /* if (headersize_in_bytes >= 16U) */ + + return HAL_OK; +} + +/** + * @brief Sets the header phase in interrupt mode + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module(Header & HeaderSize) + * @retval None + */ +static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp) +{ + uint32_t loopcounter; + uint32_t lastwordsize; + uint32_t npblb; + uint32_t mode; + uint32_t headersize_in_bytes; + uint32_t tmp; + const uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU + }; /* 8-bit data type */ + + if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD) + { + headersize_in_bytes = hcryp->Init.HeaderSize * 4U; + } + else + { + headersize_in_bytes = hcryp->Init.HeaderSize; + } + + /***************************** Header phase *********************************/ + /* Test whether or not the header phase is over. + If the test below is true, move to payload phase */ + if (headersize_in_bytes <= ((uint32_t)(hcryp->CrypHeaderCount) * 4U)) + { + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; + /* Select payload phase */ + MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD); + /* Set to 0 the number of non-valid bytes using NPBLB register*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U); + + if (hcryp->Init.Algorithm == CRYP_AES_CCM) + { + /* Increment CrypHeaderCount to pass in CRYP_GCMCCM_SetPayloadPhase_IT */ + hcryp->CrypHeaderCount++; + } + /* Write the payload Input block in the IN FIFO */ + if (hcryp->Size == 0U) + { + /* Disable interrupts */ + __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE); + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + } + else if (hcryp->Size >= 16U) + { + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + + if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) + { + /* Call the input data transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + } + else /* Size < 4 words : first block is the last block*/ + { + /* Compute the number of padding bytes in last block of payload */ + npblb = 16U - ((uint32_t)hcryp->Size); + mode = hcryp->Instance->CR & AES_CR_MODE; + if (((mode == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)) || + ((mode == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM))) + { + /* Specify the number of non-valid bytes using NPBLB register*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U); + } + + /* Number of valid words (lastwordsize) in last block */ + if ((npblb % 4U) == 0U) + { + lastwordsize = (16U - npblb) / 4U; + } + else + { + lastwordsize = ((16U - npblb) / 4U) + 1U; + } + + /* Last block optionally pad the data with zeros*/ + for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++) + { + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + } + while (loopcounter < 4U) + { + /* Pad the data with zeros to have a complete block */ + hcryp->Instance->DINR = 0x0U; + loopcounter++; + } + /* Call the input data transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + } + else if ((((headersize_in_bytes / 4U) - (hcryp->CrypHeaderCount)) >= 4U)) + { + /* Can enter full 4 header words */ +#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) + /* If suspension flag has been raised, suspend processing + only if not already at the end of the header */ + if (hcryp->SuspendRequest == HAL_CRYP_SUSPEND) + { + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + + /* reset SuspendRequest */ + hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE; + /* Disable Computation Complete Flag and Errors Interrupts */ + __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE); + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_SUSPENDED; + /* Mark that the payload phase is suspended */ + hcryp->Phase = CRYP_PHASE_HEADER_SUSPENDED; + __HAL_UNLOCK(hcryp); + } + else +#endif /* USE_HAL_CRYP_SUSPEND_RESUME */ + { + /* Write the input block in the IN FIFO */ + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++; + } + } + else /* Write last header block (4 words), padded with zeros if needed */ + { + + for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 4U) % 4U)); loopcounter++) + { + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + } + /* If the header size is a multiple of words */ + if ((headersize_in_bytes % 4U) == 0U) + { + /* Pad the data with zeros to have a complete block */ + while (loopcounter < 4U) + { + hcryp->Instance->DINR = 0x0U; + loopcounter++; + hcryp->CrypHeaderCount++; + } + } + else + { + /* Enter last bytes, padded with zeros */ + tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)]; + hcryp->Instance->DINR = tmp; + loopcounter++; + hcryp->CrypHeaderCount++; + /* Pad the data with zeros to have a complete block */ + while (loopcounter < 4U) + { + hcryp->Instance->DINR = 0x0U; + loopcounter++; + hcryp->CrypHeaderCount++; + } + } + } +} + +/** + * @brief Handle CRYP hardware block Timeout when waiting for CCF flag to be raised. + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module. + * @param Timeout Timeout duration. + * @note This function can only be used in thread mode. + * @retval HAL status + */ +static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) +{ + uint32_t tickstart; + + /* Get timeout */ + tickstart = HAL_GetTick(); + + while (HAL_IS_BIT_CLR(hcryp->Instance->ISR, AES_ISR_CCF)) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + __HAL_CRYP_DISABLE(hcryp); + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } + } + return HAL_OK; +} + +/** + * @brief Wait for Computation Complete Flag (CCF) to raise then clear it. + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module. + * @param Timeout Timeout duration. + * @note This function can be used in thread or handler mode. + * @retval HAL status + */ +static void CRYP_ClearCCFlagWhenHigh(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) +{ + uint32_t count = Timeout; + + do + { + count-- ; + if (count == 0U) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + hcryp->State = HAL_CRYP_STATE_READY; + +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered error callback*/ + hcryp->ErrorCallback(hcryp); +#else + /*Call legacy weak error callback*/ + HAL_CRYP_ErrorCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + } while (HAL_IS_BIT_CLR(hcryp->Instance->ISR, AES_ISR_CCF)); + + /* Clear CCF flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); +} + +#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) +/** + * @brief In case of message processing suspension, read the Initialization Vector. + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module. + * @param Output Pointer to the buffer containing the saved Initialization Vector. + * @note This value has to be stored for reuse by writing the AES_IVRx registers + * as soon as the suspended processing has to be resumed. + * @retval None + */ +static void CRYP_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, const uint32_t *Output) +{ + uint32_t outputaddr = (uint32_t)Output; + + *(uint32_t *)(outputaddr) = hcryp->Instance->IVR3; + outputaddr += 4U; + *(uint32_t *)(outputaddr) = hcryp->Instance->IVR2; + outputaddr += 4U; + *(uint32_t *)(outputaddr) = hcryp->Instance->IVR1; + outputaddr += 4U; + *(uint32_t *)(outputaddr) = hcryp->Instance->IVR0; +} + +/** + * @brief In case of message processing resumption, rewrite the Initialization + * Vector in the AES_IVRx registers. + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module. + * @param Input Pointer to the buffer containing the saved Initialization Vector to + * write back in the CRYP hardware block. + * @note AES must be disabled when reconfiguring the IV values. + * @retval None + */ +static void CRYP_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, const uint32_t *Input) +{ + uint32_t ivaddr = (uint32_t)Input; + + hcryp->Instance->IVR3 = *(uint32_t *)(ivaddr); + ivaddr += 4U; + hcryp->Instance->IVR2 = *(uint32_t *)(ivaddr); + ivaddr += 4U; + hcryp->Instance->IVR1 = *(uint32_t *)(ivaddr); + ivaddr += 4U; + hcryp->Instance->IVR0 = *(uint32_t *)(ivaddr); +} + +/** + * @brief In case of message GCM/GMAC/CCM processing suspension, + * read the Suspend Registers. + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module. + * @param Output Pointer to the buffer containing the saved Suspend Registers. + * @note These values have to be stored for reuse by writing back the AES_SUSPxR registers + * as soon as the suspended processing has to be resumed. + * @retval None + */ +static void CRYP_Read_SuspendRegisters(CRYP_HandleTypeDef *hcryp, const uint32_t *Output) +{ + uint32_t outputaddr = (uint32_t)Output; + uint32_t count = 0U; + + /* In case of GCM payload phase encryption, check that suspension can be carried out */ + if (READ_BIT(hcryp->Instance->CR, (AES_CR_CHMOD | AES_CR_GCMPH | AES_CR_MODE)) == (CRYP_AES_GCM_GMAC | + AES_CR_GCMPH_1 | 0x0)) + { + + /* Wait for BUSY flag to be cleared */ + count = 0xFFF; + do + { + count--; + if (count == 0U) + { + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + HAL_CRYP_ErrorCallback(hcryp); + return; + } + } while (HAL_IS_BIT_SET(hcryp->Instance->SR, AES_SR_BUSY)); + + } + + *(uint32_t *)(outputaddr) = hcryp->Instance->SUSP7R; + outputaddr += 4U; + *(uint32_t *)(outputaddr) = hcryp->Instance->SUSP6R; + outputaddr += 4U; + *(uint32_t *)(outputaddr) = hcryp->Instance->SUSP5R; + outputaddr += 4U; + *(uint32_t *)(outputaddr) = hcryp->Instance->SUSP4R; + outputaddr += 4U; + *(uint32_t *)(outputaddr) = hcryp->Instance->SUSP3R; + outputaddr += 4U; + *(uint32_t *)(outputaddr) = hcryp->Instance->SUSP2R; + outputaddr += 4U; + *(uint32_t *)(outputaddr) = hcryp->Instance->SUSP1R; + outputaddr += 4U; + *(uint32_t *)(outputaddr) = hcryp->Instance->SUSP0R; +} + +/** + * @brief In case of message GCM/GMAC/CCM processing resumption, rewrite the Suspend + * Registers in the AES_SUSPxR registers. + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module. + * @param Input Pointer to the buffer containing the saved suspend registers to + * write back in the CRYP hardware block. + * @note AES must be disabled when reconfiguring the suspend registers. + * @retval None + */ +static void CRYP_Write_SuspendRegisters(CRYP_HandleTypeDef *hcryp, const uint32_t *Input) +{ + uint32_t ivaddr = (uint32_t)Input; + + hcryp->Instance->SUSP7R = *(uint32_t *)(ivaddr); + ivaddr += 4U; + hcryp->Instance->SUSP6R = *(uint32_t *)(ivaddr); + ivaddr += 4U; + hcryp->Instance->SUSP5R = *(uint32_t *)(ivaddr); + ivaddr += 4U; + hcryp->Instance->SUSP4R = *(uint32_t *)(ivaddr); + ivaddr += 4U; + hcryp->Instance->SUSP3R = *(uint32_t *)(ivaddr); + ivaddr += 4U; + hcryp->Instance->SUSP2R = *(uint32_t *)(ivaddr); + ivaddr += 4U; + hcryp->Instance->SUSP1R = *(uint32_t *)(ivaddr); + ivaddr += 4U; + hcryp->Instance->SUSP0R = *(uint32_t *)(ivaddr); +} + +/** + * @brief In case of message GCM/GMAC/CCM processing suspension, read the Key Registers. + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module. + * @param Output Pointer to the buffer containing the saved Key Registers. + * @param KeySize Indicates the key size (128 or 256 bits). + * @note These values have to be stored for reuse by writing back the AES_KEYRx registers + * as soon as the suspended processing has to be resumed. + * @retval None + */ +static void CRYP_Read_KeyRegisters(CRYP_HandleTypeDef *hcryp, const uint32_t *Output, uint32_t KeySize) +{ + uint32_t keyaddr = (uint32_t)Output; + + switch (KeySize) + { + case CRYP_KEYSIZE_256B: + *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey); + keyaddr += 4U; + *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 1U); + keyaddr += 4U; + *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 2U); + keyaddr += 4U; + *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 3U); + keyaddr += 4U; + *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 4U); + keyaddr += 4U; + *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 5U); + keyaddr += 4U; + *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 6U); + keyaddr += 4U; + *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 7U); + break; + case CRYP_KEYSIZE_128B: + *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey); + keyaddr += 4U; + *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 1U); + keyaddr += 4U; + *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 2U); + keyaddr += 4U; + *(uint32_t *)(keyaddr) = *(uint32_t *)(hcryp->Init.pKey + 3U); + break; + default: + break; + } +} + +/** + * @brief In case of message GCM/GMAC (CCM/CMAC when applicable) processing resumption, rewrite the Key + * Registers in the AES_KEYRx registers. + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module. + * @param Input Pointer to the buffer containing the saved key registers to + * write back in the CRYP hardware block. + * @param KeySize Indicates the key size (128 or 256 bits) + * @note AES must be disabled when reconfiguring the Key registers. + * @retval None + */ +static void CRYP_Write_KeyRegisters(CRYP_HandleTypeDef *hcryp, const uint32_t *Input, uint32_t KeySize) +{ + uint32_t keyaddr = (uint32_t)Input; + + if (KeySize == CRYP_KEYSIZE_256B) + { + hcryp->Instance->KEYR7 = *(uint32_t *)(keyaddr); + keyaddr += 4U; + hcryp->Instance->KEYR6 = *(uint32_t *)(keyaddr); + keyaddr += 4U; + hcryp->Instance->KEYR5 = *(uint32_t *)(keyaddr); + keyaddr += 4U; + hcryp->Instance->KEYR4 = *(uint32_t *)(keyaddr); + keyaddr += 4U; + } + + hcryp->Instance->KEYR3 = *(uint32_t *)(keyaddr); + keyaddr += 4U; + hcryp->Instance->KEYR2 = *(uint32_t *)(keyaddr); + keyaddr += 4U; + hcryp->Instance->KEYR1 = *(uint32_t *)(keyaddr); + keyaddr += 4U; + hcryp->Instance->KEYR0 = *(uint32_t *)(keyaddr); +} + +/** + * @brief Authentication phase resumption in case of GCM/GMAC/CCM process in interrupt mode + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module(Header & HeaderSize) + * @retval None + */ +static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp) +{ + uint32_t loopcounter; + uint16_t lastwordsize; + uint16_t npblb; + uint32_t cr_temp; + + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_RWEIF | CRYP_CLEAR_CCF); + + /* Enable computation complete flag and error interrupts */ + __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE); + + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); + + /* Case of header phase resumption =================================================*/ + if (hcryp->Phase == CRYP_PHASE_HEADER_SUSPENDED) + { + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; + + /* Select header phase */ + CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); + + if (((hcryp->Init.HeaderSize) - (hcryp->CrypHeaderCount) >= 4U)) + { + /* Write the input block in the IN FIFO */ + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++; + } + else /*HeaderSize < 4 or HeaderSize >4 & HeaderSize %4 != 0*/ + { + /* Last block optionally pad the data with zeros*/ + for (loopcounter = 0U; loopcounter < (hcryp->Init.HeaderSize % 4U); loopcounter++) + { + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++; + } + while (loopcounter < 4U) + { + /* pad the data with zeros to have a complete block */ + hcryp->Instance->DINR = 0x0U; + loopcounter++; + } + } + } + /* Case of payload phase resumption =================================================*/ + else + { + if (hcryp->Phase == CRYP_PHASE_PAYLOAD_SUSPENDED) + { + + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; + + /* Select payload phase once the header phase is performed */ + MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD); + + /* Set to 0 the number of non-valid bytes using NPBLB register*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U); + + if (((hcryp->Size / 4U) - (hcryp->CrypInCount)) >= 4U) + { + /* Write the input block in the IN FIFO */ + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) + { + /* Call input transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + } + else /* Last block of payload < 128bit*/ + { + /* Compute the number of padding bytes in last block of payload */ + npblb = (((hcryp->Size / 16U) + 1U) * 16U) - (hcryp->Size); + cr_temp = hcryp->Instance->CR; + if ((((cr_temp & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)) || + (((cr_temp & AES_CR_MODE) == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM))) + { + /* Specify the number of non-valid bytes using NPBLB register*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, ((uint32_t)npblb) << 20U); + } + + /* Number of valid words (lastwordsize) in last block */ + if ((npblb % 4U) == 0U) + { + lastwordsize = (16U - npblb) / 4U; + } + else + { + lastwordsize = ((16U - npblb) / 4U) + 1U; + } + + /* Last block optionally pad the data with zeros*/ + for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++) + { + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + } + while (loopcounter < 4U) + { + /* pad the data with zeros to have a complete block */ + hcryp->Instance->DINR = 0x0U; + loopcounter++; + } + } + } + } +} +#endif /* defined (USE_HAL_CRYP_SUSPEND_RESUME) */ +/** + * @} + */ + + +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#endif /* AES */ +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_cryp_ex.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_cryp_ex.c new file mode 100644 index 0000000000..184ae6b097 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_cryp_ex.c @@ -0,0 +1,902 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_cryp_ex.c + * @author MCD Application Team + * @brief CRYPEx HAL module driver. + * This file provides firmware functions to manage the extended + * functionalities of the Cryptography (CRYP) peripheral. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @addtogroup CRYPEx + * @{ + */ + +#if defined(AES) + +#ifdef HAL_CRYP_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup CRYPEx_Private_Defines + * @{ + */ + +#define CRYP_PHASE_INIT 0x00000000U /*!< GCM/GMAC (or CCM) init phase */ +#define CRYP_PHASE_HEADER AES_CR_GCMPH_0 /*!< GCM/GMAC or CCM header phase */ +#define CRYP_PHASE_PAYLOAD AES_CR_GCMPH_1 /*!< GCM(/CCM) payload phase */ +#define CRYP_PHASE_FINAL AES_CR_GCMPH /*!< GCM/GMAC or CCM final phase */ + +#define CRYP_OPERATINGMODE_ENCRYPT 0x00000000U /*!< Encryption mode */ +#define CRYP_OPERATINGMODE_KEYDERIVATION AES_CR_MODE_0 /*!< Key derivation mode only used when performing ECB and CBC decryptions */ +#define CRYP_OPERATINGMODE_DECRYPT AES_CR_MODE_1 /*!< Decryption */ +#define CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT AES_CR_MODE /*!< Key derivation and decryption only used when performing ECB and CBC decryptions */ + +#define CRYPEx_PHASE_PROCESS 0x02U /*!< CRYP peripheral is in processing phase */ +#define CRYPEx_PHASE_FINAL 0x03U /*!< CRYP peripheral is in final phase this is relevant only with CCM and GCM modes */ + +/* CTR0 information to use in CCM algorithm */ +#define CRYP_CCM_CTR0_0 0x07FFFFFFU +#define CRYP_CCM_CTR0_3 0xFFFFFF00U + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +#if defined(SAES) +static HAL_StatusTypeDef CRYPEx_KeyDecrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); +static HAL_StatusTypeDef CRYPEx_KeyEncrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); +static HAL_StatusTypeDef CRYPEx_KeyGeneration(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); +#endif /* defined(SAES) */ +/* Exported functions---------------------------------------------------------*/ +/** @addtogroup CRYPEx_Exported_Functions + * @{ + */ + +/** @defgroup CRYPEx_Exported_Functions_Group1 Extended AES processing functions + * @brief Extended processing functions. + * +@verbatim + ============================================================================== + ##### Extended AES processing functions ##### + ============================================================================== + [..] This section provides functions allowing to generate the authentication + TAG in Polling mode + (#)HAL_CRYPEx_AESGCM_GenerateAuthTAG + (#)HAL_CRYPEx_AESCCM_GenerateAuthTAG + they should be used after Encrypt/Decrypt operation. + +@endverbatim + * @{ + */ + +/** + * @brief generate the GCM authentication TAG. + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param pAuthTag Pointer to the authentication buffer + * the pAuthTag generated here is 128bits length, if the TAG length is + * less than 128bits, user should consider only the valid part of pAuthTag + * buffer which correspond exactly to TAG length. + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, const uint32_t *pAuthTag, + uint32_t Timeout) +{ + /* Assume first Init.HeaderSize is in words */ + uint64_t headerlength = (uint64_t)hcryp->Init.HeaderSize * 32U; /* Header length in bits */ + uint64_t inputlength = (uint64_t)hcryp->SizesSum * 8U; /* Input length in bits */ + uint32_t tagaddr = (uint32_t)pAuthTag; + uint32_t i; + uint32_t tickstart; + + /* Correct headerlength if Init.HeaderSize is actually in bytes */ + if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_BYTE) + { + headerlength /= 4U; + } + + if (hcryp->State == HAL_CRYP_STATE_READY) + { + __HAL_LOCK(hcryp); + + /* Change the CRYP peripheral state */ + hcryp->State = HAL_CRYP_STATE_BUSY; + + /* Check if initialization phase has already been performed */ + if (hcryp->Phase == CRYPEx_PHASE_PROCESS) + { + /* Change the CRYP phase */ + hcryp->Phase = CRYPEx_PHASE_FINAL; + + /* Select final phase */ + MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_FINAL); + + /* Write into the AES_DINR register the number of bits in header (64 bits) + followed by the number of bits in the payload */ + hcryp->Instance->DINR = 0U; + hcryp->Instance->DINR = (uint32_t)(headerlength); + hcryp->Instance->DINR = 0U; + hcryp->Instance->DINR = (uint32_t)(inputlength); + + /* Wait for CCF flag to be raised */ + tickstart = HAL_GetTick(); + while (HAL_IS_BIT_CLR(hcryp->Instance->ISR, AES_ISR_CCF)) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } + } + + /* Read the authentication TAG in the output FIFO */ + for (i = 0U; i < 4U; i++) + { + *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR; + tagaddr += 4U; + } + + /* Clear CCF flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + + /* Disable the peripheral */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change the CRYP peripheral state */ + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + } + else /* Initialization phase has not been performed */ + { + /* Disable the Peripheral */ + __HAL_CRYP_DISABLE(hcryp); + + /* Sequence error code field */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE; + + /* Change the CRYP peripheral state */ + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } + else + { + /* Busy error code field */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY; + return HAL_ERROR; + } + /* Return function status */ + return HAL_OK; +} + +/** + * @brief AES CCM Authentication TAG generation. + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param pAuthTag Pointer to the authentication buffer + * the pAuthTag generated here is 128bits length, if the TAG length is + * less than 128bits, user should consider only the valid part of pAuthTag + * buffer which correspond exactly to TAG length. + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, const uint32_t *pAuthTag, + uint32_t Timeout) +{ + uint32_t tagaddr = (uint32_t)pAuthTag; + uint32_t i; + uint32_t tickstart; + + if (hcryp->State == HAL_CRYP_STATE_READY) + { + __HAL_LOCK(hcryp); + + /* Disable interrupts in case they were kept enabled to proceed + a single message in several iterations */ + __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_RWEIE | CRYP_IT_KEIE); + + /* Change the CRYP peripheral state */ + hcryp->State = HAL_CRYP_STATE_BUSY; + + /* Check if initialization phase has already been performed */ + if (hcryp->Phase == CRYPEx_PHASE_PROCESS) + { + /* Change the CRYP phase */ + hcryp->Phase = CRYPEx_PHASE_FINAL; + /* Select final phase */ + MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_FINAL); + + /* Wait for CCF flag to be raised */ + tickstart = HAL_GetTick(); + while (HAL_IS_BIT_CLR(hcryp->Instance->ISR, AES_ISR_CCF)) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* Disable the CRYP peripheral Clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } + } + + /* Read the authentication TAG in the output FIFO */ + for (i = 0U; i < 4U; i++) + { + *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR; + tagaddr += 4U; + } + + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + + /* Change the CRYP peripheral state */ + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + + /* Disable CRYP */ + __HAL_CRYP_DISABLE(hcryp); + } + else /* Initialization phase has not been performed */ + { + /* Disable the peripheral */ + __HAL_CRYP_DISABLE(hcryp); + + /* Sequence error code field */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE; + + /* Change the CRYP peripheral state */ + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } + else + { + /* Busy error code field */ + hcryp->ErrorCode = HAL_CRYP_ERROR_BUSY; + return HAL_ERROR; + } + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +#if defined(SAES) + +/** @defgroup CRYPEx_Exported_Functions_Group2 Wrap and Unwrap key functions + * @brief Wrap and Unwrap key functions. + * +@verbatim + ============================================================================== + ##### Wrap and Unwrap key ##### + ============================================================================== + [..] This section provides API allowing to wrap (encrypt) and unwrap (decrypt) + key using one of the following keys, and AES Algorithm. + Key selection : + - Derived hardware unique key (DHUK) + - XOR of DHUK and BHK + - Boot hardware key (BHK) + +@endverbatim + * @{ + */ + +/** + * @brief Wrap (encrypt) application keys. + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param pInput Pointer to the Key buffer to encrypt in case of ECB or CBC + * @param pOutput Pointer to the Key buffer encrypted in case of ECB or CBC + * @param Timeout Specify Timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYPEx_WrapKey(CRYP_HandleTypeDef *hcryp, uint32_t *pInput, uint32_t *pOutput, uint32_t Timeout) +{ + HAL_StatusTypeDef status; + uint32_t algo; + + if (hcryp->State == HAL_CRYP_STATE_READY) + { + /* Change state Busy */ + hcryp->State = HAL_CRYP_STATE_BUSY; + __HAL_LOCK(hcryp); + + /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/ + hcryp->CrypInCount = 0U; + hcryp->CrypOutCount = 0U; + hcryp->pCrypInBuffPtr = pInput; + hcryp->pCrypOutBuffPtr = pOutput; + + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Set the operating mode*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_KMOD, CRYP_KEYMODE_WRAPPED); + + /* Encryption operating mode(Mode 0)*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT); + + + /* algo get algorithm selected */ + algo = hcryp->Instance->CR & AES_CR_CHMOD; + + switch (algo) + { + case CRYP_AES_ECB: + case CRYP_AES_CBC: + /* AES decryption */ + status = CRYPEx_KeyEncrypt(hcryp, Timeout); + break; + case CRYP_AES_CTR: + /* AES Key generation */ + status = CRYPEx_KeyGeneration(hcryp, Timeout); + break; + default: + hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; + status = HAL_ERROR; + break; + } + } + else + { + /* Busy error code field */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY; + status = HAL_ERROR; + } + /* Return function status */ + return status; +} + +/** + * @brief Unwrap (Decrypt) application keys. + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param pInput Pointer to the Key buffer to decrypt or generated key in case of CTR. + * @param Timeout Specify Timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYPEx_UnwrapKey(CRYP_HandleTypeDef *hcryp, uint32_t *pInput, uint32_t Timeout) +{ + HAL_StatusTypeDef status; + uint32_t algo; + + if (hcryp->State == HAL_CRYP_STATE_READY) + { + /* Change state Busy */ + hcryp->State = HAL_CRYP_STATE_BUSY; + + __HAL_LOCK(hcryp); + + /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters */ + hcryp->CrypInCount = 0U; + hcryp->CrypOutCount = 0U; + hcryp->pCrypInBuffPtr = pInput; + + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Set the operating mode*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_KMOD, CRYP_KEYMODE_WRAPPED); + + /* Decryption operating mode(Mode 3)*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); + + /* algo get algorithm selected */ + algo = hcryp->Instance->CR & AES_CR_CHMOD; + + switch (algo) + { + case CRYP_AES_ECB: + case CRYP_AES_CBC: + /* AES decryption */ + status = CRYPEx_KeyDecrypt(hcryp, Timeout); + break; + + case CRYP_AES_CTR: + /* AES Key generation */ + status = CRYPEx_KeyGeneration(hcryp, Timeout); + break; + default: + hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; + status = HAL_ERROR; + break; + } + } + else + { + /* Busy error code field */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY; + status = HAL_ERROR; + } + /* Return function status */ + return status; +} + +/** + * @} + */ + +/** @defgroup CRYPEx_Exported_Functions_Group3 Encrypt and Decrypt Shared key functions + * @brief Encrypt and Decrypt Shared key functions. + * +@verbatim + ============================================================================== + ##### Encrypt and Decrypt Shared key functions ##### + ============================================================================== + [..] This section provides API allowing to Encrypt and Decrypt Shared key + +@endverbatim + * @{ + */ + +/** + * @brief Encrypt Shared key. + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param pKey Pointer to the Key buffer to share + * @param pOutput Pointer to the Key buffer encrypted + * @param ID Key share identification + * @param Timeout Specify Timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYPEx_EncryptSharedKey(CRYP_HandleTypeDef *hcryp, uint32_t *pKey, uint32_t *pOutput, uint32_t ID, + uint32_t Timeout) +{ + HAL_StatusTypeDef status; + uint32_t algo; + + if (hcryp->State == HAL_CRYP_STATE_READY) + { + /* Change state Busy */ + hcryp->State = HAL_CRYP_STATE_BUSY; + __HAL_LOCK(hcryp); + + /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters */ + hcryp->CrypInCount = 0U; + hcryp->CrypOutCount = 0U; + hcryp->pCrypInBuffPtr = pKey; + hcryp->pCrypOutBuffPtr = pOutput; + + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Set the operating mode */ + MODIFY_REG(hcryp->Instance->CR, AES_CR_KMOD | AES_CR_KSHAREID, CRYP_KEYMODE_SHARED | ID); + + /* Encryption operating mode(Mode 0)*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT); + + /* algo get algorithm selected */ + algo = hcryp->Instance->CR & AES_CR_CHMOD; + + switch (algo) + { + case CRYP_AES_ECB: + case CRYP_AES_CBC: + /* AES decryption */ + status = CRYPEx_KeyEncrypt(hcryp, Timeout); + break; + case CRYP_AES_CTR: + /* AES CTR key generation */ + status = CRYPEx_KeyGeneration(hcryp, Timeout); + break; + default: + hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; + status = HAL_ERROR; + break; + } + } + else + { + /* Busy error code field */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY; + status = HAL_ERROR; + } + /* Return function status */ + return status; +} + +/** + * @brief Decrypt Shared key. + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param pKey Pointer to the Key buffer to share + * @param ID Key share identification + * @param Timeout Specify Timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CRYPEx_DecryptSharedKey(CRYP_HandleTypeDef *hcryp, uint32_t *pKey, uint32_t ID, uint32_t Timeout) +{ + HAL_StatusTypeDef status; + uint32_t algo; + + if (hcryp->State == HAL_CRYP_STATE_READY) + { + /* Change state Busy */ + hcryp->State = HAL_CRYP_STATE_BUSY; + __HAL_LOCK(hcryp); + + /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters */ + hcryp->CrypInCount = 0U; + hcryp->CrypOutCount = 0U; + hcryp->pCrypInBuffPtr = pKey; + + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Set the operating mode */ + MODIFY_REG(hcryp->Instance->CR, AES_CR_KMOD | AES_CR_KSHAREID, CRYP_KEYMODE_SHARED | ID); + + /* Decryption operating mode(Mode 3)*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); + + /* algo get algorithm selected */ + algo = hcryp->Instance->CR & AES_CR_CHMOD; + + switch (algo) + { + case CRYP_AES_ECB: + case CRYP_AES_CBC: + /* AES decryption */ + status = CRYPEx_KeyDecrypt(hcryp, Timeout); + break; + case CRYP_AES_CTR: + /* AES CTR key generation */ + status = CRYPEx_KeyGeneration(hcryp, Timeout); + break; + default: + hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; + status = HAL_ERROR; + break; + } + } + else + { + /* Busy error code field */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY; + status = HAL_ERROR; + } + /* Return function status */ + return status; +} + +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @addtogroup CRYP_Private_Functions + * @{ + */ +/** + * @brief Key Decryption + * @param hcryp pointer to a CRYP_HandleTypeDef structure + * @param Timeout specify Timeout value + * @note It is strongly recommended to select hardware secret keys + * @retval HAL status + */ +static HAL_StatusTypeDef CRYPEx_KeyDecrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) +{ + uint32_t incount; /* Temporary CrypInCount Value */ + uint32_t i; + uint32_t tickstart; + + /* key preparation for decryption, operating mode 2*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION); + + /* Enable CRYP */ + __HAL_CRYP_ENABLE(hcryp); + + /* Wait for CCF flag to be raised */ + tickstart = HAL_GetTick(); + while (HAL_IS_BIT_CLR(hcryp->Instance->ISR, AES_ISR_CCF)) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } + } + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + + /* End of Key preparation for ECB/CBC */ + /* Return to decryption operating mode(Mode 3)*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); + + if (hcryp->Init.Algorithm != CRYP_AES_ECB) + { + /* Set the Initialization Vector */ + hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect); + hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U); + hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U); + hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U); + } + /* Enable CRYP */ + __HAL_CRYP_ENABLE(hcryp); + + /* Set the phase */ + hcryp->Phase = CRYPEx_PHASE_PROCESS; + + if (hcryp->Init.KeySize == CRYP_KEYSIZE_128B) + { + incount = 4U; + } + else + { + incount = 8U; + } + while (hcryp->CrypInCount < incount) + { + /* Write four times to input the key to encrypt */ + for (i = 0U; i < 4U; i++) + { + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + } + /* Wait for CCF flag to be raised */ + tickstart = HAL_GetTick(); + while (HAL_IS_BIT_CLR(hcryp->Instance->ISR, AES_ISR_CCF)) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } + } + + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + } + + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change the CRYP peripheral state */ + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_OK; +} + +/** + * @brief Key Encryption + * @param hcryp pointer to a CRYP_HandleTypeDef structure + * @param Timeout specify Timeout value + * @retval HAL status + */ +static HAL_StatusTypeDef CRYPEx_KeyEncrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) +{ + uint32_t incount; /* Temporary CrypInCount Value */ + uint32_t i; + uint32_t tickstart; + uint32_t temp; /* Temporary CrypOutBuff */ + + if (hcryp->Init.Algorithm != CRYP_AES_ECB) + { + /* Set the Initialization Vector */ + hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect); + hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U); + hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U); + hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U); + } + + /* Enable CRYP */ + __HAL_CRYP_ENABLE(hcryp); + + /* Set the phase */ + hcryp->Phase = CRYPEx_PHASE_PROCESS; + + if (hcryp->Init.KeySize == CRYP_KEYSIZE_128B) + { + incount = 4U; + } + else + { + incount = 8U; + } + while (hcryp->CrypInCount < incount) + { + for (i = 0U; i < 4U; i++) + { + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + } + /* Wait for CCF flag to be raised */ + tickstart = HAL_GetTick(); + while (HAL_IS_BIT_CLR(hcryp->Instance->ISR, AES_ISR_CCF)) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } + } + + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + + /* Read the output block from the output FIFO and put them in temporary buffer then + get CrypOutBuff from temporary buffer */ + for (i = 0U; i < 4U; i++) + { + temp = hcryp->Instance->DOUTR; + *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp; + hcryp->CrypOutCount++; + } + } + + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change the CRYP peripheral state */ + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_OK; +} +/** + * @brief Key Generation + * @param hcryp pointer to a CRYP_HandleTypeDef structure + * @param Timeout specify Timeout value + * @retval HAL status + */ +static HAL_StatusTypeDef CRYPEx_KeyGeneration(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) +{ + uint32_t tickstart; + + /* No swap, DATATYPE must be kept to 0x0.*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, CRYP_NO_SWAP); + + /*Writes initialization vector in IV registers*/ + if (hcryp->Init.pInitVect != NULL) + { + /* Set the Initialization Vector*/ + hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect); + hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1U); + hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2U); + /* Keeping the two least significant bit of SAES_IVR0 to 00 */ + hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3U); + hcryp->Instance->IVR0 &= 0xFFFFFFFCU ; + } + else + { + return HAL_ERROR; + } + + /* Enable CRYP */ + __HAL_CRYP_ENABLE(hcryp); + + /* Wait for CCF flag to be raised */ + tickstart = HAL_GetTick(); + while (HAL_IS_BIT_CLR(hcryp->Instance->ISR, AES_ISR_CCF)) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } + } + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEAR_CCF); + + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change the CRYP peripheral state */ + hcryp->State = HAL_CRYP_STATE_READY; + __HAL_UNLOCK(hcryp); + + return HAL_OK; +} +#endif /* defined(SAES)*/ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#endif /* AES */ +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_dma.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_dma.c new file mode 100644 index 0000000000..a4e3e243df --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_dma.c @@ -0,0 +1,1670 @@ +/** + ********************************************************************************************************************** + * @file stm32wbaxx_hal_dma.c + * @author MCD Application Team + * @brief This file provides firmware functions to manage the following functionalities of the Direct Memory Access + * (DMA) peripheral: + * + Initialization/De-Initialization Functions + * + I/O Operation Functions + * + State and Errors Functions + * + DMA Attributes Functions + * + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + @verbatim + ====================================================================================================================== + ##### How to use this driver ##### + ====================================================================================================================== + + [..] + DMA transfer modes are divided to 2 major categories : + (+) Normal transfers (legacy) + (+) Linked-list transfers + + [..] + Normal transfers mode is initialized via the standard module and linked-list mode is configured via the extended + module. + + [..] + Additionally to linked-list capability, all advanced DMA features are managed and configured via the extended + module as extensions to normal mode. + Advanced features are : + (+) Repeated block feature. + (+) Trigger feature. + (+) Data handling feature. + + [..] + DMA Legacy circular transfer, is replaced by circular linked-list configuration. + + + *** Initialization and De-Initialization *** + ============================================ + [..] + For a given channel, enable and configure the peripheral to be connected to the DMA Channel (except for internal + SRAM/FLASH memories: no initialization is necessary) please refer to Reference manual for connection between + peripherals and DMA requests. + + [..] + For a given channel, use HAL_DMA_Init function to program the required configuration for normal transfer through + the following parameters: + + (+) Request : Specifies the DMA channel request + Request parameters : + (++) can be a value of DMA_Request_Selection + + (+) BlkHWRequest : Specifies the Block hardware request mode for DMA channel + (++) can be a value of DMA_Block_Request + + (+) Direction : Specifies the transfer direction for DMA channel + (++) can be a value of DMA_Transfer_Direction + + (+) SrcInc : Specifies the source increment mode for the DMA channel + (++) can be a value of DMA_Source_Increment_Mode + + (+) DestInc : Specifies the destination increment mode for the DMA channel + (++) can be a value of DMA_Destination_Increment_Mode + + (+) SrcDataWidth : Specifies the source data width for the DMA channel + (++) can be a value of DMA_Source_Data_Width + + (+) DestDataWidth : Specifies the destination data width for the DMA channel + (++) can be a value of DMA_Destination_Data_Width + + (+) Priority : Specifies the priority for the DMA channel + (++) can be a value of DMA_Priority_Level + + (+) SrcBurstLength : Specifies the source burst length (number of beats) for the DMA channel + (++) can be a value of between 1 and 64 + + (+) DestBurstLength : Specifies the destination burst length (number of beats) for the DMA channel + (++) can be a value of between 1 and 64 + + (+) TransferAllocatedPort : Specifies the source and destination allocated ports + (++) can be a value of DMA_Transfer_Allocated_Port + + (+) TransferEventMode : Specifies the transfer event mode for the DMA channel + (++) can be a value of DMA_Transfer_Event_Mode + + (+) Mode : Specifies the transfer mode for the DMA channel + (++) can be DMA_NORMAL + + *** Polling mode IO operation *** + ================================= + [..] + (+) Use HAL_DMA_Start() to start a DMA normal transfer after the configuration of source address, destination + address and the size of data to be transferred. + + (+) Use HAL_DMA_PollForTransfer() to poll for selected transfer level. In this case a fixed Timeout can be + configured by User depending on his application. + Transfer level can be : + (++) HAL_DMA_HALF_TRANSFER + (++) HAL_DMA_FULL_TRANSFER + For circular transfer, this API returns an HAL_ERROR with HAL_DMA_ERROR_NOT_SUPPORTED error code. + + (+) Use HAL_DMA_Abort() function to abort any ongoing DMA transfer in blocking mode. + This API returns HAL_ERROR when there is no ongoing transfer or timeout is reached when disabling the DMA + channel. (This API should not be called from an interrupt service routine) + + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority() + + (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() + + (+) Use HAL_DMA_RegisterCallback() function to register user callbacks from the following list : + (++) XferCpltCallback : transfer complete callback. + (++) XferHalfCpltCallback : half transfer complete callback. + (++) XferErrorCallback : transfer error callback. + (++) XferAbortCallback : transfer abort complete callback. + (++) XferSuspendCallback : transfer suspend complete callback. + + (+) Use HAL_DMA_Start_IT() to start the DMA transfer after the enable of DMA interrupts and the configuration + of source address,destination address and the size of data to be transferred. + + (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() interrupt subroutine to handle any DMA interrupt. + + (+) Use HAL_DMA_Abort_IT() function to abort any on-going DMA transfer in non-blocking mode. + This API will suspend immediately the DMA channel execution. When the transfer is effectively suspended, + an interrupt is generated and HAL_DMA_IRQHandler() will reset the channel and execute the callback + XferAbortCallback. (This API could be called from an interrupt service routine) + + + *** State and errors *** + ======================== + [..] + (+) Use HAL_DMA_GetState() function to get the DMA state. + (+) Use HAL_DMA_GetError() function to get the DMA error code. + + + *** Security and privilege attributes *** + ========================================= + [..] + (+) Use HAL_DMA_ConfigChannelAttributes() function to configure DMA channel security and privilege attributes. + (++) Security : at channel level, at source level and at destination level. + (++) Privilege : at channel level. + (+) Use HAL_DMA_GetConfigChannelAttributes() function to get the DMA channel attributes. + (+) Use HAL_DMA_LockChannelAttributes() function to lock the DMA channel security and privilege attributes + configuration. This API can be called once after each system boot. + If called again, HAL_DMA_ConfigChannelAttributes() API has no effect. + Unlock is done either by a system boot or a by an RCC reset. + (+) Use HAL_DMA_GetLockChannelAttributes() function to get the attributes lock status. + + + *** DMA HAL driver macros list *** + ================================== + [..] + Below the list of most used macros in DMA HAL driver. + + (+) __HAL_DMA_ENABLE : Enable the specified DMA Channel. + (+) __HAL_DMA_DISABLE : Disable the specified DMA Channel. + (+) __HAL_DMA_GET_FLAG : Get the DMA Channel pending flags. + (+) __HAL_DMA_CLEAR_FLAG : Clear the DMA Channel pending flags. + (+) __HAL_DMA_ENABLE_IT : Enable the specified DMA Channel interrupts. + (+) __HAL_DMA_DISABLE_IT : Disable the specified DMA Channel interrupts. + (+) __HAL_DMA_GET_IT_SOURCE : Check whether the specified DMA Channel interrupt has occurred or not. + + [..] + (@) You can refer to the header file of the DMA HAL driver for more useful macros. + + @endverbatim + ********************************************************************************************************************** + */ + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32wbaxx_hal.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @defgroup DMA DMA + * @brief DMA HAL module driver + * @{ + */ + +#ifdef HAL_DMA_MODULE_ENABLED + +/* Private typedef ---------------------------------------------------------------------------------------------------*/ +/* Private constants -------------------------------------------------------------------------------------------------*/ +/* Private macro -----------------------------------------------------------------------------------------------------*/ +/* Private variables -------------------------------------------------------------------------------------------------*/ +/* Private function prototypes ---------------------------------------------------------------------------------------*/ +static void DMA_SetConfig(DMA_HandleTypeDef const *const hdma, + uint32_t SrcAddress, + uint32_t DstAddress, + uint32_t SrcDataSize); +static void DMA_Init(DMA_HandleTypeDef const *const hdma); + +/* Exported functions ------------------------------------------------------------------------------------------------*/ + +/** @addtogroup DMA_Exported_Functions DMA Exported Functions + * @{ + */ + +/** @addtogroup DMA_Exported_Functions_Group1 + * +@verbatim + ====================================================================================================================== + ##### Initialization and de-initialization functions ##### + ====================================================================================================================== + [..] + This section provides functions allowing to initialize and de-initialize the DMA channel in normal mode. + + [..] + (+) The HAL_DMA_Init() function follows the DMA channel configuration procedures as described in reference manual. + (+) The HAL_DMA_DeInit() function allows to de-initialize the DMA channel. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the DMA channel in normal mode according to the specified parameters in the DMA_InitTypeDef and + * create the associated handle. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *const hdma) +{ + /* Get tick number */ + uint32_t tickstart = HAL_GetTick(); + + /* Check the DMA peripheral handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); + if (hdma->Init.Direction != DMA_MEMORY_TO_MEMORY) + { + assert_param(IS_DMA_REQUEST(hdma->Init.Request)); + } + assert_param(IS_DMA_BLOCK_HW_REQUEST(hdma->Init.BlkHWRequest)); + assert_param(IS_DMA_SOURCE_INC(hdma->Init.SrcInc)); + assert_param(IS_DMA_DESTINATION_INC(hdma->Init.DestInc)); + assert_param(IS_DMA_SOURCE_DATA_WIDTH(hdma->Init.SrcDataWidth)); + assert_param(IS_DMA_DESTINATION_DATA_WIDTH(hdma->Init.DestDataWidth)); + assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); + assert_param(IS_DMA_TCEM_EVENT_MODE(hdma->Init.TransferEventMode)); + assert_param(IS_DMA_MODE(hdma->Init.Mode)); + /* Check DMA channel instance */ + if (IS_GPDMA_INSTANCE(hdma->Instance) != 0U) + { + assert_param(IS_DMA_BURST_LENGTH(hdma->Init.SrcBurstLength)); + assert_param(IS_DMA_BURST_LENGTH(hdma->Init.DestBurstLength)); + assert_param(IS_DMA_TRANSFER_ALLOCATED_PORT(hdma->Init.TransferAllocatedPort)); + } + + /* Allocate lock resource */ + __HAL_UNLOCK(hdma); + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Disable the DMA channel */ + __HAL_DMA_DISABLE(hdma); + + /* Check if the DMA channel is effectively disabled */ + while ((hdma->Instance->CCR & DMA_CCR_EN) != 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT) + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Initialize the DMA channel registers */ + DMA_Init(hdma); + + /* Update DMA channel operation mode */ + hdma->Mode = hdma->Init.Mode; + + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitialize the DMA channel when it is configured in normal mode. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *const hdma) +{ +#if defined (DMA_PRIVCFGR_PRIV0) + DMA_TypeDef *p_dma_instance; +#endif /* DMA_PRIVCFGR_PRIV0 */ + uint32_t tickstart = HAL_GetTick(); + + /* Check the DMA peripheral handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); +#if defined (DMA_PRIVCFGR_PRIV0) + /* Get DMA instance */ + p_dma_instance = GET_DMA_INSTANCE(hdma); +#endif /* DMA_PRIVCFGR_PRIV0 */ + /* Disable the selected DMA Channel */ + __HAL_DMA_DISABLE(hdma); + + /* Check if the DMA channel is effectively disabled */ + while ((hdma->Instance->CCR & DMA_CCR_EN) != 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT) + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Reset DMA Channel registers */ + hdma->Instance->CLBAR = 0U; + hdma->Instance->CCR = 0U; + hdma->Instance->CTR1 = 0U; + hdma->Instance->CTR2 = 0U; + hdma->Instance->CBR1 = 0U; + hdma->Instance->CSAR = 0U; + hdma->Instance->CDAR = 0U; + hdma->Instance->CLLR = 0U; +#if defined (DMA_PRIVCFGR_PRIV0) + /* Clear privilege attribute */ + CLEAR_BIT(p_dma_instance->PRIVCFGR, (1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU))); +#endif /* DMA_PRIVCFGR_PRIV0 */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + /* Clear secure attribute */ + CLEAR_BIT(p_dma_instance->SECCFGR, (1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU))); +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + /* Clear all flags */ + __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC | DMA_FLAG_HT | DMA_FLAG_DTE | DMA_FLAG_ULE | DMA_FLAG_USE | DMA_FLAG_SUSP | + DMA_FLAG_TO)); + + /* Clean all callbacks */ + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + hdma->XferSuspendCallback = NULL; + + /* Clean DMA queue */ + hdma->LinkedListQueue = NULL; + + /* Clean DMA parent */ + if (hdma->Parent != NULL) + { + hdma->Parent = NULL; + } + + /* Update DMA channel operation mode */ + hdma->Mode = DMA_NORMAL; + + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return HAL_OK; +} +/** + * @} + */ + +/** @addtogroup DMA_Exported_Functions_Group2 + * +@verbatim + ====================================================================================================================== + ##### IO operation functions ##### + ====================================================================================================================== + [..] + This section provides functions allowing to : + (+) Configure the source, destination address and data size and Start DMA transfer in normal mode + (+) Abort DMA transfer + (+) Poll for transfer complete + (+) Handle DMA interrupt request + (+) Register and Unregister DMA callbacks + + [..] + (+) The HAL_DMA_Start() function allows to start the DMA channel transfer in normal mode (Blocking mode). + (+) The HAL_DMA_Start_IT() function allows to start the DMA channel transfer in normal mode (Non-blocking mode). + (+) The HAL_DMA_Abort() function allows to abort any on-going transfer (Blocking mode). + (+) The HAL_DMA_Abort_IT() function allows to abort any on-going transfer (Non-blocking mode). + (+) The HAL_DMA_PollForTransfer() function allows to poll on half transfer and transfer complete (Blocking mode). + This API cannot be used for circular transfers. + (+) The HAL_DMA_IRQHandler() function allows to handle any DMA channel interrupt (Non-blocking mode). + (+) The HAL_DMA_RegisterCallback() and HAL_DMA_UnRegisterCallback() functions allow respectively to register and + unregister user customized callbacks. + User callbacks are called under HAL_DMA_IRQHandler(). + +@endverbatim + * @{ + */ + +/** + * @brief Start the DMA channel transfer in normal mode (Blocking mode). + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for + * the specified DMA Channel. + * @param SrcAddress : The source data address. + * @param DstAddress : The destination data address. + * @param SrcDataSize : The length of data to be transferred from source to destination in bytes. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *const hdma, + uint32_t SrcAddress, + uint32_t DstAddress, + uint32_t SrcDataSize) +{ + /* Check the DMA peripheral handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_BLOCK_SIZE(SrcDataSize)); + + /* Process locked */ + __HAL_LOCK(hdma); + + /* Check DMA channel state */ + if (hdma->State == HAL_DMA_STATE_READY) + { + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Configure the source address, destination address, the data size and clear flags */ + DMA_SetConfig(hdma, SrcAddress, DstAddress, SrcDataSize); + + /* Enable DMA channel */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Starts the DMA channel transfer in normal mode with interrupts enabled (Non-blocking mode). + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @param SrcAddress : The source data address. + * @param DstAddress : The destination data address. + * @param SrcDataSize : The length of data to be transferred from source to destination in bytes. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *const hdma, + uint32_t SrcAddress, + uint32_t DstAddress, + uint32_t SrcDataSize) +{ + /* Check the DMA peripheral handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_BLOCK_SIZE(SrcDataSize)); + + /* Process locked */ + __HAL_LOCK(hdma); + + /* Check DMA channel state */ + if (hdma->State == HAL_DMA_STATE_READY) + { + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Configure the source address, destination address, the data size and clear flags */ + DMA_SetConfig(hdma, SrcAddress, DstAddress, SrcDataSize); + + /* Enable common interrupts: Transfer Complete and Transfer Errors ITs */ + __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_DTE | DMA_IT_ULE | DMA_IT_USE | DMA_IT_TO)); + + /* Check half transfer complete callback */ + if (hdma->XferHalfCpltCallback != NULL) + { + /* If Half Transfer complete callback is set, enable the corresponding IT */ + __HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT); + } + + /* Check Half suspend callback */ + if (hdma->XferSuspendCallback != NULL) + { + /* If Transfer suspend callback is set, enable the corresponding IT */ + __HAL_DMA_ENABLE_IT(hdma, DMA_IT_SUSP); + } + + /* Enable DMA channel */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Abort any on-going DMA channel transfer (Blocking mode). + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @note After suspending a DMA channel, a wait until the DMA channel is effectively stopped is added. If a channel + * is suspended while a data transfer is on-going, the current data will be transferred and the channel will be + * effectively suspended only after the transfer of any on-going data is finished. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *const hdma) +{ + /* Get tick number */ + uint32_t tickstart = HAL_GetTick(); + + /* Check the DMA peripheral handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check DMA channel state */ + if (hdma->State != HAL_DMA_STATE_BUSY) + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + else + { + /* Suspend the channel */ + hdma->Instance->CCR |= DMA_CCR_SUSP; + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_SUSPEND; + + /* Check if the DMA Channel is suspended */ + while ((hdma->Instance->CSR & DMA_CSR_SUSPF) == 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT) + { + /* Update the DMA channel error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT; + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_ERROR; + + /* Check DMA channel transfer mode */ + if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + /* Update the linked-list queue state */ + hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + } + + /* Reset the channel */ + hdma->Instance->CCR |= DMA_CCR_RESET; + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_ABORT; + + /* Clear all status flags */ + __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC | DMA_FLAG_HT | DMA_FLAG_DTE | DMA_FLAG_ULE | DMA_FLAG_USE | DMA_FLAG_SUSP | + DMA_FLAG_TO)); + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Check DMA channel transfer mode */ + if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + /* Update the linked-list queue state */ + hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY; + + /* Clear remaining data size to ensure loading linked-list from memory next start */ + hdma->Instance->CBR1 = 0U; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + } + + return HAL_OK; +} + +/** + * @brief Abort any on-going DMA channel transfer in interrupt mode (Non-blocking mode). + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *const hdma) +{ + /* Check the DMA peripheral handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check DMA channel state */ + if (hdma->State != HAL_DMA_STATE_BUSY) + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + + return HAL_ERROR; + } + else + { + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_ABORT; + + /* Suspend the channel and activate suspend interrupt */ + hdma->Instance->CCR |= (DMA_CCR_SUSP | DMA_CCR_SUSPIE); + } + + return HAL_OK; +} + +/** + * @brief Polling for transfer status (Blocking mode). + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @param CompleteLevel : Specifies the DMA level complete. + * @param Timeout : Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *const hdma, + HAL_DMA_LevelCompleteTypeDef CompleteLevel, + uint32_t Timeout) +{ + /* Get tick number */ + uint32_t tickstart = HAL_GetTick(); + uint32_t level_flag; + uint32_t tmp_csr; + + /* Check the DMA peripheral handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_LEVEL_COMPLETE(CompleteLevel)); + + /* Check DMA channel state */ + if (hdma->State != HAL_DMA_STATE_BUSY) + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + + /* Polling mode is not supported in circular mode */ + if ((hdma->Mode & DMA_LINKEDLIST_CIRCULAR) == DMA_LINKEDLIST_CIRCULAR) + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; + + return HAL_ERROR; + } + + /* Get the level transfer complete flag */ + level_flag = ((CompleteLevel == HAL_DMA_FULL_TRANSFER) ? DMA_FLAG_IDLE : DMA_FLAG_HT); + + /* Get DMA channel status */ + tmp_csr = hdma->Instance->CSR; + + while ((tmp_csr & level_flag) == 0U) + { + /* Check for the timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* Update the DMA channel error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT; + + /* + If timeout, abort the current transfer. + Note that the Abort function will + - Clear all transfer flags. + - Unlock. + - Set the State. + */ + (void)HAL_DMA_Abort(hdma); + + return HAL_ERROR; + } + } + + /* Get a newer CSR register value */ + tmp_csr = hdma->Instance->CSR; + } + + /* Check trigger overrun flag */ + if ((tmp_csr & DMA_FLAG_TO) != 0U) + { + /* Update the DMA channel error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_TO; + + /* Clear the error flag */ + __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_TO); + } + + /* Check error flags */ + if ((tmp_csr & (DMA_FLAG_DTE | DMA_FLAG_ULE | DMA_FLAG_USE)) != 0U) + { + /* Check the data transfer error flag */ + if ((tmp_csr & DMA_FLAG_DTE) != 0U) + { + /* Update the DMA channel error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_DTE; + + /* Clear the error flag */ + __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_DTE); + } + + /* Check the update link error flag */ + if ((tmp_csr & DMA_FLAG_ULE) != 0U) + { + /* Update the DMA channel error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_ULE; + + /* Clear the error flag */ + __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_ULE); + } + + /* Check the user setting error flag */ + if ((tmp_csr & DMA_FLAG_USE) != 0U) + { + /* Update the DMA channel error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_USE; + + /* Clear the error flag */ + __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_USE); + } + + /* Reset the channel */ + hdma->Instance->CCR |= DMA_CCR_RESET; + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Check DMA channel transfer mode */ + if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + /* Update the linked-list queue state */ + hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + + /* Clear the transfer level flag */ + if (CompleteLevel == HAL_DMA_HALF_TRANSFER) + { + /* Clear the Half Transfer flag */ + __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_HT); + } + else if (CompleteLevel == HAL_DMA_FULL_TRANSFER) + { + /* Clear the transfer flags */ + __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC | DMA_FLAG_HT)); + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Check DMA channel transfer mode */ + if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + /* Update the linked-list queue state */ + hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY; + } + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Handle DMA interrupt request (Non-blocking mode). + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval None. + */ +void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma) +{ + const DMA_TypeDef *p_dma_instance = GET_DMA_INSTANCE(hdma); + uint32_t global_it_flag = 1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU); + uint32_t global_active_flag_ns = IS_DMA_GLOBAL_ACTIVE_FLAG_NS(p_dma_instance, global_it_flag); +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + uint32_t global_active_flag_s = IS_DMA_GLOBAL_ACTIVE_FLAG_S(p_dma_instance, global_it_flag); +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + /* Global Interrupt Flag management *********************************************************************************/ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + if ((global_active_flag_s == 0U) && (global_active_flag_ns == 0U)) +#else + if (global_active_flag_ns == 0U) +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + { + return; /* the global interrupt flag for the current channel is down , nothing to do */ + } + + /* Data Transfer Error Interrupt management *************************************************************************/ + if ((__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_DTE) != 0U)) + { + /* Check if interrupt source is enabled */ + if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DTE) != 0U) + { + /* Clear the transfer error flag */ + __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_DTE); + + /* Update the DMA channel error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_DTE; + } + } + + /* Update Linked-list Error Interrupt management ********************************************************************/ + if ((__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_ULE) != 0U)) + { + /* Check if interrupt source is enabled */ + if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_ULE) != 0U) + { + /* Clear the update linked-list error flag */ + __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_ULE); + + /* Update the DMA channel error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_ULE; + } + } + + /* User Setting Error Interrupt management **************************************************************************/ + if ((__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_USE) != 0U)) + { + /* Check if interrupt source is enabled */ + if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_USE) != 0U) + { + /* Clear the user setting error flag */ + __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_USE); + + /* Update the DMA channel error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_USE; + } + } + + /* Trigger Overrun Interrupt management *****************************************************************************/ + if ((__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_TO) != 0U)) + { + /* Check if interrupt source is enabled */ + if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TO) != 0U) + { + /* Clear the trigger overrun flag */ + __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_TO); + + /* Update the DMA channel error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_TO; + } + } + + /* Half Transfer Complete Interrupt management **********************************************************************/ + if ((__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_HT) != 0U)) + { + /* Check if interrupt source is enabled */ + if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != 0U) + { + /* Clear the half transfer flag */ + __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_HT); + + /* Check half transfer complete callback */ + if (hdma->XferHalfCpltCallback != NULL) + { + /* Half transfer callback */ + hdma->XferHalfCpltCallback(hdma); + } + } + } + + /* Suspend Transfer Interrupt management ****************************************************************************/ + if ((__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_SUSP) != 0U)) + { + /* Check if interrupt source is enabled */ + if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_SUSP) != 0U) + { + /* Clear the block transfer complete flag */ + __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_SUSP); + + /* Check DMA channel state */ + if (hdma->State == HAL_DMA_STATE_ABORT) + { + /* Disable the suspend transfer interrupt */ + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_SUSP); + + /* Reset the channel internal state and reset the FIFO */ + hdma->Instance->CCR |= DMA_CCR_RESET; + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Check DMA channel transfer mode */ + if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + /* Update the linked-list queue state */ + hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY; + + /* Clear remaining data size to ensure loading linked-list from memory next start */ + hdma->Instance->CBR1 = 0U; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Check transfer abort callback */ + if (hdma->XferAbortCallback != NULL) + { + /* Transfer abort callback */ + hdma->XferAbortCallback(hdma); + } + + return; + } + else + { + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_SUSPEND; + + /* Check transfer suspend callback */ + if (hdma->XferSuspendCallback != NULL) + { + /* Transfer suspend callback */ + hdma->XferSuspendCallback(hdma); + } + } + } + } + + /* Transfer Complete Interrupt management ***************************************************************************/ + if ((__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_TC) != 0U)) + { + /* Check if interrupt source is enabled */ + if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != 0U) + { + /* Check DMA channel transfer mode */ + if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + /* If linked-list transfer */ + if (hdma->Instance->CLLR == 0U) + { + if (hdma->Instance->CBR1 == 0U) + { + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Update the linked-list queue state */ + hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY; + } + } + } + else + { + /* If normal transfer */ + if (hdma->Instance->CBR1 == 0U) + { + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_READY; + } + } + + /* Clear TC and HT transfer flags */ + __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC | DMA_FLAG_HT)); + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Check transfer complete callback */ + if (hdma->XferCpltCallback != NULL) + { + /* Channel Transfer Complete callback */ + hdma->XferCpltCallback(hdma); + } + } + } + + /* Manage error case ************************************************************************************************/ + if (hdma->ErrorCode != HAL_DMA_ERROR_NONE) + { + /* Reset the channel internal state and reset the FIFO */ + hdma->Instance->CCR |= DMA_CCR_RESET; + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Check DMA channel transfer mode */ + if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + /* Update the linked-list queue state */ + hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + /* Check transfer error callback */ + if (hdma->XferErrorCallback != NULL) + { + /* Transfer error callback */ + hdma->XferErrorCallback(hdma); + } + } +} + +/** + * @brief Register callback according to specified ID. + * @note The HAL_DMA_RegisterCallback() may be called before HAL_DMA_Init() in HAL_DMA_STATE_RESET + * to register callbacks for HAL_DMA_MSPINIT_CB_ID and HAL_DMA_MSPDEINIT_CB_ID. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @param CallbackID : User Callback identifier which could be a value of HAL_DMA_CallbackIDTypeDef enumeration. + * @param pCallback : Pointer to private callback function. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *const hdma, + HAL_DMA_CallbackIDTypeDef CallbackID, + void (*const pCallback)(DMA_HandleTypeDef *const _hdma)) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the DMA peripheral handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check DMA channel state */ + if (hdma->State == HAL_DMA_STATE_READY) + { + /* Check callback ID */ + switch (CallbackID) + { + case HAL_DMA_XFER_CPLT_CB_ID: + { + /* Register transfer complete callback */ + hdma->XferCpltCallback = pCallback; + break; + } + + case HAL_DMA_XFER_HALFCPLT_CB_ID: + { + /* Register half transfer callback */ + hdma->XferHalfCpltCallback = pCallback; + break; + } + + case HAL_DMA_XFER_ERROR_CB_ID: + { + /* Register transfer error callback */ + hdma->XferErrorCallback = pCallback; + break; + } + + case HAL_DMA_XFER_ABORT_CB_ID: + { + /* Register abort callback */ + hdma->XferAbortCallback = pCallback; + break; + } + + case HAL_DMA_XFER_SUSPEND_CB_ID: + { + /* Register suspend callback */ + hdma->XferSuspendCallback = pCallback; + break; + } + + default: + { + /* Update error status */ + status = HAL_ERROR; + break; + } + } + } + else + { + /* Update error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister callback according to specified ID. + * @note The HAL_DMA_UnRegisterCallback() may be called before HAL_DMA_Init() in HAL_DMA_STATE_RESET + * to un-register callbacks for HAL_DMA_MSPINIT_CB_ID and HAL_DMA_MSPDEINIT_CB_ID. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @param CallbackID : User Callback identifier which could be a value of HAL_DMA_CallbackIDTypeDef enum. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *const hdma, + HAL_DMA_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the DMA peripheral handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check DMA channel state */ + if (hdma->State == HAL_DMA_STATE_READY) + { + /* Check callback ID */ + switch (CallbackID) + { + case HAL_DMA_XFER_CPLT_CB_ID: + { + /* UnRegister transfer complete callback */ + hdma->XferCpltCallback = NULL; + break; + } + + case HAL_DMA_XFER_HALFCPLT_CB_ID: + { + /* UnRegister half transfer callback */ + hdma->XferHalfCpltCallback = NULL; + break; + } + + case HAL_DMA_XFER_ERROR_CB_ID: + { + /* UnRegister transfer error callback */ + hdma->XferErrorCallback = NULL; + break; + } + + case HAL_DMA_XFER_ABORT_CB_ID: + { + /* UnRegister abort callback */ + hdma->XferAbortCallback = NULL; + break; + } + + case HAL_DMA_XFER_SUSPEND_CB_ID: + { + /* UnRegister suspend callback */ + hdma->XferSuspendCallback = NULL; + break; + } + + case HAL_DMA_XFER_ALL_CB_ID: + { + /* UnRegister all available callbacks */ + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + hdma->XferSuspendCallback = NULL; + break; + } + + default: + { + /* Update error status */ + status = HAL_ERROR; + break; + } + } + } + else + { + /* Update error status */ + status = HAL_ERROR; + } + + return status; +} +/** + * @} + */ + +/** @addtogroup DMA_Exported_Functions_Group3 + * +@verbatim + ====================================================================================================================== + ##### State and Errors functions ##### + ====================================================================================================================== + [..] + This section provides functions allowing to : + (+) Check the DMA state + (+) Get error code + + [..] + (+) The HAL_DMA_GetState() function allows to get the DMA channel state. + (+) The HAL_DMA_DeInit() function allows to get the DMA channel error code. + +@endverbatim + * @{ + */ + +/** + * @brief Returns the DMA channel state. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval DMA state. + */ +HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef const *const hdma) +{ + /* Return the DMA channel state */ + return hdma->State; +} + +/** + * @brief Return the DMA channel error code. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval DMA Error Code. + */ +uint32_t HAL_DMA_GetError(DMA_HandleTypeDef const *const hdma) +{ + /* Return the DMA channel error code */ + return hdma->ErrorCode; +} +/** + * @} + */ + +/** @addtogroup DMA_Exported_Functions_Group4 + * +@verbatim + ====================================================================================================================== + ##### DMA Attributes functions ##### + ====================================================================================================================== + [..] + This section provides functions allowing to : + (+) Configure DMA channel secure and privilege attributes. + (+) Get DMA channel secure and privilege attributes. + (+) Lock DMA channel secure and privilege attributes configuration. + (+) Check whether DMA channel secure and privilege attributes configuration is locked or not. + + [..] + (+) The HAL_DMA_ConfigChannelAttributes() function allows to configure DMA channel security and privilege + attributes. + (+) The HAL_DMA_GetConfigChannelAttributes() function allows to get DMA channel security and privilege attributes + configuration. + (+) The HAL_DMA_LockChannelAttributes() function allows to lock the DMA channel security and privilege attributes. + (+) The HAL_DMA_GetLockChannelAttributes() function allows to get the DMA channel security and privilege + attributes lock status. + +@endverbatim + * @{ + */ +#if defined (DMA_PRIVCFGR_PRIV0) +/** + * @brief Configure the DMA channel security and privilege attribute(s). + * @note These attributes cannot be modified when the corresponding lock state is enabled. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for + * the specified DMA Channel. + * @param ChannelAttributes : Specifies the DMA channel secure/privilege attributes. + * This parameter can be a one or a combination of @ref DMA_Channel_Attributes. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_DMA_ConfigChannelAttributes(DMA_HandleTypeDef *const hdma, uint32_t ChannelAttributes) +{ + DMA_TypeDef *p_dma_instance; + uint32_t channel_idx; + + /* Check the DMA peripheral handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_ATTRIBUTES(ChannelAttributes)); + + /* Get DMA instance */ + p_dma_instance = GET_DMA_INSTANCE(hdma); + + /* Get channel index */ + channel_idx = 1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU); + + /* Check DMA channel privilege attribute management */ + if ((ChannelAttributes & DMA_CHANNEL_ATTR_PRIV_MASK) == DMA_CHANNEL_ATTR_PRIV_MASK) + { + /* Configure DMA channel privilege attribute */ + if ((ChannelAttributes & DMA_CHANNEL_PRIV) == DMA_CHANNEL_PRIV) + { + p_dma_instance->PRIVCFGR |= channel_idx; + } + else + { + p_dma_instance->PRIVCFGR &= (~channel_idx); + } + } + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + /* Check DMA channel security attribute management */ + if ((ChannelAttributes & DMA_CHANNEL_ATTR_SEC_MASK) == DMA_CHANNEL_ATTR_SEC_MASK) + { + /* Configure DMA channel security attribute */ + if ((ChannelAttributes & DMA_CHANNEL_SEC) == DMA_CHANNEL_SEC) + { + p_dma_instance->SECCFGR |= channel_idx; + } + else + { + p_dma_instance->SECCFGR &= (~channel_idx); + } + } + + /* Channel source security attribute management */ + if ((ChannelAttributes & DMA_CHANNEL_ATTR_SEC_SRC_MASK) == DMA_CHANNEL_ATTR_SEC_SRC_MASK) + { + /* Configure DMA channel source security attribute */ + if ((ChannelAttributes & DMA_CHANNEL_SRC_SEC) == DMA_CHANNEL_SRC_SEC) + { + hdma->Instance->CTR1 |= DMA_CTR1_SSEC; + } + else + { + hdma->Instance->CTR1 &= (~DMA_CTR1_SSEC); + } + } + + /* Channel destination security attribute management */ + if ((ChannelAttributes & DMA_CHANNEL_ATTR_SEC_DEST_MASK) == DMA_CHANNEL_ATTR_SEC_DEST_MASK) + { + /* Configure DMA channel destination security attribute */ + if ((ChannelAttributes & DMA_CHANNEL_DEST_SEC) == DMA_CHANNEL_DEST_SEC) + { + hdma->Instance->CTR1 |= DMA_CTR1_DSEC; + } + else + { + hdma->Instance->CTR1 &= (~DMA_CTR1_DSEC); + } + } +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + return HAL_OK; +} + +/** + * @brief Get the DMA channel security and privilege attributes. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information + * for the specified DMA Channel. + * @param pChannelAttributes : Pointer to the returned attributes. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_DMA_GetConfigChannelAttributes(DMA_HandleTypeDef const *const hdma, + uint32_t *const pChannelAttributes) +{ + const DMA_TypeDef *p_dma_instance; + uint32_t attributes; + uint32_t channel_idx; + + /* Check the DMA peripheral handle and channel attributes parameters */ + if ((hdma == NULL) || (pChannelAttributes == NULL)) + { + return HAL_ERROR; + } + + /* Get DMA instance */ + p_dma_instance = GET_DMA_INSTANCE(hdma); + + /* Get channel index */ + channel_idx = 1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU); + + /* Get DMA channel privilege attribute */ + attributes = ((p_dma_instance->PRIVCFGR & channel_idx) == 0U) ? DMA_CHANNEL_NPRIV : DMA_CHANNEL_PRIV; + +#if defined (DMA_SECCFGR_SEC0) + /* Get DMA channel security attribute */ + attributes |= ((p_dma_instance->SECCFGR & channel_idx) == 0U) ? DMA_CHANNEL_NSEC : DMA_CHANNEL_SEC; + + /* Get DMA channel source security attribute */ + attributes |= ((hdma->Instance->CTR1 & DMA_CTR1_SSEC) == 0U) ? DMA_CHANNEL_SRC_NSEC : DMA_CHANNEL_SRC_SEC; + + /* Get DMA channel destination security attribute */ + attributes |= ((hdma->Instance->CTR1 & DMA_CTR1_DSEC) == 0U) ? DMA_CHANNEL_DEST_NSEC : DMA_CHANNEL_DEST_SEC; +#endif /* DMA_SECCFGR_SEC0 */ + + /* return value */ + *pChannelAttributes = attributes; + + return HAL_OK; +} +#endif /* DMA_PRIVCFGR_PRIV0 */ +#if defined (DMA_RCFGLOCKR_LOCK0) +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Lock the DMA channel security and privilege attribute(s). + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_DMA_LockChannelAttributes(DMA_HandleTypeDef const *const hdma) +{ + DMA_TypeDef *p_dma_instance; + uint32_t channel_idx; + + /* Check the DMA peripheral handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Get DMA instance */ + p_dma_instance = GET_DMA_INSTANCE(hdma); + + /* Get channel index */ + channel_idx = 1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU); + + /* Lock the DMA channel privilege and security attributes */ + p_dma_instance->RCFGLOCKR |= channel_idx; + + return HAL_OK; +} +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/** + * @brief Get the security and privilege attribute lock state of a DMA channel. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @param pLockState : Pointer to lock state (returned value can be DMA_CHANNEL_ATTRIBUTE_UNLOCKED or + * DMA_CHANNEL_ATTRIBUTE_LOCKED). + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *const hdma, uint32_t *const pLockState) +{ + DMA_TypeDef *p_dma_instance; + uint32_t channel_idx; + + /* Check the DMA peripheral handle and lock state parameters */ + if ((hdma == NULL) || (pLockState == NULL)) + { + return HAL_ERROR; + } + + /* Get DMA instance */ + p_dma_instance = GET_DMA_INSTANCE(hdma); + + /* Get channel index */ + channel_idx = 1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU); + + /* Get channel lock attribute state */ + *pLockState = ((p_dma_instance->RCFGLOCKR & channel_idx) == 0U) ? DMA_CHANNEL_ATTRIBUTE_UNLOCKED : \ + DMA_CHANNEL_ATTRIBUTE_LOCKED; + + return HAL_OK; +} +#endif /* DMA_RCFGLOCKR_LOCK0 */ +/** + * @} + */ + +/** + * @} + */ + + +/* Private functions -------------------------------------------------------------------------------------------------*/ +/** @defgroup DMA_Private_Functions DMA Private Functions + * @brief DMA Private Functions + * @{ + */ + +/** + * @brief Set the DMA channel normal transfer parameters. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @param SrcAddress : The source data address. + * @param DstAddress : The destination data address. + * @param SrcDataSize : The length of data to be transferred from source to destination in bytes. + * @retval None. + */ +static void DMA_SetConfig(DMA_HandleTypeDef const *const hdma, + uint32_t SrcAddress, + uint32_t DstAddress, + uint32_t SrcDataSize) +{ + /* Configure the DMA channel data size */ + MODIFY_REG(hdma->Instance->CBR1, DMA_CBR1_BNDT, (SrcDataSize & DMA_CBR1_BNDT)); + + /* Clear all interrupt flags */ + __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_TC | DMA_FLAG_HT | DMA_FLAG_DTE | DMA_FLAG_ULE | DMA_FLAG_USE | DMA_FLAG_SUSP | + DMA_FLAG_TO); + + /* Configure DMA channel source address */ + hdma->Instance->CSAR = SrcAddress; + + /* Configure DMA channel destination address */ + hdma->Instance->CDAR = DstAddress; +} + +/** + * @brief Initialize the DMA channel in normal mode according to the specified parameters in the DMA_InitTypeDef. + * @param hdma : pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval None. + */ +static void DMA_Init(DMA_HandleTypeDef const *const hdma) +{ + uint32_t tmpreg; + + /* Prepare DMA Channel Control Register (CCR) value *****************************************************************/ + tmpreg = hdma->Init.Priority; + + /* Write DMA Channel Control Register (CCR) */ + MODIFY_REG(hdma->Instance->CCR, DMA_CCR_PRIO | DMA_CCR_LAP | DMA_CCR_LSM, tmpreg); + + /* Prepare DMA Channel Transfer Register (CTR1) value ***************************************************************/ + tmpreg = hdma->Init.DestInc | hdma->Init.DestDataWidth | hdma->Init.SrcInc | hdma->Init.SrcDataWidth; + + /* Add parameters specific to GPDMA */ + if (IS_GPDMA_INSTANCE(hdma->Instance) != 0U) + { + tmpreg |= (hdma->Init.TransferAllocatedPort | + (((hdma->Init.DestBurstLength - 1U) << DMA_CTR1_DBL_1_Pos) & DMA_CTR1_DBL_1) | + (((hdma->Init.SrcBurstLength - 1U) << DMA_CTR1_SBL_1_Pos) & DMA_CTR1_SBL_1)); + } + + /* Write DMA Channel Transfer Register 1 (CTR1) */ +#if defined (DMA_CTR1_SSEC) + MODIFY_REG(hdma->Instance->CTR1, ~(DMA_CTR1_SSEC | DMA_CTR1_DSEC), tmpreg); +#else + WRITE_REG(hdma->Instance->CTR1, tmpreg); +#endif /* DMA_CTR1_SSEC */ + + /* Prepare DMA Channel Transfer Register 2 (CTR2) value *************************************************************/ + tmpreg = hdma->Init.BlkHWRequest | (hdma->Init.Request & DMA_CTR2_REQSEL) | hdma->Init.TransferEventMode; + + /* Memory to Peripheral Transfer */ + if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) + { + if (IS_GPDMA_INSTANCE(hdma->Instance) != 0U) + { + tmpreg |= DMA_CTR2_DREQ; + } + } + /* Memory to Memory Transfer */ + else if ((hdma->Init.Direction) == DMA_MEMORY_TO_MEMORY) + { + tmpreg |= DMA_CTR2_SWREQ; + } + else + { + /* Nothing to do */ + } + + /* Write DMA Channel Transfer Register 2 (CTR2) */ + MODIFY_REG(hdma->Instance->CTR2, (DMA_CTR2_TCEM | DMA_CTR2_TRIGPOL | DMA_CTR2_TRIGSEL | DMA_CTR2_TRIGM | + DMA_CTR2_BREQ | DMA_CTR2_DREQ | DMA_CTR2_SWREQ | DMA_CTR2_REQSEL), tmpreg); + + + /* Write DMA Channel Block Register 1 (CBR1) ************************************************************************/ + WRITE_REG(hdma->Instance->CBR1, 0U); + + /* Write DMA Channel linked-list address register (CLLR) ************************************************************/ + WRITE_REG(hdma->Instance->CLLR, 0U); +} +/** + * @} + */ + +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_dma_ex.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_dma_ex.c new file mode 100644 index 0000000000..4a02639bb7 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_dma_ex.c @@ -0,0 +1,4324 @@ +/** + ********************************************************************************************************************** + * @file stm32wbaxx_hal_dma_ex.c + * @author MCD Application Team + * @brief DMA Extension HAL module driver + * This file provides firmware functions to manage the following functionalities of the DMA extension + * peripheral: + * + Linked-List Initialization and De-Initialization Functions + * + Linked-List I/O Operation Functions + * + Linked-List Management Functions + * + Data Handling, Repeated Block and Trigger Configuration Functions + * + Suspend and Resume Operation Functions + * + FIFO Status Function + * + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + @verbatim + ====================================================================================================================== + ##### How to use this driver ##### + ====================================================================================================================== + [..] + Alternatively to the normal programming mode, a DMA channel can be programmed by a list of transfers, known as + linked-list (list of Node items). Each node is defined by its data structure. + Each node specifies a standalone DMA channel. + When enabled, the DMA channel fetch the first linked-list node from SRAM (known as head node). When executed, the + next linked list node will be fetched and executed. This operation is repeated until the end of the whole + linked-list queue. Optionally, the linked-list can be linear where the last linked-list queue node is not linked + to another queue node or circular where the last linked-list node is linked to any linked-list queue node. + + (+) Linear linked-list: + The DMA channel fetch and execute all DMA linked-list queue from first node (head node) to last node + (tail node) ones. When the last node is completed, the DMA channel remains in idle state and another + transfer can be lunched. + + (+) Circular linked-list: + The DMA channel fetch and execute all DMA linked-list queue from first node (head node) to last node (tail + node). When last node is executed, the DMA channel fetches the first circular node another time and repeat + the same sequence in an infinite loop (Circular transfer). To stop the DMA channel, an abort operation is + required. This linked-list mode replaces the legacy circular transfers. + + [..] + In order to reduce linked-list queue executing time and power consumption, the DMA channel supports executing the + dynamic linked-list format. In fact, the DMA supports the execution of 2 types of linked-list formats : static and + dynamic. + + (+) Static linked-list: + The static linked-list format refers to the full linked-list node where all DMA channel parameters are + fetched and executed independently of the redundancy of information. + + (+) Dynamic linked-list: + The dynamic linked-list format refer to the customized linked-list node where only DMA channel necessary + parameters are fetched and executed (Example: data size = 20 on previous node, and data size = 20 on the + current node => No need to update it). + + For linked-list transfers, the DMA channel can execute the linked-list queue node by node. This feature is named + link step mode. When activated, enabling the DMA channel first time allows to fetch the head node from memory + then it stops. Then, another DMA channel enable is needed to execute the node. After that, keeping enabling the + DMA channel is needed to execute each node until the end of linked-list queue. When the linked-list queue is + circular, enabling the DMA channel in an infinite loop is required to keep the DMA channel running. This feature + is useful for debug purpose or asynchronously executing queue nodes. + + [..] + Each DMA channel transfer (normal or linked-list), is highly configurable according to DMA channel instance + integrated in devices. These configuration can be : + + (+) Repeated block configuration : + If the feature is supported, the DMA channel can performs a repeated block transfers. Named also 2 + dimension addressing transfers, this feature can transfer n iteration of programmed block transfer (Block + transfer is the legacy data size). Additional to the repeat count of a block, DMA channel addresses can + jump after at burst and block level. The jump length is a programmable parameter defined by DMA user. + (++) Jump at burst level : + The DMA channel keep an empty area, between each 2 consecutive bursts transmitted. + (++) Jump at block level : + The DMA channel keep an empty area, between each 2 consecutive blocks transmitted. + + (+) Trigger : + The DMA channel transfers can be conditioned by hardware signals edges (rising or falling) named hardware + triggers. Trigger condition can be applied at : + (++) Single/Burst level : + Each single/burst data transmission is conditioned by a signal trigger hit. + (++) Block level : + Each block data transmission is conditioned by a signal trigger hit. + (++) Node level : + Each node execution is conditioned by a signal trigger hit. + The DMA channel can report a trigger overrun when detects more than 2 trigger signal edges before + executing the current transfer. + + (+) Data handling : + The data handling feature is a FIFO capability that can be : + (++) Padding pattern : + Padding selected pattern (zero padding or sign extension) when the source data width is smaller + than the destination data width at single level. + (++) Truncation : + Truncate section from the source data single when the source data width is bigger than the + destination data width. + (++) Pack/Unpack : + Pack a set of data when source data width is smaller than the destination data width. + Unpack a set of data when source data width is bigger than the destination data width. + (++) Exchange : + Exchange data at byte and half-word on the destination and at byte level on the source. + + [..] + Each DMA channel transfer (normal or linked-list) when it is active, can be suspended and resumed at run time + application. When trying to suspend an ongoing transfer, the DMA channel isn't suspended instantly but complete + the current ongoing single/burst then it stops. + When the DMA channel is suspended, the current transfer can be resumed instantly. + + [..] + The DMA channel that supports FIFO, can report in real time the number of beats remains on destination (Output) + FIFO level. + + *** Linked-List Initialization and De-Initialization operation *** + ================================================================== + [..] + Differently from normal transfers, DMA channel initialization and de-initialization need less parameters as the + remaining transfer parameters are defined by linked-list nodes. + + (+) Use HAL_DMAEx_List_Init() to initialize a DMA channel in linked-list mode according to programmed fields. + When called, the DMA channel will be ready to execute linked-list queues. + + (+) Use HAL_DMAEx_List_DeInit() to de-initialize a DMA channel in linked-list mode. + When called, the DMA channel will be in reset. It is mandatory to reinitialize it for next transfer. + + *** Linked-List I/O Operation *** + ================================= + [..] + (+) Use HAL_DMAEx_List_Start() to start a DMA transfer in linked-list mode after the configuration of + linked-list queue base address and offset in polling mode (Blocking mode). + + (+) Use HAL_DMAEx_List_Start_IT() to start a DMA transfer in linked-list mode after the configuration of + linked-list queue base address and offset in interrupt mode (Non-blocking mode). + + *** Linked-List Management *** + ============================== + [..] + The linked-list management is a software processing independently of DMA channel hardware. It allows to reset, + build, create, insert, remove, replace, circularize, convert both nodes and queue in order to perform DMA + channel transfers in linked-list mode. + Linked-list APIs and types are adapted to reduce memory footprint. + + *** Linked-list nodes building *** + [..] + At node level, the operations that can be done are building a new linked-list node or get a linked-list node + information from a built node. The linked-list nodes have two forms according to 2 dimensions addressing + capability. The linear addressing nodes contains the information of all DMA channel features except the 2 + dimension addressing features and the 2 dimensions addressing nodes contain the information of all available + features. + + (+) Use HAL_DMAEx_List_BuildNode() to build the DMA linked-list node according to the specified parameters. + Build operation allow to convert the specified parameter in values known by the DMA channel and place them + in memory. + Placing DMA linked-list in SRAM must be done in accordance to product specification to ensure that the + link access port can access to the specified SRAM. + (++) The DMA linked-list node parameter address should be 32bit aligned and should not exceed the 64 KByte + addressable space. + + (+) Use HAL_DMAEx_List_GetNodeConfig() to get the specified configuration parameter on building node. + This API can be used when need to change few parameter to build new node. + + *** Inserting nodes to linked-list queue *** + [..] + In order to build a sequence of DMA transaction with different configuration, we need to insert built node at + linked-list queue (node present an elementary DMA transaction) in linked-list queue on any position to have the + full flexibility of ordering nodes or extend the sequence of queue transactions. + + (+) Use HAL_DMAEx_List_InsertNode() to insert new built node in any queue position of linked-list queue + according to selecting previous node. When calling this API with previous node parameter is NULL, the + inserted node will be placed at the head of the linked-list queue. + (++) This API must be used after HAL_DMAEx_List_BuildNode() otherwise an error will be returned. + (++) This API must be called for static queues format. + (++) This API shall be avoided when adding new node at the head or the tail of queue (overhead of + footprint and performance : use HAL_DMAEx_List_InsertNode_Head() or HAL_DMAEx_List_InsertNode_Tail() + instead). + + (+) Use HAL_DMAEx_List_InsertNode_Head() to insert new built node at the head of linked-list queue. The head + node will not be overwritten but will be the second queue node. + (++) This API must be used after HAL_DMAEx_List_BuildNode() otherwise an error will be returned. + (++) This API must be called for static queues format. + + (+) Use HAL_DMAEx_List_InsertNode_Tail() to insert new built node at the tail of linked-list queue. The tail + node will not be overwritten but will be the penultimate queue node. + (++) This API must be used after HAL_DMAEx_List_BuildNode() otherwise an error will be returned. + (++) This API must be called for static queues format. + + *** Removing nodes from linked-list queue *** + [..] + There is some cases when removing a node from linked-list queue is needed (need to remove an elementary DMA + transaction). Removing node allows to unlink a node from DMA linked-list queue (NOT DELETED), so the removed node + can be reused for another queue or to be added to the same queue without need to rebuild it in next step. + + (+) Use HAL_DMAEx_List_RemoveNode() to remove any yet built and inserted node from linked-list queue according + to selected node. + (++) This API must be called for static queues format. + (++) This API shall be avoided when removing the head or the tail of linked-list queue (overhead of + footprint and performance : use HAL_DMAEx_List_RemoveNode_Head() or HAL_DMAEx_List_RemoveNode_Tail() + instead). + + (+) Use HAL_DMAEx_List_RemoveNode_Head() to remove the head node from linked-list queue. + (++) This API must be called for static queues format. + + (+) Use HAL_DMAEx_List_RemoveNode_Tail() to remove the tail node from linked-list queue. + (++) This API must be called for static queues format. + + *** Replacing nodes on linked-list queue *** + [..] + There is some cases when replacing a node from linked-list queue is needed (need to replace an elementary DMA + transfer, by another one that have not the same configuration). Replacing node allows to unlink the node to be + replaced from DMA linked-list queue (NOT DELETED) and link instead a new node. So the replaced node can be reused + for another queue or to be added to the same queue without need to rebuild it in next step and the new node cannot + be reused except when remove it or replaced in next step. + + (+) Use HAL_DMAEx_List_ReplaceNode() to replace any yet built and inserted node on linked-list queue according + to selected node. + (++) This API must be called for static queues format. + (++) This API shall be avoided when replacing the head or the tail linked-list queue (overhead of + footprint and performance : use HAL_DMAEx_List_ReplaceNode_Head() or + HAL_DMAEx_List_ReplaceNode_Tail() instead). + + (+) Use HAL_DMAEx_List_ReplaceNode_Head() to replace the head node of linked-list queue. + (++) This API must be called for static queues format. + + (+) Use HAL_DMAEx_List_ReplaceNode_Tail() to replace the tail node from linked-list queue. + (++) This API must be called for static queues format. + + *** Reset linked-list queue *** + [..] + After finishing using a linked-list queue, it can be reset and cleared and it's content nodes will be + unlinked (NOT DELETED) and reused on another queue. + + (+) Use HAL_DMAEx_List_ResetQ() to reset a linked-list queue and unlink all it's content nodes. + (++) This API must be called for ready state queues. + (++) This API must be called for static queues format. + + *** Inserting linked-list queue *** + [..] + To ensure the flexibility of building linked-list queue by their targeted functionalities (Example: 3 nodes for + action 1 and 5 nodes for action 2), it is possible to build a queue for action 1 that contains action 1 nodes and + a queue for action 2 that contains action 2 nodes then concatenating the 2 queues. So, there are some cases where + the management of linked-list at queue granularity is needed. + + (+) Use HAL_DMAEx_List_InsertQ() to insert source linked-list queue to a destination linked-list queue + according to selecting previous node. + (++) This API must be called for static queues format. + (++) This API shall be avoided when inserting source linked-list queue at the head or the tail of + destination queue (overhead of footprint and performance : use HAL_DMAEx_List_InsertQ_Head() or + HAL_DMAEx_List_InsertQ_Tail() instead). + + (+) Use HAL_DMAEx_List_InsertQ_Head() to insert a source linked-list queue at the head of linked-list + destination queue. + (++) This API must be called for static queues format. + + (+) Use HAL_DMAEx_List_InsertQ_Tail() to insert a source linked-list queue at the tail of linked-list + destination queue. + (++) This API must be called for static queues format. + + *** Circularizing linked-list queue *** + [..] + In order to perform tasks in infinite loop with DMA channel, it is possible to circularize the linked-list queues. + Circularizing queue allows to link last linked-list queue node to any previous node of the same queue (This node + is named first circular queue). When the first circular node is the head node, all linked-list queue nodes will be + executed in infinite loop. When the first circular node is not the head nodes, all precedent nodes are executed + once and all remaining nodes are executed in an infinite loop. + + (+) Use HAL_DMAEx_List_SetCircularModeConfig() to circularize the linked-list queue according to first + circular node selected. + (++) This API must be called for static queues format. + (++) This API shall be avoided when first circular node is the head linked-list queue node (overhead of + footprint and performance : use HAL_DMAEx_List_SetCircularMode() instead). + + (+) Use HAL_DMAEx_List_SetCircularMode() to circularize the linked-list queue with linking last queue node + with first queue node. + (++) This API must be called for static queues format. + + (+) Use HAL_DMAEx_List_ClearCircularMode() to clear any linked-list queue circular configuration. + (++) This API must be called for static queues format. + + + *** Converting linked-list queue *** + [..] + To have the best DMA channel linked-list queue execution, it is recommended to convert yet build linked-list queue + to dynamic format (Static is the default format). When linked-list queue becomes dynamic, all queue nodes are + optimized and only changed parameters will be updated between nodes. So, the DMA will fetch only changes + parameters instead of the whole node. + + (+) Use HAL_DMAEx_List_ConvertQToDynamic() to convert a linked-list queue to dynamic format. + (++) This API must be called for ready state queues. + (++) This API must be called for static queues format. + (++) This API must be called as the last API before starting the DMA channel in linked-list mode. + + (+) Use HAL_DMAEx_List_ConvertQToStatic() to convert a linked-list queue to static format. + (++) This API must be called for ready state queues. + (++) This API must be called for dynamic queues format. + (++) This API must be called as the first API after the full execution of linked-list queue when the + execution mode is linear (not circular) if it is dynamic and a linked-list queue management is + needed. + (++) This API must be called as the first API after the aborting the execution of the current linked-list + queue when the execution mode is linear (not circular) if it is dynamic and a linked-list queue + management is needed. + + [..] + When converting a circular queue to dynamic format and when the first circular node is the last queue node, it is + recommended to duplicate the last circular node in order to ensure the full optimization when calling + HAL_DMAEx_List_ConvertQToDynamic() API. In this case, updated information are only addresses which allow to reduce + 4 words of update for linear nodes per node execution and 6 words update for 2 dimensions addressing nodes per + node execution. + + + *** Linking linked-list queue to DMA channel *** + [..] + In order to have the possibility of the creation of an infinity queues (limited by available memory size), the + building of linked-list queue is fully independent from DMA channels. It is possible to build all needed queues if + their size is less then available memory at startup time, then linking each time when needed a linked-list queue + to an idle DMA channel. + + (+) Use HAL_DMAEx_List_LinkQ() to link a ready linked-list queue to ready DMA channel. + (++) This API supports the two format of linked-list (Static and dynamic). + (++) This API must be called for ready state queues and DMA channels. + + (+) Use HAL_DMAEx_List_ConvertQToStatic() to unlink a ready linked-list queue to ready DMA channel. + (++) This API supports the two format of linked-list (Static and dynamic). + (++) This API must be called for ready state queues and DMA channels. + + *** User sequence *** + [..] + To use cleanly the DMA linked-list library, ensure to apply the following call sequences : + + (+) Linear transfer : + Linked-list queue building + (++) HAL_DMAEx_List_BuildNode() + (++) HAL_DMAEx_List_InsertNode_Tail() + . + . + . + (++) HAL_DMAEx_List_BuildNode() + (++) HAL_DMAEx_List_InsertNode_Tail() + (++) HAL_DMAEx_List_ConvertQToDynamic() + Linked-list queue execution + (++) HAL_DMAEx_List_Init() + (++) HAL_DMAEx_List_LinkQ() + (++) HAL_DMAEx_List_Start() / HAL_DMAEx_List_Start_IT() + (++) HAL_DMAEx_List_UnLinkQ() + (++) HAL_DMAEx_List_DeInit() + + (+) Circular transfer : + Linked-list queue building + (++) HAL_DMAEx_List_BuildNode() + (++) HAL_DMAEx_List_InsertNode_Tail() + . + . + . + (++) HAL_DMAEx_List_BuildNode() + (++) HAL_DMAEx_List_InsertNode_Tail() + (++) HAL_DMAEx_List_SetCircularModeConfig() / HAL_DMAEx_List_SetCircularMode() + (++) HAL_DMAEx_List_ConvertQToDynamic() + Linked-list queue execution + (++) HAL_DMAEx_List_Init() + (++) HAL_DMAEx_List_LinkQ() + (++) HAL_DMAEx_List_Start() / HAL_DMAEx_List_Start_IT() + (++) HAL_DMA_Abort() / HAL_DMA_Abort_IT() + (++) HAL_DMAEx_List_UnLinkQ() + (++) HAL_DMAEx_List_DeInit() + + + *** Data Handling *** + ===================== + [..] + In order to avoid some CPU data processing in several cases, the DMA channel provides some features related to + FIFO capabilities titled data handling. + (++) Padding pattern + Padding selected pattern (zero padding or sign extension) when the source data width is smaller + than the destination data width at single level. + Zero padding (Source : 0xABAB ------> Destination : 0xABAB0000) + Sign bit extension (Source : 0x0ABA ------> Destination : 0x00000ABA) + (Source : 0xFABA ------> Destination : 0xFFFFFABA) + (++) Truncation : + Truncate section from the source data single when the source data width is bigger than the + destination data width. + Left truncation (Source : 0xABABCDCD ------> Destination : 0xCDCD) + Right truncation (Source : 0xABABCDCD ------> Destination : 0xABAB) + (++) Pack/Unpack : + Pack a set of data when source data width is smaller than the destination data width. + Unpack a set of data when source data width is bigger than the destination data width. + Pack (Source : 0xAB, 0xCD ------> Destination : 0xABCD) + UnPack (Source : 0xABCD ------> Destination : 0xAB, 0xCD) + (++) Exchange : + Exchange data at byte and half-word on the destination and at byte level on the source. + Considering source and destination are both word type. Exchange operation can be as follows. + In examples below, one exchange setting is enabled at a time. + Source byte exchange only (Source : 0xAB12CD34 ------> Destination : 0xABCD1234) + Destination byte exchange only (Source : 0xAB12CD34 ------> Destination : 0x12AB34CD) + Destination half-word exchange only (Source : 0xAB12CD34 ------> Destination : 0xCD34AB12) + + (+) Use HAL_DMAEx_ConfigDataHandling() to configure data handling features. Previous elementary explained + can be combined according to application needs. + (++) This API is complementary of normal transfers. + (++) This API must not be called for linked-list transfers as data handling information are configured at + node level. + + *** User sequence *** + [..] + To configure cleanly the DMA channel data handling, ensure to apply the following call sequence : + + (+) Linear transfer : + (++) HAL_DMA_Init() + (++) HAL_DMAEx_ConfigDataHandling() + (++) HAL_DMA_Start() + + *** Trigger Configuration *** + ============================= + [..] + When application needs that DMA transfers are conditioned by internal or external events, the trigger feature can + do that. Trigger signals are a set of device signal that are linked to DMA trigger inputs that allows to start the + DMA transfers. + To setup a trigger transfers, three DMA channel parameters are needed: + + (+) Trigger mode + This parameter specifies the trig level. + (++) Block level + (++) Repeated block level + (++) Node level + (++) Single / Burst level + + (+) Trigger polarity + This parameter specifies the DMA trigger sensitivity (Rising or falling). + + (+) Trigger selection + This parameter specifies the DMA trigger hardware signal. + + (+) Use HAL_DMAEx_ConfigTrigger() to configure trigger feature. + (++) This API is complementary to normal transfers APIs. + (++) This API must not be called for linked-list transfers as trigger information are configured at + node level. + + *** User sequence *** + [..] + To configure cleanly the DMA channel trigger, ensure to apply the following call sequence : + (+) Linear transfer : + (++) HAL_DMA_Init() + (++) HAL_DMAEx_ConfigTrigger() + (++) HAL_DMA_Start() + + *** Suspend and resume operation *** + ==================================== + [..] + There are several cases when needs to suspend a DMA current transfer (Example: liberate bandwidth for more + priority DMA channel transfer). Suspending DMA channel (same as abort) is available in polling (blocking mode) and + interrupt (non-blocking mode) modes. When suspended, a DMA channel can be instantly resumed. + + (+) Use HAL_DMAEx_Suspend() to suspend an ongoing DMA channel transfer in polling mode (Blocking mode). + + (+) Use HAL_DMAEx_Suspend_IT() to suspend an ongoing DMA channel transfer in interrupt mode (Non-blocking + mode). + + (+) Use HAL_DMAEx_Resume() to resume a suspended DMA channel transfer execution. + + *** FIFO status *** + =================== + [..] + In several cases, the information of FIFO level is useful to inform at application level how to process remaining + data. When not empty, the DMA channel FIFO cannot be flashed only by reset. + + (+) Use HAL_DMAEx_GetFifoLevel() to get the DMA channel FIFO level (available beats in FIFO). + + @endverbatim + ********************************************************************************************************************** + */ + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +#include "stm32wbaxx_hal.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @defgroup DMAEx DMAEx + * @brief DMA Extended HAL module driver + * @{ + */ + +#ifdef HAL_DMA_MODULE_ENABLED + +/* Private types -----------------------------------------------------------------------------------------------------*/ +/* Private variables -------------------------------------------------------------------------------------------------*/ +/* Private Constants -------------------------------------------------------------------------------------------------*/ +/* Private macros ----------------------------------------------------------------------------------------------------*/ +/* Private function prototypes ---------------------------------------------------------------------------------------*/ +static void DMA_List_Init(DMA_HandleTypeDef const *const hdma); +static void DMA_List_BuildNode(DMA_NodeConfTypeDef const *const pNodeConfig, + DMA_NodeTypeDef *const pNode); +static void DMA_List_GetNodeConfig(DMA_NodeConfTypeDef *const pNodeConfig, + DMA_NodeTypeDef const *const pNode); +static uint32_t DMA_List_CheckNodesBaseAddresses(DMA_NodeTypeDef const *const pNode1, + DMA_NodeTypeDef const *const pNode2, + DMA_NodeTypeDef const *const pNode3); +static uint32_t DMA_List_CheckNodesTypes(DMA_NodeTypeDef const *const pNode1, + DMA_NodeTypeDef const *const pNode2, + DMA_NodeTypeDef const *const pNode3); +static void DMA_List_GetCLLRNodeInfo(DMA_NodeTypeDef const *const pNode, + uint32_t *const cllr_mask, + uint32_t *const cllr_offset); +static uint32_t DMA_List_FindNode(DMA_QListTypeDef const *const pQList, + DMA_NodeTypeDef const *const pNode, + DMA_NodeInQInfoTypeDef *const NodeInfo); +static void DMA_List_ResetQueueNodes(DMA_QListTypeDef const *const pQList, + DMA_NodeInQInfoTypeDef const *const NodeInfo); +static void DMA_List_FillNode(DMA_NodeTypeDef const *const pSrcNode, + DMA_NodeTypeDef *const pDestNode); +static void DMA_List_ConvertNodeToDynamic(uint32_t ContextNodeAddr, + uint32_t CurrentNodeAddr, + uint32_t RegisterNumber); +static void DMA_List_ConvertNodeToStatic(uint32_t ContextNodeAddr, + uint32_t CurrentNodeAddr, + uint32_t RegisterNumber); +static void DMA_List_UpdateDynamicQueueNodesCLLR(DMA_QListTypeDef const *const pQList, + uint32_t LastNode_IsCircular); +static void DMA_List_UpdateStaticQueueNodesCLLR(DMA_QListTypeDef const *const pQList, + uint32_t operation); +static void DMA_List_FormatNode(DMA_NodeTypeDef *const pNode, + uint32_t RegisterIdx, + uint32_t RegisterNumber, + uint32_t Format); +static void DMA_List_ClearUnusedFields(DMA_NodeTypeDef *const pNode, + uint32_t FirstUnusedField); +static void DMA_List_CleanQueue(DMA_QListTypeDef *const pQList); + +/* Exported functions ------------------------------------------------------------------------------------------------*/ + +/** @addtogroup DMAEx_Exported_Functions + * @{ + */ + +/** @addtogroup DMAEx_Exported_Functions_Group1 + * +@verbatim + ====================================================================================================================== + ##### Linked-List Initialization and De-Initialization Functions ##### + ====================================================================================================================== + [..] + This section provides functions allowing to initialize and de-initialize the DMA channel in linked-list mode. + [..] + (+) The HAL_DMAEx_List_Init() function follows the DMA channel linked-list mode configuration procedures as + described in reference manual. + (+) The HAL_DMAEx_List_DeInit() function allows to de-initialize the DMA channel in linked-list mode. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the DMA channel in linked-list mode according to the specified parameters in the + * DMA_InitLinkedListTypeDef and create the associated handle. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_Init(DMA_HandleTypeDef *const hdma) +{ + /* Get tick number */ + uint32_t tickstart = HAL_GetTick(); + + /* Check the DMA channel handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + assert_param(IS_DMA_PRIORITY(hdma->InitLinkedList.Priority)); + assert_param(IS_DMA_LINK_STEP_MODE(hdma->InitLinkedList.LinkStepMode)); + assert_param(IS_DMA_TCEM_LINKEDLIST_EVENT_MODE(hdma->InitLinkedList.TransferEventMode)); + assert_param(IS_DMA_LINKEDLIST_MODE(hdma->InitLinkedList.LinkedListMode)); + /* Check DMA channel instance */ + if (IS_GPDMA_INSTANCE(hdma->Instance) != 0U) + { + assert_param(IS_DMA_LINK_ALLOCATED_PORT(hdma->InitLinkedList.LinkAllocatedPort)); + } + + /* Allocate lock resource */ + __HAL_UNLOCK(hdma); + + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Disable the DMA channel */ + __HAL_DMA_DISABLE(hdma); + + /* Check if the DMA channel is effectively disabled */ + while ((hdma->Instance->CCR & DMA_CCR_EN) != 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT) + { + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Initialize the DMA channel registers */ + DMA_List_Init(hdma); + + /* Update DMA channel operation mode */ + hdma->Mode = hdma->InitLinkedList.LinkedListMode; + + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitialize the DMA channel when it is configured in linked-list mode. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_DeInit(DMA_HandleTypeDef *const hdma) +{ +#if defined (DMA_PRIVCFGR_PRIV0) + /* Get DMA instance */ + DMA_TypeDef *p_dma_instance; +#endif /* DMA_PRIVCFGR_PRIV0 */ + + /* Get tick number */ + uint32_t tickstart = HAL_GetTick(); + + /* Check the DMA peripheral handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + +#if defined (DMA_PRIVCFGR_PRIV0) + /* Get DMA instance */ + p_dma_instance = GET_DMA_INSTANCE(hdma); +#endif /* DMA_PRIVCFGR_PRIV0 */ + + /* Disable the selected DMA Channel */ + __HAL_DMA_DISABLE(hdma); + + /* Check if the DMA channel is effectively disabled */ + while ((hdma->Instance->CCR & DMA_CCR_EN) != 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT) + { + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Reset DMA Channel registers */ + hdma->Instance->CCR = 0U; + hdma->Instance->CLBAR = 0U; + hdma->Instance->CTR1 = 0U; + hdma->Instance->CTR2 = 0U; + hdma->Instance->CBR1 = 0U; + hdma->Instance->CSAR = 0U; + hdma->Instance->CDAR = 0U; + hdma->Instance->CLLR = 0U; + +#if defined (DMA_PRIVCFGR_PRIV0) + /* Clear privilege attribute */ + CLEAR_BIT(p_dma_instance->PRIVCFGR, (1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU))); +#endif /* DMA_PRIVCFGR_PRIV0 */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + /* Clear secure attribute */ + CLEAR_BIT(p_dma_instance->SECCFGR, (1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU))); +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + /* Clear all flags */ + __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC | DMA_FLAG_HT | DMA_FLAG_DTE | DMA_FLAG_ULE | DMA_FLAG_USE | DMA_FLAG_SUSP | + DMA_FLAG_TO)); + + /* Clean all callbacks */ + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + hdma->XferSuspendCallback = NULL; + + /* Check the linked-list queue */ + if (hdma->LinkedListQueue != NULL) + { + /* Update the queue state and error code */ + hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY; + hdma->LinkedListQueue->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Clean DMA queue */ + hdma->LinkedListQueue = NULL; + } + + /* Clean DMA parent */ + if (hdma->Parent != NULL) + { + hdma->Parent = NULL; + } + + /* Update DMA channel operation mode */ + hdma->Mode = DMA_NORMAL; + + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return HAL_OK; +} +/** + * @} + */ + +/** @addtogroup DMAEx_Exported_Functions_Group2 + * +@verbatim + ====================================================================================================================== + ##### Linked-List IO Operation Functions ##### + ====================================================================================================================== + [..] + This section provides functions allowing to : + (+) Configure to start DMA transfer in linked-list mode. + + [..] + (+) The HAL_DMAEx_List_Start() function allows to start the DMA channel transfer in linked-list mode (Blocking + mode). + (+) The HAL_DMAEx_List_Start_IT() function allows to start the DMA channel transfer in linked-list mode + (Non-blocking mode). + (++) It is mandatory to register a linked-list queue to be executed by a DMA channel before starting + transfer otherwise a HAL_ERROR will be returned. + +@endverbatim + * @{ + */ + +/** + * @brief Start the DMA channel transfer in linked-list mode (Blocking mode). + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_Start(DMA_HandleTypeDef *const hdma) +{ + HAL_DMA_StateTypeDef dma_state; + uint32_t ccr_value; + uint32_t cllr_mask; + + /* Check the DMA peripheral handle and the linked-list queue parameters */ + if ((hdma == NULL) || (hdma->LinkedListQueue == NULL)) + { + return HAL_ERROR; + } + + /* Check DMA channel state */ + dma_state = hdma->State; + ccr_value = hdma->Instance->CCR & DMA_CCR_LSM; + if ((dma_state == HAL_DMA_STATE_READY) || ((dma_state == HAL_DMA_STATE_BUSY) && (ccr_value != 0U))) + { + /* Check DMA channel state is ready */ + if (hdma->State == HAL_DMA_STATE_READY) + { + /* Process locked */ + __HAL_LOCK(hdma); + + /* Update the DMA channel and the queue states */ + hdma->State = HAL_DMA_STATE_BUSY; + hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the DMA channel and the queue error codes */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + hdma->LinkedListQueue->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(hdma->LinkedListQueue->Head, &cllr_mask, NULL); + + /* Update DMA registers for linked-list transfer */ + hdma->Instance->CLBAR = ((uint32_t)hdma->LinkedListQueue->Head & DMA_CLBAR_LBA); + hdma->Instance->CLLR = ((uint32_t)hdma->LinkedListQueue->Head & DMA_CLLR_LA) | cllr_mask; + } + + /* Enable DMA channel */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Starts the DMA channel transfer in linked-list mode with interrupts enabled (Non-blocking mode). + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_Start_IT(DMA_HandleTypeDef *const hdma) +{ + HAL_DMA_StateTypeDef dma_state; + uint32_t ccr_value; + uint32_t cllr_mask; + + /* Check the DMA peripheral handle and the linked-list queue parameters */ + if ((hdma == NULL) || (hdma->LinkedListQueue == NULL)) + { + return HAL_ERROR; + } + + /* Check DMA channel state */ + dma_state = hdma->State; + ccr_value = hdma->Instance->CCR & DMA_CCR_LSM; + if ((dma_state == HAL_DMA_STATE_READY) || ((dma_state == HAL_DMA_STATE_BUSY) && (ccr_value != 0U))) + { + /* Check DMA channel state is ready */ + if (hdma->State == HAL_DMA_STATE_READY) + { + /* Process locked */ + __HAL_LOCK(hdma); + + /* Update the DMA channel and the queue states */ + hdma->State = HAL_DMA_STATE_BUSY; + hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the DMA channel and the queue error codes */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + hdma->LinkedListQueue->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Enable common interrupts: Transfer Complete and Transfer Errors ITs */ + __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_DTE | DMA_IT_ULE | DMA_IT_USE | DMA_IT_TO)); + + /* Check half transfer complete callback */ + if (hdma->XferHalfCpltCallback != NULL) + { + /* If half transfer complete callback is set, enable the corresponding IT */ + __HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT); + } + + /* Check suspend callback */ + if (hdma->XferSuspendCallback != NULL) + { + /* If transfer suspend callback is set, enable the corresponding IT */ + __HAL_DMA_ENABLE_IT(hdma, DMA_IT_SUSP); + } + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(hdma->LinkedListQueue->Head, &cllr_mask, NULL); + + /* Update DMA registers for linked-list transfer */ + hdma->Instance->CLBAR = ((uint32_t)hdma->LinkedListQueue->Head & DMA_CLBAR_LBA); + hdma->Instance->CLLR = ((uint32_t)hdma->LinkedListQueue->Head & DMA_CLLR_LA) | cllr_mask; + } + + /* Enable DMA channel */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Change the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + + return HAL_OK; +} +/** + * @} + */ + +/** @addtogroup DMAEx_Exported_Functions_Group3 + * +@verbatim + ====================================================================================================================== + ##### Linked-List Management Functions ##### + ====================================================================================================================== + [..] + This section provides functions allowing to : + (+) Build linked-list node. + (+) Get linked-list node configuration. + (+) Insert node to linked-list queue in any queue position. + (+) Remove any node from linked-list queue. + (+) Replace any node from linked-list queue. + (+) Reset linked-list queue. + (+) Insert linked-list queue in any queue position. + (+) Set circular mode configuration to linked-list queue. + (+) Clear circular mode configuration from linked-list queue. + (+) Convert static linked-list queue to dynamic format. + (+) Convert dynamic linked-list queue to static format. + (+) Link linked-list queue to DMA channel. + (+) Unlink linked-list queue from DMA channel. + + [..] + (+) The HAL_DMAEx_List_BuildNode() function allows to build linked-list node. + Node type can be : + (++) 2 dimensions addressing node. + (++) Linear addressing node. + + (+) The HAL_DMAEx_List_GetNodeConfig() function allows to get the linked-list node configuration from built node. + + (+) The HAL_DMAEx_List_InsertNode() function allows to insert built linked-list node to static linked-list queue + according to selected position. + + (+) The HAL_DMAEx_List_InsertNode_Head() and HAL_DMAEx_List_InsertNode_Tail() functions allow to insert built + linked-list node to the head (respectively the tail) of static linked-list queue. + + (+) The HAL_DMAEx_List_RemoveNode() function allows to remove selected built linked-list node from static + linked-list queue. + + (+) The HAL_DMAEx_List_RemoveNode_Head() and HAL_DMAEx_List_RemoveNode_Tail() functions allow to remove the head + (respectively the tail) built linked-list node from static linked-list queue. + + (+) The HAL_DMAEx_List_ReplaceNode() function allows to replace selected built linked-list node from static + linked-list queue. + + (+) The HAL_DMAEx_List_ReplaceNode_Head() and HAL_DMAEx_List_ReplaceNode_Tail() functions allow to replace the + head (respectively the tail) built linked-list node of static linked-list queue. + + (+) The HAL_DMAEx_List_ResetQ() function allows to reset static linked-list queue and unlink all built linked-list + nodes. + + (+) The HAL_DMAEx_List_InsertQ() function allows to insert static linked-list source queue to static linked-list + destination queue according to selected position. + + (+) The HAL_DMAEx_List_InsertQ_Head() and HAL_DMAEx_List_InsertQ_Tail() functions allow to insert static + linked-list source queue to the head (respectively the tail) of static linked-list destination queue. + + (+) The HAL_DMAEx_List_SetCircularModeConfig() function allows to link the last static linked-list queue node to + the selected first circular node. + + (+) The HAL_DMAEx_List_SetCircularMode() function allows to link the last static linked-list queue node to the + first static linked-list queue node. + + (+) The HAL_DMAEx_List_ClearCircularMode() function allows to unlink the last static linked-list queue node from + any first circular node position. + + (+) The HAL_DMAEx_List_ConvertQToDynamic() function allows to convert the static linked-list queue to dynamic + format. (Optimized queue execution) + + (+) The HAL_DMAEx_List_ConvertQToStatic() function allows to convert the dynamic linked-list queue to static + format. (Not optimized queue execution) + + (+) The HAL_DMAEx_List_LinkQ() function allows to link the (Dynamic / Static) linked-list queue to DMA channel to + be executed. + + (+) The HAL_DMAEx_List_UnLinkQ() function allows to unlink the (Dynamic / Static) linked-list queue from DMA + channel when execution is completed. + +@endverbatim + * @{ + */ + +/** + * @brief Build a DMA channel node according to the specified parameters in the DMA_NodeConfTypeDef. + * @param pNodeConfig : Pointer to a DMA_NodeConfTypeDef structure that contains the configuration information for the + * specified DMA linked-list Node. + * @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers + * configurations. + * @note The DMA linked-list node parameter address should be 32bit aligned and should not exceed the 64 KByte + * addressable space. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_BuildNode(DMA_NodeConfTypeDef const *const pNodeConfig, + DMA_NodeTypeDef *const pNode) +{ + /* Check the node configuration and physical node parameters */ + if ((pNodeConfig == NULL) || (pNode == NULL)) + { + return HAL_ERROR; + } + + /* Check node type parameter */ + assert_param(IS_DMA_NODE_TYPE(pNodeConfig->NodeType)); + + /* Check DMA channel basic transfer parameters */ + assert_param(IS_DMA_SOURCE_INC(pNodeConfig->Init.SrcInc)); + assert_param(IS_DMA_DESTINATION_INC(pNodeConfig->Init.DestInc)); + assert_param(IS_DMA_SOURCE_DATA_WIDTH(pNodeConfig->Init.SrcDataWidth)); + assert_param(IS_DMA_DESTINATION_DATA_WIDTH(pNodeConfig->Init.DestDataWidth)); + assert_param(IS_DMA_DATA_ALIGNMENT(pNodeConfig->DataHandlingConfig.DataAlignment)); + assert_param(IS_DMA_REQUEST(pNodeConfig->Init.Request)); + assert_param(IS_DMA_DIRECTION(pNodeConfig->Init.Direction)); + assert_param(IS_DMA_TCEM_EVENT_MODE(pNodeConfig->Init.TransferEventMode)); + assert_param(IS_DMA_BLOCK_HW_REQUEST(pNodeConfig->Init.BlkHWRequest)); + assert_param(IS_DMA_MODE(pNodeConfig->Init.Mode)); + + /* Check DMA channel parameters */ + if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_GPDMA) == DMA_CHANNEL_TYPE_GPDMA) + { + assert_param(IS_DMA_BURST_LENGTH(pNodeConfig->Init.SrcBurstLength)); + assert_param(IS_DMA_BURST_LENGTH(pNodeConfig->Init.DestBurstLength)); + assert_param(IS_DMA_DATA_EXCHANGE(pNodeConfig->DataHandlingConfig.DataExchange)); + assert_param(IS_DMA_TRANSFER_ALLOCATED_PORT(pNodeConfig->Init.TransferAllocatedPort)); + } + + /* Check DMA channel trigger parameters */ + assert_param(IS_DMA_TRIGGER_POLARITY(pNodeConfig->TriggerConfig.TriggerPolarity)); + if (pNodeConfig->TriggerConfig.TriggerPolarity != DMA_TRIG_POLARITY_MASKED) + { + assert_param(IS_DMA_TRIGGER_MODE(pNodeConfig->TriggerConfig.TriggerMode)); + assert_param(IS_DMA_TRIGGER_SELECTION(pNodeConfig->TriggerConfig.TriggerSelection)); + } + + /* Check DMA channel security and privilege attributes parameters */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + assert_param(IS_DMA_ATTRIBUTES(pNodeConfig->SrcSecure)); + assert_param(IS_DMA_ATTRIBUTES(pNodeConfig->DestSecure)); +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + /* Build the DMA channel node */ + DMA_List_BuildNode(pNodeConfig, pNode); + + return HAL_OK; +} + +/** + * @brief Get a DMA channel node configuration. + * @param pNodeConfig : Pointer to a DMA_NodeConfTypeDef structure that contains the configuration information for the + * specified DMA linked-list Node. + * @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers + * configurations. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_GetNodeConfig(DMA_NodeConfTypeDef *const pNodeConfig, + DMA_NodeTypeDef const *const pNode) +{ + /* Check the node configuration and physical node parameters */ + if ((pNodeConfig == NULL) || (pNode == NULL)) + { + return HAL_ERROR; + } + + /* Get the DMA channel node configuration */ + DMA_List_GetNodeConfig(pNodeConfig, pNode); + + return HAL_OK; +} + +/** + * @brief Insert new node in any queue position of linked-list queue according to selecting previous node. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @param pPrevNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list previous node registers + * configurations. + * @param pNewNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list new node registers + * configurations. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_InsertNode(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pPrevNode, + DMA_NodeTypeDef *const pNewNode) +{ + uint32_t cllr_mask; + uint32_t cllr_offset; + DMA_NodeInQInfoTypeDef node_info; + + /* Check the queue and the new node parameters */ + if ((pQList == NULL) || (pNewNode == NULL)) + { + return HAL_ERROR; + } + + /* Check queue type */ + if (pQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Check nodes base addresses */ + if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pPrevNode, pNewNode) != 0U) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; + + return HAL_ERROR; + } + + /* Check nodes types compatibility */ + if (DMA_List_CheckNodesTypes(pQList->Head, pPrevNode, pNewNode) != 0U) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pNewNode, &cllr_mask, &cllr_offset); + + /* Empty queue */ + if (pQList->Head == NULL) + { + /* Add only new node to queue */ + if (pPrevNode == NULL) + { + pQList->Head = pNewNode; + pQList->NodeNumber = 1U; + } + /* Add previous node then new node to queue */ + else + { + pQList->Head = pPrevNode; + pPrevNode->LinkRegisters[cllr_offset] = ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; + pQList->NodeNumber = 2U; + } + } + /* Not empty queue */ + else + { + /* Add new node at the head of queue */ + if (pPrevNode == NULL) + { + pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pQList->Head & DMA_CLLR_LA) | cllr_mask; + pQList->Head = pNewNode; + } + /* Add new node according to selected position */ + else + { + /* Find node and get its position in selected queue */ + node_info.cllr_offset = cllr_offset; + if (DMA_List_FindNode(pQList, pPrevNode, &node_info) == 0U) + { + /* Selected node is the last queue node */ + if (node_info.currentnode_pos == pQList->NodeNumber) + { + /* Check if queue is circular */ + if (pQList->FirstCircularNode != NULL) + { + pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pQList->FirstCircularNode & DMA_CLLR_LA) | cllr_mask; + } + + pPrevNode->LinkRegisters[cllr_offset] = ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; + } + /* Selected node is not the last queue node */ + else + { + pNewNode->LinkRegisters[cllr_offset] = pPrevNode->LinkRegisters[cllr_offset]; + pPrevNode->LinkRegisters[cllr_offset] = ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; + } + } + else + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NOTFOUND; + + return HAL_ERROR; + } + } + + /* Increment queue node number */ + pQList->NodeNumber++; + } + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Insert new node at the head of linked-list queue. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @param pNewNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list new node registers + * configurations. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_InsertNode_Head(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pNewNode) +{ + uint32_t cllr_mask; + uint32_t cllr_offset; + + /* Check the queue and the new node parameters */ + if ((pQList == NULL) || (pNewNode == NULL)) + { + return HAL_ERROR; + } + + /* Check queue type */ + if (pQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Check nodes base addresses */ + if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pNewNode, NULL) != 0U) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; + + return HAL_ERROR; + } + + /* Check nodes types compatibility */ + if (DMA_List_CheckNodesTypes(pQList->Head, pNewNode, NULL) != 0U) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Empty queue */ + if (pQList->Head == NULL) + { + pQList->Head = pNewNode; + } + /* Not empty queue */ + else + { + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pNewNode, &cllr_mask, &cllr_offset); + + pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pQList->Head & DMA_CLLR_LA) | cllr_mask; + pQList->Head = pNewNode; + } + + /* Increment queue node number */ + pQList->NodeNumber++; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Insert new node at the tail of linked-list queue. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @param pNewNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list new node registers + * configurations. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_InsertNode_Tail(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pNewNode) +{ + uint32_t cllr_mask; + uint32_t cllr_offset; + DMA_NodeInQInfoTypeDef node_info; + + /* Check the queue and the new node parameters */ + if ((pQList == NULL) || (pNewNode == NULL)) + { + return HAL_ERROR; + } + + /* Check queue type */ + if (pQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Check nodes base addresses */ + if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pNewNode, NULL) != 0U) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; + + return HAL_ERROR; + } + + /* Check nodes types compatibility */ + if (DMA_List_CheckNodesTypes(pQList->Head, pNewNode, NULL) != 0U) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Empty queue */ + if (pQList->Head == NULL) + { + pQList->Head = pNewNode; + } + /* Not empty queue */ + else + { + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pNewNode, &cllr_mask, &cllr_offset); + + /* Find node and get its position in selected queue */ + node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pQList, NULL, &node_info); + + /* Check if queue is circular */ + if (pQList->FirstCircularNode != NULL) + { + pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pQList->FirstCircularNode & DMA_CLLR_LA) | cllr_mask; + } + + ((DMA_NodeTypeDef *)node_info.currentnode_addr)->LinkRegisters[cllr_offset] = + ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; + } + + /* Increment queue node number */ + pQList->NodeNumber++; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_READY; + + /* Prevent MISRA-C2012-Rule-2.2_b */ + UNUSED(node_info); + + return HAL_OK; +} + +/** + * @brief Remove node from any linked-list queue position. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list previous node registers + * configurations. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pNode) +{ + uint32_t previousnode_addr; + uint32_t cllr_offset; + DMA_NodeInQInfoTypeDef node_info; + + /* Check the queue and the node parameters */ + if ((pQList == NULL) || (pNode == NULL)) + { + return HAL_ERROR; + } + + /* Check the queue */ + if (pQList->Head == NULL) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; + + return HAL_ERROR; + } + + /* Check queue type */ + if (pQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pNode, NULL, &cllr_offset); + + /* Find node and get its position in selected queue */ + node_info.cllr_offset = cllr_offset; + if (DMA_List_FindNode(pQList, pNode, &node_info) == 0U) + { + /* Removed node is the head node */ + if (node_info.currentnode_pos == 1U) + { + /* Check if first circular node queue is the first node */ + if (pQList->FirstCircularNode == ((DMA_NodeTypeDef *)node_info.currentnode_addr)) + { + /* Find last queue node */ + (void)DMA_List_FindNode(pQList, NULL, &node_info); + + /* Clear last node link */ + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U; + + /* Clear first circular node */ + pQList->FirstCircularNode = NULL; + } + + /* Update the queue head node */ + pQList->Head = (DMA_NodeTypeDef *)(((uint32_t)pQList->Head & DMA_CLBAR_LBA) + + (pNode->LinkRegisters[cllr_offset] & DMA_CLLR_LA)); + /* Unlink node to be removed */ + pNode->LinkRegisters[cllr_offset] = 0U; + } + /* Removed node is the last node */ + else if (node_info.currentnode_pos == pQList->NodeNumber) + { + /* Clear CLLR for previous node */ + ((DMA_NodeTypeDef *)(node_info.previousnode_addr))->LinkRegisters[cllr_offset] = 0U; + + /* Clear CLLR for last node */ + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U; + + /* Clear first circular node */ + pQList->FirstCircularNode = NULL; + } + /* Removed node is in the middle */ + else + { + /* Store previous node address to be updated later */ + previousnode_addr = node_info.previousnode_addr; + + /* Check if first circular node queue is the current node */ + if (pQList->FirstCircularNode == ((DMA_NodeTypeDef *)node_info.currentnode_addr)) + { + /* Find last queue node */ + (void)DMA_List_FindNode(pQList, NULL, &node_info); + + /* Clear last node link */ + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U; + + /* Clear first circular node */ + pQList->FirstCircularNode = NULL; + } + + /* Link previous node */ + ((DMA_NodeTypeDef *)(previousnode_addr))->LinkRegisters[cllr_offset] = pNode->LinkRegisters[cllr_offset]; + + /* Unlink node to be removed */ + pNode->LinkRegisters[cllr_offset] = 0U; + } + + /* Decrement node number */ + pQList->NodeNumber--; + } + else + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NOTFOUND; + + return HAL_ERROR; + } + + /* Check if queue is empty */ + if (pQList->NodeNumber == 0U) + { + /* Clean empty queue parameter */ + DMA_List_CleanQueue(pQList); + } + else + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_READY; + } + + /* Prevent MISRA-C2012-Rule-2.2_b */ + UNUSED(node_info); + + return HAL_OK; +} + +/** + * @brief Remove the head node from linked-list queue. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode_Head(DMA_QListTypeDef *const pQList) +{ + uint32_t cllr_offset; + uint32_t current_addr; + DMA_NodeInQInfoTypeDef node_info; + + /* Check the queue parameter */ + if (pQList == NULL) + { + return HAL_ERROR; + } + + /* Check the queue */ + if (pQList->Head == NULL) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; + + return HAL_ERROR; + } + + /* Check queue type */ + if (pQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pQList->Head, NULL, &cllr_offset); + + /* Queue contains only one node */ + if (pQList->NodeNumber == 1U) + { + pQList->Head->LinkRegisters[cllr_offset] = 0U; + pQList->FirstCircularNode = 0U; + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + } + /* Queue contains more then one node */ + else + { + /* Check if first circular node queue is the first node */ + if (pQList->FirstCircularNode == pQList->Head) + { + /* Find last queue node */ + node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pQList, NULL, &node_info); + + /* Clear last node link */ + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U; + + /* Clear first circular node */ + pQList->FirstCircularNode = NULL; + } + + current_addr = pQList->Head->LinkRegisters[cllr_offset] & DMA_CLLR_LA; + pQList->Head->LinkRegisters[cllr_offset] = 0U; + pQList->Head = ((DMA_NodeTypeDef *)(current_addr + ((uint32_t)pQList->Head & DMA_CLBAR_LBA))); + } + + /* Decrement node number */ + pQList->NodeNumber--; + + /* Check if queue is empty */ + if (pQList->NodeNumber == 0U) + { + /* Clean empty queue parameter */ + DMA_List_CleanQueue(pQList); + } + else + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_READY; + } + + /* Prevent MISRA-C2012-Rule-2.2_b */ + UNUSED(node_info); + + return HAL_OK; +} + +/** + * @brief Remove the tail node from linked-list queue. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode_Tail(DMA_QListTypeDef *const pQList) +{ + uint32_t cllr_offset; + DMA_NodeInQInfoTypeDef node_info; + + /* Check the queue parameter */ + if (pQList == NULL) + { + return HAL_ERROR; + } + + /* Check the queue */ + if (pQList->Head == NULL) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; + + return HAL_ERROR; + } + + /* Check queue type */ + if (pQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pQList->Head, NULL, &cllr_offset); + + /* Queue contains only one node */ + if (pQList->NodeNumber == 1U) + { + pQList->Head->LinkRegisters[cllr_offset] = 0U; + pQList->FirstCircularNode = 0U; + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + } + /* Queue contains more then one node */ + else + { + /* Find node and get its position in selected queue */ + node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pQList, NULL, &node_info); + + /* Clear CLLR for previous node */ + ((DMA_NodeTypeDef *)(node_info.previousnode_addr))->LinkRegisters[cllr_offset] = 0U; + + /* Clear CLLR for last node */ + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U; + + /* Clear first circular node */ + pQList->FirstCircularNode = NULL; + } + + /* Decrement node number */ + pQList->NodeNumber--; + + /* Check if queue is empty */ + if (pQList->NodeNumber == 0U) + { + /* Clean empty queue parameter */ + DMA_List_CleanQueue(pQList); + } + else + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_READY; + } + + /* Prevent MISRA-C2012-Rule-2.2_b */ + UNUSED(node_info); + + return HAL_OK; +} + +/** + * @brief Replace node in linked-list queue. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @param pOldNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list old node registers + * configurations. + * @param pNewNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list new node registers + * configurations. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pOldNode, + DMA_NodeTypeDef *const pNewNode) +{ + uint32_t cllr_mask; + uint32_t cllr_offset; + DMA_NodeInQInfoTypeDef node_info; + + /* Check the queue and the nodes parameters */ + if ((pQList == NULL) || (pOldNode == NULL) || (pNewNode == NULL)) + { + return HAL_ERROR; + } + + /* Check the queue */ + if (pQList->Head == NULL) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; + + return HAL_ERROR; + } + + /* Check queue type */ + if (pQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Check nodes base addresses */ + if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pOldNode, pNewNode) != 0U) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; + + return HAL_ERROR; + } + + /* Check nodes types compatibility */ + if (DMA_List_CheckNodesTypes(pQList->Head, pOldNode, pNewNode) != 0U) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pNewNode, &cllr_mask, &cllr_offset); + + /* Find node and get its position in selected queue */ + node_info.cllr_offset = cllr_offset; + if (DMA_List_FindNode(pQList, pOldNode, &node_info) == 0U) + { + /* Replaced node is the head node */ + if (node_info.currentnode_pos == 1U) + { + pNewNode->LinkRegisters[cllr_offset] = + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset]; + pQList->Head = pNewNode; + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U; + + /* Check if first circular node queue is the first node */ + if (pQList->FirstCircularNode == ((DMA_NodeTypeDef *)node_info.currentnode_addr)) + { + /* Find last queue node */ + (void)DMA_List_FindNode(pQList, NULL, &node_info); + + /* Clear last node link */ + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = + ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; + + /* Set new node as first circular node */ + pQList->FirstCircularNode = pNewNode; + } + } + /* Replaced node is the last */ + else if (node_info.currentnode_pos == pQList->NodeNumber) + { + ((DMA_NodeTypeDef *)(node_info.previousnode_addr))->LinkRegisters[cllr_offset] = + ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U; + + /* Check if first circular node queue is the last node */ + if (pQList->FirstCircularNode == ((DMA_NodeTypeDef *)(node_info.currentnode_addr))) + { + /* Link first circular node to new node */ + pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; + + /* Set new node as first circular node */ + pQList->FirstCircularNode = pNewNode; + } + /* Check if first circular node queue is not the last node */ + else if (pQList->FirstCircularNode != NULL) + { + /* Link first circular node to new node */ + pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pQList->FirstCircularNode & DMA_CLLR_LA) | cllr_mask; + } + else + { + /* Prevent MISRA-C2012-Rule-15.7 */ + } + } + /* Replaced node is in the middle */ + else + { + ((DMA_NodeTypeDef *)(node_info.previousnode_addr))->LinkRegisters[cllr_offset] = + ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; + pNewNode->LinkRegisters[cllr_offset] = + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset]; + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U; + + /* Check if first circular node queue is the current node */ + if (pQList->FirstCircularNode == ((DMA_NodeTypeDef *)(node_info.currentnode_addr))) + { + /* Find last node and get its position in selected queue */ + (void)DMA_List_FindNode(pQList, NULL, &node_info); + + /* Link last queue node to new node */ + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = + ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; + + /* Set new node as first circular node */ + pQList->FirstCircularNode = pNewNode; + } + } + } + else + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NOTFOUND; + + return HAL_ERROR; + } + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_READY; + + /* Prevent MISRA-C2012-Rule-2.2_b */ + UNUSED(node_info); + + return HAL_OK; +} + +/** + * @brief Replace the head node of linked-list queue. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @param pNewNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list new node registers + * configurations. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode_Head(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pNewNode) +{ + uint32_t cllr_offset; + uint32_t cllr_mask; + DMA_NodeInQInfoTypeDef node_info; + + /* Check the queue and the new node parameters */ + if ((pQList == NULL) || (pNewNode == NULL)) + { + return HAL_ERROR; + } + + /* Check the queue */ + if (pQList->Head == NULL) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; + + return HAL_ERROR; + } + + /* Check queue type */ + if (pQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Check nodes base addresses */ + if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pNewNode, NULL) != 0U) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; + + return HAL_ERROR; + } + + /* Check nodes types compatibility */ + if (DMA_List_CheckNodesTypes(pQList->Head, pNewNode, NULL) != 0U) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pNewNode, &cllr_mask, &cllr_offset); + + /* Check if first circular node queue is the first node */ + if (pQList->FirstCircularNode == pQList->Head) + { + /* Find last queue node */ + node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pQList, NULL, &node_info); + + /* Clear last node link */ + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = + ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; + + /* Set new node as first circular node */ + pQList->FirstCircularNode = pNewNode; + } + + /* Replace head node */ + pNewNode->LinkRegisters[cllr_offset] = pQList->Head->LinkRegisters[cllr_offset]; + pQList->Head->LinkRegisters[cllr_offset] = 0U; + pQList->Head = pNewNode; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_READY; + + /* Prevent MISRA-C2012-Rule-2.2_b */ + UNUSED(node_info); + + return HAL_OK; +} + +/** + * @brief Replace the tail node of linked-list queue. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @param pNewNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list new node registers + * configurations. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode_Tail(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pNewNode) +{ + uint32_t cllr_mask; + uint32_t cllr_offset; + DMA_NodeInQInfoTypeDef node_info; + + /* Check the queue and the new node parameters */ + if ((pQList == NULL) || (pNewNode == NULL)) + { + return HAL_ERROR; + } + + /* Check the queue */ + if (pQList->Head == NULL) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; + + return HAL_ERROR; + } + + /* Check queue type */ + if (pQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pNewNode, &cllr_mask, &cllr_offset); + + /* Find last node and get its position in selected queue */ + node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pQList, NULL, &node_info); + + /* Link previous node to new node */ + ((DMA_NodeTypeDef *)(node_info.previousnode_addr))->LinkRegisters[cllr_offset] = + ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; + + /* Clear CLLR for current node */ + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U; + + /* Check if first circular node queue is the last node */ + if (pQList->FirstCircularNode == ((DMA_NodeTypeDef *)(node_info.currentnode_addr))) + { + /* Link first circular node to new node */ + pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; + + /* Set new node as first circular node */ + pQList->FirstCircularNode = pNewNode; + } + /* Check if first circular node queue is not the last node */ + else if (pQList->FirstCircularNode != NULL) + { + /* Link first circular node to new node */ + pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pQList->FirstCircularNode & DMA_CLLR_LA) | cllr_mask; + } + else + { + /* Prevent MISRA-C2012-Rule-15.7 */ + } + + /* Check if queue contains one node */ + if (pQList->NodeNumber == 1U) + { + pQList->Head = pNewNode; + } + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Reset the linked-list queue and unlink queue nodes. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_ResetQ(DMA_QListTypeDef *const pQList) +{ + uint32_t cllr_offset; + DMA_NodeInQInfoTypeDef node_info; + + /* Check the queue parameter */ + if (pQList == NULL) + { + return HAL_ERROR; + } + + /* Check queue state */ + if (pQList->State == HAL_DMA_QUEUE_STATE_BUSY) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_BUSY; + + return HAL_ERROR; + } + + /* Check queue type */ + if (pQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Check the queue */ + if (pQList->Head != NULL) + { + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pQList->Head, NULL, &cllr_offset); + + /* Reset selected queue nodes */ + node_info.cllr_offset = cllr_offset; + DMA_List_ResetQueueNodes(pQList, &node_info); + } + + /* Reset head node address */ + pQList->Head = NULL; + + /* Reset node number */ + pQList->NodeNumber = 0U; + + /* Reset first circular node */ + pQList->FirstCircularNode = NULL; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_RESET; + + return HAL_OK; +} + +/** + * @brief Insert a source linked-list queue to a destination linked-list queue according to selecting previous node. + * @param pSrcQList : Pointer to a DMA_QListTypeDef structure that contains source queue information. + * @param pPrevNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list previous node registers + * configurations. + * @param pDestQList : Pointer to a DMA_QListTypeDef structure that contains destination queue information. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_InsertQ(DMA_QListTypeDef *const pSrcQList, + DMA_NodeTypeDef const *const pPrevNode, + DMA_QListTypeDef *const pDestQList) +{ + uint32_t cllr_mask; + uint32_t cllr_offset; + DMA_NodeInQInfoTypeDef src_q_node_info; + DMA_NodeInQInfoTypeDef dest_q_node_info; + + /* Check the source and destination queues and the previous node parameters */ + if ((pSrcQList == NULL) || (pDestQList == NULL)) + { + return HAL_ERROR; + } + + /* Check the source queue */ + if (pSrcQList->Head == NULL) + { + /* Update the queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; + + return HAL_ERROR; + } + + /* Check the source queue type */ + if (pSrcQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Check the destination queue type */ + if (pDestQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Check the source queue circularity */ + if (pSrcQList->FirstCircularNode != NULL) + { + /* Update the source queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Check nodes base addresses */ + if (DMA_List_CheckNodesBaseAddresses(pSrcQList->Head, pPrevNode, pDestQList->Head) != 0U) + { + /* Update the source queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; + + /* Update the destination queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; + + return HAL_ERROR; + } + + /* Check nodes types compatibility */ + if (DMA_List_CheckNodesTypes(pSrcQList->Head, pPrevNode, pDestQList->Head) != 0U) + { + /* Update the source queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + /* Update the destination queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the source queue state */ + pSrcQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the source queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the destination queue state */ + pDestQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the destination queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pSrcQList->Head, &cllr_mask, &cllr_offset); + + /* Empty destination queue */ + if (pDestQList->Head == NULL) + { + pDestQList->Head = pSrcQList->Head; + pDestQList->NodeNumber = pSrcQList->NodeNumber; + } + /* Not empty destination queue */ + else + { + /* Previous node is empty */ + if (pPrevNode == NULL) + { + /* Find node and get its position in selected queue */ + src_q_node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pSrcQList, NULL, &src_q_node_info); + + /* Check if first circular node queue is the first node */ + if (pDestQList->FirstCircularNode == pDestQList->Head) + { + /* Find node and get its position in selected queue */ + dest_q_node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pDestQList, NULL, &dest_q_node_info); + + /* Link destination queue tail node to new first circular node */ + ((DMA_NodeTypeDef *)dest_q_node_info.currentnode_addr)->LinkRegisters[cllr_offset] = + ((uint32_t)pSrcQList->Head & DMA_CLLR_LA) | cllr_mask; + + /* Set the head node of source queue as the first circular node */ + pDestQList->FirstCircularNode = pSrcQList->Head; + } + + /* Link the last node of source queue to the fist node of destination queue */ + ((DMA_NodeTypeDef *)(src_q_node_info.currentnode_addr))->LinkRegisters[cllr_offset] = + ((uint32_t)pDestQList->Head & DMA_CLLR_LA) | cllr_mask; + pDestQList->Head = pSrcQList->Head; + pDestQList->NodeNumber += pSrcQList->NodeNumber; + } + /* Previous node is not empty */ + else + { + /* Find node and get its position in selected queue */ + dest_q_node_info.cllr_offset = cllr_offset; + if (DMA_List_FindNode(pDestQList, pPrevNode, &dest_q_node_info) == 0U) + { + /* Selected node is the last destination queue node */ + if (dest_q_node_info.currentnode_pos == pDestQList->NodeNumber) + { + /* Link the first node of source queue to the last node of destination queue */ + ((DMA_NodeTypeDef *)(dest_q_node_info.currentnode_addr))->LinkRegisters[cllr_offset] = + ((uint32_t)pSrcQList->Head & DMA_CLLR_LA) | cllr_mask; + pDestQList->NodeNumber += pSrcQList->NodeNumber; + + /* Check if first circular node queue is not empty */ + if (pDestQList->FirstCircularNode != NULL) + { + /* Find node and get its position in selected queue */ + src_q_node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pSrcQList, NULL, &src_q_node_info); + + /* Find first circular node */ + (void)DMA_List_FindNode(pDestQList, pDestQList->FirstCircularNode, &dest_q_node_info); + + /* Link last source queue node to first destination queue */ + ((DMA_NodeTypeDef *)src_q_node_info.currentnode_addr)->LinkRegisters[cllr_offset] = + (dest_q_node_info.currentnode_addr & DMA_CLLR_LA) | cllr_mask; + } + } + /* Selected node is not the last destination queue node */ + else + { + /* Link the first node of source queue to the previous node of destination queue */ + ((DMA_NodeTypeDef *)(dest_q_node_info.currentnode_addr))->LinkRegisters[cllr_offset] = + ((uint32_t)pSrcQList->Head & DMA_CLLR_LA) | cllr_mask; + + /* Find node and get its position in selected queue */ + src_q_node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pSrcQList, NULL, &src_q_node_info); + + /* Link the last node of source queue to the next node of destination queue */ + ((DMA_NodeTypeDef *)(src_q_node_info.currentnode_addr))->LinkRegisters[cllr_offset] = + (dest_q_node_info.nextnode_addr & DMA_CLLR_LA) | cllr_mask; + + /* Update queues counter */ + pDestQList->NodeNumber += pSrcQList->NodeNumber; + } + } + else + { + /* Update the destination queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NOTFOUND; + + return HAL_ERROR; + } + } + } + + /* Clean the source queue variable as it is obsolete */ + DMA_List_CleanQueue(pSrcQList); + + /* Update the destination queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the destination queue state */ + pDestQList->State = HAL_DMA_QUEUE_STATE_READY; + + /* Prevent MISRA-C2012-Rule-2.2_b */ + UNUSED(src_q_node_info); + UNUSED(dest_q_node_info); + + return HAL_OK; +} + +/** + * @brief Insert a source linked-list queue at the head of destination queue. + * @param pSrcQList : Pointer to a DMA_QListTypeDef structure that contains source queue information. + * @param pDestQList : Pointer to a DMA_QListTypeDef structure that contains destination queue information. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_InsertQ_Head(DMA_QListTypeDef *const pSrcQList, + DMA_QListTypeDef *const pDestQList) +{ + uint32_t cllr_mask; + uint32_t cllr_offset; + DMA_NodeInQInfoTypeDef src_q_node_info; + DMA_NodeInQInfoTypeDef dest_q_node_info; + + /* Check the source and destination queues and the previous node parameters */ + if ((pSrcQList == NULL) || (pDestQList == NULL)) + { + return HAL_ERROR; + } + + /* Check the source queue */ + if (pSrcQList->Head == NULL) + { + /* Update the queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; + + return HAL_ERROR; + } + + /* Check the source queue type */ + if (pSrcQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Check the destination queue type */ + if (pDestQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Check nodes base addresses */ + if (DMA_List_CheckNodesBaseAddresses(pSrcQList->Head, pDestQList->Head, NULL) != 0U) + { + /* Update the source queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; + + /* Update the destination queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; + + return HAL_ERROR; + } + + /* Check nodes types compatibility */ + if (DMA_List_CheckNodesTypes(pSrcQList->Head, pDestQList->Head, NULL) != 0U) + { + /* Update the source queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + /* Update the destination queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the source queue state */ + pSrcQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the source queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the destination queue state */ + pDestQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the destination queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pSrcQList->Head, &cllr_mask, &cllr_offset); + + /* Empty destination queue */ + if (pDestQList->Head == NULL) + { + pDestQList->Head = pSrcQList->Head; + pDestQList->NodeNumber = pSrcQList->NodeNumber; + } + /* Not empty destination queue */ + else + { + /* Find node and get its position in selected queue */ + src_q_node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pSrcQList, NULL, &src_q_node_info); + + /* Check if first circular node queue is the first node */ + if (pDestQList->FirstCircularNode == pDestQList->Head) + { + /* Find node and get its position in selected queue */ + dest_q_node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pDestQList, NULL, &dest_q_node_info); + + /* Link destination queue tail node to new first circular node */ + ((DMA_NodeTypeDef *)dest_q_node_info.currentnode_addr)->LinkRegisters[cllr_offset] = + ((uint32_t)pSrcQList->Head & DMA_CLLR_LA) | cllr_mask; + + /* Set the head node of source queue as the first circular node */ + pDestQList->FirstCircularNode = pSrcQList->Head; + } + + /* Link the last node of source queue to the fist node of destination queue */ + ((DMA_NodeTypeDef *)(src_q_node_info.currentnode_addr))->LinkRegisters[cllr_offset] = + ((uint32_t)pDestQList->Head & DMA_CLLR_LA) | cllr_mask; + pDestQList->Head = pSrcQList->Head; + pDestQList->NodeNumber += pSrcQList->NodeNumber; + } + + /* Clean the source queue variable as it is obsolete */ + DMA_List_CleanQueue(pSrcQList); + + /* Update the destination queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the destination queue state */ + pDestQList->State = HAL_DMA_QUEUE_STATE_READY; + + /* Prevent MISRA-C2012-Rule-2.2_b */ + UNUSED(src_q_node_info); + UNUSED(dest_q_node_info); + + return HAL_OK; +} + +/** + * @brief Insert a source linked-list queue at the tail of destination queue. + * @param pSrcQList : Pointer to a DMA_QListTypeDef structure that contains source queue information. + * @param pDestQList : Pointer to a DMA_QListTypeDef structure that contains destination queue information. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_InsertQ_Tail(DMA_QListTypeDef *const pSrcQList, + DMA_QListTypeDef *const pDestQList) +{ + uint32_t cllr_mask; + uint32_t cllr_offset; + DMA_NodeInQInfoTypeDef src_q_node_info; + DMA_NodeInQInfoTypeDef dest_q_node_info; + + /* Check the source and destination queues and the previous node parameters */ + if ((pSrcQList == NULL) || (pDestQList == NULL)) + { + return HAL_ERROR; + } + + /* Check the source queue */ + if (pSrcQList->Head == NULL) + { + /* Update the queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; + + return HAL_ERROR; + } + + /* Check the source queue type */ + if (pSrcQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Check the destination queue type */ + if (pDestQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Check nodes base addresses */ + if (DMA_List_CheckNodesBaseAddresses(pSrcQList->Head, pDestQList->Head, NULL) != 0U) + { + /* Update the source queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; + + /* Update the destination queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; + + return HAL_ERROR; + } + + /* Check nodes types compatibility */ + if (DMA_List_CheckNodesTypes(pSrcQList->Head, pDestQList->Head, NULL) != 0U) + { + /* Update the source queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + /* Update the destination queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the source queue state */ + pSrcQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the source queue error code */ + pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the destination queue state */ + pDestQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the destination queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pSrcQList->Head, &cllr_mask, &cllr_offset); + + /* Empty destination queue */ + if (pDestQList->Head == NULL) + { + pDestQList->Head = pSrcQList->Head; + pDestQList->NodeNumber = pSrcQList->NodeNumber; + } + /* Not empty destination queue */ + else + { + /* Find node and get its position in selected queue */ + dest_q_node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pDestQList, NULL, &dest_q_node_info); + + /* Update source queue last node CLLR to link it with destination first node */ + ((DMA_NodeTypeDef *)(dest_q_node_info.currentnode_addr))->LinkRegisters[cllr_offset] = + ((uint32_t)pSrcQList->Head & DMA_CLLR_LA) | cllr_mask; + pDestQList->NodeNumber += pSrcQList->NodeNumber; + + /* Check if first circular node queue is not empty */ + if (pDestQList->FirstCircularNode != NULL) + { + /* Find node and get its position in selected queue */ + src_q_node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pSrcQList, NULL, &src_q_node_info); + + /* Find first circular node */ + (void)DMA_List_FindNode(pDestQList, pDestQList->FirstCircularNode, &dest_q_node_info); + + /* Link last source queue node to first destination queue */ + ((DMA_NodeTypeDef *)src_q_node_info.currentnode_addr)->LinkRegisters[cllr_offset] = + (dest_q_node_info.currentnode_addr & DMA_CLLR_LA) | cllr_mask; + } + } + + /* Clean the source queue variable as it is obsolete */ + DMA_List_CleanQueue(pSrcQList); + + /* Update the destination queue error code */ + pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the destination queue state */ + pDestQList->State = HAL_DMA_QUEUE_STATE_READY; + + /* Prevent MISRA-C2012-Rule-2.2_b */ + UNUSED(src_q_node_info); + + return HAL_OK; +} + +/** + * @brief Set circular mode configuration for linked-list queue. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @param pFirstCircularNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list first circular node + * registers configurations. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_SetCircularModeConfig(DMA_QListTypeDef *const pQList, + DMA_NodeTypeDef *const pFirstCircularNode) +{ + uint32_t cllr_mask; + uint32_t cllr_offset; + DMA_NodeInQInfoTypeDef node_info; + + /* Check the queue and the first circular node parameters */ + if ((pQList == NULL) || (pFirstCircularNode == NULL)) + { + return HAL_ERROR; + } + + /* Check the queue */ + if (pQList->Head == NULL) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; + + return HAL_ERROR; + } + + /* Check queue circular mode */ + if (pQList->FirstCircularNode != NULL) + { + if (pQList->FirstCircularNode == pFirstCircularNode) + { + return HAL_OK; + } + else + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + } + + /* Check queue type */ + if (pQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pFirstCircularNode, &cllr_mask, &cllr_offset); + + /* Find the first circular node and get its position in selected queue */ + node_info.cllr_offset = cllr_offset; + if (DMA_List_FindNode(pQList, pFirstCircularNode, &node_info) == 0U) + { + /* Find the last queue node and get its position in selected queue */ + (void)DMA_List_FindNode(pQList, NULL, &node_info); + + /* Set circular mode */ + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = + ((uint32_t)pFirstCircularNode & DMA_CLLR_LA) | cllr_mask; + + /* Update first circular node in queue */ + pQList->FirstCircularNode = pFirstCircularNode; + } + else + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NOTFOUND; + + return HAL_ERROR; + } + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_READY; + + /* Prevent MISRA-C2012-Rule-2.2_b */ + UNUSED(node_info); + + return HAL_OK; +} + +/** + * @brief Set circular mode for linked-list queue. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_SetCircularMode(DMA_QListTypeDef *const pQList) +{ + uint32_t cllr_mask; + uint32_t cllr_offset; + DMA_NodeInQInfoTypeDef node_info; + + /* Check the queue parameter */ + if (pQList == NULL) + { + return HAL_ERROR; + } + + /* Check the queue */ + if (pQList->Head == NULL) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; + + return HAL_ERROR; + } + + /* Check queue circular mode */ + if (pQList->FirstCircularNode != NULL) + { + if (pQList->FirstCircularNode == pQList->Head) + { + return HAL_OK; + } + else + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + } + + /* Check queue type */ + if (pQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pQList->Head, &cllr_mask, &cllr_offset); + + /* Find the last queue node and get its position in selected queue */ + node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pQList, NULL, &node_info); + + /* Set circular mode */ + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = + ((uint32_t)pQList->Head & DMA_CLLR_LA) | cllr_mask; + + /* Update linked-list circular state */ + pQList->FirstCircularNode = pQList->Head; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_READY; + + /* Prevent MISRA-C2012-Rule-2.2_b */ + UNUSED(node_info); + + return HAL_OK; +} + +/** + * @brief Clear circular mode for linked-list queue. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_ClearCircularMode(DMA_QListTypeDef *const pQList) +{ + uint32_t cllr_offset; + DMA_NodeInQInfoTypeDef node_info; + + /* Check the queue parameter */ + if (pQList == NULL) + { + return HAL_ERROR; + } + + /* Check the queue */ + if (pQList->Head == NULL) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; + + return HAL_ERROR; + } + + /* Check queue circular mode */ + if (pQList->FirstCircularNode == NULL) + { + return HAL_OK; + } + + /* Check queue type */ + if (pQList->Type == QUEUE_TYPE_DYNAMIC) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register offset */ + DMA_List_GetCLLRNodeInfo(pQList->Head, NULL, &cllr_offset); + + /* Find the last queue node and get its position in selected queue */ + node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pQList, NULL, &node_info); + + /* Clear circular mode */ + ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U; + + /* Update linked-list circular configuration */ + pQList->FirstCircularNode = NULL; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_READY; + + /* Prevent MISRA-C2012-Rule-2.2_b */ + UNUSED(node_info); + + return HAL_OK; +} + +/** + * @brief Convert a linked-list queue to dynamic (Optimized DMA queue execution). + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_ConvertQToDynamic(DMA_QListTypeDef *const pQList) +{ + uint32_t cllr_offset; + uint32_t currentnode_addr; + DMA_NodeTypeDef context_node; + DMA_NodeInQInfoTypeDef node_info; + + /* Check the queue parameter */ + if (pQList == NULL) + { + return HAL_ERROR; + } + + /* Check the queue */ + if (pQList->Head == NULL) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; + + return HAL_ERROR; + } + + /* Check if queue is dynamic */ + if (pQList->Type == QUEUE_TYPE_DYNAMIC) + { + return HAL_OK; + } + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pQList->Head, NULL, &cllr_offset); + + /* Check queue circularity */ + if (pQList->FirstCircularNode != 0U) + { + /* Find the last queue node and get its position in selected queue */ + node_info.cllr_offset = cllr_offset; + (void)DMA_List_FindNode(pQList, NULL, &node_info); + } + + /* Set current node address */ + currentnode_addr = (uint32_t)pQList->Head; + + /* Store register value */ + DMA_List_FillNode(pQList->Head, &context_node); + + /* Convert all nodes to dyncamic (Bypass head node) */ + for (uint32_t node_count = 1U; node_count < pQList->NodeNumber; node_count++) + { + /* Update node address */ + MODIFY_REG(currentnode_addr, DMA_CLLR_LA, (context_node.LinkRegisters[cllr_offset] & DMA_CLLR_LA)); + + /* Bypass the first circular node when first circular node isn't the last queue node */ + if (((uint32_t)pQList->FirstCircularNode != 0U) && + ((uint32_t)pQList->FirstCircularNode != node_info.currentnode_addr) && + ((uint32_t)pQList->FirstCircularNode == currentnode_addr)) + { + /* Copy first circular node to context node */ + DMA_List_FillNode(pQList->FirstCircularNode, &context_node); + } + else + { + /* Convert current node to dynamic */ + DMA_List_ConvertNodeToDynamic((uint32_t)&context_node, currentnode_addr, (cllr_offset + 1U)); + } + } + + /* Check if first circular node is the last node queue */ + if (((uint32_t)pQList->FirstCircularNode != 0U) && + ((uint32_t)pQList->FirstCircularNode != node_info.currentnode_addr)) + { + /* Update all queue nodes CLLR */ + DMA_List_UpdateDynamicQueueNodesCLLR(pQList, LASTNODE_ISNOT_CIRCULAR); + } + else + { + /* Update all queue nodes CLLR */ + DMA_List_UpdateDynamicQueueNodesCLLR(pQList, LASTNODE_IS_CIRCULAR); + } + + /* Set queue type */ + pQList->Type = QUEUE_TYPE_DYNAMIC; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Convert a linked-list queue to static (Not optimized DMA queue execution). + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_ConvertQToStatic(DMA_QListTypeDef *const pQList) +{ + uint32_t cllr_offset; + uint32_t currentnode_addr; + DMA_NodeTypeDef context_node; + + /* Check the queue parameter */ + if (pQList == NULL) + { + return HAL_ERROR; + } + + /* Check the queue */ + if (pQList->Head == NULL) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; + + return HAL_ERROR; + } + + /* Check if queue is static */ + if (pQList->Type == QUEUE_TYPE_STATIC) + { + return HAL_OK; + } + + /* Set current node address */ + currentnode_addr = (uint32_t)pQList->Head; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_BUSY; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Get CLLR register mask and offset */ + DMA_List_GetCLLRNodeInfo(pQList->Head, NULL, &cllr_offset); + + /* Set all CLLR queue nodes to their default positions */ + DMA_List_UpdateStaticQueueNodesCLLR(pQList, UPDATE_CLLR_POSITION); + + /* Convert all nodes to static (Bypass head node) */ + for (uint32_t node_count = 1U; node_count < pQList->NodeNumber; node_count++) + { + /* Update context node register values */ + DMA_List_FillNode((DMA_NodeTypeDef *)currentnode_addr, &context_node); + + /* Update node address */ + MODIFY_REG(currentnode_addr, DMA_CLLR_LA, (context_node.LinkRegisters[cllr_offset] & DMA_CLLR_LA)); + + /* Convert current node to static */ + DMA_List_ConvertNodeToStatic((uint32_t)&context_node, currentnode_addr, (cllr_offset + 1U)); + } + + /* Set all CLLR queue nodes to their default values */ + DMA_List_UpdateStaticQueueNodesCLLR(pQList, UPDATE_CLLR_VALUE); + + /* Set queue type */ + pQList->Type = QUEUE_TYPE_STATIC; + + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Update the queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Link linked-list queue to a DMA channel. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_LinkQ(DMA_HandleTypeDef *const hdma, + DMA_QListTypeDef *const pQList) +{ + HAL_DMA_StateTypeDef state; + + /* Check the DMA channel handle and the queue parameters */ + if ((hdma == NULL) || (pQList == NULL)) + { + return HAL_ERROR; + } + + /* Get DMA state */ + state = hdma->State; + + /* Check DMA channel state */ + if ((hdma->State == HAL_DMA_STATE_BUSY) || (state == HAL_DMA_STATE_SUSPEND)) + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + + /* Check queue state */ + if (pQList->State == HAL_DMA_QUEUE_STATE_BUSY) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_BUSY; + + return HAL_ERROR; + } + + /* Check circularity compatibility */ + if (hdma->Mode == DMA_LINKEDLIST_CIRCULAR) + { + /* Check first circular node */ + if (pQList->FirstCircularNode == NULL) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + } + else + { + /* Check first circular node */ + if (pQList->FirstCircularNode != NULL) + { + /* Update the queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; + + return HAL_ERROR; + } + } + + /* Register queue to DMA handle */ + hdma->LinkedListQueue = pQList; + + return HAL_OK; +} + +/** + * @brief Unlink linked-list queue from a DMA channel. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_List_UnLinkQ(DMA_HandleTypeDef *const hdma) +{ + HAL_DMA_StateTypeDef state; + + /* Check the DMA channel parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Get DMA state */ + state = hdma->State; + + /* Check DMA channel state */ + if ((hdma->State == HAL_DMA_STATE_BUSY) || (state == HAL_DMA_STATE_SUSPEND)) + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + + /* Clear queue information from DMA channel handle */ + hdma->LinkedListQueue = NULL; + + return HAL_OK; +} +/** + * @} + */ + +/** @addtogroup DMAEx_Exported_Functions_Group4 + * +@verbatim + ====================================================================================================================== + ##### Data handling, repeated block and trigger configuration functions ##### + ====================================================================================================================== + [..] + This section provides functions allowing to : + (+) Configure DMA channel data handling. + (+) Configure DMA channel repeated block. + (+) Configure DMA channel trigger. + + [..] + (+) The HAL_DMAEx_ConfigDataHandling() function allows to configure DMA channel data handling. + (++) GPDMA data handling : byte-based reordering, packing/unpacking, padding/truncation, sign extension + and left/right alignment. + + (+) The HAL_DMAEx_ConfigTrigger() function allows to configure DMA channel HW triggers. + +@endverbatim + * @{ + */ + +/** + * @brief Configure the DMA channel data handling according to the specified parameters in the + * DMA_DataHandlingConfTypeDef. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information + * for the specified DMA Channel. + * @param pConfigDataHandling : Pointer to a DMA_DataHandlingConfTypeDef structure that contains the data handling + * configuration. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_ConfigDataHandling(DMA_HandleTypeDef *const hdma, + DMA_DataHandlingConfTypeDef const *const pConfigDataHandling) +{ + /* Check the DMA peripheral handle and data handling parameters */ + if ((hdma == NULL) || (pConfigDataHandling == NULL)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_DATA_ALIGNMENT(pConfigDataHandling->DataAlignment)); + assert_param(IS_DMA_DATA_EXCHANGE(pConfigDataHandling->DataExchange)); + + /* Check DMA channel state */ + if (hdma->State == HAL_DMA_STATE_READY) + { + MODIFY_REG(hdma->Instance->CTR1, (DMA_CTR1_DHX | DMA_CTR1_DBX | DMA_CTR1_SBX | DMA_CTR1_PAM), + (pConfigDataHandling->DataAlignment | pConfigDataHandling->DataExchange)); + } + else + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Configure the DMA channel trigger according to the specified parameters in the DMA_TriggerConfTypeDef. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for + * the specified DMA Channel. + * @param pConfigTrigger : Pointer to a DMA_TriggerConfTypeDef structure that contains the trigger configuration. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_ConfigTrigger(DMA_HandleTypeDef *const hdma, + DMA_TriggerConfTypeDef const *const pConfigTrigger) +{ + /* Check the DMA peripheral handle and trigger parameters */ + if ((hdma == NULL) || (pConfigTrigger == NULL)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + assert_param(IS_DMA_TRIGGER_POLARITY(pConfigTrigger->TriggerPolarity)); + assert_param(IS_DMA_TRIGGER_MODE(pConfigTrigger->TriggerMode)); + assert_param(IS_DMA_TRIGGER_SELECTION(pConfigTrigger->TriggerSelection)); + + /* Check DMA channel state */ + if (hdma->State == HAL_DMA_STATE_READY) + { + MODIFY_REG(hdma->Instance->CTR2, (DMA_CTR2_TRIGPOL | DMA_CTR2_TRIGSEL | DMA_CTR2_TRIGM), + (pConfigTrigger->TriggerPolarity | pConfigTrigger->TriggerMode | + (pConfigTrigger->TriggerSelection << DMA_CTR2_TRIGSEL_Pos))); + } + else + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup DMAEx_Exported_Functions_Group5 + * +@verbatim + ====================================================================================================================== + ##### Suspend and resume operation functions ##### + ====================================================================================================================== + [..] + This section provides functions allowing to : + (+) Suspend any ongoing DMA channel transfer. + (+) Resume any suspended DMA channel transfer. + + [..] + (+) The HAL_DMAEx_Suspend() function allows to suspend any ongoing DMA channel transfer in polling mode (Blocking + mode). + + (+) The HAL_DMAEx_Suspend_IT() function allows to suspend any ongoing DMA channel transfer in interrupt mode + (Non-blocking mode). + + (+) The HAL_DMAEx_Resume() function allows to resume any suspended DMA channel transfer. + +@endverbatim + * @{ + */ + +/** + * @brief Suspend any ongoing DMA channel transfer in polling mode (Blocking mode). + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA channel. + * @note After suspending a DMA channel, a check for wait until the DMA channel is effectively suspended is added. If + * a channel is suspended while a data transfer is ongoing, the current data will be transferred and the + * channel will be effectively suspended only after the transfer of this single/burst data is finished. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_Suspend(DMA_HandleTypeDef *const hdma) +{ + /* Get tick number */ + uint32_t tickstart = HAL_GetTick(); + + /* Check the DMA peripheral handle */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check DMA channel state */ + if (hdma->State != HAL_DMA_STATE_BUSY) + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + else + { + /* Suspend the channel */ + hdma->Instance->CCR |= DMA_CCR_SUSP; + + /* Check if the DMA channel is suspended */ + while ((hdma->Instance->CSR & DMA_CSR_SUSPF) == 0U) + { + /* Check for the timeout */ + if ((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT) + { + /* Update the DMA channel error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT; + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + } + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_SUSPEND; + } + + return HAL_OK; +} + +/** + * @brief Suspend any ongoing DMA channel transfer in polling mode (Non-blocking mode). + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_Suspend_IT(DMA_HandleTypeDef *const hdma) +{ + /* Check the DMA peripheral handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check DMA channel state */ + if (hdma->State != HAL_DMA_STATE_BUSY) + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + else + { + /* Suspend the DMA channel and activate suspend interrupt */ + hdma->Instance->CCR |= (DMA_CCR_SUSP | DMA_CCR_SUSPIE); + } + + return HAL_OK; +} + +/** + * @brief Resume any suspended DMA channel transfer. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_DMAEx_Resume(DMA_HandleTypeDef *const hdma) +{ + /* Check the DMA peripheral handle parameter */ + if (hdma == NULL) + { + return HAL_ERROR; + } + + /* Check DMA channel state */ + if (hdma->State != HAL_DMA_STATE_SUSPEND) + { + /* Update the DMA channel error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + else + { + /* Resume the DMA channel */ + hdma->Instance->CCR &= (~DMA_CCR_SUSP); + + /* Clear the suspend flag */ + hdma->Instance->CFCR |= DMA_CFCR_SUSPF; + + /* Update the DMA channel state */ + hdma->State = HAL_DMA_STATE_BUSY; + } + + return HAL_OK; +} +/** + * @} + */ + +/** @addtogroup DMAEx_Exported_Functions_Group6 + * +@verbatim + ====================================================================================================================== + ##### Fifo status function ##### + ====================================================================================================================== + [..] + This section provides function allowing to get DMA channel FIFO level. + + [..] + (+) The HAL_DMAEx_GetFifoLevel() function allows to return the number of available write beats in the FIFO, in + units of the programmed destination data. + (++) This API is available only for DMA channels that supports FIFO. + +@endverbatim + * @{ + */ + +/** + * @brief Get and returns the DMA channel FIFO level. + * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval Returns the number of available beats in FIFO. + */ +uint32_t HAL_DMAEx_GetFifoLevel(DMA_HandleTypeDef const *const hdma) +{ + return ((hdma->Instance->CSR & DMA_CSR_FIFOL) >> DMA_CSR_FIFOL_Pos); +} +/** + * @} + */ + +/** + * @} + */ + +/* Private functions -------------------------------------------------------------------------------------------------*/ +/** @defgroup DMAEx_Private_Functions DMAEx Private Functions + * @brief DMAEx Private Functions + * @{ + */ + +/** + * @brief Initialize the DMA handle according to the specified parameters in the DMA_InitTypeDef. + * @param hdma : pointer to a DMA_HandleTypeDef structure that contains the configuration information for the + * specified DMA Channel. + * @retval None. + */ +static void DMA_List_Init(DMA_HandleTypeDef const *const hdma) +{ + uint32_t tmpreg; + + /* Prepare DMA Channel Control Register (CCR) value */ + tmpreg = hdma->InitLinkedList.Priority | hdma->InitLinkedList.LinkStepMode; + + /* Check DMA channel instance */ + if (IS_GPDMA_INSTANCE(hdma->Instance) != 0U) + { + tmpreg |= hdma->InitLinkedList.LinkAllocatedPort; + } + + /* Write DMA Channel Control Register (CCR) */ + MODIFY_REG(hdma->Instance->CCR, DMA_CCR_PRIO | DMA_CCR_LAP | DMA_CCR_LSM, tmpreg); + + /* Write DMA Channel Control Register (CTR1) */ + WRITE_REG(hdma->Instance->CTR1, 0U); + + /* Write DMA Channel Control Register (CTR2) */ + WRITE_REG(hdma->Instance->CTR2, hdma->InitLinkedList.TransferEventMode); + + /* Write DMA Channel Control Register (CBR1) */ + WRITE_REG(hdma->Instance->CBR1, 0U); + + /* Write DMA Channel Control Register (CSAR) */ + WRITE_REG(hdma->Instance->CSAR, 0U); + + /* Write DMA Channel Control Register (CDAR) */ + WRITE_REG(hdma->Instance->CDAR, 0U); + + /* Write DMA Channel linked-list address register (CLLR) */ + WRITE_REG(hdma->Instance->CLLR, 0U); +} + +/** + * @brief Build a DMA channel node according to the specified parameters in the DMA_NodeConfTypeDef. + * @param pNodeConfig : Pointer to a DMA_NodeConfTypeDef structure that contains the configuration information for the + * specified DMA linked-list Node. + * @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers + * configurations. + * @retval None. + */ +static void DMA_List_BuildNode(DMA_NodeConfTypeDef const *const pNodeConfig, + DMA_NodeTypeDef *const pNode) +{ + /* Update CTR1 register value ***************************************************************************************/ + /* Prepare DMA channel transfer register (CTR1) value */ + pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] = pNodeConfig->Init.DestInc | + pNodeConfig->Init.DestDataWidth | + pNodeConfig->DataHandlingConfig.DataAlignment | + pNodeConfig->Init.SrcInc | + pNodeConfig->Init.SrcDataWidth; + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + /* set source channel security attribute */ + if (pNodeConfig->SrcSecure == DMA_CHANNEL_SRC_SEC) + { + pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] |= DMA_CTR1_SSEC; + } + + /* set destination channel security attribute */ + if (pNodeConfig->DestSecure == DMA_CHANNEL_DEST_SEC) + { + pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] |= DMA_CTR1_DSEC; + } +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + /* Add parameters related to DMA configuration */ + if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_GPDMA) == DMA_CHANNEL_TYPE_GPDMA) + { + /* Prepare DMA channel transfer register (CTR1) value */ + pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] |= + (pNodeConfig->Init.TransferAllocatedPort | pNodeConfig->DataHandlingConfig.DataExchange | + (((pNodeConfig->Init.DestBurstLength - 1U) << DMA_CTR1_DBL_1_Pos) & DMA_CTR1_DBL_1) | + (((pNodeConfig->Init.SrcBurstLength - 1U) << DMA_CTR1_SBL_1_Pos) & DMA_CTR1_SBL_1)); + } + /*********************************************************************************** CTR1 register value is updated */ + + + /* Update CTR2 register value ***************************************************************************************/ + /* Prepare DMA channel transfer register 2 (CTR2) value */ + pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] = pNodeConfig->Init.TransferEventMode | + (pNodeConfig->Init.Request & (DMA_CTR2_REQSEL | DMA_CTR2_SWREQ)); + + /* Check for memory to peripheral transfer */ + if ((pNodeConfig->Init.Direction) == DMA_MEMORY_TO_PERIPH) + { + /* Check for GPDMA */ + if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_GPDMA) == DMA_CHANNEL_TYPE_GPDMA) + { + pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] |= DMA_CTR2_DREQ; + } + } + /* Memory to memory transfer */ + else if ((pNodeConfig->Init.Direction) == DMA_MEMORY_TO_MEMORY) + { + pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] |= DMA_CTR2_SWREQ; + } + else + { + /* Prevent MISRA-C2012-Rule-15.7 */ + } + + /* Check if trigger feature is active */ + if (pNodeConfig->TriggerConfig.TriggerPolarity != DMA_TRIG_POLARITY_MASKED) + { + /* Prepare DMA channel transfer register 2 (CTR2) value */ + pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] |= + pNodeConfig->TriggerConfig.TriggerMode | pNodeConfig->TriggerConfig.TriggerPolarity | + ((pNodeConfig->TriggerConfig.TriggerSelection << DMA_CTR2_TRIGSEL_Pos) & DMA_CTR2_TRIGSEL); + } + /*********************************************************************************** CTR2 register value is updated */ + + + /* Update CBR1 register value ***************************************************************************************/ + /* Prepare DMA channel block register 1 (CBR1) value */ + pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = (pNodeConfig->DataSize & DMA_CBR1_BNDT); + + /*********************************************************************************** CBR1 register value is updated */ + + + /* Update CSAR register value ***************************************************************************************/ + pNode->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = pNodeConfig->SrcAddress; + /*********************************************************************************** CSAR register value is updated */ + + + /* Update CDAR register value ***************************************************************************************/ + pNode->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = pNodeConfig->DstAddress; + /*********************************************************************************** CDAR register value is updated */ + + + /* Update node information value ************************************************************************************/ + /* Set node information */ + pNode->NodeInfo = pNodeConfig->NodeType; + pNode->NodeInfo |= (NODE_CLLR_LINEAR_DEFAULT_OFFSET << NODE_CLLR_IDX_POS); + /******************************************************************************** Node information value is updated */ +} + +/** + * @brief Get a DMA channel node configuration. + * @param pNodeConfig : Pointer to a DMA_NodeConfTypeDef structure that contains the configuration information for the + * specified DMA linked-list Node. + * @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers + * configurations. + * @retval None. + */ +static void DMA_List_GetNodeConfig(DMA_NodeConfTypeDef *const pNodeConfig, + DMA_NodeTypeDef const *const pNode) +{ + + /* Get node information *********************************************************************************************/ + pNodeConfig->NodeType = (pNode->NodeInfo & NODE_TYPE_MASK); + /*************************************************************************************** Node type value is updated */ + + + /* Get CTR1 fields values *******************************************************************************************/ + pNodeConfig->Init.SrcInc = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_SINC; + pNodeConfig->Init.DestInc = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DINC; + pNodeConfig->Init.SrcDataWidth = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_SDW_LOG2; + pNodeConfig->Init.DestDataWidth = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2; + pNodeConfig->Init.SrcBurstLength = ((pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & + DMA_CTR1_SBL_1) >> DMA_CTR1_SBL_1_Pos) + 1U; + pNodeConfig->Init.DestBurstLength = ((pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & + DMA_CTR1_DBL_1) >> DMA_CTR1_DBL_1_Pos) + 1U; + pNodeConfig->Init.TransferAllocatedPort = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & + (DMA_CTR1_SAP | DMA_CTR1_DAP); + pNodeConfig->DataHandlingConfig.DataExchange = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & + (DMA_CTR1_SBX | DMA_CTR1_DBX | DMA_CTR1_DHX); + pNodeConfig->DataHandlingConfig.DataAlignment = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_PAM; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + if ((pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_SSEC) != 0U) + { + pNodeConfig->SrcSecure = DMA_CHANNEL_SRC_SEC; + } + else + { + pNodeConfig->SrcSecure = DMA_CHANNEL_SRC_NSEC; + } + + if ((pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DSEC) != 0U) + { + pNodeConfig->DestSecure = DMA_CHANNEL_DEST_SEC; + } + else + { + pNodeConfig->DestSecure = DMA_CHANNEL_DEST_NSEC; + } +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + /*********************************************************************************** CTR1 fields values are updated */ + + + /* Get CTR2 fields values *******************************************************************************************/ + if ((pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] & DMA_CTR2_SWREQ) != 0U) + { + pNodeConfig->Init.Request = DMA_REQUEST_SW; + pNodeConfig->Init.Direction = DMA_MEMORY_TO_MEMORY; + } + else + { + pNodeConfig->Init.Request = pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] & DMA_CTR2_REQSEL; + + if ((pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] & DMA_CTR2_DREQ) != 0U) + { + pNodeConfig->Init.Direction = DMA_MEMORY_TO_PERIPH; + } + else + { + pNodeConfig->Init.Direction = DMA_PERIPH_TO_MEMORY; + } + } + + pNodeConfig->Init.BlkHWRequest = (pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] & DMA_CTR2_BREQ); + pNodeConfig->TriggerConfig.TriggerMode = pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] & DMA_CTR2_TRIGM; + pNodeConfig->TriggerConfig.TriggerPolarity = pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] & DMA_CTR2_TRIGPOL; + pNodeConfig->TriggerConfig.TriggerSelection = (pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] & + DMA_CTR2_TRIGSEL) >> DMA_CTR2_TRIGSEL_Pos; + pNodeConfig->Init.TransferEventMode = pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] & DMA_CTR2_TCEM; + /*********************************************************************************** CTR2 fields values are updated */ + + + /* Get CBR1 fields **************************************************************************************************/ + pNodeConfig->DataSize = pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] & DMA_CBR1_BNDT; + + /*********************************************************************************** CBR1 fields values are updated */ + + + /* Get CSAR field ***************************************************************************************************/ + pNodeConfig->SrcAddress = pNode->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET]; + /************************************************************************************** CSAR field value is updated */ + + + /* Get CDAR field ***************************************************************************************************/ + pNodeConfig->DstAddress = pNode->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET]; + /************************************************************************************** CDAR field value is updated */ + +} + +/** + * @brief Check nodes base addresses compatibility. + * @param pNode1 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 1 registers configurations. + * @param pNode2 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 2 registers configurations. + * @param pNode3 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 3 registers configurations. + * @retval Return 0 when nodes addresses are compatible, 1 otherwise. + */ +static uint32_t DMA_List_CheckNodesBaseAddresses(DMA_NodeTypeDef const *const pNode1, + DMA_NodeTypeDef const *const pNode2, + DMA_NodeTypeDef const *const pNode3) +{ + uint32_t temp = (((uint32_t)pNode1 | (uint32_t)pNode2 | (uint32_t)pNode3) & DMA_CLBAR_LBA); + uint32_t ref = 0U; + + /* Check node 1 address */ + if ((uint32_t)pNode1 != 0U) + { + ref = (uint32_t)pNode1; + } + /* Check node 2 address */ + else if ((uint32_t)pNode2 != 0U) + { + ref = (uint32_t)pNode2; + } + /* Check node 3 address */ + else if ((uint32_t)pNode3 != 0U) + { + ref = (uint32_t)pNode3; + } + else + { + /* Prevent MISRA-C2012-Rule-15.7 */ + } + + /* Check addresses compatibility */ + if (temp != ((uint32_t)ref & DMA_CLBAR_LBA)) + { + return 1U; + } + + return 0U; +} + +/** + * @brief Check nodes types compatibility. + * @param pNode1 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 1 registers configurations. + * @param pNode2 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 2 registers configurations. + * @param pNode3 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 3 registers configurations. + * @retval Return 0 when nodes types are compatible, otherwise nodes types are not compatible. + */ +static uint32_t DMA_List_CheckNodesTypes(DMA_NodeTypeDef const *const pNode1, + DMA_NodeTypeDef const *const pNode2, + DMA_NodeTypeDef const *const pNode3) +{ + uint32_t ref = 0U; + + /* Check node 1 parameter */ + if (pNode1 != NULL) + { + ref = pNode1->NodeInfo & NODE_TYPE_MASK; + } + /* Check node 2 parameter */ + else if (pNode2 != NULL) + { + ref = pNode2->NodeInfo & NODE_TYPE_MASK; + } + /* Check node 3 parameter */ + else if (pNode3 != NULL) + { + ref = pNode3->NodeInfo & NODE_TYPE_MASK; + } + else + { + /* Prevent MISRA-C2012-Rule-15.7 */ + } + + /* Check node 2 parameter */ + if (pNode2 != NULL) + { + /* Check node type compatibility */ + if (ref != (pNode2->NodeInfo & NODE_TYPE_MASK)) + { + return 2U; + } + } + + /* Check node 3 parameter */ + if (pNode3 != NULL) + { + /* Check node type compatibility */ + if (ref != (pNode3->NodeInfo & NODE_TYPE_MASK)) + { + return 3U; + } + } + + return 0U; +} + +/** + * @brief Check nodes types compatibility. + * @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers + * configurations. + * @param cllr_mask : Pointer to CLLR register mask value. + * @param cllr_offset : Pointer to CLLR register offset value. + * @retval None. + */ +static void DMA_List_GetCLLRNodeInfo(DMA_NodeTypeDef const *const pNode, + uint32_t *const cllr_mask, + uint32_t *const cllr_offset) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(pNode); + + /* Update CLLR register mask value */ + if (cllr_mask != NULL) + { + *cllr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_ULL; + } + + /* Update CLLR register offset */ + if (cllr_offset != NULL) + { + *cllr_offset = NODE_CLLR_LINEAR_DEFAULT_OFFSET; + } +} + +/** + * @brief Find node in queue. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers configurations. + * @param NodeInfo : Pointer to a DMA_NodeInQInfoTypeDef structure that contains node linked to queue information. + * @retval Return 0 when node is found in selected queue, otherwise node is not found. + */ +static uint32_t DMA_List_FindNode(DMA_QListTypeDef const *const pQList, + DMA_NodeTypeDef const *const pNode, + DMA_NodeInQInfoTypeDef *const NodeInfo) +{ + uint32_t node_idx = 0U; + uint32_t currentnode_address = 0U; + uint32_t previousnode_address = 0U; + uint32_t cllr_offset = NodeInfo->cllr_offset; + + /* Find last node in queue */ + if (pNode == NULL) + { + /* Check that previous node is linked to the selected queue */ + while (node_idx < pQList->NodeNumber) + { + /* Get head node address */ + if (node_idx == 0U) + { + currentnode_address = (uint32_t)pQList->Head & DMA_CLLR_LA; + } + /* Calculate nodes addresses */ + else + { + previousnode_address = currentnode_address; + currentnode_address = + ((DMA_NodeTypeDef *)(currentnode_address + + ((uint32_t)pQList->Head & DMA_CLBAR_LBA)))->LinkRegisters[cllr_offset] & DMA_CLLR_LA; + } + + /* Increment node index */ + node_idx++; + } + } + /* Find selected node node in queue */ + else + { + /* Check that previous node is linked to the selected queue */ + while ((node_idx < pQList->NodeNumber) && (currentnode_address != ((uint32_t)pNode & DMA_CLLR_LA))) + { + /* Get head node address */ + if (node_idx == 0U) + { + currentnode_address = (uint32_t)pQList->Head & DMA_CLLR_LA; + } + /* Calculate nodes addresses */ + else + { + previousnode_address = currentnode_address; + currentnode_address = + ((DMA_NodeTypeDef *)(currentnode_address + + ((uint32_t)pQList->Head & DMA_CLBAR_LBA)))->LinkRegisters[cllr_offset] & DMA_CLLR_LA; + } + + /* Increment node index */ + node_idx++; + } + } + + /* Check stored address */ + if (pNode != NULL) + { + if (currentnode_address != ((uint32_t)pNode & DMA_CLLR_LA)) + { + return 1U; + } + } + + /* Update current node position */ + NodeInfo->currentnode_pos = node_idx; + + /* Update previous node address */ + NodeInfo->previousnode_addr = previousnode_address | ((uint32_t)pQList->Head & DMA_CLBAR_LBA); + + /* Update current node address */ + NodeInfo->currentnode_addr = currentnode_address | ((uint32_t)pQList->Head & DMA_CLBAR_LBA); + + /* Update next node address */ + if (((DMA_NodeTypeDef *)NodeInfo->currentnode_addr)->LinkRegisters[cllr_offset] != 0U) + { + NodeInfo->nextnode_addr = (((DMA_NodeTypeDef *)NodeInfo->currentnode_addr)->LinkRegisters[cllr_offset] & + DMA_CLLR_LA) | ((uint32_t)pQList->Head & DMA_CLBAR_LBA); + } + + return 0U; +} + +/** + * @brief Reset queue nodes. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @param NodeInfo : Pointer to a DMA_NodeInQInfoTypeDef structure that contains node linked to queue information. + * @retval None. + */ +static void DMA_List_ResetQueueNodes(DMA_QListTypeDef const *const pQList, + DMA_NodeInQInfoTypeDef const *const NodeInfo) +{ + uint32_t node_idx = 0U; + uint32_t currentnode_address = 0U; + uint32_t previousnode_address; + uint32_t cllr_offset = NodeInfo->cllr_offset; + + /* Check that previous node is linked to the selected queue */ + while (node_idx < pQList->NodeNumber) + { + /* Get head node address */ + if (node_idx == 0U) + { + previousnode_address = (uint32_t)pQList->Head & DMA_CLLR_LA; + currentnode_address = (pQList->Head->LinkRegisters[cllr_offset] & DMA_CLLR_LA); + } + /* Calculate nodes addresses */ + else + { + previousnode_address = currentnode_address; + currentnode_address = + ((DMA_NodeTypeDef *)(currentnode_address + + ((uint32_t)pQList->Head & DMA_CLBAR_LBA)))->LinkRegisters[cllr_offset] & DMA_CLLR_LA; + } + + /* Reset node */ + ((DMA_NodeTypeDef *)(previousnode_address + + ((uint32_t)pQList->Head & DMA_CLBAR_LBA)))->LinkRegisters[cllr_offset] = 0U; + + /* Increment node index */ + node_idx++; + } +} + +/** + * @brief Fill source node registers values by destination nodes registers values. + * @param pSrcNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list source node registers + * configurations. + * @param pDestNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list destination node registers + * configurations. + * @retval None. + */ +static void DMA_List_FillNode(DMA_NodeTypeDef const *const pSrcNode, + DMA_NodeTypeDef *const pDestNode) +{ + /* Repeat for all register nodes */ + for (uint32_t reg_idx = 0U; reg_idx < NODE_MAXIMUM_SIZE; reg_idx++) + { + pDestNode->LinkRegisters[reg_idx] = pSrcNode->LinkRegisters[reg_idx]; + } + + /* Fill node information */ + pDestNode->NodeInfo = pSrcNode->NodeInfo; +} + +/** + * @brief Convert node to dynamic. + * @param ContextNodeAddr : The context node address. + * @param CurrentNodeAddr : The current node address to be converted. + * @param RegisterNumber : The register number to be converted. + * @retval None. + */ +static void DMA_List_ConvertNodeToDynamic(uint32_t ContextNodeAddr, + uint32_t CurrentNodeAddr, + uint32_t RegisterNumber) +{ + uint32_t currentnode_reg_counter = 0U; + uint32_t contextnode_reg_counter = 0U; + uint32_t cllr_idx = RegisterNumber - 1U; + DMA_NodeTypeDef *context_node = (DMA_NodeTypeDef *)ContextNodeAddr; + DMA_NodeTypeDef *current_node = (DMA_NodeTypeDef *)CurrentNodeAddr; + uint32_t update_link[NODE_MAXIMUM_SIZE] = {DMA_CLLR_UT1, DMA_CLLR_UT2, DMA_CLLR_UB1, DMA_CLLR_USA, + DMA_CLLR_UDA, DMA_CLLR_ULL + }; + + /* Update ULL position according to register number */ + update_link[cllr_idx] = update_link[NODE_MAXIMUM_SIZE - 1U]; + + /* Repeat for all node registers */ + while (contextnode_reg_counter != RegisterNumber) + { + /* Check if register values are equal (exception for CSAR, CDAR and CLLR registers) */ + if ((context_node->LinkRegisters[contextnode_reg_counter] == + current_node->LinkRegisters[currentnode_reg_counter]) && + (contextnode_reg_counter != NODE_CSAR_DEFAULT_OFFSET) && + (contextnode_reg_counter != NODE_CDAR_DEFAULT_OFFSET) && + (contextnode_reg_counter != (RegisterNumber - 1U))) + { + /* Format the node according to unused registers */ + DMA_List_FormatNode(current_node, currentnode_reg_counter, RegisterNumber, NODE_DYNAMIC_FORMAT); + + /* Update CLLR index */ + cllr_idx --; + + /* Update CLLR fields */ + current_node->LinkRegisters[cllr_idx] &= ~update_link[contextnode_reg_counter]; + } + else + { + /* Update context node register fields with new values */ + context_node->LinkRegisters[contextnode_reg_counter] = current_node->LinkRegisters[currentnode_reg_counter]; + + /* Update CLLR fields */ + current_node->LinkRegisters[cllr_idx] |= update_link[contextnode_reg_counter]; + + /* Increment current node number register counter */ + currentnode_reg_counter++; + } + + /* Increment context node number register counter */ + contextnode_reg_counter++; + } + + /* Update node information */ + MODIFY_REG(current_node->NodeInfo, NODE_CLLR_IDX, ((currentnode_reg_counter - 1U) << NODE_CLLR_IDX_POS)); + + /* Clear unused node fields */ + DMA_List_ClearUnusedFields(current_node, currentnode_reg_counter); +} + +/** + * @brief Convert node to static. + * @param ContextNodeAddr : The context node address. + * @param CurrentNodeAddr : The current node address to be converted. + * @param RegisterNumber : The register number to be converted. + * @retval None. + */ +static void DMA_List_ConvertNodeToStatic(uint32_t ContextNodeAddr, + uint32_t CurrentNodeAddr, + uint32_t RegisterNumber) +{ + uint32_t contextnode_reg_counter = 0U; + uint32_t cllr_idx; + uint32_t cllr_mask; + DMA_NodeTypeDef *context_node = (DMA_NodeTypeDef *)ContextNodeAddr; + DMA_NodeTypeDef *current_node = (DMA_NodeTypeDef *)CurrentNodeAddr; + uint32_t update_link[NODE_MAXIMUM_SIZE] = {DMA_CLLR_UT1, DMA_CLLR_UT2, DMA_CLLR_UB1, DMA_CLLR_USA, + DMA_CLLR_UDA, DMA_CLLR_ULL + }; + + /* Update ULL position according to register number */ + update_link[RegisterNumber - 1U] = update_link[NODE_MAXIMUM_SIZE - 1U]; + + /* Get context node CLLR information */ + cllr_idx = (context_node->NodeInfo & NODE_CLLR_IDX) >> NODE_CLLR_IDX_POS; + cllr_mask = context_node->LinkRegisters[cllr_idx]; + + /* Repeat for all node registers */ + while (contextnode_reg_counter != RegisterNumber) + { + /* Check if node field is dynamic */ + if ((cllr_mask & update_link[contextnode_reg_counter]) == 0U) + { + /* Format the node according to unused registers */ + DMA_List_FormatNode(current_node, contextnode_reg_counter, RegisterNumber, NODE_STATIC_FORMAT); + + /* Update node field */ + current_node->LinkRegisters[contextnode_reg_counter] = context_node->LinkRegisters[contextnode_reg_counter]; + } + + /* Increment context node number register counter */ + contextnode_reg_counter++; + } + + /* Update node information */ + MODIFY_REG(current_node->NodeInfo, NODE_CLLR_IDX, ((RegisterNumber - 1U) << NODE_CLLR_IDX_POS)); +} + +/** + * @brief Format the node according to unused registers. + * @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers + * configurations. + * @param RegisterIdx : The first register index to be formatted. + * @param RegisterNumber : The number of node registers. + * @param Format : The format type. + * @retval None. + */ +static void DMA_List_FormatNode(DMA_NodeTypeDef *const pNode, + uint32_t RegisterIdx, + uint32_t RegisterNumber, + uint32_t Format) +{ + if (Format == NODE_DYNAMIC_FORMAT) + { + /* Repeat for all registers to be formatted */ + for (uint32_t reg_idx = RegisterIdx; reg_idx < (RegisterNumber - 1U); reg_idx++) + { + pNode->LinkRegisters[reg_idx] = pNode->LinkRegisters[reg_idx + 1U]; + } + } + else + { + /* Repeat for all registers to be formatted */ + for (uint32_t reg_idx = (RegisterNumber - 2U); reg_idx > RegisterIdx; reg_idx--) + { + pNode->LinkRegisters[reg_idx] = pNode->LinkRegisters[reg_idx - 1U]; + } + } +} + +/** + * @brief Clear unused register fields. + * @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers + * configurations. + * @param FirstUnusedField : The first unused field to be cleared. + * @retval None. + */ +static void DMA_List_ClearUnusedFields(DMA_NodeTypeDef *const pNode, + uint32_t FirstUnusedField) +{ + /* Repeat for all unused fields */ + for (uint32_t reg_idx = FirstUnusedField; reg_idx < NODE_MAXIMUM_SIZE; reg_idx++) + { + pNode->LinkRegisters[reg_idx] = 0U; + } +} + +/** + * @brief Update CLLR for all dynamic queue nodes. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @param LastNode_IsCircular : The first circular node is the last queue node or not. + * @retval None. + */ +static void DMA_List_UpdateDynamicQueueNodesCLLR(DMA_QListTypeDef const *const pQList, + uint32_t LastNode_IsCircular) +{ + uint32_t previous_cllr_offset; + uint32_t current_cllr_offset = 0U; + uint32_t previousnode_addr; + uint32_t currentnode_addr = (uint32_t)pQList->Head; + uint32_t cllr_mask; + uint32_t node_idx = 0U; + + /* Repeat for all register nodes */ + while (node_idx < pQList->NodeNumber) + { + /* Get head node address */ + if (node_idx == 0U) + { + /* Get current node information */ + current_cllr_offset = (((DMA_NodeTypeDef *)currentnode_addr)->NodeInfo & NODE_CLLR_IDX) >> NODE_CLLR_IDX_POS; + } + /* Calculate nodes addresses */ + else + { + /* Get previous node information */ + previousnode_addr = currentnode_addr; + previous_cllr_offset = current_cllr_offset; + + /* Get current node information */ + currentnode_addr = (((DMA_NodeTypeDef *)(previousnode_addr))->LinkRegisters[previous_cllr_offset] & DMA_CLLR_LA) + + ((uint32_t)pQList->Head & DMA_CLBAR_LBA); + current_cllr_offset = (((DMA_NodeTypeDef *)currentnode_addr)->NodeInfo & NODE_CLLR_IDX) >> NODE_CLLR_IDX_POS; + + /* Calculate CLLR register value to be updated */ + cllr_mask = (((DMA_NodeTypeDef *)currentnode_addr)->LinkRegisters[current_cllr_offset] & ~DMA_CLLR_LA) | + (((DMA_NodeTypeDef *)(previousnode_addr))->LinkRegisters[previous_cllr_offset] & DMA_CLLR_LA); + + /* Set new CLLR value to previous node */ + ((DMA_NodeTypeDef *)(previousnode_addr))->LinkRegisters[previous_cllr_offset] = cllr_mask; + } + + /* Increment node index */ + node_idx++; + } + + /* Check queue circularity */ + if (pQList->FirstCircularNode != 0U) + { + /* First circular queue is not last queue node */ + if (LastNode_IsCircular == 0U) + { + /* Get CLLR node information */ + DMA_List_GetCLLRNodeInfo(((DMA_NodeTypeDef *)currentnode_addr), &cllr_mask, NULL); + + /* Update CLLR register for last circular node */ + ((DMA_NodeTypeDef *)currentnode_addr)->LinkRegisters[current_cllr_offset] = + ((uint32_t)pQList->Head & DMA_CLLR_LA) | cllr_mask; + } + /* First circular queue is last queue node */ + else + { + /* Disable CLLR updating */ + ((DMA_NodeTypeDef *)currentnode_addr)->LinkRegisters[current_cllr_offset] &= ~DMA_CLLR_ULL; + } + } + else + { + /* Clear CLLR register for last node */ + ((DMA_NodeTypeDef *)currentnode_addr)->LinkRegisters[current_cllr_offset] = 0U; + } +} + +/** + * @brief Update CLLR for all static queue nodes. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @param operation : The operation type. + * @retval None. + */ +static void DMA_List_UpdateStaticQueueNodesCLLR(DMA_QListTypeDef const *const pQList, + uint32_t operation) +{ + uint32_t currentnode_addr = (uint32_t)pQList->Head; + uint32_t current_cllr_offset = ((uint32_t)pQList->Head->NodeInfo & NODE_CLLR_IDX) >> NODE_CLLR_IDX_POS; + uint32_t cllr_default_offset; + uint32_t cllr_default_mask; + uint32_t cllr_mask; + uint32_t node_idx = 0U; + + /* Get CLLR node information */ + DMA_List_GetCLLRNodeInfo(pQList->Head, &cllr_default_mask, &cllr_default_offset); + + /* Repeat for all register nodes (Bypass last queue node) */ + while (node_idx < pQList->NodeNumber) + { + if (operation == UPDATE_CLLR_POSITION) + { + /* Get CLLR value */ + cllr_mask = ((DMA_NodeTypeDef *)currentnode_addr)->LinkRegisters[current_cllr_offset]; + } + else + { + /* Calculate CLLR value */ + cllr_mask = (((DMA_NodeTypeDef *)currentnode_addr)->LinkRegisters[current_cllr_offset] & DMA_CLLR_LA) | + cllr_default_mask; + } + + /* Set new CLLR value to default position */ + if ((node_idx == (pQList->NodeNumber - 1U)) && (pQList->FirstCircularNode == NULL)) + { + ((DMA_NodeTypeDef *)(currentnode_addr))->LinkRegisters[cllr_default_offset] = 0U; + } + else + { + ((DMA_NodeTypeDef *)(currentnode_addr))->LinkRegisters[cllr_default_offset] = cllr_mask; + } + + /* Update current node address with next node address */ + currentnode_addr = (currentnode_addr & DMA_CLBAR_LBA) | (cllr_mask & DMA_CLLR_LA); + + /* Update current CLLR offset with next CLLR offset */ + current_cllr_offset = (((DMA_NodeTypeDef *)currentnode_addr)->NodeInfo & NODE_CLLR_IDX) >> NODE_CLLR_IDX_POS; + + /* Increment node index */ + node_idx++; + } +} + +/** + * @brief Clean linked-list queue variable. + * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. + * @retval None. + */ +static void DMA_List_CleanQueue(DMA_QListTypeDef *const pQList) +{ + /* Clear head node */ + pQList->Head = NULL; + + /* Clear first circular queue node */ + pQList->FirstCircularNode = NULL; + + /* Reset node number */ + pQList->NodeNumber = 0U; + + /* Reset queue state */ + pQList->State = HAL_DMA_QUEUE_STATE_RESET; + + /* Reset queue error code */ + pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; + + /* Reset queue type */ + pQList->Type = QUEUE_TYPE_STATIC; +} +/** + * @} + */ + +#endif /* HAL_DMA_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_exti.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_exti.c new file mode 100644 index 0000000000..f53e24fbdb --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_exti.c @@ -0,0 +1,856 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_exti.c + * @author MCD Application Team + * @brief EXTI HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the General Purpose Input/Output (EXTI) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### EXTI Peripheral features ##### + ============================================================================== + [..] + (+) Each Exti line can be configured within this driver. + + (+) Exti line can be configured in 3 different modes + (++) Interrupt + (++) Event + (++) Both of them + + (+) Configurable Exti lines can be configured with 3 different triggers + (++) Rising + (++) Falling + (++) Both of them + + (+) When set in interrupt mode, configurable Exti lines have two diffenrents + interrupt pending registers which allow to distinguish which transition + occurs: + (++) Rising edge pending interrupt + (++) Falling + + (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can + be selected through multiplexer. + + ##### How to use this driver ##### + ============================================================================== + [..] + + (#) Configure the EXTI line using HAL_EXTI_SetConfigLine(). + (++) Choose the interrupt line number by setting "Line" member from + EXTI_ConfigTypeDef structure. + (++) Configure the interrupt and/or event mode using "Mode" member from + EXTI_ConfigTypeDef structure. + (++) For configurable lines, configure rising and/or falling trigger + "Trigger" member from EXTI_ConfigTypeDef structure. + (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel" + member from GPIO_InitTypeDef structure. + + (#) Get current Exti configuration of a dedicated line using + HAL_EXTI_GetConfigLine(). + (++) Provide exiting handle as parameter. + (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter. + + (#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine(). + (++) Provide exiting handle as parameter. + + (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback(). + (++) Provide exiting handle as first parameter. + (++) Provide which callback will be registered using one value from + EXTI_CallbackIDTypeDef. + (++) Provide callback function pointer. + + (#) Get interrupt pending bit using HAL_EXTI_GetPending(). + + (#) Clear interrupt pending bit using HAL_EXTI_GetPending(). + + (#) Generate software interrupt using HAL_EXTI_GenerateSWI(). + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @addtogroup EXTI + * @{ + */ + +#ifdef HAL_EXTI_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines ------------------------------------------------------------*/ +/** @defgroup EXTI_Private_Constants EXTI Private Constants + * @{ + */ +#define EXTI_MODE_OFFSET 0x04U /* byte offset between IMR/EMR registers */ +#define EXTI_CONFIG_OFFSET 0x08U /* byte offset between Rising/Falling configuration registers */ +#define EXTI_PRIVCFGR_OFFSET 0x04U /* byte offset between PRIVCFGR1/PRIVCFGR2 registers */ +#define EXTI_SECCFGR_OFFSET 0x04U /* byte offset between SECCFGR1/SECCFGR2 registers */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup EXTI_Exported_Functions + * @{ + */ + +/** @addtogroup EXTI_Exported_Functions_Group1 + * @brief Configuration functions + * +@verbatim + =============================================================================== + ##### Configuration functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Set configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @param pExtiConfig Pointer on EXTI configuration to be set. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) +{ + __IO uint32_t *regaddr; + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + uint32_t offset; + + /* Check null pointer */ + if ((hexti == NULL) || (pExtiConfig == NULL)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_EXTI_LINE(pExtiConfig->Line)); + assert_param(IS_EXTI_MODE(pExtiConfig->Mode)); + + /* Assign line number to handle */ + hexti->Line = pExtiConfig->Line; + + /* compute line register offset and line mask */ + offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + linepos = (pExtiConfig->Line & EXTI_PIN_MASK); + maskline = (1UL << linepos); + + /* Configure triggers for configurable lines */ + if ((pExtiConfig->Line & EXTI_CONFIG) != 0U) + { + assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger)); + + /* Configure rising trigger */ + regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0U) + { + regval |= maskline; + } + else + { + regval &= ~maskline; + } + + /* Store rising trigger mode */ + *regaddr = regval; + + /* Configure falling trigger */ + regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0U) + { + regval |= maskline; + } + else + { + regval &= ~maskline; + } + + /* Store falling trigger mode */ + *regaddr = regval; + + /* Configure gpio port selection in case of gpio exti line */ + if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel)); + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = EXTI->EXTICR[(linepos >> 2U) & 0x03UL]; + regval &= ~(EXTI_EXTICR1_EXTI0 << (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03U))); + regval |= (pExtiConfig->GPIOSel << (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03U))); + EXTI->EXTICR[(linepos >> 2U) & 0x03UL] = regval; + } + } + + /* Configure interrupt mode : read current mode */ + regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0U) + { + regval |= maskline; + } + else + { + regval &= ~maskline; + } + + /* Store interrupt mode */ + *regaddr = regval; + + /* Configure event mode : read current mode */ + regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0U) + { + regval |= maskline; + } + else + { + regval &= ~maskline; + } + + /* Store event mode */ + *regaddr = regval; + + return HAL_OK; +} + + +/** + * @brief Get configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @param pExtiConfig Pointer on structure to store Exti configuration. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) +{ + const __IO uint32_t *regaddr; + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + uint32_t offset; + + /* Check null pointer */ + if ((hexti == NULL) || (pExtiConfig == NULL)) + { + return HAL_ERROR; + } + + /* Check the parameter */ + assert_param(IS_EXTI_LINE(hexti->Line)); + + /* Store handle line number to configiguration structure */ + pExtiConfig->Line = hexti->Line; + + /* compute line register offset and line mask */ + offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + linepos = (pExtiConfig->Line & EXTI_PIN_MASK); + maskline = (1UL << linepos); + + /* 1] Get core mode : interrupt */ + regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset)); + regval = *regaddr; + + /* Check if selected line is enable */ + if ((regval & maskline) != 0U) + { + pExtiConfig->Mode = EXTI_MODE_INTERRUPT; + } + else + { + pExtiConfig->Mode = EXTI_MODE_NONE; + } + + /* Get event mode */ + regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset)); + regval = *regaddr; + + /* Check if selected line is enable */ + if ((regval & maskline) != 0U) + { + pExtiConfig->Mode |= EXTI_MODE_EVENT; + } + + /* 2] Get trigger for configurable lines : rising */ + if ((pExtiConfig->Line & EXTI_CONFIG) != 0U) + { + regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = *regaddr; + + /* Check if configuration of selected line is enable */ + if ((regval & maskline) != 0U) + { + pExtiConfig->Trigger = EXTI_TRIGGER_RISING; + } + else + { + pExtiConfig->Trigger = EXTI_TRIGGER_NONE; + } + + /* Get falling configuration */ + regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = *regaddr; + + /* Check if configuration of selected line is enable */ + if ((regval & maskline) != 0U) + { + pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING; + } + + /* Get Gpio port selection for gpio lines */ + if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = EXTI->EXTICR[(linepos >> 2U) & 0x03UL]; + pExtiConfig->GPIOSel = (regval >> (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03U))) & EXTI_EXTICR1_EXTI1_Pos; + } + else + { + pExtiConfig->GPIOSel = 0U; + } + } + else + { + pExtiConfig->Trigger = EXTI_TRIGGER_NONE; + pExtiConfig->GPIOSel = 0U; + } + + return HAL_OK; +} + + +/** + * @brief Clear whole configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(const EXTI_HandleTypeDef *hexti) +{ + __IO uint32_t *regaddr; + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + uint32_t offset; + + /* Check null pointer */ + if (hexti == NULL) + { + return HAL_ERROR; + } + + /* Check the parameter */ + assert_param(IS_EXTI_LINE(hexti->Line)); + + /* compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + linepos = (hexti->Line & EXTI_PIN_MASK); + maskline = (1UL << linepos); + + /* 1] Clear interrupt mode */ + regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset)); + regval = (*regaddr & ~maskline); + *regaddr = regval; + + /* 2] Clear event mode */ + regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset)); + regval = (*regaddr & ~maskline); + *regaddr = regval; + + /* 3] Clear triggers in case of configurable lines */ + if ((hexti->Line & EXTI_CONFIG) != 0U) + { + regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = (*regaddr & ~maskline); + *regaddr = regval; + + regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = (*regaddr & ~maskline); + *regaddr = regval; + + /* Get Gpio port selection for gpio lines */ + if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = EXTI->EXTICR[(linepos >> 2U) & 0x03UL]; + regval &= ~(EXTI_EXTICR1_EXTI0 << (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03U))); + EXTI->EXTICR[(linepos >> 2U) & 0x03UL] = regval; + } + } + + return HAL_OK; +} + + +/** + * @brief Register callback for a dedicaated Exti line. + * @param hexti Exti handle. + * @param CallbackID User callback identifier. + * This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values. + * @param pPendingCbfn function pointer to be stored as callback. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)) +{ + HAL_StatusTypeDef status = HAL_OK; + + switch (CallbackID) + { + case HAL_EXTI_COMMON_CB_ID: + hexti->RisingCallback = pPendingCbfn; + hexti->FallingCallback = pPendingCbfn; + break; + + case HAL_EXTI_RISING_CB_ID: + hexti->RisingCallback = pPendingCbfn; + break; + + case HAL_EXTI_FALLING_CB_ID: + hexti->FallingCallback = pPendingCbfn; + break; + + default: + status = HAL_ERROR; + break; + } + + return status; +} + + +/** + * @brief Store line number as handle private field. + * @param hexti Exti handle. + * @param ExtiLine Exti line number. + * This parameter can be from 0 to @ref EXTI_LINE_NB. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(ExtiLine)); + + /* Check null pointer */ + if (hexti == NULL) + { + return HAL_ERROR; + } + else + { + /* Store line number as handle private field */ + hexti->Line = ExtiLine; + + return HAL_OK; + } +} + +/** + * @} + */ + +/** @addtogroup EXTI_Exported_Functions_Group2 + * @brief EXTI IO functions. + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Handle EXTI interrupt request. + * @param hexti Exti handle. + * @retval none. + */ +void HAL_EXTI_IRQHandler(const EXTI_HandleTypeDef *hexti) +{ + __IO uint32_t *regaddr; + uint32_t regval; + uint32_t maskline; + uint32_t offset; + + /* Compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + maskline = (1UL << (hexti->Line & EXTI_PIN_MASK)); + + /* Get rising edge pending bit */ + regaddr = (__IO uint32_t *)(&EXTI->RPR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = (*regaddr & maskline); + + if (regval != 0U) + { + /* Clear pending bit */ + *regaddr = maskline; + + /* Call rising callback */ + if (hexti->RisingCallback != NULL) + { + hexti->RisingCallback(); + } + } + + /* Get falling edge pending bit */ + regaddr = (__IO uint32_t *)(&EXTI->FPR1 + (EXTI_CONFIG_OFFSET * offset)); + regval = (*regaddr & maskline); + + if (regval != 0U) + { + /* Clear pending bit */ + *regaddr = maskline; + + /* Call rising callback */ + if (hexti->FallingCallback != NULL) + { + hexti->FallingCallback(); + } + } +} + + +/** + * @brief Get interrupt pending bit of a dedicated line. + * @param hexti Exti handle. + * @param Edge Specify which pending edge as to be checked. + * This parameter can be one of the following values: + * @arg @ref EXTI_TRIGGER_RISING + * @arg @ref EXTI_TRIGGER_FALLING + * @retval 1 if interrupt is pending else 0. + */ +uint32_t HAL_EXTI_GetPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge) +{ + const __IO uint32_t *regaddr; + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + uint32_t offset; + + /* Check the parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + assert_param(IS_EXTI_PENDING_EDGE(Edge)); + + /* compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + linepos = (hexti->Line & EXTI_PIN_MASK); + maskline = (1UL << linepos); + + if (Edge != EXTI_TRIGGER_RISING) + { + /* Get falling edge pending bit */ + regaddr = (__IO uint32_t *)(&EXTI->FPR1 + (EXTI_CONFIG_OFFSET * offset)); + } + else + { + /* Get rising edge pending bit */ + regaddr = (__IO uint32_t *)(&EXTI->RPR1 + (EXTI_CONFIG_OFFSET * offset)); + } + + /* return 1 if bit is set else 0 */ + regval = ((*regaddr & maskline) >> linepos); + return regval; +} + + +/** + * @brief Clear interrupt pending bit of a dedicated line. + * @param hexti Exti handle. + * @param Edge Specify which pending edge as to be clear. + * This parameter can be one of the following values: + * @arg @ref EXTI_TRIGGER_RISING + * @arg @ref EXTI_TRIGGER_FALLING + * @retval None. + */ +void HAL_EXTI_ClearPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge) +{ + __IO uint32_t *regaddr; + uint32_t maskline; + uint32_t offset; + + /* Check the parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + assert_param(IS_EXTI_PENDING_EDGE(Edge)); + + /* compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + maskline = (1UL << (hexti->Line & EXTI_PIN_MASK)); + + if (Edge != EXTI_TRIGGER_RISING) + { + /* Get falling edge pending register address */ + regaddr = (__IO uint32_t *)(&EXTI->FPR1 + (EXTI_CONFIG_OFFSET * offset)); + } + else + { + /* Get falling edge pending register address */ + regaddr = (__IO uint32_t *)(&EXTI->RPR1 + (EXTI_CONFIG_OFFSET * offset)); + } + + /* Clear Pending bit */ + *regaddr = maskline; +} + + +/** + * @brief Generate a software interrupt for a dedicated line. + * @param hexti Exti handle. + * @retval None. + */ +void HAL_EXTI_GenerateSWI(const EXTI_HandleTypeDef *hexti) +{ + __IO uint32_t *regaddr; + uint32_t maskline; + uint32_t offset; + + /* Check the parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + + /* compute line register offset and line mask */ + offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + maskline = (1UL << (hexti->Line & EXTI_PIN_MASK)); + + regaddr = (__IO uint32_t *)(&EXTI->SWIER1 + (EXTI_CONFIG_OFFSET * offset)); + *regaddr = maskline; +} + + +/** + * @} + */ + +/** @defgroup EXTI_Exported_Functions_Group3 EXTI line attributes management functions + * @brief EXTI attributes management functions. + * +@verbatim + =============================================================================== + ##### EXTI attributes functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +#if defined(EXTI_SECCFGR1_SEC0) +/** + * @brief Configure the EXTI line attribute(s). + * @note Available attributes are to secure EXTI line and set EXT line as privileged. + * Default state is not secure and unprivileged access allowed. + * @note Secure and non-secure attributes can only be set from the secure + * state when the system implements the security (TZEN=1). + * @note Security and privilege attributes can be set independently. + * @param ExtiLine Exti line number. + * This parameter can be from 0 to @ref EXTI_LINE_NB. + * @param LineAttributes can be one or a combination of the following values: + * @arg @ref EXTI_LINE_PRIV Privileged-only access + * @arg @ref EXTI_LINE_NPRIV Privileged/Non-privileged access + * @arg @ref EXTI_LINE_SEC Secure-only access + * @arg @ref EXTI_LINE_NSEC Secure/Non-secure access + * @retval None + */ +void HAL_EXTI_ConfigLineAttributes(uint32_t ExtiLine, uint32_t LineAttributes) +{ + __IO uint32_t *regaddr; + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + uint32_t offset; + + /* Check the parameters */ + assert_param(IS_EXTI_LINE(ExtiLine)); + assert_param(IS_EXTI_LINE_ATTRIBUTES(LineAttributes)); + + /* compute line register offset and line mask */ + offset = ((ExtiLine & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + linepos = (ExtiLine & EXTI_PIN_MASK); + maskline = (1UL << linepos); + + /* Configure privilege or non-privilege attributes */ + regaddr = (__IO uint32_t *)(&EXTI->PRIVCFGR1 + (EXTI_PRIVCFGR_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((LineAttributes & EXTI_LINE_PRIV) == EXTI_LINE_PRIV) + { + regval |= maskline; + } + else if ((LineAttributes & EXTI_LINE_NPRIV) == EXTI_LINE_NPRIV) + { + regval &= ~maskline; + } + else + { + /* do nothing */ + } + + /* Store privilege or non-privilege attribute */ + *regaddr = regval; + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + + /* Configure secure or non-secure attributes */ + regaddr = (__IO uint32_t *)(&EXTI->SECCFGR1 + (EXTI_SECCFGR_OFFSET * offset)); + regval = *regaddr; + + /* Mask or set line */ + if ((LineAttributes & EXTI_LINE_SEC) == EXTI_LINE_SEC) + { + regval |= maskline; + } + else if ((LineAttributes & EXTI_LINE_NSEC) == EXTI_LINE_NSEC) + { + regval &= ~maskline; + } + else + { + /* do nothing */ + } + + /* Store secure or non-secure attribute */ + *regaddr = regval; + +#endif /* __ARM_FEATURE_CMSE */ +} + +/** + * @brief Get the EXTI line attribute(s). + * @note Secure and non-secure attributes are only available from secure state + * when the system implements the security (TZEN=1) + * @param ExtiLine Exti line number. + * This parameter can be from 0 to @ref EXTI_LINE_NB. + * @param pLineAttributes: pointer to return line attributes. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_GetConfigLineAttributes(uint32_t ExtiLine, uint32_t *pLineAttributes) +{ + const __IO uint32_t *regaddr; + uint32_t linepos; + uint32_t maskline; + uint32_t offset; + uint32_t attributes; + + /* Check null pointer */ + if (pLineAttributes == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_EXTI_LINE(ExtiLine)); + + /* Compute line register offset and line mask */ + offset = ((ExtiLine & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + linepos = (ExtiLine & EXTI_PIN_MASK); + maskline = (1UL << linepos); + + /* Get privilege or non-privilege attribute */ + regaddr = (__IO uint32_t *)(&EXTI->PRIVCFGR1 + (EXTI_PRIVCFGR_OFFSET * offset)); + + if ((*regaddr & maskline) != 0U) + { + attributes = EXTI_LINE_PRIV; + } + else + { + attributes = EXTI_LINE_NPRIV; + } + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + + /* Get secure or non-secure attribute */ + regaddr = (__IO uint32_t *)(&EXTI->SECCFGR1 + (EXTI_SECCFGR_OFFSET * offset)); + + if ((*regaddr & maskline) != 0U) + { + attributes |= EXTI_LINE_SEC; + } + else + { + attributes |= EXTI_LINE_NSEC; + } + +#endif /* __ARM_FEATURE_CMSE */ + + /* return value */ + *pLineAttributes = attributes; + + return HAL_OK; +} +#endif /* #if defined(EXTI_SECCFGR1_SEC0) */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Lock the secure and privilege configuration registers. + * @retval None + */ +void HAL_EXTI_LockAttributes(void) +{ + SET_BIT(EXTI->LOCKR, EXTI_LOCKR_LOCK); +} + +/** + * @brief Return the secure and privilege configuration registers LOCK status + * @retval 1 if the secure and privilege configuration registers have been locked else 0. + */ +uint32_t HAL_EXTI_GetLockAttributes(void) +{ + return READ_BIT(EXTI->LOCKR, EXTI_LOCKR_LOCK); +} +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_EXTI_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_flash.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_flash.c new file mode 100644 index 0000000000..f709762473 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_flash.c @@ -0,0 +1,820 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_flash.c + * @author MCD Application Team + * @brief FLASH HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the internal FLASH memory: + * + Program operations functions + * + Memory Control functions + * + Peripheral Errors functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### Flash peripheral features ##### + ============================================================================== + + [..] The Flash memory interface manages CPU AHB C-Bus accesses to the Flash memory. + It implements the erase and program Flash memory operations and the read + and write protection mechanisms. + + [..] The Flash memory interface implements the TrustZone security features (TZ) supported + by ARM Cortex-M33 core (CM33). + + [..] The FLASH main features are: + (+) Flash memory read operations + (+) Flash memory program/erase operations + (+) Read / write protections + (+) Option bytes programming + (+) TrustZone aware + (+) Watermark-based area protection including the secure hide area + (+) Block-based page protection + (+) Error code correction (ECC) : Data in flash are 137-bits word + (9 bits added per quad-word) + + ##### How to use this driver ##### + ============================================================================== + [..] + This driver provides functions and macros to configure and program the FLASH + memory of all STM32WBAxx devices. + + (#) Flash Memory IO Programming functions: + (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and + HAL_FLASH_Lock() functions + (++) Program functions: quad-words and burst program (8 quad-words) + (++) There are two modes of programming: + (+++) Polling mode using HAL_FLASH_Program() function + (+++) Interrupt mode using HAL_FLASH_Program_IT() function + + (#) Interrupts and flags management functions: + (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler() + (++) Callback functions are called when the flash operations are finished : + HAL_FLASH_EndOfOperationCallback() when everything is ok, otherwise + HAL_FLASH_OperationErrorCallback() + (++) Get error flag status by calling HAL_GetError() + + (#) Option bytes management functions : + (++) Lock and Unlock the option bytes using HAL_FLASH_OB_Unlock() and + HAL_FLASH_OB_Lock() functions + (++) Launch the reload of the option bytes using HAL_FLASH_OB_Launch() function. + In this case, a reset is generated + + [..] + In addition to these functions, this driver includes a set of macros allowing + to handle the following operations: + (+) Set the latency + (+) Enable/Disable the Flash power-down during low-power run and sleep modes + (+) Enable/Disable the Flash interrupts + (+) Monitor the Flash flags status + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @defgroup FLASH FLASH + * @brief FLASH HAL module driver + * @{ + */ + +#ifdef HAL_FLASH_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/** @addtogroup FLASH_Private_Constants + * @{ + */ +#define FLASH_NB_WORDS_IN_BURST 32 +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup FLASH_Private_Variables FLASH Private Variables + * @{ + */ +/** + * @brief Variable used for Program/Erase sectors under interruption + */ +FLASH_ProcessTypeDef pFlash = {.Lock = HAL_UNLOCKED, \ + .ErrorCode = HAL_FLASH_ERROR_NONE, \ + .ProcedureOnGoing = 0U, \ + .Address = 0U, \ + .Page = 0U, \ + .NbPagesToErase = 0U + }; +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup FLASH_Private_Functions FLASH Private Functions + * @{ + */ +static void FLASH_Program_QuadWord(uint32_t Address, uint32_t DataAddress); +static void FLASH_Program_Burst(uint32_t Address, uint32_t DataAddress); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Functions FLASH Exported Functions + * @{ + */ + +/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions + * @brief Programming operation functions + * +@verbatim + =============================================================================== + ##### Programming operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the FLASH + program operations. + +@endverbatim + * @{ + */ + +/** + * @brief Program a quad-word or a burst of 8 quad-words at a specified address. + * @note Before any operation, it is possible to check there is no operation suspended + * by call HAL_FLASHEx_IsOperationSuspended() + * @param TypeProgram Indicate the way to program at a specified address + * This parameter can be a value of @ref FLASH_TYPE_PROGRAM + * @param Address Specifies the address to be programmed. + * This parameter shall be aligned to the Flash word (128 bits) + * @param DataAddress Specifies the address of data to be programmed. + * This parameter shall be 32-bit aligned + * + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint32_t DataAddress) +{ + HAL_StatusTypeDef status; + __IO uint32_t *reg_cr; + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Reset error code */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Verify that next operation can be proceed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + /* Set current operation type */ + pFlash.ProcedureOnGoing = TypeProgram; + + /* Access to SECCR1 or NSCR1 depends on operation type */ +#if defined(FLASH_SECCR1_LOCK) + reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR1) : &(FLASH_NS->NSCR1); +#else + reg_cr = &(FLASH_NS->NSCR1); +#endif /* FLASH_SECCR1_LOCK */ + + if ((TypeProgram & (~FLASH_NON_SECURE_MASK)) == FLASH_TYPEPROGRAM_QUADWORD) + { + /* Program a quad-word (128-bit) at a specified address */ + FLASH_Program_QuadWord(Address, DataAddress); + } + else + { + /* Program a burst of 8 quad-words at a specified address */ + FLASH_Program_Burst(Address, DataAddress); + } + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + /* If the program operation is completed, disable the PG (and BWR Bit in Burst programming mode) */ + CLEAR_BIT((*reg_cr), (TypeProgram & ~(FLASH_NON_SECURE_MASK))); + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + /* return status */ + return status; +} + +/** + * @brief Program a quad-word or a burst of 8 quad-words at a specified address with interrupt enabled. + * @param TypeProgram Indicate the way to program at a specified address. + * This parameter can be a value of @ref FLASH_TYPE_PROGRAM + * @param Address Specifies the address to be programmed. + * This parameter shall be aligned to the Flash word (128 bits) + * @param DataAddress specifies the address of data to be programmed. + * This parameter shall be 32-bit aligned + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint32_t DataAddress) +{ + HAL_StatusTypeDef status; + __IO uint32_t *reg_cr; + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); + assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Reset error code */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Verify that next operation can be proceed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if (status != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + } + else + { + /* Set internal variables used by the IRQ handler */ + pFlash.ProcedureOnGoing = TypeProgram; + pFlash.Address = Address; + + /* Access to SECCR1 or NSCR1 depends on operation type */ +#if defined(FLASH_SECCR1_LOCK) + reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR1) : &(FLASH_NS->NSCR1); +#else + reg_cr = &(FLASH_NS->NSCR1); +#endif /* FLASH_SECCR1_LOCK */ + + /* Enable End of Operation and Error interrupts */ + (*reg_cr) |= (FLASH_IT_EOP | FLASH_IT_OPERR); + + if ((TypeProgram & (~FLASH_NON_SECURE_MASK)) == FLASH_TYPEPROGRAM_QUADWORD) + { + /* Program a quad-word (128-bit) at a specified address */ + FLASH_Program_QuadWord(Address, DataAddress); + } + else + { + /* Program a burst of 8 quad-words at a specified address */ + FLASH_Program_Burst(Address, DataAddress); + } + } + + /* return status */ + return status; +} + +/** + * @brief Handle FLASH interrupt request. + * @retval None + */ +void HAL_FLASH_IRQHandler(void) +{ + uint32_t param = 0U; + uint32_t error; + __IO uint32_t *reg_cr; + uint32_t type; + __IO uint32_t *reg_sr; + + type = (pFlash.ProcedureOnGoing & ~(FLASH_NON_SECURE_MASK)); + /* Access to CR and SR registers depends on operation type */ +#if defined(FLASH_SECCR1_LOCK) + reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR1) : &(FLASH_NS->NSCR1); +#else + reg_cr = &(FLASH_NS->NSCR1); +#endif /* FLASH_SECCR1_LOCK */ +#if defined(FLASH_SECSR_EOP) + reg_sr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECSR) : &(FLASH_NS->NSSR); +#else + reg_sr = &(FLASH_NS->NSSR); +#endif /* FLASH_SECSR_EOP */ + + /* Save Flash errors */ + error = (*reg_sr) & FLASH_FLAG_SR_ERRORS; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + error |= (FLASH->NSSR & FLASH_FLAG_OPTWERR); +#endif /* __ARM_FEATURE_CMSE */ + + /* Set parameter of the callback */ + if (type == FLASH_TYPEERASE_PAGES) + { + param = pFlash.Page; + } + else if (type == FLASH_TYPEPROGRAM_QUADWORD) + { + param = pFlash.Address; + } + else if (type == FLASH_TYPEPROGRAM_BURST) + { + param = pFlash.Address; + } + else + { + /* Empty statement (to be compliant MISRA 15.7) */ + } + + /* Clear operation bit on the on-going procedure */ + CLEAR_BIT((*reg_cr), (type | FLASH_NSCR1_PNB)); + + /* Check FLASH operation error flags */ + if (error != 0U) + { + /* Save the error code */ + pFlash.ErrorCode |= error; + + /* Clear error programming flags */ + (*reg_sr) = error; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + if ((error & FLASH_FLAG_OPTWERR) != 0U) + { + FLASH->NSSR = FLASH_FLAG_OPTWERR; + } +#endif /* __ARM_FEATURE_CMSE */ + + /* Stop the procedure ongoing */ + pFlash.ProcedureOnGoing = 0U; + + /* FLASH error interrupt user callback */ + HAL_FLASH_OperationErrorCallback(param); + } + + /* Check FLASH End of Operation flag */ + if (((*reg_sr) & FLASH_FLAG_EOP) != 0U) + { + /* Clear FLASH End of Operation pending bit */ + (*reg_sr) = FLASH_FLAG_EOP; + + if (type == FLASH_TYPEERASE_PAGES) + { + /* Nb of pages to erase can be decreased */ + pFlash.NbPagesToErase--; + + /* Check if there are still pages to erase */ + if (pFlash.NbPagesToErase != 0U) + { + /* Increment page number */ + pFlash.Page++; + FLASH_PageErase(pFlash.Page); + } + else + { + /* No more pages to Erase */ + pFlash.ProcedureOnGoing = 0U; + param = 0xFFFFFFFFU; + } + } + else + { + /*Clear the procedure ongoing*/ + pFlash.ProcedureOnGoing = 0U; + } + + /* FLASH EOP interrupt user callback */ + HAL_FLASH_EndOfOperationCallback(param); + } + + if (pFlash.ProcedureOnGoing == 0U) + { + /* Disable End of Operation and Error interrupts */ + (*reg_cr) &= ~(FLASH_IT_EOP | FLASH_IT_OPERR); + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + } + + /* Check ECC Correction Error */ + if ((FLASH->ECCR & (FLASH_ECCR_ECCC | FLASH_ECCR_ECCIE)) == (FLASH_ECCR_ECCC | FLASH_ECCR_ECCIE)) + { + /* Call User callback */ + HAL_FLASHEx_EccCorrectionCallback(); + + /* Clear ECC correction flag in order to allow new ECC error record */ + SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCC); + } +} + +/** + * @brief FLASH end of operation interrupt callback. + * @param ReturnValue The value saved in this parameter depends on the ongoing procedure : + * @arg Mass Erase: 0 + * @arg Page Erase: Page which has been erased + * (if 0xFFFFFFFF, it means that all the selected pages have been erased) + * @arg Program: Address which was selected for data program + * @retval None + */ +__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(ReturnValue); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_FLASH_EndOfOperationCallback could be implemented in the user file + */ +} + +/** + * @brief FLASH operation error interrupt callback. + * @param ReturnValue The value saved in this parameter depends on the ongoing procedure : + * @arg Mass Erase: 0 + * @arg Page Erase: Page number which returned an error + * @arg Program: Address which was selected for data program + * @retval None + */ +__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(ReturnValue); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_FLASH_OperationErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions + * @brief Management functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the FLASH + memory operations. + +@endverbatim + * @{ + */ + +/** + * @brief Unlock the FLASH control register access. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Unlock(void) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (READ_BIT(FLASH->NSCR1, FLASH_NSCR1_LOCK) != 0U) + { + /* Authorize the FLASH Registers access */ + WRITE_REG(FLASH->NSKEYR, FLASH_KEY1); + WRITE_REG(FLASH->NSKEYR, FLASH_KEY2); + + /* verify Flash is unlocked */ + if (READ_BIT(FLASH->NSCR1, FLASH_NSCR1_LOCK) != 0U) + { + status = HAL_ERROR; + } + } + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + if (status == HAL_OK) + { + if (READ_BIT(FLASH->SECCR1, FLASH_SECCR1_LOCK) != 0U) + { + /* Authorize the FLASH Registers access */ + WRITE_REG(FLASH->SECKEYR, FLASH_KEY1); + WRITE_REG(FLASH->SECKEYR, FLASH_KEY2); + + /* verify Flash is unlocked */ + if (READ_BIT(FLASH->SECCR1, FLASH_SECCR1_LOCK) != 0U) + { + status = HAL_ERROR; + } + } + } +#endif /* __ARM_FEATURE_CMSE */ + + return status; +} + +/** + * @brief Lock the FLASH control register access. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Lock(void) +{ + HAL_StatusTypeDef status = HAL_ERROR; + + /* Set the LOCK Bit to lock the FLASH Registers access */ + SET_BIT(FLASH->NSCR1, FLASH_NSCR1_LOCK); + + /* verify Flash is locked */ + if (READ_BIT(FLASH->NSCR1, FLASH_NSCR1_LOCK) != 0U) + { + status = HAL_OK; + } + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + if (status == HAL_OK) + { + SET_BIT(FLASH->SECCR1, FLASH_SECCR1_LOCK); + + /* verify Flash is locked */ + if (READ_BIT(FLASH->SECCR1, FLASH_SECCR1_LOCK) != 0U) + { + status = HAL_OK; + } + } +#endif /* __ARM_FEATURE_CMSE */ + + return status; +} + +/** + * @brief Unlock the FLASH Option Bytes Registers access. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) +{ + if (READ_BIT(FLASH->NSCR1, FLASH_NSCR1_OPTLOCK) != 0U) + { + /* Authorizes the Option Byte register programming */ + WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1); + WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2); + + /* Verify that the Option Bytes are unlocked */ + if (READ_BIT(FLASH->NSCR1, FLASH_NSCR1_OPTLOCK) != 0U) + { + return HAL_ERROR; + } + } + + return HAL_OK; +} + +/** + * @brief Lock the FLASH Option Bytes Registers access. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) +{ + /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */ + SET_BIT(FLASH->NSCR1, FLASH_NSCR1_OPTLOCK); + + /* Verify that the Option Bytes are locked */ + if (READ_BIT(FLASH->NSCR1, FLASH_NSCR1_OPTLOCK) != 0U) + { + return HAL_OK; + } + + return HAL_ERROR; +} + +/** + * @brief Launch the option byte loading. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) +{ + /* Set the bit to force the option byte reloading */ + SET_BIT(FLASH->NSCR1, FLASH_NSCR1_OBL_LAUNCH); + + /* We should not reach here : Option byte launch generates Option byte reset + so return error */ + return HAL_ERROR; +} + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief Peripheral Errors functions + * +@verbatim + =============================================================================== + ##### Peripheral Errors functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time Errors of the FLASH peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Get the specific FLASH error flag. + * @retval FLASH_ErrorCode The returned value can be + * @arg @ref HAL_FLASH_ERROR_NONE No error set + * @arg @ref HAL_FLASH_ERROR_OP FLASH Operation error + * @arg @ref HAL_FLASH_ERROR_PROG FLASH Programming error + * @arg @ref HAL_FLASH_ERROR_WRP FLASH Write protection error + * @arg @ref HAL_FLASH_ERROR_PGA FLASH Programming alignment error + * @arg @ref HAL_FLASH_ERROR_SIZ FLASH Size error + * @arg @ref HAL_FLASH_ERROR_PGS FLASH Programming sequence error + * @arg @ref HAL_FLASH_ERROR_OPTW FLASH Option modification error + * @arg @ref HAL_FLASH_ERROR_OPTW FLASH Option write error + */ +uint32_t HAL_FLASH_GetError(void) +{ + return pFlash.ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ + +/** @addtogroup FLASH_Private_Functions + * @{ + */ + +/** + * @brief Wait for a FLASH operation to complete. + * @param Timeout Maximum flash operation timeout + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) +{ + /* Wait for the FLASH operation to complete by polling on BUSY and WDW flags to be reset. + Even if the FLASH operation fails, the BUSY & WDW flags will be reset, and an error flag will be set */ + + uint32_t timeout = HAL_GetTick() + Timeout; + uint32_t error; + __IO uint32_t *reg_sr; + + /* Access to SECSR or NSSR registers depends on operation type */ +#if defined(FLASH_SECSR_EOP) + reg_sr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECSR) : &(FLASH_NS->NSSR); +#else + reg_sr = &(FLASH_NS->NSSR); +#endif /* FLASH_SECSR_EOP */ + + while (((*reg_sr) & (FLASH_FLAG_BSY | FLASH_FLAG_WDW)) != 0U) + { + if (Timeout != HAL_MAX_DELAY) + { + if (HAL_GetTick() >= timeout) + { + return HAL_TIMEOUT; + } + } + } + + /* Check FLASH operation error flags */ + error = ((*reg_sr) & FLASH_FLAG_SR_ERRORS); +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + error |= (FLASH->NSSR & FLASH_FLAG_OPTWERR); +#endif /* __ARM_FEATURE_CMSE */ + + if (error != 0U) + { + /*Save the error code*/ + pFlash.ErrorCode |= error; + + /* Clear error programming flags */ + (*reg_sr) = error; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + if ((error & FLASH_FLAG_OPTWERR) != 0U) + { + FLASH->NSSR = FLASH_FLAG_OPTWERR; + } +#endif /* __ARM_FEATURE_CMSE */ + + return HAL_ERROR; + } + + /* Check FLASH End of Operation flag */ + if (((*reg_sr) & FLASH_FLAG_EOP) != 0U) + { + /* Clear FLASH End of Operation pending bit */ + (*reg_sr) = FLASH_FLAG_EOP; + } + + return HAL_OK; +} + +/** + * @brief Program a quad-word (128-bit) at a specified address. + * @param Address Specifies the address to be programmed. + * @param DataAddress Specifies the address of data to be programmed. + * @retval None + */ +static void FLASH_Program_QuadWord(uint32_t Address, uint32_t DataAddress) +{ + uint8_t index = 4; + uint32_t *dest_addr = (uint32_t *)Address; + uint32_t *src_addr = (uint32_t *)DataAddress; + uint32_t primask_bit; + __IO uint32_t *reg_cr; + + /* Check the parameters */ + assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); + + /* Access to SECCR1 or NSCR1 registers depends on operation type */ +#if defined(FLASH_SECCR1_LOCK) + reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR1) : &(FLASH_NS->NSCR1); +#else + reg_cr = &(FLASH_NS->NSCR1); +#endif /* FLASH_SECCR1_LOCK */ + + /* Set PG bit */ + SET_BIT((*reg_cr), FLASH_NSCR1_PG); + + /* Enter critical section: Disable interrupts to avoid any interruption during the loop */ + primask_bit = __get_PRIMASK(); + __disable_irq(); + + /* Program the quad-word */ + do + { + *dest_addr = *src_addr; + dest_addr++; + src_addr++; + index--; + } while (index != 0U); + + /* Exit critical section: restore previous priority mask */ + __set_PRIMASK(primask_bit); +} + +/** + * @brief Program a burst of 8x quad-words at a specified address. + * @param Address Specifies the address to be programmed. + * @param DataAddress Specifies the address where the data are stored. + * @retval None + */ +static void FLASH_Program_Burst(uint32_t Address, uint32_t DataAddress) +{ + uint8_t burst_index = FLASH_NB_WORDS_IN_BURST; + uint32_t *dest_addr = (uint32_t *)Address; + uint32_t *src_addr = (uint32_t *)DataAddress; + uint32_t primask_bit; + __IO uint32_t *reg_cr; + + /* Check the parameters */ + assert_param(IS_FLASH_MAIN_MEM_ADDRESS(Address)); + + /* Access to SECCR1 or NSCR1 registers depends on operation type */ +#if defined(FLASH_SECCR1_LOCK) + reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR1) : &(FLASH_NS->NSCR1); +#else + reg_cr = &(FLASH_NS->NSCR1); +#endif /* FLASH_SECCR1_LOCK */ + + /* Set PG and BWR bits */ + SET_BIT((*reg_cr), (FLASH_NSCR1_PG | FLASH_NSCR1_BWR)); + + /* Enter critical section: Disable interrupts to avoid any interruption during the loop */ + primask_bit = __get_PRIMASK(); + __disable_irq(); + + /* Program the burst */ + do + { + *dest_addr = *src_addr; + dest_addr++; + src_addr++; + burst_index--; + } while (burst_index != 0U); + + /* Exit critical section: restore previous priority mask */ + __set_PRIMASK(primask_bit); +} + +/** + * @} + */ + +#endif /* HAL_FLASH_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_flash_ex.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_flash_ex.c new file mode 100644 index 0000000000..b08994a33c --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_flash_ex.c @@ -0,0 +1,1656 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_flash_ex.c + * @author MCD Application Team + * @brief Extended FLASH HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the FLASH extended peripheral: + * + Extended programming operations functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### Flash Extended features ##### + ============================================================================== + + [..] Comparing to other previous devices, the FLASH interface for STM32WBAxx + devices contains the following additional features + + (+) Capacity up to 2 Mbyte + (+) Watermark-based secure area including the secure hide areas + (+) Block-based secure pages + + ##### How to use this driver ##### + ============================================================================== + [..] This driver provides functions to configure and program the FLASH memory + of all STM32WBAxx devices. It includes: + (#) Flash Memory Erase functions: + (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and + HAL_FLASH_Lock() functions + (++) Erase function: page Erase and Mass Erase + (++) There are two modes of erase : + (+++) Polling Mode using HAL_FLASHEx_Erase() + (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT() + + (#) Option Bytes Programming function: Use HAL_FLASHEx_OBProgram() to: + (++) Configure the write protection for each area + (++) Set the Read protection Level + (++) Program the user Option Bytes + (++) Configure the watermark security for each area including the secure hide areas + (++) Configure the boot lock (BOOT_LOCK) + (++) Configure the Boot addresses + + (#) Get Option Bytes Configuration function: Use HAL_FLASHEx_OBGetConfig() to: + (++) Get the value of a write protection area + (++) Know if the read protection is activated + (++) Get the value of the user Option Bytes + (++) Get the configuration of a watermark security area including the secure hide areas + (++) Get the boot lock (BOOT_LOCK) configuration + (++) Get the value of a boot address + + (#) Block-based secure / privilege area configuration function: Use HAL_FLASHEx_ConfigBBAttributes() + (++) Bit-field allowing to secure or un-secure each page + (++) Bit-field allowing to privilege or un-privilege each page + + (#) Get the block-based secure / privilege area configuration function: Use HAL_FLASHEx_GetBBSec() + (++) Return the configuration of the block-based security and privilege for all the pages + + (#) Activation of the secure hide area function: Use HAL_FLASHEx_EnableSecHideProtection() + (++) Deny the access to the secure hide area + + (#) Privilege mode configuration function: Use HAL_FLASHEx_ConfigPrivMode() + (++) FLASH register can be protected against non-privilege accesses + + (#) Get the privilege mode configuration function: Use HAL_FLASHEx_GetPrivMode() + (++) Return if the FLASH registers are protected against non-privilege accesses + + (#) Security inversion configuration function: Use HAL_FLASHEx_ConfigSecInversion() + (++) FLASH secure state can be override + + (#) Get the security inversion configuration function: Use HAL_FLASHEx_GetSecInversion() + (++) Return if FLASH secure state is override + + (#) Enable low-power mode function: Use HAL_FLASHEx_EnablePowerDown() + (++) Enable low-power mode for Flash + + (#) Enable low-power read mode function: Use HAL_FLASHEx_ConfigLowPowerRead() + (++) Enable low-power read mode for Flash memory + + (#) Get the low-power read mode configuration function: Use HAL_FLASHEx_GetLowPowerRead() + (++) Return if FLASH is in low-power read mode or normal read mode + + (#) Get Flash operation function: Use HAL_FLASHEx_GetOperation() + (++) Return information about the on-going Flash operation. After a + system reset, return information about the interrupted Flash operation, if any. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @defgroup FLASHEx FLASHEx + * @brief FLASH Extended HAL module driver + * @{ + */ + +#ifdef HAL_FLASH_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions + * @{ + */ +static void FLASH_MassErase(void); +static void FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRPEndOffset, + FunctionalState WRPLock); +static void FLASH_OB_RDPConfig(uint32_t RDPLevel); +static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig); +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +static void FLASH_OB_WMSECConfig(uint32_t WMSecConfig, uint32_t WMSecStartPage, uint32_t WMSecEndPage, + uint32_t WMHDPEndPage); +static void FLASH_OB_BootLockConfig(uint32_t BootLockConfig); +#endif /* __ARM_FEATURE_CMSE */ +static void FLASH_OB_BootAddrConfig(uint32_t BootAddrConfig, uint32_t BootAddr); +static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t *WRPStartOffset, uint32_t *WRPEndOffset, + FunctionalState *WRPLock); +static uint32_t FLASH_OB_GetRDP(void); +static uint32_t FLASH_OB_GetUser(void); +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +static void FLASH_OB_GetWMSEC(uint32_t *WMSecConfig, uint32_t *WMSecStartPage, uint32_t *WMSecEndPage, + uint32_t *WMHDPEndPage); +static uint32_t FLASH_OB_GetBootLock(void); +#endif /* __ARM_FEATURE_CMSE */ +static void FLASH_OB_GetBootAddr(uint32_t BootAddrConfig, uint32_t *BootAddr); +static void FLASH_OB_RDPKeyConfig(uint32_t RDPKeyType, uint32_t RDPKey1, uint32_t RDPKey2); +/** + * @} + */ + +/* Exported functions -------------------------------------------------------*/ +/** @defgroup FLASHEx_Exported_Functions FLASH Extended Exported Functions + * @{ + */ + +/** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions + * @brief Extended IO operation functions + * +@verbatim + =============================================================================== + ##### Extended programming operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the Extended FLASH + programming operations Operations. + +@endverbatim + * @{ + */ + +/** + * @brief Perform a mass erase or erase the specified FLASH memory pages. + * @note Before any operation, it is possible to check there is no operation suspended + * by call HAL_FLASHEx_IsOperationSuspended() + * @param[in] pEraseInit Pointer to an @ref FLASH_EraseInitTypeDef structure that + * contains the configuration information for the erasing. + * + * @param[out] PageError Pointer to variable that contains the configuration + * information on faulty page in case of error (0xFFFFFFFF means that all + * the pages have been correctly erased) + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError) +{ + HAL_StatusTypeDef status; + uint32_t page_index; + __IO uint32_t *reg_cr; + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Reset error code */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Verify that next operation can be proceed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + /* Current operation type */ + pFlash.ProcedureOnGoing = pEraseInit->TypeErase; + + /* Access to SECCR1 or NSCR1 depends on operation type */ +#if defined(FLASH_SECCR1_LOCK) + reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR1) : &(FLASH_NS->NSCR1); +#else + reg_cr = &(FLASH_NS->NSCR1); +#endif /* FLASH_SECCR1_LOCK */ + + if ((pEraseInit->TypeErase & (~FLASH_NON_SECURE_MASK)) == FLASH_TYPEERASE_MASSERASE) + { + /* Mass erase to be done */ + FLASH_MassErase(); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + } + else + { + /*Initialization of PageError variable*/ + *PageError = 0xFFFFFFFFU; + + for (page_index = pEraseInit->Page; page_index < (pEraseInit->Page + pEraseInit->NbPages); page_index++) + { + /* Start erase page */ + FLASH_PageErase(page_index); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if (status != HAL_OK) + { + /* In case of error, stop erase procedure and return the faulty page */ + *PageError = page_index; + break; + } + } + } + + /* If the erase operation is completed, disable the associated bits */ + CLEAR_BIT((*reg_cr), (((pEraseInit->TypeErase) & (~(FLASH_NON_SECURE_MASK))) | FLASH_NSCR1_PNB)); + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + +/** + * @brief Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled. + * @note Before any operation, it is possible to check there is no operation suspended + * by call HAL_FLASHEx_IsOperationSuspended() + * @param pEraseInit Pointer to an @ref FLASH_EraseInitTypeDef structure that + * contains the configuration information for the erasing. + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) +{ + HAL_StatusTypeDef status; + __IO uint32_t *reg_cr; + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Reset error code */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Verify that next operation can be proceed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if (status != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + } + else + { + /* Set internal variables used by the IRQ handler */ + pFlash.ProcedureOnGoing = pEraseInit->TypeErase; + + /* Access to SECCR1 or NSCR1 depends on operation type */ +#if defined(FLASH_SECCR1_LOCK) + reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR1) : &(FLASH_NS->NSCR1); +#else + reg_cr = &(FLASH_NS->NSCR1); +#endif /* FLASH_SECCR1_LOCK */ + + /* Enable End of Operation and Error interrupts */ + (*reg_cr) |= (FLASH_IT_EOP | FLASH_IT_OPERR); + + if ((pEraseInit->TypeErase & (~FLASH_NON_SECURE_MASK)) == FLASH_TYPEERASE_MASSERASE) + { + /* Mass erase to be done */ + FLASH_MassErase(); + } + else + { + /* Erase by page to be done */ + pFlash.NbPagesToErase = pEraseInit->NbPages; + pFlash.Page = pEraseInit->Page; + + /* Erase first page and wait for IT */ + FLASH_PageErase(pEraseInit->Page); + } + } + + /* return status */ + return status; +} + +/** + * @brief Program Option bytes. + * @param pOBInit Pointer to an @ref FLASH_OBProgramInitTypeDef structure that + * contains the configuration information for the programming. + * + * @note To configure any option bytes, the option lock bit OPTLOCK must be + * cleared with the call of @ref HAL_FLASH_OB_Unlock() function. + * @note New option bytes configuration will be taken into account in two cases: + * - after an option bytes launch through the call of @ref HAL_FLASH_OB_Launch() + * - after a power reset (BOR reset or exit from Standby/Shutdown modes) + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) +{ + HAL_StatusTypeDef status; + + /* Check the parameters */ + assert_param(IS_OPTIONBYTE(pOBInit->OptionType)); + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Reset error code */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Verify that next operation can be proceed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + /* Write protection configuration */ + if ((pOBInit->OptionType & OPTIONBYTE_WRP) != 0U) + { + /* Configure of Write protection on the selected area */ + FLASH_OB_WRPConfig(pOBInit->WRPArea, pOBInit->WRPStartOffset, pOBInit->WRPEndOffset, pOBInit->WRPLock); + } + + /* Read protection configuration */ + if ((pOBInit->OptionType & OPTIONBYTE_RDP) != 0U) + { + /* Configure the Read protection level */ + FLASH_OB_RDPConfig(pOBInit->RDPLevel); + } + + /* Read protection key configuration */ + if ((pOBInit->OptionType & OPTIONBYTE_RDPKEY) != 0U) + { + /* Configure the Read protection key */ + FLASH_OB_RDPKeyConfig(pOBInit->RDPKeyType, pOBInit->RDPKey1, pOBInit->RDPKey2); + } + + /* User Configuration */ + if ((pOBInit->OptionType & OPTIONBYTE_USER) != 0U) + { + /* Configure the user option bytes */ + FLASH_OB_UserConfig(pOBInit->USERType, pOBInit->USERConfig); + } + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + /* Watermark secure configuration */ + if ((pOBInit->OptionType & OPTIONBYTE_WMSEC) != 0U) + { + /* Configure the watermark-based secure area */ + FLASH_OB_WMSECConfig(pOBInit->WMSecConfig, pOBInit->WMSecStartPage, pOBInit->WMSecEndPage, + pOBInit->WMHDPEndPage); + } + + /* Unique boot entry point configuration */ + if ((pOBInit->OptionType & OPTIONBYTE_BOOT_LOCK) != 0U) + { + /* Configure the unique boot entry point */ + FLASH_OB_BootLockConfig(pOBInit->BootLock); + } +#endif /* __ARM_FEATURE_CMSE */ + + /* Boot address configuration */ + if ((pOBInit->OptionType & OPTIONBYTE_BOOTADDR) != 0U) + { + /* Configure the boot address */ + FLASH_OB_BootAddrConfig(pOBInit->BootAddrConfig, pOBInit->BootAddr); + } + + /* Set OPTSTRT Bit */ + SET_BIT(FLASH->NSCR1, FLASH_NSCR1_OPTSTRT); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + /* return status */ + return status; +} + +/** + * @brief Get the Option bytes configuration. + * @param pOBInit Pointer to an @ref FLASH_OBProgramInitTypeDef structure that contains the + * configuration information. + * @note The fields pOBInit->WRPArea, pOBInit->WMSecConfig and pOBInit->BootAddrConfig + * should indicate which area/address is requested for the WRP, WM Security or + * Boot Address, else no information will be returned + * + * @retval None + */ +void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) +{ + pOBInit->OptionType = (OPTIONBYTE_RDP | OPTIONBYTE_USER); + + if ((pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAA) || (pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAB)) + { + pOBInit->OptionType |= OPTIONBYTE_WRP; + /* Get write protection on the selected area */ + FLASH_OB_GetWRP(pOBInit->WRPArea, &(pOBInit->WRPStartOffset), &(pOBInit->WRPEndOffset), &(pOBInit->WRPLock)); + } + + /* Get Read protection level */ + pOBInit->RDPLevel = FLASH_OB_GetRDP(); + + /* Get the user option bytes */ + pOBInit->USERConfig = FLASH_OB_GetUser(); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + /* Get the configuration of the watermark secure area for the selected area */ + if (pOBInit->WMSecConfig == OB_WMSEC_AREA1) + { + pOBInit->OptionType |= OPTIONBYTE_WMSEC; + FLASH_OB_GetWMSEC(&(pOBInit->WMSecConfig), &(pOBInit->WMSecStartPage), &(pOBInit->WMSecEndPage), + &(pOBInit->WMHDPEndPage)); + } + + pOBInit->OptionType |= OPTIONBYTE_BOOT_LOCK; + + /* Get the configuration of the unique boot entry point */ + pOBInit->BootLock = FLASH_OB_GetBootLock(); +#endif /* __ARM_FEATURE_CMSE */ + + /* Get the value of the selected boot address */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + if ((pOBInit->BootAddrConfig == OB_BOOTADDR_NS0) || (pOBInit->BootAddrConfig == OB_BOOTADDR_NS1) || + (pOBInit->BootAddrConfig == OB_BOOTADDR_SEC0)) +#else + if ((pOBInit->BootAddrConfig == OB_BOOTADDR_NS0) || (pOBInit->BootAddrConfig == OB_BOOTADDR_NS1)) +#endif /* __ARM_FEATURE_CMSE */ + { + pOBInit->OptionType |= OPTIONBYTE_BOOTADDR; + FLASH_OB_GetBootAddr(pOBInit->BootAddrConfig, &(pOBInit->BootAddr)); + } +} + +#if defined(FLASH_SECBBR1_SECBB0) || defined(FLASH_PRIVBBR1_PRIVBB0) || defined(FLASH_SECBB1R1_SECBB0) || defined(FLASH_PRIVBB1R1_PRIVBB0) +/** + * @brief Configure the block-based secure area. + * + * @param pBBAttributes pointer to an @ref FLASH_BBAttributesTypeDef structure that + * contains the configuration information for the programming. + * + * @note The field pBBAttributes->Bank should indicate which area is requested + * for the block-based attributes. + * @note The field pBBAttributes->BBAttributesType should indicate which + * block-base attribute type is requested: Secure or Privilege. + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_ConfigBBAttributes(FLASH_BBAttributesTypeDef *pBBAttributes) +{ + HAL_StatusTypeDef status; + uint8_t index; + __IO uint32_t *reg; + + /* Check the parameters */ + assert_param(IS_FLASH_BB_EXCLUSIVE(pBBAttributes->BBAttributesType)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + /* Set the first Block-Based register to write */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + if (pBBAttributes->BBAttributesType == FLASH_BB_SEC) + { + reg = &(FLASH->SECBBR1); + } + else +#endif /* __ARM_FEATURE_CMSE */ + { + reg = &(FLASH->PRIVBBR1); + } + + /* Modify the register values and check that new attributes are taken in account */ + for (index = 0; index < FLASH_BLOCKBASED_NB_REG; index++) + { + *reg = pBBAttributes->BBAttributes_array[index]; + if ((*reg) != pBBAttributes->BBAttributes_array[index]) + { + status = HAL_ERROR; + } + reg++; + } + + /* ISB instruction is called to be sure next instructions are performed with correct attributes */ + __ISB(); + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + +/** + * @brief Return the block-based attributes. + * + * @param pBBAttributes [in/out] pointer to an FLASH_BBAttributesTypeDef structure + * that contains the configuration information. + * @note The field pBBAttributes->BBAttributesType should indicate which + * block-base attribute type is requested: Secure or Privilege. + * + * @retval None + */ +void HAL_FLASHEx_GetConfigBBAttributes(FLASH_BBAttributesTypeDef *pBBAttributes) +{ + uint8_t index; + __IO uint32_t *reg; + + /* Check the parameters */ + assert_param(IS_FLASH_BB_EXCLUSIVE(pBBAttributes->BBAttributesType)); + + /* Set the first Block-Based register to read */ + if (pBBAttributes->BBAttributesType == FLASH_BB_SEC) + { + reg = &(FLASH->SECBBR1); + } + else + { + reg = &(FLASH->PRIVBBR1); + } + + /* Read the register values */ + for (index = 0; index < FLASH_BLOCKBASED_NB_REG; index++) + { + pBBAttributes->BBAttributes_array[index] = (*reg); + reg++; + } +} +#endif /* FLASH_SECBBR1_SECBB0 || FLASH_PRIVBBR1_PRIVBB0 */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Activation of the protection of the secure hide area. + * + * @param Banks indicate the bank concerned by the activation + * This parameter can be one of the following values: + * @arg FLASH_BANK_1: Bank1 to be protected + * + * @retval None + */ +void HAL_FLASHEx_EnableSecHideProtection(uint32_t Banks) +{ + /* Check the parameters */ + assert_param(IS_FLASH_BANK(Banks)); + + SET_BIT(FLASH->SECHDPCR, FLASH_SECHDPCR_HDP_ACCDIS); + +} +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @} + */ + +/** @defgroup FLASHEx_Exported_Functions_Group2 Extended Peripheral Control functions + * @brief Extended Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Extended Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the FLASH + memory operations. + +@endverbatim + * @{ + */ + +/** + * @brief Suspend new program or erase operation request. + * @param Request Indicate the suspend operation request + * This parameter can be a value of @ref FLASHEx_Suspend_Request + * @retval None + */ +void HAL_FLASHEx_SuspendOperation(uint32_t Request) +{ + /* Check the parameter */ + assert_param(IS_FLASH_SUSPEND_REQ(Request)); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SET_BIT(FLASH->SECCR2, Request); +#else + SET_BIT(FLASH->NSCR2, Request); +#endif /* __ARM_FEATURE_CMSE */ +} + +/** + * @brief Allow new program or erase operation request. + * @param Request Indicate the allow operation request + * This parameter can be a value of @ref FLASHEx_Allow_Request + * @retval None + */ +void HAL_FLASHEx_AllowOperation(uint32_t Request) +{ + /* Check the parameter */ + assert_param(IS_FLASH_ALLOW_REQ(Request)); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + CLEAR_BIT(FLASH->SECCR2, Request); +#else + CLEAR_BIT(FLASH->NSCR2, Request); +#endif /* __ARM_FEATURE_CMSE */ +} + +/** + * @brief Check if new program or erase operation request is suspended + * @retval Status + * - 0 : No suspended flash operation + * - FLASH_SUSPEND_PROGRAM : Program operations are suspended + * - FLASH_SUSPEND_ERASE : Erase operations are suspended + * - FLASH_SUSPEND_PROGRAM_ERASE : Program and erase operations are suspended + */ +uint32_t HAL_FLASHEx_IsOperationSuspended(void) +{ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + return (FLASH->SECCR2 & FLASH_SUSPEND_PROGRAM_ERASE); +#else + return (FLASH->NSCR2 & FLASH_SUSPEND_PROGRAM_ERASE); +#endif /* __ARM_FEATURE_CMSE */ +} + +#if defined(FLASH_PRIVCFGR_SPRIV) +/** + * @brief Configuration of the privilege attribute. + * + * @param PrivMode indicate privilege mode configuration + * This parameter can be one of the following values: + * @arg FLASH_SPRIV_GRANTED: access to secure Flash registers is granted to privileged or unprivileged access + * @arg FLASH_SPRIV_DENIED: access to secure Flash registers is denied to unprivileged access + * @arg FLASH_NSPRIV_GRANTED: access to non-secure Flash registers is granted to privileged or unprivileged access + * @arg FLASH_NSPRIV_DENIED: access to non-secure Flash registers is denied to unprivilege access + * + * @retval None + */ +void HAL_FLASHEx_ConfigPrivMode(uint32_t PrivMode) +{ + /* Check the parameters */ + assert_param(IS_FLASH_CFGPRIVMODE(PrivMode)); + + MODIFY_REG(FLASH->PRIVCFGR, (FLASH_PRIVCFGR_SPRIV | FLASH_PRIVCFGR_NSPRIV), PrivMode); +} + +/** + * @brief Return the value of the privilege attribute. + * + * @retval It indicates the privilege mode configuration. + * This return value can be one of the following values: + * @arg FLASH_SPRIV_GRANTED: access to secure Flash registers is granted to privileged or unprivileged access + * @arg FLASH_SPRIV_DENIED: access to secure Flash registers is denied to unprivileged access + * @arg FLASH_NSPRIV_GRANTED: access to non-secure Flash registers is granted to privileged or unprivileged access + * @arg FLASH_NSPRIV_DENIED: access to Flash registers is denied to unprivilege accessP + */ +uint32_t HAL_FLASHEx_GetPrivMode(void) +{ + return (FLASH->PRIVCFGR & (FLASH_PRIVCFGR_SPRIV | FLASH_PRIVCFGR_NSPRIV)); +} +#endif /* FLASH_PRIVCFGR_SPRIV */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Configuration of the security inversion. + * + * @param SecInvState indicate the flash security state configuration + * This parameter can be one of the following values: + * @arg FLASH_SEC_INV_DISABLE: Security state of Flash is not inverted + * @arg FLASH_SEC_INV_ENABLE: Security state of Flash is inverted + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_ConfigSecInversion(uint32_t SecInvState) +{ + HAL_StatusTypeDef status; + + /* Check the parameters */ + assert_param(IS_FLASH_CFGSECINV(SecInvState)); + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + MODIFY_REG(FLASH->SECCR1, FLASH_SECCR1_INV, SecInvState); + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + +/** + * @brief Return the value of the security inversion. + * + * @retval It indicates the flash security state configuration + * This return value can be one of the following values: + * @arg FLASH_SEC_INV_DISABLE: Security state of Flash is not inverted + * @arg FLASH_SEC_INV_ENABLE: Security state of Flash is inverted + */ +uint32_t HAL_FLASHEx_GetSecInversion(void) +{ + return (FLASH->SECCR1 & FLASH_SECCR1_INV); +} +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @brief Enable the Power-down Mode for Flash Banks + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_EnablePowerDown() +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tickstart; + + /* Check PD and PDREQ bits (Flash is not in power-down mode and not being + already under power-down request) */ + if ((FLASH->NSSR & FLASH_NSSR_PD) != 0U) + { + status = HAL_ERROR; + } + else if ((FLASH->ACR & FLASH_ACR_PDREQ) != 0U) + { + status = HAL_ERROR; + } + else + { + /* Unlock PDREQ bit */ + WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); + WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); + + /* Set PDREQ in FLASH_ACR register */ + SET_BIT(FLASH->ACR, FLASH_ACR_PDREQ); + + /* Check PD1 bit */ + tickstart = HAL_GetTick(); + while (((FLASH->NSSR & FLASH_NSSR_PD) != FLASH_NSSR_PD)) + { + if ((HAL_GetTick() - tickstart) > FLASH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + return status; +} + +/** + * @brief Configuration of the Low-Power read Mode. + * + * @param ConfigLPM indicate the Low-Power read Mode configuration. + * This parameter can be one of the following values: + * @arg FLASH_LPM_ENABLE: Flash is in low-power read mode + * @arg FLASH_LPM_DISABLE: Flash is in normal read mode + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_ConfigLowPowerRead(uint32_t ConfigLPM) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_FLASH_CFGLPM(ConfigLPM)); + + /* Set LPM Bit in FLASH_ACR register */ + MODIFY_REG(FLASH->ACR, FLASH_ACR_LPM, ConfigLPM); + + /* Check that low power read mode has been activated */ + if (READ_BIT(FLASH->ACR, FLASH_ACR_LPM) != ConfigLPM) + { + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Return the value of the Low-Power read Mode. + * + * @retval It indicates the flash low-power read mode configuration + * This return value can be one of the following values: + * @arg FLASH_LPM_ENABLE: Flash is in low-power read mode + * @arg FLASH_LPM_DISABLE: Flash is in normal read mode + */ +uint32_t HAL_FLASHEx_GetLowPowerRead(void) +{ + return (FLASH->ACR & FLASH_ACR_LPM); +} + +/** + * @brief Return the on-going Flash Operation. After a system reset, return + * the interrupted Flash operation, if any. + * @param pFlashOperation [out] pointer to a FLASH_OperationTypeDef structure + * that contains the Flash operation information. + * + * @retval None + */ +void HAL_FLASHEx_GetOperation(FLASH_OperationTypeDef *pFlashOperation) +{ + uint32_t opsr_reg = FLASH->OPSR; + + /* Get Flash operation Type */ + pFlashOperation->OperationType = opsr_reg & FLASH_OPSR_CODE_OP; + + /* Get Flash operation memory */ + pFlashOperation->FlashArea = opsr_reg & FLASH_OPSR_SYSF_OP; + + /* Get Flash operation address */ + pFlashOperation->Address = opsr_reg & FLASH_OPSR_ADDR_OP; +} + +/** + * @} + */ + +/** @defgroup FLASHEx_Exported_Functions_Group3 Extended ECC operation functions + * @brief Extended ECC operation functions + * +@verbatim + =============================================================================== + ##### Extended ECC operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the Extended FLASH + ECC Operations. + +@endverbatim + * @{ + */ +/** + * @brief Enable ECC correction interrupt + * @note ECC detection does not need to be enabled as directly linked to + * Non-Maskable Interrupt (NMI) + * @retval None + */ +void HAL_FLASHEx_EnableEccCorrectionInterrupt(void) +{ + __HAL_FLASH_ENABLE_IT(FLASH_IT_ECCC); +} + +/** + * @brief Disable ECC correction interrupt + * @retval None + */ +void HAL_FLASHEx_DisableEccCorrectionInterrupt(void) +{ + __HAL_FLASH_DISABLE_IT(FLASH_IT_ECCC); +} + +/** + * @brief Get the ECC error information. + * @param pData Pointer to an FLASH_EccInfoTypeDef structure that contains the + * ECC error information. + * @note This function should be called before ECC bit is cleared + * (in callback function) + * @retval None + */ +void HAL_FLASHEx_GetEccInfo(FLASH_EccInfoTypeDef *pData) +{ + uint32_t eccr; + /* Check Null pointer */ + assert_param(pData != NULL); + + /* Get back information from ECC register */ + eccr = FLASH->ECCR; + + /* Retrieve and sort information */ + pData->Area = (eccr & FLASH_ECCR_SYSF_ECC); + pData->Address = ((eccr & FLASH_ECCR_ADDR_ECC) << 3U); + + /* Add Base address depending on targeted area */ + if (pData->Area == FLASH_ECC_AREA_USER_BANK1) + { + pData->Address |= FLASH_BASE; + } + else + { +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + pData->Address |= SYSTEM_FLASH_BASE_S; +#else + pData->Address |= SYSTEM_FLASH_BASE_NS; +#endif /* __ARM_FEATURE_CMSE */ + } + + /* Set Master which initiates transaction. On WBA, it's necessary CPU1 */ + pData->MasterID = FLASH_ECC_MASTER_CPU1; +} + +/** + * @brief Handle Flash ECC Detection interrupt request. + * @note On STM32WBA, this Irq Handler should be called in Non-Maskable Interrupt (NMI) + * interrupt subroutine. + * @retval None + */ +void HAL_FLASHEx_ECCD_IRQHandler(void) +{ + /* Check ECC Detection Error */ + if ((FLASH->ECCR & FLASH_ECCR_ECCD) != 0U) + { + /* Call User callback */ + HAL_FLASHEx_EccDetectionCallback(); + + /* Clear ECC detection flag in order to allow new ECC error record */ + SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCD); + } +} + +/** + * @brief FLASH ECC Correction interrupt callback. + * @retval None + */ +__weak void HAL_FLASHEx_EccCorrectionCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_FLASHEx_EccCorrectionCallback could be implemented in the user file + */ +} + +/** + * @brief FLASH ECC Detection interrupt callback. + * @retval None + */ +__weak void HAL_FLASHEx_EccDetectionCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_FLASHEx_EccDetectionCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ + +/** @addtogroup FLASHEx_Private_Functions + * @{ + */ +/** + * @brief Mass erase of FLASH memory. + * @retval None + */ +static void FLASH_MassErase() +{ + __IO uint32_t *reg_cr; + + + /* Access to SECCR1 or NSCR1 registers depends on operation type */ +#if defined(FLASH_SECCR1_LOCK) + reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR1) : &(FLASH_NS->NSCR1); +#else + reg_cr = &(FLASH_NS->NSCR1); +#endif /* FLASH_SECCR1_LOCK */ + + /* Set the Mass Erase Bit for the bank 1 and proceed to erase */ + SET_BIT((*reg_cr), FLASH_NSCR1_MER | FLASH_NSCR1_STRT); +} + +/** + * @brief Erase the specified FLASH memory page. + * @param Page FLASH page to erase + * This parameter must be a value between 0 and (max number of pages in the bank - 1) + * @retval None + */ +void FLASH_PageErase(uint32_t Page) +{ + __IO uint32_t *reg_cr; + + /* Check the parameters */ + assert_param(IS_FLASH_PAGE(Page)); + + /* Access to SECCR1 or NSCR1 registers depends on operation type */ +#if defined(FLASH_SECCR1_LOCK) + reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR1) : &(FLASH_NS->NSCR1); +#else + reg_cr = &(FLASH_NS->NSCR1); +#endif /* FLASH_SECCR1_LOCK */ + + + /* Proceed to erase the page */ + MODIFY_REG((*reg_cr), (FLASH_NSCR1_PNB | FLASH_NSCR1_PER | FLASH_NSCR1_STRT), ((Page << FLASH_NSCR1_PNB_Pos) | FLASH_NSCR1_PER | FLASH_NSCR1_STRT)); +} + +/** + * @brief Configure the write protection of the desired pages. + * + * @note When WRP is active in a zone, it cannot be erased or programmed. + * Consequently, a software mass erase cannot be performed if one zone + * is write-protected. + * @note When the memory read protection level is selected (RDP level = 1), + * it is not possible to program or erase Flash memory if the CPU debug + * features are connected (JTAG or single wire) or boot code is being + * executed from RAM or System flash, even if WRP is not activated. + * @note To configure the WRP options, the option lock bit OPTLOCK must be + * cleared with the call of the @ref HAL_FLASH_OB_Unlock() function. + * @note To validate the WRP options, the option bytes must be reloaded + * through the call of the @ref HAL_FLASH_OB_Launch() function. + * + * @param WRPArea Specifies the area to be configured. + * This parameter can be one of the following values: + * @arg @ref OB_WRPAREA_BANK1_AREAA Flash Bank 1 Area A + * @arg @ref OB_WRPAREA_BANK1_AREAB Flash Bank 1 Area B + * + * @param WRPStartOffset Specifies the start page of the write protected area + * This parameter can be page number between 0 and (max number of pages in the Flash - 1) + * + * @param WRPEndOffset Specifies the end page of the write protected area + * This parameter can be page number between WRPStartOffset and (max number of pages in the Flash - 1) + * + * @param WRPLock Enables the lock of the write protected area + * This parameter can be set to ENABLE or DISABLE + * + * @retval None + */ +static void FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRPEndOffset, FunctionalState WRPLock) +{ + /* Check the parameters */ + assert_param(IS_OB_WRPAREA(WRPArea)); + assert_param(IS_FLASH_PAGE(WRPStartOffset)); + assert_param(IS_FLASH_PAGE(WRPEndOffset)); + assert_param(IS_FUNCTIONAL_STATE(WRPLock)); + + /* Configure the write protected area */ + if (WRPArea == OB_WRPAREA_BANK1_AREAA) + { + FLASH->WRPAR = (((uint32_t)(~WRPLock) << FLASH_WRPAR_UNLOCK_Pos) | \ + (WRPEndOffset << FLASH_WRPAR_WRPA_PEND_Pos) | \ + WRPStartOffset); + } + else if (WRPArea == OB_WRPAREA_BANK1_AREAB) + { + FLASH->WRPBR = (((uint32_t)(~WRPLock) << FLASH_WRPBR_UNLOCK_Pos) | \ + (WRPEndOffset << FLASH_WRPBR_WRPB_PEND_Pos) | \ + WRPStartOffset); + } + else + { + /* Empty statement (to be compliant MISRA 15.7) */ + } +} + +/** + * @brief Set the read protection level. + * + * @note To configure the RDP level, the option lock bit OPTLOCK must be + * cleared with the call of the @ref HAL_FLASH_OB_Unlock() function. + * @note To validate the RDP level, the option bytes must be reloaded + * through the call of the @ref HAL_FLASH_OB_Launch() function. + * @note !!! Warning : When enabling OB_RDP level 2 it's no more possible + * to go back to other levels !!! + * + * @param RDPLevel specifies the read protection level. + * This parameter can be one of the following values: + * @arg @ref OB_RDP_LEVEL_0 No protection + * @arg @ref OB_RDP_LEVEL_0_5 No debug access to secure area + * @arg @ref OB_RDP_LEVEL_1 Read protection of the memory + * @arg @ref OB_RDP_LEVEL_2 Full chip protection + * + * @retval None + */ +static void FLASH_OB_RDPConfig(uint32_t RDPLevel) +{ + /* Check the parameters */ + assert_param(IS_OB_RDP_LEVEL(RDPLevel)); + + /* Configure the RDP level in the option bytes register */ + MODIFY_REG(FLASH->OPTR, FLASH_OPTR_RDP, RDPLevel); +} + +/** + * @brief Set the read protection key. + * @param RDPKeyType Specifies the read protection key type. + * This parameter can be one of the following values: + * @arg @ref OB_RDP_KEY_OEM1 OEM1 key + * @arg @ref OB_RDP_KEY_OEM2 OEM2 key + * @param RDPKey1 Specifies the RDP key 1. + * @param RDPKey2 Specifies the RDP key 2. + * @retval None + */ +static void FLASH_OB_RDPKeyConfig(uint32_t RDPKeyType, uint32_t RDPKey1, uint32_t RDPKey2) +{ + /* Check the parameters */ + assert_param(IS_OB_RDP_KEY_TYPE(RDPKeyType)); + + /* Configure the RDP OEM key */ + if (RDPKeyType == OB_RDP_KEY_OEM1) + { + WRITE_REG(FLASH->OEM1KEYR1, RDPKey1); + WRITE_REG(FLASH->OEM1KEYR2, RDPKey2); + } + else + { + WRITE_REG(FLASH->OEM2KEYR1, RDPKey1); + WRITE_REG(FLASH->OEM2KEYR2, RDPKey2); + } +} + +/** + * @brief Program the FLASH User Option Byte. + * + * @note To configure the user option bytes, the option lock bit OPTLOCK must + * be cleared with the call of the @ref HAL_FLASH_OB_Unlock() function. + * @note To validate the user option bytes, the option bytes must be reloaded + * through the call of the @ref HAL_FLASH_OB_Launch() function. + * + * @param UserType The FLASH User Option Bytes to be modified. + * This parameter can be a combination of @ref FLASH_OB_USER_Type + * @param UserConfig The selected User Option Bytes values. + * This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEVEL, + * @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY, + * @ref FLASH_OB_USER_SRAM1_RST, @ref FLASH_OB_USER_IWDG_SW, + * @ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY, + * @ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_SRAM2_PAR, + * @ref FLASH_OB_USER_SRAM2_RST, @ref FLASH_OB_USER_nSWBOOT0, + * @ref FLASH_OB_USER_nBOOT0 and @ref OB_USER_TZEN(*) + * (*) Feature not available on all devices of the family + * @retval None + */ +static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig) +{ + uint32_t optr_reg_val = 0; + uint32_t optr_reg_mask = 0; + + /* Check the parameters */ + assert_param(IS_OB_USER_TYPE(UserType)); + + if ((UserType & OB_USER_BOR_LEV) != 0U) + { + /* BOR level option byte should be modified */ + assert_param(IS_OB_USER_BOR_LEVEL(UserConfig & FLASH_OPTR_BOR_LEV)); + + /* Set value and mask for BOR level option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTR_BOR_LEV); + optr_reg_mask |= FLASH_OPTR_BOR_LEV; + } + + if ((UserType & OB_USER_nRST_STOP) != 0U) + { + /* nRST_STOP option byte should be modified */ + assert_param(IS_OB_USER_STOP(UserConfig & FLASH_OPTR_nRST_STOP)); + + /* Set value and mask for nRST_STOP option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_STOP); + optr_reg_mask |= FLASH_OPTR_nRST_STOP; + } + + if ((UserType & OB_USER_nRST_STDBY) != 0U) + { + /* nRST_STDBY option byte should be modified */ + assert_param(IS_OB_USER_STANDBY(UserConfig & FLASH_OPTR_nRST_STDBY)); + + /* Set value and mask for nRST_STDBY option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_STDBY); + optr_reg_mask |= FLASH_OPTR_nRST_STDBY; + } + + if ((UserType & OB_USER_SRAM1_RST) != 0U) + { + /* SRAM1_RST option byte should be modified */ + assert_param(IS_OB_USER_SRAM1_RST(UserConfig & FLASH_OPTR_SRAM1_RST)); + + /* Set value and mask for SRAM1_RST option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM1_RST); + optr_reg_mask |= FLASH_OPTR_SRAM1_RST; + } + + if ((UserType & OB_USER_IWDG_SW) != 0U) + { + /* IWDG_SW option byte should be modified */ + assert_param(IS_OB_USER_IWDG(UserConfig & FLASH_OPTR_IWDG_SW)); + + /* Set value and mask for IWDG_SW option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_SW); + optr_reg_mask |= FLASH_OPTR_IWDG_SW; + } + + if ((UserType & OB_USER_IWDG_STOP) != 0U) + { + /* IWDG_STOP option byte should be modified */ + assert_param(IS_OB_USER_IWDG_STOP(UserConfig & FLASH_OPTR_IWDG_STOP)); + + /* Set value and mask for IWDG_STOP option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_STOP); + optr_reg_mask |= FLASH_OPTR_IWDG_STOP; + } + + if ((UserType & OB_USER_IWDG_STDBY) != 0U) + { + /* IWDG_STDBY option byte should be modified */ + assert_param(IS_OB_USER_IWDG_STDBY(UserConfig & FLASH_OPTR_IWDG_STDBY)); + + /* Set value and mask for IWDG_STDBY option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_STDBY); + optr_reg_mask |= FLASH_OPTR_IWDG_STDBY; + } + + if ((UserType & OB_USER_WWDG_SW) != 0U) + { + /* WWDG_SW option byte should be modified */ + assert_param(IS_OB_USER_WWDG(UserConfig & FLASH_OPTR_WWDG_SW)); + + /* Set value and mask for WWDG_SW option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTR_WWDG_SW); + optr_reg_mask |= FLASH_OPTR_WWDG_SW; + } + + + if ((UserType & OB_USER_SRAM2_PE) != 0U) + { + /* SRAM2_PAR option byte should be modified */ + assert_param(IS_OB_USER_SRAM2_PARITY(UserConfig & FLASH_OPTR_SRAM2_PE)); + + /* Set value and mask for SRAM2_PAR option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM2_PE); + optr_reg_mask |= FLASH_OPTR_SRAM2_PE; + } + + if ((UserType & OB_USER_SRAM2_RST) != 0U) + { + /* SRAM2_RST option byte should be modified */ + assert_param(IS_OB_USER_SRAM2_RST(UserConfig & FLASH_OPTR_SRAM2_RST)); + + /* Set value and mask for SRAM2_RST option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM2_RST); + optr_reg_mask |= FLASH_OPTR_SRAM2_RST; + } + + if ((UserType & OB_USER_nSWBOOT0) != 0U) + { + /* nSWBOOT0 option byte should be modified */ + assert_param(IS_OB_USER_SWBOOT0(UserConfig & FLASH_OPTR_nSWBOOT0)); + + /* Set value and mask for nSWBOOT0 option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTR_nSWBOOT0); + optr_reg_mask |= FLASH_OPTR_nSWBOOT0; + } + + if ((UserType & OB_USER_nBOOT0) != 0U) + { + /* nBOOT0 option byte should be modified */ + assert_param(IS_OB_USER_BOOT0(UserConfig & FLASH_OPTR_nBOOT0)); + + /* Set value and mask for nBOOT0 option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTR_nBOOT0); + optr_reg_mask |= FLASH_OPTR_nBOOT0; + } + + +#if defined(FLASH_OPTR_TZEN) + if ((UserType & OB_USER_TZEN) != 0U) + { + /* TZEN option byte should be modified */ + assert_param(IS_OB_USER_TZEN(UserConfig & FLASH_OPTR_TZEN)); + + /* Set value and mask for TZEN option byte */ + optr_reg_val |= (UserConfig & FLASH_OPTR_TZEN); + optr_reg_mask |= FLASH_OPTR_TZEN; + } +#endif /* FLASH_OPTR_TZEN */ + + /* Configure the option bytes register */ + MODIFY_REG(FLASH->OPTR, optr_reg_mask, optr_reg_val); +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Configure the watermarked-based secure area. + * + * @param WMSecConfig specifies the area to be configured. + * This parameter can be a combination of the following values: + * @arg @ref OB_WMSEC_AREA1 Select Flash Secure Area 1 + * @arg @ref OB_WMSEC_SECURE_AREA_CONFIG Configure Flash Secure Area + * @arg @ref OB_WMSEC_HDP_AREA_CONFIG Configure Flash secure hide Area + * @arg @ref OB_WMSEC_HDP_AREA_ENABLE Enable secure hide Area in Secure Area + * @arg @ref OB_WMSEC_HDP_AREA_DISABLE Disable secure hide Area in Secure Area + * + * @param WMSecStartPage Specifies the start page of the secure area + * This parameter can be page number between 0 and (max number of pages in the bank - 1) + * + * @param WMSecEndPage Specifies the end page of the secure area + * This parameter can be page number between WMSecStartPage and (max number of pages in the bank - 1) + * + * @param WMHDPEndPage Specifies the end page of the secure hide area + * This parameter can be a page number between WMSecStartPage and WMSecEndPage + * + * @retval None + */ +static void FLASH_OB_WMSECConfig(uint32_t WMSecConfig, uint32_t WMSecStartPage, uint32_t WMSecEndPage, + uint32_t WMHDPEndPage) +{ + uint32_t tmp_secwm1 = 0U; + uint32_t tmp_secwm2 = 0U; + + /* Check the parameters */ + assert_param(IS_OB_WMSEC_CONFIG(WMSecConfig)); + assert_param(IS_OB_WMSEC_AREA_EXCLUSIVE(WMSecConfig & 0x3U)); + assert_param(IS_FLASH_PAGE(WMSecStartPage)); + assert_param(IS_FLASH_PAGE(WMSecEndPage)); + assert_param(IS_FLASH_PAGE(WMHDPEndPage)); + + /* Read SECWM registers */ + if ((WMSecConfig & OB_WMSEC_AREA1) != 0U) + { + tmp_secwm1 = FLASH->SECWMR1; + tmp_secwm2 = FLASH->SECWMR2; + } + else + { + /* Nothing to do */ + } + + /* Configure Secure Area */ + if ((WMSecConfig & OB_WMSEC_SECURE_AREA_CONFIG) != 0U) + { + MODIFY_REG(tmp_secwm1, (FLASH_SECWMR1_SECWM_PSTRT | FLASH_SECWMR1_SECWM_PEND), + ((WMSecEndPage << FLASH_SECWMR1_SECWM_PEND_Pos) | WMSecStartPage)); + } + + /* Configure Secure Hide Area */ + if ((WMSecConfig & OB_WMSEC_HDP_AREA_CONFIG) != 0U) + { + tmp_secwm2 &= (~FLASH_SECWMR2_HDP_PEND); + tmp_secwm2 |= (WMHDPEndPage << FLASH_SECWMR2_HDP_PEND_Pos); + } + + /* Enable Secure Hide Area */ + if ((WMSecConfig & OB_WMSEC_HDP_AREA_ENABLE) != 0U) + { + tmp_secwm2 |= FLASH_SECWMR2_HDPEN; + } + + /* Disable Secure Hide Area */ + if ((WMSecConfig & OB_WMSEC_HDP_AREA_DISABLE) != 0U) + { + tmp_secwm2 &= (~FLASH_SECWMR2_HDPEN); + } + + /* Write SECWM registers */ + if ((WMSecConfig & OB_WMSEC_AREA1) != 0U) + { + FLASH->SECWMR1 = tmp_secwm1; + FLASH->SECWMR2 = tmp_secwm2; + } + else + { + /* Nothing to do */ + } +} + +/** + * @brief Configure the boot lock. + * @param BootLockConfig Specifies the activation of the BOOT_LOCK. + * This parameter can be one of the following values: + * @arg @ref OB_BOOT_LOCK_DISABLE Boot Lock mode deactivated + * @arg @ref OB_BOOT_LOCK_ENABLE Boot Lock mode activated + * @retval None + */ +static void FLASH_OB_BootLockConfig(uint32_t BootLockConfig) +{ + /* Check the parameters */ + assert_param(IS_OB_BOOT_LOCK(BootLockConfig)); + + /* Configure the option bytes register */ + MODIFY_REG(FLASH->SECBOOTADD0R, FLASH_SECBOOTADD0R_BOOT_LOCK, BootLockConfig); +} +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @brief Configure the boot address. + * + * @param BootAddrConfig specifies the area to be configured. + * This parameter can be one of the following values: + * @arg @ref OB_BOOTADDR_NS0 Non-secure boot address 0 + * @arg @ref OB_BOOTADDR_NS1 Non-secure boot address 1 + * @arg @ref OB_BOOTADDR_SEC0 Secure boot address 0 + * + * @param BootAddr Specifies the address used for the boot + * This parameter can be page number between 0 and 0xFFFFFF00 + * + * @retval None + */ +static void FLASH_OB_BootAddrConfig(uint32_t BootAddrConfig, uint32_t BootAddr) +{ + /* Check the parameters */ + assert_param(IS_OB_BOOTADDR_CONFIG(BootAddrConfig)); + + if (BootAddrConfig == OB_BOOTADDR_NS0) + { + MODIFY_REG(FLASH->NSBOOTADD0R, FLASH_NSBOOTADD0R_NSBOOTADD0, BootAddr); + } + else if (BootAddrConfig == OB_BOOTADDR_NS1) + { + MODIFY_REG(FLASH->NSBOOTADD1R, FLASH_NSBOOTADD1R_NSBOOTADD1, BootAddr); + } +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + else if (BootAddrConfig == OB_BOOTADDR_SEC0) + { + MODIFY_REG(FLASH->SECBOOTADD0R, FLASH_SECBOOTADD0R_SECBOOTADD0, BootAddr); + } +#endif /* __ARM_FEATURE_CMSE */ + else + { + /* Empty statement (to be compliant MISRA 15.7) */ + } +} + +/** + * @brief Return the FLASH Write Protection Option Bytes value. + * + * @param[in] WRPArea Specifies the area to be returned. + * This parameter can be one of the following values: + * @arg @ref OB_WRPAREA_BANK1_AREAA Flash Bank 1 Area A + * @arg @ref OB_WRPAREA_BANK1_AREAB Flash Bank 1 Area B + * + * @param[out] WRPStartOffset Specifies the address where to copied the start page + * of the write protected area + * + * @param[out] WRPEndOffset Specifies the address where to copied the end page of + * the write protected area + * + * @param[out] WRPLock Specifies the lock status of the write protected area. + * The returned value can be ENABLE or DISABLE + * + * @retval None + */ +static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t *WRPStartOffset, uint32_t *WRPEndOffset, FunctionalState *WRPLock) +{ + /* Get the configuration of the write protected area */ + if (WRPArea == OB_WRPAREA_BANK1_AREAA) + { + *WRPStartOffset = READ_BIT(FLASH->WRPAR, FLASH_WRPAR_WRPA_PSTRT); + *WRPEndOffset = (READ_BIT(FLASH->WRPAR, FLASH_WRPAR_WRPA_PEND) >> FLASH_WRPAR_WRPA_PEND_Pos); + *WRPLock = (READ_BIT(FLASH->WRPAR, FLASH_WRPAR_UNLOCK) != 0U) ? DISABLE : ENABLE; + } + else if (WRPArea == OB_WRPAREA_BANK1_AREAB) + { + *WRPStartOffset = READ_BIT(FLASH->WRPBR, FLASH_WRPBR_WRPB_PSTRT); + *WRPEndOffset = (READ_BIT(FLASH->WRPBR, FLASH_WRPBR_WRPB_PEND) >> FLASH_WRPBR_WRPB_PEND_Pos); + *WRPLock = (READ_BIT(FLASH->WRPBR, FLASH_WRPBR_UNLOCK) != 0U) ? DISABLE : ENABLE; + } + else + { + /* Empty statement (to be compliant MISRA 15.7) */ + } +} + +/** + * @brief Return the FLASH Read Protection level. + * @retval FLASH ReadOut Protection Level + * This return value can be one of the following values: + * @arg @ref OB_RDP_LEVEL_0 No protection + * @arg @ref OB_RDP_LEVEL_0_5 No debug access to secure area + * @arg @ref OB_RDP_LEVEL_1 Read protection of the memory + * @arg @ref OB_RDP_LEVEL_2 Full chip protection + */ +static uint32_t FLASH_OB_GetRDP(void) +{ + uint32_t rdp_level = READ_BIT(FLASH->OPTR, FLASH_OPTR_RDP); + + if ((rdp_level != OB_RDP_LEVEL_0) && (rdp_level != OB_RDP_LEVEL_0_5) && (rdp_level != OB_RDP_LEVEL_2)) + { + return (OB_RDP_LEVEL_1); + } + else + { + return (rdp_level); + } +} + +/** + * @brief Return the FLASH User Option Byte value. + * @retval The FLASH User Option Bytes values. + * The return value can be a combination of @ref FLASH_OB_USER_BOR_LEVEL, + * @arg @ref FLASH_OB_USER_nRST_STOP, @arg @ref FLASH_OB_USER_nRST_STANDBY, + * @arg @ref FLASH_OB_USER_SRAM1_RST, @arg @ref FLASH_OB_USER_IWDG_SW, + * @arg @ref FLASH_OB_USER_IWDG_STOP, @arg @ref FLASH_OB_USER_IWDG_STANDBY, + * @arg @ref FLASH_OB_USER_WWDG_SW, @arg @ref FLASH_OB_USER_SRAM2_PAR, + * @arg @ref FLASH_OB_USER_SRAM2_RST, @arg @ref FLASH_OB_USER_nSWBOOT0, + * @arg @ref FLASH_OB_USER_nBOOT0 and @arg @ref OB_USER_TZEN(*) + * (*) Feature not available on all devices of the family + */ +static uint32_t FLASH_OB_GetUser(void) +{ + uint32_t user_config = READ_REG(FLASH->OPTR); + CLEAR_BIT(user_config, FLASH_OPTR_RDP); + + return user_config; +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Return the watermarked-based secure area configuration. + * + * @param WMSecConfig [in/out] Specifies the area to be returned. + * This parameter can be one of the following values: + * @arg @ref OB_WMSEC_AREA1 select Flash Secure Area 1 + * When return from the function, this parameter will be a combinaison of the following values: + * @arg @ref OB_WMSEC_AREA1 selected Flash Secure Area 1 + * @arg @ref OB_WMSEC_HDP_AREA_ENABLE Secure Hide Area in Secure Area enabled + * @arg @ref OB_WMSEC_HDP_AREA_DISABLE Secure Hide Area in Secure Area disabled + * + * @param WMSecStartPage [out] Specifies the start page of the secure area + * + * @param WMSecEndPage [out] Specifies the end page of the secure area + * + * @param WMHDPEndPage [out] Specifies the end page of the secure hide area + * + * @retval None + */ +static void FLASH_OB_GetWMSEC(uint32_t *WMSecConfig, uint32_t *WMSecStartPage, uint32_t *WMSecEndPage, + uint32_t *WMHDPEndPage) +{ + uint32_t tmp_secwm1 = 0U; + uint32_t tmp_secwm2 = 0U; + + /* Check the parameters */ + assert_param(IS_OB_WMSEC_CONFIG(*WMSecConfig)); + assert_param(IS_FLASH_BANK_EXCLUSIVE((*WMSecConfig) & 0x3U)); + + /* Read SECWM registers */ + if (((*WMSecConfig) & OB_WMSEC_AREA1) != 0U) + { + tmp_secwm1 = FLASH->SECWMR1; + tmp_secwm2 = FLASH->SECWMR2; + } + else + { + /* Empty statement (to be compliant MISRA 15.7) */ + } + + /* Configuration of secure area */ + *WMSecStartPage = (tmp_secwm1 & FLASH_SECWMR1_SECWM_PSTRT); + *WMSecEndPage = ((tmp_secwm1 & FLASH_SECWMR1_SECWM_PEND) >> FLASH_SECWMR1_SECWM_PEND_Pos); + + /* Configuration of secure hide area */ + *WMHDPEndPage = ((tmp_secwm2 & FLASH_SECWMR2_HDP_PEND) >> FLASH_SECWMR2_HDP_PEND_Pos); + + if ((tmp_secwm2 & FLASH_SECWMR2_HDPEN) == 0U) + { + *WMSecConfig = ((*WMSecConfig) | OB_WMSEC_HDP_AREA_DISABLE); + } + else + { + *WMSecConfig = ((*WMSecConfig) | OB_WMSEC_HDP_AREA_ENABLE); + } +} + +/** + * @brief Return the boot lock configuration. + * + * @retval Value of Boot Lock configuration + * It can be one of the following values: + * @arg @ref OB_BOOT_LOCK_DISABLE Boot Lock mode deactivated + * @arg @ref OB_BOOT_LOCK_ENABLE Boot Lock mode activated + */ +static uint32_t FLASH_OB_GetBootLock(void) +{ + return (FLASH->SECBOOTADD0R & FLASH_SECBOOTADD0R_BOOT_LOCK); +} +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @brief Return the boot address. + * + * @param[in] BootAddrConfig Specifies the area to be returned + * This parameter can be one of the following values: + * @arg @ref OB_BOOTADDR_NS0 Non-secure boot address 0 + * @arg @ref OB_BOOTADDR_NS1 Non-secure boot address 1 + * @arg @ref OB_BOOTADDR_SEC0 Secure boot address 0 + * + * @param[out] BootAddr specifies the boot address value + * + * @retval None + */ +static void FLASH_OB_GetBootAddr(uint32_t BootAddrConfig, uint32_t *BootAddr) +{ + if (BootAddrConfig == OB_BOOTADDR_NS0) + { + *BootAddr = (FLASH->NSBOOTADD0R & FLASH_NSBOOTADD0R_NSBOOTADD0); + } + else if (BootAddrConfig == OB_BOOTADDR_NS1) + { + *BootAddr = (FLASH->NSBOOTADD1R & FLASH_NSBOOTADD1R_NSBOOTADD1); + } +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + else if (BootAddrConfig == OB_BOOTADDR_SEC0) + { + *BootAddr = (FLASH->SECBOOTADD0R & FLASH_SECBOOTADD0R_SECBOOTADD0); + } +#endif /* __ARM_FEATURE_CMSE */ + else + { + /* Empty statement (to be compliant MISRA 15.7) */ + } +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_FLASH_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_gpio.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_gpio.c new file mode 100644 index 0000000000..368ee4355d --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_gpio.c @@ -0,0 +1,663 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_gpio.c + * @author MCD Application Team + * @brief GPIO HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the General Purpose Input/Output (GPIO) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### GPIO Peripheral features ##### + ============================================================================== + [..] + (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually + configured by software in several modes: + (++) Input mode + (++) Analog mode + (++) Output mode + (++) Alternate function mode + (++) External interrupt/event lines + + (+) During and just after reset, the alternate functions and external interrupt + lines are not active and the I/O ports are configured in input floating mode. + + (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be + activated or not. + + (+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull + type and the IO speed can be selected depending on the VDD value. + + (+) The microcontroller IO pins are connected to onboard peripherals/modules through a + multiplexer that allows only one peripheral alternate function (AF) connected + to an IO pin at a time. In this way, there can be no conflict between peripherals + sharing the same IO pin. + + (+) All ports have external interrupt/event capability. To use external interrupt + lines, the port must be configured in input mode. All available GPIO pins are + connected to the 16 external interrupt/event lines from EXTI0 to EXTI15. + + (+) The external interrupt/event controller consists of up to 39 edge detectors + (16 lines are connected to GPIO) for generating event/interrupt requests (each + input line can be independently configured to select the type (interrupt or event) + and the corresponding trigger event (rising or falling or both). Each line can + also be masked independently. + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE(). + + (#) Configure the GPIO pin(s) using HAL_GPIO_Init(). + (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure + (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef + structure. + (++) In case of Output or alternate function mode selection: the speed is + configured through "Speed" member from GPIO_InitTypeDef structure. + (++) In alternate mode is selection, the alternate function connected to the IO + is configured through "Alternate" member from GPIO_InitTypeDef structure. + (++) Analog mode is required when a pin is to be used as ADC channel + or DAC output. + (++) In case of external interrupt/event selection the "Mode" member from + GPIO_InitTypeDef structure select the type (interrupt or event) and + the corresponding trigger event (rising or falling or both). + + (#) In case of external interrupt mode selection, configure NVIC IRQ priority + mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using + HAL_NVIC_EnableIRQ(). + When interrupt occurs, + (+) HAL_GPIO_EXTI_Rising_Callback() user callbacks will be executed : + (++) on rising edge detection. + (+) HAL_GPIO_EXTI_Rising_Callback() user callbacks will be executed : + (++) on falling edge detection. + + (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin(). + + (#) To set/reset the level of a pin configured in output mode use + HAL_GPIO_WritePin()/HAL_GPIO_TogglePin(). + + (#) To set the level of several pins and reset level of several other pins in + same cycle, use HAL_GPIO_WriteMultipleStatePin(). + + (#) To lock pin configuration until next reset use HAL_GPIO_LockPin(). + + (#) During and just after reset, the alternate functions are not + active and the GPIO pins are configured in input floating mode (except JTAG + pins). + + (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose + (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has + priority over the GPIO function. + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @addtogroup GPIO + * @{ + */ +/** MISRA C:2012 deviation rule has been granted for following rules: + * Rule-12.2 - Medium: RHS argument is in interval [0,INF] which is out of + * range of the shift operator in following API : + * HAL_GPIO_Init + * HAL_GPIO_DeInit + */ + +#ifdef HAL_GPIO_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines ------------------------------------------------------------*/ +/** @addtogroup GPIO_Private_Constants + * @{ + */ +#define GPIO_NUMBER (16U) +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup GPIO_Exported_Functions + * @{ + */ + +/** @addtogroup GPIO_Exported_Functions_Group1 + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init. + * @note If GPIOx peripheral pin is used in EXTI_MODE and the pin is secure in case + * the system implements the security (TZEN=1), it is up to the secure application to + * insure that the corresponding EXTI line is set secure. + * @param GPIOx where x can be (A..C, H). + * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains + * the configuration information for the specified GPIO peripheral. + * @retval None + */ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *GPIO_Init) +{ + uint32_t position = 0x00U; + uint32_t iocurrent; + uint32_t temp; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); + assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); + + /* Configure the port pins */ + while (((GPIO_Init->Pin) >> position) != 0x00U) + { + /* Get current io position */ + iocurrent = (GPIO_Init->Pin) & (1UL << position); + + if (iocurrent != 0x00U) + { + /*--------------------- GPIO Mode Configuration ------------------------*/ + /* In case of Output or Alternate function mode selection */ + if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) + { + /* Check the Speed parameter */ + assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); + + /* Configure the IO Speed */ + temp = GPIOx->OSPEEDR; + temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * GPIO_OSPEEDR_OSPEED1_Pos)); + temp |= (GPIO_Init->Speed << (position * GPIO_OSPEEDR_OSPEED1_Pos)); + GPIOx->OSPEEDR = temp; + + /* Configure the IO Output Type */ + temp = GPIOx->OTYPER; + temp &= ~(GPIO_OTYPER_OT0 << position) ; + temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); + GPIOx->OTYPER = temp; + } + + if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) + { + /* Check the Pull parameter */ + assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); + + /* Activate the Pull-up or Pull down resistor for the current IO */ + temp = GPIOx->PUPDR; + temp &= ~(GPIO_PUPDR_PUPD0 << (position * GPIO_PUPDR_PUPD1_Pos)); + temp |= ((GPIO_Init->Pull) << (position * GPIO_PUPDR_PUPD1_Pos)); + GPIOx->PUPDR = temp; + } + + /* In case of Alternate function mode selection */ + if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) + { + /* Check the Alternate function parameters */ + assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); + assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); + + /* Configure Alternate function mapped with the current IO */ + temp = GPIOx->AFR[position >> 3U]; + temp &= ~(0xFU << ((position & 0x07U) * GPIO_AFRL_AFSEL1_Pos)); + temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * GPIO_AFRL_AFSEL1_Pos)); + GPIOx->AFR[position >> 3U] = temp; + } + + /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + temp = GPIOx->MODER; + temp &= ~(GPIO_MODER_MODE0 << (position * GPIO_MODER_MODE1_Pos)); + temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * GPIO_MODER_MODE1_Pos)); + GPIOx->MODER = temp; + + /*--------------------- EXTI Mode Configuration ------------------------*/ + /* Configure the External Interrupt or event for the current IO */ + if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U) + { + temp = EXTI->EXTICR[position >> 2U]; + temp &= ~(0x0FUL << ((position & 0x03U) * EXTI_EXTICR1_EXTI1_Pos)); + temp |= (GPIO_GET_INDEX(GPIOx) << ((position & 0x03U) * EXTI_EXTICR1_EXTI1_Pos)); + EXTI->EXTICR[position >> 2U] = temp; + + /* Clear Rising Falling edge configuration */ + temp = EXTI->RTSR1; + temp &= ~(iocurrent); + if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) + { + temp |= iocurrent; + } + EXTI->RTSR1 = temp; + + temp = EXTI->FTSR1; + temp &= ~(iocurrent); + if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) + { + temp |= iocurrent; + } + EXTI->FTSR1 = temp; + + /* Clear EXTI line configuration */ + temp = EXTI->EMR1; + temp &= ~(iocurrent); + if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U) + { + temp |= iocurrent; + } + EXTI->EMR1 = temp; + + temp = EXTI->IMR1; + temp &= ~(iocurrent); + if ((GPIO_Init->Mode & EXTI_IT) != 0x00U) + { + temp |= iocurrent; + } + EXTI->IMR1 = temp; + } + } + + position++; + } +} + +/** + * @brief De-initialize the GPIOx peripheral registers to their default reset values. + * @param GPIOx where x can be (A..C, H). + * @param GPIO_Pin specifies the port bit to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval None + */ +void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) +{ + uint32_t position = 0x00U; + uint32_t iocurrent; + uint32_t tmp; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* Configure the port pins */ + while ((GPIO_Pin >> position) != 0x00U) + { + /* Get current io position */ + iocurrent = (GPIO_Pin) & (1UL << position); + + if (iocurrent != 0x00U) + { + /*------------------------- EXTI Mode Configuration --------------------*/ + /* Clear the External Interrupt or Event for the current IO */ + + tmp = EXTI->EXTICR[position >> 2U]; + tmp &= (0x0FUL << ((position & 0x03U) * EXTI_EXTICR1_EXTI1_Pos)); + if (tmp == (GPIO_GET_INDEX(GPIOx) << ((position & 0x03U) * EXTI_EXTICR1_EXTI1_Pos))) + { + /* Clear EXTI line configuration */ + EXTI->IMR1 &= ~(iocurrent); + EXTI->EMR1 &= ~(iocurrent); + + /* Clear Rising Falling edge configuration */ + EXTI->FTSR1 &= ~(iocurrent); + EXTI->RTSR1 &= ~(iocurrent); + + tmp = 0x0FUL << ((position & 0x03U) * EXTI_EXTICR1_EXTI1_Pos); + EXTI->EXTICR[position >> 2U] &= ~tmp; + } + + /*------------------------- GPIO Mode Configuration --------------------*/ + /* Configure IO in Analog Mode */ + GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * GPIO_MODER_MODE1_Pos)); + + /* Configure the default Alternate Function in current IO */ + GPIOx->AFR[position >> 3U] &= ~(0xFU << ((position & 0x07U) * GPIO_AFRL_AFSEL1_Pos)) ; + + /* Configure the default value for IO Speed */ + GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * GPIO_OSPEEDR_OSPEED1_Pos)); + + /* Configure the default value IO Output Type */ + GPIOx->OTYPER &= ~(GPIO_OTYPER_OT0 << position) ; + + /* Deactivate the Pull-up and Pull-down resistor for the current IO */ + GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * GPIO_PUPDR_PUPD1_Pos)); + } + + position++; + } +} + +/** + * @} + */ + +/** @addtogroup GPIO_Exported_Functions_Group2 + * @brief GPIO Read, Write, Toggle, Lock and EXTI management functions. + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Read the specified input port pin. + * @param GPIOx where x can be (A..C, H). + * @param GPIO_Pin specifies the port bit to read. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval The input port pin value. + */ +GPIO_PinState HAL_GPIO_ReadPin(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + GPIO_PinState bitstatus; + + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + if ((GPIOx->IDR & GPIO_Pin) != 0x00U) + { + bitstatus = GPIO_PIN_SET; + } + else + { + bitstatus = GPIO_PIN_RESET; + } + return bitstatus; +} + +/** + * @brief Set or clear the selected data port bit. + * @note This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify + * accesses. In this way, there is no risk of an IRQ occurring between + * the read and the modify access. + * @param GPIOx where x can be (A..C, H). + * @param GPIO_Pin specifies the port bit to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @param PinState specifies the value to be written to the selected bit. + * This parameter can be one of the GPIO_PinState enum values: + * @arg GPIO_PIN_RESET: to clear the port pin + * @arg GPIO_PIN_SET: to set the port pin + * @retval None + */ +void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) +{ + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_PIN_ACTION(PinState)); + + if (PinState != GPIO_PIN_RESET) + { + GPIOx->BSRR = (uint32_t)GPIO_Pin; + } + else + { + GPIOx->BRR = (uint32_t)GPIO_Pin; + } +} + +/** + * @brief Set and clear several pins of a dedicated port in same cycle. + * @param GPIOx where x can be (A..C, H). + * @param PinReset specifies the port bits to be reset + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15) or zero. + * @param PinSet specifies the port bits to be set + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15) or zero. + * @note Both PinReset and PinSet combinations shall not get any common bit, else + * assert would be triggered. + * @note At least one of the two parameters used to set or reset shall be different from zero. + * @retval None + */ +void HAL_GPIO_WriteMultipleStatePin(GPIO_TypeDef *GPIOx, uint16_t PinReset, uint16_t PinSet) +{ + uint32_t tmp; + + /* Check the parameters */ + /* Make sure at least one parameter is different from zero and that there is no common pin */ + assert_param(IS_GPIO_PIN((uint32_t)PinReset | (uint32_t)PinSet)); + assert_param(IS_GPIO_COMMON_PIN(PinReset, PinSet)); + + tmp = (((uint32_t)PinReset << 16) | PinSet); + GPIOx->BSRR = tmp; +} + +/** + * @brief Toggle the specified GPIO pin. + * @param GPIOx where x can be (A..C, H). + * @param GPIO_Pin specifies the pin to be toggled. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval None + */ +void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + uint32_t odr; + + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* get current Output Data Register value */ + odr = GPIOx->ODR; + + /* Set selected pins that were at low level, and reset ones that were high */ + GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin); +} + +/** + * @brief Lock GPIO Pins configuration registers. + * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, + * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. + * @note The configuration of the locked GPIO pins can no longer be modified + * until the next reset. + * @param GPIOx where x can be (A..C, H). + * @param GPIO_Pin specifies the port bits to be locked. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval None + */ +HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + __IO uint32_t tmp = GPIO_LCKR_LCKK; + + /* Check the parameters */ + assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* Apply lock key write sequence */ + tmp |= GPIO_Pin; + /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ + GPIOx->LCKR = tmp; + /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */ + GPIOx->LCKR = GPIO_Pin; + /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ + GPIOx->LCKR = tmp; + /* Read LCKK register. This read is mandatory to complete key lock sequence */ + tmp = GPIOx->LCKR; + + /* read again in order to confirm lock is active */ + if ((GPIOx->LCKR & GPIO_LCKR_LCKK) != 0x00U) + { + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Handle EXTI interrupt request. + * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. + * @retval None + */ +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) +{ + /* EXTI line interrupt detected */ + if (__HAL_GPIO_EXTI_GET_RISING_IT(GPIO_Pin) != 0x00U) + { + __HAL_GPIO_EXTI_CLEAR_RISING_IT(GPIO_Pin); + HAL_GPIO_EXTI_Rising_Callback(GPIO_Pin); + } + + if (__HAL_GPIO_EXTI_GET_FALLING_IT(GPIO_Pin) != 0x00U) + { + __HAL_GPIO_EXTI_CLEAR_FALLING_IT(GPIO_Pin); + HAL_GPIO_EXTI_Falling_Callback(GPIO_Pin); + } +} + +/** + * @brief EXTI line rising detection callback. + * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. + * @retval None + */ +__weak void HAL_GPIO_EXTI_Rising_Callback(uint16_t GPIO_Pin) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(GPIO_Pin); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_GPIO_EXTI_Rising_Callback could be implemented in the user file + */ +} + +/** + * @brief EXTI line falling detection callback. + * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. + * @retval None + */ +__weak void HAL_GPIO_EXTI_Falling_Callback(uint16_t GPIO_Pin) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(GPIO_Pin); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_GPIO_EXTI_Falling_Callback could be implemented in the user file + */ +} + +/** + * @} + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** @defgroup GPIO_Exported_Functions_Group3 IO attributes management functions + * @brief GPIO attributes management functions. + * +@verbatim + =============================================================================== + ##### IO attributes functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Configure the GPIO pins attributes. + * @note Available attributes are to secure GPIO pin(s), so this function is + * only available in secure + * @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32WBA family + * @param GPIO_Pin specifies the pin(s) to configure the secure attribute + * @param PinAttributes specifies the pin(s) to be set in secure mode, other being set non secured. + * @retval None + */ +void HAL_GPIO_ConfigPinAttributes(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, uint32_t PinAttributes) +{ + uint32_t sec; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_PIN_ATTRIBUTES(PinAttributes)); + + /* Configure the port pins */ + sec = GPIOx->SECCFGR; + if (PinAttributes != GPIO_PIN_NSEC) + { + sec |= (uint32_t)GPIO_Pin; + } + else + { + sec &= ~((uint32_t)GPIO_Pin); + } + + GPIOx->SECCFGR = sec; +} + +/** + * @brief Get the GPIO pins attributes. + * @note Available attributes are to secure GPIO pin(s), so this function is + * only available in secure + * @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32WBA family + * @param GPIO_Pin specifies the single pin to get the secure attribute from + * @param pPinAttributes pointer to return the pin attributes. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_GPIO_GetConfigPinAttributes(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, uint32_t *pPinAttributes) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_SINGLE_PIN(GPIO_Pin)); + + /* Check null pointer */ + if (pPinAttributes == NULL) + { + return HAL_ERROR; + } + + if ((GPIOx->SECCFGR & GPIO_Pin) != 0x00U) + { + *pPinAttributes = GPIO_PIN_SEC; + } + else + { + *pPinAttributes = GPIO_PIN_NSEC; + } + + return HAL_OK; +} + +/** + * @} + */ + +#endif /* __ARM_FEATURE_CMSE */ + + +/** + * @} + */ + +#endif /* HAL_GPIO_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_gtzc.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_gtzc.c new file mode 100644 index 0000000000..ae65a395a3 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_gtzc.c @@ -0,0 +1,1509 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_gtzc.c + * @author MCD Application Team + * @brief GTZC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of GTZC peripheral: + * + TZSC Initialization and Configuration functions + * + MPCBB Initialization and Configuration functions + * + TZSC and MPCBB Lock functions + * + TZIC Initialization and Configuration functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### GTZC main features ##### + ============================================================================== + [..] + (+) Global TrustZone Controller (GTZC) composed of three sub-blocks: + (++) TZSC: TrustZone security controller + This sub-block defines the secure/privileged state of master and slave + peripherals. + (++) MPCBB: Block-Based memory protection controller + This sub-block defines the secure/privileged state of all blocks + (512-byte pages) of the associated SRAM. + (++) TZIC: TrustZone illegal access controller + This sub-block gathers all illegal access events in the system and + generates a secure interrupt towards NVIC. + + (+) These sub-blocks are used to configure TrustZone system security in + a product having bus agents with programmable-security and privileged + attributes (securable) such as: + (++) on-chip RAM with programmable secure and/or privilege blocks (pages) + (++) AHB and APB peripherals with programmable security and/or privilege access + (++) AHB master granted as secure and/or privilege + (++) off-chip memories with secure and/or privilege areas + + [..] + (+) TZIC accessible only with secure privileged transactions. + (+) Secure and non-secure access supported for privileged and unprivileged + part of TZSC and MPCBB + (+) Set of registers to define product security settings: + (++) Secure and privilege blocks for internal memories + (++) Secure and privilege regions for external memories + (++) Secure and privileged access mode for securable peripherals + + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The GTZC HAL driver can be used as follows: + + (#) Configure or get back securable peripherals attributes using + HAL_GTZC_TZSC_ConfigPeriphAttributes() / HAL_GTZC_TZSC_GetConfigPeriphAttributes() + + (#) Lock TZSC sub-block or get lock status using HAL_GTZC_TZSC_Lock() / + HAL_GTZC_TZSC_GetLock() + + (#) Configure or get back MPCBB memories complete configuration using + HAL_GTZC_MPCBB_ConfigMem() / HAL_GTZC_MPCBB_GetConfigMem() + + (#) Configure or get back MPCBB memories attributes using + HAL_GTZC_MPCBB_ConfigMemAttributes() / HAL_GTZC_MPCBB_GetConfigMemAttributes() + + (#) Lock MPCBB configuration or get lock status using HAL_GTZC_MPCBB_Lock() / + HAL_GTZC_MPCBB_GetLock() + + (#) Lock MPCBB super-blocks or get lock status using HAL_GTZC_MPCBB_LockConfig() / + HAL_GTZC_MPCBB_GetLockConfig() + + (#) Illegal access detection can be configured through TZIC sub-block using + following functions: HAL_GTZC_TZIC_DisableIT() / HAL_GTZC_TZIC_EnableIT() + + (#) Illegal access flags can be retrieved through HAL_GTZC_TZIC_GetFlag() and + HAL_GTZC_TZIC_ClearFlag() functions + + (#) Illegal access interrupt service routines are served by HAL_GTZC_IRQHandler() + and user can add his own code using HAL_GTZC_TZIC_Callback() + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +#if defined(GTZC_TZSC) && defined(HAL_GTZC_MODULE_ENABLED) + +/** @defgroup GTZC GTZC + * @brief GTZC HAL module driver + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ + +/** @defgroup GTZC_Private_Constants GTZC Private Constants + * @{ + */ + +/* Definitions for GTZC TZSC & TZIC ALL register values */ +/* TZSC1 / TZIC1 instances */ +#if defined (STM32WBA54xx) || defined (STM32WBA55xx) +#define TZSC1_SECCFGR1_ALL (0x000222C3UL) +#define TZSC1_SECCFGR2_ALL (0x018F00EBUL) +#define TZSC1_SECCFGR3_ALL (0x01C17858UL) +#define TZIC1_IER4_ALL (0xC3C0EF87UL) +#else +#define TZSC1_SECCFGR1_ALL (0x000222C3UL) +#define TZSC1_SECCFGR2_ALL (0x010F006BUL) +#define TZSC1_SECCFGR3_ALL (0x00C17858UL) +#define TZIC1_IER4_ALL (0xC3C0EF87UL) +#endif /* STM32WBA54xx || STM32WBA55xx */ + +#define TZSC1_PRIVCFGR1_ALL TZSC1_SECCFGR1_ALL +#define TZSC1_PRIVCFGR2_ALL TZSC1_SECCFGR2_ALL +#define TZSC1_PRIVCFGR3_ALL TZSC1_SECCFGR3_ALL +#define TZIC1_IER1_ALL TZSC1_SECCFGR1_ALL +#define TZIC1_IER2_ALL TZSC1_SECCFGR2_ALL +#define TZIC1_IER3_ALL TZSC1_SECCFGR3_ALL +#define TZIC1_FCR1_ALL TZIC1_IER1_ALL +#define TZIC1_FCR2_ALL TZIC1_IER2_ALL +#define TZIC1_FCR3_ALL TZIC1_IER3_ALL +#define TZIC1_FCR4_ALL TZIC1_IER4_ALL +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ + +/** @defgroup GTZC_Private_Macros GTZC Private Macros + * @{ + */ + +#define IS_ADDRESS_IN(mem, address)\ + ( ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_NS(mem) ) \ + && ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_NS(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) ) \ + || ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_S(mem) ) \ + && ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_S(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) ) ) + +#define IS_ADDRESS_IN_S(mem, address)\ + ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_S(mem) ) \ + && ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_S(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) ) + +#define IS_ADDRESS_IN_NS(mem, address)\ + ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_NS(mem) ) \ + && ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_NS(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) ) + +/* MISRA C:2012 Rule-20.10 deviation granted to use the definition of GTZC_BASE_ADDRESS() */ +#define GTZC_BASE_ADDRESS(mem)\ + ( mem ## _BASE ) + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup GTZC_Exported_Functions GTZC Exported Functions + * @{ + */ + +/** @defgroup GTZC_Exported_Functions_Group1 TZSC Configuration functions + * @brief TZSC Configuration functions + * + @verbatim + ============================================================================== + ##### TZSC Configuration functions ##### + ============================================================================== + [..] + This section provides functions allowing to configure TZSC + TZSC: TrustZone Security Controller +@endverbatim + * @{ + */ + +/** + * @brief Configure TZSC on a single peripheral or on all peripherals. + * @note Secure and non-secure attributes can only be set from the secure + * state when the system implements the security (TZEN=1). + * @note Privilege and non-privilege attributes can only be set from the + * privilege state when TZEN=0 or TZEN=1 + * @note Security and privilege attributes can be set independently. + * @note Default state is non-secure and unprivileged access allowed. + * @param PeriphId Peripheral identifier + * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId. + * Use GTZC_PERIPH_ALL to select all peripherals. + * @param PeriphAttributes Peripheral attributes, see @ref GTZC_TZSC_PeriphAttributes. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GTZC_TZSC_ConfigPeriphAttributes(uint32_t PeriphId, + uint32_t PeriphAttributes) +{ + uint32_t register_address; + + /* check entry parameters */ + if ((PeriphAttributes > (GTZC_TZSC_PERIPH_SEC | GTZC_TZSC_PERIPH_PRIV)) + || (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZSC_PERIPH_NUMBER) + || (((PeriphId & GTZC_PERIPH_ALL) != 0U) + && (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U))) + { + return HAL_ERROR; + } + + if ((PeriphId & GTZC_PERIPH_ALL) != 0U) + { + /* special case where same attributes are applied to all peripherals */ + +#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + /* secure configuration */ + if ((PeriphAttributes & GTZC_TZSC_PERIPH_SEC) == GTZC_TZSC_PERIPH_SEC) + { + SET_BIT(GTZC_TZSC->SECCFGR1, TZSC1_SECCFGR1_ALL); + SET_BIT(GTZC_TZSC->SECCFGR2, TZSC1_SECCFGR2_ALL); + SET_BIT(GTZC_TZSC->SECCFGR3, TZSC1_SECCFGR3_ALL); + } + else if ((PeriphAttributes & GTZC_TZSC_PERIPH_NSEC) == GTZC_TZSC_PERIPH_NSEC) + { + CLEAR_BIT(GTZC_TZSC->SECCFGR1, TZSC1_SECCFGR1_ALL); + CLEAR_BIT(GTZC_TZSC->SECCFGR2, TZSC1_SECCFGR2_ALL); + CLEAR_BIT(GTZC_TZSC->SECCFGR3, TZSC1_SECCFGR3_ALL); + } + else + { + /* do nothing */ + } +#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + /* privilege configuration */ + if ((PeriphAttributes & GTZC_TZSC_PERIPH_PRIV) == GTZC_TZSC_PERIPH_PRIV) + { + SET_BIT(GTZC_TZSC->PRIVCFGR1, TZSC1_PRIVCFGR1_ALL); + SET_BIT(GTZC_TZSC->PRIVCFGR2, TZSC1_PRIVCFGR2_ALL); + SET_BIT(GTZC_TZSC->PRIVCFGR3, TZSC1_PRIVCFGR3_ALL); + } + else if ((PeriphAttributes & GTZC_TZSC_PERIPH_NPRIV) == GTZC_TZSC_PERIPH_NPRIV) + { + CLEAR_BIT(GTZC_TZSC->PRIVCFGR1, TZSC1_PRIVCFGR1_ALL); + CLEAR_BIT(GTZC_TZSC->PRIVCFGR2, TZSC1_PRIVCFGR2_ALL); + CLEAR_BIT(GTZC_TZSC->PRIVCFGR3, TZSC1_PRIVCFGR3_ALL); + } + else + { + /* do nothing */ + } + } + else + { + /* common case where only one peripheral is configured */ + +#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + /* secure configuration */ + register_address = (uint32_t) &(GTZC_TZSC->SECCFGR1) + + (4U * GTZC_GET_REG_INDEX(PeriphId)); + if ((PeriphAttributes & GTZC_TZSC_PERIPH_SEC) == GTZC_TZSC_PERIPH_SEC) + { + SET_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId)); + } + else if ((PeriphAttributes & GTZC_TZSC_PERIPH_NSEC) == GTZC_TZSC_PERIPH_NSEC) + { + CLEAR_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId)); + } + else + { + /* do nothing */ + } +#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + /* privilege configuration */ + register_address = (uint32_t) &(GTZC_TZSC->PRIVCFGR1) + + (4U * GTZC_GET_REG_INDEX(PeriphId)); + if ((PeriphAttributes & GTZC_TZSC_PERIPH_PRIV) == GTZC_TZSC_PERIPH_PRIV) + { + SET_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId)); + } + else if ((PeriphAttributes & GTZC_TZSC_PERIPH_NPRIV) == GTZC_TZSC_PERIPH_NPRIV) + { + CLEAR_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId)); + } + else + { + /* do nothing */ + } + } + return HAL_OK; +} + +/** + * @brief Get TZSC configuration on a single peripheral or on all peripherals. + * @param PeriphId Peripheral identifier. + * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId. + * Use GTZC_PERIPH_ALL to select all peripherals. + * @param PeriphAttributes Peripheral attribute pointer. + * This parameter can be a value of @ref GTZC_TZSC_PeriphAttributes. + * If PeriphId target a single peripheral, pointer on a single element. + * If all peripherals selected (GTZC_PERIPH_ALL), pointer to an array of + * GTZC_TZSC_PERIPH_NUMBER elements is to be provided. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GTZC_TZSC_GetConfigPeriphAttributes(uint32_t PeriphId, + uint32_t *PeriphAttributes) +{ + uint32_t i; + uint32_t reg_value; + uint32_t register_address; + + /* check entry parameters */ + if ((PeriphAttributes == NULL) + || (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZSC_PERIPH_NUMBER) + || (((PeriphId & GTZC_PERIPH_ALL) != 0U) + && (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U))) + { + return HAL_ERROR; + } + + if ((PeriphId & GTZC_PERIPH_ALL) != 0U) + { + /* get secure configuration: read each register and deploy each bit value + * of corresponding index in the destination array + */ + reg_value = READ_REG(GTZC_TZSC->SECCFGR1); + for (i = 0U; i < 32U; i++) + { + if (((reg_value & (1UL << i)) >> i) != 0U) + { + PeriphAttributes[i] = GTZC_TZSC_PERIPH_SEC; + } + else + { + PeriphAttributes[i] = GTZC_TZSC_PERIPH_NSEC; + } + } + + reg_value = READ_REG(GTZC_TZSC->SECCFGR2); + for (i = 32U; i < 64U; i++) + { + if (((reg_value & (1UL << (i - 32U))) >> (i - 32U)) != 0U) + { + PeriphAttributes[i] = GTZC_TZSC_PERIPH_SEC; + } + else + { + PeriphAttributes[i] = GTZC_TZSC_PERIPH_NSEC; + } + } + + reg_value = READ_REG(GTZC_TZSC->SECCFGR3); + for (i = 64U; i < GTZC_TZSC_PERIPH_NUMBER; i++) + { + if (((reg_value & (1UL << (i - 64U))) >> (i - 64U)) != 0U) + { + PeriphAttributes[i] = GTZC_TZSC_PERIPH_SEC; + } + else + { + PeriphAttributes[i] = GTZC_TZSC_PERIPH_NSEC; + } + } + + /* get privilege configuration: read each register and deploy each bit value + * of corresponding index in the destination array + */ + reg_value = READ_REG(GTZC_TZSC->PRIVCFGR1); + for (i = 0U; i < 32U; i++) + { + if (((reg_value & (1UL << i)) >> i) != 0U) + { + PeriphAttributes[i] |= GTZC_TZSC_PERIPH_PRIV; + } + else + { + PeriphAttributes[i] |= GTZC_TZSC_PERIPH_NPRIV; + } + } + + reg_value = READ_REG(GTZC_TZSC->PRIVCFGR2); + for (i = 32U; i < 64U; i++) + { + if (((reg_value & (1UL << (i - 32U))) >> (i - 32U)) != 0U) + { + PeriphAttributes[i] |= GTZC_TZSC_PERIPH_PRIV; + } + else + { + PeriphAttributes[i] |= GTZC_TZSC_PERIPH_NPRIV; + } + } + + reg_value = READ_REG(GTZC_TZSC->PRIVCFGR3); + for (i = 64U; i < GTZC_TZSC_PERIPH_NUMBER; i++) + { + if (((reg_value & (1UL << (i - 64U))) >> (i - 64U)) != 0U) + { + PeriphAttributes[i] |= GTZC_TZSC_PERIPH_PRIV; + } + else + { + PeriphAttributes[i] |= GTZC_TZSC_PERIPH_NPRIV; + } + } + + } + else + { + /* common case where only one peripheral is configured */ + + /* secure configuration */ + register_address = (uint32_t) &(GTZC_TZSC->SECCFGR1) + + (4U * GTZC_GET_REG_INDEX(PeriphId)); + + if (((READ_BIT(*(__IO uint32_t *)register_address, + 1UL << GTZC_GET_PERIPH_POS(PeriphId))) >> GTZC_GET_PERIPH_POS(PeriphId)) + != 0U) + { + *PeriphAttributes = GTZC_TZSC_PERIPH_SEC; + } + else + { + *PeriphAttributes = GTZC_TZSC_PERIPH_NSEC; + } + + /* privilege configuration */ + register_address = (uint32_t) &(GTZC_TZSC->PRIVCFGR1) + + (4U * GTZC_GET_REG_INDEX(PeriphId)); + if (((READ_BIT(*(__IO uint32_t *)register_address, + 1UL << GTZC_GET_PERIPH_POS(PeriphId))) >> GTZC_GET_PERIPH_POS(PeriphId)) + != 0U) + { + *PeriphAttributes |= GTZC_TZSC_PERIPH_PRIV; + } + else + { + *PeriphAttributes |= GTZC_TZSC_PERIPH_NPRIV; + } + } + return HAL_OK; +} + +/** + * @} + */ + +#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** @defgroup GTZC_Exported_Functions_Group3 TZSC Lock functions + * @brief TZSC Lock functions + * + @verbatim + ============================================================================== + ##### TZSC Lock functions ##### + ============================================================================== + [..] + This section provides functions allowing to manage the TZSC (TrustZone + Security Controller) lock. It includes lock enable, and current value read. +@endverbatim + * @{ + */ + +/** + * @brief Lock TZSC configuration. + * @note This function locks the configuration of TZSC_SECCFGRx and TZSC_PRIVCFGRx + * registers until next reset + * @param TZSC_Instance TZSC sub-block instance. + */ +void HAL_GTZC_TZSC_Lock(GTZC_TZSC_TypeDef *TZSC_Instance) +{ + SET_BIT(TZSC_Instance->CR, GTZC_TZSC_CR_LCK_Msk); +} + +/** + * @brief Get TZSC configuration lock state. + * @param TZSC_Instance TZSC sub-block instance. + * @retval Lock State (GTZC_TZSC_LOCK_OFF or GTZC_TZSC_LOCK_ON) + */ +uint32_t HAL_GTZC_TZSC_GetLock(const GTZC_TZSC_TypeDef *TZSC_Instance) +{ + return READ_BIT(TZSC_Instance->CR, GTZC_TZSC_CR_LCK_Msk); +} + +/** + * @} + */ +#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/** @defgroup GTZC_Exported_Functions_Group4 MPCBB Configuration functions + * @brief MPCBB Configuration functions + * + @verbatim + ============================================================================== + ##### MPCBB Configuration functions ##### + ============================================================================== + [..] + This section provides functions allowing to configure MPCBB + MPCBB is Memory Protection Controller Block Base +@endverbatim + * @{ + */ + +/** + * @brief Set a complete MPCBB configuration on the SRAM passed as parameter. + * @param MemBaseAddress MPCBB identifier. + * @param pMPCBB_desc pointer to MPCBB descriptor. + * The structure description is available in @ref GTZC_Exported_Types. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMem(uint32_t MemBaseAddress, + const MPCBB_ConfigTypeDef *pMPCBB_desc) +{ + GTZC_MPCBB_TypeDef *mpcbb_ptr; + uint32_t reg_value; + uint32_t mem_size; + uint32_t size_in_superblocks; + uint32_t i; +#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + uint32_t size_mask; +#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + /* check entry parameters */ + if ((!(IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress)) + && !(IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress)) + && !(IS_GTZC_BASE_ADDRESS(SRAM6, MemBaseAddress))) + || ((pMPCBB_desc->SecureRWIllegalMode + != GTZC_MPCBB_SRWILADIS_ENABLE) + && (pMPCBB_desc->SecureRWIllegalMode + != GTZC_MPCBB_SRWILADIS_DISABLE)) + || ((pMPCBB_desc->InvertSecureState + != GTZC_MPCBB_INVSECSTATE_NOT_INVERTED) + && (pMPCBB_desc->InvertSecureState + != GTZC_MPCBB_INVSECSTATE_INVERTED))) + { + return HAL_ERROR; + } + + /* write InvertSecureState and SecureRWIllegalMode properties */ + /* assume their Position/Mask is identical for all sub-blocks */ + reg_value = pMPCBB_desc->InvertSecureState; + reg_value |= pMPCBB_desc->SecureRWIllegalMode; + if (IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress)) + { + mpcbb_ptr = GTZC_MPCBB1; + mem_size = GTZC_MEM_SIZE(SRAM1); + } + else if (IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress)) + { + mpcbb_ptr = GTZC_MPCBB2; + mem_size = GTZC_MEM_SIZE(SRAM2); + } + else + { + /* Here MemBaseAddress is inside SRAM6 (parameter already checked) */ + mpcbb_ptr = GTZC_MPCBB6; + mem_size = GTZC_MEM_SIZE(SRAM6); + } + + /* translate mem_size in number of super-blocks */ + size_in_superblocks = (mem_size / GTZC_MPCBB_SUPERBLOCK_SIZE); + + /* write PRIVCFGR register information */ + for (i = 0U; i < size_in_superblocks; i++) + { + WRITE_REG(mpcbb_ptr->PRIVCFGR[i], + pMPCBB_desc->AttributeConfig.MPCBB_PrivConfig_array[i]); + } + +#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + /* write SECCFGR register information */ + for (i = 0U; i < size_in_superblocks; i++) + { + WRITE_REG(mpcbb_ptr->SECCFGR[i], + pMPCBB_desc->AttributeConfig.MPCBB_SecConfig_array[i]); + } + + /* write configuration and lock register information */ + MODIFY_REG(mpcbb_ptr->CR, + GTZC_MPCBB_CR_INVSECSTATE_Msk | GTZC_MPCBB_CR_SRWILADIS_Msk, reg_value); + size_mask = (1UL << size_in_superblocks) - 1U; + /* limitation: code not portable with memory > 512K */ + MODIFY_REG(mpcbb_ptr->CFGLOCK, size_mask, pMPCBB_desc->AttributeConfig.MPCBB_LockConfig_array[0]); +#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + return HAL_OK; +} + +/** + * @brief Get a complete MPCBB configuration on the SRAM passed as parameter. + * @param MemBaseAddress MPCBB identifier. + * @param pMPCBB_desc pointer to a MPCBB descriptor. + * The structure description is available in @ref GTZC_Exported_Types. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMem(uint32_t MemBaseAddress, + MPCBB_ConfigTypeDef *pMPCBB_desc) +{ + GTZC_MPCBB_TypeDef *mpcbb_ptr; + uint32_t mem_size; + uint32_t size_in_superblocks; + uint32_t i; + + /* check entry parameters */ + if (!(IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress)) + && !(IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress)) + && !(IS_GTZC_BASE_ADDRESS(SRAM6, MemBaseAddress))) + { + return HAL_ERROR; + } + + /* read InvertSecureState and SecureRWIllegalMode properties */ + /* assume their Position/Mask is identical for all sub-blocks */ + if (IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress)) + { + mpcbb_ptr = GTZC_MPCBB1; + mem_size = GTZC_MEM_SIZE(SRAM1); + } + else if (IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress)) + { + mpcbb_ptr = GTZC_MPCBB2; + mem_size = GTZC_MEM_SIZE(SRAM2); + } + else + { + mpcbb_ptr = GTZC_MPCBB6; + mem_size = GTZC_MEM_SIZE(SRAM6); + } + + /* translate mem_size in number of super-blocks */ + size_in_superblocks = (mem_size / GTZC_MPCBB_SUPERBLOCK_SIZE); + +#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + uint32_t reg_value; + uint32_t size_mask; + + /* read configuration and lock register information */ + reg_value = READ_REG(mpcbb_ptr->CR); + pMPCBB_desc->InvertSecureState = (reg_value & GTZC_MPCBB_CR_INVSECSTATE_Msk); + pMPCBB_desc->SecureRWIllegalMode = (reg_value & GTZC_MPCBB_CR_SRWILADIS_Msk); + size_mask = (1UL << size_in_superblocks) - 1U; + /* limitation: code not portable with memory > 512K */ + pMPCBB_desc->AttributeConfig.MPCBB_LockConfig_array[0] = READ_REG(mpcbb_ptr->CFGLOCK) + & size_mask; +#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + /* read SECCFGR / PRIVCFGR registers information */ + for (i = 0U; i < size_in_superblocks; i++) + { + pMPCBB_desc->AttributeConfig.MPCBB_SecConfig_array[i] = mpcbb_ptr->SECCFGR[i]; + pMPCBB_desc->AttributeConfig.MPCBB_PrivConfig_array[i] = mpcbb_ptr->PRIVCFGR[i]; + } + + return HAL_OK; +} + +/** + * @brief Set a MPCBB attribute configuration on the SRAM passed as parameter + * for a number of blocks. + * @param MemAddress MPCBB identifier, and start block to configure + * (must be 512 Bytes aligned). + * @param NbBlocks Number of blocks to configure + * (Block size is 512 Bytes). + * @param pMemAttributes pointer to an array (containing "NbBlocks" elements), + * with each element must be GTZC_MCPBB_BLOCK_NSEC or GTZC_MCPBB_BLOCK_SEC, + * and GTZC_MCPBB_BLOCK_NPRIV or GTZC_MCPBB_BLOCK_PRIV. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMemAttributes(uint32_t MemAddress, + uint32_t NbBlocks, + const uint32_t *pMemAttributes) +{ + GTZC_MPCBB_TypeDef *mpcbb_ptr; + uint32_t base_address; + uint32_t end_address; + uint32_t block_start; + uint32_t offset_reg_start; + uint32_t offset_bit_start; + uint32_t i; + uint32_t do_attr_change; + + /* firstly check that MemAddress is well 512 Bytes aligned */ + if ((MemAddress % GTZC_MPCBB_BLOCK_SIZE) != 0U) + { + return HAL_ERROR; + } + + /* check entry parameters and deduce physical base address */ + end_address = MemAddress + (NbBlocks * GTZC_MPCBB_BLOCK_SIZE) - 1U; + if (((IS_ADDRESS_IN_NS(SRAM1, MemAddress)) + && (IS_ADDRESS_IN_NS(SRAM1, end_address))) != 0U) + { + mpcbb_ptr = GTZC_MPCBB1; + base_address = SRAM1_BASE_NS; + } +#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + else if (((IS_ADDRESS_IN_S(SRAM1, MemAddress)) + && (IS_ADDRESS_IN_S(SRAM1, end_address))) != 0U) + { + mpcbb_ptr = GTZC_MPCBB1; + base_address = SRAM1_BASE_S; + } +#endif /* #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + else if (((IS_ADDRESS_IN_NS(SRAM2, MemAddress)) + && (IS_ADDRESS_IN_NS(SRAM2, end_address))) != 0U) + { + mpcbb_ptr = GTZC_MPCBB2; + base_address = SRAM2_BASE_NS; + } +#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + else if (((IS_ADDRESS_IN_S(SRAM2, MemAddress)) + && (IS_ADDRESS_IN_S(SRAM2, end_address))) != 0U) + { + mpcbb_ptr = GTZC_MPCBB2; + base_address = SRAM2_BASE_S; + } +#endif /* #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + else if (((IS_ADDRESS_IN_NS(SRAM6, MemAddress)) + && (IS_ADDRESS_IN_NS(SRAM6, end_address))) != 0U) + { + mpcbb_ptr = GTZC_MPCBB6; + base_address = SRAM6_BASE_NS; + } +#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + else if (((IS_ADDRESS_IN_S(SRAM6, MemAddress)) + && (IS_ADDRESS_IN_S(SRAM6, end_address))) != 0U) + { + mpcbb_ptr = GTZC_MPCBB6; + base_address = SRAM6_BASE_S; + } +#endif /* #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + else + { + return HAL_ERROR; + } + + /* get start coordinates of the configuration */ + block_start = (MemAddress - base_address) / GTZC_MPCBB_BLOCK_SIZE; + offset_reg_start = block_start / 32U; + offset_bit_start = block_start % 32U; + + for (i = 0U; i < NbBlocks; i++) + { + /* Indicate change done for protection attributes */ + do_attr_change = 0U; + +#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + /* secure configuration */ + if ((pMemAttributes[i] & GTZC_MCPBB_BLOCK_SEC) == GTZC_MCPBB_BLOCK_SEC) + { + SET_BIT(mpcbb_ptr->SECCFGR[offset_reg_start], + 1UL << (offset_bit_start % 32U)); + do_attr_change = 1U; + } + else if ((pMemAttributes[i] & GTZC_MCPBB_BLOCK_NSEC) == GTZC_MCPBB_BLOCK_NSEC) + { + CLEAR_BIT(mpcbb_ptr->SECCFGR[offset_reg_start], + 1UL << (offset_bit_start % 32U)); + do_attr_change = 1U; + } + else + { + /* nothing to do */ + } +#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + /* privilege configuration */ + if ((pMemAttributes[i] & GTZC_MCPBB_BLOCK_PRIV) == GTZC_MCPBB_BLOCK_PRIV) + { + SET_BIT(mpcbb_ptr->PRIVCFGR[offset_reg_start], + 1UL << (offset_bit_start % 32U)); + } + else if ((pMemAttributes[i] & GTZC_MCPBB_BLOCK_NPRIV) == GTZC_MCPBB_BLOCK_NPRIV) + { + CLEAR_BIT(mpcbb_ptr->PRIVCFGR[offset_reg_start], + 1UL << (offset_bit_start % 32U)); + } + else + { + /* if no change is done for security and privilege attributes: break the loop */ + if (do_attr_change == 0U) + { + break; + } + } + + offset_bit_start++; + if (offset_bit_start == 32U) + { + offset_bit_start = 0U; + offset_reg_start++; + } + } + + /* an unexpected value in pMemAttributes array leads to error status */ + if (i != NbBlocks) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Get a MPCBB attribute configuration on the SRAM passed as parameter + * for a number of blocks. + * @param MemAddress MPCBB identifier, and start block to get configuration + * (must be 512 Bytes aligned). + * @param NbBlocks Number of blocks to get configuration. + * @param pMemAttributes pointer to an array (containing "NbBlocks" elements), + * with each element will be GTZC_MCPBB_BLOCK_NSEC or GTZC_MCPBB_BLOCK_SEC, + * and GTZC_MCPBB_BLOCK_NPRIV or GTZC_MCPBB_BLOCK_PRIV. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMemAttributes(uint32_t MemAddress, + uint32_t NbBlocks, + uint32_t *pMemAttributes) +{ + GTZC_MPCBB_TypeDef *mpcbb_ptr; + uint32_t base_address; + uint32_t end_address; + uint32_t block_start; + uint32_t offset_reg_start; + uint32_t offset_bit_start; + uint32_t i; + + /* firstly check that MemAddress is well 512 Bytes aligned */ + if ((MemAddress % GTZC_MPCBB_BLOCK_SIZE) != 0U) + { + return HAL_ERROR; + } + + /* check entry parameters and deduce physical base address */ + end_address = MemAddress + (NbBlocks * GTZC_MPCBB_BLOCK_SIZE) - 1U; + if ((IS_ADDRESS_IN_NS(SRAM1, MemAddress)) + && (IS_ADDRESS_IN_NS(SRAM1, end_address))) + { + mpcbb_ptr = GTZC_MPCBB1_NS; + base_address = SRAM1_BASE_NS; + } +#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + else if ((IS_ADDRESS_IN_S(SRAM1, MemAddress)) + && (IS_ADDRESS_IN_S(SRAM1, end_address))) + { + mpcbb_ptr = GTZC_MPCBB1_S; + base_address = SRAM1_BASE_S; + } +#endif /* #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + else if ((IS_ADDRESS_IN_NS(SRAM2, MemAddress)) + && (IS_ADDRESS_IN_NS(SRAM2, end_address))) + { + mpcbb_ptr = GTZC_MPCBB2_NS; + base_address = SRAM2_BASE_NS; + } +#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + else if ((IS_ADDRESS_IN_S(SRAM2, MemAddress)) + && (IS_ADDRESS_IN_S(SRAM2, end_address))) + { + mpcbb_ptr = GTZC_MPCBB2_S; + base_address = SRAM2_BASE_S; + } +#endif /* #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + else if ((IS_ADDRESS_IN_NS(SRAM6, MemAddress)) + && (IS_ADDRESS_IN_NS(SRAM6, end_address))) + { + mpcbb_ptr = GTZC_MPCBB6_NS; + base_address = SRAM6_BASE_NS; + } +#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + else if ((IS_ADDRESS_IN_S(SRAM6, MemAddress)) + && (IS_ADDRESS_IN_S(SRAM6, end_address))) + { + mpcbb_ptr = GTZC_MPCBB6_S; + base_address = SRAM6_BASE_S; + } +#endif /* #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + else + { + return HAL_ERROR; + } + + /* get start coordinates of the configuration */ + block_start = (MemAddress - base_address) / GTZC_MPCBB_BLOCK_SIZE; + offset_reg_start = block_start / 32U; + offset_bit_start = block_start % 32U; + + for (i = 0U; i < NbBlocks; i++) + { + pMemAttributes[i] = (READ_BIT(mpcbb_ptr->SECCFGR[offset_reg_start], + 1UL << (offset_bit_start % 32U)) + >> (offset_bit_start % 32U)) | GTZC_ATTR_SEC_MASK; + pMemAttributes[i] |= (READ_BIT(mpcbb_ptr->PRIVCFGR[offset_reg_start], + 1UL << (offset_bit_start % 32U)) + >> (offset_bit_start % 32U)) | GTZC_ATTR_PRIV_MASK; + + offset_bit_start++; + if (offset_bit_start == 32U) + { + offset_bit_start = 0U; + offset_reg_start++; + } + } + + return HAL_OK; +} + +#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Lock MPCBB super-blocks on the SRAM passed as parameter. + * @param MemAddress MPCBB start-address of super-block to configure + * (must be 16KBytes aligned). + * @param NbSuperBlocks Number of super-blocks to configure. + * @param pLockAttributes pointer to an array (containing "NbSuperBlocks" elements), + * with for each element: + * value 0 super-block is unlocked, value 1 super-block is locked + * (corresponds to GTZC_MCPBB_SUPERBLOCK_UNLOCKED and + * GTZC_MCPBB_SUPERBLOCK_LOCKED values). + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GTZC_MPCBB_LockConfig(uint32_t MemAddress, + uint32_t NbSuperBlocks, + const uint32_t *pLockAttributes) +{ + __IO uint32_t *reg_mpcbb; + uint32_t base_address; + uint32_t superblock_start; + uint32_t offset_bit_start; + uint32_t i; + + /* firstly check that MemAddress is well 16KBytes aligned */ + if ((MemAddress % GTZC_MPCBB_SUPERBLOCK_SIZE) != 0U) + { + return HAL_ERROR; + } + + /* check entry parameters */ + if ((IS_ADDRESS_IN(SRAM1, MemAddress)) + && (IS_ADDRESS_IN(SRAM1, (MemAddress + + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE) + - 1U)))) + { + base_address = GTZC_BASE_ADDRESS(SRAM1); + /* limitation: code not portable with memory > 512K */ + reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB1_S->CFGLOCK; + } + else if ((IS_ADDRESS_IN(SRAM2, MemAddress)) + && (IS_ADDRESS_IN(SRAM2, (MemAddress + + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE) + - 1U)))) + { + base_address = GTZC_BASE_ADDRESS(SRAM2); + /* limitation: code not portable with memory > 512K */ + reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB2_S->CFGLOCK; + } + + else if ((IS_ADDRESS_IN(SRAM6, MemAddress)) + && (IS_ADDRESS_IN(SRAM6, (MemAddress + + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE) + - 1U)))) + { + base_address = GTZC_BASE_ADDRESS(SRAM6); + /* limitation: code not portable with memory > 512K */ + reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB6_S->CFGLOCK; + } + else + { + return HAL_ERROR; + } + + /* get start coordinates of the configuration */ + superblock_start = (MemAddress - base_address) / GTZC_MPCBB_SUPERBLOCK_SIZE; + offset_bit_start = superblock_start % 32U; + + for (i = 0U; i < NbSuperBlocks; i++) + { + if (pLockAttributes[i] == GTZC_MCPBB_SUPERBLOCK_LOCKED) + { + SET_BIT(*reg_mpcbb, 1UL << (offset_bit_start % 32U)); + } + else if (pLockAttributes[i] == GTZC_MCPBB_SUPERBLOCK_UNLOCKED) + { + CLEAR_BIT(*reg_mpcbb, 1UL << (offset_bit_start % 32U)); + } + else + { + break; + } + + offset_bit_start++; + } + + /* an unexpected value in pLockAttributes array leads to an error status */ + if (i != NbSuperBlocks) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Get MPCBB super-blocks lock configuration on the SRAM passed as parameter. + * @param MemAddress MPCBB start-address of super-block to get configuration + * (must be 16KBytes aligned). + * @param NbSuperBlocks Number of super-blocks to get configuration. + * @param pLockAttributes pointer to an array (containing "NbSuperBlocks" elements), + * with for each element: + * value 0 super-block is unlocked, value 1 super-block is locked + * (corresponds to GTZC_MCPBB_SUPERBLOCK_UNLOCKED and + * GTZC_MCPBB_SUPERBLOCK_LOCKED values). + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLockConfig(uint32_t MemAddress, + uint32_t NbSuperBlocks, + uint32_t *pLockAttributes) +{ + uint32_t reg_mpcbb; + uint32_t base_address; + uint32_t superblock_start; + uint32_t offset_bit_start; + uint32_t i; + + /* firstly check that MemAddress is well 16KBytes aligned */ + if ((MemAddress % GTZC_MPCBB_SUPERBLOCK_SIZE) != 0U) + { + return HAL_ERROR; + } + + /* check entry parameters */ + if ((IS_ADDRESS_IN(SRAM1, MemAddress)) + && (IS_ADDRESS_IN(SRAM1, (MemAddress + + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE) + - 1U)))) + { + base_address = GTZC_BASE_ADDRESS(SRAM1); + /* limitation: code not portable with memory > 512K */ + reg_mpcbb = GTZC_MPCBB1_S->CFGLOCK; + } + else if ((IS_ADDRESS_IN(SRAM2, MemAddress)) + && (IS_ADDRESS_IN(SRAM2, (MemAddress + + (NbSuperBlocks + * GTZC_MPCBB_SUPERBLOCK_SIZE) + - 1U)))) + { + base_address = GTZC_BASE_ADDRESS(SRAM2); + /* limitation: code not portable with memory > 512K */ + reg_mpcbb = GTZC_MPCBB2_S->CFGLOCK; + } + else if ((IS_ADDRESS_IN(SRAM6, MemAddress)) + && (IS_ADDRESS_IN(SRAM6, (MemAddress + + (NbSuperBlocks + * GTZC_MPCBB_SUPERBLOCK_SIZE) + - 1U)))) + { + base_address = GTZC_BASE_ADDRESS(SRAM6); + /* limitation: code not portable with memory > 512K */ + reg_mpcbb = GTZC_MPCBB6_S->CFGLOCK; + } + else + { + return HAL_ERROR; + } + + /* get start coordinates of the configuration */ + superblock_start = (MemAddress - base_address) / GTZC_MPCBB_SUPERBLOCK_SIZE; + offset_bit_start = superblock_start % 32U; + + for (i = 0U; i < NbSuperBlocks; i++) + { + pLockAttributes[i] = (reg_mpcbb & (1UL << (offset_bit_start % 32U))) + >> (offset_bit_start % 32U); + offset_bit_start++; + } + + return HAL_OK; +} + +/** + * @brief Lock a MPCBB configuration on the SRAM base address passed as parameter. + * @note This functions locks the control register of the MPCBB until next reset. + * @param MemBaseAddress MPCBB identifier. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GTZC_MPCBB_Lock(uint32_t MemBaseAddress) +{ + /* check entry parameters */ + if (IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress)) + { + SET_BIT(GTZC_MPCBB1_S->CR, GTZC_MPCBB_CR_GLOCK_Msk); + } + else if (IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress)) + { + SET_BIT(GTZC_MPCBB2_S->CR, GTZC_MPCBB_CR_GLOCK_Msk); + } + else if (IS_GTZC_BASE_ADDRESS(SRAM6, MemBaseAddress)) + { + SET_BIT(GTZC_MPCBB6_S->CR, GTZC_MPCBB_CR_GLOCK_Msk); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Get MPCBB configuration lock state on the SRAM base address passed as parameter. + * @param MemBaseAddress MPCBB identifier. + * @param pLockState pointer to Lock State (GTZC_MCPBB_LOCK_OFF or GTZC_MCPBB_LOCK_ON). + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLock(uint32_t MemBaseAddress, + uint32_t *pLockState) +{ + /* check entry parameters */ + if (IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress)) + { + *pLockState = READ_BIT(GTZC_MPCBB1_S->CR, GTZC_MPCBB_CR_GLOCK_Msk); + } + else if (IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress)) + { + *pLockState = READ_BIT(GTZC_MPCBB2_S->CR, GTZC_MPCBB_CR_GLOCK_Msk); + } + else if (IS_GTZC_BASE_ADDRESS(SRAM6, MemBaseAddress)) + { + *pLockState = READ_BIT(GTZC_MPCBB6_S->CR, GTZC_MPCBB_CR_GLOCK_Msk); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup GTZC_Exported_Functions_Group5 TZIC Configuration and Control functions + * @brief TZIC Configuration and Control functions + * + @verbatim + ============================================================================== + ##### TZIC Configuration and Control functions ##### + ============================================================================== + [..] + This section provides functions allowing to configure and control TZIC + TZIC is Trust Zone Interrupt Controller +@endverbatim + * @{ + */ + +/** + * @brief Disable the interrupt associated to a single TZIC peripheral or on all peripherals. + * @param PeriphId Peripheral identifier. + * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId. + * Use GTZC_PERIPH_ALL to select all peripherals. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GTZC_TZIC_DisableIT(uint32_t PeriphId) +{ + uint32_t register_address; + + /* check entry parameters */ + if ((HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZIC_PERIPH_NUMBER) + || (((PeriphId & GTZC_PERIPH_ALL) != 0U) + && (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U))) + { + return HAL_ERROR; + } + + if ((PeriphId & GTZC_PERIPH_ALL) != 0U) + { + /* same configuration is applied to all peripherals */ + WRITE_REG(GTZC_TZIC->IER1, 0U); + WRITE_REG(GTZC_TZIC->IER2, 0U); + WRITE_REG(GTZC_TZIC->IER3, 0U); + WRITE_REG(GTZC_TZIC->IER4, 0U); + } + else + { + /* common case where only one peripheral is configured */ + register_address = (uint32_t) &(GTZC_TZIC->IER1) + + (4U * GTZC_GET_REG_INDEX(PeriphId)); + CLEAR_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId)); + } + + return HAL_OK; +} + +/** + * @brief Enable the interrupt associated to a single TZIC peripheral or on all peripherals. + * @param PeriphId Peripheral identifier. + * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId. + * Use GTZC_PERIPH_ALL to select all peripherals. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GTZC_TZIC_EnableIT(uint32_t PeriphId) +{ + uint32_t register_address; + + /* check entry parameters */ + if ((HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZIC_PERIPH_NUMBER) + || (((PeriphId & GTZC_PERIPH_ALL) != 0U) + && (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U))) + { + return HAL_ERROR; + } + + if ((PeriphId & GTZC_PERIPH_ALL) != 0U) + { + /* same configuration is applied to all peripherals */ + WRITE_REG(GTZC_TZIC->IER1, TZIC1_IER1_ALL); + WRITE_REG(GTZC_TZIC->IER2, TZIC1_IER2_ALL); + WRITE_REG(GTZC_TZIC->IER3, TZIC1_IER3_ALL); + WRITE_REG(GTZC_TZIC->IER4, TZIC1_IER4_ALL); + } + else + { + /* common case where only one peripheral is configured */ + register_address = (uint32_t) &(GTZC_TZIC->IER1) + + (4U * GTZC_GET_REG_INDEX(PeriphId)); + SET_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId)); + } + + return HAL_OK; +} + +/** + * @brief Get TZIC flag on a single TZIC peripheral or on all peripherals. + * @param PeriphId Peripheral identifier. + * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId. + * Use GTZC_PERIPH_ALL to select all peripherals. + * @param pFlag Pointer to the flags. + * If PeriphId target a single peripheral, pointer on a single element. + * If all peripherals selected (GTZC_PERIPH_ALL), pointer to an array + * of GTZC_TZIC_PERIPH_NUMBER elements. + * Element content is either GTZC_TZIC_NO_ILA_EVENT + * or GTZC_TZSC_ILA_EVENT_PENDING. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_GTZC_TZIC_GetFlag(uint32_t PeriphId, uint32_t *pFlag) +{ + uint32_t i; + uint32_t reg_value; + uint32_t register_address; + + /* check entry parameters */ + if ((HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZIC_PERIPH_NUMBER) + || (((PeriphId & GTZC_PERIPH_ALL) != 0U) + && (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U))) + { + return HAL_ERROR; + } + + if ((PeriphId & GTZC_PERIPH_ALL) != 0U) + { + /* special case where it is applied to all peripherals */ + reg_value = READ_REG(GTZC_TZIC->SR1); + for (i = 0U; i < 32U; i++) + { + pFlag[i] = (reg_value & (1UL << i)) >> i; + } + + reg_value = READ_REG(GTZC_TZIC->SR2); + for (i = 32U; i < 64U; i++) + { + pFlag[i] = (reg_value & (1UL << (i - 32U))) >> (i - 32U); + } + + reg_value = READ_REG(GTZC_TZIC->SR3); + for (i = 64; i < 96U; i++) + { + pFlag[i] = (reg_value & (1UL << (i - 64U))) >> (i - 64U); + } + + reg_value = READ_REG(GTZC_TZIC->SR4); + for (i = 96U; i < 128U; i++) + { + pFlag[i] = (reg_value & (1UL << (i - 96U))) >> (i - 96U); + } + } + else + { + /* common case where only one peripheral is concerned */ + register_address = (uint32_t) &(GTZC_TZIC->SR1) + + (4U * GTZC_GET_REG_INDEX(PeriphId)); + *pFlag = READ_BIT(*(__IO uint32_t *)register_address, + 1UL << GTZC_GET_PERIPH_POS(PeriphId)) >> GTZC_GET_PERIPH_POS(PeriphId); + } + + return HAL_OK; +} + +/** + * @brief Clear TZIC flag on a single TZIC peripheral or on all peripherals. + * @param PeriphId Peripheral identifier. + * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId. + * Use GTZC_PERIPH_ALL to select all peripherals. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_GTZC_TZIC_ClearFlag(uint32_t PeriphId) +{ + uint32_t register_address; + + /* check entry parameters */ + if ((HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZIC_PERIPH_NUMBER) + || (((PeriphId & GTZC_PERIPH_ALL) != 0U) + && (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U))) + { + return HAL_ERROR; + } + + if ((PeriphId & GTZC_PERIPH_ALL) != 0U) + { + /* same configuration is applied to all peripherals */ + WRITE_REG(GTZC_TZIC->FCR1, TZIC1_FCR1_ALL); + WRITE_REG(GTZC_TZIC->FCR2, TZIC1_FCR2_ALL); + WRITE_REG(GTZC_TZIC->FCR3, TZIC1_FCR3_ALL); + WRITE_REG(GTZC_TZIC->FCR4, TZIC1_FCR4_ALL); + } + else + { + /* common case where only one peripheral is configured */ + register_address = (uint32_t) &(GTZC_TZIC->FCR1) + + (4U * GTZC_GET_REG_INDEX(PeriphId)); + SET_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId)); + } + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup GTZC_Exported_Functions_Group6 IRQ related functions + * @brief IRQ related functions + * + @verbatim + ============================================================================== + ##### TZIC IRQ Handler and Callback functions ##### + ============================================================================== + [..] + This section provides functions allowing to treat ISR and provide user callback + @endverbatim + * @{ + */ + +/** + * @brief This function handles GTZC TZIC interrupt request. + * @retval None. + */ +void HAL_GTZC_IRQHandler(void) +{ + uint32_t position; + uint32_t flag; + uint32_t ier_itsources; + uint32_t sr_flags; + + /*********************************************************************/ + /****************************** TZIC1 ******************************/ + /*********************************************************************/ + + /* Get current IT Flags and IT sources value on 1st register of TZIC1 */ + ier_itsources = READ_REG(GTZC_TZIC_S->IER1); + sr_flags = READ_REG(GTZC_TZIC_S->SR1); + + /* Get Mask interrupt and then clear them */ + flag = ier_itsources & sr_flags; + if (flag != 0U) + { + WRITE_REG(GTZC_TZIC_S->FCR1, flag); + + /* Loop on flag to check, which ones have been raised */ + position = 0U; + while ((flag >> position) != 0U) + { + if ((flag & (1UL << position)) != 0U) + { + HAL_GTZC_TZIC_Callback(GTZC_PERIPH_REG1 | position); + } + + /* Position bit to be updated */ + position++; + } + } + + /* Get current IT Flags and IT sources value on 2nd register of TZIC1 */ + ier_itsources = READ_REG(GTZC_TZIC_S->IER2); + sr_flags = READ_REG(GTZC_TZIC_S->SR2); + + /* Get Mask interrupt and then clear them */ + flag = ier_itsources & sr_flags; + if (flag != 0U) + { + WRITE_REG(GTZC_TZIC_S->FCR2, flag); + + /* Loop on flag to check, which ones have been raised */ + position = 0U; + while ((flag >> position) != 0U) + { + if ((flag & (1UL << position)) != 0U) + { + HAL_GTZC_TZIC_Callback(GTZC_PERIPH_REG2 | position); + } + + /* Position bit to be updated */ + position++; + } + } + + /* Get current IT Flags and IT sources value on 3rd register of TZIC1 */ + ier_itsources = READ_REG(GTZC_TZIC_S->IER3); + sr_flags = READ_REG(GTZC_TZIC_S->SR3); + + /* Get Mask interrupt and then clear them */ + flag = ier_itsources & sr_flags; + if (flag != 0U) + { + WRITE_REG(GTZC_TZIC_S->FCR3, flag); + + /* Loop on flag to check, which ones have been raised */ + position = 0U; + while ((flag >> position) != 0U) + { + if ((flag & (1UL << position)) != 0U) + { + HAL_GTZC_TZIC_Callback(GTZC_PERIPH_REG3 | position); + } + + /* Position bit to be updated */ + position++; + } + } + + /* Get current IT Flags and IT sources value on 4th register of TZIC1 */ + ier_itsources = READ_REG(GTZC_TZIC_S->IER4); + sr_flags = READ_REG(GTZC_TZIC_S->SR4); + + /* Get Mask interrupt and then clear them */ + flag = ier_itsources & sr_flags; + if (flag != 0U) + { + WRITE_REG(GTZC_TZIC_S->FCR4, flag); + + /* Loop on flag to check, which ones have been raised */ + position = 0U; + while ((flag >> position) != 0U) + { + if ((flag & (1UL << position)) != 0U) + { + HAL_GTZC_TZIC_Callback(GTZC_PERIPH_REG4 | position); + } + + /* Position bit to be updated */ + position++; + } + } + +} + +/** + * @brief GTZC TZIC sub-block interrupt callback. + * @param PeriphId Peripheral identifier triggering the illegal access. + * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId + * @retval None. + */ +__weak void HAL_GTZC_TZIC_Callback(uint32_t PeriphId) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(PeriphId); + + /* NOTE: This function should not be modified. When the callback is needed, + * the HAL_GTZC_TZIC_Callback is to be implemented in the user file + */ +} + +/** + * @} + */ + +#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(GTZC_TZSC) && defined(HAL_GTZC_MODULE_ENABLED) */ + +/** + * @} + */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_hash.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_hash.c new file mode 100644 index 0000000000..802757f48e --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_hash.c @@ -0,0 +1,3073 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_hash.c + * @author MCD Application Team + * @brief HASH HAL module driver. + * This file provides firmware functions to manage HASH peripheral + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + The HASH HAL driver can be used as follows: + + (#)Initialize the HASH low level resources by implementing the HAL_HASH_MspInit(): + (##) Enable the HASH interface clock using __HAL_RCC_HASH_CLK_ENABLE() + (##) When resorting to interrupt-based APIs (e.g. HAL_HASH_Start_IT()) + (+++) Configure the HASH interrupt priority using HAL_NVIC_SetPriority() + (+++) Enable the HASH IRQ handler using HAL_NVIC_EnableIRQ() + (+++) In HASH IRQ handler, call HAL_HASH_IRQHandler() API + (##) When resorting to DMA-based APIs (e.g. HAL_HASH_Start_DMA()) + (+++) Enable the DMA interface clock + (+++) Configure and enable one DMA to manage data transfer from + memory to peripheral (input DMA). Managing data transfer from + peripheral to memory can be performed only using CPU. + (+++) Associate the initialized DMA handle to the HASH DMA handle + using __HAL_LINKDMA() + (+++) Configure the priority and enable the NVIC for the transfer complete + interrupt on the DMA: use + HAL_NVIC_SetPriority() and + HAL_NVIC_EnableIRQ() + + (#)Initialize the HASH HAL using HAL_HASH_Init(). This function: + (##) resorts to HAL_HASH_MspInit() for low-level initialization, + (##) configures the data type: no swap, half word swap, bit swap or byte swap, + (##) configures the Algorithm : MD5, SHA1 or SHA2 + + (#)Three processing schemes are available: + (##) Polling mode: processing APIs are blocking functions + i.e. they process the data and wait till the digest computation is finished, + e.g. HAL_HASH_Start() for HASH or HAL_HMAC_Start() for HMAC + (##) Interrupt mode: processing APIs are not blocking functions + i.e. they process the data under interrupt, + e.g. HAL_HASH_Start_IT() for HASH or HAL_HMAC_Start_IT() for HMAC + (##) DMA mode: processing APIs are not blocking functions and the CPU is + not used for data transfer i.e. the data transfer is ensured by DMA, + e.g. HAL_HASH_Start_DMA() for HASH or HAL_HMAC_Start_DMA() for HMAC. + + (#)When the processing function is called after HAL_HASH_Init(), the HASH peripheral is + initialized and processes the buffer fed in input. When the input data have all been + fed to the Peripheral, the digest computation can start. + + (#)Multi-buffer processing HASH and HMAC are possible in polling, interrupt and DMA modes. + (##) In polling mode, API HAL_HASH_Accumulate()/HAL_HASH_HMAC_Accumulate() must be called + for each input buffer, except for the last one. + User must resort to HAL_HASH_AccumulateLast()/HAL_HASH_HMAC_AccumulateLast() + to enter the last one and retrieve as well the computed digest. + + (##) In interrupt mode, API HAL_HASH_Accumulate_IT()/HAL_HASH_HMAC_Accumulate_IT() must + be called for each input buffer, except for the last one. + User must resort to HAL_HASH_AccumulateLast_IT()/HAL_HASH_HMAC_AccumulateLast_IT() + to enter the last one and retrieve as well the computed digest. + + (##) In DMA mode, once initialization is done, MDMAT bit must be set through + __HAL_HASH_SET_MDMAT() macro. + From that point, each buffer can be fed to the Peripheral through HAL_HASH_Start_DMA() API + for HASH and HAL_HASH_HMAC_Start_DMA() API for HMAC . + Before entering the last buffer, reset the MDMAT bit with __HAL_HASH_RESET_MDMAT() + macro then wrap-up the HASH processing in feeding the last input buffer through the + same API HAL_HASH_Start_DMA()for HASH and HAL_HASH_HMAC_Start_DMA() API for HMAC and + retrieve as well the computed digest. + + (#)To use this driver (version 2.0.0) with application developed with old driver (version 1.0.0) user have to: + (##) Add Algorithm as parameter like DataType or KeySize. + (##) Use new API HAL_HASH_Start() for HASH and HAL_HASH_HMAC_Start() for HMAC processing instead of old API + like HAL_HASH_SHA1_Start and HAL_HMAC_SHA1_Start. + + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal.h" + + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +#if defined (HASH) + +/** @defgroup HASH HASH + * @brief HASH HAL module driver. + * @{ + */ + +#ifdef HAL_HASH_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup HASH_Private_Defines HASH Private Defines + * @{ + */ +#define HASH_TIMEOUTVALUE 1000U /*!< Time-out value */ +#define BLOCK_64B 64U /*!< block Size equal to 64 bytes */ +#define BLOCK_128B 128U /*!< block Size equal to 128 bytes */ +/** + * @} + */ + +/** @defgroup HASH_Number_Of_CSR_Registers HASH Number of Context Swap Registers + * @{ + */ +#define HASH_NUMBER_OF_CSR_REGISTERS 54U /*!< Number of Context Swap Registers */ +/** + * @} + */ + +/* Private Constants ---------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup HASH_Private_Functions HASH Private Functions + * @{ + */ +static void HASH_GetDigest(const HASH_HandleTypeDef *hhash, const uint8_t *pMsgDigest, uint8_t Size); +static void HASH_WriteData(HASH_HandleTypeDef *hhash, const uint8_t *pInBuffer, uint32_t Size); +static HAL_StatusTypeDef HASH_WriteData_IT(HASH_HandleTypeDef *hhash); +static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma); +static void HASH_DMAError(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, uint32_t Flag, FlagStatus Status, + uint32_t Timeout); +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup HASH_Exported_Functions HASH Exported Functions + * @{ + */ + +/** @defgroup HASH_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and configuration functions. + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize the HASH according to the specified parameters + in the HASH_InitTypeDef and create the associated handle + (+) DeInitialize the HASH peripheral + (+) Initialize the HASH MCU Specific Package (MSP) + (+) DeInitialize the HASH MSP + (+) Configure HASH (HAL_HASH_SetConfig) with the specified parameters in the HASH_ConfigTypeDef + Parameters which are configured in This section are : + (+) Data Type : no swap, half word swap, bit swap or byte swap + (+) Algorithm : MD5,SHA1 or SHA2 + (+) Get HASH configuration (HAL_HASH_GetConfig) from the specified parameters in the HASH_HandleTypeDef + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the HASH according to the specified parameters in the + HASH_HandleTypeDef and create the associated handle. + * @note Only Algorithm and DATATYPE bits of HASH Peripheral are set by HAL_HASH_Init(), + * other configuration bits are set by HASH or HMAC processing APIs. + * @param hhash pointer to a HASH_HandleTypeDef structure that contains + * the configuration information for HASH module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash) +{ + uint32_t cr_value; + + /* Check the hash handle allocation */ + if (hhash == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_HASH_DATATYPE(hhash->Init.DataType)); + assert_param(IS_HASH_ALGORITHM(hhash->Init.Algorithm)); + +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) + if (hhash->State == HAL_HASH_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hhash->Lock = HAL_UNLOCKED; + + /* Reset Callback pointers in HAL_HASH_STATE_RESET only */ + hhash->InCpltCallback = HAL_HASH_InCpltCallback; /* Legacy weak InCpltCallback */ + hhash->DgstCpltCallback = HAL_HASH_DgstCpltCallback; /* Legacy weak DgstCpltCallback */ + hhash->ErrorCallback = HAL_HASH_ErrorCallback; /* Legacy weak ErrorCallback */ + if (hhash->MspInitCallback == NULL) + { + hhash->MspInitCallback = HAL_HASH_MspInit; + } + + /* Init the low level hardware */ + hhash->MspInitCallback(hhash); + } +#else + if (hhash->State == HAL_HASH_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hhash->Lock = HAL_UNLOCKED; + + /* Init the low level hardware */ + HAL_HASH_MspInit(hhash); + } +#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */ + + /* Set the key size, data type and Algorithm */ + cr_value = (uint32_t)(hhash->Init.DataType | hhash->Init.Algorithm); + /* Set the key size, data type, algorithm and mode */ + MODIFY_REG(hhash->Instance->CR, HASH_CR_DATATYPE | HASH_CR_ALGO | HASH_CR_INIT, cr_value); + + /* Change HASH phase to Ready */ + hhash->Phase = HAL_HASH_PHASE_READY; + + /* Change HASH state to Ready */ + hhash->State = HAL_HASH_STATE_READY; + + /* Reset error code field */ + hhash->ErrorCode = HAL_HASH_ERROR_NONE; + +#if (USE_HAL_HASH_SUSPEND_RESUME == 1U) + /* Reset suspension request flag */ + hhash->SuspendRequest = HAL_HASH_SUSPEND_NONE; +#endif /* (USE_HAL_HASH_SUSPEND_RESUME) */ + /* Return function status */ + return HAL_OK; +} + +/** + * @brief DeInitialize the HASH peripheral. + * @param hhash pointer to a HASH_HandleTypeDef structure that contains + * the configuration information for HASH module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash) +{ + /* Check the HASH handle allocation */ + if (hhash == NULL) + { + return HAL_ERROR; + } + + /* Change the default HASH phase */ + hhash->Phase = HAL_HASH_PHASE_READY; + + /* Reset HashInCount */ + hhash->HashInCount = 0U; + + /* Reset multi buffers accumulation flag */ + hhash->Accumulation = 0U; + +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) + if (hhash->MspDeInitCallback == NULL) + { + hhash->MspDeInitCallback = HAL_HASH_MspDeInit; + } + + /* DeInit the low level hardware */ + hhash->MspDeInitCallback(hhash); +#else + /* DeInit the low level hardware: CLOCK, NVIC */ + HAL_HASH_MspDeInit(hhash); +#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */ + + /* Set the HASH state to Ready */ + hhash->State = HAL_HASH_STATE_RESET; + + __HAL_UNLOCK(hhash); + + return HAL_OK; +} + +/** + * @brief Configure the HASH according to the specified + * parameters in the HASH_ConfigTypeDef + * @param hhash pointer to a HASH_HandleTypeDef structure + * @param pConf pointer to a HASH_ConfigTypeDef structure that contains + * the configuration information for HASH module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HASH_SetConfig(HASH_HandleTypeDef *hhash, HASH_ConfigTypeDef *pConf) +{ + uint32_t cr_value; + + /* Check the HASH handle allocation */ + if ((hhash == NULL) || (pConf == NULL)) + { + return HAL_ERROR; + } + + /* Check parameters */ + assert_param(IS_HASH_DATATYPE(pConf->DataType)); + assert_param(IS_HASH_ALGORITHM(pConf->Algorithm)); + + if (hhash->State == HAL_HASH_STATE_READY) + { + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_BUSY; + __HAL_LOCK(hhash); + + /* Set HASH parameters */ + hhash->Init.DataType = pConf->DataType; + hhash->Init.pKey = pConf->pKey; + hhash->Init.Algorithm = pConf->Algorithm; + hhash->Init.KeySize = pConf->KeySize; + + /* Set the key size, data type and Algorithm */ + cr_value = (uint32_t)(hhash->Init.DataType | hhash->Init.Algorithm); + /* Set the key size, data type, algorithm and mode */ + MODIFY_REG(hhash->Instance->CR, HASH_CR_DATATYPE | HASH_CR_ALGO | HASH_CR_INIT, cr_value); + + /* Change HASH phase to Ready */ + hhash->Phase = HAL_HASH_PHASE_READY; + + /* Change HASH state to Ready */ + hhash->State = HAL_HASH_STATE_READY; + + /* Reset error code field */ + hhash->ErrorCode = HAL_HASH_ERROR_NONE; + + __HAL_UNLOCK(hhash); + + return HAL_OK; + + } + else + { + /* Busy error code field */ + hhash->ErrorCode |= HAL_HASH_ERROR_BUSY; + return HAL_ERROR; + } +} + +/** + * @brief Get HASH Configuration parameters in associated handle + * @param pConf pointer to a HASH_HandleTypeDef structure + * @param hhash pointer to a HASH_ConfigTypeDef structure that contains + * the configuration information for HASH module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HASH_GetConfig(HASH_HandleTypeDef *hhash, HASH_ConfigTypeDef *pConf) +{ + + /* Check the HASH handle allocation */ + if ((hhash == NULL) || (pConf == NULL)) + { + return HAL_ERROR; + } + + if (hhash->State == HAL_HASH_STATE_READY) + { + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_BUSY; + __HAL_LOCK(hhash); + + /* Set HASH parameters */ + pConf->DataType = hhash->Init.DataType; + pConf->pKey = hhash->Init.pKey; + pConf->Algorithm = hhash->Init.Algorithm; + pConf->KeySize = hhash->Init.KeySize; + + /* Change HASH state to Ready */ + hhash->State = HAL_HASH_STATE_READY; + __HAL_UNLOCK(hhash); + + return HAL_OK; + + } + else + { + /* Busy error code field */ + hhash->ErrorCode |= HAL_HASH_ERROR_BUSY; + return HAL_ERROR; + } +} + +/** + * @brief Initialize the HASH MSP. + * @param hhash pointer to a HASH_HandleTypeDef structure that contains + * the configuration information for HASH module. + * @retval None + */ +__weak void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhash); + + /* NOTE : This function should not be modified; when the callback is needed, + HAL_HASH_MspInit() can be implemented in the user file. + */ +} + +/** + * @brief DeInitialize the HASH MSP. + * @param hhash pointer to a HASH_HandleTypeDef structure that contains + * the configuration information for HASH module. + * @retval None + */ +__weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhash); + + /* NOTE : This function should not be modified; when the callback is needed, + HAL_HASH_MspDeInit() can be implemented in the user file. + */ +} + + +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User HASH Callback + * To be used instead of the weak (overridden) predefined callback + * @param hhash HASH handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg HAL_HASH_INPUTCPLT_CB_ID input completion callback ID + * @arg HAL_HASH_DGSTCPLT_CB_ID digest computation completion callback ID + * @arg HAL_HASH_ERROR_CB_ID error callback ID + * @arg HAL_HASH_MSPINIT_CB_ID MspInit callback ID + * @arg HAL_HASH_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_HASH_RegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID, + pHASH_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + if (hhash->State == HAL_HASH_STATE_READY) + { + switch (CallbackID) + { + case HAL_HASH_INPUTCPLT_CB_ID : + hhash->InCpltCallback = pCallback; + break; + + case HAL_HASH_DGSTCPLT_CB_ID : + hhash->DgstCpltCallback = pCallback; + break; + + case HAL_HASH_ERROR_CB_ID : + hhash->ErrorCallback = pCallback; + break; + + case HAL_HASH_MSPINIT_CB_ID : + hhash->MspInitCallback = pCallback; + break; + + case HAL_HASH_MSPDEINIT_CB_ID : + hhash->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (hhash->State == HAL_HASH_STATE_RESET) + { + switch (CallbackID) + { + case HAL_HASH_MSPINIT_CB_ID : + hhash->MspInitCallback = pCallback; + break; + + case HAL_HASH_MSPDEINIT_CB_ID : + hhash->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister a HASH Callback + * HASH Callback is redirected to the weak (overridden) predefined callback + * @param hhash HASH handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg HAL_HASH_INPUTCPLT_CB_ID HASH input completion Callback ID + * @arg HAL_HASH_DGSTCPLT_CB_ID HASH digest computation completion Callback ID + * @arg HAL_HASH_ERROR_CB_ID HASH error Callback ID + * @arg HAL_HASH_MSPINIT_CB_ID HASH MspInit callback ID + * @arg HAL_HASH_MSPDEINIT_CB_ID HASH MspDeInit callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + + if (hhash->State == HAL_HASH_STATE_READY) + { + switch (CallbackID) + { + case HAL_HASH_INPUTCPLT_CB_ID : + hhash->InCpltCallback = HAL_HASH_InCpltCallback; /* Legacy weak input completion callback */ + break; + + case HAL_HASH_DGSTCPLT_CB_ID : + hhash->DgstCpltCallback = HAL_HASH_DgstCpltCallback; /* Legacy weak digest computation + completion callback */ + break; + + case HAL_HASH_ERROR_CB_ID : + hhash->ErrorCallback = HAL_HASH_ErrorCallback; /* Legacy weak error callback */ + break; + + case HAL_HASH_MSPINIT_CB_ID : + hhash->MspInitCallback = HAL_HASH_MspInit; /* Legacy weak MspInit Callback */ + break; + + case HAL_HASH_MSPDEINIT_CB_ID : + hhash->MspDeInitCallback = HAL_HASH_MspDeInit; /* Legacy weak MspDeInit Callback */ + break; + + default : + /* Update the error code */ + hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (hhash->State == HAL_HASH_STATE_RESET) + { + switch (CallbackID) + { + case HAL_HASH_MSPINIT_CB_ID : + hhash->MspInitCallback = HAL_HASH_MspInit; /* Legacy weak MspInit Callback */ + break; + + case HAL_HASH_MSPDEINIT_CB_ID : + hhash->MspDeInitCallback = HAL_HASH_MspDeInit; /* Legacy weak MspDeInit Callback */ + break; + + default : + /* Update the error code */ + hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + return status; +} +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ + +#if (USE_HAL_HASH_SUSPEND_RESUME == 1U) +/** + * @brief Save the HASH context in case of processing suspension. + * @param hhash HASH handle. + * @param pMemBuffer pointer to the memory buffer where the HASH context + * is saved. + * @note The IMR, STR, CR then all the CSR registers are saved + * in that order. Only the r/w bits are read to be restored later on. + * @note By default, all the context swap registers (there are + * HASH_NUMBER_OF_CSR_REGISTERS of those) are saved. + * @note pMemBuffer points to a buffer allocated by the user. The buffer size + * must be at least (HASH_NUMBER_OF_CSR_REGISTERS + 3) * 4 uint8 long. + * @retval None + */ +void HAL_HASH_Suspend(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer) +{ + uint32_t mem_ptr = (uint32_t)pMemBuffer; + uint32_t csr_ptr = (uint32_t)(hhash->Instance->CSR); + uint32_t i; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhash); + + /* Save IMR register content */ + *(uint32_t *)(mem_ptr) = READ_BIT(hhash->Instance->IMR, HASH_IT_DINI | HASH_IT_DCI); + mem_ptr += 4U; + /* Save STR register content */ + *(uint32_t *)(mem_ptr) = READ_BIT(hhash->Instance->STR, HASH_STR_NBLW); + mem_ptr += 4U; + /* Save CR register content */ + *(uint32_t *)(mem_ptr) = READ_BIT(hhash->Instance->CR, HASH_CR_DMAE | HASH_CR_DATATYPE | HASH_CR_MODE | HASH_CR_ALGO | + HASH_CR_LKEY | HASH_CR_MDMAT); + + mem_ptr += 4U; + /* By default, save all CSRs registers */ + for (i = HASH_NUMBER_OF_CSR_REGISTERS; i > 0U; i--) + { + *(uint32_t *)(mem_ptr) = *(uint32_t *)(csr_ptr); + mem_ptr += 4U; + csr_ptr += 4U; + } + /* Save low-priority block HASH handle parameters */ + hhash->Init_saved = hhash->Init; + hhash->pHashOutBuffPtr_saved = hhash->pHashOutBuffPtr; + hhash->HashInCount_saved = hhash->HashInCount; + hhash->Size_saved = hhash->Size; + hhash->pHashInBuffPtr_saved = hhash->pHashInBuffPtr; + hhash->Phase_saved = hhash->Phase; + hhash->pHashKeyBuffPtr_saved = hhash->pHashKeyBuffPtr; +} + + +/** + * @brief Restore the HASH context in case of processing resumption. + * @param hhash HASH handle. + * @param pMemBuffer pointer to the memory buffer where the HASH context + * is stored. + * @note The IMR, STR, CR then all the CSR registers are restored + * in that order. Only the r/w bits are restored. + * @note By default, all the context swap registers (HASH_NUMBER_OF_CSR_REGISTERS + * of those) are restored (all of them have been saved by default + * beforehand). + * @retval None + */ +void HAL_HASH_Resume(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer) +{ + uint32_t mem_ptr = (uint32_t)pMemBuffer; + uint32_t csr_ptr = (uint32_t)(hhash->Instance->CSR); + uint32_t i; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhash); + + /* Restore IMR register content */ + WRITE_REG(hhash->Instance->IMR, (*(uint32_t *)(mem_ptr))); + mem_ptr += 4U; + /* Restore STR register content */ + WRITE_REG(hhash->Instance->STR, (*(uint32_t *)(mem_ptr))); + mem_ptr += 4U; + /* Restore CR register content */ + WRITE_REG(hhash->Instance->CR, (*(uint32_t *)(mem_ptr))); + mem_ptr += 4U; + + /* Reset the HASH processor before restoring the Context + Swap Registers (CSR) */ + SET_BIT(hhash->Instance->CR, HASH_CR_INIT); + + + /* By default, restore all CSR registers */ + for (i = HASH_NUMBER_OF_CSR_REGISTERS; i > 0U; i--) + { + WRITE_REG((*(uint32_t *)(csr_ptr)), (*(uint32_t *)(mem_ptr))); + mem_ptr += 4U; + csr_ptr += 4U; + } + + /* Restore low-priority block HASH handle parameters */ + hhash->Init = hhash->Init_saved; + hhash->pHashOutBuffPtr = hhash->pHashOutBuffPtr_saved; + hhash->HashInCount = hhash->HashInCount_saved; + hhash->Size = hhash->Size_saved; + hhash->pHashInBuffPtr = hhash->pHashInBuffPtr_saved; + hhash->Phase = hhash->Phase_saved; + hhash->State = HAL_HASH_STATE_SUSPENDED; + hhash->pHashKeyBuffPtr = hhash->pHashKeyBuffPtr_saved; +} + +/** + * @brief Initiate HASH processing suspension when in interruption mode. + * @param hhash HASH handle. + * @note Set the handle field SuspendRequest to the appropriate value so that + * the on-going HASH processing is suspended as soon as the required + * conditions are met. Note that the actual suspension is carried out + * by the functions HASH_WriteData() in polling mode and HASH_IT() in + * interruption mode. + * @retval None + */ +HAL_StatusTypeDef HAL_HASH_ProcessSuspend(HASH_HandleTypeDef *hhash) +{ + uint32_t remainingwords; /*remaining number in of source block to be transferred.*/ + uint32_t nbbytePartialHash = (((hhash->Instance->SR) >> 16U) * 4U); /* Nb byte to enter in HASH fifo + to trig a partial HASH computation*/ + uint32_t sizeinwords;/* number in word of source block to be transferred.*/ + + /* suspension in DMA mode*/ + if (__HAL_HASH_GET_FLAG(hhash, HASH_FLAG_DMAS) != RESET) + { + if (hhash->State == HAL_HASH_STATE_READY) + { + return HAL_ERROR; + } + else + { + + /* Clear the DMAE bit to disable the DMA interface */ + CLEAR_BIT(HASH->CR, HASH_CR_DMAE); + + /* Wait until the last DMA transfer is complete (DMAS = 0 in the HASH_SR register) */ + if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DMAS, SET, HASH_TIMEOUTVALUE) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* At this point, DMA interface is disabled and no transfer is on-going */ + /* Retrieve from the DMA handle how many words remain to be written */ + /* DMA3 used, DMA_CBR1_BNDT in bytes, DMA_CSR_FIFOL in words */ + remainingwords = ((((DMA_Channel_TypeDef *)hhash->hdmain->Instance)->CBR1) \ + & DMA_CBR1_BNDT) / 4U; + remainingwords += ((((DMA_Channel_TypeDef *)hhash->hdmain->Instance)->CSR) \ + & DMA_CSR_FIFOL) >> DMA_CSR_FIFOL_Pos; + + if (remainingwords <= nbbytePartialHash) + { + /* No suspension attempted since almost to the end of the transferred data. */ + /* Best option for user code is to wrap up low priority message hashing */ + return HAL_ERROR; + } + + /* Disable DMA channel */ + /* Note that the Abort function will + - Clear the transfer error flags + - Unlock + - Set the State + */ + if (HAL_DMA_Abort(hhash->hdmain) != HAL_OK) + { + return HAL_ERROR; + } + + if (__HAL_HASH_GET_FLAG(hhash, HASH_FLAG_DCIS) != RESET) + { + return HAL_ERROR; + } + + /* Wait until the hash processor is ready (no block is being processed), that is wait for DINIS=1 in HASH_SR */ + if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DINIS, RESET, HASH_TIMEOUTVALUE) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Compute how many words were supposed to be transferred by DMA */ + sizeinwords = (((hhash->Size % 4U) != 0U) ? \ + ((hhash->Size + 3U) / 4U) : (hhash->Size / 4U)); + /* Accordingly, update the input pointer that points at the next word to be + transferred to the Peripheral by DMA */ + hhash->pHashInBuffPtr += 4U * (sizeinwords - remainingwords) ; + + /* And store in HashInCount the remaining size to transfer (in bytes) */ + hhash->HashInCount = 4U * remainingwords; + + + hhash->State = HAL_HASH_STATE_SUSPENDED; + __HAL_UNLOCK(hhash); + return HAL_OK; + } + + } + else /* suspension when in interruption mode*/ + { + /* Set Handle Suspend Request field */ + hhash->SuspendRequest = HAL_HASH_SUSPEND; + return HAL_OK; + } +} +#endif /* USE_HAL_HASH_SUSPEND_RESUME */ +/** + * @} + */ + + +/** @defgroup HASH_Exported_Functions_Group2 HASH processing functions + * @brief HASH processing functions using different mode. + * +@verbatim + =============================================================================== + ##### HASH processing functions ##### + =============================================================================== + [..] This section provides API allowing to calculate the hash value using + one of the HASH algorithms supported by the peripheral. + + [..] For a single buffer to be hashed, user can resort to one of three processing + functions available . + (+) Polling mode : HAL_HASH_Start() + (+) Interrupt mode : HAL_HASH_Start_IT() + (+) DMA mode : HAL_HASH_Start_DMA() + + [..] In case of multi-buffer HASH processing (a single digest is computed while + several buffers are fed to the Peripheral), the user can resort to successive calls + to : + (+) Polling mode : HAL_HASH_Accumulate() and wrap-up the digest computation by a call + to HAL_HASH_AccumulateLast() + (+) Interrupt mode : HAL_HASH_Accumulate_IT() and wrap-up the digest computation by a call + to HAL_HASH_AccumulateLast_IT() + (+) DMA mode : HAL_HASH_Start_DMA(), MDMAT bit must be set through __HAL_HASH_SET_MDMAT() macro, + before entering the last buffer, reset the MDMAT bit with __HAL_HASH_RESET_MDMAT() + macro then wrap-up the HASH processing in feeding the last input buffer through the + same API HAL_HASH_Start_DMA() + +@endverbatim + * @{ + */ + +/** + * @brief HASH peripheral processes in polling mode pInBuffer then reads the computed digest. + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes. + * @param pOutBuffer pointer to the computed digest. + * @param Timeout specify timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HASH_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *const pOutBuffer, uint32_t Timeout) +{ + /* Check the hash handle allocation */ + if (hhash == NULL) + { + return HAL_ERROR; + } + + /* Check if peripheral is ready to start process */ + if (hhash->State == HAL_HASH_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hhash); + + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_BUSY; + + /* Reset HashInCount and Initialize Size, pHashInBuffPtr and pHashOutBuffPtr parameters */ + hhash->pHashInBuffPtr = pInBuffer; + hhash->pHashOutBuffPtr = pOutBuffer; + hhash->HashInCount = 0U; + hhash->Size = Size; + + /* Set HASH mode */ + CLEAR_BIT(hhash->Instance->CR, HASH_CR_MODE); + /* Reset the HASH processor core */ + MODIFY_REG(hhash->Instance->CR, HASH_CR_INIT, HASH_CR_INIT); + + /* Configure the number of valid bits in last word of the message */ + MODIFY_REG(hhash->Instance->STR, HASH_STR_NBLW, 8U * (Size % 4U)); + + /* Set the phase */ + hhash->Phase = HAL_HASH_PHASE_PROCESS; + + HASH_WriteData(hhash, pInBuffer, Size); + + /* Start the message padding then the Digest calculation */ + SET_BIT(hhash->Instance->STR, HASH_STR_DCAL); + + /* Wait for digest calculation completion status(DCIS) flag to be set */ + if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DCIS, RESET, Timeout) != HAL_OK) + { + return HAL_ERROR; + } + + /* Read the message digest */ + HASH_GetDigest(hhash, pOutBuffer, HASH_DIGEST_LENGTH(hhash)); + + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_READY; + + /* Reset HASH state machine */ + hhash->Phase = HAL_HASH_PHASE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hhash); + + /* Return function status */ + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + + +/** + * @brief HASH peripheral processes in interrupt mode pInBuffer then reads the computed digest. + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes. + * @param pOutBuffer pointer to the computed digest. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HASH_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *const pOutBuffer) +{ + HAL_StatusTypeDef status; + HAL_HASH_StateTypeDef temp_state; + + /* Check the hash handle allocation */ + if (hhash == NULL) + { + return HAL_ERROR; + } + + /* Check if peripheral is ready to start process or suspended */ + temp_state = hhash->State; + if ((temp_state == HAL_HASH_STATE_READY) || (temp_state == HAL_HASH_STATE_SUSPENDED)) + { + /* Process Locked */ + __HAL_LOCK(hhash); + + if (hhash->State == HAL_HASH_STATE_READY) + { + /* Reset HashInCount and Initialize Size, pHashInBuffPtr and pHashOutBuffPtr parameters */ + hhash->HashInCount = 0U; + hhash->pHashInBuffPtr = pInBuffer; + hhash->pHashOutBuffPtr = pOutBuffer; + hhash->Size = Size; + + /* Set HASH mode */ + CLEAR_BIT(hhash->Instance->CR, HASH_CR_MODE); + /* Reset the HASH processor core */ + MODIFY_REG(hhash->Instance->CR, HASH_CR_INIT, HASH_CR_INIT); + + /* Configure the number of valid bits in last word of the message */ + MODIFY_REG(hhash->Instance->STR, HASH_STR_NBLW, 8U * (Size % 4U)); + } + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_BUSY; + /* Set the phase */ + hhash->Phase = HAL_HASH_PHASE_PROCESS; + + /* Enable the specified HASH interrupt*/ + __HAL_HASH_ENABLE_IT(hhash, HASH_IT_DINI | HASH_IT_DCI); + + status = HASH_WriteData_IT(hhash); + } + else + { + status = HAL_BUSY; + } + /* Return function status */ + return status; +} + +/** + * @brief HASH peripheral processes in DMA mode pInBuffer then reads the computed digest. + * @note Multi-buffer HASH processing is possible, consecutive calls to HAL_HASH_Start_DMA + * (MDMAT bit must be set) can be used to feed several input buffers + * back-to-back to the Peripheral that will yield a single + * HASH signature once all buffers have been entered. Wrap-up of input + * buffers feeding and retrieval of digest is done by a call to + * HAL_HASH_Start_DMA (MDMAT bit must be reset). + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes (must be a multiple of 4 in + * case of Multi-buffer and not last buffer). + * @param pOutBuffer pointer to the computed digest. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HASH_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *const pOutBuffer) +{ + HAL_StatusTypeDef status; + HAL_HASH_StateTypeDef temp_state; + + /* Check the hash handle allocation */ + if (hhash == NULL) + { + return HAL_ERROR; + } + + /* Check if peripheral is ready to start process or suspended */ + temp_state = hhash->State; + if ((temp_state == HAL_HASH_STATE_READY) || (temp_state == HAL_HASH_STATE_SUSPENDED)) + { + + /* Process Locked */ + __HAL_LOCK(hhash); + + /* Check if initialization phase has not been already performed */ + if (hhash->State == HAL_HASH_STATE_READY) + { + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_BUSY; + + /* Reset HashInCount and Initialize Size, pHashInBuffPtr and pHashOutBuffPtr parameters */ + hhash->HashInCount = 0U; + hhash->pHashInBuffPtr = pInBuffer; + hhash->pHashOutBuffPtr = pOutBuffer; + hhash->HashInCount = 0U; + hhash->Size = Size; + + /* Check if initialization phase has already been performed. + If Phase is already set to HAL_HASH_PHASE_PROCESS, this means the + API is processing a new input data message in case of multi-buffer HASH + computation. */ + if (hhash->Phase == HAL_HASH_PHASE_READY) + { + /* Set HASH mode */ + CLEAR_BIT(hhash->Instance->CR, HASH_CR_MODE); + /* Reset the HASH processor core */ + MODIFY_REG(hhash->Instance->CR, HASH_CR_INIT, HASH_CR_INIT); + + /* Set the phase */ + hhash->Phase = HAL_HASH_PHASE_PROCESS; + } + /* Configure the number of valid bits in last word of the message */ + if ((hhash->Instance->CR & HASH_CR_MDMAT) == 0U) + { + /* Configure the number of valid bits in last word of the message */ + MODIFY_REG(hhash->Instance->STR, HASH_STR_NBLW, 8U * ((hhash->Size) % 4U)); + } + else + { + /* Configure the number of valid bits in last word of the message */ + MODIFY_REG(hhash->Instance->STR, HASH_STR_NBLW, 0U); + } + + } + else /* HAL_HASH_STATE_SUSPENDED */ + { + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_BUSY; + /*only part not yet hashed to compute */ + hhash->Size = hhash->HashInCount; + } + /* Set the HASH DMA transfer complete callback */ + hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt; + /* Set the DMA error callback */ + hhash->hdmain->XferErrorCallback = HASH_DMAError; + + if ((hhash->hdmain->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if ((hhash->hdmain->LinkedListQueue != NULL) && (hhash->hdmain->LinkedListQueue->Head != NULL)) + { + /* Enable the DMA channel */ + hhash->hdmain->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET]\ + = ((((hhash->Size) % 4U) != 0U) ? ((hhash->Size) + (4U - ((hhash->Size) % 4U))) : (hhash->Size)); + hhash->hdmain->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET]\ + = (uint32_t)(hhash->pHashInBuffPtr); /* Set DMA source address */ + hhash->hdmain->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET]\ + = (uint32_t)&hhash->Instance->DIN; /* Set DMA destination address */ + + status = HAL_DMAEx_List_Start_IT(hhash->hdmain); + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + } + else + { + status = HAL_DMA_Start_IT(hhash->hdmain, (uint32_t)pInBuffer, (uint32_t)&hhash->Instance->DIN, \ + ((((hhash->Size) % 4U) != 0U) ? ((hhash->Size) + (4U - ((hhash->Size) % 4U))) : \ + (hhash->Size))); + } + if (status != HAL_OK) + { + /* DMA error code field */ + hhash->ErrorCode |= HAL_HASH_ERROR_DMA; + + /* Return error */ +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U) + /*Call registered error callback*/ + hhash->ErrorCallback(hhash); +#else + /*Call legacy weak error callback*/ + HAL_HASH_ErrorCallback(hhash); +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ + } + else + { + /* Enable DMA requests */ + SET_BIT(hhash->Instance->CR, HASH_CR_DMAE); + } + } + else + { + status = HAL_BUSY; + + } + + /* Return function status */ + return status; +} + + +/** + * @brief HASH peripheral processes in polling mode several input buffers. + * @note Consecutive calls to HAL_HASH_Accumulate() can be used to feed + * several input buffers back-to-back to the Peripheral that will yield a single + * HASH signature once all buffers have been entered. Wrap-up of input + * buffers feeding and retrieval of digest is done by a call to + * HAL_HASH_AccumulateLast() + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes and a multiple of 4. + * @param Timeout specify timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HASH_Accumulate(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint32_t Timeout) +{ + HAL_HASH_StateTypeDef temp_state; + + /* Check the hash handle allocation and buffer length multiple of 4 */ + if ((hhash == NULL) || ((Size % 4U) != 0U)) + { + return HAL_ERROR; + } + + /* Check if peripheral is ready to start process or suspended */ + temp_state = hhash->State; + if ((temp_state == HAL_HASH_STATE_READY) || (temp_state == HAL_HASH_STATE_SUSPENDED)) + { + /* Process Locked */ + __HAL_LOCK(hhash); + + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_BUSY; + + /* Reset HashInCount and Initialize Size, pHashInBuffPtr and pHashOutBuffPtr parameters */ + hhash->pHashInBuffPtr = pInBuffer; + hhash->HashInCount = 0U; + hhash->Size = Size; + + if (hhash->Phase == HAL_HASH_PHASE_READY) + { + /* Set HASH mode */ + CLEAR_BIT(hhash->Instance->CR, HASH_CR_MODE); + /* Reset the HASH processor core */ + MODIFY_REG(hhash->Instance->CR, HASH_CR_INIT, HASH_CR_INIT); + + /* Set the phase */ + hhash->Phase = HAL_HASH_PHASE_PROCESS; + } + HASH_WriteData(hhash, pInBuffer, Size); + + /* Wait for BUSY flag to be cleared */ + if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, Timeout) != HAL_OK) + { + return HAL_ERROR; + } + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hhash); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + + +/** + * @brief End computation of a single HASH signature after several calls to HAL_HASH_Accumulate() API. + * @note Digest is available in pOutBuffer + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes. + * @param pOutBuffer pointer to the computed digest. + * @param Timeout specify timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HASH_AccumulateLast(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *const pOutBuffer, uint32_t Timeout) +{ + HAL_HASH_StateTypeDef temp_state; + + /* Check the hash handle allocation */ + if (hhash == NULL) + { + return HAL_ERROR; + } + + /* Check if peripheral is ready to start process or suspended */ + temp_state = hhash->State; + if ((temp_state == HAL_HASH_STATE_READY) || (temp_state == HAL_HASH_STATE_SUSPENDED)) + { + /* Process Locked */ + __HAL_LOCK(hhash); + + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_BUSY; + + /* Reset HashInCount and Initialize Size, pHashInBuffPtr and pHashOutBuffPtr parameters */ + hhash->pHashInBuffPtr = pInBuffer; + hhash->pHashOutBuffPtr = pOutBuffer; + hhash->HashInCount = 0U; + hhash->Size = Size; + + if (hhash->Phase == HAL_HASH_PHASE_READY) + { + /* Set HASH mode */ + CLEAR_BIT(hhash->Instance->CR, HASH_CR_MODE); + /* Reset the HASH processor core */ + MODIFY_REG(hhash->Instance->CR, HASH_CR_INIT, HASH_CR_INIT); + + /* Set the phase */ + hhash->Phase = HAL_HASH_PHASE_PROCESS; + } + /* Configure the number of valid bits in last word of the message */ + MODIFY_REG(hhash->Instance->STR, HASH_STR_NBLW, 8U * (Size % 4U)); + + + HASH_WriteData(hhash, pInBuffer, Size); + + /* Start the message padding then the Digest calculation */ + SET_BIT(hhash->Instance->STR, HASH_STR_DCAL); + + /* Wait for digest calculation completion status(DCIS) flag to be set */ + if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DCIS, RESET, Timeout) != HAL_OK) + { + return HAL_ERROR; + } + /* Read the message digest */ + HASH_GetDigest(hhash, pOutBuffer, HASH_DIGEST_LENGTH(hhash)); + + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_READY; + + /* Reset HASH state machine */ + hhash->Phase = HAL_HASH_PHASE_READY; + hhash->Accumulation = 0; + /* Process Unlocked */ + __HAL_UNLOCK(hhash); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief HASH peripheral processes in interrupt mode several input buffers. + * @note Consecutive calls to HAL_HASH_Accumulate_IT() can be used to feed + * several input buffers back-to-back to the Peripheral that will yield a single + * HASH signature once all buffers have been entered. Wrap-up of input + * buffers feeding and retrieval of digest is done by a call to + * HAL_HASH_AccumulateLast_IT() + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes and a multiple of 4. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) +{ + HAL_StatusTypeDef status; + + /* Check the hash handle allocation */ + if ((hhash == NULL) || ((Size % 4U) != 0U)) + { + return HAL_ERROR; + } + + /* Check if peripheral is ready to start process */ + if (hhash->State == HAL_HASH_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hhash); + + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_BUSY; + + /* Reset HashInCount and Initialize Size and pHashInBuffPtr parameters */ + hhash->pHashInBuffPtr = pInBuffer; + hhash->HashInCount = 0U; + hhash->Size = Size; + /* Set multi buffers accumulation flag */ + hhash->Accumulation = 1U; + + if (hhash->Phase == HAL_HASH_PHASE_READY) + { + /* Set HASH mode */ + CLEAR_BIT(hhash->Instance->CR, HASH_CR_MODE); + /* Reset the HASH processor core */ + MODIFY_REG(hhash->Instance->CR, HASH_CR_INIT, HASH_CR_INIT); + /* Set the phase */ + hhash->Phase = HAL_HASH_PHASE_PROCESS; + } + /* Enable the specified HASH interrupt*/ + __HAL_HASH_ENABLE_IT(hhash, HASH_IT_DINI); + + status = HASH_WriteData_IT(hhash); + + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hhash); + } + else + { + status = HAL_BUSY; + } + /* Return function status */ + return status; +} + + +/** + * @brief End computation of a single HASH signature after several calls to HAL_HASH_Accumulate_IT() API. + * @note Digest is available in pOutBuffer + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes. + * @param pOutBuffer pointer to the computed digest. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HASH_AccumulateLast_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *const pOutBuffer) +{ + HAL_StatusTypeDef status; + + /* Check the hash handle allocation */ + if (hhash == NULL) + { + return HAL_ERROR; + } + + /* Check if peripheral is ready to start process */ + if (hhash->State == HAL_HASH_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hhash); + + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_BUSY; + + /* Reset HashInCount and Initialize Size, pHashInBuffPtr and pHashOutBuffPtr parameters */ + hhash->pHashInBuffPtr = pInBuffer; + hhash->pHashOutBuffPtr = pOutBuffer; + hhash->HashInCount = 0U; + hhash->Size = Size; + if (hhash->Phase == HAL_HASH_PHASE_READY) + { + /* Set HASH mode */ + CLEAR_BIT(hhash->Instance->CR, HASH_CR_MODE); + /* Reset the HASH processor core */ + MODIFY_REG(hhash->Instance->CR, HASH_CR_INIT, HASH_CR_INIT); + + /* Set the phase */ + hhash->Phase = HAL_HASH_PHASE_PROCESS; + } + /* Configure the number of valid bits in last word of the message */ + MODIFY_REG(hhash->Instance->STR, HASH_STR_NBLW, 8U * (Size % 4U)); + + /* Enable the specified HASH interrupt*/ + __HAL_HASH_ENABLE_IT(hhash, HASH_IT_DINI | HASH_IT_DCI); + + status = HASH_WriteData_IT(hhash); + + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_READY; + + /* Reset HASH state machine */ + hhash->Phase = HAL_HASH_PHASE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hhash); + } + else + { + status = HAL_BUSY; + } + /* Return function status */ + return status; +} + +/** + * @} + */ + + +/** @defgroup HASH_Exported_Functions_Group3 HMAC processing functions + * @brief HMAC processing functions using different mode. + * +@verbatim + =============================================================================== + ##### HMAC processing functions ##### + =============================================================================== + [..] This section provides API allowing to calculate the HMAC (keyed-hash + message authentication code) value using: + (+) one of the algorithms supported by the peripheral + (+) Key selection + (++) Long key : HMAC key is longer than the block size + (++) Short key : HMAC key is shorter or equal to the block size + + [..] To calculate the HMAC for a single buffer, user can resort to one of three processing + functions available . + (+) Polling mode : HAL_HASH_HMAC_Start() + (+) Interrupt mode : HAL_HASH_HMAC_Start_IT() + (+) DMA mode : HAL_HASH_HMAC_Start_DMA() + + [..] In case of multi-buffer HMAC processing (a single digest is computed while + several buffers are fed to the Peripheral), the user can resort to successive calls + to : + (+) Polling mode : HAL_HASH_HMAC_Accumulate() and wrap-up the digest computation by a call + to HAL_HASH_HMAC_AccumulateLast() + (+) Interrupt mode : HAL_HASH_HMAC_Accumulate_IT() and wrap-up the digest computation by a call + to HAL_HASH_HMAC_AccumulateLast_IT() + (+) DMA mode : HAL_HASH_HMAC_Start_DMA(),MDMAT bit must be set through __HAL_HASH_SET_MDMAT() macro, + before entering the last buffer, reset the MDMAT bit with __HAL_HASH_RESET_MDMAT() + macro then wrap-up the HMAC processing in feeding the last input buffer through the + same API HAL_HASH_HMAC_Start_DMA() + +@endverbatim + * @{ + */ + +/** + * @brief HMAC in polling mode, HASH peripheral processes Key then pInBuffer then reads the computed digest. + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes. + * @param pOutBuffer pointer to the computed digest. + * @param Timeout specify timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HASH_HMAC_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *const pOutBuffer, uint32_t Timeout) +{ + uint32_t blocksize; /* Block size in bytes */ + + /* Check the hash handle allocation */ + if (hhash == NULL) + { + return HAL_ERROR; + } + + /* Check if peripheral is ready to start process */ + if (hhash->State == HAL_HASH_STATE_READY) + { + + /* Process Locked */ + __HAL_LOCK(hhash); + + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_BUSY; + + /* Reset HASH Phase */ + hhash->Phase = HAL_HASH_PHASE_READY; + + /* Reset HashInCount and Initialize Size, pHashKeyBuffPtr, pHashInBuffPtr and pHashOutBuffPtr parameters */ + hhash->pHashInBuffPtr = pInBuffer; + hhash->pHashOutBuffPtr = pOutBuffer; + hhash->pHashKeyBuffPtr = hhash->Init.pKey; + hhash->HashInCount = 0U; + hhash->Size = Size; + + blocksize = BLOCK_64B; + if (hhash->Init.KeySize > blocksize) + { + MODIFY_REG(hhash->Instance->CR, HASH_CR_LKEY | HASH_CR_MODE | HASH_CR_INIT, + HASH_ALGOMODE_HMAC | HASH_LONGKEY | HASH_CR_INIT); + } + else + { + + MODIFY_REG(hhash->Instance->CR, HASH_CR_LKEY | HASH_CR_MODE | HASH_CR_INIT, + HASH_ALGOMODE_HMAC | HASH_CR_INIT); + } + + /* Configure the number of valid bits in last word of the Key */ + MODIFY_REG(hhash->Instance->STR, HASH_STR_NBLW, 8U * ((hhash->Init.KeySize) % 4U)); + + + /* Set the phase */ + hhash->Phase = HAL_HASH_PHASE_PROCESS; + /* Write Key */ + HASH_WriteData(hhash, hhash->Init.pKey, hhash->Init.KeySize); + + /* Start the Key padding then the Digest calculation */ + SET_BIT(hhash->Instance->STR, HASH_STR_DCAL); + + /* Wait for BUSY flag to be cleared */ + if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, Timeout) != HAL_OK) + { + return HAL_ERROR; + } + + /* Configure the number of valid bits in last word of the message */ + MODIFY_REG(hhash->Instance->STR, HASH_STR_NBLW, 8U * (Size % 4U)); + + /* Write message */ + HASH_WriteData(hhash, pInBuffer, Size); + + /* Start the message padding then the Digest calculation */ + SET_BIT(hhash->Instance->STR, HASH_STR_DCAL); + + /* Wait for BUSY flag to be cleared */ + if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, Timeout) != HAL_OK) + { + return HAL_ERROR; + } + /* Configure the number of valid bits in last word of the Key */ + MODIFY_REG(hhash->Instance->STR, HASH_STR_NBLW, 8U * ((hhash->Init.KeySize) % 4U)); + + /* Write Key */ + HASH_WriteData(hhash, hhash->Init.pKey, hhash->Init.KeySize); + + /* Start the Key padding then the Digest calculation */ + SET_BIT(hhash->Instance->STR, HASH_STR_DCAL); + + /* Wait for digest calculation completion status(DCIS) flag to be set */ + if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DCIS, RESET, Timeout) != HAL_OK) + { + return HAL_ERROR; + } + + /* Read the message digest */ + HASH_GetDigest(hhash, pOutBuffer, HASH_DIGEST_LENGTH(hhash)); + + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_READY; + + /* Change the HASH phase */ + hhash->Phase = HAL_HASH_PHASE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hhash); + + /* Return function status */ + return HAL_OK; + + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief HMAC accumulate mode, HASH peripheral processes Key then several input buffers. + * @note Consecutive calls to HAL_HASH_HMAC_Accumulate() can be used to feed + * several input buffers back-to-back to the Peripheral that will yield a single + * HASH signature once all buffers have been entered. Wrap-up of input + * buffers feeding and retrieval of digest is done by a call to + * HAL_HASH_HMAC_AccumulateLast() + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes and a multiple of 4 + * @param Timeout specify timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HASH_HMAC_Accumulate(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint32_t Timeout) +{ + uint32_t blocksize; /* Block size in bytes */ + + /* Check the hash handle allocation and buffer length multiple of 4 */ + if ((hhash == NULL) || ((Size % 4U) != 0U)) + { + return HAL_ERROR; + } + + /* Check if peripheral is ready to start process */ + if (hhash->State == HAL_HASH_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hhash); + + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_BUSY; + + /* Initialize Size, pHashInBuffPtr and pHashKeyBuffPtr parameters */ + hhash->pHashInBuffPtr = pInBuffer; + hhash->pHashKeyBuffPtr = hhash->Init.pKey; + hhash->Size = Size; + + if (hhash->Phase == HAL_HASH_PHASE_READY) + { + /* Reset HashInCount parameter */ + hhash->HashInCount = 0U; + /* Check if key size is larger than 64 bytes, accordingly set LKEY and the other setting bits */ + blocksize = BLOCK_64B; + if (hhash->Init.KeySize > blocksize) + { + MODIFY_REG(hhash->Instance->CR, HASH_CR_LKEY | HASH_CR_MODE | HASH_CR_INIT, + HASH_ALGOMODE_HMAC | HASH_LONGKEY | HASH_CR_INIT); + } + else + { + + MODIFY_REG(hhash->Instance->CR, HASH_CR_LKEY | HASH_CR_MODE | HASH_CR_INIT, + HASH_ALGOMODE_HMAC | HASH_CR_INIT); + } + /* Set phase process */ + hhash->Phase = HAL_HASH_PHASE_PROCESS; + + /* Configure the number of valid bits in last word of the Key */ + MODIFY_REG(hhash->Instance->STR, HASH_STR_NBLW, 8U * ((hhash->Init.KeySize) % 4U)); + + /* Write Key */ + HASH_WriteData(hhash, hhash->Init.pKey, hhash->Init.KeySize); + + /* Start the Key padding then the Digest calculation */ + SET_BIT(hhash->Instance->STR, HASH_STR_DCAL); + + /* Wait for BUSY flag to be cleared */ + if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, Timeout) != HAL_OK) + { + return HAL_ERROR; + } + } + + /* Change the number of valid bits in last word of the message */ + MODIFY_REG(hhash->Instance->STR, HASH_STR_NBLW, 0U); + + /* Write message */ + HASH_WriteData(hhash, pInBuffer, Size); + + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hhash); + + /* Return function status */ + return HAL_OK; + + } + else + { + return HAL_BUSY; + } +} +/** + * @brief End computation of a single HMAC signature after several calls to HAL_HASH_HMAC_Accumulate() API. + * @note Digest is available in pOutBuffer + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes. + * @param pOutBuffer pointer to the computed digest. + * @param Timeout specify timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HASH_HMAC_AccumulateLast(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *const pOutBuffer, uint32_t Timeout) +{ + /* Check the hash handle allocation */ + if (hhash == NULL) + { + return HAL_ERROR; + } + + /* Check if peripheral is ready to start process */ + if (hhash->State == HAL_HASH_STATE_READY) + { + + /* Process Locked */ + __HAL_LOCK(hhash); + + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_BUSY; + + /* Initialize Size, pHashInBuffPtr, pHashKeyBuffPtr and pHashOutBuffPtr parameters */ + hhash->pHashInBuffPtr = pInBuffer; + hhash->pHashOutBuffPtr = pOutBuffer; + hhash->pHashKeyBuffPtr = hhash->Init.pKey; + hhash->Size = Size; + + if (hhash->Phase != HAL_HASH_PHASE_PROCESS) + { + return HAL_ERROR; + } + else + { + /* Configure the number of valid bits in last word of the message */ + MODIFY_REG(hhash->Instance->STR, HASH_STR_NBLW, 8U * (Size % 4U)); + + /* Write message */ + HASH_WriteData(hhash, pInBuffer, Size); + + /* Start the message padding then the Digest calculation */ + SET_BIT(hhash->Instance->STR, HASH_STR_DCAL); + + /* Wait for BUSY flag to be cleared */ + if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, Timeout) != HAL_OK) + { + return HAL_ERROR; + } + /* Configure the number of valid bits in last word of the Key */ + MODIFY_REG(hhash->Instance->STR, HASH_STR_NBLW, 8U * ((hhash->Init.KeySize) % 4U)); + + /* Write Key */ + HASH_WriteData(hhash, hhash->Init.pKey, hhash->Init.KeySize); + + /* Start the Key padding then the Digest calculation */ + SET_BIT(hhash->Instance->STR, HASH_STR_DCAL); + + /* Wait for digest calculation completion status(DCIS) flag to be set */ + if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DCIS, RESET, Timeout) != HAL_OK) + { + return HAL_ERROR; + } + + /* Read the message digest */ + HASH_GetDigest(hhash, pOutBuffer, HASH_DIGEST_LENGTH(hhash)); + } + + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_READY; + + /* Reset HASH state machine */ + hhash->Phase = HAL_HASH_PHASE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hhash); + + /* Return function status */ + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief HMAC in interrupt mode, HASH peripheral process Key then pInBuffer then read the computed digest. + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes. + * @param pOutBuffer pointer to the computed digest. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HASH_HMAC_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *const pOutBuffer) +{ + HAL_StatusTypeDef status; + uint32_t blocksize; /* Block size in bytes */ + + /* Check the hash handle allocation */ + if (hhash == NULL) + { + return HAL_ERROR; + } + + /* Check if peripheral is ready to start process */ + if (hhash->State == HAL_HASH_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hhash); + + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_BUSY; + + /* Reset HASH Phase */ + hhash->Phase = HAL_HASH_PHASE_READY; + + /* Reset HashInCount and Initialize Size, pHashKeyBuffPtr, pHashInBuffPtr and pHashOutBuffPtr parameters */ + hhash->pHashInBuffPtr = pInBuffer; + hhash->pHashOutBuffPtr = pOutBuffer; + hhash->pHashKeyBuffPtr = hhash->Init.pKey; + hhash->HashInCount = 0U; + hhash->Size = Size; + + /* Check if key size is larger than block size of the algorithm, accordingly set LKEY and the other setting bits */ + blocksize = BLOCK_64B; + if (hhash->Init.KeySize > blocksize) + { + MODIFY_REG(hhash->Instance->CR, HASH_CR_LKEY | HASH_CR_MODE | HASH_CR_INIT, + HASH_ALGOMODE_HMAC | HASH_LONGKEY | HASH_CR_INIT); + } + else + { + + MODIFY_REG(hhash->Instance->CR, HASH_CR_LKEY | HASH_CR_MODE | HASH_CR_INIT, + HASH_ALGOMODE_HMAC | HASH_CR_INIT); + } + + /* Configure the number of valid bits in last word of the Key */ + MODIFY_REG(hhash->Instance->STR, HASH_STR_NBLW, 8U * ((hhash->Init.KeySize) % 4U)); + + /* Set the phase */ + hhash->Phase = HAL_HASH_PHASE_PROCESS; + } + else if (hhash->State == HAL_HASH_STATE_SUSPENDED) + { + /* Process Locked */ + __HAL_LOCK(hhash); + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_BUSY; + } + else + { + return HAL_BUSY; + } + + /* Enable the specified HASH interrupt*/ + __HAL_HASH_ENABLE_IT(hhash, HASH_IT_DINI | HASH_IT_DCI); + + status = HASH_WriteData_IT(hhash); + + /* Return function status */ + return status; +} + +/** + * @brief HMAC accumulate in interrupt mode, HASH peripheral processes Key then several input buffers. + * @note Consecutive calls to HAL_HASH_HMAC_Accumulate_IT() can be used to feed + * several input buffers back-to-back to the Peripheral that will yield a single + * HASH signature once all buffers have been entered. Wrap-up of input + * buffers feeding and retrieval of digest is done by a call to + * HAL_HASH_HMAC_AccumulateLast_IT() + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes and a multiple of 4. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HASH_HMAC_Accumulate_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) +{ + HAL_StatusTypeDef status; + uint32_t blocksize; /* Block size in bytes */ + + /* Check the hash handle allocation and buffer length multiple of 4 */ + if ((hhash == NULL) || ((Size % 4U) != 0U)) + { + return HAL_ERROR; + } + + /* Check if peripheral is ready to start process */ + if (hhash->State == HAL_HASH_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hhash); + + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_BUSY; + + /* Reset HashInCount and Initialize Size, pHashInBuffPtr and pHashOutBuffPtr parameters */ + hhash->pHashInBuffPtr = pInBuffer; + hhash->pHashKeyBuffPtr = hhash->Init.pKey; + hhash->HashInCount = 0U; + hhash->Size = Size; + /* Set multi buffers accumulation flag */ + hhash->Accumulation = 1U; + + if (hhash->Phase == HAL_HASH_PHASE_READY) + { + /* Check if key size is larger than block size of the algorithm, accordingly set LKEY and the other setting */ + blocksize = BLOCK_64B; + if (hhash->Init.KeySize > blocksize) + { + MODIFY_REG(hhash->Instance->CR, HASH_CR_LKEY | HASH_CR_MODE | HASH_CR_INIT, + HASH_ALGOMODE_HMAC | HASH_LONGKEY | HASH_CR_INIT); + } + else + { + + MODIFY_REG(hhash->Instance->CR, HASH_CR_LKEY | HASH_CR_MODE | HASH_CR_INIT, + HASH_ALGOMODE_HMAC | HASH_CR_INIT); + } + + /* Configure the number of valid bits in last word of the Key */ + MODIFY_REG(hhash->Instance->STR, HASH_STR_NBLW, 8U * ((hhash->Init.KeySize) % 4U)); + + /* Set the phase */ + hhash->Phase = HAL_HASH_PHASE_PROCESS; + } + /* Enable the specified HASH interrupt*/ + __HAL_HASH_ENABLE_IT(hhash, HASH_IT_DINI | HASH_IT_DCI); + + status = HASH_WriteData_IT(hhash); + } + else + { + status = HAL_BUSY; + } + /* Return function status */ + return status; +} +/** + * @brief End computation of a single HMAC signature in interrupt mode, after + * several calls to HAL_HASH_HMAC_Accumulate() API. + * @note Digest is available in pOutBuffer + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes. + * @param pOutBuffer pointer to the computed digest. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HASH_HMAC_AccumulateLast_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, + uint32_t Size, uint8_t *const pOutBuffer) +{ + HAL_StatusTypeDef status; + + /* Check the hash handle allocation */ + if (hhash == NULL) + { + return HAL_ERROR; + } + + /* Check if peripheral is ready to start process*/ + if (hhash->State == HAL_HASH_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hhash); + + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_BUSY; + + /* Reset HashInCount and Initialize Size, pHashInBuffPtr and pHashOutBuffPtr parameters */ + hhash->pHashInBuffPtr = pInBuffer; + hhash->pHashOutBuffPtr = pOutBuffer; + hhash->pHashKeyBuffPtr = hhash->Init.pKey; + hhash->HashInCount = 0U; + hhash->Size = Size; + /* Set multi buffers accumulation flag */ + hhash->Accumulation = 0U; + /* Enable the specified HASH interrupt*/ + __HAL_HASH_ENABLE_IT(hhash, HASH_IT_DINI | HASH_IT_DCI); + + status = HASH_WriteData_IT(hhash); + } + else + { + status = HAL_BUSY; + } + /* Return function status */ + return status; +} + +/** + * @brief HMAC in DMA mode,HASH peripheral processes Key then pInBuffer in DMA mode + * then read the computed digest. + * @note Multi-buffer HMAC processing is possible, consecutive calls to HAL_HASH_HMAC_Start_DMA + * (MDMAT bit must be set) can be used to feed several input buffers + * back-to-back to the Peripheral that will yield a single + * HASH signature once all buffers have been entered. Wrap-up of input + * buffers feeding and retrieval of digest is done by a call to + * HAL_HASH_HMAC_Start_DMA (MDMAT bit must be reset). + * @param hhash HASH handle. + * @param pInBuffer pointer to the input buffer (buffer to be hashed). + * @param Size length of the input buffer in bytes. + * @param pOutBuffer pointer to the computed digest. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HASH_HMAC_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *const pOutBuffer) +{ + HAL_StatusTypeDef status; + uint32_t count; + uint32_t blocksize; /* Block size in bytes */ + + /* Check the hash handle allocation */ + if (hhash == NULL) + { + return HAL_ERROR; + } + + /* Check if peripheral is ready to start process*/ + if (hhash->State == HAL_HASH_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hhash); + + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_BUSY; + + /* Reset HashInCount and Initialize Size, pHashInBuffPtr and pHashOutBuffPtr parameters */ + hhash->pHashInBuffPtr = pInBuffer; + hhash->pHashOutBuffPtr = pOutBuffer; + hhash->pHashKeyBuffPtr = hhash->Init.pKey; + hhash->HashInCount = 0U; + hhash->Size = Size; + + /* Set the phase */ + if (hhash->Phase == HAL_HASH_PHASE_READY) + { + /* Check if key size is larger than block size of the algorithm, accordingly set LKEY and the other setting */ + blocksize = BLOCK_64B; + if (hhash->Init.KeySize > blocksize) + { + MODIFY_REG(hhash->Instance->CR, HASH_CR_LKEY | HASH_CR_MODE | HASH_CR_INIT, + HASH_ALGOMODE_HMAC | HASH_LONGKEY | HASH_CR_INIT); + } + else + { + + MODIFY_REG(hhash->Instance->CR, HASH_CR_LKEY | HASH_CR_MODE | HASH_CR_INIT, + HASH_ALGOMODE_HMAC | HASH_CR_INIT); + } + + /* Set the phase */ + hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_1; + + /* Configure the number of valid bits in last word of the Key */ + MODIFY_REG(hhash->Instance->STR, HASH_STR_NBLW, 8U * ((hhash->Init.KeySize) % 4U)); + + /* Write Key */ + HASH_WriteData(hhash, hhash->Init.pKey, hhash->Init.KeySize); + + /* Start the Key padding then the Digest calculation */ + SET_BIT(hhash->Instance->STR, HASH_STR_DCAL); + + /* Wait for DCIS flag to be set */ + count = HASH_TIMEOUTVALUE; + do + { + count--; + if (count == 0U) + { + /* Change state */ + hhash->ErrorCode |= HAL_HASH_ERROR_TIMEOUT; + hhash->State = HAL_HASH_STATE_READY; + __HAL_UNLOCK(hhash); + return HAL_ERROR; + } + } while (HAL_IS_BIT_CLR(hhash->Instance->SR, HASH_FLAG_BUSY)); + } + + hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_2; + if ((hhash->Instance->CR & HASH_CR_MDMAT) == 0U) + { + /* Configure the number of valid bits in last word of the message */ + MODIFY_REG(hhash->Instance->STR, HASH_STR_NBLW, 8U * ((hhash->Size) % 4U)); + } + else + { + /* Configure the number of valid bits in last word of the message */ + MODIFY_REG(hhash->Instance->STR, HASH_STR_NBLW, 0U); + } + } + else if (hhash->State == HAL_HASH_STATE_SUSPENDED) + { + /* Process Locked */ + __HAL_LOCK(hhash); + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_BUSY; + + /*only part not yet hashed to compute */ + hhash->Size = hhash->HashInCount; + } + + else + { + /* Return busy status */ + return HAL_BUSY; + } + + /* Set the HASH DMA transfer complete callback */ + hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt; + /* Set the DMA error callback */ + hhash->hdmain->XferErrorCallback = HASH_DMAError; + + if ((hhash->hdmain->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if ((hhash->hdmain->LinkedListQueue != NULL) && (hhash->hdmain->LinkedListQueue->Head != NULL)) + { + /* Enable the DMA channel */ + hhash->hdmain->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET]\ + = ((((hhash->Size) % 4U) != 0U) ? ((hhash->Size) + (4U - ((hhash->Size) % 4U))) : ((hhash->Size))); + hhash->hdmain->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET]\ + = (uint32_t)(hhash->pHashInBuffPtr); /* Set DMA source address */ + hhash->hdmain->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET]\ + = (uint32_t)&hhash->Instance->DIN; /* Set DMA destination address */ + + status = HAL_DMAEx_List_Start_IT(hhash->hdmain); + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + } + else + { + status = HAL_DMA_Start_IT(hhash->hdmain, (uint32_t)(hhash->pHashInBuffPtr), (uint32_t)&hhash->Instance->DIN, \ + ((((hhash->Size) % 4U) != 0U) ? ((hhash->Size) + (4U - ((hhash->Size) % 4U))) : \ + ((hhash->Size)))); + } + if (status != HAL_OK) + { + /* DMA error code field */ + hhash->ErrorCode |= HAL_HASH_ERROR_DMA; + + /* Return error */ +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U) + /*Call registered error callback*/ + hhash->ErrorCallback(hhash); +#else + /*Call legacy weak error callback*/ + HAL_HASH_ErrorCallback(hhash); +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ + } + else + { + /* Enable DMA requests */ + SET_BIT(hhash->Instance->CR, HASH_CR_DMAE); + } + + /* Return function status */ + return status; +} + + +/** + * @} + */ + +/** @defgroup HASH_Exported_Functions_Group4 HASH IRQ handler management + * @brief HASH IRQ handler. + * +@verbatim + ============================================================================== + ##### HASH IRQ handler management ##### + ============================================================================== +[..] This section provides HASH IRQ handler and callback functions. + (+) HAL_HASH_IRQHandler HASH interrupt request + (+) HAL_HASH_InCpltCallback input data transfer complete callback + (+) HAL_HASH_DgstCpltCallback digest computation complete callback + (+) HAL_HASH_ErrorCallback HASH error callback + (+) HAL_HASH_GetState return the HASH state + (+) HAL_HASH_GetError return the HASH error code +@endverbatim + * @{ + */ + +/** + * @brief Handle HASH interrupt request. + * @param hhash HASH handle. + * @note HAL_HASH_IRQHandler() handles interrupts in HMAC processing as well. + * @retval None + */ +void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash) +{ + HAL_StatusTypeDef status; + uint32_t itsource = hhash->Instance->IMR; + uint32_t itflag = hhash->Instance->SR; + + /* If digest is ready */ + if ((itflag & HASH_FLAG_DCIS) == HASH_FLAG_DCIS) + { + /* Read the digest */ + HASH_GetDigest(hhash, hhash->pHashOutBuffPtr, HASH_DIGEST_LENGTH(hhash)); + + /* Disable Interrupts */ + __HAL_HASH_DISABLE_IT(hhash, HASH_IT_DINI | HASH_IT_DCI); + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_READY; + /* Reset HASH state machine */ + hhash->Phase = HAL_HASH_PHASE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hhash); + /* Call digest computation complete call back */ +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) + hhash->DgstCpltCallback(hhash); +#else + HAL_HASH_DgstCpltCallback(hhash); +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ + + } + /* If Peripheral ready to accept new data */ + if ((itflag & HASH_FLAG_DINIS) == HASH_FLAG_DINIS) + { + if ((itsource & HASH_IT_DINI) == HASH_IT_DINI) + { + status = HASH_WriteData_IT(hhash); + if (status != HAL_OK) + { + /* Call error callback */ +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) + hhash->ErrorCallback(hhash); +#else + HAL_HASH_ErrorCallback(hhash); +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ + } + } + } +} + +/** + * @brief Input data transfer complete call back. + * @note HAL_HASH_InCpltCallback() is called when the complete input message + * has been fed to the Peripheral. This API is invoked only when input data are + * entered under interruption or through DMA. + * @note In case of HASH or HMAC multi-buffer DMA feeding case (MDMAT bit set), + * HAL_HASH_InCpltCallback() is called at the end of each buffer feeding + * to the Peripheral. + * @param hhash pointer to a HASH_HandleTypeDef structure that contains + * the configuration information for HASH module. + * @retval None + */ +__weak void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhash); + + /* NOTE : This function should not be modified; when the callback is needed, + HAL_HASH_InCpltCallback() can be implemented in the user file. + */ +} + +/** + * @brief Digest computation complete call back. + * @note HAL_HASH_DgstCpltCallback() is used under interruption, is not + * relevant with DMA. + * @param hhash pointer to a HASH_HandleTypeDef structure that contains + * the configuration information for HASH module. + * @retval None + */ +__weak void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhash); + + /* NOTE : This function should not be modified; when the callback is needed, + HAL_HASH_DgstCpltCallback() can be implemented in the user file. + */ +} + +/** + * @brief HASH error callback. + * @note Code user can resort to hhash->Status (HAL_ERROR, HAL_TIMEOUT,...) + * to retrieve the error type. + * @param hhash pointer to a HASH_HandleTypeDef structure that contains + * the configuration information for HASH module. + * @retval None + */ +__weak void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhash); + + /* NOTE : This function should not be modified; when the callback is needed, + HAL_HASH_ErrorCallback() can be implemented in the user file. + */ +} + +/** + * @brief Return the HASH handle state. + * @note The API yields the current state of the handle (BUSY, READY,...). + * @param hhash HASH handle. + * @retval HAL HASH state + */ +HAL_HASH_StateTypeDef HAL_HASH_GetState(const HASH_HandleTypeDef *hhash) +{ + return hhash->State; +} + +/** + * @brief Return the HASH handle error code. + * @param hhash pointer to a HASH_HandleTypeDef structure. + * @retval HASH Error Code + */ +uint32_t HAL_HASH_GetError(const HASH_HandleTypeDef *hhash) +{ + /* Return HASH Error Code */ + return hhash->ErrorCode; +} +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @addtogroup HASH_Private_Functions + * @{ + */ + +/** + * @brief DMA HASH Input Data transfer completion callback. + * @param hdma DMA handle. + * @retval None + */ +static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma) +{ + HASH_HandleTypeDef *hhash = (HASH_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + uint32_t count; + + if (READ_BIT(hhash->Instance->CR, HASH_CR_MODE) == 0U) + { + if ((hhash->Instance->CR & HASH_CR_MDMAT) == 0U) + { + /* Disable the DMA transfer */ + CLEAR_BIT(hhash->Instance->CR, HASH_CR_DMAE); + + + /* Wait for DCIS flag to be set */ + count = HASH_TIMEOUTVALUE; + do + { + count--; + if (count == 0U) + { + /* Change state */ + hhash->ErrorCode |= HAL_HASH_ERROR_TIMEOUT; + hhash->State = HAL_HASH_STATE_READY; + __HAL_UNLOCK(hhash); +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) + hhash->ErrorCallback(hhash); +#else + HAL_HASH_ErrorCallback(hhash); +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ + } + } while (HAL_IS_BIT_CLR(hhash->Instance->SR, HASH_FLAG_DCIS)); + /* Call Input data transfer complete call back */ +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) + hhash->InCpltCallback(hhash); +#else + HAL_HASH_InCpltCallback(hhash); +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ + + /* Read the message digest */ + HASH_GetDigest(hhash, hhash->pHashOutBuffPtr, HASH_DIGEST_LENGTH(hhash)); + + /* Change the HASH state to ready */ + hhash->State = HAL_HASH_STATE_READY; + + /* Reset HASH state machine */ + hhash->Phase = HAL_HASH_PHASE_READY; + + /* Process UnLock */ + __HAL_UNLOCK(hhash); + + /* Call digest complete call back */ +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) + hhash->DgstCpltCallback(hhash); +#else + HAL_HASH_DgstCpltCallback(hhash); +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ + } + else + { + hhash->State = HAL_HASH_STATE_READY; + __HAL_UNLOCK(hhash); + } + } + else /*HMAC DMA*/ + { + if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2) + { + if ((hhash->Instance->CR & HASH_CR_MDMAT) == 0U) + { + /* Set the phase */ + hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_3; + /* Configure the number of valid bits in last word of the Key */ + MODIFY_REG(hhash->Instance->STR, HASH_STR_NBLW, 8U * ((hhash->Init.KeySize) % 4U)); + /* Write Key */ + HASH_WriteData(hhash, hhash->Init.pKey, hhash->Init.KeySize); + + /* Start the Key padding then the Digest calculation */ + SET_BIT(hhash->Instance->STR, HASH_STR_DCAL); + + /* Wait for DCIS flag to be set */ + count = HASH_TIMEOUTVALUE; + do + { + count--; + if (count == 0U) + { + /* Disable the DMA transfer */ + CLEAR_BIT(hhash->Instance->CR, HASH_CR_DMAE); + + /* Change state */ + hhash->ErrorCode |= HAL_HASH_ERROR_DMA; + hhash->State = HAL_HASH_STATE_READY; + __HAL_UNLOCK(hhash); +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) + hhash->ErrorCallback(hhash); +#else + HAL_HASH_ErrorCallback(hhash); +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ + } + } while (HAL_IS_BIT_CLR(hhash->Instance->SR, HASH_FLAG_DCIS)); + + /* Read the message digest */ + HASH_GetDigest(hhash, hhash->pHashOutBuffPtr, HASH_DIGEST_LENGTH(hhash)); + + /* Change the HASH state to ready */ + hhash->State = HAL_HASH_STATE_READY; + + /* Reset HASH state machine */ + hhash->Phase = HAL_HASH_PHASE_READY; + + /* Process UnLock */ + __HAL_UNLOCK(hhash); + + /* Call digest complete call back */ +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) + hhash->DgstCpltCallback(hhash); +#else + HAL_HASH_DgstCpltCallback(hhash); +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ + + } + else + { + hhash->State = HAL_HASH_STATE_READY; + __HAL_UNLOCK(hhash); + hhash->Accumulation = 1; + } + } + } +} + +/** + * @brief DMA HASH communication error callback. + * @param hdma DMA handle. + * @retval None + */ +static void HASH_DMAError(DMA_HandleTypeDef *hdma) +{ + HASH_HandleTypeDef *hhash = (HASH_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + hhash->ErrorCode |= HAL_HASH_ERROR_DMA; + /* Set HASH state to ready to prevent any blocking issue in user code + present in HAL_HASH_ErrorCallback() */ + hhash->State = HAL_HASH_STATE_READY; + +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) + hhash->ErrorCallback(hhash); +#else + HAL_HASH_ErrorCallback(hhash); +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ +} + +/** + * @brief Feed the input buffer to the HASH peripheral in polling. + * @param hhash HASH handle. + * @param pInBuffer pointer to input buffer. + * @param Size the size of input buffer in bytes. + * @retval HAL status + */ +static void HASH_WriteData(HASH_HandleTypeDef *hhash, const uint8_t *pInBuffer, uint32_t Size) +{ + uint32_t buffercounter; + __IO uint32_t inputaddr = (uint32_t) pInBuffer; + uint8_t tmp1; + uint8_t tmp2; + uint8_t tmp3; + + for (buffercounter = 0U; buffercounter < (Size / 4U) ; buffercounter++) + { + /* Write input data 4 bytes at a time */ + hhash->Instance->DIN = *(uint32_t *)inputaddr; + inputaddr += 4U; + hhash->HashInCount += 4U; + } + + if ((Size % 4U) != 0U) + { + if (hhash->Init.DataType == HASH_HALFWORD_SWAP) + { + /* Write remaining input data */ + if ((Size % 4U) <= 2U) + { + hhash->Instance->DIN = (uint32_t) * (uint16_t *)inputaddr; + } + if ((Size % 4U) == 3U) + { + hhash->Instance->DIN = *(uint32_t *)inputaddr; + } + } + else if ((hhash->Init.DataType == HASH_BYTE_SWAP) + || (hhash->Init.DataType == HASH_BIT_SWAP)) /* byte swap or bit swap or */ + { + /* Write remaining input data */ + if ((Size % 4U) == 1U) + { + hhash->Instance->DIN = (uint32_t) * (uint8_t *)inputaddr; + } + if ((Size % 4U) == 2U) + { + hhash->Instance->DIN = (uint32_t) * (uint16_t *)inputaddr; + } + if ((Size % 4U) == 3U) + { + tmp1 = *(uint8_t *)inputaddr; + tmp2 = *(((uint8_t *)inputaddr) + 1U); + tmp3 = *(((uint8_t *)inputaddr) + 2U); + hhash->Instance->DIN = ((uint32_t)tmp1) | ((uint32_t)tmp2 << 8U) | ((uint32_t)tmp3 << 16U); + } + } + else + { + hhash->Instance->DIN = *(uint32_t *)inputaddr; + } + hhash->HashInCount += 4U; + } +} + +/** + * @brief Feed the input buffer to the HASH peripheral in interruption mode. + * @param hhash HASH handle. + * @retval HAL status + */ +static HAL_StatusTypeDef HASH_WriteData_IT(HASH_HandleTypeDef *hhash) +{ + uint32_t buffercounter; + uint32_t count; + __IO uint32_t keyaddr = (uint32_t)(hhash->pHashKeyBuffPtr); + __IO uint32_t inputaddr = (uint32_t)(hhash->pHashInBuffPtr); + uint32_t nbbytePartialHash = (((hhash->Instance->SR) >> 16U) * 4U); /* Nb byte to enter in HASH fifo to trig + a partial HASH computation*/ + + if (hhash->State == HAL_HASH_STATE_BUSY) + { + if ((hhash->Instance->CR & HASH_CR_MODE) == 0U) + { +#if (USE_HAL_HASH_SUSPEND_RESUME == 1U) + /* If suspension flag has been raised, suspend processing */ + if (hhash->SuspendRequest == HAL_HASH_SUSPEND) + { + /* reset SuspendRequest */ + hhash->SuspendRequest = HAL_HASH_SUSPEND_NONE; + /* Disable Computation Complete Flag and Errors Interrupts */ + __HAL_HASH_DISABLE_IT(hhash, HASH_IT_DINI | HASH_IT_DCI); + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_SUSPENDED; + __HAL_UNLOCK(hhash); + } + else + { +#endif /* USE_HAL_HASH_SUSPEND_RESUME */ + + if (((hhash->HashInCount) + nbbytePartialHash) < (hhash->Size)) + { + for (buffercounter = 0U; buffercounter < nbbytePartialHash ; buffercounter += 4U) + { + /* Write input data 4 bytes at a time */ + hhash->Instance->DIN = *(uint32_t *)inputaddr; + inputaddr += 4U; + hhash->HashInCount += 4U; + hhash->pHashInBuffPtr += 4U; + } + /* Wait for HASH_IT_DINI flag to be set */ + count = HASH_TIMEOUTVALUE; + do + { + count--; + if (count == 0U) + { + /* Disable Interrupts */ + __HAL_HASH_DISABLE_IT(hhash, HASH_IT_DINI | HASH_IT_DCI); + + /* Change state */ + hhash->ErrorCode |= HAL_HASH_ERROR_TIMEOUT; + hhash->State = HAL_HASH_STATE_READY; + __HAL_UNLOCK(hhash); + return HAL_ERROR; + } + } while (HAL_IS_BIT_CLR(hhash->Instance->SR, HASH_FLAG_DINIS)); + } + else + { + while ((hhash->HashInCount) < hhash->Size) + { + /* Write input data 4 bytes at a time */ + hhash->Instance->DIN = *(uint32_t *)inputaddr; + inputaddr += 4U; + hhash->HashInCount += 4U; + hhash->pHashInBuffPtr += 4U; + } + /* Call Input transfer complete callback */ +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hhash->InCpltCallback(hhash); +#else + /*Call legacy weak Input complete callback*/ + HAL_HASH_InCpltCallback(hhash); +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ + if (hhash->Accumulation == 0U) + { + if (__HAL_HASH_GET_IT_SOURCE(hhash, HASH_IT_DINI)) + { + /* Start the message padding then the Digest calculation */ + SET_BIT(hhash->Instance->STR, HASH_STR_DCAL); + + /* Wait for HASH_FLAG_DCIS flag to be set */ + count = HASH_TIMEOUTVALUE; + do + { + count--; + if (count == 0U) + { + /* Disable Interrupts */ + __HAL_HASH_DISABLE_IT(hhash, HASH_IT_DINI | HASH_IT_DCI); + + /* Change state */ + hhash->ErrorCode |= HAL_HASH_ERROR_TIMEOUT; + hhash->State = HAL_HASH_STATE_READY; + __HAL_UNLOCK(hhash); + return HAL_ERROR; + } + } while (HAL_IS_BIT_CLR(hhash->Instance->SR, HASH_FLAG_DCIS)); + } + } + else + { + /* Reset multi buffers accumulation flag */ + hhash->Accumulation = 0U; + /* Disable Interrupts */ + __HAL_HASH_DISABLE_IT(hhash, HASH_IT_DINI); + } + } +#if (USE_HAL_HASH_SUSPEND_RESUME == 1U) + } +#endif /* USE_HAL_HASH_SUSPEND_RESUME */ + } + else /*HMAC */ + { + if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2) /* loading input*/ + { +#if (USE_HAL_HASH_SUSPEND_RESUME == 1U) + /* If suspension flag has been raised, suspend processing */ + if (hhash->SuspendRequest == HAL_HASH_SUSPEND) + { + /* reset SuspendRequest */ + hhash->SuspendRequest = HAL_HASH_SUSPEND_NONE; + /* Disable Computation Complete Flag and Errors Interrupts */ + __HAL_HASH_DISABLE_IT(hhash, HASH_IT_DINI | HASH_IT_DCI); + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_SUSPENDED; + __HAL_UNLOCK(hhash); + } + else + { +#endif /* USE_HAL_HASH_SUSPEND_RESUME */ + if (hhash->Accumulation == 1U) + { + /* Configure the number of valid bits in last word of the message */ + MODIFY_REG(hhash->Instance->STR, HASH_STR_NBLW, 0U); + } + else + { + /* Configure the number of valid bits in last word of the message */ + MODIFY_REG(hhash->Instance->STR, HASH_STR_NBLW, 8U * (hhash->Size % 4U)); + } + if (((hhash->HashInCount) + nbbytePartialHash) < (hhash->Size)) + { + for (buffercounter = 0U; buffercounter < nbbytePartialHash ; buffercounter += 4U) + { + /* Write input data 4 bytes at a time */ + hhash->Instance->DIN = *(uint32_t *)inputaddr; + inputaddr += 4U; + hhash->HashInCount += 4U; + hhash->pHashInBuffPtr += 4U; + } + /* Wait for HASH_IT_DINI flag to be set */ + count = HASH_TIMEOUTVALUE; + do + { + count--; + if (count == 0U) + { + /* Disable Interrupts */ + __HAL_HASH_DISABLE_IT(hhash, HASH_IT_DINI | HASH_IT_DCI); + + /* Change state */ + hhash->ErrorCode |= HAL_HASH_ERROR_TIMEOUT; + hhash->State = HAL_HASH_STATE_READY; + __HAL_UNLOCK(hhash); + return HAL_ERROR; + } + } while (HAL_IS_BIT_CLR(hhash->Instance->SR, HASH_FLAG_DINIS)); + } + else + { + while ((hhash->HashInCount) < hhash->Size) + { + /* Write input data 4 bytes at a time */ + hhash->Instance->DIN = *(uint32_t *)inputaddr; + inputaddr += 4U; + hhash->HashInCount += 4U; + hhash->pHashInBuffPtr += 4U; + } + /* Call Input transfer complete callback */ +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hhash->InCpltCallback(hhash); +#else + /*Call legacy weak Input complete callback*/ + HAL_HASH_InCpltCallback(hhash); +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ + + if (hhash->Accumulation == 0U) + { + if (__HAL_HASH_GET_IT_SOURCE(hhash, HASH_IT_DINI)) + { + /* Start the message padding then the Digest calculation */ + SET_BIT(hhash->Instance->STR, HASH_STR_DCAL); + + /* Wait for HASH_FLAG_BUSY flag to be set */ + count = HASH_TIMEOUTVALUE; + do + { + count--; + if (count == 0U) + { + /* Disable Interrupts */ + __HAL_HASH_DISABLE_IT(hhash, HASH_IT_DINI | HASH_IT_DCI); + + /* Change state */ + hhash->ErrorCode |= HAL_HASH_ERROR_TIMEOUT; + hhash->State = HAL_HASH_STATE_READY; + __HAL_UNLOCK(hhash); + return HAL_ERROR; + } + } while (HAL_IS_BIT_SET(hhash->Instance->SR, HASH_FLAG_BUSY)); + + hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_3; + hhash->HashInCount = 0U; + hhash->pHashKeyBuffPtr = hhash->Init.pKey; + } + } + + else + { + /* Disable Interrupts */ + __HAL_HASH_DISABLE_IT(hhash, HASH_IT_DINI | HASH_IT_DCI); + hhash->State = HAL_HASH_STATE_READY; + __HAL_UNLOCK(hhash); + return HAL_OK; + } + } +#if (USE_HAL_HASH_SUSPEND_RESUME == 1U) + } +#endif /* USE_HAL_HASH_SUSPEND_RESUME */ + } + + else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3)/* loading Key*/ + { + + /* Configure the number of valid bits in last word of the Key */ + MODIFY_REG(hhash->Instance->STR, HASH_STR_NBLW, 8U * ((hhash->Init.KeySize) % 4U)); + + if (((hhash->HashInCount) + nbbytePartialHash) < (hhash->Init.KeySize)) + { + for (buffercounter = 0U; buffercounter < nbbytePartialHash ; buffercounter += 4U) + { + /* Write input data 4 bytes at a time */ + hhash->Instance->DIN = *(uint32_t *)keyaddr; + keyaddr += 4U; + hhash->HashInCount += 4U; + hhash->pHashKeyBuffPtr += 4U; + } + /* Wait for HASH_IT_DINI flag to be set */ + count = HASH_TIMEOUTVALUE; + do + { + count--; + if (count == 0U) + { + /* Disable Interrupts */ + __HAL_HASH_DISABLE_IT(hhash, HASH_IT_DINI | HASH_IT_DCI); + + /* Change state */ + hhash->ErrorCode |= HAL_HASH_ERROR_TIMEOUT; + hhash->State = HAL_HASH_STATE_READY; + __HAL_UNLOCK(hhash); + return HAL_ERROR; + } + } while (HAL_IS_BIT_CLR(hhash->Instance->SR, HASH_FLAG_DINIS)); + } + else + { + while ((hhash->HashInCount) < (hhash->Init.KeySize)) + { + /* Write input data 4 bytes at a time */ + hhash->Instance->DIN = *(uint32_t *)keyaddr; + keyaddr += 4U; + hhash->HashInCount += 4U; + } + /* Start the message padding then the Digest calculation */ + SET_BIT(hhash->Instance->STR, HASH_STR_DCAL); + + /* Wait for HASH_FLAG_DCIS flag to be set */ + count = HASH_TIMEOUTVALUE; + do + { + count--; + if (count == 0U) + { + /* Disable Interrupts */ + __HAL_HASH_DISABLE_IT(hhash, HASH_IT_DINI | HASH_IT_DCI); + + /* Change state */ + hhash->ErrorCode |= HAL_HASH_ERROR_TIMEOUT; + hhash->State = HAL_HASH_STATE_READY; + __HAL_UNLOCK(hhash); + return HAL_ERROR; + } + } while (HAL_IS_BIT_CLR(hhash->Instance->SR, HASH_FLAG_DCIS)); + } + } + else /*first step , loading key*/ + { + + hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_1; + + if (((hhash->HashInCount) + nbbytePartialHash) < (hhash->Init.KeySize)) + { + for (buffercounter = 0U; buffercounter < nbbytePartialHash ; buffercounter += 4U) + { + /* Write input data 4 bytes at a time */ + hhash->Instance->DIN = *(uint32_t *)keyaddr; + keyaddr += 4U; + hhash->HashInCount += 4U; + hhash->pHashKeyBuffPtr += 4U; + } + /* Wait for HASH_IT_DINI flag to be set */ + count = HASH_TIMEOUTVALUE; + do + { + count--; + if (count == 0U) + { + /* Disable Interrupts */ + __HAL_HASH_DISABLE_IT(hhash, HASH_IT_DINI | HASH_IT_DCI); + + /* Change state */ + hhash->ErrorCode |= HAL_HASH_ERROR_TIMEOUT; + hhash->State = HAL_HASH_STATE_READY; + __HAL_UNLOCK(hhash); + return HAL_ERROR; + } + } while (HAL_IS_BIT_CLR(hhash->Instance->SR, HASH_FLAG_DINIS)); + } + else + { + while ((hhash->HashInCount) < (hhash->Init.KeySize)) + { + /* Write input data 4 bytes at a time */ + hhash->Instance->DIN = *(uint32_t *)keyaddr; + keyaddr += 4U; + hhash->HashInCount += 4U; + hhash->pHashKeyBuffPtr += 4U; + } + /* Start the message padding then the Digest calculation */ + SET_BIT(hhash->Instance->STR, HASH_STR_DCAL); + + /* Wait for HASH_FLAG_BUSY flag to be set */ + count = HASH_TIMEOUTVALUE; + do + { + count--; + if (count == 0U) + { + /* Disable Interrupts */ + __HAL_HASH_DISABLE_IT(hhash, HASH_IT_DINI | HASH_IT_DCI); + + /* Change state */ + hhash->ErrorCode |= HAL_HASH_ERROR_TIMEOUT; + hhash->State = HAL_HASH_STATE_READY; + __HAL_UNLOCK(hhash); + return HAL_ERROR; + } + } while (HAL_IS_BIT_SET(hhash->Instance->SR, HASH_FLAG_BUSY)); + /*change Phase to step 2*/ + hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_2; + hhash->HashInCount = 0U; + } + } + } + } + else if ((hhash->State == HAL_HASH_STATE_SUSPENDED)) + { + return HAL_OK; + } + else + { + /* Busy error code field */ + hhash->ErrorCode |= HAL_HASH_ERROR_BUSY; +#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U) + /*Call registered error callback*/ + hhash->ErrorCallback(hhash); +#else + /*Call legacy weak error callback*/ + HAL_HASH_ErrorCallback(hhash); +#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} + +/** + * @brief Retrieve the message digest. + * @param hhash HASH handle + * @param pMsgDigest pointer to the computed digest. + * @param Size message digest size in bytes. + * @retval None + */ +static void HASH_GetDigest(const HASH_HandleTypeDef *hhash, const uint8_t *pMsgDigest, uint8_t Size) +{ + uint32_t msgdigest = (uint32_t)pMsgDigest; + + switch (Size) + { + /* Read the message digest */ + case 16: /* MD5 */ + *(uint32_t *)(msgdigest) = __REV(hhash->Instance->HR[0]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(hhash->Instance->HR[1]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(hhash->Instance->HR[2]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(hhash->Instance->HR[3]); + break; + case 20: /* SHA1 */ + *(uint32_t *)(msgdigest) = __REV(hhash->Instance->HR[0]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(hhash->Instance->HR[1]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(hhash->Instance->HR[2]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(hhash->Instance->HR[3]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(hhash->Instance->HR[4]); + break; + + case 28: /* SHA224 */ + *(uint32_t *)(msgdigest) = __REV(hhash->Instance->HR[0]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(hhash->Instance->HR[1]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(hhash->Instance->HR[2]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(hhash->Instance->HR[3]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(hhash->Instance->HR[4]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[5]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[6]); + + break; + case 32: /* SHA256 */ + *(uint32_t *)(msgdigest) = __REV(hhash->Instance->HR[0]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(hhash->Instance->HR[1]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(hhash->Instance->HR[2]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(hhash->Instance->HR[3]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(hhash->Instance->HR[4]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[5]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[6]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[7]); + break; + default: + break; + } +} + +/** + * @brief Handle HASH processing Timeout. + * @param hhash HASH handle. + * @param Flag specifies the HASH flag to check. + * @param Status the Flag status (SET or RESET). + * @param Timeout Timeout duration. + * @retval HAL status + */ +static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, uint32_t Flag, FlagStatus Status, + uint32_t Timeout) +{ + uint32_t tickstart = HAL_GetTick(); + + /* Wait until flag is set */ + if (Status == RESET) + { + while (__HAL_HASH_GET_FLAG(hhash, Flag) == RESET) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* Set State to Ready to be able to restart later on */ + hhash->State = HAL_HASH_STATE_READY; + hhash->ErrorCode |= HAL_HASH_ERROR_TIMEOUT; + /* Process Unlocked */ + __HAL_UNLOCK(hhash); + return HAL_ERROR; + } + } + } + } + else + { + while (__HAL_HASH_GET_FLAG(hhash, Flag) != RESET) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* Set State to Ready to be able to restart later on */ + hhash->State = HAL_HASH_STATE_READY; + hhash->ErrorCode |= HAL_HASH_ERROR_TIMEOUT; + /* Process Unlocked */ + __HAL_UNLOCK(hhash); + + return HAL_ERROR; + } + } + } + } + return HAL_OK; +} + +/** + * @} + */ + + +#endif /* HAL_HASH_MODULE_ENABLED */ + +#endif /* HASH*/ +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_hsem.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_hsem.c new file mode 100644 index 0000000000..84a253b8f6 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_hsem.c @@ -0,0 +1,482 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_hsem.c + * @author MCD Application Team + * @brief HSEM HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the semaphore peripheral: + * + Semaphore Take function (2-Step Procedure) , non blocking + * + Semaphore FastTake function (1-Step Procedure) , non blocking + * + Semaphore Status check + * + Semaphore Clear Key Set and Get + * + Release and release all functions + * + Semaphore notification enabling and disabling and callnack functions + * + IRQ handler management + * + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#)Take a semaphore In 2-Step mode Using function HAL_HSEM_Take. This function takes as parameters : + (++) the semaphore ID from 0 to 15 + (++) the process ID from 0 to 255 + (#) Fast Take semaphore In 1-Step mode Using function HAL_HSEM_FastTake. This function takes as parameter : + (++) the semaphore ID from 0_ID to 15. Note that the process ID value is implicitly assumed as zero + (#) Check if a semaphore is Taken using function HAL_HSEM_IsSemTaken. This function takes as parameter : + (++) the semaphore ID from 0_ID to 15 + (++) It returns 1 if the given semaphore is taken otherwise (Free) zero + (#)Release a semaphore using function with HAL_HSEM_Release. This function takes as parameters : + (++) the semaphore ID from 0 to 15 + (++) the process ID from 0 to 255: + (++) Note: If ProcessID and MasterID match, semaphore is freed, and an interrupt + may be generated when enabled (notification activated). If ProcessID or MasterID does not match, + semaphore remains taken (locked) + + (#)Release all semaphores at once taken by a given Master using function HAL_HSEM_Release_All + This function takes as parameters : + (++) the Release Key (value from 0 to 0xFFFF) can be Set or Get respectively by + HAL_HSEM_SetClearKey() or HAL_HSEM_GetClearKey functions + (++) the Master ID: + (++) Note: If the Key and MasterID match, all semaphores taken by the given CPU that corresponds + to MasterID will be freed, and an interrupt may be generated when enabled (notification activated). If the + Key or the MasterID doesn't match, semaphores remains taken (locked) + + (#)Semaphores Release all key functions: + (++) HAL_HSEM_SetClearKey() to set semaphore release all Key + (++) HAL_HSEM_GetClearKey() to get release all Key + (#)Semaphores notification functions : + (++) HAL_HSEM_ActivateNotification to activate a notification callback on + a given semaphores Mask (bitfield). When one or more semaphores defined by the mask are released + the callback HAL_HSEM_FreeCallback will be asserted giving as parameters a mask of the released + semaphores (bitfield). + + (++) HAL_HSEM_DeactivateNotification to deactivate the notification of a given semaphores Mask (bitfield). + (++) See the description of the macro __HAL_HSEM_SEMID_TO_MASK to check how to calculate a semaphore mask + Used by the notification functions + *** HSEM HAL driver macros list *** + ============================================= + [..] Below the list of most used macros in HSEM HAL driver. + + (+) __HAL_HSEM_SEMID_TO_MASK: Helper macro to convert a Semaphore ID to a Mask. + [..] Example of use : + [..] mask = __HAL_HSEM_SEMID_TO_MASK(8) | __HAL_HSEM_SEMID_TO_MASK(21) | __HAL_HSEM_SEMID_TO_MASK(25). + [..] All next macros take as parameter a semaphore Mask (bitfiled) that can be constructed using __HAL_HSEM_SEMID_TO_MASK as the above example. + (+) __HAL_HSEM_ENABLE_IT: Enable the specified semaphores Mask interrupts. + (+) __HAL_HSEM_DISABLE_IT: Disable the specified semaphores Mask interrupts. + (+) __HAL_HSEM_GET_IT: Checks whether the specified semaphore interrupt has occurred or not. + (+) __HAL_HSEM_GET_FLAG: Get the semaphores status release flags. + (+) __HAL_HSEM_CLEAR_FLAG: Clear the semaphores status release flags. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @defgroup HSEM HSEM + * @brief HSEM HAL module driver + * @{ + */ + +#ifdef HAL_HSEM_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup HSEM_Private_Constants HSEM Private Constants + * @{ + */ + +#ifndef HSEM_R_MASTERID +#define HSEM_R_MASTERID HSEM_R_LOCKID +#endif + +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup HSEM_Exported_Functions HSEM Exported Functions + * @{ + */ + +/** @defgroup HSEM_Exported_Functions_Group1 Take and Release functions + * @brief HSEM Take and Release functions + * +@verbatim + ============================================================================== + ##### HSEM Take and Release functions ##### + ============================================================================== +[..] This section provides functions allowing to: + (+) Take a semaphore with 2 Step method + (+) Fast Take a semaphore with 1 Step method + (+) Check semaphore state Taken or not + (+) Release a semaphore + (+) Release all semaphore at once + +@endverbatim + * @{ + */ + + +/** + * @brief Take a semaphore in 2 Step mode. + * @param SemID: semaphore ID from 0 to 15 + * @param ProcessID: Process ID from 0 to 255 + * @param Attribute: semaphore privilege and security attributes + * This parameter can be one of the following values: + * @arg HSEM_NSEC_PRIV: NSecure and Privileged attribute + * @arg HSEM_NSEC_NPRIV: NSecure and NPrivileged attribute + * @arg HSEM_SEC_PRIV: Secure and Privileged attribute + * @arg HSEM_SEC_NPRIV: Secure and NPrivileged attribute + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HSEM_Take(uint32_t SemID, uint32_t ProcessID, uint32_t Attribute) +{ + /* Check the parameters */ + assert_param(IS_HSEM_SEMID(SemID)); + assert_param(IS_HSEM_PROCESSID(ProcessID)); + + /* First step write R register with MasterID, processID, privilege and security attributes and take bit=1*/ + HSEM->R[SemID] = (ProcessID | HSEM_CR_LOCKID_CURRENT | HSEM_R_LOCK | Attribute); + + /* second step : read the R register . Take achieved if privilege and security attributes, MasterID and processID match and take bit set to 1 */ + if (HSEM->R[SemID] == (ProcessID | HSEM_CR_LOCKID_CURRENT | HSEM_R_LOCK | Attribute)) + { + /*take success when MasterID and ProcessID match and take bit set*/ + return HAL_OK; + } + + /* Semaphore take fails*/ + return HAL_ERROR; +} + +/** + * @brief Fast Take a semaphore with 1 Step mode. + * @param SemID: semaphore ID from 0 to 15 + * @param Attribute: semaphore privilege and security attributes + * This parameter can be one of the following values: + * @arg HSEM_NSEC_PRIV: NSecure and Privileged attribute + * @arg HSEM_NSEC_NPRIV: NSecure and NPrivileged attribute + * @arg HSEM_SEC_PRIV: Secure and Privileged attribute + * @arg HSEM_SEC_NPRIV: Secure and NPrivileged attribute + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HSEM_FastTake(uint32_t SemID, uint32_t Attribute) +{ + /* Check the parameters */ + assert_param(IS_HSEM_SEMID(SemID)); + + /* Read the RLR register to take the semaphore */ + if (HSEM->RLR[SemID] == (HSEM_CR_LOCKID_CURRENT | HSEM_R_LOCK | Attribute)) + { + /*take success when MasterID match and take bit set*/ + return HAL_OK; + } + + /* Semaphore take fails */ + return HAL_ERROR; +} +/** + * @brief Check semaphore state Taken or not. + * @param SemID: semaphore ID + * @retval HAL HSEM state + */ +uint32_t HAL_HSEM_IsSemTaken(uint32_t SemID) +{ + return (((HSEM->R[SemID] & HSEM_R_LOCK) != 0U) ? 1UL : 0UL); +} + + +/** + * @brief Release a semaphore. + * @param SemID: semaphore ID from 0 to 15 + * @param ProcessID: Process ID from 0 to 255 + * @param Attribute: semaphore privilege and security attributes + * This parameter can be one of the following values: + * @arg HSEM_NSEC_PRIV: NSecure and Privileged attribute + * @arg HSEM_NSEC_NPRIV: NSecure and NPrivileged attribute + * @arg HSEM_SEC_PRIV: Secure and Privileged attribute + * @arg HSEM_SEC_NPRIV: Secure and NPrivileged attribute + * @retval None + */ +void HAL_HSEM_Release(uint32_t SemID, uint32_t ProcessID, uint32_t Attribute) +{ + /* Check the parameters */ + assert_param(IS_HSEM_SEMID(SemID)); + assert_param(IS_HSEM_PROCESSID(ProcessID)); + + /* Clear the semaphore by writing to the R register : the MasterID , the processID and take bit = 0 */ + HSEM->R[SemID] = (ProcessID | HSEM_CR_LOCKID_CURRENT | Attribute); + +} + +/** + * @brief Release All semaphore used by a given Master . + * @param Key: Semaphore Key , value from 0 to 0xFFFF + * @param CoreID: CoreID of the CPU that is using semaphores to be released + * @param Attribute: semaphore privilege and security attributes + * This parameter can be one of the following values: + * @arg HSEM_NSEC_PRIV: NSecure and Privileged attribute + * @arg HSEM_NSEC_NPRIV: NSecure and NPrivileged attribute + * @arg HSEM_SEC_PRIV: Secure and Privileged attribute + * @arg HSEM_SEC_NPRIV: Secure and NPrivileged attribute + * @retval None + */ +void HAL_HSEM_ReleaseAll(uint32_t Key, uint32_t CoreID, uint32_t Attribute) +{ + assert_param(IS_HSEM_KEY(Key)); + assert_param(IS_HSEM_LOCKID(CoreID)); + + HSEM->CR = ((Key << HSEM_CR_KEY_Pos) | (CoreID << HSEM_CR_LOCKID_Pos) | Attribute); +} + +/** + * @} + */ + +/** @defgroup HSEM_Exported_Functions_Group2 HSEM Set and Get Key functions + * @brief HSEM Set and Get Key functions. + * +@verbatim + ============================================================================== + ##### HSEM Set and Get Key functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Set semaphore Key + (+) Get semaphore Key +@endverbatim + + * @{ + */ + +/** + * @brief Set semaphore Key . + * @param Key: Semaphore Key , value from 0 to 0xFFFF + * @retval None + */ +void HAL_HSEM_SetClearKey(uint32_t Key) +{ + assert_param(IS_HSEM_KEY(Key)); + + MODIFY_REG(HSEM->KEYR, HSEM_KEYR_KEY, (Key << HSEM_KEYR_KEY_Pos)); + +} + +/** + * @brief Get semaphore Key . + * @retval Semaphore Key , value from 0 to 0xFFFF + */ +uint32_t HAL_HSEM_GetClearKey(void) +{ + return (HSEM->KEYR >> HSEM_KEYR_KEY_Pos); +} + +/** + * @} + */ + +/** @defgroup HSEM_Exported_Functions_Group3 HSEM IRQ handler management + * @brief HSEM Notification functions. + * +@verbatim + ============================================================================== + ##### HSEM IRQ handler management and Notification functions ##### + ============================================================================== +[..] This section provides HSEM IRQ handler and Notification function. + +@endverbatim + * @{ + */ + +/** + * @brief Activate Semaphore release Notification for a given Semaphores Mask . + * @param SemMask: Mask of Released semaphores + * @retval Semaphore Key + */ +void HAL_HSEM_ActivateNotification(uint32_t SemMask) +{ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + HSEM_COMMON->SIER |= SemMask; +#else + HSEM_COMMON->IER |= SemMask; +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +} + +/** + * @brief Deactivate Semaphore release Notification for a given Semaphores Mask . + * @param SemMask: Mask of Released semaphores + * @retval Semaphore Key + */ +void HAL_HSEM_DeactivateNotification(uint32_t SemMask) +{ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + HSEM_COMMON->SIER &= ~SemMask; +#else + HSEM_COMMON->IER &= ~SemMask; +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +} + +/** + * @brief This function handles HSEM interrupt request + * @retval None + */ +void HAL_HSEM_IRQHandler(void) +{ + uint32_t statusreg; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + /* Get the list of masked freed semaphores*/ + statusreg = HSEM_COMMON->SMISR; + + /*Disable Interrupts*/ + HSEM_COMMON->SIER &= ~((uint32_t)statusreg); + + /*Clear Flags*/ + HSEM_COMMON->SICR = ((uint32_t)statusreg); +#else + /* Get the list of masked freed semaphores*/ + statusreg = HSEM_COMMON->MISR; + + /*Disable Interrupts*/ + HSEM_COMMON->IER &= ~((uint32_t)statusreg); + + /*Clear Flags*/ + HSEM_COMMON->ICR = ((uint32_t)statusreg); +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + /* Call FreeCallback */ + HAL_HSEM_FreeCallback(statusreg); +} + +/** + * @brief Semaphore Released Callback. + * @param SemMask: Mask of Released semaphores + * @retval None + */ +__weak void HAL_HSEM_FreeCallback(uint32_t SemMask) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(SemMask); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_HSEM_FreeCallback can be implemented in the user file + */ +} + +/** @defgroup HSEM_Exported_Functions_Group4 HSEM Security and privilege management + * @brief HSEM Attributes functions. + * +@verbatim + ============================================================================== + ##### Secure and privilege setting clearing reading functions ##### + ============================================================================== +[..] This section provides HSEM attributes setting and reading functions. + +@endverbatim + * @{ + */ + +#if defined(HSEM_SECCFGR_SEC0) +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Set semaphore access limited to secure access only. + * @param SemMask: Mask of secure semaphores + * @retval None + */ +void HAL_HSEM_SetSemaphoreSecure(uint32_t SemMask) +{ + SET_BIT(HSEM->SECCFGR, SemMask); +} + +/** + * @brief Allow secure and non-secure access to semaphore. + * @param SemMask: Mask of non-secure semaphores + * @retval None + */ +void HAL_HSEM_SetSemaphoreNonSecure(uint32_t SemMask) +{ + CLEAR_BIT(HSEM->SECCFGR, SemMask); +} +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/** + * @brief Get semaphores with access limited to secure access only. + * @retval Mask of secure semaphores + */ +uint32_t HAL_HSEM_GetSemaphoreSecure(void) +{ + return HSEM->SECCFGR; +} +#endif /* (HSEM_SECCFGR_SEC0) */ + +#if defined(HSEM_PRIVCFGR_PRIV0) +/** + * @brief Set semaphore access limited to privilege access only. + * @param SemMask: Mask of privilege semaphores + * @retval None + */ +void HAL_HSEM_SetSemaphorePrivilege(uint32_t SemMask) +{ + SET_BIT(HSEM->PRIVCFGR, SemMask); +} + +/** + * @brief Allow privilege and non-privilege access to semaphore. + * @param SemMask: Mask of non-privilege semaphores + * @retval None + */ +void HAL_HSEM_SetSemaphoreNonPrivilege(uint32_t SemMask) +{ + CLEAR_BIT(HSEM->PRIVCFGR, SemMask); +} + +/** + * @brief Get semaphores with access limited to privilege access only. + * @retval Mask of privilege semaphores + */ +uint32_t HAL_HSEM_GetSemaphorePrivilege(void) +{ + return HSEM->PRIVCFGR; +} +#endif /* (HSEM_PRIVCFGR_PRIV0) */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_HSEM_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_i2c.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_i2c.c new file mode 100644 index 0000000000..0befd7d3cb --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_i2c.c @@ -0,0 +1,7810 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_i2c.c + * @author MCD Application Team + * @brief I2C HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Inter Integrated Circuit (I2C) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State and Errors functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The I2C HAL driver can be used as follows: + + (#) Declare a I2C_HandleTypeDef handle structure, for example: + I2C_HandleTypeDef hi2c; + + (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API: + (##) Enable the I2Cx interface clock + (##) I2C pins configuration + (+++) Enable the clock for the I2C GPIOs + (+++) Configure I2C pins as alternate function open-drain + (##) NVIC configuration if you need to use interrupt process + (+++) Configure the I2Cx interrupt priority + (+++) Enable the NVIC I2C IRQ Channel + (##) DMA Configuration if you need to use DMA process + (+++) Declare a DMA_HandleTypeDef handle structure for + the transmit or receive channel + (+++) Enable the DMAx interface clock using + (+++) Configure the DMA handle parameters + (+++) Configure the DMA Tx or Rx channel + (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on + the DMA Tx or Rx channel + + (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode, + Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure. + + (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware + (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API. + + (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady() + + (#) For I2C IO and IO MEM operations, three operation modes are available within this driver : + + *** Polling mode IO operation *** + ================================= + [..] + (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit() + (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive() + (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit() + (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive() + + *** Polling mode IO MEM operation *** + ===================================== + [..] + (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write() + (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read() + + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT() + (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT() + (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT() + (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT() + (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_I2C_ErrorCallback() + (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() + (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. + This action will inform Master to generate a Stop condition to discard the communication. + + + *** Interrupt mode or DMA mode IO sequential operation *** + ========================================================== + [..] + (@) These interfaces allow to manage a sequential transfer with a repeated start condition + when a direction change during transfer + [..] + (+) A specific option field manage the different steps of a sequential transfer + (+) Option field values are defined through I2C_XFEROPTIONS and are listed below: + (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in + no sequential mode + (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address + and data to transfer without a final stop condition + (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with + start condition, address and data to transfer without a final stop condition, + an then permit a call the same master sequential interface several times + (like HAL_I2C_Master_Seq_Transmit_IT() then HAL_I2C_Master_Seq_Transmit_IT() + or HAL_I2C_Master_Seq_Transmit_DMA() then HAL_I2C_Master_Seq_Transmit_DMA()) + (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address + and with new data to transfer if the direction change or manage only the new data to + transfer + if no direction change and without a final stop condition in both cases + (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address + and with new data to transfer if the direction change or manage only the new data to + transfer + if no direction change and with a final stop condition in both cases + (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition + after several call of the same master sequential interface several times + (link with option I2C_FIRST_AND_NEXT_FRAME). + Usage can, transfer several bytes one by one using + HAL_I2C_Master_Seq_Transmit_IT + or HAL_I2C_Master_Seq_Receive_IT + or HAL_I2C_Master_Seq_Transmit_DMA + or HAL_I2C_Master_Seq_Receive_DMA + with option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME. + Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or + Receive sequence permit to call the opposite interface Receive or Transmit + without stopping the communication and so generate a restart condition. + (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after + each call of the same master sequential + interface. + Usage can, transfer several bytes one by one with a restart with slave address between + each bytes using + HAL_I2C_Master_Seq_Transmit_IT + or HAL_I2C_Master_Seq_Receive_IT + or HAL_I2C_Master_Seq_Transmit_DMA + or HAL_I2C_Master_Seq_Receive_DMA + with option I2C_FIRST_FRAME then I2C_OTHER_FRAME. + Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic + generation of STOP condition. + + (+) Different sequential I2C interfaces are listed below: + (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using + HAL_I2C_Master_Seq_Transmit_IT() or using HAL_I2C_Master_Seq_Transmit_DMA() + (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and + users can add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using + HAL_I2C_Master_Seq_Receive_IT() or using HAL_I2C_Master_Seq_Receive_DMA() + (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + (++) Abort a master IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() + (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() + HAL_I2C_DisableListen_IT() + (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and users can + add their own code to check the Address Match Code and the transmission direction request by master + (Write/Read). + (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_ListenCpltCallback() + (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using + HAL_I2C_Slave_Seq_Transmit_IT() or using HAL_I2C_Slave_Seq_Transmit_DMA() + (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and + users can add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using + HAL_I2C_Slave_Seq_Receive_IT() or using HAL_I2C_Slave_Seq_Receive_DMA() + (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_I2C_ErrorCallback() + (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. + This action will inform Master to generate a Stop condition to discard the communication. + + *** Interrupt mode IO MEM operation *** + ======================================= + [..] + (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using + HAL_I2C_Mem_Write_IT() + (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback() + (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using + HAL_I2C_Mem_Read_IT() + (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_I2C_ErrorCallback() + + *** DMA mode IO operation *** + ============================== + [..] + (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using + HAL_I2C_Master_Transmit_DMA() + (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + (+) Receive in master mode an amount of data in non-blocking mode (DMA) using + HAL_I2C_Master_Receive_DMA() + (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using + HAL_I2C_Slave_Transmit_DMA() + (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using + HAL_I2C_Slave_Receive_DMA() + (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_I2C_ErrorCallback() + (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() + (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. + This action will inform Master to generate a Stop condition to discard the communication. + + *** DMA mode IO MEM operation *** + ================================= + [..] + (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using + HAL_I2C_Mem_Write_DMA() + (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback() + (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using + HAL_I2C_Mem_Read_DMA() + (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_I2C_ErrorCallback() + + + *** I2C HAL driver macros list *** + ================================== + [..] + Below the list of most used macros in I2C HAL driver. + + (+) __HAL_I2C_ENABLE: Enable the I2C peripheral + (+) __HAL_I2C_DISABLE: Disable the I2C peripheral + (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode + (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not + (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag + (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt + (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt + + *** Callback registration *** + ============================================= + [..] + The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use Functions HAL_I2C_RegisterCallback() or HAL_I2C_RegisterAddrCallback() + to register an interrupt callback. + [..] + Function HAL_I2C_RegisterCallback() allows to register following callbacks: + (+) MasterTxCpltCallback : callback for Master transmission end of transfer. + (+) MasterRxCpltCallback : callback for Master reception end of transfer. + (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. + (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. + (+) ListenCpltCallback : callback for end of listen mode. + (+) MemTxCpltCallback : callback for Memory transmission end of transfer. + (+) MemRxCpltCallback : callback for Memory reception end of transfer. + (+) ErrorCallback : callback for error detection. + (+) AbortCpltCallback : callback for abort completion process. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + [..] + For specific callback AddrCallback use dedicated register callbacks : HAL_I2C_RegisterAddrCallback(). + [..] + Use function HAL_I2C_UnRegisterCallback to reset a callback to the default + weak function. + HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) MasterTxCpltCallback : callback for Master transmission end of transfer. + (+) MasterRxCpltCallback : callback for Master reception end of transfer. + (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. + (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. + (+) ListenCpltCallback : callback for end of listen mode. + (+) MemTxCpltCallback : callback for Memory transmission end of transfer. + (+) MemRxCpltCallback : callback for Memory reception end of transfer. + (+) ErrorCallback : callback for error detection. + (+) AbortCpltCallback : callback for abort completion process. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + [..] + For callback AddrCallback use dedicated register callbacks : HAL_I2C_UnRegisterAddrCallback(). + [..] + By default, after the HAL_I2C_Init() and when the state is HAL_I2C_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MasterRxCpltCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak functions in the HAL_I2C_Init()/ HAL_I2C_DeInit() only when + these callbacks are null (not registered beforehand). + If MspInit or MspDeInit are not null, the HAL_I2C_Init()/ HAL_I2C_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + [..] + Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only. + Exception done MspInit/MspDeInit functions that can be registered/unregistered + in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + Then, the user first registers the MspInit/MspDeInit user callbacks + using HAL_I2C_RegisterCallback() before calling HAL_I2C_DeInit() + or HAL_I2C_Init() function. + [..] + When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + [..] + (@) You can refer to the I2C HAL driver header file for more useful macros + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @defgroup I2C I2C + * @brief I2C HAL module driver + * @{ + */ + +#ifdef HAL_I2C_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/** @defgroup I2C_Private_Define I2C Private Define + * @{ + */ +#define TIMING_CLEAR_MASK (0xF0FFFFFFU) /*!< I2C TIMING clear register Mask */ +#define I2C_TIMEOUT_ADDR (10000U) /*!< 10 s */ +#define I2C_TIMEOUT_BUSY (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_DIR (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_RXNE (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_STOPF (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_TC (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_TCR (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_TXIS (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_FLAG (25U) /*!< 25 ms */ + +#define MAX_NBYTE_SIZE 255U +#define SLAVE_ADDR_SHIFT 7U +#define SLAVE_ADDR_MSK 0x06U + +/* Private define for @ref PreviousState usage */ +#define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | \ + (uint32_t)HAL_I2C_STATE_BUSY_RX) & \ + (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY)))) +/*!< Mask State define, keep only RX and TX bits */ +#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) +/*!< Default Value */ +#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_MASTER)) +/*!< Master Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_MASTER)) +/*!< Master Busy RX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_SLAVE)) +/*!< Slave Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_SLAVE)) +/*!< Slave Busy RX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_MEM)) +/*!< Memory Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_MEM)) +/*!< Memory Busy RX, combinaison of State LSB and Mode enum */ + + +/* Private define to centralize the enable/disable of Interrupts */ +#define I2C_XFER_TX_IT (uint16_t)(0x0001U) /*!< Bit field can be combinated with + @ref I2C_XFER_LISTEN_IT */ +#define I2C_XFER_RX_IT (uint16_t)(0x0002U) /*!< Bit field can be combinated with + @ref I2C_XFER_LISTEN_IT */ +#define I2C_XFER_LISTEN_IT (uint16_t)(0x8000U) /*!< Bit field can be combinated with @ref I2C_XFER_TX_IT + and @ref I2C_XFER_RX_IT */ + +#define I2C_XFER_ERROR_IT (uint16_t)(0x0010U) /*!< Bit definition to manage addition of global Error + and NACK treatment */ +#define I2C_XFER_CPLT_IT (uint16_t)(0x0020U) /*!< Bit definition to manage only STOP evenement */ +#define I2C_XFER_RELOAD_IT (uint16_t)(0x0040U) /*!< Bit definition to manage only Reload of NBYTE */ + +/* Private define Sequential Transfer Options default/reset value */ +#define I2C_NO_OPTION_FRAME (0xFFFF0000U) +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup I2C_Private_Macro + * @{ + */ +#if defined(HAL_DMA_MODULE_ENABLED) +/* Macro to get remaining data to transfer on DMA side */ +#define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) (__HAL_DMA_GET_COUNTER(__HANDLE__) + HAL_DMAEx_GetFifoLevel(__HANDLE__)) +#endif /* HAL_DMA_MODULE_ENABLED */ +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + +/** @defgroup I2C_Private_Functions I2C Private Functions + * @{ + */ +#if defined(HAL_DMA_MODULE_ENABLED) +/* Private functions to handle DMA transfer */ +static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMAError(DMA_HandleTypeDef *hdma); +static void I2C_DMAAbort(DMA_HandleTypeDef *hdma); + +#endif /* HAL_DMA_MODULE_ENABLED */ + +/* Private functions to handle IT transfer */ +static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c); +static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c); +static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode); + +/* Private functions to handle IT transfer */ +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart); +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart); + +/* Private functions for I2C transfer IRQ handler */ +static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); +static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); +static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); +#if defined(HAL_DMA_MODULE_ENABLED) +static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); +static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); +static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); +#endif /* HAL_DMA_MODULE_ENABLED */ + +/* Private functions to handle flags during polling transfer */ +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, + uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart); +static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart); + +/* Private functions to centralize the enable/disable of Interrupts */ +static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); +static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); + +/* Private function to treat different error callback */ +static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c); + +/* Private function to flush TXDR register */ +static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c); + +/* Private function to handle start, restart or stop a transfer */ +static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, + uint32_t Request); + +/* Private function to Convert Specific options */ +static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup I2C_Exported_Functions I2C Exported Functions + * @{ + */ + +/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + deinitialize the I2Cx peripheral: + + (+) User must Implement HAL_I2C_MspInit() function in which he configures + all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). + + (+) Call the function HAL_I2C_Init() to configure the selected device with + the selected configuration: + (++) Clock Timing + (++) Own Address 1 + (++) Addressing mode (Master, Slave) + (++) Dual Addressing mode + (++) Own Address 2 + (++) Own Address 2 Mask + (++) General call mode + (++) Nostretch mode + + (+) Call the function HAL_I2C_DeInit() to restore the default configuration + of the selected I2Cx peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the I2C according to the specified parameters + * in the I2C_InitTypeDef and initialize the associated handle. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) +{ + /* Check the I2C handle allocation */ + if (hi2c == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1)); + assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode)); + assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); + assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); + assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks)); + assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); + assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); + + if (hi2c->State == HAL_I2C_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hi2c->Lock = HAL_UNLOCKED; + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + /* Init the I2C Callback settings */ + hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */ + hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */ + hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */ + hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */ + hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */ + hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */ + hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */ + hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */ + hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */ + + if (hi2c->MspInitCallback == NULL) + { + hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + hi2c->MspInitCallback(hi2c); +#else + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + HAL_I2C_MspInit(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /*---------------------------- I2Cx TIMINGR Configuration ------------------*/ + /* Configure I2Cx: Frequency range */ + hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK; + + /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ + /* Disable Own Address1 before set the Own Address1 configuration */ + hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN; + + /* Configure I2Cx: Own Address1 and ack own address1 mode */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) + { + hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1); + } + else /* I2C_ADDRESSINGMODE_10BIT */ + { + hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1); + } + + /*---------------------------- I2Cx CR2 Configuration ----------------------*/ + /* Configure I2Cx: Addressing Master mode */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + { + SET_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10); + } + else + { + /* Clear the I2C ADD10 bit */ + CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10); + } + /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */ + hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK); + + /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ + /* Disable Own Address2 before set the Own Address2 configuration */ + hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE; + + /* Configure I2Cx: Dual mode and Own Address2 */ + hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \ + (hi2c->Init.OwnAddress2Masks << 8)); + + /*---------------------------- I2Cx CR1 Configuration ----------------------*/ + /* Configure I2Cx: Generalcall and NoStretch mode */ + hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode); + + /* Enable the selected I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->Mode = HAL_I2C_MODE_NONE; + + return HAL_OK; +} + +/** + * @brief DeInitialize the I2C peripheral. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) +{ + /* Check the I2C handle allocation */ + if (hi2c == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the I2C Peripheral Clock */ + __HAL_I2C_DISABLE(hi2c); + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + if (hi2c->MspDeInitCallback == NULL) + { + hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + hi2c->MspDeInitCallback(hi2c); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_I2C_MspDeInit(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->State = HAL_I2C_STATE_RESET; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Release Lock */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Initialize the I2C MSP. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitialize the I2C MSP. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MspDeInit could be implemented in the user file + */ +} + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User I2C Callback + * To be used instead of the weak predefined callback + * @note The HAL_I2C_RegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET + * to register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID + * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID + * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID + * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID + * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID + * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID + * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID + * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, + pI2C_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (HAL_I2C_STATE_READY == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MASTER_TX_COMPLETE_CB_ID : + hi2c->MasterTxCpltCallback = pCallback; + break; + + case HAL_I2C_MASTER_RX_COMPLETE_CB_ID : + hi2c->MasterRxCpltCallback = pCallback; + break; + + case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : + hi2c->SlaveTxCpltCallback = pCallback; + break; + + case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : + hi2c->SlaveRxCpltCallback = pCallback; + break; + + case HAL_I2C_LISTEN_COMPLETE_CB_ID : + hi2c->ListenCpltCallback = pCallback; + break; + + case HAL_I2C_MEM_TX_COMPLETE_CB_ID : + hi2c->MemTxCpltCallback = pCallback; + break; + + case HAL_I2C_MEM_RX_COMPLETE_CB_ID : + hi2c->MemRxCpltCallback = pCallback; + break; + + case HAL_I2C_ERROR_CB_ID : + hi2c->ErrorCallback = pCallback; + break; + + case HAL_I2C_ABORT_CB_ID : + hi2c->AbortCpltCallback = pCallback; + break; + + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = pCallback; + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_I2C_STATE_RESET == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = pCallback; + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister an I2C Callback + * I2C callback is redirected to the weak predefined callback + * @note The HAL_I2C_UnRegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET + * to un-register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * This parameter can be one of the following values: + * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID + * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID + * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID + * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID + * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID + * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID + * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID + * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (HAL_I2C_STATE_READY == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MASTER_TX_COMPLETE_CB_ID : + hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */ + break; + + case HAL_I2C_MASTER_RX_COMPLETE_CB_ID : + hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */ + break; + + case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : + hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */ + break; + + case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : + hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */ + break; + + case HAL_I2C_LISTEN_COMPLETE_CB_ID : + hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */ + break; + + case HAL_I2C_MEM_TX_COMPLETE_CB_ID : + hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */ + break; + + case HAL_I2C_MEM_RX_COMPLETE_CB_ID : + hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */ + break; + + case HAL_I2C_ERROR_CB_ID : + hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_I2C_ABORT_CB_ID : + hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + break; + + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_I2C_STATE_RESET == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Register the Slave Address Match I2C Callback + * To be used instead of the weak HAL_I2C_AddrCallback() predefined callback + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pCallback pointer to the Address Match Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (HAL_I2C_STATE_READY == hi2c->State) + { + hi2c->AddrCallback = pCallback; + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief UnRegister the Slave Address Match I2C Callback + * Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (HAL_I2C_STATE_READY == hi2c->State) + { + hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */ + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the I2C data + transfers. + + (#) There are two modes of transfer: + (++) Blocking mode : The communication is performed in the polling mode. + The status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode : The communication is performed using Interrupts + or DMA. These functions return the status of the transfer startup. + The end of the data processing will be indicated through the + dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + + (#) Blocking mode functions are : + (++) HAL_I2C_Master_Transmit() + (++) HAL_I2C_Master_Receive() + (++) HAL_I2C_Slave_Transmit() + (++) HAL_I2C_Slave_Receive() + (++) HAL_I2C_Mem_Write() + (++) HAL_I2C_Mem_Read() + (++) HAL_I2C_IsDeviceReady() + + (#) No-Blocking mode functions with Interrupt are : + (++) HAL_I2C_Master_Transmit_IT() + (++) HAL_I2C_Master_Receive_IT() + (++) HAL_I2C_Slave_Transmit_IT() + (++) HAL_I2C_Slave_Receive_IT() + (++) HAL_I2C_Mem_Write_IT() + (++) HAL_I2C_Mem_Read_IT() + (++) HAL_I2C_Master_Seq_Transmit_IT() + (++) HAL_I2C_Master_Seq_Receive_IT() + (++) HAL_I2C_Slave_Seq_Transmit_IT() + (++) HAL_I2C_Slave_Seq_Receive_IT() + (++) HAL_I2C_EnableListen_IT() + (++) HAL_I2C_DisableListen_IT() + (++) HAL_I2C_Master_Abort_IT() + + (#) No-Blocking mode functions with DMA are : + (++) HAL_I2C_Master_Transmit_DMA() + (++) HAL_I2C_Master_Receive_DMA() + (++) HAL_I2C_Slave_Transmit_DMA() + (++) HAL_I2C_Slave_Receive_DMA() + (++) HAL_I2C_Mem_Write_DMA() + (++) HAL_I2C_Mem_Read_DMA() + (++) HAL_I2C_Master_Seq_Transmit_DMA() + (++) HAL_I2C_Master_Seq_Receive_DMA() + (++) HAL_I2C_Slave_Seq_Transmit_DMA() + (++) HAL_I2C_Slave_Seq_Receive_DMA() + + (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: + (++) HAL_I2C_MasterTxCpltCallback() + (++) HAL_I2C_MasterRxCpltCallback() + (++) HAL_I2C_SlaveTxCpltCallback() + (++) HAL_I2C_SlaveRxCpltCallback() + (++) HAL_I2C_MemTxCpltCallback() + (++) HAL_I2C_MemRxCpltCallback() + (++) HAL_I2C_AddrCallback() + (++) HAL_I2C_ListenCpltCallback() + (++) HAL_I2C_ErrorCallback() + (++) HAL_I2C_AbortCpltCallback() + +@endverbatim + * @{ + */ + +/** + * @brief Transmits in master mode an amount of data in blocking mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_GENERATE_START_WRITE); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_WRITE); + } + + while (hi2c->XferCount > 0U) + { + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_NO_STARTSTOP); + } + } + } + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receives in master mode an amount of data in blocking mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_GENERATE_START_READ); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_READ); + } + + while (hi2c->XferCount > 0U) + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_NO_STARTSTOP); + } + } + } + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmits in slave mode an amount of data in blocking mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t Timeout) +{ + uint32_t tickstart; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Wait until ADDR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Preload TX data if no stretch enable */ + if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE) + { + /* Preload TX register */ + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + + /* If 10bit addressing mode is selected */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + { + /* Wait until ADDR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Wait until DIR flag is set Transmitter mode */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + while (hi2c->XferCount > 0U) + { + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + } + + /* Wait until AF flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Clear AF flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Wait until STOP flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + return HAL_ERROR; + } + + /* Clear STOP flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Wait until BUSY flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in blocking mode + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t Timeout) +{ + uint32_t tickstart; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferISR = NULL; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Wait until ADDR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + + /* Wait until DIR flag is reset Receiver mode */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + while (hi2c->XferCount > 0U) + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Store Last receive data if any */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) + { + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + } + + return HAL_ERROR; + } + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + } + + /* Wait until STOP flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Clear STOP flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Wait until BUSY flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size) +{ + uint32_t xfermode; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_IT; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ + /* Check if the Autonomous mode is enabled */ + if ((hi2c->Instance->AUTOCR & I2C_AUTOCR_TRIGEN) == I2C_AUTOCR_TRIGEN) + { + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_NO_START_WRITE); + } + else + { + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size) +{ + uint32_t xfermode; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_IT; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ + /* Check if the Autonomous mode is enabled */ + if ((hi2c->Instance->AUTOCR & I2C_AUTOCR_TRIGEN) == I2C_AUTOCR_TRIGEN) + { + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_NO_START_READ); + } + else + { + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_IT; + + /* Preload TX data if no stretch enable */ + if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE) + { + /* Preload TX register */ + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_IT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Transmit in master mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size) +{ + uint32_t xfermode; + HAL_StatusTypeDef dmaxferstatus; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_DMA; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + if (hi2c->XferSize > 0U) + { + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hi2c->hdmatx->LinkedListQueue != NULL) + { + /* Set DMA data size */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize; + + /* Set DMA source address */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData; + + /* Set DMA destination address */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] \ + = (uint32_t)&hi2c->Instance->TXDR; + + dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); + } + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + /* Check if the Autonomous mode is enabled */ + if ((hi2c->Instance->AUTOCR & I2C_AUTOCR_TRIGEN) == I2C_AUTOCR_TRIGEN) + { + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, + I2C_GENERATE_NO_START_WRITE); + } + else + { + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); + } + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Update Transfer ISR function pointer */ + hi2c->XferISR = I2C_Master_ISR_IT; + + /* Send Slave Address */ + /* Set NBYTES to write and generate START condition */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in master mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size) +{ + uint32_t xfermode; + HAL_StatusTypeDef dmaxferstatus; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_DMA; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + if (hi2c->XferSize > 0U) + { + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hi2c->hdmarx->LinkedListQueue != NULL) + { + /* Set DMA data size */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize; + + /* Set DMA source address */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] \ + = (uint32_t)&hi2c->Instance->RXDR; + + /* Set DMA destination address */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData; + + dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, + hi2c->XferSize); + } + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address */ + /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + /* Check if the Autonomous mode is enabled */ + if ((hi2c->Instance->AUTOCR & I2C_AUTOCR_TRIGEN) == I2C_AUTOCR_TRIGEN) + { + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, + I2C_GENERATE_NO_START_READ); + } + else + { + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + } + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Update Transfer ISR function pointer */ + hi2c->XferISR = I2C_Master_ISR_IT; + + /* Send Slave Address */ + /* Set NBYTES to read and generate START condition */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_READ); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef dmaxferstatus; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_DMA; + + /* Preload TX data if no stretch enable */ + if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE) + { + /* Preload TX register */ + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + } + + if (hi2c->XferCount != 0U) + { + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hi2c->hdmatx->LinkedListQueue != NULL) + { + /* Set DMA data size */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize; + + /* Set DMA source address */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)hi2c->pBuffPtr; + + /* Set DMA destination address */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] \ + = (uint32_t)&hi2c->Instance->TXDR; + + dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, + (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); + } + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef dmaxferstatus; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_DMA; + + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hi2c->hdmarx->LinkedListQueue != NULL) + { + /* Set DMA data size */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize; + + /* Set DMA source address */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] \ + = (uint32_t)&hi2c->Instance->RXDR; + + /* Set DMA destination address */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData; + + dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, + hi2c->XferSize); + } + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Write an amount of data in blocking mode to a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + + do + { + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_NO_STARTSTOP); + } + } + + } while (hi2c->XferCount > 0U); + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Read an amount of data in blocking mode from a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_GENERATE_START_READ); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_READ); + } + + do + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE, + I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_NO_STARTSTOP); + } + } + } while (hi2c->XferCount > 0U); + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +/** + * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->XferSize = 0U; + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Mem_ISR_IT; + hi2c->Devaddress = DevAddress; + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Prefetch Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; + } + /* If Memory address size is 16Bit */ + else + { + /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + + /* Prepare Memaddress buffer for LSB part */ + hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); + } + /* Send Slave Address and Memory Address */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Mem_ISR_IT; + hi2c->Devaddress = DevAddress; + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Prefetch Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; + } + /* If Memory address size is 16Bit */ + else + { + /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + + /* Prepare Memaddress buffer for LSB part */ + hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); + } + /* Send Slave Address and Memory Address */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Mem_ISR_DMA; + hi2c->Devaddress = DevAddress; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + } + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Prefetch Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; + } + /* If Memory address size is 16Bit */ + else + { + /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + + /* Prepare Memaddress buffer for LSB part */ + hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); + } + + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hi2c->hdmatx->LinkedListQueue != NULL) + { + /* Set DMA data size */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize; + + /* Set DMA source address */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData; + + /* Set DMA destination address */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] \ + = (uint32_t)&hi2c->Instance->TXDR; + + dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); + } + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address and Memory Address */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be read + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Mem_ISR_DMA; + hi2c->Devaddress = DevAddress; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + } + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Prefetch Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; + } + /* If Memory address size is 16Bit */ + else + { + /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + + /* Prepare Memaddress buffer for LSB part */ + hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); + } + + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hi2c->hdmarx->LinkedListQueue != NULL) + { + /* Set DMA data size */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize; + + /* Set DMA source address */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] \ + = (uint32_t)&hi2c->Instance->RXDR; + + /* Set DMA destination address */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData; + + dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, + hi2c->XferSize); + } + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address and Memory Address */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Checks if target device is ready for communication. + * @note This function is used with Memory devices + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param Trials Number of trials + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, + uint32_t Timeout) +{ + uint32_t tickstart; + + __IO uint32_t I2C_Trials = 0UL; + + FlagStatus tmp1; + FlagStatus tmp2; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + do + { + /* Generate Start */ + hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress); + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is set or a NACK flag is set*/ + tickstart = HAL_GetTick(); + + tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF); + tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); + + while ((tmp1 == RESET) && (tmp2 == RESET)) + { + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + + tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF); + tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); + } + + /* Check if the NACKF flag has not been set */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) + { + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Device is ready */ + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Clear STOP Flag, auto generated with autoend*/ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } + + /* Increment Trials */ + I2C_Trials++; + } while (I2C_Trials < Trials); + + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt. + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) +{ + uint32_t xfermode; + uint32_t xferrequest = I2C_GENERATE_START_WRITE; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Master_ISR_IT; + + /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = hi2c->XferOptions; + } + + /* If transfer direction not change and there is no request to start another frame, + do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \ + (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + { + xferrequest = I2C_NO_STARTSTOP; + } + else + { + /* Convert OTHER_xxx XferOptions if any */ + I2C_ConvertOtherXferOptions(hi2c); + + /* Update xfermode accordingly if no reload is necessary */ + if (hi2c->XferCount <= MAX_NBYTE_SIZE) + { + xfermode = hi2c->XferOptions; + } + } + + /* Send Slave Address and set NBYTES to write */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA. + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) +{ + uint32_t xfermode; + uint32_t xferrequest = I2C_GENERATE_START_WRITE; + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Master_ISR_DMA; + + /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = hi2c->XferOptions; + } + + /* If transfer direction not change and there is no request to start another frame, + do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \ + (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + { + xferrequest = I2C_NO_STARTSTOP; + } + else + { + /* Convert OTHER_xxx XferOptions if any */ + I2C_ConvertOtherXferOptions(hi2c); + + /* Update xfermode accordingly if no reload is necessary */ + if (hi2c->XferCount <= MAX_NBYTE_SIZE) + { + xfermode = hi2c->XferOptions; + } + } + + if (hi2c->XferSize > 0U) + { + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hi2c->hdmatx->LinkedListQueue != NULL) + { + /* Set DMA data size */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize; + + /* Set DMA source address */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData; + + /* Set DMA destination address */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] \ + = (uint32_t)&hi2c->Instance->TXDR; + + dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); + } + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address and set NBYTES to write */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Update Transfer ISR function pointer */ + hi2c->XferISR = I2C_Master_ISR_IT; + + /* Send Slave Address */ + /* Set NBYTES to write and generate START condition */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) +{ + uint32_t xfermode; + uint32_t xferrequest = I2C_GENERATE_START_READ; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Master_ISR_IT; + + /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = hi2c->XferOptions; + } + + /* If transfer direction not change and there is no request to start another frame, + do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \ + (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + { + xferrequest = I2C_NO_STARTSTOP; + } + else + { + /* Convert OTHER_xxx XferOptions if any */ + I2C_ConvertOtherXferOptions(hi2c); + + /* Update xfermode accordingly if no reload is necessary */ + if (hi2c->XferCount <= MAX_NBYTE_SIZE) + { + xfermode = hi2c->XferOptions; + } + } + + /* Send Slave Address and set NBYTES to read */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) +{ + uint32_t xfermode; + uint32_t xferrequest = I2C_GENERATE_START_READ; + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Master_ISR_DMA; + + /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = hi2c->XferOptions; + } + + /* If transfer direction not change and there is no request to start another frame, + do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \ + (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + { + xferrequest = I2C_NO_STARTSTOP; + } + else + { + /* Convert OTHER_xxx XferOptions if any */ + I2C_ConvertOtherXferOptions(hi2c); + + /* Update xfermode accordingly if no reload is necessary */ + if (hi2c->XferCount <= MAX_NBYTE_SIZE) + { + xfermode = hi2c->XferOptions; + } + } + + if (hi2c->XferSize > 0U) + { + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hi2c->hdmarx->LinkedListQueue != NULL) + { + /* Set DMA data size */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize; + + /* Set DMA source address */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] \ + = (uint32_t)&hi2c->Instance->RXDR; + + /* Set DMA destination address */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData; + + dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx); + } + else + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, + hi2c->XferSize); + } + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address and set NBYTES to read */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Update Transfer ISR function pointer */ + hi2c->XferISR = I2C_Master_ISR_IT; + + /* Send Slave Address */ + /* Set NBYTES to read and generate START condition */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_READ); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) +{ + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + FlagStatus tmp; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave RX state to TX state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + /* Disable associated Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Abort DMA Xfer if any */ + if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + } +#endif /* HAL_DMA_MODULE_ENABLED */ + } + + hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Slave_ISR_IT; + + tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); + if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET)) + { + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the Master */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* REnable ADDR interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) +{ + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + FlagStatus tmp; + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave RX state to TX state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + /* Disable associated Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + + if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + { + /* Abort DMA Xfer if any */ + if (hi2c->hdmarx != NULL) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + } + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* Abort DMA Xfer if any */ + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + } + } + else + { + /* Nothing to do */ + } + + hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Slave_ISR_DMA; + + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hi2c->hdmatx->LinkedListQueue != NULL) + { + /* Set DMA data size */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize; + + /* Set DMA source address */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData; + + /* Set DMA destination address */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] \ + = (uint32_t)&hi2c->Instance->TXDR; + + dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); + } + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Reset XferSize */ + hi2c->XferSize = 0; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); + if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET)) + { + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the Master */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) +{ + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + FlagStatus tmp; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave TX state to RX state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + /* Disable associated Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + +#if defined(HAL_DMA_MODULE_ENABLED) + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* Abort DMA Xfer if any */ + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + } +#endif /* HAL_DMA_MODULE_ENABLED */ + } + + hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Slave_ISR_IT; + + tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); + if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET)) + { + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the Master */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* REnable ADDR interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) +{ + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + FlagStatus tmp; + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave TX state to RX state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + /* Disable associated Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + { + /* Abort DMA Xfer if any */ + if (hi2c->hdmatx != NULL) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + } + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + /* Abort DMA Xfer if any */ + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + } + } + else + { + /* Nothing to do */ + } + + hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Slave_ISR_DMA; + + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hi2c->hdmarx->LinkedListQueue != NULL) + { + /* Set DMA data size */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize; + + /* Set DMA source address */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] \ + = (uint32_t)&hi2c->Instance->RXDR; + + /* Set DMA destination address */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData; + + dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, + hi2c->XferSize); + } + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Reset XferSize */ + hi2c->XferSize = 0; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); + if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET)) + { + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the Master */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* REnable ADDR interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Enable the Address listen mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c) +{ + if (hi2c->State == HAL_I2C_STATE_READY) + { + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->XferISR = I2C_Slave_ISR_IT; + + /* Enable the Address Match interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Disable the Address listen mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + uint32_t tmp; + + /* Disable Address listen mode only if a transfer is not ongoing */ + if (hi2c->State == HAL_I2C_STATE_LISTEN) + { + tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK; + hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode); + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferISR = NULL; + + /* Disable the Address Match interrupt */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Abort a master I2C IT or DMA process communication with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) +{ + if (hi2c->Mode == HAL_I2C_MODE_MASTER) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Disable Interrupts and Store Previous state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + } + else + { + /* Do nothing */ + } + + /* Set State at HAL_I2C_STATE_ABORT */ + hi2c->State = HAL_I2C_STATE_ABORT; + + /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */ + /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */ + I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + + return HAL_OK; + } + else + { + /* Wrong usage of abort function */ + /* This function should be used only in case of abort monitored by master device */ + return HAL_ERROR; + } +} + +/** + * @} + */ + +/** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks + * @{ + */ + +/** + * @brief This function handles I2C event interrupt request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) /* Derogation MISRAC2012-Rule-8.13 */ +{ + /* Get current IT Flags and IT sources value */ + uint32_t itflags = READ_REG(hi2c->Instance->ISR); + uint32_t itsources = READ_REG(hi2c->Instance->CR1); + + /* I2C events treatment -------------------------------------*/ + if (hi2c->XferISR != NULL) + { + hi2c->XferISR(hi2c, itflags, itsources); + } +} + +/** + * @brief This function handles I2C error interrupt request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) +{ + uint32_t itflags = READ_REG(hi2c->Instance->ISR); + uint32_t itsources = READ_REG(hi2c->Instance->CR1); + uint32_t tmperror; + + /* I2C Bus error interrupt occurred ------------------------------------*/ + if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_BERR; + + /* Clear BERR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); + } + + /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/ + if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_OVR; + + /* Clear OVR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); + } + + /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/ + if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && \ + (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO; + + /* Clear ARLO flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); + } + + /* Store current volatile hi2c->ErrorCode, misra rule */ + tmperror = hi2c->ErrorCode; + + /* Call the Error Callback in case of Error detected */ + if ((tmperror & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE) + { + I2C_ITError(hi2c, tmperror); + } +} + +/** + * @brief Master Tx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MasterTxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Master Rx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MasterRxCpltCallback could be implemented in the user file + */ +} + +/** @brief Slave Tx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Slave Rx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Slave Address Match callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION + * @param AddrMatchCode Address Match Code + * @retval None + */ +__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + UNUSED(TransferDirection); + UNUSED(AddrMatchCode); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_AddrCallback() could be implemented in the user file + */ +} + +/** + * @brief Listen Complete callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_ListenCpltCallback() could be implemented in the user file + */ +} + +/** + * @brief Memory Tx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MemTxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Memory Rx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MemRxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief I2C error callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_ErrorCallback could be implemented in the user file + */ +} + +/** + * @brief I2C abort callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_AbortCpltCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions + * @brief Peripheral State, Mode and Error functions + * +@verbatim + =============================================================================== + ##### Peripheral State, Mode and Error functions ##### + =============================================================================== + [..] + This subsection permit to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the I2C handle state. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL state + */ +HAL_I2C_StateTypeDef HAL_I2C_GetState(const I2C_HandleTypeDef *hi2c) +{ + /* Return I2C handle state */ + return hi2c->State; +} + +/** + * @brief Returns the I2C Master, Slave, Memory or no mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL mode + */ +HAL_I2C_ModeTypeDef HAL_I2C_GetMode(const I2C_HandleTypeDef *hi2c) +{ + return hi2c->Mode; +} + +/** + * @brief Return the I2C error code. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval I2C Error Code + */ +uint32_t HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c) +{ + return hi2c->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup I2C_Private_Functions + * @{ + */ + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint16_t devaddress; + uint32_t tmpITFlags = ITFlags; + + /* Process Locked */ + __HAL_LOCK(hi2c); + + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set corresponding Error Code */ + /* No need to generate STOP, it is automatically done */ + /* Error callback will be send during stop flag treatment */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + { + /* Remove RXNE flag on temporary variable as read done */ + tmpITFlags &= ~I2C_FLAG_RXNE; + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + { + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD); + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + { + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, + hi2c->XferOptions, I2C_NO_STARTSTOP); + } + else + { + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, + I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + } + } + else + { + /* Call TxCpltCallback() if no stop mode is set */ + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + { + /* Call I2C Master Sequential complete process */ + I2C_ITMasterSeqCplt(hi2c); + } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + if (hi2c->XferCount == 0U) + { + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + { + /* Generate a stop condition in case of no transfer option */ + if (hi2c->XferOptions == I2C_NO_OPTION_FRAME) + { + /* Generate Stop */ + hi2c->Instance->CR2 |= I2C_CR2_STOP; + } + else + { + /* Call I2C Master Sequential complete process */ + I2C_ITMasterSeqCplt(hi2c); + } + } + } + else + { + /* Wrong size Status regarding TC flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + else + { + /* Nothing to do */ + } + + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Master complete process */ + I2C_ITMasterCplt(hi2c, tmpITFlags); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint32_t direction = I2C_GENERATE_START_WRITE; + uint32_t tmpITFlags = ITFlags; + + /* Process Locked */ + __HAL_LOCK(hi2c); + + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set corresponding Error Code */ + /* No need to generate STOP, it is automatically done */ + /* Error callback will be send during stop flag treatment */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + { + /* Remove RXNE flag on temporary variable as read done */ + tmpITFlags &= ~I2C_FLAG_RXNE; + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + { + if (hi2c->Memaddress == 0xFFFFFFFFU) + { + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + } + else + { + /* Write LSB part of Memory Address */ + hi2c->Instance->TXDR = hi2c->Memaddress; + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + /* Disable Interrupt related to address step */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Enable ERR, TC, STOP, NACK and RXI interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + direction = I2C_GENERATE_START_READ; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_RELOAD_MODE, direction); + } + else + { + hi2c->XferSize = hi2c->XferCount; + + /* Set NBYTES to write and generate RESTART */ + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_AUTOEND_MODE, direction); + } + } + else + { + /* Nothing to do */ + } + + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Master complete process */ + I2C_ITMasterCplt(hi2c, tmpITFlags); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint32_t tmpoptions = hi2c->XferOptions; + uint32_t tmpITFlags = ITFlags; + + /* Process locked */ + __HAL_LOCK(hi2c); + + /* Check if STOPF is set */ + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Slave complete process */ + I2C_ITSlaveCplt(hi2c, tmpITFlags); + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Check that I2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0*/ + /* So clear Flag NACKF only */ + if (hi2c->XferCount == 0U) + { + if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) + /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + Warning[Pa134]: left and right operands are identical */ + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, tmpITFlags); + } + else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + } + else + { + /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + } + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + { + if (hi2c->XferCount > 0U) + { + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + } + + if ((hi2c->XferCount == 0U) && \ + (tmpoptions != I2C_NO_OPTION_FRAME)) + { + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) + { + I2C_ITAddrCplt(hi2c, tmpITFlags); + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + { + /* Write data to TXDR only if XferCount not reach "0" */ + /* A TXIS flag can be set, during STOP treatment */ + /* Check if all Data have already been sent */ + /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ + if (hi2c->XferCount > 0U) + { + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + } + else + { + if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME)) + { + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + } + } + else + { + /* Nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint16_t devaddress; + uint32_t xfermode; + + /* Process Locked */ + __HAL_LOCK(hi2c); + + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set corresponding Error Code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* No need to generate STOP, it is automatically done */ + /* But enable STOP interrupt, to treat it */ + /* Error callback will be send during stop flag treatment */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + /* Disable TC interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI); + + if (hi2c->XferCount != 0U) + { + /* Recover Slave address */ + devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD); + + /* Prepare the new XferSize to transfer */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + { + xfermode = hi2c->XferOptions; + } + else + { + xfermode = I2C_AUTOEND_MODE; + } + } + + /* Set the new XferSize in Nbytes register */ + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Enable DMA Request */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + } + else + { + /* Call TxCpltCallback() if no stop mode is set */ + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + { + /* Call I2C Master Sequential complete process */ + I2C_ITMasterSeqCplt(hi2c); + } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + if (hi2c->XferCount == 0U) + { + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + { + /* Generate a stop condition in case of no transfer option */ + if (hi2c->XferOptions == I2C_NO_OPTION_FRAME) + { + /* Generate Stop */ + hi2c->Instance->CR2 |= I2C_CR2_STOP; + } + else + { + /* Call I2C Master Sequential complete process */ + I2C_ITMasterSeqCplt(hi2c); + } + } + } + else + { + /* Wrong size Status regarding TC flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Master complete process */ + I2C_ITMasterCplt(hi2c, ITFlags); + } + else + { + /* Nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with DMA. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint32_t direction = I2C_GENERATE_START_WRITE; + + /* Process Locked */ + __HAL_LOCK(hi2c); + + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set corresponding Error Code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* No need to generate STOP, it is automatically done */ + /* But enable STOP interrupt, to treat it */ + /* Error callback will be send during stop flag treatment */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TXIS) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + { + /* Write LSB part of Memory Address */ + hi2c->Instance->TXDR = hi2c->Memaddress; + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + /* Disable Interrupt related to address step */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Enable only Error interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + if (hi2c->XferCount != 0U) + { + /* Prepare the new XferSize to transfer */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Enable DMA Request */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + /* Disable Interrupt related to address step */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Enable only Error and NACK interrupt for data transfer */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + direction = I2C_GENERATE_START_READ; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_RELOAD_MODE, direction); + } + else + { + hi2c->XferSize = hi2c->XferCount; + + /* Set NBYTES to write and generate RESTART */ + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_AUTOEND_MODE, direction); + } + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Enable DMA Request */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Master complete process */ + I2C_ITMasterCplt(hi2c, ITFlags); + } + else + { + /* Nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint32_t tmpoptions = hi2c->XferOptions; + uint32_t treatdmanack = 0U; + HAL_I2C_StateTypeDef tmpstate; + + /* Process locked */ + __HAL_LOCK(hi2c); + + /* Check if STOPF is set */ + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Slave complete process */ + I2C_ITSlaveCplt(hi2c, ITFlags); + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Check that I2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0 */ + /* So clear Flag NACKF only */ + if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) || + (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)) + { + /* Split check of hdmarx, for MISRA compliance */ + if (hi2c->hdmarx != NULL) + { + if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET) + { + if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) + { + treatdmanack = 1U; + } + } + } + + /* Split check of hdmatx, for MISRA compliance */ + if (hi2c->hdmatx != NULL) + { + if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) + { + if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx) == 0U) + { + treatdmanack = 1U; + } + } + } + + if (treatdmanack == 1U) + { + if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) + /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + Warning[Pa134]: left and right operands are identical */ + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, ITFlags); + } + else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + } + else + { + /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* Store current hi2c->State, solve MISRA2012-Rule-13.5 */ + tmpstate = hi2c->State; + + if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) + { + if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN)) + { + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + } + else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + } + else + { + /* Do nothing */ + } + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + } + } + } + else + { + /* Only Clear NACK Flag, no DMA treatment is pending */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) + { + I2C_ITAddrCplt(hi2c, ITFlags); + } + else + { + /* Nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Master sends target device address followed by internal memory address for write request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart) +{ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); + + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Send Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + } + /* If Memory address size is 16Bit */ + else + { + /* Send MSB of Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Send LSB of Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + } + + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Master sends target device address followed by internal memory address for read request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart) +{ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); + + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Send Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + } + /* If Memory address size is 16Bit */ + else + { + /* Send MSB of Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Send LSB of Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + } + + /* Wait until TC flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief I2C Address complete process callback. + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. + * @retval None + */ +static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + uint8_t transferdirection; + uint16_t slaveaddrcode; + uint16_t ownadd1code; + uint16_t ownadd2code; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(ITFlags); + + /* In case of Listen state, need to inform upper layer of address match code event */ + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + transferdirection = I2C_GET_DIR(hi2c); + slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c); + ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c); + ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c); + + /* If 10bits addressing mode is selected */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + { + if ((slaveaddrcode & SLAVE_ADDR_MSK) == ((ownadd1code >> SLAVE_ADDR_SHIFT) & SLAVE_ADDR_MSK)) + { + slaveaddrcode = ownadd1code; + hi2c->AddrEventCount++; + if (hi2c->AddrEventCount == 2U) + { + /* Reset Address Event counter */ + hi2c->AddrEventCount = 0U; + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call Slave Addr callback */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); +#else + HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + else + { + slaveaddrcode = ownadd2code; + + /* Disable ADDR Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call Slave Addr callback */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); +#else + HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + /* else 7 bits addressing mode is selected */ + else + { + /* Disable ADDR Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call Slave Addr callback */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); +#else + HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + /* Else clear address flag only */ + else + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + } +} + +/** + * @brief I2C Master sequential complete process. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c) +{ + /* Reset I2C handle mode */ + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* No Generate Stop, to permit restart mode */ + /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + hi2c->XferISR = NULL; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterTxCpltCallback(hi2c); +#else + HAL_I2C_MasterTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ + else + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + hi2c->XferISR = NULL; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterRxCpltCallback(hi2c); +#else + HAL_I2C_MasterRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } +} + +/** + * @brief I2C Slave sequential complete process. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c) +{ + uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); + + /* Reset I2C handle mode */ + hi2c->Mode = HAL_I2C_MODE_NONE; + +#if defined(HAL_DMA_MODULE_ENABLED) + /* If a DMA is ongoing, Update handle size context */ + if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + } + else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + } + else + { + /* Do nothing */ + } +#endif /* HAL_DMA_MODULE_ENABLED */ + + if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveTxCpltCallback(hi2c); +#else + HAL_I2C_SlaveTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveRxCpltCallback(hi2c); +#else + HAL_I2C_SlaveRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + /* Nothing to do */ + } +} + +/** + * @brief I2C Master complete process. + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. + * @retval None + */ +static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + uint32_t tmperror; + uint32_t tmpITFlags = ITFlags; + __IO uint32_t tmpreg; + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Disable Interrupts and Store Previous state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + } + else + { + /* Do nothing */ + } + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + /* Reset handle parameters */ + hi2c->XferISR = NULL; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set acknowledge error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + + /* Fetch Last receive data if any */ + if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)) + { + /* Read data from RXDR */ + tmpreg = (uint8_t)hi2c->Instance->RXDR; + UNUSED(tmpreg); + } + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Store current volatile hi2c->ErrorCode, misra rule */ + tmperror = hi2c->ErrorCode; + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + if ((hi2c->State == HAL_I2C_STATE_ABORT) || (tmperror != HAL_I2C_ERROR_NONE)) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + } + /* hi2c->State == HAL_I2C_STATE_BUSY_TX */ + else if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + if (hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MemTxCpltCallback(hi2c); +#else + HAL_I2C_MemTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterTxCpltCallback(hi2c); +#else + HAL_I2C_MasterTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + if (hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MemRxCpltCallback(hi2c); +#else + HAL_I2C_MemRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterRxCpltCallback(hi2c); +#else + HAL_I2C_MasterRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + else + { + /* Nothing to do */ + } +} + +/** + * @brief I2C Slave complete process. + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. + * @retval None + */ +static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); + uint32_t tmpITFlags = ITFlags; + uint32_t tmpoptions = hi2c->XferOptions; + HAL_I2C_StateTypeDef tmpstate = hi2c->State; + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Disable Interrupts and Store Previous state */ + if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN)) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + } + else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + } + else if (tmpstate == HAL_I2C_STATE_LISTEN) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_NONE; + } + else + { + /* Do nothing */ + } + + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* If a DMA is ongoing, Update handle size context */ + if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + if (hi2c->hdmatx != NULL) + { + hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx); + } + } + else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + if (hi2c->hdmarx != NULL) + { + hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx); + } + } + else + { + /* Do nothing */ + } +#endif /* HAL_DMA_MODULE_ENABLED */ + + /* Store Last receive data if any */ + if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) + { + /* Remove RXNE flag on temporary variable as read done */ + tmpITFlags &= ~I2C_FLAG_RXNE; + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + if ((hi2c->XferSize > 0U)) + { + hi2c->XferSize--; + hi2c->XferCount--; + } + } + + /* All data are not transferred, so set error code accordingly */ + if (hi2c->XferCount != 0U) + { + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_IT_NACKI) != RESET)) + { + /* Check that I2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0*/ + /* So clear Flag NACKF only */ + if (hi2c->XferCount == 0U) + { + if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) + /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + Warning[Pa134]: left and right operands are identical */ + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, tmpITFlags); + } + else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + } + else + { + /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + } + } + } + + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferISR = NULL; + + if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ + if (hi2c->State == HAL_I2C_STATE_LISTEN) + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, tmpITFlags); + } + } + else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + { + /* Call the Sequential Complete callback, to inform upper layer of the end of Transfer */ + I2C_ITSlaveSeqCplt(hi2c); + + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ListenCpltCallback(hi2c); +#else + HAL_I2C_ListenCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + /* Call the corresponding callback to inform upper layer of End of Transfer */ + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveRxCpltCallback(hi2c); +#else + HAL_I2C_SlaveRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveTxCpltCallback(hi2c); +#else + HAL_I2C_SlaveTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } +} + +/** + * @brief I2C Listen complete process. + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. + * @retval None + */ +static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + /* Reset handle parameters */ + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferISR = NULL; + + /* Store Last receive data if any */ + if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET) + { + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + if ((hi2c->XferSize > 0U)) + { + hi2c->XferSize--; + hi2c->XferCount--; + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + } + + /* Disable all Interrupts*/ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); + + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ListenCpltCallback(hi2c); +#else + HAL_I2C_ListenCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +} + +/** + * @brief I2C interrupts error process. + * @param hi2c I2C handle. + * @param ErrorCode Error code to handle. + * @retval None + */ +static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) +{ + HAL_I2C_StateTypeDef tmpstate = hi2c->State; + +#if defined(HAL_DMA_MODULE_ENABLED) + uint32_t tmppreviousstate; +#endif /* HAL_DMA_MODULE_ENABLED */ + + /* Reset handle parameters */ + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferCount = 0U; + + /* Set new error code */ + hi2c->ErrorCode |= ErrorCode; + + /* Disable Interrupts */ + if ((tmpstate == HAL_I2C_STATE_LISTEN) || + (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) || + (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + /* Disable all interrupts, except interrupts related to LISTEN state */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT); + + /* keep HAL_I2C_STATE_LISTEN if set */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->XferISR = I2C_Slave_ISR_IT; + } + else + { + /* Disable all interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* If state is an abort treatment on going, don't change state */ + /* This change will be do later */ + if (hi2c->State != HAL_I2C_STATE_ABORT) + { + /* Set HAL_I2C_STATE_READY */ + hi2c->State = HAL_I2C_STATE_READY; + + /* Check if a STOPF is detected */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + { + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } + + } + hi2c->XferISR = NULL; + } + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Abort DMA TX transfer if any */ + tmppreviousstate = hi2c->PreviousState; + + if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \ + (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX))) + { + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + } + + if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + else + { + I2C_TreatErrorCallback(hi2c); + } + } + /* Abort DMA RX transfer if any */ + else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || \ + (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX))) + { + if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + } + + if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + else + { + I2C_TreatErrorCallback(hi2c); + } + } + else +#endif /* HAL_DMA_MODULE_ENABLED */ + { + I2C_TreatErrorCallback(hi2c); + } +} + +/** + * @brief I2C Error callback treatment. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c) +{ + if (hi2c->State == HAL_I2C_STATE_ABORT) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AbortCpltCallback(hi2c); +#else + HAL_I2C_AbortCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->PreviousState = I2C_STATE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ErrorCallback(hi2c); +#else + HAL_I2C_ErrorCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } +} + +/** + * @brief I2C Tx data register flush process. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c) +{ + /* If a pending TXIS flag is set */ + /* Write a dummy data in TXDR to clear it */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET) + { + hi2c->Instance->TXDR = 0x00U; + } + + /* Flush TX register if not empty */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) + { + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE); + } +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief DMA I2C master transmit process complete callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) +{ + HAL_StatusTypeDef dmaxferstatus = HAL_OK; + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* If last transfer, enable STOP interrupt */ + if (hi2c->XferCount == 0U) + { + /* Enable STOP interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + } + /* else prepare a new DMA transfer and enable TCReload interrupt */ + else + { + /* Update Buffer pointer */ + hi2c->pBuffPtr += hi2c->XferSize; + + /* Set the XferSize to transfer */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + } + + /* Enable the DMA channel */ + if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hi2c->hdmatx->LinkedListQueue != NULL) + { + /* Set DMA data size */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize; + + /* Set DMA source address */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)hi2c->pBuffPtr; + + /* Set DMA destination address */ + hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)&hi2c->Instance->TXDR; + + dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx); + } + else + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); + } + } + else + { + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); + } + + if (dmaxferstatus != HAL_OK) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); + } + else + { + /* Enable TC interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); + } + } +} + + +/** + * @brief DMA I2C slave transmit process complete callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) +{ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + uint32_t tmpoptions = hi2c->XferOptions; + + if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME)) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* No specific action, Master fully manage the generation of STOP condition */ + /* Mean that this generation can arrive at any time, at the end or during DMA process */ + /* So STOP condition should be manage through Interrupt treatment */ + } +} + + +/** + * @brief DMA I2C master receive process complete callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) +{ + HAL_StatusTypeDef dmaxferstatus = HAL_OK; + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + /* If last transfer, enable STOP interrupt */ + if (hi2c->XferCount == 0U) + { + /* Enable STOP interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + } + /* else prepare a new DMA transfer and enable TCReload interrupt */ + else + { + /* Update Buffer pointer */ + hi2c->pBuffPtr += hi2c->XferSize; + + /* Set the XferSize to transfer */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + } + + /* Enable the DMA channel */ + if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hi2c->hdmarx->LinkedListQueue != NULL) + { + /* Set DMA data size */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize; + + /* Set DMA source address */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)&hi2c->Instance->RXDR; + + /* Set DMA destination address */ + hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)hi2c->pBuffPtr; + + dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx); + } + else + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); + } + } + else + { + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, + hi2c->XferSize); + } + + if (dmaxferstatus != HAL_OK) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); + } + else + { + /* Enable TC interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); + } + } +} + + +/** + * @brief DMA I2C slave receive process complete callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) +{ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + uint32_t tmpoptions = hi2c->XferOptions; + + if ((I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) && \ + (tmpoptions != I2C_NO_OPTION_FRAME)) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* No specific action, Master fully manage the generation of STOP condition */ + /* Mean that this generation can arrive at any time, at the end or during DMA process */ + /* So STOP condition should be manage through Interrupt treatment */ + } +} + + +/** + * @brief DMA I2C communication error callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMAError(DMA_HandleTypeDef *hdma) +{ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + + /* Disable Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); +} + + +/** + * @brief DMA I2C communication abort callback + * (To be called at end of DMA Abort procedure). + * @param hdma DMA handle. + * @retval None + */ +static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) +{ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + + /* Reset AbortCpltCallback */ + if (hi2c->hdmatx != NULL) + { + hi2c->hdmatx->XferAbortCallback = NULL; + } + if (hi2c->hdmarx != NULL) + { + hi2c->hdmarx->XferAbortCallback = NULL; + } + + I2C_TreatErrorCallback(hi2c); +} + +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief This function handles I2C Communication Timeout. It waits + * until a flag is no longer in the specified status. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Flag Specifies the I2C flag to check. + * @param Status The actual Flag status (SET or RESET). + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, + uint32_t Timeout, uint32_t Tickstart) +{ + while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) + { + /* Check if an error is detected */ + if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of TXIS flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart) +{ + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) + { + /* Check if an error is detected */ + if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of STOP flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart) +{ + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + { + /* Check if an error is detected */ + if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check for the Timeout */ + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart) +{ + HAL_StatusTypeDef status = HAL_OK; + + while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) && (status == HAL_OK)) + { + /* Check if an error is detected */ + if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) + { + status = HAL_ERROR; + } + + /* Check if a STOPF is detected */ + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) && (status == HAL_OK)) + { + /* Check if an RXNE is pending */ + /* Store Last receive data if any */ + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U)) + { + /* Return HAL_OK */ + /* The Reading of data from RXDR will be done in caller function */ + status = HAL_OK; + } + + /* Check a no-acknowledge have been detected */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + { + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + hi2c->ErrorCode = HAL_I2C_ERROR_AF; + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + status = HAL_ERROR; + } + else + { + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + } + } + + /* Check for the Timeout */ + if ((((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) && (status == HAL_OK)) + { + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + status = HAL_ERROR; + } + } + } + return status; +} + +/** + * @brief This function handles errors detection during an I2C Communication. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t itflag = hi2c->Instance->ISR; + uint32_t error_code = 0; + uint32_t tickstart = Tickstart; + uint32_t tmp1; + HAL_I2C_ModeTypeDef tmp2; + + if (HAL_IS_BIT_SET(itflag, I2C_FLAG_AF)) + { + /* Clear NACKF Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Wait until STOP Flag is set or timeout occurred */ + /* AutoEnd should be initiate after AF */ + while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK)) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + tmp1 = (uint32_t)(hi2c->Instance->CR2 & I2C_CR2_STOP); + tmp2 = hi2c->Mode; + + /* In case of I2C still busy, try to regenerate a STOP manually */ + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && \ + (tmp1 != I2C_CR2_STOP) && \ + (tmp2 != HAL_I2C_MODE_SLAVE)) + { + /* Generate Stop */ + hi2c->Instance->CR2 |= I2C_CR2_STOP; + + /* Update Tick with new reference */ + tickstart = HAL_GetTick(); + } + + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > I2C_TIMEOUT_STOPF) + { + error_code |= HAL_I2C_ERROR_TIMEOUT; + + status = HAL_ERROR; + + break; + } + } + } + } + } + + /* In case STOP Flag is detected, clear it */ + if (status == HAL_OK) + { + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } + + error_code |= HAL_I2C_ERROR_AF; + + status = HAL_ERROR; + } + + /* Refresh Content of Status register */ + itflag = hi2c->Instance->ISR; + + /* Then verify if an additional errors occurs */ + /* Check if a Bus error occurred */ + if (HAL_IS_BIT_SET(itflag, I2C_FLAG_BERR)) + { + error_code |= HAL_I2C_ERROR_BERR; + + /* Clear BERR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); + + status = HAL_ERROR; + } + + /* Check if an Over-Run/Under-Run error occurred */ + if (HAL_IS_BIT_SET(itflag, I2C_FLAG_OVR)) + { + error_code |= HAL_I2C_ERROR_OVR; + + /* Clear OVR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); + + status = HAL_ERROR; + } + + /* Check if an Arbitration Loss error occurred */ + if (HAL_IS_BIT_SET(itflag, I2C_FLAG_ARLO)) + { + error_code |= HAL_I2C_ERROR_ARLO; + + /* Clear ARLO flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); + + status = HAL_ERROR; + } + + if (status != HAL_OK) + { + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->ErrorCode |= error_code; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + } + + return status; +} + +/** + * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set). + * @param hi2c I2C handle. + * @param DevAddress Specifies the slave address to be programmed. + * @param Size Specifies the number of bytes to be programmed. + * This parameter must be a value between 0 and 255. + * @param Mode New state of the I2C START condition generation. + * This parameter can be one of the following values: + * @arg @ref I2C_RELOAD_MODE Enable Reload mode . + * @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode. + * @arg @ref I2C_SOFTEND_MODE Enable Software end mode. + * @param Request New state of the I2C START condition generation. + * This parameter can be one of the following values: + * @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition. + * @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0). + * @arg @ref I2C_GENERATE_START_READ Generate Restart for read request. + * @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request. + * @retval None + */ +static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, + uint32_t Request) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_TRANSFER_MODE(Mode)); + assert_param(IS_TRANSFER_REQUEST(Request)); + + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ + (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ + (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); + + /* update CR2 register */ + MODIFY_REG(hi2c->Instance->CR2, \ + ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \ + (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \ + I2C_CR2_START | I2C_CR2_STOP)), tmp); +} + +/** + * @brief Manage the enabling of Interrupts. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. + * @retval None + */ +static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) +{ + uint32_t tmpisr = 0U; + +#if defined(HAL_DMA_MODULE_ENABLED) + if ((hi2c->XferISR != I2C_Master_ISR_DMA) && \ + (hi2c->XferISR != I2C_Slave_ISR_DMA) && \ + (hi2c->XferISR != I2C_Mem_ISR_DMA)) +#endif /* HAL_DMA_MODULE_ENABLED */ + { + if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + { + /* Enable ERR, STOP, NACK and ADDR interrupts */ + tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + + if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + { + /* Enable ERR, TC, STOP, NACK and TXI interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; + } + + if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + { + /* Enable ERR, TC, STOP, NACK and RXI interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; + } + + if (InterruptRequest == I2C_XFER_ERROR_IT) + { + /* Enable ERR and NACK interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; + } + + if (InterruptRequest == I2C_XFER_CPLT_IT) + { + /* Enable STOP interrupts */ + tmpisr |= I2C_IT_STOPI; + } + } + +#if defined(HAL_DMA_MODULE_ENABLED) + else + { + if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + { + /* Enable ERR, STOP, NACK and ADDR interrupts */ + tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + + if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + { + /* Enable ERR, TC, STOP, NACK and TXI interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; + } + + if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + { + /* Enable ERR, TC, STOP, NACK and RXI interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; + } + + if (InterruptRequest == I2C_XFER_ERROR_IT) + { + /* Enable ERR and NACK interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; + } + + if (InterruptRequest == I2C_XFER_CPLT_IT) + { + /* Enable STOP interrupts */ + tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI); + } + + if (InterruptRequest == I2C_XFER_RELOAD_IT) + { + /* Enable TC interrupts */ + tmpisr |= I2C_IT_TCI; + } + } +#endif /* HAL_DMA_MODULE_ENABLED */ + + /* Enable interrupts only at the end */ + /* to avoid the risk of I2C interrupt handle execution before */ + /* all interrupts requested done */ + __HAL_I2C_ENABLE_IT(hi2c, tmpisr); +} + +/** + * @brief Manage the disabling of Interrupts. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. + * @retval None + */ +static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) +{ + uint32_t tmpisr = 0U; + + if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + { + /* Disable TC and TXI interrupts */ + tmpisr |= I2C_IT_TCI | I2C_IT_TXI; + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN) + { + /* Disable NACK and STOP interrupts */ + tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + } + + if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + { + /* Disable TC and RXI interrupts */ + tmpisr |= I2C_IT_TCI | I2C_IT_RXI; + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN) + { + /* Disable NACK and STOP interrupts */ + tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + } + + if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + { + /* Disable ADDR, NACK and STOP interrupts */ + tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + + if (InterruptRequest == I2C_XFER_ERROR_IT) + { + /* Enable ERR and NACK interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; + } + + if (InterruptRequest == I2C_XFER_CPLT_IT) + { + /* Enable STOP interrupts */ + tmpisr |= I2C_IT_STOPI; + } + + if (InterruptRequest == I2C_XFER_RELOAD_IT) + { + /* Enable TC interrupts */ + tmpisr |= I2C_IT_TCI; + } + + /* Disable interrupts only at the end */ + /* to avoid a breaking situation like at "t" time */ + /* all disable interrupts request are not done */ + __HAL_I2C_DISABLE_IT(hi2c, tmpisr); +} + +/** + * @brief Convert I2Cx OTHER_xxx XferOptions to functional XferOptions. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c) +{ + /* if user set XferOptions to I2C_OTHER_FRAME */ + /* it request implicitly to generate a restart condition */ + /* set XferOptions to I2C_FIRST_FRAME */ + if (hi2c->XferOptions == I2C_OTHER_FRAME) + { + hi2c->XferOptions = I2C_FIRST_FRAME; + } + /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */ + /* it request implicitly to generate a restart condition */ + /* then generate a stop condition at the end of transfer */ + /* set XferOptions to I2C_FIRST_AND_LAST_FRAME */ + else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME) + { + hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME; + } + else + { + /* Nothing to do */ + } +} + +/** + * @} + */ + +#endif /* HAL_I2C_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_i2c_ex.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_i2c_ex.c new file mode 100644 index 0000000000..aead07eccd --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_i2c_ex.c @@ -0,0 +1,506 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_i2c_ex.c + * @author MCD Application Team + * @brief I2C Extended HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of I2C Extended peripheral: + * + Filter Mode Functions + * + WakeUp Mode Functions + * + FastModePlus Functions + * + Autonomous Mode Functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### I2C peripheral Extended features ##### + ============================================================================== + + [..] Comparing to other previous devices, the I2C interface for STM32WBAxx + devices contains the following additional features + + (+) Possibility to disable or enable Analog Noise Filter + (+) Use of a configured Digital Noise Filter + (+) Disable or enable wakeup from Stop mode(s) + (+) Disable or enable Fast Mode Plus + (+) Configure Autonomous mode + + ##### How to use this driver ##### + ============================================================================== + [..] This driver provides functions to configure Noise Filter and Wake Up Feature + (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter() + (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter() + (#) Configure the enable or disable of I2C Wake Up Mode using the functions : + (++) HAL_I2CEx_EnableWakeUp() + (++) HAL_I2CEx_DisableWakeUp() + (#) Configure the enable or disable of fast mode plus driving capability using the functions : + (++) HAL_I2CEx_ConfigFastModePlus() + (#) Set or get or clear the autonomous mode configuration using these functions : + (++) HAL_I2CEx_SetConfigAutonomousMode() + (++) HAL_I2CEx_GetConfigAutonomousMode() + (++) HAL_I2CEx_ClearConfigAutonomousMode() + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @defgroup I2CEx I2CEx + * @brief I2C Extended HAL module driver + * @{ + */ + +#ifdef HAL_I2C_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions + * @{ + */ + +/** @defgroup I2CEx_Exported_Functions_Group1 Filter Mode Functions + * @brief Filter Mode Functions + * +@verbatim + =============================================================================== + ##### Filter Mode Functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure Noise Filters + +@endverbatim + * @{ + */ + +/** + * @brief Configure I2C Analog noise filter. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @param AnalogFilter New state of the Analog filter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Reset I2Cx ANOFF bit */ + hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF); + + /* Set analog filter bit*/ + hi2c->Instance->CR1 |= AnalogFilter; + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Configure I2C Digital noise filter. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) +{ + uint32_t tmpreg; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Get the old register value */ + tmpreg = hi2c->Instance->CR1; + + /* Reset I2Cx DNF bits [11:8] */ + tmpreg &= ~(I2C_CR1_DNF); + + /* Set I2Cx DNF coefficient */ + tmpreg |= DigitalFilter << 8U; + + /* Store the new register value */ + hi2c->Instance->CR1 = tmpreg; + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +/** + * @} + */ + +/** @defgroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions + * @brief WakeUp Mode Functions + * +@verbatim + =============================================================================== + ##### WakeUp Mode Functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure Wake Up Feature + +@endverbatim + * @{ + */ + +/** + * @brief Enable I2C wakeup from Stop mode(s). + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c) +{ + /* Check the parameters */ + assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Enable wakeup from stop mode */ + hi2c->Instance->CR1 |= I2C_CR1_WUPEN; + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Disable I2C wakeup from Stop mode(s). + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c) +{ + /* Check the parameters */ + assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Enable wakeup from stop mode */ + hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN); + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +/** + * @} + */ + +/** @defgroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions + * @brief Fast Mode Plus Functions + * +@verbatim + =============================================================================== + ##### Fast Mode Plus Functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure Fast Mode Plus + +@endverbatim + * @{ + */ + +/** + * @brief Configure I2C Fast Mode Plus. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @param FastModePlus New state of the Fast Mode Plus. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_ConfigFastModePlus(I2C_HandleTypeDef *hi2c, uint32_t FastModePlus) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_FASTMODEPLUS(FastModePlus)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + if (FastModePlus == I2C_FASTMODEPLUS_ENABLE) + { + /* Set I2Cx FMP bit */ + hi2c->Instance->CR1 |= (I2C_CR1_FMP); + } + else + { + /* Reset I2Cx FMP bit */ + hi2c->Instance->CR1 &= ~(I2C_CR1_FMP); + } + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @} + */ + +/** @defgroup I2CEx_Exported_Functions_Group4 Autonomous Mode Functions + * @brief Autonomous Mode Functions + * +@verbatim + =============================================================================== + ##### Autonomous Mode functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure Autonomous Mode + +@endverbatim + * @{ + */ + +/** + * @brief Set Autonomous Mode configuration + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @param sConfig Pointer to a I2C_AutonomousModeConfTypeDef structure that contains + * the configuration information of the autonomous mode for the specified I2Cx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_SetConfigAutonomousMode(I2C_HandleTypeDef *hi2c, + const I2C_AutonomousModeConfTypeDef *sConfig) +{ + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Check the parameters */ + assert_param(IS_I2C_TRIG_INPUT_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_TRIG_SOURCE(hi2c->Instance, sConfig->TriggerSelection)); + assert_param(IS_I2C_AUTO_MODE_TRG_POL(sConfig->TriggerPolarity)); + + /* Disable the selected I2C peripheral to be able to configure AUTOCR */ + __HAL_I2C_DISABLE(hi2c); + + /* I2Cx AUTOCR Configuration */ + WRITE_REG(hi2c->Instance->AUTOCR, + (sConfig->TriggerState | \ + ((sConfig->TriggerSelection) & I2C_AUTOCR_TRIGSEL_Msk) | \ + sConfig->TriggerPolarity)); + + /* Enable the selected I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Get Autonomous Mode configuration + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @param sConfig Pointer to a I2C_AutonomousModeConfTypeDef structure that contains + * the configuration information of the autonomous mode for the specified I2Cx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_GetConfigAutonomousMode(const I2C_HandleTypeDef *hi2c, + I2C_AutonomousModeConfTypeDef *sConfig) +{ + uint32_t autocr_tmp; + + /* Check the parameters */ + assert_param(IS_I2C_TRIG_INPUT_INSTANCE(hi2c->Instance)); + + autocr_tmp = hi2c->Instance->AUTOCR; + + sConfig->TriggerState = (autocr_tmp & I2C_AUTOCR_TRIGEN); +#if defined(I2C_TRIG_GRP1) + if (IS_I2C_GRP2_INSTANCE(hi2c->Instance)) + { + sConfig->TriggerSelection = ((autocr_tmp & I2C_AUTOCR_TRIGSEL) | I2C_TRIG_GRP2); + } + else + { + sConfig->TriggerSelection = ((autocr_tmp & I2C_AUTOCR_TRIGSEL) | I2C_TRIG_GRP1); + } +#else + sConfig->TriggerSelection = ((autocr_tmp & I2C_AUTOCR_TRIGSEL) | I2C_TRIG_GRP2); +#endif /* I2C_TRIG_GRP1 */ + sConfig->TriggerPolarity = (autocr_tmp & I2C_AUTOCR_TRIGPOL); + + return HAL_OK; +} + +/** + * @brief Clear Autonomous Mode configuration + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_ClearConfigAutonomousMode(I2C_HandleTypeDef *hi2c) +{ + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Check the parameters */ + assert_param(IS_I2C_TRIG_INPUT_INSTANCE(hi2c->Instance)); + + /* Disable the selected I2C peripheral to be able to clear AUTOCR */ + __HAL_I2C_DISABLE(hi2c); + + CLEAR_REG(hi2c->Instance->AUTOCR); + + /* Enable the selected I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_I2C_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_icache.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_icache.c new file mode 100644 index 0000000000..ebcb7d3199 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_icache.c @@ -0,0 +1,651 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_icache.c + * @author MCD Application Team + * @brief ICACHE HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Instruction Cache (ICACHE). + * + Initialization and Configuration + * + Invalidate functions + * + Monitoring management + * + Memory address remap management + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### ICACHE main features ##### + ============================================================================== + [..] + The Instruction Cache (ICACHE) is introduced on C-AHB code bus of + Cortex-M33 processor to improve performance when fetching instruction + and data from both internal and external memories. It allows close to + zero wait states performance. + + (+) The ICACHE provides two performance counters (Hit and Miss), + cache invalidate maintenance operation, error management and TrustZone + security support. + + (+) The ICACHE provides additionally the possibility to remap input address + falling into up to four memory regions (used to remap aliased code in + external memories to the internal Code region, for execution) + + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + The ICACHE HAL driver can be used as follows: + + (#) Optionally configure the Instruction Cache mode with + HAL_ICACHE_ConfigAssociativityMode() if the default configuration + does not suit the application requirements. + + (#) Enable and disable the Instruction Cache with respectively + HAL_ICACHE_Enable() and HAL_ICACHE_Disable(). + Use HAL_ICACHE_IsEnabled() to get the Instruction Cache status. + To ensure a deterministic cache behavior after power on, system reset or after + a call to @ref HAL_ICACHE_Disable(), the application must call + @ref HAL_ICACHE_WaitForInvalidateComplete(). Indeed on power on, system reset + or cache disable, an automatic cache invalidation procedure is launched and the + cache is bypassed until the operation completes. + + (#) Initiate the cache maintenance invalidation procedure with either + HAL_ICACHE_Invalidate() (blocking mode) or HAL_ICACHE_Invalidate_IT() + (interrupt mode). When interrupt mode is used, the callback function + HAL_ICACHE_InvalidateCompleteCallback() is called when the invalidate + procedure is complete. The function HAL_ICACHE_WaitForInvalidateComplete() + may be called to wait for the end of the invalidate procedure automatically + initiated when disabling the Instruction Cache with HAL_ICACHE_Disable(). + The cache operation is bypassed during the invalidation procedure. + + (#) Use the performance monitoring counters for Hit and Miss with the following + functions: HAL_ICACHE_Monitor_Start(), HAL_ICACHE_Monitor_Stop(), + HAL_ICACHE_Monitor_Reset(), HAL_ICACHE_Monitor_GetHitValue() and + HAL_ICACHE_Monitor_GetMissValue() + + (#) Enable and disable up to four regions to remap input address from external + memories to the internal Code region for execution with + HAL_ICACHE_EnableRemapRegion() and HAL_ICACHE_DisableRemapRegion() + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @defgroup ICACHE ICACHE + * @brief HAL ICACHE module driver + * @{ + */ +#if defined(ICACHE) && defined (HAL_ICACHE_MODULE_ENABLED) + +/* Private typedef -----------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup ICACHE_Private_Constants ICACHE Private Constants + * @{ + */ +#define ICACHE_INVALIDATE_TIMEOUT_VALUE 1U /* 1ms */ +#define ICACHE_DISABLE_TIMEOUT_VALUE 1U /* 1ms */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup ICACHE_Private_Macros ICACHE Private Macros + * @{ + */ + +#define IS_ICACHE_ASSOCIATIVITY_MODE(__MODE__) (((__MODE__) == ICACHE_1WAY) || \ + ((__MODE__) == ICACHE_2WAYS)) + +#define IS_ICACHE_MONITOR_TYPE(__TYPE__) (((__TYPE__) == ICACHE_MONITOR_HIT_MISS) || \ + ((__TYPE__) == ICACHE_MONITOR_HIT) || \ + ((__TYPE__) == ICACHE_MONITOR_MISS)) + +#define IS_ICACHE_REGION_NUMBER(__NUMBER__) ((__NUMBER__) < 4U) + +#define IS_ICACHE_REGION_SIZE(__SIZE__) (((__SIZE__) == ICACHE_REGIONSIZE_2MB) || \ + ((__SIZE__) == ICACHE_REGIONSIZE_4MB) || \ + ((__SIZE__) == ICACHE_REGIONSIZE_8MB) || \ + ((__SIZE__) == ICACHE_REGIONSIZE_16MB) || \ + ((__SIZE__) == ICACHE_REGIONSIZE_32MB) || \ + ((__SIZE__) == ICACHE_REGIONSIZE_64MB) || \ + ((__SIZE__) == ICACHE_REGIONSIZE_128MB)) + +#define IS_ICACHE_REGION_TRAFFIC_ROUTE(__TRAFFICROUTE__) (((__TRAFFICROUTE__) == ICACHE_MASTER1_PORT) || \ + ((__TRAFFICROUTE__) == ICACHE_MASTER2_PORT)) + +#define IS_ICACHE_REGION_OUTPUT_BURST_TYPE(__OUTPUTBURSTTYPE_) (((__OUTPUTBURSTTYPE_) == ICACHE_OUTPUT_BURST_WRAP) || \ + ((__OUTPUTBURSTTYPE_) == ICACHE_OUTPUT_BURST_INCR)) + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup ICACHE_Exported_Functions ICACHE Exported Functions + * @{ + */ + +/** @defgroup ICACHE_Exported_Functions_Group1 Initialization and control functions + * @brief Initialization and control functions + * + @verbatim + ============================================================================== + ##### Initialization and control functions ##### + ============================================================================== + [..] + This section provides functions allowing to initialize and control the + Instruction Cache (mode, invalidate procedure, performance counters). + @endverbatim + * @{ + */ + +/** + * @brief Configure the Instruction Cache cache associativity mode selection. + * @param AssociativityMode Associativity mode selection + * This parameter can be one of the following values: + * @arg ICACHE_1WAY 1-way cache (direct mapped cache) + * @arg ICACHE_2WAYS 2-ways set associative cache (default) + * @retval HAL status (HAL_OK/HAL_ERROR) + */ +HAL_StatusTypeDef HAL_ICACHE_ConfigAssociativityMode(uint32_t AssociativityMode) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_ICACHE_ASSOCIATIVITY_MODE(AssociativityMode)); + + /* Check cache is not enabled */ + if (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U) + { + status = HAL_ERROR; + } + else + { + MODIFY_REG(ICACHE->CR, ICACHE_CR_WAYSEL, AssociativityMode); + } + + return status; +} + +/** + * @brief DeInitialize the Instruction Cache. + * @retval HAL status (HAL_OK) + */ +HAL_StatusTypeDef HAL_ICACHE_DeInit(void) +{ + /* Reset interrupt enable value */ + WRITE_REG(ICACHE->IER, 0U); + + /* Clear any pending flags */ + WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF | ICACHE_FCR_CERRF); + + /* Disable cache then set default associative mode value */ + CLEAR_BIT(ICACHE->CR, ICACHE_CR_EN); + WRITE_REG(ICACHE->CR, ICACHE_CR_WAYSEL); + + /* Stop monitor and reset monitor values */ + CLEAR_BIT(ICACHE->CR, ICACHE_MONITOR_HIT_MISS); + SET_BIT(ICACHE->CR, (ICACHE_MONITOR_HIT_MISS << 2U)); + CLEAR_BIT(ICACHE->CR, (ICACHE_MONITOR_HIT_MISS << 2U)); + + /* Reset regions configuration values */ + WRITE_REG(ICACHE->CRR0, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos); + WRITE_REG(ICACHE->CRR1, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos); + WRITE_REG(ICACHE->CRR2, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos); + WRITE_REG(ICACHE->CRR3, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos); + + return HAL_OK; +} + +/** + * @brief Enable the Instruction Cache. + * @note This function always returns HAL_OK even if there is any ongoing + * cache operation. The Instruction Cache is bypassed until the + * cache operation completes. + * @retval HAL status (HAL_OK) + */ +HAL_StatusTypeDef HAL_ICACHE_Enable(void) +{ + SET_BIT(ICACHE->CR, ICACHE_CR_EN); + + return HAL_OK; +} + +/** + * @brief Disable the Instruction Cache. + * @note This function waits for the cache being disabled but + * not for the end of the automatic cache invalidation procedure. + * @retval HAL status (HAL_OK/HAL_TIMEOUT) + */ +HAL_StatusTypeDef HAL_ICACHE_Disable(void) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tickstart; + + /* Make sure BSYENDF is reset before to disable the instruction cache */ + /* as it automatically starts a cache invalidation procedure */ + WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); + + CLEAR_BIT(ICACHE->CR, ICACHE_CR_EN); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for instruction cache being disabled */ + while (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U) + { + if ((HAL_GetTick() - tickstart) > ICACHE_DISABLE_TIMEOUT_VALUE) + { + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U) + { + status = HAL_TIMEOUT; + break; + } + } + } + + return status; +} + +/** + * @brief Check whether the Instruction Cache is enabled or not. + * @retval Status (0: disabled, 1: enabled) + */ +uint32_t HAL_ICACHE_IsEnabled(void) +{ + return ((READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U) ? 1UL : 0UL); +} + +/** + * @brief Invalidate the Instruction Cache. + * @note This function waits for the end of cache invalidation procedure + * and clears the associated BSYENDF flag. + * @retval HAL status (HAL_OK/HAL_ERROR/HAL_TIMEOUT) + */ +HAL_StatusTypeDef HAL_ICACHE_Invalidate(void) +{ + HAL_StatusTypeDef status; + + /* Check if no ongoing operation */ + if (READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) == 0U) + { + /* Launch cache invalidation */ + SET_BIT(ICACHE->CR, ICACHE_CR_CACHEINV); + } + + status = HAL_ICACHE_WaitForInvalidateComplete(); + + return status; +} + +/** + * @brief Invalidate the Instruction Cache with interrupt. + * @note This function launches cache invalidation and returns. + * User application shall resort to interrupt generation to check + * the end of the cache invalidation with the BSYENDF flag and the + * HAL_ICACHE_InvalidateCompleteCallback() callback. + * @retval HAL status (HAL_OK/HAL_ERROR) + */ +HAL_StatusTypeDef HAL_ICACHE_Invalidate_IT(void) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check no ongoing operation */ + if (READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) != 0U) + { + status = HAL_ERROR; + } + else + { + /* Make sure BSYENDF is reset before to start cache invalidation */ + WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); + + /* Enable end of cache invalidation interrupt */ + SET_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE); + + /* Launch cache invalidation */ + SET_BIT(ICACHE->CR, ICACHE_CR_CACHEINV); + } + + return status; +} + +/** + * @brief Wait for the end of the Instruction Cache invalidate procedure. + * @note This function checks and clears the BSYENDF flag when set. + * @retval HAL status (HAL_OK/HAL_TIMEOUT) + */ +HAL_StatusTypeDef HAL_ICACHE_WaitForInvalidateComplete(void) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tickstart; + + /* Check if ongoing invalidation operation */ + if (READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) != 0U) + { + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for end of cache invalidation */ + while (READ_BIT(ICACHE->SR, ICACHE_SR_BSYENDF) == 0U) + { + if ((HAL_GetTick() - tickstart) > ICACHE_INVALIDATE_TIMEOUT_VALUE) + { + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(ICACHE->SR, ICACHE_SR_BSYENDF) == 0U) + { + status = HAL_TIMEOUT; + break; + } + } + } + } + + /* Clear BSYENDF */ + WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); + + return status; +} + + +/** + * @brief Start the Instruction Cache performance monitoring. + * @param MonitorType Monitoring type + * This parameter can be one of the following values: + * @arg ICACHE_MONITOR_HIT_MISS Hit & Miss monitoring + * @arg ICACHE_MONITOR_HIT Hit monitoring + * @arg ICACHE_MONITOR_MISS Miss monitoring + * @retval HAL status (HAL_OK) + */ +HAL_StatusTypeDef HAL_ICACHE_Monitor_Start(uint32_t MonitorType) +{ + /* Check the parameters */ + assert_param(IS_ICACHE_MONITOR_TYPE(MonitorType)); + + SET_BIT(ICACHE->CR, MonitorType); + + return HAL_OK; +} + +/** + * @brief Stop the Instruction Cache performance monitoring. + * @note Stopping the monitoring does not reset the values. + * @param MonitorType Monitoring type + * This parameter can be one of the following values: + * @arg ICACHE_MONITOR_HIT_MISS Hit & Miss monitoring + * @arg ICACHE_MONITOR_HIT Hit monitoring + * @arg ICACHE_MONITOR_MISS Miss monitoring + * @retval HAL status (HAL_OK) + */ +HAL_StatusTypeDef HAL_ICACHE_Monitor_Stop(uint32_t MonitorType) +{ + /* Check the parameters */ + assert_param(IS_ICACHE_MONITOR_TYPE(MonitorType)); + + CLEAR_BIT(ICACHE->CR, MonitorType); + + return HAL_OK; +} + +/** + * @brief Reset the Instruction Cache performance monitoring values. + * @param MonitorType Monitoring type + * This parameter can be one of the following values: + * @arg ICACHE_MONITOR_HIT_MISS Hit & Miss monitoring + * @arg ICACHE_MONITOR_HIT Hit monitoring + * @arg ICACHE_MONITOR_MISS Miss monitoring + * @retval HAL status (HAL_OK) + */ +HAL_StatusTypeDef HAL_ICACHE_Monitor_Reset(uint32_t MonitorType) +{ + /* Check the parameters */ + assert_param(IS_ICACHE_MONITOR_TYPE(MonitorType)); + + /* Force/Release reset */ + SET_BIT(ICACHE->CR, (MonitorType << 2U)); + CLEAR_BIT(ICACHE->CR, (MonitorType << 2U)); + + return HAL_OK; +} + +/** + * @brief Get the Instruction Cache performance Hit monitoring value. + * @note Upon reaching the 32-bit maximum value, monitor does not wrap. + * @retval Hit monitoring value + */ +uint32_t HAL_ICACHE_Monitor_GetHitValue(void) +{ + return (ICACHE->HMONR); +} + +/** + * @brief Get the Instruction Cache performance Miss monitoring value. + * @note Upon reaching the 32-bit maximum value, monitor does not wrap. + * @retval Miss monitoring value + */ +uint32_t HAL_ICACHE_Monitor_GetMissValue(void) +{ + return (ICACHE->MMONR); +} + +/** + * @} + */ + +/** @defgroup ICACHE_Exported_Functions_Group2 IRQ and callback functions + * @brief IRQ and callback functions + * + @verbatim + ============================================================================== + ##### IRQ and callback functions ##### + ============================================================================== + [..] + This section provides functions allowing to handle ICACHE global interrupt + and the associated callback functions. + @endverbatim + * @{ + */ + +/** + * @brief Handle the Instruction Cache interrupt request. + * @note This function should be called under the ICACHE_IRQHandler(). + * @note This function respectively disables the interrupt and clears the + * flag of any pending flag before calling the associated user callback. + * @retval None + */ +void HAL_ICACHE_IRQHandler(void) +{ + /* Get current interrupt flags and interrupt sources value */ + uint32_t itflags = READ_REG(ICACHE->SR); + uint32_t itsources = READ_REG(ICACHE->IER); + + /* Check Instruction cache Error interrupt flag */ + if (((itflags & itsources) & ICACHE_FLAG_ERROR) != 0U) + { + /* Disable error interrupt */ + CLEAR_BIT(ICACHE->IER, ICACHE_IER_ERRIE); + + /* Clear ERR pending flag */ + WRITE_REG(ICACHE->FCR, ICACHE_FCR_CERRF); + + /* Instruction cache error interrupt user callback */ + HAL_ICACHE_ErrorCallback(); + } + + /* Check Instruction cache BusyEnd interrupt flag */ + if (((itflags & itsources) & ICACHE_FLAG_BUSYEND) != 0U) + { + /* Disable end of cache invalidation interrupt */ + CLEAR_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE); + + /* Clear BSYENDF pending flag */ + WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); + + /* Instruction cache busyend interrupt user callback */ + HAL_ICACHE_InvalidateCompleteCallback(); + } +} + +/** + * @brief Cache invalidation complete callback. + */ +__weak void HAL_ICACHE_InvalidateCompleteCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_ICACHE_InvalidateCompleteCallback() should be implemented in the user file + */ +} + +/** + * @brief Error callback. + */ +__weak void HAL_ICACHE_ErrorCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_ICACHE_ErrorCallback() should be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup ICACHE_Exported_Functions_Group3 Memory remapped regions functions + * @brief Memory remapped regions functions + * + @verbatim + ============================================================================== + ##### Memory remapped regions functions ##### + ============================================================================== + [..] + This section provides functions allowing to manage the remapping of + external memories to internal Code for execution. + @endverbatim + * @{ + */ + +/** + * @brief Configure and enable a region for memory remapping. + * @note The Instruction Cache and the region must be disabled. + * @param Region Region number + This parameter can be a value of @arg @ref ICACHE_Region + * @param pRegionConfig Pointer to structure of ICACHE region configuration parameters + * @retval HAL status (HAL_OK/HAL_ERROR) + */ +HAL_StatusTypeDef HAL_ICACHE_EnableRemapRegion(uint32_t Region, const ICACHE_RegionConfigTypeDef *const pRegionConfig) +{ + HAL_StatusTypeDef status = HAL_OK; + __IO uint32_t *p_reg; + uint32_t value; + + /* Check the parameters */ + assert_param(IS_ICACHE_REGION_NUMBER(Region)); + assert_param(IS_ICACHE_REGION_SIZE(pRegionConfig->Size)); + assert_param(IS_ICACHE_REGION_TRAFFIC_ROUTE(pRegionConfig->TrafficRoute)); + assert_param(IS_ICACHE_REGION_OUTPUT_BURST_TYPE(pRegionConfig->OutputBurstType)); + + /* Check cache is not enabled */ + if (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U) + { + status = HAL_ERROR; + } + else + { + /* Get region control register address */ + p_reg = &(ICACHE->CRR0) + (1U * Region); + + /* Check region is not already enabled */ + if ((*p_reg & ICACHE_CRRx_REN) != 0U) + { + status = HAL_ERROR; + } + else + { + /* Region 2MB: BaseAddress size 8 bits, RemapAddress size 11 bits */ + /* Region 4MB: BaseAddress size 7 bits, RemapAddress size 10 bits */ + /* Region 8MB: BaseAddress size 6 bits, RemapAddress size 9 bits */ + /* Region 16MB: BaseAddress size 5 bits, RemapAddress size 8 bits */ + /* Region 32MB: BaseAddress size 4 bits, RemapAddress size 7 bits */ + /* Region 64MB: BaseAddress size 3 bits, RemapAddress size 6 bits */ + /* Region 128MB: BaseAddress size 2 bits, RemapAddress size 5 bits */ + value = ((pRegionConfig->BaseAddress & 0x1FFFFFFFU) >> 21U) & \ + (0xFFU & ~(pRegionConfig->Size - 1U)); + value |= ((pRegionConfig->RemapAddress >> 5U) & \ + ((uint32_t)(0x7FFU & ~(pRegionConfig->Size - 1U)) << ICACHE_CRRx_REMAPADDR_Pos)); + value |= (pRegionConfig->Size << ICACHE_CRRx_RSIZE_Pos) | pRegionConfig->TrafficRoute | \ + pRegionConfig->OutputBurstType; + *p_reg = (value | ICACHE_CRRx_REN); + } + } + + return status; +} + +/** + * @brief Disable the memory remapping for a predefined region. + * @param Region Region number + This parameter can be a value of @arg @ref ICACHE_Region + * @retval HAL status (HAL_OK/HAL_ERROR) + */ +HAL_StatusTypeDef HAL_ICACHE_DisableRemapRegion(uint32_t Region) +{ + HAL_StatusTypeDef status = HAL_OK; + __IO uint32_t *p_reg; + + /* Check the parameters */ + assert_param(IS_ICACHE_REGION_NUMBER(Region)); + + /* Check cache is not enabled */ + if (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U) + { + status = HAL_ERROR; + } + else + { + /* Get region control register address */ + p_reg = &(ICACHE->CRR0) + (1U * Region); + + *p_reg &= ~ICACHE_CRRx_REN; + } + + return status; +} + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* ICACHE && HAL_ICACHE_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_irda.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_irda.c new file mode 100644 index 0000000000..1b1cd42b8b --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_irda.c @@ -0,0 +1,3006 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_irda.c + * @author MCD Application Team + * @brief IRDA HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the IrDA (Infrared Data Association) Peripheral + * (IRDA) + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State and Errors functions + * + Peripheral Control functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The IRDA HAL driver can be used as follows: + + (#) Declare a IRDA_HandleTypeDef handle structure (eg. IRDA_HandleTypeDef hirda). + (#) Initialize the IRDA low level resources by implementing the HAL_IRDA_MspInit() API + in setting the associated USART or UART in IRDA mode: + (++) Enable the USARTx/UARTx interface clock. + (++) USARTx/UARTx pins configuration: + (+++) Enable the clock for the USARTx/UARTx GPIOs. + (+++) Configure these USARTx/UARTx pins (TX as alternate function pull-up, RX as alternate function Input). + (++) NVIC configuration if you need to use interrupt process (HAL_IRDA_Transmit_IT() + and HAL_IRDA_Receive_IT() APIs): + (+++) Configure the USARTx/UARTx interrupt priority. + (+++) Enable the NVIC USARTx/UARTx IRQ handle. + (+++) The specific IRDA interrupts (Transmission complete interrupt, + RXNE interrupt and Error Interrupts) will be managed using the macros + __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process. + + (++) DMA Configuration if you need to use DMA process (HAL_IRDA_Transmit_DMA() + and HAL_IRDA_Receive_DMA() APIs): + (+++) Declare a DMA handle structure for the Tx/Rx channel. + (+++) Enable the DMAx interface clock. + (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. + (+++) Configure the DMA Tx/Rx channel. + (+++) Associate the initialized DMA handle to the IRDA DMA Tx/Rx handle. + (+++) Configure the priority and enable the NVIC for the transfer + complete interrupt on the DMA Tx/Rx channel. + + (#) Program the Baud Rate, Word Length and Parity and Mode(Receiver/Transmitter), + the normal or low power mode and the clock prescaler in the hirda handle Init structure. + + (#) Initialize the IRDA registers by calling the HAL_IRDA_Init() API: + (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) + by calling the customized HAL_IRDA_MspInit() API. + + -@@- The specific IRDA interrupts (Transmission complete interrupt, + RXNE interrupt and Error Interrupts) will be managed using the macros + __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process. + + (#) Three operation modes are available within this driver : + + *** Polling mode IO operation *** + ================================= + [..] + (+) Send an amount of data in blocking mode using HAL_IRDA_Transmit() + (+) Receive an amount of data in blocking mode using HAL_IRDA_Receive() + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Send an amount of data in non-blocking mode using HAL_IRDA_Transmit_IT() + (+) At transmission end of transfer HAL_IRDA_TxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_IRDA_TxCpltCallback() + (+) Receive an amount of data in non-blocking mode using HAL_IRDA_Receive_IT() + (+) At reception end of transfer HAL_IRDA_RxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_IRDA_RxCpltCallback() + (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_IRDA_ErrorCallback() + + *** DMA mode IO operation *** + ============================== + [..] + (+) Send an amount of data in non-blocking mode (DMA) using HAL_IRDA_Transmit_DMA() + (+) At transmission half of transfer HAL_IRDA_TxHalfCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_IRDA_TxHalfCpltCallback() + (+) At transmission end of transfer HAL_IRDA_TxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_IRDA_TxCpltCallback() + (+) Receive an amount of data in non-blocking mode (DMA) using HAL_IRDA_Receive_DMA() + (+) At reception half of transfer HAL_IRDA_RxHalfCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_IRDA_RxHalfCpltCallback() + (+) At reception end of transfer HAL_IRDA_RxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_IRDA_RxCpltCallback() + (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_IRDA_ErrorCallback() + + *** IRDA HAL driver macros list *** + ==================================== + [..] + Below the list of most used macros in IRDA HAL driver. + + (+) __HAL_IRDA_ENABLE: Enable the IRDA peripheral + (+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral + (+) __HAL_IRDA_GET_FLAG : Check whether the specified IRDA flag is set or not + (+) __HAL_IRDA_CLEAR_FLAG : Clear the specified IRDA pending flag + (+) __HAL_IRDA_ENABLE_IT: Enable the specified IRDA interrupt + (+) __HAL_IRDA_DISABLE_IT: Disable the specified IRDA interrupt + (+) __HAL_IRDA_GET_IT_SOURCE: Check whether or not the specified IRDA interrupt is enabled + + [..] + (@) You can refer to the IRDA HAL driver header file for more useful macros + + ##### Callback registration ##### + ================================== + + [..] + The compilation define USE_HAL_IRDA_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + [..] + Use Function HAL_IRDA_RegisterCallback() to register a user callback. + Function HAL_IRDA_RegisterCallback() allows to register following callbacks: + (+) TxHalfCpltCallback : Tx Half Complete Callback. + (+) TxCpltCallback : Tx Complete Callback. + (+) RxHalfCpltCallback : Rx Half Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) AbortCpltCallback : Abort Complete Callback. + (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. + (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. + (+) MspInitCallback : IRDA MspInit. + (+) MspDeInitCallback : IRDA MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + [..] + Use function HAL_IRDA_UnRegisterCallback() to reset a callback to the default + weak function. + HAL_IRDA_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) TxHalfCpltCallback : Tx Half Complete Callback. + (+) TxCpltCallback : Tx Complete Callback. + (+) RxHalfCpltCallback : Rx Half Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) AbortCpltCallback : Abort Complete Callback. + (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. + (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. + (+) MspInitCallback : IRDA MspInit. + (+) MspDeInitCallback : IRDA MspDeInit. + + [..] + By default, after the HAL_IRDA_Init() and when the state is HAL_IRDA_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxHalfCpltCallback(). + Exception done for MspInit and MspDeInit functions that are respectively + reset to the legacy weak functions in the HAL_IRDA_Init() + and HAL_IRDA_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_IRDA_Init() and HAL_IRDA_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand). + + [..] + Callbacks can be registered/unregistered in HAL_IRDA_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_IRDA_STATE_READY or HAL_IRDA_STATE_RESET state, thus registered (user) + MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_IRDA_RegisterCallback() before calling HAL_IRDA_DeInit() + or HAL_IRDA_Init() function. + + [..] + When The compilation define USE_HAL_IRDA_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available + and weak callbacks are used. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @defgroup IRDA IRDA + * @brief HAL IRDA module driver + * @{ + */ + +#ifdef HAL_IRDA_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup IRDA_Private_Constants IRDA Private Constants + * @{ + */ +#define IRDA_TEACK_REACK_TIMEOUT 1000U /*!< IRDA TX or RX enable acknowledge time-out value */ + +#define IRDA_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE \ + | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE)) /*!< UART or USART CR1 fields of parameters set by IRDA_SetConfig API */ + +#define USART_BRR_MIN 0x10U /*!< USART BRR minimum authorized value */ + +#define USART_BRR_MAX 0x0000FFFFU /*!< USART BRR maximum authorized value */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup IRDA_Private_Macros IRDA Private Macros + * @{ + */ +/** @brief BRR division operation to set BRR register in 16-bit oversampling mode. + * @param __PCLK__ IRDA clock source. + * @param __BAUD__ Baud rate set by the user. + * @param __PRESCALER__ IRDA clock prescaler value. + * @retval Division result + */ +#define IRDA_DIV_SAMPLING16(__PCLK__, __BAUD__, __PRESCALER__) ((((__PCLK__)/IRDAPrescTable[(__PRESCALER__)])\ + + ((__BAUD__)/2U)) / (__BAUD__)) +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup IRDA_Private_Functions + * @{ + */ +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) +void IRDA_InitCallbacksToDefault(IRDA_HandleTypeDef *hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ +static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda); +static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda); +static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout); +#if defined(HAL_DMA_MODULE_ENABLED) +static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda); +#endif /* HAL_DMA_MODULE_ENABLED */ +static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda); +#if defined(HAL_DMA_MODULE_ENABLED) +static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma); +static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma); +static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma); +static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma); +static void IRDA_DMAError(DMA_HandleTypeDef *hdma); +static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma); +static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma); +static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma); +static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma); +static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma); +#endif /* HAL_DMA_MODULE_ENABLED */ +static void IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda); +static void IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda); +static void IRDA_Receive_IT(IRDA_HandleTypeDef *hirda); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup IRDA_Exported_Functions IRDA Exported Functions + * @{ + */ + +/** @defgroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and Configuration functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to initialize the USARTx + in asynchronous IRDA mode. + (+) For the asynchronous mode only these parameters can be configured: + (++) Baud Rate + (++) Word Length + (++) Parity: If the parity is enabled, then the MSB bit of the data written + in the data register is transmitted but is changed by the parity bit. + (++) Power mode + (++) Prescaler setting + (++) Receiver/transmitter modes + + [..] + The HAL_IRDA_Init() API follows the USART asynchronous configuration procedures + (details for the procedures are available in reference manual). + +@endverbatim + + Depending on the frame length defined by the M1 and M0 bits (7-bit, + 8-bit or 9-bit), the possible IRDA frame formats are listed in the + following table. + + Table 1. IRDA frame format. + +-----------------------------------------------------------------------+ + | M1 bit | M0 bit | PCE bit | IRDA frame | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 0 | | SB | 8 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 0 | | SB | 9 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 0 | | SB | 7 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | + +-----------------------------------------------------------------------+ + + * @{ + */ + +/** + * @brief Initialize the IRDA mode according to the specified + * parameters in the IRDA_InitTypeDef and initialize the associated handle. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda) +{ + /* Check the IRDA handle allocation */ + if (hirda == NULL) + { + return HAL_ERROR; + } + + /* Check the USART/UART associated to the IRDA handle */ + assert_param(IS_IRDA_INSTANCE(hirda->Instance)); + + if (hirda->gState == HAL_IRDA_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hirda->Lock = HAL_UNLOCKED; + +#if USE_HAL_IRDA_REGISTER_CALLBACKS == 1 + IRDA_InitCallbacksToDefault(hirda); + + if (hirda->MspInitCallback == NULL) + { + hirda->MspInitCallback = HAL_IRDA_MspInit; + } + + /* Init the low level hardware */ + hirda->MspInitCallback(hirda); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_IRDA_MspInit(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ + } + + hirda->gState = HAL_IRDA_STATE_BUSY; + + /* Disable the Peripheral to update the configuration registers */ + __HAL_IRDA_DISABLE(hirda); + + /* Set the IRDA Communication parameters */ + if (IRDA_SetConfig(hirda) == HAL_ERROR) + { + return HAL_ERROR; + } + + /* In IRDA mode, the following bits must be kept cleared: + - LINEN, STOP and CLKEN bits in the USART_CR2 register, + - SCEN and HDSEL bits in the USART_CR3 register.*/ + CLEAR_BIT(hirda->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP)); + CLEAR_BIT(hirda->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL)); + + /* set the UART/USART in IRDA mode */ + hirda->Instance->CR3 |= USART_CR3_IREN; + + /* Enable the Peripheral */ + __HAL_IRDA_ENABLE(hirda); + + /* TEACK and/or REACK to check before moving hirda->gState and hirda->RxState to Ready */ + return (IRDA_CheckIdleState(hirda)); +} + +/** + * @brief DeInitialize the IRDA peripheral. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda) +{ + /* Check the IRDA handle allocation */ + if (hirda == NULL) + { + return HAL_ERROR; + } + + /* Check the USART/UART associated to the IRDA handle */ + assert_param(IS_IRDA_INSTANCE(hirda->Instance)); + + hirda->gState = HAL_IRDA_STATE_BUSY; + + /* DeInit the low level hardware */ +#if USE_HAL_IRDA_REGISTER_CALLBACKS == 1 + if (hirda->MspDeInitCallback == NULL) + { + hirda->MspDeInitCallback = HAL_IRDA_MspDeInit; + } + /* DeInit the low level hardware */ + hirda->MspDeInitCallback(hirda); +#else + HAL_IRDA_MspDeInit(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ + /* Disable the Peripheral */ + __HAL_IRDA_DISABLE(hirda); + + hirda->ErrorCode = HAL_IRDA_ERROR_NONE; + hirda->gState = HAL_IRDA_STATE_RESET; + hirda->RxState = HAL_IRDA_STATE_RESET; + + /* Process Unlock */ + __HAL_UNLOCK(hirda); + + return HAL_OK; +} + +/** + * @brief Initialize the IRDA MSP. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval None + */ +__weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hirda); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_IRDA_MspInit can be implemented in the user file + */ +} + +/** + * @brief DeInitialize the IRDA MSP. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval None + */ +__weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hirda); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_IRDA_MspDeInit can be implemented in the user file + */ +} + +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User IRDA Callback + * To be used to override the weak predefined callback + * @note The HAL_IRDA_RegisterCallback() may be called before HAL_IRDA_Init() in HAL_IRDA_STATE_RESET + * to register callbacks for HAL_IRDA_MSPINIT_CB_ID and HAL_IRDA_MSPDEINIT_CB_ID + * @param hirda irda handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_IRDA_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID + * @arg @ref HAL_IRDA_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_IRDA_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID + * @arg @ref HAL_IRDA_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_IRDA_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_IRDA_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + * @arg @ref HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID + * @arg @ref HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID + * @arg @ref HAL_IRDA_MSPINIT_CB_ID MspInit Callback ID + * @arg @ref HAL_IRDA_MSPDEINIT_CB_ID MspDeInit Callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID, + pIRDA_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (hirda->gState == HAL_IRDA_STATE_READY) + { + switch (CallbackID) + { + case HAL_IRDA_TX_HALFCOMPLETE_CB_ID : + hirda->TxHalfCpltCallback = pCallback; + break; + + case HAL_IRDA_TX_COMPLETE_CB_ID : + hirda->TxCpltCallback = pCallback; + break; + + case HAL_IRDA_RX_HALFCOMPLETE_CB_ID : + hirda->RxHalfCpltCallback = pCallback; + break; + + case HAL_IRDA_RX_COMPLETE_CB_ID : + hirda->RxCpltCallback = pCallback; + break; + + case HAL_IRDA_ERROR_CB_ID : + hirda->ErrorCallback = pCallback; + break; + + case HAL_IRDA_ABORT_COMPLETE_CB_ID : + hirda->AbortCpltCallback = pCallback; + break; + + case HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID : + hirda->AbortTransmitCpltCallback = pCallback; + break; + + case HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID : + hirda->AbortReceiveCpltCallback = pCallback; + break; + + case HAL_IRDA_MSPINIT_CB_ID : + hirda->MspInitCallback = pCallback; + break; + + case HAL_IRDA_MSPDEINIT_CB_ID : + hirda->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hirda->gState == HAL_IRDA_STATE_RESET) + { + switch (CallbackID) + { + case HAL_IRDA_MSPINIT_CB_ID : + hirda->MspInitCallback = pCallback; + break; + + case HAL_IRDA_MSPDEINIT_CB_ID : + hirda->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister an IRDA callback + * IRDA callback is redirected to the weak predefined callback + * @note The HAL_IRDA_UnRegisterCallback() may be called before HAL_IRDA_Init() in HAL_IRDA_STATE_RESET + * to un-register callbacks for HAL_IRDA_MSPINIT_CB_ID and HAL_IRDA_MSPDEINIT_CB_ID + * @param hirda irda handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_IRDA_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID + * @arg @ref HAL_IRDA_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_IRDA_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID + * @arg @ref HAL_IRDA_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_IRDA_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_IRDA_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + * @arg @ref HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID + * @arg @ref HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID + * @arg @ref HAL_IRDA_MSPINIT_CB_ID MspInit Callback ID + * @arg @ref HAL_IRDA_MSPDEINIT_CB_ID MspDeInit Callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (HAL_IRDA_STATE_READY == hirda->gState) + { + switch (CallbackID) + { + case HAL_IRDA_TX_HALFCOMPLETE_CB_ID : + hirda->TxHalfCpltCallback = HAL_IRDA_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + break; + + case HAL_IRDA_TX_COMPLETE_CB_ID : + hirda->TxCpltCallback = HAL_IRDA_TxCpltCallback; /* Legacy weak TxCpltCallback */ + break; + + case HAL_IRDA_RX_HALFCOMPLETE_CB_ID : + hirda->RxHalfCpltCallback = HAL_IRDA_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + break; + + case HAL_IRDA_RX_COMPLETE_CB_ID : + hirda->RxCpltCallback = HAL_IRDA_RxCpltCallback; /* Legacy weak RxCpltCallback */ + break; + + case HAL_IRDA_ERROR_CB_ID : + hirda->ErrorCallback = HAL_IRDA_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_IRDA_ABORT_COMPLETE_CB_ID : + hirda->AbortCpltCallback = HAL_IRDA_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + break; + + case HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID : + hirda->AbortTransmitCpltCallback = HAL_IRDA_AbortTransmitCpltCallback; /* Legacy weak + AbortTransmitCpltCallback */ + break; + + case HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID : + hirda->AbortReceiveCpltCallback = HAL_IRDA_AbortReceiveCpltCallback; /* Legacy weak + AbortReceiveCpltCallback */ + break; + + case HAL_IRDA_MSPINIT_CB_ID : + hirda->MspInitCallback = HAL_IRDA_MspInit; /* Legacy weak MspInitCallback */ + break; + + case HAL_IRDA_MSPDEINIT_CB_ID : + hirda->MspDeInitCallback = HAL_IRDA_MspDeInit; /* Legacy weak MspDeInitCallback */ + break; + + default : + /* Update the error code */ + hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_IRDA_STATE_RESET == hirda->gState) + { + switch (CallbackID) + { + case HAL_IRDA_MSPINIT_CB_ID : + hirda->MspInitCallback = HAL_IRDA_MspInit; + break; + + case HAL_IRDA_MSPDEINIT_CB_ID : + hirda->MspDeInitCallback = HAL_IRDA_MspDeInit; + break; + + default : + /* Update the error code */ + hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} +#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup IRDA_Exported_Functions_Group2 IO operation functions + * @brief IRDA Transmit and Receive functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the IRDA data transfers. + + [..] + IrDA is a half duplex communication protocol. If the Transmitter is busy, any data + on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver + is busy, data on the TX from the USART to IrDA will not be encoded by IrDA. + While receiving data, transmission should be avoided as the data to be transmitted + could be corrupted. + + [..] + (#) There are two modes of transfer: + (++) Blocking mode: the communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (++) Non-Blocking mode: the communication is performed using Interrupts + or DMA, these API's return the HAL status. + The end of the data processing will be indicated through the + dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks + will be executed respectively at the end of the Transmit or Receive process + The HAL_IRDA_ErrorCallback() user callback will be executed when a communication error is detected + + (#) Blocking mode APIs are : + (++) HAL_IRDA_Transmit() + (++) HAL_IRDA_Receive() + + (#) Non Blocking mode APIs with Interrupt are : + (++) HAL_IRDA_Transmit_IT() + (++) HAL_IRDA_Receive_IT() + (++) HAL_IRDA_IRQHandler() + + (#) Non Blocking mode functions with DMA are : + (++) HAL_IRDA_Transmit_DMA() + (++) HAL_IRDA_Receive_DMA() + (++) HAL_IRDA_DMAPause() + (++) HAL_IRDA_DMAResume() + (++) HAL_IRDA_DMAStop() + + (#) A set of Transfer Complete Callbacks are provided in Non Blocking mode: + (++) HAL_IRDA_TxHalfCpltCallback() + (++) HAL_IRDA_TxCpltCallback() + (++) HAL_IRDA_RxHalfCpltCallback() + (++) HAL_IRDA_RxCpltCallback() + (++) HAL_IRDA_ErrorCallback() + + (#) Non-Blocking mode transfers could be aborted using Abort API's : + (++) HAL_IRDA_Abort() + (++) HAL_IRDA_AbortTransmit() + (++) HAL_IRDA_AbortReceive() + (++) HAL_IRDA_Abort_IT() + (++) HAL_IRDA_AbortTransmit_IT() + (++) HAL_IRDA_AbortReceive_IT() + + (#) For Abort services based on interrupts (HAL_IRDA_Abortxxx_IT), a set of Abort Complete Callbacks are provided: + (++) HAL_IRDA_AbortCpltCallback() + (++) HAL_IRDA_AbortTransmitCpltCallback() + (++) HAL_IRDA_AbortReceiveCpltCallback() + + (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. + Errors are handled as follows : + (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is + to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error + in Interrupt mode reception . + Received character is then retrieved and stored in Rx buffer, Error code is set to allow user + to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed. + Transfer is kept ongoing on IRDA side. + If user wants to abort it, Abort services should be called by user. + (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted. + This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. + Error code is set to allow user to identify error type, and + HAL_IRDA_ErrorCallback() user callback is executed. + +@endverbatim + * @{ + */ + +/** + * @brief Send an amount of data in blocking mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must reflect the number + * of u16 available through pData. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. + * @param Timeout Specify timeout value. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + const uint8_t *pdata8bits; + const uint16_t *pdata16bits; + uint32_t tickstart; + + /* Check that a Tx process is not already ongoing */ + if (hirda->gState == HAL_IRDA_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hirda); + + hirda->ErrorCode = HAL_IRDA_ERROR_NONE; + hirda->gState = HAL_IRDA_STATE_BUSY_TX; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + hirda->TxXferSize = Size; + hirda->TxXferCount = Size; + + /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */ + if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE)) + { + pdata8bits = NULL; + pdata16bits = (const uint16_t *) pData; /* Derogation R.11.3 */ + } + else + { + pdata8bits = pData; + pdata16bits = NULL; + } + + while (hirda->TxXferCount > 0U) + { + hirda->TxXferCount--; + + if (IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + if (pdata8bits == NULL) + { + hirda->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU); + pdata16bits++; + } + else + { + hirda->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU); + pdata8bits++; + } + } + + if (IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* At end of Tx process, restore hirda->gState to Ready */ + hirda->gState = HAL_IRDA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in blocking mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must reflect the number + * of u16 available through pData. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @param Timeout Specify timeout value. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint8_t *pdata8bits; + uint16_t *pdata16bits; + uint16_t uhMask; + uint32_t tickstart; + + /* Check that a Rx process is not already ongoing */ + if (hirda->RxState == HAL_IRDA_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hirda); + + hirda->ErrorCode = HAL_IRDA_ERROR_NONE; + hirda->RxState = HAL_IRDA_STATE_BUSY_RX; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + hirda->RxXferSize = Size; + hirda->RxXferCount = Size; + + /* Computation of the mask to apply to RDR register + of the UART associated to the IRDA */ + IRDA_MASK_COMPUTATION(hirda); + uhMask = hirda->Mask; + + /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ + if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE)) + { + pdata8bits = NULL; + pdata16bits = (uint16_t *) pData; /* Derogation R.11.3 */ + } + else + { + pdata8bits = pData; + pdata16bits = NULL; + } + + /* Check data remaining to be received */ + while (hirda->RxXferCount > 0U) + { + hirda->RxXferCount--; + + if (IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + if (pdata8bits == NULL) + { + *pdata16bits = (uint16_t)(hirda->Instance->RDR & uhMask); + pdata16bits++; + } + else + { + *pdata8bits = (uint8_t)(hirda->Instance->RDR & (uint8_t)uhMask); + pdata8bits++; + } + } + + /* At end of Rx process, restore hirda->RxState to Ready */ + hirda->RxState = HAL_IRDA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Send an amount of data in interrupt mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must reflect the number + * of u16 available through pData. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size) +{ + /* Check that a Tx process is not already ongoing */ + if (hirda->gState == HAL_IRDA_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hirda); + + hirda->pTxBuffPtr = pData; + hirda->TxXferSize = Size; + hirda->TxXferCount = Size; + + hirda->ErrorCode = HAL_IRDA_ERROR_NONE; + hirda->gState = HAL_IRDA_STATE_BUSY_TX; + + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + + /* Enable the IRDA Transmit Data Register Empty Interrupt */ + SET_BIT(hirda->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in interrupt mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must reflect the number + * of u16 available through pData. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) +{ + /* Check that a Rx process is not already ongoing */ + if (hirda->RxState == HAL_IRDA_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hirda); + + hirda->pRxBuffPtr = pData; + hirda->RxXferSize = Size; + hirda->RxXferCount = Size; + + /* Computation of the mask to apply to the RDR register + of the UART associated to the IRDA */ + IRDA_MASK_COMPUTATION(hirda); + + hirda->ErrorCode = HAL_IRDA_ERROR_NONE; + hirda->RxState = HAL_IRDA_STATE_BUSY_RX; + + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + + if (hirda->Init.Parity != IRDA_PARITY_NONE) + { + /* Enable the IRDA Parity Error and Data Register not empty Interrupts */ + SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); + } + else + { + /* Enable the IRDA Data Register not empty Interrupts */ + SET_BIT(hirda->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + } + + /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(hirda->Instance->CR3, USART_CR3_EIE); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Send an amount of data in DMA mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must reflect the number + * of u16 available through pData. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @param pData pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef status; + uint16_t nbByte = Size; + + /* Check that a Tx process is not already ongoing */ + if (hirda->gState == HAL_IRDA_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hirda); + + hirda->pTxBuffPtr = pData; + hirda->TxXferSize = Size; + hirda->TxXferCount = Size; + + hirda->ErrorCode = HAL_IRDA_ERROR_NONE; + hirda->gState = HAL_IRDA_STATE_BUSY_TX; + + /* Set the IRDA DMA transfer complete callback */ + hirda->hdmatx->XferCpltCallback = IRDA_DMATransmitCplt; + + /* Set the IRDA DMA half transfer complete callback */ + hirda->hdmatx->XferHalfCpltCallback = IRDA_DMATransmitHalfCplt; + + /* Set the DMA error callback */ + hirda->hdmatx->XferErrorCallback = IRDA_DMAError; + + /* Set the DMA abort callback */ + hirda->hdmatx->XferAbortCallback = NULL; + + /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter + should be aligned on a u16 frontier, so nbByte should be equal to Size multiplied by 2 */ + if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE)) + { + nbByte = Size * 2U; + } + + /* Check linked list mode */ + if ((hirda->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if ((hirda->hdmatx->LinkedListQueue != NULL) && (hirda->hdmatx->LinkedListQueue->Head != NULL)) + { + /* Set DMA data size */ + hirda->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = nbByte; + + /* Set DMA source address */ + hirda->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = + (uint32_t)hirda->pTxBuffPtr; + + /* Set DMA destination address */ + hirda->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = + (uint32_t)&hirda->Instance->TDR; + + /* Enable the IRDA transmit DMA channel */ + status = HAL_DMAEx_List_Start_IT(hirda->hdmatx); + } + else + { + /* Update status */ + status = HAL_ERROR; + } + } + else + { + /* Enable the IRDA transmit DMA channel */ + status = HAL_DMA_Start_IT(hirda->hdmatx, (uint32_t)hirda->pTxBuffPtr, (uint32_t)&hirda->Instance->TDR, nbByte); + } + + if (status == HAL_OK) + { + /* Clear the TC flag in the ICR register */ + __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_TCF); + + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + + /* Enable the DMA transfer for transmit request by setting the DMAT bit + in the USART CR3 register */ + SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT); + + return HAL_OK; + } + else + { + /* Set error code to DMA */ + hirda->ErrorCode = HAL_IRDA_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + + /* Restore hirda->gState to ready */ + hirda->gState = HAL_IRDA_STATE_READY; + + return HAL_ERROR; + } + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in DMA mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must reflect the number + * of u16 available through pData. + * @note When the IRDA parity is enabled (PCE = 1), the received data contains + * the parity bit (MSB position). + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef status; + uint16_t nbByte = Size; + + /* Check that a Rx process is not already ongoing */ + if (hirda->RxState == HAL_IRDA_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hirda); + + hirda->pRxBuffPtr = pData; + hirda->RxXferSize = Size; + + hirda->ErrorCode = HAL_IRDA_ERROR_NONE; + hirda->RxState = HAL_IRDA_STATE_BUSY_RX; + + /* Set the IRDA DMA transfer complete callback */ + hirda->hdmarx->XferCpltCallback = IRDA_DMAReceiveCplt; + + /* Set the IRDA DMA half transfer complete callback */ + hirda->hdmarx->XferHalfCpltCallback = IRDA_DMAReceiveHalfCplt; + + /* Set the DMA error callback */ + hirda->hdmarx->XferErrorCallback = IRDA_DMAError; + + /* Set the DMA abort callback */ + hirda->hdmarx->XferAbortCallback = NULL; + + /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter + should be aligned on a u16 frontier, so nbByte should be equal to Size multiplied by 2 */ + if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE)) + { + nbByte = Size * 2U; + } + + /* Check linked list mode */ + if ((hirda->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if ((hirda->hdmarx->LinkedListQueue != NULL) && (hirda->hdmarx->LinkedListQueue->Head != NULL)) + { + /* Set DMA data size */ + hirda->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = nbByte; + + /* Set DMA source address */ + hirda->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = + (uint32_t)&hirda->Instance->RDR; + + /* Set DMA destination address */ + hirda->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)hirda->pRxBuffPtr; + + /* Enable the DMA channel */ + status = HAL_DMAEx_List_Start_IT(hirda->hdmarx); + } + else + { + /* Update status */ + status = HAL_ERROR; + } + } + else + { + /* Enable the DMA channel */ + status = HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->RDR, (uint32_t)hirda->pRxBuffPtr, nbByte); + } + + if (status == HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + + if (hirda->Init.Parity != IRDA_PARITY_NONE) + { + /* Enable the UART Parity Error Interrupt */ + SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE); + } + + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(hirda->Instance->CR3, USART_CR3_EIE); + + /* Enable the DMA transfer for the receiver request by setting the DMAR bit + in the USART CR3 register */ + SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR); + + return HAL_OK; + } + else + { + /* Set error code to DMA */ + hirda->ErrorCode = HAL_IRDA_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + + /* Restore hirda->RxState to ready */ + hirda->RxState = HAL_IRDA_STATE_READY; + + return HAL_ERROR; + } + } + else + { + return HAL_BUSY; + } +} + + +/** + * @brief Pause the DMA Transfer. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda) +{ + /* Process Locked */ + __HAL_LOCK(hirda); + + if (hirda->gState == HAL_IRDA_STATE_BUSY_TX) + { + if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) + { + /* Disable the IRDA DMA Tx request */ + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); + } + } + if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX) + { + if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) + { + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE); + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); + + /* Disable the IRDA DMA Rx request */ + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + + return HAL_OK; +} + +/** + * @brief Resume the DMA Transfer. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda) +{ + /* Process Locked */ + __HAL_LOCK(hirda); + + if (hirda->gState == HAL_IRDA_STATE_BUSY_TX) + { + /* Enable the IRDA DMA Tx request */ + SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT); + } + if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX) + { + /* Clear the Overrun flag before resuming the Rx transfer*/ + __HAL_IRDA_CLEAR_OREFLAG(hirda); + + /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */ + if (hirda->Init.Parity != IRDA_PARITY_NONE) + { + SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE); + } + SET_BIT(hirda->Instance->CR3, USART_CR3_EIE); + + /* Enable the IRDA DMA Rx request */ + SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + + return HAL_OK; +} + +/** + * @brief Stop the DMA Transfer. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda) +{ + /* The Lock is not implemented on this API to allow the user application + to call the HAL IRDA API under callbacks HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback() / + HAL_IRDA_TxHalfCpltCallback / HAL_IRDA_RxHalfCpltCallback: + indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete + interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of + the stream and the corresponding call back is executed. */ + + /* Stop IRDA DMA Tx request if ongoing */ + if (hirda->gState == HAL_IRDA_STATE_BUSY_TX) + { + if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); + + /* Abort the IRDA DMA Tx channel */ + if (hirda->hdmatx != NULL) + { + if (HAL_DMA_Abort(hirda->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(hirda->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + hirda->ErrorCode = HAL_IRDA_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + + IRDA_EndTxTransfer(hirda); + } + } + + /* Stop IRDA DMA Rx request if ongoing */ + if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX) + { + if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); + + /* Abort the IRDA DMA Rx channel */ + if (hirda->hdmarx != NULL) + { + if (HAL_DMA_Abort(hirda->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(hirda->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + hirda->ErrorCode = HAL_IRDA_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + + IRDA_EndRxTransfer(hirda); + } + } + + return HAL_OK; +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Abort ongoing transfers (blocking mode). + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable IRDA Interrupts (Tx and Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda) +{ + /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | \ + USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Disable the IRDA DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); + + /* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */ + if (hirda->hdmatx != NULL) + { + /* Set the IRDA DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + hirda->hdmatx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(hirda->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(hirda->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + hirda->ErrorCode = HAL_IRDA_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + + /* Disable the IRDA DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); + + /* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */ + if (hirda->hdmarx != NULL) + { + /* Set the IRDA DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + hirda->hdmarx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(hirda->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(hirda->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + hirda->ErrorCode = HAL_IRDA_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } +#endif /* HAL_DMA_MODULE_ENABLED */ + + /* Reset Tx and Rx transfer counters */ + hirda->TxXferCount = 0U; + hirda->RxXferCount = 0U; + + /* Clear the Error flags in the ICR register */ + __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF); + + /* Restore hirda->gState and hirda->RxState to Ready */ + hirda->gState = HAL_IRDA_STATE_READY; + hirda->RxState = HAL_IRDA_STATE_READY; + + /* Reset Handle ErrorCode to No Error */ + hirda->ErrorCode = HAL_IRDA_ERROR_NONE; + + return HAL_OK; +} + +/** + * @brief Abort ongoing Transmit transfer (blocking mode). + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable IRDA Interrupts (Tx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda) +{ + /* Disable TXEIE and TCIE interrupts */ + CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Disable the IRDA DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); + + /* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */ + if (hirda->hdmatx != NULL) + { + /* Set the IRDA DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + hirda->hdmatx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(hirda->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(hirda->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + hirda->ErrorCode = HAL_IRDA_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } +#endif /* HAL_DMA_MODULE_ENABLED */ + + /* Reset Tx transfer counter */ + hirda->TxXferCount = 0U; + + /* Restore hirda->gState to Ready */ + hirda->gState = HAL_IRDA_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Abort ongoing Receive transfer (blocking mode). + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable IRDA Interrupts (Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda) +{ + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Disable the IRDA DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); + + /* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */ + if (hirda->hdmarx != NULL) + { + /* Set the IRDA DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + hirda->hdmarx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(hirda->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(hirda->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + hirda->ErrorCode = HAL_IRDA_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } +#endif /* HAL_DMA_MODULE_ENABLED */ + + /* Reset Rx transfer counter */ + hirda->RxXferCount = 0U; + + /* Clear the Error flags in the ICR register */ + __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF); + + /* Restore hirda->RxState to Ready */ + hirda->RxState = HAL_IRDA_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Abort ongoing transfers (Interrupt mode). + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable IRDA Interrupts (Tx and Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda) +{ + uint32_t abortcplt = 1U; + + /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | \ + USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* If DMA Tx and/or DMA Rx Handles are associated to IRDA Handle, DMA Abort complete callbacks should be initialised + before any call to DMA Abort functions */ + /* DMA Tx Handle is valid */ + if (hirda->hdmatx != NULL) + { + /* Set DMA Abort Complete callback if IRDA DMA Tx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) + { + hirda->hdmatx->XferAbortCallback = IRDA_DMATxAbortCallback; + } + else + { + hirda->hdmatx->XferAbortCallback = NULL; + } + } + /* DMA Rx Handle is valid */ + if (hirda->hdmarx != NULL) + { + /* Set DMA Abort Complete callback if IRDA DMA Rx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) + { + hirda->hdmarx->XferAbortCallback = IRDA_DMARxAbortCallback; + } + else + { + hirda->hdmarx->XferAbortCallback = NULL; + } + } + + /* Disable the IRDA DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) + { + /* Disable DMA Tx at UART level */ + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); + + /* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */ + if (hirda->hdmatx != NULL) + { + /* IRDA Tx DMA Abort callback has already been initialised : + will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */ + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK) + { + hirda->hdmatx->XferAbortCallback = NULL; + } + else + { + abortcplt = 0U; + } + } + } + + /* Disable the IRDA DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); + + /* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */ + if (hirda->hdmarx != NULL) + { + /* IRDA Rx DMA Abort callback has already been initialised : + will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */ + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK) + { + hirda->hdmarx->XferAbortCallback = NULL; + abortcplt = 1U; + } + else + { + abortcplt = 0U; + } + } + } +#endif /* HAL_DMA_MODULE_ENABLED */ + + /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ + if (abortcplt == 1U) + { + /* Reset Tx and Rx transfer counters */ + hirda->TxXferCount = 0U; + hirda->RxXferCount = 0U; + + /* Reset errorCode */ + hirda->ErrorCode = HAL_IRDA_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF); + + /* Restore hirda->gState and hirda->RxState to Ready */ + hirda->gState = HAL_IRDA_STATE_READY; + hirda->RxState = HAL_IRDA_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + hirda->AbortCpltCallback(hirda); +#else + /* Call legacy weak Abort complete callback */ + HAL_IRDA_AbortCpltCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ + } + + return HAL_OK; +} + +/** + * @brief Abort ongoing Transmit transfer (Interrupt mode). + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable IRDA Interrupts (Tx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda) +{ + /* Disable TXEIE and TCIE interrupts */ + CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Disable the IRDA DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); + + /* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */ + if (hirda->hdmatx != NULL) + { + /* Set the IRDA DMA Abort callback : + will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */ + hirda->hdmatx->XferAbortCallback = IRDA_DMATxOnlyAbortCallback; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK) + { + /* Call Directly hirda->hdmatx->XferAbortCallback function in case of error */ + hirda->hdmatx->XferAbortCallback(hirda->hdmatx); + } + } + else + { + /* Reset Tx transfer counter */ + hirda->TxXferCount = 0U; + + /* Restore hirda->gState to Ready */ + hirda->gState = HAL_IRDA_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + hirda->AbortTransmitCpltCallback(hirda); +#else + /* Call legacy weak Abort Transmit Complete Callback */ + HAL_IRDA_AbortTransmitCpltCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ + } + } + else +#endif /* HAL_DMA_MODULE_ENABLED */ + { + /* Reset Tx transfer counter */ + hirda->TxXferCount = 0U; + + /* Restore hirda->gState to Ready */ + hirda->gState = HAL_IRDA_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + hirda->AbortTransmitCpltCallback(hirda); +#else + /* Call legacy weak Abort Transmit Complete Callback */ + HAL_IRDA_AbortTransmitCpltCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ + } + + return HAL_OK; +} + +/** + * @brief Abort ongoing Receive transfer (Interrupt mode). + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable IRDA Interrupts (Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda) +{ + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Disable the IRDA DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); + + /* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */ + if (hirda->hdmarx != NULL) + { + /* Set the IRDA DMA Abort callback : + will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */ + hirda->hdmarx->XferAbortCallback = IRDA_DMARxOnlyAbortCallback; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK) + { + /* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */ + hirda->hdmarx->XferAbortCallback(hirda->hdmarx); + } + } + else + { + /* Reset Rx transfer counter */ + hirda->RxXferCount = 0U; + + /* Clear the Error flags in the ICR register */ + __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF); + + /* Restore hirda->RxState to Ready */ + hirda->RxState = HAL_IRDA_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + hirda->AbortReceiveCpltCallback(hirda); +#else + /* Call legacy weak Abort Receive Complete Callback */ + HAL_IRDA_AbortReceiveCpltCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ + } + } + else +#endif /* HAL_DMA_MODULE_ENABLED */ + { + /* Reset Rx transfer counter */ + hirda->RxXferCount = 0U; + + /* Clear the Error flags in the ICR register */ + __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF); + + /* Restore hirda->RxState to Ready */ + hirda->RxState = HAL_IRDA_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + hirda->AbortReceiveCpltCallback(hirda); +#else + /* Call legacy weak Abort Receive Complete Callback */ + HAL_IRDA_AbortReceiveCpltCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ + } + + return HAL_OK; +} + +/** + * @brief Handle IRDA interrupt request. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval None + */ +void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) +{ + uint32_t isrflags = READ_REG(hirda->Instance->ISR); + uint32_t cr1its = READ_REG(hirda->Instance->CR1); + uint32_t cr3its; + uint32_t errorflags; + uint32_t errorcode; + + /* If no error occurs */ + errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE)); + if (errorflags == 0U) + { + /* IRDA in mode Receiver ---------------------------------------------------*/ + if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) && ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)) + { + IRDA_Receive_IT(hirda); + return; + } + } + + /* If some errors occur */ + cr3its = READ_REG(hirda->Instance->CR3); + if ((errorflags != 0U) + && (((cr3its & USART_CR3_EIE) != 0U) + || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != 0U))) + { + /* IRDA parity error interrupt occurred -------------------------------------*/ + if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) + { + __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_PEF); + + hirda->ErrorCode |= HAL_IRDA_ERROR_PE; + } + + /* IRDA frame error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_FEF); + + hirda->ErrorCode |= HAL_IRDA_ERROR_FE; + } + + /* IRDA noise error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_NEF); + + hirda->ErrorCode |= HAL_IRDA_ERROR_NE; + } + + /* IRDA Over-Run interrupt occurred -----------------------------------------*/ + if (((isrflags & USART_ISR_ORE) != 0U) && + (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || ((cr3its & USART_CR3_EIE) != 0U))) + { + __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_OREF); + + hirda->ErrorCode |= HAL_IRDA_ERROR_ORE; + } + + /* Call IRDA Error Call back function if need be --------------------------*/ + if (hirda->ErrorCode != HAL_IRDA_ERROR_NONE) + { + /* IRDA in mode Receiver ---------------------------------------------------*/ + if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) && ((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)) + { + IRDA_Receive_IT(hirda); + } + + /* If Overrun error occurs, or if any error occurs in DMA mode reception, + consider error as blocking */ + errorcode = hirda->ErrorCode; + if ((HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) || + ((errorcode & HAL_IRDA_ERROR_ORE) != 0U)) + { + /* Blocking error : transfer is aborted + Set the IRDA state ready to be able to start again the process, + Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ + IRDA_EndRxTransfer(hirda); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Disable the IRDA DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); + + /* Abort the IRDA DMA Rx channel */ + if (hirda->hdmarx != NULL) + { + /* Set the IRDA DMA Abort callback : + will lead to call HAL_IRDA_ErrorCallback() at end of DMA abort procedure */ + hirda->hdmarx->XferAbortCallback = IRDA_DMAAbortOnError; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK) + { + /* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */ + hirda->hdmarx->XferAbortCallback(hirda->hdmarx); + } + } + else + { +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered user error callback */ + hirda->ErrorCallback(hirda); +#else + /* Call legacy weak user error callback */ + HAL_IRDA_ErrorCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ + } + } + else +#endif /* HAL_DMA_MODULE_ENABLED */ + { +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered user error callback */ + hirda->ErrorCallback(hirda); +#else + /* Call legacy weak user error callback */ + HAL_IRDA_ErrorCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ + } + } + else + { + /* Non Blocking error : transfer could go on. + Error is notified to user through user error callback */ +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered user error callback */ + hirda->ErrorCallback(hirda); +#else + /* Call legacy weak user error callback */ + HAL_IRDA_ErrorCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ + hirda->ErrorCode = HAL_IRDA_ERROR_NONE; + } + } + return; + + } /* End if some error occurs */ + + /* IRDA in mode Transmitter ------------------------------------------------*/ + if (((isrflags & USART_ISR_TXE_TXFNF) != 0U) && ((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U)) + { + IRDA_Transmit_IT(hirda); + return; + } + + /* IRDA in mode Transmitter (transmission end) -----------------------------*/ + if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U)) + { + IRDA_EndTransmit_IT(hirda); + return; + } + +} + +/** + * @brief Tx Transfer completed callback. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval None + */ +__weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hirda); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_IRDA_TxCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Tx Half Transfer completed callback. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified USART module. + * @retval None + */ +__weak void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hirda); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_IRDA_TxHalfCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Rx Transfer completed callback. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval None + */ +__weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hirda); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_IRDA_RxCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Rx Half Transfer complete callback. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval None + */ +__weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hirda); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_IRDA_RxHalfCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief IRDA error callback. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval None + */ +__weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hirda); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_IRDA_ErrorCallback can be implemented in the user file. + */ +} + +/** + * @brief IRDA Abort Complete callback. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval None + */ +__weak void HAL_IRDA_AbortCpltCallback(IRDA_HandleTypeDef *hirda) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hirda); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_IRDA_AbortCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief IRDA Abort Complete callback. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval None + */ +__weak void HAL_IRDA_AbortTransmitCpltCallback(IRDA_HandleTypeDef *hirda) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hirda); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_IRDA_AbortTransmitCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief IRDA Abort Receive Complete callback. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval None + */ +__weak void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hirda); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_IRDA_AbortReceiveCpltCallback can be implemented in the user file. + */ +} + +/** + * @} + */ + +/** @defgroup IRDA_Exported_Functions_Group4 Peripheral State and Error functions + * @brief IRDA State and Errors functions + * +@verbatim + ============================================================================== + ##### Peripheral State and Error functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to return the State of IrDA + communication process and also return Peripheral Errors occurred during communication process + (+) HAL_IRDA_GetState() API can be helpful to check in run-time the state + of the IRDA peripheral handle. + (+) HAL_IRDA_GetError() checks in run-time errors that could occur during + communication. + +@endverbatim + * @{ + */ + +/** + * @brief Return the IRDA handle state. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval HAL state + */ +HAL_IRDA_StateTypeDef HAL_IRDA_GetState(const IRDA_HandleTypeDef *hirda) +{ + /* Return IRDA handle state */ + uint32_t temp1; + uint32_t temp2; + temp1 = (uint32_t)hirda->gState; + temp2 = (uint32_t)hirda->RxState; + + return (HAL_IRDA_StateTypeDef)(temp1 | temp2); +} + +/** + * @brief Return the IRDA handle error code. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval IRDA Error Code + */ +uint32_t HAL_IRDA_GetError(const IRDA_HandleTypeDef *hirda) +{ + return hirda->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup IRDA_Private_Functions IRDA Private Functions + * @{ + */ + +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) +/** + * @brief Initialize the callbacks to their default values. + * @param hirda IRDA handle. + * @retval none + */ +void IRDA_InitCallbacksToDefault(IRDA_HandleTypeDef *hirda) +{ + /* Init the IRDA Callback settings */ + hirda->TxHalfCpltCallback = HAL_IRDA_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + hirda->TxCpltCallback = HAL_IRDA_TxCpltCallback; /* Legacy weak TxCpltCallback */ + hirda->RxHalfCpltCallback = HAL_IRDA_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + hirda->RxCpltCallback = HAL_IRDA_RxCpltCallback; /* Legacy weak RxCpltCallback */ + hirda->ErrorCallback = HAL_IRDA_ErrorCallback; /* Legacy weak ErrorCallback */ + hirda->AbortCpltCallback = HAL_IRDA_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + hirda->AbortTransmitCpltCallback = HAL_IRDA_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */ + hirda->AbortReceiveCpltCallback = HAL_IRDA_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */ + +} +#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ + +/** + * @brief Configure the IRDA peripheral. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval HAL status + */ +static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda) +{ + uint32_t tmpreg; + IRDA_ClockSourceTypeDef clocksource; + HAL_StatusTypeDef ret = HAL_OK; + static const uint16_t IRDAPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U}; + uint32_t pclk; + + /* Check the communication parameters */ + assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate)); + assert_param(IS_IRDA_WORD_LENGTH(hirda->Init.WordLength)); + assert_param(IS_IRDA_PARITY(hirda->Init.Parity)); + assert_param(IS_IRDA_TX_RX_MODE(hirda->Init.Mode)); + assert_param(IS_IRDA_PRESCALER(hirda->Init.Prescaler)); + assert_param(IS_IRDA_POWERMODE(hirda->Init.PowerMode)); + assert_param(IS_IRDA_CLOCKPRESCALER(hirda->Init.ClockPrescaler)); + + /*-------------------------- USART CR1 Configuration -----------------------*/ + /* Configure the IRDA Word Length, Parity and transfer Mode: + Set the M bits according to hirda->Init.WordLength value + Set PCE and PS bits according to hirda->Init.Parity value + Set TE and RE bits according to hirda->Init.Mode value */ + tmpreg = (uint32_t)hirda->Init.WordLength | hirda->Init.Parity | hirda->Init.Mode ; + + MODIFY_REG(hirda->Instance->CR1, IRDA_CR1_FIELDS, tmpreg); + + /*-------------------------- USART CR3 Configuration -----------------------*/ + MODIFY_REG(hirda->Instance->CR3, USART_CR3_IRLP, hirda->Init.PowerMode); + + /*--------------------- USART clock PRESC Configuration ----------------*/ + /* Configure + * - IRDA Clock Prescaler: set PRESCALER according to hirda->Init.ClockPrescaler value */ + MODIFY_REG(hirda->Instance->PRESC, USART_PRESC_PRESCALER, hirda->Init.ClockPrescaler); + + /*-------------------------- USART GTPR Configuration ----------------------*/ + MODIFY_REG(hirda->Instance->GTPR, (uint16_t)USART_GTPR_PSC, (uint16_t)hirda->Init.Prescaler); + + /*-------------------------- USART BRR Configuration -----------------------*/ + IRDA_GETCLOCKSOURCE(hirda, clocksource); + tmpreg = 0U; + switch (clocksource) + { + case IRDA_CLOCKSOURCE_PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); + break; + case IRDA_CLOCKSOURCE_PCLK2: + pclk = HAL_RCC_GetPCLK2Freq(); + tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); + break; + case IRDA_CLOCKSOURCE_HSI: + tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(HSI_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); + break; + case IRDA_CLOCKSOURCE_SYSCLK: + pclk = HAL_RCC_GetSysClockFreq(); + tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); + break; + case IRDA_CLOCKSOURCE_LSE: + tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16((uint32_t)LSE_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); + break; + default: + ret = HAL_ERROR; + break; + } + + /* USARTDIV must be greater than or equal to 0d16 */ + if ((tmpreg >= USART_BRR_MIN) && (tmpreg <= USART_BRR_MAX)) + { + hirda->Instance->BRR = (uint16_t)tmpreg; + } + else + { + ret = HAL_ERROR; + } + + return ret; +} + +/** + * @brief Check the IRDA Idle State. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval HAL status + */ +static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda) +{ + uint32_t tickstart; + + /* Initialize the IRDA ErrorCode */ + hirda->ErrorCode = HAL_IRDA_ERROR_NONE; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + /* Check if the Transmitter is enabled */ + if ((hirda->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) + { + /* Wait until TEACK flag is set */ + if (IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_TEACK, RESET, tickstart, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK) + { + /* Timeout occurred */ + return HAL_TIMEOUT; + } + } + /* Check if the Receiver is enabled */ + if ((hirda->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) + { + /* Wait until REACK flag is set */ + if (IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_REACK, RESET, tickstart, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK) + { + /* Timeout occurred */ + return HAL_TIMEOUT; + } + } + + /* Initialize the IRDA state*/ + hirda->gState = HAL_IRDA_STATE_READY; + hirda->RxState = HAL_IRDA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + + return HAL_OK; +} + +/** + * @brief Handle IRDA Communication Timeout. It waits + * until a flag is no longer in the specified status. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @param Flag Specifies the IRDA flag to check. + * @param Status The actual Flag status (SET or RESET) + * @param Tickstart Tick start value + * @param Timeout Timeout duration + * @retval HAL status + */ +static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout) +{ + /* Wait until flag is set */ + while ((__HAL_IRDA_GET_FLAG(hirda, Flag) ? SET : RESET) == Status) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) + interrupts for the interrupt process */ + CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE)); + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); + + hirda->gState = HAL_IRDA_STATE_READY; + hirda->RxState = HAL_IRDA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hirda); + return HAL_TIMEOUT; + } + } + } + return HAL_OK; +} + + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief End ongoing Tx transfer on IRDA peripheral (following error detection or Transmit completion). + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval None + */ +static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda) +{ + /* Disable TXEIE and TCIE interrupts */ + CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + + /* At end of Tx process, restore hirda->gState to Ready */ + hirda->gState = HAL_IRDA_STATE_READY; +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval None + */ +static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda) +{ + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); + + /* At end of Rx process, restore hirda->RxState to Ready */ + hirda->RxState = HAL_IRDA_STATE_READY; +} + + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief DMA IRDA transmit process complete callback. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma) +{ + IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent); + + /* DMA Normal mode */ + if (hdma->Mode != DMA_LINKEDLIST_CIRCULAR) + { + hirda->TxXferCount = 0U; + + /* Disable the DMA transfer for transmit request by resetting the DMAT bit + in the IRDA CR3 register */ + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); + + /* Enable the IRDA Transmit Complete Interrupt */ + SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE); + } + /* DMA Circular mode */ + else + { +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered Tx complete callback */ + hirda->TxCpltCallback(hirda); +#else + /* Call legacy weak Tx complete callback */ + HAL_IRDA_TxCpltCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ + } + +} + +/** + * @brief DMA IRDA transmit process half complete callback. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma) +{ + IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent); + +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered Tx Half complete callback */ + hirda->TxHalfCpltCallback(hirda); +#else + /* Call legacy weak Tx complete callback */ + HAL_IRDA_TxHalfCpltCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ +} + +/** + * @brief DMA IRDA receive process complete callback. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +{ + IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent); + + /* DMA Normal mode */ + if (hdma->Mode != DMA_LINKEDLIST_CIRCULAR) + { + hirda->RxXferCount = 0U; + + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE); + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); + + /* Disable the DMA transfer for the receiver request by resetting the DMAR bit + in the IRDA CR3 register */ + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); + + /* At end of Rx process, restore hirda->RxState to Ready */ + hirda->RxState = HAL_IRDA_STATE_READY; + } + +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered Rx complete callback */ + hirda->RxCpltCallback(hirda); +#else + /* Call legacy weak Rx complete callback */ + HAL_IRDA_RxCpltCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA IRDA receive process half complete callback. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma) +{ + IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent); + +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /*Call registered Rx Half complete callback*/ + hirda->RxHalfCpltCallback(hirda); +#else + /* Call legacy weak Rx Half complete callback */ + HAL_IRDA_RxHalfCpltCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ +} + +/** + * @brief DMA IRDA communication error callback. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void IRDA_DMAError(DMA_HandleTypeDef *hdma) +{ + IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent); + + /* Stop IRDA DMA Tx request if ongoing */ + if (hirda->gState == HAL_IRDA_STATE_BUSY_TX) + { + if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) + { + hirda->TxXferCount = 0U; + IRDA_EndTxTransfer(hirda); + } + } + + /* Stop IRDA DMA Rx request if ongoing */ + if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX) + { + if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) + { + hirda->RxXferCount = 0U; + IRDA_EndRxTransfer(hirda); + } + } + + hirda->ErrorCode |= HAL_IRDA_ERROR_DMA; +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered user error callback */ + hirda->ErrorCallback(hirda); +#else + /* Call legacy weak user error callback */ + HAL_IRDA_ErrorCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ +} + +/** + * @brief DMA IRDA communication abort callback, when initiated by HAL services on Error + * (To be called at end of DMA Abort procedure following error occurrence). + * @param hdma DMA handle. + * @retval None + */ +static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma) +{ + IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent); + hirda->RxXferCount = 0U; + hirda->TxXferCount = 0U; + +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered user error callback */ + hirda->ErrorCallback(hirda); +#else + /* Call legacy weak user error callback */ + HAL_IRDA_ErrorCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ +} + +/** + * @brief DMA IRDA Tx communication abort callback, when initiated by user + * (To be called at end of DMA Tx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Rx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma) +{ + IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent); + + hirda->hdmatx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if (hirda->hdmarx != NULL) + { + if (hirda->hdmarx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + hirda->TxXferCount = 0U; + hirda->RxXferCount = 0U; + + /* Reset errorCode */ + hirda->ErrorCode = HAL_IRDA_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF); + + /* Restore hirda->gState and hirda->RxState to Ready */ + hirda->gState = HAL_IRDA_STATE_READY; + hirda->RxState = HAL_IRDA_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + hirda->AbortCpltCallback(hirda); +#else + /* Call legacy weak Abort complete callback */ + HAL_IRDA_AbortCpltCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ +} + + +/** + * @brief DMA IRDA Rx communication abort callback, when initiated by user + * (To be called at end of DMA Rx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Tx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma) +{ + IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent); + + hirda->hdmarx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if (hirda->hdmatx != NULL) + { + if (hirda->hdmatx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + hirda->TxXferCount = 0U; + hirda->RxXferCount = 0U; + + /* Reset errorCode */ + hirda->ErrorCode = HAL_IRDA_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF); + + /* Restore hirda->gState and hirda->RxState to Ready */ + hirda->gState = HAL_IRDA_STATE_READY; + hirda->RxState = HAL_IRDA_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + hirda->AbortCpltCallback(hirda); +#else + /* Call legacy weak Abort complete callback */ + HAL_IRDA_AbortCpltCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ +} + + +/** + * @brief DMA IRDA Tx communication abort callback, when initiated by user by a call to + * HAL_IRDA_AbortTransmit_IT API (Abort only Tx transfer) + * (This callback is executed at end of DMA Tx Abort procedure following user abort request, + * and leads to user Tx Abort Complete callback execution). + * @param hdma DMA handle. + * @retval None + */ +static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma) +{ + IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent); + + hirda->TxXferCount = 0U; + + /* Restore hirda->gState to Ready */ + hirda->gState = HAL_IRDA_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + hirda->AbortTransmitCpltCallback(hirda); +#else + /* Call legacy weak Abort Transmit Complete Callback */ + HAL_IRDA_AbortTransmitCpltCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ +} + +/** + * @brief DMA IRDA Rx communication abort callback, when initiated by user by a call to + * HAL_IRDA_AbortReceive_IT API (Abort only Rx transfer) + * (This callback is executed at end of DMA Rx Abort procedure following user abort request, + * and leads to user Rx Abort Complete callback execution). + * @param hdma DMA handle. + * @retval None + */ +static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) +{ + IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + hirda->RxXferCount = 0U; + + /* Clear the Error flags in the ICR register */ + __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF); + + /* Restore hirda->RxState to Ready */ + hirda->RxState = HAL_IRDA_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + hirda->AbortReceiveCpltCallback(hirda); +#else + /* Call legacy weak Abort Receive Complete Callback */ + HAL_IRDA_AbortReceiveCpltCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Send an amount of data in interrupt mode. + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_IRDA_Transmit_IT(). + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval None + */ +static void IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda) +{ + const uint16_t *tmp; + + /* Check that a Tx process is ongoing */ + if (hirda->gState == HAL_IRDA_STATE_BUSY_TX) + { + if (hirda->TxXferCount == 0U) + { + /* Disable the IRDA Transmit Data Register Empty Interrupt */ + CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); + + /* Enable the IRDA Transmit Complete Interrupt */ + SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE); + } + else + { + if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE)) + { + tmp = (const uint16_t *) hirda->pTxBuffPtr; /* Derogation R.11.3 */ + hirda->Instance->TDR = (uint16_t)(*tmp & 0x01FFU); + hirda->pTxBuffPtr += 2U; + } + else + { + hirda->Instance->TDR = (uint8_t)(*hirda->pTxBuffPtr & 0xFFU); + hirda->pTxBuffPtr++; + } + hirda->TxXferCount--; + } + } +} + +/** + * @brief Wrap up transmission in non-blocking mode. + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval None + */ +static void IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda) +{ + /* Disable the IRDA Transmit Complete Interrupt */ + CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TCIE); + + /* Tx process is ended, restore hirda->gState to Ready */ + hirda->gState = HAL_IRDA_STATE_READY; + +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered Tx complete callback */ + hirda->TxCpltCallback(hirda); +#else + /* Call legacy weak Tx complete callback */ + HAL_IRDA_TxCpltCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ +} + +/** + * @brief Receive an amount of data in interrupt mode. + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_IRDA_Receive_IT() + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval None + */ +static void IRDA_Receive_IT(IRDA_HandleTypeDef *hirda) +{ + uint16_t *tmp; + uint16_t uhMask = hirda->Mask; + uint16_t uhdata; + + /* Check that a Rx process is ongoing */ + if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX) + { + uhdata = (uint16_t) READ_REG(hirda->Instance->RDR); + if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE)) + { + tmp = (uint16_t *) hirda->pRxBuffPtr; /* Derogation R.11.3 */ + *tmp = (uint16_t)(uhdata & uhMask); + hirda->pRxBuffPtr += 2U; + } + else + { + *hirda->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); + hirda->pRxBuffPtr++; + } + + hirda->RxXferCount--; + if (hirda->RxXferCount == 0U) + { + /* Disable the IRDA Parity Error Interrupt and RXNE interrupt */ + CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + + /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */ + CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); + + /* Rx process is completed, restore hirda->RxState to Ready */ + hirda->RxState = HAL_IRDA_STATE_READY; + +#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) + /* Call registered Rx complete callback */ + hirda->RxCpltCallback(hirda); +#else + /* Call legacy weak Rx complete callback */ + HAL_IRDA_RxCpltCallback(hirda); +#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ + } + } + else + { + /* Clear RXNE interrupt flag */ + __HAL_IRDA_SEND_REQ(hirda, IRDA_RXDATA_FLUSH_REQUEST); + } +} + +/** + * @} + */ + +#endif /* HAL_IRDA_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_iwdg.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_iwdg.c new file mode 100644 index 0000000000..e31bb26c6f --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_iwdg.c @@ -0,0 +1,510 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_iwdg.c + * @author MCD Application Team + * @brief IWDG HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Independent Watchdog (IWDG) peripheral: + * + Initialization and Start functions + * + IO operation functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### IWDG Generic features ##### + ============================================================================== + [..] + (+) The IWDG can be started by either software or hardware (configurable + through option byte). + + (+) The IWDG is clocked by the Low-Speed Internal clock (LSI) and thus stays + active even if the main clock fails. + + (+) Once the IWDG is started, the LSI is forced ON and both cannot be + disabled. The counter starts counting down from the reset value (0xFFF). + When it reaches the end of count value (0x000) a reset signal is + generated (IWDG reset). + + (+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register, + the IWDG_RLR value is reloaded into the counter and the watchdog reset + is prevented. + + (+) The IWDG is implemented in the VDD voltage domain that is still functional + in STOP and STANDBY mode (IWDG reset can wake up the CPU from STANDBY). + IWDGRST flag in RCC_CSR register can be used to inform when an IWDG + reset occurs. + + (+) Debug mode: When the microcontroller enters debug mode (core halted), + the IWDG counter either continues to work normally or stops, depending + on DBG_IWDG_STOP configuration bit in DBG module, accessible through + __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros. + + [..] Min-max timeout value @32KHz (LSI): ~125us / ~131.04s + The IWDG timeout may vary due to LSI clock frequency dispersion. + STM32WBAxx devices provide the capability to measure the LSI clock + frequency (LSI clock is internally connected to TIM16 CH1 input capture). + The measured value can be used to have an IWDG timeout with an + acceptable accuracy. + + [..] Default timeout value (necessary for IWDG_SR status register update): + Constant LSI_VALUE is defined based on the nominal LSI clock frequency. + This frequency being subject to variations as mentioned above, the + default timeout value (defined through constant HAL_IWDG_DEFAULT_TIMEOUT + below) may become too short or too long. + In such cases, this default timeout value can be tuned by redefining + the constant LSI_VALUE at user-application level (based, for instance, + on the measured LSI clock frequency as explained above). + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Register callback to treat Iwdg interrupt and MspInit using HAL_IWDG_RegisterCallback(). + (++) Provide exiting handle as first parameter. + (++) Provide which callback will be registered using one value from + HAL_IWDG_CallbackIDTypeDef. + (++) Provide callback function pointer. + + (#) Use IWDG using HAL_IWDG_Init() function to : + (++) Enable instance by writing Start keyword in IWDG_KEY register. LSI + clock is forced ON and IWDG counter starts counting down. + (++) Enable write access to configuration registers: + IWDG_PR, IWDG_RLR, IWDG_WINR and EWCR. + (++) Configure the IWDG prescaler and counter reload value. This reload + value will be loaded in the IWDG counter each time the watchdog is + reloaded, then the IWDG will start counting down from this value. + (++) Depending on window parameter: + (+++) If Window Init parameter is same as Window register value, + nothing more is done but reload counter value in order to exit + function with exact time base. + (+++) Else modify Window register. This will automatically reload + watchdog counter. + (++) Depending on Early Wakeup Interrupt parameter: + (+++) If EWI is set to disable, comparator is set to 0, interrupt is + disable & flag is clear. + (+++) Else modify EWCR register, setting comparator value, enable + interrupt & clear flag. + (++) Wait for status flags to be reset. + + (#) Then the application program must refresh the IWDG counter at regular + intervals during normal operation to prevent an MCU reset, using + HAL_IWDG_Refresh() function. + + *** IWDG HAL driver macros list *** + ==================================== + [..] + Below the list of most used macros in IWDG HAL driver: + (+) __HAL_IWDG_START: Enable the IWDG peripheral + (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in + the reload register + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +#ifdef HAL_IWDG_MODULE_ENABLED +/** @addtogroup IWDG + * @brief IWDG HAL module driver. + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup IWDG_Private_Defines IWDG Private Defines + * @{ + */ +/* Status register needs up to 5 LSI clock periods to be updated. However a + synchronisation is added on prescaled LSI clock rising edge, so we only + consider a highest prescaler cycle. + The timeout value is calculated using the highest prescaler (1024) and + the LSI_VALUE constant. The value of this constant can be changed by the user + to take into account possible LSI clock period variations. + The timeout value is multiplied by 1000 to be converted in milliseconds. + LSI startup time is also considered here by adding LSI_STARTUP_TIME + converted in milliseconds. */ +#define HAL_IWDG_DEFAULT_TIMEOUT (((1UL * 1024UL * 1000UL) / LSI_VALUE) + ((LSI_STARTUP_TIME / 1000UL) + 1UL)) +#define IWDG_KERNEL_UPDATE_FLAGS (IWDG_SR_EWU | IWDG_SR_WVU | IWDG_SR_RVU | IWDG_SR_PVU) +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup IWDG_Exported_Functions + * @{ + */ + +/** @addtogroup IWDG_Exported_Functions_Group1 + * @brief Initialization and Start functions. + * +@verbatim + =============================================================================== + ##### Initialization and Start functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize the IWDG according to the specified parameters in the + IWDG_InitTypeDef of associated handle. + (+) Manage Window option. + (+) Once initialization is performed in HAL_IWDG_Init function, Watchdog + is reloaded in order to exit function with correct time base. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the IWDG according to the specified parameters in the + * IWDG_InitTypeDef and start watchdog. Before exiting function, + * watchdog is refreshed in order to have correct time base. + * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains + * the configuration information for the specified IWDG module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) +{ + uint32_t tickstart; + + /* Check the IWDG handle allocation */ + if (hiwdg == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance)); + assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler)); + assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload)); + assert_param(IS_IWDG_WINDOW(hiwdg->Init.Window)); + assert_param(IS_IWDG_EWI(hiwdg->Init.EWI)); + +#if (USE_HAL_IWDG_REGISTER_CALLBACKS == 1) + /* Reset Callback pointers */ + if (hiwdg->EwiCallback == NULL) + { + hiwdg->EwiCallback = HAL_IWDG_EarlyWakeupCallback; + } + if (hiwdg->MspInitCallback == NULL) + { + hiwdg->MspInitCallback = HAL_IWDG_MspInit; + } + + /* Init the low level hardware */ + hiwdg->MspInitCallback(hiwdg); +#else + /* Init the low level hardware */ + HAL_IWDG_MspInit(hiwdg); +#endif /* USE_HAL_IWDG_REGISTER_CALLBACKS */ + + /* Enable IWDG. LSI is turned on automatically */ + __HAL_IWDG_START(hiwdg); + + /* Enable write access to IWDG_PR, IWDG_RLR, IWDG_WINR and EWCR registers by writing + 0x5555 in KR */ + IWDG_ENABLE_WRITE_ACCESS(hiwdg); + + /* Write to IWDG registers the Prescaler & Reload values to work with */ + hiwdg->Instance->PR = hiwdg->Init.Prescaler; + hiwdg->Instance->RLR = hiwdg->Init.Reload; + + /* Check Reload update flag, before performing any reload of the counter, else previous value + will be taken. */ + tickstart = HAL_GetTick(); + + /* Wait for register to be updated */ + while ((hiwdg->Instance->SR & IWDG_SR_RVU) != 0x00u) + { + if ((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT) + { + if ((hiwdg->Instance->SR & IWDG_SR_RVU) != 0x00u) + { + return HAL_TIMEOUT; + } + } + } + + if (hiwdg->Init.EWI == IWDG_EWI_DISABLE) + { + /* EWI comparator value equal 0, disable the early wakeup interrupt + * acknowledge the early wakeup interrupt in any cases. it clears the EWIF flag in SR register + * Set Watchdog Early Wakeup Comparator to 0x00 */ + hiwdg->Instance->EWCR = IWDG_EWCR_EWIC; + } + else + { + /* EWI comparator value different from 0, enable the early wakeup interrupt, + * acknowledge the early wakeup interrupt in any cases. it clears the EWIF flag in SR register + * Set Watchdog Early Wakeup Comparator value */ + hiwdg->Instance->EWCR = IWDG_EWCR_EWIE | IWDG_EWCR_EWIC | hiwdg->Init.EWI; + } + + /* Check pending flag, if previous update not done, return timeout */ + tickstart = HAL_GetTick(); + + /* Wait for register to be updated */ + while ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u) + { + if ((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT) + { + if ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u) + { + return HAL_TIMEOUT; + } + } + } + + /* If window parameter is different than current value, modify window + register */ + if (hiwdg->Instance->WINR != hiwdg->Init.Window) + { + /* Write to IWDG WINR the IWDG_Window value to compare with. In any case, + even if window feature is disabled, Watchdog will be reloaded by writing + windows register */ + hiwdg->Instance->WINR = hiwdg->Init.Window; + } + else + { + /* Reload IWDG counter with value defined in the reload register */ + __HAL_IWDG_RELOAD_COUNTER(hiwdg); + } + + /* Return function status */ + return HAL_OK; +} + + +/** + * @brief Initialize the IWDG MSP. + * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains + * the configuration information for the specified IWDG module. + * @note When rewriting this function in user file, mechanism may be added + * to avoid multiple initialize when HAL_IWDG_Init function is called + * again to change parameters. + * @retval None + */ +__weak void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hiwdg); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_IWDG_MspInit could be implemented in the user file + */ +} + + +#if (USE_HAL_IWDG_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User IWDG Callback + * To be used instead of the weak (surcharged) predefined callback + * @param hiwdg IWDG handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_IWDG_EWI_CB_ID Early WakeUp Interrupt Callback ID + * @arg @ref HAL_IWDG_MSPINIT_CB_ID MspInit callback ID + * @param pCallback pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_IWDG_RegisterCallback(IWDG_HandleTypeDef *hiwdg, HAL_IWDG_CallbackIDTypeDef CallbackID, + pIWDG_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + status = HAL_ERROR; + } + else + { + switch (CallbackID) + { + case HAL_IWDG_EWI_CB_ID: + hiwdg->EwiCallback = pCallback; + break; + case HAL_IWDG_MSPINIT_CB_ID: + hiwdg->MspInitCallback = pCallback; + break; + + default: + status = HAL_ERROR; + break; + } + } + + return status; +} + + +/** + * @brief Unregister a IWDG Callback + * IWDG Callback is redirected to the weak (surcharged) predefined callback + * @param hiwdg IWDG handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_IWDG_EWI_CB_ID Early WakeUp Interrupt Callback ID + * @arg @ref HAL_IWDG_MSPINIT_CB_ID MspInit callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_IWDG_UnRegisterCallback(IWDG_HandleTypeDef *hiwdg, HAL_IWDG_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + switch (CallbackID) + { + case HAL_IWDG_EWI_CB_ID: + hiwdg->EwiCallback = HAL_IWDG_EarlyWakeupCallback; + break; + case HAL_IWDG_MSPINIT_CB_ID: + hiwdg->MspInitCallback = HAL_IWDG_MspInit; + break; + + default: + status = HAL_ERROR; + break; + } + + return status; +} +#endif /* USE_HAL_IWDG_REGISTER_CALLBACKS */ + + +/** + * @} + */ + + +/** @addtogroup IWDG_Exported_Functions_Group2 + * @brief IO operation functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Refresh the IWDG. + +@endverbatim + * @{ + */ + +/** + * @brief Refresh the IWDG. + * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains + * the configuration information for the specified IWDG module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg) +{ + /* Reload IWDG counter with value defined in the reload register */ + __HAL_IWDG_RELOAD_COUNTER(hiwdg); + + /* Return function status */ + return HAL_OK; +} + + +/** + * @brief Get back IWDG running status + * @note This API allows to know if IWDG has been started by other master, thread + * or by hardware. + * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains + * the configuration information for the specified IWDG module. + * @retval can be one of following value : + * @arg @ref IWDG_STATUS_DISABLE + * @arg @ref IWDG_STATUS_ENABLE + */ +uint32_t HAL_IWDG_GetActiveStatus(const IWDG_HandleTypeDef *hiwdg) +{ + uint32_t status; + + /* Get back ONF flag */ + status = (hiwdg->Instance->SR & IWDG_SR_ONF); + + /* Return status */ + return status; +} + + +/** + * @brief Handle IWDG interrupt request. + * @note The Early Wakeup Interrupt (EWI) can be used if specific safety operations + * or data logging must be performed before the actual reset is generated. + * The EWI interrupt is enabled by calling HAL_IWDG_Init function with + * EWIMode set to IWDG_EWI_ENABLE. + * When the downcounter reaches the value 0x40, and EWI interrupt is + * generated and the corresponding Interrupt Service Routine (ISR) can + * be used to trigger specific actions (such as communications or data + * logging), before resetting the device. + * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains + * the configuration information for the specified IWDG module. + * @retval None + */ +void HAL_IWDG_IRQHandler(IWDG_HandleTypeDef *hiwdg) +{ + /* Check if IWDG Early Wakeup Interrupt occurred */ + if ((hiwdg->Instance->SR & IWDG_SR_EWIF) != 0x00u) + { + /* Clear the IWDG Early Wakeup flag */ + hiwdg->Instance->EWCR |= IWDG_EWCR_EWIC; + +#if (USE_HAL_IWDG_REGISTER_CALLBACKS == 1) + /* Early Wakeup registered callback */ + hiwdg->EwiCallback(hiwdg); +#else + /* Early Wakeup callback */ + HAL_IWDG_EarlyWakeupCallback(hiwdg); +#endif /* USE_HAL_IWDG_REGISTER_CALLBACKS */ + } +} + + +/** + * @brief IWDG Early Wakeup callback. + * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains + * the configuration information for the specified IWDG module. + * @retval None + */ +__weak void HAL_IWDG_EarlyWakeupCallback(IWDG_HandleTypeDef *hiwdg) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hiwdg); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_IWDG_EarlyWakeupCallback could be implemented in the user file + */ +} + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_IWDG_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_lptim.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_lptim.c new file mode 100644 index 0000000000..c611fb09ba --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_lptim.c @@ -0,0 +1,3717 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_lptim.c + * @author MCD Application Team + * @brief LPTIM HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Low Power Timer (LPTIM) peripheral: + * + Initialization and de-initialization functions. + * + Start/Stop operation functions in polling mode. + * + Start/Stop operation functions in interrupt mode. + * + Reading operation functions. + * + Peripheral State functions. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LPTIM HAL driver can be used as follows: + + (#)Initialize the LPTIM low level resources by implementing the + HAL_LPTIM_MspInit(): + (++) Enable the LPTIM interface clock using __HAL_RCC_LPTIMx_CLK_ENABLE(). + (++) In case of using interrupts (e.g. HAL_LPTIM_PWM_Start_IT()): + (+++) Configure the LPTIM interrupt priority using HAL_NVIC_SetPriority(). + (+++) Enable the LPTIM IRQ handler using HAL_NVIC_EnableIRQ(). + (+++) In LPTIM IRQ handler, call HAL_LPTIM_IRQHandler(). + + (#)Initialize the LPTIM HAL using HAL_LPTIM_Init(). This function + configures mainly: + (++) The instance: LPTIM1 or LPTIM2. + (++) Clock: the counter clock. + (+++) Source : it can be either the ULPTIM input (IN1) or one of + the internal clock; (APB, LSE, LSI or HSI). + (+++) Prescaler: select the clock divider. + (++) UltraLowPowerClock : To be used only if the ULPTIM is selected + as counter clock source. + (+++) Polarity: polarity of the active edge for the counter unit + if the ULPTIM input is selected. + (+++) SampleTime: clock sampling time to configure the clock glitch + filter. + (++) Trigger: How the counter start. + (+++) Source: trigger can be software or one of the hardware triggers. + (+++) ActiveEdge : only for hardware trigger. + (+++) SampleTime : trigger sampling time to configure the trigger + glitch filter. + (++) OutputPolarity : 2 opposite polarities are possible. + (++) UpdateMode: specifies whether the update of the autoreload and + the compare values is done immediately or after the end of current + period. + (++) Input1Source: Source selected for input1 (GPIO or comparator output). + (++) Input2Source: Source selected for input2 (GPIO or comparator output). + Input2 is used only for encoder feature so is used only for LPTIM1 instance. + + (#)Six modes are available: + + (++) PWM Mode: To generate a PWM signal with specified period and pulse, + call HAL_LPTIM_PWM_Start() or HAL_LPTIM_PWM_Start_IT() for interruption + mode. + + (++) One Pulse Mode: To generate pulse with specified width in response + to a stimulus, call HAL_LPTIM_OnePulse_Start() or + HAL_LPTIM_OnePulse_Start_IT() for interruption mode. + + (++) Set once Mode: In this mode, the output changes the level (from + low level to high level if the output polarity is configured high, else + the opposite) when a compare match occurs. To start this mode, call + HAL_LPTIM_SetOnce_Start() or HAL_LPTIM_SetOnce_Start_IT() for + interruption mode. + + (++) Encoder Mode: To use the encoder interface call + HAL_LPTIM_Encoder_Start() or HAL_LPTIM_Encoder_Start_IT() for + interruption mode. Only available for LPTIM1 instance. + + (++) Time out Mode: an active edge on one selected trigger input rests + the counter. The first trigger event will start the timer, any + successive trigger event will reset the counter and the timer will + restart. To start this mode call HAL_LPTIM_TimeOut_Start_IT() or + HAL_LPTIM_TimeOut_Start_IT() for interruption mode. + + (++) Counter Mode: counter can be used to count external events on + the LPTIM Input1 or it can be used to count internal clock cycles. + To start this mode, call HAL_LPTIM_Counter_Start() or + HAL_LPTIM_Counter_Start_IT() for interruption mode. + + + (#) User can stop any process by calling the corresponding API: + HAL_LPTIM_Xxx_Stop() or HAL_LPTIM_Xxx_Stop_IT() if the process is + already started in interruption mode. + + (#) De-initialize the LPTIM peripheral using HAL_LPTIM_DeInit(). + + *** Callback registration *** + ============================================= + [..] + The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + [..] + Use Function HAL_LPTIM_RegisterCallback() to register a callback. + HAL_LPTIM_RegisterCallback() takes as parameters the HAL peripheral handle, + the Callback ID and a pointer to the user callback function. + [..] + Use function HAL_LPTIM_UnRegisterCallback() to reset a callback to the + default weak function. + HAL_LPTIM_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + [..] + These functions allow to register/unregister following callbacks: + + (+) MspInitCallback : LPTIM Base Msp Init Callback. + (+) MspDeInitCallback : LPTIM Base Msp DeInit Callback. + (+) CompareMatchCallback : Compare match Callback. + (+) AutoReloadMatchCallback : Auto-reload match Callback. + (+) TriggerCallback : External trigger event detection Callback. + (+) CompareWriteCallback : Compare register write complete Callback. + (+) AutoReloadWriteCallback : Auto-reload register write complete Callback. + (+) DirectionUpCallback : Up-counting direction change Callback. + (+) DirectionDownCallback : Down-counting direction change Callback. + (+) UpdateEventCallback : Update event detection Callback. + (+) RepCounterWriteCallback : Repetition counter register write complete Callback. + + [..] + By default, after the Init and when the state is HAL_LPTIM_STATE_RESET + all interrupt callbacks are set to the corresponding weak functions: + examples HAL_LPTIM_TriggerCallback(), HAL_LPTIM_CompareMatchCallback(). + + [..] + Exception done for MspInit and MspDeInit functions that are reset to the legacy weak + functionalities in the Init/DeInit only when these callbacks are null + (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init/DeInit + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + + [..] + Callbacks can be registered/unregistered in HAL_LPTIM_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_LPTIM_STATE_READY or HAL_LPTIM_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_LPTIM_RegisterCallback() before calling DeInit or Init function. + + [..] + When The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @defgroup LPTIM LPTIM + * @brief LPTIM HAL module driver. + * @{ + */ + +#ifdef HAL_LPTIM_MODULE_ENABLED + +#if defined (LPTIM1) || defined (LPTIM2) + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup LPTIM_Private_Constants + * @{ + */ +#define TIMEOUT 1000UL /* Timeout is 1s */ +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static HAL_StatusTypeDef LPTIM_OC1_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_OC_ConfigTypeDef *sConfig); +static HAL_StatusTypeDef LPTIM_OC2_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_OC_ConfigTypeDef *sConfig); +static void LPTIM_IC1_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_IC_ConfigTypeDef *sConfig); +static void LPTIM_IC2_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_IC_ConfigTypeDef *sConfig); +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) +static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ +static HAL_StatusTypeDef LPTIM_WaitForFlag(const LPTIM_HandleTypeDef *hlptim, uint32_t flag); +void LPTIM_DMAError(DMA_HandleTypeDef *hdma); +void LPTIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); +void LPTIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma); +void LPTIM_DMAUpdateEventCplt(DMA_HandleTypeDef *hdma); +void LPTIM_DMAUpdateEventHalfCplt(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef LPTIM_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t src, uint32_t dst, + uint32_t length); + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions + * @{ + */ + +/** @defgroup LPTIM_Exported_Functions_Group1 Initialization/de-initialization functions + * @brief Initialization and Configuration functions. + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Initialize the LPTIM according to the specified parameters in the + LPTIM_InitTypeDef and initialize the associated handle. + (+) DeInitialize the LPTIM peripheral. + (+) Initialize the LPTIM MSP. + (+) DeInitialize the LPTIM MSP. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the LPTIM according to the specified parameters in the + * LPTIM_InitTypeDef and initialize the associated handle. + * @param hlptim LPTIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) +{ + uint32_t tmpcfgr; + + /* Check the LPTIM handle allocation */ + if (hlptim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); + assert_param(IS_LPTIM_PERIOD(hlptim->Init.Period)); + + assert_param(IS_LPTIM_CLOCK_SOURCE(hlptim->Init.Clock.Source)); + assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler)); + if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) + || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) + { + assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity)); + assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime)); + } + assert_param(IS_LPTIM_TRG_SOURCE(hlptim->Init.Trigger.Source)); + if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE) + { + assert_param(IS_LPTIM_EXT_TRG_POLARITY(hlptim->Init.Trigger.ActiveEdge)); + assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(hlptim->Init.Trigger.SampleTime)); + } + assert_param(IS_LPTIM_UPDATE_MODE(hlptim->Init.UpdateMode)); + assert_param(IS_LPTIM_COUNTER_SOURCE(hlptim->Init.CounterSource)); + assert_param(IS_LPTIM_REPETITION(hlptim->Init.RepetitionCounter)); + + if (hlptim->State == HAL_LPTIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hlptim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + LPTIM_ResetCallback(hlptim); + + if (hlptim->MspInitCallback == NULL) + { + hlptim->MspInitCallback = HAL_LPTIM_MspInit; + } + + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + hlptim->MspInitCallback(hlptim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + HAL_LPTIM_MspInit(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + } + + /* Change the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_REPOK); + + /* Set the repetition counter */ + __HAL_LPTIM_REPETITIONCOUNTER_SET(hlptim, hlptim->Init.RepetitionCounter); + + /* Wait for the completion of the write operation to the LPTIM_RCR register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_REPOK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); + + /* Set LPTIM Period */ + __HAL_LPTIM_AUTORELOAD_SET(hlptim, hlptim->Init.Period); + + /* Wait for the completion of the write operation to the LPTIM_ARR register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + /* Get the LPTIMx CFGR value */ + tmpcfgr = hlptim->Instance->CFGR; + + if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) + || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) + { + tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL | LPTIM_CFGR_CKFLT)); + } + if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE) + { + tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGSEL)); + } + + /* Clear CKSEL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */ + tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD | + LPTIM_CFGR_PRESC | LPTIM_CFGR_COUNTMODE)); + + /* Set initialization parameters */ + tmpcfgr |= (hlptim->Init.Clock.Source | + hlptim->Init.Clock.Prescaler | + hlptim->Init.UpdateMode | + hlptim->Init.CounterSource); + + /* Glitch filters for internal triggers and external inputs are configured + * only if an internal clock source is provided to the LPTIM + */ + if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC) + { + tmpcfgr |= (hlptim->Init.Trigger.SampleTime | + hlptim->Init.UltraLowPowerClock.SampleTime); + } + + /* Configure LPTIM external clock polarity and digital filter */ + if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) + || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) + { + tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity | + hlptim->Init.UltraLowPowerClock.SampleTime); + } + + /* Configure LPTIM external trigger */ + if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE) + { + /* Enable External trigger and set the trigger source */ + tmpcfgr |= (hlptim->Init.Trigger.Source | + hlptim->Init.Trigger.ActiveEdge | + hlptim->Init.Trigger.SampleTime); + } + + /* Write to LPTIMx CFGR */ + hlptim->Instance->CFGR = tmpcfgr; + + /* Check LPTIM Input1 and Input2 sources */ + assert_param(IS_LPTIM_INPUT1_SOURCE(hlptim->Instance, hlptim->Init.Input1Source)); + assert_param(IS_LPTIM_INPUT2_SOURCE(hlptim->Instance, hlptim->Init.Input2Source)); + + /* Configure LPTIM Input1 and Input2 sources */ + hlptim->Instance->CFGR2 = (hlptim->Init.Input1Source | hlptim->Init.Input2Source); + + /* Initialize the LPTIM channels state */ + LPTIM_CHANNEL_STATE_SET_ALL(hlptim, HAL_LPTIM_CHANNEL_STATE_READY); + + /* Change the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief DeInitialize the LPTIM peripheral. + * @param hlptim LPTIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim) +{ + /* Check the LPTIM handle allocation */ + if (hlptim == NULL) + { + return HAL_ERROR; + } + + /* Change the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + __HAL_LPTIM_ENABLE(hlptim); + if (IS_LPTIM_CC2_INSTANCE(hlptim->Instance)) + { + hlptim->Instance->CCMR1 = 0; + } + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP1OK); + + __HAL_LPTIM_COMPARE_SET(hlptim, LPTIM_CHANNEL_1, 0); + /* Wait for the completion of the write operation to the LPTIM_CCR1 register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMP1OK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + if (IS_LPTIM_CC2_INSTANCE(hlptim->Instance)) + { + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP2OK); + + __HAL_LPTIM_COMPARE_SET(hlptim, LPTIM_CHANNEL_2, 0); + /* Wait for the completion of the write operation to the LPTIM_CCR2 register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMP2OK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + } + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); + + __HAL_LPTIM_AUTORELOAD_SET(hlptim, 0); + + /* Wait for the completion of the write operation to the LPTIM_ARR register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Disable the LPTIM Peripheral Clock */ + __HAL_LPTIM_DISABLE(hlptim); + + hlptim->Instance->CFGR = 0; + hlptim->Instance->CFGR2 = 0; + +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + if (hlptim->MspDeInitCallback == NULL) + { + hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit; + } + + /* DeInit the low level hardware: CLOCK, NVIC.*/ + hlptim->MspDeInitCallback(hlptim); +#else + /* DeInit the low level hardware: CLOCK, NVIC.*/ + HAL_LPTIM_MspDeInit(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + + /* Change the LPTIM channels state */ + LPTIM_CHANNEL_STATE_SET_ALL(hlptim, HAL_LPTIM_CHANNEL_STATE_RESET); + + /* Change the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hlptim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initialize the LPTIM MSP. + * @param hlptim LPTIM handle + * @retval None + */ +__weak void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hlptim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LPTIM_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitialize LPTIM MSP. + * @param hlptim LPTIM handle + * @retval None + */ +__weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hlptim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LPTIM_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup LPTIM_Exported_Functions_Group2 LPTIM Start-Stop operation functions + * @brief Start-Stop operation functions. + * +@verbatim + ============================================================================== + ##### LPTIM Start Stop operation functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Start the PWM mode. + (+) Stop the PWM mode. + (+) Start the One pulse mode. + (+) Stop the One pulse mode. + (+) Start the Set once mode. + (+) Stop the Set once mode. + (+) Start the Encoder mode. + (+) Stop the Encoder mode. + (+) Start the Timeout mode. + (+) Stop the Timeout mode. + (+) Start the Counter mode. + (+) Stop the Counter mode. + + +@endverbatim + * @{ + */ + +/** + * @brief Start the LPTIM PWM generation. + * @param hlptim LPTIM handle + * @param Channel LPTIM Channel to be enabled + * This parameter can be one of the following values: + * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected + * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel)); + + /* Check LPTIM channel state */ + if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Set the LPTIM channel state */ + LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY); + + /* Reset WAVE bit to set PWM mode */ + hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE; + + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Enable LPTIM signal on the corresponding output pin */ + __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel); + + /* Start timer in continuous mode */ + __HAL_LPTIM_START_CONTINUOUS(hlptim); + + /* Change the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stop the LPTIM PWM generation. + * @param hlptim LPTIM handle + * @param Channel LPTIM Channel to be disabled + * This parameter can be one of the following values: + * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected + * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel)); + + /* Change the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Disable LPTIM signal from the corresponding output pin */ + __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel); + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + /* Set the LPTIM channel state */ + LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Start the LPTIM PWM generation in interrupt mode. + * @param hlptim LPTIM handle + * @param Channel LPTIM Channel to be enabled + * This parameter can be one of the following values: + * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected + * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel)); + + /* Check LPTIM channel state */ + if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Set the LPTIM channel state */ + LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY); + + /* Reset WAVE bit to set PWM mode */ + hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE; + + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK); + + switch (Channel) + { + case LPTIM_CHANNEL_1: + /* Enable interrupt */ + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMP1OK | LPTIM_IT_CC1 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK | + LPTIM_IT_UPDATE); + break; + case LPTIM_CHANNEL_2: + /* Enable interrupt */ + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMP2OK | LPTIM_IT_CC2 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK | + LPTIM_IT_UPDATE); + break; + default: + break; + } + + /* Wait for the completion of the write operation to the LPTIM_DIER register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* If external trigger source is used, then enable external trigger interrupt */ + if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) + { + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK); + + /* Enable external trigger interrupt */ + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG); + + /* Wait for the completion of the write operation to the LPTIM_DIER register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + } + + __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel); + + /* Start timer in continuous mode */ + __HAL_LPTIM_START_CONTINUOUS(hlptim); + + /* Change the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stop the LPTIM PWM generation in interrupt mode. + * @param hlptim LPTIM handle + * @param Channel LPTIM Channel to be disabled + * This parameter can be one of the following values: + * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected + * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel)); + + /* Change the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Disable LPTIM signal from the corresponding output pin */ + __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel); + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK); + + switch (Channel) + { + case LPTIM_CHANNEL_1: + /* Disable interrupt */ + __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMP1OK | LPTIM_IT_CC1 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK | + LPTIM_IT_UPDATE); + break; + case LPTIM_CHANNEL_2: + /* Disable interrupt */ + __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMP2OK | LPTIM_IT_CC2 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK | + LPTIM_IT_UPDATE); + break; + default: + break; + } + + /* Wait for the completion of the write operation to the LPTIM_DIER register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* If external trigger source is used, then enable external trigger interrupt */ + if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) + { + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK); + + /* Enable external trigger interrupt */ + __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG); + + /* Wait for the completion of the write operation to the LPTIM_DIER register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + } + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + /* Set the LPTIM channel state */ + LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Start the LPTIM PWM generation in DMA mode. + * @param hlptim LPTIM handle + * @param Channel LPTIM Channel to be enabled + * This parameter can be one of the following values: + * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected + * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected + * @param pData The destination Buffer address + * @param Length The length of data to be transferred from LPTIM peripheral to memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_PWM_Start_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t Channel, const uint32_t *pData, + uint32_t Length) +{ + DMA_HandleTypeDef *hdma; + + /* Check the parameters */ + assert_param(IS_LPTIM_DMA_INSTANCE(hlptim->Instance)); + assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel)); + + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + + /* Check LPTIM channel state */ + if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Set the LPTIM channel state */ + LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY); + + /* Reset WAVE bit to set PWM mode */ + hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE; + + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Enable update event DMA request */ + __HAL_LPTIM_ENABLE_DMA(hlptim, LPTIM_DMA_UPDATE); + + /* Wait for the completion of the write operation to the LPTIM_DIER register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + switch (Channel) + { + case LPTIM_CHANNEL_1: + /* Set the DMA update event callbacks */ + hlptim->hdma[LPTIM_DMA_ID_CC1]->XferCpltCallback = LPTIM_DMAUpdateEventCplt; + hlptim->hdma[LPTIM_DMA_ID_CC1]->XferHalfCpltCallback = LPTIM_DMAUpdateEventHalfCplt; + + /* Set the DMA error callback */ + hlptim->hdma[LPTIM_DMA_ID_CC1]->XferErrorCallback = LPTIM_DMAError; + + /* Enable the DMA Channel */ + hdma = hlptim->hdma[LPTIM_DMA_ID_CC1]; + if (LPTIM_DMA_Start_IT(hdma, (uint32_t)pData, (uint32_t)&hlptim->Instance->CCR1, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + case LPTIM_CHANNEL_2: + /* Set the DMA update event callbacks */ + hlptim->hdma[LPTIM_DMA_ID_CC2]->XferCpltCallback = LPTIM_DMAUpdateEventCplt; + hlptim->hdma[LPTIM_DMA_ID_CC2]->XferHalfCpltCallback = LPTIM_DMAUpdateEventHalfCplt; + + /* Set the DMA error callback */ + hlptim->hdma[LPTIM_DMA_ID_CC2]->XferErrorCallback = LPTIM_DMAError; + + /* Enable the DMA Channel */ + hdma = hlptim->hdma[LPTIM_DMA_ID_CC2]; + if (LPTIM_DMA_Start_IT(hdma, (uint32_t)pData, (uint32_t)&hlptim->Instance->CCR2, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + default: + break; + } + + /* Enable LPTIM signal on the corresponding output pin */ + __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel); + + /* Start timer in continuous mode */ + __HAL_LPTIM_START_CONTINUOUS(hlptim); + + /* Change the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stop the LPTIM PWM generation in DMA mode. + * @param hlptim LPTIM handle + * @param Channel LPTIM Channel to be disabled + * This parameter can be one of the following values: + * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected + * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_DMA_INSTANCE(hlptim->Instance)); + assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel)); + + /* Change the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Disable update event DMA request */ + __HAL_LPTIM_DISABLE_DMA(hlptim, LPTIM_DMA_UPDATE); + + switch (Channel) + { + case LPTIM_CHANNEL_1: + /* Disable update event DMA request */ + (void)HAL_DMA_Abort_IT(hlptim->hdma[LPTIM_DMA_ID_CC1]); + break; + case LPTIM_CHANNEL_2: + /* Disable update event DMA request */ + (void)HAL_DMA_Abort_IT(hlptim->hdma[LPTIM_DMA_ID_CC2]); + break; + default: + break; + } + + /* Disable LPTIM signal from the corresponding output pin */ + __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel); + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + /* Set the LPTIM channel state */ + LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Start the LPTIM One pulse generation. + * @param hlptim LPTIM handle + * @param Channel LPTIM Channel to be enabled + * This parameter can be one of the following values: + * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected + * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel)); + + /* Check LPTIM channel state */ + if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Set the LPTIM channel state */ + LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY); + + /* Reset WAVE bit to set one pulse mode */ + hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE; + + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Enable LPTIM signal on the corresponding output pin */ + __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel); + + /* Start timer in single (one shot) mode */ + __HAL_LPTIM_START_SINGLE(hlptim); + + /* Change the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stop the LPTIM One pulse generation. + * @param hlptim LPTIM handle + * @param Channel LPTIM Channel to be disabled + * This parameter can be one of the following values: + * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected + * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel)); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Disable LPTIM signal on the corresponding output pin */ + __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel); + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + /* Set the LPTIM channel state */ + LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Start the LPTIM One pulse generation in interrupt mode. + * @param hlptim LPTIM handle + * @param Channel LPTIM Channel to be enabled + * This parameter can be one of the following values: + * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected + * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel)); + + /* Check LPTIM channel state */ + if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Set the LPTIM channel state */ + LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY); + + /* Reset WAVE bit to set one pulse mode */ + hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE; + + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK); + + switch (Channel) + { + case LPTIM_CHANNEL_1: + /* Enable interrupt */ + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMP1OK | LPTIM_IT_CC1 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK | + LPTIM_IT_UPDATE); + break; + case LPTIM_CHANNEL_2: + /* Enable interrupt */ + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMP2OK | LPTIM_IT_CC2 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK | + LPTIM_IT_UPDATE); + break; + default: + break; + } + + /* Wait for the completion of the write operation to the LPTIM_DIER register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* If external trigger source is used, then enable external trigger interrupt */ + if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) + { + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK); + /* Enable external trigger interrupt */ + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG); + /* Wait for the completion of the write operation to the LPTIM_DIER register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + } + + /* Enable LPTIM signal on the corresponding output pin */ + __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel); + + /* Start timer in single (one shot) mode */ + __HAL_LPTIM_START_SINGLE(hlptim); + + /* Change the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stop the LPTIM One pulse generation in interrupt mode. + * @param hlptim LPTIM handle + * @param Channel LPTIM Channel to be disabled + * This parameter can be one of the following values: + * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected + * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel)); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Disable LPTIM signal on the corresponding output pin */ + __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel); + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK); + + switch (Channel) + { + case LPTIM_CHANNEL_1: + /* Disable interrupt */ + __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMP1OK | LPTIM_IT_CC1 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK | + LPTIM_IT_UPDATE); + break; + case LPTIM_CHANNEL_2: + /* Disable interrupt */ + __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMP2OK | LPTIM_IT_CC2 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK | + LPTIM_IT_UPDATE); + break; + default: + break; + } + + /* Wait for the completion of the write operation to the LPTIM_DIER register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* If external trigger source is used, then enable external trigger interrupt */ + if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) + { + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK); + /* Enable external trigger interrupt */ + __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG); + /* Wait for the completion of the write operation to the LPTIM_DIER register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + } + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + /* Set the LPTIM channel state */ + LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Start the LPTIM in Set once mode. + * @param hlptim LPTIM handle + * @param Channel LPTIM Channel to be enabled + * This parameter can be one of the following values: + * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected + * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel)); + + /* Check LPTIM channel state */ + if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Set the LPTIM channel state */ + LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY); + + /* Set WAVE bit to enable the set once mode */ + hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE; + + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Enable LPTIM signal on the corresponding output pin */ + __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel); + + /* Start timer in single (one shot) mode */ + __HAL_LPTIM_START_SINGLE(hlptim); + + /* Change the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stop the LPTIM Set once mode. + * @param hlptim LPTIM handle + * @param Channel LPTIM Channel to be disabled + * This parameter can be one of the following values: + * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected + * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel)); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Disable LPTIM signal on the corresponding output pin */ + __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel); + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + /* Set the LPTIM channel state */ + LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Start the LPTIM Set once mode in interrupt mode. + * @param hlptim LPTIM handle + * @param Channel LPTIM Channel to be enabled + * This parameter can be one of the following values: + * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected + * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel)); + + /* Check LPTIM channel state */ + if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Set the LPTIM channel state */ + LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY); + + /* Set WAVE bit to enable the set once mode */ + hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE; + + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK); + + switch (Channel) + { + case LPTIM_CHANNEL_1: + /* Enable interrupt */ + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMP1OK | LPTIM_IT_CC1 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_UPDATE); + break; + case LPTIM_CHANNEL_2: + /* Enable interrupt */ + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMP2OK | LPTIM_IT_CC2 | LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_UPDATE); + break; + default: + break; + } + + /* Wait for the completion of the write operation to the LPTIM_DIER register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* If external trigger source is used, then enable external trigger interrupt */ + if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) + { + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK); + /* Enable external trigger interrupt */ + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG); + /* Wait for the completion of the write operation to the LPTIM_DIER register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + } + + /* Enable LPTIM signal on the corresponding output pin */ + __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel); + + /* Start timer in single (one shot) mode */ + __HAL_LPTIM_START_SINGLE(hlptim); + + /* Change the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stop the LPTIM Set once mode in interrupt mode. + * @param hlptim LPTIM handle + * @param Channel LPTIM Channel to be disabled + * This parameter can be one of the following values: + * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected + * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel)); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Disable LPTIM signal on the corresponding output pin */ + __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel); + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK); + + switch (Channel) + { + case LPTIM_CHANNEL_1: + /* Disable interrupt */ + __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMP1OK | LPTIM_IT_CC1 | LPTIM_IT_ARROK | LPTIM_IT_ARRM); + break; + case LPTIM_CHANNEL_2: + /* Disable interrupt */ + __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMP2OK | LPTIM_IT_CC2 | LPTIM_IT_ARROK | LPTIM_IT_ARRM); + break; + default: + break; + } + + /* Wait for the completion of the write operation to the LPTIM_DIER register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* If external trigger source is used, then enable external trigger interrupt */ + if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) + { + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK); + /* Enable external trigger interrupt */ + __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG); + + /* Wait for the completion of the write operation to the LPTIM_DIER register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + } + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + /* Set the LPTIM channel state */ + LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Start the Encoder interface. + * @param hlptim LPTIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim) +{ + uint32_t tmpcfgr; + + /* Check the parameters */ + assert_param(IS_LPTIM_ENCODER_INTERFACE_INSTANCE(hlptim->Instance)); + assert_param(hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC); + assert_param(hlptim->Init.Clock.Prescaler == LPTIM_PRESCALER_DIV1); + assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity)); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Get the LPTIMx CFGR value */ + tmpcfgr = hlptim->Instance->CFGR; + + /* Clear CKPOL bits */ + tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL); + + /* Set Input polarity */ + tmpcfgr |= hlptim->Init.UltraLowPowerClock.Polarity; + + /* Write to LPTIMx CFGR */ + hlptim->Instance->CFGR = tmpcfgr; + + /* Set ENC bit to enable the encoder interface */ + hlptim->Instance->CFGR |= LPTIM_CFGR_ENC; + + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Start timer in continuous mode */ + __HAL_LPTIM_START_CONTINUOUS(hlptim); + + /* Change the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stop the Encoder interface. + * @param hlptim LPTIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_ENCODER_INTERFACE_INSTANCE(hlptim->Instance)); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + /* Reset ENC bit to disable the encoder interface */ + hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC; + + /* Change the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Start the Encoder interface in interrupt mode. + * @param hlptim LPTIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim) +{ + uint32_t tmpcfgr; + + /* Check the parameters */ + assert_param(IS_LPTIM_ENCODER_INTERFACE_INSTANCE(hlptim->Instance)); + assert_param(hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC); + assert_param(hlptim->Init.Clock.Prescaler == LPTIM_PRESCALER_DIV1); + assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity)); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Configure edge sensitivity for encoder mode */ + /* Get the LPTIMx CFGR value */ + tmpcfgr = hlptim->Instance->CFGR; + + /* Clear CKPOL bits */ + tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL); + + /* Set Input polarity */ + tmpcfgr |= hlptim->Init.UltraLowPowerClock.Polarity; + + /* Write to LPTIMx CFGR */ + hlptim->Instance->CFGR = tmpcfgr; + + /* Set ENC bit to enable the encoder interface */ + hlptim->Instance->CFGR |= LPTIM_CFGR_ENC; + + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK); + + /* Enable "switch to up/down direction" interrupt */ + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_UP | LPTIM_IT_DOWN); + + /* Wait for the completion of the write operation to the LPTIM_DIER register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + + /* Start timer in continuous mode */ + __HAL_LPTIM_START_CONTINUOUS(hlptim); + + /* Change the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stop the Encoder interface in interrupt mode. + * @param hlptim LPTIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_ENCODER_INTERFACE_INSTANCE(hlptim->Instance)); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + /* Reset ENC bit to disable the encoder interface */ + hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC; + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK); + + /* Disable "switch to down/up direction" interrupt */ + __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_UP | LPTIM_IT_DOWN); + + /* Wait for the completion of the write operation to the LPTIM_DIER register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + /* Change the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Start the Timeout function. + * @note The first trigger event will start the timer, any successive + * trigger event will reset the counter and the timer restarts. + * @param hlptim LPTIM handle + * @param Timeout Specifies the TimeOut value to reset the counter. + * This parameter must be a value between 0x0000 and 0xFFFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Timeout) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); + assert_param(IS_LPTIM_PULSE(Timeout)); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Set TIMOUT bit to enable the timeout function */ + hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT; + + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP1OK); + + /* Load the Timeout value in the compare register */ + __HAL_LPTIM_COMPARE_SET(hlptim, LPTIM_CHANNEL_1, Timeout); + + /* Wait for the completion of the write operation to the LPTIM_CCR1 register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMP1OK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Start timer in continuous mode */ + __HAL_LPTIM_START_CONTINUOUS(hlptim); + + /* Change the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stop the Timeout function. + * @param hlptim LPTIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + /* Reset TIMOUT bit to enable the timeout function */ + hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT; + + /* Change the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Start the Timeout function in interrupt mode. + * @note The first trigger event will start the timer, any successive + * trigger event will reset the counter and the timer restarts. + * @param hlptim LPTIM handle + * @param Timeout Specifies the TimeOut value to reset the counter. + * This parameter must be a value between 0x0000 and 0xFFFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Timeout) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); + assert_param(IS_LPTIM_PULSE(Timeout)); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Set TIMOUT bit to enable the timeout function */ + hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT; + + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK); + + /* Enable Compare match CH1 interrupt */ + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CC1); + + /* Wait for the completion of the write operation to the LPTIM_DIER register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP1OK); + + /* Load the Timeout value in the compare register */ + __HAL_LPTIM_COMPARE_SET(hlptim, LPTIM_CHANNEL_1, Timeout); + + /* Wait for the completion of the write operation to the LPTIM_CCR1 register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMP1OK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Start timer in continuous mode */ + __HAL_LPTIM_START_CONTINUOUS(hlptim); + + /* Change the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stop the Timeout function in interrupt mode. + * @param hlptim LPTIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + /* Reset TIMOUT bit to enable the timeout function */ + hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT; + + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK); + + /* Disable Compare match CH1 interrupt */ + __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CC1); + + /* Wait for the completion of the write operation to the LPTIM_DIER register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + /* Change the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Start the Counter mode. + * @param hlptim LPTIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */ + if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) + && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) + { + /* Check if clock is prescaled */ + assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler)); + /* Set clock prescaler to 0 */ + hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC; + } + + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Start timer in continuous mode */ + __HAL_LPTIM_START_CONTINUOUS(hlptim); + + /* Change the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stop the Counter mode. + * @param hlptim LPTIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + /* Change the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Start the Counter mode in interrupt mode. + * @param hlptim LPTIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */ + if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) + && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) + { + /* Check if clock is prescaled */ + assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler)); + /* Set clock prescaler to 0 */ + hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC; + } + + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK); + + /* Enable interrupt */ + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK | LPTIM_IT_UPDATE); + + /* Wait for the completion of the write operation to the LPTIM_DIER register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Start timer in continuous mode */ + __HAL_LPTIM_START_CONTINUOUS(hlptim); + + /* Change the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stop the Counter mode in interrupt mode. + * @param hlptim LPTIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DIEROK); + + /* Disable interrupt */ + __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK | LPTIM_IT_ARRM | LPTIM_IT_REPOK | LPTIM_IT_UPDATE); + + /* Wait for the completion of the write operation to the LPTIM_DIER register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + /* Change the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the LPTIM Input Capture measurement. + * @param hlptim LPTIM Input Capture handle + * @param Channel LPTIM Channels to be enabled + * This parameter can be one of the following values: + * @arg LPTIM_CHANNEL_1: TIM Channel 1 selected + * @arg LPTIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_IC_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_INPUT_CAPTURE_INSTANCE(hlptim->Instance)); + assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel)); + + /* Check LPTIM channel state */ + if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Set the LPTIM channel state */ + LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY); + + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Start timer in continuous mode */ + __HAL_LPTIM_START_CONTINUOUS(hlptim); + + /* Enable capture */ + __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel); + + /* Change the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the LPTIM Input Capture measurement. + * @param hlptim LPTIM Input Capture handle + * @param Channel LPTIM Channels to be disabled + * This parameter can be one of the following values: + * @arg LPTIM_CHANNEL_1: TIM Channel 1 selected + * @arg LPTIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_IC_Stop(LPTIM_HandleTypeDef *hlptim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_INPUT_CAPTURE_INSTANCE(hlptim->Instance)); + assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel)); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Disable capture */ + __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel); + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + /* Set the LPTIM channel state */ + LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the LPTIM Input Capture measurement in interrupt mode. + * @param hlptim LPTIM Input Capture handle + * @param Channel LPTIM Channels to be enabled + * This parameter can be one of the following values: + * @arg LPTIM_CHANNEL_1: TIM Channel 1 selected + * @arg LPTIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_IC_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_INPUT_CAPTURE_INSTANCE(hlptim->Instance)); + assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel)); + + /* Check LPTIM channel state */ + if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Set the LPTIM channel state */ + LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY); + + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + switch (Channel) + { + case LPTIM_CHANNEL_1: + /* Enable Capture/Compare 1 interrupt */ + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CC1); + break; + case LPTIM_CHANNEL_2: + /* Disable Capture/Compare 2 interrupt */ + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CC2); + break; + default: + break; + } + + /* Wait for the completion of the write operation to the LPTIM_DIER register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Start timer in continuous mode */ + __HAL_LPTIM_START_CONTINUOUS(hlptim); + + /* Enable capture */ + __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the LPTIM Input Capture measurement in interrupt mode. + * @param hlptim LPTIM Input Capture handle + * @param Channel LPTIM Channels to be disabled + * This parameter can be one of the following values: + * @arg LPTIM_CHANNEL_1: TIM Channel 1 selected + * @arg LPTIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_IC_Stop_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_INPUT_CAPTURE_INSTANCE(hlptim->Instance)); + assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel)); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + switch (Channel) + { + case LPTIM_CHANNEL_1: + /* Disable Capture/Compare 1 interrupt */ + __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CC1); + break; + case LPTIM_CHANNEL_2: + /* Disable Capture/Compare 2 interrupt */ + __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CC2); + break; + default: + return HAL_ERROR; + break; + } + /* Disable capture */ + __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel); + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + /* Set the LPTIM channel state */ + LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the LPTIM Input Capture measurement in DMA mode. + * @param hlptim LPTIM Input Capture handle + * @param Channel LPTIM Channels to be enabled + * This parameter can be one of the following values: + * @arg LPTIM_CHANNEL_1: TIM Channel 1 selected + * @arg LPTIM_CHANNEL_2: TIM Channel 2 selected + * @param pData The destination Buffer address + * @param Length The length of data to be transferred from LPTIM peripheral to memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_IC_Start_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t Channel, uint32_t *pData, + uint32_t Length) +{ + DMA_HandleTypeDef *hdma; + + /* Check the parameters */ + assert_param(IS_LPTIM_DMA_INSTANCE(hlptim->Instance)); + assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel)); + + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + + /* Check LPTIM channel state */ + if (LPTIM_CHANNEL_STATE_GET(hlptim, Channel) != HAL_LPTIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + /* Set the LPTIM channel state */ + LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_BUSY); + + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + switch (Channel) + { + case LPTIM_CHANNEL_1: + /* Set the DMA capture callbacks */ + hlptim->hdma[LPTIM_DMA_ID_CC1]->XferCpltCallback = LPTIM_DMACaptureCplt; + hlptim->hdma[LPTIM_DMA_ID_CC1]->XferHalfCpltCallback = LPTIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + hlptim->hdma[LPTIM_DMA_ID_CC1]->XferErrorCallback = LPTIM_DMAError; + + /* Enable the DMA Channel */ + hdma = hlptim->hdma[LPTIM_DMA_ID_CC1]; + if (LPTIM_DMA_Start_IT(hdma, (uint32_t)&hlptim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable Capture/Compare 1 DMA request */ + __HAL_LPTIM_ENABLE_DMA(hlptim, LPTIM_DMA_CC1); + break; + + case LPTIM_CHANNEL_2: + /* Set the DMA capture callbacks */ + hlptim->hdma[LPTIM_DMA_ID_CC2]->XferCpltCallback = LPTIM_DMACaptureCplt; + hlptim->hdma[LPTIM_DMA_ID_CC2]->XferHalfCpltCallback = LPTIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + hlptim->hdma[LPTIM_DMA_ID_CC2]->XferErrorCallback = LPTIM_DMAError; + + /* Enable the DMA Channel */ + hdma = hlptim->hdma[LPTIM_DMA_ID_CC2]; + if (LPTIM_DMA_Start_IT(hdma, (uint32_t)&hlptim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable Capture/Compare 2 DMA request */ + __HAL_LPTIM_ENABLE_DMA(hlptim, LPTIM_DMA_CC2); + break; + + default: + break; + } + + /* Wait for the completion of the write operation to the LPTIM_DIER register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_DIEROK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Start timer in continuous mode */ + __HAL_LPTIM_START_CONTINUOUS(hlptim); + + /* Enable capture */ + __HAL_LPTIM_CAPTURE_COMPARE_ENABLE(hlptim, Channel); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the LPTIM Input Capture measurement in DMA mode. + * @param hlptim LPTIM Input Capture handle + * @param Channel LPTIM Channels to be disabled + * This parameter can be one of the following values: + * @arg LPTIM_CHANNEL_1: TIM Channel 1 selected + * @arg LPTIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_IC_Stop_DMA(LPTIM_HandleTypeDef *hlptim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_DMA_INSTANCE(hlptim->Instance)); + assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel)); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + + switch (Channel) + { + case LPTIM_CHANNEL_1: + /* Disable Capture/Compare 1 DMA request */ + __HAL_LPTIM_DISABLE_DMA(hlptim, LPTIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(hlptim->hdma[LPTIM_DMA_ID_CC1]); + break; + + case LPTIM_CHANNEL_2: + /* Disable Capture/Compare 2 DMA request */ + __HAL_LPTIM_DISABLE_DMA(hlptim, LPTIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(hlptim->hdma[LPTIM_DMA_ID_CC2]); + break; + default: + return HAL_ERROR; + break; + } + + /* Disable capture */ + __HAL_LPTIM_CAPTURE_COMPARE_DISABLE(hlptim, Channel); + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + /* Set the LPTIM channel state */ + LPTIM_CHANNEL_STATE_SET(hlptim, Channel, HAL_LPTIM_CHANNEL_STATE_READY); + + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} +/** + * @} + */ + +/** @defgroup LPTIM_Exported_Functions_Group3 LPTIM Read operation functions + * @brief Read operation functions. + * +@verbatim + ============================================================================== + ##### LPTIM Read operation functions ##### + ============================================================================== +[..] This section provides LPTIM Reading functions. + (+) Read the counter value. + (+) Read the period (Auto-reload) value. + (+) Read the pulse (Compare)value. +@endverbatim + * @{ + */ + +/** + * @brief Return the current counter value. + * @param hlptim LPTIM handle + * @retval Counter value. + */ +uint32_t HAL_LPTIM_ReadCounter(const LPTIM_HandleTypeDef *hlptim) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); + + return (hlptim->Instance->CNT); +} + +/** + * @brief Return the current Autoreload (Period) value. + * @param hlptim LPTIM handle + * @retval Autoreload value. + */ +uint32_t HAL_LPTIM_ReadAutoReload(const LPTIM_HandleTypeDef *hlptim) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); + + return (hlptim->Instance->ARR); +} + +/** + * @brief Return the current Compare (Pulse) value. + * @param hlptim LPTIM handle + * @param Channel LPTIM Channel to be selected + * This parameter can be one of the following values: + * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected + * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected + * @retval Compare value. + */ +uint32_t HAL_LPTIM_ReadCapturedValue(const LPTIM_HandleTypeDef *hlptim, uint32_t Channel) +{ + uint32_t tmpccr; + + /* Check the parameters */ + assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel)); + + switch (Channel) + { + case LPTIM_CHANNEL_1: + tmpccr = hlptim->Instance->CCR1; + break; + case LPTIM_CHANNEL_2: + tmpccr = hlptim->Instance->CCR2; + break; + default: + tmpccr = 0; + break; + } + return tmpccr; +} + +/** + * @brief LPTimer Input Capture Get Offset(in counter step unit) + * @note The real capture value corresponding to the input capture trigger can be calculated using + * the formula hereafter : Real capture value = captured(LPTIM_CCRx) - offset + * The Offset value is depending on the glitch filter value for the channel + * and the value of the prescaler for the kernel clock. + * Please check Errata Sheet V1_8 for more details under "variable latency + * on input capture channel" section. + * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains + * the configuration information for LPTIM module. + * @param Channel This parameter can be one of the following values: + * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected + * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected + * @retval The offset value + */ +uint8_t HAL_LPTIM_IC_GetOffset(const LPTIM_HandleTypeDef *hlptim, uint32_t Channel) +{ + + uint8_t offset ; + uint32_t prescaler; + uint32_t filter ; + + /* Get prescaler value */ + prescaler = LL_LPTIM_GetPrescaler(hlptim->Instance); + + /* Get filter value */ + filter = LL_LPTIM_IC_GetFilter(hlptim->Instance, Channel); + + /* Get offset value */ + offset = LL_LPTIM_IC_GET_OFFSET(prescaler, filter); + + /* return offset value */ + return offset; +} + +/** + * @} + */ +/** @defgroup LPTIM_Exported_Functions_Group5 LPTIM Config function + * @brief Config channel + * +@verbatim + ============================================================================== + ##### LPTIM Config function ##### + ============================================================================== +[..] This section provides LPTIM Config function. + (+) Configure channel: Output Compare mode, Period, Polarity. +@endverbatim + * @{ + */ + +/** + * @brief + * @param hlptim LPTIM handle + * @param sConfig The output configuration structure + * @param Channel LPTIM Channel to be configured + * This parameter can be one of the following values: + * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected + * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected + * @note Successive calls to HAL_LPTIM_OC_ConfigChannel can only be performed + * after a delay that must be greater or equal than the value of + * (PRESC x 3) kernel clock cycles, PRESC[2:0] being the clock decimal + * division factor (1, 2, 4, ..., 128). Any successive call violating + * this delay, leads to unpredictable results. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_OC_ConfigChannel(LPTIM_HandleTypeDef *hlptim, const LPTIM_OC_ConfigTypeDef *sConfig, + uint32_t Channel) +{ + HAL_StatusTypeDef status; + /* Check the parameters */ + assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel)); + assert_param(IS_LPTIM_OC_POLARITY(sConfig->OCPolarity)); + assert_param(IS_LPTIM_PULSE(sConfig->Pulse)); + + hlptim->State = HAL_LPTIM_STATE_BUSY; + + switch (Channel) + { + case LPTIM_CHANNEL_1: + { + /* Check the parameters */ + assert_param(IS_LPTIM_CC1_INSTANCE(hlptim->Instance)); + + /* Configure the LPTIM Channel 1 in Output Compare */ + status = LPTIM_OC1_SetConfig(hlptim, sConfig); + if (status != HAL_OK) + { + return status; + } + break; + } + case LPTIM_CHANNEL_2: + { + /* Check the parameters */ + assert_param(IS_LPTIM_CC2_INSTANCE(hlptim->Instance)); + + /* Configure the LPTIM Channel 2 in Output Compare */ + status = LPTIM_OC2_SetConfig(hlptim, sConfig); + if (status != HAL_OK) + { + return status; + } + break; + } + default: + break; + } + + /* Change the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief + * @param hlptim LPTIM handle + * @param sConfig The input configuration structure + * @param Channel LPTIM Channel to be configured + * This parameter can be one of the following values: + * @arg LPTIM_CHANNEL_1: LPTIM Channel 1 selected + * @arg LPTIM_CHANNEL_2: LPTIM Channel 2 selected + * @note Successive calls to HAL_LPTIM_IC_ConfigChannel can only be performed + * after a delay that must be greater or equal than the value of + * (PRESC x 3) kernel clock cycles, PRESC[2:0] being the clock decimal + * division factor (1, 2, 4, ..., 128). Any successive call violating + * this delay, leads to unpredictable results. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LPTIM_IC_ConfigChannel(LPTIM_HandleTypeDef *hlptim, const LPTIM_IC_ConfigTypeDef *sConfig, + uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_CCX_INSTANCE(hlptim->Instance, Channel)); + assert_param(IS_LPTIM_IC_PRESCALER(sConfig->ICPrescaler)); + assert_param(IS_LPTIM_IC_POLARITY(sConfig->ICPolarity)); + assert_param(IS_LPTIM_IC_FILTER(sConfig->ICFilter)); + + hlptim->State = HAL_LPTIM_STATE_BUSY; + + switch (Channel) + { + case LPTIM_CHANNEL_1: + { + /* Check the parameters */ + assert_param(IS_LPTIM_CC1_INSTANCE(hlptim->Instance)); + assert_param(IS_LPTIM_IC1_SOURCE(hlptim->Instance, sConfig->ICInputSource)); + + /* Configure the LPTIM Channel 1 in Input Capture */ + LPTIM_IC1_SetConfig(hlptim, sConfig); + break; + } + case LPTIM_CHANNEL_2: + { + /* Check the parameters */ + assert_param(IS_LPTIM_CC2_INSTANCE(hlptim->Instance)); + assert_param(IS_LPTIM_IC2_SOURCE(hlptim->Instance, sConfig->ICInputSource)); + + /* Configure the LPTIM Channel 2 in Input Capture */ + LPTIM_IC2_SetConfig(hlptim, sConfig); + break; + } + default: + break; + } + + /* Change the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_READY; + /* Return function status */ + return HAL_OK; +} +/** + * @} + */ + +/** @defgroup LPTIM_Exported_Functions_Group4 LPTIM IRQ handler and callbacks + * @brief LPTIM IRQ handler. + * +@verbatim + ============================================================================== + ##### LPTIM IRQ handler and callbacks ##### + ============================================================================== +[..] This section provides LPTIM IRQ handler and callback functions called within + the IRQ handler: + (+) LPTIM interrupt request handler + (+) Compare match Callback + (+) Auto-reload match Callback + (+) External trigger event detection Callback + (+) Compare register write complete Callback + (+) Auto-reload register write complete Callback + (+) Up-counting direction change Callback + (+) Down-counting direction change Callback + +@endverbatim + * @{ + */ + +/** + * @brief Handle LPTIM interrupt request. + * @param hlptim LPTIM handle + * @retval None + */ +void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim) +{ + /* Capture Compare 1 interrupt */ + if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CC1) != RESET) + { + if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_FLAG_CC1) != RESET) + { + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CC1); + hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_1; + + /* Input capture event */ + if ((hlptim->Instance->CCMR1 & LPTIM_CCMR1_CC1SEL) != 0x00U) + { +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->IC_CaptureCallback(hlptim); +#else + HAL_LPTIM_IC_CaptureCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->CompareMatchCallback(hlptim); +#else + HAL_LPTIM_CompareMatchCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + } + hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED; + } + } + + /* Capture Compare 2 interrupt */ + if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CC2) != RESET) + { + if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_FLAG_CC2) != RESET) + { + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CC2); + hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_2; + + /* Input capture event */ + if ((hlptim->Instance->CCMR1 & LPTIM_CCMR1_CC2SEL) != 0x00U) + { +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->IC_CaptureCallback(hlptim); +#else + HAL_LPTIM_IC_CaptureCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->CompareMatchCallback(hlptim); +#else + HAL_LPTIM_CompareMatchCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + } + hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED; + } + } + + /* Over Capture 1 interrupt */ + if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CC1O) != RESET) + { + if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_FLAG_CC1O) != RESET) + { + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CC1O); + hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_1; + + /* Over capture event */ +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->IC_OverCaptureCallback(hlptim); +#else + HAL_LPTIM_IC_OverCaptureCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED; + } + } + + /* Over Capture 2 interrupt */ + if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CC2O) != RESET) + { + if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_FLAG_CC2O) != RESET) + { + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CC2O); + hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_2; + + /* Over capture event */ +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->IC_OverCaptureCallback(hlptim); +#else + HAL_LPTIM_IC_OverCaptureCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED; + } + } + + /* Autoreload match interrupt */ + if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARRM) != RESET) + { + if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARRM) != RESET) + { + /* Clear Autoreload match flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARRM); + + /* Autoreload match Callback */ +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->AutoReloadMatchCallback(hlptim); +#else + HAL_LPTIM_AutoReloadMatchCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + } + } + + /* Trigger detected interrupt */ + if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_EXTTRIG) != RESET) + { + if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_EXTTRIG) != RESET) + { + /* Clear Trigger detected flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_EXTTRIG); + + /* Trigger detected callback */ +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->TriggerCallback(hlptim); +#else + HAL_LPTIM_TriggerCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + } + } + + /* Compare write interrupt */ + if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMP1OK) != RESET) + { + if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMP1OK) != RESET) + { + /* Clear Compare write flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP1OK); + hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_1; + /* Compare write Callback */ +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->CompareWriteCallback(hlptim); +#else + HAL_LPTIM_CompareWriteCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + } + } + + /* Compare write interrupt */ + if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMP2OK) != RESET) + { + if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMP2OK) != RESET) + { + /* Clear Compare write flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP2OK); + hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_2; + /* Compare write Callback */ +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->CompareWriteCallback(hlptim); +#else + HAL_LPTIM_CompareWriteCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + } + } + + /* Autoreload write interrupt */ + if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARROK) != RESET) + { + if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARROK) != RESET) + { + /* Clear Autoreload write flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); + + /* Autoreload write Callback */ +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->AutoReloadWriteCallback(hlptim); +#else + HAL_LPTIM_AutoReloadWriteCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + } + } + + /* Direction counter changed from Down to Up interrupt */ + if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_UP) != RESET) + { + if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_UP) != RESET) + { + /* Clear Direction counter changed from Down to Up flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_UP); + + /* Direction counter changed from Down to Up Callback */ +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->DirectionUpCallback(hlptim); +#else + HAL_LPTIM_DirectionUpCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + } + } + + /* Direction counter changed from Up to Down interrupt */ + if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_DOWN) != RESET) + { + if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_DOWN) != RESET) + { + /* Clear Direction counter changed from Up to Down flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DOWN); + + /* Direction counter changed from Up to Down Callback */ +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->DirectionDownCallback(hlptim); +#else + HAL_LPTIM_DirectionDownCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + } + } + + /* Repetition counter underflowed (or contains zero) and the LPTIM counter + overflowed */ + if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_UPDATE) != RESET) + { + if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_UPDATE) != RESET) + { + /* Clear update event flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_UPDATE); + + /* Update event Callback */ +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->UpdateEventCallback(hlptim); +#else + HAL_LPTIM_UpdateEventCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + } + } + + /* Successful APB bus write to repetition counter register */ + if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_REPOK) != RESET) + { + if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_REPOK) != RESET) + { + /* Clear successful APB bus write to repetition counter flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_REPOK); + + /* Successful APB bus write to repetition counter Callback */ +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->RepCounterWriteCallback(hlptim); +#else + HAL_LPTIM_RepCounterWriteCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + } + } +} + +/** + * @brief Compare match callback in non-blocking mode. + * @param hlptim LPTIM handle + * @retval None + */ +__weak void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hlptim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LPTIM_CompareMatchCallback could be implemented in the user file + */ +} + +/** + * @brief Autoreload match callback in non-blocking mode. + * @param hlptim LPTIM handle + * @retval None + */ +__weak void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hlptim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LPTIM_AutoReloadMatchCallback could be implemented in the user file + */ +} + +/** + * @brief Trigger detected callback in non-blocking mode. + * @param hlptim LPTIM handle + * @retval None + */ +__weak void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hlptim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LPTIM_TriggerCallback could be implemented in the user file + */ +} + +/** + * @brief Compare write callback in non-blocking mode. + * @param hlptim LPTIM handle + * @retval None + */ +__weak void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hlptim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LPTIM_CompareWriteCallback could be implemented in the user file + */ +} + +/** + * @brief Autoreload write callback in non-blocking mode. + * @param hlptim LPTIM handle + * @retval None + */ +__weak void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hlptim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LPTIM_AutoReloadWriteCallback could be implemented in the user file + */ +} + +/** + * @brief Direction counter changed from Down to Up callback in non-blocking mode. + * @param hlptim LPTIM handle + * @retval None + */ +__weak void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hlptim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LPTIM_DirectionUpCallback could be implemented in the user file + */ +} + +/** + * @brief Direction counter changed from Up to Down callback in non-blocking mode. + * @param hlptim LPTIM handle + * @retval None + */ +__weak void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hlptim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LPTIM_DirectionDownCallback could be implemented in the user file + */ +} + +/** + * @brief Repetition counter underflowed (or contains zero) and LPTIM counter overflowed callback in non-blocking mode. + * @param hlptim LPTIM handle + * @retval None + */ +__weak void HAL_LPTIM_UpdateEventCallback(LPTIM_HandleTypeDef *hlptim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hlptim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LPTIM_UpdateEventCallback could be implemented in the user file + */ +} + +/** + * @brief Successful APB bus write to repetition counter register callback in non-blocking mode. + * @param hlptim LPTIM handle + * @retval None + */ +__weak void HAL_LPTIM_RepCounterWriteCallback(LPTIM_HandleTypeDef *hlptim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hlptim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LPTIM_RepCounterWriteCallback could be implemented in the user file + */ +} + +/** + * @brief Input Capture callback in non-blocking mode + * @param hlptim LPTIM handle + * @retval None + */ +__weak void HAL_LPTIM_IC_CaptureCallback(LPTIM_HandleTypeDef *hlptim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hlptim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LPTIM_IC_CaptureCallback could be implemented in the user file + */ +} + +/** + * @brief Over Capture callback in non-blocking mode + * @param hlptim LPTIM handle + * @retval None + */ +__weak void HAL_LPTIM_IC_OverCaptureCallback(LPTIM_HandleTypeDef *hlptim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hlptim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LPTIM_IC_OverCaptureCallback could be implemented in the user file + */ +} + +/** + * @brief Input Capture half complete callback in non-blocking mode + * @param hlptim LPTIM IC handle + * @retval None + */ +__weak void HAL_LPTIM_IC_CaptureHalfCpltCallback(LPTIM_HandleTypeDef *hlptim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hlptim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LPTIM_IC_CaptureHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Update event half complete callback in non-blocking mode + * @param hlptim LPTIM handle + * @retval None + */ +__weak void HAL_LPTIM_UpdateEventHalfCpltCallback(LPTIM_HandleTypeDef *hlptim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hlptim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LPTIM_UpdateEventHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Error callback in non-blocking mode + * @param hlptim LPTIM handle + * @retval None + */ +__weak void HAL_LPTIM_ErrorCallback(LPTIM_HandleTypeDef *hlptim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hlptim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_LPTIM_ErrorCallback could be implemented in the user file + */ +} + + +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User LPTIM callback to be used instead of the weak predefined callback + * @param hlptim LPTIM handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_LPTIM_MSPINIT_CB_ID LPTIM Base Msp Init Callback ID + * @arg @ref HAL_LPTIM_MSPDEINIT_CB_ID LPTIM Base Msp DeInit Callback ID + * @arg @ref HAL_LPTIM_COMPARE_MATCH_CB_ID Compare match Callback ID + * @arg @ref HAL_LPTIM_AUTORELOAD_MATCH_CB_ID Auto-reload match Callback ID + * @arg @ref HAL_LPTIM_TRIGGER_CB_ID External trigger event detection Callback ID + * @arg @ref HAL_LPTIM_COMPARE_WRITE_CB_ID Compare register write complete Callback ID + * @arg @ref HAL_LPTIM_AUTORELOAD_WRITE_CB_ID Auto-reload register write complete Callback ID + * @arg @ref HAL_LPTIM_DIRECTION_UP_CB_ID Up-counting direction change Callback ID + * @arg @ref HAL_LPTIM_DIRECTION_DOWN_CB_ID Down-counting direction change Callback ID + * @arg @ref HAL_LPTIM_UPDATE_EVENT_CB_ID Update event detection Callback ID + * @arg @ref HAL_LPTIM_REP_COUNTER_WRITE_CB_ID Repetition counter register write complete Callback ID + * @arg @ref HAL_LPTIM_UPDATE_EVENT_HALF_CB_ID Update event Half detection Callback ID + * @arg @ref HAL_LPTIM_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_LPTIM_IC_CAPTURE_CB_ID Input Capture Callback ID + * @arg @ref HAL_LPTIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID + * @arg @ref HAL_LPTIM_OVER_CAPTURE_CB_ID Over Capture Callback ID + * @param pCallback pointer to the callback function + * @retval status + */ +HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *hlptim, + HAL_LPTIM_CallbackIDTypeDef CallbackID, + pLPTIM_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + return HAL_ERROR; + } + + if (hlptim->State == HAL_LPTIM_STATE_READY) + { + switch (CallbackID) + { + case HAL_LPTIM_MSPINIT_CB_ID : + hlptim->MspInitCallback = pCallback; + break; + + case HAL_LPTIM_MSPDEINIT_CB_ID : + hlptim->MspDeInitCallback = pCallback; + break; + + case HAL_LPTIM_COMPARE_MATCH_CB_ID : + hlptim->CompareMatchCallback = pCallback; + break; + + case HAL_LPTIM_AUTORELOAD_MATCH_CB_ID : + hlptim->AutoReloadMatchCallback = pCallback; + break; + + case HAL_LPTIM_TRIGGER_CB_ID : + hlptim->TriggerCallback = pCallback; + break; + + case HAL_LPTIM_COMPARE_WRITE_CB_ID : + hlptim->CompareWriteCallback = pCallback; + break; + + case HAL_LPTIM_AUTORELOAD_WRITE_CB_ID : + hlptim->AutoReloadWriteCallback = pCallback; + break; + + case HAL_LPTIM_DIRECTION_UP_CB_ID : + hlptim->DirectionUpCallback = pCallback; + break; + + case HAL_LPTIM_DIRECTION_DOWN_CB_ID : + hlptim->DirectionDownCallback = pCallback; + break; + + case HAL_LPTIM_UPDATE_EVENT_CB_ID : + hlptim->UpdateEventCallback = pCallback; + break; + + case HAL_LPTIM_REP_COUNTER_WRITE_CB_ID : + hlptim->RepCounterWriteCallback = pCallback; + break; + + case HAL_LPTIM_UPDATE_EVENT_HALF_CB_ID : + hlptim->UpdateEventHalfCpltCallback = pCallback; + break; + + case HAL_LPTIM_ERROR_CB_ID : + hlptim->ErrorCallback = pCallback; + break; + + case HAL_LPTIM_IC_CAPTURE_CB_ID : + hlptim->IC_CaptureCallback = pCallback; + break; + + case HAL_LPTIM_IC_CAPTURE_HALF_CB_ID : + hlptim->IC_CaptureHalfCpltCallback = pCallback; + break; + + case HAL_LPTIM_OVER_CAPTURE_CB_ID : + hlptim->IC_OverCaptureCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hlptim->State == HAL_LPTIM_STATE_RESET) + { + switch (CallbackID) + { + case HAL_LPTIM_MSPINIT_CB_ID : + hlptim->MspInitCallback = pCallback; + break; + + case HAL_LPTIM_MSPDEINIT_CB_ID : + hlptim->MspDeInitCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister a LPTIM callback + * LLPTIM callback is redirected to the weak predefined callback + * @param hlptim LPTIM handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_LPTIM_MSPINIT_CB_ID LPTIM Base Msp Init Callback ID + * @arg @ref HAL_LPTIM_MSPDEINIT_CB_ID LPTIM Base Msp DeInit Callback ID + * @arg @ref HAL_LPTIM_COMPARE_MATCH_CB_ID Compare match Callback ID + * @arg @ref HAL_LPTIM_AUTORELOAD_MATCH_CB_ID Auto-reload match Callback ID + * @arg @ref HAL_LPTIM_TRIGGER_CB_ID External trigger event detection Callback ID + * @arg @ref HAL_LPTIM_COMPARE_WRITE_CB_ID Compare register write complete Callback ID + * @arg @ref HAL_LPTIM_AUTORELOAD_WRITE_CB_ID Auto-reload register write complete Callback ID + * @arg @ref HAL_LPTIM_DIRECTION_UP_CB_ID Up-counting direction change Callback ID + * @arg @ref HAL_LPTIM_DIRECTION_DOWN_CB_ID Down-counting direction change Callback ID + * @arg @ref HAL_LPTIM_UPDATE_EVENT_CB_ID Update event detection Callback ID + * @arg @ref HAL_LPTIM_REP_COUNTER_WRITE_CB_ID Repetition counter register write complete Callback ID + * @arg @ref HAL_LPTIM_UPDATE_EVENT_HALF_CB_ID Update event Half detection Callback ID + * @arg @ref HAL_LPTIM_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_LPTIM_IC_CAPTURE_CB_ID Input Capture Callback ID + * @arg @ref HAL_LPTIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID + * @arg @ref HAL_LPTIM_OVER_CAPTURE_CB_ID Over Capture Callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlptim, + HAL_LPTIM_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hlptim->State == HAL_LPTIM_STATE_READY) + { + switch (CallbackID) + { + case HAL_LPTIM_MSPINIT_CB_ID : + /* Legacy weak MspInit Callback */ + hlptim->MspInitCallback = HAL_LPTIM_MspInit; + break; + + case HAL_LPTIM_MSPDEINIT_CB_ID : + /* Legacy weak Msp DeInit Callback */ + hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit; + break; + + case HAL_LPTIM_COMPARE_MATCH_CB_ID : + /* Legacy weak Compare match Callback */ + hlptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback; + break; + + case HAL_LPTIM_AUTORELOAD_MATCH_CB_ID : + /* Legacy weak Auto-reload match Callback */ + hlptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback; + break; + + case HAL_LPTIM_TRIGGER_CB_ID : + /* Legacy weak External trigger event detection Callback */ + hlptim->TriggerCallback = HAL_LPTIM_TriggerCallback; + break; + + case HAL_LPTIM_COMPARE_WRITE_CB_ID : + /* Legacy weak Compare register write complete Callback */ + hlptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback; + break; + + case HAL_LPTIM_AUTORELOAD_WRITE_CB_ID : + /* Legacy weak Auto-reload register write complete Callback */ + hlptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback; + break; + + case HAL_LPTIM_DIRECTION_UP_CB_ID : + /* Legacy weak Up-counting direction change Callback */ + hlptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback; + break; + + case HAL_LPTIM_DIRECTION_DOWN_CB_ID : + /* Legacy weak Down-counting direction change Callback */ + hlptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback; + break; + + case HAL_LPTIM_UPDATE_EVENT_CB_ID : + /* Legacy weak Update event detection Callback */ + hlptim->UpdateEventCallback = HAL_LPTIM_UpdateEventCallback; + break; + + case HAL_LPTIM_REP_COUNTER_WRITE_CB_ID : + /* Legacy weak Repetition counter register write complete Callback */ + hlptim->RepCounterWriteCallback = HAL_LPTIM_RepCounterWriteCallback; + break; + + case HAL_LPTIM_UPDATE_EVENT_HALF_CB_ID : + /* Legacy weak Update event half complete detection Callback */ + hlptim->UpdateEventHalfCpltCallback = HAL_LPTIM_UpdateEventHalfCpltCallback; + break; + + case HAL_LPTIM_ERROR_CB_ID : + /* Legacy weak error Callback */ + hlptim->ErrorCallback = HAL_LPTIM_ErrorCallback; + break; + + case HAL_LPTIM_IC_CAPTURE_CB_ID : + /* Legacy weak IC Capture Callback */ + hlptim->IC_CaptureCallback = HAL_LPTIM_IC_CaptureCallback; + break; + + case HAL_LPTIM_IC_CAPTURE_HALF_CB_ID : + /* Legacy weak IC Capture half complete Callback */ + hlptim->IC_CaptureHalfCpltCallback = HAL_LPTIM_IC_CaptureHalfCpltCallback; + break; + + case HAL_LPTIM_OVER_CAPTURE_CB_ID : + /* Legacy weak IC over capture Callback */ + hlptim->IC_OverCaptureCallback = HAL_LPTIM_IC_OverCaptureCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hlptim->State == HAL_LPTIM_STATE_RESET) + { + switch (CallbackID) + { + case HAL_LPTIM_MSPINIT_CB_ID : + /* Legacy weak MspInit Callback */ + hlptim->MspInitCallback = HAL_LPTIM_MspInit; + break; + + case HAL_LPTIM_MSPDEINIT_CB_ID : + /* Legacy weak Msp DeInit Callback */ + hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup LPTIM_Group5 Peripheral State functions + * @brief Peripheral State functions. + * +@verbatim + ============================================================================== + ##### Peripheral State functions ##### + ============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Return the LPTIM handle state. + * @param hlptim LPTIM handle + * @retval HAL state + */ +HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(const LPTIM_HandleTypeDef *hlptim) +{ + /* Return LPTIM handle state */ + return hlptim->State; +} + +/** + * @} + */ + + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup LPTIM_Private_Functions LPTIM Private Functions + * @{ + */ +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) +/** + * @brief Reset interrupt callbacks to the legacy weak callbacks. + * @param lptim pointer to a LPTIM_HandleTypeDef structure that contains + * the configuration information for LPTIM module. + * @retval None + */ +static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim) +{ + /* Reset the LPTIM callback to the legacy weak callbacks */ + lptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback; + lptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback; + lptim->TriggerCallback = HAL_LPTIM_TriggerCallback; + lptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback; + lptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback; + lptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback; + lptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback; + lptim->UpdateEventCallback = HAL_LPTIM_UpdateEventCallback; + lptim->RepCounterWriteCallback = HAL_LPTIM_RepCounterWriteCallback; + lptim->UpdateEventHalfCpltCallback = HAL_LPTIM_UpdateEventHalfCpltCallback; + lptim->IC_CaptureCallback = HAL_LPTIM_IC_CaptureCallback; + lptim->IC_CaptureHalfCpltCallback = HAL_LPTIM_IC_CaptureHalfCpltCallback; + lptim->IC_OverCaptureCallback = HAL_LPTIM_IC_OverCaptureCallback; + lptim->ErrorCallback = HAL_LPTIM_ErrorCallback; +} +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + +/** + * @brief LPTimer Wait for flag set + * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains + * the configuration information for LPTIM module. + * @param flag The lptim flag + * @retval HAL status + */ +static HAL_StatusTypeDef LPTIM_WaitForFlag(const LPTIM_HandleTypeDef *hlptim, uint32_t flag) +{ + HAL_StatusTypeDef result = HAL_OK; + uint32_t count = TIMEOUT * (SystemCoreClock / 20UL / 1000UL); + do + { + count--; + if (count == 0UL) + { + result = HAL_TIMEOUT; + } + } while ((!(__HAL_LPTIM_GET_FLAG((hlptim), (flag)))) && (count != 0UL)); + + return result; +} + +/** + * @brief LPTIM DMA error callback + * @param hdma pointer to DMA handle. + * @retval None + */ +void LPTIM_DMAError(DMA_HandleTypeDef *hdma) +{ + LPTIM_HandleTypeDef *hlptim = (LPTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + hlptim->State = HAL_LPTIM_STATE_READY; + +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->ErrorCallback(hlptim); +#else + HAL_LPTIM_ErrorCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ +} + +/** + * @brief LPTIM DMA Capture complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void LPTIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) +{ + LPTIM_HandleTypeDef *hlptim = (LPTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + hlptim->State = HAL_LPTIM_STATE_READY; + + if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC1]) + { + hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_1; + } + else if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC2]) + { + hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_2; + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->IC_CaptureCallback(hlptim); +#else + HAL_LPTIM_IC_CaptureCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + + hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief LPTIM DMA Capture half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void LPTIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma) +{ + LPTIM_HandleTypeDef *hlptim = (LPTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + hlptim->State = HAL_LPTIM_STATE_READY; + + if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC1]) + { + hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_1; + } + else if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC2]) + { + hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_2; + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->IC_CaptureHalfCpltCallback(hlptim); +#else + HAL_LPTIM_IC_CaptureHalfCpltCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + + hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief LPTIM DMA Update event complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void LPTIM_DMAUpdateEventCplt(DMA_HandleTypeDef *hdma) +{ + LPTIM_HandleTypeDef *hlptim = (LPTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + hlptim->State = HAL_LPTIM_STATE_READY; + + if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC1]) + { + hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_1; + } + else if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC2]) + { + hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_2; + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->UpdateEventCallback(hlptim); +#else + HAL_LPTIM_UpdateEventCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + + hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief LPTIM DMA Capture half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void LPTIM_DMAUpdateEventHalfCplt(DMA_HandleTypeDef *hdma) +{ + LPTIM_HandleTypeDef *hlptim = (LPTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + hlptim->State = HAL_LPTIM_STATE_READY; + + if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC1]) + { + hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_1; + } + else if (hdma == hlptim->hdma[LPTIM_DMA_ID_CC2]) + { + hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_2; + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) + hlptim->UpdateEventHalfCpltCallback(hlptim); +#else + HAL_LPTIM_UpdateEventHalfCpltCallback(hlptim); +#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ + + hlptim->Channel = HAL_LPTIM_ACTIVE_CHANNEL_CLEARED; +} +/** + * @brief LPTimer Output Compare 1 configuration + * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains + * the configuration information for LPTIM module. + * @param sConfig The output configuration structure + * @retval None + */ +static HAL_StatusTypeDef LPTIM_OC1_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_OC_ConfigTypeDef *sConfig) +{ + uint32_t tmpccmr1; + + tmpccmr1 = hlptim->Instance->CCMR1; + tmpccmr1 &= ~(LPTIM_CCMR1_CC1P_Msk | LPTIM_CCMR1_CC1SEL_Msk); + + tmpccmr1 |= sConfig->OCPolarity << LPTIM_CCMR1_CC1P_Pos; + + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP1OK); + + /* Write to CCR1 register */ + __HAL_LPTIM_COMPARE_SET(hlptim, LPTIM_CHANNEL_1, sConfig->Pulse); + + /* Wait for the completion of the write operation to the LPTIM_CCR1 register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMP1OK) == HAL_TIMEOUT) + { + return HAL_TIMEOUT; + } + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + /* Write to CCMR1 register */ + hlptim->Instance->CCMR1 = tmpccmr1; + + return HAL_OK; +} + +/** + * @brief LPTimer Output Compare 2 configuration + * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains + * the configuration information for LPTIM module. + * @param sConfig The output configuration structure + * @retval None + */ +static HAL_StatusTypeDef LPTIM_OC2_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_OC_ConfigTypeDef *sConfig) +{ + uint32_t tmpccmr1; + + tmpccmr1 = hlptim->Instance->CCMR1; + tmpccmr1 &= ~(LPTIM_CCMR1_CC2P_Msk | LPTIM_CCMR1_CC2SEL_Msk); + tmpccmr1 |= sConfig->OCPolarity << LPTIM_CCMR1_CC2P_Pos; + + /* Enable the Peripheral */ + __HAL_LPTIM_ENABLE(hlptim); + + /* Clear flag */ + __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMP2OK); + + /* Write to CCR2 register */ + __HAL_LPTIM_COMPARE_SET(hlptim, LPTIM_CHANNEL_2, sConfig->Pulse); + + /* Wait for the completion of the write operation to the LPTIM_CCR2 register */ + if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMP2OK) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Disable the Peripheral */ + __HAL_LPTIM_DISABLE(hlptim); + + /* Write to CCMR1 register */ + hlptim->Instance->CCMR1 = tmpccmr1; + + return HAL_OK; +} + +/** + * @brief LPTimer Input Capture 1 configuration + * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains + * the configuration information for LPTIM module. + * @param sConfig The input configuration structure + * @retval None + */ +static void LPTIM_IC1_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_IC_ConfigTypeDef *sConfig) +{ + uint32_t tmpccmr1; + uint32_t tmpcfgr2; + + tmpccmr1 = hlptim->Instance->CCMR1; + tmpccmr1 &= ~(LPTIM_CCMR1_IC1PSC_Msk | LPTIM_CCMR1_CC1P_Msk | LPTIM_CCMR1_IC1F_Msk); + tmpccmr1 |= sConfig->ICPrescaler | + sConfig->ICPolarity | + sConfig->ICFilter | + LPTIM_CCMR1_CC1SEL; + + tmpcfgr2 = hlptim->Instance->CFGR2; + tmpcfgr2 &= ~(LPTIM_CFGR2_IC1SEL_Msk); + tmpcfgr2 |= sConfig->ICInputSource; + + /* Write to CCMR1 register */ + hlptim->Instance->CCMR1 = tmpccmr1; + + /* Write to CFGR2 register */ + hlptim->Instance->CFGR2 = tmpcfgr2; +} + +/** + * @brief LPTimer Input Capture 2 configuration + * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains + * the configuration information for LPTIM module. + * @param sConfig The input configuration structure + * @retval None + */ +static void LPTIM_IC2_SetConfig(LPTIM_HandleTypeDef *hlptim, const LPTIM_IC_ConfigTypeDef *sConfig) +{ + uint32_t tmpccmr1; + uint32_t tmpcfgr2; + + tmpccmr1 = hlptim->Instance->CCMR1; + tmpccmr1 &= ~(LPTIM_CCMR1_IC2PSC_Msk | LPTIM_CCMR1_CC2P_Msk | LPTIM_CCMR1_IC2F_Msk); + tmpccmr1 |= (sConfig->ICPrescaler << (LPTIM_CCMR1_IC2PSC_Pos - LPTIM_CCMR1_IC1PSC_Pos)) | + (sConfig->ICPolarity << (LPTIM_CCMR1_CC2P_Pos - LPTIM_CCMR1_CC1P_Pos)) | + (sConfig->ICFilter << (LPTIM_CCMR1_IC2F_Pos - LPTIM_CCMR1_IC1F_Pos)) | + LPTIM_CCMR1_CC2SEL; + + tmpcfgr2 = hlptim->Instance->CFGR2; + tmpcfgr2 &= ~(LPTIM_CFGR2_IC2SEL_Msk); + tmpcfgr2 |= sConfig->ICInputSource; + + /* Write to CCMR1 register */ + hlptim->Instance->CCMR1 = tmpccmr1; + + /* Write to CFGR2 register */ + hlptim->Instance->CFGR2 = tmpcfgr2; +} + +/** + * @brief Start the DMA data transfer. + * @param hdma DMA handle + * @param src The source memory Buffer address. + * @param dst The destination memory Buffer address. + * @param length The size of a source block transfer in byte. + * @retval HAL status + */ +HAL_StatusTypeDef LPTIM_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t src, uint32_t dst, + uint32_t length) +{ + HAL_StatusTypeDef status; + + /* Enable the DMA channel */ + if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if ((hdma->LinkedListQueue != 0U) && (hdma->LinkedListQueue->Head != 0U)) + { + /* Enable the DMA channel */ + hdma->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = length; + hdma->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)src; + hdma->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)dst; + + status = HAL_DMAEx_List_Start_IT(hdma); + } + else + { + status = HAL_ERROR; + } + } + else + { + status = HAL_DMA_Start_IT(hdma, src, dst, length); + } + + return status; +} +/** + * @} + */ +#endif /* LPTIM1 || LPTIM2 */ + +#endif /* HAL_LPTIM_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_msp_template.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_msp_template.c new file mode 100644 index 0000000000..f8feb92843 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_msp_template.c @@ -0,0 +1,100 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_msp_template.c + * @author MCD Application Team + * @brief HAL MSP module. + * This file template is located in the HAL folder and should be copied + * to the user folder. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @defgroup HAL_MSP HAL MSP module driver + * @brief HAL MSP module. + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup HAL_MSP_Private_Functions HAL MSP Private Functions + * @{ + */ + +/** + * @brief Initializes the Global MSP. + * @retval None + */ +void HAL_MspInit(void) +{ + +} + +/** + * @brief DeInitializes the Global MSP. + * @retval None + */ +void HAL_MspDeInit(void) +{ + +} + +/** + * @brief Initialize the PPP MSP. + * @retval None + */ +/* +void HAL_PPP_MspInit(void) +{ +} +*/ + +/** + * @brief DeInitialize the PPP MSP. + * @retval None + */ +/* +void HAL_PPP_MspDeInit(void) +{ +} +*/ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_pka.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_pka.c new file mode 100644 index 0000000000..961b4b300b --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_pka.c @@ -0,0 +1,3042 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_pka.c + * @author MCD Application Team + * @brief PKA HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of public key accelerator(PKA): + * + Initialization and de-initialization functions + * + Start an operation + * + Retrieve the operation result + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The PKA HAL driver can be used as follows: + + (#) Declare a PKA_HandleTypeDef handle structure, for example: PKA_HandleTypeDef hpka; + + (#) Initialize the PKA low level resources by implementing the HAL_PKA_MspInit() API: + (##) Enable the PKA interface clock + (##) NVIC configuration if you need to use interrupt process + (+++) Configure the PKA interrupt priority + (+++) Enable the NVIC PKA IRQ Channel + + (#) Initialize the PKA registers by calling the HAL_PKA_Init() API which trig + HAL_PKA_MspInit(). + + (#) Fill entirely the input structure corresponding to your operation: + For instance: PKA_ModExpInTypeDef for HAL_PKA_ModExp(). + + (#) Execute the operation (in polling or interrupt) and check the returned value. + + (#) Retrieve the result of the operation (For instance, HAL_PKA_ModExp_GetResult for + HAL_PKA_ModExp operation). The function to gather the result is different for each + kind of operation. The correspondence can be found in the following section. + + (#) Call the function HAL_PKA_DeInit() to restore the default configuration which trig + HAL_PKA_MspDeInit(). + + *** High level operation *** + ================================= + [..] + (+) Input structure requires buffers as uint8_t array. + + (+) Output structure requires buffers as uint8_t array. + + (+) Modular exponentiation using: + (++) HAL_PKA_ModExp(). + (++) HAL_PKA_ModExp_IT(). + (++) HAL_PKA_ModExpFastMode(). + (++) HAL_PKA_ModExpFastMode_IT(). + (++) HAL_PKA_ModExpProtectMode(). + (++) HAL_PKA_ModExpProtectMode_IT(). + (++) HAL_PKA_ModExp_GetResult() to retrieve the result of the operation. + + (+) RSA Chinese Remainder Theorem (CRT) using: + (++) HAL_PKA_RSACRTExp(). + (++) HAL_PKA_RSACRTExp_IT(). + (++) HAL_PKA_RSACRTExp_GetResult() to retrieve the result of the operation. + + (+) ECC Point Check using: + (++) HAL_PKA_PointCheck(). + (++) HAL_PKA_PointCheck_IT(). + (++) HAL_PKA_PointCheck_IsOnCurve() to retrieve the result of the operation. + + (+) ECDSA Sign + (++) HAL_PKA_ECDSASign(). + (++) HAL_PKA_ECDSASign_IT(). + (++) HAL_PKA_ECDSASign_GetResult() to retrieve the result of the operation. + + (+) ECDSA Verify + (++) HAL_PKA_ECDSAVerif(). + (++) HAL_PKA_ECDSAVerif_IT(). + (++) HAL_PKA_ECDSAVerif_IsValidSignature() to retrieve the result of the operation. + + (+) ECC Scalar Multiplication using: + (++) HAL_PKA_ECCMul(). + (++) HAL_PKA_ECCMul_IT(). + (++) HAL_PKA_ECCMul_GetResult() to retrieve the result of the operation. + + (+) ECC double base ladder using: + (++) HAL_PKA_ECCDoubleBaseLadder(). + (++) HAL_PKA_ECCDoubleBaseLadder_IT(). + (++) HAL_PKA_ECCDoubleBaseLadder_GetResult() to retrieve the result of the operation. + + (+) ECC projective to affine using: + (++) HAL_PKA_ECCProjective2Affine(). + (++) HAL_PKA_ECCProjective2Affine_IT(). + (++) HAL_PKA_ECCProjective2Affine_GetResult() to retrieve the result of the operation. + + (+) ECC complete addition using: + (++) HAL_PKA_ECCCompleteAddition(). + (++) HAL_PKA_ECCCompleteAddition_IT(). + (++) HAL_PKA_ECCCompleteAddition_GetResult() to retrieve the result of the operation. + + *** Low level operation *** + ================================= + [..] + (+) Input structure requires buffers as uint32_t array. + + (+) Output structure requires buffers as uint32_t array. + + (+) Arithmetic addition using: + (++) HAL_PKA_Add(). + (++) HAL_PKA_Add_IT(). + (++) HAL_PKA_Arithmetic_GetResult() to retrieve the result of the operation. + The resulting size can be the input parameter or the input parameter size + 1 (overflow). + + (+) Arithmetic subtraction using: + (++) HAL_PKA_Sub(). + (++) HAL_PKA_Sub_IT(). + (++) HAL_PKA_Arithmetic_GetResult() to retrieve the result of the operation. + + (+) Arithmetic multiplication using: + (++) HAL_PKA_Mul(). + (++) HAL_PKA_Mul_IT(). + (++) HAL_PKA_Arithmetic_GetResult() to retrieve the result of the operation. + + (+) Comparison using: + (++) HAL_PKA_Cmp(). + (++) HAL_PKA_Cmp_IT(). + (++) HAL_PKA_Arithmetic_GetResult() to retrieve the result of the operation. + + (+) Modular addition using: + (++) HAL_PKA_ModAdd(). + (++) HAL_PKA_ModAdd_IT(). + (++) HAL_PKA_Arithmetic_GetResult() to retrieve the result of the operation. + + (+) Modular subtraction using: + (++) HAL_PKA_ModSub(). + (++) HAL_PKA_ModSub_IT(). + (++) HAL_PKA_Arithmetic_GetResult() to retrieve the result of the operation. + + (+) Modular inversion using: + (++) HAL_PKA_ModInv(). + (++) HAL_PKA_ModInv_IT(). + (++) HAL_PKA_Arithmetic_GetResult() to retrieve the result of the operation. + + (+) Modular reduction using: + (++) HAL_PKA_ModRed(). + (++) HAL_PKA_ModRed_IT(). + (++) HAL_PKA_Arithmetic_GetResult() to retrieve the result of the operation. + + (+) Montgomery multiplication using: + (++) HAL_PKA_MontgomeryMul(). + (++) HAL_PKA_MontgomeryMul_IT(). + (++) HAL_PKA_Arithmetic_GetResult() to retrieve the result of the operation. + + *** Montgomery parameter *** + ================================= + (+) For some operation, the computation of the Montgomery parameter is a prerequisite. + (+) Input structure requires buffers as uint8_t array. + (+) Output structure requires buffers as uint32_t array.(Only used inside PKA). + (+) You can compute the Montgomery parameter using: + (++) HAL_PKA_MontgomeryParam(). + (++) HAL_PKA_MontgomeryParam_IT(). + (++) HAL_PKA_MontgomeryParam_GetResult() to retrieve the result of the operation. + + *** Polling mode operation *** + =================================== + [..] + (+) When an operation is started in polling mode, the function returns when: + (++) A timeout is encounter. + (++) The operation is completed. + + *** Interrupt mode operation *** + =================================== + [..] + (+) Add HAL_PKA_IRQHandler to the IRQHandler of PKA. + (+) Enable the IRQ using HAL_NVIC_EnableIRQ(). + (+) When an operation is started in interrupt mode, the function returns immediately. + (+) When the operation is completed, the callback HAL_PKA_OperationCpltCallback is called. + (+) When an error is encountered, the callback HAL_PKA_ErrorCallback is called. + (+) To stop any operation in interrupt mode, use HAL_PKA_Abort(). + + *** Utilities *** + =================================== + [..] + (+) To clear the PKA RAM, use HAL_PKA_RAMReset(). + (+) To get current state, use HAL_PKA_GetState(). + (+) To get current error, use HAL_PKA_GetError(). + + *** Callback registration *** + ============================================= + [..] + + The compilation flag USE_HAL_PKA_REGISTER_CALLBACKS, when set to 1, + allows the user to configure dynamically the driver callbacks. + Use Functions HAL_PKA_RegisterCallback() + to register an interrupt callback. + [..] + + Function HAL_PKA_RegisterCallback() allows to register following callbacks: + (+) OperationCpltCallback : callback for End of operation. + (+) ErrorCallback : callback for error detection. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + [..] + + Use function HAL_PKA_UnRegisterCallback to reset a callback to the default + weak function. + [..] + + HAL_PKA_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) OperationCpltCallback : callback for End of operation. + (+) ErrorCallback : callback for error detection. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + [..] + + By default, after the HAL_PKA_Init() and when the state is HAL_PKA_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples HAL_PKA_OperationCpltCallback(), HAL_PKA_ErrorCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak functions in the HAL_PKA_Init()/ HAL_PKA_DeInit() only when + these callbacks are null (not registered beforehand). + [..] + + If MspInit or MspDeInit are not null, the HAL_PKA_Init()/ HAL_PKA_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + [..] + + Callbacks can be registered/unregistered in HAL_PKA_STATE_READY state only. + Exception done MspInit/MspDeInit functions that can be registered/unregistered + in HAL_PKA_STATE_READY or HAL_PKA_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + [..] + + Then, the user first registers the MspInit/MspDeInit user callbacks + using HAL_PKA_RegisterCallback() before calling HAL_PKA_DeInit() + or HAL_PKA_Init() function. + [..] + + When the compilation flag USE_HAL_PKA_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +#if defined(PKA) && defined(HAL_PKA_MODULE_ENABLED) + +/** @defgroup PKA PKA + * @brief PKA HAL module driver. + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup PKA_Private_Define PKA Private Define + * @{ + */ +#define PKA_RAM_SIZE 1334U + +/* Private macro -------------------------------------------------------------*/ +#define __PKA_RAM_PARAM_END(TAB,INDEX) do{ \ + TAB[INDEX] = 0UL; \ + TAB[INDEX + 1U] = 0UL; \ + } while(0) +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +static uint32_t primeordersize; +static uint32_t opsize; +static uint32_t modulussize; +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup PKA_Private_Functions PKA Private Functions + * @{ + */ +uint32_t PKA_GetMode(const PKA_HandleTypeDef *hpka); +HAL_StatusTypeDef PKA_PollEndOfOperation(const PKA_HandleTypeDef *hpka, uint32_t Timeout, uint32_t Tickstart); +uint32_t PKA_CheckError(const PKA_HandleTypeDef *hpka, uint32_t mode); +uint32_t PKA_GetBitSize_u8(uint32_t byteNumber); +uint32_t PKA_GetOptBitSize_u8(uint32_t byteNumber, uint8_t msb); +uint32_t PKA_GetBitSize_u32(uint32_t wordNumber); +uint32_t PKA_GetArraySize_u8(uint32_t bitSize); +void PKA_Memcpy_u32_to_u8(uint8_t dst[], __IO const uint32_t src[], size_t n); +void PKA_Memcpy_u8_to_u32(__IO uint32_t dst[], const uint8_t src[], size_t n); +void PKA_Memcpy_u32_to_u32(__IO uint32_t dst[], __IO const uint32_t src[], size_t n); +HAL_StatusTypeDef PKA_Process(PKA_HandleTypeDef *hpka, uint32_t mode, uint32_t Timeout); +HAL_StatusTypeDef PKA_Process_IT(PKA_HandleTypeDef *hpka, uint32_t mode); +void PKA_ModExp_Set(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef *in); +void PKA_ModExpFastMode_Set(PKA_HandleTypeDef *hpka, PKA_ModExpFastModeInTypeDef *in); +void PKA_ModExpProtectMode_Set(PKA_HandleTypeDef *hpka, PKA_ModExpProtectModeInTypeDef *in); +void PKA_ECCMulEx_Set(PKA_HandleTypeDef *hpka, PKA_ECCMulExInTypeDef *in); +void PKA_ECDSASign_Set(PKA_HandleTypeDef *hpka, PKA_ECDSASignInTypeDef *in); +void PKA_ECDSAVerif_Set(PKA_HandleTypeDef *hpka, PKA_ECDSAVerifInTypeDef *in); +void PKA_RSACRTExp_Set(PKA_HandleTypeDef *hpka, PKA_RSACRTExpInTypeDef *in); +void PKA_PointCheck_Set(PKA_HandleTypeDef *hpka, PKA_PointCheckInTypeDef *in); +void PKA_ECCMul_Set(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in); +void PKA_ModRed_Set(PKA_HandleTypeDef *hpka, PKA_ModRedInTypeDef *in); +void PKA_ModInv_Set(PKA_HandleTypeDef *hpka, PKA_ModInvInTypeDef *in); +void PKA_MontgomeryParam_Set(PKA_HandleTypeDef *hpka, const uint32_t size, const uint8_t *pOp1); +void PKA_ARI_Set(PKA_HandleTypeDef *hpka, const uint32_t size, const uint32_t *pOp1, const uint32_t *pOp2, + const uint8_t *pOp3); +void PKA_ECCDoubleBaseLadder_Set(PKA_HandleTypeDef *hpka, PKA_ECCDoubleBaseLadderInTypeDef *in); +void PKA_ECCProjective2Affine_Set(PKA_HandleTypeDef *hpka, PKA_ECCProjective2AffineInTypeDef *in); +void PKA_ECCCompleteAddition_Set(PKA_HandleTypeDef *hpka, PKA_ECCCompleteAdditionInTypeDef *in); +HAL_StatusTypeDef PKA_WaitOnFlagUntilTimeout(PKA_HandleTypeDef *hpka, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout); +uint32_t PKA_Result_GetSize(const PKA_HandleTypeDef *hpka, uint32_t Startindex, uint32_t Maxsize); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup PKA_Exported_Functions PKA Exported Functions + * @{ + */ + +/** @defgroup PKA_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and de-initialization functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + deinitialize the PKAx peripheral: + + (+) User must implement HAL_PKA_MspInit() function in which he configures + all related peripherals resources (CLOCK, IT and NVIC ). + + (+) Call the function HAL_PKA_Init() to configure the device. + + (+) Call the function HAL_PKA_DeInit() to restore the default configuration + of the selected PKAx peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the PKA according to the specified + * parameters in the PKA_InitTypeDef and initialize the associated handle. + * @param hpka PKA handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_Init(PKA_HandleTypeDef *hpka) +{ + HAL_StatusTypeDef err = HAL_OK; + uint32_t tickstart; + + /* Check the PKA handle allocation */ + if (hpka != NULL) + { + /* Check the parameters */ + assert_param(IS_PKA_ALL_INSTANCE(hpka->Instance)); + + if (hpka->State == HAL_PKA_STATE_RESET) + { + +#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1) + /* Init the PKA Callback settings */ + hpka->OperationCpltCallback = HAL_PKA_OperationCpltCallback; /* Legacy weak OperationCpltCallback */ + hpka->ErrorCallback = HAL_PKA_ErrorCallback; /* Legacy weak ErrorCallback */ + + if (hpka->MspInitCallback == NULL) + { + hpka->MspInitCallback = HAL_PKA_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware */ + hpka->MspInitCallback(hpka); +#else + /* Init the low level hardware */ + HAL_PKA_MspInit(hpka); +#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */ + } + + /* Set the state to busy */ + hpka->State = HAL_PKA_STATE_BUSY; + + /* Reset the control register and enable the PKA */ + hpka->Instance->CR = PKA_CR_EN; + + /* Get current tick */ + tickstart = HAL_GetTick(); + + /* Wait the INITOK flag Setting */ + if (PKA_WaitOnFlagUntilTimeout(hpka, PKA_SR_INITOK, RESET, tickstart, 5000) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Reset any pending flag */ + SET_BIT(hpka->Instance->CLRFR, PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC | PKA_CLRFR_ADDRERRFC | PKA_CLRFR_OPERRFC); + + /* Initialize the error code */ + hpka->ErrorCode = HAL_PKA_ERROR_NONE; + + /* Set the state to ready */ + hpka->State = HAL_PKA_STATE_READY; + } + else + { + err = HAL_ERROR; + } + + return err; +} + +/** + * @brief DeInitialize the PKA peripheral. + * @param hpka PKA handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_DeInit(PKA_HandleTypeDef *hpka) +{ + HAL_StatusTypeDef err = HAL_OK; + + /* Check the PKA handle allocation */ + if (hpka != NULL) + { + /* Check the parameters */ + assert_param(IS_PKA_ALL_INSTANCE(hpka->Instance)); + + /* Set the state to busy */ + hpka->State = HAL_PKA_STATE_BUSY; + + /* Reset the control register */ + /* This abort any operation in progress (PKA RAM content is not guaranteed in this case) */ + hpka->Instance->CR = 0; + + /* Reset any pending flag */ + SET_BIT(hpka->Instance->CLRFR, PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC | PKA_CLRFR_ADDRERRFC | PKA_CLRFR_OPERRFC); + +#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1) + if (hpka->MspDeInitCallback == NULL) + { + hpka->MspDeInitCallback = HAL_PKA_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + hpka->MspDeInitCallback(hpka); +#else + /* DeInit the low level hardware: CLOCK, NVIC */ + HAL_PKA_MspDeInit(hpka); +#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */ + + /* Reset the error code */ + hpka->ErrorCode = HAL_PKA_ERROR_NONE; + + /* Reset the state */ + hpka->State = HAL_PKA_STATE_RESET; + } + else + { + err = HAL_ERROR; + } + + return err; +} + +/** + * @brief Initialize the PKA MSP. + * @param hpka PKA handle + * @retval None + */ +__weak void HAL_PKA_MspInit(PKA_HandleTypeDef *hpka) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpka); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PKA_MspInit can be implemented in the user file + */ +} + +/** + * @brief DeInitialize the PKA MSP. + * @param hpka PKA handle + * @retval None + */ +__weak void HAL_PKA_MspDeInit(PKA_HandleTypeDef *hpka) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpka); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PKA_MspDeInit can be implemented in the user file + */ +} + +#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User PKA Callback + * To be used instead of the weak predefined callback + * @param hpka Pointer to a PKA_HandleTypeDef structure that contains + * the configuration information for the specified PKA. + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_PKA_OPERATION_COMPLETE_CB_ID End of operation callback ID + * @arg @ref HAL_PKA_ERROR_CB_ID Error callback ID + * @arg @ref HAL_PKA_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_PKA_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_RegisterCallback(PKA_HandleTypeDef *hpka, HAL_PKA_CallbackIDTypeDef CallbackID, + pPKA_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hpka->ErrorCode |= HAL_PKA_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (HAL_PKA_STATE_READY == hpka->State) + { + switch (CallbackID) + { + case HAL_PKA_OPERATION_COMPLETE_CB_ID : + hpka->OperationCpltCallback = pCallback; + break; + + case HAL_PKA_ERROR_CB_ID : + hpka->ErrorCallback = pCallback; + break; + + case HAL_PKA_MSPINIT_CB_ID : + hpka->MspInitCallback = pCallback; + break; + + case HAL_PKA_MSPDEINIT_CB_ID : + hpka->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hpka->ErrorCode |= HAL_PKA_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_PKA_STATE_RESET == hpka->State) + { + switch (CallbackID) + { + case HAL_PKA_MSPINIT_CB_ID : + hpka->MspInitCallback = pCallback; + break; + + case HAL_PKA_MSPDEINIT_CB_ID : + hpka->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hpka->ErrorCode |= HAL_PKA_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hpka->ErrorCode |= HAL_PKA_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister a PKA Callback + * PKA callback is redirected to the weak predefined callback + * @param hpka Pointer to a PKA_HandleTypeDef structure that contains + * the configuration information for the specified PKA. + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_PKA_OPERATION_COMPLETE_CB_ID End of operation callback ID + * @arg @ref HAL_PKA_ERROR_CB_ID Error callback ID + * @arg @ref HAL_PKA_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_PKA_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_UnRegisterCallback(PKA_HandleTypeDef *hpka, HAL_PKA_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (HAL_PKA_STATE_READY == hpka->State) + { + switch (CallbackID) + { + case HAL_PKA_OPERATION_COMPLETE_CB_ID : + hpka->OperationCpltCallback = HAL_PKA_OperationCpltCallback; /* Legacy weak OperationCpltCallback */ + break; + + case HAL_PKA_ERROR_CB_ID : + hpka->ErrorCallback = HAL_PKA_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_PKA_MSPINIT_CB_ID : + hpka->MspInitCallback = HAL_PKA_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_PKA_MSPDEINIT_CB_ID : + hpka->MspDeInitCallback = HAL_PKA_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hpka->ErrorCode |= HAL_PKA_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_PKA_STATE_RESET == hpka->State) + { + switch (CallbackID) + { + case HAL_PKA_MSPINIT_CB_ID : + hpka->MspInitCallback = HAL_PKA_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_PKA_MSPDEINIT_CB_ID : + hpka->MspDeInitCallback = HAL_PKA_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hpka->ErrorCode |= HAL_PKA_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hpka->ErrorCode |= HAL_PKA_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup PKA_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the PKA operations. + + (#) There are two modes of operation: + + (++) Blocking mode : The operation is performed in the polling mode. + These functions return when data operation is completed. + (++) No-Blocking mode : The operation is performed using Interrupts. + These functions return immediately. + The end of the operation is indicated by HAL_PKA_ErrorCallback in case of error. + The end of the operation is indicated by HAL_PKA_OperationCpltCallback in case of success. + To stop any operation in interrupt mode, use HAL_PKA_Abort(). + + (#) Blocking mode functions are : + + (++) HAL_PKA_ModExp() + (++) HAL_PKA_ModExpFastMode() + (++) HAL_PKA_ModExpProtectMode() + (++) HAL_PKA_ModExp_GetResult(); + + (++) HAL_PKA_ECDSASign() + (++) HAL_PKA_ECDSASign_GetResult(); + + (++) HAL_PKA_ECDSAVerif() + (++) HAL_PKA_ECDSAVerif_IsValidSignature(); + + (++) HAL_PKA_RSACRTExp() + (++) HAL_PKA_RSACRTExp_GetResult(); + + (++) HAL_PKA_PointCheck() + (++) HAL_PKA_PointCheck_IsOnCurve(); + + (++) HAL_PKA_ECCMul() + (++) HAL_PKA_ECCMulFastMode() + (++) HAL_PKA_ECCMul_GetResult(); + + (++) HAL_PKA_ECCMulEx() + (++) HAL_PKA_ECCDoubleBaseLadder() + (++) HAL_PKA_ECCDoubleBaseLadder_GetResult(); + (++) HAL_PKA_ECCProjective2Affine() + (++) HAL_PKA_ECCProjective2Affine_GetResult(); + (++) HAL_PKA_ECCCompleteAddition() + (++) HAL_PKA_ECCCompleteAddition_GetResult(); + + (++) HAL_PKA_Add() + (++) HAL_PKA_Sub() + (++) HAL_PKA_Cmp() + (++) HAL_PKA_Mul() + (++) HAL_PKA_ModAdd() + (++) HAL_PKA_ModSub() + (++) HAL_PKA_ModInv() + (++) HAL_PKA_ModRed() + (++) HAL_PKA_MontgomeryMul() + (++) HAL_PKA_Arithmetic_GetResult(P); + + (++) HAL_PKA_MontgomeryParam() + (++) HAL_PKA_MontgomeryParam_GetResult(); + + (#) No-Blocking mode functions with Interrupt are : + + (++) HAL_PKA_ModExp_IT(); + (++) HAL_PKA_ModExpFastMode_IT(); + (++) HAL_PKA_ModExpProtectMode_IT() + (++) HAL_PKA_ModExp_GetResult(); + + (++) HAL_PKA_ECDSASign_IT(); + (++) HAL_PKA_ECDSASign_GetResult(); + + (++) HAL_PKA_ECDSAVerif_IT(); + (++) HAL_PKA_ECDSAVerif_IsValidSignature(); + + (++) HAL_PKA_RSACRTExp_IT(); + (++) HAL_PKA_RSACRTExp_GetResult(); + + (++) HAL_PKA_PointCheck_IT(); + (++) HAL_PKA_PointCheck_IsOnCurve(); + + (++) HAL_PKA_ECCMul_IT(); + (++) HAL_PKA_ECCMulFastMode_IT(); + (++) HAL_PKA_ECCMul_GetResult(); + + (++) HAL_PKA_ECCMulEx_IT(); + (++) HAL_PKA_ECCDoubleBaseLadder_IT() + (++) HAL_PKA_ECCDoubleBaseLadder_GetResult(); + (++) HAL_PKA_ECCProjective2Affine_IT() + (++) HAL_PKA_ECCProjective2Affine_GetResult(); + (++) HAL_PKA_ECCCompleteAddition_IT() + (++) HAL_PKA_ECCCompleteAddition_GetResult(); + (++) HAL_PKA_Add_IT(); + (++) HAL_PKA_Sub_IT(); + (++) HAL_PKA_Cmp_IT(); + (++) HAL_PKA_Mul_IT(); + (++) HAL_PKA_ModAdd_IT(); + (++) HAL_PKA_ModSub_IT(); + (++) HAL_PKA_ModInv_IT(); + (++) HAL_PKA_ModRed_IT(); + (++) HAL_PKA_MontgomeryMul_IT(); + (++) HAL_PKA_Arithmetic_GetResult(); + + (++) HAL_PKA_MontgomeryParam_IT(); + (++) HAL_PKA_MontgomeryParam_GetResult(); + + (++) HAL_PKA_Abort(); + +@endverbatim + * @{ + */ + +/** + * @brief Modular exponentiation in blocking mode. + * @param hpka PKA handle + * @param in Input information + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_ModExp(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef *in, uint32_t Timeout) +{ + /* Set input parameter in PKA RAM */ + PKA_ModExp_Set(hpka, in); + + opsize = in->OpSize; + + /* Start the operation */ + return PKA_Process(hpka, PKA_MODE_MODULAR_EXP, Timeout); +} + +/** + * @brief Modular exponentiation in non-blocking mode with Interrupt. + * @param hpka PKA handle + * @param in Input information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_ModExp_IT(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef *in) +{ + /* Set input parameter in PKA RAM */ + PKA_ModExp_Set(hpka, in); + + opsize = in->OpSize; + + /* Start the operation */ + return PKA_Process_IT(hpka, PKA_MODE_MODULAR_EXP); +} + +/** + * @brief Modular exponentiation in blocking mode. + * @param hpka PKA handle + * @param in Input information + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_ModExpFastMode(PKA_HandleTypeDef *hpka, PKA_ModExpFastModeInTypeDef *in, uint32_t Timeout) +{ + /* Set input parameter in PKA RAM */ + PKA_ModExpFastMode_Set(hpka, in); + + opsize = in->OpSize; + + /* Start the operation */ + return PKA_Process(hpka, PKA_MODE_MODULAR_EXP_FAST_MODE, Timeout); +} + +/** + * @brief Modular exponentiation in non-blocking mode with Interrupt. + * @param hpka PKA handle + * @param in Input information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_ModExpFastMode_IT(PKA_HandleTypeDef *hpka, PKA_ModExpFastModeInTypeDef *in) +{ + /* Set input parameter in PKA RAM */ + PKA_ModExpFastMode_Set(hpka, in); + + opsize = in->OpSize; + + /* Start the operation */ + return PKA_Process_IT(hpka, PKA_MODE_MODULAR_EXP_FAST_MODE); +} + +/** + * @brief Modular exponentiation (protected) in blocking mode. + * Useful when a secret information is involved (RSA decryption) + * @param hpka PKA handle + * @param in Input information + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_ModExpProtectMode(PKA_HandleTypeDef *hpka, PKA_ModExpProtectModeInTypeDef *in, + uint32_t Timeout) +{ + /* Set input parameter in PKA RAM */ + PKA_ModExpProtectMode_Set(hpka, in); + + opsize = in->OpSize; + + return PKA_Process(hpka, PKA_MODE_MODULAR_EXP_PROTECT, Timeout); +} + +/** + * @brief Modular exponentiation (protected) in non-blocking mode with Interrupt. + * Useful when a secret information is involved (RSA decryption) + * @param hpka PKA handle + * @param in Input information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_ModExpProtectMode_IT(PKA_HandleTypeDef *hpka, PKA_ModExpProtectModeInTypeDef *in) +{ + /* Set input parameter in PKA RAM */ + PKA_ModExpProtectMode_Set(hpka, in); + + opsize = in->OpSize; + + return PKA_Process_IT(hpka, PKA_MODE_MODULAR_EXP_PROTECT); +} + + +/** + * @brief Retrieve operation result. + * @param hpka PKA handle + * @param pRes Output buffer + * @retval HAL status + */ +void HAL_PKA_ModExp_GetResult(PKA_HandleTypeDef *hpka, uint8_t *pRes) +{ + uint32_t size; + + /* Get output result size */ + size = opsize; + + /* Move the result to appropriate location (indicated in out parameter) */ + PKA_Memcpy_u32_to_u8(pRes, &hpka->Instance->RAM[PKA_MODULAR_EXP_OUT_RESULT], size); +} + +/** + * @brief Sign a message using elliptic curves over prime fields in blocking mode. + * @param hpka PKA handle + * @param in Input information + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_ECDSASign(PKA_HandleTypeDef *hpka, PKA_ECDSASignInTypeDef *in, uint32_t Timeout) +{ + /* Set input parameter in PKA RAM */ + PKA_ECDSASign_Set(hpka, in); + + primeordersize = in->primeOrderSize; + + /* Start the operation */ + return PKA_Process(hpka, PKA_MODE_ECDSA_SIGNATURE, Timeout); +} + +/** + * @brief Sign a message using elliptic curves over prime fields in non-blocking mode with Interrupt. + * @param hpka PKA handle + * @param in Input information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_ECDSASign_IT(PKA_HandleTypeDef *hpka, PKA_ECDSASignInTypeDef *in) +{ + /* Set input parameter in PKA RAM */ + PKA_ECDSASign_Set(hpka, in); + + primeordersize = in->primeOrderSize; + + /* Start the operation */ + return PKA_Process_IT(hpka, PKA_MODE_ECDSA_SIGNATURE); +} + +/** + * @brief Retrieve operation result. + * @param hpka PKA handle + * @param out Output information + * @param outExt Additional Output information (facultative) + */ +void HAL_PKA_ECDSASign_GetResult(PKA_HandleTypeDef *hpka, PKA_ECDSASignOutTypeDef *out, + PKA_ECDSASignOutExtParamTypeDef *outExt) +{ + uint32_t size; + + /* Get output result size */ + size = primeordersize; + + + if (out != NULL) + { + PKA_Memcpy_u32_to_u8(out->RSign, &hpka->Instance->RAM[PKA_ECDSA_SIGN_OUT_SIGNATURE_R], size); + PKA_Memcpy_u32_to_u8(out->SSign, &hpka->Instance->RAM[PKA_ECDSA_SIGN_OUT_SIGNATURE_S], size); + } + + /* If user requires the additional information */ + if (outExt != NULL) + { + /* Move the result to appropriate location (indicated in outExt parameter) */ + PKA_Memcpy_u32_to_u8(outExt->ptX, &hpka->Instance->RAM[PKA_ECDSA_SIGN_OUT_FINAL_POINT_X], size); + PKA_Memcpy_u32_to_u8(outExt->ptY, &hpka->Instance->RAM[PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y], size); + } +} + +/** + * @brief Verify the validity of a signature using elliptic curves over prime fields in blocking mode. + * @param hpka PKA handle + * @param in Input information + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_ECDSAVerif(PKA_HandleTypeDef *hpka, PKA_ECDSAVerifInTypeDef *in, uint32_t Timeout) +{ + /* Set input parameter in PKA RAM */ + PKA_ECDSAVerif_Set(hpka, in); + + /* Start the operation */ + return PKA_Process(hpka, PKA_MODE_ECDSA_VERIFICATION, Timeout); +} + +/** + * @brief Verify the validity of a signature using elliptic curves + * over prime fields in non-blocking mode with Interrupt. + * @param hpka PKA handle + * @param in Input information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_ECDSAVerif_IT(PKA_HandleTypeDef *hpka, PKA_ECDSAVerifInTypeDef *in) +{ + /* Set input parameter in PKA RAM */ + PKA_ECDSAVerif_Set(hpka, in); + + /* Start the operation */ + return PKA_Process_IT(hpka, PKA_MODE_ECDSA_VERIFICATION); +} + +/** + * @brief Return the result of the ECDSA verification operation. + * @param hpka PKA handle + * @retval 1 if signature is verified, 0 in other case + */ +uint32_t HAL_PKA_ECDSAVerif_IsValidSignature(PKA_HandleTypeDef const *const hpka) +{ + return (hpka->Instance->RAM[PKA_ECDSA_VERIF_OUT_RESULT] == 0xD60DU) ? 1UL : 0UL; +} + +/** + * @brief RSA CRT exponentiation in blocking mode. + * @param hpka PKA handle + * @param in Input information + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_RSACRTExp(PKA_HandleTypeDef *hpka, PKA_RSACRTExpInTypeDef *in, uint32_t Timeout) +{ + /* Set input parameter in PKA RAM */ + PKA_RSACRTExp_Set(hpka, in); + + /* Start the operation */ + return PKA_Process(hpka, PKA_MODE_RSA_CRT_EXP, Timeout); +} + +/** + * @brief RSA CRT exponentiation in non-blocking mode with Interrupt. + * @param hpka PKA handle + * @param in Input information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_RSACRTExp_IT(PKA_HandleTypeDef *hpka, PKA_RSACRTExpInTypeDef *in) +{ + /* Set input parameter in PKA RAM */ + PKA_RSACRTExp_Set(hpka, in); + + /* Start the operation */ + return PKA_Process_IT(hpka, PKA_MODE_RSA_CRT_EXP); +} + +/** + * @brief Retrieve operation result. + * @param hpka PKA handle + * @param pRes Pointer to memory location to receive the result of the operation + * @retval HAL status + */ +void HAL_PKA_RSACRTExp_GetResult(PKA_HandleTypeDef *hpka, uint8_t *pRes) +{ + uint32_t size; + + /* Move the result to appropriate location (indicated in out parameter) */ + size = (hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_MOD_NB_BITS] + 7UL) / 8UL; + + PKA_Memcpy_u32_to_u8(pRes, &hpka->Instance->RAM[PKA_RSA_CRT_EXP_OUT_RESULT], size); +} + +/** + * @brief Point on elliptic curve check in blocking mode. + * @param hpka PKA handle + * @param in Input information + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_PointCheck(PKA_HandleTypeDef *hpka, PKA_PointCheckInTypeDef *in, uint32_t Timeout) +{ + /* Set input parameter in PKA RAM */ + PKA_PointCheck_Set(hpka, in); + + /* Start the operation */ + return PKA_Process(hpka, PKA_MODE_POINT_CHECK, Timeout); +} + +/** + * @brief Point on elliptic curve check in non-blocking mode with Interrupt. + * @param hpka PKA handle + * @param in Input information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_PointCheck_IT(PKA_HandleTypeDef *hpka, PKA_PointCheckInTypeDef *in) +{ + /* Set input parameter in PKA RAM */ + PKA_PointCheck_Set(hpka, in); + + /* Start the operation */ + return PKA_Process_IT(hpka, PKA_MODE_POINT_CHECK); +} + +/** + * @brief Return the result of the point check operation. + * @param hpka PKA handle + * @retval 1 if point is on curve, 0 in other case + */ +uint32_t HAL_PKA_PointCheck_IsOnCurve(PKA_HandleTypeDef const *const hpka) +{ +#define PKA_POINT_IS_ON_CURVE 0xD60DUL + /* Invert the value of the PKA RAM containing the result of the operation */ + return (hpka->Instance->RAM[PKA_POINT_CHECK_OUT_ERROR] == PKA_POINT_IS_ON_CURVE) ? 1UL : 0UL; +} + +/** + * @brief ECC scalar multiplication in blocking mode. + * @param hpka PKA handle + * @param in Input information + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_ECCMul(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in, uint32_t Timeout) +{ + /* Set input parameter in PKA RAM */ + PKA_ECCMul_Set(hpka, in); + + modulussize = in->modulusSize; + + /* Start the operation */ + return PKA_Process(hpka, PKA_MODE_ECC_MUL, Timeout); +} + +/** + * @brief ECC scalar multiplication in non-blocking mode with Interrupt. + * @param hpka PKA handle + * @param in Input information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_ECCMul_IT(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in) +{ + /* Set input parameter in PKA RAM */ + PKA_ECCMul_Set(hpka, in); + + modulussize = in->modulusSize; + + /* Start the operation */ + return PKA_Process_IT(hpka, PKA_MODE_ECC_MUL); +} +/** + * @brief ECC scalar multiplication extended in blocking mode. + * @param hpka PKA handle + * @param in Input information + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_ECCMulEx(PKA_HandleTypeDef *hpka, PKA_ECCMulExInTypeDef *in, uint32_t Timeout) +{ + /* Set input parameter in PKA RAM */ + PKA_ECCMulEx_Set(hpka, in); + + modulussize = in->modulusSize; + + /* Start the operation */ + return PKA_Process(hpka, PKA_MODE_ECC_MUL, Timeout); +} + +/** + * @brief ECC scalar multiplication extended in non-blocking mode with Interrupt. + * @param hpka PKA handle + * @param in Input information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_ECCMulEx_IT(PKA_HandleTypeDef *hpka, PKA_ECCMulExInTypeDef *in) +{ + /* Set input parameter in PKA RAM */ + PKA_ECCMulEx_Set(hpka, in); + + modulussize = in->modulusSize; + + /* Start the operation */ + return PKA_Process_IT(hpka, PKA_MODE_ECC_MUL); +} +/** + * @brief Retrieve operation result. + * @param hpka PKA handle + * @param out Output information + * @retval HAL status + */ +void HAL_PKA_ECCMul_GetResult(PKA_HandleTypeDef *hpka, PKA_ECCMulOutTypeDef *out) +{ + uint32_t size; + + /* Get output result size */ + size = modulussize; + + /* If a destination buffer is provided */ + if (out != NULL) + { + /* Move the result to appropriate location (indicated in out parameter) */ + PKA_Memcpy_u32_to_u8(out->ptX, &hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_OUT_RESULT_X], size); + PKA_Memcpy_u32_to_u8(out->ptY, &hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_OUT_RESULT_Y], size); + } +} + +/** + * @brief Arithmetic addition in blocking mode. + * @param hpka PKA handle + * @param in Input information + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_Add(PKA_HandleTypeDef *hpka, PKA_AddInTypeDef *in, uint32_t Timeout) +{ + /* Set input parameter in PKA RAM */ + PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, NULL); + + /* Start the operation */ + return PKA_Process(hpka, PKA_MODE_ARITHMETIC_ADD, Timeout); +} + +/** + * @brief Arithmetic addition in non-blocking mode with Interrupt. + * @param hpka PKA handle + * @param in Input information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_Add_IT(PKA_HandleTypeDef *hpka, PKA_AddInTypeDef *in) +{ + /* Set input parameter in PKA RAM */ + PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, NULL); + + /* Start the operation */ + return PKA_Process_IT(hpka, PKA_MODE_ARITHMETIC_ADD); +} + +/** + * @brief Arithmetic subtraction in blocking mode. + * @param hpka PKA handle + * @param in Input information + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_Sub(PKA_HandleTypeDef *hpka, PKA_SubInTypeDef *in, uint32_t Timeout) +{ + /* Set input parameter in PKA RAM */ + PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, NULL); + + /* Start the operation */ + return PKA_Process(hpka, PKA_MODE_ARITHMETIC_SUB, Timeout); +} + +/** + * @brief Arithmetic subtraction in non-blocking mode with Interrupt. + * @param hpka PKA handle + * @param in Input information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_Sub_IT(PKA_HandleTypeDef *hpka, PKA_SubInTypeDef *in) +{ + /* Set input parameter in PKA RAM */ + PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, NULL); + + /* Start the operation */ + return PKA_Process_IT(hpka, PKA_MODE_ARITHMETIC_SUB); +} + +/** + * @brief Arithmetic multiplication in blocking mode. + * @param hpka PKA handle + * @param in Input information + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_Mul(PKA_HandleTypeDef *hpka, PKA_MulInTypeDef *in, uint32_t Timeout) +{ + /* Set input parameter in PKA RAM */ + PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, NULL); + + /* Start the operation */ + return PKA_Process(hpka, PKA_MODE_ARITHMETIC_MUL, Timeout); +} + +/** + * @brief Arithmetic multiplication in non-blocking mode with Interrupt. + * @param hpka PKA handle + * @param in Input information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_Mul_IT(PKA_HandleTypeDef *hpka, PKA_MulInTypeDef *in) +{ + /* Set input parameter in PKA RAM */ + PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, NULL); + + /* Start the operation */ + return PKA_Process_IT(hpka, PKA_MODE_ARITHMETIC_MUL); +} + +/** + * @brief Comparison in blocking mode. + * @param hpka PKA handle + * @param in Input information + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_Cmp(PKA_HandleTypeDef *hpka, PKA_CmpInTypeDef *in, uint32_t Timeout) +{ + /* Set input parameter in PKA RAM */ + PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, NULL); + + /* Start the operation */ + return PKA_Process(hpka, PKA_MODE_COMPARISON, Timeout); +} + +/** + * @brief Comparison in non-blocking mode with Interrupt. + * @param hpka PKA handle + * @param in Input information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_Cmp_IT(PKA_HandleTypeDef *hpka, PKA_CmpInTypeDef *in) +{ + /* Set input parameter in PKA RAM */ + PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, NULL); + + /* Start the operation */ + return PKA_Process_IT(hpka, PKA_MODE_COMPARISON); +} + +/** + * @brief Modular addition in blocking mode. + * @param hpka PKA handle + * @param in Input information + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_ModAdd(PKA_HandleTypeDef *hpka, PKA_ModAddInTypeDef *in, uint32_t Timeout) +{ + /* Set input parameter in PKA RAM */ + PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, in->pOp3); + + /* Start the operation */ + return PKA_Process(hpka, PKA_MODE_MODULAR_ADD, Timeout); +} + +/** + * @brief Modular addition in non-blocking mode with Interrupt. + * @param hpka PKA handle + * @param in Input information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_ModAdd_IT(PKA_HandleTypeDef *hpka, PKA_ModAddInTypeDef *in) +{ + /* Set input parameter in PKA RAM */ + PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, in->pOp3); + + /* Start the operation */ + return PKA_Process_IT(hpka, PKA_MODE_MODULAR_ADD); +} + +/** + * @brief Modular inversion in blocking mode. + * @param hpka PKA handle + * @param in Input information + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_ModInv(PKA_HandleTypeDef *hpka, PKA_ModInvInTypeDef *in, uint32_t Timeout) +{ + /* Set input parameter in PKA RAM */ + PKA_ModInv_Set(hpka, in); + + /* Start the operation */ + return PKA_Process(hpka, PKA_MODE_MODULAR_INV, Timeout); +} + +/** + * @brief Modular inversion in non-blocking mode with Interrupt. + * @param hpka PKA handle + * @param in Input information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_ModInv_IT(PKA_HandleTypeDef *hpka, PKA_ModInvInTypeDef *in) +{ + /* Set input parameter in PKA RAM */ + PKA_ModInv_Set(hpka, in); + + /* Start the operation */ + return PKA_Process_IT(hpka, PKA_MODE_MODULAR_INV); +} + +/** + * @brief Modular subtraction in blocking mode. + * @param hpka PKA handle + * @param in Input information + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_ModSub(PKA_HandleTypeDef *hpka, PKA_ModSubInTypeDef *in, uint32_t Timeout) +{ + /* Set input parameter in PKA RAM */ + PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, in->pOp3); + + /* Start the operation */ + return PKA_Process(hpka, PKA_MODE_MODULAR_SUB, Timeout); +} + +/** + * @brief Modular subtraction in non-blocking mode with Interrupt. + * @param hpka PKA handle + * @param in Input information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_ModSub_IT(PKA_HandleTypeDef *hpka, PKA_ModSubInTypeDef *in) +{ + /* Set input parameter in PKA RAM */ + PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, in->pOp3); + + /* Start the operation */ + return PKA_Process_IT(hpka, PKA_MODE_MODULAR_SUB); +} + +/** + * @brief Modular reduction in blocking mode. + * @param hpka PKA handle + * @param in Input information + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_ModRed(PKA_HandleTypeDef *hpka, PKA_ModRedInTypeDef *in, uint32_t Timeout) +{ + /* Set input parameter in PKA RAM */ + PKA_ModRed_Set(hpka, in); + + /* Start the operation */ + return PKA_Process(hpka, PKA_MODE_MODULAR_RED, Timeout); +} + +/** + * @brief Modular reduction in non-blocking mode with Interrupt. + * @param hpka PKA handle + * @param in Input information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_ModRed_IT(PKA_HandleTypeDef *hpka, PKA_ModRedInTypeDef *in) +{ + /* Set input parameter in PKA RAM */ + PKA_ModRed_Set(hpka, in); + + /* Start the operation */ + return PKA_Process_IT(hpka, PKA_MODE_MODULAR_RED); +} + +/** + * @brief Montgomery multiplication in blocking mode. + * @param hpka PKA handle + * @param in Input information + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_MontgomeryMul(PKA_HandleTypeDef *hpka, PKA_MontgomeryMulInTypeDef *in, uint32_t Timeout) +{ + /* Set input parameter in PKA RAM */ + PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, in->pOp3); + + /* Start the operation */ + return PKA_Process(hpka, PKA_MODE_MONTGOMERY_MUL, Timeout); +} + +/** + * @brief Montgomery multiplication in non-blocking mode with Interrupt. + * @param hpka PKA handle + * @param in Input information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_MontgomeryMul_IT(PKA_HandleTypeDef *hpka, PKA_MontgomeryMulInTypeDef *in) +{ + /* Set input parameter in PKA RAM */ + PKA_ARI_Set(hpka, in->size, in->pOp1, in->pOp2, in->pOp3); + + /* Start the operation */ + return PKA_Process_IT(hpka, PKA_MODE_MONTGOMERY_MUL); +} + +/** + * @brief Retrieve operation result. + * @param hpka PKA handle + * @param pRes Pointer to memory location to receive the result of the operation + */ +void HAL_PKA_Arithmetic_GetResult(PKA_HandleTypeDef *hpka, uint32_t *pRes) +{ + uint32_t mode = (hpka->Instance->CR & PKA_CR_MODE_Msk) >> PKA_CR_MODE_Pos; + uint32_t size = 0; + + /* Move the result to appropriate location (indicated in pRes parameter) */ + switch (mode) + { + case PKA_MODE_MONTGOMERY_PARAM: + case PKA_MODE_ARITHMETIC_SUB: + case PKA_MODE_MODULAR_ADD: + case PKA_MODE_MODULAR_RED: + case PKA_MODE_MODULAR_INV: + case PKA_MODE_MONTGOMERY_MUL: + size = hpka->Instance->RAM[2] / 32UL; + break; + case PKA_MODE_ARITHMETIC_ADD: + case PKA_MODE_MODULAR_SUB: + size = hpka->Instance->RAM[PKA_ARITHMETIC_ALL_OPS_NB_BITS] / 32UL; + + /* Manage the overflow of the addition */ + if (hpka->Instance->RAM[PKA_ARITHMETIC_ALL_OPS_OUT_RESULT + size] != 0UL) + { + size += 1UL; + } + + break; + case PKA_MODE_COMPARISON: + size = 1; + break; + case PKA_MODE_ARITHMETIC_MUL: + size = hpka->Instance->RAM[PKA_ARITHMETIC_MUL_NB_BITS] / 32UL * 2UL; + break; + default: + break; + } + + if (pRes != NULL) + { + switch (mode) + { + case PKA_MODE_ARITHMETIC_SUB: + case PKA_MODE_MODULAR_ADD: + case PKA_MODE_MODULAR_RED: + case PKA_MODE_MODULAR_INV: + case PKA_MODE_MODULAR_SUB: + case PKA_MODE_MONTGOMERY_MUL: + case PKA_MODE_ARITHMETIC_ADD: + case PKA_MODE_COMPARISON: + case PKA_MODE_ARITHMETIC_MUL: + PKA_Memcpy_u32_to_u32(pRes, &hpka->Instance->RAM[PKA_ARITHMETIC_ALL_OPS_OUT_RESULT], size); + break; + default: + break; + } + } +} + +/** + * @brief Montgomery parameter computation in blocking mode. + * @param hpka PKA handle + * @param in Input information + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_MontgomeryParam(PKA_HandleTypeDef *hpka, PKA_MontgomeryParamInTypeDef *in, uint32_t Timeout) +{ + /* Set input parameter in PKA RAM */ + PKA_MontgomeryParam_Set(hpka, in->size, in->pOp1); + + /* Start the operation */ + return PKA_Process(hpka, PKA_MODE_MONTGOMERY_PARAM, Timeout); +} + +/** + * @brief Montgomery parameter computation in non-blocking mode with Interrupt. + * @param hpka PKA handle + * @param in Input information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_MontgomeryParam_IT(PKA_HandleTypeDef *hpka, PKA_MontgomeryParamInTypeDef *in) +{ + /* Set input parameter in PKA RAM */ + PKA_MontgomeryParam_Set(hpka, in->size, in->pOp1); + + /* Start the operation */ + return PKA_Process_IT(hpka, PKA_MODE_MONTGOMERY_PARAM); +} + +/** + * @brief ECC double base ladder in blocking mode. + * @param hpka PKA handle + * @param in Input information + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_ECCDoubleBaseLadder(PKA_HandleTypeDef *hpka, PKA_ECCDoubleBaseLadderInTypeDef *in, + uint32_t Timeout) +{ + /* Set input parameter in PKA RAM */ + PKA_ECCDoubleBaseLadder_Set(hpka, in); + + return PKA_Process(hpka, PKA_MODE_DOUBLE_BASE_LADDER, Timeout); +} + +/** + * @brief ECC double base ladder in non-blocking mode with Interrupt. + * @param hpka PKA handle + * @param in Input information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_ECCDoubleBaseLadder_IT(PKA_HandleTypeDef *hpka, PKA_ECCDoubleBaseLadderInTypeDef *in) +{ + /* Set input parameter in PKA RAM */ + PKA_ECCDoubleBaseLadder_Set(hpka, in); + + return PKA_Process_IT(hpka, PKA_MODE_DOUBLE_BASE_LADDER); +} + +/** + * @brief ECC projective to affine in blocking mode. + * @param hpka PKA handle + * @param in Input information + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_ECCProjective2Affine(PKA_HandleTypeDef *hpka, PKA_ECCProjective2AffineInTypeDef *in, + uint32_t Timeout) +{ + /* Set input parameter in PKA RAM */ + PKA_ECCProjective2Affine_Set(hpka, in); + + return PKA_Process(hpka, PKA_MODE_ECC_PROJECTIVE_AFF, Timeout); +} + +/** + * @brief ECC projective to affine in non-blocking mode with Interrupt. + * @param hpka PKA handle + * @param in Input information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_ECCProjective2Affine_IT(PKA_HandleTypeDef *hpka, PKA_ECCProjective2AffineInTypeDef *in) +{ + /* Set input parameter in PKA RAM */ + PKA_ECCProjective2Affine_Set(hpka, in); + + return PKA_Process_IT(hpka, PKA_MODE_ECC_PROJECTIVE_AFF); +} + +/** + * @brief ECC complete addition in blocking mode. + * @param hpka PKA handle + * @param in Input information + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_ECCCompleteAddition(PKA_HandleTypeDef *hpka, PKA_ECCCompleteAdditionInTypeDef *in, + uint32_t Timeout) +{ + /* Set input parameter in PKA RAM */ + PKA_ECCCompleteAddition_Set(hpka, in); + + return PKA_Process(hpka, PKA_MODE_ECC_COMPLETE_ADD, Timeout); +} + +/** + * @brief ECC complete addition in non-blocking mode with Interrupt. + * @param hpka PKA handle + * @param in Input information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_ECCCompleteAddition_IT(PKA_HandleTypeDef *hpka, PKA_ECCCompleteAdditionInTypeDef *in) +{ + /* Set input parameter in PKA RAM */ + PKA_ECCCompleteAddition_Set(hpka, in); + + return PKA_Process_IT(hpka, PKA_MODE_ECC_COMPLETE_ADD); +} + +/** + * @brief Retrieve operation result. + * @param hpka PKA handle + * @param pRes pointer to buffer where the result will be copied + * @retval HAL status + */ +void HAL_PKA_MontgomeryParam_GetResult(PKA_HandleTypeDef *hpka, uint32_t *pRes) +{ + uint32_t size; + + /* Retrieve the size of the buffer from the PKA RAM */ + size = (hpka->Instance->RAM[PKA_MONTGOMERY_PARAM_IN_MOD_NB_BITS] + 31UL) / 32UL; + + /* Move the result to appropriate location (indicated in out parameter) */ + PKA_Memcpy_u32_to_u32(pRes, &hpka->Instance->RAM[PKA_MONTGOMERY_PARAM_OUT_PARAMETER], size); +} + +/** + * @brief Abort any ongoing operation. + * @param hpka PKA handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PKA_Abort(PKA_HandleTypeDef *hpka) +{ + HAL_StatusTypeDef err = HAL_OK; + + /* Clear EN bit */ + /* This abort any operation in progress (PKA RAM content is not guaranteed in this case) */ + CLEAR_BIT(hpka->Instance->CR, PKA_CR_EN); + SET_BIT(hpka->Instance->CR, PKA_CR_EN); + + /* Reset any pending flag */ + SET_BIT(hpka->Instance->CLRFR, PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC | PKA_CLRFR_ADDRERRFC | PKA_CLRFR_OPERRFC); + + /* Reset the error code */ + hpka->ErrorCode = HAL_PKA_ERROR_NONE; + + /* Reset the state */ + hpka->State = HAL_PKA_STATE_READY; + + return err; +} + +/** + * @brief Reset the PKA RAM. + * @param hpka PKA handle + * @retval None + */ +void HAL_PKA_RAMReset(PKA_HandleTypeDef *hpka) +{ + uint32_t index; + + /* For each element in the PKA RAM */ + for (index = 0; index < PKA_RAM_SIZE; index++) + { + /* Clear the content */ + hpka->Instance->RAM[index] = 0UL; + } +} + +/** + * @brief This function handles PKA event interrupt request. + * @param hpka PKA handle + * @retval None + */ +void HAL_PKA_IRQHandler(PKA_HandleTypeDef *hpka) +{ + uint32_t mode = PKA_GetMode(hpka); + uint32_t itsource = READ_REG(hpka->Instance->CR); + uint32_t flag = READ_REG(hpka->Instance->SR); + + /* Address error interrupt occurred */ + if (((itsource & PKA_IT_ADDRERR) == PKA_IT_ADDRERR) && ((flag & PKA_FLAG_ADDRERR) == PKA_FLAG_ADDRERR)) + { + hpka->ErrorCode |= HAL_PKA_ERROR_ADDRERR; + + /* Clear ADDRERR flag */ + __HAL_PKA_CLEAR_FLAG(hpka, PKA_FLAG_ADDRERR); + } + + /* RAM access error interrupt occurred */ + if (((itsource & PKA_IT_RAMERR) == PKA_IT_RAMERR) && ((flag & PKA_FLAG_RAMERR) == PKA_FLAG_RAMERR)) + { + hpka->ErrorCode |= HAL_PKA_ERROR_RAMERR; + + /* Clear RAMERR flag */ + __HAL_PKA_CLEAR_FLAG(hpka, PKA_FLAG_RAMERR); + } + + /* OPERATION access error interrupt occurred */ + if (((itsource & PKA_IT_OPERR) == PKA_IT_OPERR) && ((flag & PKA_FLAG_OPERR) == PKA_FLAG_OPERR)) + { + hpka->ErrorCode |= HAL_PKA_ERROR_OPERATION; + + /* Clear OPERR flag */ + __HAL_PKA_CLEAR_FLAG(hpka, PKA_FLAG_OPERR); + } + + /* Check the operation success in case of ECDSA signature */ + switch (mode) + { + case PKA_MODE_ECDSA_SIGNATURE : + /* If error output result is different from no error, operation need to be repeated */ + if (hpka->Instance->RAM[PKA_ECDSA_SIGN_OUT_ERROR] != PKA_NO_ERROR) + { + hpka->ErrorCode |= HAL_PKA_ERROR_OPERATION; + } + break; + + case PKA_MODE_DOUBLE_BASE_LADDER : + /* If error output result is different from no error, operation need to be repeated */ + if (hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_OUT_ERROR] != PKA_NO_ERROR) + { + hpka->ErrorCode |= HAL_PKA_ERROR_OPERATION; + } + break; + + case PKA_MODE_ECC_PROJECTIVE_AFF : + /* If error output result is different from no error, operation need to be repeated */ + if (hpka->Instance->RAM[PKA_ECC_PROJECTIVE_AFF_OUT_ERROR] != PKA_NO_ERROR) + { + hpka->ErrorCode |= HAL_PKA_ERROR_OPERATION; + } + break; + + case PKA_MODE_ECC_MUL : + /* If error output result is different from no error, operation need to be repeated */ + if (hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_OUT_ERROR] != PKA_NO_ERROR) + { + hpka->ErrorCode |= HAL_PKA_ERROR_OPERATION; + } + break; + + case PKA_MODE_MODULAR_EXP_PROTECT : + /* If error output result is different from no error, operation need to be repeated */ + if (hpka->Instance->RAM[PKA_MODULAR_EXP_OUT_ERROR] != PKA_NO_ERROR) + { + hpka->ErrorCode |= HAL_PKA_ERROR_OPERATION; + } + break; + default : + break; + } + /* Trigger the error callback if an error is present */ + if (hpka->ErrorCode != HAL_PKA_ERROR_NONE) + { +#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1) + hpka->ErrorCallback(hpka); +#else + HAL_PKA_ErrorCallback(hpka); +#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */ + } + + /* End Of Operation interrupt occurred */ + if (((itsource & PKA_IT_PROCEND) == PKA_IT_PROCEND) && ((flag & PKA_FLAG_PROCEND) == PKA_FLAG_PROCEND)) + { + /* Clear PROCEND flag */ + __HAL_PKA_CLEAR_FLAG(hpka, PKA_FLAG_PROCEND); + + /* Set the state to ready */ + hpka->State = HAL_PKA_STATE_READY; + +#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1) + hpka->OperationCpltCallback(hpka); +#else + HAL_PKA_OperationCpltCallback(hpka); +#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */ + } +} + +/** + * @brief Process completed callback. + * @param hpka PKA handle + * @retval None + */ +__weak void HAL_PKA_OperationCpltCallback(PKA_HandleTypeDef *hpka) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpka); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PKA_OperationCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Error callback. + * @param hpka PKA handle + * @retval None + */ +__weak void HAL_PKA_ErrorCallback(PKA_HandleTypeDef *hpka) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpka); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PKA_ErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup PKA_Exported_Functions_Group3 Peripheral State and Error functions + * @brief Peripheral State and Error functions + * + @verbatim + =============================================================================== + ##### Peripheral State and Error functions ##### + =============================================================================== + [..] + This subsection permit to get in run-time the status of the peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Return the PKA handle state. + * @param hpka PKA handle + * @retval HAL status + */ +HAL_PKA_StateTypeDef HAL_PKA_GetState(const PKA_HandleTypeDef *hpka) +{ + /* Return PKA handle state */ + return hpka->State; +} + +/** + * @brief Return the PKA error code. + * @param hpka PKA handle + * @retval PKA error code + */ +uint32_t HAL_PKA_GetError(const PKA_HandleTypeDef *hpka) +{ + /* Return PKA handle error code */ + return hpka->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup PKA_Private_Functions + * @{ + */ + +/** + * @brief Get PKA operating mode. + * @param hpka PKA handle + * @retval Return the current mode + */ +uint32_t PKA_GetMode(const PKA_HandleTypeDef *hpka) +{ + /* return the shifted PKA_CR_MODE value */ + return (uint32_t)(READ_BIT(hpka->Instance->CR, PKA_CR_MODE) >> PKA_CR_MODE_Pos); +} + +/** + * @brief Wait for operation completion or timeout. + * @param hpka PKA handle + * @param Timeout Timeout duration in millisecond. + * @param Tickstart Tick start value + * @retval HAL status + */ +HAL_StatusTypeDef PKA_PollEndOfOperation(const PKA_HandleTypeDef *hpka, uint32_t Timeout, uint32_t Tickstart) +{ + /* Wait for the end of operation or timeout */ + while ((hpka->Instance->SR & PKA_SR_PROCENDF) == 0UL) + { + /* Check if timeout is disabled (set to infinite wait) */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0UL)) + { + return HAL_TIMEOUT; + } + } + } + return HAL_OK; +} + +/** + * @brief Return a hal error code based on PKA error flags. + * @param hpka PKA handle + * @param mode PKA operating mode + * @retval error code + */ +uint32_t PKA_CheckError(const PKA_HandleTypeDef *hpka, uint32_t mode) +{ + uint32_t err = HAL_PKA_ERROR_NONE; + + /* Check RAMERR error */ + if (__HAL_PKA_GET_FLAG(hpka, PKA_FLAG_RAMERR) == SET) + { + err |= HAL_PKA_ERROR_RAMERR; + } + + /* Check ADDRERR error */ + if (__HAL_PKA_GET_FLAG(hpka, PKA_FLAG_ADDRERR) == SET) + { + err |= HAL_PKA_ERROR_ADDRERR; + } + + /* Check OPEERR error */ + if (__HAL_PKA_GET_FLAG(hpka, PKA_FLAG_OPERR) == SET) + { + err |= HAL_PKA_ERROR_OPERATION; + } + + /* Check the operation success in case of ECDSA signature */ + if (mode == PKA_MODE_ECDSA_SIGNATURE) + { +#define EDCSA_SIGN_NOERROR PKA_NO_ERROR + /* If error output result is different from no error, ecsa sign operation need to be repeated */ + if (hpka->Instance->RAM[PKA_ECDSA_SIGN_OUT_ERROR] != EDCSA_SIGN_NOERROR) + { + err |= HAL_PKA_ERROR_OPERATION; + } + } + + /* Check the operation success in case of ECC double base ladder*/ + if (mode == PKA_MODE_DOUBLE_BASE_LADDER) + { + /* If error output result is different from no error, PKA operation need to be repeated */ + if (hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_OUT_ERROR] != PKA_NO_ERROR) + { + err |= HAL_PKA_ERROR_OPERATION; + } + } + + /* Check the operation success in case of ECC projective to affine*/ + if (mode == PKA_MODE_ECC_PROJECTIVE_AFF) + { + /* If error output result is different from no error, PKA operation need to be repeated */ + if (hpka->Instance->RAM[PKA_ECC_PROJECTIVE_AFF_OUT_ERROR] != PKA_NO_ERROR) + { + err |= HAL_PKA_ERROR_OPERATION; + } + } + + /* Check the operation success in case of ECC Fp scalar multiplication*/ + if (mode == PKA_MODE_ECC_MUL) + { + /* If error output result is different from no error, PKA operation need to be repeated */ + if (hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_OUT_ERROR] != PKA_NO_ERROR) + { + err |= HAL_PKA_ERROR_OPERATION; + } + } + + /* Check the operation success in case of protected modular exponentiation*/ + if (mode == PKA_MODE_MODULAR_EXP_PROTECT) + { + /* If error output result is different from no error, PKA operation need to be repeated */ + if (hpka->Instance->RAM[PKA_MODULAR_EXP_OUT_ERROR] != PKA_NO_ERROR) + { + err |= HAL_PKA_ERROR_OPERATION; + } + } + + return err; +} + +/** + * @brief Get number of bits inside an array of u8. + * @param byteNumber Number of u8 inside the array + */ +uint32_t PKA_GetBitSize_u8(uint32_t byteNumber) +{ + /* Convert from number of uint8_t in an array to the associated number of bits in this array */ + return byteNumber * 8UL; +} + +/** + * @brief Get optimal number of bits inside an array of u8. + * @param byteNumber Number of u8 inside the array + * @param msb Most significant uint8_t of the array + */ +uint32_t PKA_GetOptBitSize_u8(uint32_t byteNumber, uint8_t msb) +{ + uint32_t position; + + position = 32UL - __CLZ(msb); + + return (((byteNumber - 1UL) * 8UL) + position); +} + +/** + * @brief Get number of bits inside an array of u32. + * @param wordNumber Number of u32 inside the array + */ +uint32_t PKA_GetBitSize_u32(uint32_t wordNumber) +{ + /* Convert from number of uint32_t in an array to the associated number of bits in this array */ + return wordNumber * 32UL; +} + +/** + * @brief Get number of uint8_t element in an array of bitSize bits. + * @param bitSize Number of bits in an array + */ +uint32_t PKA_GetArraySize_u8(uint32_t bitSize) +{ + /* Manage the non aligned on uint8_t bitsize: */ + /* 512 bits requires 64 uint8_t */ + /* 521 bits requires 66 uint8_t */ + return ((bitSize + 7UL) / 8UL); +} + +/** + * @brief Copy uint32_t array to uint8_t array to fit PKA number representation. + * @param dst Pointer to destination + * @param src Pointer to source + * @param n Number of uint8_t to copy + * @retval dst + */ +void PKA_Memcpy_u32_to_u8(uint8_t dst[], __IO const uint32_t src[], size_t n) +{ + if (dst != NULL) + { + if (src != NULL) + { + uint32_t index_uint32_t = 0UL; /* This index is used outside of the loop */ + + for (; index_uint32_t < (n / 4UL); index_uint32_t++) + { + /* Avoid casting from uint8_t* to uint32_t* by copying 4 uint8_t in a row */ + /* Apply __REV equivalent */ + uint32_t index_uint8_t = n - 4UL - (index_uint32_t * 4UL); + dst[index_uint8_t + 3UL] = (uint8_t)((src[index_uint32_t] & 0x000000FFU)); + dst[index_uint8_t + 2UL] = (uint8_t)((src[index_uint32_t] & 0x0000FF00U) >> 8UL); + dst[index_uint8_t + 1UL] = (uint8_t)((src[index_uint32_t] & 0x00FF0000U) >> 16UL); + dst[index_uint8_t + 0UL] = (uint8_t)((src[index_uint32_t] & 0xFF000000U) >> 24UL); + } + + /* Manage the buffers not aligned on uint32_t */ + if ((n % 4UL) == 1UL) + { + dst[0UL] = (uint8_t)((src[index_uint32_t] & 0x000000FFU)); + } + else if ((n % 4UL) == 2UL) + { + dst[1UL] = (uint8_t)((src[index_uint32_t] & 0x000000FFU)); + dst[0UL] = (uint8_t)((src[index_uint32_t] & 0x0000FF00U) >> 8UL); + } + else if ((n % 4UL) == 3UL) + { + dst[2UL] = (uint8_t)((src[index_uint32_t] & 0x000000FFU)); + dst[1UL] = (uint8_t)((src[index_uint32_t] & 0x0000FF00U) >> 8UL); + dst[0UL] = (uint8_t)((src[index_uint32_t] & 0x00FF0000U) >> 16UL); + } + else + { + /* The last element is already handle in the loop */ + } + } + } +} + +/** + * @brief Copy uint8_t array to uint32_t array to fit PKA number representation. + * @param dst Pointer to destination + * @param src Pointer to source + * @param n Number of uint8_t to copy (must be multiple of 4) + * @retval dst + */ +void PKA_Memcpy_u8_to_u32(__IO uint32_t dst[], const uint8_t src[], size_t n) +{ + if (dst != NULL) + { + if (src != NULL) + { + uint32_t index = 0UL; /* This index is used outside of the loop */ + + for (; index < (n / 4UL); index++) + { + /* Apply the equivalent of __REV from uint8_t to uint32_t */ + dst[index] = ((uint32_t)src[(n - (index * 4UL) - 1UL)]) \ + | ((uint32_t)src[(n - (index * 4UL) - 2UL)] << 8UL) \ + | ((uint32_t)src[(n - (index * 4UL) - 3UL)] << 16UL) \ + | ((uint32_t)src[(n - (index * 4UL) - 4UL)] << 24UL); + } + + /* Manage the buffers not aligned on uint32_t */ + if ((n % 4UL) == 1UL) + { + dst[index] = (uint32_t)src[(n - (index * 4UL) - 1UL)]; + } + else if ((n % 4UL) == 2UL) + { + dst[index] = ((uint32_t)src[(n - (index * 4UL) - 1UL)]) \ + | ((uint32_t)src[(n - (index * 4UL) - 2UL)] << 8UL); + } + else if ((n % 4UL) == 3UL) + { + dst[index] = ((uint32_t)src[(n - (index * 4UL) - 1UL)]) \ + | ((uint32_t)src[(n - (index * 4UL) - 2UL)] << 8UL) \ + | ((uint32_t)src[(n - (index * 4UL) - 3UL)] << 16UL); + } + else + { + /* The last element is already handle in the loop */ + } + } + } +} + +/** + * @brief Copy uint32_t array to uint32_t array. + * @param dst Pointer to destination + * @param src Pointer to source + * @param n Number of u32 to be handled + * @retval dst + */ +void PKA_Memcpy_u32_to_u32(__IO uint32_t dst[], __IO const uint32_t src[], size_t n) +{ + /* If a destination buffer is provided */ + if (dst != NULL) + { + /* If a source buffer is provided */ + if (src != NULL) + { + /* For each element in the array */ + for (uint32_t index = 0UL; index < n; index++) + { + /* Copy the content */ + dst[index] = src[index]; + } + } + } +} + +/** + * @brief Generic function to start a PKA operation in blocking mode. + * @param hpka PKA handle + * @param mode PKA operation + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef PKA_Process(PKA_HandleTypeDef *hpka, uint32_t mode, uint32_t Timeout) +{ + HAL_StatusTypeDef err = HAL_OK; + uint32_t tickstart; + + if (hpka->State == HAL_PKA_STATE_READY) + { + /* Set the state to busy */ + hpka->State = HAL_PKA_STATE_BUSY; + + /* Clear any pending error */ + hpka->ErrorCode = HAL_PKA_ERROR_NONE; + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + /* Set the mode and deactivate the interrupts */ + MODIFY_REG(hpka->Instance->CR, PKA_CR_MODE | PKA_CR_PROCENDIE | PKA_CR_RAMERRIE | PKA_CR_ADDRERRIE | PKA_CR_OPERRIE, + mode << PKA_CR_MODE_Pos); + + /* Start the computation */ + hpka->Instance->CR |= PKA_CR_START; + + /* Wait for the end of operation or timeout */ + if (PKA_PollEndOfOperation(hpka, Timeout, tickstart) != HAL_OK) + { + /* Abort any ongoing operation */ + CLEAR_BIT(hpka->Instance->CR, PKA_CR_EN); + + hpka->ErrorCode |= HAL_PKA_ERROR_TIMEOUT; + + /* Make ready for the next operation */ + SET_BIT(hpka->Instance->CR, PKA_CR_EN); + } + + /* Check error */ + hpka->ErrorCode |= PKA_CheckError(hpka, mode); + + /* Clear all flags */ + hpka->Instance->CLRFR |= (PKA_CLRFR_PROCENDFC | PKA_CLRFR_RAMERRFC | PKA_CLRFR_ADDRERRFC | PKA_CLRFR_OPERRFC); + + /* Set the state to ready */ + hpka->State = HAL_PKA_STATE_READY; + + /* Manage the result based on encountered errors */ + if (hpka->ErrorCode != HAL_PKA_ERROR_NONE) + { + err = HAL_ERROR; + } + } + else + { + err = HAL_ERROR; + } + return err; +} + +/** + * @brief Generic function to start a PKA operation in non-blocking mode with Interrupt. + * @param hpka PKA handle + * @param mode PKA operation + * @retval HAL status + */ +HAL_StatusTypeDef PKA_Process_IT(PKA_HandleTypeDef *hpka, uint32_t mode) +{ + HAL_StatusTypeDef err = HAL_OK; + + if (hpka->State == HAL_PKA_STATE_READY) + { + /* Set the state to busy */ + hpka->State = HAL_PKA_STATE_BUSY; + + /* Clear any pending error */ + hpka->ErrorCode = HAL_PKA_ERROR_NONE; + + /* Set the mode and activate interrupts */ + MODIFY_REG(hpka->Instance->CR, PKA_CR_MODE | PKA_CR_PROCENDIE | PKA_CR_RAMERRIE | PKA_CR_ADDRERRIE | PKA_CR_OPERRIE, + (mode << PKA_CR_MODE_Pos) | PKA_CR_PROCENDIE | PKA_CR_RAMERRIE | PKA_CR_ADDRERRIE | PKA_CR_OPERRIE); + + /* Start the computation */ + hpka->Instance->CR |= PKA_CR_START; + } + else + { + err = HAL_ERROR; + } + return err; +} + +/** + * @brief Set input parameters. + * @param hpka PKA handle + * @param in Input information + */ +void PKA_ModExp_Set(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef *in) +{ + /* Get the number of bit per operand */ + hpka->Instance->RAM[PKA_MODULAR_EXP_IN_OP_NB_BITS] = PKA_GetBitSize_u8(in->OpSize); + + /* Get the number of bit of the exponent */ + hpka->Instance->RAM[PKA_MODULAR_EXP_IN_EXP_NB_BITS] = PKA_GetBitSize_u8(in->expSize); + + /* Move the input parameters pOp1 to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_EXPONENT_BASE], in->pOp1, in->OpSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_EXPONENT_BASE + ((in->OpSize + 3UL) / 4UL)); + + /* Move the exponent to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_EXPONENT], in->pExp, in->expSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_EXPONENT + ((in->expSize + 3UL) / 4UL)); + + /* Move the modulus to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_MODULUS], in->pMod, in->OpSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_MODULUS + ((in->OpSize + 3UL) / 4UL)); +} + +/** + * @brief Set input parameters. + * @param hpka PKA handle + * @param in Input information + */ +void PKA_ModExpFastMode_Set(PKA_HandleTypeDef *hpka, PKA_ModExpFastModeInTypeDef *in) +{ + /* Get the number of bit per operand */ + hpka->Instance->RAM[PKA_MODULAR_EXP_IN_OP_NB_BITS] = PKA_GetBitSize_u8(in->OpSize); + + /* Get the number of bit of the exponent */ + hpka->Instance->RAM[PKA_MODULAR_EXP_IN_EXP_NB_BITS] = PKA_GetBitSize_u8(in->expSize); + + /* Move the input parameters pOp1 to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_EXPONENT_BASE], in->pOp1, in->OpSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_EXPONENT_BASE + (in->OpSize / 4UL)); + + /* Move the exponent to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_EXPONENT], in->pExp, in->expSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_EXPONENT + (in->expSize / 4UL)); + + /* Move the modulus to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_MODULUS], in->pMod, in->OpSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_MODULUS + (in->OpSize / 4UL)); + + /* Move the Montgomery parameter to PKA RAM */ + PKA_Memcpy_u32_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM], in->pMontgomeryParam, + in->OpSize / 4UL); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM + (in->OpSize / 4UL)); +} + +/** + * @brief Set input parameters. + * @param hpka PKA handle + * @param in Input information + */ +void PKA_ModExpProtectMode_Set(PKA_HandleTypeDef *hpka, PKA_ModExpProtectModeInTypeDef *in) +{ + /* Get the number of bit per operand */ + hpka->Instance->RAM[PKA_MODULAR_EXP_IN_OP_NB_BITS] = PKA_GetBitSize_u8(in->OpSize); + + /* Get the number of bit of the exponent */ + hpka->Instance->RAM[PKA_MODULAR_EXP_IN_EXP_NB_BITS] = PKA_GetBitSize_u8(in->expSize); + + /* Move the input parameters pOp1 to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE], in->pOp1, in->OpSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE + (in->OpSize / 4UL)); + + /* Move the exponent to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_PROTECT_IN_EXPONENT], in->pExp, in->expSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_PROTECT_IN_EXPONENT + (in->expSize / 4UL)); + + /* Move the modulus to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_PROTECT_IN_MODULUS], in->pMod, in->OpSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_PROTECT_IN_MODULUS + (in->OpSize / 4UL)); + + /* Move Phi value to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_PROTECT_IN_PHI], in->pPhi, in->OpSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_PROTECT_IN_PHI + (in->OpSize / 4UL)); +} + +/** + * @brief Set input parameters. + * @param hpka PKA handle + * @param in Input information + * @note If the modulus size is bigger than the hash size (with a curve SECP521R1 when using a SHA256 hash + * for example)the hash value should be written at the end of the buffer with zeros padding at beginning. + */ +void PKA_ECDSASign_Set(PKA_HandleTypeDef *hpka, PKA_ECDSASignInTypeDef *in) +{ + /* Get the prime order n length */ + hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_ORDER_NB_BITS] = PKA_GetOptBitSize_u8(in->primeOrderSize, *(in->primeOrder)); + + /* Get the modulus p length */ + hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_MOD_NB_BITS] = PKA_GetOptBitSize_u8(in->modulusSize, *(in->modulus)); + + /* Get the coefficient a sign */ + hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_A_COEFF_SIGN] = in->coefSign; + + /* Move the input parameters coefficient |a| to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_A_COEFF], in->coef, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_SIGN_IN_A_COEFF + ((in->modulusSize + 3UL) / 4UL)); + + /* Move the input parameters coefficient B to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_B_COEFF], in->coefB, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_SIGN_IN_B_COEFF + ((in->modulusSize + 3UL) / 4UL)); + + /* Move the input parameters modulus value p to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_MOD_GF], in->modulus, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_SIGN_IN_MOD_GF + ((in->modulusSize + 3UL) / 4UL)); + + /* Move the input parameters integer k to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_K], in->integer, in->primeOrderSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_SIGN_IN_K + ((in->primeOrderSize + 3UL) / 4UL)); + + /* Move the input parameters base point G coordinate x to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_INITIAL_POINT_X], in->basePointX, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_SIGN_IN_INITIAL_POINT_X + ((in->modulusSize + 3UL) / 4UL)); + + /* Move the input parameters base point G coordinate y to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y], in->basePointY, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y + ((in->modulusSize + 3UL) / 4UL)); + + /* Move the input parameters hash of message z to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_HASH_E], in->hash, in->primeOrderSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_SIGN_IN_HASH_E + ((in->primeOrderSize + 3UL) / 4UL)); + + /* Move the input parameters private key d to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D], in->privateKey, in->primeOrderSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D + ((in->primeOrderSize + 3UL) / 4UL)); + + /* Move the input parameters prime order n to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_ORDER_N], in->primeOrder, in->primeOrderSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_SIGN_IN_ORDER_N + ((in->primeOrderSize + 3UL) / 4UL)); +} + +/** + * @brief Set input parameters. + * @param hpka PKA handle + * @param in Input information + */ +void PKA_ECDSAVerif_Set(PKA_HandleTypeDef *hpka, PKA_ECDSAVerifInTypeDef *in) +{ + /* Get the prime order n length */ + hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_ORDER_NB_BITS] = PKA_GetOptBitSize_u8(in->primeOrderSize, *(in->primeOrder)); + + /* Get the modulus p length */ + hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_MOD_NB_BITS] = PKA_GetOptBitSize_u8(in->modulusSize, *(in->modulus)); + + /* Get the coefficient a sign */ + hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_A_COEFF_SIGN] = in->coefSign; + + /* Move the input parameters coefficient |a| to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_A_COEFF], in->coef, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_VERIF_IN_A_COEFF + ((in->modulusSize + 3UL) / 4UL)); + + /* Move the input parameters modulus value p to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_MOD_GF], in->modulus, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_VERIF_IN_MOD_GF + ((in->modulusSize + 3UL) / 4UL)); + + /* Move the input parameters base point G coordinate x to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_INITIAL_POINT_X], in->basePointX, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_VERIF_IN_INITIAL_POINT_X + ((in->modulusSize + 3UL) / 4UL)); + + /* Move the input parameters base point G coordinate y to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y], in->basePointY, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y + ((in->modulusSize + 3UL) / 4UL)); + + /* Move the input parameters public-key curve point Q coordinate xQ to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X], in->pPubKeyCurvePtX, + in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X + ((in->modulusSize + 3UL) / 4UL)); + + /* Move the input parameters public-key curve point Q coordinate xQ to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y], in->pPubKeyCurvePtY, + in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y + ((in->modulusSize + 3UL) / 4UL)); + + /* Move the input parameters signature part r to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_SIGNATURE_R], in->RSign, in->primeOrderSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_VERIF_IN_SIGNATURE_R + ((in->primeOrderSize + 3UL) / 4UL)); + + /* Move the input parameters signature part s to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_SIGNATURE_S], in->SSign, in->primeOrderSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_VERIF_IN_SIGNATURE_S + ((in->primeOrderSize + 3UL) / 4UL)); + + /* Move the input parameters hash of message z to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_HASH_E], in->hash, in->primeOrderSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_VERIF_IN_HASH_E + ((in->primeOrderSize + 3UL) / 4UL)); + + /* Move the input parameters curve prime order n to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_ORDER_N], in->primeOrder, in->primeOrderSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_VERIF_IN_ORDER_N + ((in->primeOrderSize + 3UL) / 4UL)); +} + +/** + * @brief Set input parameters. + * @param hpka PKA handle + * @param in Input information + */ +void PKA_RSACRTExp_Set(PKA_HandleTypeDef *hpka, PKA_RSACRTExpInTypeDef *in) +{ + /* Get the operand length M */ + hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_MOD_NB_BITS] = PKA_GetBitSize_u8(in->size); + + /* Move the input parameters operand dP to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_DP_CRT], in->pOpDp, in->size / 2UL); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_RSA_CRT_EXP_IN_DP_CRT + (in->size / 8UL)); + + /* Move the input parameters operand dQ to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_DQ_CRT], in->pOpDq, in->size / 2UL); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_RSA_CRT_EXP_IN_DQ_CRT + (in->size / 8UL)); + + /* Move the input parameters operand qinv to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_QINV_CRT], in->pOpQinv, in->size / 2UL); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_RSA_CRT_EXP_IN_QINV_CRT + (in->size / 8UL)); + + /* Move the input parameters prime p to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_PRIME_P], in->pPrimeP, in->size / 2UL); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_RSA_CRT_EXP_IN_PRIME_P + (in->size / 8UL)); + + /* Move the input parameters prime q to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_PRIME_Q], in->pPrimeQ, in->size / 2UL); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_RSA_CRT_EXP_IN_PRIME_Q + (in->size / 8UL)); + + /* Move the input parameters operand A to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_EXPONENT_BASE], in->popA, in->size); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_RSA_CRT_EXP_IN_EXPONENT_BASE + (in->size / 4UL)); +} + +/** + * @brief Set input parameters. + * @param hpka PKA handle + * @param in Input information + */ +void PKA_PointCheck_Set(PKA_HandleTypeDef *hpka, PKA_PointCheckInTypeDef *in) +{ + /* Get the modulus length */ + hpka->Instance->RAM[PKA_POINT_CHECK_IN_MOD_NB_BITS] = PKA_GetOptBitSize_u8(in->modulusSize, *(in->modulus)); + + /* Get the coefficient a sign */ + hpka->Instance->RAM[PKA_POINT_CHECK_IN_A_COEFF_SIGN] = in->coefSign; + + /* Move the input parameters coefficient |a| to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_POINT_CHECK_IN_A_COEFF], in->coefA, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_POINT_CHECK_IN_A_COEFF + ((in->modulusSize + 3UL) / 4UL)); + + /* Move the input parameters coefficient b to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_POINT_CHECK_IN_B_COEFF], in->coefB, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_POINT_CHECK_IN_B_COEFF + ((in->modulusSize + 3UL) / 4UL)); + + /* Move the input parameters modulus value p to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_POINT_CHECK_IN_MOD_GF], in->modulus, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_POINT_CHECK_IN_MOD_GF + ((in->modulusSize + 3UL) / 4UL)); + + /* Move the input parameters Point P coordinate x to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_POINT_CHECK_IN_INITIAL_POINT_X], in->pointX, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_POINT_CHECK_IN_INITIAL_POINT_X + ((in->modulusSize + 3UL) / 4UL)); + + /* Move the input parameters Point P coordinate y to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_POINT_CHECK_IN_INITIAL_POINT_Y], in->pointY, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_POINT_CHECK_IN_INITIAL_POINT_Y + ((in->modulusSize + 3UL) / 4UL)); + + /* Move the input parameters montgomery param R2 modulus N to PKA RAM */ + PKA_Memcpy_u32_to_u32(&hpka->Instance->RAM[PKA_POINT_CHECK_IN_MONTGOMERY_PARAM], in->pMontgomeryParam, + (in->modulusSize / 4UL)); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_POINT_CHECK_IN_MONTGOMERY_PARAM + ((in->modulusSize + 3UL) / 4UL)); +} + +/** + * @brief Set input parameters. + * @param hpka PKA handle + * @param in Input information + */ +void PKA_ECCMul_Set(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in) +{ + /* Get the prime order n length */ + hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS] = PKA_GetOptBitSize_u8(in->scalarMulSize, *(in->primeOrder)); + + /* Get the modulus length */ + hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS] = PKA_GetOptBitSize_u8(in->modulusSize, *(in->modulus)); + + /* Get the coefficient a sign */ + hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN] = in->coefSign; + + /* Move the input parameters coefficient |a| to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_A_COEFF], in->coefA, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_A_COEFF + ((in->modulusSize + 3UL) / 4UL)); + + /* Move the input parameters coefficient b to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_B_COEFF], in->coefB, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_B_COEFF + ((in->modulusSize + 3UL) / 4UL)); + + /* Move the input parameters modulus value p to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_MOD_GF], in->modulus, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_MOD_GF + ((in->modulusSize + 3UL) / 4UL)); + + /* Move the input parameters scalar multiplier k to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_K], in->scalarMul, in->scalarMulSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_K + ((in->scalarMulSize + 3UL) / 4UL)); + + /* Move the input parameters Point P coordinate x to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X], in->pointX, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X + ((in->modulusSize + 3UL) / 4UL)); + + /* Move the input parameters Point P coordinate y to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y], in->pointY, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y + ((in->modulusSize + 3UL) / 4UL)); + + /* Move the input parameters curve prime order N to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER], in->primeOrder, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER + ((in->modulusSize + 3UL) / 4UL)); +} +/** + * @brief Set input parameters. + * @param hpka PKA handle + * @param in Input information + */ +void PKA_ECCMulEx_Set(PKA_HandleTypeDef *hpka, PKA_ECCMulExInTypeDef *in) +{ + /* Get the prime order n length */ + hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS] = PKA_GetOptBitSize_u8(in->primeOrderSize, *(in->primeOrder)); + + /* Get the modulus length */ + hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS] = PKA_GetOptBitSize_u8(in->modulusSize, *(in->modulus)); + + /* Get the coefficient a sign */ + hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN] = in->coefSign; + + /* Move the input parameters coefficient |a| to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_A_COEFF], in->coefA, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_A_COEFF + ((in->modulusSize + 3UL) / 4UL)); + + /* Move the input parameters coefficient b to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_B_COEFF], in->coefB, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_B_COEFF + ((in->modulusSize + 3UL) / 4UL)); + + /* Move the input parameters modulus value p to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_MOD_GF], in->modulus, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_MOD_GF + ((in->modulusSize + 3UL) / 4UL)); + + /* Move the input parameters scalar multiplier k to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_K], in->scalarMul, in->scalarMulSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_K + ((in->scalarMulSize + 3UL) / 4UL)); + + /* Move the input parameters Point P coordinate x to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X], in->pointX, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X + ((in->modulusSize + 3UL) / 4UL)); + + /* Move the input parameters Point P coordinate y to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y], in->pointY, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y + ((in->modulusSize + 3UL) / 4UL)); + + /* Move the input parameters curve prime order N to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER], in->primeOrder, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER + ((in->modulusSize + 3UL) / 4UL)); +} + +/** + * @brief Set input parameters. + * @param hpka PKA handle + * @param in Input information + */ +void PKA_ModInv_Set(PKA_HandleTypeDef *hpka, PKA_ModInvInTypeDef *in) +{ + /* Get the number of bit per operand */ + hpka->Instance->RAM[PKA_MODULAR_INV_NB_BITS] = PKA_GetBitSize_u32(in->size); + + /* Move the input parameters operand A to PKA RAM */ + PKA_Memcpy_u32_to_u32(&hpka->Instance->RAM[PKA_MODULAR_INV_IN_OP1], in->pOp1, in->size); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_INV_IN_OP1 + in->size); + + /* Move the input parameters modulus value n to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_INV_IN_OP2_MOD], in->pMod, in->size * 4UL); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_INV_IN_OP2_MOD + in->size); +} + +/** + * @brief Set input parameters. + * @param hpka PKA handle + * @param in Input information + */ +void PKA_ModRed_Set(PKA_HandleTypeDef *hpka, PKA_ModRedInTypeDef *in) +{ + /* Get the number of bit per operand */ + hpka->Instance->RAM[PKA_MODULAR_REDUC_IN_OP_LENGTH] = PKA_GetBitSize_u32(in->OpSize); + + /* Get the number of bit per modulus */ + hpka->Instance->RAM[PKA_MODULAR_REDUC_IN_MOD_LENGTH] = PKA_GetBitSize_u8(in->modSize); + + /* Move the input parameters operand A to PKA RAM */ + PKA_Memcpy_u32_to_u32(&hpka->Instance->RAM[PKA_MODULAR_REDUC_IN_OPERAND], in->pOp1, in->OpSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_REDUC_IN_OPERAND + in->OpSize); + + /* Move the input parameters modulus value n to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_REDUC_IN_MODULUS], in->pMod, in->modSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_REDUC_IN_MODULUS + ((in->modSize + 3UL) / 4UL)); +} + +/** + * @brief Set input parameters. + * @param hpka PKA handle + * @param size Size of the operand + * @param pOp1 Generic pointer to input data + */ +void PKA_MontgomeryParam_Set(PKA_HandleTypeDef *hpka, const uint32_t size, const uint8_t *pOp1) +{ + uint32_t bytetoskip = 0UL; + uint32_t newSize; + + if (pOp1 != NULL) + { + /* Count the number of zero bytes */ + while ((bytetoskip < size) && (pOp1[bytetoskip] == 0UL)) + { + bytetoskip++; + } + + /* Get new size after skipping zero bytes */ + newSize = size - bytetoskip; + + /* Get the number of bit per operand */ + hpka->Instance->RAM[PKA_MONTGOMERY_PARAM_IN_MOD_NB_BITS] = PKA_GetOptBitSize_u8(newSize, pOp1[bytetoskip]); + + /* Move the input parameters pOp1 to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MONTGOMERY_PARAM_IN_MODULUS], pOp1, size); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MONTGOMERY_PARAM_IN_MODULUS + ((size + 3UL) / 4UL)); + } +} + +/** + * @brief Set input parameters. + * @param hpka PKA handle + * @param in Input information + */ +void PKA_ECCDoubleBaseLadder_Set(PKA_HandleTypeDef *hpka, PKA_ECCDoubleBaseLadderInTypeDef *in) +{ + /* Get the prime order n length */ + hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS] = PKA_GetBitSize_u8(in->primeOrderSize); + + /* Get the modulus p length */ + hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS] = PKA_GetBitSize_u8(in->modulusSize); + + /* Get the coefficient a sign */ + hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN] = in->coefSign; + + /* Move the input parameters coefficient |a| to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_A_COEFF], in->coefA, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_DOUBLE_LADDER_IN_A_COEFF + (in->modulusSize / 4UL)); + + /* Move the input parameters modulus value p to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_MOD_P], in->modulus, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_DOUBLE_LADDER_IN_MOD_P + (in->modulusSize / 4UL)); + + /* Move the input parameters integer k to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER], in->integerK, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER + (in->modulusSize / 4UL)); + + /* Move the input parameters integer m to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER], in->integerM, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER + (in->modulusSize / 4UL)); + + /* Move the input parameters first point coordinate x to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_POINT1_X], in->basePointX1, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_DOUBLE_LADDER_IN_POINT1_X + (in->modulusSize / 4UL)); + + /* Move the input parameters first point coordinate y to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y], in->basePointY1, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y + (in->modulusSize / 4UL)); + + /* Move the input parameters first point coordinate z to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z], in->basePointZ1, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z + (in->modulusSize / 4UL)); + + /* Move the input parameters second point coordinate x to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_POINT2_X], in->basePointX2, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_DOUBLE_LADDER_IN_POINT2_X + (in->modulusSize / 4UL)); + + /* Move the input parameters second point coordinate y to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y], in->basePointY2, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y + (in->modulusSize / 4UL)); + + /* Move the input parameters second point coordinate z to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z], in->basePointZ2, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z + (in->modulusSize / 4UL)); +} + +/** + * @brief Retrieve operation result. + * @param hpka PKA handle + * @param out Output information + * @retval HAL status + */ +void HAL_PKA_ECCDoubleBaseLadder_GetResult(PKA_HandleTypeDef *hpka, PKA_ECCDoubleBaseLadderOutTypeDef *out) +{ + uint32_t size; + + /* Move the result to appropriate location (indicated in out parameter) */ + size = hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS] / 8UL; + if (out != NULL) + { + PKA_Memcpy_u32_to_u8(out->ptX, &hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X], size); + PKA_Memcpy_u32_to_u8(out->ptY, &hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y], size); + } +} + +/** + * @brief Set input parameters. + * @param hpka PKA handle + * @param in Input information + */ +void PKA_ECCProjective2Affine_Set(PKA_HandleTypeDef *hpka, PKA_ECCProjective2AffineInTypeDef *in) +{ + /* Get the modulus p length */ + hpka->Instance->RAM[PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS] = PKA_GetBitSize_u8(in->modulusSize); + + /* Move the input parameters modulus value p to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_PROJECTIVE_AFF_IN_MOD_P], in->modulus, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_PROJECTIVE_AFF_IN_MOD_P + (in->modulusSize / 4UL)); + + /* Move the input parameters point coordinate x to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_PROJECTIVE_AFF_IN_POINT_X], in->basePointX, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_PROJECTIVE_AFF_IN_POINT_X + (in->modulusSize / 4UL)); + + /* Move the input parameters point coordinate y to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y], in->basePointY, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y + (in->modulusSize / 4UL)); + + /* Move the input parameters point coordinate z to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z], in->basePointZ, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z + (in->modulusSize / 4UL)); + + /* Move the input parameters montgomery parameter R2 modulus n to PKA RAM */ + PKA_Memcpy_u32_to_u32(&hpka->Instance->RAM[PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2], in->pMontgomeryParam, + (in->modulusSize / 4UL)); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2 + (in->modulusSize / 4UL)); +} + +/** + * @brief Retrieve operation result. + * @param hpka PKA handle + * @param out Output information + * @retval HAL status + */ +void HAL_PKA_ECCProjective2Affine_GetResult(PKA_HandleTypeDef *hpka, PKA_ECCProjective2AffineOutTypeDef *out) +{ + uint32_t size; + + /* Move the result to appropriate location (indicated in out parameter) */ + size = hpka->Instance->RAM[PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS] / 8UL; + if (out != NULL) + { + PKA_Memcpy_u32_to_u8(out->ptX, &hpka->Instance->RAM[PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X], size); + PKA_Memcpy_u32_to_u8(out->ptY, &hpka->Instance->RAM[PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y], size); + } +} + +/** + * @brief Set input parameters. + * @param hpka PKA handle + * @param in Input information + */ +void PKA_ECCCompleteAddition_Set(PKA_HandleTypeDef *hpka, PKA_ECCCompleteAdditionInTypeDef *in) +{ + /* Get the modulus p length */ + hpka->Instance->RAM[PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS] = PKA_GetBitSize_u8(in->modulusSize); + + /* Get the coefficient a sign */ + hpka->Instance->RAM[PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN] = in->coefSign; + + /* Move the input parameters modulus value p to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_COMPLETE_ADD_IN_MOD_P], in->modulus, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_COMPLETE_ADD_IN_MOD_P + (in->modulusSize / 4UL)); + + /* Move the input parameters coefA value to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_COMPLETE_ADD_IN_A_COEFF], in->coefA, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_COMPLETE_ADD_IN_A_COEFF + (in->modulusSize / 4UL)); + + /* Move the input parameters first point x value to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_COMPLETE_ADD_IN_POINT1_X], in->basePointX1, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_COMPLETE_ADD_IN_POINT1_X + (in->modulusSize / 4UL)); + + /* Move the input parameters first point y value to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_COMPLETE_ADD_IN_POINT1_Y], in->basePointY1, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_COMPLETE_ADD_IN_POINT1_Y + (in->modulusSize / 4UL)); + + /* Move the input parameters first point z value to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_COMPLETE_ADD_IN_POINT1_Z], in->basePointZ1, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_COMPLETE_ADD_IN_POINT1_Z + (in->modulusSize / 4UL)); + + /* Move the input parameters second point x value to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_COMPLETE_ADD_IN_POINT2_X], in->basePointX2, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_COMPLETE_ADD_IN_POINT2_X + (in->modulusSize / 4UL)); + + /* Move the input parameters second point y value to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_COMPLETE_ADD_IN_POINT2_Y], in->basePointY2, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_COMPLETE_ADD_IN_POINT2_Y + (in->modulusSize / 4UL)); + + /* Move the input parameters second point z value to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_COMPLETE_ADD_IN_POINT2_Z], in->basePointZ2, in->modulusSize); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_COMPLETE_ADD_IN_POINT2_Z + (in->modulusSize / 4UL)); +} + +/** + * @brief Retrieve operation result. + * @param hpka PKA handle + * @param out Output information + * @retval HAL status + */ +void HAL_PKA_ECCCompleteAddition_GetResult(PKA_HandleTypeDef *hpka, PKA_ECCCompleteAdditionOutTypeDef *out) +{ + uint32_t size; + + /* Move the result to appropriate location (indicated in out parameter) */ + size = (hpka->Instance->RAM[PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS] + 7UL) / 8UL; + if (out != NULL) + { + PKA_Memcpy_u32_to_u8(out->ptX, &hpka->Instance->RAM[PKA_ECC_COMPLETE_ADD_OUT_RESULT_X], size); + PKA_Memcpy_u32_to_u8(out->ptY, &hpka->Instance->RAM[PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y], size); + PKA_Memcpy_u32_to_u8(out->ptZ, &hpka->Instance->RAM[PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z], size); + } +} +/** + * @brief Generic function to set input parameters. + * @param hpka PKA handle + * @param size Size of the operand + * @param pOp1 Generic pointer to input data + * @param pOp2 Generic pointer to input data + * @param pOp3 Generic pointer to input data + */ +void PKA_ARI_Set(PKA_HandleTypeDef *hpka, const uint32_t size, const uint32_t *pOp1, const uint32_t *pOp2, + const uint8_t *pOp3) +{ + /* Get the number of bit per operand */ + hpka->Instance->RAM[PKA_ARITHMETIC_ALL_OPS_NB_BITS] = PKA_GetBitSize_u32(size); + + if (pOp1 != NULL) + { + /* Move the input parameters pOp1 to PKA RAM */ + PKA_Memcpy_u32_to_u32(&hpka->Instance->RAM[PKA_ARITHMETIC_ALL_OPS_IN_OP1], pOp1, size); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ARITHMETIC_ALL_OPS_IN_OP1 + size); + } + + if (pOp2 != NULL) + { + /* Move the input parameters pOp2 to PKA RAM */ + PKA_Memcpy_u32_to_u32(&hpka->Instance->RAM[PKA_ARITHMETIC_ALL_OPS_IN_OP2], pOp2, size); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ARITHMETIC_ALL_OPS_IN_OP2 + size); + } + + if (pOp3 != NULL) + { + /* Move the input parameters pOp3 to PKA RAM */ + PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ARITHMETIC_ALL_OPS_IN_OP3], pOp3, size * 4UL); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ARITHMETIC_ALL_OPS_IN_OP3 + size); + } +} +/** + * @brief Handle PKA init Timeout. + * @param hpka PKA handle. + * @param Flag Specifies the PKA flag to check + * @param Status Flag status (SET or RESET) + * @param Tickstart Tick start value + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef PKA_WaitOnFlagUntilTimeout(PKA_HandleTypeDef *hpka, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout) +{ + /* Wait until flag is set */ + while (__HAL_PKA_GET_FLAG(hpka, Flag) == Status) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + /* Set the state to ready */ + hpka->State = HAL_PKA_STATE_READY; + + /* Set the error code to timeout error */ + hpka->ErrorCode = HAL_PKA_ERROR_TIMEOUT; + + return HAL_TIMEOUT; + } + } + } + return HAL_OK; +} + +/** + * @brief Get the size of output result. + * @param hpka PKA handle + * @param Startindex Specifies the start index of the result in the PKA RAM + * @param Maxsize Specifies the possible max size of the result in words + * @retval size + */ +uint32_t PKA_Result_GetSize(const PKA_HandleTypeDef *hpka, uint32_t Startindex, uint32_t Maxsize) +{ + uint32_t size; + uint32_t current_index = Maxsize - 1UL; + + /* Determinate the last index of the result in the PKA RAM */ + while ((hpka->Instance->RAM[Startindex + current_index] == 0UL) && (current_index != 0UL)) + { + current_index--; + } + /* Get the size in bytes */ + size = (current_index + 1UL) * 4UL; + + return size; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(PKA) && defined(HAL_PKA_MODULE_ENABLED) */ + +/** + * @} + */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_pwr.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_pwr.c new file mode 100644 index 0000000000..0bb4c5bfb0 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_pwr.c @@ -0,0 +1,1149 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_pwr.c + * @author MCD Application Team + * @brief PWR HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Power Controller (PWR) peripheral: + * + Initialization/De-Initialization Functions. + * + Peripheral Control Functions. + * + PWR Attributes Functions. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### PWR peripheral overview ##### + ============================================================================== + [..] + (#) The Power control (PWR) provides an overview of the supply architecture + for the different power domains and of the supply configuration + controller. + + (#) Every entity has low power mode as described below : + (#) The CPU low power modes are : + (+) CPU CRun. + (+) CPU CSleep. + (+) CPU CStop. + (#) The Core low power modes are : + (+) Run. + (+) Stop 0. + (+) Stop 1. + (+) Standby with retention + (+) Standby. + + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) After startup, power management peripheral is not active by default. Use + __HAL_RCC_PWR_CLK_ENABLE() macro to enable power interface. + + (#) Call HAL_PWR_EnableBkUpAccess() and HAL_PWR_DisableBkUpAccess() functions + to enable/disable access to the backup domain (RCC Backup domain control + register RCC_BDCR, RTC registers, TAMP registers, backup registers and + backup SRAM). + + (#) Call HAL_PWR_ConfigPVD() after setting parameters to be configured (event + mode and voltage threshold) in order to set up the Programmed Voltage + Detector, then use HAL_PWR_EnablePVD() and HAL_PWR_DisablePVD() + functions to start and stop the PVD detection. + (+) PVD level can be one of the following values : + (++) 2V0 + (++) 2V2 + (++) 2V4 + (++) 2V5 + (++) 2V6 + (++) 2V8 + (++) 2V9 + (++) External input analog voltage PVD_IN (compared internally to + VREFINT) + + (#) Call HAL_PWR_EnableWakeUpPin() and HAL_PWR_DisableWakeUpPin() functions + with the right parameter to configure the wake up pin polarity (Low or + High), the wake up pin selection and to enable and disable it. + + (#) Call HAL_PWR_EnterSLEEPMode() function to enter the CPU in Sleep mode. + Wake-up from Sleep mode could be following to an event or an + interrupt according to low power mode intrinsic request called (__WFI() + or __WFE()). + + (#) Call HAL_PWR_EnterSTOPMode() function to enter the whole system to Stop + mode. Wake-up from Stop mode could be following to an event or an + interrupt according to low power mode intrinsic request called (__WFI() + or __WFE()). + + (#) Call HAL_PWR_EnterSTANDBYMode() function to enter the whole system in + Standby mode. Wake-up from Standby mode can be following only by an + interrupt. + + (#) Call HAL_PWR_EnableSleepOnExit() and HAL_PWR_DisableSleepOnExit() APIs to + enable and disable the Cortex-M33 re-entry in Sleep mode after an + interruption handling is over. + + (#) Call HAL_PWR_EnableSEVOnPend() and HAL_PWR_DisableSEVOnPend() functions + to configure the Cortex-M33 to wake-up after any pending event / interrupt + even if it's disabled or has insufficient priority to cause exception + entry. + + (#) Call HAL_PWR_PVD_IRQHandler() under PVD_IRQHandler() function to + handle the PWR PVD interrupt request. + + (#) Call HAL_PWR_WAKEUP_PIN_IRQHandler() function to handle all wake-up + pins interrupts. + + (#) Call HAL_PWR_ConfigAttributes() function to configure PWR item secure and + privilege attributes and call HAL_PWR_GetConfigAttributes() function to + get the attribute configuration for the selected item. + + *** PWR HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in PWR HAL driver. + + (+) __HAL_PWR_GET_FLAG() : Get the PWR pending flags. + (+) __HAL_PWR_CLEAR_FLAG() : Clear the PWR pending flags. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @defgroup PWR PWR + * @brief PWR HAL module driver + * @{ + */ + +#if defined(HAL_PWR_MODULE_ENABLED) + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/** @defgroup PWR_Private_Defines PWR Private Defines + * @{ + */ + +/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask + * @{ + */ +#define PVD_RISING_EDGE (0x01U) /*!< Mask for rising edge set as PVD trigger */ +#define PVD_FALLING_EDGE (0x02U) /*!< Mask for falling edge set as PVD trigger */ +#define PVD_MODE_IT (0x04U) /*!< Mask for interruption yielded by PVD threshold crossing */ +#define PVD_MODE_EVT (0x08U) /*!< Mask for event yielded by PVD threshold crossing */ +/** + * @} + */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup PWR_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @defgroup PWR_Exported_Functions_Group1 Initialization and De-Initialization Functions + * @brief Initialization and de-Initialization functions + * +@verbatim + =============================================================================== + ##### Initialization and De-Initialization Functions ##### + =============================================================================== + [..] + This section provides functions allowing to deinitialize power peripheral. + + [..] + After system reset, the backup domain (RCC Backup domain control register + RCC_BDCR, RTC registers, TAMP registers, backup registers and backup SRAM) + is protected against possible unwanted write accesses. + The HAL_PWR_EnableBkUpAccess() function enables the access to the backup + domain. + The HAL_PWR_DisableBkUpAccess() function disables the access to the backup + domain. + +@endverbatim + * @{ + */ + +/** + * @brief Deinitialize the HAL PWR peripheral registers to their default reset + * values. + * @note This functionality is not available in this product. + * The prototype is kept just to maintain compatibility with other + * products. + * @retval None. + */ +void HAL_PWR_DeInit(void) +{ +} + +/** + * @brief Enable access to the backup domain (RCC Backup domain control + * register RCC_BDCR, RTC registers, TAMP registers, backup registers + * and backup SRAM). + * @note After a system reset, the backup domain is protected against + * possible unwanted write accesses. + * @retval None. + */ +void HAL_PWR_EnableBkUpAccess(void) +{ + SET_BIT(PWR->DBPR, PWR_DBPR_DBP); +} + +/** + * @brief Disable access to the backup domain (RCC Backup domain control + * register RCC_BDCR, RTC registers, TAMP registers, backup registers + * and backup SRAM). + * @retval None. + */ +void HAL_PWR_DisableBkUpAccess(void) +{ + CLEAR_BIT(PWR->DBPR, PWR_DBPR_DBP); +} +/** + * @} + */ + + +/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control Functions + * @brief Low power modes configuration functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This section provides functions allowing to control power peripheral. + + *** PVD configuration *** + ========================= + [..] + (+) The PVD can be used to monitor the VDD power supply by comparing it + to a threshold selected by the PVDLS[2:0] bits in the PWR supply + voltage monitoring control register (PWR_SVMCR) and can be enabled by + setting the PVDE bit. + + (+) A PVDO flag is available in the PWR supply voltage monitoring control + register (PWR_SVMCR) to indicate if VDD is higher or lower than the + PVD threshold. This event is internally connected to the EXTI line 16 + and can generate an interrupt if enabled through the EXTI registers. + It is configurable through __HAL_PWR_PVD_EXTI_ENABLE_IT() macro. + + (+) The PVD can remain active in Stop 0 and Stop 1 modes. The PVD + is not functional in Standby mode. + + (+) During Stop 0 and Stop 1 modes, it is possible to set the PVD + in ultra-low-power mode to further reduce the current consumption by + setting the ULPMEN bit in PWR_CR1 register. + + *** Wake-up pin configuration *** + ================================= + [..] + (+) Wake-up pin is used to wake up the system from Standby mode. + The pin selection is configurable through the WUCR3 register to map + internal signal to wake up pin line. + The pin polarity is configurable through the WUCR2 register to be + active on rising or falling edges. + + (+) There are up to 19 wake-up signals that can be mapped to up to 8 + wake-up lines in the STM32WBA family. + + (+) When a wakeup pin event is received the HAL_PWR_WAKEUP_PIN_IRQHandler + is called and the appropriate flag is set in the PWR_WKUPFR register. + Then in the HAL_PWR_WAKEUP_PIN_IRQHandler function the wakeup pin flag + will be cleared and the appropriate user callback will be called. + The user can add his own code by customization of function pointer + HAL_PWR_WKUPx_Callback. + + *** Low Power modes configuration *** + ===================================== + [..] + This section presents 4 principles low-power modes : + (+) Sleep mode : Cortex-M33 is stopped and all PWR domains are remaining + active (powered and clocked). + + (+) Stop 0 mode : Cortex-M33 is stopped, clocks are stopped and the + main regulator is running. + + (+) Stop 1 mode : Cortex-M33 is stopped, clocks are stopped and the + regulator is in low power mode. Several peripheral can + operate in this mode. + + (+) Standby mode : Cortex-M33 is in SleepDeep mode and the voltage + supply regulator is powered off. + + *** Sleep mode *** + ================== + [..] + (+) Entry : + The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode() + function. + + (++) PWR_SLEEPENTRY_WFI: enter Sleep mode with WFI instruction. + (++) PWR_SLEEPENTRY_WFE: enter Sleep mode with WFE instruction. + + -@@- The Regulator parameter is not used for the STM32WBA family and is + kept as parameter just to maintain compatibility with other families. + + (+) Exit : + According to Sleep entry, any event when entry is __WFE() intrinsic + and any interrupt when entry is __WFI() intrinsic can wake up the + device from Sleep mode. + + *** Stop 0 & Stop 1 modes *** + =================== + [..] + The Stop 0 and Stop 1 mode are based on the Cortex-M33 Deepsleep mode combined with + the peripheral clock gating. + In Stop 0 mode, the voltage regulator is configured in main. + In Stop 1 mode, The voltage regulator is configured in low power mode. + all clocks in the VCORE domain are stopped. + In Stop mode 0 the PLL, HSI16 and HSE32 oscillators are disabled. + Some peripherals with the LPBAM capability can switch on HSI16 or HSE32 for + transferring data. All SRAMs and register contents are preserved, + but the SRAMs can totally or not be switched off to further reduce + consumption. + The BOR is always available in Stop mode. + + (+) Entry: + The Stop mode is entered using the HAL_PWR_EnterSTOPMode() function + with : + (++) Regulator: + (+++) PWR_MAINREGULATOR_ON : Main regulator ON (Stop 0 mode). + (+++) PWR_LOWPOWERREGULATOR_ON : Low power regulator ON (Stop 1 mode). + + (++) STOPEntry: + (+++) PWR_STOPENTRY_WFI: enter Stop mode with WFI instruction. + (+++) PWR_STOPENTRY_WFE: enter Stop mode with WFE instruction. + + (+) Exit: + Any EXTI line configured in interrupt mode (the corresponding EXTI + interrupt vector must be enabled in the NVIC). The interrupt source + can be external interrupts or peripherals with wakeup capability. + Any peripheral interrupt occurring when the AHB/APB clocks are present + due to an autonomous peripheral clock request (the peripheral vector + must be enabled in the NVIC). + Any EXTI line configured in event mode. + + *** Standby mode *** + ==================== + [..] + The Standby mode is used to achieve the lowest power consumption with BOR. + The internal regulator is switched off so that the VCORE domain is powered + off. + The PLL, the HSI16 RC and the HSE32 crystal oscillators are also switched off. + The RTC can remain active (Standby mode with RTC, Standby mode without + RTC). + The Brownout reset (BOR) always remains active in Standby mode. + The state of each I/O during Standby mode can be selected by software: + I/O with internal pull-up, internal pull-down or floating. + After entering Standby mode, SRAMs and register contents are lost except + for registers and backup SRAM in the Backup domain and Standby circuitry. + Optionally, the full SRAM1 and SRAM2 can be retained in Standby mode depending + on R1RSB1 and R2RSB1 bit configuration in PWR_CR1. In this case, the low-power + regulator is ON and provides the supply to SRAM1 and or SRAM2. Also the 2.4 + GHz RADIO SRAMs can be retained, and the sleep timer kept operational depending + on RADIOSB bit configuration in PWR_CR1. + The BORL (Brownout reset detector low) can be configured in ultra low + power mode to further reduce power consumption during Standby mode. + The device exits Standby mode when an external reset (NRST pin), an IWDG + reset, WKUP pin event (configurable rising or falling edge), an RTC event + occurs (alarm, periodic wakeup, timestamp), or a tamper detection. + The system clock after wakeup is HSI16. + + (++) Entry: + The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() + function. + + (++) Exit: + WKUPx pin edge, RTC event, external Reset in NRST pin, IWDG Reset, + BOR reset. + +@endverbatim + * @{ + */ + +/** + * @brief Configure the voltage threshold detected by the Programmed Voltage + * Detector (PVD). + * @param sConfigPVD : Pointer to a PWR_PVDTypeDef structure that contains the + * PVD configuration information (PVDLevel and EventMode). + * @retval None. + */ +HAL_StatusTypeDef HAL_PWR_ConfigPVD(const PWR_PVDTypeDef *sConfigPVD) +{ + /* Check the parameters */ + assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel)); + assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode)); + + /* Set PLS[2:0] bits according to PVDLevel value */ + MODIFY_REG(PWR->SVMCR, PWR_SVMCR_PVDLS, sConfigPVD->PVDLevel); + + /* Disable PVD Event/Interrupt */ + __HAL_PWR_PVD_EXTI_DISABLE_EVENT(); + __HAL_PWR_PVD_EXTI_DISABLE_IT(); + __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); + __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); + + /* Configure the PVD in interrupt mode */ + if ((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) + { + __HAL_PWR_PVD_EXTI_ENABLE_IT(); + } + + /* Configure the PVD in event mode */ + if ((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) + { + __HAL_PWR_PVD_EXTI_ENABLE_EVENT(); + } + + /* Configure the PVD in rising edge */ + if ((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) + { + __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); + } + + /* Configure the PVD in falling edge */ + if ((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) + { + __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); + } + + return HAL_OK; +} + +/** + * @brief Enable the programmable voltage detector (PVD). + * @retval None. + */ +void HAL_PWR_EnablePVD(void) +{ + SET_BIT(PWR->SVMCR, PWR_SVMCR_PVDE); +} + +/** + * @brief Disable the programmable voltage detector (PVD). + * @retval None. + */ +void HAL_PWR_DisablePVD(void) +{ + CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_PVDE); +} + +/** + * @brief Enable the wake up line functionality. + * @note Wake up lines are used to wake up the system from Sleep, Stop 0-1 and + * Standby modes. + * @param WakeUpPin : Specifies which wake up line to enable. This parameter + * can be one of PWR_WakeUp_Pins_High_Polarity define + * group where every param select the wake up line, the + * wake up source with high polatiry detection and the wake + * up selected I/O or can be one of + * PWR_WakeUp_Pins_Low_Polarity define group where every + * param select the wake up line, the wake up source with + * low polarity and the wake up selected I/O or can be one + * of PWR_WakeUp_Pins define group where every param select + * the wake up line, the wake up source with + * high polarity and the first wake up I/O. + * @retval None. + */ +void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPin) +{ + /* Check the parameter */ + assert_param(IS_PWR_WAKEUP_PIN(WakeUpPin)); + + /* Specifies the wake up line polarity for the event detection (rising or falling edge) */ + MODIFY_REG(PWR->WUCR2, (PWR_EWUP_MASK & WakeUpPin), (WakeUpPin >> PWR_WUP_POLARITY_SHIFT)); + + /* Specifies the wake up line I/O selection */ + MODIFY_REG(PWR->WUCR3, (3UL << (POSITION_VAL(PWR_EWUP_MASK & WakeUpPin) * 2U)), + (WakeUpPin >> PWR_WUP_SELECT_SIGNAL_SHIFT)); + + /* Enable wake-up line */ + SET_BIT(PWR->WUCR1, (PWR_EWUP_MASK & WakeUpPin)); +} + +/** + * @brief Disable the wake up line functionality. + * @param WakeUpPin : Specifies the wake up line to disable. + * This parameter can be a combination of all the following + * values when available: + * @arg @ref PWR_WAKEUP_PIN1 + * @arg @ref PWR_WAKEUP_PIN2 + * @arg @ref PWR_WAKEUP_PIN3 + * @arg @ref PWR_WAKEUP_PIN4 + * @arg @ref PWR_WAKEUP_PIN6 + * @arg @ref PWR_WAKEUP_PIN5 + * @arg @ref PWR_WAKEUP_PIN7 + * @arg @ref PWR_WAKEUP_PIN8 + * @retval None + */ +void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPin) +{ + /* Check the parameters */ + assert_param(IS_PWR_WAKEUP_PIN(WakeUpPin)); + + /* Disable wake-up pin */ + CLEAR_BIT(PWR->WUCR1, (PWR_EWUP_MASK & WakeUpPin)); +} + +/** + * @brief Get and Clear Wake-up source. + * @retval WakeUpPin : This parameter can be a combination of all the following + * values when available: + * @arg @ref PWR_WAKEUP_PIN1 + * @arg @ref PWR_WAKEUP_PIN2 + * @arg @ref PWR_WAKEUP_PIN3 + * @arg @ref PWR_WAKEUP_PIN4 + * @arg @ref PWR_WAKEUP_PIN6 + * @arg @ref PWR_WAKEUP_PIN5 + * @arg @ref PWR_WAKEUP_PIN7 + * @arg @ref PWR_WAKEUP_PIN8 + */ +uint32_t HAL_PWR_GetClearWakeupSource(void) +{ + uint32_t wakeuppin; + + /* Get all wake-up pins */ + wakeuppin = PWR->WUSR; + + /* Clear all the wake-up interrupt flags */ + PWR->WUSCR = wakeuppin; + + return wakeuppin; +} + +/** + * @brief Enter the CPU in Sleep mode. + * @note In Sleep mode, all I/O pins keep the same state as in Run mode. + * @note CPU clock is off and all peripherals including Cortex-M33 core such + * as NVIC and SysTick can run and wake up the CPU when an interrupt + * or an event occurs. + * @param Regulator : Specifies the regulator state in Sleep mode. + * This parameter can be one of the following values : + * @arg @ref PWR_MAINREGULATOR_ON + * @arg @ref PWR_LOWPOWERREGULATOR_ON + * @note This parameter is not available in this product. + * The parameter is kept just to maintain compatibility with other + * products. + * @param SLEEPEntry : Specifies if Sleep mode is entered with WFI or WFE + * instruction. + * This parameter can be one of the following values : + * @arg @ref PWR_SLEEPENTRY_WFI enter Sleep mode with Wait + * For Interrupt request. + * @arg @ref PWR_SLEEPENTRY_WFE enter Sleep mode with Wait + * For Event request. + * @note When WFI entry is used, ticks interrupt must be disabled to avoid + * unexpected CPU wake up. + * @retval None. + */ +void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) +{ + UNUSED(Regulator); + + /* Check the parameter */ + assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); + + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); + + /* Select Sleep mode entry */ + if (SLEEPEntry == PWR_SLEEPENTRY_WFI) + { + /* Wait For Interrupt Request */ + __WFI(); + } + else + { + /* Wait For Event Request */ + __SEV(); + __WFE(); + __WFE(); + } +} + +/** + * @brief Enter the whole system to Stop mode. + * @note In Stop 0 mode, the regulator remains in main regulator mode, + * allowing a very fast wakeup time but with much higher consumption + * comparing to other Stop modes. + * @note Stop 0 offers the largest number of active peripherals and wakeup + * sources, a smaller wakeup time but a higher consumption. + * @note Stop 1 mode, The voltage regulator is configured in low power mode. + * Stop 1 achieves the lowest power consumption while retaining + * the content of SRAM and registers. All clocks in the VCORE domain + * are stopped. The PLL, HSI16 and HSE32 oscillators are disabled. + * The LSE or LSI is still running. + * @note When exiting Stop mode by issuing an interrupt or a + * wakeup event, the HSI16 oscillator is selected as system clock + * The MCU is in Run mode same range as before entering Stop mode. + * @note On STM32WBAXX_SI_CUT1_0 : + * Under a critical timing wakeup condition, CPU is executing code + * after WFI while the system is still evolving to manage the enter and + * exit from STOP mode. Under this condition it results that STOPF flag + * is set and SYSCLK source change during CPU wakeup code execution. + * Worst case scenario is when the system is running on PLL, fed by + * HSE32, and HSI16 is on. In this case STOPF flag bit is set and + * SYSCLK clock source is changed 25 sys clock cycles after WFI. + * Undoing any PLL1ON, HSEON, HSION and SYSCLK modification. + * Workaround at application level is to call this API under critical + * section and add a wait loop of at least 25 system clock cycles, + * before reading the STOPF flag and making any modification to PLL1ON, + * HSEON, HSION and SYSCLK selection. + * @param Regulator : Specifies the regulator state in Stop mode + * This parameter can be one of the following values: + * @arg @ref PWR_LOWPOWERMODE_STOP0 Stop 0 mode (main regulator ON) + * @arg @ref PWR_LOWPOWERMODE_STOP1 Stop 1 mode (low power regulator ON) + * @param STOPEntry : Specifies if Stop mode is entered with WFI or WFE + * instruction. + * This parameter can be one of the following values : + * @arg @ref PWR_STOPENTRY_WFI enter Stop mode with Wait + * For Interrupt request. + * @arg @ref PWR_STOPENTRY_WFE enter Stop mode with Wait + * For Event request. + * @retval None. + */ +void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) +{ + /* Check the parameter */ + assert_param(IS_PWR_REGULATOR(Regulator)); + assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); + + /* Select Stop mode */ + MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, Regulator); + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); + + /* Select Stop mode entry */ + if (STOPEntry == PWR_STOPENTRY_WFI) + { + /* Wait For Interrupt Request */ + __WFI(); + } + else + { + /* Wait For Event Request */ + __SEV(); + __WFE(); + __WFE(); + } + + /* Reset SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); +} + +/** + * @brief Enter the whole system to Standby mode. + * @note The Standby mode is used to achieve the lowest power consumption + * with BOR. The internal regulator is switched off so that the VCORE + * domain is powered off. The PLL, the HSI16 and the HSE32 crystal + * oscillators are also switched off. + * @note After entering Standby mode, SRAMs and register contents are lost + * except for registers and backup SRAM in the Backup domain and + * Standby circuitry. Optionally, the full SRAM1 or SRAM2 can be + * retained in Standby mode, supplied by the low-power regulator. + * @note The state of each I/O during Standby mode can be selected by + * software : Enable GPIO state retention in Standby mode through + * HAL_PWREx_EnableStandbyIORetention() and disable through + * HAL_PWREx_DisableStandbyIORetention(). + * @retval None. + */ +void HAL_PWR_EnterSTANDBYMode(void) +{ + /* Select Standby mode */ + MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_2); + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); + + /* Wait For Interrupt Request */ + __WFI(); +} + +/** + * @brief Indicate SLEEP-ON-EXIT feature when returning from handler mode to + * thread mode. + * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the + * processor re-enters Sleep mode when an interruption handling is over. + * Setting this bit is useful when the processor is expected to run + * only on interruptions handling. + * @retval None. + */ +void HAL_PWR_EnableSleepOnExit(void) +{ + /* Set SLEEPONEXIT bit of Cortex-M33 System Control Register */ + SET_BIT(SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk); +} + +/** + * @brief Disable SLEEP-ON-EXIT feature when returning from handler mode to + * thread mode. + * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the + * processor re-enters Sleep mode when an interruption handling is over. + * @retval None. + */ +void HAL_PWR_DisableSleepOnExit(void) +{ + /* Clear SLEEPONEXIT bit of Cortex-M33 System Control Register */ + CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk); +} + +/** + * @brief Enable CORTEX SEV-ON-PEND feature. + * @note Sets SEVONPEND bit of SCR register. When this bit is set, any + * pending event / interrupt even if it's disabled or has insufficient + * priority to cause exception entry wakes up the Cortex-M33. + * @retval None. + */ +void HAL_PWR_EnableSEVOnPend(void) +{ + /* Set SEVONPEND bit of Cortex-M33 System Control Register */ + SET_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk); +} + +/** + * @brief Disable CORTEX SEVONPEND feature. + * @note Resets SEVONPEND bit of SCR register. When this bit is reset, only + * enabled pending causes exception entry wakes up the Cortex-M33. + * @retval None. + */ +void HAL_PWR_DisableSEVOnPend(void) +{ + /* Clear SEVONPEND bit of Cortex-M33 System Control Register */ + CLEAR_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk); +} + +/** + * @brief This function handles the PWR PVD interrupt request. + * @note This API should be called under the PVD_IRQHandler(). + * @retval None. + */ +void HAL_PWR_PVD_IRQHandler(void) +{ + uint32_t rising_flag; + uint32_t falling_flag; + + rising_flag = READ_REG(EXTI->RPR1); + falling_flag = READ_REG(EXTI->FPR1); + + /* Check PWR exti rising flag */ + if ((rising_flag & PWR_EXTI_LINE_PVD) != 0U) + { + /* Clear PVD exti pending bit */ + __HAL_PWR_PVD_EXTI_CLEAR_RISING_FLAG(); + + /* PWR PVD interrupt rising user callback */ + HAL_PWR_PVD_Rising_Callback(); + } + + /* Check PWR exti fallling flag */ + if ((falling_flag & PWR_EXTI_LINE_PVD) != 0U) + { + /* Clear PVD exti pending bit */ + __HAL_PWR_PVD_EXTI_CLEAR_FALLING_FLAG(); + + /* PWR PVD interrupt falling user callback */ + HAL_PWR_PVD_Falling_Callback(); + } +} + +/** + * @brief PWR PVD interrupt rising callback + * @retval None + */ +__weak void HAL_PWR_PVD_Rising_Callback(void) +{ + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_PWR_PVD_Rising_Callback can be implemented in the user file + */ +} + +/** + * @brief PWR PVD interrupt Falling callback + * @retval None + */ +__weak void HAL_PWR_PVD_Falling_Callback(void) +{ + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_PWR_PVD_Falling_Callback can be implemented in the user file + */ +} +/** + * @} + */ + +/** + * @brief This function handles the PWR WAKEUP interrupt request. + * @note This API should be called under the WKUP_IRQHandler(). + * @retval None. + */ +void HAL_PWR_WKUP_IRQHandler(void) +{ + uint32_t wakeuppin; + + wakeuppin = HAL_PWR_GetClearWakeupSource(); + + /* Wakeup pin EXTI line interrupt detected */ + if ((wakeuppin & PWR_WUSR_WUF1) != 0U) + { + /* PWR WKUP1 interrupt user callback */ + HAL_PWR_WKUP1_Callback(); + } +#if defined(PWR_WUCR1_WUPEN2) + if ((wakeuppin & PWR_WUSR_WUF2) != 0U) + { + /* PWR WKUP2 interrupt user callback */ + HAL_PWR_WKUP2_Callback(); + } +#endif /* defined(PWR_WUCR1_WUPEN2) */ + if ((wakeuppin & PWR_WUSR_WUF3) != 0U) + { + /* PWR WKUP3 interrupt user callback */ + HAL_PWR_WKUP3_Callback(); + } + + if ((wakeuppin & PWR_WUSR_WUF4) != 0U) + { + /* PWR WKUP4 interrupt user callback */ + HAL_PWR_WKUP4_Callback(); + } +#if defined(PWR_WUCR1_WUPEN5) + if ((wakeuppin & PWR_WUSR_WUF5) != 0U) + { + /* PWR WKUP5 interrupt user callback */ + HAL_PWR_WKUP5_Callback(); + } +#endif /* defined(PWR_WUCR1_WUPEN5) */ + if ((wakeuppin & PWR_WUSR_WUF6) != 0U) + { + /* PWR WKUP6 interrupt user callback */ + HAL_PWR_WKUP6_Callback(); + } + if ((wakeuppin & PWR_WUSR_WUF7) != 0U) + { + /* PWR WKUP7 interrupt user callback */ + HAL_PWR_WKUP7_Callback(); + } + if ((wakeuppin & PWR_WUSR_WUF8) != 0U) + { + /* PWR WKUP8 interrupt user callback */ + HAL_PWR_WKUP8_Callback(); + } +} + +/** + * @brief PWR WKUP1 interrupt callback. + * @retval None. + */ +__weak void HAL_PWR_WKUP1_Callback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PWR_WKUP1Callback can be implemented in the user file + */ +} + +#if defined(PWR_WUCR1_WUPEN2) +/** + * @brief PWR WKUP2 interrupt callback. + * @retval None. + */ +__weak void HAL_PWR_WKUP2_Callback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PWR_WKUP2Callback can be implemented in the user file + */ +} +#endif /* defined(PWR_WUCR1_WUPEN2) */ + +/** + * @brief PWR WKUP3 interrupt callback. + * @retval None. + */ +__weak void HAL_PWR_WKUP3_Callback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PWR_WKUP3Callback can be implemented in the user file + */ +} + +/** + * @brief PWR WKUP4 interrupt callback. + * @retval None. + */ +__weak void HAL_PWR_WKUP4_Callback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PWR_WKUP4Callback can be implemented in the user file + */ +} + +#if defined(PWR_WUCR1_WUPEN5) +/** + * @brief PWR WKUP5 interrupt callback. + * @retval None. + */ +__weak void HAL_PWR_WKUP5_Callback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PWR_WKUP5Callback can be implemented in the user file + */ +} +#endif /* defined(PWR_WUCR1_WUPEN5) */ + +/** + * @brief PWR WKUP6 interrupt callback. + * @retval None. + */ +__weak void HAL_PWR_WKUP6_Callback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PWR_WKUP6Callback can be implemented in the user file + */ +} + +/** + * @brief PWR WKUP7 interrupt callback. + * @retval None. + */ +__weak void HAL_PWR_WKUP7_Callback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PWR_WKUP7Callback can be implemented in the user file + */ +} + +/** + * @brief PWR WKUP8 interrupt callback. + * @retval None. + */ +__weak void HAL_PWR_WKUP8_Callback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PWR_WKUP8Callback can be implemented in the user file + */ +} +/** + * @} + */ + +#if defined(PWR_PRIVCFGR_NSPRIV) +/** @defgroup PWR_Exported_Functions_Group3 Attributes Management Functions + * @brief Attributes management functions + * +@verbatim + =============================================================================== + ##### PWR Attributes Functions ##### + =============================================================================== + [..] + When the TrustZone security is activated by the TZEN option bit in the + FLASH_OPTR register, some PWR register fields can be secured against + non-secure access. + The PWR TrustZone security allows the following features to be secured + through the PWR_SECCFGR register : + + (++) Low-power mode. + (++) Wake-up (WKUP) pins. + (++) Voltage detection and monitoring. + (++) VBAT mode. + (++) I/Os pull-up/pull-down configuration. + + Other PWR configuration bits are secure when : + (++) The system clock selection is secure in RCC: the voltage scaling + (VOS) configuration is secure. + (++) A GPIO is configured as secure: its corresponding bit for pull-up / + pull-down configuration in Standby mode is secure. + + A non-secure access to a secure-protected register bit is denied : + (++) The secured bits are not written (WI) with a non-secure write access. + (++) The secured bits are read as 0 (RAZ) with a non-secure read access. + + [..] + When the TrustZone security is disabled (TZEN = 0), PWR_SECCFGR is RAZ/WI + and all other registers are non-secure. + + [..] + By default, after a reset, all PWR registers can be read or written with + both privileged and unprivileged accesses, except PWR_PRIVCFGR that can be + written with privileged access only. PWR_PRIVCFGR can be read by secure + and non secure, privileged and unprivileged accesses. + The SPRIV bit in PWR_PRIVCFGR can be written with secure privileged access + only. This bit configures the privileged access of all PWR secure + functions (defined by PWR_SECCFGR, GTZC, RCC or GPIO). + When the SPRIV bit is set in PWR_PRIVCFGR: + (++) The PWR secure bits can be written only with privileged access, + including PWR_SECCFGR. + (++) The PWR secure bits can be read only with privileged access except + PWR_SECCFGR and PWR_PRIVCFGR that can be read by privileged or + unprivileged access. + (++) An unprivileged access to a privileged PWR bit or register is + discarded : the bits are read as zero and the write to these bits is + ignored (RAZ/WI). + The NSPRIV bit of PWR_PRIVCFGR can be written with privileged access only, + secure or non-secure. This bit configures the privileged access of all PWR + securable functions that are configured as non-secure (defined by + PWR_SECCFGR, GTZC, RCC or GPIO). + When the NSPRIV bit is set in PWR_PRIVCFGR : + (++) The PWR securable bits that are configured as non-secure, can be + written only with privileged access. + (++) The PWR securable bits that are configured as non-secure, can be read + only with privileged access except PWR_PRIVCFGR that can be read by + privileged or unprivileged accesses. + (++) The VOSRDY bit in PWR_VOSR, PWR_SR, PWR_SVMSR and PWR_WUSR, can be read + with privileged or unprivileged accesses. + (++) An unprivileged access to a privileged PWR bit or register is + discarded : the bits are read as zero and the write to these bits is + ignored (RAZ/WI). + +@endverbatim + * @{ + */ + +/** + * @brief Configure the PWR item attributes. + * @note Available attributes are security and privilege protection. + * @note Security attribute can only be set only by secure access. + * @note Privilege attribute for secure items can be managed only by a secure + * privileged access. + * @note Privilege attribute for nsecure items can be managed by a secure + * privileged access or by a nsecure privileged access. + * @param Item : Specifies the item(s) to set attributes on. + * This parameter can be a combination of PWR_ITEMS. + * @param Attributes : Specifies the available attribute(s). + * This parameter can be one of PWR_ATTRIBUTES. + * @retval None. + */ +void HAL_PWR_ConfigAttributes(uint32_t Item, uint32_t Attributes) +{ + /* Check the parameters */ + assert_param(IS_PWR_ITEMS_ATTRIBUTES(Item)); + assert_param(IS_PWR_ATTRIBUTES(Attributes)); + +#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + /* Secure item management (TZEN = 1) */ + if ((Attributes & PWR_ITEM_ATTR_SEC_PRIV_MASK) == PWR_ITEM_ATTR_SEC_PRIV_MASK) + { + /* Privilege item management */ + if ((Attributes & PWR_SEC_PRIV) == PWR_SEC_PRIV) + { + SET_BIT(PWR_S->SECCFGR, Item); + SET_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_SPRIV); + } + else + { + SET_BIT(PWR_S->SECCFGR, Item); + CLEAR_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_SPRIV); + } + } + /* NSecure item management */ + else + { + /* Privilege item management */ + if ((Attributes & PWR_NSEC_PRIV) == PWR_NSEC_PRIV) + { + CLEAR_BIT(PWR_S->SECCFGR, Item); + SET_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV); + } + else + { + CLEAR_BIT(PWR_S->SECCFGR, Item); + CLEAR_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV); + } + } +#else + /* NSecure item management (TZEN = 0) */ + if ((Attributes & PWR_ITEM_ATTR_NSEC_PRIV_MASK) == PWR_ITEM_ATTR_NSEC_PRIV_MASK) + { + /* Privilege item management */ + if ((Attributes & PWR_NSEC_PRIV) == PWR_NSEC_PRIV) + { + SET_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV); + } + else + { + CLEAR_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV); + } + } +#endif /* __ARM_FEATURE_CMSE */ +} + + +/** + * @brief Get attribute(s) of a PWR item. + * @param Item : Specifies the item(s) to set attributes on. + * This parameter can be one of PWR_ITEMS. + * @param pAttributes : Pointer to return attribute(s). + * Returned value could be on of PWR_ATTRIBUTES. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_PWR_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes) +{ + uint32_t attributes; + + /* Check attribute pointer */ + if (pAttributes == NULL) + { + return HAL_ERROR; + } + + /* Check the parameter */ + assert_param(IS_PWR_ITEMS_ATTRIBUTES(Item)); + +#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + /* Check item security */ + if ((PWR->SECCFGR & Item) == Item) + { + /* Get Secure privileges attribute */ + attributes = ((PWR->PRIVCFGR & PWR_PRIVCFGR_SPRIV) == 0U) ? PWR_SEC_NPRIV : PWR_SEC_PRIV; + } + else + { + /* Get Non-Secure privileges attribute */ + attributes = ((PWR->PRIVCFGR & PWR_PRIVCFGR_NSPRIV) == 0U) ? PWR_NSEC_NPRIV : PWR_NSEC_PRIV; + } +#else + /* Get Non-Secure privileges attribute */ + attributes = ((PWR->PRIVCFGR & PWR_PRIVCFGR_NSPRIV) == 0U) ? PWR_NSEC_NPRIV : PWR_NSEC_PRIV; +#endif /* __ARM_FEATURE_CMSE */ + + /* return value */ + *pAttributes = attributes; + + return HAL_OK; +} +/** + * @} + */ +#endif /* #if defined(PWR_PRIVCFGR_SPRIV) */ + +/** + * @} + */ + +#endif /* defined(HAL_PWR_MODULE_ENABLED) */ +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_pwr_ex.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_pwr_ex.c new file mode 100644 index 0000000000..c9183a4517 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_pwr_ex.c @@ -0,0 +1,1053 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_pwr_ex.c + * @author MCD Application Team + * @brief Extended PWR HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Power Controller extension peripheral : + * + Power Supply Control Functions + * + Low Power Control Functions + * + Voltage Monitoring Functions + * + Memories Retention Functions + * + I/O Retention Functions + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Call HAL_PWREx_ControlVoltageScaling() and HAL_PWREx_GetVoltageRange() to + set / get the voltage scaling range. + (+) Voltage scaling can be one of the following values : + (++) voltage output scale 1 : + => Used when system clock frequency is up to 100 MHz + (++) voltage output scale 2 : + => Used when system clock frequency is up to 16 MHz + + (#) Call HAL_PWREx_EnableUltraLowPowerMode() and + HAL_PWREx_DisableUltraLowPowerMode() to enable / disable the BOR ultra + low power mode. + + (#) Call HAL_PWREx_EnableSRAM1ContentStandbyRetention() and + HAL_PWREx_DisableSRAM1ContentStandbyRetention() to + enable / disable the SRAM1 content retention in Standby low + power mode. + + (#) Call HAL_PWREx_EnableSRAM2ContentStandbyRetention() and + HAL_PWREx_DisableSRAM2ContentStandbyRetention() to + enable / disable the SRAM2 content retention in Standby low + power mode. + + (#) Call HAL_PWREx_EnableRAMsContentStopRetention() and + HAL_PWREx_DisableRAMsContentStopRetention() to + enable / disable the RAMs content retention in Stop mode (Stop 0/1). + (+) Retained RAM can be one of the following RAMs : + (++) SRAM1 + (++) SRAM2 + (++) ICACHE + + (#) Call HAL_PWREx_EnableFlashFastWakeUp() and + HAL_PWREx_DisableFlashFastWakeUp() to enable / disable the flash memory + fast wakeup from Stop mode (Stop 0/1). + + (#) Call HAL_PWREx_EnableStandbyIORetention() and HAL_PWREx_DisableStandbyIORetention() + to enable / disable the IO state retention while in Standby mode. + + (#) Call HAL_PWREx_GetStandbyIORetentionStatus() to retrieve for a given port for which + IO the state was retained while in Standby mode. + + (#) Call HAL_PWREx_DisableStandbyRetainedIOState() to disable the IO state retained in + Standby mode. + + (#) Call HAL_PWREx_ConfigSupply to Configure the system Power Supply. + + (#) Call HAL_PWREx_GetRADIOOperatingMode to get the 2.4 GHz RADIO operating mode. + + (#) Call HAL_PWREx_GetRADIOPHYOperatingModeto get the 2.4 GHz RADIO PHY operating mode. + + (#) Call HAL_PWREx_GetRADIOEncryptionOperatingMode to get the radio encryption mode. + + (#) Call HAL_PWREx_GetRFVDDHPA to get the 2.4 GHz RADIO control. + + (#) Call HAL_PWREx_SetREGVDDHPAInputSupply and HAL_PWREx_GetREGVDDHPAInputSupply + set / get the regulator VDDHPA input supply selection. + + (#) Call HAL_PWREx_EnableREGVDDHPABypass and HAL_PWREx_DisableREGVDDHPABypass + to enable / disable regulator REG_VDDHPA bypass + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @defgroup PWREx PWREx + * @brief PWR Extended HAL module driver + * @{ + */ + +#if defined(HAL_PWR_MODULE_ENABLED) + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/** @defgroup PWR_Extended_Private_Defines PWR Extended Private Defines + * @{ + */ +#if defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) +#define PWR_PORTA_AVAILABLE_PINS (0x0FFFFU) +#define PWR_PORTB_AVAILABLE_PINS (0x0FFFFU) +#define PWR_PORTC_AVAILABLE_PINS (0x0E000U) +#define PWR_PORTH_AVAILABLE_PINS (0x00008U) +#elif defined(STM32WBA50xx) +#define PWR_PORTA_AVAILABLE_PINS (0x0F1E3U) +#define PWR_PORTB_AVAILABLE_PINS (0x09318U) +#define PWR_PORTC_AVAILABLE_PINS (0x0C000U) +#define PWR_PORTH_AVAILABLE_PINS (0x00008U) +#endif /* defined(STM32WBA52xx) || defined(STM32WBA54xx) || defined(STM32WBA55xx) */ +/*!< Time out value of flags setting */ +#define PWR_VOSF_SETTING_DELAY_VALUE (0x32U) /*!< Time out value for VOSF flag setting */ +#define PWR_MODE_CHANGE_DELAY_VALUE (0x32U) /*!< Time out for step down converter operating mode */ +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup PWREx_Exported_Functions PWR Extended Exported Functions + * @{ + */ + +/** @defgroup PWREx_Exported_Functions_Group1 Power Supply Control Functions + * @brief Power supply control functions + * +@verbatim + =============================================================================== + ##### Power supply control functions ##### + =============================================================================== + [..] + This section provides functions allowing to control power supply. + + [..] + (+) The STM32WBA series devices embed two regulators : one LDO (linear + voltage regulator) and one SMPS (step down converter) in parallel to + provide the VCORE supply for digital peripherals, SRAM1, SRAM2 and + embedded Flash memory. + + (+) The SMPS allows the power consumption to be reduced but some + peripherals can be perturbed by the noise generated by the SMPS, + requiring the application to switch to LDO when running this + peripheral in order to reach the best performances. + + (+) The LDO and the SMPS regulators have two modes: Main regulator mode + (used when performance is needed), and Low-power regulator mode. LDO + or SMPS can be used in all voltage scaling ranges, and in all Stop + and Standby with retention modes. + + (+) After reset, the regulator is the LDO, in Range 2. Switching to SMPS + provides lower consumption in particular at high VDD voltage. It is + possible to switch from LDO to SMPS, or from SMPS to LDO on the fly in + any range, by configuring the REGSEL bit. It is recommended to switch + first to SMPS before changing the voltage range. + + (+) When exiting from Stop or Standby retention modes, the regulator is the + same than when entering these low-power modes. + + (+) When exiting from Standby modes, the LDO regulator is always used. When Standby + has been entered from the SMPS regulator, after exiting standby with the LDO, + the regulator is subsequently switched to SMPS regulator. + + (+) When exiting from Stop 0 modes the voltage range is the same as on entering Stop 0 + mode. When exiting from Stop 1 and Standby modes the voltage range 2 is used. + + (+) When the 2.4 GHz RADIO is active the regulator and range can not be changed. Any + requested regulator or range change while the 2.4 GHz RADIO is active is suspended + and will only take effect after the 2.4 GHz RADIO has entered Sleep or Deepsleep mode. + + (+) Both regulators can provide four different voltages (voltage scaling) + and can operate in Stop modes. + Voltage scaling ranges can be one of the following values : + (++) voltage output scale 1 : + => Used when system clock frequency is up to 100 MHz + (++) voltage output scale 2 : + => Used when system clock frequency is up to 16 MHz + +@endverbatim + * @{ + */ + +/** + * @brief Configure the main internal regulator output voltage to achieve + * a tradeoff between performance and power consumption. + * @param VoltageScaling : Specifies the regulator output voltage scale. + * This parameter can be one of the following values : + * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 : Regulator voltage output range 1. + * Used when system clock frequency is up to 100 MHz. + * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 : Regulator voltage output range 2. + * Used when system clock frequency is up to 16 MHz. + * @note Before moving to voltage scaling 2, it is mandatory to ensure that + * the system frequency is equal or below 16 MHz. + * @note When the 2.4 GHz RADIO is active, the range cannot be changed. + * Any requested range change while the 2.4 GHz RADIO is active is suspended and will + * only take effect after the 2.4 GHz RADIO has entered Sleep or Deepsleep mode. + * @note In range 2, the 2.4 GHz RADIO shall not transmit nor receive. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) +{ + uint32_t timeout; + + /* Check the parameter */ + assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling)); + + /* Get the current voltage scale applied */ + uint32_t vos_old = READ_BIT(PWR->SVMSR, PWR_SVMSR_ACTVOS); + + /* No change, nothing to do */ + if (vos_old == VoltageScaling) + { + return HAL_OK; + } + + /* Set voltage scaling level */ + MODIFY_REG(PWR->VOSR, PWR_VOSR_VOS, VoltageScaling); + + + /* Wait until VOSRDY is set */ + timeout = ((PWR_VOSF_SETTING_DELAY_VALUE * SystemCoreClock) / 1000000U) + 1U; + while (HAL_IS_BIT_CLR(PWR->VOSR, PWR_VOSR_VOSRDY) && (timeout != 0U)) + { + timeout--; + } + + /* Check time out */ + if (timeout == 0U) + { + return HAL_TIMEOUT; + } + + /* Wait until ACTVOSRDY is set */ + timeout = ((PWR_VOSF_SETTING_DELAY_VALUE * SystemCoreClock) / 1000000U) + 1U; + while ((HAL_IS_BIT_CLR(PWR->SVMSR, PWR_SVMSR_ACTVOSRDY)) && (timeout != 0U)) + { + timeout--; + } + + /* Check time out */ + if (timeout == 0U) + { + return HAL_TIMEOUT; + } + + return HAL_OK; +} + +/** + * @brief Return voltage scaling range. + * @retval Applied voltage scaling value. + */ +uint32_t HAL_PWREx_GetVoltageRange(void) +{ + return (PWR->SVMSR & PWR_SVMSR_ACTVOS); +} + +#if defined(PWR_CR3_REGSEL) +/** + * @brief Configure the system Power Supply. + * @param SupplySource : Specifies the Power Supply source. + * This parameter can be one of the following values : + * @arg PWR_LDO_SUPPLY : The LDO regulator supplies the Vcore Power Domains. + * @arg PWR_SMPS_SUPPLY : The SMPS regulator supplies the Vcore Power Domains. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_PWREx_ConfigSupply(uint32_t SupplySource) +{ + uint32_t timeout; + + /* Check the parameter */ + assert_param(IS_PWR_SUPPLY(SupplySource)); + + /* Set maximum time out */ + timeout = ((PWR_MODE_CHANGE_DELAY_VALUE * SystemCoreClock) / 1000000U) + 1U; + + /* Configure the LDO as system regulator supply */ + if (SupplySource == PWR_LDO_SUPPLY) + { + /* Set the power supply configuration */ + CLEAR_BIT(PWR->CR3, PWR_CR3_REGSEL); + + /* Wait until system switch on new regulator */ + while (HAL_IS_BIT_SET(PWR->SVMSR, PWR_SVMSR_REGS) && (timeout != 0U)) + { + timeout--; + } + } + /* Configure the SMPS as system regulator supply */ + else + { + /* Set the power supply configuration */ + SET_BIT(PWR->CR3, PWR_CR3_REGSEL); + + /* Wait until system switch on new regulator */ + while (HAL_IS_BIT_CLR(PWR->SVMSR, PWR_SVMSR_REGS) && (timeout != 0U)) + { + timeout--; + } + } + + /* Check time out */ + if (timeout == 0U) + { + return HAL_TIMEOUT; + } + + return HAL_OK; +} + +/** + * @brief Get the power supply configuration. + * @retval The supply configured. + */ +uint32_t HAL_PWREx_GetSupplyConfig(void) +{ + return (PWR->SVMSR & PWR_SVMSR_REGS); +} +#endif /* defined(PWR_CR3_REGSEL) */ + +#if defined(PWR_CR2_FPWM) +/** + * @brief Enable SMPS PWM mode + * @note FPWM bit is used to reduce the SMPS switching harmonics in range 1. + * @note Setting FPWM bit has no effect in range 2 + * @retval None. + */ +void HAL_PWREx_EnableSMPSPWM(void) +{ + SET_BIT(PWR->CR2, PWR_CR2_FPWM); +} + +/** + * @brief Disable SMPS PWM mode + * @retval None. + */ +void HAL_PWREx_DisableSMPSPWM(void) +{ + CLEAR_BIT(PWR->CR2, PWR_CR2_FPWM); +} +#endif /* defined(PWR_CR2_FPWM) */ +/** + * @brief Enable fast soft start for the current regulator. + * @retval None. + */ +void HAL_PWREx_EnableFastSoftStart(void) +{ + SET_BIT(PWR->CR3, PWR_CR3_FSTEN); +} + +/** + * @brief Disable fast soft start for the current regulator. + * @retval None. + */ +void HAL_PWREx_DisableFastSoftStart(void) +{ + CLEAR_BIT(PWR->CR3, PWR_CR3_FSTEN); +} + +/** + * @} + */ + +/** @defgroup PWREx_Exported_Functions_Group2 Low Power Control Functions + * @brief Low power control functions + */ + +/** + * @brief Enable BOR and PVD ultra-low power mode. + * @note BOR and PVD operations can be in discontinuous (ultra-low power) mode in + * Stop 1 and Standby modes. + * @note This bit must be set to reach the lowest power consumption in the low-power modes. + * @note This bit shall not be set together with autonomous peripherals using HSI16 + * as kernel clock. + * @retval None. + */ +void HAL_PWREx_EnableUltraLowPowerMode(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_ULPMEN); +} + +/** + * @brief Disable BOR and PVD ultra-low power mode. + * @retval None. + */ +void HAL_PWREx_DisableUltraLowPowerMode(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_ULPMEN); +} +/** + * @} + */ + + + +/** @defgroup PWREx_Exported_Functions_Group4 Memories Retention Functions + * @brief Memories retention functions + * +@verbatim + =============================================================================== + ##### Memories Retention Functions ##### + =============================================================================== + [..] + Several STM32WBA devices RAMs are configurable to retain or lose RAMs content + during Stop mode. + (+) Retained content RAMs in Stop modes are : + (++) SRAM1 + (++) SRAM2 + (++) ICACHE + + [..] + Several STM32WBA devices RAMs are configurable to retain or lose RAMs content + in Standby mode. + (+) Retained content RAMs in Standby mode are : + (++) SRAM1 + (++) SRAM2 + +@endverbatim + * @{ + */ + +/** + * @brief Enable SRAM1 content retention in Standby mode. + * @note When R1RSB1 bit is set, SRAM1 is powered by the low-power regulator in + * Standby mode and its content is kept. + * @param SRAM1Pages : Specifies the SRAM1 area + * This parameter can be combination of the following values : + * @arg PWR_SRAM1_FULL_STANDBY_RETENTION : full SRAM1 retention. + * @retval None. + */ +void HAL_PWREx_EnableSRAM1ContentStandbyRetention(uint32_t SRAM1Pages) +{ + /* Check the parameters */ + assert_param(IS_PWR_SRAM1_STANDBY_RETENTION(SRAM1Pages)); + + /* Set RRSx bit(s) */ + MODIFY_REG(PWR->CR1, PWR_SRAM1_FULL_STANDBY_RETENTION, SRAM1Pages); +} + +/** + * @brief Disable SRAM1 content retention in Standby mode. + * @note When R1RSB1 bit is reset, SRAM1 is powered off in Standby + * mode and its content is lost. + * @retval None. + */ +void HAL_PWREx_DisableSRAM1ContentStandbyRetention(void) +{ + /* Clear R1RSB1 bit */ + CLEAR_BIT(PWR->CR1, PWR_SRAM1_FULL_STANDBY_RETENTION); +} + +/** + * @brief Enable SRAM2 content retention in Standby mode. + * @note When R2RSB1 bit is set, SRAM2 is powered by the low-power regulator in + * Standby mode and its content is kept. + * @param SRAM2Pages : Specifies the SRAM2 area + * This parameter can be one of the following values : + * @arg PWR_SRAM2_FULL_STANDBY_RETENTION : full SRAM2 retention. + * @retval None. + */ +void HAL_PWREx_EnableSRAM2ContentStandbyRetention(uint32_t SRAM2Pages) +{ + /* Check the parameters */ + assert_param(IS_PWR_SRAM2_STANDBY_RETENTION(SRAM2Pages)); + + /* Set RRSx bit(s) */ + MODIFY_REG(PWR->CR1, PWR_SRAM2_FULL_STANDBY_RETENTION, SRAM2Pages); +} + +/** + * @brief Disable SRAM2 content retention in Standby mode. + * @note When R2RSB1 bit is reset, SRAM2 is powered off in Standby + * mode and its content is lost. + * @retval None. + */ +void HAL_PWREx_DisableSRAM2ContentStandbyRetention(void) +{ + /* Clear R2RSB1 bit */ + CLEAR_BIT(PWR->CR1, PWR_SRAM2_FULL_STANDBY_RETENTION); +} + +/** + * @brief Enable 2.4GHz RADIO SRAMs and Sleep clock retention in Standby mode. + * @note When RADIORSB bit is set, the 2.4 GHz RADIO SRAMs (TXRX and Sequence) content + * is retained in Standby mode and the 2.4 GHz RADIO sleep timer counter remains + * operational. + * @param RadioSRAM : Specifies the Radio SRAM area + * This parameter can be one of the following values : + * @arg PWR_RADIOSRAM_FULL_STANDBY_RETENTION: full Radio SRAM and sleep counter retention. + * @retval None. + */ +void HAL_PWREx_EnableRadioSRAMClockStandbyRetention(uint32_t RadioSRAM) +{ + /* Check the parameters */ + assert_param(IS_PWR_RADIOSRAM_STANDBY_RETENTION(RadioSRAM)); + + /* Set Radio RAM retention bit(s) */ + MODIFY_REG(PWR->CR1, PWR_RADIOSRAM_FULL_STANDBY_RETENTION, RadioSRAM); +} + +/** + * @brief Disable 2.4GHz RADIO SRAMs and Sleep clock retention in Standby mode. + * @note When RADIORSB bit is reset, the 2.4 GHz RADIO SRAMs and the sleep timer counter + * are not retained in Standby mode. + * @retval None. + */ +void HAL_PWREx_DisableRadioSRAMClockStandbyRetention(void) +{ + /* Clear RADIORSB bit */ + CLEAR_BIT(PWR->CR1, PWR_RADIOSRAM_FULL_STANDBY_RETENTION); +} + +/** + * @brief Enable RAMs content retention in Stop modes. + * @note When enabling content retention for a given ram, memory is kept powered + * on in Stop mode. (Consumption is not optimized) + * @note On Silicon Cut 1.0, it is mandatory to disable the ICACHE before going into + * stop modes otherwise an hard fault may occur when waking up from stop modes. + * @param RAMSelection: Specifies RAMs content to be retained in Stop mode. + * This parameter can be one or a combination of the values: + * @arg PWR_SRAM1_FULL_STOP_RETENTION : full SRAM1 retention . + * @arg PWR_SRAM2_FULL_STOP_RETENTION : full SRAM2 retention. + * @arg PWR_ICACHE_FULL_STOP_RETENTION : I-CACHE SRAM retention. + * @retval None. + */ +void HAL_PWREx_EnableRAMsContentStopRetention(uint32_t RAMSelection) +{ + /* Check the parameters */ + assert_param(IS_PWR_RAM_STOP_RETENTION(RAMSelection)); + + /* Enable RAM retention in Stop mode */ + CLEAR_BIT(PWR->CR2, RAMSelection); +} + +/** + * @brief Disable RAMs content retention in Stop modes. + * @note When disabling content retention for a given RAM, memory is + * powered down in Stop mode. (Consumption is optimized) + * @param RAMSelection: Specifies RAMs content to be lost in Stop mode. + * This parameter can be one or a combination of the values: + * @arg PWR_SRAM1_FULL_STOP_RETENTION : full SRAM1 retention . + * @arg PWR_SRAM2_FULL_STOP_RETENTION : full SRAM2 retention. + * @arg PWR_ICACHE_FULL_STOP_RETENTION : I-CACHE SRAM retention. + * @retval None. + */ +void HAL_PWREx_DisableRAMsContentStopRetention(uint32_t RAMSelection) +{ + /* Check the parameters */ + assert_param(IS_PWR_RAM_STOP_RETENTION(RAMSelection)); + + /* Disable RAM retention in Stop mode */ + MODIFY_REG(PWR->CR2, PWR_ALL_RAM_STOP_RETENTION_MASK, RAMSelection); +} + +/** + * @brief Enable the flash memory fast wakeup from Stop 0 and Stop 1 modes. + * @note This feature is used to obtain the best trade-off between low-power + * consumption and wakeup time when exiting the Stop 0 or Stop 1 modes. + * When this feature is enabled, the Flash memory remains in normal + * mode in Stop 0 and Stop 1 modes, which offers a faster startup time + * with higher consumption. + * @retval None. + */ +void HAL_PWREx_EnableFlashFastWakeUp(void) +{ + SET_BIT(PWR->CR2, PWR_CR2_FLASHFWU); +} + +/** + * @brief Disable the Flash Power Down in Stop mode. + * @note This feature is used to obtain the best trade-off between low-power + * consumption and wakeup time when exiting the Stop 0 or Stop 1 modes. + * When this feature is disabled, the Flash memory enters low-power + * mode in Stop 0 and Stop 1 modes, which causes a slower startup time + * with lower consumption. + * @retval None. + */ +void HAL_PWREx_DisableFlashFastWakeUp(void) +{ + CLEAR_BIT(PWR->CR2, PWR_CR2_FLASHFWU); +} +/** + * @} + */ + +/** @defgroup PWREx_Exported_Functions_Group5 I/O Retention Functions + * @brief I/O retention functions + * +@verbatim + =============================================================================== + ##### IOs retention functions ##### + =============================================================================== + [..] + In Standby mode, the GPIOs are by default in floating state. If Standby GPIO + retention is enabled in the PWR_IORETENRx register, the GPIO will retain the pull + or output level. When entering Standby mode, GPIOs that are enabled for Standby mode + retention keep their pull or level during and after exiting from Standby mode until + the PWR_IORETRx bit is cleared by software. + + [..] + When entering Standby mode the PWR_IORETRx bit will be set by hardware for the GPIOs with + Standby retention enabled in. Once PWR_IORETRx is cleared by software, the GPIO configuration + will switch to the one defined as below: + (+) when GPIO is not selecting an alternate function, GPIO configuration is applied, + (+) when GPIO is selecting an alternate function, the selected peripheral alternate function + control will be applied. + The GPIO Standby retention enable information in PWR_IORETENRx is lost and has to be reconfigured + for sub-sequent entering into Standby mode. + +@endverbatim + * @{ + */ + +/** + * @brief Enable GPIO state retention in Standby mode. + * @note Set the relevant Pxy bits of PWR_IORETENRx register to configure the I/O + * state retention in Standby mode. + * @note The configuration is kept when exiting the Standby mode. + * @param GPIO_Port : Specify the IO port. + * This parameter can be a value of + * @ref PWREx_GPIO_Port. + * @param GPIO_Pin : Specify the I/O pins numbers. + * This parameter can be a value of + * @ref PWREx_GPIO_Pin_Mask. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_PWREx_EnableStandbyIORetention(uint32_t GPIO_Port, uint32_t GPIO_Pin) +{ + HAL_StatusTypeDef ret = HAL_OK; + + /* Check the parameters */ + assert_param(IS_PWR_GPIO_PORT(GPIO_Port)); + assert_param(IS_PWR_GPIO_PIN_MASK(GPIO_Pin)); + + /* Check GPIO port */ + switch (GPIO_Port) + { + case PWR_GPIO_A: /* Enables the Standby GPIO retention feature for PAy */ + if (((GPIO_Pin & PWR_PORTA_AVAILABLE_PINS) == 0U) || \ + ((GPIO_Pin & (~PWR_PORTA_AVAILABLE_PINS)) != 0U)) + { + ret = HAL_ERROR; + } + else + { + SET_BIT(PWR->IORETENRA, GPIO_Pin); + } + break; + + case PWR_GPIO_B: /* Enables the Standby GPIO retention feature for PBy */ + if (((GPIO_Pin & PWR_PORTB_AVAILABLE_PINS) == 0U) || \ + ((GPIO_Pin & (~PWR_PORTB_AVAILABLE_PINS)) != 0U)) + { + ret = HAL_ERROR; + } + else + { + SET_BIT(PWR->IORETENRB, GPIO_Pin); + } + break; + + case PWR_GPIO_C: /* Enables the Standby GPIO retention feature for PCy */ + if (((GPIO_Pin & PWR_PORTC_AVAILABLE_PINS) == 0U) || \ + ((GPIO_Pin & (~PWR_PORTC_AVAILABLE_PINS)) != 0U)) + { + ret = HAL_ERROR; + } + else + { + SET_BIT(PWR->IORETENRC, GPIO_Pin); + } + break; + + case PWR_GPIO_H: /* Enables the Standby GPIO retention feature for PHy */ + if (((GPIO_Pin & PWR_PORTH_AVAILABLE_PINS) == 0U) || \ + ((GPIO_Pin & (~PWR_PORTH_AVAILABLE_PINS)) != 0U)) + { + ret = HAL_ERROR; + } + else + { + SET_BIT(PWR->IORETENRH, GPIO_Pin); + } + break; + + default: + ret = HAL_ERROR; + break; + } + + return ret; +} + +/** + * @brief Disable GPIO state retention in Standby mode. + * @note Clear the relevant Pxy bits of PWR_IORETENRx register to disable + * the I/O state retention in Standby mode. + * @note The configuration is kept when exiting the Standby mode. + * @param GPIO_Port : Specify the IO port. + * This parameter can be a value of + * @ref PWREx_GPIO_Port. + * @param GPIO_Pin : Specify the I/O pins numbers. + * This parameter can be a value of + * @ref PWREx_GPIO_Pin_Mask. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_PWREx_DisableStandbyIORetention(uint32_t GPIO_Port, uint32_t GPIO_Pin) +{ + HAL_StatusTypeDef ret = HAL_OK; + + /* Check the parameters */ + assert_param(IS_PWR_GPIO_PORT(GPIO_Port)); + assert_param(IS_PWR_GPIO_PIN_MASK(GPIO_Pin)); + + /* Check GPIO port */ + switch (GPIO_Port) + { + case PWR_GPIO_A: /* Disables the Standby GPIO retention feature for PAy */ + if (((GPIO_Pin & PWR_PORTA_AVAILABLE_PINS) == 0U) || \ + ((GPIO_Pin & (~PWR_PORTA_AVAILABLE_PINS)) != 0U)) + { + ret = HAL_ERROR; + } + else + { + CLEAR_BIT(PWR->IORETENRA, GPIO_Pin); + } + break; + + case PWR_GPIO_B: /* Disables the Standby GPIO retention feature for PBy */ + if (((GPIO_Pin & PWR_PORTB_AVAILABLE_PINS) == 0U) || \ + ((GPIO_Pin & (~PWR_PORTB_AVAILABLE_PINS)) != 0U)) + { + ret = HAL_ERROR; + } + else + { + CLEAR_BIT(PWR->IORETENRB, GPIO_Pin); + } + break; + + case PWR_GPIO_C: /* Disables the Standby GPIO retention feature for PCy */ + if (((GPIO_Pin & PWR_PORTC_AVAILABLE_PINS) == 0U) || \ + ((GPIO_Pin & (~PWR_PORTC_AVAILABLE_PINS)) != 0U)) + { + ret = HAL_ERROR; + } + else + { + CLEAR_BIT(PWR->IORETENRC, GPIO_Pin); + } + break; + + case PWR_GPIO_H: /* Disables the Standby GPIO retention feature for PHy */ + if (((GPIO_Pin & PWR_PORTH_AVAILABLE_PINS) == 0U) || \ + ((GPIO_Pin & (~PWR_PORTH_AVAILABLE_PINS)) != 0U)) + { + ret = HAL_ERROR; + } + else + { + CLEAR_BIT(PWR->IORETENRH, GPIO_Pin); + } + break; + + default: + ret = HAL_ERROR; + break; + } + + return ret; +} + +/** + * @brief Return for a given port for which IO the state was retained in Standby mode. + * @param GPIO_Port : Specify the IO port. + * This parameter can be a value of + * @ref PWREx_GPIO_Port. + * @note The API returns the whole set of IOs for a given GPIO. A '1' at GPIO_Pin + * position indicates that this IO state (pull or level) was retained when + * the device entered Standby mode. + * @retval HAL Status. + */ +uint32_t HAL_PWREx_GetStandbyIORetentionStatus(uint32_t GPIO_Port) +{ + /* Check the parameters */ + assert_param(IS_PWR_GPIO_PORT(GPIO_Port)); + + /* Check GPIO port Standby IO retention status */ + switch (GPIO_Port) + { + case PWR_GPIO_A: /* Get port A standby GPIO retention status */ + return READ_REG(PWR->IORETRA); + break; + + case PWR_GPIO_B: /* Get port B standby GPIO retention status */ + return READ_REG(PWR->IORETRB); + break; + + case PWR_GPIO_C: /* Get port C standby GPIO retention status */ + return READ_REG(PWR->IORETRC); + break; + + case PWR_GPIO_H: /* Get port H standby GPIO retention status */ + return READ_REG(PWR->IORETRH); + break; + + default: + return 0U; + break; + } +} + +/** + * @brief Disable the GPIO state retained in Standby mode + * @param GPIO_Port : Specify the IO port. + * This parameter can be a value of + * @ref PWREx_GPIO_Port. + * @param GPIO_Pin : Specify the I/O pins numbers. + * This parameter can be a value of + * @ref PWREx_GPIO_Pin_Mask. + * @note This API can be used to disable after Standby mode the IO state that + * was configured to be retained by HAL_PWREx_EnableStandbyIORetention(). + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_PWREx_DisableStandbyRetainedIOState(uint32_t GPIO_Port, uint32_t GPIO_Pin) +{ + HAL_StatusTypeDef ret = HAL_OK; + + /* Check the parameters */ + assert_param(IS_PWR_GPIO_PORT(GPIO_Port)); + assert_param(IS_PWR_GPIO_PIN_MASK(GPIO_Pin)); + + /* Check GPIO port */ + switch (GPIO_Port) + { + case PWR_GPIO_A: /* Disable the IO state (pull or level) retained for PAy in Standby mode */ + if (((GPIO_Pin & PWR_PORTA_AVAILABLE_PINS) == 0U) || \ + ((GPIO_Pin & (~PWR_PORTA_AVAILABLE_PINS)) != 0U)) + { + ret = HAL_ERROR; + } + else + { + CLEAR_BIT(PWR->IORETRA, GPIO_Pin); + } + break; + + case PWR_GPIO_B: /* Disable the IO state (pull or level) retained for PBy in Standby mode */ + if (((GPIO_Pin & PWR_PORTB_AVAILABLE_PINS) == 0U) || \ + ((GPIO_Pin & (~PWR_PORTB_AVAILABLE_PINS)) != 0U)) + { + ret = HAL_ERROR; + } + else + { + CLEAR_BIT(PWR->IORETRB, GPIO_Pin); + } + break; + + case PWR_GPIO_C: /* Disable the IO state (pull or level) retained for PCy in Standby mode */ + if (((GPIO_Pin & PWR_PORTC_AVAILABLE_PINS) == 0U) || \ + ((GPIO_Pin & (~PWR_PORTC_AVAILABLE_PINS)) != 0U)) + { + ret = HAL_ERROR; + } + else + { + CLEAR_BIT(PWR->IORETRC, GPIO_Pin); + } + break; + + case PWR_GPIO_H: /* Disable the IO state (pull or level) retained for PHy in Standby mode */ + if (((GPIO_Pin & PWR_PORTH_AVAILABLE_PINS) == 0U) || \ + ((GPIO_Pin & (~PWR_PORTH_AVAILABLE_PINS)) != 0U)) + { + ret = HAL_ERROR; + } + else + { + CLEAR_BIT(PWR->IORETRH, GPIO_Pin); + } + break; + + default: + ret = HAL_ERROR; + break; + } + + return ret; +} + +/** + * @} + */ + +/** @defgroup PWREx_Exported_Functions_Group6 I/O RADIO Configuration and Status Reading Functions + * @brief RADIO power amplifier setting and RADIO status reading functions + * +@verbatim + =============================================================================== + ##### RADIO configuration and status reading functions ##### + =============================================================================== +@endverbatim + * @{ + */ + +/** + * @brief Get the 2.4 GHz RADIO operating mode. + * @note The output can be any value from + * @ref PWREx_RADIO_Mode. + * @arg PWR_RADIO_DEEPSLEEP_MODE : 2.4 GHz RADIO deep sleep mode. + * @arg PWR_RADIO_SLEEP_MODE : 2.4 GHz RADIO sleep mode. + * @arg PWR_RADIO_ACTIVE_MODE : 2.4 GHz RADIO active mode. + * @retval The operating mode + */ +uint32_t HAL_PWREx_GetRADIOOperatingMode(void) +{ + uint32_t temp = READ_BIT(PWR->RADIOSCR, PWR_RADIOSCR_MODE); + + if ((temp & PWR_RADIOSCR_MODE_1) == PWR_RADIOSCR_MODE_1) + { + temp = PWR_RADIO_ACTIVE_MODE; + + } + return temp; +} + +/** + * @brief Get the 2.4 GHz RADIO PHY operating mode. + * @note The output can be any value from + * @ref PWREx_RADIO_PHY_Mode. + * @arg PWR_RADIO_PHY_SLEEP_MODE : 2.4 GHz RADIO PHY sleep mode. + * @arg PWR_RADIO_PHY_STANDBY_MODE : 2.4 GHz RADIO PHY standby mode. + * @retval The PHY operating mode + */ +uint32_t HAL_PWREx_GetRADIOPHYOperatingMode(void) +{ + return READ_BIT(PWR->RADIOSCR, PWR_RADIOSCR_PHYMODE); +} + +/** + * @brief Get the 2.4 GHz RADIO encryption operating mode. + * @note The output can be any value from + * @arg PWR_RADIO_ENCMODE_ENABLED : 2.4 GHz RADIO encryption function enabled. + * @arg PWR_RADIO_ENCMODE_DISABLED : 2.4 GHz RADIO encryption function disabled. + * @retval The Radio encryption operating mode + */ +uint32_t HAL_PWREx_GetRADIOEncryptionOperatingMode(void) +{ + return READ_BIT(PWR->RADIOSCR, PWR_RADIOSCR_ENCMODE); +} + +/** + * @brief Get the 2.4 GHz RADIO control. + * @note The output can be any value from + * Bits [3:0] output power table format + * Bit [4] rf_event. + * @retval The PHY operating mode + */ +uint32_t HAL_PWREx_GetRFVDDHPA(void) +{ + return READ_BIT(PWR->RADIOSCR, PWR_RADIOSCR_RFVDDHPA); +} + +#if defined(PWR_RADIOSCR_REGPASEL) +/** + * @brief Set the regulator REG_VDDHPA input supply selection. + * @param SupplySelection : Specifies the regulator REG_VDDHPA input supply. + * This parameter can be one of the following values : + * @arg PWR_RADIO_REG_VDDRFPA : VDDRFPA pin selected as regulator REG_VDDHPA input supply. + * @arg PWR_RADIO_REG_VDDHPA_VD11 : Regulator REG_VDDHPA input supply selection between VDDRFPA + * and VDD11 dependent on requested regulated output voltage. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_PWREx_SetREGVDDHPAInputSupply(uint32_t SupplySelection) +{ + /* Check the parameters */ + assert_param(IS_PWR_REGPASEL_SUPPLYSELECTION(SupplySelection)); + + MODIFY_REG(PWR->RADIOSCR, PWR_RADIOSCR_REGPASEL, SupplySelection); + + return HAL_OK; +} + +/** + * @brief Get the regulator REG_VDDHPA input supply selection. + * @note The output can be one of the following values : + * @arg PWR_RADIO_REG_VDDRFPA : VDDRFPA pin selected as regulator REG_VDDHPA input supply. + * @arg PWR_RADIO_REG_VDDHPA_VD11 : Regulator REG_VDDHPA input supply selection between VDDRFPA + * and VDD11 dependent on requested regulated output voltage. + * @retval The regulator REG_VDDHPA input supply selection. + */ +uint32_t HAL_PWREx_GetREGVDDHPAInputSupply(void) +{ + return READ_BIT(PWR->RADIOSCR, PWR_RADIOSCR_REGPASEL); +} +#endif /* defined(PWR_RADIOSCR_REGPASEL) */ + +#if defined(PWR_RADIOSCR_REGPABYPEN) +/** + * @brief Enable regulator REG_VDDHPA bypass + * @note Make 2.4 GHz RADIO PA 1.2 V supplied directly from internal VDD11. (only available when + * REGPASEL = 0) + * @note This API shall only be called when the VDDHPA regulator is not used + * @retval None. + */ +void HAL_PWREx_EnableREGVDDHPABypass(void) +{ + SET_BIT(PWR->RADIOSCR, PWR_RADIOSCR_REGPABYPEN); +} + +/** + * @brief Disable regulator REG_VDDHPA bypass + * @retval None. + */ +void HAL_PWREx_DisableREGVDDHPABypass(void) +{ + CLEAR_BIT(PWR->RADIOSCR, PWR_RADIOSCR_REGPABYPEN); +} +#endif /* defined(PWR_RADIOSCR_REGPABYPEN) */ + +/** + * @} + */ + +#endif /* defined(HAL_PWR_MODULE_ENABLED) */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_ramcfg.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_ramcfg.c new file mode 100644 index 0000000000..66d7e8071e --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_ramcfg.c @@ -0,0 +1,1122 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_ramcfg.c + * @author MCD Application Team + * @brief RAMCFG HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the RAMs configuration controller peripheral: + * + RAMCFG Initialization and De-initialization Functions. + * + RAMCFG Parity Error Detection Functions. + * + RAMCFG Configure Wait State Functions. + * + RAMCFG Write Protection Functions. + * + RAMCFG Erase Operation Functions. + * + RAMCFG Handle Interrupt and Callbacks Functions. + * + RAMCFG State and Error Functions. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### RAMCFG Peripheral features ##### + ============================================================================== + [..] + (+) Each SRAM is managed by a RAMCFG instance. + (++) SRAM1 placed in Core Domain. + (+++) Size = 64 kB (STM32WBA54xx, STM32WBA55xx) + (+++) Size = 16 kB (STM32WBA50xx) + (+++) Base Address = 0x20000000. + + (++) SRAM2 placed in Core Domain. + (+++) Size = 64 kB (STM32WBA54xx, STM32WBA55xx) + (+++) Size = 48 kB (STM32WBA50xx) + (+++) Base Address = 0x20010000. + + (++) SRAM6 controls the 2.4 GHz RADIO TXRX and sequence SRAMs. + + In what follows, only the wait state value can be set for SRAM6. Otherwise, + only SRAM1 and/or SRAM2 are considered. + + (+) Each SRAM can be erased independently through its RAMCFG instance. + + (+) The wait state value for each SRAM can be configured independently + through its RAMCFG instance. + + (+) SRAM2 is divided into 64 or 48 pages (depending on the product) with + 1 kB granularity. Each page can be write protected independently through + its RAMCFG instance. + + (+) SRAM2 supports Parity Error Detection (PED)correction feature. + When the ALE bit is set in RAMCFG SRAM2 control register (RAMCFG_M2CR), + the failing parity SRAM offset word address is stored in the RAMCFG SRAM2 + parity error address register RAMCFG_M2PEAR. + + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Call HAL_RAMCFG_Init() to initialize the RAMCFG peripheral before using + any feature. Call HAL_RAMCFG_DeInit() to de-initialize the RAMCFG when + using this peripheral is no more needed or a hardware issue has occurred. + + *** Parity Error Detection (PED) feature *** + ============================================ + [..] + (+) Parity is supported by SRAM2 when enabled with the SRAM2_PE user option bit + in FLASH_OPTR register. + + When enabling SRAM2 parity, it is advised to initialize by software the whole + RAM memory at the beginning of the code. This to avoid getting parity errors + when reading non-initialized addresses. + + (+) Call HAL_RAMCFG_EnableNotification() and HAL_RAMCFG_DisableNotification() + to enable and disable PED interrupts. Interrupts could be: + (++) Parity error detection interrupt. + (++) Parity error detection interrupt redirected to Non Maskable + interrupt (NMI). + + When a parity error is detected the PED and CPED bits are set in RAMCFG SRAM2 + interrupt status register (RAMCFG_M2ISR) and RAMCFG SRAM2 interrupt clear register + (RAMCFG_M2ICR). An interrupt or NMI can be generated if enabled by the PEIE or PENMI + bits in the RAMCFG SRAM2 control register (RAMCFG_M2CR). + + (+) Call HAL_RAMCFG_LatchParityErrorAddress() to set ALE bit and track parity error location address + + (+) Call HAL_RAMCFG_GetParityErrorAddress() to get the failing parity SRAM offset word + address stored in the RAMCFG parity error address register (RAMCFG_M2PEAR) together + with the failing byte(s) parity error flag and the AHB bus master ID. + + When the PED and CPED bits are already set any subsequent parity failing access SRAM + offset word address is no longer updated. A new parity error SRAM offset word address will + only be latched when PED and CPED are cleared. + + (+) Call HAL_RAMCFG_IsParityErrorDetected() to check if an Parity error was detected. + This API is used in silent mode (No PED interrupt is enabled). + + *** Wait State feature *** + ========================== + [..] + (+) Call HAL_RAMCFG_ConfigWaitState() to configure the wait state value + for a given SRAM according to the HCLK frequency and voltage range + scaling. + + (+) Call HAL_RAMCFG_GetWaitState() to get the current configured wait + state value. + + *** Write protection feature *** + ================================ + [..] + (+) Call HAL_RAMCFG_EnableWriteProtection() to enable the write + protection for the given SRAM2 page(s). + + (+) There is no API to disable write protection as this feature can + be disabled only by a global peripheral reset or system reset. + + (+) Any write access to a write protected area of SRAM2 causes a + HardFault interrupt. + + *** Erase feature *** + ===================== + [..] + (+) Call HAL_RAMCFG_Erase() to launch a hardware erase for the given + SRAM. + + (+) The erase value is equal to 0 when launching erase hardware through + RAMCFG. + + (+) SRAM2 write protected pages are erased when performing an erase + through RAMCFG. + + *** RAMCFG HAL driver macros list *** + ===================================== + [..] + Below the list of used macros in RAMCFG HAL driver. + + (+) __HAL_RAMCFG_ENABLE_IT : Enable the specified RAMCFG interrupts. + (+) __HAL_RAMCFG_DISABLE_IT : Disable the specified RAMCFG interrupts. + (+) __HAL_RAMCFG_GET_FLAG : Get the RAMCFG pending flags. + (+) __HAL_RAMCFG_CLEAR_FLAG : Clear the RAMCFG pending flags. + (+) __HAL_RAMCFG_GET_IT_SOURCE : Check whether the specified RAMCFG + interrupt source is enabled or not. + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @defgroup RAMCFG RAMCFG + * @brief RAMCFG HAL module driver + * @{ + */ + +#ifdef HAL_RAMCFG_MODULE_ENABLED + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ + +/** @addtogroup RAMCFG_Private_Constants + * @{ + */ +#define RAMCFG_TIMEOUT_VALUE 50000U +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup RAMCFG_Exported_Functions + * @{ + */ + +/** @addtogroup RAMCFG_Exported_Functions_Group1 + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization Functions ##### + =============================================================================== + [..] + This section provides functions to initialize and de-initialize the + RAMCFG instance. + [..] + The HAL_RAMCFG_Init() function follows the RAMCFG instance configuration + procedures as described in the reference manual. + The HAL_RAMCFG_DeInit() function allows deinitializing the RAMCFG instance. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the RAMCFG by clearing flags and disabling interrupts. + * @param hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that contains + * the configuration information for the specified RAMCFG + * instance. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_RAMCFG_Init(RAMCFG_HandleTypeDef *hramcfg) +{ + /* Check the RAMCFG peripheral handle */ + if (hramcfg == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RAMCFG_ALL_INSTANCE(hramcfg->Instance)); + + /* Update RAMCFG peripheral state */ + hramcfg->State = HAL_RAMCFG_STATE_BUSY; + +#if (USE_HAL_RAMCFG_REGISTER_CALLBACKS == 1U) + + /* Init the low level hardware */ + /* Check if a valid MSP API was registered */ + if (hramcfg->MspInitCallback == NULL) + { + /* Legacy callback */ + hramcfg->MspInitCallback = HAL_RAMCFG_MspInit; + } + hramcfg->MspInitCallback(hramcfg); +#else + HAL_RAMCFG_MspInit(hramcfg); +#endif /* USE_HAL_RAMCFG_REGISTER_CALLBACKS */ + + /* Initialize the RAMCFG error code */ + hramcfg->ErrorCode = HAL_RAMCFG_ERROR_NONE; + + /* Initialize the RAMCFG state */ + hramcfg->State = HAL_RAMCFG_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitialize the RAMCFG peripheral. + * @param hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that contains + * the configuration information for the specified RAMCFG + * instance. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_RAMCFG_DeInit(RAMCFG_HandleTypeDef *hramcfg) +{ + /* Check the RAMCFG peripheral handle */ + if (hramcfg == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RAMCFG_ALL_INSTANCE(hramcfg->Instance)); + + /* Disable the PED feature */ + hramcfg->Instance->CR &= ~(RAMCFG_CR_ALE); + + /* Disable all RAMCFG interrupts */ + __HAL_RAMCFG_DISABLE_IT(hramcfg, RAMCFG_IT_ALL); + + /* Clear RAMCFG monitor flags */ + __HAL_RAMCFG_CLEAR_FLAG(hramcfg, RAMCFG_FLAG_PARITYERR); + +#if (USE_HAL_RAMCFG_REGISTER_CALLBACKS == 1U) + /* Check if a valid MSP API was registered */ + if (hramcfg->MspDeInitCallback != NULL) + { + /* Init the low level hardware */ + hramcfg->MspDeInitCallback(hramcfg); + } + + /* Clean callbacks */ + hramcfg->DetectParityErrorCallback = NULL; +#else + HAL_RAMCFG_MspDeInit(hramcfg); +#endif /* USE_HAL_RAMCFG_REGISTER_CALLBACKS */ + + /* Reset the RAMCFG error code */ + hramcfg->ErrorCode = HAL_RAMCFG_ERROR_NONE; + + /* Reset the RAMCFG state */ + hramcfg->State = HAL_RAMCFG_STATE_RESET; + + return HAL_OK; +} + +/** + * @brief Initialize the RAMCFG MSP. + * @param hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that contains + * the configuration information for the specified RAMCFG. + * @retval None. + */ +__weak void HAL_RAMCFG_MspInit(RAMCFG_HandleTypeDef *hramcfg) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hramcfg); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RAMCFG_MspInit can be implemented in the user file */ +} + +/** + * @brief DeInitialize the RAMCFG MSP. + * @param hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that contains + * the configuration information for the specified RAMCFG. + * @retval None. + */ +__weak void HAL_RAMCFG_MspDeInit(RAMCFG_HandleTypeDef *hramcfg) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hramcfg); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RAMCFG_MspDeInit can be implemented in the user file */ +} +/** + * @} + */ + +/** @addtogroup RAMCFG_Exported_Functions_Group2 + * +@verbatim + =============================================================================== + ##### (Parity Error Detection) PED Operations Functions ##### + =============================================================================== + [..] + This section provides functions to manage Parity Error Detection + (PED) feature provided by the RAMCFG peripheral. + [..] + The HAL_RAMCFG_LatchParityErrorAddress() function allows enabling the parity error + fail address latch for the selected RAMCFG instance. + The HAL_RAMCFG_UnlatchParityErrorAddress() function allows disabling the parity error + fail address latch for the selected RAMCFG instance. + The HAL_RAMCFG_EnableNotification() function allows enabling interrupts + for parity error detection and NMI error. + The HAL_RAMCFG_DisableNotification() function allows disabling interrupts + for parity error detection. When NMI interrupt is enabled, it can only be + disabled by a global peripheral reset or by a system reset. + The HAL_RAMCFG_IsParityErrorDetected() function allows checking if a parity + error is detected. + The HAL_RAMCFG_GetParityErrorAddress() function allows getting the address of + the parity error detected. This address is defined by three elements parts of + the structure RAMCFG_PEAddressTypeDef: + (+) byte : Byte parity error flag + 1xxx: parity error detected on 4th byte in word aligned address + x1xx: parity error detected on 3rd byte in word aligned address + xx1x: parity error detected on 2th byte in word aligned address + xxx1: parity error detected on 1st byte in word aligned address + (+) ID : Parity error AHB bus master ID + (+) AddressOffset: Parity error SRAM word aligned address offset + +@endverbatim + * @{ + */ + +/** + * @brief Parity error fail address latch enable. + * @param hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that contains + * the configuration information for the specified RAMCFG + * instance. + * @note Parity Error Detection mechanism is enabled in setting SRAM2_PE user + * option bit in FLASH_OPTR register. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_RAMCFG_LatchParityErrorAddress(RAMCFG_HandleTypeDef *hramcfg) +{ + /* Check the parameters */ + assert_param(IS_RAMCFG_PED_INSTANCE(hramcfg->Instance)); + + /* Check RAMCFG state */ + if (hramcfg->State == HAL_RAMCFG_STATE_READY) + { + /* Update RAMCFG peripheral state */ + hramcfg->State = HAL_RAMCFG_STATE_BUSY; + + /* Enable parity error fail address latch */ + SET_BIT(hramcfg->Instance->CR, RAMCFG_CR_ALE); + } + else + { + /* Update the error code */ + hramcfg->ErrorCode = HAL_RAMCFG_ERROR_BUSY; + + /* Return error status */ + return HAL_ERROR; + } + + /* Update the RAMCFG state */ + hramcfg->State = HAL_RAMCFG_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Parity error fail address latch disable + * @param hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that contains + * the configuration information for the specified RAMCFG + * instance. + * @note Parity Error Detection mechanism is disabled in clearing SRAM2_PE user + * option bit in FLASH_OPTR register. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_RAMCFG_UnlatchParityErrorAddress(RAMCFG_HandleTypeDef *hramcfg) +{ + /* Check the parameters */ + assert_param(IS_RAMCFG_PED_INSTANCE(hramcfg->Instance)); + + /* Check RAMCFG state */ + if (hramcfg->State == HAL_RAMCFG_STATE_READY) + { + /* Update RAMCFG peripheral state */ + hramcfg->State = HAL_RAMCFG_STATE_BUSY; + + /* Disable parity error fail address latch */ + CLEAR_BIT(hramcfg->Instance->CR, RAMCFG_CR_ALE); + } + else + { + /* Update the error code */ + hramcfg->ErrorCode = HAL_RAMCFG_ERROR_BUSY; + + /* Return error status */ + return HAL_ERROR; + } + + /* Update the RAMCFG state */ + hramcfg->State = HAL_RAMCFG_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Enable the RAMCFG error interrupts. + * @param hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that + * contains the configuration information for the + * specified RAMCFG instance. + * @param Notifications : Select the notification to be enabled. + * This parameter could be any value of @ref RAMCFG_Interrupt group. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_RAMCFG_EnableNotification(RAMCFG_HandleTypeDef *hramcfg, uint32_t Notifications) +{ + /* Check the parameters */ + assert_param(IS_RAMCFG_PED_INSTANCE(hramcfg->Instance)); + assert_param(IS_RAMCFG_INTERRUPT(Notifications)); + + /* Check RAMCFG state */ + if (hramcfg->State == HAL_RAMCFG_STATE_READY) + { + /* Update RAMCFG peripheral state */ + hramcfg->State = HAL_RAMCFG_STATE_BUSY; + + /* Enable RAMCFG interrupts */ + __HAL_RAMCFG_ENABLE_IT(hramcfg, Notifications); + } + else + { + /* Update the error code */ + hramcfg->ErrorCode = HAL_RAMCFG_ERROR_BUSY; + + /* Return error status */ + return HAL_ERROR; + } + + /* Update the RAMCFG state */ + hramcfg->State = HAL_RAMCFG_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Disable the RAMCFG error interrupts. + * @param hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that + * contains the configuration information for the + * specified RAMCFG instance. + * @param Notifications : Select the notification to be disabled. + * This parameter could be : + * RAMCFG_IT_PARITYERR : Parity Error Detection. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_RAMCFG_DisableNotification(RAMCFG_HandleTypeDef *hramcfg, uint32_t Notifications) +{ + /* Check the parameters */ + assert_param(IS_RAMCFG_PED_INSTANCE(hramcfg->Instance)); + assert_param(IS_RAMCFG_INTERRUPT(Notifications)); + + /* Check RAMCFG state */ + if (hramcfg->State == HAL_RAMCFG_STATE_READY) + { + /* Update RAMCFG peripheral state */ + hramcfg->State = HAL_RAMCFG_STATE_BUSY; + + /* Disable RAMCFG interrupts */ + __HAL_RAMCFG_DISABLE_IT(hramcfg, Notifications); + } + else + { + /* Update the error code */ + hramcfg->ErrorCode = HAL_RAMCFG_ERROR_BUSY; + + /* Return error status */ + return HAL_ERROR; + } + + /* Update the RAMCFG state */ + hramcfg->State = HAL_RAMCFG_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Check if a parity error was detected. + * @param hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that + * contains the configuration information for the + * specified RAMCFG instance. + * @retval State of bit (1 or 0). + */ +uint32_t HAL_RAMCFG_IsParityErrorDetected(const RAMCFG_HandleTypeDef *hramcfg) +{ + /* Check the parameters */ + assert_param(IS_RAMCFG_PED_INSTANCE(hramcfg->Instance)); + + /* Return the state of PED flag */ + return ((READ_BIT(hramcfg->Instance->ISR, RAMCFG_FLAG_PARITYERR) == (RAMCFG_FLAG_PARITYERR)) ? 1UL : 0UL); +} + +/** + * @brief Get the RAMCFG parity error address. + * @param hramcfg Pointer to a RAMCFG_HandleTypeDef structure that + * contains the configuration information for the + * specified RAMCFG instance. + * @param sPEAddress Pointer to a structure filled with all the information relevant to parity error address + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_RAMCFG_GetParityErrorAddress(const RAMCFG_HandleTypeDef *hramcfg, RAMCFG_PEAddressTypeDef *sPEAddress) +{ + uint32_t tmp; + /* Check the parameters */ + assert_param(IS_RAMCFG_PED_INSTANCE(hramcfg->Instance)); + + tmp = READ_REG(hramcfg->Instance->PEAR); + sPEAddress->Byte = (tmp & RAMCFG_PEAR_BYTE_Msk) >> RAMCFG_PEAR_BYTE_Pos; + sPEAddress->BusMasterId = (tmp & RAMCFG_PEAR_ID_Msk) >> RAMCFG_PEAR_ID_Pos; + sPEAddress->AddressOffset = (tmp & RAMCFG_PEAR_PEA_Msk) >> RAMCFG_PEAR_PEA_Pos; + + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup RAMCFG_Exported_Functions_Group3 + * +@verbatim + =============================================================================== + ##### Wait State Functions ##### + =============================================================================== + [..] + This section provides functions to get and configure the wait state + value . + [..] + The HAL_RAMCFG_ConfigWaitState() function allows configuring the wait state + value. + The HAL_RAMCFG_GetWaitState() function allows getting the current wait state + value. + +@endverbatim + * @{ + */ + +/** + * @brief Configure the wait state value for the given SRAM. + * @param hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that + * contains the configuration information for the + * specified RAMCFG instance. + * @param WaitState : Select the value of wait state to be configured. + * This parameter could be any value of @ref RAMCFG_WaitState group + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_RAMCFG_ConfigWaitState(RAMCFG_HandleTypeDef *hramcfg, uint32_t WaitState) +{ + /* Check the parameters */ + assert_param(IS_RAMCFG_ALL_INSTANCE(hramcfg->Instance)); + assert_param(IS_RAMCFG_WAITSTATE(WaitState)); + + /* Get RAMCFG state */ + if (hramcfg->State == HAL_RAMCFG_STATE_READY) + { + /* Update RAMCFG peripheral state */ + hramcfg->State = HAL_RAMCFG_STATE_BUSY; + + /* Set the SRAM wait state */ + hramcfg->Instance->CR = WaitState; + } + else + { + /* Update the error code */ + hramcfg->ErrorCode = HAL_RAMCFG_ERROR_BUSY; + + return HAL_ERROR; + } + + /* Update RAMCFG peripheral state */ + hramcfg->State = HAL_RAMCFG_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Get the current wait state value for the given SRAM. + * @param hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that + * contains the configuration information for the + * specified RAMCFG instance. + * @retval Wait state value, part of @ref RAMCFG_WaitState group. + */ +uint32_t HAL_RAMCFG_GetWaitState(const RAMCFG_HandleTypeDef *hramcfg) +{ + /* Check the parameters */ + assert_param(IS_RAMCFG_ALL_INSTANCE(hramcfg->Instance)); + + /* Return the configured wait state number */ + return (hramcfg->Instance->CR & RAMCFG_CR_WSC); +} +/** + * @} + */ + +/** @addtogroup RAMCFG_Exported_Functions_Group4 + * +@verbatim + =============================================================================== + ##### Write Protection Functions ##### + =============================================================================== + [..] + This section provides functions to enable write protection feature for + the page(s) of SRAM2. + [..] + The HAL_RAMCFG_EnableWriteProtection() function allows enabling the write + protection for the page(s) of SRAM2. + Disabling SRAM2 page(s) protection is performed only by a global + peripheral reset or a by a system reset. + +@endverbatim + * @{ + */ + +/** + * @brief Enable write protection for the given page(s). + * @note Write protection feature could be disabled only by system reset. + * @param hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that + * contains the configuration information for the + * specified RAMCFG instance. + * @param StartPage : Select the start page number (from 0 to 63) + * @param NbPage : Number of pages to be protected. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_RAMCFG_EnableWriteProtection(RAMCFG_HandleTypeDef *hramcfg, uint32_t StartPage, uint32_t NbPage) +{ + uint32_t page_mask_0 = 0U; + uint32_t page_mask_1 = 0U; + + /* Check the parameters */ + assert_param(IS_RAMCFG_WP_INSTANCE(hramcfg->Instance)); + assert_param(IS_RAMCFG_WRITEPROTECTION_PAGE(StartPage + NbPage)); + + /* Check RAMCFG state */ + if (hramcfg->State == HAL_RAMCFG_STATE_READY) + { + /* Update RAMCFG peripheral state */ + hramcfg->State = HAL_RAMCFG_STATE_BUSY; + + /* Repeat for page number to be protected */ + for (uint32_t count = 0U; count < NbPage; count++) + { + if ((StartPage + count) < 32U) + { + page_mask_0 |= (1UL << (StartPage + count)); + } + else + { + page_mask_1 |= (1UL << ((StartPage + count) - 32U)); + } + } + + /* Apply mask to protect pages */ + WRITE_REG(hramcfg->Instance->WPR1, page_mask_0); + WRITE_REG(hramcfg->Instance->WPR2, page_mask_1); + } + else + { + /* Update the error code */ + hramcfg->ErrorCode = HAL_RAMCFG_ERROR_BUSY; + + /* Return error status */ + return HAL_ERROR; + } + + /* Update the RAMCFG state */ + hramcfg->State = HAL_RAMCFG_STATE_READY; + + return HAL_OK; +} +/** + * @} + */ + +/** @addtogroup RAMCFG_Exported_Functions_Group5 + * +@verbatim + =============================================================================== + ##### Erase Operation Functions ##### + =============================================================================== + [..] + This section provides functions allowing a hardware erase for the given SRAM. + [..] + The HAL_RAMCFG_Erase() function allowing a hardware mass erase for the given + SRAM. The erase value for all SRAMs is 0. + +@endverbatim + * @{ + */ + +/** + * @brief Launches and waits for the mass erase completion of a given SRAM. + * @param hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that + * contains the configuration information for the + * specified RAMCFG instance. + + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_RAMCFG_Erase(RAMCFG_HandleTypeDef *hramcfg) +{ + uint32_t tickstart = HAL_GetTick(); + + /* Check the parameters */ + assert_param(IS_RAMCFG_ER_INSTANCE(hramcfg->Instance)); + + /* Check RAMCFG state */ + if (hramcfg->State == HAL_RAMCFG_STATE_READY) + { + /* Update RAMCFG peripheral state */ + hramcfg->State = HAL_RAMCFG_STATE_BUSY; + + /* Unlock the RAMCFG erase bit */ + WRITE_REG(hramcfg->Instance->ERKEYR, RAMCFG_ERASE_KEY1); + WRITE_REG(hramcfg->Instance->ERKEYR, RAMCFG_ERASE_KEY2); + + /* Start the SRAM erase operation */ + SET_BIT(hramcfg->Instance->CR, RAMCFG_CR_SRAMER); + + /* Wait for the SRAM hardware erase operation to complete by polling on + SRAMBUSY flag to be reset. */ + while (__HAL_RAMCFG_GET_FLAG(hramcfg, RAMCFG_FLAG_SRAMBUSY) != 0U) + { + if ((HAL_GetTick() - tickstart) > RAMCFG_TIMEOUT_VALUE) + { + /* Update the RAMCFG error code */ + hramcfg->ErrorCode = HAL_RAMCFG_ERROR_TIMEOUT; + + /* Update the RAMCFG state */ + hramcfg->State = HAL_RAMCFG_STATE_ERROR; + + /* Return error status */ + return HAL_ERROR; + } + } + } + else + { + /* Update the error code */ + hramcfg->ErrorCode = HAL_RAMCFG_ERROR_BUSY; + + /* Return error status */ + return HAL_ERROR; + } + + /* Update the RAMCFG state */ + hramcfg->State = HAL_RAMCFG_STATE_READY; + + return HAL_OK; +} +/** + * @} + */ + +/** @addtogroup RAMCFG_Exported_Functions_Group6 + * +@verbatim + =============================================================================== + ##### Handle Interrupt and Callbacks Functions ##### + =============================================================================== + [..] + This section provides functions to handle RAMCFG interrupts and + Register / UnRegister the different callbacks. + [..] + The HAL_RAMCFG_IRQHandler() function allows handling the active RAMCFG + interrupt request. + The HAL_RAMCFG_RegisterCallback() function allows registering the selected + RAMCFG callbacks. + The HAL_RAMCFG_UnRegisterCallback() function allows unregistering the + selected RAMCFG callbacks. +@endverbatim + * @{ + */ + +/** + * @brief Handles RAMCFG interrupt request. + * @param hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that + * contains the configuration information for the + * specified RAMCFG instance. + * @retval None. + */ +void HAL_RAMCFG_IRQHandler(RAMCFG_HandleTypeDef *hramcfg) +{ + /* Single Error Interrupt Management ****************************************/ + if (__HAL_RAMCFG_GET_IT_SOURCE(hramcfg, RAMCFG_IT_PARITYERR) != 0U) + { + if (__HAL_RAMCFG_GET_FLAG(hramcfg, RAMCFG_FLAG_PARITYERR) != 0U) + { + /* Clear active flags */ + __HAL_RAMCFG_CLEAR_FLAG(hramcfg, RAMCFG_FLAG_PARITYERR); + +#if (USE_HAL_RAMCFG_REGISTER_CALLBACKS == 1U) + /* Check if a valid single error callback is registered */ + if (hramcfg->DetectParityErrorCallback == NULL) + { + /* Legacy callback */ + hramcfg->DetectParityErrorCallback = HAL_RAMCFG_DetectParityErrorCallback; + } + hramcfg->DetectParityErrorCallback(hramcfg); +#else + HAL_RAMCFG_DetectParityErrorCallback(hramcfg); +#endif /* USE_HAL_RAMCFG_REGISTER_CALLBACKS */ + } + } +} + +/** + * @brief RAMCFG parity error detection callback. + * @param hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that contains + * the configuration information for the specified RAMCFG. + * @retval None. + */ +__weak void HAL_RAMCFG_DetectParityErrorCallback(RAMCFG_HandleTypeDef *hramcfg) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hramcfg); + + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_RAMCFG_DetectParityErrorCallback can be implemented in + the user file. */ +} + +#if (USE_HAL_RAMCFG_REGISTER_CALLBACKS == 1U) +/** + * @brief Register RAMCFG callbacks. + * @param hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that + * contains the configuration information for the + * specified RAMCFG instance. + * @param CallbackID : User Callback identifier a HAL_RAMCFG_CallbackIDTypeDef + * ENUM as parameter. + * @param pCallback : Pointer to private callback function. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_RAMCFG_RegisterCallback(RAMCFG_HandleTypeDef *hramcfg, + HAL_RAMCFG_CallbackIDTypeDef CallbackID, + void (* pCallback)(RAMCFG_HandleTypeDef *_hramcfg)) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hramcfg->ErrorCode = HAL_RAMCFG_ERROR_INVALID_CALLBACK; + + /* Return error status */ + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RAMCFG_ALL_INSTANCE(hramcfg->Instance)); + + /* Check RAMCFG state */ + if (hramcfg->State == HAL_RAMCFG_STATE_READY) + { + switch (CallbackID) + { + case HAL_RAMCFG_PE_DETECT_CB_ID: + /* Register parity error detection callback */ + hramcfg->DetectParityErrorCallback = pCallback; + break; + + case HAL_RAMCFG_MSPINIT_CB_ID : + /* Register msp init callback */ + hramcfg->MspInitCallback = pCallback; + break; + + case HAL_RAMCFG_MSPDEINIT_CB_ID : + /* Register msp de-init callback */ + hramcfg->MspDeInitCallback = pCallback; + break; + + default: + /* Update the error code */ + hramcfg->ErrorCode = HAL_RAMCFG_ERROR_INVALID_CALLBACK; + + /* Update return status */ + status = HAL_ERROR; + break; + } + } + else if (hramcfg->State == HAL_RAMCFG_STATE_RESET) + { + switch (CallbackID) + { + case HAL_RAMCFG_MSPINIT_CB_ID : + /* Register msp init callback */ + hramcfg->MspInitCallback = pCallback; + break; + + case HAL_RAMCFG_MSPDEINIT_CB_ID : + /* Register msp de-init callback */ + hramcfg->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hramcfg->ErrorCode = HAL_RAMCFG_ERROR_INVALID_CALLBACK; + + /* Update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hramcfg->ErrorCode = HAL_RAMCFG_ERROR_INVALID_CALLBACK; + + /* Update return status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief UnRegister RAMCFG callbacks. + * @param hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that + * contains the configuration information for the + * specified RAMCFG instance. + * @param CallbackID : User Callback identifier a HAL_RAMCFG_CallbackIDTypeDef + * ENUM as parameter. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_RAMCFG_UnRegisterCallback(RAMCFG_HandleTypeDef *hramcfg, HAL_RAMCFG_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_RAMCFG_ALL_INSTANCE(hramcfg->Instance)); + + /* Check RAMCFG state */ + if (hramcfg->State == HAL_RAMCFG_STATE_READY) + { + switch (CallbackID) + { + case HAL_RAMCFG_PE_DETECT_CB_ID: + /* UnRegister parity error detection callback */ + hramcfg->DetectParityErrorCallback = NULL; + break; + + case HAL_RAMCFG_MSPINIT_CB_ID : + /* UnRegister msp init callback */ + hramcfg->MspInitCallback = NULL; + break; + + case HAL_RAMCFG_MSPDEINIT_CB_ID : + /* UnRegister msp de-init callback */ + hramcfg->MspDeInitCallback = NULL; + break; + + case HAL_RAMCFG_ALL_CB_ID: + /* UnRegister all available callbacks */ + hramcfg->DetectParityErrorCallback = NULL; + hramcfg->MspDeInitCallback = NULL; + hramcfg->MspInitCallback = NULL; + break; + + default: + /* Update the error code */ + hramcfg->ErrorCode = HAL_RAMCFG_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hramcfg->State == HAL_RAMCFG_STATE_RESET) + { + switch (CallbackID) + { + case HAL_RAMCFG_MSPINIT_CB_ID : + /* UnRegister msp init callback */ + hramcfg->MspInitCallback = NULL; + break; + + case HAL_RAMCFG_MSPDEINIT_CB_ID : + /* UnRegister msp de-init callback */ + hramcfg->MspDeInitCallback = NULL; + break; + + case HAL_RAMCFG_ALL_CB_ID: + /* UnRegister all available callbacks */ + hramcfg->MspDeInitCallback = NULL; + hramcfg->MspInitCallback = NULL; + break; + + default : + /* Update the error code */ + hramcfg->ErrorCode = HAL_RAMCFG_ERROR_INVALID_CALLBACK; + + /* Update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hramcfg->ErrorCode = HAL_RAMCFG_ERROR_INVALID_CALLBACK; + + /* Update return status */ + status = HAL_ERROR; + } + + return status; +} +/** + * @} + */ +#endif /* USE_HAL_RAMCFG_REGISTER_CALLBACKS */ + +/** @addtogroup RAMCFG_Exported_Functions_Group7 + * +@verbatim + =============================================================================== + ##### State and Error Functions ##### + =============================================================================== + [..] + This section provides functions to check and get the RAMCFG state + and the error code . + [..] + The HAL_RAMCFG_GetState() function allows getting the RAMCFG peripheral + state. + The HAL_RAMCFG_GetError() function allows getting the RAMCFG peripheral error + code. + +@endverbatim + * @{ + */ + +/** + * @brief Get the RAMCFG peripheral state. + * @param hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that + * contains the configuration information for the + * specified RAMCFG instance. + * @retval RAMCFG state. + */ +HAL_RAMCFG_StateTypeDef HAL_RAMCFG_GetState(const RAMCFG_HandleTypeDef *hramcfg) +{ + /* Check the parameters */ + assert_param(IS_RAMCFG_ALL_INSTANCE(hramcfg->Instance)); + + /* Return the RAMCFG state */ + return hramcfg->State; +} + +/** + * @brief Get the RAMCFG peripheral error code. + * @param hramcfg : Pointer to a RAMCFG_HandleTypeDef structure that + * contains the configuration information for the + * specified RAMCFG instance. + * @retval RAMCFG error code. + */ +uint32_t HAL_RAMCFG_GetError(const RAMCFG_HandleTypeDef *hramcfg) +{ + /* Check the parameters */ + assert_param(IS_RAMCFG_ALL_INSTANCE(hramcfg->Instance)); + + /* Return the RAMCFG error code */ + return hramcfg->ErrorCode; +} +/** + * @} + */ + + +#endif /* HAL_RAMCFG_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_rcc.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_rcc.c new file mode 100644 index 0000000000..d9e342f11a --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_rcc.c @@ -0,0 +1,1820 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_rcc.c + * @author MCD Application Team + * @brief RCC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Reset and Clock Control (RCC) peripheral: + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### RCC specific features ##### + ============================================================================== + [..] + After reset the device is running from High Speed Internal oscillator + (from 8 MHz to reach 16MHz) with Flash 0 wait state. Flash prefetch buffer + is disabled. + (+) There is no prescaler on High speed (AHBs) except for AHB5 and no + prescaler Low speed (APBs) busses: all peripherals mapped on these + busses are running at HSI speed. + (+) The clock for all peripherals is switched off, except SRAMs and FLASH. + (+) All GPIOs are in analog mode, except the JTAG pins which + are assigned to be used for debug purpose. + + [..] + Once the device started, the user application has to: + (+) Configure the clock source to be used to drive the System clock + (if the application needs higher frequency/performance) + (+) Configure the System clock frequency and Flash settings + (+) Configure the AHB and APB busses prescalers + (+) Enable the clock for the peripheral(s) to be used + (+) Configure the kernel clock source(s) for peripherals which clocks are + not derived from the System clock. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @defgroup RCC RCC + * @brief RCC HAL module driver + * @{ + */ + +#ifdef HAL_RCC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup RCC_Private_Constants RCC Private Constants + * @{ + */ +/* timeout value */ +/* LSI maximum timeout is 16 us plus 4 LSI clock cycles when prediv is used */ +#define LSI_TIMEOUT_VALUE ((5u * 128u * 1000u) / LSI_VALUE) +#define PLL_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ +#define PLL_FRAC_WAIT_VALUE 1U /* PLL Fractional part waiting time before new latch enable : 1 ms */ +#define PLL1_NDIV_TIMEOUT_VALUE 10U /* SYSCLK divider delay when going from divide to not divide. 10 ms when 2-steps */ +#define CLOCKSWITCH_TIMEOUT_VALUE 5000U /* 5 s */ +#define PLL_INPUTRANGE0_FREQMAX 8000000u /* 8 MHz is maximum frequency for VCO input range 0 */ +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup RCC_Private_Macros RCC Private Macros + * @{ + */ +#define __MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() +#define MCO1_GPIO_PORT GPIOA +#define MCO1_PIN GPIO_PIN_8 +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ + +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup RCC_Private_Functions RCC Private Functions + * @{ + */ +static float_t RCC_PLL1_GetVCOOutputFreq(void); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Functions RCC Exported Functions + * @{ + */ + +/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * + @verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to configure the internal and external oscillators + (HSE, HSI, LSE, LSI (LSI1 or LSI2), PLL1, CSS and MCO) and the System busses clocks (SYSCLK, + AHB1, AHB2, AHB4, AHB5, APB1, APB2 and APB7). + + [..] Internal/external clock and PLL1 configuration + (+) HSI (high-speed internal): 16 MHz factory-trimmed RC used directly or through + the PLL1 as System clock source. + + (+) LSI (low-speed internal): + (++) LSI1: 32 kHz low-speed low power internal RC that drives the independent watchdog + and optionally the RTC used for auto-wakeup from Stop and Standby modes + (++) LSI2: 32 kHz low-speed low drift internal RC that drives optionally the RTC or + 2.4 GHz RADIO sleep timer used for auto-wakeup from Stop and Standby modes. + + (+) HSE (high-speed external): 32 MHz crystal oscillator used directly or + through the PLL1 as System clock source. Can be used also optionally as RTC clock source. + + (+) LSE (low-speed external): 32.768 KHz oscillator used optionally as RTC clock source + and 2.4 GHz RADIO sleep timer. + + (+) PLL1 (clocked by HSI or HSE) providing up to three independent output clocks: + (++) The P output is used to generate an accurate clock to achieve + high-quality audio performance on SAI interface and ADC4. + (++) The Q output is used to generate the clock for the SAI1 and RNG. + (++) The R output is used to generate the high speed system clock (up to 100MHz). + + (+) CSS (Clock security system): once enabled, if a HSE clock failure occurs + (HSE used directly or through PLL1 as System clock source), the System clock + is automatically switched to HSI and an interrupt is generated if enabled. + The interrupt is linked to the Cortex-M33 NMI (Non-Maskable Interrupt) + exception vector. + + (+) MCO (microcontroller clock output): used to output LSI, HSI, LSE, HSE32, SYSCLK, HCLK5 and + PLL1 R, P, Q clocks (through a configurable prescaler) on PA8 pin. + + [..] System, AHB and APB busses clocks configuration + (+) Several clock sources can be used to drive the System clock (SYSCLK): HSI, + HSE and main PLL1. + The AHB clock (HCLK) is derived from System clock through configurable + prescaler and used to clock the CPU, memory and peripherals mapped + on AHB bus (DMA, GPIO...). APB1 (PCLK1), APB2 (PCLK2) and APB7 (PCLK7) clocks are derived + from AHB clock through configurable prescalers and used to clock + the peripherals mapped on these busses. You can use + "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. + + -@- All the peripheral kernel clocks are derived from the System clock (SYSCLK) but some + peripheral can select a different source (you have to use HAL_RCCEx_PeriphCLKConfig() + function to configure it) : + (+@) U(S)ARTx (x = 1, 2) : Kernel clock can be PCLKx, SYSCLK, HSI or LSE. + (+@) I2Cx (x = 1, 3) : Kernel clock can be PCLKx, SYSCLK or HSI. + (+@) LPTIMx (x = 1, 2) : Kernel clock can be PCLKx, LSI, HSI or LSE. + (+@) SPIx (x = 1, 3) : Kernel clock can be PCLKx, SYSCLK or HSI. + (+@) SAI1 : Kernel clock can be PLL1P, PLL1Q, SYSCLK, a clock provided on CKIN pin or HSI. + (+@) RNG : Kernel clock can be LSE, LSI, HSI or PLL1Q. + (+@) LPUART1 : Kernel clock can be PCLKx, SYSCLK, HSI or LSE. + (+@) RTC : Kernel clock can be derived either from the LSI, LSE or HSE clock divided by 32. + (+@) ADC4 : Kernel clock can be HCLK, SYSCLK, PLL1P, HSE or HSI clock. + (+@) 2.4 GHz RADIO sleep timer : Kernel clock can be LSE, LSI, or HSE divided by 1000 clock. + + + (+) The maximum frequency of SYSCLK / AHB1 / AHB2 / AHB4 / APB1 / APB2 / APB7 is + (++) 100 MHz at voltage range 1 + (++) 16 MHZ at voltage range 2 + + (+) The maximum frequency of AHB5 is + (++) 32 MHz at voltage range 1 + (++) 12 MHZ at voltage range 2 + + The clock source frequency should be adapted depending on the device voltage range + as listed in the Reference Manual "Clock source frequency versus voltage scaling" chapter. + + @endverbatim + + (++) Table 1. HCLK clock frequency for STM32WBAxx devices + (++) +-------------------------------------------------------+ + (++) | Latency | HCLK clock frequency (MHz) | + (++) | |-------------------------------------| + (++) | | voltage scaling | voltage scaling | + (++) | | range 1 | range 1 | + (++) |-----------------|------------------|------------------| + (++) |0WS(1 CPU cycles)| HCLK <= 32 | HCLK <= 8 | + (++) |-----------------|------------------|------------------| + (++) |1WS(2 CPU cycles)| HCLK <= 64 | HCLK <= 16 | + (++) |-----------------|------------------|------------------| + (++) |2WS(3 CPU cycles)| HCLK <= 96 | - | + (++) |-----------------|------------------|------------------| + (++) |3WS(4 CPU cycles)| HCLK <= 100 | - | + (++) +-----------------+------------------+------------------+ + * @{ + */ + +/** + * @brief Reset the RCC clock configuration to the default reset state. + * @note The default reset state of the clock configuration is given below: + * - HSI ON and used as system clock source + * - HSE and PLL1 OFF + * - AHB, APB1, APB2 and APB7 prescaler set to 1. + * - CSS, MCO1 OFF + * - All interrupts disabled and cleared + * @note This function doesn't modify the configuration of the + * - Peripheral clocks + * - LSI, LSE and RTC clocks + * @retval None + */ +HAL_StatusTypeDef HAL_RCC_DeInit(void) +{ + uint32_t tickstart; + + /* Get start tick*/ + tickstart = HAL_GetTick(); + + /* Set HSION bit */ + SET_BIT(RCC->CR, RCC_CR_HSION); + + /* Wait till HSI is ready */ + while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Set HSITRIM default value */ + MODIFY_REG(RCC->ICSCR3, RCC_ICSCR3_HSITRIM, 0x00100000U); + + /* Get start tick*/ + tickstart = HAL_GetTick(); + + /* Reset CFGR1 register (HSI is selected as system clock source) */ + CLEAR_REG(RCC->CFGR1); + + /* Wait till clock switch is ready */ + while (READ_BIT(RCC->CFGR1, RCC_CFGR1_SWS) != 0U) + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Set AHBx and APBx prescaler to their default values */ + CLEAR_REG(RCC->CFGR2); + CLEAR_REG(RCC->CFGR3); + WRITE_REG(RCC->CFGR4, 0x00000010); + + /* Clear CR register in 2 steps: first to clear HSEON in case bypass was enabled */ + RCC->CR = RCC_CR_HSION; + + /* Then again to HSEBYP in case bypass was enabled */ + RCC->CR = RCC_CR_HSION; + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Wait till PLL1 is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLL1RDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Reset PLL1CFGR register */ + CLEAR_REG(RCC->PLL1CFGR); + + /* Reset PLL1DIVR register */ + WRITE_REG(RCC->PLL1DIVR, 0x01010280U); + + /* Reset PLL1FRACR register */ + CLEAR_REG(RCC->PLL1FRACR); + + /* Disable all interrupts */ + CLEAR_REG(RCC->CIER); + + /* Clear all interrupts flags */ + WRITE_REG(RCC->CICR, 0xFFFFFFFFU); + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HSI_VALUE; + + /* Adapt Systick interrupt period */ + if (HAL_InitTick(uwTickPrio) != HAL_OK) + { + return HAL_ERROR; + } + else + { + return HAL_OK; + } +} + + +/** + * @brief Initialize the RCC Oscillators according to the specified parameters in the + * RCC_OscInitTypeDef. + * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that + * contains the configuration information for the RCC Oscillators. + * @note The PLL1 is not disabled when used as system clock. + * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not + * supported by this function. User should request a transition to HSE Off + * first and then to HSE On or HSE Bypass. + * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not + * supported by this function. User should request a transition to LSE Off + * first and then LSE On or LSE Bypass. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + uint32_t tickstart; + uint32_t sysclksrc; + uint32_t pllsrc; + uint32_t tmpreg1; + uint32_t tmpreg2; + uint32_t mask; + + /* Check Null pointer */ + if (RCC_OscInitStruct == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); + + sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); + pllsrc = __HAL_RCC_GET_PLL1_OSCSOURCE(); + + /*------------------------------- HSE Configuration ------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + { + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); + + /* When the HSE is used as system clock or clock source for PLL1 in these cases it is not allowed to be disabled */ + if ((sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSE) || + ((sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pllsrc == RCC_PLLSOURCE_HSE))) + { + if (RCC_OscInitStruct->HSEState == RCC_HSE_OFF) + { + return HAL_ERROR; + } + else + { + /* Otherwise, applying divider is allowed */ + if (sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSE) + { + assert_param(IS_RCC_HSEDIV(RCC_OscInitStruct->HSEDiv)); + + /* Adjust the HSE division factor */ + __HAL_RCC_HSE_CONFIG(RCC_HSE_ON | RCC_OscInitStruct->HSEDiv); + + /* Update the SystemCoreClock global variable with HSE value */ + SystemCoreClock = (HSE_VALUE / (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSEPRE)) >> RCC_CR_HSEPRE_Pos))); + + /* Adapt Systick interrupt period */ + if (HAL_InitTick(uwTickPrio) != HAL_OK) + { + return HAL_ERROR; + } + } + } + } + else + { + /* Check the HSE State */ + if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) + { + assert_param(IS_RCC_HSEDIV(RCC_OscInitStruct->HSEDiv)); + + /* Set the new HSE configuration ---------------------------------------*/ + __HAL_RCC_HSE_CONFIG((RCC_OscInitStruct->HSEState | RCC_OscInitStruct->HSEDiv)); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSE is ready */ + while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Set the new HSE configuration ---------------------------------------*/ + __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSE is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + + /*----------------------------- HSI Configuration --------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + { + /* Check the parameters */ + assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); + assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); + + /* Check if HSI is used as system clock or as PLL1 source when PLL1 is selected as system clock */ + if ((sysclksrc == RCC_SYSCLKSOURCE_STATUS_HSI) || + ((sysclksrc == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pllsrc == RCC_PLLSOURCE_HSI))) + { + /* When HSI is used as system clock it will not be disabled */ + if (RCC_OscInitStruct->HSIState == RCC_HSI_OFF) + { + return HAL_ERROR; + } + /* Otherwise, just the calibration is allowed */ + else + { + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + } + } + else + { + /* Check the HSI State */ + if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) + { + /* Enable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSI is ready */ + while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + } + else + { + /* Disable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSI is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + + /*------------------------------ LSI Configuration -------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + { + /* Check the parameters */ + assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); + + FlagStatus pwrclkchanged = RESET; + + /* Update LSI1 configuration in Backup Domain control register */ + /* Requires to enable write access to Backup Domain of necessary */ + if (__HAL_RCC_PWR_IS_CLK_ENABLED() != 0x01) + { + __HAL_RCC_PWR_CLK_ENABLE(); + pwrclkchanged = SET; + } + + if (HAL_IS_BIT_CLR(PWR->DBPR, PWR_DBPR_DBP)) + { + /* Enable write access to Backup domain */ + SET_BIT(PWR->DBPR, PWR_DBPR_DBP); + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + + while (HAL_IS_BIT_CLR(PWR->DBPR, PWR_DBPR_DBP)) + { + if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Get BDCR1 register value */ + tmpreg1 = RCC->BDCR1; + + /* Define mask depending on LSI presence */ + mask = RCC_BDCR1_LSI1ON; +#if defined(RCC_LSI2_SUPPORT) + mask |= RCC_BDCR1_LSI2ON; +#endif /* RCC_LSI2_SUPPORT */ + + /* Check the LSI1 State */ + if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF) + { + if ((RCC_OscInitStruct->LSIState & RCC_LSI1_ON) != 0x00u) + { + /* Check LSI1 division factor */ + assert_param(IS_RCC_LSIDIV(RCC_OscInitStruct->LSIDiv)); + + /* Check is LSIDiv is requested to be changed and LSI is already ON */ + if ((RCC_OscInitStruct->LSIDiv != (tmpreg1 & RCC_BDCR1_LSI1PREDIV)) && ((tmpreg1 & RCC_BDCR1_LSI1RDY) != 0x00u)) + { + /* Disable LSI1 */ + tmpreg1 &= ~RCC_BDCR1_LSI1ON; + RCC->BDCR1 = tmpreg1; + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSI1 is disabled */ + while (READ_BIT(RCC->BDCR1, RCC_BDCR1_LSI1RDY) != 0x00u) + { + if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + { + /* LSI1 may be forced ON by IWDG */ + return HAL_TIMEOUT; + } + } +#if defined(STM32WBAXX_SI_CUT1_0) + /* Wait at least 1 half LSI clock period before apppling new LSI1 prediv value */ + HAL_Delay(1); +#endif + } + + /* Set LSI1 division factor */ + tmpreg1 &= ~RCC_BDCR1_LSI1PREDIV; + tmpreg1 |= RCC_OscInitStruct->LSIDiv; + } + + /* Enable Concerned LSI */ + tmpreg1 |= RCC_OscInitStruct->LSIState; + RCC->BDCR1 = tmpreg1; + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSI is ready : LSIRDY bit is position ON shifted by 1 */ + while (READ_BIT(RCC->BDCR1, (RCC_OscInitStruct->LSIState << 1)) == 0x00u) + { + if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + +#if defined(RCC_LSI2_SUPPORT) + /* Disable other LSI in case it was ON */ + mask ^= RCC_OscInitStruct->LSIState; + tmpreg1 &= ~mask; + RCC->BDCR1 = tmpreg1; + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till other LSI is disabled */ + while (READ_BIT(RCC->BDCR1, (mask << 1)) != 0x00u) + { + if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } +#endif + } + else + { + /* Disable the Internal Low Speed oscillator LSI1 and LSI2 is available */ + tmpreg1 &= ~mask; + RCC->BDCR1 = tmpreg1; + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSI is disabled : LSIRDY bit position is ON shifted by 1 */ + while (READ_BIT(RCC->BDCR1, (mask << 1)) != 0x00u) + { + if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + /* Restore clock configuration if changed */ + if (pwrclkchanged == SET) + { + __HAL_RCC_PWR_CLK_DISABLE(); + } + } + + /*------------------------------ LSE Configuration -------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + { + FlagStatus pwrclkchanged = RESET; + + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); + + /* Update LSE configuration in Backup Domain control register */ + /* Requires to enable write access to Backup Domain of necessary */ + if (__HAL_RCC_PWR_IS_CLK_ENABLED() != 0x01) + { + __HAL_RCC_PWR_CLK_ENABLE(); + pwrclkchanged = SET; + } + + if (HAL_IS_BIT_CLR(PWR->DBPR, PWR_DBPR_DBP)) + { + /* Enable write access to Backup domain */ + SET_BIT(PWR->DBPR, PWR_DBPR_DBP); + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + + while (HAL_IS_BIT_CLR(PWR->DBPR, PWR_DBPR_DBP)) + { + if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Set the new LSE configuration -----------------------------------------*/ + /* Check the LSE State */ + if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) + { + /* If LSE is already on or in bypass mode, only LSE system can be modified */ + tmpreg1 = (RCC->BDCR1 & ~RCC_BDCR1_LSESYSEN); + tmpreg1 |= RCC_OscInitStruct->LSEState; + RCC->BDCR1 = tmpreg1; + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while (READ_BIT(RCC->BDCR1, RCC_BDCR1_LSERDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Enable LSESYS additionally if requested */ + if ((RCC_OscInitStruct->LSEState & RCC_BDCR1_LSESYSEN) != 0U) + { + /* Wait till LSESYS is ready */ + while (READ_BIT(RCC->BDCR1, RCC_BDCR1_LSESYSRDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Wait till LSESYSRDY is cleared */ + while (READ_BIT(RCC->BDCR1, RCC_BDCR1_LSESYSRDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + else + { + CLEAR_BIT(RCC->BDCR1, (RCC_BDCR1_LSEON | RCC_BDCR1_LSESYSEN)); + CLEAR_BIT(RCC->BDCR1, RCC_BDCR1_LSEBYP); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSE is disabled */ + while (READ_BIT(RCC->BDCR1, RCC_BDCR1_LSERDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + if (READ_BIT(RCC->BDCR1, RCC_BDCR1_LSESYSEN) != 0U) + { + /* Wait till LSESYSRDY is cleared */ + while (READ_BIT(RCC->BDCR1, RCC_BDCR1_LSESYSRDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + + /* Restore clock configuration if changed */ + if (pwrclkchanged == SET) + { + __HAL_RCC_PWR_CLK_DISABLE(); + } + } + + /*-------------------------------- PLL1 Configuration -----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL1.PLLState)); + + if ((RCC_OscInitStruct->PLL1.PLLState) != RCC_PLL_NONE) + { + /* Check if the PLL1 is used as system clock or not */ + if (sysclksrc != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + { + if ((RCC_OscInitStruct->PLL1.PLLState) == RCC_PLL_ON) + { + /* Check the parameters */ + assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL1.PLLSource)); + assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL1.PLLM)); + assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL1.PLLN)); + assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL1.PLLP)); + assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL1.PLLQ)); + assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL1.PLLR)); + + /* Disable the main PLL1. */ + tmpreg1 = (RCC->CR & ~RCC_CR_PLL1ON); + RCC->CR = tmpreg1; + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL1 is disabled */ + do + { + tmpreg1 = RCC->CR; + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } while ((tmpreg1 & RCC_CR_PLL1RDY) != 0U); + + /* Compute VCO input frequency and define range accordingly. First check clock source frequency */ + if (RCC_OscInitStruct->PLL1.PLLSource == RCC_PLLSOURCE_HSE) + { + /* Clock source is HSE or HSE/2 */ + pllsrc = HSE_VALUE >> ((tmpreg1 & RCC_CR_HSEPRE) >> RCC_CR_HSEPRE_Pos); + } + else + { + /* Clock source is HSI */ + pllsrc = HSI_VALUE; + } + + /* Compute VCO input frequency depending on M divider */ + pllsrc = (pllsrc / RCC_OscInitStruct->PLL1.PLLM); + assert_param(IS_RCC_PLL_VCOINPUTFREQ(pllsrc)); + + if (pllsrc > PLL_INPUTRANGE0_FREQMAX) + { + /* Reuse pllsrc local variable to store range */ + pllsrc = RCC_PLL_VCOINPUT_RANGE1; + } + else + { + /* Reuse pllsrc local variable to store range */ + pllsrc = RCC_PLL_VCOINPUT_RANGE0; + } + + /* Configure PLL1 source, PLLM divider, VCO input range and enable PLL1R output. Clear also FRACEN*/ + tmpreg2 = RCC->PLL1CFGR; + tmpreg2 &= ~(RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1RGE | RCC_PLL1CFGR_PLL1FRACEN | RCC_PLL1CFGR_PLL1M); + tmpreg2 |= (RCC_OscInitStruct->PLL1.PLLSource | pllsrc | + ((RCC_OscInitStruct->PLL1.PLLM - 1u) << RCC_PLL1CFGR_PLL1M_Pos) | RCC_PLL1CFGR_PLL1REN); + RCC->PLL1CFGR = tmpreg2; + + /* Configure PLLN multiplication factor and PLLP, PLLQ, PLLR dividers */ + tmpreg2 = ((RCC_OscInitStruct->PLL1.PLLN - 1u) | + ((RCC_OscInitStruct->PLL1.PLLP - 1u) << RCC_PLL1DIVR_PLL1P_Pos) | + ((RCC_OscInitStruct->PLL1.PLLQ - 1u) << RCC_PLL1DIVR_PLL1Q_Pos) | + ((RCC_OscInitStruct->PLL1.PLLR - 1u) << RCC_PLL1DIVR_PLL1R_Pos)); + RCC->PLL1DIVR = tmpreg2; + + if (RCC_OscInitStruct->PLL1.PLLFractional != 0x00u) + { + assert_param(IS_RCC_PLLFRACN_VALUE(RCC_OscInitStruct->PLL1.PLLFractional)); + + /* Configure PLL1 PLL1FRACN */ + __HAL_RCC_PLL1_FRACN_CONFIG(RCC_OscInitStruct->PLL1.PLLFractional); + + /* Enable PLL1FRACEN */ + __HAL_RCC_PLL1_FRACN_ENABLE(); + } + + /* Enable the main PLL1. */ + __HAL_RCC_PLL1_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL1 is ready */ + while (READ_BIT(RCC->CR, RCC_CR_PLL1RDY) == 0U) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the main PLL1. */ + __HAL_RCC_PLL1_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL1 is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLL1RDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* CLear the PLL1 source and disable outputs to save power when PLL1 is off */ + CLEAR_BIT(RCC->PLL1CFGR, (RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1PEN | \ + RCC_PLL1CFGR_PLL1QEN | RCC_PLL1CFGR_PLL1REN)); + } + } + else + { + /* Check if there is a request to disable the PLL1 used as System clock source */ + if ((RCC_OscInitStruct->PLL1.PLLState) == RCC_PLL_OFF) + { + return HAL_ERROR; + } + else + { + /* Do not return HAL_ERROR if request repeats the current configuration */ + tmpreg1 = RCC->PLL1CFGR; + tmpreg2 = RCC->PLL1DIVR; + + if (((tmpreg1 & RCC_PLL1CFGR_PLL1SRC) != RCC_OscInitStruct->PLL1.PLLSource) || + (((tmpreg1 & RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos) != (RCC_OscInitStruct->PLL1.PLLM - 1u)) || + (((tmpreg2 & RCC_PLL1DIVR_PLL1N) >> RCC_PLL1DIVR_PLL1N_Pos) != (RCC_OscInitStruct->PLL1.PLLN - 1u)) || + (((tmpreg2 & RCC_PLL1DIVR_PLL1P) >> RCC_PLL1DIVR_PLL1P_Pos) != (RCC_OscInitStruct->PLL1.PLLP - 1u)) || + (((tmpreg2 & RCC_PLL1DIVR_PLL1Q) >> RCC_PLL1DIVR_PLL1Q_Pos) != (RCC_OscInitStruct->PLL1.PLLQ - 1u)) || + (((tmpreg2 & RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) != (RCC_OscInitStruct->PLL1.PLLR - 1u))) + { + return HAL_ERROR; + } + else + { + /* Check if only fractional part needs to be updated */ + tmpreg1 = ((RCC->PLL1FRACR & RCC_PLL1FRACR_PLL1FRACN) >> RCC_PLL1FRACR_PLL1FRACN_Pos); + + if (RCC_OscInitStruct->PLL1.PLLFractional != tmpreg1) + { + assert_param(IS_RCC_PLLFRACN_VALUE(RCC_OscInitStruct->PLL1.PLLFractional)); + + /* Disable PLL1FRACEN */ + __HAL_RCC_PLL1_FRACN_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait at least 2 CK_REF (PLL input source divided by M) period to make sure next latched value will be taken into account. */ + while ((HAL_GetTick() - tickstart) < PLL_FRAC_WAIT_VALUE) + { + } + + /* Configure PLL1 PLL1FRACN */ + __HAL_RCC_PLL1_FRACN_CONFIG(RCC_OscInitStruct->PLL1.PLLFractional); + + /* Enable PLL1FRACEN to latch new value. */ + __HAL_RCC_PLL1_FRACN_ENABLE(); + } + } + } + } + } + return HAL_OK; +} + +/** + * @brief Initialize the CPU, AHB and APB bus clocks according to the specified + * parameters in the RCC_ClkInitStruct. + * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that + * contains the configuration information for the RCC peripheral. + * @param FLatency FLASH Latency + * This parameter can be one of the following values: + * @arg FLASH_LATENCY_0 FLASH 0 Latency cycle + * @arg FLASH_LATENCY_1 FLASH 1 Latency cycle + * @arg FLASH_LATENCY_2 FLASH 2 Latency cycles + * @arg FLASH_LATENCY_3 FLASH 3 Latency cycles + * @arg FLASH_LATENCY_4 FLASH 4 Latency cycles + * @arg FLASH_LATENCY_5 FLASH 5 Latency cycles + * @arg FLASH_LATENCY_6 FLASH 6 Latency cycles + * @arg FLASH_LATENCY_7 FLASH 7 Latency cycles + * @arg FLASH_LATENCY_8 FLASH 8 Latency cycles + * @arg FLASH_LATENCY_9 FLASH 9 Latency cycles + * @arg FLASH_LATENCY_10 FLASH 10 Latency cycles + * @arg FLASH_LATENCY_11 FLASH 11 Latency cycles + * @arg FLASH_LATENCY_12 FLASH 12 Latency cycles + * @arg FLASH_LATENCY_13 FLASH 13 Latency cycles + * @arg FLASH_LATENCY_14 FLASH 14 Latency cycles + * @arg FLASH_LATENCY_15 FLASH 15 Latency cycles + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency. + * @note The HSI (16 MHz) is used by default as system clock source after + * startup from Reset, wake-up from STANDBY mode. + * @note A switch from one clock source to another occurs only if the target + * clock source is ready (clock stable after startup delay or PLL1 locked). + * If a clock source which is not yet ready is selected, the switch will + * occur when the clock source is ready. + * @note You can use HAL_RCC_GetClockConfig() function to know which clock is + * currently used as system clock source. + * @note The SYSCLK shall only be switched to a higher frequency when incremental + * frequency step is 47 MHz. When this is not respected device operation cannot + * be guaranteed. For bigger incremental frequency steps the PLL1RCLKPRE division + * shall be used. + * @note HCLK5 frequency shall not be higher than 32 MHz in range 1, 12 MHz in range 2. + * Two different fields allow to configure HCLK5 prescaler: one when System clock + * source is to PLL1, other for any other sources. + * HCLK5 prescaler is switched automatically by hardware, but configuration shall + * always be performed before setting new PLL1 source as Sysclk source. + * @retval None + */ +HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) +{ + uint32_t tmpreg1; + uint32_t update; + uint32_t tickstart; + + /* Check Null pointer */ + if (RCC_ClkInitStruct == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType)); + assert_param(IS_FLASH_LATENCY(FLatency)); + + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the CPU clock + (HCLK) and the supply voltage of the device. */ + + /* Increasing the number of wait states because of higher CPU frequency */ + if (FLatency > __HAL_FLASH_GET_LATENCY()) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if (__HAL_FLASH_GET_LATENCY() != FLatency) + { + return HAL_ERROR; + } + } + + /*-------------------------- HCLK5 Configuration --------------------------*/ + /* HCLK5 prescaler is switched automatically by hardware, but configuration shall + always be performed before setting new PLL1 source as Sysclk source. */ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK5) == RCC_CLOCKTYPE_HCLK5) + { + assert_param(IS_RCC_HCLK5_HSEHSI(RCC_ClkInitStruct->AHB5_HSEHSI_CLKDivider)); + assert_param(IS_RCC_HCLK5_PLL1(RCC_ClkInitStruct->AHB5_PLL1_CLKDivider)); + MODIFY_REG(RCC->CFGR4, (RCC_CFGR4_HDIV5 | RCC_CFGR4_HPRE5), + (RCC_ClkInitStruct->AHB5_PLL1_CLKDivider | RCC_ClkInitStruct->AHB5_HSEHSI_CLKDivider)); + } + + /*------------------------- SYSCLK Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + { + assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); + + /* Read CR register */ + tmpreg1 = RCC->CR; + + /* PLL1 is selected as System Clock Source */ + if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + { + /* Check the PLL1 ready flag */ + if ((tmpreg1 & RCC_CR_PLL1RDY) == 0U) + { + return HAL_ERROR; + } + else + { + if (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR1_SWS_Pos)) + { + /* Whatever is PLL frequency, use step prediv to reach maximum frequency. */ + /* Select pll1r to be prediv with 2-step divider when selected as Sysclk source */ + MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1RCLKPRESTEP, RCC_PLL1CFGR_PLL1RCLKPRE); +#if defined(STM32WBAXX_SI_CUT1_0) + /* add 2 pulse on CLKPRE bit : clear and set it back */ + CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1RCLKPRE); + SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1RCLKPRE); + CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1RCLKPRE); + SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1RCLKPRE); +#endif + } + } + } + else + { + /* HSE is selected as System Clock Source */ + if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + { + /* Check the HSE ready flag */ + if ((tmpreg1 & RCC_CR_HSERDY) == 0U) + { + return HAL_ERROR; + } + } + /* HSI is selected as System Clock Source */ + else + { + /* Check the HSI ready flag */ + if ((tmpreg1 & RCC_CR_HSIRDY) == 0U) + { + return HAL_ERROR; + } + } + } + + /* Switch System clock source */ + MODIFY_REG(RCC->CFGR1, RCC_CFGR1_SW, RCC_ClkInitStruct->SYSCLKSource); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR1_SWS_Pos)) + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* If PLL1rCLK is asked to be SYSCLK source, clear prediv. */ + if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + { + /* Set PLL1R prediv to not divided */ + CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1RCLKPRE); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait until PLL1 not divided is ready */ + while ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1RCLKPRERDY) == 0x00u) + { + if ((HAL_GetTick() - tickstart) > PLL1_NDIV_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + + /* Get CFGR2 content value, and reset update variable */ + tmpreg1 = RCC->CFGR2; + update = 0x00u; + + /*-------------------------- HCLK Configuration --------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + { + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + + /* update HCLK1 divider and notify register is required */ + tmpreg1 &= ~RCC_CFGR2_HPRE; + tmpreg1 |= RCC_ClkInitStruct->AHBCLKDivider; + update = 0x01u; + } + + + /*-------------------------- PCLK1 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); + + /* update PCLK1 divider and notify register is required */ + tmpreg1 &= ~RCC_CFGR2_PPRE1; + tmpreg1 |= RCC_ClkInitStruct->APB1CLKDivider; + update = 0x01u; + } + + /*-------------------------- PCLK2 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); + + /* update PCLK2 divider and notify register is required */ + tmpreg1 &= ~RCC_CFGR2_PPRE2; + tmpreg1 |= (RCC_ClkInitStruct->APB2CLKDivider << (RCC_CFGR2_PPRE2_Pos - RCC_CFGR2_PPRE1_Pos)); + update = 0x01u; + } + + /* update CFGR2 if required */ + if (update != 0x00u) + { + RCC->CFGR2 = tmpreg1; + } + + /*-------------------------- PCLK7 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK7) == RCC_CLOCKTYPE_PCLK7) + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB7CLKDivider)); + WRITE_REG(RCC->CFGR3, RCC_ClkInitStruct->APB7CLKDivider); + } + + /* Decreasing the number of wait states because of lower CPU frequency */ + if (FLatency < __HAL_FLASH_GET_LATENCY()) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if (__HAL_FLASH_GET_LATENCY() != FLatency) + { + return HAL_ERROR; + } + } + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR2 & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos]; + + /* Configure the source of time base considering new system clocks settings*/ + return HAL_InitTick(uwTickPrio); +} + +/** + * @} + */ + +/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions + * @brief RCC clocks control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to: + + (+) Output clock to MCO pin. + (+) Retrieve current clock frequencies. + (+) Enable the Clock Security System. + +@endverbatim + * @{ + */ + +/** + * @brief Select the clock source to output on MCO pin (PA8). + * @note PA8 should be configured in alternate function mode. + * @param RCC_MCOx specifies the output direction for the clock source. + * For STM32WBAxx family this parameter can have only one value: + * @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8). + * @param RCC_MCOSource specifies the clock source to output. + * This parameter can be one of the following values: + * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled, no clock on MCO + * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_PLL1RCLK PLL1R clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_PLL1PCLK PLL1P clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_PLL1QCLK PLL1Q clock selected as MCO source + * @arg @ref RCC_MCO1SOURCE_HCLK5 HCLK5 clock selected as MCO source + * @param RCC_MCODiv specifies the MCO prescaler. + * This parameter can be one of the following values: + * @arg @ref RCC_MCODIV_1 no division applied to MCO clock + * @arg @ref RCC_MCODIV_2 division by 2 applied to MCO clock + * @arg @ref RCC_MCODIV_4 division by 4 applied to MCO clock + * @arg @ref RCC_MCODIV_8 division by 8 applied to MCO clock + * @arg @ref RCC_MCODIV_16 division by 16 applied to MCO clock + * @retval None + */ +void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) +{ + GPIO_InitTypeDef GPIO_InitStruct; + + /* Check the parameters */ + assert_param(IS_RCC_MCO(RCC_MCOx)); + assert_param(IS_RCC_MCODIV(RCC_MCODiv)); + assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); + + /* MCO Clock Enable */ + __MCO1_CLK_ENABLE(); + + /* Configure the MCO1 pin in alternate function mode */ + GPIO_InitStruct.Pin = MCO1_PIN; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Alternate = GPIO_AF0_MCO; + HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct); + + /* Mask MCOSEL[] and MCOPRE[] bits then set MCO1 clock source and prescaler */ + MODIFY_REG(RCC->CFGR1, (RCC_CFGR1_MCOSEL | RCC_CFGR1_MCOPRE), (RCC_MCOSource | RCC_MCODiv)); +} + +/** + * @brief Return the SYSCLK frequency. + * @note The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) + * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**) + * @note If SYSCLK source is PLL1, function returns values based on HSE_VALUE(**), + * HSI_VALUE(*) or MSI Value multiplied/divided by the PLL1 factors. + * @note (*) HSI_VALUE is a constant defined in stm32wbaxx_hal_conf.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * @note (**) HSE_VALUE is a constant defined in stm32wbaxx_hal_conf.h file (default value + * 32 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * @note The result of this function could be not correct when using fractional + * value for HSE crystal. + * @note This function can be used by the user application to compute the + * baudrate for the communication peripherals or configure other parameters. + * @note Each time SYSCLK changes, this function must be called to update the + * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. + * @retval SYSCLK frequency + */ +uint32_t HAL_RCC_GetSysClockFreq(void) +{ + uint32_t sysclk; + + /* Get SYSCLK source */ + sysclk = __HAL_RCC_GET_SYSCLK_SOURCE(); + + if (sysclk == RCC_SYSCLKSOURCE_STATUS_HSI) + { + /* HSI used as system clock source */ + sysclk = HSI_VALUE; + } + else if (sysclk == RCC_SYSCLKSOURCE_STATUS_HSE) + { + /* HSE used as system clock source. Check if HSE is divided by 2 */ + sysclk = (HSE_VALUE >> ((RCC->CR & RCC_CR_HSEPRE) >> RCC_CR_HSEPRE_Pos)); + } + else + { + /* PLL1 used as system clock source */ + sysclk = HAL_RCC_GetPLL1RFreq(); + } + + return sysclk; +} + +/** + * @brief Return the HCLK frequency. + * @note Each time HCLK changes, this function must be called to update the + * right HCLK value. Otherwise, any configuration based on this function will be incorrect. + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency. + * @retval HCLK frequency in Hz + */ +uint32_t HAL_RCC_GetHCLKFreq(void) +{ + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR2 & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos]; + return SystemCoreClock; +} + +/** + * @brief Return the PCLK1 frequency. + * @note Each time PCLK1 changes, this function must be called to update the + * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK1 frequency in Hz + */ +uint32_t HAL_RCC_GetPCLK1Freq(void) +{ + /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR2 & RCC_CFGR2_PPRE1) >> RCC_CFGR2_PPRE1_Pos]); +} + +/** + * @brief Return the PCLK2 frequency. + * @note Each time PCLK2 changes, this function must be called to update the + * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK2 frequency in Hz + */ +uint32_t HAL_RCC_GetPCLK2Freq(void) +{ + /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR2 & RCC_CFGR2_PPRE2) >> RCC_CFGR2_PPRE2_Pos]); +} + +/** + * @brief Return the PCLK7 frequency. + * @note Each time PCLK7 changes, this function must be called to update the + * right PCLK7 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK7 frequency in Hz + */ +uint32_t HAL_RCC_GetPCLK7Freq(void) +{ + /* Get HCLK source and Compute PCLK7 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR3 & RCC_CFGR3_PPRE7) >> RCC_CFGR3_PPRE7_Pos]); +} + +/** + * @brief Return the HCLK5 frequency. + * @note Each time HCLK5 changes, this function must be called to update the + * right HCLK5 value. Otherwise, any configuration based on this function will be incorrect. + * @note HCLK5 frequency depends on System clock source : + - whenever PLL1 is selected as System clock source, HPRE5 prescaler is internally used to + divide SYSCLK frequency and feed HCLK5. + - whenever HSI or HSE are selected as System clock source, HDIV5 prescaler is internally used to + divide SYSCLK frequency and feed HCLK5. + * right HCLK5 value. Otherwise, any configuration based on this function will be incorrect. + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency. + * @retval HCLK frequency in Hz + */ +uint32_t HAL_RCC_GetHCLK5Freq(void) +{ + uint32_t tmp; + uint32_t hclk5freq; + + /* Get source of SYSCLK */ + tmp = (RCC->CFGR1 & RCC_CFGR1_SWS); + + /* Depending on SYSCLK source */ + if (tmp != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + { + /* HSI or HSE are source of SYSCLK, compute divider */ + tmp = (RCC->CFGR4 & RCC_CFGR4_HDIV5) >> RCC_CFGR4_HDIV5_Pos; + tmp += 1u; + } + else + { + /* PLL1 is source of SYSCLK, compute prescaler */ + tmp = AHB5PrescTable[(RCC->CFGR4 & RCC_CFGR4_HPRE5)]; + } + + /* Get SYCLK frequency */ + hclk5freq = (HAL_RCC_GetSysClockFreq() / tmp); + + return hclk5freq; +} + +/** + * @brief Return the PLL1P frequency. + * @retval PLL1P frequency in Hz + */ +uint32_t HAL_RCC_GetPLL1PFreq(void) +{ + uint32_t pllp; + + /* PLL1P divider */ + pllp = ((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1P) >> RCC_PLL1DIVR_PLL1P_Pos) + 1U; + + /* Compute VCO output frequency and return PLL1P one */ + return ((uint32_t)RCC_PLL1_GetVCOOutputFreq() / pllp); +} + +/** + * @brief Return the PLL1Q frequency. + * @retval PLL1Q frequency in Hz + */ +uint32_t HAL_RCC_GetPLL1QFreq(void) +{ + uint32_t pllq; + + /* PLL1Q divider */ + pllq = ((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1Q) >> RCC_PLL1DIVR_PLL1Q_Pos) + 1U; + + /* Compute VCO output frequency and return PLL1Q one */ + return ((uint32_t)RCC_PLL1_GetVCOOutputFreq() / pllq); +} + +/** + * @brief Return the PLL1R frequency. + * @retval PLL1R frequency in Hz + */ +uint32_t HAL_RCC_GetPLL1RFreq(void) +{ + uint32_t pllr; + + /* PLL1R divider */ + pllr = ((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1U; + + /* Compute VCO output frequency and return PLL1R one */ + return ((uint32_t)RCC_PLL1_GetVCOOutputFreq() / pllr); +} + +/** + * @brief Configure the RCC_OscInitStruct according to the internal + * RCC configuration registers. + * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that + * will be configured. + * @retval None + */ +void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + uint32_t regvalue; + uint32_t mask; + + /* Check the parameters */ + assert_param(RCC_OscInitStruct != (void *)NULL); + + /* Set all possible values for the Oscillator type parameter ---------------*/ + RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | \ + RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI; + + /* Get Backup Domain register 1 */ + regvalue = RCC->BDCR1; + + /* Get the LSE configuration -----------------------------------------------*/ + mask = (RCC_BDCR1_LSEBYP | RCC_BDCR1_LSESYSEN | RCC_BDCR1_LSEON); + RCC_OscInitStruct->LSEState = (regvalue & mask); + + /* Get the LSI configuration -----------------------------------------------*/ + mask = RCC_BDCR1_LSI1ON; +#if defined(RCC_LSI2_SUPPORT) + mask |= RCC_BDCR1_LSI2ON; +#endif + RCC_OscInitStruct->LSIState = (regvalue & mask); + RCC_OscInitStruct->LSIDiv = (regvalue & RCC_BDCR1_LSI1PREDIV); + + /* Get Control register */ + regvalue = RCC->CR; + + /* Get the HSE configuration -----------------------------------------------*/ + RCC_OscInitStruct->HSEState = (regvalue & RCC_CR_HSEON); + RCC_OscInitStruct->HSEDiv = (regvalue & RCC_CR_HSEPRE); + + /* Get the HSI configuration -----------------------------------------------*/ + RCC_OscInitStruct->HSIState = (regvalue & RCC_CR_HSION); + RCC_OscInitStruct->HSICalibrationValue = ((RCC->ICSCR3 & RCC_ICSCR3_HSITRIM) >> RCC_ICSCR3_HSITRIM_Pos); + + /* Get the PLL1 configuration -----------------------------------------------*/ + if ((regvalue & RCC_CR_PLL1ON) != 0x00u) + { + RCC_OscInitStruct->PLL1.PLLState = RCC_PLL_ON; + } + else + { + RCC_OscInitStruct->PLL1.PLLState = RCC_PLL_OFF; + } + + /* Get PLL1 configuration register */ + regvalue = RCC->PLL1CFGR; + RCC_OscInitStruct->PLL1.PLLSource = (regvalue & RCC_PLL1CFGR_PLL1SRC); + RCC_OscInitStruct->PLL1.PLLM = (((regvalue & RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos) + 1U); + + /* Check if fractional part is enable */ + if ((regvalue & RCC_PLL1CFGR_PLL1FRACEN) != 0x00u) + { + regvalue = (((RCC->PLL1FRACR & RCC_PLL1FRACR_PLL1FRACN) >> RCC_PLL1FRACR_PLL1FRACN_Pos)); + } + else + { + regvalue = 0; + } + RCC_OscInitStruct->PLL1.PLLFractional = regvalue; + + /* Get PLL1 dividers register */ + regvalue = RCC->PLL1DIVR; + RCC_OscInitStruct->PLL1.PLLN = ((regvalue & RCC_PLL1DIVR_PLL1N) + 1U); + RCC_OscInitStruct->PLL1.PLLQ = (((regvalue & RCC_PLL1DIVR_PLL1Q) >> RCC_PLL1DIVR_PLL1Q_Pos) + 1U); + RCC_OscInitStruct->PLL1.PLLR = (((regvalue & RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1U); + RCC_OscInitStruct->PLL1.PLLP = (((regvalue & RCC_PLL1DIVR_PLL1P) >> RCC_PLL1DIVR_PLL1P_Pos) + 1U); + +} + +/** + * @brief Configure the RCC_ClkInitStruct according to the internal + * RCC configuration registers. + * @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that + * will be configured. + * @param pFLatency Pointer on the Flash Latency. + * @retval None + */ +void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) +{ + uint32_t tmpreg1; + + /* Check the parameters */ + assert_param(RCC_ClkInitStruct != (void *)NULL); + assert_param(pFLatency != (void *)NULL); + + /* Set all possible values for the Clock type parameter --------------------*/ + RCC_ClkInitStruct->ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | + RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK7 | RCC_CLOCKTYPE_HCLK5); + + /* Get the SYSCLK configuration --------------------------------------------*/ + RCC_ClkInitStruct->SYSCLKSource = (RCC->CFGR1 & RCC_CFGR1_SW); + + /* Get the HCLK configuration ----------------------------------------------*/ + tmpreg1 = RCC->CFGR2; + RCC_ClkInitStruct->AHBCLKDivider = (tmpreg1 & RCC_CFGR2_HPRE); + + /* Get the PCLK1 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB1CLKDivider = (tmpreg1 & RCC_CFGR2_PPRE1); + + /* Get the PCLK2 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB2CLKDivider = ((tmpreg1 & RCC_CFGR2_PPRE2) >> (RCC_CFGR2_PPRE2_Pos - RCC_CFGR2_PPRE1_Pos)); + + /* Get the PCLK7 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB7CLKDivider = (RCC->CFGR3 & RCC_CFGR3_PPRE7); + + /* Get the PCLK1 configuration ----------------------------------------------*/ + tmpreg1 = RCC->CFGR4; + RCC_ClkInitStruct->AHB5_PLL1_CLKDivider = (tmpreg1 & RCC_CFGR4_HPRE5); + RCC_ClkInitStruct->AHB5_HSEHSI_CLKDivider = (tmpreg1 & RCC_CFGR4_HDIV5); + + /* Get the Flash Wait State (Latency) configuration ------------------------*/ + *pFLatency = (FLASH->ACR & FLASH_ACR_LATENCY); +} + +/** + * @brief Enable the Clock Security System. + * @note If a failure is detected on the HSE oscillator clock, this oscillator + * is automatically disabled and an interrupt is generated to inform the + * software about the failure (Clock Security System Interrupt, CSSI), + * allowing the MCU to perform rescue operations. The CSSI is linked to + * the Cortex-M33 NMI (Non-Maskable Interrupt) exception vector. + * @note The Clock Security System can only be cleared by reset. + * @retval None + */ +void HAL_RCC_EnableCSS(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSECSSON); +} + +/** + * @brief Handle the RCC Clock Security System interrupt request. + * @note This API should be called under the NMI_Handler(). + * @retval None + */ +void HAL_RCC_NMI_IRQHandler(void) +{ + /* Check RCC CSSF interrupt flag */ + if (__HAL_RCC_GET_IT(RCC_IT_CSS)) + { + /* Clear RCC CSS pending bit */ + __HAL_RCC_CLEAR_IT(RCC_IT_CSS); + + /* RCC Clock Security System interrupt user callback */ + HAL_RCC_CSSCallback(); + } +} + +/** + * @brief RCC Clock Security System interrupt callback. + * @retval none + */ +__weak void HAL_RCC_CSSCallback(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RCC_CSSCallback should be implemented in the user file + */ +} + +/** + * @brief Get and clear reset flags + * @note Once reset flags are retrieved, this API is clearing them in order + * to isolate next reset reason. + * @retval can be a combination of @ref RCC_Reset_Flag + */ +uint32_t HAL_RCC_GetResetSource(void) +{ + uint32_t reset; + + /* Get all reset flags */ + reset = RCC->CSR & RCC_RESET_FLAG_ALL; + + /* Clear Reset flags */ + RCC->CSR |= RCC_CSR_RMVF; + + return reset; +} + +/** + * @} + */ + +#if defined(RCC_PRIVCFGR_NSPRIV) +/** @defgroup RCC_Exported_Functions_Group3 Attributes management functions + * @brief Attributes management functions. + * +@verbatim + =============================================================================== + ##### RCC attributes functions ##### + =============================================================================== +@endverbatim + * @{ + */ +/** + * @brief Configure the RCC item attribute(s). + * @note Available attributes are to secure items and set RCC as privileged. + * @param Item Item(s) to set attributes on. + * This parameter can be a one or a combination of @ref RCC_items + * @param Attributes specifies the RCC secure/privilege attributes. + * This parameter can be a value of @ref RCC_attributes + * @retval None + */ +void HAL_RCC_ConfigAttributes(uint32_t Item, uint32_t Attributes) +{ + /* Check the parameters */ + assert_param(IS_RCC_ITEM_ATTRIBUTES(Item)); + assert_param(IS_RCC_ATTRIBUTES(Attributes)); + + switch (Attributes) + { +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + /* Secure Privilege attribute */ + case RCC_SEC_PRIV: + SET_BIT(RCC->SECCFGR, Item); + SET_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_SPRIV); + break; + /* Secure Non-Privilege attribute */ + case RCC_SEC_NPRIV: + SET_BIT(RCC->SECCFGR, Item); + CLEAR_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_SPRIV); + break; + /* Non-secure Privilege attribute */ + case RCC_NSEC_PRIV: + CLEAR_BIT(RCC->SECCFGR, Item); + SET_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV); + break; + /* Non-secure Non-Privilege attribute */ + case RCC_NSEC_NPRIV: + CLEAR_BIT(RCC->SECCFGR, Item); + CLEAR_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV); + break; +#else + /* Non-secure Privilege attribute */ + case RCC_NSEC_PRIV: + SET_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV); + break; + /* Non-secure Non-Privilege attribute */ + case RCC_NSEC_NPRIV: + CLEAR_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV); + break; +#endif /* __ARM_FEATURE_CMSE */ + default: + /* Nothing to do */ + break; + } +} +/** + * @} + */ + +/** + * @brief Get the attribute of a RCC item. + * @note Secure and non-secure attributes are only available from secure state + * when the system implements the security (TZEN=1) + * @param Item Single item to get secure/non-secure and privilege/non-privilege attribute from. + * This parameter can be a one value of @ref RCC_items except RCC_ALL. + * @param pAttributes pointer to return the attributes. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_RCC_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes) +{ + uint32_t attributes; + + /* Check null pointer */ + if (pAttributes == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RCC_ITEM_ATTRIBUTES(Item)); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + /* Check item security */ + if ((RCC->SECCFGR & Item) == Item) + { + /* Get Secure privileges attribute */ + attributes = ((RCC->PRIVCFGR & RCC_PRIVCFGR_SPRIV) == 0U) ? RCC_SEC_NPRIV : RCC_SEC_PRIV; + } + else + { + /* Get Non-Secure privileges attribute */ + attributes = ((RCC->PRIVCFGR & RCC_PRIVCFGR_NSPRIV) == 0U) ? RCC_NSEC_NPRIV : RCC_NSEC_PRIV; + } +#else + /* Get Non-Secure privileges attribute */ + attributes = ((RCC->PRIVCFGR & RCC_PRIVCFGR_NSPRIV) == 0U) ? RCC_NSEC_NPRIV : RCC_NSEC_PRIV; +#endif /* __ARM_FEATURE_CMSE */ + + /* return value */ + *pAttributes = attributes; + + return HAL_OK; +} +/** + * @} + */ +#endif + +/* Private functions ---------------------------------------------------------*/ +/** @addtogroup RCC_Private_Functions + * @{ + */ +/** + * @brief Compute PLL1 VCO output frequency + * @retval Value of PLL1 VCO output frequency + */ +static float_t RCC_PLL1_GetVCOOutputFreq(void) +{ + uint32_t tmpreg1; + uint32_t tmp; + float_t pllsrc; + float_t pllm; + float_t plln; + float_t pllfracn; + + /* Get PLL1 DIVR register value */ + tmpreg1 = RCC->PLL1DIVR; + + /* Retrieve PLL1 multiplication factor */ + tmp = (tmpreg1 & RCC_PLL1DIVR_PLL1N) + 1U; + plln = (float_t) tmp; + + /* Get PLL1 CFGR register value */ + tmpreg1 = RCC->PLL1CFGR; + + /* Retrieve PLL1 divider */ + tmp = ((tmpreg1 & RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos) + 1U; + pllm = (float_t) tmp; + + /* Check if fractional part is enable */ + if ((tmpreg1 & RCC_PLL1CFGR_PLL1FRACEN) != 0x00u) + { + tmp = ((RCC->PLL1FRACR & RCC_PLL1FRACR_PLL1FRACN) >> RCC_PLL1FRACR_PLL1FRACN_Pos); + } + else + { + tmp = 0u; + } + pllfracn = (float_t)tmp; + + /* determine PLL source */ + switch (tmpreg1 & RCC_PLL1CFGR_PLL1SRC) + { + /* HSI used as PLL1 clock source */ + case RCC_PLLSOURCE_HSI: + pllsrc = (float_t)HSI_VALUE; + break; + + /* HSE used as PLL1 clock source */ + case RCC_PLLSOURCE_HSE: + tmp = (HSE_VALUE >> ((RCC->CR & RCC_CR_HSEPRE) >> RCC_CR_HSEPRE_Pos)); + pllsrc = (float_t)tmp; + break; + + default: + pllsrc = (float_t)0; + break; + } + + /* Compute VCO output frequency */ + return ((pllsrc / pllm) * (plln + (pllfracn / (float_t)0x2000u))); +} + + +/** + * @} + */ +#endif /* HAL_RCC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_rcc_ex.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_rcc_ex.c new file mode 100644 index 0000000000..d06b427902 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_rcc_ex.c @@ -0,0 +1,1361 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_rcc_ex.c + * @author MCD Application Team + * @brief Extended RCC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities RCC extended peripheral: + * + Extended Peripheral Control functions + * + Extended Clock management functions + * + Extended Clock Recovery System Control functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @defgroup RCCEx RCCEx + * @brief RCC Extended HAL module driver + * @{ + */ + +#ifdef HAL_RCC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions + * @{ + */ + +/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions + * @brief Extended Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Extended Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the RCC Clocks + frequencies. + [..] + (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to + select the RTC clock source; in this case the Backup domain will be reset in + order to modify the RTC Clock source, as consequence RTC registers (including + the backup registers) are set to their reset values. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the RCC extended peripherals clocks according to the specified + * parameters in the RCC_PeriphCLKInitTypeDef. + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + * contains a field PeriphClockSelection which can be a combination of the following values: + * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock + * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_SPI1 SPI1 peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_SYSTICK SYSTICK peripheral clock + * @arg @ref RCC_PERIPHCLK_TIMIC TIMIC peripheral clock + * @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_RNG RNG peripheral clock + * @arg @ref RCC_PERIPHCLK_AUDIOSYNC AUDIOSYNC peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock + * @arg @ref RCC_PERIPHCLK_SPI3 SPI3 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock + * @arg @ref RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock + * @arg @ref RCC_PERIPHCLK_ADC ADC4 peripheral clock + * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock + * @note (*) Peripherals are not available on all devices + * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select + * the RTC clock source: in this case the access to Backup domain is enabled. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tmpreg1; + uint32_t tmpreg2; + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); + + /*-------------------------- USART1 clock source configuration -------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) + { + /* Check the parameters */ + assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); + + /* Configure the USART1 clock source */ + __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); + } + +#if defined (USART2) + /*-------------------------- USART2 clock source configuration -------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) + { + /* Check the parameters */ + assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); + + /* Configure the USART2 clock source */ + __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); + } +#endif + + +#if defined (I2C1) + /*-------------------------- I2C1 clock source configuration ---------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); + + /* Configure the I2C1 clock source */ + __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); + } +#endif + + + + +#if defined (LPTIM2) + /*-------------------------- LPTIM2 clock source configuration -------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == (RCC_PERIPHCLK_LPTIM2)) + { + /* Check the parameters */ + assert_param(IS_RCC_LPTIM2CLKSOURCE(PeriphClkInit->Lptim2ClockSelection)); + + /* Configure the LPTIM2 clock source */ + __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection); + } +#endif + +#if defined (SPI1) + /*-------------------------- SPI1 clock source configuration ----------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI1) == RCC_PERIPHCLK_SPI1) + { + /* Check the parameters */ + assert_param(IS_RCC_SPI1CLKSOURCE(PeriphClkInit->Spi1ClockSelection)); + + /* Configure the SPI1 clock source */ + __HAL_RCC_SPI1_CONFIG(PeriphClkInit->Spi1ClockSelection); + } +#endif + + /*-------------------------- SYSTICK clock source configuration ----------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SYSTICK) == RCC_PERIPHCLK_SYSTICK) + { + /* Check the parameters */ + assert_param(IS_RCC_SYSTICKCLKSOURCE(PeriphClkInit->SystickClockSelection)); + + /* Configure the SYSTICK clock source */ + __HAL_RCC_SYSTICK_CONFIG(PeriphClkInit->SystickClockSelection); + } + + /*-------------------------- TIMIC clock source configuration ----------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIMIC) == RCC_PERIPHCLK_TIMIC) + { + /* Check the parameters */ + assert_param(IS_RCC_TIMICCLKSOURCE(PeriphClkInit->TimIcClockSelection)); + + /* Configure the TIMIC clock source */ + __HAL_RCC_TIMIC_CONFIG(PeriphClkInit->TimIcClockSelection); + } + +#if defined (SAI1) + /*-------------------------- SAI1 clock source configuration ---------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) + { + /* Check the parameters */ + assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection)); + + /* Set the source of SAI1 clock*/ + __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); + + if (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLL1P) + { + /* Enable PLL1 PCLK output */ + __HAL_RCC_PLL1CLKOUT_ENABLE(RCC_PLL1_PCLK); + } + else if (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLL1Q) + { + /* Enable PLL1 QCLK output */ + __HAL_RCC_PLL1CLKOUT_ENABLE(RCC_PLL1_QCLK); + } + else + { + /* Do nothing ; for misra 15.7 error only */ + } + } +#endif + + /*------------------------------ RNG Configuration -------------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) + { + /* Check the parameters */ + assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection)); + + /* Set the source of RNG clock*/ + __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection); + + if (PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL1Q) + { + /* Enable PLL1 QCLK output */ + __HAL_RCC_PLL1CLKOUT_ENABLE(RCC_PLL1_QCLK); + } + } + + +#if defined (RCC_CCIPR2_ASSEL) + /*-------------------------- AS clock source configuration -------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_AUDIOSYNC) == RCC_PERIPHCLK_AUDIOSYNC) + { + /* Check the parameters */ + assert_param(IS_RCC_ASCLKSOURCE(PeriphClkInit->AudioSyncClockSelection)); + + /* Configure the AS clock source */ + __HAL_RCC_AUDIOSYNC_CONFIG(PeriphClkInit->AudioSyncClockSelection); + } +#endif + + /*-------------------------- LPUART1 clock source configuration ------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) + { + /* Check the parameters */ + assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection)); + + /* Configure the LPUART1 clock source */ + __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection); + } + + /*-------------------------- SPI3 clock source configuration ----------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI3) == RCC_PERIPHCLK_SPI3) + { + /* Check the parameters */ + assert_param(IS_RCC_SPI3CLKSOURCE(PeriphClkInit->Spi3ClockSelection)); + + /* Configure the SPI3 clock source */ + __HAL_RCC_SPI3_CONFIG(PeriphClkInit->Spi3ClockSelection); + } + + + /*-------------------------- I2C3 clock source configuration ---------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection)); + + /* Configure the I2C3 clock source */ + __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection); + } + + /*-------------------------- LPTIM1 clock source configuration -------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1)) + { + /* Check the parameters */ + assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection)); + + /* Configure the I2C3 clock source */ + __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); + } + + /*-------------------------- ADC clock source configuration ----------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) + { + /* Check the parameters */ + assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection)); + + /* Configure the ADC4 interface clock source */ + __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); + + if (PeriphClkInit->AdcClockSelection == RCC_PERIPHCLK_ADC) + { + /* Enable PLL1 PCLK output */ + __HAL_RCC_PLL1CLKOUT_ENABLE(RCC_PLL1_PCLK); + } + } + + /*-------------------------- RTC clock source configuration ----------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) + { + FlagStatus pwrclkchanged = RESET; + + /* Check for RTC Parameters used to output RTCCLK */ + assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); + + /* Reset the Backup domain only if the RTC Clock source selection is modified from default */ + tmpreg2 = __HAL_RCC_GET_RTC_SOURCE(); + + /* Check if RTC clock source needs to be changed */ + if (tmpreg2 != PeriphClkInit->RTCClockSelection) + { + /* Enable Power Clock */ + if (__HAL_RCC_PWR_IS_CLK_ENABLED() != 0x01u) + { + __HAL_RCC_PWR_CLK_ENABLE(); + pwrclkchanged = SET; + } + + /* Enable write access to Backup domain */ + SET_BIT(PWR->DBPR, PWR_DBPR_DBP); + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + + while (HAL_IS_BIT_CLR(PWR->DBPR, PWR_DBPR_DBP)) + { + if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Save BDCR1 content */ + tmpreg1 = (RCC->BDCR1 & ~RCC_BDCR1_RTCSEL); + + /* Check if a backup domain reset is required */ + if (tmpreg2 != RCC_RTCCLKSOURCE_DISABLE) + { + /* Save BDCR2 content */ + tmpreg2 = RCC->BDCR2; + + /* RTC Clock selection can be changed only if the Backup Domain is reset */ + __HAL_RCC_BACKUPRESET_FORCE(); + __HAL_RCC_BACKUPRESET_RELEASE(); + + /* Restore previously saved BDCR2 */ + RCC->BDCR2 = tmpreg2; + } + + /* Apply new RTC clock source selection */ + RCC->BDCR1 = (tmpreg1 | PeriphClkInit->RTCClockSelection); + + /* mask all ON bits */ + tmpreg2 = (RCC_BDCR1_LSEON | RCC_BDCR1_LSI1ON); +#if defined(RCC_LSI2_SUPPORT) + tmpreg2 |= RCC_BDCR1_LSI2ON; +#endif + + /* Check which oscillators were enable */ + tmpreg2 &= tmpreg1; + + if (tmpreg2 != 0x00u) + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till all oscillators are enabled : RDY bit position is ON shifted by 1 */ + while (READ_BIT(RCC->BDCR1, (tmpreg2 << 1)) == 0x00u) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + /* Restore clock configuration if changed */ + if (pwrclkchanged == SET) + { + __HAL_RCC_PWR_CLK_DISABLE(); + } + } + } + + /*-------------------------- RADIO Sleep Timer clock source configuration --*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RADIOST) == RCC_PERIPHCLK_RADIOST) + { + /* Check the parameters */ + assert_param(IS_RCC_RADIOSLEEPTIMERSOURCE(PeriphClkInit->RadioSlpTimClockSelection)); + + /* Configure the RADIO Sleep Timer clock source */ + __HAL_RCC_RADIOSLPTIM_CONFIG(PeriphClkInit->RadioSlpTimClockSelection); + } + + return HAL_OK; +} + + +/** + * @brief Get the peripheral kernel clock configuration. + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + * returns the configuration information for all existing peripheral kernel clocks. (*) + * @note (*) Peripherals are not available on all devices + * @retval None + */ +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tmpreg; + + /* Check the parameters */ + assert_param(PeriphClkInit != NULL); + + /* Set all possible values for the extended clock type parameter------------*/ + PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLOCK_ALL; + + /* Get CCIPR1 register value */ + tmpreg = RCC->CCIPR1; + + /* Get the USART1 clock source ---------------------------------------------*/ + PeriphClkInit->Usart1ClockSelection = (tmpreg & RCC_CCIPR1_USART1SEL); + +#if defined (USART2) + /* Get the USART2 clock source ---------------------------------------------*/ + PeriphClkInit->Usart2ClockSelection = (tmpreg & RCC_CCIPR1_USART2SEL); +#endif + + + + + +#if defined (I2C1) + /* Get the I2C1 clock source -----------------------------------------------*/ + PeriphClkInit->I2c1ClockSelection = (tmpreg & RCC_CCIPR1_I2C1SEL); +#endif + +#if defined (LPTIM2) + /* Get the LPTIM2 clock source ---------------------------------------------*/ + PeriphClkInit->Lptim2ClockSelection = (tmpreg & RCC_CCIPR1_LPTIM2SEL); +#endif + +#if defined (SPI1) + /* Get the SPI1 clock source -----------------------------------------------*/ + PeriphClkInit->Spi1ClockSelection = (tmpreg & RCC_CCIPR1_SPI1SEL); +#endif + + /* Get the SYSTICK clock source --------------------------------------------*/ + PeriphClkInit->SystickClockSelection = (tmpreg & RCC_CCIPR1_SYSTICKSEL); + + /* Get the TIMIC clock source ----------------------------------------------*/ + PeriphClkInit->TimIcClockSelection = (tmpreg & RCC_CCIPR1_TIMICSEL); + + /* Get CCIPR2 register value */ + tmpreg = RCC->CCIPR2; + +#if defined (SAI1) + /* Get the SAI1 clock source -----------------------------------------------*/ + PeriphClkInit->Sai1ClockSelection = (tmpreg & RCC_CCIPR2_SAI1SEL); +#endif + + /* Get the RNG clock source ------------------------------------------------*/ + PeriphClkInit->RngClockSelection = (tmpreg & RCC_CCIPR2_RNGSEL); + + +#if defined (RCC_CCIPR2_ASSEL) + /* Get the Audio sync clock source -----------------------------------------*/ + PeriphClkInit->AudioSyncClockSelection = (tmpreg & RCC_CCIPR2_ASSEL); +#endif + + /* Get CCIPR3 register value */ + tmpreg = RCC->CCIPR3; + + /* Get the LPUART1 clock source --------------------------------------------*/ + PeriphClkInit->Lpuart1ClockSelection = (tmpreg & RCC_CCIPR3_LPUART1SEL); + + /* Get the SPI3 clock source -----------------------------------------------*/ + PeriphClkInit->Spi3ClockSelection = (tmpreg & RCC_CCIPR3_SPI3SEL); + + /* Get the I2C3 clock source -----------------------------------------------*/ + PeriphClkInit->I2c3ClockSelection = (tmpreg & RCC_CCIPR3_I2C3SEL); + + /* Get the LPTIM1 clock source ---------------------------------------------*/ + PeriphClkInit->Lptim1ClockSelection = (tmpreg & RCC_CCIPR3_LPTIM1SEL); + + /* Get the ADC clock source ------------------------------------------------*/ + PeriphClkInit->AdcClockSelection = (tmpreg & RCC_CCIPR3_ADCSEL); + + /* Get BDCR1 register value */ + tmpreg = RCC->BDCR1; + + /* Get the RTC clock source ------------------------------------------------*/ + PeriphClkInit->RTCClockSelection = (tmpreg & RCC_BDCR1_RTCSEL); + + /* Get the Radio Sleep Timer clock source ----------------------------------*/ + PeriphClkInit->RadioSlpTimClockSelection = (tmpreg & RCC_BDCR1_RADIOSTSEL); +} + + +/** + * @brief Return the peripheral clock frequency for peripherals + * @note Return 0 if peripheral clock identifier not managed by this API + * @param PeriphClk Peripheral clock identifier + * This parameter can be one of the following values: + * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock + * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_SPI1 SPI1 peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_SYSTICK SYSTICK peripheral clock + * @arg @ref RCC_PERIPHCLK_TIMIC TIMIC peripheral clock + * @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_RNG RNG peripheral clock + * @arg @ref RCC_PERIPHCLK_AUDIOSYNC AUDIOSYNC peripheral clock (*) + * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock + * @arg @ref RCC_PERIPHCLK_SPI3 SPI3 peripheral clock + * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock + * @arg @ref RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock + * @arg @ref RCC_PERIPHCLK_ADC ADC4 peripheral clock + * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock + * @note (*) Peripherals are not available on all devices + * @retval Frequency in Hz + */ +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) +{ + uint32_t frequency = 0; + uint32_t srcclk; + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClk)); + + switch (PeriphClk) + { + case RCC_PERIPHCLK_USART1: + /* Get the current USART1 source */ + srcclk = __HAL_RCC_GET_USART1_SOURCE(); + + if (srcclk == RCC_USART1CLKSOURCE_PCLK2) + { + frequency = HAL_RCC_GetPCLK2Freq(); + } + else if (srcclk == RCC_USART1CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if (srcclk == RCC_USART1CLKSOURCE_HSI) + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) + { + frequency = HSI_VALUE; + } + } + else + { + if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSERDY)) + { + frequency = LSE_VALUE; + } + } + break; + +#if defined (USART2) + case RCC_PERIPHCLK_USART2: + /* Get the current USART2 source */ + srcclk = __HAL_RCC_GET_USART2_SOURCE(); + + if (srcclk == RCC_USART2CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else if (srcclk == RCC_USART2CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if (srcclk == RCC_USART2CLKSOURCE_HSI) + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) + { + frequency = HSI_VALUE; + } + } + else + { + if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSERDY)) + { + frequency = LSE_VALUE; + } + } + break; +#endif + + +#if defined(I2C1) + case RCC_PERIPHCLK_I2C1: + /* Get the current I2C1 source */ + srcclk = __HAL_RCC_GET_I2C1_SOURCE(); + + if (srcclk == RCC_I2C1CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + else if (srcclk == RCC_I2C1CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if (srcclk == RCC_I2C1CLKSOURCE_HSI) + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) + { + frequency = HSI_VALUE; + } + } + else + { + /* Do nothing ; for misra 15.7 error only */ + } + break; +#endif + + + +#if defined(LPTIM2) + case RCC_PERIPHCLK_LPTIM2: + /* Get the current LPTIM2 source */ + srcclk = __HAL_RCC_GET_LPTIM2_SOURCE(); + + if (srcclk == RCC_LPTIM2CLKSOURCE_PCLK1) + { + frequency = HAL_RCC_GetPCLK1Freq(); + } + /* Check if LSI1 or LIS2 is ready and if LPTIM2 clock selection is LSI */ + else if (srcclk == RCC_LPTIM2CLKSOURCE_LSI) + { + if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSI1RDY)) + { + /* LSI Frequency */ + frequency = LSI_VALUE; + + /* Check is LSI1 is divided */ + if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSI1PREDIV)) + { + frequency /= 128U; + } + } +#if defined(RCC_LSI2_SUPPORT) + else if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSI2RDY)) + { + frequency = LSI2_VALUE; + } + else + { + /* Do nothing ; for misra 15.7 error only */ + } +#endif + } + else if (srcclk == RCC_LPTIM2CLKSOURCE_HSI) + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) + { + frequency = HSI_VALUE; + } + } + else + { + if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSERDY)) + { + frequency = LSE_VALUE; + } + } + break; +#endif + +#if defined(SPI1) + case RCC_PERIPHCLK_SPI1: + /* Get the current SPI1 kernel source */ + srcclk = __HAL_RCC_GET_SPI1_SOURCE(); + + if (srcclk == RCC_SPI1CLKSOURCE_PCLK2) + { + frequency = HAL_RCC_GetPCLK2Freq(); + } + else if (srcclk == RCC_SPI1CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if (srcclk == RCC_SPI1CLKSOURCE_HSI) + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) + { + frequency = HSI_VALUE; + } + } + else + { + /* Do nothing ; for misra 15.7 error only */ + } + break; +#endif + + case RCC_PERIPHCLK_SYSTICK: + /* Get the current SYSTICK kernel source */ + srcclk = __HAL_RCC_GET_SYSTICK_SOURCE(); + + if (srcclk == RCC_SYSTICKCLKSOURCE_HCLK_DIV8) + { + frequency = (HAL_RCC_GetHCLKFreq() / 8U); + } + else if (srcclk == RCC_SYSTICKCLKSOURCE_LSE) + { + if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSERDY)) + { + frequency = LSE_VALUE; + } + } + else if (srcclk == RCC_SYSTICKCLKSOURCE_LSI) + { + if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSI1RDY)) + { + /* LSI Frequency */ + frequency = LSI_VALUE; + + /* Check is LSI1 is divided */ + if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSI1PREDIV)) + { + frequency /= 128U; + } + } +#if defined(RCC_LSI2_SUPPORT) + else if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSI2RDY)) + { + frequency = LSI2_VALUE; + } + else + { + /* Do nothing ; for misra 15.7 error only */ + } +#endif + } + else + { + /* Do nothing ; for misra 15.7 error only */ + } + break; + + case RCC_PERIPHCLK_TIMIC: + /* Get the current TIMIC source */ + srcclk = __HAL_RCC_GET_TIMIC_SOURCE(); + + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) + { + frequency = HSI_VALUE; + if (srcclk == RCC_TIMICCLKSOURCE_HSI_DIV256) + { + frequency /= 256U; + } + } + break; + +#if defined (SAI1) + case RCC_PERIPHCLK_SAI1: + /* Get the current SAI1 source */ + srcclk = __HAL_RCC_GET_SAI1_SOURCE(); + + if (srcclk == RCC_SAI1CLKSOURCE_PLL1P) + { + frequency = HAL_RCC_GetPLL1PFreq(); + } + else if (srcclk == RCC_SAI1CLKSOURCE_PLL1Q) + { + frequency = HAL_RCC_GetPLL1QFreq(); + } + else if (srcclk == RCC_SAI1CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if (srcclk == RCC_SAI1CLKSOURCE_PIN) + { + frequency = EXTERNAL_SAI1_CLOCK_VALUE; + } + else if (srcclk == RCC_SAI1CLKSOURCE_HSI) + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) + { + frequency = HSI_VALUE; + } + } + else + { + /* Do nothing ; for misra 15.7 error only */ + } + break; +#endif + + case RCC_PERIPHCLK_RNG: + /* Get the current RNG source */ + srcclk = __HAL_RCC_GET_RNG_SOURCE(); + + if (srcclk == RCC_RNGCLKSOURCE_LSE) + { + if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSERDY)) + { + frequency = LSE_VALUE; + } + } + else if (srcclk == RCC_RNGCLKSOURCE_LSI) + { + if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSI1RDY)) + { + /* LSI Frequency */ + frequency = LSI_VALUE; + + /* Check is LSI1 is divided */ + if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSI1PREDIV)) + { + frequency /= 128U; + } + } +#if defined(RCC_LSI2_SUPPORT) + else if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSI2RDY)) + { + frequency = LSI2_VALUE; + } + else + { + /* Do nothing ; for misra 15.7 error only */ + } +#endif + } + else if (srcclk == RCC_RNGCLKSOURCE_HSI) + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) + { + frequency = HSI_VALUE; + } + } + else + { + frequency = HAL_RCC_GetPLL1QFreq(); + } + break; + + +#if defined (RCC_CCIPR2_ASSEL) + case RCC_PERIPHCLK_AUDIOSYNC: + /* Get the current Audio Sync source */ + srcclk = __HAL_RCC_GET_AUDIOSYNC_SOURCE(); + + if (srcclk == RCC_ASCLKSOURCE_PLL1P) + { + frequency = HAL_RCC_GetPLL1PFreq(); + } + else + { + frequency = HAL_RCC_GetPLL1QFreq(); + } + break; +#endif + + case RCC_PERIPHCLK_LPUART1: + /* Get the current LPUART1 source */ + srcclk = __HAL_RCC_GET_LPUART1_SOURCE(); + + if (srcclk == RCC_LPUART1CLKSOURCE_PCLK7) + { + frequency = HAL_RCC_GetPCLK7Freq(); + } + else if (srcclk == RCC_LPUART1CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if (srcclk == RCC_LPUART1CLKSOURCE_HSI) + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) + { + frequency = HSI_VALUE; + } + } + else + { + if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSERDY)) + { + frequency = LSE_VALUE; + } + } + break; + + case RCC_PERIPHCLK_SPI3: + /* Get the current SPI3 kernel source */ + srcclk = __HAL_RCC_GET_SPI3_SOURCE(); + + if (srcclk == RCC_SPI3CLKSOURCE_PCLK7) + { + frequency = HAL_RCC_GetPCLK7Freq(); + } + else if (srcclk == RCC_SPI3CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if (srcclk == RCC_SPI3CLKSOURCE_HSI) + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) + { + frequency = HSI_VALUE; + } + } + else + { + /* Do nothing ; for misra 15.7 error only */ + } + break; + + case RCC_PERIPHCLK_I2C3: + /* Get the current I2C3 source */ + srcclk = __HAL_RCC_GET_I2C3_SOURCE(); + + if (srcclk == RCC_I2C3CLKSOURCE_PCLK7) + { + frequency = HAL_RCC_GetPCLK7Freq(); + } + else if (srcclk == RCC_I2C3CLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if (srcclk == RCC_I2C3CLKSOURCE_HSI) + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) + { + frequency = HSI_VALUE; + } + } + else + { + /* Do nothing ; for misra 15.7 error only */ + } + break; + + case RCC_PERIPHCLK_LPTIM1: + /* Get the current LPTIM1 source */ + srcclk = __HAL_RCC_GET_LPTIM1_SOURCE(); + + if (srcclk == RCC_LPTIM1CLKSOURCE_PCLK7) + { + frequency = HAL_RCC_GetPCLK7Freq(); + } + else if (srcclk == RCC_LPTIM1CLKSOURCE_LSI) + { + /* Check if LSI1 or LIS2 is ready */ + if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSI1RDY)) + { + /* LSI Frequency */ + frequency = LSI_VALUE; + + /* Check is LSI1 is divided */ + if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSI1PREDIV)) + { + frequency /= 128U; + } + } +#if defined(RCC_LSI2_SUPPORT) + else if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSI2RDY)) + { + frequency = LSI2_VALUE; + } + else + { + /* Do nothing ; for misra 15.7 error only */ + } +#endif + } + else if (srcclk == RCC_LPTIM1CLKSOURCE_HSI) + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) + { + frequency = HSI_VALUE; + } + } + else + { + if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSERDY)) + { + frequency = LSE_VALUE; + } + } + break; + + case RCC_PERIPHCLK_ADC: + /* Get the current ADC kernel source */ + srcclk = __HAL_RCC_GET_ADC_SOURCE(); + + if (srcclk == RCC_ADCCLKSOURCE_HCLK) + { + frequency = HAL_RCC_GetHCLKFreq(); + } + else if (srcclk == RCC_ADCCLKSOURCE_SYSCLK) + { + frequency = HAL_RCC_GetSysClockFreq(); + } + else if (srcclk == RCC_ADCCLKSOURCE_PLL1P) + { + frequency = HAL_RCC_GetPLL1PFreq(); + } + else if (srcclk == RCC_ADCCLKSOURCE_HSE) + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) + { + frequency = HSE_VALUE; + } + } + else if (srcclk == RCC_ADCCLKSOURCE_HSI) + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) + { + frequency = HSI_VALUE; + } + } + else + { + /* Do nothing ; for misra 15.7 error only */ + } + break; + + case RCC_PERIPHCLK_RTC: + /* Get the current RTC source */ + srcclk = __HAL_RCC_GET_RTC_SOURCE(); + + /* Check if LSE is ready and if RTC clock selection is LSE */ + if (srcclk == RCC_RTCCLKSOURCE_LSE) + { + if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSERDY)) + { + frequency = LSE_VALUE; + } + } + /* Check if LSI1 or LIS2 is ready and if RTC clock selection is LSI */ + else if (srcclk == RCC_RTCCLKSOURCE_LSI) + { + if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSI1RDY)) + { + /* LSI Frequency */ + frequency = LSI_VALUE; + + /* Check is LSI1 is divided */ + if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSI1PREDIV)) + { + frequency /= 128U; + } + } +#if defined(RCC_LSI2_SUPPORT) + else if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSI2RDY)) + { + frequency = LSI2_VALUE; + } + else + { + /* Do nothing ; for misra 15.7 error only */ + } +#endif /* RCC_LSI2_SUPPORT */ + } + /* Check if HSE is ready and if RTC clock selection is HSI_DIV32 */ + else + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) + { + frequency = (HSE_VALUE / 32U); + } + } + break; + + case RCC_PERIPHCLK_RADIOST: + /* Get the current RADIOST kernel source */ + srcclk = __HAL_RCC_GET_RADIOSLPTIM_SOURCE(); + + if (srcclk == RCC_RADIOSTCLKSOURCE_HSE_DIV1000) + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) + { + frequency = (HSE_VALUE / 1000U); + } + } + else if (srcclk == RCC_RADIOSTCLKSOURCE_LSE) + { + if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSERDY)) + { + frequency = LSE_VALUE; + } + } + else if (srcclk == RCC_RADIOSTCLKSOURCE_LSI) + { + if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSI1RDY)) + { + /* LSI Frequency */ + frequency = LSI_VALUE; + + /* Check is LSI1 is divided */ + if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSI1PREDIV)) + { + frequency /= 128U; + } + } +#if defined(RCC_LSI2_SUPPORT) + else if (HAL_IS_BIT_SET(RCC->BDCR1, RCC_BDCR1_LSI2RDY)) + { + frequency = LSI2_VALUE; + } + else + { + /* Do nothing ; for misra 15.7 error only */ + } +#endif + } + else + { + /* Do nothing ; for misra 15.7 error only */ + } + break; + + default: + break; + } + + return (frequency); +} + +/** + * @} + */ + +/** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions + * @brief Extended Clock management functions + * +@verbatim + =============================================================================== + ##### Extended clock management functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the + activation or deactivation of LSE CSS, Low Speed Clock Output (LSCO), HSE and + LSE trimming and LSI2 configuration (when applicable). +@endverbatim + * @{ + */ + +/** + * @brief Enable the LSE Clock Security System. + * @note Prior to enable the LSE Clock Security System, LSE oscillator is to be enabled + * with HAL_RCC_OscConfig() and the LSE oscillator clock is to be selected as RTC + * clock with HAL_RCCEx_PeriphCLKConfig(). + * @retval None + */ +void HAL_RCCEx_EnableLSECSS(void) +{ + SET_BIT(RCC->BDCR1, RCC_BDCR1_LSECSSON); +} + +/** + * @brief Disable the LSE Clock Security System. + * @note LSE Clock Security System can only be disabled after a LSE failure detection. + * @retval None + */ +void HAL_RCCEx_DisableLSECSS(void) +{ + CLEAR_BIT(RCC->BDCR1, RCC_BDCR1_LSECSSON); +} + +/** + * @brief Select the Low Speed clock source to output on LSCO pin (PA2). + * @param LSCOSource specifies the Low Speed clock source to output. + * This parameter can be one of the following values: + * @arg @ref RCC_LSCOSOURCE_LSI LSI clock selected as LSCO source + * @arg @ref RCC_LSCOSOURCE_LSE LSE clock selected as LSCO source + * @retval None + */ +void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_LSCOSOURCE(LSCOSource)); + + /* Update LSCO selection according to parameter and enable LSCO */ + MODIFY_REG(RCC->BDCR1, RCC_BDCR1_LSCOSEL, LSCOSource | RCC_BDCR1_LSCOEN); +} + +/** + * @brief Disable the Low Speed clock output. + * @retval None + */ +void HAL_RCCEx_DisableLSCO(void) +{ + /* Clear LSCOEN in BDCR register */ + CLEAR_BIT(RCC->BDCR1, RCC_BDCR1_LSCOEN); +} + +/** + * @brief Set HSE trimming value + * @param Trimming specifies the HSE trimmign value. + * This parameter should be below 0x3F. + * @retval None + */ +void HAL_RCCEx_HSESetTrimming(uint32_t Trimming) +{ + /* Check the parameters */ + assert_param(IS_RCC_HSETRIM(Trimming)); + + MODIFY_REG(RCC->ECSCR1, RCC_ECSCR1_HSETRIM, Trimming << RCC_ECSCR1_HSETRIM_Pos); +} + +/** + * @brief Get HSE trimming value + * @retval The programmed HSE trimmign value + */ +uint32_t HAL_RCCEx_HSEGetTrimming(void) +{ + return ((RCC->ECSCR1 & RCC_ECSCR1_HSETRIM) >> RCC_ECSCR1_HSETRIM_Pos); +} + +/** + * @brief Set LSE trimming value + * @param Trimming specifies the Low Speed clock source to output. + * This parameter can be one of the following values: + * @arg @ref RCC_LSETRIMMING_R current source resistance R + * @arg @ref RCC_LSETRIMMING_3_4_R current source resistance 3/4*R + * @arg @ref RCC_LSETRIMMING_2_3_R current source resistance 2/3*R + * @arg @ref RCC_LSETRIMMING_1_2_R current source resistance 1/2*R + * @retval None + */ +void HAL_RCCEx_LSESetTrimming(uint32_t Trimming) +{ + /* Check the parameters */ + assert_param(IS_RCC_LSETRIM(Trimming)); + + MODIFY_REG(RCC->BDCR1, RCC_BDCR1_LSETRIM, Trimming); +} + +/** + * @brief Get LSE trimming value + * @retval The programmed LSE trimmign value + */ +uint32_t HAL_RCCEx_LSEGetTrimming(void) +{ + return (RCC->BDCR1 & RCC_BDCR1_LSETRIM); +} + +#if defined(RCC_LSI2_SUPPORT) +/** + * @brief Set LSI2 Configuration + * @param pConfig pointer to an RCC_LSIConfigTypeDef structure that + * contains the configuration information for the LSI2 oscillattor + * @retval None + */ +void HAL_RCCEx_LSI2SetConfig(const RCC_LSIConfigTypeDef *pConfig) +{ + /* Check the parameters */ + assert_param(pConfig != NULL); + assert_param(IS_RCC_LSI2_FREQTEMPSENS(pConfig->FreqTempSens)); + assert_param(IS_RCC_LSI2_OPERATINGMODE(pConfig->OpMode)); + + WRITE_REG(RCC->BDCR2, (pConfig->FreqTempSens | pConfig->OpMode)); +} + +/** + * @brief Set LSI2 Configuration + * @param pConfig pointer to an RCC_LSIConfigTypeDef structure that + * contains the configuration information for the LSI2 oscillattor + * @retval None + */ +void HAL_RCCEx_LSI2GetConfig(RCC_LSIConfigTypeDef *pConfig) +{ + uint32_t regbdcr2; + + /* Check the parameters */ + assert_param(pConfig != NULL); + + /* Get register value */ + regbdcr2 = RCC->BDCR2; + + pConfig->FreqTempSens = (regbdcr2 & RCC_BDCR2_LSI2CFG); + pConfig->OpMode = (regbdcr2 & RCC_BDCR2_LSI2MODE); +} + +#endif /* RCC_BDCR1_LSI2ON */ + +/** + * @} + */ + +/** @defgroup RCCEx_Exported_Functions_Group3 Radio clock management functions + * @brief Radio clock management functions + * +@verbatim + =============================================================================== + ##### Extended radio clock management functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the + radio-related parameters. +@endverbatim + * @{ + */ + +/** + * @brief Enable the 2.4 GHz RADIO baseband clock + * @retval None + */ +void HAL_RCCEx_EnableRadioBBClock(void) +{ + SET_BIT(RCC->RADIOENR, RCC_RADIOENR_BBCLKEN); +} + +/** + * @brief Disable the 2.4 GHz RADIO baseband clock + * @retval None + */ +void HAL_RCCEx_DisableRadioBBClock(void) +{ + CLEAR_BIT(RCC->RADIOENR, RCC_RADIOENR_BBCLKEN); +} + +/** + * @brief Enable the 2.4 GHz RADIO bus clock and HSE32 oscillator by 2.4 GHz RADIO sleep timer wakeup event + * @retval None + */ +void HAL_RCCEx_EnableRequestUponRadioWakeUpEvent(void) +{ + SET_BIT(RCC->RADIOENR, RCC_RADIOENR_STRADIOCLKON); +} + +/** + * @brief Disable the 2.4 GHz RADIO bus clock and HSE32 oscillator by 2.4 GHz RADIO sleep timer wakeup event + * @retval None + */ +void HAL_RCCEx_DisableRequestUponRadioWakeUpEvent(void) +{ + CLEAR_BIT(RCC->RADIOENR, RCC_RADIOENR_STRADIOCLKON); +} + +/** + * @brief Get the 2.4 GHz RADIO bus clock readiness. + * @note Indicate that the 2.4 GHz RADIO bus clock is ready and the 2.4 GHz RADIO registers can be accessed. + * @note The output can be one of the following values : + * @arg RCC_RADIO_BUS_CLOCK_NOT_READY : 2.4 GHz RADIO bus clock not ready. + * @arg RCC_RADIO_BUS_CLOCK_READY : 2.4 GHz RADIO bus clock ready. + * @retval The regulator REG_VDDHPA input supply selection. + */ +uint32_t HAL_RCCEx_GetRadioBusClockReadiness(void) +{ + return READ_BIT(RCC->RADIOENR, RCC_RADIOENR_RADIOCLKRDY); +} +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_RCC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_rng.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_rng.c new file mode 100644 index 0000000000..4b335fed2e --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_rng.c @@ -0,0 +1,1027 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_rng.c + * @author MCD Application Team + * @brief RNG HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Random Number Generator (RNG) peripheral: + * + Initialization and configuration functions + * + Peripheral Control functions + * + Peripheral State functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The RNG HAL driver can be used as follows: + + (#) Enable the RNG controller clock using __HAL_RCC_RNG_CLK_ENABLE() macro + in HAL_RNG_MspInit(). + (#) Activate the RNG peripheral using HAL_RNG_Init() function. + (#) Wait until the 32 bit Random Number Generator contains a valid + random data using (polling/interrupt) mode. + (#) Get the 32 bit random number using HAL_RNG_GenerateRandomNumber() function. + + ##### Callback registration ##### + ================================== + + [..] + The compilation define USE_HAL_RNG_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + [..] + Use Function HAL_RNG_RegisterCallback() to register a user callback. + Function HAL_RNG_RegisterCallback() allows to register following callbacks: + (+) ErrorCallback : RNG Error Callback. + (+) MspInitCallback : RNG MspInit. + (+) MspDeInitCallback : RNG MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + [..] + Use function HAL_RNG_UnRegisterCallback() to reset a callback to the default + weak (overridden) function. + HAL_RNG_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) ErrorCallback : RNG Error Callback. + (+) MspInitCallback : RNG MspInit. + (+) MspDeInitCallback : RNG MspDeInit. + + [..] + For specific callback ReadyDataCallback, use dedicated register callbacks: + respectively HAL_RNG_RegisterReadyDataCallback() , HAL_RNG_UnRegisterReadyDataCallback(). + + [..] + By default, after the HAL_RNG_Init() and when the state is HAL_RNG_STATE_RESET + all callbacks are set to the corresponding weak (overridden) functions: + example HAL_RNG_ErrorCallback(). + Exception done for MspInit and MspDeInit functions that are respectively + reset to the legacy weak (overridden) functions in the HAL_RNG_Init() + and HAL_RNG_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_RNG_Init() and HAL_RNG_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand). + + [..] + Callbacks can be registered/unregistered in HAL_RNG_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_RNG_STATE_READY or HAL_RNG_STATE_RESET state, thus registered (user) + MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_RNG_RegisterCallback() before calling HAL_RNG_DeInit() + or HAL_RNG_Init() function. + + [..] + When The compilation define USE_HAL_RNG_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available + and weak (overridden) callbacks are used. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +#if defined (RNG) + +/** @addtogroup RNG + * @brief RNG HAL module driver. + * @{ + */ + +#ifdef HAL_RNG_MODULE_ENABLED + +/* Private types -------------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup RNG_Private_Constants RNG Private Constants + * @{ + */ +#define RNG_TIMEOUT_VALUE 10U +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +/* Private functions prototypes ----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup RNG_Exported_Functions + * @{ + */ + +/** @addtogroup RNG_Exported_Functions_Group1 + * @brief Initialization and configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize the RNG according to the specified parameters + in the RNG_InitTypeDef and create the associated handle + (+) DeInitialize the RNG peripheral + (+) Initialize the RNG MSP + (+) DeInitialize RNG MSP + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the RNG peripheral and creates the associated handle. + * @param hrng pointer to a RNG_HandleTypeDef structure that contains + * the configuration information for RNG. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) +{ + uint32_t tickstart; + /* Check the RNG handle allocation */ + if (hrng == NULL) + { + return HAL_ERROR; + } + /* Check the parameters */ + assert_param(IS_RNG_ALL_INSTANCE(hrng->Instance)); + assert_param(IS_RNG_CED(hrng->Init.ClockErrorDetection)); + +#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) + if (hrng->State == HAL_RNG_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hrng->Lock = HAL_UNLOCKED; + + hrng->ReadyDataCallback = HAL_RNG_ReadyDataCallback; /* Legacy weak ReadyDataCallback */ + hrng->ErrorCallback = HAL_RNG_ErrorCallback; /* Legacy weak ErrorCallback */ + + if (hrng->MspInitCallback == NULL) + { + hrng->MspInitCallback = HAL_RNG_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware */ + hrng->MspInitCallback(hrng); + } +#else + if (hrng->State == HAL_RNG_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hrng->Lock = HAL_UNLOCKED; + + /* Init the low level hardware */ + HAL_RNG_MspInit(hrng); + } +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ + + /* Change RNG peripheral state */ + hrng->State = HAL_RNG_STATE_BUSY; + + /* Disable RNG */ + __HAL_RNG_DISABLE(hrng); + + /* Clock Error Detection Configuration when CONDRT bit is set to 1 */ + MODIFY_REG(hrng->Instance->CR, RNG_CR_CED | RNG_CR_CONDRST | RNG_CR_RNG_CONFIG2, + hrng->Init.ClockErrorDetection | RNG_CR_CONDRST | (1U << RNG_CR_RNG_CONFIG2_Pos)); + + /* Writing bit CONDRST=0 */ + CLEAR_BIT(hrng->Instance->CR, RNG_CR_CONDRST); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for conditioning reset process to be completed */ + while (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST)) + { + if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE) + { + /* New check to avoid false timeout detection in case of preemption */ + if (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST)) + { + hrng->State = HAL_RNG_STATE_READY; + hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; + return HAL_ERROR; + } + } + } + + /* Enable the RNG Peripheral */ + __HAL_RNG_ENABLE(hrng); + + /* verify that no seed error */ + if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET) + { + hrng->State = HAL_RNG_STATE_ERROR; + return HAL_ERROR; + } + /* Get tick */ + tickstart = HAL_GetTick(); + /* Check if data register contains valid random data */ + while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET) + { + if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE) + { + /* New check to avoid false timeout detection in case of preemption */ + if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET) + { + hrng->State = HAL_RNG_STATE_ERROR; + hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; + return HAL_ERROR; + } + } + } + + /* Initialize the RNG state */ + hrng->State = HAL_RNG_STATE_READY; + + /* Initialise the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_NONE; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief DeInitializes the RNG peripheral. + * @param hrng pointer to a RNG_HandleTypeDef structure that contains + * the configuration information for RNG. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng) +{ + uint32_t tickstart; + + /* Check the RNG handle allocation */ + if (hrng == NULL) + { + return HAL_ERROR; + } + + /* Clear Clock Error Detection bit when CONDRT bit is set to 1 */ + MODIFY_REG(hrng->Instance->CR, RNG_CR_CED | RNG_CR_CONDRST, RNG_CED_ENABLE | RNG_CR_CONDRST); + + /* Writing bit CONDRST=0 */ + CLEAR_BIT(hrng->Instance->CR, RNG_CR_CONDRST); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for conditioning reset process to be completed */ + while (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST)) + { + if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE) + { + /* New check to avoid false timeout detection in case of preemption */ + if (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST)) + { + hrng->State = HAL_RNG_STATE_READY; + hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; + /* Process Unlocked */ + __HAL_UNLOCK(hrng); + return HAL_ERROR; + } + } + } + + /* Disable the RNG Peripheral */ + CLEAR_BIT(hrng->Instance->CR, RNG_CR_IE | RNG_CR_RNGEN); + + /* Clear RNG interrupt status flags */ + CLEAR_BIT(hrng->Instance->SR, RNG_SR_CEIS | RNG_SR_SEIS); + +#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) + if (hrng->MspDeInitCallback == NULL) + { + hrng->MspDeInitCallback = HAL_RNG_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware */ + hrng->MspDeInitCallback(hrng); +#else + /* DeInit the low level hardware */ + HAL_RNG_MspDeInit(hrng); +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ + + /* Update the RNG state */ + hrng->State = HAL_RNG_STATE_RESET; + + /* Initialise the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_NONE; + + /* Release Lock */ + __HAL_UNLOCK(hrng); + + /* Return the function status */ + return HAL_OK; +} + +/** + * @brief Initializes the RNG MSP. + * @param hrng pointer to a RNG_HandleTypeDef structure that contains + * the configuration information for RNG. + * @retval None + */ +__weak void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrng); + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_RNG_MspInit must be implemented in the user file. + */ +} + +/** + * @brief DeInitializes the RNG MSP. + * @param hrng pointer to a RNG_HandleTypeDef structure that contains + * the configuration information for RNG. + * @retval None + */ +__weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrng); + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_RNG_MspDeInit must be implemented in the user file. + */ +} + +#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User RNG Callback + * To be used instead of the weak predefined callback + * @param hrng RNG handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_RNG_ERROR_CB_ID Error callback ID + * @arg @ref HAL_RNG_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_RNG_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID, + pRNG_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + if (HAL_RNG_STATE_READY == hrng->State) + { + switch (CallbackID) + { + case HAL_RNG_ERROR_CB_ID : + hrng->ErrorCallback = pCallback; + break; + + case HAL_RNG_MSPINIT_CB_ID : + hrng->MspInitCallback = pCallback; + break; + + case HAL_RNG_MSPDEINIT_CB_ID : + hrng->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_RNG_STATE_RESET == hrng->State) + { + switch (CallbackID) + { + case HAL_RNG_MSPINIT_CB_ID : + hrng->MspInitCallback = pCallback; + break; + + case HAL_RNG_MSPDEINIT_CB_ID : + hrng->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister an RNG Callback + * RNG callback is redirected to the weak predefined callback + * @param hrng RNG handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_RNG_ERROR_CB_ID Error callback ID + * @arg @ref HAL_RNG_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_RNG_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + + if (HAL_RNG_STATE_READY == hrng->State) + { + switch (CallbackID) + { + case HAL_RNG_ERROR_CB_ID : + hrng->ErrorCallback = HAL_RNG_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_RNG_MSPINIT_CB_ID : + hrng->MspInitCallback = HAL_RNG_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_RNG_MSPDEINIT_CB_ID : + hrng->MspDeInitCallback = HAL_RNG_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_RNG_STATE_RESET == hrng->State) + { + switch (CallbackID) + { + case HAL_RNG_MSPINIT_CB_ID : + hrng->MspInitCallback = HAL_RNG_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_RNG_MSPDEINIT_CB_ID : + hrng->MspDeInitCallback = HAL_RNG_MspDeInit; /* Legacy weak MspInit */ + break; + + default : + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Register Data Ready RNG Callback + * To be used instead of the weak HAL_RNG_ReadyDataCallback() predefined callback + * @param hrng RNG handle + * @param pCallback pointer to the Data Ready Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RNG_RegisterReadyDataCallback(RNG_HandleTypeDef *hrng, pRNG_ReadyDataCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hrng); + + if (HAL_RNG_STATE_READY == hrng->State) + { + hrng->ReadyDataCallback = pCallback; + } + else + { + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hrng); + return status; +} + +/** + * @brief UnRegister the Data Ready RNG Callback + * Data Ready RNG Callback is redirected to the weak HAL_RNG_ReadyDataCallback() predefined callback + * @param hrng RNG handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback(RNG_HandleTypeDef *hrng) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hrng); + + if (HAL_RNG_STATE_READY == hrng->State) + { + hrng->ReadyDataCallback = HAL_RNG_ReadyDataCallback; /* Legacy weak ReadyDataCallback */ + } + else + { + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hrng); + return status; +} + +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @addtogroup RNG_Exported_Functions_Group2 + * @brief Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Get the 32 bit Random number + (+) Get the 32 bit Random number with interrupt enabled + (+) Handle RNG interrupt request + +@endverbatim + * @{ + */ + +/** + * @brief Generates a 32-bit random number. + * @note This function checks value of RNG_FLAG_DRDY flag to know if valid + * random number is available in the DR register (RNG_FLAG_DRDY flag set + * whenever a random number is available through the RNG_DR register). + * After transitioning from 0 to 1 (random number available), + * RNG_FLAG_DRDY flag remains high until output buffer becomes empty after reading + * four words from the RNG_DR register, i.e. further function calls + * will immediately return a new u32 random number (additional words are + * available and can be read by the application, till RNG_FLAG_DRDY flag remains high). + * @note When no more random number data is available in DR register, RNG_FLAG_DRDY + * flag is automatically cleared. + * @param hrng pointer to a RNG_HandleTypeDef structure that contains + * the configuration information for RNG. + * @param random32bit pointer to generated random number variable if successful. + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit) +{ + uint32_t tickstart; + HAL_StatusTypeDef status = HAL_OK; + + /* Process Locked */ + __HAL_LOCK(hrng); + + /* Check RNG peripheral state */ + if (hrng->State == HAL_RNG_STATE_READY) + { + /* Change RNG peripheral state */ + hrng->State = HAL_RNG_STATE_BUSY; + /* Check if there is a seed error */ + if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET) + { + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_SEED; + /* Reset from seed error */ + status = RNG_RecoverSeedError(hrng); + if (status == HAL_ERROR) + { + return status; + } + } + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Check if data register contains valid random data */ + while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE) + { + /* New check to avoid false timeout detection in case of preemption */ + if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET) + { + hrng->State = HAL_RNG_STATE_READY; + hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; + /* Process Unlocked */ + __HAL_UNLOCK(hrng); + return HAL_ERROR; + } + } + } + + /* Get a 32bit Random number */ + hrng->RandomNumber = hrng->Instance->DR; + /* In case of seed error, the value available in the RNG_DR register must not + be used as it may not have enough entropy */ + if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET) + { + /* Update the error code and status */ + hrng->ErrorCode = HAL_RNG_ERROR_SEED; + status = HAL_ERROR; + /* Clear bit DRDY */ + CLEAR_BIT(hrng->Instance->SR, RNG_FLAG_DRDY); + } + else /* No seed error */ + { + *random32bit = hrng->RandomNumber; + } + hrng->State = HAL_RNG_STATE_READY; + } + else + { + hrng->ErrorCode = HAL_RNG_ERROR_BUSY; + status = HAL_ERROR; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hrng); + + return status; +} + +/** + * @brief Generates a 32-bit random number in interrupt mode. + * @param hrng pointer to a RNG_HandleTypeDef structure that contains + * the configuration information for RNG. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process Locked */ + __HAL_LOCK(hrng); + + /* Check RNG peripheral state */ + if (hrng->State == HAL_RNG_STATE_READY) + { + /* Change RNG peripheral state */ + hrng->State = HAL_RNG_STATE_BUSY; + + /* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */ + __HAL_RNG_ENABLE_IT(hrng); + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hrng); + + hrng->ErrorCode = HAL_RNG_ERROR_BUSY; + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Handles RNG interrupt request. + * @note In the case of a clock error, the RNG is no more able to generate + * random numbers because the PLL48CLK clock is not correct. User has + * to check that the clock controller is correctly configured to provide + * the RNG clock and clear the CEIS bit using __HAL_RNG_CLEAR_IT(). + * The clock error has no impact on the previously generated + * random numbers, and the RNG_DR register contents can be used. + * @note In the case of a seed error, the generation of random numbers is + * interrupted as long as the SECS bit is '1'. If a number is + * available in the RNG_DR register, it must not be used because it may + * not have enough entropy. In this case, it is recommended to clear the + * SEIS bit using __HAL_RNG_CLEAR_IT(), then disable and enable + * the RNG peripheral to reinitialize and restart the RNG. + * @note User-written HAL_RNG_ErrorCallback() API is called once whether SEIS + * or CEIS are set. + * @param hrng pointer to a RNG_HandleTypeDef structure that contains + * the configuration information for RNG. + * @retval None + + */ +void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng) +{ + uint32_t rngclockerror = 0U; + uint32_t itflag = hrng->Instance->SR; + + /* RNG clock error interrupt occurred */ + if ((itflag & RNG_IT_CEI) == RNG_IT_CEI) + { + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_CLOCK; + rngclockerror = 1U; + } + else if ((itflag & RNG_IT_SEI) == RNG_IT_SEI) + { + /* Check if Seed Error Current Status (SECS) is set */ + if ((itflag & RNG_FLAG_SECS) != RNG_FLAG_SECS) + { + /* RNG IP performed the reset automatically (auto-reset) */ + /* Clear bit SEIS */ + CLEAR_BIT(hrng->Instance->SR, RNG_IT_SEI); + } + else + { + /* Seed Error has not been recovered : Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_SEED; + rngclockerror = 1U; + /* Disable the IT */ + __HAL_RNG_DISABLE_IT(hrng); + } + } + else + { + /* Nothing to do */ + } + + if (rngclockerror == 1U) + { + /* Change RNG peripheral state */ + hrng->State = HAL_RNG_STATE_ERROR; + +#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) + /* Call registered Error callback */ + hrng->ErrorCallback(hrng); +#else + /* Call legacy weak Error callback */ + HAL_RNG_ErrorCallback(hrng); +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ + + /* Clear the clock error flag */ + __HAL_RNG_CLEAR_IT(hrng, RNG_IT_CEI | RNG_IT_SEI); + + return; + } + + /* Check RNG data ready interrupt occurred */ + if ((itflag & RNG_IT_DRDY) == RNG_IT_DRDY) + { + /* Generate random number once, so disable the IT */ + __HAL_RNG_DISABLE_IT(hrng); + + /* Get the 32bit Random number (DRDY flag automatically cleared) */ + hrng->RandomNumber = hrng->Instance->DR; + + if (hrng->State != HAL_RNG_STATE_ERROR) + { + /* Change RNG peripheral state */ + hrng->State = HAL_RNG_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hrng); + +#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) + /* Call registered Data Ready callback */ + hrng->ReadyDataCallback(hrng, hrng->RandomNumber); +#else + /* Call legacy weak Data Ready callback */ + HAL_RNG_ReadyDataCallback(hrng, hrng->RandomNumber); +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ + } + } +} + +/** + * @brief Read latest generated random number. + * @param hrng pointer to a RNG_HandleTypeDef structure that contains + * the configuration information for RNG. + * @retval random value + */ +uint32_t HAL_RNG_ReadLastRandomNumber(const RNG_HandleTypeDef *hrng) +{ + return (hrng->RandomNumber); +} + +/** + * @brief Data Ready callback in non-blocking mode. + * @note When RNG_FLAG_DRDY flag value is set, first random number has been read + * from DR register in IRQ Handler and is provided as callback parameter. + * Depending on valid data available in the conditioning output buffer, + * additional words can be read by the application from DR register till + * DRDY bit remains high. + * @param hrng pointer to a RNG_HandleTypeDef structure that contains + * the configuration information for RNG. + * @param random32bit generated random number. + * @retval None + */ +__weak void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrng); + UNUSED(random32bit); + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_RNG_ReadyDataCallback must be implemented in the user file. + */ +} + +/** + * @brief RNG error callbacks. + * @param hrng pointer to a RNG_HandleTypeDef structure that contains + * the configuration information for RNG. + * @retval None + */ +__weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrng); + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_RNG_ErrorCallback must be implemented in the user file. + */ +} +/** + * @} + */ + + +/** @addtogroup RNG_Exported_Functions_Group3 + * @brief Peripheral State functions + * +@verbatim + =============================================================================== + ##### Peripheral State functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Returns the RNG state. + * @param hrng pointer to a RNG_HandleTypeDef structure that contains + * the configuration information for RNG. + * @retval HAL state + */ +HAL_RNG_StateTypeDef HAL_RNG_GetState(const RNG_HandleTypeDef *hrng) +{ + return hrng->State; +} + +/** + * @brief Return the RNG handle error code. + * @param hrng: pointer to a RNG_HandleTypeDef structure. + * @retval RNG Error Code + */ +uint32_t HAL_RNG_GetError(const RNG_HandleTypeDef *hrng) +{ + /* Return RNG Error Code */ + return hrng->ErrorCode; +} +/** + * @} + */ + +/** + * @} + */ +/* Private functions ---------------------------------------------------------*/ +/** @addtogroup RNG_Private_Functions + * @{ + */ + +/** + * @brief RNG sequence to recover from a seed error + * @param hrng pointer to a RNG_HandleTypeDef structure. + * @retval HAL status + */ +HAL_StatusTypeDef RNG_RecoverSeedError(RNG_HandleTypeDef *hrng) +{ + __IO uint32_t count = 0U; + + /*Check if seed error current status (SECS)is set */ + if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) == RESET) + { + /* RNG performed the reset automatically (auto-reset) */ + /* Clear bit SEIS */ + CLEAR_BIT(hrng->Instance->SR, RNG_IT_SEI); + } + else /* Sequence to fully recover from a seed error*/ + { + /* Writing bit CONDRST=1*/ + SET_BIT(hrng->Instance->CR, RNG_CR_CONDRST); + /* Writing bit CONDRST=0*/ + CLEAR_BIT(hrng->Instance->CR, RNG_CR_CONDRST); + + /* Wait for conditioning reset process to be completed */ + count = RNG_TIMEOUT_VALUE; + do + { + count-- ; + if (count == 0U) + { + hrng->State = HAL_RNG_STATE_READY; + hrng->ErrorCode |= HAL_RNG_ERROR_TIMEOUT; + /* Process Unlocked */ + __HAL_UNLOCK(hrng); +#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) + /* Call registered Error callback */ + hrng->ErrorCallback(hrng); +#else + /* Call legacy weak Error callback */ + HAL_RNG_ErrorCallback(hrng); +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ + return HAL_ERROR; + } + } while (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST)); + + if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET) + { + /* Clear bit SEIS */ + CLEAR_BIT(hrng->Instance->SR, RNG_IT_SEI); + } + + /* Wait for SECS to be cleared */ + count = RNG_TIMEOUT_VALUE; + do + { + count-- ; + if (count == 0U) + { + hrng->State = HAL_RNG_STATE_READY; + hrng->ErrorCode |= HAL_RNG_ERROR_TIMEOUT; + /* Process Unlocked */ + __HAL_UNLOCK(hrng); +#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) + /* Call registered Error callback */ + hrng->ErrorCallback(hrng); +#else + /* Call legacy weak Error callback */ + HAL_RNG_ErrorCallback(hrng); +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ + return HAL_ERROR; + } + } while (HAL_IS_BIT_SET(hrng->Instance->SR, RNG_FLAG_SECS)); + } + /* Update the error code */ + hrng->ErrorCode &= ~ HAL_RNG_ERROR_SEED; + return HAL_OK; +} + +/** + * @} + */ + + +#endif /* HAL_RNG_MODULE_ENABLED */ +/** + * @} + */ + +#endif /* RNG */ + +/** + * @} + */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_rng_ex.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_rng_ex.c new file mode 100644 index 0000000000..3de5f9f590 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_rng_ex.c @@ -0,0 +1,338 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_rng_ex.c + * @author MCD Application Team + * @brief Extended RNG HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Random Number Generator (RNG) peripheral: + * + Lock configuration functions + * + Reset the RNG + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +#if defined(RNG) + +/** @addtogroup RNG_Ex + * @brief RNG Extended HAL module driver. + * @{ + */ + +#ifdef HAL_RNG_MODULE_ENABLED +#if defined(RNG_CR_CONDRST) +/* Private types -------------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup RNG_Ex_Private_Constants + * @{ + */ +#define RNG_TIMEOUT_VALUE 2U +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +/* Private functions prototypes ----------------------------------------------*/ +/* Private functions --------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup RNG_Ex_Exported_Functions RNG_Ex Exported Functions + * @{ + */ + +/** @defgroup RNG_Ex_Exported_Functions_Group1 Configuration and lock functions + * @brief Configuration functions + * +@verbatim + =============================================================================== + ##### Configuration and lock functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure the RNG with the specified parameters in the RNG_ConfigTypeDef + (+) Lock RNG configuration Allows user to lock a configuration until next reset. + +@endverbatim + * @{ + */ + +/** + * @brief Configure the RNG with the specified parameters in the + * RNG_ConfigTypeDef. + * @param hrng pointer to a RNG_HandleTypeDef structure that contains + * the configuration information for RNG. + * @param pConf pointer to a RNG_ConfigTypeDef structure that contains + * the configuration information for RNG module + + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, const RNG_ConfigTypeDef *pConf) +{ + uint32_t tickstart; + uint32_t cr_value; + HAL_StatusTypeDef status ; + + /* Check the RNG handle allocation */ + if ((hrng == NULL) || (pConf == NULL)) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RNG_ALL_INSTANCE(hrng->Instance)); + assert_param(IS_RNG_CLOCK_DIVIDER(pConf->ClockDivider)); + assert_param(IS_RNG_NIST_COMPLIANCE(pConf->NistCompliance)); + assert_param(IS_RNG_CONFIG1(pConf->Config1)); + assert_param(IS_RNG_CONFIG2(pConf->Config2)); + assert_param(IS_RNG_CONFIG3(pConf->Config3)); + assert_param(IS_RNG_ARDIS(pConf->AutoReset)); + + /* Check RNG peripheral state */ + if (hrng->State == HAL_RNG_STATE_READY) + { + /* Change RNG peripheral state */ + hrng->State = HAL_RNG_STATE_BUSY; + + /* Disable RNG */ + __HAL_RNG_DISABLE(hrng); + + /* RNG CR register configuration. Set value in CR register for : + - NIST Compliance setting + - Clock divider value + - Automatic reset to clear SECS bit + - CONFIG 1, CONFIG 2 and CONFIG 3 values */ + cr_value = (uint32_t)(pConf->ClockDivider | pConf->NistCompliance | pConf->AutoReset + | (pConf->Config1 << RNG_CR_RNG_CONFIG1_Pos) + | (pConf->Config2 << RNG_CR_RNG_CONFIG2_Pos) + | (pConf->Config3 << RNG_CR_RNG_CONFIG3_Pos)); + + MODIFY_REG(hrng->Instance->CR, RNG_CR_NISTC | RNG_CR_CLKDIV | RNG_CR_RNG_CONFIG1 + | RNG_CR_RNG_CONFIG2 | RNG_CR_RNG_CONFIG3 | RNG_CR_ARDIS, + (uint32_t)(RNG_CR_CONDRST | cr_value)); + + /* RNG health test control in accordance with NIST */ + WRITE_REG(hrng->Instance->HTCR, pConf->HealthTest); + + /* Writing bit CONDRST=0*/ + CLEAR_BIT(hrng->Instance->CR, RNG_CR_CONDRST); + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for conditioning reset process to be completed */ + while (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST)) + { + if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE) + { + /* New check to avoid false timeout detection in case of prememption */ + if (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST)) + { + hrng->State = HAL_RNG_STATE_READY; + hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; + return HAL_ERROR; + } + } + } + + /* Enable RNG */ + __HAL_RNG_ENABLE(hrng); + + /* Initialize the RNG state */ + hrng->State = HAL_RNG_STATE_READY; + + /* function status */ + status = HAL_OK; + } + else + { + hrng->ErrorCode = HAL_RNG_ERROR_BUSY; + status = HAL_ERROR; + } + + /* Return the function status */ + return status; +} + +/** + * @brief Get the RNG Configuration and fill parameters in the + * RNG_ConfigTypeDef. + * @param hrng pointer to a RNG_HandleTypeDef structure that contains + * the configuration information for RNG. + * @param pConf pointer to a RNG_ConfigTypeDef structure that contains + * the configuration information for RNG module + + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RNGEx_GetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef *pConf) +{ + + HAL_StatusTypeDef status ; + + /* Check the RNG handle allocation */ + if ((hrng == NULL) || (pConf == NULL)) + { + return HAL_ERROR; + } + + /* Check RNG peripheral state */ + if (hrng->State == HAL_RNG_STATE_READY) + { + /* Change RNG peripheral state */ + hrng->State = HAL_RNG_STATE_BUSY; + + /* Get RNG parameters */ + pConf->Config1 = (uint32_t)((hrng->Instance->CR & RNG_CR_RNG_CONFIG1) >> RNG_CR_RNG_CONFIG1_Pos) ; + pConf->Config2 = (uint32_t)((hrng->Instance->CR & RNG_CR_RNG_CONFIG2) >> RNG_CR_RNG_CONFIG2_Pos); + pConf->Config3 = (uint32_t)((hrng->Instance->CR & RNG_CR_RNG_CONFIG3) >> RNG_CR_RNG_CONFIG3_Pos); + pConf->ClockDivider = (hrng->Instance->CR & RNG_CR_CLKDIV); + pConf->NistCompliance = (hrng->Instance->CR & RNG_CR_NISTC); + pConf->AutoReset = (hrng->Instance->CR & RNG_CR_ARDIS); + pConf->HealthTest = (hrng->Instance->HTCR); + + /* Initialize the RNG state */ + hrng->State = HAL_RNG_STATE_READY; + + /* function status */ + status = HAL_OK; + } + else + { + hrng->ErrorCode |= HAL_RNG_ERROR_BUSY; + status = HAL_ERROR; + } + + /* Return the function status */ + return status; +} + +/** + * @brief RNG current configuration lock. + * @note This function allows to lock RNG peripheral configuration. + * Once locked, HW RNG reset has to be performed prior any further + * configuration update. + * @param hrng pointer to a RNG_HandleTypeDef structure that contains + * the configuration information for RNG. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng) +{ + HAL_StatusTypeDef status; + + /* Check the RNG handle allocation */ + if (hrng == NULL) + { + return HAL_ERROR; + } + + /* Check RNG peripheral state */ + if (hrng->State == HAL_RNG_STATE_READY) + { + /* Change RNG peripheral state */ + hrng->State = HAL_RNG_STATE_BUSY; + + /* Perform RNG configuration Lock */ + MODIFY_REG(hrng->Instance->CR, RNG_CR_CONFIGLOCK, RNG_CR_CONFIGLOCK); + + /* Change RNG peripheral state */ + hrng->State = HAL_RNG_STATE_READY; + + /* function status */ + status = HAL_OK; + } + else + { + hrng->ErrorCode = HAL_RNG_ERROR_BUSY; + status = HAL_ERROR; + } + + /* Return the function status */ + return status; +} + + +/** + * @} + */ + +/** @defgroup RNG_Ex_Exported_Functions_Group2 Recover from seed error function + * @brief Recover from seed error function + * +@verbatim + =============================================================================== + ##### Recover from seed error function ##### + =============================================================================== + [..] This section provide function allowing to: + (+) Recover from a seed error + +@endverbatim + * @{ + */ + +/** + * @brief RNG sequence to recover from a seed error + * @param hrng: pointer to a RNG_HandleTypeDef structure. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng) +{ + HAL_StatusTypeDef status; + + /* Check the RNG handle allocation */ + if (hrng == NULL) + { + return HAL_ERROR; + } + + /* Check RNG peripheral state */ + if (hrng->State == HAL_RNG_STATE_READY) + { + /* Change RNG peripheral state */ + hrng->State = HAL_RNG_STATE_BUSY; + + /* sequence to fully recover from a seed error */ + status = RNG_RecoverSeedError(hrng); + } + else + { + hrng->ErrorCode = HAL_RNG_ERROR_BUSY; + status = HAL_ERROR; + } + + /* Return the function status */ + return status; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* RNG_CR_CONDRST */ +#endif /* HAL_RNG_MODULE_ENABLED */ +/** + * @} + */ + +#endif /* RNG */ + +/** + * @} + */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_rtc.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_rtc.c new file mode 100644 index 0000000000..b288722a44 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_rtc.c @@ -0,0 +1,2221 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_rtc.c + * @author MCD Application Team + * @brief RTC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Real-Time Clock (RTC) peripheral: + * + Initialization/de-initialization functions + * + Calendar (Time and Date) configuration + * + Alarms (Alarm A and Alarm B) configuration + * + WakeUp Timer configuration + * + TimeStamp configuration + * + Tampers configuration + * + Backup Data Registers configuration + * + RTC Tamper and TimeStamp Pins Selection + * + Interrupts and flags management + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + =============================================================================== + ##### RTC Operating Condition ##### + =============================================================================== + [..] The real-time clock (RTC) and the RTC backup registers can be powered + from the VBAT voltage when the main VDD supply is powered off. + To retain the content of the RTC backup registers and supply the RTC + when VDD is turned off, VBAT pin can be connected to an optional + standby voltage supplied by a battery or by another source. + + ##### Backup Domain Reset ##### + =============================================================================== + [..] The backup domain reset sets all RTC registers and the RCC_BDCR register + to their reset values. + A backup domain reset is generated when one of the following events occurs: + (#) Software reset, triggered by setting the BDRST bit in the + RCC Backup domain control register (RCC_BDCR). + (#) VDD or VBAT power on, if both supplies have previously been powered off. + (#) Tamper detection event resets all data backup registers. + + ##### Backup Domain Access ##### + ================================================================== + [..] After reset, the backup domain (RTC registers and RTC backup data registers) + is protected against possible unwanted write accesses. + [..] To enable access to the RTC Domain and RTC registers, proceed as follows: + (+) Enable the Power Controller (PWR) AHB4 interface clock using the + __HAL_RCC_PWR_CLK_ENABLE() function. + (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. + (+) Call the function HAL_RCCEx_PeriphCLKConfig with RCC_PERIPHCLK_RTC for + PeriphClockSelection and select RTCClockSelection (LSE, LSI or HSEdiv32) + (+) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() function. + + ##### How to use RTC Driver ##### + =================================================================== + [..] + (+) Enable the RTC domain access (see description in the section above). + (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour + format using the HAL_RTC_Init() function. + + *** Time and Date configuration *** + =================================== + [..] + (+) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime() + and HAL_RTC_SetDate() functions. + (+) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions. + + *** Alarm configuration *** + =========================== + [..] + (+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function. + You can also configure the RTC Alarm with interrupt mode using the + HAL_RTC_SetAlarm_IT() function. + (+) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function. + + ##### RTC and low power modes ##### + ================================================================== + [..] The MCU can be woken up from a low power mode by an RTC alternate + function. + [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B), + RTC wakeup, RTC tamper event detection and RTC time stamp event detection. + These RTC alternate functions can wake up the system from the Stop and + Standby low power modes. + [..] The system can also wake up from low power modes without depending + on an external interrupt (Auto-wakeup mode), by using the RTC alarm + or the RTC wakeup events. + [..] The RTC provides a programmable time base for waking up from the + Stop or Standby mode at regular intervals. + Wakeup from STOP and STANDBY modes is possible only when the RTC clock source + is LSE or LSI. + + *** Callback registration *** + ============================================= + When The compilation define USE_HAL_RTC_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. This is the recommended configuration + in order to optimize memory/code consumption footprint/performances. + + The compilation define USE_RTC_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use Function HAL_RTC_RegisterCallback() to register an interrupt callback. + + Function HAL_RTC_RegisterCallback() allows to register following callbacks: + (+) AlarmAEventCallback : RTC Alarm A Event callback. + (+) AlarmBEventCallback : RTC Alarm B Event callback. + (+) TimeStampEventCallback : RTC TimeStamp Event callback. + (+) WakeUpTimerEventCallback : RTC WakeUpTimer Event callback. + (+) SSRUEventCallback : RTC SSRU Event callback. + (+) Tamper1EventCallback : RTC Tamper 1 Event callback. + (+) Tamper2EventCallback : RTC Tamper 2 Event callback. + (+) Tamper3EventCallback : RTC Tamper 3 Event callback. + (+) Tamper4EventCallback : RTC Tamper 4 Event callback. + (+) Tamper5EventCallback : RTC Tamper 5 Event callback. + (+) Tamper6EventCallback : RTC Tamper 6 Event callback. + (+) InternalTamper3EventCallback : RTC InternalTamper 3 Event callback. + (+) InternalTamper5EventCallback : RTC InternalTamper 5 Event callback. + (+) InternalTamper6EventCallback : RTC InternalTamper 6 Event callback. + (+) InternalTamper7EventCallback : RTC InternalTamper 7 Event callback. + (+) InternalTamper8EventCallback : RTC InternalTamper 8 Event callback. + (+) InternalTamper9EventCallback : RTC InternalTamper 9 Event callback. + (+) InternalTamper11EventCallback : RTC InternalTamper 11 Event callback. + (+) InternalTamper12EventCallback : RTC InternalTamper 12 Event callback. + (+) InternalTamper13EventCallback : RTC InternalTamper 13 Event callback. + (+) MspInitCallback : RTC MspInit callback. + (+) MspDeInitCallback : RTC MspDeInit callback. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + Use function HAL_RTC_UnRegisterCallback() to reset a callback to the default + weak function. + HAL_RTC_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) AlarmAEventCallback : RTC Alarm A Event callback. + (+) AlarmBEventCallback : RTC Alarm B Event callback. + (+) TimeStampEventCallback : RTC TimeStamp Event callback. + (+) WakeUpTimerEventCallback : RTC WakeUpTimer Event callback. + (+) SSRUEventCallback : RTC SSRU Event callback. + (+) Tamper1EventCallback : RTC Tamper 1 Event callback. + (+) Tamper2EventCallback : RTC Tamper 2 Event callback. + (+) Tamper3EventCallback : RTC Tamper 3 Event callback. + (+) Tamper4EventCallback : RTC Tamper 4 Event callback. + (+) Tamper5EventCallback : RTC Tamper 5 Event callback. + (+) Tamper6EventCallback : RTC Tamper 6 Event callback. + (+) InternalTamper3EventCallback : RTC InternalTamper 3 Event callback. + (+) InternalTamper5EventCallback : RTC InternalTamper 5 Event callback. + (+) InternalTamper6EventCallback : RTC InternalTamper 6 Event callback. + (+) InternalTamper7EventCallback : RTC InternalTamper 7 Event callback. + (+) InternalTamper8EventCallback : RTC InternalTamper 8 Event callback. + (+) InternalTamper9EventCallback : RTC InternalTamper 9 Event callback. + (+) InternalTamper11EventCallback : RTC InternalTamper 11 Event callback. + (+) InternalTamper12EventCallback : RTC InternalTamper 12 Event callback. + (+) InternalTamper13EventCallback : RTC InternalTamper 13 Event callback. + (+) MspInitCallback : RTC MspInit callback. + (+) MspDeInitCallback : RTC MspDeInit callback. + + By default, after the HAL_RTC_Init() and when the state is HAL_RTC_STATE_RESET, + all callbacks are set to the corresponding weak functions : + examples AlarmAEventCallback(), TimeStampEventCallback(). + Exception done for MspInit and MspDeInit callbacks that are reset to the legacy weak function + in the HAL_RTC_Init()/HAL_RTC_DeInit() only when these callbacks are null + (not registered beforehand). + If not, MspInit or MspDeInit are not null, HAL_RTC_Init()/HAL_RTC_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + + Callbacks can be registered/unregistered in HAL_RTC_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_RTC_STATE_READY or HAL_RTC_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_RTC_RegisterCallback() before calling HAL_RTC_DeInit() + or HAL_RTC_Init() function. + + When The compilation define USE_HAL_RTC_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + + +/** @addtogroup RTC + * @brief RTC HAL module driver + * @{ + */ + +#ifdef HAL_RTC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup RTC_Exported_Functions + * @{ + */ + +/** @addtogroup RTC_Exported_Functions_Group1 + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to initialize and configure the + RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable + RTC registers Write protection, enter and exit the RTC initialization mode, + RTC registers synchronization check and reference clock detection enable. + (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base. + It is split into 2 programmable prescalers to minimize power consumption. + (++) A 7-bit asynchronous prescaler and a 15-bit synchronous prescaler. + (++) When both prescalers are used, it is recommended to configure the + asynchronous prescaler to a high value to minimize power consumption. + (#) All RTC registers are Write protected. Writing to the RTC registers + is enabled by writing a key into the Write Protection register, RTC_WPR. + (#) To configure the RTC Calendar, user application should enter + initialization mode. In this mode, the calendar counter is stopped + and its value can be updated. When the initialization sequence is + complete, the calendar restarts counting after 4 RTCCLK cycles. + (#) To read the calendar through the shadow registers after Calendar + initialization, calendar update or after wakeup from low power modes + the software must first clear the RSF flag. The software must then + wait until it is set again before reading the calendar, which means + that the calendar registers have been correctly copied into the + RTC_TR and RTC_DR shadow registers. The HAL_RTC_WaitForSynchro() function + implements the above software sequence (RSF clear and RSF check). + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the RTC peripheral + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) +{ + HAL_StatusTypeDef status = HAL_ERROR; + + /* Check the RTC peripheral state */ + if (hrtc != NULL) + { + /* Check the parameters */ + assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance)); + assert_param(IS_RTC_HOUR_FORMAT(hrtc->Init.HourFormat)); + assert_param(IS_RTC_ASYNCH_PREDIV(hrtc->Init.AsynchPrediv)); + assert_param(IS_RTC_SYNCH_PREDIV(hrtc->Init.SynchPrediv)); +#if defined(RTC_CR_OSEL) + assert_param(IS_RTC_OUTPUT(hrtc->Init.OutPut)); + assert_param(IS_RTC_OUTPUT_POL(hrtc->Init.OutPutPolarity)); + assert_param(IS_RTC_OUTPUT_TYPE(hrtc->Init.OutPutType)); + assert_param(IS_RTC_OUTPUT_PULLUP(hrtc->Init.OutPutPullUp)); +#endif /* RTC_CR_OSEL */ +#if defined(RTC_CR_OUT2EN) + assert_param(IS_RTC_OUTPUT_REMAP(hrtc->Init.OutPutRemap)); +#endif /* RTC_CR_OUT2EN */ + assert_param(IS_RTC_BINARY_MODE(hrtc->Init.BinMode)); + assert_param(IS_RTC_BINARY_MIX_BCDU(hrtc->Init.BinMixBcdU)); + +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + if (hrtc->State == HAL_RTC_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hrtc->Lock = HAL_UNLOCKED; + + /* Legacy weak AlarmAEventCallback */ + hrtc->AlarmAEventCallback = HAL_RTC_AlarmAEventCallback; + /* Legacy weak AlarmBEventCallback */ + hrtc->AlarmBEventCallback = HAL_RTCEx_AlarmBEventCallback; + /* Legacy weak TimeStampEventCallback */ + hrtc->TimeStampEventCallback = HAL_RTCEx_TimeStampEventCallback; + /* Legacy weak WakeUpTimerEventCallback */ + hrtc->WakeUpTimerEventCallback = HAL_RTCEx_WakeUpTimerEventCallback; + /* Legacy weak SSRUEventCallback */ + hrtc->SSRUEventCallback = HAL_RTCEx_SSRUEventCallback; + /* Legacy weak Tamper1EventCallback */ + hrtc->Tamper1EventCallback = HAL_RTCEx_Tamper1EventCallback; + /* Legacy weak Tamper2EventCallback */ + hrtc->Tamper2EventCallback = HAL_RTCEx_Tamper2EventCallback; + /* Legacy weak Tamper3EventCallback */ + hrtc->Tamper3EventCallback = HAL_RTCEx_Tamper3EventCallback; + /* Legacy weak Tamper4EventCallback */ + hrtc->Tamper4EventCallback = HAL_RTCEx_Tamper4EventCallback; + /* Legacy weak Tamper5EventCallback */ + hrtc->Tamper5EventCallback = HAL_RTCEx_Tamper5EventCallback; + /* Legacy weak Tamper6EventCallback */ + hrtc->Tamper6EventCallback = HAL_RTCEx_Tamper6EventCallback; + /* Legacy weak InternalTamper3EventCallback */ + hrtc->InternalTamper3EventCallback = HAL_RTCEx_InternalTamper3EventCallback; + /* Legacy weak InternalTamper5EventCallback */ + hrtc->InternalTamper5EventCallback = HAL_RTCEx_InternalTamper5EventCallback; + /* Legacy weak InternalTamper6EventCallback */ + hrtc->InternalTamper6EventCallback = HAL_RTCEx_InternalTamper6EventCallback; + /* Legacy weak InternalTamper7EventCallback */ + hrtc->InternalTamper7EventCallback = HAL_RTCEx_InternalTamper7EventCallback; + /* Legacy weak InternalTamper8EventCallback */ + hrtc->InternalTamper8EventCallback = HAL_RTCEx_InternalTamper8EventCallback; + /* Legacy weak InternalTamper9EventCallback */ + hrtc->InternalTamper9EventCallback = HAL_RTCEx_InternalTamper9EventCallback; + /* Legacy weak InternalTamper11EventCallback */ + hrtc->InternalTamper11EventCallback = HAL_RTCEx_InternalTamper11EventCallback; + /* Legacy weak InternalTamper12EventCallback */ + hrtc->InternalTamper12EventCallback = HAL_RTCEx_InternalTamper12EventCallback; + /* Legacy weak InternalTamper13EventCallback */ + hrtc->InternalTamper13EventCallback = HAL_RTCEx_InternalTamper13EventCallback; + + if (hrtc->MspInitCallback == NULL) + { + hrtc->MspInitCallback = HAL_RTC_MspInit; + } + /* Init the low level hardware */ + hrtc->MspInitCallback(hrtc); + + if (hrtc->MspDeInitCallback == NULL) + { + hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; + } + } +#else + if (hrtc->State == HAL_RTC_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hrtc->Lock = HAL_UNLOCKED; + + /* Initialize RTC MSP */ + HAL_RTC_MspInit(hrtc); + } +#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ + + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Check if the calendar has been not initialized */ + if (__HAL_RTC_IS_CALENDAR_INITIALIZED(hrtc) == 0U) + { + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); + if (status == HAL_OK) + { +#if defined(RTC_CR_OSEL) + /* Clear RTC_CR FMT, OSEL and POL Bits */ + CLEAR_BIT(RTC->CR, (RTC_CR_FMT | RTC_CR_POL | RTC_CR_OSEL | RTC_CR_TAMPOE)); + + /* Set RTC_CR register */ + SET_BIT(RTC->CR, (hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity)); +#else + /* Clear RTC_CR FMT Bits */ + CLEAR_BIT(RTC->CR, RTC_CR_FMT); + + /* Set RTC_CR register */ + SET_BIT(RTC->CR, hrtc->Init.HourFormat); +#endif /* RTC_CR_OSEL */ + + /* Configure the RTC PRER */ + WRITE_REG(RTC->PRER, ((hrtc->Init.SynchPrediv) | (hrtc->Init.AsynchPrediv << RTC_PRER_PREDIV_A_Pos))); + + /* Configure the Binary mode */ + MODIFY_REG(RTC->ICSR, RTC_ICSR_BIN | RTC_ICSR_BCDU, hrtc->Init.BinMode | hrtc->Init.BinMixBcdU); + + /* Exit Initialization mode */ + status = RTC_ExitInitMode(hrtc); + +#if defined(RTC_CR_OSEL) + if (status == HAL_OK) + { +#if defined(RTC_CR_OUT2EN) + MODIFY_REG(RTC->CR, \ + RTC_CR_TAMPALRM_PU | RTC_CR_TAMPALRM_TYPE | RTC_CR_OUT2EN, \ + hrtc->Init.OutPutPullUp | hrtc->Init.OutPutType | hrtc->Init.OutPutRemap); +#else + MODIFY_REG(RTC->CR, \ + RTC_CR_TAMPALRM_PU | RTC_CR_TAMPALRM_TYPE, \ + hrtc->Init.OutPutPullUp | hrtc->Init.OutPutType); +#endif /* RTC_CR_OUT2EN */ + } +#endif /* RTC_CR_OSEL */ + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + } + else + { + /* Calendar is already initialized */ + /* Set flag to OK */ + status = HAL_OK; + } + + if (status == HAL_OK) + { + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + } + } + + return status; +} + +/** + * @brief DeInitialize the RTC peripheral. + * @note This function does not reset the RTC Backup Data registers. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc) +{ + HAL_StatusTypeDef status; + + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); + if (status == HAL_OK) + { + /* Reset all RTC CR register bits */ + CLEAR_REG(RTC->CR); + WRITE_REG(RTC->DR, (uint32_t)(RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0)); + CLEAR_REG(RTC->TR); + WRITE_REG(RTC->WUTR, RTC_WUTR_WUT); + WRITE_REG(RTC->PRER, ((uint32_t)(RTC_PRER_PREDIV_A | 0xFFU))); + CLEAR_REG(RTC->ALRMAR); + CLEAR_REG(RTC->ALRMBR); + CLEAR_REG(RTC->SHIFTR); + CLEAR_REG(RTC->CALR); + CLEAR_REG(RTC->ALRMASSR); + CLEAR_REG(RTC->ALRMBSSR); + WRITE_REG(RTC->SCR, RTC_SCR_CTSOVF | RTC_SCR_CTSF | RTC_SCR_CWUTF | RTC_SCR_CALRBF | RTC_SCR_CALRAF); +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + CLEAR_REG(RTC->SECCFGR); +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#if defined (RTC_PRIVCFGR_ALRAPRIV) + CLEAR_REG(RTC->PRIVCFGR); +#endif /* RTC_PRIVCFGR_ALRAPRIV */ + + /* Exit initialization mode */ + status = RTC_ExitInitMode(hrtc); + if (status == HAL_OK) + { + /* Reset TAMP registers */ + CLEAR_REG(TAMP->CR1); + CLEAR_REG(TAMP->CR2); + CLEAR_REG(TAMP->CR3); + CLEAR_REG(TAMP->FLTCR); + WRITE_REG(TAMP->ATCR1, TAMP_ATCR1_ATCKSEL); + CLEAR_REG(TAMP->ATOR); + CLEAR_REG(TAMP->ATCR2); +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + CLEAR_REG(TAMP->SECCFGR); +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#if defined (TAMP_PRIVCFGR_TAMPPRIV) + CLEAR_REG(TAMP->PRIVCFGR); +#endif /* TAMP_PRIVCFGR_TAMPPRIV */ + } + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + if (status == HAL_OK) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + if (hrtc->MspDeInitCallback == NULL) + { + hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; + } + + /* DeInit the low level hardware: CLOCK, NVIC.*/ + hrtc->MspDeInitCallback(hrtc); + +#else + /* De-Initialize RTC MSP */ + HAL_RTC_MspDeInit(hrtc); +#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_RESET; + } + + /* Release Lock */ + __HAL_UNLOCK(hrtc); + + return status; +} + +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User RTC Callback + * To be used instead of the weak predefined callback + * @param hrtc RTC handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_RTC_ALARM_A_EVENT_CB_ID Alarm A Event Callback ID + * @arg @ref HAL_RTC_ALARM_B_EVENT_CB_ID Alarm B Event Callback ID + * @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID TimeStamp Event Callback ID + * @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID WakeUp Timer Event Callback ID + * @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID + * @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID Tamper 2 Callback ID + * @arg @ref HAL_RTC_TAMPER3_EVENT_CB_ID Tamper 3 Callback ID + * @arg @ref HAL_RTC_TAMPER4_EVENT_CB_ID Tamper 4 Callback ID + * @arg @ref HAL_RTC_TAMPER5_EVENT_CB_ID Tamper 5 Callback ID + * @arg @ref HAL_RTC_TAMPER6_EVENT_CB_ID Tamper 6 Callback ID + * @arg @ref HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID Internal Tamper 3 Callback ID + * @arg @ref HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID Internal Tamper 5 Callback ID + * @arg @ref HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID Internal Tamper 6 Callback ID + * @arg @ref HAL_RTC_INTERNAL_TAMPER7_EVENT_CB_ID Internal Tamper 7 Callback ID + * @arg @ref HAL_RTC_INTERNAL_TAMPER8_EVENT_CB_ID Internal Tamper 8 Callback ID + * @arg @ref HAL_RTC_INTERNAL_TAMPER9_EVENT_CB_ID Internal Tamper 9 Callback ID + * @arg @ref HAL_RTC_INTERNAL_TAMPER11_EVENT_CB_ID Internal Tamper 11 Callback ID + * @arg @ref HAL_RTC_INTERNAL_TAMPER12_EVENT_CB_ID Internal Tamper 12 Callback ID + * @arg @ref HAL_RTC_INTERNAL_TAMPER13_EVENT_CB_ID Internal Tamper 13 Callback ID + * @arg @ref HAL_RTC_MSPINIT_CB_ID Msp Init callback ID + * @arg @ref HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID + * @param pCallback pointer to the Callback function + * @note The HAL_RTC_RegisterCallback() may be called before HAL_RTC_Init() in HAL_RTC_STATE_RESET + * to register callbacks for HAL_RTC_MSPINIT_CB_ID and HAL_RTC_MSPDEINIT_CB_ID. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, + pRTC_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + return HAL_ERROR; + } + + if (HAL_RTC_STATE_READY == hrtc->State) + { + switch (CallbackID) + { + case HAL_RTC_ALARM_A_EVENT_CB_ID : + hrtc->AlarmAEventCallback = pCallback; + break; + + case HAL_RTC_ALARM_B_EVENT_CB_ID : + hrtc->AlarmBEventCallback = pCallback; + break; + + case HAL_RTC_TIMESTAMP_EVENT_CB_ID : + hrtc->TimeStampEventCallback = pCallback; + break; + + case HAL_RTC_WAKEUPTIMER_EVENT_CB_ID : + hrtc->WakeUpTimerEventCallback = pCallback; + break; + + case HAL_RTC_SSRU_EVENT_CB_ID : + hrtc->SSRUEventCallback = pCallback; + break; + + case HAL_RTC_TAMPER1_EVENT_CB_ID : + hrtc->Tamper1EventCallback = pCallback; + break; + + case HAL_RTC_TAMPER2_EVENT_CB_ID : + hrtc->Tamper2EventCallback = pCallback; + break; + + case HAL_RTC_TAMPER3_EVENT_CB_ID : + hrtc->Tamper3EventCallback = pCallback; + break; + + case HAL_RTC_TAMPER4_EVENT_CB_ID : + hrtc->Tamper4EventCallback = pCallback; + break; + + case HAL_RTC_TAMPER5_EVENT_CB_ID : + hrtc->Tamper5EventCallback = pCallback; + break; + + case HAL_RTC_TAMPER6_EVENT_CB_ID : + hrtc->Tamper6EventCallback = pCallback; + break; + + case HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID : + hrtc->InternalTamper3EventCallback = pCallback; + break; + + case HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID : + hrtc->InternalTamper5EventCallback = pCallback; + break; + + case HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID : + hrtc->InternalTamper6EventCallback = pCallback; + break; + + case HAL_RTC_INTERNAL_TAMPER7_EVENT_CB_ID : + hrtc->InternalTamper7EventCallback = pCallback; + break; + + case HAL_RTC_INTERNAL_TAMPER8_EVENT_CB_ID : + hrtc->InternalTamper8EventCallback = pCallback; + break; + + case HAL_RTC_INTERNAL_TAMPER9_EVENT_CB_ID : + hrtc->InternalTamper9EventCallback = pCallback; + break; + + case HAL_RTC_INTERNAL_TAMPER11_EVENT_CB_ID : + hrtc->InternalTamper11EventCallback = pCallback; + break; + + case HAL_RTC_INTERNAL_TAMPER12_EVENT_CB_ID : + hrtc->InternalTamper12EventCallback = pCallback; + break; + + case HAL_RTC_INTERNAL_TAMPER13_EVENT_CB_ID : + hrtc->InternalTamper13EventCallback = pCallback; + break; + + case HAL_RTC_MSPINIT_CB_ID : + hrtc->MspInitCallback = pCallback; + break; + + case HAL_RTC_MSPDEINIT_CB_ID : + hrtc->MspDeInitCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_RTC_STATE_RESET == hrtc->State) + { + switch (CallbackID) + { + case HAL_RTC_MSPINIT_CB_ID : + hrtc->MspInitCallback = pCallback; + break; + + case HAL_RTC_MSPDEINIT_CB_ID : + hrtc->MspDeInitCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister an RTC Callback + * RTC callback is redirected to the weak predefined callback + * @param hrtc RTC handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * This parameter can be one of the following values: + * @arg @ref HAL_RTC_ALARM_A_EVENT_CB_ID Alarm A Event Callback ID + * @arg @ref HAL_RTC_ALARM_B_EVENT_CB_ID Alarm B Event Callback ID + * @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID TimeStamp Event Callback ID + * @arg @ref HAL_RTC_SSRU_EVENT_CB_ID SSRU Callback ID + * @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID WakeUp Timer Event Callback ID + * @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID + * @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID Tamper 2 Callback ID + * @arg @ref HAL_RTC_TAMPER3_EVENT_CB_ID Tamper 3 Callback ID + * @arg @ref HAL_RTC_TAMPER4_EVENT_CB_ID Tamper 4 Callback ID + * @arg @ref HAL_RTC_TAMPER5_EVENT_CB_ID Tamper 5 Callback ID + * @arg @ref HAL_RTC_TAMPER6_EVENT_CB_ID Tamper 6 Callback ID + * @arg @ref HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID Internal Tamper 3 Callback ID + * @arg @ref HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID Internal Tamper 5 Callback ID + * @arg @ref HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID Internal Tamper 6 Callback ID + * @arg @ref HAL_RTC_INTERNAL_TAMPER7_EVENT_CB_ID Internal Tamper 7 Callback ID + * @arg @ref HAL_RTC_INTERNAL_TAMPER8_EVENT_CB_ID Internal Tamper 8 Callback ID + * @arg @ref HAL_RTC_INTERNAL_TAMPER9_EVENT_CB_ID Internal Tamper 9 Callback ID + * @arg @ref HAL_RTC_INTERNAL_TAMPER11_EVENT_CB_ID Internal Tamper 11 Callback ID + * @arg @ref HAL_RTC_INTERNAL_TAMPER12_EVENT_CB_ID Internal Tamper 12 Callback ID + * @arg @ref HAL_RTC_INTERNAL_TAMPER13_EVENT_CB_ID Internal Tamper 13 Callback ID + * @arg @ref HAL_RTC_MSPINIT_CB_ID Msp Init callback ID + * @arg @ref HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID + * @note The HAL_RTC_UnRegisterCallback() may be called before HAL_RTC_Init() in HAL_RTC_STATE_RESET + * to un-register callbacks for HAL_RTC_MSPINIT_CB_ID and HAL_RTC_MSPDEINIT_CB_ID. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (HAL_RTC_STATE_READY == hrtc->State) + { + switch (CallbackID) + { + case HAL_RTC_ALARM_A_EVENT_CB_ID : + /* Legacy weak AlarmAEventCallback */ + hrtc->AlarmAEventCallback = HAL_RTC_AlarmAEventCallback; + break; + + case HAL_RTC_ALARM_B_EVENT_CB_ID : + /* Legacy weak AlarmBEventCallback */ + hrtc->AlarmBEventCallback = HAL_RTCEx_AlarmBEventCallback; + break; + + case HAL_RTC_TIMESTAMP_EVENT_CB_ID : + /* Legacy weak TimeStampEventCallback */ + hrtc->TimeStampEventCallback = HAL_RTCEx_TimeStampEventCallback; + break; + + case HAL_RTC_WAKEUPTIMER_EVENT_CB_ID : + /* Legacy weak WakeUpTimerEventCallback */ + hrtc->WakeUpTimerEventCallback = HAL_RTCEx_WakeUpTimerEventCallback; + break; + + case HAL_RTC_SSRU_EVENT_CB_ID : + /* Legacy weak SSRUEventCallback */ + hrtc->SSRUEventCallback = HAL_RTCEx_SSRUEventCallback; + break; + + case HAL_RTC_TAMPER1_EVENT_CB_ID : + /* Legacy weak Tamper1EventCallback */ + hrtc->Tamper1EventCallback = HAL_RTCEx_Tamper1EventCallback; + break; + + case HAL_RTC_TAMPER2_EVENT_CB_ID : + /* Legacy weak Tamper2EventCallback */ + hrtc->Tamper2EventCallback = HAL_RTCEx_Tamper2EventCallback; + break; + + case HAL_RTC_TAMPER3_EVENT_CB_ID : + /* Legacy weak Tamper3EventCallback */ + hrtc->Tamper3EventCallback = HAL_RTCEx_Tamper3EventCallback; + break; + + case HAL_RTC_TAMPER4_EVENT_CB_ID : + /* Legacy weak Tamper4EventCallback */ + hrtc->Tamper4EventCallback = HAL_RTCEx_Tamper4EventCallback; + break; + + case HAL_RTC_TAMPER5_EVENT_CB_ID : + /* Legacy weak Tamper5EventCallback */ + hrtc->Tamper5EventCallback = HAL_RTCEx_Tamper5EventCallback; + break; + + case HAL_RTC_TAMPER6_EVENT_CB_ID : + /* Legacy weak Tamper6EventCallback */ + hrtc->Tamper6EventCallback = HAL_RTCEx_Tamper6EventCallback; + break; + + case HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID : + /* Legacy weak InternalTamper3EventCallback */ + hrtc->InternalTamper3EventCallback = HAL_RTCEx_InternalTamper3EventCallback; + break; + + case HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID : + /* Legacy weak InternalTamper5EventCallback */ + hrtc->InternalTamper5EventCallback = HAL_RTCEx_InternalTamper5EventCallback; + break; + + case HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID : + /* Legacy weak InternalTamper6EventCallback */ + hrtc->InternalTamper6EventCallback = HAL_RTCEx_InternalTamper6EventCallback; + break; + + case HAL_RTC_INTERNAL_TAMPER7_EVENT_CB_ID : + /* Legacy weak InternalTamper7EventCallback */ + hrtc->InternalTamper7EventCallback = HAL_RTCEx_InternalTamper7EventCallback; + break; + + case HAL_RTC_INTERNAL_TAMPER8_EVENT_CB_ID : + /* Legacy weak InternalTamper8EventCallback */ + hrtc->InternalTamper8EventCallback = HAL_RTCEx_InternalTamper8EventCallback; + break; + + case HAL_RTC_INTERNAL_TAMPER9_EVENT_CB_ID : + /* Legacy weak InternalTamper9EventCallback */ + hrtc->InternalTamper9EventCallback = HAL_RTCEx_InternalTamper9EventCallback; + break; + + case HAL_RTC_INTERNAL_TAMPER11_EVENT_CB_ID : + /* Legacy weak InternalTamper11EventCallback */ + hrtc->InternalTamper11EventCallback = HAL_RTCEx_InternalTamper11EventCallback; + break; + + case HAL_RTC_INTERNAL_TAMPER12_EVENT_CB_ID : + /* Legacy weak InternalTamper12EventCallback */ + hrtc->InternalTamper12EventCallback = HAL_RTCEx_InternalTamper12EventCallback; + break; + + case HAL_RTC_INTERNAL_TAMPER13_EVENT_CB_ID : + /* Legacy weak InternalTamper13EventCallback */ + hrtc->InternalTamper13EventCallback = HAL_RTCEx_InternalTamper13EventCallback; + break; + + case HAL_RTC_MSPINIT_CB_ID : + hrtc->MspInitCallback = HAL_RTC_MspInit; + break; + + case HAL_RTC_MSPDEINIT_CB_ID : + hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_RTC_STATE_RESET == hrtc->State) + { + switch (CallbackID) + { + case HAL_RTC_MSPINIT_CB_ID : + hrtc->MspInitCallback = HAL_RTC_MspInit; + break; + + case HAL_RTC_MSPDEINIT_CB_ID : + hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + +/** + * @brief Initialize the RTC MSP. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTC_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitialize the RTC MSP. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTC_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @addtogroup RTC_Exported_Functions_Group2 + * @brief RTC Time and Date functions + * +@verbatim + =============================================================================== + ##### RTC Time and Date functions ##### + =============================================================================== + + [..] This section provides functions allowing to configure Time and Date features + +@endverbatim + * @{ + */ + +/** + * @brief Set RTC current time. + * @param hrtc RTC handle + * @param sTime Pointer to Time structure + * if Binary mode is RTC_BINARY_ONLY, this parameter is not used and RTC_SSR will be automatically + * reset to 0xFFFFFFFF + * else sTime->SubSeconds is not used and RTC_SSR will be automatically reset to the + * A 7-bit async prescaler (RTC_PRER_PREDIV_A) + * @param Format Format of sTime->Hours, sTime->Minutes and sTime->Seconds. + * if Binary mode is RTC_BINARY_ONLY, this parameter is not used + * else this parameter can be one of the following values + * @arg RTC_FORMAT_BIN: Binary format + * @arg RTC_FORMAT_BCD: BCD format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) +{ + uint32_t tmpreg; + HAL_StatusTypeDef status; + +#ifdef USE_FULL_ASSERT + /* Check the parameters depending of the Binary mode with 32-bit free-running counter configuration */ + if (READ_BIT(RTC->ICSR, RTC_ICSR_BIN) == RTC_BINARY_NONE) + { + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + } +#endif /* USE_FULL_ASSERT */ + + /* Process Locked */ + __HAL_LOCK(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); + if (status == HAL_OK) + { + /* Check Binary mode ((32-bit free-running counter) */ + if (READ_BIT(RTC->ICSR, RTC_ICSR_BIN) != RTC_BINARY_ONLY) + { + if (Format == RTC_FORMAT_BIN) + { + if (READ_BIT(RTC->CR, RTC_CR_FMT) != 0U) + { + assert_param(IS_RTC_HOUR12(sTime->Hours)); + assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat)); + } + else + { + sTime->TimeFormat = 0x00U; + assert_param(IS_RTC_HOUR24(sTime->Hours)); + } + assert_param(IS_RTC_MINUTES(sTime->Minutes)); + assert_param(IS_RTC_SECONDS(sTime->Seconds)); + + tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << RTC_TR_HU_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << RTC_TR_MNU_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sTime->Seconds) << RTC_TR_SU_Pos) | \ + (((uint32_t)sTime->TimeFormat) << RTC_TR_PM_Pos)); + } + else + { + if (READ_BIT(RTC->CR, RTC_CR_FMT) != 0U) + { + assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sTime->Hours))); + assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat)); + } + else + { + sTime->TimeFormat = 0x00U; + assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours))); + } + assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes))); + assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds))); + tmpreg = (((uint32_t)(sTime->Hours) << RTC_TR_HU_Pos) | \ + ((uint32_t)(sTime->Minutes) << RTC_TR_MNU_Pos) | \ + ((uint32_t)(sTime->Seconds) << RTC_TR_SU_Pos) | \ + ((uint32_t)(sTime->TimeFormat) << RTC_TR_PM_Pos)); + } + + /* Set the RTC_TR register */ + WRITE_REG(RTC->TR, (tmpreg & RTC_TR_RESERVED_MASK)); + + /* Clear the bits to be configured */ + CLEAR_BIT(RTC->CR, RTC_CR_BKP); + } + + /* Exit Initialization mode */ + status = RTC_ExitInitMode(hrtc); + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + if (status == HAL_OK) + { + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return status; +} + +/** + * @brief Get RTC current time. + * @note You can use SubSeconds and SecondFraction (sTime structure fields returned) to convert SubSeconds + * value in second fraction ratio with time unit following generic formula: + * Second fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit + * This conversion can be performed only if no shift operation is pending (ie. SHFP=0) when PREDIV_S >= SS + * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values + * in the higher-order calendar shadow registers to ensure consistency between the time and date values. + * Reading RTC current time locks the values in calendar shadow registers until Current date is read + * to ensure consistency between the time and date values. + * @param hrtc RTC handle + * @param sTime + * if Binary mode is RTC_BINARY_ONLY, sTime->SubSeconds only is updated + * else + * Pointer to Time structure with Hours, Minutes and Seconds fields returned + * with input format (BIN or BCD), also SubSeconds field returning the + * RTC_SSR register content and SecondFraction field the Synchronous pre-scaler + * factor to be used for second fraction ratio computation. + * @param Format Format of sTime->Hours, sTime->Minutes and sTime->Seconds. + * if Binary mode is RTC_BINARY_ONLY, this parameter is not used + * else this parameter can be one of the following values: + * @arg RTC_FORMAT_BIN: Binary format + * @arg RTC_FORMAT_BCD: BCD format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_GetTime(const RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) +{ + uint32_t tmpreg; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* Get subseconds structure field from the corresponding register */ + sTime->SubSeconds = READ_REG(RTC->SSR); + + if (READ_BIT(RTC->ICSR, RTC_ICSR_BIN) != RTC_BINARY_ONLY) + { + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + + /* Get SecondFraction structure field from the corresponding register field */ + sTime->SecondFraction = (uint32_t)(READ_REG(RTC->PRER) & RTC_PRER_PREDIV_S); + + /* Get the TR register */ + tmpreg = (uint32_t)(READ_REG(RTC->TR) & RTC_TR_RESERVED_MASK); + + /* Fill the structure fields with the read parameters */ + sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> RTC_TR_HU_Pos); + sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >> RTC_TR_MNU_Pos); + sTime->Seconds = (uint8_t)((tmpreg & (RTC_TR_ST | RTC_TR_SU)) >> RTC_TR_SU_Pos); + sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> RTC_TR_PM_Pos); + + /* Check the input parameters format */ + if (Format == RTC_FORMAT_BIN) + { + /* Convert the time structure parameters to Binary format */ + sTime->Hours = (uint8_t)RTC_Bcd2ToByte(sTime->Hours); + sTime->Minutes = (uint8_t)RTC_Bcd2ToByte(sTime->Minutes); + sTime->Seconds = (uint8_t)RTC_Bcd2ToByte(sTime->Seconds); + } + } + + return HAL_OK; +} + +/** + * @brief Set RTC current date. + * @param hrtc RTC handle + * @param sDate Pointer to date structure + * @param Format Format of sDate->Year, sDate->Month and sDate->Weekday. + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN: Binary format + * @arg RTC_FORMAT_BCD: BCD format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) +{ + uint32_t datetmpreg; + HAL_StatusTypeDef status; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + + if ((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10U) == 0x10U)) + { + sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10U)) + (uint8_t)0x0AU); + } + + assert_param(IS_RTC_WEEKDAY(sDate->WeekDay)); + + if (Format == RTC_FORMAT_BIN) + { + assert_param(IS_RTC_YEAR(sDate->Year)); + assert_param(IS_RTC_MONTH(sDate->Month)); + assert_param(IS_RTC_DATE(sDate->Date)); + + datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << RTC_DR_YU_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sDate->Month) << RTC_DR_MU_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sDate->Date) << RTC_DR_DU_Pos) | \ + ((uint32_t)sDate->WeekDay << RTC_DR_WDU_Pos)); + } + else + { + assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year))); + assert_param(IS_RTC_MONTH(RTC_Bcd2ToByte(sDate->Month))); + assert_param(IS_RTC_DATE(RTC_Bcd2ToByte(sDate->Date))); + + datetmpreg = ((((uint32_t)sDate->Year) << RTC_DR_YU_Pos) | \ + (((uint32_t)sDate->Month) << RTC_DR_MU_Pos) | \ + (((uint32_t)sDate->Date) << RTC_DR_DU_Pos) | \ + (((uint32_t)sDate->WeekDay) << RTC_DR_WDU_Pos)); + } + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); + if (status == HAL_OK) + { + /* Set the RTC_DR register */ + WRITE_REG(RTC->DR, (uint32_t)(datetmpreg & RTC_DR_RESERVED_MASK)); + + /* Exit Initialization mode */ + status = RTC_ExitInitMode(hrtc); + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + if (status == HAL_OK) + { + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return status; +} + +/** + * @brief Get RTC current date. + * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values + * in the higher-order calendar shadow registers to ensure consistency between the time and date values. + * Reading RTC current time locks the values in calendar shadow registers until Current date is read. + * @param hrtc RTC handle + * @param sDate Pointer to Date structure + * @param Format Format of sDate->Year, sDate->Month and sDate->Weekday. + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN: Binary format + * @arg RTC_FORMAT_BCD: BCD format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_GetDate(const RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) +{ + uint32_t datetmpreg; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + + /* Get the DR register */ + datetmpreg = (uint32_t)(READ_REG(RTC->DR) & RTC_DR_RESERVED_MASK); + + /* Fill the structure fields with the read parameters */ + sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> RTC_DR_YU_Pos); + sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> RTC_DR_MU_Pos); + sDate->Date = (uint8_t)((datetmpreg & (RTC_DR_DT | RTC_DR_DU)) >> RTC_DR_DU_Pos); + sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> RTC_DR_WDU_Pos); + + /* Check the input parameters format */ + if (Format == RTC_FORMAT_BIN) + { + /* Convert the date structure parameters to Binary format */ + sDate->Year = (uint8_t)RTC_Bcd2ToByte(sDate->Year); + sDate->Month = (uint8_t)RTC_Bcd2ToByte(sDate->Month); + sDate->Date = (uint8_t)RTC_Bcd2ToByte(sDate->Date); + } + return HAL_OK; +} + +/** + * @brief Daylight Saving Time, Add one hour to the calendar in one single operation + * without going through the initialization procedure. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTC_DST_Add1Hour(const RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Set RTC_CR_ADD1H Bit */ + SET_BIT(RTC->CR, RTC_CR_ADD1H); + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); +} + +/** + * @brief Daylight Saving Time, Subtract one hour from the calendar in one + * single operation without going through the initialization procedure. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTC_DST_Sub1Hour(const RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Set RTC_CR_SUB1H Bit */ + SET_BIT(RTC->CR, RTC_CR_SUB1H); + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); +} + +/** + * @brief Daylight Saving Time, Set the store operation bit. + * @note It can be used by the software in order to memorize the DST status. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTC_DST_SetStoreOperation(const RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* Set RTC_CR_BKP Bit */ + SET_BIT(RTC->CR, RTC_CR_BKP); +} + +/** + * @brief Daylight Saving Time, Clear the store operation bit. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTC_DST_ClearStoreOperation(const RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* Clear RTC_CR_BKP Bit */ + CLEAR_BIT(RTC->CR, RTC_CR_BKP); +} + +/** + * @brief Daylight Saving Time, Read the store operation bit. + * @param hrtc RTC handle + * @retval operation see RTC_StoreOperation_Definitions + */ +uint32_t HAL_RTC_DST_ReadStoreOperation(const RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* Get RTC_CR_BKP Bit */ + return READ_BIT(RTC->CR, RTC_CR_BKP); +} + + +/** + * @} + */ + +/** @addtogroup RTC_Exported_Functions_Group3 + * @brief RTC Alarm functions + * +@verbatim + =============================================================================== + ##### RTC Alarm functions ##### + =============================================================================== + + [..] This section provides functions allowing to configure Alarm feature + +@endverbatim + * @{ + */ +/** + * @brief Set the specified RTC Alarm. + * @param hrtc RTC handle + * @param sAlarm Pointer to Alarm structure + * if Binary mode is RTC_BINARY_ONLY, 3 fields only are used + * sAlarm->AlarmTime.SubSeconds + * sAlarm->AlarmSubSecondMask + * sAlarm->BinaryAutoClr + * @param Format of the entered parameters. + * if Binary mode is RTC_BINARY_ONLY, this parameter is not used + * else this parameter can be one of the following values + * @arg RTC_FORMAT_BIN: Binary format + * @arg RTC_FORMAT_BCD: BCD format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format) +{ + uint32_t tmpreg = 0; + uint32_t binary_mode; + + /* Process Locked */ + __HAL_LOCK(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + +#ifdef USE_FULL_ASSERT + /* Check the parameters depending of the Binary mode (32-bit free-running counter configuration) */ + if (READ_BIT(RTC->ICSR, RTC_ICSR_BIN) == RTC_BINARY_NONE) + { + assert_param(IS_RTC_FORMAT(Format)); + assert_param(IS_RTC_ALARM(sAlarm->Alarm)); + assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask)); + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel)); + assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds)); + assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask)); + } + else if (READ_BIT(RTC->ICSR, RTC_ICSR_BIN) == RTC_BINARY_ONLY) + { + assert_param(IS_RTC_ALARM_SUB_SECOND_BINARY_MASK(sAlarm->AlarmSubSecondMask)); + assert_param(IS_RTC_ALARMSUBSECONDBIN_AUTOCLR(sAlarm->BinaryAutoClr)); + } + else /* RTC_BINARY_MIX */ + { + assert_param(IS_RTC_FORMAT(Format)); + assert_param(IS_RTC_ALARM(sAlarm->Alarm)); + assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask)); + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel)); + /* In Binary Mix Mode, the RTC can not generate an alarm on a match + involving all calendar items + the upper SSR bits */ + assert_param((sAlarm->AlarmSubSecondMask >> RTC_ALRMASSR_MASKSS_Pos) <= + (8U + (READ_BIT(RTC->ICSR, RTC_ICSR_BCDU) >> RTC_ICSR_BCDU_Pos))); + } +#endif /* USE_FULL_ASSERT */ + + /* Get Binary mode (32-bit free-running counter configuration) */ + binary_mode = READ_BIT(RTC->ICSR, RTC_ICSR_BIN); + + if (binary_mode != RTC_BINARY_ONLY) + { + if (Format == RTC_FORMAT_BIN) + { + if (READ_BIT(RTC->CR, RTC_CR_FMT) != 0U) + { + assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours)); + assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); + } + else + { + sAlarm->AlarmTime.TimeFormat = 0x00U; + assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours)); + } + assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes)); + assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds)); + + if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay)); + } + else + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay)); + } + tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos) | \ + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \ + ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ + ((uint32_t)sAlarm->AlarmMask)); + } + else /* format BCD */ + { + if (READ_BIT(RTC->CR, RTC_CR_FMT) != 0U) + { + assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); + assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); + } + else + { + sAlarm->AlarmTime.TimeFormat = 0x00U; + assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); + } + + assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes))); + assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds))); + +#ifdef USE_FULL_ASSERT + if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay))); + } + else + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay))); + } + +#endif /* USE_FULL_ASSERT */ + tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ + ((uint32_t)(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \ + ((uint32_t)(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos) | \ + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \ + ((uint32_t)(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \ + ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ + ((uint32_t)sAlarm->AlarmMask)); + } + } + + /* Configure the Alarm register */ + if (sAlarm->Alarm == RTC_ALARM_A) + { + /* Disable the Alarm A interrupt */ + + /* In case of interrupt mode is used, the interrupt source must disabled */ + CLEAR_BIT(RTC->CR, (RTC_CR_ALRAE | RTC_CR_ALRAIE)); + + /* Clear flag alarm A */ + WRITE_REG(RTC->SCR, RTC_SCR_CALRAF); + + if (binary_mode == RTC_BINARY_ONLY) + { + WRITE_REG(RTC->ALRMASSR, sAlarm->AlarmSubSecondMask | sAlarm->BinaryAutoClr); + } + else + { + WRITE_REG(RTC->ALRMAR, tmpreg); + WRITE_REG(RTC->ALRMASSR, sAlarm->AlarmSubSecondMask); + } + + WRITE_REG(RTC->ALRABINR, sAlarm->AlarmTime.SubSeconds); + + if (sAlarm->FlagAutoClr == ALARM_FLAG_AUTOCLR_ENABLE) + { + /* Configure the Alarm A output clear */ + SET_BIT(RTC->CR, RTC_CR_ALRAFCLR); + } + else + { + /* Disable the Alarm A output clear */ + CLEAR_BIT(RTC->CR, RTC_CR_ALRAFCLR); + } + /* Configure the Alarm state: Enable Alarm */ + SET_BIT(RTC->CR, RTC_CR_ALRAE); + } + else + { + /* Disable the Alarm B interrupt */ + + /* In case of interrupt mode is used, the interrupt source must disabled */ + CLEAR_BIT(RTC->CR, (RTC_CR_ALRBE | RTC_CR_ALRBIE)); + + /* Clear flag alarm B */ + WRITE_REG(RTC->SCR, RTC_SCR_CALRBF); + + if (binary_mode == RTC_BINARY_ONLY) + { + WRITE_REG(RTC->ALRMBSSR, sAlarm->AlarmSubSecondMask | sAlarm->BinaryAutoClr); + } + else + { + WRITE_REG(RTC->ALRMBR, tmpreg); + + WRITE_REG(RTC->ALRMBSSR, sAlarm->AlarmSubSecondMask); + } + + WRITE_REG(RTC->ALRBBINR, sAlarm->AlarmTime.SubSeconds); + + if (sAlarm->FlagAutoClr == ALARM_FLAG_AUTOCLR_ENABLE) + { + /* Configure the Alarm B output clear */ + SET_BIT(RTC->CR, RTC_CR_ALRBFCLR); + } + else + { + /* Disable the Alarm B output clear */ + CLEAR_BIT(RTC->CR, RTC_CR_ALRBFCLR); + } + + /* Configure the Alarm state: Enable Alarm */ + SET_BIT(RTC->CR, RTC_CR_ALRBE); + } + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Set the specified RTC Alarm with Interrupt. + * @param hrtc RTC handle + * @param sAlarm Pointer to Alarm structure + * if Binary mode is RTC_BINARY_ONLY, 3 fields only are used + * sAlarm->AlarmTime.SubSeconds + * sAlarm->AlarmSubSecondMask + * sAlarm->BinaryAutoClr + * @param Format Specifies the format of the entered parameters. + * if Binary mode is RTC_BINARY_ONLY, this parameter is not used + * else this parameter can be one of the following values + * @arg RTC_FORMAT_BIN: Binary format + * @arg RTC_FORMAT_BCD: BCD format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format) +{ + uint32_t tmpreg = 0; + uint32_t binary_mode; + + /* Process Locked */ + __HAL_LOCK(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + +#ifdef USE_FULL_ASSERT + /* Check the parameters depending of the Binary mode (32-bit free-running counter configuration) */ + if (READ_BIT(RTC->ICSR, RTC_ICSR_BIN) == RTC_BINARY_NONE) + { + assert_param(IS_RTC_FORMAT(Format)); + assert_param(IS_RTC_ALARM(sAlarm->Alarm)); + assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask)); + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel)); + assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds)); + assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask)); + } + else if (READ_BIT(RTC->ICSR, RTC_ICSR_BIN) == RTC_BINARY_ONLY) + { + assert_param(IS_RTC_ALARM_SUB_SECOND_BINARY_MASK(sAlarm->AlarmSubSecondMask)); + assert_param(IS_RTC_ALARMSUBSECONDBIN_AUTOCLR(sAlarm->BinaryAutoClr)); + } + else /* RTC_BINARY_MIX */ + { + assert_param(IS_RTC_FORMAT(Format)); + assert_param(IS_RTC_ALARM(sAlarm->Alarm)); + assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask)); + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel)); + /* In Binary Mix Mode, the RTC can not generate an alarm on a match + involving all calendar items + the upper SSR bits */ + assert_param((sAlarm->AlarmSubSecondMask >> RTC_ALRMASSR_MASKSS_Pos) <= + (8U + (READ_BIT(RTC->ICSR, RTC_ICSR_BCDU) >> RTC_ICSR_BCDU_Pos))); + } +#endif /* USE_FULL_ASSERT */ + + /* Get Binary mode (32-bit free-running counter configuration) */ + binary_mode = READ_BIT(RTC->ICSR, RTC_ICSR_BIN); + + if (binary_mode != RTC_BINARY_ONLY) + { + if (Format == RTC_FORMAT_BIN) + { + if (READ_BIT(RTC->CR, RTC_CR_FMT) != 0U) + { + assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours)); + assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); + } + else + { + sAlarm->AlarmTime.TimeFormat = 0x00U; + assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours)); + } + assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes)); + assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds)); + + if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay)); + } + else + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay)); + } + tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos) | \ + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \ + ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ + ((uint32_t)sAlarm->AlarmMask)); + } + else /* Format BCD */ + { + if (READ_BIT(RTC->CR, RTC_CR_FMT) != 0U) + { + assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); + assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); + } + else + { + sAlarm->AlarmTime.TimeFormat = 0x00U; + assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); + } + + assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes))); + assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds))); + +#ifdef USE_FULL_ASSERT + if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay))); + } + else + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay))); + } + +#endif /* USE_FULL_ASSERT */ + tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ + ((uint32_t)(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \ + ((uint32_t)(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos) | \ + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \ + ((uint32_t)(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \ + ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ + ((uint32_t)sAlarm->AlarmMask)); + + } + } + + /* Configure the Alarm registers */ + if (sAlarm->Alarm == RTC_ALARM_A) + { + /* Disable the Alarm A interrupt */ + CLEAR_BIT(RTC->CR, RTC_CR_ALRAE | RTC_CR_ALRAIE); + + /* Clear flag alarm A */ + WRITE_REG(RTC->SCR, RTC_SCR_CALRAF); + + if (binary_mode == RTC_BINARY_ONLY) + { + RTC->ALRMASSR = sAlarm->AlarmSubSecondMask | sAlarm->BinaryAutoClr; + } + else + { + WRITE_REG(RTC->ALRMAR, tmpreg); + + WRITE_REG(RTC->ALRMASSR, sAlarm->AlarmSubSecondMask); + } + + WRITE_REG(RTC->ALRABINR, sAlarm->AlarmTime.SubSeconds); + + if (sAlarm->FlagAutoClr == ALARM_FLAG_AUTOCLR_ENABLE) + { + /* Configure the Alarm A output clear */ + SET_BIT(RTC->CR, RTC_CR_ALRAFCLR); + } + else + { + /* Disable the Alarm A output clear */ + CLEAR_BIT(RTC->CR, RTC_CR_ALRAFCLR); + } + + /* Configure the Alarm interrupt */ + SET_BIT(RTC->CR, RTC_CR_ALRAE | RTC_CR_ALRAIE); + } + else + { + /* Disable the Alarm B interrupt */ + CLEAR_BIT(RTC->CR, RTC_CR_ALRBE | RTC_CR_ALRBIE); + + /* Clear flag alarm B */ + WRITE_REG(RTC->SCR, RTC_SCR_CALRBF); + + if (binary_mode == RTC_BINARY_ONLY) + { + WRITE_REG(RTC->ALRMBSSR, sAlarm->AlarmSubSecondMask | sAlarm->BinaryAutoClr); + } + else + { + WRITE_REG(RTC->ALRMBR, tmpreg); + + WRITE_REG(RTC->ALRMBSSR, sAlarm->AlarmSubSecondMask); + } + + WRITE_REG(RTC->ALRBBINR, sAlarm->AlarmTime.SubSeconds); + + if (sAlarm->FlagAutoClr == ALARM_FLAG_AUTOCLR_ENABLE) + { + /* Configure the Alarm B Output clear */ + SET_BIT(RTC->CR, RTC_CR_ALRBFCLR); + } + else + { + /* Disable the Alarm B Output clear */ + CLEAR_BIT(RTC->CR, RTC_CR_ALRBFCLR); + } + + /* Configure the Alarm interrupt */ + SET_BIT(RTC->CR, RTC_CR_ALRBE | RTC_CR_ALRBIE); + } + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Deactivate the specified RTC Alarm. + * @param hrtc RTC handle + * @param Alarm Specifies the Alarm. + * This parameter can be one of the following values: + * @arg RTC_ALARM_A: AlarmA + * @arg RTC_ALARM_B: AlarmB + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm) +{ + /* Check the parameters */ + assert_param(IS_RTC_ALARM(Alarm)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + + /* In case of interrupt mode is used, the interrupt source must disabled */ + if (Alarm == RTC_ALARM_A) + { + CLEAR_BIT(RTC->CR, RTC_CR_ALRAE | RTC_CR_ALRAIE); + + /* AlarmA, Clear SSCLR */ + CLEAR_BIT(RTC->ALRMASSR, RTC_ALRMASSR_SSCLR); + } + else + { + CLEAR_BIT(RTC->CR, RTC_CR_ALRBE | RTC_CR_ALRBIE); + + /* AlarmB, Clear SSCLR */ + CLEAR_BIT(RTC->ALRMBSSR, RTC_ALRMBSSR_SSCLR); + } + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Get the RTC Alarm value and masks. + * @param hrtc RTC handle + * @param sAlarm Pointer to Date structure + * @param Alarm Specifies the Alarm. + * This parameter can be one of the following values: + * @arg RTC_ALARM_A: AlarmA + * @arg RTC_ALARM_B: AlarmB + * @param Format Specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN: Binary format + * @arg RTC_FORMAT_BCD: BCD format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_GetAlarm(const RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, + uint32_t Format) +{ + uint32_t tmpreg; + uint32_t subsecondtmpreg; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + assert_param(IS_RTC_ALARM(Alarm)); + + if (Alarm == RTC_ALARM_A) + { + /* AlarmA */ + sAlarm->Alarm = RTC_ALARM_A; + + tmpreg = READ_REG(RTC->ALRMAR); + subsecondtmpreg = (uint32_t)(READ_REG(RTC->ALRMASSR) & RTC_ALRMASSR_SS); + + /* Fill the structure with the read parameters */ + sAlarm->AlarmTime.Hours = (uint8_t)((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> RTC_ALRMAR_HU_Pos); + sAlarm->AlarmTime.Minutes = (uint8_t)((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> RTC_ALRMAR_MNU_Pos); + sAlarm->AlarmTime.Seconds = (uint8_t)((tmpreg & (RTC_ALRMAR_ST | RTC_ALRMAR_SU)) >> RTC_ALRMAR_SU_Pos); + sAlarm->AlarmTime.TimeFormat = (uint8_t)((tmpreg & RTC_ALRMAR_PM) >> RTC_ALRMAR_PM_Pos); + sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg; + sAlarm->AlarmDateWeekDay = (uint8_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> RTC_ALRMAR_DU_Pos); + sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL); + sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL); + } + else + { + sAlarm->Alarm = RTC_ALARM_B; + + tmpreg = READ_REG(RTC->ALRMBR); + subsecondtmpreg = (uint32_t)(READ_REG(RTC->ALRMBSSR) & RTC_ALRMBSSR_SS); + + /* Fill the structure with the read parameters */ + sAlarm->AlarmTime.Hours = (uint8_t)((tmpreg & (RTC_ALRMBR_HT | RTC_ALRMBR_HU)) >> RTC_ALRMBR_HU_Pos); + sAlarm->AlarmTime.Minutes = (uint8_t)((tmpreg & (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU)) >> RTC_ALRMBR_MNU_Pos); + sAlarm->AlarmTime.Seconds = (uint8_t)((tmpreg & (RTC_ALRMBR_ST | RTC_ALRMBR_SU)) >> RTC_ALRMBR_SU_Pos); + sAlarm->AlarmTime.TimeFormat = (uint8_t)((tmpreg & RTC_ALRMBR_PM) >> RTC_ALRMBR_PM_Pos); + sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg; + sAlarm->AlarmDateWeekDay = (uint8_t)((tmpreg & (RTC_ALRMBR_DT | RTC_ALRMBR_DU)) >> RTC_ALRMBR_DU_Pos); + sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMBR_WDSEL); + sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL); + } + + if (Format == RTC_FORMAT_BIN) + { + sAlarm->AlarmTime.Hours = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours); + sAlarm->AlarmTime.Minutes = RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes); + sAlarm->AlarmTime.Seconds = RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds); + sAlarm->AlarmDateWeekDay = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay); + } + + return HAL_OK; +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Handle Alarm secure interrupt request. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc) +{ + /* Get interrupt status */ + uint32_t tmp = READ_REG(RTC->SMISR); + + if ((tmp & RTC_SMISR_ALRAMF) != 0U) + { + /* Clear the AlarmA interrupt pending bit */ + WRITE_REG(RTC->SCR, RTC_SCR_CALRAF); + +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Compare Match registered Callback */ + hrtc->AlarmAEventCallback(hrtc); +#else + HAL_RTC_AlarmAEventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + } + + if ((tmp & RTC_SMISR_ALRBMF) != 0U) + { + /* Clear the AlarmB interrupt pending bit */ + WRITE_REG(RTC->SCR, RTC_SCR_CALRBF); + +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Compare Match registered Callback */ + hrtc->AlarmBEventCallback(hrtc); +#else + HAL_RTCEx_AlarmBEventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + + } + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; +} + +#else /* #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/** + * @brief Handle Alarm non-secure interrupt request. + * @note Alarm non-secure is available in non-secure driver. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc) +{ + /* Get interrupt status */ + uint32_t tmp = READ_REG(RTC->MISR); + + if ((tmp & RTC_MISR_ALRAMF) != 0U) + { + /* Clear the AlarmA interrupt pending bit */ + WRITE_REG(RTC->SCR, RTC_SCR_CALRAF); + +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Compare Match registered Callback */ + hrtc->AlarmAEventCallback(hrtc); +#else + HAL_RTC_AlarmAEventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + } + + if ((tmp & RTC_MISR_ALRBMF) != 0U) + { + /* Clear the AlarmB interrupt pending bit */ + WRITE_REG(RTC->SCR, RTC_SCR_CALRBF); + +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Compare Match registered Callback */ + hrtc->AlarmBEventCallback(hrtc); +#else + HAL_RTCEx_AlarmBEventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + } + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; +} +#endif /* #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/** + * @brief Alarm A secure callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the secure callback is needed, + the HAL_RTC_AlarmAEventCallback could be implemented in the user file + */ +} + +/** + * @brief Handle Alarm A Polling request. + * @param hrtc RTC handle + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(const RTC_HandleTypeDef *hrtc, uint32_t Timeout) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + uint32_t tickstart = HAL_GetTick(); + + while (READ_BIT(RTC->SR, RTC_SR_ALRAF) == 0U) + { + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RTC->SR, RTC_SR_ALRAF) == 0U) + { + return HAL_TIMEOUT; + } + else + { + break; + } + } + } + } + + /* Clear the Alarm interrupt pending bit */ + WRITE_REG(RTC->SCR, RTC_SCR_CALRAF); + + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup RTC_Exported_Functions_Group4 + * @brief Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Wait for RTC Time and Date Synchronization + +@endverbatim + * @{ + */ + +/** + * @brief Wait until the RTC Time and Date registers (RTC_TR and RTC_DR) are + * synchronized with RTC APB clock. + * @note The RTC Resynchronization mode is write protected, use the + * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function. + * @note To read the calendar through the shadow registers after Calendar + * initialization, calendar update or after wakeup from low power modes + * the software must first clear the RSF flag. + * The software must then wait until it is set again before reading + * the calendar, which means that the calendar registers have been + * correctly copied into the RTC_TR and RTC_DR shadow registers. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc) +{ + uint32_t tickstart; + + /* Clear RSF flag */ + CLEAR_BIT(RTC->ICSR, RTC_ICSR_RSF); + + tickstart = HAL_GetTick(); + + /* Wait the registers to be synchronised */ + while (READ_BIT(RTC->ICSR, RTC_ICSR_RSF) == 0U) + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + { + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RTC->ICSR, RTC_ICSR_RSF) == 0U) + { + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_TIMEOUT; + return HAL_TIMEOUT; + } + else + { + break; + } + } + } + + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup RTC_Exported_Functions_Group5 + * @brief Peripheral State functions + * +@verbatim + =============================================================================== + ##### Peripheral State functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Get RTC state + +@endverbatim + * @{ + */ +/** + * @brief Return the RTC handle state. + * @param hrtc RTC handle + * @retval HAL state + */ +HAL_RTCStateTypeDef HAL_RTC_GetState(const RTC_HandleTypeDef *hrtc) +{ + /* Return RTC handle state */ + return hrtc->State; +} + +/** + * @} + */ +/** + * @} + */ + +/** @addtogroup RTC_Private_Functions + * @{ + */ +/** + * @brief Enter the RTC Initialization mode. + * @note The RTC Initialization mode is write protected, use the + * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc) +{ + uint32_t tickstart; + HAL_StatusTypeDef status = HAL_OK; + + /* Check if the Initialization mode is set */ + if (READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == 0U) + { + /* Set the Initialization mode */ + SET_BIT(RTC->ICSR, RTC_ICSR_INIT); + + tickstart = HAL_GetTick(); + /* Wait till RTC is in INIT state and if Time out is reached exit */ + while ((READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == 0U) && (status != HAL_TIMEOUT)) + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + { + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == 0U) + { + status = HAL_TIMEOUT; + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_TIMEOUT; + } + else + { + break; + } + } + } + } + + return status; +} + +/** + * @brief Exit the RTC Initialization mode. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Exit Initialization mode */ + CLEAR_BIT(RTC->ICSR, RTC_ICSR_INIT); + + /* If CR_BYPSHAD bit = 0, wait for synchro */ + if (READ_BIT(RTC->CR, RTC_CR_BYPSHAD) == 0U) + { + if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) + { + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_TIMEOUT; + status = HAL_TIMEOUT; + } + } + else /* WA 2.9.6 Calendar initialization may fail in case of consecutive INIT mode entry. */ + { + /* Clear BYPSHAD bit */ + CLEAR_BIT(RTC->CR, RTC_CR_BYPSHAD); + if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) + { + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_TIMEOUT; + status = HAL_TIMEOUT; + } + /* Restore BYPSHAD bit */ + SET_BIT(RTC->CR, RTC_CR_BYPSHAD); + } + return status; +} + +/** + * @brief Convert a 2 digit decimal to BCD format. + * @param Value Byte to be converted + * @retval Converted byte + */ +uint8_t RTC_ByteToBcd2(uint8_t Value) +{ + uint32_t bcd_high = 0U; + uint8_t tmp_value = Value; + + while (tmp_value >= 10U) + { + bcd_high++; + tmp_value -= 10U; + } + + return ((uint8_t)(bcd_high << 4U) | tmp_value); +} + +/** + * @brief Convert from 2 digit BCD to Binary. + * @param Value BCD value to be converted + * @retval Converted word + */ +uint8_t RTC_Bcd2ToByte(uint8_t Value) +{ + uint32_t tmp; + + tmp = (((uint32_t)Value & 0xF0U) >> 4) * 10U; + + return (uint8_t)(tmp + ((uint32_t)Value & 0x0FU)); +} + +/** + * @} + */ + +#endif /* HAL_RTC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_rtc_ex.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_rtc_ex.c new file mode 100644 index 0000000000..27b2e0dd9f --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_rtc_ex.c @@ -0,0 +1,2886 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_rtc_ex.c + * @author MCD Application Team + * @brief Extended RTC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Real Time Clock (RTC) Extended peripheral: + * + RTC Time Stamp functions + * + RTC Tamper functions + * + RTC Wake-up functions + * + Extended Control functions + * + Extended RTC features functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (+) Enable the RTC domain access. + (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour + format using the HAL_RTC_Init() function. + + *** RTC Wakeup configuration *** + ================================ + [..] + (+) To configure the RTC Wakeup Clock source and Counter use the HAL_RTCEx_SetWakeUpTimer() + function. You can also configure the RTC Wakeup timer with interrupt mode + using the HAL_RTCEx_SetWakeUpTimer_IT() function. + (+) To read the RTC WakeUp Counter register, use the HAL_RTCEx_GetWakeUpTimer() + function. + + *** Outputs configuration *** + ============================= + [..] The RTC has 2 outputs pins (RTC_OUT1 & RTC_OUT2). + To configure the outputs, use the HAL_RTC_Init() function. + (+) RTC_OUT1 and RTC_OUT2 which select one of the following two outputs: + (+) CALIB: 512Hz or 1Hz clock output (with an LSE frequency of 32.768kHz). + To enable the CALIB, use the HAL_RTCEx_SetCalibrationOutPut() function. + (+) TAMPALRM: This output is the OR between rtc_tamp_evt and ALARM signals. + ALARM is enabled by configuring the OSEL[1:0] bits in the RTC_CR register + which select the alarm A, alarm B or wakeup outputs. + rtc_tamp_evt is enabled by setting the TAMPOE bit + in the RTC_CR register which selects the tamper event outputs. + + *** Smooth digital Calibration configuration *** + ================================================ + [..] + (+) Configure the RTC Original Digital Calibration Value and the corresponding + calibration cycle period (32s,16s and 8s) using the HAL_RTCEx_SetSmoothCalib() + function. + + *** RTC synchronization *** + ================================================ + [..] + (+) The RTC can be finely adjusted using HAL_RTCEx_SetSynchroShift() function. + Writing to RTC_SHIFTR can shift (either delay or advance) the clock with + a resolution of 1 ck_apre period. + The shift operation consists in adding the SUBFS[14:0] value to the synchronous + prescaler counter SS[15:0]: this delays the clock. + + *** Bypass shadow registers *** + ================================================ + [..] + (+) Enable bypass shadow registers using the HAL_RTCEx_EnableBypassShadow(). + When the Bypass Shadow is enabled the calendar value are taken directly + from the Calendar counter. + Thus eliminating the need to wait for the RSF bit to be set. + This is especially useful after exiting from low-power modes (Stop or Standby), + since the shadow registers are not updated during these modes. + + *** RTC ultra-low-power mode *** + ================================================ + [..] + (+) Configure the RTC ultra-low-power mode using HAL_RTCEx_SetLowPowerCalib() function. + In this case, the calibration mechanism is applied on ck_apre instead of RTCCLK. + The resulting accuracy is the same, but the calibration is performed during a + calibration cycle of about 220 x PREDIV_A x RTCCLK pulses instead of 220 RTCCLK pulses. + + *** RTC subsecond register underflow interruption *** + ================================================ + [..] + (+) Enable the RTC SSRU interruption mode using HAL_RTCEx_SetSSRU_IT() function. + In this case, when the SSR rolls under 0, an SSRU interruption is triggered. + Disable the RTC SSRU interruption mode using HAL_RTCEx_DeactivateSSRU() function. + + *** TimeStamp configuration *** + =============================== + [..] + (+) Enable the RTC TimeStamp using the HAL_RTCEx_SetTimeStamp() function. + You can also configure the RTC TimeStamp with interrupt mode using the + HAL_RTCEx_SetTimeStamp_IT() function. + (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp() + function. + + *** Tamper configuration *** + ============================ + [..] + (+) Enable the RTC Tamper and configure the Tamper filter count, trigger Edge + or Level according to the Tamper filter (if equal to 0 Edge else Level) + value, sampling frequency, NoErase, MaskFlag, precharge or discharge and + Pull-UP using the HAL_RTCEx_SetTamper() function. You can configure RTC Tamper + with interrupt mode using HAL_RTCEx_SetTamper_IT() function. + (+) The default configuration of the Tamper erases the backup registers. To avoid + erase, enable the TAMPxPOM field on the TAMP_CR2 register. + (+) With new RTC tamper configuration, you have to call HAL_RTC_Init() in order to + perform TAMP base address offset calculation. + (+) Enable Internal tamper using HAL_RTCEx_SetInternalTamper. IT mode can be chosen using + setting Interrupt field. + + *** Backup Data Registers and Device Secrets configuration *** + =========================================== + [..] + (+) To write to the RTC Backup Data registers, use the HAL_RTCEx_BKUPWrite() + function. + (+) To read the RTC Backup registers, use the HAL_RTCEx_BKUPRead() + function. + (+) To reset the RTC Backup registers and erase the device secrets, + use HAL_RTCEx_BKUPErase() function. + (+) Enable the lock of the Boot hardware Key using the HAL_RTCEx_LockBootHardwareKey() + function. + The backup registers from TAMP_BKP0R to TAMP_BKP7R cannot be accessed neither in + read nor in write (they are read as 0 and write ignore). + (+) Configure the erase of the Device Secrets using HAL_RTCEx_ConfigEraseDeviceSecrets() + function. + (+) Block the access to the RTC Backup registers and all the device secrets + using HAL_RTCEx_BKUPBlock() function. + + *** Monotonic counter *** + ================================================ + [..] + (+) To increment the Monotonic counter, use the HAL_RTCEx_MonotonicCounterIncrement() + function. + (+) To get the current value of the Monotonic counter, use the HAL_RTCEx_MonotonicCounterGet() + function. + + *** RTC & TAMP secure protection modes *** + ================================================ + [..] + (+) Set the security level of the RTC/TAMP/Backup registers using HAL_RTCEx_SecureModeSet() + function. + +) Get the security level of the RTC/TAMP/Backup registers using HAL_RTCEx_SecureModeGet() + function. + + *** RTC & TAMP privilege protection modes *** + ================================================ + [..] + (+) Set the privilege level of the RTC/TAMP/Backup registers using HAL_RTCEx_PrivilegeModeSet() + function. + +) Get the privilege level of the RTC/TAMP/Backup registers using HAL_RTCEx_PrivilegeModeGet() + function. + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @addtogroup RTCEx + * @brief RTC Extended HAL module driver + * @{ + */ + +#ifdef HAL_RTC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#ifdef TAMP_CR1_TAMP4E +#define TAMP_ALL (TAMP_CR1_TAMP1E | TAMP_CR1_TAMP2E | TAMP_CR1_TAMP3E | TAMP_CR1_TAMP4E | \ + TAMP_CR1_TAMP5E | TAMP_CR1_TAMP6E) +#else +#define TAMP_ALL (TAMP_CR1_TAMP1E | TAMP_CR1_TAMP2E | TAMP_CR1_TAMP3E) +#endif /* TAMP_CR1_TAMP4E */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup RTCEx_Exported_Functions + * @{ + */ + + +/** @addtogroup RTCEx_Exported_Functions_Group1 + * @brief RTC TimeStamp and Tamper functions + * +@verbatim + =============================================================================== + ##### RTC TimeStamp and Tamper functions ##### + =============================================================================== + + [..] This section provides functions allowing to configure TimeStamp feature + +@endverbatim + * @{ + */ + +#ifdef RTC_CR_TSE +/** + * @brief Set TimeStamp. + * @note This API must be called before enabling the TimeStamp feature. + * @param hrtc RTC handle + * @param TimeStampEdge Specifies the pin edge on which the TimeStamp is + * activated. + * This parameter can be one of the following values: + * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the + * rising edge of the related pin. + * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the + * falling edge of the related pin. + * @param RTC_TimeStampPin specifies the RTC TimeStamp Pin. + * This parameter can be one of the following values: + * @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin. + * The RTC TimeStamp Pin is per default PC13, but for reasons of + * compatibility, this parameter is required. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin) +{ + /* Check the parameters */ +#if defined(RTC_CR_TSEDGE) + assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge)); +#endif /* RTC_CR_TSEDGE */ + assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin)); + UNUSED(RTC_TimeStampPin); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Get the RTC_CR register and clear the bits to be configured */ +#if defined(RTC_CR_TSEDGE) + CLEAR_BIT(RTC->CR, (RTC_CR_TSEDGE | RTC_CR_TSE)); +#else + CLEAR_BIT(RTC->CR, RTC_CR_TSE); +#endif /* RTC_CR_TSEDGE */ + + /* Configure the Time Stamp TSEDGE and Enable bits */ + SET_BIT(RTC->CR, (uint32_t)TimeStampEdge | RTC_CR_TSE); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Set TimeStamp with Interrupt. + * @note This API must be called before enabling the TimeStamp feature. + * @param hrtc RTC handle + * @param TimeStampEdge Specifies the pin edge on which the TimeStamp is + * activated. + * This parameter can be one of the following values: + * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the + * rising edge of the related pin. + * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the + * falling edge of the related pin. + * @param RTC_TimeStampPin Specifies the RTC TimeStamp Pin. + * This parameter can be one of the following values: + * @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin. + * The RTC TimeStamp Pin is per default PC13, but for reasons of + * compatibility, this parameter is required. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin) +{ + /* Check the parameters */ +#if defined(RTC_CR_TSEDGE) + assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge)); +#endif /* RTC_CR_TSEDGE */ + assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin)); + UNUSED(RTC_TimeStampPin); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Get the RTC_CR register and clear the bits to be configured */ +#if defined(RTC_CR_TSEDGE) + CLEAR_BIT(RTC->CR, (RTC_CR_TSEDGE | RTC_CR_TSE | RTC_CR_TSIE)); +#else + CLEAR_BIT(RTC->CR, (RTC_CR_TSE | RTC_CR_TSIE)); +#endif /* RTC_CR_TSEDGE */ + + /* Configure the Time Stamp TSEDGE before Enable bit to avoid unwanted TSF setting. */ + SET_BIT(RTC->CR, (uint32_t)TimeStampEdge); + + /* Enable timestamp and IT */ + SET_BIT(RTC->CR, RTC_CR_TSE | RTC_CR_TSIE); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Deactivate TimeStamp. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc) +{ + /* Process Locked */ + __HAL_LOCK(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + + /* In case of interrupt mode is used, the interrupt source must disabled */ +#if defined(RTC_CR_TSEDGE) + CLEAR_BIT(RTC->CR, (RTC_CR_TSEDGE | RTC_CR_TSE | RTC_CR_TSIE)); +#else + CLEAR_BIT(RTC->CR, (RTC_CR_TSE | RTC_CR_TSIE)); +#endif /* RTC_CR_TSEDGE */ + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} +#endif /* RTC_CR_TSE */ + +/** + * @brief Get the RTC TimeStamp value. + * @param hrtc RTC handle + * @param sTimeStamp Pointer to Time structure + * @param sTimeStampDate Pointer to Date structure + * @param Format specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BCD: BCD data format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(const RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, + RTC_DateTypeDef *sTimeStampDate, uint32_t Format) +{ + uint32_t tmptime; + uint32_t tmpdate; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(Format)); + + /* Get the TimeStamp time and date registers values */ + tmptime = READ_BIT(RTC->TSTR, RTC_TR_RESERVED_MASK); + tmpdate = READ_BIT(RTC->TSDR, RTC_DR_RESERVED_MASK); + + /* Fill the Time structure fields with the read parameters */ + sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TSTR_HT | RTC_TSTR_HU)) >> RTC_TSTR_HU_Pos); + sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TSTR_MNT | RTC_TSTR_MNU)) >> RTC_TSTR_MNU_Pos); + sTimeStamp->Seconds = (uint8_t)((tmptime & (RTC_TSTR_ST | RTC_TSTR_SU)) >> RTC_TSTR_SU_Pos); + sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TSTR_PM)) >> RTC_TSTR_PM_Pos); + sTimeStamp->SubSeconds = READ_BIT(RTC->TSSSR, RTC_TSSSR_SS); + + /* Fill the Date structure fields with the read parameters */ + sTimeStampDate->Year = 0U; + sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_TSDR_MT | RTC_TSDR_MU)) >> RTC_TSDR_MU_Pos); + sTimeStampDate->Date = (uint8_t)(tmpdate & (RTC_TSDR_DT | RTC_TSDR_DU)); + sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_TSDR_WDU)) >> RTC_TSDR_WDU_Pos); + + /* Check the input parameters format */ + if (Format == RTC_FORMAT_BIN) + { + /* Convert the TimeStamp structure parameters to Binary format */ + sTimeStamp->Hours = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Hours); + sTimeStamp->Minutes = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Minutes); + sTimeStamp->Seconds = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Seconds); + + /* Convert the DateTimeStamp structure parameters to Binary format */ + sTimeStampDate->Month = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Month); + sTimeStampDate->Date = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Date); + sTimeStampDate->WeekDay = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->WeekDay); + } + + /* Check if TIMESTAMP flag is set */ + if (READ_BIT(RTC->SR, RTC_SR_TSF) != 0U) + { + /* Clear the TIMESTAMP Flags */ + WRITE_REG(RTC->SCR, RTC_SCR_CTSF); + + /* Check if TIMESTAMP OverRun flag is set */ + if (READ_BIT(RTC->SR, RTC_SR_TSOVF) != 0U) + { + /* Clear the TIMESTAMP OverRun Flag */ + WRITE_REG(RTC->SCR, RTC_SCR_CTSOVF); + + return HAL_ERROR; + } + } + + return HAL_OK; +} + +/** + * @brief Handle TimeStamp interrupt request. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTCEx_TimeStampIRQHandler(RTC_HandleTypeDef *hrtc) +{ + /* Get the pending status of the TimeStamp Interrupt */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + if (READ_BIT(RTC->SMISR, RTC_SMISR_TSMF) != 0U) +#else + if (READ_BIT(RTC->MISR, RTC_MISR_TSMF) != 0U) +#endif /* #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call TimeStampEvent registered Callback */ + hrtc->TimeStampEventCallback(hrtc); +#else + HAL_RTCEx_TimeStampEventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + + /* Clearing flags after the Callback because the content of RTC_TSTR and RTC_TSDR are cleared when + TSF bit is reset.*/ + WRITE_REG(RTC->SCR, RTC_SCR_CTSF); + } + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; +} + +/** + * @brief TimeStamp callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_TimeStampEventCallback could be implemented in the user file + */ +} + +/** + * @brief Handle TimeStamp polling request. + * @param hrtc RTC handle + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(const RTC_HandleTypeDef *hrtc, uint32_t Timeout) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + uint32_t tickstart = HAL_GetTick(); + + while (READ_BIT(RTC->SR, RTC_SR_TSF) == 0U) + { + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RTC->SR, RTC_SR_TSF) == 0U) + { + return HAL_TIMEOUT; + } + else + { + break; + } + } + } + } + + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup RTCEx_Exported_Functions_Group2 + * @brief RTC Wake-up functions + * +@verbatim + =============================================================================== + ##### RTC Wake-up functions ##### + =============================================================================== + + [..] This section provides functions allowing to configure Wake-up feature + +@endverbatim + * @{ + */ + +/** + * @brief Set wake up timer. + * @param hrtc RTC handle + * @param WakeUpCounter Wake up counter + * @param WakeUpClock Wake up clock + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock)); + assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Clear WUTE in RTC_CR to disable the wakeup timer */ + CLEAR_BIT(RTC->CR, RTC_CR_WUTE); + + /* Poll WUTWF until it is set in RTC_ICSR to make sure the access to wakeup autoreload + counter and to WUCKSEL[2:0] bits is allowed. This step must be skipped in + calendar initialization mode. */ + if (READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == 0U) + { + tickstart = HAL_GetTick(); + + while (READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == 0U) + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + { + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == 0U) + { + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; + } + else + { + break; + } + } + } + } + + /* Configure the clock source */ + MODIFY_REG(RTC->CR, RTC_CR_WUCKSEL, (uint32_t)WakeUpClock); + + /* Configure the Wakeup Timer counter */ + WRITE_REG(RTC->WUTR, (uint32_t)WakeUpCounter); + + /* Enable the Wakeup Timer */ + SET_BIT(RTC->CR, RTC_CR_WUTE); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Set wake up timer with interrupt. + * @param hrtc RTC handle + * @param WakeUpCounter Wake up counter + * @param WakeUpClock Wake up clock + * @param WakeUpAutoClr Wake up auto clear value (look at WUTOCLR in reference manual) + * - No effect if WakeUpAutoClr is set to zero + * - This feature is meaningful in case of Low power mode to avoid any RTC software execution + * after Wake Up. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock, + uint32_t WakeUpAutoClr) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock)); + assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter)); + /* (0x0000<=WUTOCLR<=WUT) */ + assert_param(WakeUpAutoClr <= WakeUpCounter); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Clear WUTE in RTC_CR to disable the wakeup timer */ + CLEAR_BIT(RTC->CR, RTC_CR_WUTE); + + /* Clear flag Wake-Up */ + WRITE_REG(RTC->SCR, RTC_SCR_CWUTF); + + /* Poll WUTWF until it is set in RTC_ICSR to make sure the access to wakeup autoreload + counter and to WUCKSEL[2:0] bits is allowed. This step must be skipped in + calendar initialization mode. */ + if (READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == 0U) + { + tickstart = HAL_GetTick(); + while (READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == 0U) + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + { + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == 0U) + { + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; + } + else + { + break; + } + } + } + } + + /* Configure the Wakeup Timer counter and auto clear value */ + WRITE_REG(RTC->WUTR, (uint32_t)(WakeUpCounter | (WakeUpAutoClr << RTC_WUTR_WUTOCLR_Pos))); + + /* Configure the clock source */ + MODIFY_REG(RTC->CR, RTC_CR_WUCKSEL, (uint32_t)WakeUpClock); + + /* Configure the Interrupt in the RTC_CR register and Enable the Wakeup Timer*/ + SET_BIT(RTC->CR, (RTC_CR_WUTIE | RTC_CR_WUTE)); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Deactivate wake up timer counter. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc) +{ + /* Process Locked */ + __HAL_LOCK(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the Wakeup Timer */ + /* In case of interrupt mode is used, the interrupt source must disabled */ + CLEAR_BIT(RTC->CR, (RTC_CR_WUTE | RTC_CR_WUTIE)); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Get wake up timer counter. + * @param hrtc RTC handle + * @retval Counter value + */ +uint32_t HAL_RTCEx_GetWakeUpTimer(const RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* Get the counter value */ + return (uint32_t)(READ_BIT(RTC->WUTR, RTC_WUTR_WUT)); +} + +/** + * @brief Handle Wake Up Timer interrupt request. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc) +{ + /* Get the pending status of the Wake-Up Timer Interrupt */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + if (READ_BIT(RTC->SMISR, RTC_SMISR_WUTMF) != 0U) +#else + if (READ_BIT(RTC->MISR, RTC_MISR_WUTMF) != 0U) +#endif /* #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + { + /* Immediately clear flags */ + WRITE_REG(RTC->SCR, RTC_SCR_CWUTF); +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call wake up timer registered Callback */ + hrtc->WakeUpTimerEventCallback(hrtc); +#else + HAL_RTCEx_WakeUpTimerEventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + } + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; +} + +/** + * @brief Wake Up Timer callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_WakeUpTimerEventCallback could be implemented in the user file + */ +} + +/** + * @brief Handle Wake Up Timer Polling. + * @param hrtc RTC handle + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(const RTC_HandleTypeDef *hrtc, uint32_t Timeout) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + uint32_t tickstart = HAL_GetTick(); + + while (READ_BIT(RTC->SR, RTC_SR_WUTF) == 0U) + { + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RTC->SR, RTC_SR_WUTF) == 0U) + { + return HAL_TIMEOUT; + } + else + { + break; + } + } + } + } + + /* Clear the WAKEUPTIMER Flag */ + WRITE_REG(RTC->SCR, RTC_SCR_CWUTF); + + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup RTCEx_Exported_Functions_Group3 + * @brief Extended Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Extended Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Write a data in a specified RTC Backup data register + (+) Read a data in a specified RTC Backup data register + (+) Set the Coarse calibration parameters. + (+) Deactivate the Coarse calibration parameters + (+) Set the Smooth calibration parameters. + (+) Set Low Power calibration parameter. + (+) Configure the Synchronization Shift Control Settings. + (+) Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). + (+) Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). + (+) Enable the RTC reference clock detection. + (+) Disable the RTC reference clock detection. + (+) Enable the Bypass Shadow feature. + (+) Disable the Bypass Shadow feature. + +@endverbatim + * @{ + */ + +/** + * @brief Set the Smooth calibration parameters. + * @note To deactivate the smooth calibration, the field SmoothCalibPlusPulses + * must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field + * SmoothCalibMinusPulsesValue must be equal to 0. + * @param hrtc RTC handle + * @param SmoothCalibPeriod Select the Smooth Calibration Period. + * This parameter can be one of the following values : + * @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s. + * @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration period is 16s. + * @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibration period is 8s. + * @param SmoothCalibPlusPulses Select to Set or reset the CALP bit. + * This parameter can be one of the following values: + * @arg RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK pulse every 2*11 pulses. + * @arg RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added. + * @param SmoothCalibMinusPulsesValue Select the value of CALM[8:0] bits. + * This parameter can be one any value from 0 to 0x000001FF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, + uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(SmoothCalibPeriod)); + assert_param(IS_RTC_SMOOTH_CALIB_PLUS(SmoothCalibPlusPulses)); + assert_param(IS_RTC_SMOOTH_CALIB_MINUS(SmoothCalibMinusPulsesValue)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + + tickstart = HAL_GetTick(); + + /* check if a calibration is pending */ + while (READ_BIT(RTC->ICSR, RTC_ICSR_RECALPF) != 0U) + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + { + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RTC->ICSR, RTC_ICSR_RECALPF) != 0U) + { + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; + } + else + { + break; + } + } + } + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Configure the Smooth calibration settings */ + MODIFY_REG(RTC->CALR, (RTC_CALR_CALP | RTC_CALR_CALW8 | RTC_CALR_CALW16 | RTC_CALR_CALM), + (uint32_t)(SmoothCalibPeriod | SmoothCalibPlusPulses | SmoothCalibMinusPulsesValue)); + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Select the low power Calibration mode. + * @param hrtc: RTC handle + * @param LowPowerCalib: Low power Calibration mode. + * This parameter can be one of the following values : + * @arg RTC_LPCAL_SET: Low power mode. + * @arg RTC_LPCAL_RESET: High consumption mode. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetLowPowerCalib(RTC_HandleTypeDef *hrtc, uint32_t LowPowerCalib) +{ + /* Check the parameters */ + assert_param(IS_RTC_LOW_POWER_CALIB(LowPowerCalib)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Configure the Smooth calibration settings */ + MODIFY_REG(RTC->CALR, RTC_CALR_LPCAL, LowPowerCalib); + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Configure the Synchronization Shift Control Settings. + * @note When REFCKON is set, firmware must not write to Shift control register. + * @param hrtc RTC handle + * @param ShiftAdd1S Select to add or not 1 second to the time calendar. + * This parameter can be one of the following values: + * @arg RTC_SHIFTADD1S_SET: Add one second to the clock calendar. + * @arg RTC_SHIFTADD1S_RESET: No effect. + * @param ShiftSubFS Select the number of Second Fractions to substitute. + * This parameter can be one any value from 0 to 0x7FFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_RTC_SHIFT_ADD1S(ShiftAdd1S)); + assert_param(IS_RTC_SHIFT_SUBFS(ShiftSubFS)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + + tickstart = HAL_GetTick(); + + /* Wait until the shift is completed */ + while (READ_BIT(RTC->ICSR, RTC_ICSR_SHPF) != 0U) + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + { + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RTC->ICSR, RTC_ICSR_SHPF) != 0U) + { + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; + } + else + { + break; + } + } + } + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + +#if defined(RTC_CR_REFCKON) + /* Check if the reference clock detection is disabled */ + if (READ_BIT(RTC->CR, RTC_CR_REFCKON) == 0U) + { +#endif /* RTC_CR_REFCKON */ + /* Configure the Shift settings */ + MODIFY_REG(RTC->SHIFTR, RTC_SHIFTR_SUBFS, (uint32_t)(ShiftSubFS) | (uint32_t)(ShiftAdd1S)); + + /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ + if (READ_BIT(RTC->CR, RTC_CR_BYPSHAD) == 0U) + { + if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_ERROR; + } + } +#if defined(RTC_CR_REFCKON) + } + else + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_ERROR; + } +#endif /* RTC_CR_REFCKON */ + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +#if defined(RTC_CR_COSEL) +/** + * @brief Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). + * @param hrtc RTC handle + * @param CalibOutput Select the Calibration output Selection . + * This parameter can be one of the following values: + * @arg RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz. + * @arg RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput) +{ + /* Check the parameters */ + assert_param(IS_RTC_CALIB_OUTPUT(CalibOutput)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Configure the RTC_CR register */ + MODIFY_REG(RTC->CR, RTC_CR_COSEL, CalibOutput); + + /* Enable calibration output */ + SET_BIT(RTC->CR, RTC_CR_COE); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc) +{ + /* Process Locked */ + __HAL_LOCK(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable calibration output */ + CLEAR_BIT(RTC->CR, RTC_CR_COE); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} +#endif /* RTC_CR_COSEL */ + +#if defined(RTC_CR_REFCKON) +/** + * @brief Enable the RTC reference clock detection. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc) +{ + HAL_StatusTypeDef status; + + /* Process Locked */ + __HAL_LOCK(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); + if (status == HAL_OK) + { + /* Enable clockref detection */ + SET_BIT(RTC->CR, RTC_CR_REFCKON); + + /* Exit Initialization mode */ + status = RTC_ExitInitMode(hrtc); + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + if (status == HAL_OK) + { + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return status; +} + +/** + * @brief Disable the RTC reference clock detection. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc) +{ + HAL_StatusTypeDef status; + + /* Process Locked */ + __HAL_LOCK(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); + if (status == HAL_OK) + { + /* Disable clockref detection */ + CLEAR_BIT(RTC->CR, RTC_CR_REFCKON); + + /* Exit Initialization mode */ + status = RTC_ExitInitMode(hrtc); + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + if (status == HAL_OK) + { + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return status; +} +#endif /* RTC_CR_REFCKON */ + +/** + * @brief Enable the Bypass Shadow feature. + * @note When the Bypass Shadow is enabled the calendar value are taken + * directly from the Calendar counter. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc) +{ + /* Process Locked */ + __HAL_LOCK(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Set the BYPSHAD bit */ + SET_BIT(RTC->CR, RTC_CR_BYPSHAD); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Disable the Bypass Shadow feature. + * @note When the Bypass Shadow is enabled the calendar value are taken + * directly from the Calendar counter. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc) +{ + /* Process Locked */ + __HAL_LOCK(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Reset the BYPSHAD bit */ + CLEAR_BIT(RTC->CR, RTC_CR_BYPSHAD); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Increment Monotonic counter. + * @param hrtc RTC handle + * @param Instance Monotonic counter Instance + * This parameter can be one of the following values : + * @arg RTC_MONOTONIC_COUNTER_1 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterIncrement(const RTC_HandleTypeDef *hrtc, uint32_t Instance) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + UNUSED(Instance); + + /* This register is read-only only and is incremented by one when a write access is done to this + register. This register cannot roll-over and is frozen when reaching the maximum value. */ + CLEAR_REG(TAMP->COUNT1R); + + return HAL_OK; +} + +/** + * @brief Monotonic counter. + * @param hrtc RTC handle + * @param Instance Monotonic counter Instance + * This parameter can be one of the following values : + * @arg RTC_MONOTONIC_COUNTER_1 + * @param pValue Pointer to the counter monotonic counter value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterGet(const RTC_HandleTypeDef *hrtc, uint32_t Instance, uint32_t *pValue) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + UNUSED(Instance); + + /* This register is read-only only and is incremented by one when a write access is done to this + register. This register cannot roll-over and is frozen when reaching the maximum value. */ + *pValue = READ_REG(TAMP->COUNT1R); + + return HAL_OK; +} + +/** + * @brief Set SSR Underflow detection with Interrupt. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetSSRU_IT(RTC_HandleTypeDef *hrtc) +{ + /* Process Locked */ + __HAL_LOCK(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Enable IT SSRU */ + __HAL_RTC_SSRU_ENABLE_IT(hrtc, RTC_IT_SSRU); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Deactivate SSR Underflow. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_DeactivateSSRU(RTC_HandleTypeDef *hrtc) +{ + /* Process Locked */ + __HAL_LOCK(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + + /* In case of interrupt mode is used, the interrupt source must disabled */ + __HAL_RTC_SSRU_DISABLE_IT(hrtc, RTC_IT_SSRU); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; +} + +/** + * @brief Handle SSR underflow interrupt request. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTCEx_SSRUIRQHandler(RTC_HandleTypeDef *hrtc) +{ + /* Get the pending status of the SSR Underflow Interrupt */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + if (READ_BIT(RTC->SMISR, RTC_SMISR_SSRUMF) != 0U) +#else + if (READ_BIT(RTC->MISR, RTC_MISR_SSRUMF) != 0U) +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + { + /* Immediately clear SSR underflow flag */ + WRITE_REG(RTC->SCR, RTC_SCR_CSSRUF); + + /* SSRU callback */ +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call SSRUEvent registered Callback */ + hrtc->SSRUEventCallback(hrtc); +#else + HAL_RTCEx_SSRUEventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + + } + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; +} + +/** + * @brief SSR underflow callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_SSRUEventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_SSRUEventCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @addtogroup RTCEx_Exported_Functions_Group4 + * @brief Extended features functions + * +@verbatim + =============================================================================== + ##### Extended features functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) RTC Alarm B callback + (+) RTC Poll for Alarm B request + +@endverbatim + * @{ + */ + +/** + * @brief Alarm B callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_AlarmBEventCallback could be implemented in the user file + */ +} + +/** + * @brief Handle Alarm B Polling request. + * @param hrtc RTC handle + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(const RTC_HandleTypeDef *hrtc, uint32_t Timeout) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + uint32_t tickstart = HAL_GetTick(); + + while (READ_BIT(RTC->SR, RTC_SR_ALRBF) == 0U) + { + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RTC->SR, RTC_SR_ALRBF) == 0U) + { + return HAL_TIMEOUT; + } + else + { + break; + } + } + } + } + + /* Clear the Alarm Flag */ + WRITE_REG(RTC->SCR, RTC_SCR_CALRBF); + + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup RTCEx_Exported_Functions_Group5 + * @brief Extended RTC Tamper functions + * +@verbatim + ============================================================================== + ##### Tamper functions ##### + ============================================================================== + [..] + (+) Before calling any tamper or internal tamper function, you have to call first + HAL_RTC_Init() function. + (+) In that one you can select to output tamper event on RTC pin. + [..] + (+) Enable the Tamper and configure the Tamper filter count, trigger Edge + or Level according to the Tamper filter (if equal to 0 Edge else Level) + value, sampling frequency, NoErase, MaskFlag, precharge or discharge and + Pull-UP, timestamp using the HAL_RTCEx_SetTamper() function. + You can configure Tamper with interrupt mode using HAL_RTCEx_SetTamper_IT() function. + (+) The default configuration of the Tamper erases the backup registers. To avoid + erase, enable the NoErase field on the TAMP_TAMPCR register. + [..] + (+) Enable Internal Tamper and configure it with interrupt, timestamp using + the HAL_RTCEx_SetInternalTamper() function. + +@endverbatim + * @{ + */ + + +/** + * @brief Set Tamper + * @param hrtc RTC handle + * @param sTamper Pointer to Tamper Structure. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetTamper(const RTC_HandleTypeDef *hrtc, const RTC_TamperTypeDef *sTamper) +{ + uint32_t tmpreg; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* Check the parameters */ + assert_param(IS_RTC_TAMPER(sTamper->Tamper)); + assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger)); + assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase)); + assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag)); + assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection)); + /* Mask flag only supported by TAMPER 1, 2 and 3 */ + assert_param(!((sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE) && (sTamper->Tamper > RTC_TAMPER_3))); + assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter)); + assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency)); + assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration)); + assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp)); + /* Trigger and Filter have exclusive configurations */ + assert_param(((sTamper->Filter != RTC_TAMPERFILTER_DISABLE) && + ((sTamper->Trigger == RTC_TAMPERTRIGGER_LOWLEVEL) || + (sTamper->Trigger == RTC_TAMPERTRIGGER_HIGHLEVEL))) || + ((sTamper->Filter == RTC_TAMPERFILTER_DISABLE) && + ((sTamper->Trigger == RTC_TAMPERTRIGGER_RISINGEDGE) || + (sTamper->Trigger == RTC_TAMPERTRIGGER_FALLINGEDGE)))); + + /* Configuration register 2 */ + tmpreg = READ_REG(TAMP->CR2); + tmpreg &= ~((sTamper->Tamper << TAMP_CR2_TAMP1TRG_Pos) | (sTamper->Tamper << TAMP_CR2_TAMP1MSK_Pos) | + (sTamper->Tamper << TAMP_CR2_TAMP1POM_Pos)); + + if ((sTamper->Trigger == RTC_TAMPERTRIGGER_HIGHLEVEL) || (sTamper->Trigger == RTC_TAMPERTRIGGER_FALLINGEDGE)) + { + tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1TRG_Pos); + } + + if (sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE) + { + tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1MSK_Pos); + } + + if (sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE) + { + tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1POM_Pos); + } + WRITE_REG(TAMP->CR2, tmpreg); + + /* Filter control register */ + WRITE_REG(TAMP->FLTCR, sTamper->Filter | sTamper->SamplingFrequency | sTamper->PrechargeDuration | + sTamper->TamperPullUp); + + /* Timestamp on tamper */ + if (READ_BIT(RTC->CR, RTC_CR_TAMPTS) != sTamper->TimeStampOnTamperDetection) + { + MODIFY_REG(RTC->CR, RTC_CR_TAMPTS, sTamper->TimeStampOnTamperDetection); + } + + /* Control register 1 */ + SET_BIT(TAMP->CR1, sTamper->Tamper); + + return HAL_OK; +} + + +/** + * @brief Set Tamper in IT mode + * @param hrtc RTC handle + * @param sTamper Pointer to Tamper Structure. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(const RTC_HandleTypeDef *hrtc, const RTC_TamperTypeDef *sTamper) +{ + uint32_t tmpreg; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* Check the parameters */ + assert_param(IS_RTC_TAMPER(sTamper->Tamper)); + assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger)); + assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase)); + assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection)); + /* The interrupt must not be enabled when TAMPxMSK is set. */ + assert_param(sTamper->MaskFlag == RTC_TAMPERMASK_FLAG_DISABLE); + assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter)); + assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency)); + assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration)); + assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp)); + /* Trigger and Filter have exclusive configurations */ + assert_param(((sTamper->Filter != RTC_TAMPERFILTER_DISABLE) && + ((sTamper->Trigger == RTC_TAMPERTRIGGER_LOWLEVEL) || + (sTamper->Trigger == RTC_TAMPERTRIGGER_HIGHLEVEL))) || + ((sTamper->Filter == RTC_TAMPERFILTER_DISABLE) && + ((sTamper->Trigger == RTC_TAMPERTRIGGER_RISINGEDGE) || + (sTamper->Trigger == RTC_TAMPERTRIGGER_FALLINGEDGE)))); + + /* Configuration register 2 */ + tmpreg = READ_REG(TAMP->CR2); + tmpreg &= ~((sTamper->Tamper << TAMP_CR2_TAMP1TRG_Pos) | (sTamper->Tamper << TAMP_CR2_TAMP1MSK_Pos) | + (sTamper->Tamper << TAMP_CR2_TAMP1POM_Pos)); + + if ((sTamper->Trigger == RTC_TAMPERTRIGGER_HIGHLEVEL) || (sTamper->Trigger == RTC_TAMPERTRIGGER_FALLINGEDGE)) + { + tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1TRG_Pos); + } + + if (sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE) + { + tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1POM_Pos); + } + WRITE_REG(TAMP->CR2, tmpreg); + + /* Filter control register */ + WRITE_REG(TAMP->FLTCR, sTamper->Filter | sTamper->SamplingFrequency | sTamper->PrechargeDuration | + sTamper->TamperPullUp); + + /* Timestamp on tamper */ + if (READ_BIT(RTC->CR, RTC_CR_TAMPTS) != sTamper->TimeStampOnTamperDetection) + { + MODIFY_REG(RTC->CR, RTC_CR_TAMPTS, sTamper->TimeStampOnTamperDetection); + } + + /* Interrupt enable register */ + SET_BIT(TAMP->IER, sTamper->Tamper); + + /* Control register 1 */ + SET_BIT(TAMP->CR1, sTamper->Tamper); + + return HAL_OK; +} + +/** + * @brief Deactivate Tamper. + * @param hrtc RTC handle + * @param Tamper Selected tamper pin. + * This parameter can be a combination of the following values: + * @arg RTC_TAMPER_1 + * @arg RTC_TAMPER_2 + * @arg RTC_TAMPER_3 + * @arg RTC_TAMPER_4 + * @arg RTC_TAMPER_5 + * @arg RTC_TAMPER_6 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(const RTC_HandleTypeDef *hrtc, uint32_t Tamper) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + assert_param(IS_RTC_TAMPER(Tamper)); + + /* Disable the selected Tamper pin */ + CLEAR_BIT(TAMP->CR1, Tamper); + + /* Clear tamper interrupt and event flags (WO register) */ + WRITE_REG(TAMP->SCR, Tamper); + + /* Clear tamper mask/noerase/trigger configuration */ + CLEAR_BIT(TAMP->CR2, (Tamper << TAMP_CR2_TAMP1TRG_Pos) | (Tamper << TAMP_CR2_TAMP1MSK_Pos) | \ + (Tamper << TAMP_CR2_TAMP1POM_Pos)); + + /* Clear tamper interrupt mode configuration */ + CLEAR_BIT(TAMP->IER, Tamper); + + return HAL_OK; +} + +/** + * @brief Set all active Tampers at the same time. + * @param hrtc RTC handle + * @param sAllTamper Pointer to active Tamper Structure. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetActiveTampers(RTC_HandleTypeDef *hrtc, const RTC_ActiveTampersTypeDef *sAllTamper) +{ + uint32_t tmp_ier; + uint32_t tmp_cr1; + uint32_t tmp_cr2; + uint32_t tmp_atcr1; + uint32_t tmp_atcr2; + uint32_t tmp_cr; + uint32_t i; + uint32_t tickstart; + +#ifdef USE_FULL_ASSERT + for (i = 0; i < RTC_TAMP_NB; i++) + { + assert_param(IS_RTC_TAMPER_ERASE_MODE(sAllTamper->TampInput[i].NoErase)); + assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sAllTamper->TampInput[i].MaskFlag)); + /* Mask flag only supported by TAMPER 1, 2 and 3 */ + assert_param(!((sAllTamper->TampInput[i].MaskFlag == RTC_TAMPERMASK_FLAG_ENABLE) && + (i >= RTC_TAMPER_MASKABLE_NB))); + } + assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sAllTamper->TimeStampOnTamperDetection)); + assert_param(IS_RTC_ATAMPER_FILTER(sAllTamper->ActiveFilter)); + assert_param(IS_RTC_ATAMPER_OUTPUT_CHANGE_PERIOD(sAllTamper->ActiveOutputChangePeriod)); + assert_param(IS_RTC_ATAMPER_ASYNCPRES_RTCCLK(sAllTamper->ActiveAsyncPrescaler)); +#endif /* USE_FULL_ASSERT */ + + /* Active Tampers must not be already enabled */ + if (READ_BIT(TAMP->ATOR, TAMP_ATOR_INITS) != 0U) + { + /* Disable all actives tampers with HAL_RTCEx_DeactivateActiveTampers. + No need to check return value because it returns always HAL_OK */ + (void) HAL_RTCEx_DeactivateActiveTampers(hrtc); + } + + /* Set TimeStamp on tamper detection */ + tmp_cr = READ_REG(RTC->CR); + if ((tmp_cr & RTC_CR_TAMPTS) != (sAllTamper->TimeStampOnTamperDetection)) + { + MODIFY_REG(RTC->CR, RTC_CR_TAMPTS, sAllTamper->TimeStampOnTamperDetection); + } + + tmp_cr1 = READ_REG(TAMP->CR1); + tmp_cr2 = READ_REG(TAMP->CR2); + tmp_atcr2 = 0U; + tmp_ier = READ_REG(TAMP->IER); + + /* Set common parameters */ + tmp_atcr1 = (sAllTamper->ActiveFilter | (sAllTamper->ActiveOutputChangePeriod << TAMP_ATCR1_ATPER_Pos) | + sAllTamper->ActiveAsyncPrescaler); + + /* Set specific parameters for each active tamper inputs if enable */ + for (i = 0; i < RTC_TAMP_NB; i++) + { + if (sAllTamper->TampInput[i].Enable != RTC_ATAMP_DISABLE) + { + tmp_cr1 |= (TAMP_CR1_TAMP1E << i); + tmp_atcr1 |= (TAMP_ATCR1_TAMP1AM << i); + + if (sAllTamper->TampInput[i].Interrupt != RTC_ATAMP_INTERRUPT_DISABLE) + { + /* Interrupt enable register */ + tmp_ier |= (TAMP_IER_TAMP1IE << i); + } + + if (sAllTamper->TampInput[i].MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE) + { + tmp_cr2 |= (TAMP_CR2_TAMP1MSK << i); + } + + if (sAllTamper->TampInput[i].NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE) + { + tmp_cr2 |= (TAMP_CR2_TAMP1POM << i); + } + + /* Configure ATOSELx[] in case of output sharing */ + tmp_atcr2 |= sAllTamper->TampInput[i].Output << ((3U * i) + TAMP_ATCR2_ATOSEL1_Pos); + + if (i != sAllTamper->TampInput[i].Output) + { + tmp_atcr1 |= TAMP_ATCR1_ATOSHARE; + } + } + } + + WRITE_REG(TAMP->IER, tmp_ier); + WRITE_REG(TAMP->ATCR1, tmp_atcr1); + WRITE_REG(TAMP->ATCR2, tmp_atcr2); + WRITE_REG(TAMP->CR2, tmp_cr2); + WRITE_REG(TAMP->CR1, tmp_cr1); + + /* Write seed */ + for (i = 0; i < RTC_ATAMP_SEED_NB_UINT32; i++) + { + WRITE_REG(TAMP->ATSEEDR, sAllTamper->Seed[i]); + } + + /* Wait till RTC SEEDF flag is cleared and if Time out is reached exit */ + tickstart = HAL_GetTick(); + while (READ_BIT(TAMP->ATOR, TAMP_ATOR_SEEDF) != 0U) + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + { + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(TAMP->ATOR, TAMP_ATOR_SEEDF) != 0U) + { + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + return HAL_TIMEOUT; + } + else + { + break; + } + } + } + + return HAL_OK; +} + +/** + * @brief Write a new seed. Active tamper must be enabled. + * @param hrtc RTC handle + * @param pSeed Pointer to active tamper seed values. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetActiveSeed(RTC_HandleTypeDef *hrtc, const uint32_t *pSeed) +{ + uint32_t i; + uint32_t tickstart; + + /* Active Tampers must be enabled */ + if (READ_BIT(TAMP->ATOR, TAMP_ATOR_INITS) == 0U) + { + return HAL_ERROR; + } + + for (i = 0; i < RTC_ATAMP_SEED_NB_UINT32; i++) + { + WRITE_REG(TAMP->ATSEEDR, pSeed[i]); + } + + /* Wait till RTC SEEDF flag is cleared and if Time out is reached exit */ + tickstart = HAL_GetTick(); + while (READ_BIT(TAMP->ATOR, TAMP_ATOR_SEEDF) != 0U) + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + { + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(TAMP->ATOR, TAMP_ATOR_SEEDF) != 0U) + { + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + return HAL_TIMEOUT; + } + else + { + break; + } + } + } + + return HAL_OK; +} + +#if defined(TAMP_SECCFGR_BHKLOCK) +/** + * @brief Lock the Boot hardware Key + * @param hrtc RTC handle + * @note The backup registers from TAMP_BKP0R to TAMP_BKP7R cannot be accessed neither in + * read nor in write (they are read as 0 and write ignore). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_LockBootHardwareKey(const RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + WRITE_REG(TAMP->SECCFGR, TAMP_SECCFGR_BHKLOCK); + + return HAL_OK; +} +#endif /* TAMP_SECCFGR_BHKLOCK */ + +/** + * @brief Deactivate all Active Tampers at the same time. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_DeactivateActiveTampers(const RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* Get Active tampers */ + uint32_t atamp_mask = READ_BIT(TAMP->ATCR1, TAMP_ALL); + + /* Disable all actives tampers but not passives tampers */ + CLEAR_BIT(TAMP->CR1, atamp_mask); + + /* Clear tamper interrupt and event flags (WO register) of all actives tampers but not passives tampers */ + WRITE_REG(TAMP->SCR, atamp_mask); + + /* Disable no erase and mask */ + CLEAR_BIT(TAMP->CR2, (atamp_mask | ((atamp_mask & (TAMP_ATCR1_TAMP1AM | TAMP_ATCR1_TAMP2AM | TAMP_ATCR1_TAMP3AM)) << + TAMP_CR2_TAMP1MSK_Pos))); + + /* Clear all active tampers interrupt mode configuration but not passives tampers */ + CLEAR_BIT(TAMP->IER, atamp_mask); + + /* Set reset value for active tamper control register 1 */ + WRITE_REG(TAMP->ATCR1, TAMP_ATCR1_ATCKSEL); + + /* Set reset value for active tamper control register 2 */ + CLEAR_REG(TAMP->ATCR2); + + return HAL_OK; +} + + +/** + * @brief Tamper event polling. + * @param hrtc RTC handle + * @param Tamper Selected tamper pin. + * This parameter can be a combination of the following values: + * @arg RTC_TAMPER_1 + * @arg RTC_TAMPER_2 + * @arg RTC_TAMPER_3 + * @arg RTC_TAMPER_4 + * @arg RTC_TAMPER_5 + * @arg RTC_TAMPER_6 + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_PollForTamperEvent(const RTC_HandleTypeDef *hrtc, uint32_t Tamper, uint32_t Timeout) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + assert_param(IS_RTC_TAMPER(Tamper)); + + uint32_t tickstart = HAL_GetTick(); + + /* Get the status of the Interrupt */ + while (READ_BIT(TAMP->SR, Tamper) != Tamper) + { + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(TAMP->SR, Tamper) != Tamper) + { + return HAL_TIMEOUT; + } + else + { + break; + } + } + } + } + + /* Clear the Tamper Flag */ + WRITE_REG(TAMP->SCR, Tamper); + + return HAL_OK; +} + + +/** + * @brief Set Internal Tamper + * @param hrtc RTC handle + * @param sIntTamper Pointer to Internal Tamper Structure. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper(const RTC_HandleTypeDef *hrtc, + const RTC_InternalTamperTypeDef *sIntTamper) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* Check the parameters */ + assert_param(IS_RTC_INTERNAL_TAMPER(sIntTamper->IntTamper)); + assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sIntTamper->TimeStampOnTamperDetection)); + assert_param(IS_RTC_TAMPER_ERASE_MODE(sIntTamper->NoErase)); + + /* Timestamp enable on internal tamper */ + if (READ_BIT(RTC->CR, RTC_CR_TAMPTS) != sIntTamper->TimeStampOnTamperDetection) + { + MODIFY_REG(RTC->CR, RTC_CR_TAMPTS, sIntTamper->TimeStampOnTamperDetection); + } + + /* No Erase Backup register enable for Internal Tamper */ + if (sIntTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE) + { + SET_BIT(TAMP->CR3, (sIntTamper->IntTamper >> (TAMP_CR1_ITAMP3E_Pos - TAMP_CR3_ITAMP3POM_Pos))); + } + else + { + CLEAR_BIT(TAMP->CR3, (sIntTamper->IntTamper >> (TAMP_CR1_ITAMP3E_Pos - TAMP_CR3_ITAMP3POM_Pos))); + } + + /* Enable Internal Tamper */ + SET_BIT(TAMP->CR1, sIntTamper->IntTamper); + + return HAL_OK; +} + + +/** + * @brief Set Internal Tamper in interrupt mode + * @param hrtc RTC handle + * @param sIntTamper Pointer to Internal Tamper Structure. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper_IT(const RTC_HandleTypeDef *hrtc, + const RTC_InternalTamperTypeDef *sIntTamper) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* Check the parameters */ + assert_param(IS_RTC_INTERNAL_TAMPER(sIntTamper->IntTamper)); + assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sIntTamper->TimeStampOnTamperDetection)); + assert_param(IS_RTC_TAMPER_ERASE_MODE(sIntTamper->NoErase)); + + /* Timestamp enable on internal tamper */ + if (READ_BIT(RTC->CR, RTC_CR_TAMPTS) != sIntTamper->TimeStampOnTamperDetection) + { + MODIFY_REG(RTC->CR, RTC_CR_TAMPTS, sIntTamper->TimeStampOnTamperDetection); + } + + /* Interrupt enable register */ + SET_BIT(TAMP->IER, sIntTamper->IntTamper); + + /* No Erase Backup register enable for Internal Tamper */ + if (sIntTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE) + { + SET_BIT(TAMP->CR3, (sIntTamper->IntTamper >> (TAMP_CR1_ITAMP3E_Pos - TAMP_CR3_ITAMP3POM_Pos))); + } + else + { + CLEAR_BIT(TAMP->CR3, (sIntTamper->IntTamper >> (TAMP_CR1_ITAMP3E_Pos - TAMP_CR3_ITAMP3POM_Pos))); + } + + /* Enable Internal Tamper */ + SET_BIT(TAMP->CR1, sIntTamper->IntTamper); + + return HAL_OK; +} + +/** + * @brief Deactivate Internal Tamper. + * @param hrtc RTC handle + * @param IntTamper Selected internal tamper event. + * This parameter can be any combination of existing internal tampers. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTamper(const RTC_HandleTypeDef *hrtc, uint32_t IntTamper) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + assert_param(IS_RTC_INTERNAL_TAMPER(IntTamper)); + + /* Disable the selected Tamper pin */ + CLEAR_BIT(TAMP->CR1, IntTamper); + + /* Clear internal tamper interrupt mode configuration */ + CLEAR_BIT(TAMP->IER, IntTamper); + + /* Clear internal tamper interrupt */ + WRITE_REG(TAMP->SCR, IntTamper); + + return HAL_OK; +} + +/** + * @brief Internal Tamper event polling. + * @param hrtc RTC handle + * @param IntTamper selected tamper. + * This parameter can be any combination of existing internal tampers. + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_PollForInternalTamperEvent(const RTC_HandleTypeDef *hrtc, uint32_t IntTamper, + uint32_t Timeout) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + assert_param(IS_RTC_INTERNAL_TAMPER(IntTamper)); + + uint32_t tickstart = HAL_GetTick(); + + /* Get the status of the Interrupt */ + while (READ_BIT(TAMP->SR, IntTamper) != IntTamper) + { + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(TAMP->SR, IntTamper) != IntTamper) + { + return HAL_TIMEOUT; + } + else + { + break; + } + } + } + } + + /* Clear the Tamper Flag */ + WRITE_REG(TAMP->SCR, IntTamper); + + return HAL_OK; +} + +/** + * @brief Handle Tamper interrupt request. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTCEx_TamperIRQHandler(RTC_HandleTypeDef *hrtc) +{ + /* Get the pending status of the Tampers Interrupt */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + uint32_t tmp = READ_REG(TAMP->SMISR); +#else + uint32_t tmp = READ_REG(TAMP->MISR); +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + /* Check Tamper1 status */ + if ((tmp & RTC_TAMPER_1) == RTC_TAMPER_1) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Tamper 1 Event registered secure Callback */ + hrtc->Tamper1EventCallback(hrtc); +#else + /* Tamper1 secure callback */ + HAL_RTCEx_Tamper1EventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + } + + /* Check Tamper2 status */ + if ((tmp & RTC_TAMPER_2) == RTC_TAMPER_2) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Tamper 2 Event registered secure Callback */ + hrtc->Tamper2EventCallback(hrtc); +#else + /* Tamper2 secure callback */ + HAL_RTCEx_Tamper2EventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + } + + /* Check Tamper3 status */ + if ((tmp & RTC_TAMPER_3) == RTC_TAMPER_3) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Tamper 3 Event registered secure Callback */ + hrtc->Tamper3EventCallback(hrtc); +#else + /* Tamper3 secure callback */ + HAL_RTCEx_Tamper3EventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + } + +#ifdef RTC_TAMPER_4 + /* Check Tamper4 status */ + if ((tmp & RTC_TAMPER_4) == RTC_TAMPER_4) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Tamper 4 Event registered secure Callback */ + hrtc->Tamper4EventCallback(hrtc); +#else + /* Tamper4 secure callback */ + HAL_RTCEx_Tamper4EventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + } + + /* Check Tamper5 status */ + if ((tmp & RTC_TAMPER_5) == RTC_TAMPER_5) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Tamper 5 Event registered secure Callback */ + hrtc->Tamper5EventCallback(hrtc); +#else + /* Tamper5 secure callback */ + HAL_RTCEx_Tamper5EventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + } + + /* Check Tamper6 status */ + if ((tmp & RTC_TAMPER_6) == RTC_TAMPER_6) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Tamper 6 Event registered secure Callback */ + hrtc->Tamper6EventCallback(hrtc); +#else + /* Tamper6 secure callback */ + HAL_RTCEx_Tamper6EventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + } +#endif /* RTC_TAMPER_4 */ + + /* Check Internal Tamper3 status */ + if ((tmp & RTC_INT_TAMPER_3) == RTC_INT_TAMPER_3) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Internal Tamper 3 Event registered secure Callback */ + hrtc->InternalTamper3EventCallback(hrtc); +#else + /* Internal Tamper3 secure callback */ + HAL_RTCEx_InternalTamper3EventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + } + + /* Check Internal Tamper5 status */ + if ((tmp & RTC_INT_TAMPER_5) == RTC_INT_TAMPER_5) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Internal Tamper 5 Event registered secure Callback */ + hrtc->InternalTamper5EventCallback(hrtc); +#else + /* Internal Tamper5 secure callback */ + HAL_RTCEx_InternalTamper5EventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + } + + /* Check Internal Tamper6 status */ + if ((tmp & RTC_INT_TAMPER_6) == RTC_INT_TAMPER_6) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Internal Tamper 6 Event registered secure Callback */ + hrtc->InternalTamper6EventCallback(hrtc); +#else + /* Internal Tamper6 secure callback */ + HAL_RTCEx_InternalTamper6EventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + } + + /* Check Internal Tamper7 status */ + if ((tmp & RTC_INT_TAMPER_7) == RTC_INT_TAMPER_7) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Internal Tamper 7 Event registered secure Callback */ + hrtc->InternalTamper7EventCallback(hrtc); +#else + /* Internal Tamper7 secure callback */ + HAL_RTCEx_InternalTamper7EventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + } + + /* Check Internal Tamper8 status */ + if ((tmp & RTC_INT_TAMPER_8) == RTC_INT_TAMPER_8) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Internal Tamper 8 Event registered secure Callback */ + hrtc->InternalTamper8EventCallback(hrtc); +#else + /* Internal Tamper8 secure callback */ + HAL_RTCEx_InternalTamper8EventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + } + + /* Check Internal Tamper9 status */ + if ((tmp & RTC_INT_TAMPER_9) == RTC_INT_TAMPER_9) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Internal Tamper 9 Event registered secure Callback */ + hrtc->InternalTamper9EventCallback(hrtc); +#else + /* Internal Tamper9 secure callback */ + HAL_RTCEx_InternalTamper9EventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + } + + /* Check Internal Tamper11 status */ + if ((tmp & RTC_INT_TAMPER_11) == RTC_INT_TAMPER_11) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Internal Tamper 11 Event registered secure Callback */ + hrtc->InternalTamper11EventCallback(hrtc); +#else + /* Internal Tamper11 secure callback */ + HAL_RTCEx_InternalTamper11EventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + } + + /* Check Internal Tamper12 status */ + if ((tmp & RTC_INT_TAMPER_12) == RTC_INT_TAMPER_12) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Internal Tamper 12 Event registered secure Callback */ + hrtc->InternalTamper12EventCallback(hrtc); +#else + /* Internal Tamper12 secure callback */ + HAL_RTCEx_InternalTamper12EventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + } + + /* Check Internal Tamper13 status */ + if ((tmp & RTC_INT_TAMPER_13) == RTC_INT_TAMPER_13) + { +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call Internal Tamper 13 Event registered secure Callback */ + hrtc->InternalTamper13EventCallback(hrtc); +#else + /* Internal Tamper13 secure callback */ + HAL_RTCEx_InternalTamper13EventCallback(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + } + + /* Clear flags after treatment to allow the potential tamper feature */ + WRITE_REG(TAMP->SCR, tmp); +} + +/** + * @brief Tamper 1 callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_Tamper1EventCallback could be implemented in the user file + */ +} + +/** + * @brief Tamper 2 callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_Tamper2EventCallback could be implemented in the user file + */ +} + +/** + * @brief Tamper 3 callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_Tamper3EventCallback could be implemented in the user file + */ +} + +/** + * @brief Tamper 4 callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_Tamper4EventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_Tamper4EventCallback could be implemented in the user file + */ +} + +/** + * @brief Tamper 5 callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_Tamper5EventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_Tamper5EventCallback could be implemented in the user file + */ +} + +/** + * @brief Tamper 6 callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_Tamper6EventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_Tamper6EventCallback could be implemented in the user file + */ +} + +/** + * @brief Internal Tamper 3 callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_InternalTamper3EventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_InternalTamper3EventCallback could be implemented in the user file + */ +} + +/** + * @brief Internal Tamper 5 callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_InternalTamper5EventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_InternalTamper5EventCallback could be implemented in the user file + */ +} + +/** + * @brief Internal Tamper 6 callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_InternalTamper6EventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_InternalTamper6EventCallback could be implemented in the user file + */ +} + +/** + * @brief Internal Tamper 7 callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_InternalTamper7EventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_InternalTamper7EventCallback could be implemented in the user file + */ +} + +/** + * @brief Internal Tamper 8 callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_InternalTamper8EventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_InternalTamper8EventCallback could be implemented in the user file + */ +} + +/** + * @brief Internal Tamper 9 callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_InternalTamper9EventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_InternalTamper9EventCallback could be implemented in the user file + */ +} + +/** + * @brief Internal Tamper 11 callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_InternalTamper11EventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_InternalTamper11EventCallback could be implemented in the user file + */ +} + +/** + * @brief Internal Tamper 12 callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_InternalTamper12EventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_InternalTamper12EventCallback could be implemented in the user file + */ +} + +/** + * @brief Internal Tamper 13 callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_InternalTamper13EventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_InternalTamper13EventCallback could be implemented in the user file + */ +} +/** + * @} + */ + + +/** @addtogroup RTCEx_Exported_Functions_Group6 + * @brief Extended RTC Backup register functions + * +@verbatim + =============================================================================== + ##### Extended RTC Backup register functions ##### + =============================================================================== + [..] + (+) Before calling any tamper or internal tamper function, you have to call first + HAL_RTC_Init() function. + (+) In that one you can select to output tamper event on RTC pin. + [..] + This subsection provides functions allowing to + (+) Write a data in a specified RTC Backup data register + (+) Read a data in a specified RTC Backup data register +@endverbatim + * @{ + */ + + +/** + * @brief Write a data in a specified RTC Backup data register. + * @param hrtc RTC handle + * @param BackupRegister RTC Backup data Register number. + * This parameter can be RTC_BKP_DRx where x can be from 0 to RTC_BACKUP_NB + * @param Data Data to be written in the specified Backup data register. + * @retval None + */ +void HAL_RTCEx_BKUPWrite(const RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data) +{ + uint32_t tmp; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* Check the parameters */ + assert_param(IS_RTC_BKP(BackupRegister)); + + /* Determine address of the specified Backup register */ + tmp = (uint32_t)(&(TAMP->BKP0R)); + tmp += (BackupRegister * 4U); + + /* Write data in the specified register Backup register */ + *(__IO uint32_t *)tmp = (uint32_t)Data; +} + + +/** + * @brief Reads data from the specified RTC Backup data Register. + * @param hrtc RTC handle + * @param BackupRegister RTC Backup data Register number. + * This parameter can be RTC_BKP_DRx where x can be from 0 to RTC_BACKUP_NB + * @retval Read value + */ +uint32_t HAL_RTCEx_BKUPRead(const RTC_HandleTypeDef *hrtc, uint32_t BackupRegister) +{ + uint32_t tmp; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* Check the parameters */ + assert_param(IS_RTC_BKP(BackupRegister)); + + /* Determine address of the specified Backup register */ + tmp = (uint32_t)(&(TAMP->BKP0R)); + tmp += (BackupRegister * 4U); + + /* Read the data from the specified register */ + return (*(__IO uint32_t *)tmp); +} + +/** + * @brief Reset the RTC Backup data Registers and the device secrets. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTCEx_BKUPErase(const RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + SET_BIT(TAMP->CR2, TAMP_CR2_BKERASE); +} + +/** + * @brief Block the access to the RTC Backup data Register and all the device secrets. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTCEx_BKUPBlock(const RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + WRITE_REG(TAMP->CR2, TAMP_CR2_BKBLOCK); +} + +/** + * @brief Disable the Block to the access to the RTC Backup data Register and the device secrets. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTCEx_BKUPUnblock(const RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + CLEAR_BIT(TAMP->CR2, TAMP_CR2_BKBLOCK); +} + +#ifdef TAMP_RPCFGR_RPCFG +/** + * @brief Enable and Disable the erase of the configurable Device Secrets + * @note This API must be called before enabling the Tamper. + * @param hrtc RTC handle + * @param DeviceSecretConf Specifies the configuration of the Device Secrets + * This parameter can be a combination of the following values: + * @arg TAMP_DEVICESECRETS_ERASE_NONE + * @arg TAMP_DEVICESECRETS_ERASE_SRAM2 + * @arg TAMP_DEVICESECRETS_ERASE_RHUK + * @arg TAMP_DEVICESECRETS_ERASE_ICACHE + * @arg TAMP_DEVICESECRETS_ERASE_SAES_AES_HASH + * @arg TAMP_DEVICESECRETS_ERASE_PKA_SRAM + * @arg TAMP_DEVICESECRETS_ERASE_ALL + * + * @retval None + */ +void HAL_RTCEx_ConfigEraseDeviceSecrets(const RTC_HandleTypeDef *hrtc, uint32_t DeviceSecretConf) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + MODIFY_REG(TAMP->RPCFGR, TAMP_RPCFGR_RPCFG, DeviceSecretConf); +} +#endif /* TAMP_RPCFGR_RPCFG */ + +/** + * @} + */ + +#if defined(RTC_SECCFGR_SEC) +/** @addtogroup RTCEx_Exported_Functions_Group7 + * @brief Extended RTC security functions + * +@verbatim + =============================================================================== + ##### Extended RTC security functions ##### + =============================================================================== + [..] + (+) Before calling security function, you have to call first + HAL_RTC_Init() function. +@endverbatim + * @{ + */ + +/** + * @brief Get the security level of the RTC/TAMP/Backup registers. + * To set the secure level please call HAL_RTCEx_SecureModeSet. + * @param hrtc RTC handle + * @param secureState Secure state + * @retval HAL_StatusTypeDef + */ +HAL_StatusTypeDef HAL_RTCEx_SecureModeGet(const RTC_HandleTypeDef *hrtc, RTC_SecureStateTypeDef *secureState) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* Read registers */ + uint32_t rtc_seccfgr = READ_REG(RTC->SECCFGR); + uint32_t tamp_seccfgr = READ_REG(TAMP->SECCFGR); + + /* RTC */ + secureState->rtcSecureFull = READ_BIT(rtc_seccfgr, RTC_SECCFGR_SEC); + + /* Warning, rtcNonSecureFeatures is only relevant if secureState->rtcSecureFull == RTC_SECURE_FULL_NO */ + secureState->rtcNonSecureFeatures = ~(READ_BIT(rtc_seccfgr, RTC_NONSECURE_FEATURE_ALL)) & RTC_NONSECURE_FEATURE_ALL; + + /* TAMP */ + secureState->tampSecureFull = READ_BIT(tamp_seccfgr, TAMP_SECCFGR_TAMPSEC); + + /* Monotonic Counter */ + secureState->MonotonicCounterSecure = READ_BIT(tamp_seccfgr, TAMP_SECCFGR_CNT1SEC); + + /* Backup register start zones + Warning : Backup register start zones are shared with privilege configuration */ + secureState->backupRegisterStartZone2 = READ_BIT(tamp_seccfgr, TAMP_SECCFGR_BKPRWSEC) >> TAMP_SECCFGR_BKPRWSEC_Pos; + secureState->backupRegisterStartZone3 = READ_BIT(tamp_seccfgr, TAMP_SECCFGR_BKPWSEC) >> TAMP_SECCFGR_BKPWSEC_Pos; + + return HAL_OK; +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Set the security level of the RTC/TAMP/Backup registers. + * To get the current security level call HAL_RTCEx_SecureModeGet. + * @param hrtc RTC handle + * @param secureState Secure state + * @retval HAL_StatusTypeDef + */ +HAL_StatusTypeDef HAL_RTCEx_SecureModeSet(const RTC_HandleTypeDef *hrtc, const RTC_SecureStateTypeDef *secureState) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + assert_param(IS_RTC_SECURE_FULL(secureState->rtcSecureFull)); + assert_param(IS_RTC_NONSECURE_FEATURES(secureState->rtcNonSecureFeatures)); + assert_param(IS_TAMP_SECURE_FULL(secureState->tampSecureFull)); + assert_param(IS_RTC_BKP(secureState->backupRegisterStartZone2)); + assert_param(IS_RTC_BKP(secureState->backupRegisterStartZone3)); + assert_param(IS_TAMP_MONOTONIC_CNT_SECURE(secureState->MonotonicCounterSecure)); + + /* RTC, rtcNonSecureFeatures is only relevant if secureState->rtcSecureFull == RTC_SECURE_FULL_NO */ + WRITE_REG(RTC->SECCFGR, secureState->rtcSecureFull | (~(secureState->rtcNonSecureFeatures) & + RTC_NONSECURE_FEATURE_ALL)); + + /* Tamper + Backup register + Monotonic counter + Warning : Backup register start zone are Shared with privilege configuration */ + WRITE_REG(TAMP->SECCFGR, + secureState->tampSecureFull | secureState->MonotonicCounterSecure | + (TAMP_SECCFGR_BKPRWSEC & (secureState->backupRegisterStartZone2 << TAMP_SECCFGR_BKPRWSEC_Pos)) | + (TAMP_SECCFGR_BKPWSEC & (secureState->backupRegisterStartZone3 << TAMP_SECCFGR_BKPWSEC_Pos))); + + return HAL_OK; +} + + +#endif /* #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/** + * @} + */ +#endif /* RTC_SECCFGR_SEC */ + +#if defined(TAMP_PRIVCFGR_TAMPPRIV) +/** @addtogroup RTCEx_Exported_Functions_Group8 + * @brief Extended RTC privilege functions + * +@verbatim + =============================================================================== + ##### Extended RTC privilege functions ##### + =============================================================================== + [..] + (+) Before calling privilege function, you have to call first + HAL_RTC_Init() function. +@endverbatim + * @{ + */ + +/** + * @brief Set the privilege level of the RTC/TAMP/Backup registers. + * To get the current privilege level call HAL_RTCEx_PrivilegeModeGet. + * @param hrtc RTC handle + * @param privilegeState Privilege state + * @retval HAL_StatusTypeDef + */ +HAL_StatusTypeDef HAL_RTCEx_PrivilegeModeSet(const RTC_HandleTypeDef *hrtc, + const RTC_PrivilegeStateTypeDef *privilegeState) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + assert_param(IS_RTC_PRIVILEGE_FULL(privilegeState->rtcPrivilegeFull)); + assert_param(IS_RTC_PRIVILEGE_FEATURES(privilegeState->rtcPrivilegeFeatures)); + assert_param(IS_TAMP_PRIVILEGE_FULL(privilegeState->tampPrivilegeFull)); + assert_param(IS_TAMP_MONOTONIC_CNT_PRIVILEGE(privilegeState->MonotonicCounterPrivilege)); + assert_param(IS_RTC_PRIVILEGE_BKUP_ZONE(privilegeState->backupRegisterPrivZone)); + assert_param(IS_RTC_BKP(privilegeState->backupRegisterStartZone2)); + assert_param(IS_RTC_BKP(privilegeState->backupRegisterStartZone3)); + + /* RTC privilege configuration */ + WRITE_REG(RTC->PRIVCFGR, privilegeState->rtcPrivilegeFull | privilegeState->rtcPrivilegeFeatures); + + /* TAMP, Monotonic counter and Backup registers privilege configuration + Warning : privilegeState->backupRegisterPrivZone is only writable in secure mode or if trustzone is disabled. + In non secure mode, a notification is generated through a flag/interrupt in the TZIC + (TrustZone interrupt controller). The bits are not written. */ + WRITE_REG(TAMP->PRIVCFGR, privilegeState->tampPrivilegeFull | privilegeState->backupRegisterPrivZone | \ + privilegeState->MonotonicCounterPrivilege); + + /* Backup register start zone + Warning : This parameter is only writable in secure mode or if trustzone is disabled. + In non secure mode, a notification is generated through a flag/interrupt in the TZIC + (TrustZone interrupt controller). The bits are not written. + Warning : Backup register start zones are shared with secure configuration */ + MODIFY_REG(TAMP->SECCFGR, + (TAMP_SECCFGR_BKPRWSEC | TAMP_SECCFGR_BKPWSEC), + ((privilegeState->backupRegisterStartZone2 << TAMP_SECCFGR_BKPRWSEC_Pos) | \ + (privilegeState->backupRegisterStartZone3 << TAMP_SECCFGR_BKPWSEC_Pos))); + + return HAL_OK; +} + +/** + * @brief Get the privilege level of the RTC/TAMP/Backup registers. + * To set the privilege level please call HAL_RTCEx_PrivilegeModeSet. + * @param hrtc RTC handle + * @param privilegeState Privilege state + * @retval HAL_StatusTypeDef + */ +HAL_StatusTypeDef HAL_RTCEx_PrivilegeModeGet(const RTC_HandleTypeDef *hrtc, RTC_PrivilegeStateTypeDef *privilegeState) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + /* Read registers */ + uint32_t rtc_privcfgr = READ_REG(RTC->PRIVCFGR); + uint32_t tamp_privcfgr = READ_REG(TAMP->PRIVCFGR); + uint32_t tamp_seccfgr = READ_REG(TAMP->SECCFGR); + + /* RTC privilege configuration */ + privilegeState->rtcPrivilegeFull = READ_BIT(rtc_privcfgr, RTC_PRIVCFGR_PRIV); + + /* Warning, rtcPrivilegeFeatures is only relevant if privilegeState->rtcPrivilegeFull == RTC_PRIVILEGE_FULL_NO */ + privilegeState->rtcPrivilegeFeatures = READ_BIT(rtc_privcfgr, RTC_PRIVILEGE_FEATURE_ALL); + + /* TAMP and Backup registers privilege configuration */ + privilegeState->tampPrivilegeFull = READ_BIT(tamp_privcfgr, TAMP_PRIVCFGR_TAMPPRIV); + + /* Monotonic registers privilege configuration */ + privilegeState->MonotonicCounterPrivilege = READ_BIT(tamp_privcfgr, TAMP_PRIVCFGR_CNT1PRIV); + + /* Backup registers Zones */ + privilegeState->backupRegisterPrivZone = READ_BIT(tamp_privcfgr, (TAMP_PRIVCFGR_BKPWPRIV | TAMP_PRIVCFGR_BKPRWPRIV)); + + /* Backup register start zones + Warning : Shared with secure configuration */ + privilegeState->backupRegisterStartZone2 = READ_BIT(tamp_seccfgr, TAMP_SECCFGR_BKPRWSEC) >> TAMP_SECCFGR_BKPRWSEC_Pos; + privilegeState->backupRegisterStartZone3 = READ_BIT(tamp_seccfgr, TAMP_SECCFGR_BKPWSEC) >> TAMP_SECCFGR_BKPWSEC_Pos; + + return HAL_OK; +} + +/** + * @} + */ +#endif /* TAMP_PRIVCFGR_TAMPPRIV */ + +/** + * @} + */ + +#endif /* HAL_RTC_MODULE_ENABLED */ + +/** + * @} + */ + + +/** + * @} + */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_sai.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_sai.c new file mode 100644 index 0000000000..4b79ad874b --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_sai.c @@ -0,0 +1,2862 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_sai.c + * @author MCD Application Team + * @brief SAI HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Serial Audio Interface (SAI) peripheral: + * + Initialization/de-initialization functions + * + I/O operation functions + * + Peripheral Control functions + * + Peripheral State functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + + [..] + The SAI HAL driver can be used as follows: + + (#) Declare a SAI_HandleTypeDef handle structure (eg. SAI_HandleTypeDef hsai). + (#) Initialize the SAI low level resources by implementing the HAL_SAI_MspInit() API: + (##) Enable the SAI interface clock. + (##) SAI pins configuration: + (+++) Enable the clock for the SAI GPIOs. + (+++) Configure these SAI pins as alternate function pull-up. + (##) NVIC configuration if you need to use interrupt process (HAL_SAI_Transmit_IT() + and HAL_SAI_Receive_IT() APIs): + (+++) Configure the SAI interrupt priority. + (+++) Enable the NVIC SAI IRQ handle. + + (##) DMA Configuration if you need to use DMA process (HAL_SAI_Transmit_DMA() + and HAL_SAI_Receive_DMA() APIs): + (+++) Declare a DMA handle structure for the Tx/Rx stream. + (+++) Enable the DMAx interface clock. + (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. + (+++) Configure the DMA Tx/Rx Stream. + (+++) Associate the initialized DMA handle to the SAI DMA Tx/Rx handle. + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the + DMA Tx/Rx Stream. + + (#) The initialization can be done by two ways + (##) Expert mode : Initialize the structures Init, FrameInit and SlotInit and call HAL_SAI_Init(). + (##) Simplified mode : Initialize the high part of Init Structure and call HAL_SAI_InitProtocol(). + + [..] + (@) The specific SAI interrupts (FIFO request and Overrun underrun interrupt) + will be managed using the macros __HAL_SAI_ENABLE_IT() and __HAL_SAI_DISABLE_IT() + inside the transmit and receive process. + [..] + (@) Make sure that either: + (+@) System clock is configured or + (+@) HSI clock is configured or + (+@) PLL_P output is configured or + (+@) PLL_Q output is configured or + (+@) External clock source is configured after setting correctly + the define constant EXTERNAL_SAI1_CLOCK_VALUE in the stm32wbaxx_hal_conf.h file. + + [..] + (@) In master Tx mode: enabling the audio block immediately generates the bit clock + for the external slaves even if there is no data in the FIFO, However FS signal + generation is conditioned by the presence of data in the FIFO. + + [..] + (@) In master Rx mode: enabling the audio block immediately generates the bit clock + and FS signal for the external slaves. + + [..] + (@) It is mandatory to respect the following conditions in order to avoid bad SAI behavior: + (+@) First bit Offset <= (SLOT size - Data size) + (+@) Data size <= SLOT size + (+@) Number of SLOT x SLOT size = Frame length + (+@) The number of slots should be even when SAI_FS_CHANNEL_IDENTIFICATION is selected. + + [..] + (@) PDM interface can be activated through HAL_SAI_Init function. + Please note that PDM interface is only available for SAI1 sub-block A. + PDM microphone delays can be tuned with HAL_SAIEx_ConfigPdmMicDelay function. + + [..] + Three operation modes are available within this driver : + + *** Polling mode IO operation *** + ================================= + [..] + (+) Send an amount of data in blocking mode using HAL_SAI_Transmit() + (+) Receive an amount of data in blocking mode using HAL_SAI_Receive() + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Send an amount of data in non-blocking mode using HAL_SAI_Transmit_IT() + (+) At transmission end of transfer HAL_SAI_TxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_SAI_TxCpltCallback() + (+) Receive an amount of data in non-blocking mode using HAL_SAI_Receive_IT() + (+) At reception end of transfer HAL_SAI_RxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_SAI_RxCpltCallback() + (+) In case of flag error, HAL_SAI_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_SAI_ErrorCallback() + + *** DMA mode IO operation *** + ============================= + [..] + (+) Send an amount of data in non-blocking mode (DMA) using HAL_SAI_Transmit_DMA() + (+) At transmission end of transfer HAL_SAI_TxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_SAI_TxCpltCallback() + (+) Receive an amount of data in non-blocking mode (DMA) using HAL_SAI_Receive_DMA() + (+) At reception end of transfer HAL_SAI_RxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_SAI_RxCpltCallback() + (+) In case of flag error, HAL_SAI_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_SAI_ErrorCallback() + (+) Pause the DMA Transfer using HAL_SAI_DMAPause() + (+) Resume the DMA Transfer using HAL_SAI_DMAResume() + (+) Stop the DMA Transfer using HAL_SAI_DMAStop() + + *** SAI HAL driver additional function list *** + =============================================== + [..] + Below the list the others API available SAI HAL driver : + + (+) HAL_SAI_EnableTxMuteMode(): Enable the mute in tx mode + (+) HAL_SAI_DisableTxMuteMode(): Disable the mute in tx mode + (+) HAL_SAI_EnableRxMuteMode(): Enable the mute in Rx mode + (+) HAL_SAI_DisableRxMuteMode(): Disable the mute in Rx mode + (+) HAL_SAI_FlushRxFifo(): Flush the rx fifo. + (+) HAL_SAI_Abort(): Abort the current transfer + + *** SAI HAL driver macros list *** + ================================== + [..] + Below the list of most used macros in SAI HAL driver : + + (+) __HAL_SAI_ENABLE(): Enable the SAI peripheral + (+) __HAL_SAI_DISABLE(): Disable the SAI peripheral + (+) __HAL_SAI_ENABLE_IT(): Enable the specified SAI interrupts + (+) __HAL_SAI_DISABLE_IT(): Disable the specified SAI interrupts + (+) __HAL_SAI_GET_IT_SOURCE(): Check if the specified SAI interrupt source is + enabled or disabled + (+) __HAL_SAI_GET_FLAG(): Check whether the specified SAI flag is set or not + + *** Callback registration *** + ============================= + [..] + The compilation define USE_HAL_SAI_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use functions HAL_SAI_RegisterCallback() to register a user callback. + + [..] + Function HAL_SAI_RegisterCallback() allows to register following callbacks: + (+) RxCpltCallback : SAI receive complete. + (+) RxHalfCpltCallback : SAI receive half complete. + (+) TxCpltCallback : SAI transmit complete. + (+) TxHalfCpltCallback : SAI transmit half complete. + (+) ErrorCallback : SAI error. + (+) MspInitCallback : SAI MspInit. + (+) MspDeInitCallback : SAI MspDeInit. + [..] + This function takes as parameters the HAL peripheral handle, the callback ID + and a pointer to the user callback function. + + [..] + Use function HAL_SAI_UnRegisterCallback() to reset a callback to the default + weak function. + HAL_SAI_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the callback ID. + [..] + This function allows to reset following callbacks: + (+) RxCpltCallback : SAI receive complete. + (+) RxHalfCpltCallback : SAI receive half complete. + (+) TxCpltCallback : SAI transmit complete. + (+) TxHalfCpltCallback : SAI transmit half complete. + (+) ErrorCallback : SAI error. + (+) MspInitCallback : SAI MspInit. + (+) MspDeInitCallback : SAI MspDeInit. + + [..] + By default, after the HAL_SAI_Init and if the state is HAL_SAI_STATE_RESET + all callbacks are reset to the corresponding legacy weak functions: + examples HAL_SAI_RxCpltCallback(), HAL_SAI_ErrorCallback(). + Exception done for MspInit and MspDeInit callbacks that are respectively + reset to the legacy weak functions in the HAL_SAI_Init + and HAL_SAI_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_SAI_Init and HAL_SAI_DeInit + keep and use the user MspInit/MspDeInit callbacks (registered beforehand). + + [..] + Callbacks can be registered/unregistered in READY state only. + Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered + in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used + during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_SAI_RegisterCallback before calling HAL_SAI_DeInit + or HAL_SAI_Init function. + + [..] + When the compilation define USE_HAL_SAI_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak callbacks are used. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ +#if defined (SAI1) + +/** @defgroup SAI SAI + * @brief SAI HAL module driver + * @{ + */ + +#ifdef HAL_SAI_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/** @defgroup SAI_Private_Typedefs SAI Private Typedefs + * @{ + */ +typedef enum +{ + SAI_MODE_DMA, + SAI_MODE_IT +} SAI_ModeTypedef; +/** + * @} + */ + +/* Private define ------------------------------------------------------------*/ +/** @defgroup SAI_Private_Constants SAI Private Constants + * @{ + */ +#define SAI_DEFAULT_TIMEOUT 4U +#define SAI_LONG_TIMEOUT 1000U +#define SAI_SPDIF_FRAME_LENGTH 64U +#define SAI_AC97_FRAME_LENGTH 256U +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup SAI_Private_Functions SAI Private Functions + * @{ + */ +static void SAI_FillFifo(SAI_HandleTypeDef *hsai); +static uint32_t SAI_InterruptFlag(const SAI_HandleTypeDef *hsai, SAI_ModeTypedef mode); +static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot); +static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot); + +static HAL_StatusTypeDef SAI_Disable(SAI_HandleTypeDef *hsai); +static void SAI_Transmit_IT8Bit(SAI_HandleTypeDef *hsai); +static void SAI_Transmit_IT16Bit(SAI_HandleTypeDef *hsai); +static void SAI_Transmit_IT32Bit(SAI_HandleTypeDef *hsai); +static void SAI_Receive_IT8Bit(SAI_HandleTypeDef *hsai); +static void SAI_Receive_IT16Bit(SAI_HandleTypeDef *hsai); +static void SAI_Receive_IT32Bit(SAI_HandleTypeDef *hsai); + +static void SAI_DMATxCplt(DMA_HandleTypeDef *hdma); +static void SAI_DMATxHalfCplt(DMA_HandleTypeDef *hdma); +static void SAI_DMARxCplt(DMA_HandleTypeDef *hdma); +static void SAI_DMARxHalfCplt(DMA_HandleTypeDef *hdma); +static void SAI_DMAError(DMA_HandleTypeDef *hdma); +static void SAI_DMAAbort(DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ +/** @defgroup SAI_Exported_Functions SAI Exported Functions + * @{ + */ + +/** @defgroup SAI_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + de-initialize the SAIx peripheral: + + (+) User must implement HAL_SAI_MspInit() function in which he configures + all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). + + (+) Call the function HAL_SAI_Init() to configure the selected device with + the selected configuration: + (++) Mode (Master/slave TX/RX) + (++) Protocol + (++) Data Size + (++) MCLK Output + (++) Audio frequency + (++) FIFO Threshold + (++) Frame Config + (++) Slot Config + (++) PDM Config + + (+) Call the function HAL_SAI_DeInit() to restore the default configuration + of the selected SAI peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the structure FrameInit, SlotInit and the low part of + * Init according to the specified parameters and call the function + * HAL_SAI_Init to initialize the SAI block. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @param protocol one of the supported protocol @ref SAI_Protocol + * @param datasize one of the supported datasize @ref SAI_Protocol_DataSize + * the configuration information for SAI module. + * @param nbslot Number of slot. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot) +{ + HAL_StatusTypeDef status; + + /* Check the parameters */ + assert_param(IS_SAI_SUPPORTED_PROTOCOL(protocol)); + assert_param(IS_SAI_PROTOCOL_DATASIZE(datasize)); + + switch (protocol) + { + case SAI_I2S_STANDARD : + case SAI_I2S_MSBJUSTIFIED : + case SAI_I2S_LSBJUSTIFIED : + status = SAI_InitI2S(hsai, protocol, datasize, nbslot); + break; + case SAI_PCM_LONG : + case SAI_PCM_SHORT : + status = SAI_InitPCM(hsai, protocol, datasize, nbslot); + break; + default : + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + status = HAL_SAI_Init(hsai); + } + + return status; +} + +/** + * @brief Initialize the SAI according to the specified parameters. + * in the SAI_InitTypeDef structure and initialize the associated handle. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai) +{ + uint32_t ckstr_bits; + uint32_t syncen_bits; + + /* Check the SAI handle allocation */ + if (hsai == NULL) + { + return HAL_ERROR; + } + + /* check the instance */ + assert_param(IS_SAI_ALL_INSTANCE(hsai->Instance)); + + /* Check the SAI Block parameters */ + assert_param(IS_SAI_AUDIO_FREQUENCY(hsai->Init.AudioFrequency)); + assert_param(IS_SAI_BLOCK_PROTOCOL(hsai->Init.Protocol)); + assert_param(IS_SAI_BLOCK_MODE(hsai->Init.AudioMode)); + assert_param(IS_SAI_BLOCK_DATASIZE(hsai->Init.DataSize)); + assert_param(IS_SAI_BLOCK_FIRST_BIT(hsai->Init.FirstBit)); + assert_param(IS_SAI_BLOCK_CLOCK_STROBING(hsai->Init.ClockStrobing)); + assert_param(IS_SAI_BLOCK_SYNCHRO(hsai->Init.Synchro)); + assert_param(IS_SAI_BLOCK_MCK_OUTPUT(hsai->Init.MckOutput)); + assert_param(IS_SAI_BLOCK_OUTPUT_DRIVE(hsai->Init.OutputDrive)); + assert_param(IS_SAI_BLOCK_NODIVIDER(hsai->Init.NoDivider)); + assert_param(IS_SAI_BLOCK_FIFO_THRESHOLD(hsai->Init.FIFOThreshold)); + assert_param(IS_SAI_MONO_STEREO_MODE(hsai->Init.MonoStereoMode)); + assert_param(IS_SAI_BLOCK_COMPANDING_MODE(hsai->Init.CompandingMode)); + assert_param(IS_SAI_BLOCK_TRISTATE_MANAGEMENT(hsai->Init.TriState)); + assert_param(IS_SAI_BLOCK_SYNCEXT(hsai->Init.SynchroExt)); + assert_param(IS_SAI_BLOCK_MCK_OVERSAMPLING(hsai->Init.MckOverSampling)); + + /* Check the SAI Block Frame parameters */ + assert_param(IS_SAI_BLOCK_FRAME_LENGTH(hsai->FrameInit.FrameLength)); + assert_param(IS_SAI_BLOCK_ACTIVE_FRAME(hsai->FrameInit.ActiveFrameLength)); + assert_param(IS_SAI_BLOCK_FS_DEFINITION(hsai->FrameInit.FSDefinition)); + assert_param(IS_SAI_BLOCK_FS_POLARITY(hsai->FrameInit.FSPolarity)); + assert_param(IS_SAI_BLOCK_FS_OFFSET(hsai->FrameInit.FSOffset)); + + /* Check the SAI Block Slot parameters */ + assert_param(IS_SAI_BLOCK_FIRSTBIT_OFFSET(hsai->SlotInit.FirstBitOffset)); + assert_param(IS_SAI_BLOCK_SLOT_SIZE(hsai->SlotInit.SlotSize)); + assert_param(IS_SAI_BLOCK_SLOT_NUMBER(hsai->SlotInit.SlotNumber)); + assert_param(IS_SAI_SLOT_ACTIVE(hsai->SlotInit.SlotActive)); + + /* Check the SAI PDM parameters */ + assert_param(IS_FUNCTIONAL_STATE(hsai->Init.PdmInit.Activation)); + if (hsai->Init.PdmInit.Activation == ENABLE) + { + assert_param(IS_SAI_PDM_MIC_PAIRS_NUMBER(hsai->Init.PdmInit.MicPairsNbr)); + assert_param(IS_SAI_PDM_CLOCK_ENABLE(hsai->Init.PdmInit.ClockEnable)); + /* Check that SAI sub-block is SAI1 sub-block A, in master RX mode with free protocol */ + if ((hsai->Instance != SAI1_Block_A) || + (hsai->Init.AudioMode != SAI_MODEMASTER_RX) || + (hsai->Init.Protocol != SAI_FREE_PROTOCOL)) + { + return HAL_ERROR; + } + } + + if (hsai->State == HAL_SAI_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hsai->Lock = HAL_UNLOCKED; + +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + /* Reset callback pointers to the weak predefined callbacks */ + hsai->RxCpltCallback = HAL_SAI_RxCpltCallback; + hsai->RxHalfCpltCallback = HAL_SAI_RxHalfCpltCallback; + hsai->TxCpltCallback = HAL_SAI_TxCpltCallback; + hsai->TxHalfCpltCallback = HAL_SAI_TxHalfCpltCallback; + hsai->ErrorCallback = HAL_SAI_ErrorCallback; + + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + if (hsai->MspInitCallback == NULL) + { + hsai->MspInitCallback = HAL_SAI_MspInit; + } + hsai->MspInitCallback(hsai); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_SAI_MspInit(hsai); +#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ + } + + /* Disable the selected SAI peripheral */ + if (SAI_Disable(hsai) != HAL_OK) + { + return HAL_ERROR; + } + + hsai->State = HAL_SAI_STATE_BUSY; + + /* SAI Block Synchro Configuration -----------------------------------------*/ + /* This setting must be done with both audio block (A & B) disabled */ + switch (hsai->Init.Synchro) + { + case SAI_ASYNCHRONOUS : + syncen_bits = 0; + break; + case SAI_SYNCHRONOUS : + syncen_bits = SAI_xCR1_SYNCEN_0; + break; + default : + syncen_bits = 0; + break; + } + + SAI1->GCR = 0; + + if (hsai->Init.AudioFrequency != SAI_AUDIO_FREQUENCY_MCKDIV) + { + uint32_t freq; + uint32_t tmpval; + + /* In this case, the MCKDIV value is calculated to get AudioFrequency */ + freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI1); + + /* Configure Master Clock Divider using the following formula : + - If NODIV = 1 : + MCKDIV[5:0] = SAI_CK_x / (FS * (FRL + 1)) + - If NODIV = 0 : + MCKDIV[5:0] = SAI_CK_x / (FS * (OSR + 1) * 256) */ + if (hsai->Init.NoDivider == SAI_MASTERDIVIDER_DISABLE) + { + /* NODIV = 1 */ + uint32_t tmpframelength; + + if (hsai->Init.Protocol == SAI_SPDIF_PROTOCOL) + { + /* For SPDIF protocol, frame length is set by hardware to 64 */ + tmpframelength = SAI_SPDIF_FRAME_LENGTH; + } + else if (hsai->Init.Protocol == SAI_AC97_PROTOCOL) + { + /* For AC97 protocol, frame length is set by hardware to 256 */ + tmpframelength = SAI_AC97_FRAME_LENGTH; + } + else + { + /* For free protocol, frame length is set by user */ + tmpframelength = hsai->FrameInit.FrameLength; + } + + /* (freq x 10) to keep Significant digits */ + tmpval = (freq * 10U) / (hsai->Init.AudioFrequency * tmpframelength); + } + else + { + /* NODIV = 0 */ + uint32_t tmposr; + tmposr = (hsai->Init.MckOverSampling == SAI_MCK_OVERSAMPLING_ENABLE) ? 2U : 1U; + /* (freq x 10) to keep Significant digits */ + tmpval = (freq * 10U) / (hsai->Init.AudioFrequency * tmposr * 256U); + } + hsai->Init.Mckdiv = tmpval / 10U; + + /* Round result to the nearest integer */ + if ((tmpval % 10U) > 8U) + { + hsai->Init.Mckdiv += 1U; + } + + /* For SPDIF protocol, SAI shall provide a bit clock twice faster the symbol-rate */ + if (hsai->Init.Protocol == SAI_SPDIF_PROTOCOL) + { + hsai->Init.Mckdiv = hsai->Init.Mckdiv >> 1; + } + } + + /* Check the SAI Block master clock divider parameter */ + assert_param(IS_SAI_BLOCK_MASTER_DIVIDER(hsai->Init.Mckdiv)); + + /* Compute CKSTR bits of SAI CR1 according ClockStrobing and AudioMode */ + if ((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX)) + { + /* Transmit */ + ckstr_bits = (hsai->Init.ClockStrobing == SAI_CLOCKSTROBING_RISINGEDGE) ? 0U : SAI_xCR1_CKSTR; + } + else + { + /* Receive */ + ckstr_bits = (hsai->Init.ClockStrobing == SAI_CLOCKSTROBING_RISINGEDGE) ? SAI_xCR1_CKSTR : 0U; + } + + /* SAI Block Configuration -------------------------------------------------*/ + /* SAI CR1 Configuration */ + hsai->Instance->CR1 &= ~(SAI_xCR1_MODE | SAI_xCR1_PRTCFG | SAI_xCR1_DS | \ + SAI_xCR1_LSBFIRST | SAI_xCR1_CKSTR | SAI_xCR1_SYNCEN | \ + SAI_xCR1_MONO | SAI_xCR1_OUTDRIV | SAI_xCR1_DMAEN | \ + SAI_xCR1_NODIV | SAI_xCR1_MCKDIV | SAI_xCR1_OSR | \ + SAI_xCR1_MCKEN); + + hsai->Instance->CR1 |= (hsai->Init.AudioMode | hsai->Init.Protocol | \ + hsai->Init.DataSize | hsai->Init.FirstBit | \ + ckstr_bits | syncen_bits | \ + hsai->Init.MonoStereoMode | hsai->Init.OutputDrive | \ + hsai->Init.NoDivider | (hsai->Init.Mckdiv << 20) | \ + hsai->Init.MckOverSampling | hsai->Init.MckOutput); + + /* SAI CR2 Configuration */ + hsai->Instance->CR2 &= ~(SAI_xCR2_FTH | SAI_xCR2_FFLUSH | SAI_xCR2_COMP | SAI_xCR2_CPL); + hsai->Instance->CR2 |= (hsai->Init.FIFOThreshold | hsai->Init.CompandingMode | hsai->Init.TriState); + + /* SAI Frame Configuration -----------------------------------------*/ + hsai->Instance->FRCR &= (~(SAI_xFRCR_FRL | SAI_xFRCR_FSALL | SAI_xFRCR_FSDEF | \ + SAI_xFRCR_FSPOL | SAI_xFRCR_FSOFF)); + hsai->Instance->FRCR |= ((hsai->FrameInit.FrameLength - 1U) | + hsai->FrameInit.FSOffset | + hsai->FrameInit.FSDefinition | + hsai->FrameInit.FSPolarity | + ((hsai->FrameInit.ActiveFrameLength - 1U) << 8)); + + /* SAI Block_x SLOT Configuration ------------------------------------------*/ + /* This register has no meaning in AC 97 and SPDIF audio protocol */ + hsai->Instance->SLOTR &= (~(SAI_xSLOTR_FBOFF | SAI_xSLOTR_SLOTSZ | \ + SAI_xSLOTR_NBSLOT | SAI_xSLOTR_SLOTEN)); + + hsai->Instance->SLOTR |= hsai->SlotInit.FirstBitOffset | hsai->SlotInit.SlotSize | \ + (hsai->SlotInit.SlotActive << 16) | ((hsai->SlotInit.SlotNumber - 1U) << 8); + + /* SAI PDM Configuration ---------------------------------------------------*/ + if (hsai->Instance == SAI1_Block_A) + { + /* Disable PDM interface */ + SAI1->PDMCR &= ~(SAI_PDMCR_PDMEN); + if (hsai->Init.PdmInit.Activation == ENABLE) + { + /* Configure and enable PDM interface */ + SAI1->PDMCR = (hsai->Init.PdmInit.ClockEnable | + ((hsai->Init.PdmInit.MicPairsNbr - 1U) << SAI_PDMCR_MICNBR_Pos)); + SAI1->PDMCR |= SAI_PDMCR_PDMEN; + } + } + + /* Initialize the error code */ + hsai->ErrorCode = HAL_SAI_ERROR_NONE; + + /* Initialize the SAI state */ + hsai->State = HAL_SAI_STATE_READY; + + /* Release Lock */ + __HAL_UNLOCK(hsai); + + return HAL_OK; +} + +/** + * @brief DeInitialize the SAI peripheral. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SAI_DeInit(SAI_HandleTypeDef *hsai) +{ + /* Check the SAI handle allocation */ + if (hsai == NULL) + { + return HAL_ERROR; + } + + hsai->State = HAL_SAI_STATE_BUSY; + + /* Disabled All interrupt and clear all the flag */ + hsai->Instance->IMR = 0; + hsai->Instance->CLRFR = 0xFFFFFFFFU; + + /* Disable the SAI */ + if (SAI_Disable(hsai) != HAL_OK) + { + /* Reset SAI state to ready */ + hsai->State = HAL_SAI_STATE_READY; + + /* Release Lock */ + __HAL_UNLOCK(hsai); + + return HAL_ERROR; + } + + /* Flush the fifo */ + SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH); + + /* Disable SAI PDM interface */ + if (hsai->Instance == SAI1_Block_A) + { + /* Reset PDM delays */ + SAI1->PDMDLY = 0U; + + /* Disable PDM interface */ + SAI1->PDMCR &= ~(SAI_PDMCR_PDMEN); + } + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + if (hsai->MspDeInitCallback == NULL) + { + hsai->MspDeInitCallback = HAL_SAI_MspDeInit; + } + hsai->MspDeInitCallback(hsai); +#else + HAL_SAI_MspDeInit(hsai); +#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ + + /* Initialize the error code */ + hsai->ErrorCode = HAL_SAI_ERROR_NONE; + + /* Initialize the SAI state */ + hsai->State = HAL_SAI_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hsai); + + return HAL_OK; +} + +/** + * @brief Initialize the SAI MSP. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @retval None + */ +__weak void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsai); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SAI_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitialize the SAI MSP. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @retval None + */ +__weak void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsai); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SAI_MspDeInit could be implemented in the user file + */ +} + +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) +/** + * @brief Register a user SAI callback + * to be used instead of the weak predefined callback. + * @param hsai SAI handle. + * @param CallbackID ID of the callback to be registered. + * This parameter can be one of the following values: + * @arg @ref HAL_SAI_RX_COMPLETE_CB_ID receive complete callback ID. + * @arg @ref HAL_SAI_RX_HALFCOMPLETE_CB_ID receive half complete callback ID. + * @arg @ref HAL_SAI_TX_COMPLETE_CB_ID transmit complete callback ID. + * @arg @ref HAL_SAI_TX_HALFCOMPLETE_CB_ID transmit half complete callback ID. + * @arg @ref HAL_SAI_ERROR_CB_ID error callback ID. + * @arg @ref HAL_SAI_MSPINIT_CB_ID MSP init callback ID. + * @arg @ref HAL_SAI_MSPDEINIT_CB_ID MSP de-init callback ID. + * @param pCallback pointer to the callback function. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_SAI_RegisterCallback(SAI_HandleTypeDef *hsai, + HAL_SAI_CallbackIDTypeDef CallbackID, + pSAI_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* update the error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + else + { + if (HAL_SAI_STATE_READY == hsai->State) + { + switch (CallbackID) + { + case HAL_SAI_RX_COMPLETE_CB_ID : + hsai->RxCpltCallback = pCallback; + break; + case HAL_SAI_RX_HALFCOMPLETE_CB_ID : + hsai->RxHalfCpltCallback = pCallback; + break; + case HAL_SAI_TX_COMPLETE_CB_ID : + hsai->TxCpltCallback = pCallback; + break; + case HAL_SAI_TX_HALFCOMPLETE_CB_ID : + hsai->TxHalfCpltCallback = pCallback; + break; + case HAL_SAI_ERROR_CB_ID : + hsai->ErrorCallback = pCallback; + break; + case HAL_SAI_MSPINIT_CB_ID : + hsai->MspInitCallback = pCallback; + break; + case HAL_SAI_MSPDEINIT_CB_ID : + hsai->MspDeInitCallback = pCallback; + break; + default : + /* update the error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_SAI_STATE_RESET == hsai->State) + { + switch (CallbackID) + { + case HAL_SAI_MSPINIT_CB_ID : + hsai->MspInitCallback = pCallback; + break; + case HAL_SAI_MSPDEINIT_CB_ID : + hsai->MspDeInitCallback = pCallback; + break; + default : + /* update the error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* update the error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + } + return status; +} + +/** + * @brief Unregister a user SAI callback. + * SAI callback is redirected to the weak predefined callback. + * @param hsai SAI handle. + * @param CallbackID ID of the callback to be unregistered. + * This parameter can be one of the following values: + * @arg @ref HAL_SAI_RX_COMPLETE_CB_ID receive complete callback ID. + * @arg @ref HAL_SAI_RX_HALFCOMPLETE_CB_ID receive half complete callback ID. + * @arg @ref HAL_SAI_TX_COMPLETE_CB_ID transmit complete callback ID. + * @arg @ref HAL_SAI_TX_HALFCOMPLETE_CB_ID transmit half complete callback ID. + * @arg @ref HAL_SAI_ERROR_CB_ID error callback ID. + * @arg @ref HAL_SAI_MSPINIT_CB_ID MSP init callback ID. + * @arg @ref HAL_SAI_MSPDEINIT_CB_ID MSP de-init callback ID. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_SAI_UnRegisterCallback(SAI_HandleTypeDef *hsai, + HAL_SAI_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (HAL_SAI_STATE_READY == hsai->State) + { + switch (CallbackID) + { + case HAL_SAI_RX_COMPLETE_CB_ID : + hsai->RxCpltCallback = HAL_SAI_RxCpltCallback; + break; + case HAL_SAI_RX_HALFCOMPLETE_CB_ID : + hsai->RxHalfCpltCallback = HAL_SAI_RxHalfCpltCallback; + break; + case HAL_SAI_TX_COMPLETE_CB_ID : + hsai->TxCpltCallback = HAL_SAI_TxCpltCallback; + break; + case HAL_SAI_TX_HALFCOMPLETE_CB_ID : + hsai->TxHalfCpltCallback = HAL_SAI_TxHalfCpltCallback; + break; + case HAL_SAI_ERROR_CB_ID : + hsai->ErrorCallback = HAL_SAI_ErrorCallback; + break; + case HAL_SAI_MSPINIT_CB_ID : + hsai->MspInitCallback = HAL_SAI_MspInit; + break; + case HAL_SAI_MSPDEINIT_CB_ID : + hsai->MspDeInitCallback = HAL_SAI_MspDeInit; + break; + default : + /* update the error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_SAI_STATE_RESET == hsai->State) + { + switch (CallbackID) + { + case HAL_SAI_MSPINIT_CB_ID : + hsai->MspInitCallback = HAL_SAI_MspInit; + break; + case HAL_SAI_MSPDEINIT_CB_ID : + hsai->MspDeInitCallback = HAL_SAI_MspDeInit; + break; + default : + /* update the error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* update the error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + return status; +} +#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup SAI_Exported_Functions_Group2 IO operation functions + * @brief Data transfers functions + * +@verbatim + ============================================================================== + ##### IO operation functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to manage the SAI data + transfers. + + (+) There are two modes of transfer: + (++) Blocking mode : The communication is performed in the polling mode. + The status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode : The communication is performed using Interrupts + or DMA. These functions return the status of the transfer startup. + The end of the data processing will be indicated through the + dedicated SAI IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + + (+) Blocking mode functions are : + (++) HAL_SAI_Transmit() + (++) HAL_SAI_Receive() + + (+) Non Blocking mode functions with Interrupt are : + (++) HAL_SAI_Transmit_IT() + (++) HAL_SAI_Receive_IT() + + (+) Non Blocking mode functions with DMA are : + (++) HAL_SAI_Transmit_DMA() + (++) HAL_SAI_Receive_DMA() + + (+) A set of Transfer Complete Callbacks are provided in non Blocking mode: + (++) HAL_SAI_TxCpltCallback() + (++) HAL_SAI_RxCpltCallback() + (++) HAL_SAI_ErrorCallback() + +@endverbatim + * @{ + */ + +/** + * @brief Transmit an amount of data in blocking mode. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart = HAL_GetTick(); + uint32_t temp; + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + if (hsai->State == HAL_SAI_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsai); + + hsai->XferSize = Size; + hsai->XferCount = Size; + hsai->pBuffPtr = pData; + hsai->State = HAL_SAI_STATE_BUSY_TX; + hsai->ErrorCode = HAL_SAI_ERROR_NONE; + + /* Check if the SAI is already enabled */ + if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U) + { + /* fill the fifo with data before to enabled the SAI */ + SAI_FillFifo(hsai); + /* Enable SAI peripheral */ + __HAL_SAI_ENABLE(hsai); + } + + while (hsai->XferCount > 0U) + { + /* Write data if the FIFO is not full */ + if ((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_FULL) + { + if ((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING)) + { + hsai->Instance->DR = *hsai->pBuffPtr; + hsai->pBuffPtr++; + } + else if (hsai->Init.DataSize <= SAI_DATASIZE_16) + { + temp = (uint32_t)(*hsai->pBuffPtr); + hsai->pBuffPtr++; + temp |= ((uint32_t)(*hsai->pBuffPtr) << 8); + hsai->pBuffPtr++; + hsai->Instance->DR = temp; + } + else + { + temp = (uint32_t)(*hsai->pBuffPtr); + hsai->pBuffPtr++; + temp |= ((uint32_t)(*hsai->pBuffPtr) << 8); + hsai->pBuffPtr++; + temp |= ((uint32_t)(*hsai->pBuffPtr) << 16); + hsai->pBuffPtr++; + temp |= ((uint32_t)(*hsai->pBuffPtr) << 24); + hsai->pBuffPtr++; + hsai->Instance->DR = temp; + } + hsai->XferCount--; + } + else + { + /* Check for the Timeout */ + if ((((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) && (Timeout != HAL_MAX_DELAY)) + { + /* Update error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT; + + /* Clear all the flags */ + hsai->Instance->CLRFR = 0xFFFFFFFFU; + + /* Disable SAI peripheral */ + /* No need to check return value because state update, unlock and error return will be performed later */ + (void) SAI_Disable(hsai); + + /* Flush the fifo */ + SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH); + + /* Change the SAI state */ + hsai->State = HAL_SAI_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsai); + + return HAL_ERROR; + } + } + } + + hsai->State = HAL_SAI_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsai); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in blocking mode. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @param pData Pointer to data buffer + * @param Size Amount of data to be received + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart = HAL_GetTick(); + uint32_t temp; + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + if (hsai->State == HAL_SAI_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsai); + + hsai->pBuffPtr = pData; + hsai->XferSize = Size; + hsai->XferCount = Size; + hsai->State = HAL_SAI_STATE_BUSY_RX; + hsai->ErrorCode = HAL_SAI_ERROR_NONE; + + /* Check if the SAI is already enabled */ + if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U) + { + /* Enable SAI peripheral */ + __HAL_SAI_ENABLE(hsai); + } + + /* Receive data */ + while (hsai->XferCount > 0U) + { + if ((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_EMPTY) + { + if ((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING)) + { + *hsai->pBuffPtr = (uint8_t)hsai->Instance->DR; + hsai->pBuffPtr++; + } + else if (hsai->Init.DataSize <= SAI_DATASIZE_16) + { + temp = hsai->Instance->DR; + *hsai->pBuffPtr = (uint8_t)temp; + hsai->pBuffPtr++; + *hsai->pBuffPtr = (uint8_t)(temp >> 8); + hsai->pBuffPtr++; + } + else + { + temp = hsai->Instance->DR; + *hsai->pBuffPtr = (uint8_t)temp; + hsai->pBuffPtr++; + *hsai->pBuffPtr = (uint8_t)(temp >> 8); + hsai->pBuffPtr++; + *hsai->pBuffPtr = (uint8_t)(temp >> 16); + hsai->pBuffPtr++; + *hsai->pBuffPtr = (uint8_t)(temp >> 24); + hsai->pBuffPtr++; + } + hsai->XferCount--; + } + else + { + /* Check for the Timeout */ + if ((((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) && (Timeout != HAL_MAX_DELAY)) + { + /* Update error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT; + + /* Clear all the flags */ + hsai->Instance->CLRFR = 0xFFFFFFFFU; + + /* Disable SAI peripheral */ + /* No need to check return value because state update, unlock and error return will be performed later */ + (void) SAI_Disable(hsai); + + /* Flush the fifo */ + SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH); + + /* Change the SAI state */ + hsai->State = HAL_SAI_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsai); + + return HAL_ERROR; + } + } + } + + hsai->State = HAL_SAI_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsai); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit an amount of data in non-blocking mode with Interrupt. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size) +{ + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + if (hsai->State == HAL_SAI_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsai); + + hsai->pBuffPtr = pData; + hsai->XferSize = Size; + hsai->XferCount = Size; + hsai->ErrorCode = HAL_SAI_ERROR_NONE; + hsai->State = HAL_SAI_STATE_BUSY_TX; + + if ((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING)) + { + hsai->InterruptServiceRoutine = SAI_Transmit_IT8Bit; + } + else if (hsai->Init.DataSize <= SAI_DATASIZE_16) + { + hsai->InterruptServiceRoutine = SAI_Transmit_IT16Bit; + } + else + { + hsai->InterruptServiceRoutine = SAI_Transmit_IT32Bit; + } + + /* Fill the fifo before starting the communication */ + SAI_FillFifo(hsai); + + /* Enable FRQ and OVRUDR interrupts */ + __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); + + /* Check if the SAI is already enabled */ + if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U) + { + /* Enable SAI peripheral */ + __HAL_SAI_ENABLE(hsai); + } + /* Process Unlocked */ + __HAL_UNLOCK(hsai); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in non-blocking mode with Interrupt. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @param pData Pointer to data buffer + * @param Size Amount of data to be received + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size) +{ + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + if (hsai->State == HAL_SAI_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsai); + + hsai->pBuffPtr = pData; + hsai->XferSize = Size; + hsai->XferCount = Size; + hsai->ErrorCode = HAL_SAI_ERROR_NONE; + hsai->State = HAL_SAI_STATE_BUSY_RX; + + if ((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING)) + { + hsai->InterruptServiceRoutine = SAI_Receive_IT8Bit; + } + else if (hsai->Init.DataSize <= SAI_DATASIZE_16) + { + hsai->InterruptServiceRoutine = SAI_Receive_IT16Bit; + } + else + { + hsai->InterruptServiceRoutine = SAI_Receive_IT32Bit; + } + + /* Enable TXE and OVRUDR interrupts */ + __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); + + /* Check if the SAI is already enabled */ + if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U) + { + /* Enable SAI peripheral */ + __HAL_SAI_ENABLE(hsai); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hsai); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Pause the audio stream playing from the Media. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SAI_DMAPause(SAI_HandleTypeDef *hsai) +{ + /* Process Locked */ + __HAL_LOCK(hsai); + + /* Pause the audio file playing by disabling the SAI DMA requests */ + hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN; + + /* Process Unlocked */ + __HAL_UNLOCK(hsai); + + return HAL_OK; +} + +/** + * @brief Resume the audio stream playing from the Media. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai) +{ + /* Process Locked */ + __HAL_LOCK(hsai); + + /* Enable the SAI DMA requests */ + hsai->Instance->CR1 |= SAI_xCR1_DMAEN; + + /* If the SAI peripheral is still not enabled, enable it */ + if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U) + { + /* Enable SAI peripheral */ + __HAL_SAI_ENABLE(hsai); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hsai); + + return HAL_OK; +} + +/** + * @brief Stop the audio stream playing from the Media. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process Locked */ + __HAL_LOCK(hsai); + + /* Disable SAI peripheral */ + if (SAI_Disable(hsai) != HAL_OK) + { + status = HAL_ERROR; + } + + /* Disable the SAI DMA request */ + hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN; + + /* Abort the SAI Tx DMA Stream */ + if ((hsai->State == HAL_SAI_STATE_BUSY_TX) && (hsai->hdmatx != NULL)) + { + if (HAL_DMA_Abort(hsai->hdmatx) != HAL_OK) + { + /* If the DMA Tx errorCode is different from DMA No Transfer then return Error */ + if (hsai->hdmatx->ErrorCode != HAL_DMA_ERROR_NO_XFER) + { + status = HAL_ERROR; + hsai->ErrorCode |= HAL_SAI_ERROR_DMA; + } + } + } + + /* Abort the SAI Rx DMA Stream */ + if ((hsai->State == HAL_SAI_STATE_BUSY_RX) && (hsai->hdmarx != NULL)) + { + if (HAL_DMA_Abort(hsai->hdmarx) != HAL_OK) + { + /* If the DMA Rx errorCode is different from DMA No Transfer then return Error */ + if (hsai->hdmarx->ErrorCode != HAL_DMA_ERROR_NO_XFER) + { + status = HAL_ERROR; + hsai->ErrorCode |= HAL_SAI_ERROR_DMA; + } + } + } + + /* Flush the fifo */ + SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH); + + /* Set hsai state to ready */ + hsai->State = HAL_SAI_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsai); + + return status; +} + +/** + * @brief Abort the current transfer and disable the SAI. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process Locked */ + __HAL_LOCK(hsai); + + /* Disable SAI peripheral */ + if (SAI_Disable(hsai) != HAL_OK) + { + status = HAL_ERROR; + } + + /* Check SAI DMA is enabled or not */ + if ((hsai->Instance->CR1 & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN) + { + /* Disable the SAI DMA request */ + hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN; + + /* Abort the SAI Tx DMA Stream */ + if ((hsai->State == HAL_SAI_STATE_BUSY_TX) && (hsai->hdmatx != NULL)) + { + if (HAL_DMA_Abort(hsai->hdmatx) != HAL_OK) + { + /* If the DMA Tx errorCode is different from DMA No Transfer then return Error */ + if (hsai->hdmatx->ErrorCode != HAL_DMA_ERROR_NO_XFER) + { + status = HAL_ERROR; + hsai->ErrorCode |= HAL_SAI_ERROR_DMA; + } + } + } + + /* Abort the SAI Rx DMA Stream */ + if ((hsai->State == HAL_SAI_STATE_BUSY_RX) && (hsai->hdmarx != NULL)) + { + if (HAL_DMA_Abort(hsai->hdmarx) != HAL_OK) + { + /* If the DMA Rx errorCode is different from DMA No Transfer then return Error */ + if (hsai->hdmarx->ErrorCode != HAL_DMA_ERROR_NO_XFER) + { + status = HAL_ERROR; + hsai->ErrorCode |= HAL_SAI_ERROR_DMA; + } + } + } + } + + /* Disabled All interrupt and clear all the flag */ + hsai->Instance->IMR = 0; + hsai->Instance->CLRFR = 0xFFFFFFFFU; + + /* Flush the fifo */ + SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH); + + /* Set hsai state to ready */ + hsai->State = HAL_SAI_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsai); + + return status; +} + +/** + * @brief Transmit an amount of data in non-blocking mode with DMA. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef status; + uint32_t tickstart = HAL_GetTick(); + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + if (hsai->State == HAL_SAI_STATE_READY) + { + uint32_t dmaSrcSize; + + /* Process Locked */ + __HAL_LOCK(hsai); + + hsai->pBuffPtr = pData; + hsai->XferSize = Size; + hsai->XferCount = Size; + hsai->ErrorCode = HAL_SAI_ERROR_NONE; + hsai->State = HAL_SAI_STATE_BUSY_TX; + + /* Set the SAI Tx DMA Half transfer complete callback */ + hsai->hdmatx->XferHalfCpltCallback = SAI_DMATxHalfCplt; + + /* Set the SAI TxDMA transfer complete callback */ + hsai->hdmatx->XferCpltCallback = SAI_DMATxCplt; + + /* Set the DMA error callback */ + hsai->hdmatx->XferErrorCallback = SAI_DMAError; + + /* Set the DMA Tx abort callback */ + hsai->hdmatx->XferAbortCallback = NULL; + + /* For transmission, the DMA source is data buffer. + We have to compute DMA size of a source block transfer in bytes according SAI data size. */ + if ((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING)) + { + dmaSrcSize = (uint32_t) Size; + } + else if (hsai->Init.DataSize <= SAI_DATASIZE_16) + { + dmaSrcSize = 2U * (uint32_t) Size; + } + else + { + dmaSrcSize = 4U * (uint32_t) Size; + } + + /* Enable the Tx DMA Stream */ + if ((hsai->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hsai->hdmatx->LinkedListQueue != NULL) + { + /* Set DMA data size */ + hsai->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = dmaSrcSize; + + /* Set DMA source address */ + hsai->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)hsai->pBuffPtr; + + /* Set DMA destination address */ + hsai->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)&hsai->Instance->DR; + + status = HAL_DMAEx_List_Start_IT(hsai->hdmatx); + } + else + { + __HAL_UNLOCK(hsai); + return HAL_ERROR; + } + } + else + { + status = HAL_DMA_Start_IT(hsai->hdmatx, (uint32_t)hsai->pBuffPtr, (uint32_t)&hsai->Instance->DR, dmaSrcSize); + } + + if (status != HAL_OK) + { + __HAL_UNLOCK(hsai); + return HAL_ERROR; + } + + /* Enable the interrupts for error handling */ + __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA)); + + /* Enable SAI Tx DMA Request */ + hsai->Instance->CR1 |= SAI_xCR1_DMAEN; + + /* Wait until FIFO is not empty */ + while ((hsai->Instance->SR & SAI_xSR_FLVL) == SAI_FIFOSTATUS_EMPTY) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > SAI_LONG_TIMEOUT) + { + /* Update error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hsai); + + return HAL_TIMEOUT; + } + } + + /* Check if the SAI is already enabled */ + if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U) + { + /* Enable SAI peripheral */ + __HAL_SAI_ENABLE(hsai); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hsai); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in non-blocking mode with DMA. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @param pData Pointer to data buffer + * @param Size Amount of data to be received + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef status; + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + if (hsai->State == HAL_SAI_STATE_READY) + { + uint32_t dmaSrcSize; + + /* Process Locked */ + __HAL_LOCK(hsai); + + hsai->pBuffPtr = pData; + hsai->XferSize = Size; + hsai->XferCount = Size; + hsai->ErrorCode = HAL_SAI_ERROR_NONE; + hsai->State = HAL_SAI_STATE_BUSY_RX; + + /* Set the SAI Rx DMA Half transfer complete callback */ + hsai->hdmarx->XferHalfCpltCallback = SAI_DMARxHalfCplt; + + /* Set the SAI Rx DMA transfer complete callback */ + hsai->hdmarx->XferCpltCallback = SAI_DMARxCplt; + + /* Set the DMA error callback */ + hsai->hdmarx->XferErrorCallback = SAI_DMAError; + + /* Set the DMA Rx abort callback */ + hsai->hdmarx->XferAbortCallback = NULL; + + /* For reception, the DMA source is SAI DR register. + We have to compute DMA size of a source block transfer in bytes according SAI data size. */ + if ((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING)) + { + dmaSrcSize = (uint32_t) Size; + } + else if (hsai->Init.DataSize <= SAI_DATASIZE_16) + { + dmaSrcSize = 2U * (uint32_t) Size; + } + else + { + dmaSrcSize = 4U * (uint32_t) Size; + } + + /* Enable the Rx DMA Stream */ + if ((hsai->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hsai->hdmarx->LinkedListQueue != NULL) + { + /* Set DMA data size */ + hsai->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = dmaSrcSize; + + /* Set DMA source address */ + hsai->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)&hsai->Instance->DR; + + /* Set DMA destination address */ + hsai->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)hsai->pBuffPtr; + + status = HAL_DMAEx_List_Start_IT(hsai->hdmarx); + } + else + { + __HAL_UNLOCK(hsai); + return HAL_ERROR; + } + } + else + { + status = HAL_DMA_Start_IT(hsai->hdmarx, (uint32_t)&hsai->Instance->DR, (uint32_t)hsai->pBuffPtr, dmaSrcSize); + } + + if (status != HAL_OK) + { + __HAL_UNLOCK(hsai); + return HAL_ERROR; + } + + /* Enable the interrupts for error handling */ + __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA)); + + /* Enable SAI Rx DMA Request */ + hsai->Instance->CR1 |= SAI_xCR1_DMAEN; + + /* Check if the SAI is already enabled */ + if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U) + { + /* Enable SAI peripheral */ + __HAL_SAI_ENABLE(hsai); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hsai); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Enable the Tx mute mode. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @param val value sent during the mute @ref SAI_Block_Mute_Value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val) +{ + assert_param(IS_SAI_BLOCK_MUTE_VALUE(val)); + + if (hsai->State != HAL_SAI_STATE_RESET) + { + CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTEVAL | SAI_xCR2_MUTE); + SET_BIT(hsai->Instance->CR2, SAI_xCR2_MUTE | (uint32_t)val); + return HAL_OK; + } + return HAL_ERROR; +} + +/** + * @brief Disable the Tx mute mode. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode(SAI_HandleTypeDef *hsai) +{ + if (hsai->State != HAL_SAI_STATE_RESET) + { + CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTEVAL | SAI_xCR2_MUTE); + return HAL_OK; + } + return HAL_ERROR; +} + +/** + * @brief Enable the Rx mute detection. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @param callback function called when the mute is detected. + * @param counter number a data before mute detection max 63. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter) +{ + assert_param(IS_SAI_BLOCK_MUTE_COUNTER(counter)); + + if (hsai->State != HAL_SAI_STATE_RESET) + { + /* set the mute counter */ + CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTECNT); + SET_BIT(hsai->Instance->CR2, (uint32_t)((uint32_t)counter << SAI_xCR2_MUTECNT_Pos)); + hsai->mutecallback = callback; + /* enable the IT interrupt */ + __HAL_SAI_ENABLE_IT(hsai, SAI_IT_MUTEDET); + return HAL_OK; + } + return HAL_ERROR; +} + +/** + * @brief Disable the Rx mute detection. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SAI_DisableRxMuteMode(SAI_HandleTypeDef *hsai) +{ + if (hsai->State != HAL_SAI_STATE_RESET) + { + /* set the mutecallback to NULL */ + hsai->mutecallback = NULL; + /* enable the IT interrupt */ + __HAL_SAI_DISABLE_IT(hsai, SAI_IT_MUTEDET); + return HAL_OK; + } + return HAL_ERROR; +} + +/** + * @brief Handle SAI interrupt request. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @retval None + */ +void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai) +{ + if (hsai->State != HAL_SAI_STATE_RESET) + { + uint32_t itflags = hsai->Instance->SR; + uint32_t itsources = hsai->Instance->IMR; + uint32_t cr1config = hsai->Instance->CR1; + uint32_t tmperror; + + /* SAI Fifo request interrupt occurred -----------------------------------*/ + if (((itflags & SAI_xSR_FREQ) == SAI_xSR_FREQ) && ((itsources & SAI_IT_FREQ) == SAI_IT_FREQ)) + { + hsai->InterruptServiceRoutine(hsai); + } + /* SAI Overrun error interrupt occurred ----------------------------------*/ + else if (((itflags & SAI_FLAG_OVRUDR) == SAI_FLAG_OVRUDR) && ((itsources & SAI_IT_OVRUDR) == SAI_IT_OVRUDR)) + { + /* Clear the SAI Overrun flag */ + __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR); + /* Get the SAI error code */ + tmperror = ((hsai->State == HAL_SAI_STATE_BUSY_RX) ? HAL_SAI_ERROR_OVR : HAL_SAI_ERROR_UDR); + /* Change the SAI error code */ + hsai->ErrorCode |= tmperror; + /* the transfer is not stopped, we will forward the information to the user and we let + the user decide what needs to be done */ +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->ErrorCallback(hsai); +#else + HAL_SAI_ErrorCallback(hsai); +#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ + } + /* SAI mutedet interrupt occurred ----------------------------------*/ + else if (((itflags & SAI_FLAG_MUTEDET) == SAI_FLAG_MUTEDET) && ((itsources & SAI_IT_MUTEDET) == SAI_IT_MUTEDET)) + { + /* Clear the SAI mutedet flag */ + __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_MUTEDET); + /* call the call back function */ + if (hsai->mutecallback != NULL) + { + /* inform the user that an RX mute event has been detected */ + hsai->mutecallback(); + } + } + /* SAI AFSDET interrupt occurred ----------------------------------*/ + else if (((itflags & SAI_FLAG_AFSDET) == SAI_FLAG_AFSDET) && ((itsources & SAI_IT_AFSDET) == SAI_IT_AFSDET)) + { + /* Clear the SAI AFSDET flag */ + __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_AFSDET); + + /* Change the SAI error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_AFSDET; + + /* Check SAI DMA is enabled or not */ + if ((cr1config & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN) + { + /* Abort the SAI DMA Streams */ + if (hsai->hdmatx != NULL) + { + /* Set the DMA Tx abort callback */ + hsai->hdmatx->XferAbortCallback = SAI_DMAAbort; + + /* Abort DMA in IT mode */ + if (HAL_DMA_Abort_IT(hsai->hdmatx) != HAL_OK) + { + /* Update SAI error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_DMA; + + /* Call SAI error callback */ +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->ErrorCallback(hsai); +#else + HAL_SAI_ErrorCallback(hsai); +#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ + } + } + if (hsai->hdmarx != NULL) + { + /* Set the DMA Rx abort callback */ + hsai->hdmarx->XferAbortCallback = SAI_DMAAbort; + + /* Abort DMA in IT mode */ + if (HAL_DMA_Abort_IT(hsai->hdmarx) != HAL_OK) + { + /* Update SAI error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_DMA; + + /* Call SAI error callback */ +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->ErrorCallback(hsai); +#else + HAL_SAI_ErrorCallback(hsai); +#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ + } + } + } + else + { + /* Abort SAI */ + /* No need to check return value because HAL_SAI_ErrorCallback will be called later */ + (void) HAL_SAI_Abort(hsai); + + /* Set error callback */ +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->ErrorCallback(hsai); +#else + HAL_SAI_ErrorCallback(hsai); +#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ + } + } + /* SAI LFSDET interrupt occurred ----------------------------------*/ + else if (((itflags & SAI_FLAG_LFSDET) == SAI_FLAG_LFSDET) && ((itsources & SAI_IT_LFSDET) == SAI_IT_LFSDET)) + { + /* Clear the SAI LFSDET flag */ + __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_LFSDET); + + /* Change the SAI error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_LFSDET; + + /* Check SAI DMA is enabled or not */ + if ((cr1config & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN) + { + /* Abort the SAI DMA Streams */ + if (hsai->hdmatx != NULL) + { + /* Set the DMA Tx abort callback */ + hsai->hdmatx->XferAbortCallback = SAI_DMAAbort; + + /* Abort DMA in IT mode */ + if (HAL_DMA_Abort_IT(hsai->hdmatx) != HAL_OK) + { + /* Update SAI error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_DMA; + + /* Call SAI error callback */ +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->ErrorCallback(hsai); +#else + HAL_SAI_ErrorCallback(hsai); +#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ + } + } + if (hsai->hdmarx != NULL) + { + /* Set the DMA Rx abort callback */ + hsai->hdmarx->XferAbortCallback = SAI_DMAAbort; + + /* Abort DMA in IT mode */ + if (HAL_DMA_Abort_IT(hsai->hdmarx) != HAL_OK) + { + /* Update SAI error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_DMA; + + /* Call SAI error callback */ +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->ErrorCallback(hsai); +#else + HAL_SAI_ErrorCallback(hsai); +#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ + } + } + } + else + { + /* Abort SAI */ + /* No need to check return value because HAL_SAI_ErrorCallback will be called later */ + (void) HAL_SAI_Abort(hsai); + + /* Set error callback */ +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->ErrorCallback(hsai); +#else + HAL_SAI_ErrorCallback(hsai); +#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ + } + } + /* SAI WCKCFG interrupt occurred ----------------------------------*/ + else if (((itflags & SAI_FLAG_WCKCFG) == SAI_FLAG_WCKCFG) && ((itsources & SAI_IT_WCKCFG) == SAI_IT_WCKCFG)) + { + /* Clear the SAI WCKCFG flag */ + __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_WCKCFG); + + /* Change the SAI error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_WCKCFG; + + /* Check SAI DMA is enabled or not */ + if ((cr1config & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN) + { + /* Abort the SAI DMA Streams */ + if (hsai->hdmatx != NULL) + { + /* Set the DMA Tx abort callback */ + hsai->hdmatx->XferAbortCallback = SAI_DMAAbort; + + /* Abort DMA in IT mode */ + if (HAL_DMA_Abort_IT(hsai->hdmatx) != HAL_OK) + { + /* Update SAI error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_DMA; + + /* Call SAI error callback */ +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->ErrorCallback(hsai); +#else + HAL_SAI_ErrorCallback(hsai); +#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ + } + } + if (hsai->hdmarx != NULL) + { + /* Set the DMA Rx abort callback */ + hsai->hdmarx->XferAbortCallback = SAI_DMAAbort; + + /* Abort DMA in IT mode */ + if (HAL_DMA_Abort_IT(hsai->hdmarx) != HAL_OK) + { + /* Update SAI error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_DMA; + + /* Call SAI error callback */ +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->ErrorCallback(hsai); +#else + HAL_SAI_ErrorCallback(hsai); +#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ + } + } + } + else + { + /* If WCKCFG occurs, SAI audio block is automatically disabled */ + /* Disable all interrupts and clear all flags */ + hsai->Instance->IMR = 0U; + hsai->Instance->CLRFR = 0xFFFFFFFFU; + /* Set the SAI state to ready to be able to start again the process */ + hsai->State = HAL_SAI_STATE_READY; + + /* Initialize XferCount */ + hsai->XferCount = 0U; + + /* SAI error callback */ +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->ErrorCallback(hsai); +#else + HAL_SAI_ErrorCallback(hsai); +#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ + } + } + /* SAI CNRDY interrupt occurred ----------------------------------*/ + else if (((itflags & SAI_FLAG_CNRDY) == SAI_FLAG_CNRDY) && ((itsources & SAI_IT_CNRDY) == SAI_IT_CNRDY)) + { + /* Clear the SAI CNRDY flag */ + __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_CNRDY); + /* Change the SAI error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_CNREADY; + /* the transfer is not stopped, we will forward the information to the user and we let + the user decide what needs to be done */ +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->ErrorCallback(hsai); +#else + HAL_SAI_ErrorCallback(hsai); +#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ + } + else + { + /* Nothing to do */ + } + } +} + +/** + * @brief Tx Transfer completed callback. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @retval None + */ +__weak void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsai); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SAI_TxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Tx Transfer Half completed callback. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @retval None + */ +__weak void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsai); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SAI_TxHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Rx Transfer completed callback. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @retval None + */ +__weak void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsai); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SAI_RxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Rx Transfer half completed callback. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @retval None + */ +__weak void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsai); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SAI_RxHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief SAI error callback. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @retval None + */ +__weak void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsai); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SAI_ErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup SAI_Exported_Functions_Group3 Peripheral State functions + * @brief Peripheral State functions + * +@verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the SAI handle state. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @retval HAL state + */ +HAL_SAI_StateTypeDef HAL_SAI_GetState(const SAI_HandleTypeDef *hsai) +{ + return hsai->State; +} + +/** + * @brief Return the SAI error code. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for the specified SAI Block. + * @retval SAI Error Code + */ +uint32_t HAL_SAI_GetError(const SAI_HandleTypeDef *hsai) +{ + return hsai->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup SAI_Private_Functions + * @brief Private functions + * @{ + */ + +/** + * @brief Initialize the SAI I2S protocol according to the specified parameters + * in the SAI_InitTypeDef and create the associated handle. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @param protocol one of the supported protocol. + * @param datasize one of the supported datasize @ref SAI_Protocol_DataSize. + * @param nbslot number of slot minimum value is 2 and max is 16. + * the value must be a multiple of 2. + * @retval HAL status + */ +static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot) +{ + HAL_StatusTypeDef status = HAL_OK; + + hsai->Init.Protocol = SAI_FREE_PROTOCOL; + hsai->Init.FirstBit = SAI_FIRSTBIT_MSB; + /* Compute ClockStrobing according AudioMode */ + if ((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX)) + { + /* Transmit */ + hsai->Init.ClockStrobing = SAI_CLOCKSTROBING_FALLINGEDGE; + } + else + { + /* Receive */ + hsai->Init.ClockStrobing = SAI_CLOCKSTROBING_RISINGEDGE; + } + hsai->FrameInit.FSDefinition = SAI_FS_CHANNEL_IDENTIFICATION; + hsai->SlotInit.SlotActive = SAI_SLOTACTIVE_ALL; + hsai->SlotInit.FirstBitOffset = 0; + hsai->SlotInit.SlotNumber = nbslot; + + /* in IS2 the number of slot must be even */ + if ((nbslot & 0x1U) != 0U) + { + return HAL_ERROR; + } + + if (protocol == SAI_I2S_STANDARD) + { + hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_LOW; + hsai->FrameInit.FSOffset = SAI_FS_BEFOREFIRSTBIT; + } + else + { + /* SAI_I2S_MSBJUSTIFIED or SAI_I2S_LSBJUSTIFIED */ + hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_HIGH; + hsai->FrameInit.FSOffset = SAI_FS_FIRSTBIT; + } + + /* Frame definition */ + switch (datasize) + { + case SAI_PROTOCOL_DATASIZE_16BIT: + hsai->Init.DataSize = SAI_DATASIZE_16; + hsai->FrameInit.FrameLength = 32U * (nbslot / 2U); + hsai->FrameInit.ActiveFrameLength = 16U * (nbslot / 2U); + hsai->SlotInit.SlotSize = SAI_SLOTSIZE_16B; + break; + case SAI_PROTOCOL_DATASIZE_16BITEXTENDED : + hsai->Init.DataSize = SAI_DATASIZE_16; + hsai->FrameInit.FrameLength = 64U * (nbslot / 2U); + hsai->FrameInit.ActiveFrameLength = 32U * (nbslot / 2U); + hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B; + break; + case SAI_PROTOCOL_DATASIZE_24BIT: + hsai->Init.DataSize = SAI_DATASIZE_24; + hsai->FrameInit.FrameLength = 64U * (nbslot / 2U); + hsai->FrameInit.ActiveFrameLength = 32U * (nbslot / 2U); + hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B; + break; + case SAI_PROTOCOL_DATASIZE_32BIT: + hsai->Init.DataSize = SAI_DATASIZE_32; + hsai->FrameInit.FrameLength = 64U * (nbslot / 2U); + hsai->FrameInit.ActiveFrameLength = 32U * (nbslot / 2U); + hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B; + break; + default : + status = HAL_ERROR; + break; + } + if (protocol == SAI_I2S_LSBJUSTIFIED) + { + if (datasize == SAI_PROTOCOL_DATASIZE_16BITEXTENDED) + { + hsai->SlotInit.FirstBitOffset = 16; + } + if (datasize == SAI_PROTOCOL_DATASIZE_24BIT) + { + hsai->SlotInit.FirstBitOffset = 8; + } + } + return status; +} + +/** + * @brief Initialize the SAI PCM protocol according to the specified parameters + * in the SAI_InitTypeDef and create the associated handle. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @param protocol one of the supported protocol + * @param datasize one of the supported datasize @ref SAI_Protocol_DataSize + * @param nbslot number of slot minimum value is 1 and the max is 16. + * @retval HAL status + */ +static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot) +{ + HAL_StatusTypeDef status = HAL_OK; + + hsai->Init.Protocol = SAI_FREE_PROTOCOL; + hsai->Init.FirstBit = SAI_FIRSTBIT_MSB; + /* Compute ClockStrobing according AudioMode */ + if ((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX)) + { + /* Transmit */ + hsai->Init.ClockStrobing = SAI_CLOCKSTROBING_RISINGEDGE; + } + else + { + /* Receive */ + hsai->Init.ClockStrobing = SAI_CLOCKSTROBING_FALLINGEDGE; + } + hsai->FrameInit.FSDefinition = SAI_FS_STARTFRAME; + hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_HIGH; + hsai->FrameInit.FSOffset = SAI_FS_BEFOREFIRSTBIT; + hsai->SlotInit.FirstBitOffset = 0; + hsai->SlotInit.SlotNumber = nbslot; + hsai->SlotInit.SlotActive = SAI_SLOTACTIVE_ALL; + + if (protocol == SAI_PCM_SHORT) + { + hsai->FrameInit.ActiveFrameLength = 1; + } + else + { + /* SAI_PCM_LONG */ + hsai->FrameInit.ActiveFrameLength = 13; + } + + switch (datasize) + { + case SAI_PROTOCOL_DATASIZE_16BIT: + hsai->Init.DataSize = SAI_DATASIZE_16; + hsai->FrameInit.FrameLength = 16U * nbslot; + hsai->SlotInit.SlotSize = SAI_SLOTSIZE_16B; + break; + case SAI_PROTOCOL_DATASIZE_16BITEXTENDED : + hsai->Init.DataSize = SAI_DATASIZE_16; + hsai->FrameInit.FrameLength = 32U * nbslot; + hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B; + break; + case SAI_PROTOCOL_DATASIZE_24BIT : + hsai->Init.DataSize = SAI_DATASIZE_24; + hsai->FrameInit.FrameLength = 32U * nbslot; + hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B; + break; + case SAI_PROTOCOL_DATASIZE_32BIT: + hsai->Init.DataSize = SAI_DATASIZE_32; + hsai->FrameInit.FrameLength = 32U * nbslot; + hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B; + break; + default : + status = HAL_ERROR; + break; + } + + return status; +} + +/** + * @brief Fill the fifo. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @retval None + */ +static void SAI_FillFifo(SAI_HandleTypeDef *hsai) +{ + uint32_t temp; + + /* fill the fifo with data before to enabled the SAI */ + while (((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_FULL) && (hsai->XferCount > 0U)) + { + if ((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING)) + { + hsai->Instance->DR = *hsai->pBuffPtr; + hsai->pBuffPtr++; + } + else if (hsai->Init.DataSize <= SAI_DATASIZE_16) + { + temp = (uint32_t)(*hsai->pBuffPtr); + hsai->pBuffPtr++; + temp |= ((uint32_t)(*hsai->pBuffPtr) << 8); + hsai->pBuffPtr++; + hsai->Instance->DR = temp; + } + else + { + temp = (uint32_t)(*hsai->pBuffPtr); + hsai->pBuffPtr++; + temp |= ((uint32_t)(*hsai->pBuffPtr) << 8); + hsai->pBuffPtr++; + temp |= ((uint32_t)(*hsai->pBuffPtr) << 16); + hsai->pBuffPtr++; + temp |= ((uint32_t)(*hsai->pBuffPtr) << 24); + hsai->pBuffPtr++; + hsai->Instance->DR = temp; + } + hsai->XferCount--; + } +} + +/** + * @brief Return the interrupt flag to set according the SAI setup. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @param mode SAI_MODE_DMA or SAI_MODE_IT + * @retval the list of the IT flag to enable + */ +static uint32_t SAI_InterruptFlag(const SAI_HandleTypeDef *hsai, SAI_ModeTypedef mode) +{ + uint32_t tmpIT = SAI_IT_OVRUDR; + + if (mode == SAI_MODE_IT) + { + tmpIT |= SAI_IT_FREQ; + } + + if ((hsai->Init.Protocol == SAI_AC97_PROTOCOL) && + ((hsai->Init.AudioMode == SAI_MODESLAVE_RX) || (hsai->Init.AudioMode == SAI_MODEMASTER_RX))) + { + tmpIT |= SAI_IT_CNRDY; + } + + if ((hsai->Init.AudioMode == SAI_MODESLAVE_RX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX)) + { + tmpIT |= SAI_IT_AFSDET | SAI_IT_LFSDET; + } + else + { + /* hsai has been configured in master mode */ + tmpIT |= SAI_IT_WCKCFG; + } + return tmpIT; +} + +/** + * @brief Disable the SAI and wait for the disabling. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @retval None + */ +static HAL_StatusTypeDef SAI_Disable(SAI_HandleTypeDef *hsai) +{ + uint32_t count = SAI_DEFAULT_TIMEOUT * (SystemCoreClock / 7U / 1000U); + HAL_StatusTypeDef status = HAL_OK; + + /* Disable the SAI instance */ + __HAL_SAI_DISABLE(hsai); + + do + { + /* Check for the Timeout */ + if (count == 0U) + { + /* Update error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT; + status = HAL_TIMEOUT; + break; + } + count--; + } while ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) != 0U); + + return status; +} + +/** + * @brief Tx Handler for Transmit in Interrupt mode 8-Bit transfer. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @retval None + */ +static void SAI_Transmit_IT8Bit(SAI_HandleTypeDef *hsai) +{ + if (hsai->XferCount == 0U) + { + /* Handle the end of the transmission */ + /* Disable FREQ and OVRUDR interrupts */ + __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); + hsai->State = HAL_SAI_STATE_READY; +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->TxCpltCallback(hsai); +#else + HAL_SAI_TxCpltCallback(hsai); +#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ + } + else + { + /* Write data on DR register */ + hsai->Instance->DR = *hsai->pBuffPtr; + hsai->pBuffPtr++; + hsai->XferCount--; + } +} + +/** + * @brief Tx Handler for Transmit in Interrupt mode for 16-Bit transfer. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @retval None + */ +static void SAI_Transmit_IT16Bit(SAI_HandleTypeDef *hsai) +{ + if (hsai->XferCount == 0U) + { + /* Handle the end of the transmission */ + /* Disable FREQ and OVRUDR interrupts */ + __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); + hsai->State = HAL_SAI_STATE_READY; +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->TxCpltCallback(hsai); +#else + HAL_SAI_TxCpltCallback(hsai); +#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ + } + else + { + /* Write data on DR register */ + uint32_t temp; + temp = (uint32_t)(*hsai->pBuffPtr); + hsai->pBuffPtr++; + temp |= ((uint32_t)(*hsai->pBuffPtr) << 8); + hsai->pBuffPtr++; + hsai->Instance->DR = temp; + hsai->XferCount--; + } +} + +/** + * @brief Tx Handler for Transmit in Interrupt mode for 32-Bit transfer. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @retval None + */ +static void SAI_Transmit_IT32Bit(SAI_HandleTypeDef *hsai) +{ + if (hsai->XferCount == 0U) + { + /* Handle the end of the transmission */ + /* Disable FREQ and OVRUDR interrupts */ + __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); + hsai->State = HAL_SAI_STATE_READY; +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->TxCpltCallback(hsai); +#else + HAL_SAI_TxCpltCallback(hsai); +#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ + } + else + { + /* Write data on DR register */ + uint32_t temp; + temp = (uint32_t)(*hsai->pBuffPtr); + hsai->pBuffPtr++; + temp |= ((uint32_t)(*hsai->pBuffPtr) << 8); + hsai->pBuffPtr++; + temp |= ((uint32_t)(*hsai->pBuffPtr) << 16); + hsai->pBuffPtr++; + temp |= ((uint32_t)(*hsai->pBuffPtr) << 24); + hsai->pBuffPtr++; + hsai->Instance->DR = temp; + hsai->XferCount--; + } +} + +/** + * @brief Rx Handler for Receive in Interrupt mode 8-Bit transfer. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @retval None + */ +static void SAI_Receive_IT8Bit(SAI_HandleTypeDef *hsai) +{ + /* Receive data */ + *hsai->pBuffPtr = (uint8_t)hsai->Instance->DR; + hsai->pBuffPtr++; + hsai->XferCount--; + + /* Check end of the transfer */ + if (hsai->XferCount == 0U) + { + /* Disable TXE and OVRUDR interrupts */ + __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); + + /* Clear the SAI Overrun flag */ + __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR); + + hsai->State = HAL_SAI_STATE_READY; +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->RxCpltCallback(hsai); +#else + HAL_SAI_RxCpltCallback(hsai); +#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ + } +} + +/** + * @brief Rx Handler for Receive in Interrupt mode for 16-Bit transfer. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @retval None + */ +static void SAI_Receive_IT16Bit(SAI_HandleTypeDef *hsai) +{ + uint32_t temp; + + /* Receive data */ + temp = hsai->Instance->DR; + *hsai->pBuffPtr = (uint8_t)temp; + hsai->pBuffPtr++; + *hsai->pBuffPtr = (uint8_t)(temp >> 8); + hsai->pBuffPtr++; + hsai->XferCount--; + + /* Check end of the transfer */ + if (hsai->XferCount == 0U) + { + /* Disable TXE and OVRUDR interrupts */ + __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); + + /* Clear the SAI Overrun flag */ + __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR); + + hsai->State = HAL_SAI_STATE_READY; +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->RxCpltCallback(hsai); +#else + HAL_SAI_RxCpltCallback(hsai); +#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ + } +} + +/** + * @brief Rx Handler for Receive in Interrupt mode for 32-Bit transfer. + * @param hsai pointer to a SAI_HandleTypeDef structure that contains + * the configuration information for SAI module. + * @retval None + */ +static void SAI_Receive_IT32Bit(SAI_HandleTypeDef *hsai) +{ + uint32_t temp; + + /* Receive data */ + temp = hsai->Instance->DR; + *hsai->pBuffPtr = (uint8_t)temp; + hsai->pBuffPtr++; + *hsai->pBuffPtr = (uint8_t)(temp >> 8); + hsai->pBuffPtr++; + *hsai->pBuffPtr = (uint8_t)(temp >> 16); + hsai->pBuffPtr++; + *hsai->pBuffPtr = (uint8_t)(temp >> 24); + hsai->pBuffPtr++; + hsai->XferCount--; + + /* Check end of the transfer */ + if (hsai->XferCount == 0U) + { + /* Disable TXE and OVRUDR interrupts */ + __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); + + /* Clear the SAI Overrun flag */ + __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR); + + hsai->State = HAL_SAI_STATE_READY; +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->RxCpltCallback(hsai); +#else + HAL_SAI_RxCpltCallback(hsai); +#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ + } +} + +/** + * @brief DMA SAI transmit process complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SAI_DMATxCplt(DMA_HandleTypeDef *hdma) +{ + SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Check if DMA in circular mode */ + if (hdma->Mode != DMA_LINKEDLIST_CIRCULAR) + { + hsai->XferCount = 0; + + /* Disable SAI Tx DMA Request */ + hsai->Instance->CR1 &= (uint32_t)(~SAI_xCR1_DMAEN); + + /* Stop the interrupts error handling */ + __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA)); + + hsai->State = HAL_SAI_STATE_READY; + } + +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->TxCpltCallback(hsai); +#else + HAL_SAI_TxCpltCallback(hsai); +#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SAI transmit process half complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SAI_DMATxHalfCplt(DMA_HandleTypeDef *hdma) +{ + SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->TxHalfCpltCallback(hsai); +#else + HAL_SAI_TxHalfCpltCallback(hsai); +#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SAI receive process complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SAI_DMARxCplt(DMA_HandleTypeDef *hdma) +{ + SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Check if DMA in circular mode*/ + if (hdma->Mode != DMA_LINKEDLIST_CIRCULAR) + { + /* Disable Rx DMA Request */ + hsai->Instance->CR1 &= (uint32_t)(~SAI_xCR1_DMAEN); + hsai->XferCount = 0; + + /* Stop the interrupts error handling */ + __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA)); + + hsai->State = HAL_SAI_STATE_READY; + } + +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->RxCpltCallback(hsai); +#else + HAL_SAI_RxCpltCallback(hsai); +#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SAI receive process half complete callback + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SAI_DMARxHalfCplt(DMA_HandleTypeDef *hdma) +{ + SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->RxHalfCpltCallback(hsai); +#else + HAL_SAI_RxHalfCpltCallback(hsai); +#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SAI communication error callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SAI_DMAError(DMA_HandleTypeDef *hdma) +{ + SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Set SAI error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_DMA; + + /* Disable the SAI DMA request */ + hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN; + + /* Disable SAI peripheral */ + /* No need to check return value because state will be updated and HAL_SAI_ErrorCallback will be called later */ + (void) SAI_Disable(hsai); + + /* Set the SAI state ready to be able to start again the process */ + hsai->State = HAL_SAI_STATE_READY; + + /* Initialize XferCount */ + hsai->XferCount = 0U; + + /* SAI error Callback */ +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->ErrorCallback(hsai); +#else + HAL_SAI_ErrorCallback(hsai); +#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SAI Abort callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SAI_DMAAbort(DMA_HandleTypeDef *hdma) +{ + SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Disable DMA request */ + hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN; + + /* Disable all interrupts and clear all flags */ + hsai->Instance->IMR = 0U; + hsai->Instance->CLRFR = 0xFFFFFFFFU; + + if (hsai->ErrorCode != HAL_SAI_ERROR_WCKCFG) + { + /* Disable SAI peripheral */ + /* No need to check return value because state will be updated and HAL_SAI_ErrorCallback will be called later */ + (void) SAI_Disable(hsai); + + /* Flush the fifo */ + SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH); + } + /* Set the SAI state to ready to be able to start again the process */ + hsai->State = HAL_SAI_STATE_READY; + + /* Initialize XferCount */ + hsai->XferCount = 0U; + + /* SAI error Callback */ +#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) + hsai->ErrorCallback(hsai); +#else + HAL_SAI_ErrorCallback(hsai); +#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ +} + +/** + * @} + */ + +#endif /* HAL_SAI_MODULE_ENABLED */ +/** + * @} + */ +#endif /* SAI1 */ +/** + * @} + */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_sai_ex.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_sai_ex.c new file mode 100644 index 0000000000..092e106794 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_sai_ex.c @@ -0,0 +1,131 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_sai_ex.c + * @author MCD Application Team + * @brief SAI Extended HAL module driver. + * This file provides firmware functions to manage the following + * functionality of the SAI Peripheral Controller: + * + Modify PDM microphone delays. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ +#if defined (SAI1) +#ifdef HAL_SAI_MODULE_ENABLED + +/** @defgroup SAIEx SAIEx + * @brief SAI Extended HAL module driver + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup SAIEx_Private_Defines SAIEx Extended Private Defines + * @{ + */ +#define SAI_PDM_DELAY_MASK 0x77U +#define SAI_PDM_DELAY_OFFSET 8U +#define SAI_PDM_RIGHT_DELAY_OFFSET 4U +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup SAIEx_Exported_Functions SAIEx Extended Exported Functions + * @{ + */ + +/** @defgroup SAIEx_Exported_Functions_Group1 Peripheral Control functions + * @brief SAIEx control functions + * +@verbatim + =============================================================================== + ##### Extended features functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Modify PDM microphone delays + +@endverbatim + * @{ + */ + +/** + * @brief Configure PDM microphone delays. + * @param hsai SAI handle. + * @param pdmMicDelay Microphone delays configuration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay(const SAI_HandleTypeDef *hsai, + const SAIEx_PdmMicDelayParamTypeDef *pdmMicDelay) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t offset; + + /* Check that SAI sub-block is SAI1 sub-block A */ + if (hsai->Instance != SAI1_Block_A) + { + status = HAL_ERROR; + } + else + { + /* Check microphone delay parameters */ + assert_param(IS_SAI_PDM_MIC_PAIRS_NUMBER(pdmMicDelay->MicPair)); + assert_param(IS_SAI_PDM_MIC_DELAY(pdmMicDelay->LeftDelay)); + assert_param(IS_SAI_PDM_MIC_DELAY(pdmMicDelay->RightDelay)); + + /* Compute offset on PDMDLY register according mic pair number */ + offset = SAI_PDM_DELAY_OFFSET * (pdmMicDelay->MicPair - 1U); + + /* Check SAI state and offset */ + if ((hsai->State != HAL_SAI_STATE_RESET) && (offset <= 24U)) + { + /* Reset current delays for specified microphone */ + SAI1->PDMDLY &= ~(SAI_PDM_DELAY_MASK << offset); + + /* Apply new microphone delays */ + SAI1->PDMDLY |= (((pdmMicDelay->RightDelay << SAI_PDM_RIGHT_DELAY_OFFSET) | pdmMicDelay->LeftDelay) << offset); + } + else + { + status = HAL_ERROR; + } + } + return status; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_SAI_MODULE_ENABLED */ +#endif /* SAI1 */ +/** + * @} + */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_smartcard.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_smartcard.c new file mode 100644 index 0000000000..8a293e0bbb --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_smartcard.c @@ -0,0 +1,3267 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_smartcard.c + * @author MCD Application Team + * @brief SMARTCARD HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the SMARTCARD peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State and Error functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The SMARTCARD HAL driver can be used as follows: + + (#) Declare a SMARTCARD_HandleTypeDef handle structure (eg. SMARTCARD_HandleTypeDef hsmartcard). + (#) Associate a USART to the SMARTCARD handle hsmartcard. + (#) Initialize the SMARTCARD low level resources by implementing the HAL_SMARTCARD_MspInit() API: + (++) Enable the USARTx interface clock. + (++) USART pins configuration: + (+++) Enable the clock for the USART GPIOs. + (+++) Configure the USART pins (TX as alternate function pull-up, RX as alternate function Input). + (++) NVIC configuration if you need to use interrupt process (HAL_SMARTCARD_Transmit_IT() + and HAL_SMARTCARD_Receive_IT() APIs): + (+++) Configure the USARTx interrupt priority. + (+++) Enable the NVIC USART IRQ handle. + (++) DMA Configuration if you need to use DMA process (HAL_SMARTCARD_Transmit_DMA() + and HAL_SMARTCARD_Receive_DMA() APIs): + (+++) Declare a DMA handle structure for the Tx/Rx channel. + (+++) Enable the DMAx interface clock. + (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. + (+++) Configure the DMA Tx/Rx channel. + (+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle. + (+++) Configure the priority and enable the NVIC for the transfer complete + interrupt on the DMA Tx/Rx channel. + + (#) Program the Baud Rate, Parity, Mode(Receiver/Transmitter), clock enabling/disabling and accordingly, + the clock parameters (parity, phase, last bit), prescaler value, guard time and NACK on transmission + error enabling or disabling in the hsmartcard handle Init structure. + + (#) If required, program SMARTCARD advanced features (TX/RX pins swap, TimeOut, auto-retry counter,...) + in the hsmartcard handle AdvancedInit structure. + + (#) Initialize the SMARTCARD registers by calling the HAL_SMARTCARD_Init() API: + (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) + by calling the customized HAL_SMARTCARD_MspInit() API. + [..] + (@) The specific SMARTCARD interrupts (Transmission complete interrupt, + RXNE interrupt and Error Interrupts) will be managed using the macros + __HAL_SMARTCARD_ENABLE_IT() and __HAL_SMARTCARD_DISABLE_IT() inside the transmit and receive process. + + [..] + [..] Three operation modes are available within this driver : + + *** Polling mode IO operation *** + ================================= + [..] + (+) Send an amount of data in blocking mode using HAL_SMARTCARD_Transmit() + (+) Receive an amount of data in blocking mode using HAL_SMARTCARD_Receive() + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Send an amount of data in non-blocking mode using HAL_SMARTCARD_Transmit_IT() + (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback() + (+) Receive an amount of data in non-blocking mode using HAL_SMARTCARD_Receive_IT() + (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback() + (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback() + + *** DMA mode IO operation *** + ============================== + [..] + (+) Send an amount of data in non-blocking mode (DMA) using HAL_SMARTCARD_Transmit_DMA() + (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback() + (+) Receive an amount of data in non-blocking mode (DMA) using HAL_SMARTCARD_Receive_DMA() + (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback() + (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback() + + *** SMARTCARD HAL driver macros list *** + ======================================== + [..] + Below the list of most used macros in SMARTCARD HAL driver. + + (+) __HAL_SMARTCARD_GET_FLAG : Check whether or not the specified SMARTCARD flag is set + (+) __HAL_SMARTCARD_CLEAR_FLAG : Clear the specified SMARTCARD pending flag + (+) __HAL_SMARTCARD_ENABLE_IT: Enable the specified SMARTCARD interrupt + (+) __HAL_SMARTCARD_DISABLE_IT: Disable the specified SMARTCARD interrupt + (+) __HAL_SMARTCARD_GET_IT_SOURCE: Check whether or not the specified SMARTCARD interrupt is enabled + + [..] + (@) You can refer to the SMARTCARD HAL driver header file for more useful macros + + ##### Callback registration ##### + ================================== + + [..] + The compilation define USE_HAL_SMARTCARD_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + [..] + Use Function HAL_SMARTCARD_RegisterCallback() to register a user callback. + Function HAL_SMARTCARD_RegisterCallback() allows to register following callbacks: + (+) TxCpltCallback : Tx Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) AbortCpltCallback : Abort Complete Callback. + (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. + (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. + (+) RxFifoFullCallback : Rx Fifo Full Callback. + (+) TxFifoEmptyCallback : Tx Fifo Empty Callback. + (+) MspInitCallback : SMARTCARD MspInit. + (+) MspDeInitCallback : SMARTCARD MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + [..] + Use function HAL_SMARTCARD_UnRegisterCallback() to reset a callback to the default + weak function. + HAL_SMARTCARD_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) TxCpltCallback : Tx Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) AbortCpltCallback : Abort Complete Callback. + (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. + (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. + (+) RxFifoFullCallback : Rx Fifo Full Callback. + (+) TxFifoEmptyCallback : Tx Fifo Empty Callback. + (+) MspInitCallback : SMARTCARD MspInit. + (+) MspDeInitCallback : SMARTCARD MspDeInit. + + [..] + By default, after the HAL_SMARTCARD_Init() and when the state is HAL_SMARTCARD_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback(). + Exception done for MspInit and MspDeInit functions that are respectively + reset to the legacy weak functions in the HAL_SMARTCARD_Init() + and HAL_SMARTCARD_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_SMARTCARD_Init() and HAL_SMARTCARD_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand). + + [..] + Callbacks can be registered/unregistered in HAL_SMARTCARD_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_SMARTCARD_STATE_READY or HAL_SMARTCARD_STATE_RESET state, thus registered (user) + MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_SMARTCARD_RegisterCallback() before calling HAL_SMARTCARD_DeInit() + or HAL_SMARTCARD_Init() function. + + [..] + When The compilation define USE_HAL_SMARTCARD_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available + and weak callbacks are used. + + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @defgroup SMARTCARD SMARTCARD + * @brief HAL SMARTCARD module driver + * @{ + */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants + * @{ + */ +#define SMARTCARD_TEACK_REACK_TIMEOUT 1000U /*!< SMARTCARD TX or RX enable acknowledge time-out value */ + +#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | \ + USART_CR1_RE | USART_CR1_OVER8| \ + USART_CR1_FIFOEN)) /*!< USART CR1 fields of parameters set by SMARTCARD_SetConfig API */ + +#define USART_CR2_CLK_FIELDS ((uint32_t)(USART_CR2_CLKEN | USART_CR2_CPOL | \ + USART_CR2_CPHA | USART_CR2_LBCL)) /*!< SMARTCARD clock-related USART CR2 fields of parameters */ + +#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_RTOEN | USART_CR2_CLK_FIELDS | \ + USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by SMARTCARD_SetConfig API */ + +#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_ONEBIT | USART_CR3_NACK | USART_CR3_SCARCNT | \ + USART_CR3_TXFTCFG | USART_CR3_RXFTCFG )) /*!< USART CR3 fields of parameters set by SMARTCARD_SetConfig API */ + +#define USART_BRR_MIN 0x10U /*!< USART BRR minimum authorized value */ + +#define USART_BRR_MAX 0x0000FFFFU /*!< USART BRR maximum authorized value */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup SMARTCARD_Private_Functions + * @{ + */ +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) +void SMARTCARD_InitCallbacksToDefault(SMARTCARD_HandleTypeDef *hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ +static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard); +static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard); +static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard); +static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, + FlagStatus Status, uint32_t Tickstart, uint32_t Timeout); +static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsmartcard); +static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsmartcard); +#if defined(HAL_DMA_MODULE_ENABLED) +static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma); +static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma); +static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma); +static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma); +static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma); +static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma); +static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma); +static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma); +#endif /* HAL_DMA_MODULE_ENABLED */ +static void SMARTCARD_TxISR(SMARTCARD_HandleTypeDef *hsmartcard); +static void SMARTCARD_TxISR_FIFOEN(SMARTCARD_HandleTypeDef *hsmartcard); +static void SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard); +static void SMARTCARD_RxISR(SMARTCARD_HandleTypeDef *hsmartcard); +static void SMARTCARD_RxISR_FIFOEN(SMARTCARD_HandleTypeDef *hsmartcard); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup SMARTCARD_Exported_Functions SMARTCARD Exported Functions + * @{ + */ + +/** @defgroup SMARTCARD_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and Configuration functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to initialize the USARTx + associated to the SmartCard. + (+) These parameters can be configured: + (++) Baud Rate + (++) Parity: parity should be enabled, frame Length is fixed to 8 bits plus parity + (++) Receiver/transmitter modes + (++) Synchronous mode (and if enabled, phase, polarity and last bit parameters) + (++) Prescaler value + (++) Guard bit time + (++) NACK enabling or disabling on transmission error + + (+) The following advanced features can be configured as well: + (++) TX and/or RX pin level inversion + (++) data logical level inversion + (++) RX and TX pins swap + (++) RX overrun detection disabling + (++) DMA disabling on RX error + (++) MSB first on communication line + (++) Time out enabling (and if activated, timeout value) + (++) Block length + (++) Auto-retry counter + [..] + The HAL_SMARTCARD_Init() API follows the USART synchronous configuration procedures + (details for the procedures are available in reference manual). + +@endverbatim + + The USART frame format is given in the following table: + + Table 1. USART frame format. + +---------------------------------------------------------------+ + | M1M0 bits | PCE bit | USART frame | + |-----------------------|---------------------------------------| + | 01 | 1 | | SB | 8 bit data | PB | STB | | + +---------------------------------------------------------------+ + + + * @{ + */ + +/** + * @brief Initialize the SMARTCARD mode according to the specified + * parameters in the SMARTCARD_HandleTypeDef and initialize the associated handle. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Check the SMARTCARD handle allocation */ + if (hsmartcard == NULL) + { + return HAL_ERROR; + } + + /* Check the USART associated to the SMARTCARD handle */ + assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance)); + + if (hsmartcard->gState == HAL_SMARTCARD_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hsmartcard->Lock = HAL_UNLOCKED; + +#if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1 + SMARTCARD_InitCallbacksToDefault(hsmartcard); + + if (hsmartcard->MspInitCallback == NULL) + { + hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit; + } + + /* Init the low level hardware */ + hsmartcard->MspInitCallback(hsmartcard); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_SMARTCARD_MspInit(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ + } + + hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY; + + /* Disable the Peripheral to set smartcard mode */ + CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); + + /* In SmartCard mode, the following bits must be kept cleared: + - LINEN in the USART_CR2 register, + - HDSEL and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(hsmartcard->Instance->CR2, USART_CR2_LINEN); + CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN)); + + /* set the USART in SMARTCARD mode */ + SET_BIT(hsmartcard->Instance->CR3, USART_CR3_SCEN); + + /* Set the SMARTCARD Communication parameters */ + if (SMARTCARD_SetConfig(hsmartcard) == HAL_ERROR) + { + return HAL_ERROR; + } + + /* Set the SMARTCARD transmission completion indication */ + SMARTCARD_TRANSMISSION_COMPLETION_SETTING(hsmartcard); + + if (hsmartcard->AdvancedInit.AdvFeatureInit != SMARTCARD_ADVFEATURE_NO_INIT) + { + SMARTCARD_AdvFeatureConfig(hsmartcard); + } + + /* Enable the Peripheral */ + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); + + /* TEACK and/or REACK to check before moving hsmartcard->gState and hsmartcard->RxState to Ready */ + return (SMARTCARD_CheckIdleState(hsmartcard)); +} + +/** + * @brief DeInitialize the SMARTCARD peripheral. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Check the SMARTCARD handle allocation */ + if (hsmartcard == NULL) + { + return HAL_ERROR; + } + + /* Check the USART/UART associated to the SMARTCARD handle */ + assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance)); + + hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY; + + /* Disable the Peripheral */ + CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); + + WRITE_REG(hsmartcard->Instance->CR1, 0x0U); + WRITE_REG(hsmartcard->Instance->CR2, 0x0U); + WRITE_REG(hsmartcard->Instance->CR3, 0x0U); + WRITE_REG(hsmartcard->Instance->RTOR, 0x0U); + WRITE_REG(hsmartcard->Instance->GTPR, 0x0U); + + /* DeInit the low level hardware */ +#if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1 + if (hsmartcard->MspDeInitCallback == NULL) + { + hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit; + } + /* DeInit the low level hardware */ + hsmartcard->MspDeInitCallback(hsmartcard); +#else + HAL_SMARTCARD_MspDeInit(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ + + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; + hsmartcard->gState = HAL_SMARTCARD_STATE_RESET; + hsmartcard->RxState = HAL_SMARTCARD_STATE_RESET; + + /* Process Unlock */ + __HAL_UNLOCK(hsmartcard); + + return HAL_OK; +} + +/** + * @brief Initialize the SMARTCARD MSP. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval None + */ +__weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsmartcard); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMARTCARD_MspInit can be implemented in the user file + */ +} + +/** + * @brief DeInitialize the SMARTCARD MSP. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval None + */ +__weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsmartcard); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMARTCARD_MspDeInit can be implemented in the user file + */ +} + +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User SMARTCARD Callback + * To be used to override the weak predefined callback + * @note The HAL_SMARTCARD_RegisterCallback() may be called before HAL_SMARTCARD_Init() + * in HAL_SMARTCARD_STATE_RESET to register callbacks for HAL_SMARTCARD_MSPINIT_CB_ID + * and HAL_SMARTCARD_MSPDEINIT_CB_ID + * @param hsmartcard smartcard handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_SMARTCARD_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_SMARTCARD_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_SMARTCARD_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_SMARTCARD_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + * @arg @ref HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID + * @arg @ref HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID + * @arg @ref HAL_SMARTCARD_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID + * @arg @ref HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID + * @arg @ref HAL_SMARTCARD_MSPINIT_CB_ID MspInit Callback ID + * @arg @ref HAL_SMARTCARD_MSPDEINIT_CB_ID MspDeInit Callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, + HAL_SMARTCARD_CallbackIDTypeDef CallbackID, + pSMARTCARD_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) + { + switch (CallbackID) + { + + case HAL_SMARTCARD_TX_COMPLETE_CB_ID : + hsmartcard->TxCpltCallback = pCallback; + break; + + case HAL_SMARTCARD_RX_COMPLETE_CB_ID : + hsmartcard->RxCpltCallback = pCallback; + break; + + case HAL_SMARTCARD_ERROR_CB_ID : + hsmartcard->ErrorCallback = pCallback; + break; + + case HAL_SMARTCARD_ABORT_COMPLETE_CB_ID : + hsmartcard->AbortCpltCallback = pCallback; + break; + + case HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID : + hsmartcard->AbortTransmitCpltCallback = pCallback; + break; + + case HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID : + hsmartcard->AbortReceiveCpltCallback = pCallback; + break; + + case HAL_SMARTCARD_RX_FIFO_FULL_CB_ID : + hsmartcard->RxFifoFullCallback = pCallback; + break; + + case HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID : + hsmartcard->TxFifoEmptyCallback = pCallback; + break; + + case HAL_SMARTCARD_MSPINIT_CB_ID : + hsmartcard->MspInitCallback = pCallback; + break; + + case HAL_SMARTCARD_MSPDEINIT_CB_ID : + hsmartcard->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hsmartcard->gState == HAL_SMARTCARD_STATE_RESET) + { + switch (CallbackID) + { + case HAL_SMARTCARD_MSPINIT_CB_ID : + hsmartcard->MspInitCallback = pCallback; + break; + + case HAL_SMARTCARD_MSPDEINIT_CB_ID : + hsmartcard->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister an SMARTCARD callback + * SMARTCARD callback is redirected to the weak predefined callback + * @note The HAL_SMARTCARD_UnRegisterCallback() may be called before HAL_SMARTCARD_Init() + * in HAL_SMARTCARD_STATE_RESET to un-register callbacks for HAL_SMARTCARD_MSPINIT_CB_ID + * and HAL_SMARTCARD_MSPDEINIT_CB_ID + * @param hsmartcard smartcard handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_SMARTCARD_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_SMARTCARD_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_SMARTCARD_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_SMARTCARD_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + * @arg @ref HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID + * @arg @ref HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID + * @arg @ref HAL_SMARTCARD_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID + * @arg @ref HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID + * @arg @ref HAL_SMARTCARD_MSPINIT_CB_ID MspInit Callback ID + * @arg @ref HAL_SMARTCARD_MSPDEINIT_CB_ID MspDeInit Callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, + HAL_SMARTCARD_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (HAL_SMARTCARD_STATE_READY == hsmartcard->gState) + { + switch (CallbackID) + { + case HAL_SMARTCARD_TX_COMPLETE_CB_ID : + hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */ + break; + + case HAL_SMARTCARD_RX_COMPLETE_CB_ID : + hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */ + break; + + case HAL_SMARTCARD_ERROR_CB_ID : + hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_SMARTCARD_ABORT_COMPLETE_CB_ID : + hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + break; + + case HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID : + hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak + AbortTransmitCpltCallback*/ + break; + + case HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID : + hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak + AbortReceiveCpltCallback */ + break; + + case HAL_SMARTCARD_RX_FIFO_FULL_CB_ID : + hsmartcard->RxFifoFullCallback = HAL_SMARTCARDEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */ + break; + + case HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID : + hsmartcard->TxFifoEmptyCallback = HAL_SMARTCARDEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ + break; + + case HAL_SMARTCARD_MSPINIT_CB_ID : + hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit; /* Legacy weak MspInitCallback */ + break; + + case HAL_SMARTCARD_MSPDEINIT_CB_ID : + hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit; /* Legacy weak MspDeInitCallback */ + break; + + default : + /* Update the error code */ + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_SMARTCARD_STATE_RESET == hsmartcard->gState) + { + switch (CallbackID) + { + case HAL_SMARTCARD_MSPINIT_CB_ID : + hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit; + break; + + case HAL_SMARTCARD_MSPDEINIT_CB_ID : + hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit; + break; + + default : + /* Update the error code */ + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup SMARTCARD_Exported_Functions_Group2 IO operation functions + * @brief SMARTCARD Transmit and Receive functions + * +@verbatim + ============================================================================== + ##### IO operation functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to manage the SMARTCARD data transfers. + + [..] + Smartcard is a single wire half duplex communication protocol. + The Smartcard interface is designed to support asynchronous protocol Smartcards as + defined in the ISO 7816-3 standard. The USART should be configured as: + (+) 8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register + (+) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register. + + [..] + (#) There are two modes of transfer: + (##) Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (##) Non-Blocking mode: The communication is performed using Interrupts + or DMA, the relevant API's return the HAL status. + The end of the data processing will be indicated through the + dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + (##) The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks + will be executed respectively at the end of the Transmit or Receive process + The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication + error is detected. + + (#) Blocking mode APIs are : + (##) HAL_SMARTCARD_Transmit() + (##) HAL_SMARTCARD_Receive() + + (#) Non Blocking mode APIs with Interrupt are : + (##) HAL_SMARTCARD_Transmit_IT() + (##) HAL_SMARTCARD_Receive_IT() + (##) HAL_SMARTCARD_IRQHandler() + + (#) Non Blocking mode functions with DMA are : + (##) HAL_SMARTCARD_Transmit_DMA() + (##) HAL_SMARTCARD_Receive_DMA() + + (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: + (##) HAL_SMARTCARD_TxCpltCallback() + (##) HAL_SMARTCARD_RxCpltCallback() + (##) HAL_SMARTCARD_ErrorCallback() + + [..] + (#) Non-Blocking mode transfers could be aborted using Abort API's : + (##) HAL_SMARTCARD_Abort() + (##) HAL_SMARTCARD_AbortTransmit() + (##) HAL_SMARTCARD_AbortReceive() + (##) HAL_SMARTCARD_Abort_IT() + (##) HAL_SMARTCARD_AbortTransmit_IT() + (##) HAL_SMARTCARD_AbortReceive_IT() + + (#) For Abort services based on interrupts (HAL_SMARTCARD_Abortxxx_IT), + a set of Abort Complete Callbacks are provided: + (##) HAL_SMARTCARD_AbortCpltCallback() + (##) HAL_SMARTCARD_AbortTransmitCpltCallback() + (##) HAL_SMARTCARD_AbortReceiveCpltCallback() + + (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. + Errors are handled as follows : + (##) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is + to be evaluated by user : this concerns Frame Error, + Parity Error or Noise Error in Interrupt mode reception . + Received character is then retrieved and stored in Rx buffer, + Error code is set to allow user to identify error type, + and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side. + If user wants to abort it, Abort services should be called by user. + (##) Error is considered as Blocking : Transfer could not be completed properly and is aborted. + This concerns Frame Error in Interrupt mode transmission, Overrun Error in Interrupt + mode reception and all errors in DMA mode. + Error code is set to allow user to identify error type, + and HAL_SMARTCARD_ErrorCallback() user callback is executed. + +@endverbatim + * @{ + */ + +/** + * @brief Send an amount of data in blocking mode. + * @note When FIFO mode is enabled, writing a data in the TDR register adds one + * data to the TXFIFO. Write operations to the TDR register are performed + * when TXFNF flag is set. From hardware perspective, TXFNF flag and + * TXE are mapped on the same bit-field. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @param pData pointer to data buffer. + * @param Size amount of data to be sent. + * @param Timeout Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size, + uint32_t Timeout) +{ + uint32_t tickstart; + const uint8_t *ptmpdata = pData; + + /* Check that a Tx process is not already ongoing */ + if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) + { + if ((ptmpdata == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hsmartcard); + + hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + /* Disable the Peripheral first to update mode for TX master */ + CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); + + /* In case of TX only mode, if NACK is enabled, the USART must be able to monitor + the bidirectional line to detect a NACK signal in case of parity error. + Therefore, the receiver block must be enabled as well (RE bit must be set). */ + if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX) + && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) + { + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); + } + /* Enable Tx */ + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE); + + /* Enable the Peripheral */ + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); + + /* Perform a TX/RX FIFO Flush */ + __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard); + + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; + hsmartcard->TxXferSize = Size; + hsmartcard->TxXferCount = Size; + + while (hsmartcard->TxXferCount > 0U) + { + hsmartcard->TxXferCount--; + if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + hsmartcard->Instance->TDR = (uint8_t)(*ptmpdata & 0xFFU); + ptmpdata++; + } + if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_TRANSMISSION_COMPLETION_FLAG(hsmartcard), RESET, + tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Disable the Peripheral first to update mode */ + CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); + if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX) + && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) + { + /* In case of TX only mode, if NACK is enabled, receiver block has been enabled + for Transmit phase. Disable this receiver block. */ + CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); + } + if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX) + || (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) + { + /* Perform a TX FIFO Flush at end of Tx phase, as all sent bytes are appearing in Rx Data register */ + __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard); + } + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); + + /* At end of Tx process, restore hsmartcard->gState to Ready */ + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in blocking mode. + * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO + * is not empty. Read operations from the RDR register are performed when + * RXFNE flag is set. From hardware perspective, RXFNE flag and + * RXNE are mapped on the same bit-field. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @param pData pointer to data buffer. + * @param Size amount of data to be received. + * @param Timeout Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, + uint32_t Timeout) +{ + uint32_t tickstart; + uint8_t *ptmpdata = pData; + + /* Check that a Rx process is not already ongoing */ + if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY) + { + if ((ptmpdata == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hsmartcard); + + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; + hsmartcard->RxState = HAL_SMARTCARD_STATE_BUSY_RX; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + hsmartcard->RxXferSize = Size; + hsmartcard->RxXferCount = Size; + + /* Check the remain data to be received */ + while (hsmartcard->RxXferCount > 0U) + { + hsmartcard->RxXferCount--; + + if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + *ptmpdata = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0x00FF); + ptmpdata++; + } + + /* At end of Rx process, restore hsmartcard->RxState to Ready */ + hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Send an amount of data in interrupt mode. + * @note When FIFO mode is disabled, USART interrupt is generated whenever + * USART_TDR register is empty, i.e one interrupt per data to transmit. + * @note When FIFO mode is enabled, USART interrupt is generated whenever + * TXFIFO threshold reached. In that case the interrupt rate depends on + * TXFIFO threshold configuration. + * @note This function sets the hsmartcard->TxIsr function pointer according to + * the FIFO mode (data transmission processing depends on FIFO mode). + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @param pData pointer to data buffer. + * @param Size amount of data to be sent. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size) +{ + /* Check that a Tx process is not already ongoing */ + if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hsmartcard); + + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; + hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX; + + hsmartcard->pTxBuffPtr = pData; + hsmartcard->TxXferSize = Size; + hsmartcard->TxXferCount = Size; + hsmartcard->TxISR = NULL; + + /* Disable the Peripheral first to update mode for TX master */ + CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); + + /* In case of TX only mode, if NACK is enabled, the USART must be able to monitor + the bidirectional line to detect a NACK signal in case of parity error. + Therefore, the receiver block must be enabled as well (RE bit must be set). */ + if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX) + && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) + { + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); + } + /* Enable Tx */ + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE); + + /* Enable the Peripheral */ + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); + + /* Perform a TX/RX FIFO Flush */ + __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard); + + /* Configure Tx interrupt processing */ + if (hsmartcard->FifoMode == SMARTCARD_FIFOMODE_ENABLE) + { + /* Set the Tx ISR function pointer */ + hsmartcard->TxISR = SMARTCARD_TxISR_FIFOEN; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + /* Enable the SMARTCARD Error Interrupt: (Frame error) */ + SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); + + /* Enable the TX FIFO threshold interrupt */ + SET_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTIE); + } + else + { + /* Set the Tx ISR function pointer */ + hsmartcard->TxISR = SMARTCARD_TxISR; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + /* Enable the SMARTCARD Error Interrupt: (Frame error) */ + SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); + + /* Enable the SMARTCARD Transmit Data Register Empty Interrupt */ + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in interrupt mode. + * @note When FIFO mode is disabled, USART interrupt is generated whenever + * USART_RDR register can be read, i.e one interrupt per data to receive. + * @note When FIFO mode is enabled, USART interrupt is generated whenever + * RXFIFO threshold reached. In that case the interrupt rate depends on + * RXFIFO threshold configuration. + * @note This function sets the hsmartcard->RxIsr function pointer according to + * the FIFO mode (data reception processing depends on FIFO mode). + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @param pData pointer to data buffer. + * @param Size amount of data to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size) +{ + /* Check that a Rx process is not already ongoing */ + if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hsmartcard); + + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; + hsmartcard->RxState = HAL_SMARTCARD_STATE_BUSY_RX; + + hsmartcard->pRxBuffPtr = pData; + hsmartcard->RxXferSize = Size; + hsmartcard->RxXferCount = Size; + + /* Configure Rx interrupt processing */ + if ((hsmartcard->FifoMode == SMARTCARD_FIFOMODE_ENABLE) && (Size >= hsmartcard->NbRxDataToProcess)) + { + /* Set the Rx ISR function pointer */ + hsmartcard->RxISR = SMARTCARD_RxISR_FIFOEN; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + /* Enable the SMARTCART Parity Error interrupt and RX FIFO Threshold interrupt */ + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE); + SET_BIT(hsmartcard->Instance->CR3, USART_CR3_RXFTIE); + } + else + { + /* Set the Rx ISR function pointer */ + hsmartcard->RxISR = SMARTCARD_RxISR; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + /* Enable the SMARTCARD Parity Error and Data Register not empty Interrupts */ + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); + } + + /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Send an amount of data in DMA mode. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @param pData pointer to data buffer. + * @param Size amount of data to be sent. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef status; + + /* Check that a Tx process is not already ongoing */ + if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hsmartcard); + + hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX; + + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; + hsmartcard->pTxBuffPtr = pData; + hsmartcard->TxXferSize = Size; + hsmartcard->TxXferCount = Size; + + /* Disable the Peripheral first to update mode for TX master */ + CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); + + /* In case of TX only mode, if NACK is enabled, the USART must be able to monitor + the bidirectional line to detect a NACK signal in case of parity error. + Therefore, the receiver block must be enabled as well (RE bit must be set). */ + if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX) + && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) + { + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); + } + /* Enable Tx */ + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE); + + /* Enable the Peripheral */ + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); + + /* Perform a TX/RX FIFO Flush */ + __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard); + + /* Set the SMARTCARD DMA transfer complete callback */ + hsmartcard->hdmatx->XferCpltCallback = SMARTCARD_DMATransmitCplt; + + /* Set the SMARTCARD error callback */ + hsmartcard->hdmatx->XferErrorCallback = SMARTCARD_DMAError; + + /* Set the DMA abort callback */ + hsmartcard->hdmatx->XferAbortCallback = NULL; + + /* Check linked list mode */ + if ((hsmartcard->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if ((hsmartcard->hdmatx->LinkedListQueue != NULL) && (hsmartcard->hdmatx->LinkedListQueue->Head != NULL)) + { + /* Set DMA data size */ + hsmartcard->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = Size; + + /* Set DMA source address */ + hsmartcard->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = + (uint32_t)hsmartcard->pTxBuffPtr; + + /* Set DMA destination address */ + hsmartcard->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = + (uint32_t)&hsmartcard->Instance->TDR; + + /* Enable the SMARTCARD transmit DMA channel */ + status = HAL_DMAEx_List_Start_IT(hsmartcard->hdmatx); + } + else + { + /* Update status */ + status = HAL_ERROR; + } + } + else + { + /* Enable the SMARTCARD transmit DMA channel */ + status = HAL_DMA_Start_IT(hsmartcard->hdmatx, (uint32_t)hsmartcard->pTxBuffPtr, + (uint32_t)&hsmartcard->Instance->TDR, Size); + } + + if (status == HAL_OK) + { + /* Clear the TC flag in the ICR register */ + CLEAR_BIT(hsmartcard->Instance->ICR, USART_ICR_TCCF); + + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + /* Enable the UART Error Interrupt: (Frame error) */ + SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); + + /* Enable the DMA transfer for transmit request by setting the DMAT bit + in the SMARTCARD associated USART CR3 register */ + SET_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); + + return HAL_OK; + } + else + { + /* Set error code to DMA */ + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + /* Restore hsmartcard->State to ready */ + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + + return HAL_ERROR; + } + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in DMA mode. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @param pData pointer to data buffer. + * @param Size amount of data to be received. + * @note The SMARTCARD-associated USART parity is enabled (PCE = 1), + * the received data contain the parity bit (MSB position). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef status; + + /* Check that a Rx process is not already ongoing */ + if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hsmartcard); + + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; + hsmartcard->RxState = HAL_SMARTCARD_STATE_BUSY_RX; + + hsmartcard->pRxBuffPtr = pData; + hsmartcard->RxXferSize = Size; + + /* Set the SMARTCARD DMA transfer complete callback */ + hsmartcard->hdmarx->XferCpltCallback = SMARTCARD_DMAReceiveCplt; + + /* Set the SMARTCARD DMA error callback */ + hsmartcard->hdmarx->XferErrorCallback = SMARTCARD_DMAError; + + /* Set the DMA abort callback */ + hsmartcard->hdmarx->XferAbortCallback = NULL; + + /* Check linked list mode */ + if ((hsmartcard->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if ((hsmartcard->hdmarx->LinkedListQueue != NULL) && (hsmartcard->hdmarx->LinkedListQueue->Head != NULL)) + { + /* Set DMA data size */ + hsmartcard->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = Size; + + /* Set DMA source address */ + hsmartcard->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = + (uint32_t)&hsmartcard->Instance->RDR; + + /* Set DMA destination address */ + hsmartcard->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = + (uint32_t)hsmartcard->pRxBuffPtr; + + /* Enable the SMARTCARD receive DMA channel */ + status = HAL_DMAEx_List_Start_IT(hsmartcard->hdmarx); + } + else + { + /* Update status */ + status = HAL_ERROR; + } + } + else + { + /* Enable the DMA channel */ + status = HAL_DMA_Start_IT(hsmartcard->hdmarx, (uint32_t)&hsmartcard->Instance->RDR, + (uint32_t)hsmartcard->pRxBuffPtr, Size); + } + + if (status == HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + /* Enable the SMARTCARD Parity Error Interrupt */ + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE); + + /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); + + /* Enable the DMA transfer for the receiver request by setting the DMAR bit + in the SMARTCARD associated USART CR3 register */ + SET_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); + + return HAL_OK; + } + else + { + /* Set error code to DMA */ + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + /* Restore hsmartcard->State to ready */ + hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; + + return HAL_ERROR; + } + } + else + { + return HAL_BUSY; + } +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Abort ongoing transfers (blocking mode). + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable SMARTCARD Interrupts (Tx and Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and + ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(hsmartcard->Instance->CR1, + (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE | USART_CR1_RTOIE | + USART_CR1_EOBIE)); + CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Disable the SMARTCARD DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); + + /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */ + if (hsmartcard->hdmatx != NULL) + { + /* Set the SMARTCARD DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + hsmartcard->hdmatx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(hsmartcard->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(hsmartcard->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + + /* Disable the SMARTCARD DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); + + /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */ + if (hsmartcard->hdmarx != NULL) + { + /* Set the SMARTCARD DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + hsmartcard->hdmarx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(hsmartcard->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(hsmartcard->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } +#endif /* HAL_DMA_MODULE_ENABLED */ + + /* Reset Tx and Rx transfer counters */ + hsmartcard->TxXferCount = 0U; + hsmartcard->RxXferCount = 0U; + + /* Clear the Error flags in the ICR register */ + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | + SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); + + /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */ + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; + + /* Reset Handle ErrorCode to No Error */ + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; + + return HAL_OK; +} + +/** + * @brief Abort ongoing Transmit transfer (blocking mode). + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable SMARTCARD Interrupts (Tx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Disable TCIE, TXEIE and TXFTIE interrupts */ + CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTIE); + + /* Check if a receive process is ongoing or not. If not disable ERR IT */ + if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY) + { + /* Disable the SMARTCARD Error Interrupt: (Frame error) */ + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); + } + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Disable the SMARTCARD DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); + + /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */ + if (hsmartcard->hdmatx != NULL) + { + /* Set the SMARTCARD DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + hsmartcard->hdmatx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(hsmartcard->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(hsmartcard->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } +#endif /* HAL_DMA_MODULE_ENABLED */ + + /* Reset Tx transfer counter */ + hsmartcard->TxXferCount = 0U; + + /* Clear the Error flags in the ICR register */ + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF); + + /* Restore hsmartcard->gState to Ready */ + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Abort ongoing Receive transfer (blocking mode). + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable SMARTCARD Interrupts (Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Disable RTOIE, EOBIE, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | + USART_CR1_EOBIE)); + CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + + /* Check if a Transmit process is ongoing or not. If not disable ERR IT */ + if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) + { + /* Disable the SMARTCARD Error Interrupt: (Frame error) */ + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); + } + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Disable the SMARTCARD DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); + + /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */ + if (hsmartcard->hdmarx != NULL) + { + /* Set the SMARTCARD DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + hsmartcard->hdmarx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(hsmartcard->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(hsmartcard->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } +#endif /* HAL_DMA_MODULE_ENABLED */ + + /* Reset Rx transfer counter */ + hsmartcard->RxXferCount = 0U; + + /* Clear the Error flags in the ICR register */ + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | + SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); + + /* Restore hsmartcard->RxState to Ready */ + hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Abort ongoing transfers (Interrupt mode). + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable SMARTCARD Interrupts (Tx and Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard) +{ + uint32_t abortcplt = 1U; + + /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and + ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(hsmartcard->Instance->CR1, + (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE | USART_CR1_RTOIE | + USART_CR1_EOBIE)); + CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle, + DMA Abort complete callbacks should be initialised before any call + to DMA Abort functions */ + /* DMA Tx Handle is valid */ + if (hsmartcard->hdmatx != NULL) + { + /* Set DMA Abort Complete callback if SMARTCARD DMA Tx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) + { + hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMATxAbortCallback; + } + else + { + hsmartcard->hdmatx->XferAbortCallback = NULL; + } + } + /* DMA Rx Handle is valid */ + if (hsmartcard->hdmarx != NULL) + { + /* Set DMA Abort Complete callback if SMARTCARD DMA Rx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) + { + hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMARxAbortCallback; + } + else + { + hsmartcard->hdmarx->XferAbortCallback = NULL; + } + } + + /* Disable the SMARTCARD DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) + { + /* Disable DMA Tx at UART level */ + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); + + /* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */ + if (hsmartcard->hdmatx != NULL) + { + /* SMARTCARD Tx DMA Abort callback has already been initialised : + will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */ + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK) + { + hsmartcard->hdmatx->XferAbortCallback = NULL; + } + else + { + abortcplt = 0U; + } + } + } + + /* Disable the SMARTCARD DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); + + /* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */ + if (hsmartcard->hdmarx != NULL) + { + /* SMARTCARD Rx DMA Abort callback has already been initialised : + will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */ + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK) + { + hsmartcard->hdmarx->XferAbortCallback = NULL; + abortcplt = 1U; + } + else + { + abortcplt = 0U; + } + } + } +#endif /* HAL_DMA_MODULE_ENABLED */ + + /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ + if (abortcplt == 1U) + { + /* Reset Tx and Rx transfer counters */ + hsmartcard->TxXferCount = 0U; + hsmartcard->RxXferCount = 0U; + + /* Clear ISR function pointers */ + hsmartcard->RxISR = NULL; + hsmartcard->TxISR = NULL; + + /* Reset errorCode */ + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | + SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); + + /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */ + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + hsmartcard->AbortCpltCallback(hsmartcard); +#else + /* Call legacy weak Abort complete callback */ + HAL_SMARTCARD_AbortCpltCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ + } + + return HAL_OK; +} + +/** + * @brief Abort ongoing Transmit transfer (Interrupt mode). + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable SMARTCARD Interrupts (Tx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Disable TCIE, TXEIE and TXFTIE interrupts */ + CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTIE); + + /* Check if a receive process is ongoing or not. If not disable ERR IT */ + if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY) + { + /* Disable the SMARTCARD Error Interrupt: (Frame error) */ + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); + } + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Disable the SMARTCARD DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); + + /* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */ + if (hsmartcard->hdmatx != NULL) + { + /* Set the SMARTCARD DMA Abort callback : + will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */ + hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMATxOnlyAbortCallback; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK) + { + /* Call Directly hsmartcard->hdmatx->XferAbortCallback function in case of error */ + hsmartcard->hdmatx->XferAbortCallback(hsmartcard->hdmatx); + } + } + else + { + /* Reset Tx transfer counter */ + hsmartcard->TxXferCount = 0U; + + /* Clear TxISR function pointers */ + hsmartcard->TxISR = NULL; + + /* Restore hsmartcard->gState to Ready */ + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + hsmartcard->AbortTransmitCpltCallback(hsmartcard); +#else + /* Call legacy weak Abort Transmit Complete Callback */ + HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ + } + } + else +#endif /* HAL_DMA_MODULE_ENABLED */ + { + /* Reset Tx transfer counter */ + hsmartcard->TxXferCount = 0U; + + /* Clear TxISR function pointers */ + hsmartcard->TxISR = NULL; + + /* Clear the Error flags in the ICR register */ + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF); + + /* Restore hsmartcard->gState to Ready */ + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + hsmartcard->AbortTransmitCpltCallback(hsmartcard); +#else + /* Call legacy weak Abort Transmit Complete Callback */ + HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ + } + + return HAL_OK; +} + +/** + * @brief Abort ongoing Receive transfer (Interrupt mode). + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable SMARTCARD Interrupts (Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Disable RTOIE, EOBIE, RXNE, PE, RXFT and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | + USART_CR1_EOBIE)); + CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + + /* Check if a Transmit process is ongoing or not. If not disable ERR IT */ + if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) + { + /* Disable the SMARTCARD Error Interrupt: (Frame error) */ + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); + } + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Disable the SMARTCARD DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); + + /* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */ + if (hsmartcard->hdmarx != NULL) + { + /* Set the SMARTCARD DMA Abort callback : + will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */ + hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMARxOnlyAbortCallback; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK) + { + /* Call Directly hsmartcard->hdmarx->XferAbortCallback function in case of error */ + hsmartcard->hdmarx->XferAbortCallback(hsmartcard->hdmarx); + } + } + else + { + /* Reset Rx transfer counter */ + hsmartcard->RxXferCount = 0U; + + /* Clear RxISR function pointer */ + hsmartcard->RxISR = NULL; + + /* Clear the Error flags in the ICR register */ + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | + SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); + + /* Restore hsmartcard->RxState to Ready */ + hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + hsmartcard->AbortReceiveCpltCallback(hsmartcard); +#else + /* Call legacy weak Abort Receive Complete Callback */ + HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ + } + } + else +#endif /* HAL_DMA_MODULE_ENABLED */ + { + /* Reset Rx transfer counter */ + hsmartcard->RxXferCount = 0U; + + /* Clear RxISR function pointer */ + hsmartcard->RxISR = NULL; + + /* Clear the Error flags in the ICR register */ + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | + SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); + + /* Restore hsmartcard->RxState to Ready */ + hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + hsmartcard->AbortReceiveCpltCallback(hsmartcard); +#else + /* Call legacy weak Abort Receive Complete Callback */ + HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ + } + + return HAL_OK; +} + +/** + * @brief Handle SMARTCARD interrupt requests. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval None + */ +void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) +{ + uint32_t isrflags = READ_REG(hsmartcard->Instance->ISR); + uint32_t cr1its = READ_REG(hsmartcard->Instance->CR1); + uint32_t cr3its = READ_REG(hsmartcard->Instance->CR3); + uint32_t errorflags; + uint32_t errorcode; + + /* If no error occurs */ + errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF)); + if (errorflags == 0U) + { + /* SMARTCARD in mode Receiver ---------------------------------------------------*/ + if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) + || ((cr3its & USART_CR3_RXFTIE) != 0U))) + { + if (hsmartcard->RxISR != NULL) + { + hsmartcard->RxISR(hsmartcard); + } + return; + } + } + + /* If some errors occur */ + if ((errorflags != 0U) + && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U) + || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != 0U)))) + { + /* SMARTCARD parity error interrupt occurred -------------------------------------*/ + if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) + { + __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_PEF); + + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_PE; + } + + /* SMARTCARD frame error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_FEF); + + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_FE; + } + + /* SMARTCARD noise error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_NEF); + + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_NE; + } + + /* SMARTCARD Over-Run interrupt occurred -----------------------------------------*/ + if (((isrflags & USART_ISR_ORE) != 0U) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) + || ((cr3its & USART_CR3_RXFTIE) != 0U) + || ((cr3its & USART_CR3_EIE) != 0U))) + { + __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_OREF); + + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_ORE; + } + + /* SMARTCARD receiver timeout interrupt occurred -----------------------------------------*/ + if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U)) + { + __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_RTOF); + + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_RTO; + } + + /* Call SMARTCARD Error Call back function if need be --------------------------*/ + if (hsmartcard->ErrorCode != HAL_SMARTCARD_ERROR_NONE) + { + /* SMARTCARD in mode Receiver ---------------------------------------------------*/ + if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) + || ((cr3its & USART_CR3_RXFTIE) != 0U))) + { + if (hsmartcard->RxISR != NULL) + { + hsmartcard->RxISR(hsmartcard); + } + } + + /* If Error is to be considered as blocking : + - Receiver Timeout error in Reception + - Overrun error in Reception + - any error occurs in DMA mode reception + */ + errorcode = hsmartcard->ErrorCode; + if ((HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) + || ((errorcode & (HAL_SMARTCARD_ERROR_RTO | HAL_SMARTCARD_ERROR_ORE)) != 0U)) + { + /* Blocking error : transfer is aborted + Set the SMARTCARD state ready to be able to start again the process, + Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ + SMARTCARD_EndRxTransfer(hsmartcard); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Disable the SMARTCARD DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); + + /* Abort the SMARTCARD DMA Rx channel */ + if (hsmartcard->hdmarx != NULL) + { + /* Set the SMARTCARD DMA Abort callback : + will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */ + hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMAAbortOnError; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK) + { + /* Call Directly hsmartcard->hdmarx->XferAbortCallback function in case of error */ + hsmartcard->hdmarx->XferAbortCallback(hsmartcard->hdmarx); + } + } + else + { +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered user error callback */ + hsmartcard->ErrorCallback(hsmartcard); +#else + /* Call legacy weak user error callback */ + HAL_SMARTCARD_ErrorCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ + } + } + else +#endif /* HAL_DMA_MODULE_ENABLED */ + { +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered user error callback */ + hsmartcard->ErrorCallback(hsmartcard); +#else + /* Call legacy weak user error callback */ + HAL_SMARTCARD_ErrorCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ + } + } + /* other error type to be considered as blocking : + - Frame error in Transmission + */ + else if ((hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX) + && ((errorcode & HAL_SMARTCARD_ERROR_FE) != 0U)) + { + /* Blocking error : transfer is aborted + Set the SMARTCARD state ready to be able to start again the process, + Disable Tx Interrupts, and disable Tx DMA request, if ongoing */ + SMARTCARD_EndTxTransfer(hsmartcard); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Disable the SMARTCARD DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); + + /* Abort the SMARTCARD DMA Tx channel */ + if (hsmartcard->hdmatx != NULL) + { + /* Set the SMARTCARD DMA Abort callback : + will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */ + hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMAAbortOnError; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK) + { + /* Call Directly hsmartcard->hdmatx->XferAbortCallback function in case of error */ + hsmartcard->hdmatx->XferAbortCallback(hsmartcard->hdmatx); + } + } + else + { +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered user error callback */ + hsmartcard->ErrorCallback(hsmartcard); +#else + /* Call legacy weak user error callback */ + HAL_SMARTCARD_ErrorCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ + } + } + else +#endif /* HAL_DMA_MODULE_ENABLED */ + { +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered user error callback */ + hsmartcard->ErrorCallback(hsmartcard); +#else + /* Call legacy weak user error callback */ + HAL_SMARTCARD_ErrorCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ + } + } + else + { + /* Non Blocking error : transfer could go on. + Error is notified to user through user error callback */ +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered user error callback */ + hsmartcard->ErrorCallback(hsmartcard); +#else + /* Call legacy weak user error callback */ + HAL_SMARTCARD_ErrorCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; + } + } + return; + + } /* End if some error occurs */ + + /* SMARTCARD in mode Receiver, end of block interruption ------------------------*/ + if (((isrflags & USART_ISR_EOBF) != 0U) && ((cr1its & USART_CR1_EOBIE) != 0U)) + { + hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; + __HAL_UNLOCK(hsmartcard); +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered Rx complete callback */ + hsmartcard->RxCpltCallback(hsmartcard); +#else + /* Call legacy weak Rx complete callback */ + HAL_SMARTCARD_RxCpltCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ + /* Clear EOBF interrupt after HAL_SMARTCARD_RxCpltCallback() call for the End of Block information + to be available during HAL_SMARTCARD_RxCpltCallback() processing */ + __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_EOBF); + return; + } + + /* SMARTCARD in mode Transmitter ------------------------------------------------*/ + if (((isrflags & USART_ISR_TXE_TXFNF) != 0U) + && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U) + || ((cr3its & USART_CR3_TXFTIE) != 0U))) + { + if (hsmartcard->TxISR != NULL) + { + hsmartcard->TxISR(hsmartcard); + } + return; + } + + /* SMARTCARD in mode Transmitter (transmission end) ------------------------*/ + if (__HAL_SMARTCARD_GET_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET) + { + if (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET) + { + SMARTCARD_EndTransmit_IT(hsmartcard); + return; + } + } + + /* SMARTCARD TX Fifo Empty occurred ----------------------------------------------*/ + if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U)) + { +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered Tx Fifo Empty Callback */ + hsmartcard->TxFifoEmptyCallback(hsmartcard); +#else + /* Call legacy weak Tx Fifo Empty Callback */ + HAL_SMARTCARDEx_TxFifoEmptyCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ + return; + } + + /* SMARTCARD RX Fifo Full occurred ----------------------------------------------*/ + if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U)) + { +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered Rx Fifo Full Callback */ + hsmartcard->RxFifoFullCallback(hsmartcard); +#else + /* Call legacy weak Rx Fifo Full Callback */ + HAL_SMARTCARDEx_RxFifoFullCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ + return; + } +} + +/** + * @brief Tx Transfer completed callback. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval None + */ +__weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsmartcard); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMARTCARD_TxCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Rx Transfer completed callback. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval None + */ +__weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsmartcard); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMARTCARD_RxCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief SMARTCARD error callback. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval None + */ +__weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsmartcard); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMARTCARD_ErrorCallback can be implemented in the user file. + */ +} + +/** + * @brief SMARTCARD Abort Complete callback. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval None + */ +__weak void HAL_SMARTCARD_AbortCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsmartcard); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMARTCARD_AbortCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief SMARTCARD Abort Complete callback. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval None + */ +__weak void HAL_SMARTCARD_AbortTransmitCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsmartcard); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMARTCARD_AbortTransmitCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief SMARTCARD Abort Receive Complete callback. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval None + */ +__weak void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsmartcard); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMARTCARD_AbortReceiveCpltCallback can be implemented in the user file. + */ +} + +/** + * @} + */ + +/** @defgroup SMARTCARD_Exported_Functions_Group4 Peripheral State and Errors functions + * @brief SMARTCARD State and Errors functions + * +@verbatim + ============================================================================== + ##### Peripheral State and Errors functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to return the State of SmartCard + handle and also return Peripheral Errors occurred during communication process + (+) HAL_SMARTCARD_GetState() API can be helpful to check in run-time the state + of the SMARTCARD peripheral. + (+) HAL_SMARTCARD_GetError() checks in run-time errors that could occur during + communication. + +@endverbatim + * @{ + */ + +/** + * @brief Return the SMARTCARD handle state. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval SMARTCARD handle state + */ +HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(const SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Return SMARTCARD handle state */ + uint32_t temp1; + uint32_t temp2; + temp1 = (uint32_t)hsmartcard->gState; + temp2 = (uint32_t)hsmartcard->RxState; + + return (HAL_SMARTCARD_StateTypeDef)(temp1 | temp2); +} + +/** + * @brief Return the SMARTCARD handle error code. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval SMARTCARD handle Error Code + */ +uint32_t HAL_SMARTCARD_GetError(const SMARTCARD_HandleTypeDef *hsmartcard) +{ + return hsmartcard->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions + * @{ + */ + +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) +/** + * @brief Initialize the callbacks to their default values. + * @param hsmartcard SMARTCARD handle. + * @retval none + */ +void SMARTCARD_InitCallbacksToDefault(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Init the SMARTCARD Callback settings */ + hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */ + hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */ + hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */ + hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak + AbortTransmitCpltCallback */ + hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak + AbortReceiveCpltCallback */ + hsmartcard->RxFifoFullCallback = HAL_SMARTCARDEx_RxFifoFullCallback; /* Legacy weak + RxFifoFullCallback */ + hsmartcard->TxFifoEmptyCallback = HAL_SMARTCARDEx_TxFifoEmptyCallback; /* Legacy weak + TxFifoEmptyCallback */ + +} +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ + +/** + * @brief Configure the SMARTCARD associated USART peripheral. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval HAL status + */ +static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard) +{ + uint32_t tmpreg; + SMARTCARD_ClockSourceTypeDef clocksource; + HAL_StatusTypeDef ret = HAL_OK; + static const uint16_t SMARTCARDPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U}; + uint32_t pclk; + + /* Check the parameters */ + assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance)); + assert_param(IS_SMARTCARD_BAUDRATE(hsmartcard->Init.BaudRate)); + assert_param(IS_SMARTCARD_WORD_LENGTH(hsmartcard->Init.WordLength)); + assert_param(IS_SMARTCARD_STOPBITS(hsmartcard->Init.StopBits)); + assert_param(IS_SMARTCARD_PARITY(hsmartcard->Init.Parity)); + assert_param(IS_SMARTCARD_MODE(hsmartcard->Init.Mode)); + assert_param(IS_SMARTCARD_POLARITY(hsmartcard->Init.CLKPolarity)); + assert_param(IS_SMARTCARD_PHASE(hsmartcard->Init.CLKPhase)); + assert_param(IS_SMARTCARD_LASTBIT(hsmartcard->Init.CLKLastBit)); + assert_param(IS_SMARTCARD_ONE_BIT_SAMPLE(hsmartcard->Init.OneBitSampling)); + assert_param(IS_SMARTCARD_NACK(hsmartcard->Init.NACKEnable)); + assert_param(IS_SMARTCARD_TIMEOUT(hsmartcard->Init.TimeOutEnable)); + assert_param(IS_SMARTCARD_AUTORETRY_COUNT(hsmartcard->Init.AutoRetryCount)); + assert_param(IS_SMARTCARD_CLOCKPRESCALER(hsmartcard->Init.ClockPrescaler)); + + /*-------------------------- USART CR1 Configuration -----------------------*/ + /* In SmartCard mode, M and PCE are forced to 1 (8 bits + parity). + * Oversampling is forced to 16 (OVER8 = 0). + * Configure the Parity and Mode: + * set PS bit according to hsmartcard->Init.Parity value + * set TE and RE bits according to hsmartcard->Init.Mode value */ + tmpreg = (((uint32_t)hsmartcard->Init.Parity) | ((uint32_t)hsmartcard->Init.Mode) | + ((uint32_t)hsmartcard->Init.WordLength)); + MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_FIELDS, tmpreg); + + /*-------------------------- USART CR2 Configuration -----------------------*/ + tmpreg = hsmartcard->Init.StopBits; + /* Synchronous mode is activated by default */ + tmpreg |= (uint32_t) USART_CR2_CLKEN | hsmartcard->Init.CLKPolarity; + tmpreg |= (uint32_t) hsmartcard->Init.CLKPhase | hsmartcard->Init.CLKLastBit; + tmpreg |= (uint32_t) hsmartcard->Init.TimeOutEnable; + MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_FIELDS, tmpreg); + + /*-------------------------- USART CR3 Configuration -----------------------*/ + /* Configure + * - one-bit sampling method versus three samples' majority rule + * according to hsmartcard->Init.OneBitSampling + * - NACK transmission in case of parity error according + * to hsmartcard->Init.NACKEnable + * - autoretry counter according to hsmartcard->Init.AutoRetryCount */ + + tmpreg = (uint32_t) hsmartcard->Init.OneBitSampling | hsmartcard->Init.NACKEnable; + tmpreg |= ((uint32_t)hsmartcard->Init.AutoRetryCount << USART_CR3_SCARCNT_Pos); + MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_FIELDS, tmpreg); + + /*--------------------- SMARTCARD clock PRESC Configuration ----------------*/ + /* Configure + * - SMARTCARD Clock Prescaler: set PRESCALER according to hsmartcard->Init.ClockPrescaler value */ + MODIFY_REG(hsmartcard->Instance->PRESC, USART_PRESC_PRESCALER, hsmartcard->Init.ClockPrescaler); + + /*-------------------------- USART GTPR Configuration ----------------------*/ + tmpreg = (hsmartcard->Init.Prescaler | ((uint32_t)hsmartcard->Init.GuardTime << USART_GTPR_GT_Pos)); + MODIFY_REG(hsmartcard->Instance->GTPR, (uint16_t)(USART_GTPR_GT | USART_GTPR_PSC), (uint16_t)tmpreg); + + /*-------------------------- USART RTOR Configuration ----------------------*/ + tmpreg = ((uint32_t)hsmartcard->Init.BlockLength << USART_RTOR_BLEN_Pos); + if (hsmartcard->Init.TimeOutEnable == SMARTCARD_TIMEOUT_ENABLE) + { + assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue)); + tmpreg |= (uint32_t) hsmartcard->Init.TimeOutValue; + } + WRITE_REG(hsmartcard->Instance->RTOR, tmpreg); + + /*-------------------------- USART BRR Configuration -----------------------*/ + SMARTCARD_GETCLOCKSOURCE(hsmartcard, clocksource); + tmpreg = 0U; + switch (clocksource) + { + case SMARTCARD_CLOCKSOURCE_PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + tmpreg = (uint32_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); + break; + case SMARTCARD_CLOCKSOURCE_PCLK2: + pclk = HAL_RCC_GetPCLK2Freq(); + tmpreg = (uint32_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); + break; + case SMARTCARD_CLOCKSOURCE_HSI: + tmpreg = (uint32_t)(((HSI_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); + break; + case SMARTCARD_CLOCKSOURCE_SYSCLK: + pclk = HAL_RCC_GetSysClockFreq(); + tmpreg = (uint32_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); + break; + case SMARTCARD_CLOCKSOURCE_LSE: + tmpreg = (uint32_t)(((uint16_t)(LSE_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); + break; + default: + ret = HAL_ERROR; + break; + } + + /* USARTDIV must be greater than or equal to 0d16 */ + if ((tmpreg >= USART_BRR_MIN) && (tmpreg <= USART_BRR_MAX)) + { + hsmartcard->Instance->BRR = (uint16_t)tmpreg; + } + else + { + ret = HAL_ERROR; + } + + /* Initialize the number of data to process during RX/TX ISR execution */ + hsmartcard->NbTxDataToProcess = 1U; + hsmartcard->NbRxDataToProcess = 1U; + + /* Clear ISR function pointers */ + hsmartcard->RxISR = NULL; + hsmartcard->TxISR = NULL; + + return ret; +} + + +/** + * @brief Configure the SMARTCARD associated USART peripheral advanced features. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval None + */ +static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Check whether the set of advanced features to configure is properly set */ + assert_param(IS_SMARTCARD_ADVFEATURE_INIT(hsmartcard->AdvancedInit.AdvFeatureInit)); + + /* if required, configure TX pin active level inversion */ + if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXINVERT_INIT)) + { + assert_param(IS_SMARTCARD_ADVFEATURE_TXINV(hsmartcard->AdvancedInit.TxPinLevelInvert)); + MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_TXINV, hsmartcard->AdvancedInit.TxPinLevelInvert); + } + + /* if required, configure RX pin active level inversion */ + if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_RXINVERT_INIT)) + { + assert_param(IS_SMARTCARD_ADVFEATURE_RXINV(hsmartcard->AdvancedInit.RxPinLevelInvert)); + MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_RXINV, hsmartcard->AdvancedInit.RxPinLevelInvert); + } + + /* if required, configure data inversion */ + if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_DATAINVERT_INIT)) + { + assert_param(IS_SMARTCARD_ADVFEATURE_DATAINV(hsmartcard->AdvancedInit.DataInvert)); + MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_DATAINV, hsmartcard->AdvancedInit.DataInvert); + } + + /* if required, configure RX/TX pins swap */ + if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_SWAP_INIT)) + { + assert_param(IS_SMARTCARD_ADVFEATURE_SWAP(hsmartcard->AdvancedInit.Swap)); + MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_SWAP, hsmartcard->AdvancedInit.Swap); + } + + /* if required, configure RX overrun detection disabling */ + if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT)) + { + assert_param(IS_SMARTCARD_OVERRUN(hsmartcard->AdvancedInit.OverrunDisable)); + MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_OVRDIS, hsmartcard->AdvancedInit.OverrunDisable); + } + + /* if required, configure DMA disabling on reception error */ + if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT)) + { + assert_param(IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(hsmartcard->AdvancedInit.DMADisableonRxError)); + MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_DDRE, hsmartcard->AdvancedInit.DMADisableonRxError); + } + + /* if required, configure MSB first on communication line */ + if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_MSBFIRST_INIT)) + { + assert_param(IS_SMARTCARD_ADVFEATURE_MSBFIRST(hsmartcard->AdvancedInit.MSBFirst)); + MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_MSBFIRST, hsmartcard->AdvancedInit.MSBFirst); + } + +} + +/** + * @brief Check the SMARTCARD Idle State. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval HAL status + */ +static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard) +{ + uint32_t tickstart; + + /* Initialize the SMARTCARD ErrorCode */ + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + /* Check if the Transmitter is enabled */ + if ((hsmartcard->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) + { + /* Wait until TEACK flag is set */ + if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_TEACK, RESET, tickstart, + SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK) + { + /* Timeout occurred */ + return HAL_TIMEOUT; + } + } + /* Check if the Receiver is enabled */ + if ((hsmartcard->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) + { + /* Wait until REACK flag is set */ + if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_REACK, RESET, tickstart, + SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK) + { + /* Timeout occurred */ + return HAL_TIMEOUT; + } + } + + /* Initialize the SMARTCARD states */ + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + return HAL_OK; +} + +/** + * @brief Handle SMARTCARD Communication Timeout. It waits + * until a flag is no longer in the specified status. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @param Flag Specifies the SMARTCARD flag to check. + * @param Status The actual Flag status (SET or RESET). + * @param Tickstart Tick start value + * @param Timeout Timeout duration. + * @retval HAL status + */ +static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, + FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) +{ + /* Wait until flag is set */ + while ((__HAL_SMARTCARD_GET_FLAG(hsmartcard, Flag) ? SET : RESET) == Status) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) + interrupts for the interrupt process */ + CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE)); + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); + + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + return HAL_TIMEOUT; + } + } + } + return HAL_OK; +} + + +/** + * @brief End ongoing Tx transfer on SMARTCARD peripheral (following error detection or Transmit completion). + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval None + */ +static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Disable TXEIE, TCIE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); + + /* At end of Tx process, restore hsmartcard->gState to Ready */ + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; +} + + +/** + * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval None + */ +static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); + + /* At end of Rx process, restore hsmartcard->RxState to Ready */ + hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; +} + + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief DMA SMARTCARD transmit process complete callback. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma) +{ + SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent); + hsmartcard->TxXferCount = 0U; + + /* Disable the DMA transfer for transmit request by resetting the DMAT bit + in the SMARTCARD associated USART CR3 register */ + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); + + /* Enable the SMARTCARD Transmit Complete Interrupt */ + __HAL_SMARTCARD_ENABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication); +} + +/** + * @brief DMA SMARTCARD receive process complete callback. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +{ + SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent); + hsmartcard->RxXferCount = 0U; + + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE); + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); + + /* Disable the DMA transfer for the receiver request by resetting the DMAR bit + in the SMARTCARD associated USART CR3 register */ + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); + + /* At end of Rx process, restore hsmartcard->RxState to Ready */ + hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; + +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered Rx complete callback */ + hsmartcard->RxCpltCallback(hsmartcard); +#else + /* Call legacy weak Rx complete callback */ + HAL_SMARTCARD_RxCpltCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ +} + +/** + * @brief DMA SMARTCARD communication error callback. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma) +{ + SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent); + + /* Stop SMARTCARD DMA Tx request if ongoing */ + if (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX) + { + if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) + { + hsmartcard->TxXferCount = 0U; + SMARTCARD_EndTxTransfer(hsmartcard); + } + } + + /* Stop SMARTCARD DMA Rx request if ongoing */ + if (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX) + { + if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) + { + hsmartcard->RxXferCount = 0U; + SMARTCARD_EndRxTransfer(hsmartcard); + } + } + + hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_DMA; +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered user error callback */ + hsmartcard->ErrorCallback(hsmartcard); +#else + /* Call legacy weak user error callback */ + HAL_SMARTCARD_ErrorCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ +} + +/** + * @brief DMA SMARTCARD communication abort callback, when initiated by HAL services on Error + * (To be called at end of DMA Abort procedure following error occurrence). + * @param hdma DMA handle. + * @retval None + */ +static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma) +{ + SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent); + hsmartcard->RxXferCount = 0U; + hsmartcard->TxXferCount = 0U; + +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered user error callback */ + hsmartcard->ErrorCallback(hsmartcard); +#else + /* Call legacy weak user error callback */ + HAL_SMARTCARD_ErrorCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ +} + +/** + * @brief DMA SMARTCARD Tx communication abort callback, when initiated by user + * (To be called at end of DMA Tx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Rx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma) +{ + SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent); + + hsmartcard->hdmatx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if (hsmartcard->hdmarx != NULL) + { + if (hsmartcard->hdmarx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + hsmartcard->TxXferCount = 0U; + hsmartcard->RxXferCount = 0U; + + /* Reset errorCode */ + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | + SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); + + /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */ + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; + +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + hsmartcard->AbortCpltCallback(hsmartcard); +#else + /* Call legacy weak Abort complete callback */ + HAL_SMARTCARD_AbortCpltCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ +} + + +/** + * @brief DMA SMARTCARD Rx communication abort callback, when initiated by user + * (To be called at end of DMA Rx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Tx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma) +{ + SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent); + + hsmartcard->hdmarx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if (hsmartcard->hdmatx != NULL) + { + if (hsmartcard->hdmatx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + hsmartcard->TxXferCount = 0U; + hsmartcard->RxXferCount = 0U; + + /* Reset errorCode */ + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | + SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); + + /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */ + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; + +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + hsmartcard->AbortCpltCallback(hsmartcard); +#else + /* Call legacy weak Abort complete callback */ + HAL_SMARTCARD_AbortCpltCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ +} + + +/** + * @brief DMA SMARTCARD Tx communication abort callback, when initiated by user by a call to + * HAL_SMARTCARD_AbortTransmit_IT API (Abort only Tx transfer) + * (This callback is executed at end of DMA Tx Abort procedure following user abort request, + * and leads to user Tx Abort Complete callback execution). + * @param hdma DMA handle. + * @retval None + */ +static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma) +{ + SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent); + + hsmartcard->TxXferCount = 0U; + + /* Clear the Error flags in the ICR register */ + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF); + + /* Restore hsmartcard->gState to Ready */ + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + hsmartcard->AbortTransmitCpltCallback(hsmartcard); +#else + /* Call legacy weak Abort Transmit Complete Callback */ + HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ +} + +/** + * @brief DMA SMARTCARD Rx communication abort callback, when initiated by user by a call to + * HAL_SMARTCARD_AbortReceive_IT API (Abort only Rx transfer) + * (This callback is executed at end of DMA Rx Abort procedure following user abort request, + * and leads to user Rx Abort Complete callback execution). + * @param hdma DMA handle. + * @retval None + */ +static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) +{ + SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent); + + hsmartcard->RxXferCount = 0U; + + /* Clear the Error flags in the ICR register */ + __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | + SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); + + /* Restore hsmartcard->RxState to Ready */ + hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; + +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + hsmartcard->AbortReceiveCpltCallback(hsmartcard); +#else + /* Call legacy weak Abort Receive Complete Callback */ + HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Send an amount of data in non-blocking mode. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_SMARTCARD_Transmit_IT() + * and when the FIFO mode is disabled. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval None + */ +static void SMARTCARD_TxISR(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Check that a Tx process is ongoing */ + if (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX) + { + if (hsmartcard->TxXferCount == 0U) + { + /* Disable the SMARTCARD Transmit Data Register Empty Interrupt */ + CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); + + /* Enable the SMARTCARD Transmit Complete Interrupt */ + __HAL_SMARTCARD_ENABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication); + } + else + { + hsmartcard->Instance->TDR = (uint8_t)(*hsmartcard->pTxBuffPtr & 0xFFU); + hsmartcard->pTxBuffPtr++; + hsmartcard->TxXferCount--; + } + } +} + +/** + * @brief Send an amount of data in non-blocking mode. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_SMARTCARD_Transmit_IT() + * and when the FIFO mode is enabled. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval None + */ +static void SMARTCARD_TxISR_FIFOEN(SMARTCARD_HandleTypeDef *hsmartcard) +{ + uint16_t nb_tx_data; + + /* Check that a Tx process is ongoing */ + if (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX) + { + for (nb_tx_data = hsmartcard->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) + { + if (hsmartcard->TxXferCount == 0U) + { + /* Disable the SMARTCARD Transmit Data Register Empty Interrupt */ + CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); + + /* Enable the SMARTCARD Transmit Complete Interrupt */ + __HAL_SMARTCARD_ENABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication); + } + else if (READ_BIT(hsmartcard->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U) + { + hsmartcard->Instance->TDR = (uint8_t)(*hsmartcard->pTxBuffPtr & 0xFFU); + hsmartcard->pTxBuffPtr++; + hsmartcard->TxXferCount--; + } + else + { + /* Nothing to do */ + } + } + } +} + +/** + * @brief Wrap up transmission in non-blocking mode. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval None + */ +static void SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Disable the SMARTCARD Transmit Complete Interrupt */ + __HAL_SMARTCARD_DISABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication); + + /* Check if a receive process is ongoing or not. If not disable ERR IT */ + if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY) + { + /* Disable the SMARTCARD Error Interrupt: (Frame error) */ + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); + } + + /* Disable the Peripheral first to update mode */ + CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); + if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX) + && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) + { + /* In case of TX only mode, if NACK is enabled, receiver block has been enabled + for Transmit phase. Disable this receiver block. */ + CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); + } + if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX) + || (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) + { + /* Perform a TX FIFO Flush at end of Tx phase, as all sent bytes are appearing in Rx Data register */ + __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard); + } + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); + + /* Tx process is ended, restore hsmartcard->gState to Ready */ + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + + /* Clear TxISR function pointer */ + hsmartcard->TxISR = NULL; + +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered Tx complete callback */ + hsmartcard->TxCpltCallback(hsmartcard); +#else + /* Call legacy weak Tx complete callback */ + HAL_SMARTCARD_TxCpltCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ +} + +/** + * @brief Receive an amount of data in non-blocking mode. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_SMARTCARD_Receive_IT() + * and when the FIFO mode is disabled. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval None + */ +static void SMARTCARD_RxISR(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Check that a Rx process is ongoing */ + if (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX) + { + *hsmartcard->pRxBuffPtr = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0xFF); + hsmartcard->pRxBuffPtr++; + + hsmartcard->RxXferCount--; + if (hsmartcard->RxXferCount == 0U) + { + CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + + /* Check if a transmit process is ongoing or not. If not disable ERR IT */ + if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) + { + /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); + } + + /* Disable the SMARTCARD Parity Error Interrupt */ + CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE); + + hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; + + /* Clear RxISR function pointer */ + hsmartcard->RxISR = NULL; + +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered Rx complete callback */ + hsmartcard->RxCpltCallback(hsmartcard); +#else + /* Call legacy weak Rx complete callback */ + HAL_SMARTCARD_RxCpltCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ + } + } + else + { + /* Clear RXNE interrupt flag */ + __HAL_SMARTCARD_SEND_REQ(hsmartcard, SMARTCARD_RXDATA_FLUSH_REQUEST); + } +} + +/** + * @brief Receive an amount of data in non-blocking mode. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_SMARTCARD_Receive_IT() + * and when the FIFO mode is enabled. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval None + */ +static void SMARTCARD_RxISR_FIFOEN(SMARTCARD_HandleTypeDef *hsmartcard) +{ + uint16_t nb_rx_data; + uint16_t rxdatacount; + + /* Check that a Rx process is ongoing */ + if (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX) + { + for (nb_rx_data = hsmartcard->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--) + { + *hsmartcard->pRxBuffPtr = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0xFF); + hsmartcard->pRxBuffPtr++; + + hsmartcard->RxXferCount--; + if (hsmartcard->RxXferCount == 0U) + { + CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + + /* Check if a transmit process is ongoing or not. If not disable ERR IT */ + if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) + { + /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); + } + + /* Disable the SMARTCARD Parity Error Interrupt */ + CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE); + + hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; + + /* Clear RxISR function pointer */ + hsmartcard->RxISR = NULL; + +#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) + /* Call registered Rx complete callback */ + hsmartcard->RxCpltCallback(hsmartcard); +#else + /* Call legacy weak Rx complete callback */ + HAL_SMARTCARD_RxCpltCallback(hsmartcard); +#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ + } + } + + /* When remaining number of bytes to receive is less than the RX FIFO + threshold, next incoming frames are processed as if FIFO mode was + disabled (i.e. one interrupt per received frame). + */ + rxdatacount = hsmartcard->RxXferCount; + if (((rxdatacount != 0U)) && (rxdatacount < hsmartcard->NbRxDataToProcess)) + { + /* Disable the UART RXFT interrupt*/ + CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_RXFTIE); + + /* Update the RxISR function pointer */ + hsmartcard->RxISR = SMARTCARD_RxISR; + + /* Enable the UART Data Register Not Empty interrupt */ + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + } + } + else + { + /* Clear RXNE interrupt flag */ + __HAL_SMARTCARD_SEND_REQ(hsmartcard, SMARTCARD_RXDATA_FLUSH_REQUEST); + } +} + +/** + * @} + */ + +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_smartcard_ex.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_smartcard_ex.c new file mode 100644 index 0000000000..aaf329dbb2 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_smartcard_ex.c @@ -0,0 +1,494 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_smartcard_ex.c + * @author MCD Application Team + * @brief SMARTCARD HAL module driver. + * This file provides extended firmware functions to manage the following + * functionalities of the SmartCard. + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================= + ##### SMARTCARD peripheral extended features ##### + ============================================================================= + [..] + The Extended SMARTCARD HAL driver can be used as follows: + + (#) After having configured the SMARTCARD basic features with HAL_SMARTCARD_Init(), + then program SMARTCARD advanced features if required (TX/RX pins swap, TimeOut, + auto-retry counter,...) in the hsmartcard AdvancedInit structure. + + (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming. + + -@- When SMARTCARD operates in FIFO mode, FIFO mode must be enabled prior + starting RX/TX transfers. Also RX/TX FIFO thresholds must be + configured prior starting RX/TX transfers. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @defgroup SMARTCARDEx SMARTCARDEx + * @brief SMARTCARD Extended HAL module driver + * @{ + */ +#ifdef HAL_SMARTCARD_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup SMARTCARDEx_Private_Constants SMARTCARD Extended Private Constants + * @{ + */ +/* UART RX FIFO depth */ +#define RX_FIFO_DEPTH 8U + +/* UART TX FIFO depth */ +#define TX_FIFO_DEPTH 8U +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static void SMARTCARDEx_SetNbDataToProcess(SMARTCARD_HandleTypeDef *hsmartcard); + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup SMARTCARDEx_Exported_Functions SMARTCARD Extended Exported Functions + * @{ + */ + +/** @defgroup SMARTCARDEx_Exported_Functions_Group1 Extended Peripheral Control functions + * @brief Extended control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to initialize the SMARTCARD. + (+) HAL_SMARTCARDEx_BlockLength_Config() API allows to configure the Block Length on the fly + (+) HAL_SMARTCARDEx_TimeOut_Config() API allows to configure the receiver timeout value on the fly + (+) HAL_SMARTCARDEx_EnableReceiverTimeOut() API enables the receiver timeout feature + (+) HAL_SMARTCARDEx_DisableReceiverTimeOut() API disables the receiver timeout feature + +@endverbatim + * @{ + */ + +/** @brief Update on the fly the SMARTCARD block length in RTOR register. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @param BlockLength SMARTCARD block length (8-bit long at most) + * @retval None + */ +void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength) +{ + MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_BLEN, ((uint32_t)BlockLength << USART_RTOR_BLEN_Pos)); +} + +/** @brief Update on the fly the receiver timeout value in RTOR register. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @param TimeOutValue receiver timeout value in number of baud blocks. The timeout + * value must be less or equal to 0x0FFFFFFFF. + * @retval None + */ +void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue) +{ + assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue)); + MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_RTO, TimeOutValue); +} + +/** @brief Enable the SMARTCARD receiver timeout feature. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard) +{ + if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsmartcard); + + hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY; + + /* Set the USART RTOEN bit */ + SET_BIT(hsmartcard->Instance->CR2, USART_CR2_RTOEN); + + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** @brief Disable the SMARTCARD receiver timeout feature. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard) +{ + if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsmartcard); + + hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY; + + /* Clear the USART RTOEN bit */ + CLEAR_BIT(hsmartcard->Instance->CR2, USART_CR2_RTOEN); + + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @} + */ + +/** @defgroup SMARTCARDEx_Exported_Functions_Group2 Extended Peripheral IO operation functions + * @brief SMARTCARD Transmit and Receive functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of FIFO mode related callback functions. + + (#) TX/RX Fifos Callbacks: + (++) HAL_SMARTCARDEx_RxFifoFullCallback() + (++) HAL_SMARTCARDEx_TxFifoEmptyCallback() + +@endverbatim + * @{ + */ + +/** + * @brief SMARTCARD RX Fifo full callback. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval None + */ +__weak void HAL_SMARTCARDEx_RxFifoFullCallback(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsmartcard); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMARTCARDEx_RxFifoFullCallback can be implemented in the user file. + */ +} + +/** + * @brief SMARTCARD TX Fifo empty callback. + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains + * the configuration information for the specified SMARTCARD module. + * @retval None + */ +__weak void HAL_SMARTCARDEx_TxFifoEmptyCallback(SMARTCARD_HandleTypeDef *hsmartcard) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsmartcard); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMARTCARDEx_TxFifoEmptyCallback can be implemented in the user file. + */ +} + +/** + * @} + */ + +/** @defgroup SMARTCARDEx_Exported_Functions_Group3 Extended Peripheral FIFO Control functions + * @brief SMARTCARD control functions + * +@verbatim + =============================================================================== + ##### Peripheral FIFO Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the SMARTCARD + FIFO feature. + (+) HAL_SMARTCARDEx_EnableFifoMode() API enables the FIFO mode + (+) HAL_SMARTCARDEx_DisableFifoMode() API disables the FIFO mode + (+) HAL_SMARTCARDEx_SetTxFifoThreshold() API sets the TX FIFO threshold + (+) HAL_SMARTCARDEx_SetRxFifoThreshold() API sets the RX FIFO threshold +@endverbatim + * @{ + */ + +/** + * @brief Enable the FIFO mode. + * @param hsmartcard SMARTCARD handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARDEx_EnableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard) +{ + uint32_t tmpcr1; + + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(hsmartcard->Instance)); + + /* Process Locked */ + __HAL_LOCK(hsmartcard); + + hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY; + + /* Save actual SMARTCARD configuration */ + tmpcr1 = READ_REG(hsmartcard->Instance->CR1); + + /* Disable SMARTCARD */ + __HAL_SMARTCARD_DISABLE(hsmartcard); + + /* Enable FIFO mode */ + SET_BIT(tmpcr1, USART_CR1_FIFOEN); + hsmartcard->FifoMode = SMARTCARD_FIFOMODE_ENABLE; + + /* Restore SMARTCARD configuration */ + WRITE_REG(hsmartcard->Instance->CR1, tmpcr1); + + /* Determine the number of data to process during RX/TX ISR execution */ + SMARTCARDEx_SetNbDataToProcess(hsmartcard); + + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + return HAL_OK; +} + +/** + * @brief Disable the FIFO mode. + * @param hsmartcard SMARTCARD handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARDEx_DisableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard) +{ + uint32_t tmpcr1; + + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(hsmartcard->Instance)); + + /* Process Locked */ + __HAL_LOCK(hsmartcard); + + hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY; + + /* Save actual SMARTCARD configuration */ + tmpcr1 = READ_REG(hsmartcard->Instance->CR1); + + /* Disable SMARTCARD */ + __HAL_SMARTCARD_DISABLE(hsmartcard); + + /* Enable FIFO mode */ + CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); + hsmartcard->FifoMode = SMARTCARD_FIFOMODE_DISABLE; + + /* Restore SMARTCARD configuration */ + WRITE_REG(hsmartcard->Instance->CR1, tmpcr1); + + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + return HAL_OK; +} + +/** + * @brief Set the TXFIFO threshold. + * @param hsmartcard SMARTCARD handle. + * @param Threshold TX FIFO threshold value + * This parameter can be one of the following values: + * @arg @ref SMARTCARD_TXFIFO_THRESHOLD_1_8 + * @arg @ref SMARTCARD_TXFIFO_THRESHOLD_1_4 + * @arg @ref SMARTCARD_TXFIFO_THRESHOLD_1_2 + * @arg @ref SMARTCARD_TXFIFO_THRESHOLD_3_4 + * @arg @ref SMARTCARD_TXFIFO_THRESHOLD_7_8 + * @arg @ref SMARTCARD_TXFIFO_THRESHOLD_8_8 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARDEx_SetTxFifoThreshold(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold) +{ + uint32_t tmpcr1; + + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(hsmartcard->Instance)); + assert_param(IS_SMARTCARD_TXFIFO_THRESHOLD(Threshold)); + + /* Process Locked */ + __HAL_LOCK(hsmartcard); + + hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY; + + /* Save actual SMARTCARD configuration */ + tmpcr1 = READ_REG(hsmartcard->Instance->CR1); + + /* Disable SMARTCARD */ + __HAL_SMARTCARD_DISABLE(hsmartcard); + + /* Update TX threshold configuration */ + MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_TXFTCFG, Threshold); + + /* Determine the number of data to process during RX/TX ISR execution */ + SMARTCARDEx_SetNbDataToProcess(hsmartcard); + + /* Restore SMARTCARD configuration */ + MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_UE, tmpcr1); + + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + return HAL_OK; +} + +/** + * @brief Set the RXFIFO threshold. + * @param hsmartcard SMARTCARD handle. + * @param Threshold RX FIFO threshold value + * This parameter can be one of the following values: + * @arg @ref SMARTCARD_RXFIFO_THRESHOLD_1_8 + * @arg @ref SMARTCARD_RXFIFO_THRESHOLD_1_4 + * @arg @ref SMARTCARD_RXFIFO_THRESHOLD_1_2 + * @arg @ref SMARTCARD_RXFIFO_THRESHOLD_3_4 + * @arg @ref SMARTCARD_RXFIFO_THRESHOLD_7_8 + * @arg @ref SMARTCARD_RXFIFO_THRESHOLD_8_8 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMARTCARDEx_SetRxFifoThreshold(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold) +{ + uint32_t tmpcr1; + + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(hsmartcard->Instance)); + assert_param(IS_SMARTCARD_RXFIFO_THRESHOLD(Threshold)); + + /* Process Locked */ + __HAL_LOCK(hsmartcard); + + hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY; + + /* Save actual SMARTCARD configuration */ + tmpcr1 = READ_REG(hsmartcard->Instance->CR1); + + /* Disable SMARTCARD */ + __HAL_SMARTCARD_DISABLE(hsmartcard); + + /* Update RX threshold configuration */ + MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_RXFTCFG, Threshold); + + /* Determine the number of data to process during RX/TX ISR execution */ + SMARTCARDEx_SetNbDataToProcess(hsmartcard); + + /* Restore SMARTCARD configuration */ + MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_UE, tmpcr1); + + hsmartcard->gState = HAL_SMARTCARD_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmartcard); + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup SMARTCARDEx_Private_Functions SMARTCARD Extended Private Functions + * @{ + */ + +/** + * @brief Calculate the number of data to process in RX/TX ISR. + * @note The RX FIFO depth and the TX FIFO depth is extracted from + * the USART configuration registers. + * @param hsmartcard SMARTCARD handle. + * @retval None + */ +static void SMARTCARDEx_SetNbDataToProcess(SMARTCARD_HandleTypeDef *hsmartcard) +{ + uint8_t rx_fifo_depth; + uint8_t tx_fifo_depth; + uint8_t rx_fifo_threshold; + uint8_t tx_fifo_threshold; + /* 2 0U/1U added for MISRAC2012-Rule-18.1_b and MISRAC2012-Rule-18.1_d */ + static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; + static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; + + if (hsmartcard->FifoMode == SMARTCARD_FIFOMODE_DISABLE) + { + hsmartcard->NbTxDataToProcess = 1U; + hsmartcard->NbRxDataToProcess = 1U; + } + else + { + rx_fifo_depth = RX_FIFO_DEPTH; + tx_fifo_depth = TX_FIFO_DEPTH; + rx_fifo_threshold = (uint8_t)(READ_BIT(hsmartcard->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); + tx_fifo_threshold = (uint8_t)(READ_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); + hsmartcard->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / \ + (uint16_t)denominator[tx_fifo_threshold]; + hsmartcard->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / \ + (uint16_t)denominator[rx_fifo_threshold]; + } +} + +/** + * @} + */ + +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_smbus.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_smbus.c new file mode 100644 index 0000000000..ccda2e6bfb --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_smbus.c @@ -0,0 +1,2813 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_smbus.c + * @author MCD Application Team + * @brief SMBUS HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the System Management Bus (SMBus) peripheral, + * based on I2C principles of operation : + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State and Errors functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The SMBUS HAL driver can be used as follows: + + (#) Declare a SMBUS_HandleTypeDef handle structure, for example: + SMBUS_HandleTypeDef hsmbus; + + (#)Initialize the SMBUS low level resources by implementing the HAL_SMBUS_MspInit() API: + (##) Enable the SMBUSx interface clock + (##) SMBUS pins configuration + (+++) Enable the clock for the SMBUS GPIOs + (+++) Configure SMBUS pins as alternate function open-drain + (##) NVIC configuration if you need to use interrupt process + (+++) Configure the SMBUSx interrupt priority + (+++) Enable the NVIC SMBUS IRQ Channel + + (#) Configure the Communication Clock Timing, Bus Timeout, Own Address1, Master Addressing mode, + Dual Addressing mode, Own Address2, Own Address2 Mask, General call, Nostretch mode, + Peripheral mode and Packet Error Check mode in the hsmbus Init structure. + + (#) Initialize the SMBUS registers by calling the HAL_SMBUS_Init() API: + (++) These API's configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) + by calling the customized HAL_SMBUS_MspInit(&hsmbus) API. + + (#) To check if target device is ready for communication, use the function HAL_SMBUS_IsDeviceReady() + + (#) For SMBUS IO operations, only one mode of operations is available within this driver + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Transmit in master/host SMBUS mode an amount of data in non-blocking mode + using HAL_SMBUS_Master_Transmit_IT() + (++) At transmission end of transfer HAL_SMBUS_MasterTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_SMBUS_MasterTxCpltCallback() + (+) Receive in master/host SMBUS mode an amount of data in non-blocking mode + using HAL_SMBUS_Master_Receive_IT() + (++) At reception end of transfer HAL_SMBUS_MasterRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_SMBUS_MasterRxCpltCallback() + (+) Abort a master/host SMBUS process communication with Interrupt using HAL_SMBUS_Master_Abort_IT() + (++) The associated previous transfer callback is called at the end of abort process + (++) mean HAL_SMBUS_MasterTxCpltCallback() in case of previous state was master transmit + (++) mean HAL_SMBUS_MasterRxCpltCallback() in case of previous state was master receive + (+) Enable/disable the Address listen mode in slave/device or host/slave SMBUS mode + using HAL_SMBUS_EnableListen_IT() HAL_SMBUS_DisableListen_IT() + (++) When address slave/device SMBUS match, HAL_SMBUS_AddrCallback() is executed and users can + add their own code to check the Address Match Code and the transmission direction + request by master/host (Write/Read). + (++) At Listen mode end HAL_SMBUS_ListenCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_SMBUS_ListenCpltCallback() + (+) Transmit in slave/device SMBUS mode an amount of data in non-blocking mode + using HAL_SMBUS_Slave_Transmit_IT() + (++) At transmission end of transfer HAL_SMBUS_SlaveTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_SMBUS_SlaveTxCpltCallback() + (+) Receive in slave/device SMBUS mode an amount of data in non-blocking mode + using HAL_SMBUS_Slave_Receive_IT() + (++) At reception end of transfer HAL_SMBUS_SlaveRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_SMBUS_SlaveRxCpltCallback() + (+) Enable/Disable the SMBUS alert mode using + HAL_SMBUS_EnableAlert_IT() or HAL_SMBUS_DisableAlert_IT() + (++) When SMBUS Alert is generated HAL_SMBUS_ErrorCallback() is executed and users can + add their own code by customization of function pointer HAL_SMBUS_ErrorCallback() + to check the Alert Error Code using function HAL_SMBUS_GetError() + (+) Get HAL state machine or error values using HAL_SMBUS_GetState() or HAL_SMBUS_GetError() + (+) In case of transfer Error, HAL_SMBUS_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_SMBUS_ErrorCallback() + to check the Error Code using function HAL_SMBUS_GetError() + + *** SMBUS HAL driver macros list *** + ================================== + [..] + Below the list of most used macros in SMBUS HAL driver. + + (+) __HAL_SMBUS_ENABLE: Enable the SMBUS peripheral + (+) __HAL_SMBUS_DISABLE: Disable the SMBUS peripheral + (+) __HAL_SMBUS_GET_FLAG: Check whether the specified SMBUS flag is set or not + (+) __HAL_SMBUS_CLEAR_FLAG: Clear the specified SMBUS pending flag + (+) __HAL_SMBUS_ENABLE_IT: Enable the specified SMBUS interrupt + (+) __HAL_SMBUS_DISABLE_IT: Disable the specified SMBUS interrupt + + *** Callback registration *** + ============================================= + [..] + The compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use Functions HAL_SMBUS_RegisterCallback() or HAL_SMBUS_RegisterAddrCallback() + to register an interrupt callback. + [..] + Function HAL_SMBUS_RegisterCallback() allows to register following callbacks: + (+) MasterTxCpltCallback : callback for Master transmission end of transfer. + (+) MasterRxCpltCallback : callback for Master reception end of transfer. + (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. + (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. + (+) ListenCpltCallback : callback for end of listen mode. + (+) ErrorCallback : callback for error detection. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + [..] + For specific callback AddrCallback use dedicated register callbacks : HAL_SMBUS_RegisterAddrCallback. + [..] + Use function HAL_SMBUS_UnRegisterCallback to reset a callback to the default + weak function. + HAL_SMBUS_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) MasterTxCpltCallback : callback for Master transmission end of transfer. + (+) MasterRxCpltCallback : callback for Master reception end of transfer. + (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. + (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. + (+) ListenCpltCallback : callback for end of listen mode. + (+) ErrorCallback : callback for error detection. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + [..] + For callback AddrCallback use dedicated register callbacks : HAL_SMBUS_UnRegisterAddrCallback. + [..] + By default, after the HAL_SMBUS_Init() and when the state is HAL_I2C_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples HAL_SMBUS_MasterTxCpltCallback(), HAL_SMBUS_MasterRxCpltCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak functions in the HAL_SMBUS_Init()/ HAL_SMBUS_DeInit() only when + these callbacks are null (not registered beforehand). + If MspInit or MspDeInit are not null, the HAL_SMBUS_Init()/ HAL_SMBUS_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + [..] + Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only. + Exception done MspInit/MspDeInit functions that can be registered/unregistered + in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + Then, the user first registers the MspInit/MspDeInit user callbacks + using HAL_SMBUS_RegisterCallback() before calling HAL_SMBUS_DeInit() + or HAL_SMBUS_Init() function. + [..] + When the compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + [..] + (@) You can refer to the SMBUS HAL driver header file for more useful macros + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @defgroup SMBUS SMBUS + * @brief SMBUS HAL module driver + * @{ + */ + +#ifdef HAL_SMBUS_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup SMBUS_Private_Define SMBUS Private Constants + * @{ + */ +#define TIMING_CLEAR_MASK (0xF0FFFFFFUL) /*!< SMBUS TIMING clear register Mask */ +#define HAL_TIMEOUT_ADDR (10000U) /*!< 10 s */ +#define HAL_TIMEOUT_BUSY (25U) /*!< 25 ms */ +#define HAL_TIMEOUT_DIR (25U) /*!< 25 ms */ +#define HAL_TIMEOUT_RXNE (25U) /*!< 25 ms */ +#define HAL_TIMEOUT_STOPF (25U) /*!< 25 ms */ +#define HAL_TIMEOUT_TC (25U) /*!< 25 ms */ +#define HAL_TIMEOUT_TCR (25U) /*!< 25 ms */ +#define HAL_TIMEOUT_TXIS (25U) /*!< 25 ms */ +#define MAX_NBYTE_SIZE 255U +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup SMBUS_Private_Functions SMBUS Private Functions + * @{ + */ +/* Private functions to handle flags during polling transfer */ +static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, + FlagStatus Status, uint32_t Timeout); + +/* Private functions for SMBUS transfer IRQ handler */ +static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags); +static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags); +static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus); + +/* Private functions to centralize the enable/disable of Interrupts */ +static void SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest); +static void SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest); + +/* Private function to flush TXDR register */ +static void SMBUS_Flush_TXDR(SMBUS_HandleTypeDef *hsmbus); + +/* Private function to handle start, restart or stop a transfer */ +static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, + uint32_t Mode, uint32_t Request); + +/* Private function to Convert Specific options */ +static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup SMBUS_Exported_Functions SMBUS Exported Functions + * @{ + */ + +/** @defgroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + deinitialize the SMBUSx peripheral: + + (+) User must Implement HAL_SMBUS_MspInit() function in which he configures + all related peripherals resources (CLOCK, GPIO, IT and NVIC ). + + (+) Call the function HAL_SMBUS_Init() to configure the selected device with + the selected configuration: + (++) Clock Timing + (++) Bus Timeout + (++) Analog Filer mode + (++) Own Address 1 + (++) Addressing mode (Master, Slave) + (++) Dual Addressing mode + (++) Own Address 2 + (++) Own Address 2 Mask + (++) General call mode + (++) Nostretch mode + (++) Packet Error Check mode + (++) Peripheral mode + + + (+) Call the function HAL_SMBUS_DeInit() to restore the default configuration + of the selected SMBUSx peripheral. + + (+) Enable/Disable Analog/Digital filters with HAL_SMBUS_ConfigAnalogFilter() and + HAL_SMBUS_ConfigDigitalFilter(). + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the SMBUS according to the specified parameters + * in the SMBUS_InitTypeDef and initialize the associated handle. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus) +{ + /* Check the SMBUS handle allocation */ + if (hsmbus == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance)); + assert_param(IS_SMBUS_ANALOG_FILTER(hsmbus->Init.AnalogFilter)); + assert_param(IS_SMBUS_OWN_ADDRESS1(hsmbus->Init.OwnAddress1)); + assert_param(IS_SMBUS_ADDRESSING_MODE(hsmbus->Init.AddressingMode)); + assert_param(IS_SMBUS_DUAL_ADDRESS(hsmbus->Init.DualAddressMode)); + assert_param(IS_SMBUS_OWN_ADDRESS2(hsmbus->Init.OwnAddress2)); + assert_param(IS_SMBUS_OWN_ADDRESS2_MASK(hsmbus->Init.OwnAddress2Masks)); + assert_param(IS_SMBUS_GENERAL_CALL(hsmbus->Init.GeneralCallMode)); + assert_param(IS_SMBUS_NO_STRETCH(hsmbus->Init.NoStretchMode)); + assert_param(IS_SMBUS_PEC(hsmbus->Init.PacketErrorCheckMode)); + assert_param(IS_SMBUS_PERIPHERAL_MODE(hsmbus->Init.PeripheralMode)); + + if (hsmbus->State == HAL_SMBUS_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hsmbus->Lock = HAL_UNLOCKED; + +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + hsmbus->MasterTxCpltCallback = HAL_SMBUS_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */ + hsmbus->MasterRxCpltCallback = HAL_SMBUS_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */ + hsmbus->SlaveTxCpltCallback = HAL_SMBUS_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */ + hsmbus->SlaveRxCpltCallback = HAL_SMBUS_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */ + hsmbus->ListenCpltCallback = HAL_SMBUS_ListenCpltCallback; /* Legacy weak ListenCpltCallback */ + hsmbus->ErrorCallback = HAL_SMBUS_ErrorCallback; /* Legacy weak ErrorCallback */ + hsmbus->AddrCallback = HAL_SMBUS_AddrCallback; /* Legacy weak AddrCallback */ + + if (hsmbus->MspInitCallback == NULL) + { + hsmbus->MspInitCallback = HAL_SMBUS_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + hsmbus->MspInitCallback(hsmbus); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + HAL_SMBUS_MspInit(hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ + } + + hsmbus->State = HAL_SMBUS_STATE_BUSY; + + /* Disable the selected SMBUS peripheral */ + __HAL_SMBUS_DISABLE(hsmbus); + + /*---------------------------- SMBUSx TIMINGR Configuration ------------------------*/ + /* Configure SMBUSx: Frequency range */ + hsmbus->Instance->TIMINGR = hsmbus->Init.Timing & TIMING_CLEAR_MASK; + + /*---------------------------- SMBUSx TIMEOUTR Configuration ------------------------*/ + /* Configure SMBUSx: Bus Timeout */ + hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TIMOUTEN; + hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TEXTEN; + hsmbus->Instance->TIMEOUTR = hsmbus->Init.SMBusTimeout; + + /*---------------------------- SMBUSx OAR1 Configuration -----------------------*/ + /* Configure SMBUSx: Own Address1 and ack own address1 mode */ + hsmbus->Instance->OAR1 &= ~I2C_OAR1_OA1EN; + + if (hsmbus->Init.OwnAddress1 != 0UL) + { + if (hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_7BIT) + { + hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN | hsmbus->Init.OwnAddress1); + } + } + + /*---------------------------- SMBUSx CR2 Configuration ------------------------*/ + /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process) */ + /* AUTOEND and NACK bit will be manage during Transfer process */ + hsmbus->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK); + + /*---------------------------- SMBUSx OAR2 Configuration -----------------------*/ + /* Configure SMBUSx: Dual mode and Own Address2 */ + hsmbus->Instance->OAR2 = (hsmbus->Init.DualAddressMode | hsmbus->Init.OwnAddress2 | \ + (hsmbus->Init.OwnAddress2Masks << 8U)); + + /*---------------------------- SMBUSx CR1 Configuration ------------------------*/ + /* Configure SMBUSx: Generalcall and NoStretch mode */ + hsmbus->Instance->CR1 = (hsmbus->Init.GeneralCallMode | hsmbus->Init.NoStretchMode | \ + hsmbus->Init.PacketErrorCheckMode | hsmbus->Init.PeripheralMode | \ + hsmbus->Init.AnalogFilter); + + /* Enable Slave Byte Control only in case of Packet Error Check is enabled + and SMBUS Peripheral is set in Slave mode */ + if ((hsmbus->Init.PacketErrorCheckMode == SMBUS_PEC_ENABLE) && \ + ((hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \ + (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))) + { + hsmbus->Instance->CR1 |= I2C_CR1_SBC; + } + + /* Enable the selected SMBUS peripheral */ + __HAL_SMBUS_ENABLE(hsmbus); + + hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; + hsmbus->PreviousState = HAL_SMBUS_STATE_READY; + hsmbus->State = HAL_SMBUS_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitialize the SMBUS peripheral. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus) +{ + /* Check the SMBUS handle allocation */ + if (hsmbus == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance)); + + hsmbus->State = HAL_SMBUS_STATE_BUSY; + + /* Disable the SMBUS Peripheral Clock */ + __HAL_SMBUS_DISABLE(hsmbus); + +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + if (hsmbus->MspDeInitCallback == NULL) + { + hsmbus->MspDeInitCallback = HAL_SMBUS_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + hsmbus->MspDeInitCallback(hsmbus); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_SMBUS_MspDeInit(hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ + + hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; + hsmbus->PreviousState = HAL_SMBUS_STATE_RESET; + hsmbus->State = HAL_SMBUS_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hsmbus); + + return HAL_OK; +} + +/** + * @brief Initialize the SMBUS MSP. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @retval None + */ +__weak void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsmbus); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMBUS_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitialize the SMBUS MSP. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @retval None + */ +__weak void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsmbus); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMBUS_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Configure Analog noise filter. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @param AnalogFilter This parameter can be one of the following values: + * @arg @ref SMBUS_ANALOGFILTER_ENABLE + * @arg @ref SMBUS_ANALOGFILTER_DISABLE + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter) +{ + /* Check the parameters */ + assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance)); + assert_param(IS_SMBUS_ANALOG_FILTER(AnalogFilter)); + + if (hsmbus->State == HAL_SMBUS_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsmbus); + + hsmbus->State = HAL_SMBUS_STATE_BUSY; + + /* Disable the selected SMBUS peripheral */ + __HAL_SMBUS_DISABLE(hsmbus); + + /* Reset ANOFF bit */ + hsmbus->Instance->CR1 &= ~(I2C_CR1_ANFOFF); + + /* Set analog filter bit*/ + hsmbus->Instance->CR1 |= AnalogFilter; + + __HAL_SMBUS_ENABLE(hsmbus); + + hsmbus->State = HAL_SMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Configure Digital noise filter. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter) +{ + uint32_t tmpreg; + + /* Check the parameters */ + assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance)); + assert_param(IS_SMBUS_DIGITAL_FILTER(DigitalFilter)); + + if (hsmbus->State == HAL_SMBUS_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsmbus); + + hsmbus->State = HAL_SMBUS_STATE_BUSY; + + /* Disable the selected SMBUS peripheral */ + __HAL_SMBUS_DISABLE(hsmbus); + + /* Get the old register value */ + tmpreg = hsmbus->Instance->CR1; + + /* Reset I2C DNF bits [11:8] */ + tmpreg &= ~(I2C_CR1_DNF); + + /* Set I2Cx DNF coefficient */ + tmpreg |= DigitalFilter << I2C_CR1_DNF_Pos; + + /* Store the new register value */ + hsmbus->Instance->CR1 = tmpreg; + + __HAL_SMBUS_ENABLE(hsmbus); + + hsmbus->State = HAL_SMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User SMBUS Callback + * To be used instead of the weak predefined callback + * @note The HAL_SMBUS_RegisterCallback() may be called before HAL_SMBUS_Init() in + * HAL_SMBUS_STATE_RESET to register callbacks for HAL_SMBUS_MSPINIT_CB_ID and + * HAL_SMBUS_MSPDEINIT_CB_ID. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID + * @arg @ref HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID + * @arg @ref HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID + * @arg @ref HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID + * @arg @ref HAL_SMBUS_LISTEN_COMPLETE_CB_ID Listen Complete callback ID + * @arg @ref HAL_SMBUS_ERROR_CB_ID Error callback ID + * @arg @ref HAL_SMBUS_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_SMBUS_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, + HAL_SMBUS_CallbackIDTypeDef CallbackID, + pSMBUS_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (HAL_SMBUS_STATE_READY == hsmbus->State) + { + switch (CallbackID) + { + case HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID : + hsmbus->MasterTxCpltCallback = pCallback; + break; + + case HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID : + hsmbus->MasterRxCpltCallback = pCallback; + break; + + case HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID : + hsmbus->SlaveTxCpltCallback = pCallback; + break; + + case HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID : + hsmbus->SlaveRxCpltCallback = pCallback; + break; + + case HAL_SMBUS_LISTEN_COMPLETE_CB_ID : + hsmbus->ListenCpltCallback = pCallback; + break; + + case HAL_SMBUS_ERROR_CB_ID : + hsmbus->ErrorCallback = pCallback; + break; + + case HAL_SMBUS_MSPINIT_CB_ID : + hsmbus->MspInitCallback = pCallback; + break; + + case HAL_SMBUS_MSPDEINIT_CB_ID : + hsmbus->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_SMBUS_STATE_RESET == hsmbus->State) + { + switch (CallbackID) + { + case HAL_SMBUS_MSPINIT_CB_ID : + hsmbus->MspInitCallback = pCallback; + break; + + case HAL_SMBUS_MSPDEINIT_CB_ID : + hsmbus->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister an SMBUS Callback + * SMBUS callback is redirected to the weak predefined callback + * @note The HAL_SMBUS_UnRegisterCallback() may be called before HAL_SMBUS_Init() in + * HAL_SMBUS_STATE_RESET to un-register callbacks for HAL_SMBUS_MSPINIT_CB_ID and + * HAL_SMBUS_MSPDEINIT_CB_ID + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * This parameter can be one of the following values: + * @arg @ref HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID + * @arg @ref HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID + * @arg @ref HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID + * @arg @ref HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID + * @arg @ref HAL_SMBUS_LISTEN_COMPLETE_CB_ID Listen Complete callback ID + * @arg @ref HAL_SMBUS_ERROR_CB_ID Error callback ID + * @arg @ref HAL_SMBUS_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_SMBUS_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, + HAL_SMBUS_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (HAL_SMBUS_STATE_READY == hsmbus->State) + { + switch (CallbackID) + { + case HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID : + hsmbus->MasterTxCpltCallback = HAL_SMBUS_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */ + break; + + case HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID : + hsmbus->MasterRxCpltCallback = HAL_SMBUS_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */ + break; + + case HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID : + hsmbus->SlaveTxCpltCallback = HAL_SMBUS_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */ + break; + + case HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID : + hsmbus->SlaveRxCpltCallback = HAL_SMBUS_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */ + break; + + case HAL_SMBUS_LISTEN_COMPLETE_CB_ID : + hsmbus->ListenCpltCallback = HAL_SMBUS_ListenCpltCallback; /* Legacy weak ListenCpltCallback */ + break; + + case HAL_SMBUS_ERROR_CB_ID : + hsmbus->ErrorCallback = HAL_SMBUS_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_SMBUS_MSPINIT_CB_ID : + hsmbus->MspInitCallback = HAL_SMBUS_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_SMBUS_MSPDEINIT_CB_ID : + hsmbus->MspDeInitCallback = HAL_SMBUS_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_SMBUS_STATE_RESET == hsmbus->State) + { + switch (CallbackID) + { + case HAL_SMBUS_MSPINIT_CB_ID : + hsmbus->MspInitCallback = HAL_SMBUS_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_SMBUS_MSPDEINIT_CB_ID : + hsmbus->MspDeInitCallback = HAL_SMBUS_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Register the Slave Address Match SMBUS Callback + * To be used instead of the weak HAL_SMBUS_AddrCallback() predefined callback + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @param pCallback pointer to the Address Match Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, + pSMBUS_AddrCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (HAL_SMBUS_STATE_READY == hsmbus->State) + { + hsmbus->AddrCallback = pCallback; + } + else + { + /* Update the error code */ + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief UnRegister the Slave Address Match SMBUS Callback + * Info Ready SMBUS Callback is redirected to the weak HAL_SMBUS_AddrCallback() predefined callback + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (HAL_SMBUS_STATE_READY == hsmbus->State) + { + hsmbus->AddrCallback = HAL_SMBUS_AddrCallback; /* Legacy weak AddrCallback */ + } + else + { + /* Update the error code */ + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup SMBUS_Exported_Functions_Group2 Input and Output operation functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the SMBUS data + transfers. + + (#) Blocking mode function to check if device is ready for usage is : + (++) HAL_SMBUS_IsDeviceReady() + + (#) There is only one mode of transfer: + (++) Non-Blocking mode : The communication is performed using Interrupts. + These functions return the status of the transfer startup. + The end of the data processing will be indicated through the + dedicated SMBUS IRQ when using Interrupt mode. + + (#) Non-Blocking mode functions with Interrupt are : + (++) HAL_SMBUS_Master_Transmit_IT() + (++) HAL_SMBUS_Master_Receive_IT() + (++) HAL_SMBUS_Slave_Transmit_IT() + (++) HAL_SMBUS_Slave_Receive_IT() + (++) HAL_SMBUS_EnableListen_IT() or alias HAL_SMBUS_EnableListen_IT() + (++) HAL_SMBUS_DisableListen_IT() + (++) HAL_SMBUS_EnableAlert_IT() + (++) HAL_SMBUS_DisableAlert_IT() + + (#) A set of Transfer Complete Callbacks are provided in non-Blocking mode: + (++) HAL_SMBUS_MasterTxCpltCallback() + (++) HAL_SMBUS_MasterRxCpltCallback() + (++) HAL_SMBUS_SlaveTxCpltCallback() + (++) HAL_SMBUS_SlaveRxCpltCallback() + (++) HAL_SMBUS_AddrCallback() + (++) HAL_SMBUS_ListenCpltCallback() + (++) HAL_SMBUS_ErrorCallback() + +@endverbatim + * @{ + */ + +/** + * @brief Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, + uint8_t *pData, uint16_t Size, uint32_t XferOptions) +{ + uint32_t tmp; + + /* Check the parameters */ + assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hsmbus->State == HAL_SMBUS_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsmbus); + + hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX; + hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; + /* Prepare transfer parameters */ + hsmbus->pBuffPtr = pData; + hsmbus->XferCount = Size; + hsmbus->XferOptions = XferOptions; + + /* In case of Quick command, remove autoend mode */ + /* Manage the stop generation by software */ + if (hsmbus->pBuffPtr == NULL) + { + hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE; + } + + if (Size > MAX_NBYTE_SIZE) + { + hsmbus->XferSize = MAX_NBYTE_SIZE; + } + else + { + hsmbus->XferSize = Size; + } + + /* Send Slave Address */ + /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ + if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE)) + { + /* Check if the Autonomous mode is enabled */ + if ((hsmbus->Instance->AUTOCR & I2C_AUTOCR_TRIGEN) == I2C_AUTOCR_TRIGEN) + { + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, + SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), + SMBUS_GENERATE_NO_START_WRITE); + } + else + { + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, + SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), + SMBUS_GENERATE_START_WRITE); + } + } + else + { + /* If transfer direction not change, do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + + /* Store current volatile XferOptions, misra rule */ + tmp = hsmbus->XferOptions; + + if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) && \ + (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0)) + { + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, + SMBUS_NO_STARTSTOP); + } + /* Else transfer direction change, so generate Restart with new transfer direction */ + else + { + /* Convert OTHER_xxx XferOptions if any */ + SMBUS_ConvertOtherXferOptions(hsmbus); + + /* Handle Transfer */ + /* Check if the Autonomous mode is enabled */ + if ((hsmbus->Instance->AUTOCR & I2C_AUTOCR_TRIGEN) == I2C_AUTOCR_TRIGEN) + { + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, + hsmbus->XferOptions, + SMBUS_GENERATE_NO_START_WRITE); + } + else + { + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, + hsmbus->XferOptions, + SMBUS_GENERATE_START_WRITE); + } + } + + /* If PEC mode is enable, size to transmit manage by SW part should be Size-1 byte, corresponding to PEC byte */ + /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ + if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL) + { + if (hsmbus->XferSize > 0U) + { + hsmbus->XferSize--; + hsmbus->XferCount--; + } + else + { + return HAL_ERROR; + } + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + /* Note : The SMBUS interrupts must be enabled after unlocking current process + to avoid the risk of SMBUS interrupt handle execution before current + process unlock */ + SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) +{ + uint32_t tmp; + + /* Check the parameters */ + assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hsmbus->State == HAL_SMBUS_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsmbus); + + hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX; + hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; + + /* Prepare transfer parameters */ + hsmbus->pBuffPtr = pData; + hsmbus->XferCount = Size; + hsmbus->XferOptions = XferOptions; + + /* In case of Quick command, remove autoend mode */ + /* Manage the stop generation by software */ + if (hsmbus->pBuffPtr == NULL) + { + hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE; + } + + if (Size > MAX_NBYTE_SIZE) + { + hsmbus->XferSize = MAX_NBYTE_SIZE; + } + else + { + hsmbus->XferSize = Size; + } + + /* Send Slave Address */ + /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ + if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE)) + { + /* Check if the Autonomous mode is enabled */ + if ((hsmbus->Instance->AUTOCR & I2C_AUTOCR_TRIGEN) == I2C_AUTOCR_TRIGEN) + { + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, + SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), + SMBUS_GENERATE_NO_START_READ); + } + else + { + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, + SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), + SMBUS_GENERATE_START_READ); + } + } + else + { + /* If transfer direction not change, do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + + /* Store current volatile XferOptions, Misra rule */ + tmp = hsmbus->XferOptions; + + if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) && \ + (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0)) + { + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, + SMBUS_NO_STARTSTOP); + } + /* Else transfer direction change, so generate Restart with new transfer direction */ + else + { + /* Convert OTHER_xxx XferOptions if any */ + SMBUS_ConvertOtherXferOptions(hsmbus); + + /* Handle Transfer */ + /* Check if the Autonomous mode is enabled */ + if ((hsmbus->Instance->AUTOCR & I2C_AUTOCR_TRIGEN) == I2C_AUTOCR_TRIGEN) + { + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, + hsmbus->XferOptions, + SMBUS_GENERATE_NO_START_READ); + } + else + { + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, + hsmbus->XferOptions, + SMBUS_GENERATE_START_READ); + } + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + /* Note : The SMBUS interrupts must be enabled after unlocking current process + to avoid the risk of SMBUS interrupt handle execution before current + process unlock */ + SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Abort a master/host SMBUS process communication with Interrupt. + * @note This abort can be called only if state is ready + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress) +{ + if (hsmbus->State == HAL_SMBUS_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsmbus); + + /* Keep the same state as previous */ + /* to perform as well the call of the corresponding end of transfer callback */ + if (hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) + { + hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX; + } + else if (hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) + { + hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX; + } + else + { + /* Wrong usage of abort function */ + /* This function should be used only in case of abort monitored by master device */ + return HAL_ERROR; + } + hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; + + /* Set NBYTES to 1 to generate a dummy read on SMBUS peripheral */ + /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */ + SMBUS_TransferConfig(hsmbus, DevAddress, 1, SMBUS_AUTOEND_MODE, SMBUS_NO_STARTSTOP); + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + /* Note : The SMBUS interrupts must be enabled after unlocking current process + to avoid the risk of SMBUS interrupt handle execution before current + process unlock */ + if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX) + { + SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX); + } + else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) + { + SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX); + } + else + { + /* Nothing to do */ + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) +{ + /* Check the parameters */ + assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0UL)) + { + hsmbus->ErrorCode = HAL_SMBUS_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR | SMBUS_IT_TX); + + /* Process Locked */ + __HAL_LOCK(hsmbus); + + hsmbus->State = (HAL_SMBUS_STATE_SLAVE_BUSY_TX | HAL_SMBUS_STATE_LISTEN); + hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; + + /* Set SBC bit to manage Acknowledge at each bit */ + hsmbus->Instance->CR1 |= I2C_CR1_SBC; + + /* Enable Address Acknowledge */ + hsmbus->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hsmbus->pBuffPtr = pData; + hsmbus->XferCount = Size; + hsmbus->XferOptions = XferOptions; + + /* Convert OTHER_xxx XferOptions if any */ + SMBUS_ConvertOtherXferOptions(hsmbus); + + if (Size > MAX_NBYTE_SIZE) + { + hsmbus->XferSize = MAX_NBYTE_SIZE; + } + else + { + hsmbus->XferSize = Size; + } + + /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ + if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE)) + { + SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, + SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), + SMBUS_NO_STARTSTOP); + } + else + { + /* Set NBYTE to transmit */ + SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, + SMBUS_NO_STARTSTOP); + + /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ + /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ + if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL) + { + hsmbus->XferSize--; + hsmbus->XferCount--; + } + } + + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the HOST */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR); + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + /* Note : The SMBUS interrupts must be enabled after unlocking current process + to avoid the risk of SMBUS interrupt handle execution before current + process unlock */ + /* REnable ADDR interrupt */ + SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX | SMBUS_IT_ADDR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) +{ + /* Check the parameters */ + assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0UL)) + { + hsmbus->ErrorCode = HAL_SMBUS_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR | SMBUS_IT_RX); + + /* Process Locked */ + __HAL_LOCK(hsmbus); + + hsmbus->State = (HAL_SMBUS_STATE_SLAVE_BUSY_RX | HAL_SMBUS_STATE_LISTEN); + hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; + + /* Set SBC bit to manage Acknowledge at each bit */ + hsmbus->Instance->CR1 |= I2C_CR1_SBC; + + /* Enable Address Acknowledge */ + hsmbus->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hsmbus->pBuffPtr = pData; + hsmbus->XferSize = Size; + hsmbus->XferCount = Size; + hsmbus->XferOptions = XferOptions; + + /* Convert OTHER_xxx XferOptions if any */ + SMBUS_ConvertOtherXferOptions(hsmbus); + + /* Set NBYTE to receive */ + /* If XferSize equal "1", or XferSize equal "2" with PEC requested (mean 1 data byte + 1 PEC byte */ + /* no need to set RELOAD bit mode, a ACK will be automatically generated in that case */ + /* else need to set RELOAD bit mode to generate an automatic ACK at each byte Received */ + /* This RELOAD bit will be reset for last BYTE to be receive in SMBUS_Slave_ISR */ + if (((SMBUS_GET_PEC_MODE(hsmbus) != 0UL) && (hsmbus->XferSize == 2U)) || (hsmbus->XferSize == 1U)) + { + SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, + SMBUS_NO_STARTSTOP); + } + else + { + SMBUS_TransferConfig(hsmbus, 0, 1, hsmbus->XferOptions | SMBUS_RELOAD_MODE, SMBUS_NO_STARTSTOP); + } + + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the HOST */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR); + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + /* Note : The SMBUS interrupts must be enabled after unlocking current process + to avoid the risk of SMBUS interrupt handle execution before current + process unlock */ + /* REnable ADDR interrupt */ + SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_ADDR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Enable the Address listen mode with Interrupt. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus) +{ + hsmbus->State = HAL_SMBUS_STATE_LISTEN; + + /* Enable the Address Match interrupt */ + SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ADDR); + + return HAL_OK; +} + +/** + * @brief Disable the Address listen mode with Interrupt. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus) +{ + /* Disable Address listen mode only if a transfer is not ongoing */ + if (hsmbus->State == HAL_SMBUS_STATE_LISTEN) + { + hsmbus->State = HAL_SMBUS_STATE_READY; + + /* Disable the Address Match interrupt */ + SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Enable the SMBUS alert mode with Interrupt. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUSx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus) +{ + /* Enable SMBus alert */ + hsmbus->Instance->CR1 |= I2C_CR1_ALERTEN; + + /* Clear ALERT flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT); + + /* Enable Alert Interrupt */ + SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ALERT); + + return HAL_OK; +} +/** + * @brief Disable the SMBUS alert mode with Interrupt. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUSx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus) +{ + /* Enable SMBus alert */ + hsmbus->Instance->CR1 &= ~I2C_CR1_ALERTEN; + + /* Disable Alert Interrupt */ + SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ALERT); + + return HAL_OK; +} + +/** + * @brief Check if target device is ready for communication. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param Trials Number of trials + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, + uint32_t Timeout) +{ + uint32_t tickstart; + + __IO uint32_t SMBUS_Trials = 0UL; + + FlagStatus tmp1; + FlagStatus tmp2; + + if (hsmbus->State == HAL_SMBUS_STATE_READY) + { + if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BUSY) != RESET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hsmbus); + + hsmbus->State = HAL_SMBUS_STATE_BUSY; + hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; + + do + { + /* Generate Start */ + hsmbus->Instance->CR2 = SMBUS_GENERATE_START(hsmbus->Init.AddressingMode, DevAddress); + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is set or a NACK flag is set*/ + tickstart = HAL_GetTick(); + + tmp1 = __HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF); + tmp2 = __HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF); + + while ((tmp1 == RESET) && (tmp2 == RESET)) + { + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) + { + /* Device is ready */ + hsmbus->State = HAL_SMBUS_STATE_READY; + + /* Update SMBUS error code */ + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_HALTIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + return HAL_ERROR; + } + } + + tmp1 = __HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF); + tmp2 = __HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF); + } + + /* Check if the NACKF flag has not been set */ + if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET) + { + /* Wait until STOPF flag is reset */ + if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); + + /* Device is ready */ + hsmbus->State = HAL_SMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + return HAL_OK; + } + else + { + /* Wait until STOPF flag is reset */ + if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear NACK Flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF); + + /* Clear STOP Flag, auto generated with autoend*/ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); + } + + /* Check if the maximum allowed number of trials has been reached */ + if (SMBUS_Trials == Trials) + { + /* Generate Stop */ + hsmbus->Instance->CR2 |= I2C_CR2_STOP; + + /* Wait until STOPF flag is reset */ + if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); + } + + /* Increment Trials */ + SMBUS_Trials++; + } while (SMBUS_Trials < Trials); + + hsmbus->State = HAL_SMBUS_STATE_READY; + + /* Update SMBUS error code */ + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_HALTIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + return HAL_ERROR; + } + else + { + return HAL_BUSY; + } +} +/** + * @} + */ + +/** @defgroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks + * @{ + */ + +/** + * @brief Handle SMBUS event interrupt request. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @retval None + */ +void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus) +{ + /* Use a local variable to store the current ISR flags */ + /* This action will avoid a wrong treatment due to ISR flags change during interrupt handler */ + uint32_t tmpisrvalue = READ_REG(hsmbus->Instance->ISR); + uint32_t tmpcr1value = READ_REG(hsmbus->Instance->CR1); + + /* SMBUS in mode Transmitter ---------------------------------------------------*/ + if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI | + SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET) && + ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) || + (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || + (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || + (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || + (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET))) + { + /* Slave mode selected */ + if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX) + { + (void)SMBUS_Slave_ISR(hsmbus, tmpisrvalue); + } + /* Master mode selected */ + else if ((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_TX) == HAL_SMBUS_STATE_MASTER_BUSY_TX) + { + (void)SMBUS_Master_ISR(hsmbus, tmpisrvalue); + } + else + { + /* Nothing to do */ + } + } + + /* SMBUS in mode Receiver ----------------------------------------------------*/ + if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI | + SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET) && + ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) || + (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || + (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || + (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || + (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET))) + { + /* Slave mode selected */ + if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX) + { + (void)SMBUS_Slave_ISR(hsmbus, tmpisrvalue); + } + /* Master mode selected */ + else if ((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_RX) == HAL_SMBUS_STATE_MASTER_BUSY_RX) + { + (void)SMBUS_Master_ISR(hsmbus, tmpisrvalue); + } + else + { + /* Nothing to do */ + } + } + + /* SMBUS in mode Listener Only --------------------------------------------------*/ + if (((SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_ADDRI) != RESET) || + (SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_STOPI) != RESET) || + (SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_NACKI) != RESET)) && + ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_ADDR) != RESET) || + (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || + (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET))) + { + if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN) + { + (void)SMBUS_Slave_ISR(hsmbus, tmpisrvalue); + } + } +} + +/** + * @brief Handle SMBUS error interrupt request. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @retval None + */ +void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus) +{ + SMBUS_ITErrorHandler(hsmbus); +} + +/** + * @brief Master Tx Transfer completed callback. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @retval None + */ +__weak void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsmbus); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMBUS_MasterTxCpltCallback() could be implemented in the user file + */ +} + +/** + * @brief Master Rx Transfer completed callback. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @retval None + */ +__weak void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsmbus); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMBUS_MasterRxCpltCallback() could be implemented in the user file + */ +} + +/** @brief Slave Tx Transfer completed callback. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @retval None + */ +__weak void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsmbus); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMBUS_SlaveTxCpltCallback() could be implemented in the user file + */ +} + +/** + * @brief Slave Rx Transfer completed callback. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @retval None + */ +__weak void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsmbus); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMBUS_SlaveRxCpltCallback() could be implemented in the user file + */ +} + +/** + * @brief Slave Address Match callback. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @param TransferDirection Master request Transfer Direction (Write/Read) + * @param AddrMatchCode Address Match Code + * @retval None + */ +__weak void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, + uint16_t AddrMatchCode) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsmbus); + UNUSED(TransferDirection); + UNUSED(AddrMatchCode); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMBUS_AddrCallback() could be implemented in the user file + */ +} + +/** + * @brief Listen Complete callback. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @retval None + */ +__weak void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsmbus); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMBUS_ListenCpltCallback() could be implemented in the user file + */ +} + +/** + * @brief SMBUS error callback. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @retval None + */ +__weak void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsmbus); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SMBUS_ErrorCallback() could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief Peripheral State and Errors functions + * +@verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the SMBUS handle state. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @retval HAL state + */ +uint32_t HAL_SMBUS_GetState(const SMBUS_HandleTypeDef *hsmbus) +{ + /* Return SMBUS handle state */ + return hsmbus->State; +} + +/** + * @brief Return the SMBUS error code. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @retval SMBUS Error Code + */ +uint32_t HAL_SMBUS_GetError(const SMBUS_HandleTypeDef *hsmbus) +{ + return hsmbus->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup SMBUS_Private_Functions SMBUS Private Functions + * @brief Data transfers Private functions + * @{ + */ + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @param StatusFlags Value of Interrupt Flags. + * @retval HAL status + */ +static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags) +{ + uint16_t DevAddress; + + /* Process Locked */ + __HAL_LOCK(hsmbus); + + if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_AF) != RESET) + { + /* Clear NACK Flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF); + + /* Set corresponding Error Code */ + /* No need to generate STOP, it is automatically done */ + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF; + + /* Flush TX register */ + SMBUS_Flush_TXDR(hsmbus); + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + /* Call the Error callback to inform upper layer */ +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + hsmbus->ErrorCallback(hsmbus); +#else + HAL_SMBUS_ErrorCallback(hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ + } + else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_STOPF) != RESET) + { + /* Check and treat errors if errors occurs during STOP process */ + SMBUS_ITErrorHandler(hsmbus); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX) + { + /* Disable Interrupt */ + SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX); + + /* Clear STOP Flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + SMBUS_RESET_CR2(hsmbus); + + /* Flush remaining data in Fifo register in case of error occurs before TXEmpty */ + /* Disable the selected SMBUS peripheral */ + __HAL_SMBUS_DISABLE(hsmbus); + + hsmbus->PreviousState = HAL_SMBUS_STATE_READY; + hsmbus->State = HAL_SMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + /* Re-enable the selected SMBUS peripheral */ + __HAL_SMBUS_ENABLE(hsmbus); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + hsmbus->MasterTxCpltCallback(hsmbus); +#else + HAL_SMBUS_MasterTxCpltCallback(hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ + } + else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) + { + /* Store Last receive data if any */ + if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_RXNE) != RESET) + { + /* Read data from RXDR */ + *hsmbus->pBuffPtr = (uint8_t)(hsmbus->Instance->RXDR); + + /* Increment Buffer pointer */ + hsmbus->pBuffPtr++; + + if ((hsmbus->XferSize > 0U)) + { + hsmbus->XferSize--; + hsmbus->XferCount--; + } + } + + /* Disable Interrupt */ + SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX); + + /* Clear STOP Flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + SMBUS_RESET_CR2(hsmbus); + + hsmbus->PreviousState = HAL_SMBUS_STATE_READY; + hsmbus->State = HAL_SMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + hsmbus->MasterRxCpltCallback(hsmbus); +#else + HAL_SMBUS_MasterRxCpltCallback(hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ + } + else + { + /* Nothing to do */ + } + } + else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_RXNE) != RESET) + { + /* Read data from RXDR */ + *hsmbus->pBuffPtr = (uint8_t)(hsmbus->Instance->RXDR); + + /* Increment Buffer pointer */ + hsmbus->pBuffPtr++; + + /* Increment Size counter */ + hsmbus->XferSize--; + hsmbus->XferCount--; + } + else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TXIS) != RESET) + { + /* Write data to TXDR */ + hsmbus->Instance->TXDR = *hsmbus->pBuffPtr; + + /* Increment Buffer pointer */ + hsmbus->pBuffPtr++; + + /* Increment Size counter */ + hsmbus->XferSize--; + hsmbus->XferCount--; + } + else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TCR) != RESET) + { + if ((hsmbus->XferCount != 0U) && (hsmbus->XferSize == 0U)) + { + DevAddress = (uint16_t)(hsmbus->Instance->CR2 & I2C_CR2_SADD); + + if (hsmbus->XferCount > MAX_NBYTE_SIZE) + { + SMBUS_TransferConfig(hsmbus, DevAddress, MAX_NBYTE_SIZE, + (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), + SMBUS_NO_STARTSTOP); + hsmbus->XferSize = MAX_NBYTE_SIZE; + } + else + { + hsmbus->XferSize = hsmbus->XferCount; + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, + SMBUS_NO_STARTSTOP); + /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ + /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ + if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL) + { + hsmbus->XferSize--; + hsmbus->XferCount--; + } + } + } + else if ((hsmbus->XferCount == 0U) && (hsmbus->XferSize == 0U)) + { + /* Call TxCpltCallback() if no stop mode is set */ + if (SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX) + { + /* Disable Interrupt */ + SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX); + hsmbus->PreviousState = hsmbus->State; + hsmbus->State = HAL_SMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + hsmbus->MasterTxCpltCallback(hsmbus); +#else + HAL_SMBUS_MasterTxCpltCallback(hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ + } + else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) + { + SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX); + hsmbus->PreviousState = hsmbus->State; + hsmbus->State = HAL_SMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + hsmbus->MasterRxCpltCallback(hsmbus); +#else + HAL_SMBUS_MasterRxCpltCallback(hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ + } + else + { + /* Nothing to do */ + } + } + } + else + { + /* Nothing to do */ + } + } + else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TC) != RESET) + { + if (hsmbus->XferCount == 0U) + { + /* Specific use case for Quick command */ + if (hsmbus->pBuffPtr == NULL) + { + /* Generate a Stop command */ + hsmbus->Instance->CR2 |= I2C_CR2_STOP; + } + /* Call TxCpltCallback() if no stop mode is set */ + else if (SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE) + { + /* No Generate Stop, to permit restart mode */ + /* The stop will be done at the end of transfer, when SMBUS_AUTOEND_MODE enable */ + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX) + { + /* Disable Interrupt */ + SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX); + hsmbus->PreviousState = hsmbus->State; + hsmbus->State = HAL_SMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + hsmbus->MasterTxCpltCallback(hsmbus); +#else + HAL_SMBUS_MasterTxCpltCallback(hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ + } + else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) + { + SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX); + hsmbus->PreviousState = hsmbus->State; + hsmbus->State = HAL_SMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + hsmbus->MasterRxCpltCallback(hsmbus); +#else + HAL_SMBUS_MasterRxCpltCallback(hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ + } + else + { + /* Nothing to do */ + } + } + else + { + /* Nothing to do */ + } + } + } + else + { + /* Nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + return HAL_OK; +} +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @param StatusFlags Value of Interrupt Flags. + * @retval HAL status + */ +static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags) +{ + uint8_t TransferDirection; + uint16_t SlaveAddrCode; + + /* Process Locked */ + __HAL_LOCK(hsmbus); + + if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_AF) != RESET) + { + /* Check that SMBUS transfer finished */ + /* if yes, normal usecase, a NACK is sent by the HOST when Transfer is finished */ + /* Mean XferCount == 0*/ + /* So clear Flag NACKF only */ + if (hsmbus->XferCount == 0U) + { + /* Clear NACK Flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF); + + /* Flush TX register */ + SMBUS_Flush_TXDR(hsmbus); + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + } + else + { + /* if no, error usecase, a Non-Acknowledge of last Data is generated by the HOST*/ + /* Clear NACK Flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF); + + /* Set HAL State to "Idle" State, mean to LISTEN state */ + /* So reset Slave Busy state */ + hsmbus->PreviousState = hsmbus->State; + hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_TX); + hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_RX); + + /* Disable RX/TX Interrupts, keep only ADDR Interrupt */ + SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_TX); + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF; + + /* Flush TX register */ + SMBUS_Flush_TXDR(hsmbus); + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + /* Call the Error callback to inform upper layer */ +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + hsmbus->ErrorCallback(hsmbus); +#else + HAL_SMBUS_ErrorCallback(hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ + } + } + else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_ADDR) != RESET) + { + TransferDirection = (uint8_t)(SMBUS_GET_DIR(hsmbus)); + SlaveAddrCode = (uint16_t)(SMBUS_GET_ADDR_MATCH(hsmbus)); + + /* Disable ADDR interrupt to prevent multiple ADDRInterrupt*/ + /* Other ADDRInterrupt will be treat in next Listen usecase */ + __HAL_SMBUS_DISABLE_IT(hsmbus, SMBUS_IT_ADDRI); + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + /* Call Slave Addr callback */ +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + hsmbus->AddrCallback(hsmbus, TransferDirection, SlaveAddrCode); +#else + HAL_SMBUS_AddrCallback(hsmbus, TransferDirection, SlaveAddrCode); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ + } + else if ((SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_RXNE) != RESET) || + (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TCR) != RESET)) + { + if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX) + { + /* Read data from RXDR */ + *hsmbus->pBuffPtr = (uint8_t)(hsmbus->Instance->RXDR); + + /* Increment Buffer pointer */ + hsmbus->pBuffPtr++; + + hsmbus->XferSize--; + hsmbus->XferCount--; + + if (hsmbus->XferCount == 1U) + { + /* Receive last Byte, can be PEC byte in case of PEC BYTE enabled */ + /* or only the last Byte of Transfer */ + /* So reset the RELOAD bit mode */ + hsmbus->XferOptions &= ~SMBUS_RELOAD_MODE; + SMBUS_TransferConfig(hsmbus, 0, 1, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); + } + else if (hsmbus->XferCount == 0U) + { + /* Last Byte is received, disable Interrupt */ + SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX); + + /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_RX, keep only HAL_SMBUS_STATE_LISTEN */ + hsmbus->PreviousState = hsmbus->State; + hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_RX); + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + hsmbus->SlaveRxCpltCallback(hsmbus); +#else + HAL_SMBUS_SlaveRxCpltCallback(hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ + } + else + { + /* Set Reload for next Bytes */ + SMBUS_TransferConfig(hsmbus, 0, 1, + SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), + SMBUS_NO_STARTSTOP); + + /* Ack last Byte Read */ + hsmbus->Instance->CR2 &= ~I2C_CR2_NACK; + } + } + else if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX) + { + if ((hsmbus->XferCount != 0U) && (hsmbus->XferSize == 0U)) + { + if (hsmbus->XferCount > MAX_NBYTE_SIZE) + { + SMBUS_TransferConfig(hsmbus, 0, MAX_NBYTE_SIZE, + (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), + SMBUS_NO_STARTSTOP); + hsmbus->XferSize = MAX_NBYTE_SIZE; + } + else + { + hsmbus->XferSize = hsmbus->XferCount; + SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, + SMBUS_NO_STARTSTOP); + /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ + /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ + if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL) + { + hsmbus->XferSize--; + hsmbus->XferCount--; + } + } + } + } + else + { + /* Nothing to do */ + } + } + else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TXIS) != RESET) + { + /* Write data to TXDR only if XferCount not reach "0" */ + /* A TXIS flag can be set, during STOP treatment */ + /* Check if all Data have already been sent */ + /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ + if (hsmbus->XferCount > 0U) + { + /* Write data to TXDR */ + hsmbus->Instance->TXDR = *hsmbus->pBuffPtr; + + /* Increment Buffer pointer */ + hsmbus->pBuffPtr++; + + hsmbus->XferCount--; + hsmbus->XferSize--; + } + + if (hsmbus->XferCount == 0U) + { + /* Last Byte is Transmitted */ + /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_TX, keep only HAL_SMBUS_STATE_LISTEN */ + SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX); + hsmbus->PreviousState = hsmbus->State; + hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_TX); + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + hsmbus->SlaveTxCpltCallback(hsmbus); +#else + HAL_SMBUS_SlaveTxCpltCallback(hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ + } + } + else + { + /* Nothing to do */ + } + + /* Check if STOPF is set */ + if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_STOPF) != RESET) + { + if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN) + { + /* Store Last receive data if any */ + if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) + { + /* Read data from RXDR */ + *hsmbus->pBuffPtr = (uint8_t)(hsmbus->Instance->RXDR); + + /* Increment Buffer pointer */ + hsmbus->pBuffPtr++; + + if ((hsmbus->XferSize > 0U)) + { + hsmbus->XferSize--; + hsmbus->XferCount--; + } + } + + /* Disable RX and TX Interrupts */ + SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_TX); + + /* Disable ADDR Interrupt */ + SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR); + + /* Disable Address Acknowledge */ + hsmbus->Instance->CR2 |= I2C_CR2_NACK; + + /* Clear Configuration Register 2 */ + SMBUS_RESET_CR2(hsmbus); + + /* Clear STOP Flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); + + /* Clear ADDR flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR); + + hsmbus->XferOptions = 0; + hsmbus->PreviousState = hsmbus->State; + hsmbus->State = HAL_SMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + hsmbus->ListenCpltCallback(hsmbus); +#else + HAL_SMBUS_ListenCpltCallback(hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + return HAL_OK; +} +/** + * @brief Manage the enabling of Interrupts. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @param InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition. + * @retval HAL status + */ +static void SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest) +{ + uint32_t tmpisr = 0UL; + + if ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT) + { + /* Enable ERR interrupt */ + tmpisr |= SMBUS_IT_ERRI; + } + + if ((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR) + { + /* Enable ADDR, STOP interrupt */ + tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_ERRI; + } + + if ((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX) + { + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ + tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI; + } + + if ((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX) + { + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI; + } + + /* Enable interrupts only at the end */ + /* to avoid the risk of SMBUS interrupt handle execution before */ + /* all interrupts requested done */ + __HAL_SMBUS_ENABLE_IT(hsmbus, tmpisr); +} +/** + * @brief Manage the disabling of Interrupts. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @param InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition. + * @retval HAL status + */ +static void SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest) +{ + uint32_t tmpisr = 0UL; + uint32_t tmpstate = hsmbus->State; + + if ((tmpstate == HAL_SMBUS_STATE_READY) && ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT)) + { + /* Disable ERR interrupt */ + tmpisr |= SMBUS_IT_ERRI; + } + + if ((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX) + { + /* Disable TC, STOP, NACK and TXI interrupt */ + tmpisr |= SMBUS_IT_TCI | SMBUS_IT_TXI; + + if ((SMBUS_GET_ALERT_ENABLED(hsmbus) == 0UL) + && ((tmpstate & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)) + { + /* Disable ERR interrupt */ + tmpisr |= SMBUS_IT_ERRI; + } + + if ((tmpstate & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN) + { + /* Disable STOP and NACK interrupt */ + tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI; + } + } + + if ((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX) + { + /* Disable TC, STOP, NACK and RXI interrupt */ + tmpisr |= SMBUS_IT_TCI | SMBUS_IT_RXI; + + if ((SMBUS_GET_ALERT_ENABLED(hsmbus) == 0UL) + && ((tmpstate & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)) + { + /* Disable ERR interrupt */ + tmpisr |= SMBUS_IT_ERRI; + } + + if ((tmpstate & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN) + { + /* Disable STOP and NACK interrupt */ + tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI; + } + } + + if ((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR) + { + /* Disable ADDR, STOP and NACK interrupt */ + tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI; + + if (SMBUS_GET_ALERT_ENABLED(hsmbus) == 0UL) + { + /* Disable ERR interrupt */ + tmpisr |= SMBUS_IT_ERRI; + } + } + + /* Disable interrupts only at the end */ + /* to avoid a breaking situation like at "t" time */ + /* all disable interrupts request are not done */ + __HAL_SMBUS_DISABLE_IT(hsmbus, tmpisr); +} + +/** + * @brief SMBUS interrupts error handler. + * @param hsmbus SMBUS handle. + * @retval None + */ +static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) +{ + uint32_t itflags = READ_REG(hsmbus->Instance->ISR); + uint32_t itsources = READ_REG(hsmbus->Instance->CR1); + uint32_t tmpstate; + uint32_t tmperror; + + /* SMBUS Bus error interrupt occurred ------------------------------------*/ + if (((itflags & SMBUS_FLAG_BERR) == SMBUS_FLAG_BERR) && \ + ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) + { + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BERR; + + /* Clear BERR flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_BERR); + } + + /* SMBUS Over-Run/Under-Run interrupt occurred ----------------------------------------*/ + if (((itflags & SMBUS_FLAG_OVR) == SMBUS_FLAG_OVR) && \ + ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) + { + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_OVR; + + /* Clear OVR flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_OVR); + } + + /* SMBUS Arbitration Loss error interrupt occurred ------------------------------------*/ + if (((itflags & SMBUS_FLAG_ARLO) == SMBUS_FLAG_ARLO) && \ + ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) + { + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ARLO; + + /* Clear ARLO flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ARLO); + } + + /* SMBUS Timeout error interrupt occurred ---------------------------------------------*/ + if (((itflags & SMBUS_FLAG_TIMEOUT) == SMBUS_FLAG_TIMEOUT) && \ + ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) + { + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BUSTIMEOUT; + + /* Clear TIMEOUT flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT); + } + + /* SMBUS Alert error interrupt occurred -----------------------------------------------*/ + if (((itflags & SMBUS_FLAG_ALERT) == SMBUS_FLAG_ALERT) && \ + ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) + { + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ALERT; + + /* Clear ALERT flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT); + } + + /* SMBUS Packet Error Check error interrupt occurred ----------------------------------*/ + if (((itflags & SMBUS_FLAG_PECERR) == SMBUS_FLAG_PECERR) && \ + ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) + { + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_PECERR; + + /* Clear PEC error flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR); + } + + /* Flush TX register */ + SMBUS_Flush_TXDR(hsmbus); + + /* Store current volatile hsmbus->ErrorCode, misra rule */ + tmperror = hsmbus->ErrorCode; + + /* Call the Error Callback in case of Error detected */ + if ((tmperror != HAL_SMBUS_ERROR_NONE) && (tmperror != HAL_SMBUS_ERROR_ACKF)) + { + /* Do not Reset the HAL state in case of ALERT error */ + if ((tmperror & HAL_SMBUS_ERROR_ALERT) != HAL_SMBUS_ERROR_ALERT) + { + /* Store current volatile hsmbus->State, misra rule */ + tmpstate = hsmbus->State; + + if (((tmpstate & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX) + || ((tmpstate & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)) + { + /* Reset only HAL_SMBUS_STATE_SLAVE_BUSY_XX */ + /* keep HAL_SMBUS_STATE_LISTEN if set */ + hsmbus->PreviousState = HAL_SMBUS_STATE_READY; + hsmbus->State = HAL_SMBUS_STATE_LISTEN; + } + } + + /* Call the Error callback to inform upper layer */ +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) + hsmbus->ErrorCallback(hsmbus); +#else + HAL_SMBUS_ErrorCallback(hsmbus); +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ + } +} + +/** + * @brief Handle SMBUS Communication Timeout. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS. + * @param Flag Specifies the SMBUS flag to check. + * @param Status The new Flag status (SET or RESET). + * @param Timeout Timeout duration + * @retval HAL status + */ +static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, + FlagStatus Status, uint32_t Timeout) +{ + uint32_t tickstart = HAL_GetTick(); + + /* Wait until flag is set */ + while ((FlagStatus)(__HAL_SMBUS_GET_FLAG(hsmbus, Flag)) == Status) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) + { + hsmbus->PreviousState = hsmbus->State; + hsmbus->State = HAL_SMBUS_STATE_READY; + + /* Update SMBUS error code */ + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_HALTIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + return HAL_ERROR; + } + } + } + + return HAL_OK; +} + +/** + * @brief SMBUS Tx data register flush process. + * @param hsmbus SMBUS handle. + * @retval None + */ +static void SMBUS_Flush_TXDR(SMBUS_HandleTypeDef *hsmbus) +{ + /* If a pending TXIS flag is set */ + /* Write a dummy data in TXDR to clear it */ + if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET) + { + hsmbus->Instance->TXDR = 0x00U; + } + + /* Flush TX register if not empty */ + if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXE) == RESET) + { + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_TXE); + } +} + +/** + * @brief Handle SMBUSx communication when starting transfer or during transfer (TC or TCR flag are set). + * @param hsmbus SMBUS handle. + * @param DevAddress specifies the slave address to be programmed. + * @param Size specifies the number of bytes to be programmed. + * This parameter must be a value between 0 and 255. + * @param Mode New state of the SMBUS START condition generation. + * This parameter can be one or a combination of the following values: + * @arg @ref SMBUS_RELOAD_MODE Enable Reload mode. + * @arg @ref SMBUS_AUTOEND_MODE Enable Automatic end mode. + * @arg @ref SMBUS_SOFTEND_MODE Enable Software end mode and Reload mode. + * @arg @ref SMBUS_SENDPEC_MODE Enable Packet Error Calculation mode. + * @param Request New state of the SMBUS START condition generation. + * This parameter can be one of the following values: + * @arg @ref SMBUS_NO_STARTSTOP Don't Generate stop and start condition. + * @arg @ref SMBUS_GENERATE_STOP Generate stop condition (Size should be set to 0). + * @arg @ref SMBUS_GENERATE_START_READ Generate Restart for read request. + * @arg @ref SMBUS_GENERATE_START_WRITE Generate Restart for write request. + * @retval None + */ +static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, + uint32_t Mode, uint32_t Request) +{ + /* Check the parameters */ + assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance)); + assert_param(IS_SMBUS_TRANSFER_MODE(Mode)); + assert_param(IS_SMBUS_TRANSFER_REQUEST(Request)); + + /* update CR2 register */ + MODIFY_REG(hsmbus->Instance->CR2, + ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \ + (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31UL - I2C_CR2_RD_WRN_Pos))) | \ + I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE)), \ + (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ + (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ + (uint32_t)Mode | (uint32_t)Request)); +} + +/** + * @brief Convert SMBUSx OTHER_xxx XferOptions to functional XferOptions. + * @param hsmbus SMBUS handle. + * @retval None + */ +static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus) +{ + /* if user set XferOptions to SMBUS_OTHER_FRAME_NO_PEC */ + /* it request implicitly to generate a restart condition */ + /* set XferOptions to SMBUS_FIRST_FRAME */ + if (hsmbus->XferOptions == SMBUS_OTHER_FRAME_NO_PEC) + { + hsmbus->XferOptions = SMBUS_FIRST_FRAME; + } + /* else if user set XferOptions to SMBUS_OTHER_FRAME_WITH_PEC */ + /* it request implicitly to generate a restart condition */ + /* set XferOptions to SMBUS_FIRST_FRAME | SMBUS_SENDPEC_MODE */ + else if (hsmbus->XferOptions == SMBUS_OTHER_FRAME_WITH_PEC) + { + hsmbus->XferOptions = SMBUS_FIRST_FRAME | SMBUS_SENDPEC_MODE; + } + /* else if user set XferOptions to SMBUS_OTHER_AND_LAST_FRAME_NO_PEC */ + /* it request implicitly to generate a restart condition */ + /* then generate a stop condition at the end of transfer */ + /* set XferOptions to SMBUS_FIRST_AND_LAST_FRAME_NO_PEC */ + else if (hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) + { + hsmbus->XferOptions = SMBUS_FIRST_AND_LAST_FRAME_NO_PEC; + } + /* else if user set XferOptions to SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC */ + /* it request implicitly to generate a restart condition */ + /* then generate a stop condition at the end of transfer */ + /* set XferOptions to SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC */ + else if (hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC) + { + hsmbus->XferOptions = SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC; + } + else + { + /* Nothing to do */ + } +} +/** + * @} + */ + +#endif /* HAL_SMBUS_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_smbus_ex.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_smbus_ex.c new file mode 100644 index 0000000000..2e6a216014 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_smbus_ex.c @@ -0,0 +1,388 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_smbus_ex.c + * @author MCD Application Team + * @brief SMBUS Extended HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of SMBUS Extended peripheral: + * + Extended features functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### SMBUS peripheral Extended features ##### + ============================================================================== + + [..] Comparing to other previous devices, the SMBUS interface for STM32WBAxx + devices contains the following additional features + + (+) Disable or enable wakeup from Stop mode(s) + (+) Disable or enable Fast Mode Plus + + ##### How to use this driver ##### + ============================================================================== + (#) Configure the enable or disable of SMBUS Wake Up Mode using the functions : + (++) HAL_SMBUSEx_EnableWakeUp() + (++) HAL_SMBUSEx_DisableWakeUp() + (#) Configure the enable or disable of fast mode plus driving capability using the functions : + (++) HAL_SMBUSEx_ConfigFastModePlus() + (#) Set or get or clear the autonomous mode configuration using these functions : + (++) HAL_SMBUSEx_SetConfigAutonomousMode() + (++) HAL_SMBUSEx_GetConfigAutonomousMode() + (++) HAL_SMBUSEx_ClearConfigAutonomousMode() + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @defgroup SMBUSEx SMBUSEx + * @brief SMBUS Extended HAL module driver + * @{ + */ + +#ifdef HAL_SMBUS_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup SMBUSEx_Exported_Functions SMBUS Extended Exported Functions + * @{ + */ + +/** @defgroup SMBUSEx_Exported_Functions_Group2 WakeUp Mode Functions + * @brief WakeUp Mode Functions + * +@verbatim + =============================================================================== + ##### WakeUp Mode Functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure Wake Up Feature + +@endverbatim + * @{ + */ + +/** + * @brief Enable SMBUS wakeup from Stop mode(s). + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUSx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUSEx_EnableWakeUp(SMBUS_HandleTypeDef *hsmbus) +{ + /* Check the parameters */ + assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hsmbus->Instance)); + + if (hsmbus->State == HAL_SMBUS_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsmbus); + + hsmbus->State = HAL_SMBUS_STATE_BUSY; + + /* Disable the selected SMBUS peripheral */ + __HAL_SMBUS_DISABLE(hsmbus); + + /* Enable wakeup from stop mode */ + hsmbus->Instance->CR1 |= I2C_CR1_WUPEN; + + __HAL_SMBUS_ENABLE(hsmbus); + + hsmbus->State = HAL_SMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Disable SMBUS wakeup from Stop mode(s). + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUSx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUSEx_DisableWakeUp(SMBUS_HandleTypeDef *hsmbus) +{ + /* Check the parameters */ + assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hsmbus->Instance)); + + if (hsmbus->State == HAL_SMBUS_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsmbus); + + hsmbus->State = HAL_SMBUS_STATE_BUSY; + + /* Disable the selected SMBUS peripheral */ + __HAL_SMBUS_DISABLE(hsmbus); + + /* Disable wakeup from stop mode */ + hsmbus->Instance->CR1 &= ~(I2C_CR1_WUPEN); + + __HAL_SMBUS_ENABLE(hsmbus); + + hsmbus->State = HAL_SMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +/** + * @} + */ + +/** @defgroup SMBUSEx_Exported_Functions_Group3 Fast Mode Plus Functions + * @brief Fast Mode Plus Functions + * +@verbatim + =============================================================================== + ##### Fast Mode Plus Functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure Fast Mode Plus + +@endverbatim + * @{ + */ + +/** + * @brief Configure SMBUS Fast Mode Plus. + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUSx peripheral. + * @param FastModePlus New state of the Fast Mode Plus. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUSEx_ConfigFastModePlus(SMBUS_HandleTypeDef *hsmbus, uint32_t FastModePlus) +{ + /* Check the parameters */ + assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance)); + assert_param(IS_SMBUS_FASTMODEPLUS(FastModePlus)); + + if (hsmbus->State == HAL_SMBUS_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsmbus); + + hsmbus->State = HAL_SMBUS_STATE_BUSY; + + /* Disable the selected SMBUS peripheral */ + __HAL_SMBUS_DISABLE(hsmbus); + + if (FastModePlus == SMBUS_FASTMODEPLUS_ENABLE) + { + /* Set SMBUSx FMP bit */ + hsmbus->Instance->CR1 |= (I2C_CR1_FMP); + } + else + { + /* Reset SMBUSx FMP bit */ + hsmbus->Instance->CR1 &= ~(I2C_CR1_FMP); + } + + __HAL_SMBUS_ENABLE(hsmbus); + + hsmbus->State = HAL_SMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup SMBUSEx_Exported_Functions_Group4 Autonomous Mode Functions + * @brief Autonomous Mode Functions + * +@verbatim + =============================================================================== + ##### Autonomous Mode functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure Autonomous Mode + +@endverbatim + * @{ + */ + +/** + * @brief Set Autonomous Mode configuration + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUSx peripheral. + * @param sConfig Pointer to a SMBUS_AutonomousModeConfTypeDef structure that contains + * the configuration information of the autonomous mode for the specified SMBUSx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUSEx_SetConfigAutonomousMode(SMBUS_HandleTypeDef *hsmbus, + const SMBUS_AutonomousModeConfTypeDef *sConfig) +{ + if (hsmbus->State == HAL_SMBUS_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsmbus); + + hsmbus->State = HAL_SMBUS_STATE_BUSY; + + /* Check the parameters */ + assert_param(IS_SMBUS_TRIG_INPUT_INSTANCE(hsmbus->Instance)); + assert_param(IS_SMBUS_TRIG_SOURCE(hsmbus->Instance, sConfig->TriggerSelection)); + assert_param(IS_SMBUS_AUTO_MODE_TRG_POL(sConfig->TriggerPolarity)); + + /* Disable the selected SMBUS peripheral to be able to configure AUTOCR */ + __HAL_SMBUS_DISABLE(hsmbus); + + /* SMBUSx AUTOCR Configuration */ + WRITE_REG(hsmbus->Instance->AUTOCR, + (sConfig->TriggerState | \ + ((sConfig->TriggerSelection) & I2C_AUTOCR_TRIGSEL_Msk) | \ + sConfig->TriggerPolarity)); + + /* Enable the selected SMBUS peripheral */ + __HAL_SMBUS_ENABLE(hsmbus); + + hsmbus->State = HAL_SMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Get Autonomous Mode configuration + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUSx peripheral. + * @param sConfig Pointer to a SMBUS_AutonomousModeConfTypeDef structure that contains + * the configuration information of the autonomous mode for the specified SMBUSx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUSEx_GetConfigAutonomousMode(const SMBUS_HandleTypeDef *hsmbus, + SMBUS_AutonomousModeConfTypeDef *sConfig) +{ + uint32_t autocr_tmp; + + /* Check the parameters */ + assert_param(IS_SMBUS_TRIG_INPUT_INSTANCE(hsmbus->Instance)); + + autocr_tmp = hsmbus->Instance->AUTOCR; + + sConfig->TriggerState = (autocr_tmp & I2C_AUTOCR_TRIGEN); +#if defined(SMBUS_TRIG_GRP1) + if (IS_SMBUS_GRP2_INSTANCE(hsmbus->Instance)) + { + sConfig->TriggerSelection = ((autocr_tmp & I2C_AUTOCR_TRIGSEL) | SMBUS_TRIG_GRP2); + } + else + { + sConfig->TriggerSelection = ((autocr_tmp & I2C_AUTOCR_TRIGSEL) | SMBUS_TRIG_GRP1); + } +#else + sConfig->TriggerSelection = ((autocr_tmp & I2C_AUTOCR_TRIGSEL) | SMBUS_TRIG_GRP2); +#endif /* SMBUS_TRIG_GRP1 */ + sConfig->TriggerPolarity = (autocr_tmp & I2C_AUTOCR_TRIGPOL); + + return HAL_OK; +} + +/** + * @brief Clear Autonomous Mode configuration + * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains + * the configuration information for the specified SMBUS peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SMBUSEx_ClearConfigAutonomousMode(SMBUS_HandleTypeDef *hsmbus) +{ + if (hsmbus->State == HAL_SMBUS_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsmbus); + + hsmbus->State = HAL_SMBUS_STATE_BUSY; + + /* Check the parameters */ + assert_param(IS_SMBUS_TRIG_INPUT_INSTANCE(hsmbus->Instance)); + + /* Disable the selected SMBUS peripheral to be able to clear AUTOCR */ + __HAL_SMBUS_DISABLE(hsmbus); + + CLEAR_REG(hsmbus->Instance->AUTOCR); + + /* Enable the selected SMBUS peripheral */ + __HAL_SMBUS_ENABLE(hsmbus); + + hsmbus->State = HAL_SMBUS_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_SMBUS_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_spi.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_spi.c new file mode 100644 index 0000000000..cf6cc737a8 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_spi.c @@ -0,0 +1,3753 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_spi.c + * @author MCD Application Team + * @brief SPI HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Serial Peripheral Interface (SPI) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The SPI HAL driver can be used as follows: + + (#) Declare a SPI_HandleTypeDef handle structure, for example: + SPI_HandleTypeDef hspi; + + (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API: + (##) Enable the SPIx interface clock + (##) SPI pins configuration + (+++) Enable the clock for the SPI GPIOs + (+++) Configure these SPI pins as alternate function push-pull + (##) NVIC configuration if you need to use interrupt process or DMA process + (+++) Configure the SPIx interrupt priority + (+++) Enable the NVIC SPI IRQ handle + (##) DMA Configuration if you need to use DMA process + (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel + (+++) Enable the DMAx clock + (+++) Configure the DMA handle parameters + (+++) Configure the DMA Tx or Rx Stream/Channel + (+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx + or Rx Stream/Channel + + (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS + management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure. + + (#) Initialize the SPI registers by calling the HAL_SPI_Init() API: + (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) + by calling the customized HAL_SPI_MspInit() API. + [..] + Callback registration: + + (#) The compilation flag USE_HAL_SPI_REGISTER_CALLBACKS when set to 1UL + allows the user to configure dynamically the driver callbacks. + Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback. + + Function HAL_SPI_RegisterCallback() allows to register following callbacks: + (+) TxCpltCallback : SPI Tx Completed callback + (+) RxCpltCallback : SPI Rx Completed callback + (+) TxRxCpltCallback : SPI TxRx Completed callback + (+) TxHalfCpltCallback : SPI Tx Half Completed callback + (+) RxHalfCpltCallback : SPI Rx Half Completed callback + (+) TxRxHalfCpltCallback : SPI TxRx Half Completed callback + (+) ErrorCallback : SPI Error callback + (+) AbortCpltCallback : SPI Abort callback + (+) SuspendCallback : SPI Suspend callback + (+) MspInitCallback : SPI Msp Init callback + (+) MspDeInitCallback : SPI Msp DeInit callback + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + + (#) Use function HAL_SPI_UnRegisterCallback to reset a callback to the default + weak function. + HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) TxCpltCallback : SPI Tx Completed callback + (+) RxCpltCallback : SPI Rx Completed callback + (+) TxRxCpltCallback : SPI TxRx Completed callback + (+) TxHalfCpltCallback : SPI Tx Half Completed callback + (+) RxHalfCpltCallback : SPI Rx Half Completed callback + (+) TxRxHalfCpltCallback : SPI TxRx Half Completed callback + (+) ErrorCallback : SPI Error callback + (+) AbortCpltCallback : SPI Abort callback + (+) SuspendCallback : SPI Suspend callback + (+) MspInitCallback : SPI Msp Init callback + (+) MspDeInitCallback : SPI Msp DeInit callback + + By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak functions in the HAL_SPI_Init()/ HAL_SPI_DeInit() only when + these callbacks are null (not registered beforehand). + If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + + Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only. + Exception done MspInit/MspDeInit functions that can be registered/unregistered + in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + Then, the user first registers the MspInit/MspDeInit user callbacks + using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit() + or HAL_SPI_Init() function. + + When The compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or not defined, + the callback registering feature is not available and weak callbacks are used. + + SuspendCallback restriction: + SuspendCallback is called only when MasterReceiverAutoSusp is enabled and + EOT interrupt is activated. SuspendCallback is used in relation with functions + HAL_SPI_Transmit_IT, HAL_SPI_Receive_IT and HAL_SPI_TransmitReceive_IT. + + [..] + Circular mode restriction: + (+) The DMA circular mode cannot be used when the SPI is configured in these modes: + (++) Master 2Lines RxOnly + (++) Master 1Line Rx + (+) The CRC feature is not managed when the DMA circular mode is enabled + (+) The functions HAL_SPI_DMAPause()/ HAL_SPI_DMAResume() are not supported. Return always + HAL_ERROR with ErrorCode set to HAL_SPI_ERROR_NOT_SUPPORTED. + Those functions are maintained for backward compatibility reasons. + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @defgroup SPI SPI + * @brief SPI HAL module driver + * @{ + */ +#ifdef HAL_SPI_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/** @defgroup SPI_Private_Constants SPI Private Constants + * @{ + */ +#define SPI_DEFAULT_TIMEOUT 100UL +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup SPI_Private_Functions SPI Private Functions + * @{ + */ +static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAError(DMA_HandleTypeDef *hdma); +static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma); +static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma); +static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(const SPI_HandleTypeDef *hspi, uint32_t Flag, + FlagStatus FlagStatus, uint32_t Timeout, uint32_t Tickstart); +static void SPI_TxISR_8BIT(SPI_HandleTypeDef *hspi); +static void SPI_TxISR_16BIT(SPI_HandleTypeDef *hspi); +static void SPI_TxISR_32BIT(SPI_HandleTypeDef *hspi); +static void SPI_RxISR_8BIT(SPI_HandleTypeDef *hspi); +static void SPI_RxISR_16BIT(SPI_HandleTypeDef *hspi); +static void SPI_RxISR_32BIT(SPI_HandleTypeDef *hspi); +static void SPI_AbortTransfer(SPI_HandleTypeDef *hspi); +static void SPI_CloseTransfer(SPI_HandleTypeDef *hspi); +static uint32_t SPI_GetPacketSize(const SPI_HandleTypeDef *hspi); + + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup SPI_Exported_Functions SPI Exported Functions + * @{ + */ + +/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + de-initialize the SPIx peripheral: + + (+) User must implement HAL_SPI_MspInit() function in which he configures + all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). + + (+) Call the function HAL_SPI_Init() to configure the selected device with + the selected configuration: + (++) Mode + (++) Direction + (++) Data Size + (++) Clock Polarity and Phase + (++) NSS Management + (++) BaudRate Prescaler + (++) FirstBit + (++) TIMode + (++) CRC Calculation + (++) CRC Polynomial if CRC enabled + (++) CRC Length, used only with Data8 and Data16 + (++) FIFO reception threshold + (++) FIFO transmission threshold + + (+) Call the function HAL_SPI_DeInit() to restore the default configuration + of the selected SPIx peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the SPI according to the specified parameters + * in the SPI_InitTypeDef and initialize the associated handle. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) +{ + uint32_t crc_length; + uint32_t packet_length; + + /* Check the SPI handle allocation */ + if (hspi == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance)); + assert_param(IS_SPI_MODE(hspi->Init.Mode)); + assert_param(IS_SPI_DIRECTION(hspi->Init.Direction)); + if (IS_SPI_LIMITED_INSTANCE(hspi->Instance)) + { + assert_param(IS_SPI_LIMITED_DATASIZE(hspi->Init.DataSize)); + assert_param(IS_SPI_LIMITED_FIFOTHRESHOLD(hspi->Init.FifoThreshold)); + } + else + { + assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize)); + assert_param(IS_SPI_FIFOTHRESHOLD(hspi->Init.FifoThreshold)); + } + assert_param(IS_SPI_NSS(hspi->Init.NSS)); + assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode)); + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit)); + assert_param(IS_SPI_TIMODE(hspi->Init.TIMode)); + if (hspi->Init.TIMode == SPI_TIMODE_DISABLE) + { + assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); + assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); + } +#if (USE_SPI_CRC != 0UL) + assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation)); + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + if (IS_SPI_LIMITED_INSTANCE(hspi->Instance)) + { + assert_param(IS_SPI_LIMITED_CRC_LENGTH(hspi->Init.CRCLength)); + } + else + { + assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength)); + } + assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); + assert_param(IS_SPI_CRC_INITIALIZATION_PATTERN(hspi->Init.TxCRCInitializationPattern)); + assert_param(IS_SPI_CRC_INITIALIZATION_PATTERN(hspi->Init.RxCRCInitializationPattern)); + } +#else + hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; +#endif /* USE_SPI_CRC */ + + assert_param(IS_SPI_RDY_MASTER_MANAGEMENT(hspi->Init.ReadyMasterManagement)); + assert_param(IS_SPI_RDY_POLARITY(hspi->Init.ReadyPolarity)); + assert_param(IS_SPI_MASTER_RX_AUTOSUSP(hspi->Init.MasterReceiverAutoSusp)); + + /* Verify that the SPI instance supports Data Size higher than 16bits */ + if ((IS_SPI_LIMITED_INSTANCE(hspi->Instance)) && (hspi->Init.DataSize > SPI_DATASIZE_16BIT)) + { + return HAL_ERROR; + } + + /* Verify that the SPI instance supports requested data packing */ + packet_length = SPI_GetPacketSize(hspi); + if (((IS_SPI_LIMITED_INSTANCE(hspi->Instance)) && (packet_length > SPI_LOWEND_FIFO_SIZE)) || + ((IS_SPI_FULL_INSTANCE(hspi->Instance)) && (packet_length > SPI_HIGHEND_FIFO_SIZE))) + { + return HAL_ERROR; + } +#if (USE_SPI_CRC != 0UL) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Verify that the SPI instance supports CRC Length higher than 16bits */ + if ((IS_SPI_LIMITED_INSTANCE(hspi->Instance)) && (hspi->Init.CRCLength > SPI_CRC_LENGTH_16BIT)) + { + return HAL_ERROR; + } + + /* Align the CRC Length on the data size */ + if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE) + { + crc_length = (hspi->Init.DataSize >> SPI_CFG1_DSIZE_Pos) << SPI_CFG1_CRCSIZE_Pos; + } + else + { + crc_length = hspi->Init.CRCLength; + } + + /* Verify that the CRC Length is higher than DataSize */ + if ((hspi->Init.DataSize >> SPI_CFG1_DSIZE_Pos) > (crc_length >> SPI_CFG1_CRCSIZE_Pos)) + { + return HAL_ERROR; + } + } + else + { + crc_length = hspi->Init.DataSize << SPI_CFG1_CRCSIZE_Pos; + } +#endif /* USE_SPI_CRC */ + + if (hspi->State == HAL_SPI_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hspi->Lock = HAL_UNLOCKED; + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + /* Init the SPI Callback settings */ + hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */ + hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */ + hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */ + hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */ + hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */ + hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + hspi->SuspendCallback = HAL_SPI_SuspendCallback; /* Legacy weak SuspendCallback */ + + if (hspi->MspInitCallback == NULL) + { + hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + hspi->MspInitCallback(hspi); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + HAL_SPI_MspInit(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + + hspi->State = HAL_SPI_STATE_BUSY; + + /* Disable the selected SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + +#if (USE_SPI_CRC == 0) + /* Keep the default value of CRCSIZE in case of CRC is not used */ + crc_length = hspi->Instance->CFG1 & SPI_CFG1_CRCSIZE; +#endif /* USE_SPI_CRC */ + + /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ + /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management, + Communication speed, First bit, CRC calculation state, CRC Length */ + + /* SPIx NSS Software Management Configuration */ + if ((hspi->Init.NSS == SPI_NSS_SOFT) && (((hspi->Init.Mode == SPI_MODE_MASTER) && \ + (hspi->Init.NSSPolarity == SPI_NSS_POLARITY_LOW)) || \ + ((hspi->Init.Mode == SPI_MODE_SLAVE) && \ + (hspi->Init.NSSPolarity == SPI_NSS_POLARITY_HIGH)))) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_SSI); + } + + /* SPIx Master Rx Auto Suspend Configuration */ + if (((hspi->Init.Mode & SPI_MODE_MASTER) == SPI_MODE_MASTER) && (hspi->Init.DataSize >= SPI_DATASIZE_8BIT)) + { + MODIFY_REG(hspi->Instance->CR1, SPI_CR1_MASRX, hspi->Init.MasterReceiverAutoSusp); + } + else + { + CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_MASRX); + } + + /* SPIx CFG1 Configuration */ + WRITE_REG(hspi->Instance->CFG1, (hspi->Init.BaudRatePrescaler | hspi->Init.CRCCalculation | crc_length | + hspi->Init.FifoThreshold | hspi->Init.DataSize)); + + /* SPIx CFG2 Configuration */ + WRITE_REG(hspi->Instance->CFG2, (hspi->Init.NSSPMode | hspi->Init.TIMode | + hspi->Init.NSSPolarity | hspi->Init.NSS | + hspi->Init.CLKPolarity | hspi->Init.CLKPhase | + hspi->Init.FirstBit | hspi->Init.Mode | + hspi->Init.MasterInterDataIdleness | hspi->Init.Direction | + hspi->Init.MasterSSIdleness | hspi->Init.IOSwap | + hspi->Init.ReadyMasterManagement | hspi->Init.ReadyPolarity)); + +#if (USE_SPI_CRC != 0UL) + /*---------------------------- SPIx CRCPOLY Configuration ------------------*/ + /* Configure : CRC Polynomial */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Initialize TXCRC Pattern Initial Value */ + if (hspi->Init.TxCRCInitializationPattern == SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_TCRCINI); + } + else + { + CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_TCRCINI); + } + + /* Initialize RXCRC Pattern Initial Value */ + if (hspi->Init.RxCRCInitializationPattern == SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_RCRCINI); + } + else + { + CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_RCRCINI); + } + + /* Enable 33/17 bits CRC computation */ + if (((IS_SPI_LIMITED_INSTANCE(hspi->Instance)) && (crc_length == SPI_CRC_LENGTH_16BIT)) || + ((IS_SPI_FULL_INSTANCE(hspi->Instance)) && (crc_length == SPI_CRC_LENGTH_32BIT))) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRC33_17); + } + else + { + CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_CRC33_17); + } + + /* Write CRC polynomial in SPI Register */ + WRITE_REG(hspi->Instance->CRCPOLY, hspi->Init.CRCPolynomial); + } +#endif /* USE_SPI_CRC */ + + /* Insure that Underrun configuration is managed only by Salve */ + if (hspi->Init.Mode == SPI_MODE_SLAVE) + { +#if (USE_SPI_CRC != 0UL) + MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRCFG, SPI_CFG1_UDRCFG); +#endif /* USE_SPI_CRC */ + } + +#if defined(SPI_I2SCFGR_I2SMOD) + /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */ + CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD); +#endif /* SPI_I2SCFGR_I2SMOD */ + + /* Insure that AFCNTR is managed only by Master */ + if ((hspi->Init.Mode & SPI_MODE_MASTER) == SPI_MODE_MASTER) + { + /* Alternate function GPIOs control */ + MODIFY_REG(hspi->Instance->CFG2, SPI_CFG2_AFCNTR, (hspi->Init.MasterKeepIOState)); + } + + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->State = HAL_SPI_STATE_READY; + + return HAL_OK; +} + +/** + * @brief De-Initialize the SPI peripheral. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) +{ + /* Check the SPI handle allocation */ + if (hspi == NULL) + { + return HAL_ERROR; + } + + /* Check SPI Instance parameter */ + assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance)); + + hspi->State = HAL_SPI_STATE_BUSY; + + /* Disable the SPI Peripheral Clock */ + __HAL_SPI_DISABLE(hspi); + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + if (hspi->MspDeInitCallback == NULL) + { + hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ + hspi->MspDeInitCallback(hspi); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ + HAL_SPI_MspDeInit(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->State = HAL_SPI_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hspi); + + return HAL_OK; +} + +/** + * @brief Initialize the SPI MSP. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_MspInit should be implemented in the user file + */ +} + +/** + * @brief De-Initialize the SPI MSP. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_MspDeInit should be implemented in the user file + */ +} + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) +/** + * @brief Register a User SPI Callback + * To be used instead of the weak predefined callback + * @param hspi Pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI. + * @param CallbackID ID of the callback to be registered + * @param pCallback pointer to the Callback function + * @note The HAL_SPI_RegisterCallback() may be called before HAL_SPI_Init() in HAL_SPI_STATE_RESET + * to register callbacks for HAL_SPI_MSPINIT_CB_ID and HAL_SPI_MSPDEINIT_CB_ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, + pSPI_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hspi->ErrorCode |= HAL_SPI_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (HAL_SPI_STATE_READY == hspi->State) + { + switch (CallbackID) + { + case HAL_SPI_TX_COMPLETE_CB_ID : + hspi->TxCpltCallback = pCallback; + break; + + case HAL_SPI_RX_COMPLETE_CB_ID : + hspi->RxCpltCallback = pCallback; + break; + + case HAL_SPI_TX_RX_COMPLETE_CB_ID : + hspi->TxRxCpltCallback = pCallback; + break; + + case HAL_SPI_TX_HALF_COMPLETE_CB_ID : + hspi->TxHalfCpltCallback = pCallback; + break; + + case HAL_SPI_RX_HALF_COMPLETE_CB_ID : + hspi->RxHalfCpltCallback = pCallback; + break; + + case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID : + hspi->TxRxHalfCpltCallback = pCallback; + break; + + case HAL_SPI_ERROR_CB_ID : + hspi->ErrorCallback = pCallback; + break; + + case HAL_SPI_ABORT_CB_ID : + hspi->AbortCpltCallback = pCallback; + break; + + case HAL_SPI_SUSPEND_CB_ID : + hspi->SuspendCallback = pCallback; + break; + + case HAL_SPI_MSPINIT_CB_ID : + hspi->MspInitCallback = pCallback; + break; + + case HAL_SPI_MSPDEINIT_CB_ID : + hspi->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_SPI_STATE_RESET == hspi->State) + { + switch (CallbackID) + { + case HAL_SPI_MSPINIT_CB_ID : + hspi->MspInitCallback = pCallback; + break; + + case HAL_SPI_MSPDEINIT_CB_ID : + hspi->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister an SPI Callback + * SPI callback is redirected to the weak predefined callback + * @param hspi Pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI. + * @param CallbackID ID of the callback to be unregistered + * @note The HAL_SPI_UnRegisterCallback() may be called before HAL_SPI_Init() in HAL_SPI_STATE_RESET + * to un-register callbacks for HAL_SPI_MSPINIT_CB_ID and HAL_SPI_MSPDEINIT_CB_ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (HAL_SPI_STATE_READY == hspi->State) + { + switch (CallbackID) + { + case HAL_SPI_TX_COMPLETE_CB_ID : + hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */ + break; + + case HAL_SPI_RX_COMPLETE_CB_ID : + hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */ + break; + + case HAL_SPI_TX_RX_COMPLETE_CB_ID : + hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */ + break; + + case HAL_SPI_TX_HALF_COMPLETE_CB_ID : + hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + break; + + case HAL_SPI_RX_HALF_COMPLETE_CB_ID : + hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + break; + + case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID : + hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */ + break; + + case HAL_SPI_ERROR_CB_ID : + hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_SPI_ABORT_CB_ID : + hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + break; + + case HAL_SPI_SUSPEND_CB_ID : + hspi->SuspendCallback = HAL_SPI_SuspendCallback; /* Legacy weak SuspendCallback */ + break; + + case HAL_SPI_MSPINIT_CB_ID : + hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_SPI_MSPDEINIT_CB_ID : + hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_SPI_STATE_RESET == hspi->State) + { + switch (CallbackID) + { + case HAL_SPI_MSPINIT_CB_ID : + hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_SPI_MSPDEINIT_CB_ID : + hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup SPI_Exported_Functions_Group2 IO operation functions + * @brief Data transfers functions + * +@verbatim + ============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the SPI + data transfers. + + [..] The SPI supports master and slave mode : + + (#) There are two modes of transfer: + (##) Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (##) No-Blocking mode: The communication is performed using Interrupts + or DMA, These APIs return the HAL status. + The end of the data processing will be indicated through the + dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks + will be executed respectively at the end of the transmit or Receive process + The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected + + (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA) + exist for 1Line (simplex) and 2Lines (full duplex) modes. + +@endverbatim + * @{ + */ + +/** + * @brief Transmit an amount of data in blocking mode. + * @param hspi : pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData : pointer to data buffer + * @param Size : amount of data to be sent + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ +#if defined (__GNUC__) + __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->TXDR)); +#endif /* __GNUC__ */ + + uint32_t tickstart; + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction)); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (hspi->State != HAL_SPI_STATE_READY) + { + return HAL_BUSY; + } + + if ((pData == NULL) || (Size == 0UL)) + { + return HAL_ERROR; + } + + /* Lock the process */ + __HAL_LOCK(hspi); + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_TX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pTxBuffPtr = (const uint8_t *)pData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->pRxBuffPtr = NULL; + hspi->RxXferSize = (uint16_t) 0UL; + hspi->RxXferCount = (uint16_t) 0UL; + hspi->TxISR = NULL; + hspi->RxISR = NULL; + + /* Configure communication direction : 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_TX(hspi); + } + else + { + SPI_2LINES_TX(hspi); + } + + /* Set the number of data at current transfer */ + MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size); + + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + + if (((hspi->Instance->AUTOCR & SPI_AUTOCR_TRIGEN) == 0U) && (hspi->Init.Mode == SPI_MODE_MASTER)) + { + /* Master transfer start */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); + } + + /* Transmit data in 32 Bit mode */ + if ((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (IS_SPI_FULL_INSTANCE(hspi->Instance))) + { + /* Transmit data in 32 Bit mode */ + while (hspi->TxXferCount > 0UL) + { + /* Wait until TXP flag is set to send data */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) + { + *((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint32_t); + hspi->TxXferCount--; + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + /* Call standard close procedure with error check */ + SPI_CloseTransfer(hspi); + + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + return HAL_TIMEOUT; + } + } + } + } + /* Transmit data in 16 Bit mode */ + else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + /* Transmit data in 16 Bit mode */ + while (hspi->TxXferCount > 0UL) + { + /* Wait until TXP flag is set to send data */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) + { + if ((hspi->TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA)) + { + *((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint32_t); + hspi->TxXferCount -= (uint16_t)2UL; + } + else + { +#if defined (__GNUC__) + *ptxdr_16bits = *((const uint16_t *)hspi->pTxBuffPtr); +#else + *((__IO uint16_t *)&hspi->Instance->TXDR) = *((const uint16_t *)hspi->pTxBuffPtr); +#endif /* __GNUC__ */ + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + } + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + /* Call standard close procedure with error check */ + SPI_CloseTransfer(hspi); + + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + return HAL_TIMEOUT; + } + } + } + } + /* Transmit data in 8 Bit mode */ + else + { + while (hspi->TxXferCount > 0UL) + { + /* Wait until TXP flag is set to send data */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) + { + if ((hspi->TxXferCount > 3UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_03DATA)) + { + *((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint32_t); + hspi->TxXferCount -= (uint16_t)4UL; + } + else if ((hspi->TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA)) + { +#if defined (__GNUC__) + *ptxdr_16bits = *((const uint16_t *)hspi->pTxBuffPtr); +#else + *((__IO uint16_t *)&hspi->Instance->TXDR) = *((const uint16_t *)hspi->pTxBuffPtr); +#endif /* __GNUC__ */ + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount -= (uint16_t)2UL; + } + else + { + *((__IO uint8_t *)&hspi->Instance->TXDR) = *((const uint8_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint8_t); + hspi->TxXferCount--; + } + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + /* Call standard close procedure with error check */ + SPI_CloseTransfer(hspi); + + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + return HAL_TIMEOUT; + } + } + } + } + + /* Wait for Tx (and CRC) data to be sent */ + if (SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_EOT, RESET, Timeout, tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Call standard close procedure with error check */ + SPI_CloseTransfer(hspi); + + hspi->State = HAL_SPI_STATE_READY; + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + return HAL_ERROR; + } + else + { + return HAL_OK; + } +} + +/** + * @brief Receive an amount of data in blocking mode. + * @param hspi : pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData : pointer to data buffer + * @param Size : amount of data to be received + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart; +#if defined (__GNUC__) + __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->RXDR)); +#endif /* __GNUC__ */ + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction)); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (hspi->State != HAL_SPI_STATE_READY) + { + return HAL_BUSY; + } + + if ((pData == NULL) || (Size == 0UL)) + { + return HAL_ERROR; + } + + /* Lock the process */ + __HAL_LOCK(hspi); + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_RX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pRxBuffPtr = (uint8_t *)pData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->pTxBuffPtr = NULL; + hspi->TxXferSize = (uint16_t) 0UL; + hspi->TxXferCount = (uint16_t) 0UL; + hspi->RxISR = NULL; + hspi->TxISR = NULL; + + /* Configure communication direction: 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_RX(hspi); + } + else + { + SPI_2LINES_RX(hspi); + } + + /* Set the number of data at current transfer */ + MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size); + + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + + if (((hspi->Instance->AUTOCR & SPI_AUTOCR_TRIGEN) == 0U) && (hspi->Init.Mode == SPI_MODE_MASTER)) + { + /* Master transfer start */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); + } + + /* Receive data in 32 Bit mode */ + if ((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (IS_SPI_FULL_INSTANCE(hspi->Instance))) + { + /* Transfer loop */ + while (hspi->RxXferCount > 0UL) + { + /* Check the RXWNE/EOT flag */ + if ((hspi->Instance->SR & (SPI_FLAG_RXWNE | SPI_FLAG_EOT)) != 0UL) + { + *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint32_t); + hspi->RxXferCount--; + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + /* Call standard close procedure with error check */ + SPI_CloseTransfer(hspi); + + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + return HAL_TIMEOUT; + } + } + } + } + /* Receive data in 16 Bit mode */ + else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + /* Transfer loop */ + while (hspi->RxXferCount > 0UL) + { + /* Check the RXP flag */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) + { +#if defined (__GNUC__) + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; +#else + *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); +#endif /* __GNUC__ */ + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + /* Call standard close procedure with error check */ + SPI_CloseTransfer(hspi); + + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + return HAL_TIMEOUT; + } + } + } + } + /* Receive data in 8 Bit mode */ + else + { + /* Transfer loop */ + while (hspi->RxXferCount > 0UL) + { + /* Check the RXP flag */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) + { + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + hspi->RxXferCount--; + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + /* Call standard close procedure with error check */ + SPI_CloseTransfer(hspi); + + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + return HAL_TIMEOUT; + } + } + } + } + +#if (USE_SPI_CRC != 0UL) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Wait for crc data to be received */ + if (SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_EOT, RESET, Timeout, tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + } +#endif /* USE_SPI_CRC */ + + /* Call standard close procedure with error check */ + SPI_CloseTransfer(hspi); + + hspi->State = HAL_SPI_STATE_READY; + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + return HAL_ERROR; + } + else + { + return HAL_OK; + } +} + +/** + * @brief Transmit and Receive an amount of data in blocking mode. + * @param hspi : pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pTxData: pointer to transmission data buffer + * @param pRxData: pointer to reception data buffer + * @param Size : amount of data to be sent and received + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size, uint32_t Timeout) +{ +#if defined (__GNUC__) + __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->TXDR)); + __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->RXDR)); +#endif /* __GNUC__ */ + + uint32_t tickstart; + uint32_t fifo_length; + uint16_t initial_TxXferCount; + uint16_t initial_RxXferCount; + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + initial_TxXferCount = Size; + initial_RxXferCount = Size; + + if (hspi->State != HAL_SPI_STATE_READY) + { + return HAL_BUSY; + } + + if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0UL)) + { + return HAL_ERROR; + } + + /* Lock the process */ + __HAL_LOCK(hspi); + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pRxBuffPtr = (uint8_t *)pRxData; + hspi->RxXferCount = Size; + hspi->RxXferSize = Size; + hspi->pTxBuffPtr = (const uint8_t *)pTxData; + hspi->TxXferCount = Size; + hspi->TxXferSize = Size; + + /*Init field not used in handle to zero */ + hspi->RxISR = NULL; + hspi->TxISR = NULL; + + /* Set Full-Duplex mode */ + SPI_2LINES(hspi); + + /* Initialize FIFO length */ + if (IS_SPI_FULL_INSTANCE(hspi->Instance)) + { + fifo_length = SPI_HIGHEND_FIFO_SIZE; + } + else + { + fifo_length = SPI_LOWEND_FIFO_SIZE; + } + + /* Set the number of data at current transfer */ + MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size); + + __HAL_SPI_ENABLE(hspi); + + if (((hspi->Instance->AUTOCR & SPI_AUTOCR_TRIGEN) == 0U) && (hspi->Init.Mode == SPI_MODE_MASTER)) + { + /* Master transfer start */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); + } + + /* Transmit and Receive data in 32 Bit mode */ + if ((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (IS_SPI_FULL_INSTANCE(hspi->Instance))) + { + /* Adapt fifo length to 32bits data width */ + fifo_length = (fifo_length / 4UL); + + while ((initial_TxXferCount > 0UL) || (initial_RxXferCount > 0UL)) + { + /* Check TXP flag */ + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (initial_TxXferCount > 0UL) && + (initial_RxXferCount < (initial_TxXferCount + fifo_length))) + { + *((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint32_t); + hspi->TxXferCount --; + initial_TxXferCount = hspi->TxXferCount; + } + + /* Check RXWNE/EOT flag */ + if (((hspi->Instance->SR & (SPI_FLAG_RXWNE | SPI_FLAG_EOT)) != 0UL) && (initial_RxXferCount > 0UL)) + { + *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint32_t); + hspi->RxXferCount --; + initial_RxXferCount = hspi->RxXferCount; + } + + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + /* Call standard close procedure with error check */ + SPI_CloseTransfer(hspi); + + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + return HAL_TIMEOUT; + } + } + } + /* Transmit and Receive data in 16 Bit mode */ + else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + /* Adapt fifo length to 16bits data width */ + fifo_length = (fifo_length / 2UL); + + while ((initial_TxXferCount > 0UL) || (initial_RxXferCount > 0UL)) + { + /* Check the TXP flag */ + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (initial_TxXferCount > 0UL) && + (initial_RxXferCount < (initial_TxXferCount + fifo_length))) + { +#if defined (__GNUC__) + *ptxdr_16bits = *((const uint16_t *)hspi->pTxBuffPtr); +#else + *((__IO uint16_t *)&hspi->Instance->TXDR) = *((const uint16_t *)hspi->pTxBuffPtr); +#endif /* __GNUC__ */ + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + initial_TxXferCount = hspi->TxXferCount; + } + + /* Check the RXP flag */ + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) && (initial_RxXferCount > 0UL)) + { +#if defined (__GNUC__) + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; +#else + *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); +#endif /* __GNUC__ */ + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; + initial_RxXferCount = hspi->RxXferCount; + } + + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + /* Call standard close procedure with error check */ + SPI_CloseTransfer(hspi); + + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + return HAL_TIMEOUT; + } + } + } + /* Transmit and Receive data in 8 Bit mode */ + else + { + while ((initial_TxXferCount > 0UL) || (initial_RxXferCount > 0UL)) + { + /* Check the TXP flag */ + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (initial_TxXferCount > 0UL) && + (initial_RxXferCount < (initial_TxXferCount + fifo_length))) + { + *((__IO uint8_t *)&hspi->Instance->TXDR) = *((const uint8_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint8_t); + hspi->TxXferCount--; + initial_TxXferCount = hspi->TxXferCount; + } + + /* Check the RXP flag */ + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) && (initial_RxXferCount > 0UL)) + { + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + hspi->RxXferCount--; + initial_RxXferCount = hspi->RxXferCount; + } + + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + /* Call standard close procedure with error check */ + SPI_CloseTransfer(hspi); + + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); + hspi->State = HAL_SPI_STATE_READY; + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + return HAL_TIMEOUT; + } + } + } + + /* Wait for Tx/Rx (and CRC) data to be sent/received */ + if (SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_EOT, RESET, Timeout, tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Call standard close procedure with error check */ + SPI_CloseTransfer(hspi); + + hspi->State = HAL_SPI_STATE_READY; + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + return HAL_ERROR; + } + else + { + return HAL_OK; + } +} + +/** + * @brief Transmit an amount of data in non-blocking mode with Interrupt. + * @param hspi : pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData: pointer to data buffer + * @param Size : amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size) +{ + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction)); + + if ((pData == NULL) || (Size == 0UL)) + { + return HAL_ERROR; + } + + if (hspi->State != HAL_SPI_STATE_READY) + { + return HAL_BUSY; + } + + /* Lock the process */ + __HAL_LOCK(hspi); + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_TX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pTxBuffPtr = (const uint8_t *)pData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + + /* Init field not used in handle to zero */ + hspi->pRxBuffPtr = NULL; + hspi->RxXferSize = (uint16_t) 0UL; + hspi->RxXferCount = (uint16_t) 0UL; + hspi->RxISR = NULL; + + /* Set the function for IT treatment */ + if ((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (IS_SPI_FULL_INSTANCE(hspi->Instance))) + { + hspi->TxISR = SPI_TxISR_32BIT; + } + else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + hspi->TxISR = SPI_TxISR_16BIT; + } + else + { + hspi->TxISR = SPI_TxISR_8BIT; + } + + /* Configure communication direction : 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_TX(hspi); + } + else + { + SPI_2LINES_TX(hspi); + } + + /* Set the number of data at current transfer */ + MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size); + + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + /* Enable EOT, TXP, FRE, MODF and UDR interrupts */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_TXP | SPI_IT_UDR | SPI_IT_FRE | SPI_IT_MODF)); + + if (((hspi->Instance->AUTOCR & SPI_AUTOCR_TRIGEN) == 0U) && (hspi->Init.Mode == SPI_MODE_MASTER)) + { + /* Master transfer start */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); + } + + return HAL_OK; +} + +/** + * @brief Receive an amount of data in non-blocking mode with Interrupt. + * @param hspi : pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData: pointer to data buffer + * @param Size : amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +{ + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction)); + + if (hspi->State != HAL_SPI_STATE_READY) + { + return HAL_BUSY; + } + + if ((pData == NULL) || (Size == 0UL)) + { + return HAL_ERROR; + } + + /* Lock the process */ + __HAL_LOCK(hspi); + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_RX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pRxBuffPtr = (uint8_t *)pData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /* Init field not used in handle to zero */ + hspi->pTxBuffPtr = NULL; + hspi->TxXferSize = (uint16_t) 0UL; + hspi->TxXferCount = (uint16_t) 0UL; + hspi->TxISR = NULL; + + /* Set the function for IT treatment */ + if ((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (IS_SPI_FULL_INSTANCE(hspi->Instance))) + { + hspi->RxISR = SPI_RxISR_32BIT; + } + else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + hspi->RxISR = SPI_RxISR_16BIT; + } + else + { + hspi->RxISR = SPI_RxISR_8BIT; + } + + /* Configure communication direction : 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_RX(hspi); + } + else + { + SPI_2LINES_RX(hspi); + } + + /* Note : The SPI must be enabled after unlocking current process + to avoid the risk of SPI interrupt handle execution before current + process unlock */ + + /* Set the number of data at current transfer */ + MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size); + + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + /* Enable EOT, RXP, OVR, FRE and MODF interrupts */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_RXP | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF)); + + if (((hspi->Instance->AUTOCR & SPI_AUTOCR_TRIGEN) == 0U) && (hspi->Init.Mode == SPI_MODE_MASTER)) + { + /* Master transfer start */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); + } + + return HAL_OK; +} + +/** + * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt. + * @param hspi : pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pTxData: pointer to transmission data buffer + * @param pRxData: pointer to reception data buffer + * @param Size : amount of data to be sent and received + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size) +{ + uint32_t tmp_TxXferCount; +#if defined (__GNUC__) + __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->TXDR)); +#endif /* __GNUC__ */ + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); + + if (hspi->State != HAL_SPI_STATE_READY) + { + return HAL_BUSY; + } + + if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0UL)) + { + return HAL_ERROR; + } + + /* Lock the process */ + __HAL_LOCK(hspi); + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pTxBuffPtr = (const uint8_t *)pTxData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + hspi->pRxBuffPtr = (uint8_t *)pRxData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + tmp_TxXferCount = hspi->TxXferCount; + + /* Set the function for IT treatment */ + if ((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (IS_SPI_FULL_INSTANCE(hspi->Instance))) + { + hspi->TxISR = SPI_TxISR_32BIT; + hspi->RxISR = SPI_RxISR_32BIT; + } + else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + hspi->RxISR = SPI_RxISR_16BIT; + hspi->TxISR = SPI_TxISR_16BIT; + } + else + { + hspi->RxISR = SPI_RxISR_8BIT; + hspi->TxISR = SPI_TxISR_8BIT; + } + + /* Set Full-Duplex mode */ + SPI_2LINES(hspi); + + /* Set the number of data at current transfer */ + MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size); + + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + + /* Fill in the TxFIFO */ + while ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (tmp_TxXferCount != 0UL)) + { + /* Transmit data in 32 Bit mode */ + if (hspi->Init.DataSize > SPI_DATASIZE_16BIT) + { + *((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint32_t); + hspi->TxXferCount--; + tmp_TxXferCount = hspi->TxXferCount; + } + /* Transmit data in 16 Bit mode */ + else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { +#if defined (__GNUC__) + *ptxdr_16bits = *((const uint16_t *)hspi->pTxBuffPtr); +#else + *((__IO uint16_t *)&hspi->Instance->TXDR) = *((const uint16_t *)hspi->pTxBuffPtr); +#endif /* __GNUC__ */ + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + tmp_TxXferCount = hspi->TxXferCount; + } + /* Transmit data in 8 Bit mode */ + else + { + *((__IO uint8_t *)&hspi->Instance->TXDR) = *((const uint8_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint8_t); + hspi->TxXferCount--; + tmp_TxXferCount = hspi->TxXferCount; + } + } + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + /* Enable EOT, DXP, UDR, OVR, FRE and MODF interrupts */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_DXP | SPI_IT_UDR | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF)); + + if (((hspi->Instance->AUTOCR & SPI_AUTOCR_TRIGEN) == 0U) && (hspi->Init.Mode == SPI_MODE_MASTER)) + { + /* Start Master transfer */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); + } + + return HAL_OK; +} + + + + +/** + * @brief Transmit an amount of data in non-blocking mode with DMA. + * @param hspi : pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData: pointer to data buffer + * @param Size : amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef status; + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction)); + + if (hspi->State != HAL_SPI_STATE_READY) + { + return HAL_BUSY; + } + + if ((pData == NULL) || (Size == 0UL)) + { + return HAL_ERROR; + } + + /* Lock the process */ + __HAL_LOCK(hspi); + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_TX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pTxBuffPtr = (const uint8_t *)pData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + + /* Init field not used in handle to zero */ + hspi->pRxBuffPtr = NULL; + hspi->TxISR = NULL; + hspi->RxISR = NULL; + hspi->RxXferSize = (uint16_t)0UL; + hspi->RxXferCount = (uint16_t)0UL; + + /* Configure communication direction : 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_TX(hspi); + } + else + { + SPI_2LINES_TX(hspi); + } + + /* Packing mode management is enabled by the DMA settings */ + if (((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (hspi->hdmatx->Init.SrcDataWidth != DMA_SRC_DATAWIDTH_WORD) && \ + (IS_SPI_FULL_INSTANCE(hspi->Instance))) || \ + ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_BYTE))) + { + /* Restriction the DMA data received is not allowed in this mode */ + __HAL_UNLOCK(hspi); + return HAL_ERROR; + } + + /* Adjust XferCount according to DMA alignment / Data size */ + if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT) + { + if (hspi->hdmatx->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_HALFWORD) + { + hspi->TxXferCount = (hspi->TxXferCount + (uint16_t) 1UL) >> 1UL; + } + if (hspi->hdmatx->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD) + { + hspi->TxXferCount = (hspi->TxXferCount + (uint16_t) 3UL) >> 2UL; + } + } + else if (hspi->Init.DataSize <= SPI_DATASIZE_16BIT) + { + if (hspi->hdmatx->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD) + { + hspi->TxXferCount = (hspi->TxXferCount + (uint16_t) 1UL) >> 1UL; + } + } + else + { + /* Adjustment done */ + } + + /* Set the SPI TxDMA Half transfer complete callback */ + hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt; + + /* Set the SPI TxDMA transfer complete callback */ + hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt; + + /* Set the DMA error callback */ + hspi->hdmatx->XferErrorCallback = SPI_DMAError; + + /* Set the DMA AbortCpltCallback */ + hspi->hdmatx->XferAbortCallback = NULL; + + /* Clear TXDMAEN bit*/ + CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN); + + if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT) + { + hspi->TxXferCount = Size; + } + else if (hspi->Init.DataSize <= SPI_DATASIZE_16BIT) + { + hspi->TxXferCount = Size * 2U; + } + else + { + hspi->TxXferCount = Size * 4U; + } + + /* Enable the Tx DMA Stream/Channel */ + if ((hspi->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hspi->hdmatx->LinkedListQueue != NULL) + { + /* Set DMA data size */ + hspi->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hspi->TxXferCount; + + /* Set DMA source address */ + hspi->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)hspi->pTxBuffPtr; + + /* Set DMA destination address */ + hspi->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)&hspi->Instance->TXDR; + + status = HAL_DMAEx_List_Start_IT(hspi->hdmatx); + } + else + { + status = HAL_ERROR; + } + } + else + { + status = HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->TXDR, + hspi->TxXferCount); + } + + /* Check status */ + if (status != HAL_OK) + { + /* Update SPI error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + hspi->State = HAL_SPI_STATE_READY; + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + return HAL_ERROR; + } + + /* Set the number of data at current transfer */ + if (hspi->hdmatx->Mode == DMA_LINKEDLIST_CIRCULAR) + { + MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, 0UL); + } + else + { + MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size); + } + + /* Enable Tx DMA Request */ + SET_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN); + + /* Enable the SPI Error Interrupt Bit */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_UDR | SPI_IT_FRE | SPI_IT_MODF)); + + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + + if (((hspi->Instance->AUTOCR & SPI_AUTOCR_TRIGEN) == 0U) && (hspi->Init.Mode == SPI_MODE_MASTER)) + { + /* Master transfer start */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); + } + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + return HAL_OK; +} + +/** + * @brief Receive an amount of data in non-blocking mode with DMA. + * @param hspi : pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData: pointer to data buffer + * @param Size : amount of data to be sent + * @note When the CRC feature is enabled the pData Length must be Size + 1. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef status; + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction)); + + + if (hspi->State != HAL_SPI_STATE_READY) + { + __HAL_UNLOCK(hspi); + return HAL_BUSY; + } + + if ((pData == NULL) || (Size == 0UL)) + { + __HAL_UNLOCK(hspi); + return HAL_ERROR; + } + + /* Lock the process */ + __HAL_LOCK(hspi); + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_RX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pRxBuffPtr = (uint8_t *)pData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->RxISR = NULL; + hspi->TxISR = NULL; + hspi->TxXferSize = (uint16_t) 0UL; + hspi->TxXferCount = (uint16_t) 0UL; + + /* Configure communication direction : 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + SPI_1LINE_RX(hspi); + } + else + { + SPI_2LINES_RX(hspi); + } + + /* Packing mode management is enabled by the DMA settings */ + if (((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (hspi->hdmarx->Init.DestDataWidth != DMA_DEST_DATAWIDTH_WORD) && \ + (IS_SPI_FULL_INSTANCE(hspi->Instance))) || \ + ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_BYTE))) + { + /* Restriction the DMA data received is not allowed in this mode */ + __HAL_UNLOCK(hspi); + return HAL_ERROR; + } + + /* Clear RXDMAEN bit */ + CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN); + + /* Adjust XferCount according to DMA alignment / Data size */ + if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT) + { + if (hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_HALFWORD) + { + hspi->RxXferCount = (hspi->RxXferCount + (uint16_t) 1UL) >> 1UL; + } + if (hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_WORD) + { + hspi->RxXferCount = (hspi->RxXferCount + (uint16_t) 3UL) >> 2UL; + } + } + else if (hspi->Init.DataSize <= SPI_DATASIZE_16BIT) + { + if (hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_WORD) + { + hspi->RxXferCount = (hspi->RxXferCount + (uint16_t) 1UL) >> 1UL; + } + } + else + { + /* Adjustment done */ + } + + /* Set the SPI RxDMA Half transfer complete callback */ + hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt; + + /* Set the SPI Rx DMA transfer complete callback */ + hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt; + + /* Set the DMA error callback */ + hspi->hdmarx->XferErrorCallback = SPI_DMAError; + + /* Set the DMA AbortCpltCallback */ + hspi->hdmarx->XferAbortCallback = NULL; + + if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT) + { + hspi->RxXferCount = Size; + } + else if (hspi->Init.DataSize <= SPI_DATASIZE_16BIT) + { + hspi->RxXferCount = Size * 2U; + } + else + { + hspi->RxXferCount = Size * 4U; + } + + /* Enable the Rx DMA Stream/Channel */ + if ((hspi->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hspi->hdmarx->LinkedListQueue != NULL) + { + /* Set DMA data size */ + hspi->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hspi->RxXferCount; + + /* Set DMA source address */ + hspi->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)&hspi->Instance->RXDR; + + /* Set DMA destination address */ + hspi->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)hspi->pRxBuffPtr; + + status = HAL_DMAEx_List_Start_IT(hspi->hdmarx); + } + else + { + status = HAL_ERROR; + } + } + else + { + status = HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->RXDR, (uint32_t)hspi->pRxBuffPtr, + hspi->RxXferCount); + } + + /* Check status */ + if (status != HAL_OK) + { + /* Update SPI error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + hspi->State = HAL_SPI_STATE_READY; + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + return HAL_ERROR; + } + + /* Set the number of data at current transfer */ + if (hspi->hdmarx->Mode == DMA_LINKEDLIST_CIRCULAR) + { + MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, 0UL); + } + else + { + MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size); + } + + /* Enable Rx DMA Request */ + SET_BIT(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN); + + /* Enable the SPI Error Interrupt Bit */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF)); + + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + + if (((hspi->Instance->AUTOCR & SPI_AUTOCR_TRIGEN) == 0U) && (hspi->Init.Mode == SPI_MODE_MASTER)) + { + /* Master transfer start */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); + } + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + return HAL_OK; +} + +/** + * @brief Transmit and Receive an amount of data in non-blocking mode with DMA. + * @param hspi : pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pTxData: pointer to transmission data buffer + * @param pRxData: pointer to reception data buffer + * @param Size : amount of data to be sent + * @note When the CRC feature is enabled the pRxData Length must be Size + 1 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size) +{ + HAL_StatusTypeDef status; + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); + + if (hspi->State != HAL_SPI_STATE_READY) + { + return HAL_BUSY; + } + + if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0UL)) + { + return HAL_ERROR; + } + + /* Lock the process */ + __HAL_LOCK(hspi); + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pTxBuffPtr = (const uint8_t *)pTxData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + hspi->pRxBuffPtr = (uint8_t *)pRxData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /* Init field not used in handle to zero */ + hspi->RxISR = NULL; + hspi->TxISR = NULL; + + /* Set Full-Duplex mode */ + SPI_2LINES(hspi); + + /* Reset the Tx/Rx DMA bits */ + CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN); + + /* Packing mode management is enabled by the DMA settings */ + if (((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (hspi->hdmarx->Init.DestDataWidth != DMA_DEST_DATAWIDTH_WORD) && \ + (IS_SPI_FULL_INSTANCE(hspi->Instance))) || \ + ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_BYTE))) + { + /* Restriction the DMA data received is not allowed in this mode */ + /* Unlock the process */ + __HAL_UNLOCK(hspi); + return HAL_ERROR; + } + + /* Adjust XferCount according to DMA alignment / Data size */ + if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT) + { + if (hspi->hdmatx->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_HALFWORD) + { + hspi->TxXferCount = (hspi->TxXferCount + (uint16_t) 1UL) >> 1UL; + } + if (hspi->hdmatx->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD) + { + hspi->TxXferCount = (hspi->TxXferCount + (uint16_t) 3UL) >> 2UL; + } + if (hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_HALFWORD) + { + hspi->RxXferCount = (hspi->RxXferCount + (uint16_t) 1UL) >> 1UL; + } + if (hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_WORD) + { + hspi->RxXferCount = (hspi->RxXferCount + (uint16_t) 3UL) >> 2UL; + } + } + else if (hspi->Init.DataSize <= SPI_DATASIZE_16BIT) + { + if (hspi->hdmatx->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD) + { + hspi->TxXferCount = (hspi->TxXferCount + (uint16_t) 1UL) >> 1UL; + } + if (hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_WORD) + { + hspi->RxXferCount = (hspi->RxXferCount + (uint16_t) 1UL) >> 1UL; + } + } + else + { + /* Adjustment done */ + } + + /* Set the SPI Tx/Rx DMA Half transfer complete callback */ + hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt; + hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt; + + /* Set the DMA error callback */ + hspi->hdmarx->XferErrorCallback = SPI_DMAError; + + /* Set the DMA AbortCallback */ + hspi->hdmarx->XferAbortCallback = NULL; + + if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT) + { + hspi->RxXferCount = Size; + } + else if (hspi->Init.DataSize <= SPI_DATASIZE_16BIT) + { + hspi->RxXferCount = Size * 2U; + } + else + { + hspi->RxXferCount = Size * 4U; + } + /* Enable the Rx DMA Stream/Channel */ + if ((hspi->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hspi->hdmarx->LinkedListQueue != NULL) + { + /* Set DMA data size */ + hspi->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hspi->RxXferCount; + + /* Set DMA source address */ + hspi->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)&hspi->Instance->RXDR; + + /* Set DMA destination address */ + hspi->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)hspi->pRxBuffPtr; + + status = HAL_DMAEx_List_Start_IT(hspi->hdmarx); + } + else + { + status = HAL_ERROR; + } + } + else + { + status = HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->RXDR, (uint32_t)hspi->pRxBuffPtr, + hspi->RxXferCount); + } + + /* Check status */ + if (status != HAL_OK) + { + /* Update SPI error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + hspi->State = HAL_SPI_STATE_READY; + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + return HAL_ERROR; + } + + /* Enable Rx DMA Request */ + SET_BIT(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN); + + /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing + is performed in DMA reception complete callback */ + hspi->hdmatx->XferHalfCpltCallback = NULL; + hspi->hdmatx->XferCpltCallback = NULL; + hspi->hdmatx->XferAbortCallback = NULL; + + /* Set the DMA error callback */ + hspi->hdmatx->XferErrorCallback = SPI_DMAError; + + if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT) + { + hspi->TxXferCount = Size; + } + else if (hspi->Init.DataSize <= SPI_DATASIZE_16BIT) + { + hspi->TxXferCount = Size * 2U; + } + else + { + hspi->TxXferCount = Size * 4U; + } + + /* Enable the Tx DMA Stream/Channel */ + if ((hspi->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if (hspi->hdmatx->LinkedListQueue != NULL) + { + /* Set DMA data size */ + hspi->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hspi->TxXferCount; + + /* Set DMA source address */ + hspi->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)hspi->pTxBuffPtr; + + /* Set DMA destination address */ + hspi->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)&hspi->Instance->TXDR; + + status = HAL_DMAEx_List_Start_IT(hspi->hdmatx); + } + else + { + status = HAL_ERROR; + } + } + else + { + status = HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->TXDR, + hspi->TxXferCount); + } + + /* Check status */ + if (status != HAL_OK) + { + /* Abort Rx DMA Channel already started */ + (void)HAL_DMA_Abort(hspi->hdmarx); + + /* Update SPI error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + hspi->State = HAL_SPI_STATE_READY; + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + return HAL_ERROR; + } + + if ((hspi->hdmarx->Mode == DMA_LINKEDLIST_CIRCULAR) && (hspi->hdmatx->Mode == DMA_LINKEDLIST_CIRCULAR)) + { + MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, 0UL); + } + else + { + MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size); + } + + /* Enable Tx DMA Request */ + SET_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN); + + /* Enable the SPI Error Interrupt Bit */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_OVR | SPI_IT_UDR | SPI_IT_FRE | SPI_IT_MODF)); + + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + + if (((hspi->Instance->AUTOCR & SPI_AUTOCR_TRIGEN) == 0U) && (hspi->Init.Mode == SPI_MODE_MASTER)) + { + /* Master transfer start */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); + } + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + return HAL_OK; +} + +/** + * @brief Abort ongoing transfer (blocking mode). + * @param hspi SPI handle. + * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx), + * started in Interrupt or DMA mode. + * @note This procedure performs following operations : + * + Disable SPI Interrupts (depending of transfer direction) + * + Disable the DMA transfer in the peripheral register (if enabled) + * + Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * + Set handle State to READY. + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) +{ + HAL_StatusTypeDef errorcode; + + __IO uint32_t count; + + /* Lock the process */ + __HAL_LOCK(hspi); + + /* Set hspi->state to aborting to avoid any interaction */ + hspi->State = HAL_SPI_STATE_ABORT; + + /* Initialized local variable */ + errorcode = HAL_OK; + count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24UL / 1000UL); + + /* If master communication on going, make sure current frame is done before closing the connection */ + if (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART)) + { + /* Disable EOT interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_EOT); + do + { + count--; + if (count == 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + } while (HAL_IS_BIT_SET(hspi->Instance->IER, SPI_IT_EOT)); + + /* Request a Suspend transfer */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CSUSP); + do + { + count--; + if (count == 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + } while (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART)); + + /* Clear SUSP flag */ + __HAL_SPI_CLEAR_SUSPFLAG(hspi); + do + { + count--; + if (count == 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + } while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_SUSP)); + } + + /* Disable the SPI DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN)) + { + if (hspi->hdmatx != NULL) + { + /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */ + hspi->hdmatx->XferAbortCallback = NULL; + + /* Abort DMA Tx Handle linked to SPI Peripheral */ + if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(hspi->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + } + } + } + + /* Disable the SPI DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN)) + { + if (hspi->hdmarx != NULL) + { + /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */ + hspi->hdmarx->XferAbortCallback = NULL; + + /* Abort DMA Rx Handle linked to SPI Peripheral */ + if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(hspi->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + } + } + } + + /* Proceed with abort procedure */ + SPI_AbortTransfer(hspi); + + /* Check error during Abort procedure */ + if (HAL_IS_BIT_SET(hspi->ErrorCode, HAL_SPI_ERROR_ABORT)) + { + /* return HAL_Error in case of error during Abort procedure */ + errorcode = HAL_ERROR; + } + else + { + /* Reset errorCode */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + } + + /* Restore hspi->state to ready */ + hspi->State = HAL_SPI_STATE_READY; + + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + return errorcode; +} + +/** + * @brief Abort ongoing transfer (Interrupt mode). + * @param hspi SPI handle. + * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx), + * started in Interrupt or DMA mode. + * @note This procedure performs following operations : + * + Disable SPI Interrupts (depending of transfer direction) + * + Disable the DMA transfer in the peripheral register (if enabled) + * + Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * + Set handle State to READY + * + At abort completion, call user abort complete callback. + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) +{ + HAL_StatusTypeDef errorcode; + __IO uint32_t count; + uint32_t dma_tx_abort_done = 1UL; + uint32_t dma_rx_abort_done = 1UL; + + /* Set hspi->state to aborting to avoid any interaction */ + hspi->State = HAL_SPI_STATE_ABORT; + + /* Initialized local variable */ + errorcode = HAL_OK; + count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24UL / 1000UL); + + /* If master communication on going, make sure current frame is done before closing the connection */ + if (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART)) + { + /* Disable EOT interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_EOT); + do + { + count--; + if (count == 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + } while (HAL_IS_BIT_SET(hspi->Instance->IER, SPI_IT_EOT)); + + /* Request a Suspend transfer */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CSUSP); + do + { + count--; + if (count == 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + } while (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART)); + + /* Clear SUSP flag */ + __HAL_SPI_CLEAR_SUSPFLAG(hspi); + do + { + count--; + if (count == 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + } while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_SUSP)); + } + + /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialized + before any call to DMA Abort functions */ + + if (hspi->hdmatx != NULL) + { + if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN)) + { + /* Set DMA Abort Complete callback if SPI DMA Tx request if enabled */ + hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback; + + dma_tx_abort_done = 0UL; + + /* Abort DMA Tx Handle linked to SPI Peripheral */ + if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(hspi->hdmatx) == HAL_DMA_ERROR_NO_XFER) + { + dma_tx_abort_done = 1UL; + hspi->hdmatx->XferAbortCallback = NULL; + } + } + } + else + { + hspi->hdmatx->XferAbortCallback = NULL; + } + } + + if (hspi->hdmarx != NULL) + { + if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN)) + { + /* Set DMA Abort Complete callback if SPI DMA Rx request if enabled */ + hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback; + + dma_rx_abort_done = 0UL; + + /* Abort DMA Rx Handle linked to SPI Peripheral */ + if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(hspi->hdmarx) == HAL_DMA_ERROR_NO_XFER) + { + dma_rx_abort_done = 1UL; + hspi->hdmarx->XferAbortCallback = NULL; + } + } + } + else + { + hspi->hdmarx->XferAbortCallback = NULL; + } + } + + /* If no running DMA transfer, finish cleanup and call callbacks */ + if ((dma_tx_abort_done == 1UL) && (dma_rx_abort_done == 1UL)) + { + /* Proceed with abort procedure */ + SPI_AbortTransfer(hspi); + + /* Check error during Abort procedure */ + if (HAL_IS_BIT_SET(hspi->ErrorCode, HAL_SPI_ERROR_ABORT)) + { + /* return HAL_Error in case of error during Abort procedure */ + errorcode = HAL_ERROR; + } + else + { + /* Reset errorCode */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + } + + /* Restore hspi->state to ready */ + hspi->State = HAL_SPI_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + hspi->AbortCpltCallback(hspi); +#else + HAL_SPI_AbortCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + + return errorcode; +} + +/** + * @brief Pause the DMA Transfer. + * This API is not supported, it is maintained for backward compatibility. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval HAL_ERROR + */ +HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi) +{ + /* Set error code to not supported */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_NOT_SUPPORTED); + + return HAL_ERROR; +} + +/** + * @brief Resume the DMA Transfer. + * This API is not supported, it is maintained for backward compatibility. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval HAL_ERROR + */ +HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi) +{ + /* Set error code to not supported */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_NOT_SUPPORTED); + + return HAL_ERROR; +} + +/** + * @brief Stop the DMA Transfer. + * This API is not supported, it is maintained for backward compatibility. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval HAL_ERROR + */ +HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi) +{ + /* Set error code to not supported */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_NOT_SUPPORTED); + + return HAL_ERROR; +} + +/** + * @brief Handle SPI interrupt request. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval None + */ +void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) +{ + uint32_t itsource = hspi->Instance->IER; + uint32_t itflag = hspi->Instance->SR; + uint32_t trigger = itsource & itflag; + uint32_t cfg1 = hspi->Instance->CFG1; + uint32_t handled = 0UL; + + HAL_SPI_StateTypeDef State = hspi->State; +#if defined (__GNUC__) + __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->RXDR)); +#endif /* __GNUC__ */ + + /* SPI in SUSPEND mode ----------------------------------------------------*/ + if (HAL_IS_BIT_SET(itflag, SPI_FLAG_SUSP) && HAL_IS_BIT_SET(itsource, SPI_FLAG_EOT)) + { + /* Clear the Suspend flag */ + __HAL_SPI_CLEAR_SUSPFLAG(hspi); + + /* Suspend on going, Call the Suspend callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + hspi->SuspendCallback(hspi); +#else + HAL_SPI_SuspendCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + return; + } + + /* SPI in mode Transmitter and Receiver ------------------------------------*/ + if (HAL_IS_BIT_CLR(trigger, SPI_FLAG_OVR) && HAL_IS_BIT_CLR(trigger, SPI_FLAG_UDR) && \ + HAL_IS_BIT_SET(trigger, SPI_FLAG_DXP)) + { + hspi->TxISR(hspi); + hspi->RxISR(hspi); + handled = 1UL; + } + + /* SPI in mode Receiver ----------------------------------------------------*/ + if (HAL_IS_BIT_CLR(trigger, SPI_FLAG_OVR) && HAL_IS_BIT_SET(trigger, SPI_FLAG_RXP) && \ + HAL_IS_BIT_CLR(trigger, SPI_FLAG_DXP)) + { + hspi->RxISR(hspi); + handled = 1UL; + } + + /* SPI in mode Transmitter -------------------------------------------------*/ + if (HAL_IS_BIT_CLR(trigger, SPI_FLAG_UDR) && HAL_IS_BIT_SET(trigger, SPI_FLAG_TXP) && \ + HAL_IS_BIT_CLR(trigger, SPI_FLAG_DXP)) + { + hspi->TxISR(hspi); + handled = 1UL; + } + + if (handled != 0UL) + { + return; + } + + /* SPI End Of Transfer: DMA or IT based transfer */ + if (HAL_IS_BIT_SET(trigger, SPI_FLAG_EOT)) + { + /* Clear EOT/TXTF/SUSP flag */ + __HAL_SPI_CLEAR_EOTFLAG(hspi); + __HAL_SPI_CLEAR_TXTFFLAG(hspi); + __HAL_SPI_CLEAR_SUSPFLAG(hspi); + + /* Disable EOT interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_EOT); + + /* For the IT based receive extra polling maybe required for last packet */ + if (HAL_IS_BIT_CLR(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN)) + { + /* Pooling remaining data */ + while (hspi->RxXferCount != 0UL) + { + /* Receive data in 32 Bit mode */ + if (hspi->Init.DataSize > SPI_DATASIZE_16BIT) + { + *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint32_t); + } + /* Receive data in 16 Bit mode */ + else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { +#if defined (__GNUC__) + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; +#else + *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); +#endif /* __GNUC__ */ + hspi->pRxBuffPtr += sizeof(uint16_t); + } + /* Receive data in 8 Bit mode */ + else + { + *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + } + + hspi->RxXferCount--; + } + } + + /* Call SPI Standard close procedure */ + SPI_CloseTransfer(hspi); + + hspi->State = HAL_SPI_STATE_READY; + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + return; + } + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + /* Call appropriate user callback */ + if (State == HAL_SPI_STATE_BUSY_TX_RX) + { + hspi->TxRxCpltCallback(hspi); + } + else if (State == HAL_SPI_STATE_BUSY_RX) + { + hspi->RxCpltCallback(hspi); + } + else if (State == HAL_SPI_STATE_BUSY_TX) + { + hspi->TxCpltCallback(hspi); + } +#else + /* Call appropriate user callback */ + if (State == HAL_SPI_STATE_BUSY_TX_RX) + { + HAL_SPI_TxRxCpltCallback(hspi); + } + else if (State == HAL_SPI_STATE_BUSY_RX) + { + HAL_SPI_RxCpltCallback(hspi); + } + else if (State == HAL_SPI_STATE_BUSY_TX) + { + HAL_SPI_TxCpltCallback(hspi); + } +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + else + { + /* End of the appropriate call */ + } + + return; + } + + /* SPI in Error Treatment --------------------------------------------------*/ + if ((trigger & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE | SPI_FLAG_UDR)) != 0UL) + { + /* SPI Overrun error interrupt occurred ----------------------------------*/ + if ((trigger & SPI_FLAG_OVR) != 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR); + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + + /* SPI Mode Fault error interrupt occurred -------------------------------*/ + if ((trigger & SPI_FLAG_MODF) != 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF); + __HAL_SPI_CLEAR_MODFFLAG(hspi); + } + + /* SPI Frame error interrupt occurred ------------------------------------*/ + if ((trigger & SPI_FLAG_FRE) != 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE); + __HAL_SPI_CLEAR_FREFLAG(hspi); + } + + /* SPI Underrun error interrupt occurred ------------------------------------*/ + if ((trigger & SPI_FLAG_UDR) != 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_UDR); + __HAL_SPI_CLEAR_UDRFLAG(hspi); + } + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + + /* Disable all interrupts */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_RXP | SPI_IT_TXP | SPI_IT_MODF | + SPI_IT_OVR | SPI_IT_FRE | SPI_IT_UDR)); + + /* Disable the SPI DMA requests if enabled */ + if (HAL_IS_BIT_SET(cfg1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN)) + { + /* Disable the SPI DMA requests */ + CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN); + + /* Abort the SPI DMA Rx channel */ + if (hspi->hdmarx != NULL) + { + /* Set the SPI DMA Abort callback : + will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */ + hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError; + if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmarx)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + } + } + /* Abort the SPI DMA Tx channel */ + if (hspi->hdmatx != NULL) + { + /* Set the SPI DMA Abort callback : + will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */ + hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError; + if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmatx)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + } + } + } + else + { + /* Restore hspi->State to Ready */ + hspi->State = HAL_SPI_STATE_READY; + + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + } + return; + } +} + +/** + * @brief Tx Transfer completed callback. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */ +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_TxCpltCallback should be implemented in the user file + */ +} + +/** + * @brief Rx Transfer completed callback. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */ +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_RxCpltCallback should be implemented in the user file + */ +} + +/** + * @brief Tx and Rx Transfer completed callback. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */ +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_TxRxCpltCallback should be implemented in the user file + */ +} + +/** + * @brief Tx Half Transfer completed callback. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */ +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_TxHalfCpltCallback should be implemented in the user file + */ +} + +/** + * @brief Rx Half Transfer completed callback. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */ +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file + */ +} + +/** + * @brief Tx and Rx Half Transfer callback. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */ +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file + */ +} + +/** + * @brief SPI error callback. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */ +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_ErrorCallback should be implemented in the user file + */ + /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes + and user can use HAL_SPI_GetError() API to check the latest error occurred + */ +} + +/** + * @brief SPI Abort Complete callback. + * @param hspi SPI handle. + * @retval None + */ +__weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */ +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_AbortCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief SPI Suspend callback. + * @param hspi SPI handle. + * @retval None + */ +__weak void HAL_SPI_SuspendCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */ +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_SuspendCallback can be implemented in the user file. + */ +} + +/** + * @} + */ + +/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief SPI control functions + * +@verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the SPI. + (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral + (+) HAL_SPI_GetError() check in run-time Errors occurring during communication +@endverbatim + * @{ + */ + +/** + * @brief Return the SPI handle state. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval SPI state + */ +HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi) +{ + /* Return SPI handle state */ + return hspi->State; +} + +/** + * @brief Return the SPI error code. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval SPI error code in bitmap format + */ +uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi) +{ + /* Return SPI ErrorCode */ + return hspi->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup SPI_Private_Functions + * @brief Private functions + * @{ + */ + +/** + * @brief DMA SPI transmit process complete callback. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hspi->State != HAL_SPI_STATE_ABORT) + { + if (hspi->hdmatx->Mode == DMA_LINKEDLIST_CIRCULAR) + { +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + hspi->TxCpltCallback(hspi); +#else + HAL_SPI_TxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + else + { + /* Enable EOT interrupt */ + __HAL_SPI_ENABLE_IT(hspi, SPI_IT_EOT); + } + } +} + +/** + * @brief DMA SPI receive process complete callback. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hspi->State != HAL_SPI_STATE_ABORT) + { + if (hspi->hdmarx->Mode == DMA_LINKEDLIST_CIRCULAR) + { +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + hspi->RxCpltCallback(hspi); +#else + HAL_SPI_RxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + else + { + /* Enable EOT interrupt */ + __HAL_SPI_ENABLE_IT(hspi, SPI_IT_EOT); + } + } +} + +/** + * @brief DMA SPI transmit receive process complete callback. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hspi->State != HAL_SPI_STATE_ABORT) + { + if ((hspi->hdmarx->Mode == DMA_LINKEDLIST_CIRCULAR) && + (hspi->hdmatx->Mode == DMA_LINKEDLIST_CIRCULAR)) + { +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + hspi->TxRxCpltCallback(hspi); +#else + HAL_SPI_TxRxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + else + { + /* Enable EOT interrupt */ + __HAL_SPI_ENABLE_IT(hspi, SPI_IT_EOT); + } + } +} + +/** + * @brief DMA SPI half transmit process complete callback. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) /* Derogation MISRAC2012-Rule-8.13 */ +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *) + ((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-8.13 */ + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + hspi->TxHalfCpltCallback(hspi); +#else + HAL_SPI_TxHalfCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI half receive process complete callback + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) /* Derogation MISRAC2012-Rule-8.13 */ +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *) + ((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-8.13 */ + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + hspi->RxHalfCpltCallback(hspi); +#else + HAL_SPI_RxHalfCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI half transmit receive process complete callback. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) /* Derogation MISRAC2012-Rule-8.13 */ +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *) + ((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-8.13 */ + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + hspi->TxRxHalfCpltCallback(hspi); +#else + HAL_SPI_TxRxHalfCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI communication error callback. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAError(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* if DMA error is FIFO error ignore it */ + if (HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_NONE) + { + /* Call SPI standard close procedure */ + SPI_CloseTransfer(hspi); + + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + hspi->State = HAL_SPI_STATE_READY; +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } +} + +/** + * @brief DMA SPI communication abort callback, when initiated by HAL services on Error + * (To be called at end of DMA Abort procedure following error occurrence). + * @param hdma DMA handle. + * @retval None + */ +static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + hspi->RxXferCount = (uint16_t) 0UL; + hspi->TxXferCount = (uint16_t) 0UL; + + /* Restore hspi->State to Ready */ + hspi->State = HAL_SPI_STATE_READY; + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI Tx communication abort callback, when initiated by user + * (To be called at end of DMA Tx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Rx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + hspi->hdmatx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if (hspi->hdmarx != NULL) + { + if (hspi->hdmarx->XferAbortCallback != NULL) + { + return; + } + } + + /* Call the Abort procedure */ + SPI_AbortTransfer(hspi); + + /* Restore hspi->State to Ready */ + hspi->State = HAL_SPI_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + hspi->AbortCpltCallback(hspi); +#else + HAL_SPI_AbortCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI Rx communication abort callback, when initiated by user + * (To be called at end of DMA Rx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Tx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + hspi->hdmarx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if (hspi->hdmatx != NULL) + { + if (hspi->hdmatx->XferAbortCallback != NULL) + { + return; + } + } + + /* Call the Abort procedure */ + SPI_AbortTransfer(hspi); + + /* Restore hspi->State to Ready */ + hspi->State = HAL_SPI_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) + hspi->AbortCpltCallback(hspi); +#else + HAL_SPI_AbortCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief Manage the receive 8-bit in Interrupt context. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_RxISR_8BIT(SPI_HandleTypeDef *hspi) +{ + /* Receive data in 8 Bit mode */ + *((uint8_t *)hspi->pRxBuffPtr) = (*(__IO uint8_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint8_t); + hspi->RxXferCount--; + + /* Disable IT if no more data excepted */ + if (hspi->RxXferCount == 0UL) + { + /* Disable RXP interrupts */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXP); + } +} + + +/** + * @brief Manage the 16-bit receive in Interrupt context. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_RxISR_16BIT(SPI_HandleTypeDef *hspi) +{ + /* Receive data in 16 Bit mode */ +#if defined (__GNUC__) + __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->RXDR)); + + *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; +#else + *((uint16_t *)hspi->pRxBuffPtr) = (*(__IO uint16_t *)&hspi->Instance->RXDR); +#endif /* __GNUC__ */ + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; + + /* Disable IT if no more data excepted */ + if (hspi->RxXferCount == 0UL) + { + /* Disable RXP interrupts */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXP); + } +} + + +/** + * @brief Manage the 32-bit receive in Interrupt context. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_RxISR_32BIT(SPI_HandleTypeDef *hspi) +{ + /* Receive data in 32 Bit mode */ + *((uint32_t *)hspi->pRxBuffPtr) = (*(__IO uint32_t *)&hspi->Instance->RXDR); + hspi->pRxBuffPtr += sizeof(uint32_t); + hspi->RxXferCount--; + + /* Disable IT if no more data excepted */ + if (hspi->RxXferCount == 0UL) + { + /* Disable RXP interrupts */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXP); + } +} + + +/** + * @brief Handle the data 8-bit transmit in Interrupt mode. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_TxISR_8BIT(SPI_HandleTypeDef *hspi) +{ + /* Transmit data in 8 Bit mode */ + *(__IO uint8_t *)&hspi->Instance->TXDR = *((const uint8_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint8_t); + hspi->TxXferCount--; + + /* Disable IT if no more data excepted */ + if (hspi->TxXferCount == 0UL) + { + /* Disable TXP interrupts */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXP); + } +} + +/** + * @brief Handle the data 16-bit transmit in Interrupt mode. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_TxISR_16BIT(SPI_HandleTypeDef *hspi) +{ + /* Transmit data in 16 Bit mode */ +#if defined (__GNUC__) + __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->TXDR)); + + *ptxdr_16bits = *((const uint16_t *)hspi->pTxBuffPtr); +#else + *((__IO uint16_t *)&hspi->Instance->TXDR) = *((const uint16_t *)hspi->pTxBuffPtr); +#endif /* __GNUC__ */ + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + + /* Disable IT if no more data excepted */ + if (hspi->TxXferCount == 0UL) + { + /* Disable TXP interrupts */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXP); + } +} + +/** + * @brief Handle the data 32-bit transmit in Interrupt mode. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_TxISR_32BIT(SPI_HandleTypeDef *hspi) +{ + /* Transmit data in 32 Bit mode */ + *((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint32_t); + hspi->TxXferCount--; + + /* Disable IT if no more data excepted */ + if (hspi->TxXferCount == 0UL) + { + /* Disable TXP interrupts */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXP); + } +} + +/** + * @brief Abort Transfer and clear flags. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_AbortTransfer(SPI_HandleTypeDef *hspi) +{ + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + + /* Disable ITs */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_TXP | SPI_IT_RXP | SPI_IT_DXP | SPI_IT_UDR | SPI_IT_OVR | \ + SPI_IT_FRE | SPI_IT_MODF)); + + /* Clear the Status flags in the SR register */ + __HAL_SPI_CLEAR_EOTFLAG(hspi); + __HAL_SPI_CLEAR_TXTFFLAG(hspi); + + /* Disable Tx DMA Request */ + CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN); + + /* Clear the Error flags in the SR register */ + __HAL_SPI_CLEAR_OVRFLAG(hspi); + __HAL_SPI_CLEAR_UDRFLAG(hspi); + __HAL_SPI_CLEAR_FREFLAG(hspi); + __HAL_SPI_CLEAR_MODFFLAG(hspi); + __HAL_SPI_CLEAR_SUSPFLAG(hspi); + +#if (USE_SPI_CRC != 0U) + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); +#endif /* USE_SPI_CRC */ + + hspi->TxXferCount = (uint16_t)0UL; + hspi->RxXferCount = (uint16_t)0UL; +} + + +/** + * @brief Close Transfer and clear flags. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval HAL_ERROR: if any error detected + * HAL_OK: if nothing detected + */ +static void SPI_CloseTransfer(SPI_HandleTypeDef *hspi) +{ + uint32_t itflag = hspi->Instance->SR; + + __HAL_SPI_CLEAR_EOTFLAG(hspi); + __HAL_SPI_CLEAR_TXTFFLAG(hspi); + + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + + /* Disable ITs */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_TXP | SPI_IT_RXP | SPI_IT_DXP | SPI_IT_UDR | SPI_IT_OVR | \ + SPI_IT_FRE | SPI_IT_MODF)); + + /* Disable Tx DMA Request */ + CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN); + + /* Report UnderRun error for non RX Only communication */ + if (hspi->State != HAL_SPI_STATE_BUSY_RX) + { + if ((itflag & SPI_FLAG_UDR) != 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_UDR); + __HAL_SPI_CLEAR_UDRFLAG(hspi); + } + } + + /* Report OverRun error for non TX Only communication */ + if (hspi->State != HAL_SPI_STATE_BUSY_TX) + { + if ((itflag & SPI_FLAG_OVR) != 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR); + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + +#if (USE_SPI_CRC != 0UL) + /* Check if CRC error occurred */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + if ((itflag & SPI_FLAG_CRCERR) != 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + } + } +#endif /* USE_SPI_CRC */ + } + + /* SPI Mode Fault error interrupt occurred -------------------------------*/ + if ((itflag & SPI_FLAG_MODF) != 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF); + __HAL_SPI_CLEAR_MODFFLAG(hspi); + } + + /* SPI Frame error interrupt occurred ------------------------------------*/ + if ((itflag & SPI_FLAG_FRE) != 0UL) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE); + __HAL_SPI_CLEAR_FREFLAG(hspi); + } + + hspi->TxXferCount = (uint16_t)0UL; + hspi->RxXferCount = (uint16_t)0UL; +} + +/** + * @brief Handle SPI Communication Timeout. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param Flag: SPI flag to check + * @param Status: flag state to check + * @param Timeout: Timeout duration + * @param Tickstart: Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(const SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, + uint32_t Timeout, uint32_t Tickstart) +{ + /* Wait until flag is set */ + while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) == Status) + { + /* Check for the Timeout */ + if ((((HAL_GetTick() - Tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + return HAL_TIMEOUT; + } + } + return HAL_OK; +} + +/** + * @brief Compute configured packet size from fifo perspective. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval Packet size occupied in the fifo + */ +static uint32_t SPI_GetPacketSize(const SPI_HandleTypeDef *hspi) +{ + uint32_t fifo_threashold = (hspi->Init.FifoThreshold >> SPI_CFG1_FTHLV_Pos) + 1UL; + uint32_t data_size = (hspi->Init.DataSize >> SPI_CFG1_DSIZE_Pos) + 1UL; + + /* Convert data size to Byte */ + data_size = (data_size + 7UL) / 8UL; + + return data_size * fifo_threashold; +} + +/** + * @} + */ + +#endif /* HAL_SPI_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_spi_ex.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_spi_ex.c new file mode 100644 index 0000000000..cb78786aaa --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_spi_ex.c @@ -0,0 +1,346 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_spi_ex.c + * @author MCD Application Team + * @brief Extended SPI HAL module driver. + * This file provides firmware functions to manage the following + * SPI peripheral extended functionalities : + * + IO operation functions + * + Peripheral Control functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @defgroup SPIEx SPIEx + * @brief SPI Extended HAL module driver + * @{ + */ +#ifdef HAL_SPI_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup SPIEx_Exported_Functions SPIEx Exported Functions + * @{ + */ + +/** @defgroup SPIEx_Exported_Functions_Group1 IO operation functions + * @brief Data transfers functions + * +@verbatim + ============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of extended functions to manage the SPI + data transfers. + + (#) SPIEx function: + (++) HAL_SPIEx_FlushRxFifo() + (++) HAL_SPIEx_FlushRxFifo() + (++) HAL_SPIEx_EnableLockConfiguration() + (++) HAL_SPIEx_ConfigureUnderrun() + +@endverbatim + * @{ + */ + +/** + * @brief Flush the RX fifo. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(const SPI_HandleTypeDef *hspi) +{ + uint8_t count = 0; + uint32_t itflag = hspi->Instance->SR; + __IO uint32_t tmpreg; + + while (((hspi->Instance->SR & SPI_FLAG_FRLVL) != SPI_RX_FIFO_0PACKET) || ((itflag & SPI_FLAG_RXWNE) != 0UL)) + { + count += (uint8_t)4UL; + tmpreg = hspi->Instance->RXDR; + UNUSED(tmpreg); /* To avoid GCC warning */ + + if (IS_SPI_FULL_INSTANCE(hspi->Instance)) + { + if (count > SPI_HIGHEND_FIFO_SIZE) + { + return HAL_TIMEOUT; + } + } + else + { + if (count > SPI_LOWEND_FIFO_SIZE) + { + return HAL_TIMEOUT; + } + } + } + return HAL_OK; +} + + +/** + * @brief Enable the Lock for the AF configuration of associated IOs + * and write protect the Content of Configuration register 2 + * when SPI is enabled + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +HAL_StatusTypeDef HAL_SPIEx_EnableLockConfiguration(SPI_HandleTypeDef *hspi) +{ + HAL_StatusTypeDef errorcode = HAL_OK; + + /* Process Locked */ + __HAL_LOCK(hspi); + + if (hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + hspi->State = HAL_SPI_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return errorcode; + } + + /* Check if the SPI is disabled to edit IOLOCK bit */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_IOLOCK); + } + else + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + + SET_BIT(hspi->Instance->CR1, SPI_CR1_IOLOCK); + + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + hspi->State = HAL_SPI_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return errorcode; +} + +/** + * @brief Configure the UNDERRUN condition and behavior of slave transmitter. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param UnderrunDetection : Detection of underrun condition at slave transmitter + * This parameter is not supported in this SPI version. + * It is kept in order to not break the compatibility. + * @param UnderrunBehaviour : Behavior of slave transmitter at underrun condition + * This parameter can be a value of @ref SPI_Underrun_Behaviour. + * @retval None + */ +HAL_StatusTypeDef HAL_SPIEx_ConfigureUnderrun(SPI_HandleTypeDef *hspi, uint32_t UnderrunDetection, + uint32_t UnderrunBehaviour) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(UnderrunDetection); + + HAL_StatusTypeDef errorcode = HAL_OK; + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Check State and Insure that Underrun configuration is managed only by Salve */ + if ((hspi->State != HAL_SPI_STATE_READY) || (hspi->Init.Mode != SPI_MODE_SLAVE)) + { + errorcode = HAL_BUSY; + hspi->State = HAL_SPI_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return errorcode; + } + + /* Check the parameters */ + assert_param(IS_SPI_UNDERRUN_BEHAVIOUR(UnderrunBehaviour)); + + /* Check if the SPI is disabled to edit CFG1 register */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Configure Underrun fields */ + MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRCFG, UnderrunBehaviour); + } + else + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + + /* Configure Underrun fields */ + MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRCFG, UnderrunBehaviour); + + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + + hspi->State = HAL_SPI_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return errorcode; +} + +/** + * @brief Set Autonomous Mode configuration + * @param hspi Pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPIx peripheral. + * @param sConfig Pointer to a SPI_HandleTypeDef structure that contains + * the configuration information of the autonomous mode for the specified SPIx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPIEx_SetConfigAutonomousMode(SPI_HandleTypeDef *hspi, + const SPI_AutonomousModeConfTypeDef *sConfig) +{ + if (hspi->State == HAL_SPI_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hspi); + + hspi->State = HAL_SPI_STATE_BUSY; + + /* Check the parameters */ + assert_param(IS_SPI_AUTONOMOUS_INSTANCE(hspi->Instance)); + assert_param(IS_SPI_TRIG_SOURCE(hspi->Instance, sConfig->TriggerSelection)); + assert_param(IS_SPI_AUTO_MODE_TRG_POL(sConfig->TriggerPolarity)); + + /* Disable the selected SPI peripheral to be able to configure AUTOCR */ + __HAL_SPI_DISABLE(hspi); + + /* SPIx AUTOCR Configuration */ + WRITE_REG(hspi->Instance->AUTOCR, (sConfig->TriggerState | ((sConfig->TriggerSelection) & SPI_AUTOCR_TRIGSEL_Msk) | + sConfig->TriggerPolarity)); + + hspi->State = HAL_SPI_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Get Autonomous Mode configuration + * @param hspi Pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPIx peripheral. + * @param sConfig Pointer to a SPI_HandleTypeDef structure that contains + * the configuration information of the autonomous mode for the specified SPIx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPIEx_GetConfigAutonomousMode(const SPI_HandleTypeDef *hspi, + SPI_AutonomousModeConfTypeDef *sConfig) +{ + uint32_t autocr_tmp; + + /* Check the parameters */ + assert_param(IS_SPI_AUTONOMOUS_INSTANCE(hspi->Instance)); + + autocr_tmp = hspi->Instance->AUTOCR; + + sConfig->TriggerState = (autocr_tmp & SPI_AUTOCR_TRIGEN); +#if defined(SPI_TRIG_GRP1) + if (IS_SPI_GRP2_INSTANCE(hspi->Instance)) + { + sConfig->TriggerSelection = ((autocr_tmp & SPI_AUTOCR_TRIGSEL) | SPI_TRIG_GRP2); + } + else + { + sConfig->TriggerSelection = ((autocr_tmp & SPI_AUTOCR_TRIGSEL) | SPI_TRIG_GRP1); + } +#else + sConfig->TriggerSelection = ((autocr_tmp & SPI_AUTOCR_TRIGSEL) | SPI_TRIG_GRP2); +#endif /* SPI_TRIG_GRP1 */ + sConfig->TriggerPolarity = (autocr_tmp & SPI_AUTOCR_TRIGPOL); + + return HAL_OK; +} + +/** + * @brief Clear Autonomous Mode configuration + * @param hspi Pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPIx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPIEx_ClearConfigAutonomousMode(SPI_HandleTypeDef *hspi) +{ + if (hspi->State == HAL_SPI_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hspi); + + hspi->State = HAL_SPI_STATE_BUSY; + + /* Check the parameters */ + assert_param(IS_SPI_AUTONOMOUS_INSTANCE(hspi->Instance)); + + /* Disable the selected SPI peripheral to be able to clear AUTOCR */ + __HAL_SPI_DISABLE(hspi); + + CLEAR_REG(hspi->Instance->AUTOCR); + + /* Enable the selected SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + + hspi->State = HAL_SPI_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_SPI_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_tim.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_tim.c new file mode 100644 index 0000000000..de7fb7c7e7 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_tim.c @@ -0,0 +1,8241 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_tim.c + * @author MCD Application Team + * @brief TIM HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Timer (TIM) peripheral: + * + TIM Time Base Initialization + * + TIM Time Base Start + * + TIM Time Base Start Interruption + * + TIM Time Base Start DMA + * + TIM Output Compare/PWM Initialization + * + TIM Output Compare/PWM Channel Configuration + * + TIM Output Compare/PWM Start + * + TIM Output Compare/PWM Start Interruption + * + TIM Output Compare/PWM Start DMA + * + TIM Input Capture Initialization + * + TIM Input Capture Channel Configuration + * + TIM Input Capture Start + * + TIM Input Capture Start Interruption + * + TIM Input Capture Start DMA + * + TIM One Pulse Initialization + * + TIM One Pulse Channel Configuration + * + TIM One Pulse Start + * + TIM Encoder Interface Initialization + * + TIM Encoder Interface Start + * + TIM Encoder Interface Start Interruption + * + TIM Encoder Interface Start DMA + * + Commutation Event configuration with Interruption and DMA + * + TIM OCRef clear configuration + * + TIM External Clock configuration + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### TIMER Generic features ##### + ============================================================================== + [..] The Timer features include: + (#) 16-bit up, down, up/down auto-reload counter. + (#) 16-bit programmable prescaler allowing dividing (also on the fly) the + counter clock frequency either by any factor between 1 and 65536. + (#) Up to 4 independent channels for: + (++) Input Capture + (++) Output Compare + (++) PWM generation (Edge and Center-aligned Mode) + (++) One-pulse mode output + (#) Synchronization circuit to control the timer with external signals and to interconnect + several timers together. + (#) Supports incremental encoder for positioning purposes + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Initialize the TIM low level resources by implementing the following functions + depending on the selected feature: + (++) Time Base : HAL_TIM_Base_MspInit() + (++) Input Capture : HAL_TIM_IC_MspInit() + (++) Output Compare : HAL_TIM_OC_MspInit() + (++) PWM generation : HAL_TIM_PWM_MspInit() + (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit() + (++) Encoder mode output : HAL_TIM_Encoder_MspInit() + + (#) Initialize the TIM low level resources : + (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); + (##) TIM pins configuration + (+++) Enable the clock for the TIM GPIOs using the following function: + __HAL_RCC_GPIOx_CLK_ENABLE(); + (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); + + (#) The external Clock can be configured, if needed (the default clock is the + internal clock from the APBx), using the following function: + HAL_TIM_ConfigClockSource, the clock configuration should be done before + any start function. + + (#) Configure the TIM in the desired functioning mode using one of the + Initialization function of this driver: + (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base + (++) HAL_TIM_OC_Init, HAL_TIM_OC_ConfigChannel and optionally HAL_TIMEx_OC_ConfigPulseOnCompare: + to use the Timer to generate an Output Compare signal. + (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a + PWM signal. + (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an + external signal. + (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer + in One Pulse Mode. + (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface. + + (#) Activate the TIM peripheral using one of the start functions depending from the feature used: + (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT() + (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT() + (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT() + (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT() + (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT() + (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(). + + (#) The DMA Burst is managed with the two following functions: + HAL_TIM_DMABurst_WriteStart() + HAL_TIM_DMABurst_ReadStart() + + *** Callback registration *** + ============================================= + + [..] + The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + [..] + Use Function HAL_TIM_RegisterCallback() to register a callback. + HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle, + the Callback ID and a pointer to the user callback function. + + [..] + Use function HAL_TIM_UnRegisterCallback() to reset a callback to the default + weak function. + HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + + [..] + These functions allow to register/unregister following callbacks: + (+) Base_MspInitCallback : TIM Base Msp Init Callback. + (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback. + (+) IC_MspInitCallback : TIM IC Msp Init Callback. + (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback. + (+) OC_MspInitCallback : TIM OC Msp Init Callback. + (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback. + (+) PWM_MspInitCallback : TIM PWM Msp Init Callback. + (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback. + (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback. + (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback. + (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback. + (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback. + (+) HallSensor_MspInitCallback : TIM Hall Sensor Msp Init Callback. + (+) HallSensor_MspDeInitCallback : TIM Hall Sensor Msp DeInit Callback. + (+) PeriodElapsedCallback : TIM Period Elapsed Callback. + (+) PeriodElapsedHalfCpltCallback : TIM Period Elapsed half complete Callback. + (+) TriggerCallback : TIM Trigger Callback. + (+) TriggerHalfCpltCallback : TIM Trigger half complete Callback. + (+) IC_CaptureCallback : TIM Input Capture Callback. + (+) IC_CaptureHalfCpltCallback : TIM Input Capture half complete Callback. + (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback. + (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback. + (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback. + (+) ErrorCallback : TIM Error Callback. + (+) CommutationCallback : TIM Commutation Callback. + (+) CommutationHalfCpltCallback : TIM Commutation half complete Callback. + (+) BreakCallback : TIM Break Callback. + (+) Break2Callback : TIM Break2 Callback. + (+) EncoderIndexCallback : TIM Encoder Index Callback. + (+) DirectionChangeCallback : TIM Direction Change Callback + (+) IndexErrorCallback : TIM Index Error Callback. + (+) TransitionErrorCallback : TIM Transition Error Callback + + [..] +By default, after the Init and when the state is HAL_TIM_STATE_RESET +all interrupt callbacks are set to the corresponding weak functions: + examples HAL_TIM_TriggerCallback(), HAL_TIM_ErrorCallback(). + + [..] + Exception done for MspInit and MspDeInit functions that are reset to the legacy weak + functionalities in the Init / DeInit only when these callbacks are null + (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit + keep and use the user MspInit / MspDeInit callbacks(registered beforehand) + + [..] + Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only. + Exception done MspInit / MspDeInit that can be registered / unregistered + in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state, + thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_TIM_RegisterCallback() before calling DeInit or Init function. + + [..] + When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @defgroup TIM TIM + * @brief TIM HAL module driver + * @{ + */ + +#ifdef HAL_TIM_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup TIM_Private_Constants + * @{ + */ +#define TIMx_AF2_OCRSEL TIM_AF2_OCRSEL + +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup TIM_Private_Functions + * @{ + */ +static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); +static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); +static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); +static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); +static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); +static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource); +static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, + const TIM_SlaveConfigTypeDef *sSlaveConfig); +/** + * @} + */ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup TIM_Exported_Functions TIM Exported Functions + * @{ + */ + +/** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions + * @brief Time Base functions + * +@verbatim + ============================================================================== + ##### Time Base functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM base. + (+) De-initialize the TIM base. + (+) Start the Time Base. + (+) Stop the Time Base. + (+) Start the Time Base and enable interrupt. + (+) Stop the Time Base and disable interrupt. + (+) Start the Time Base and enable DMA transfer. + (+) Stop the Time Base and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Time base Unit according to the specified + * parameters in the TIM_HandleTypeDef and initialize the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->Base_MspInitCallback == NULL) + { + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->Base_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + HAL_TIM_Base_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Set the Time Base configuration */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM Base peripheral + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->Base_MspDeInitCallback == NULL) + { + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; + } + /* DeInit the low level hardware */ + htim->Base_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_Base_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Base MSP. + * @param htim TIM Base handle + * @retval None + */ +__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Base_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Base MSP. + * @param htim TIM Base handle + * @retval None + */ +__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Base_MspDeInit could be implemented in the user file + */ +} + + +/** + * @brief Starts the TIM Base generation. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Check the TIM state */ + if (htim->State != HAL_TIM_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Base generation. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Base generation in interrupt mode. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Check the TIM state */ + if (htim->State != HAL_TIM_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Enable the TIM Update interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Base generation in interrupt mode. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Disable the TIM Update interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Base generation in DMA mode. + * @param htim TIM Base handle + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); + + /* Set the TIM state */ + if (htim->State == HAL_TIM_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->State == HAL_TIM_STATE_READY) + { + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + else + { + return HAL_ERROR; + } + + /* Set the DMA Period elapsed callbacks */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable the TIM Update DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Base generation in DMA mode. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); + + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE); + + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions + * @brief TIM Output Compare functions + * +@verbatim + ============================================================================== + ##### TIM Output Compare functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Output Compare. + (+) De-initialize the TIM Output Compare. + (+) Start the TIM Output Compare. + (+) Stop the TIM Output Compare. + (+) Start the TIM Output Compare and enable interrupt. + (+) Stop the TIM Output Compare and disable interrupt. + (+) Start the TIM Output Compare and enable DMA transfer. + (+) Stop the TIM Output Compare and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Output Compare according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init() + * @param htim TIM Output Compare handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->OC_MspInitCallback == NULL) + { + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->OC_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_OC_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Init the base time for the Output Compare */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM peripheral + * @param htim TIM Output Compare handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->OC_MspDeInitCallback == NULL) + { + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; + } + /* DeInit the low level hardware */ + htim->OC_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_OC_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Output Compare MSP. + * @param htim TIM Output Compare handle + * @retval None + */ +__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OC_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Output Compare MSP. + * @param htim TIM Output Compare handle + * @retval None + */ +__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OC_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Output Compare signal generation. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Output Compare signal generation in interrupt mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM Output Compare signal generation in interrupt mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @brief Starts the TIM Output Compare signal generation in DMA mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + + /* Set the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) + { + return HAL_BUSY; + } + else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) + { + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM Output Compare signal generation in DMA mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions + * @brief TIM PWM functions + * +@verbatim + ============================================================================== + ##### TIM PWM functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM PWM. + (+) De-initialize the TIM PWM. + (+) Start the TIM PWM. + (+) Stop the TIM PWM. + (+) Start the TIM PWM and enable interrupt. + (+) Stop the TIM PWM and disable interrupt. + (+) Start the TIM PWM and enable DMA transfer. + (+) Stop the TIM PWM and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM PWM Time Base according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() + * @param htim TIM PWM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->PWM_MspInitCallback == NULL) + { + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->PWM_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_PWM_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Init the base time for the PWM */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM peripheral + * @param htim TIM PWM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->PWM_MspDeInitCallback == NULL) + { + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; + } + /* DeInit the low level hardware */ + htim->PWM_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_PWM_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM PWM MSP. + * @param htim TIM PWM handle + * @retval None + */ +__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM PWM MSP. + * @param htim TIM PWM handle + * @retval None + */ +__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the PWM signal generation. + * @param htim TIM handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the PWM signal generation. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the PWM signal generation in interrupt mode. + * @param htim TIM PWM handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the PWM signal generation in interrupt mode. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @brief Starts the TIM PWM signal generation in DMA mode. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + + /* Set the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) + { + return HAL_BUSY; + } + else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) + { + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Output Capture/Compare 3 request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM PWM signal generation in DMA mode. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions + * @brief TIM Input Capture functions + * +@verbatim + ============================================================================== + ##### TIM Input Capture functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Input Capture. + (+) De-initialize the TIM Input Capture. + (+) Start the TIM Input Capture. + (+) Stop the TIM Input Capture. + (+) Start the TIM Input Capture and enable interrupt. + (+) Stop the TIM Input Capture and disable interrupt. + (+) Start the TIM Input Capture and enable DMA transfer. + (+) Stop the TIM Input Capture and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Input Capture Time base according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init() + * @param htim TIM Input Capture handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->IC_MspInitCallback == NULL) + { + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->IC_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_IC_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Init the base time for the input capture */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM peripheral + * @param htim TIM Input Capture handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->IC_MspDeInitCallback == NULL) + { + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; + } + /* DeInit the low level hardware */ + htim->IC_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_IC_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Input Capture MSP. + * @param htim TIM Input Capture handle + * @retval None + */ +__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Input Capture MSP. + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Input Capture measurement. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); + + /* Check the parameters */ + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Input Capture measurement. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Input Capture measurement in interrupt mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); + + /* Check the parameters */ + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM Input Capture measurement in interrupt mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @brief Starts the TIM Input Capture measurement in DMA mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData The destination Buffer address. + * @param Length The length of data to be transferred from TIM peripheral to memory. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); + + /* Check the parameters */ + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + + /* Set the TIM channel state */ + if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM Input Capture measurement in DMA mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions + * @brief TIM One Pulse functions + * +@verbatim + ============================================================================== + ##### TIM One Pulse functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM One Pulse. + (+) De-initialize the TIM One Pulse. + (+) Start the TIM One Pulse. + (+) Stop the TIM One Pulse. + (+) Start the TIM One Pulse and enable interrupt. + (+) Stop the TIM One Pulse and disable interrupt. + (+) Start the TIM One Pulse and enable DMA transfer. + (+) Stop the TIM One Pulse and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM One Pulse Time Base according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init() + * @note When the timer instance is initialized in One Pulse mode, timer + * channels 1 and channel 2 are reserved and cannot be used for other + * purpose. + * @param htim TIM One Pulse handle + * @param OnePulseMode Select the One pulse mode. + * This parameter can be one of the following values: + * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated. + * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_OPM_MODE(OnePulseMode)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->OnePulse_MspInitCallback == NULL) + { + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->OnePulse_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_OnePulse_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Configure the Time base in the One Pulse Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Reset the OPM Bit */ + htim->Instance->CR1 &= ~TIM_CR1_OPM; + + /* Configure the OPM Mode */ + htim->Instance->CR1 |= OnePulseMode; + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM One Pulse + * @param htim TIM One Pulse handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->OnePulse_MspDeInitCallback == NULL) + { + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; + } + /* DeInit the low level hardware */ + htim->OnePulse_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_OnePulse_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM One Pulse MSP. + * @param htim TIM One Pulse handle + * @retval None + */ +__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OnePulse_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM One Pulse MSP. + * @param htim TIM One Pulse handle + * @retval None + */ +__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM One Pulse signal generation. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel See note above + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together + + No need to enable the counter, it's enabled automatically by hardware + (the counter starts in response to a stimulus and generate a pulse */ + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel See note above + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Disable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM One Pulse signal generation in interrupt mode. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel See note above + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together + + No need to enable the counter, it's enabled automatically by hardware + (the counter starts in response to a stimulus and generate a pulse */ + + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation in interrupt mode. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel See note above + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + + /* Disable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions + * @brief TIM Encoder functions + * +@verbatim + ============================================================================== + ##### TIM Encoder functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Encoder. + (+) De-initialize the TIM Encoder. + (+) Start the TIM Encoder. + (+) Stop the TIM Encoder. + (+) Start the TIM Encoder and enable interrupt. + (+) Stop the TIM Encoder and disable interrupt. + (+) Start the TIM Encoder and enable DMA transfer. + (+) Stop the TIM Encoder and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Encoder Interface and initialize the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init() + * @note Encoder mode and External clock mode 2 are not compatible and must not be selected together + * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource + * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa + * @note When the timer instance is initialized in Encoder mode, timer + * channels 1 and channel 2 are reserved and cannot be used for other + * purpose. + * @param htim TIM Encoder Interface handle + * @param sConfig TIM Encoder Interface configuration structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig) +{ + uint32_t tmpsmcr; + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode)); + assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection)); + assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection)); + assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity)); + assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->Encoder_MspInitCallback == NULL) + { + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->Encoder_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_Encoder_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Reset the SMS and ECE bits */ + htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE); + + /* Configure the Time base in the Encoder Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = htim->Instance->CCMR1; + + /* Get the TIMx CCER register value */ + tmpccer = htim->Instance->CCER; + + /* Set the encoder Mode */ + tmpsmcr |= sConfig->EncoderMode; + + /* Select the Capture Compare 1 and the Capture Compare 2 as input */ + tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); + tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U)); + + /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ + tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); + tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); + tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U); + tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U); + + /* Set the TI1 and the TI2 Polarities */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); + tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP); + tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U); + + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + + /* Write to TIMx CCMR1 */ + htim->Instance->CCMR1 = tmpccmr1; + + /* Write to TIMx CCER */ + htim->Instance->CCER = tmpccer; + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + + +/** + * @brief DeInitializes the TIM Encoder interface + * @param htim TIM Encoder Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->Encoder_MspDeInitCallback == NULL) + { + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; + } + /* DeInit the low level hardware */ + htim->Encoder_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_Encoder_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Encoder Interface MSP. + * @param htim TIM Encoder Interface handle + * @retval None + */ +__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Encoder_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Encoder Interface MSP. + * @param htim TIM Encoder Interface handle + * @retval None + */ +__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Encoder_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Encoder Interface. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Set the TIM channel(s) state */ + if (Channel == TIM_CHANNEL_1) + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else if (Channel == TIM_CHANNEL_2) + { + if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + + /* Enable the encoder interface channels */ + switch (Channel) + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + break; + } + + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + break; + } + + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + break; + } + } + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Encoder Interface. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1 and 2 + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + switch (Channel) + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + break; + } + + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + break; + } + + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + break; + } + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel(s) state */ + if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Encoder Interface in interrupt mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Set the TIM channel(s) state */ + if (Channel == TIM_CHANNEL_1) + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else if (Channel == TIM_CHANNEL_2) + { + if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + + /* Enable the encoder interface channels */ + /* Enable the capture compare Interrupts 1 and/or 2 */ + switch (Channel) + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + } + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Encoder Interface in interrupt mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1 and 2 + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + if (Channel == TIM_CHANNEL_1) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts 1 */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + } + else if (Channel == TIM_CHANNEL_2) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts 2 */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + } + else + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts 1 and 2 */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel(s) state */ + if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Encoder Interface in DMA mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @param pData1 The destination Buffer address for IC1. + * @param pData2 The destination Buffer address for IC2. + * @param Length The length of data to be transferred from TIM peripheral to memory. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, + uint32_t *pData2, uint16_t Length) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Set the TIM channel(s) state */ + if (Channel == TIM_CHANNEL_1) + { + if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData1 == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + } + else if (Channel == TIM_CHANNEL_2) + { + if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData2 == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + } + else + { + if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((((pData1 == NULL) || (pData2 == NULL))) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + break; + } + + default: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + break; + } + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Encoder Interface in DMA mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1 and 2 + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + if (Channel == TIM_CHANNEL_1) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the capture compare DMA Request 1 */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + } + else if (Channel == TIM_CHANNEL_2) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare DMA Request 2 */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + } + else + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare DMA Request 1 and 2 */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel(s) state */ + if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ +/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management + * @brief TIM IRQ handler management + * +@verbatim + ============================================================================== + ##### IRQ handler management ##### + ============================================================================== + [..] + This section provides Timer IRQ handler function. + +@endverbatim + * @{ + */ +/** + * @brief This function handles TIM interrupts requests. + * @param htim TIM handle + * @retval None + */ +void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) +{ + uint32_t itsource = htim->Instance->DIER; + uint32_t itflag = htim->Instance->SR; + + /* Capture compare 1 event */ + if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1)) + { + if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1)) + { + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + /* Input capture event */ + if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + } + /* Capture compare 2 event */ + if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2)) + { + if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2)) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + /* Input capture event */ + if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* Capture compare 3 event */ + if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3)) + { + if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3)) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + /* Input capture event */ + if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* Capture compare 4 event */ + if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4)) + { + if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4)) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + /* Input capture event */ + if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* TIM Update event */ + if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE)) + { + if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE)) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedCallback(htim); +#else + HAL_TIM_PeriodElapsedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Break input event */ + if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \ + ((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK))) + { + if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->BreakCallback(htim); +#else + HAL_TIMEx_BreakCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Break2 input event */ + if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2)) + { + if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->Break2Callback(htim); +#else + HAL_TIMEx_Break2Callback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Trigger detection event */ + if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER)) + { + if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER)) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerCallback(htim); +#else + HAL_TIM_TriggerCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM commutation event */ + if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM)) + { + if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM)) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->CommutationCallback(htim); +#else + HAL_TIMEx_CommutCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Encoder index event */ + if ((itflag & (TIM_FLAG_IDX)) == (TIM_FLAG_IDX)) + { + if ((itsource & (TIM_IT_IDX)) == (TIM_IT_IDX)) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_IDX); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->EncoderIndexCallback(htim); +#else + HAL_TIMEx_EncoderIndexCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Direction change event */ + if ((itflag & (TIM_FLAG_DIR)) == (TIM_FLAG_DIR)) + { + if ((itsource & (TIM_IT_DIR)) == (TIM_IT_DIR)) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_DIR); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->DirectionChangeCallback(htim); +#else + HAL_TIMEx_DirectionChangeCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Index error event */ + if ((itflag & (TIM_FLAG_IERR)) == (TIM_FLAG_IERR)) + { + if ((itsource & (TIM_IT_IERR)) == (TIM_IT_IERR)) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_IERR); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IndexErrorCallback(htim); +#else + HAL_TIMEx_IndexErrorCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Transition error event */ + if ((itflag & (TIM_FLAG_TERR)) == (TIM_FLAG_TERR)) + { + if ((itsource & (TIM_IT_TERR)) == (TIM_IT_TERR)) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TERR); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TransitionErrorCallback(htim); +#else + HAL_TIMEx_TransitionErrorCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions + * @brief TIM Peripheral Control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. + (+) Configure External Clock source. + (+) Configure Complementary channels, break features and dead time. + (+) Configure Master and the Slave synchronization. + (+) Configure the DMA Burst Mode. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the TIM Output Compare Channels according to the specified + * parameters in the TIM_OC_InitTypeDef. + * @param htim TIM Output Compare handle + * @param sConfig TIM Output Compare configuration structure + * @param Channel TIM Channels to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, + const TIM_OC_InitTypeDef *sConfig, + uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CHANNELS(Channel)); + assert_param(IS_TIM_OC_CHANNEL_MODE(sConfig->OCMode, Channel)); + assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); + + /* Process Locked */ + __HAL_LOCK(htim); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 1 in Output Compare */ + TIM_OC1_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 2 in Output Compare */ + TIM_OC2_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_3: + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 3 in Output Compare */ + TIM_OC3_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_4: + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 4 in Output Compare */ + TIM_OC4_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_5: + { + /* Check the parameters */ + assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 5 in Output Compare */ + TIM_OC5_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_6: + { + /* Check the parameters */ + assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 6 in Output Compare */ + TIM_OC6_SetConfig(htim->Instance, sConfig); + break; + } + + default: + status = HAL_ERROR; + break; + } + + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Initializes the TIM Input Capture Channels according to the specified + * parameters in the TIM_IC_InitTypeDef. + * @param htim TIM IC handle + * @param sConfig TIM Input Capture configuration structure + * @param Channel TIM Channel to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity)); + assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter)); + + /* Process Locked */ + __HAL_LOCK(htim); + + if (Channel == TIM_CHANNEL_1) + { + /* TI1 Configuration */ + TIM_TI1_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + + /* Set the IC1PSC value */ + htim->Instance->CCMR1 |= sConfig->ICPrescaler; + } + else if (Channel == TIM_CHANNEL_2) + { + /* TI2 Configuration */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + TIM_TI2_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC2PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; + + /* Set the IC2PSC value */ + htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U); + } + else if (Channel == TIM_CHANNEL_3) + { + /* TI3 Configuration */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + TIM_TI3_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC3PSC Bits */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC; + + /* Set the IC3PSC value */ + htim->Instance->CCMR2 |= sConfig->ICPrescaler; + } + else if (Channel == TIM_CHANNEL_4) + { + /* TI4 Configuration */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + TIM_TI4_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC4PSC Bits */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC; + + /* Set the IC4PSC value */ + htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U); + } + else + { + status = HAL_ERROR; + } + + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Initializes the TIM PWM channels according to the specified + * parameters in the TIM_OC_InitTypeDef. + * @param htim TIM PWM handle + * @param sConfig TIM PWM configuration structure + * @param Channel TIM Channels to be configured + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, + const TIM_OC_InitTypeDef *sConfig, + uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CHANNELS(Channel)); + assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); + assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); + assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); + + /* Process Locked */ + __HAL_LOCK(htim); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Configure the Channel 1 in PWM mode */ + TIM_OC1_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel1 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; + htim->Instance->CCMR1 |= sConfig->OCFastMode; + break; + } + + case TIM_CHANNEL_2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Configure the Channel 2 in PWM mode */ + TIM_OC2_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel2 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; + htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; + break; + } + + case TIM_CHANNEL_3: + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Configure the Channel 3 in PWM mode */ + TIM_OC3_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel3 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; + htim->Instance->CCMR2 |= sConfig->OCFastMode; + break; + } + + case TIM_CHANNEL_4: + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Configure the Channel 4 in PWM mode */ + TIM_OC4_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel4 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; + htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; + break; + } + + case TIM_CHANNEL_5: + { + /* Check the parameters */ + assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); + + /* Configure the Channel 5 in PWM mode */ + TIM_OC5_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel5*/ + htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE; + htim->Instance->CCMR3 |= sConfig->OCFastMode; + break; + } + + case TIM_CHANNEL_6: + { + /* Check the parameters */ + assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); + + /* Configure the Channel 6 in PWM mode */ + TIM_OC6_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel6 */ + htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE; + htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U; + break; + } + + default: + status = HAL_ERROR; + break; + } + + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Initializes the TIM One Pulse Channels according to the specified + * parameters in the TIM_OnePulse_InitTypeDef. + * @param htim TIM One Pulse handle + * @param sConfig TIM One Pulse configuration structure + * @param OutputChannel TIM output channel to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @param InputChannel TIM input Channel to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @note To output a waveform with a minimum delay user can enable the fast + * mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx + * output is forced in response to the edge detection on TIx input, + * without taking in account the comparison. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, + uint32_t OutputChannel, uint32_t InputChannel) +{ + HAL_StatusTypeDef status = HAL_OK; + TIM_OC_InitTypeDef temp1; + + /* Check the parameters */ + assert_param(IS_TIM_OPM_CHANNELS(OutputChannel)); + assert_param(IS_TIM_OPM_CHANNELS(InputChannel)); + + if (OutputChannel != InputChannel) + { + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Extract the Output compare configuration from sConfig structure */ + temp1.OCMode = sConfig->OCMode; + temp1.Pulse = sConfig->Pulse; + temp1.OCPolarity = sConfig->OCPolarity; + temp1.OCNPolarity = sConfig->OCNPolarity; + temp1.OCIdleState = sConfig->OCIdleState; + temp1.OCNIdleState = sConfig->OCNIdleState; + + switch (OutputChannel) + { + case TIM_CHANNEL_1: + { + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + TIM_OC1_SetConfig(htim->Instance, &temp1); + break; + } + + case TIM_CHANNEL_2: + { + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + TIM_OC2_SetConfig(htim->Instance, &temp1); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + switch (InputChannel) + { + case TIM_CHANNEL_1: + { + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, + sConfig->ICSelection, sConfig->ICFilter); + + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + + /* Select the Trigger source */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI1FP1; + + /* Select the Slave Mode */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + break; + } + + case TIM_CHANNEL_2: + { + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, + sConfig->ICSelection, sConfig->ICFilter); + + /* Reset the IC2PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; + + /* Select the Trigger source */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI2FP2; + + /* Select the Slave Mode */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + break; + } + + default: + status = HAL_ERROR; + break; + } + } + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return status; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @arg TIM_DMABASE_CCMR3 + * @arg TIM_DMABASE_CCR5 + * @arg TIM_DMABASE_CCR6 + * @arg TIM_DMABASE_DTR2 + * @arg TIM_DMABASE_ECR + * @arg TIM_DMABASE_TISEL + * @arg TIM_DMABASE_AF1 + * @arg TIM_DMABASE_AF2 + * @arg TIM_DMABASE_OR + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER. + * @note This function should be used only when BurstLength is equal to DMA data transfer length. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, + uint32_t BurstLength) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t BlockDataLength = 0; + uint32_t data_width; + const DMA_HandleTypeDef *hdma = NULL; + + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + hdma = htim->hdma[TIM_DMA_ID_UPDATE]; + break; + } + case TIM_DMA_CC1: + { + hdma = htim->hdma[TIM_DMA_ID_CC1]; + break; + } + case TIM_DMA_CC2: + { + hdma = htim->hdma[TIM_DMA_ID_CC2]; + break; + } + case TIM_DMA_CC3: + { + hdma = htim->hdma[TIM_DMA_ID_CC3]; + break; + } + case TIM_DMA_CC4: + { + hdma = htim->hdma[TIM_DMA_ID_CC4]; + break; + } + case TIM_DMA_COM: + { + hdma = htim->hdma[TIM_DMA_ID_COMMUTATION]; + break; + } + case TIM_DMA_TRIGGER: + { + hdma = htim->hdma[TIM_DMA_ID_TRIGGER]; + break; + } + default: + status = HAL_ERROR; + break; + } + + if (hdma != NULL) + { + + if (((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) && (hdma->LinkedListQueue != 0U) + && (hdma->LinkedListQueue->Head != 0U)) + { + data_width = hdma->LinkedListQueue->Head->LinkRegisters[0] & DMA_CTR1_SDW_LOG2; + } + else + { + data_width = hdma->Init.SrcDataWidth; + } + + switch (data_width) + { + case DMA_SRC_DATAWIDTH_BYTE: + { + BlockDataLength = (BurstLength >> TIM_DCR_DBL_Pos) + 1UL; + break; + } + case DMA_SRC_DATAWIDTH_HALFWORD: + { + BlockDataLength = ((BurstLength >> TIM_DCR_DBL_Pos) + 1UL) * 2UL; + break; + } + case DMA_SRC_DATAWIDTH_WORD: + { + BlockDataLength = ((BurstLength >> TIM_DCR_DBL_Pos) + 1UL) * 4UL; + break; + } + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, + BlockDataLength); + } + } + + + return status; +} + +/** + * @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @arg TIM_DMABASE_CCMR3 + * @arg TIM_DMABASE_CCR5 + * @arg TIM_DMABASE_CCR6 + * @arg TIM_DMABASE_DTR2 + * @arg TIM_DMABASE_ECR + * @arg TIM_DMABASE_TISEL + * @arg TIM_DMABASE_AF1 + * @arg TIM_DMABASE_AF2 + * @arg TIM_DMABASE_OR + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER. + * @param DataLength Data length. This parameter can be one value + * between 1 and 0xFFFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpDBSS = 0; + + /* Check the parameters */ + assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); + assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + assert_param(IS_TIM_DMA_LENGTH(BurstLength)); + assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); + + if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) + { + if ((BurstBuffer == NULL) && (BurstLength > 0U)) + { + return HAL_ERROR; + } + else + { + htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; + } + } + else + { + /* nothing to do */ + } + + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + /* Set the DMA Period elapsed callbacks */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Configure the DMA Burst Source Selection */ + tmpDBSS = TIM_DCR_DBSS_0; + break; + } + case TIM_DMA_CC1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Configure the DMA Burst Source Selection */ + tmpDBSS = TIM_DCR_DBSS_1; + break; + } + case TIM_DMA_CC2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Configure the DMA Burst Source Selection */ + tmpDBSS = (TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0); + break; + } + case TIM_DMA_CC3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Configure the DMA Burst Source Selection */ + tmpDBSS = TIM_DCR_DBSS_2; + break; + } + case TIM_DMA_CC4: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Configure the DMA Burst Source Selection */ + tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_0); + break; + } + case TIM_DMA_COM: + { + /* Set the DMA commutation callbacks */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Configure the DMA Burst Source Selection */ + tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1); + break; + } + case TIM_DMA_TRIGGER: + { + /* Set the DMA trigger callbacks */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; + htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Configure the DMA Burst Source Selection */ + tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0); + break; + } + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Configure the DMA Burst Mode */ + htim->Instance->DCR = (BurstBaseAddress | BurstLength | tmpDBSS); + /* Enable the TIM DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM DMA Burst mode + * @param htim TIM handle + * @param BurstRequestSrc TIM DMA Request sources to disable + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + + /* Abort the DMA transfer (at least disable the DMA channel) */ + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + break; + } + case TIM_DMA_CC1: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + case TIM_DMA_CC2: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + case TIM_DMA_CC3: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + case TIM_DMA_CC4: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + case TIM_DMA_COM: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); + break; + } + case TIM_DMA_TRIGGER: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); + break; + } + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + } + + /* Return function status */ + return status; +} + +/** + * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @arg TIM_DMABASE_CCMR3 + * @arg TIM_DMABASE_CCR5 + * @arg TIM_DMABASE_CCR6 + * @arg TIM_DMABASE_DTR2 + * @arg TIM_DMABASE_ECR + * @arg TIM_DMABASE_TISEL + * @arg TIM_DMABASE_AF1 + * @arg TIM_DMABASE_AF2 + * @arg TIM_DMABASE_OR + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER. + * @note This function should be used only when BurstLength is equal to DMA data transfer length. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t BlockDataLength = 0; + uint32_t data_width; + const DMA_HandleTypeDef *hdma = NULL; + + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + hdma = htim->hdma[TIM_DMA_ID_UPDATE]; + break; + } + case TIM_DMA_CC1: + { + hdma = htim->hdma[TIM_DMA_ID_CC1]; + break; + } + case TIM_DMA_CC2: + { + hdma = htim->hdma[TIM_DMA_ID_CC2]; + break; + } + case TIM_DMA_CC3: + { + hdma = htim->hdma[TIM_DMA_ID_CC3]; + break; + } + case TIM_DMA_CC4: + { + hdma = htim->hdma[TIM_DMA_ID_CC4]; + break; + } + case TIM_DMA_COM: + { + hdma = htim->hdma[TIM_DMA_ID_COMMUTATION]; + break; + } + case TIM_DMA_TRIGGER: + { + hdma = htim->hdma[TIM_DMA_ID_TRIGGER]; + break; + } + default: + status = HAL_ERROR; + break; + } + + if (hdma != NULL) + { + + if (((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) && (hdma->LinkedListQueue != 0U) + && (hdma->LinkedListQueue->Head != 0U)) + { + data_width = hdma->LinkedListQueue->Head->LinkRegisters[0] & DMA_CTR1_SDW_LOG2; + } + else + { + data_width = hdma->Init.SrcDataWidth; + } + + switch (data_width) + + { + case DMA_SRC_DATAWIDTH_BYTE: + { + BlockDataLength = ((BurstLength) >> TIM_DCR_DBL_Pos) + 1UL; + break; + } + case DMA_SRC_DATAWIDTH_HALFWORD: + { + BlockDataLength = ((BurstLength >> TIM_DCR_DBL_Pos) + 1UL) * 2UL; + break; + } + case DMA_SRC_DATAWIDTH_WORD: + { + BlockDataLength = ((BurstLength >> TIM_DCR_DBL_Pos) + 1UL) * 4UL; + break; + } + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, + BlockDataLength); + } + } + + return status; +} + +/** + * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @arg TIM_DMABASE_CCMR3 + * @arg TIM_DMABASE_CCR5 + * @arg TIM_DMABASE_CCR6 + * @arg TIM_DMABASE_DTR2 + * @arg TIM_DMABASE_ECR + * @arg TIM_DMABASE_TISEL + * @arg TIM_DMABASE_AF1 + * @arg TIM_DMABASE_AF2 + * @arg TIM_DMABASE_OR + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER. + * @param DataLength Data length. This parameter can be one value + * between 1 and 0xFFFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpDBSS = 0; + + /* Check the parameters */ + assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); + assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + assert_param(IS_TIM_DMA_LENGTH(BurstLength)); + assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); + + if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) + { + if ((BurstBuffer == NULL) && (BurstLength > 0U)) + { + return HAL_ERROR; + } + else + { + htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; + } + } + else + { + /* nothing to do */ + } + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + /* Set the DMA Period elapsed callbacks */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Configure the DMA Burst Source Selection */ + tmpDBSS = TIM_DCR_DBSS_0; + break; + } + case TIM_DMA_CC1: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Configure the DMA Burst Source Selection */ + tmpDBSS = TIM_DCR_DBSS_1; + break; + } + case TIM_DMA_CC2: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Configure the DMA Burst Source Selection */ + tmpDBSS = (TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0); + break; + } + case TIM_DMA_CC3: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Configure the DMA Burst Source Selection */ + tmpDBSS = TIM_DCR_DBSS_2; + break; + } + case TIM_DMA_CC4: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Configure the DMA Burst Source Selection */ + tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_0); + break; + } + case TIM_DMA_COM: + { + /* Set the DMA commutation callbacks */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Configure the DMA Burst Source Selection */ + tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1); + break; + } + case TIM_DMA_TRIGGER: + { + /* Set the DMA trigger callbacks */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; + htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Configure the DMA Burst Source Selection */ + tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0); + break; + } + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Configure the DMA Burst Mode */ + htim->Instance->DCR = (BurstBaseAddress | BurstLength | tmpDBSS); + + /* Enable the TIM DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); + } + + /* Return function status */ + return status; +} + +/** + * @brief Stop the DMA burst reading + * @param htim TIM handle + * @param BurstRequestSrc TIM DMA Request sources to disable. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + + /* Abort the DMA transfer (at least disable the DMA channel) */ + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + break; + } + case TIM_DMA_CC1: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + case TIM_DMA_CC2: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + case TIM_DMA_CC3: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + case TIM_DMA_CC4: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + case TIM_DMA_COM: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); + break; + } + case TIM_DMA_TRIGGER: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); + break; + } + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + } + + /* Return function status */ + return status; +} + +/** + * @brief Generate a software event + * @param htim TIM handle + * @param EventSource specifies the event source. + * This parameter can be one of the following values: + * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source + * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source + * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source + * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source + * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source + * @arg TIM_EVENTSOURCE_COM: Timer COM event source + * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source + * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source + * @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source + * @note Basic timers can only generate an update event. + * @note TIM_EVENTSOURCE_COM is relevant only with advanced timer instances. + * @note TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are relevant + * only for timer instances supporting break input(s). + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_EVENT_SOURCE(EventSource)); + + /* Process Locked */ + __HAL_LOCK(htim); + + /* Change the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Set the event sources */ + htim->Instance->EGR = EventSource; + + /* Change the TIM state */ + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Configures the OCRef clear feature + * @param htim TIM handle + * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that + * contains the OCREF clear feature and parameters for the TIM peripheral. + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @arg TIM_CHANNEL_5: TIM Channel 5 + * @arg TIM_CHANNEL_6: TIM Channel 6 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, + const TIM_ClearInputConfigTypeDef *sClearInputConfig, + uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource)); + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + switch (sClearInputConfig->ClearInputSource) + { + case TIM_CLEARINPUTSOURCE_NONE: + { + /* Clear the OCREF clear selection bit and the the ETR Bits */ + CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_OCCS | TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP)); + break; + } + + case TIM_CLEARINPUTSOURCE_COMP1: + case TIM_CLEARINPUTSOURCE_COMP2: + { + /* Clear the OCREF clear selection bit */ + CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS); + + /* Set the clear input source */ + MODIFY_REG(htim->Instance->AF2, TIMx_AF2_OCRSEL, sClearInputConfig->ClearInputSource); + break; + } + + case TIM_CLEARINPUTSOURCE_ETR: + { + /* Check the parameters */ + assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity)); + assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler)); + assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter)); + + /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */ + if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1) + { + htim->State = HAL_TIM_STATE_READY; + __HAL_UNLOCK(htim); + return HAL_ERROR; + } + + TIM_ETR_SetConfig(htim->Instance, + sClearInputConfig->ClearInputPrescaler, + sClearInputConfig->ClearInputPolarity, + sClearInputConfig->ClearInputFilter); + + /* Set the OCREF clear selection bit */ + SET_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + switch (Channel) + { + case TIM_CHANNEL_1: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 1 */ + SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); + } + else + { + /* Disable the OCREF clear feature for Channel 1 */ + CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); + } + break; + } + case TIM_CHANNEL_2: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 2 */ + SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); + } + else + { + /* Disable the OCREF clear feature for Channel 2 */ + CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); + } + break; + } + case TIM_CHANNEL_3: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 3 */ + SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); + } + else + { + /* Disable the OCREF clear feature for Channel 3 */ + CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); + } + break; + } + case TIM_CHANNEL_4: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 4 */ + SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); + } + else + { + /* Disable the OCREF clear feature for Channel 4 */ + CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); + } + break; + } + case TIM_CHANNEL_5: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 5 */ + SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE); + } + else + { + /* Disable the OCREF clear feature for Channel 5 */ + CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE); + } + break; + } + case TIM_CHANNEL_6: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 6 */ + SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE); + } + else + { + /* Disable the OCREF clear feature for Channel 6 */ + CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE); + } + break; + } + default: + break; + } + } + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Configures the clock source to be used + * @param htim TIM handle + * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that + * contains the clock source information for the TIM peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Check the parameters */ + assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); + + /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ + tmpsmcr = htim->Instance->SMCR; + tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + htim->Instance->SMCR = tmpsmcr; + + switch (sClockSourceConfig->ClockSource) + { + case TIM_CLOCKSOURCE_INTERNAL: + { + assert_param(IS_TIM_INSTANCE(htim->Instance)); + break; + } + + case TIM_CLOCKSOURCE_ETRMODE1: + { + /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/ + assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); + + /* Check ETR input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + /* Configure the ETR Clock source */ + TIM_ETR_SetConfig(htim->Instance, + sClockSourceConfig->ClockPrescaler, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + + /* Select the External clock mode1 and the ETRF trigger */ + tmpsmcr = htim->Instance->SMCR; + tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + break; + } + + case TIM_CLOCKSOURCE_ETRMODE2: + { + /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/ + assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance)); + + /* Check ETR input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + /* Configure the ETR Clock source */ + TIM_ETR_SetConfig(htim->Instance, + sClockSourceConfig->ClockPrescaler, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + /* Enable the External clock mode2 */ + htim->Instance->SMCR |= TIM_SMCR_ECE; + break; + } + + case TIM_CLOCKSOURCE_TI1: + { + /* Check whether or not the timer instance supports external clock mode 1 */ + assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + + /* Check TI1 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI1_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); + break; + } + + case TIM_CLOCKSOURCE_TI2: + { + /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/ + assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + + /* Check TI2 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI2_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); + break; + } + + case TIM_CLOCKSOURCE_TI1ED: + { + /* Check whether or not the timer instance supports external clock mode 1 */ + assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + + /* Check TI1 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI1_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); + break; + } + + case TIM_CLOCKSOURCE_ITR0: + case TIM_CLOCKSOURCE_ITR1: + case TIM_CLOCKSOURCE_ITR2: + case TIM_CLOCKSOURCE_ITR7: + case TIM_CLOCKSOURCE_ITR8: + { + /* Check whether or not the timer instance supports internal trigger input */ + assert_param(IS_TIM_CLOCKSOURCE_INSTANCE((htim->Instance), sClockSourceConfig->ClockSource)); + + TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); + break; + } + + default: + status = HAL_ERROR; + break; + } + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Selects the signal connected to the TI1 input: direct from CH1_input + * or a XOR combination between CH1_input, CH2_input & CH3_input + * @param htim TIM handle. + * @param TI1_Selection Indicate whether or not channel 1 is connected to the + * output of a XOR gate. + * This parameter can be one of the following values: + * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input + * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3 + * pins are connected to the TI1 input (XOR combination) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection) +{ + uint32_t tmpcr2; + + /* Check the parameters */ + assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TI1SELECTION(TI1_Selection)); + + /* Get the TIMx CR2 register value */ + tmpcr2 = htim->Instance->CR2; + + /* Reset the TI1 selection */ + tmpcr2 &= ~TIM_CR2_TI1S; + + /* Set the TI1 selection */ + tmpcr2 |= TI1_Selection; + + /* Write to TIMxCR2 */ + htim->Instance->CR2 = tmpcr2; + + return HAL_OK; +} + +/** + * @brief Configures the TIM in Slave mode + * @param htim TIM handle. + * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that + * contains the selected trigger (internal trigger input, filtered + * timer input or external trigger input) and the Slave mode + * (Disable, Reset, Gated, Trigger, External clock mode 1, Reset + Trigger, Gated + Reset). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig) +{ + /* Check the parameters */ + assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); + assert_param(IS_TIM_TRIGGER_INSTANCE(htim->Instance, sSlaveConfig->InputTrigger)); + + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) + { + htim->State = HAL_TIM_STATE_READY; + __HAL_UNLOCK(htim); + return HAL_ERROR; + } + + /* Disable Trigger Interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER); + + /* Disable Trigger DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the TIM in Slave mode in interrupt mode + * @param htim TIM handle. + * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that + * contains the selected trigger (internal trigger input, filtered + * timer input or external trigger input) and the Slave mode + * (Disable, Reset, Gated, Trigger, External clock mode 1, Reset + Trigger, Gated + Reset). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, + const TIM_SlaveConfigTypeDef *sSlaveConfig) +{ + /* Check the parameters */ + assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); + assert_param(IS_TIM_TRIGGER_INSTANCE(htim->Instance, sSlaveConfig->InputTrigger)); + + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) + { + htim->State = HAL_TIM_STATE_READY; + __HAL_UNLOCK(htim); + return HAL_ERROR; + } + + /* Enable Trigger Interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER); + + /* Disable Trigger DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Read the captured value from Capture Compare unit + * @param htim TIM handle. + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval Captured value + */ +uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpreg = 0U; + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Return the capture 1 value */ + tmpreg = htim->Instance->CCR1; + + break; + } + case TIM_CHANNEL_2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Return the capture 2 value */ + tmpreg = htim->Instance->CCR2; + + break; + } + + case TIM_CHANNEL_3: + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Return the capture 3 value */ + tmpreg = htim->Instance->CCR3; + + break; + } + + case TIM_CHANNEL_4: + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Return the capture 4 value */ + tmpreg = htim->Instance->CCR4; + + break; + } + + default: + break; + } + + return tmpreg; +} + +/** + * @brief Start the DMA data transfer. + * @param hdma DMA handle + * @param src : The source memory Buffer address. + * @param dst : The destination memory Buffer address. + * @param length : The size of a source block transfer in byte. + * @retval HAL status + */ +HAL_StatusTypeDef TIM_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t src, uint32_t dst, + uint32_t length) +{ + HAL_StatusTypeDef status ; + + /* Enable the DMA channel */ + if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if ((hdma->LinkedListQueue != 0U) && (hdma->LinkedListQueue->Head != 0U)) + { + /* Enable the DMA channel */ + hdma->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = length; + hdma->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = src; + hdma->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = dst; + + status = HAL_DMAEx_List_Start_IT(hdma); + } + else + { + status = HAL_ERROR; + } + } + else + { + status = HAL_DMA_Start_IT(hdma, src, dst, length); + } + + return status; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions + * @brief TIM Callbacks functions + * +@verbatim + ============================================================================== + ##### TIM Callbacks functions ##### + ============================================================================== + [..] + This section provides TIM callback functions: + (+) TIM Period elapsed callback + (+) TIM Output Compare callback + (+) TIM Input capture callback + (+) TIM Trigger callback + (+) TIM Error callback + (+) TIM Index callback + (+) TIM Direction change callback + (+) TIM Index error callback + (+) TIM Transition error callback + +@endverbatim + * @{ + */ + +/** + * @brief Period elapsed callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PeriodElapsedCallback could be implemented in the user file + */ +} + +/** + * @brief Period elapsed half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Output Compare callback in non-blocking mode + * @param htim TIM OC handle + * @retval None + */ +__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file + */ +} + +/** + * @brief Input Capture callback in non-blocking mode + * @param htim TIM IC handle + * @retval None + */ +__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_CaptureCallback could be implemented in the user file + */ +} + +/** + * @brief Input Capture half complete callback in non-blocking mode + * @param htim TIM IC handle + * @retval None + */ +__weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief PWM Pulse finished callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file + */ +} + +/** + * @brief PWM Pulse finished half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Hall Trigger detection callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_TriggerCallback could be implemented in the user file + */ +} + +/** + * @brief Hall Trigger detection half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Timer error callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_ErrorCallback could be implemented in the user file + */ +} + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User TIM callback to be used instead of the weak predefined callback + * @param htim tim handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID + * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID + * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID + * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID + * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID + * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID + * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID + * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID + * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID + * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID + * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID + * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID + * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID + * @arg @ref HAL_TIM_ENCODER_INDEX_CB_ID Encoder Index Callback ID + * @arg @ref HAL_TIM_DIRECTION_CHANGE_CB_ID Direction Change Callback ID + * @arg @ref HAL_TIM_INDEX_ERROR_CB_ID Index Error Callback ID + * @arg @ref HAL_TIM_TRANSITION_ERROR_CB_ID Transition Error Callback ID + * @param pCallback pointer to the callback function + * @retval status + */ +HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, + pTIM_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + return HAL_ERROR; + } + + if (htim->State == HAL_TIM_STATE_READY) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + htim->Base_MspInitCallback = pCallback; + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + htim->Base_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + htim->IC_MspInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + htim->IC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + htim->OC_MspInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + htim->OC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + htim->PWM_MspInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + htim->PWM_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + htim->OnePulse_MspInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + htim->OnePulse_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + htim->Encoder_MspInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + htim->Encoder_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + htim->HallSensor_MspInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + htim->HallSensor_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_PERIOD_ELAPSED_CB_ID : + htim->PeriodElapsedCallback = pCallback; + break; + + case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : + htim->PeriodElapsedHalfCpltCallback = pCallback; + break; + + case HAL_TIM_TRIGGER_CB_ID : + htim->TriggerCallback = pCallback; + break; + + case HAL_TIM_TRIGGER_HALF_CB_ID : + htim->TriggerHalfCpltCallback = pCallback; + break; + + case HAL_TIM_IC_CAPTURE_CB_ID : + htim->IC_CaptureCallback = pCallback; + break; + + case HAL_TIM_IC_CAPTURE_HALF_CB_ID : + htim->IC_CaptureHalfCpltCallback = pCallback; + break; + + case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : + htim->OC_DelayElapsedCallback = pCallback; + break; + + case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : + htim->PWM_PulseFinishedCallback = pCallback; + break; + + case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : + htim->PWM_PulseFinishedHalfCpltCallback = pCallback; + break; + + case HAL_TIM_ERROR_CB_ID : + htim->ErrorCallback = pCallback; + break; + + case HAL_TIM_COMMUTATION_CB_ID : + htim->CommutationCallback = pCallback; + break; + + case HAL_TIM_COMMUTATION_HALF_CB_ID : + htim->CommutationHalfCpltCallback = pCallback; + break; + + case HAL_TIM_BREAK_CB_ID : + htim->BreakCallback = pCallback; + break; + + case HAL_TIM_BREAK2_CB_ID : + htim->Break2Callback = pCallback; + break; + + case HAL_TIM_ENCODER_INDEX_CB_ID : + htim->EncoderIndexCallback = pCallback; + break; + + case HAL_TIM_DIRECTION_CHANGE_CB_ID : + htim->DirectionChangeCallback = pCallback; + break; + + case HAL_TIM_INDEX_ERROR_CB_ID : + htim->IndexErrorCallback = pCallback; + break; + + case HAL_TIM_TRANSITION_ERROR_CB_ID : + htim->TransitionErrorCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (htim->State == HAL_TIM_STATE_RESET) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + htim->Base_MspInitCallback = pCallback; + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + htim->Base_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + htim->IC_MspInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + htim->IC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + htim->OC_MspInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + htim->OC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + htim->PWM_MspInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + htim->PWM_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + htim->OnePulse_MspInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + htim->OnePulse_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + htim->Encoder_MspInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + htim->Encoder_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + htim->HallSensor_MspInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + htim->HallSensor_MspDeInitCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister a TIM callback + * TIM callback is redirected to the weak predefined callback + * @param htim tim handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID + * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID + * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID + * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID + * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID + * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID + * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID + * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID + * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID + * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID + * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID + * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID + * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID + * @arg @ref HAL_TIM_ENCODER_INDEX_CB_ID Encoder Index Callback ID + * @arg @ref HAL_TIM_DIRECTION_CHANGE_CB_ID Direction Change Callback ID + * @arg @ref HAL_TIM_INDEX_ERROR_CB_ID Index Error Callback ID + * @arg @ref HAL_TIM_TRANSITION_ERROR_CB_ID Transition Error Callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (htim->State == HAL_TIM_STATE_READY) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + /* Legacy weak Base MspInit Callback */ + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + /* Legacy weak Base Msp DeInit Callback */ + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + /* Legacy weak IC Msp Init Callback */ + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + /* Legacy weak IC Msp DeInit Callback */ + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + /* Legacy weak OC Msp Init Callback */ + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + /* Legacy weak OC Msp DeInit Callback */ + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + /* Legacy weak PWM Msp Init Callback */ + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + /* Legacy weak PWM Msp DeInit Callback */ + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + /* Legacy weak One Pulse Msp Init Callback */ + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + /* Legacy weak One Pulse Msp DeInit Callback */ + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + /* Legacy weak Encoder Msp Init Callback */ + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + /* Legacy weak Encoder Msp DeInit Callback */ + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + /* Legacy weak Hall Sensor Msp Init Callback */ + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + /* Legacy weak Hall Sensor Msp DeInit Callback */ + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; + break; + + case HAL_TIM_PERIOD_ELAPSED_CB_ID : + /* Legacy weak Period Elapsed Callback */ + htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; + break; + + case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : + /* Legacy weak Period Elapsed half complete Callback */ + htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; + break; + + case HAL_TIM_TRIGGER_CB_ID : + /* Legacy weak Trigger Callback */ + htim->TriggerCallback = HAL_TIM_TriggerCallback; + break; + + case HAL_TIM_TRIGGER_HALF_CB_ID : + /* Legacy weak Trigger half complete Callback */ + htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; + break; + + case HAL_TIM_IC_CAPTURE_CB_ID : + /* Legacy weak IC Capture Callback */ + htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; + break; + + case HAL_TIM_IC_CAPTURE_HALF_CB_ID : + /* Legacy weak IC Capture half complete Callback */ + htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; + break; + + case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : + /* Legacy weak OC Delay Elapsed Callback */ + htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; + break; + + case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : + /* Legacy weak PWM Pulse Finished Callback */ + htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; + break; + + case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : + /* Legacy weak PWM Pulse Finished half complete Callback */ + htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; + break; + + case HAL_TIM_ERROR_CB_ID : + /* Legacy weak Error Callback */ + htim->ErrorCallback = HAL_TIM_ErrorCallback; + break; + + case HAL_TIM_COMMUTATION_CB_ID : + /* Legacy weak Commutation Callback */ + htim->CommutationCallback = HAL_TIMEx_CommutCallback; + break; + + case HAL_TIM_COMMUTATION_HALF_CB_ID : + /* Legacy weak Commutation half complete Callback */ + htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; + break; + + case HAL_TIM_BREAK_CB_ID : + /* Legacy weak Break Callback */ + htim->BreakCallback = HAL_TIMEx_BreakCallback; + break; + + case HAL_TIM_BREAK2_CB_ID : + /* Legacy weak Break2 Callback */ + htim->Break2Callback = HAL_TIMEx_Break2Callback; + break; + + case HAL_TIM_ENCODER_INDEX_CB_ID : + /* Legacy weak Encoder Index Callback */ + htim->EncoderIndexCallback = HAL_TIMEx_EncoderIndexCallback; + break; + + case HAL_TIM_DIRECTION_CHANGE_CB_ID : + /* Legacy weak Direction Change Callback */ + htim->DirectionChangeCallback = HAL_TIMEx_DirectionChangeCallback; + break; + + case HAL_TIM_INDEX_ERROR_CB_ID : + /* Legacy weak Index Error Callback */ + htim->IndexErrorCallback = HAL_TIMEx_IndexErrorCallback; + break; + + case HAL_TIM_TRANSITION_ERROR_CB_ID : + /* Legacy weak Transition Error Callback */ + htim->TransitionErrorCallback = HAL_TIMEx_TransitionErrorCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (htim->State == HAL_TIM_STATE_RESET) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + /* Legacy weak Base MspInit Callback */ + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + /* Legacy weak Base Msp DeInit Callback */ + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + /* Legacy weak IC Msp Init Callback */ + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + /* Legacy weak IC Msp DeInit Callback */ + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + /* Legacy weak OC Msp Init Callback */ + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + /* Legacy weak OC Msp DeInit Callback */ + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + /* Legacy weak PWM Msp Init Callback */ + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + /* Legacy weak PWM Msp DeInit Callback */ + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + /* Legacy weak One Pulse Msp Init Callback */ + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + /* Legacy weak One Pulse Msp DeInit Callback */ + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + /* Legacy weak Encoder Msp Init Callback */ + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + /* Legacy weak Encoder Msp DeInit Callback */ + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + /* Legacy weak Hall Sensor Msp Init Callback */ + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + /* Legacy weak Hall Sensor Msp DeInit Callback */ + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions + * @brief TIM Peripheral State functions + * +@verbatim + ============================================================================== + ##### Peripheral State functions ##### + ============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the TIM Base handle state. + * @param htim TIM Base handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM OC handle state. + * @param htim TIM Output Compare handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM PWM handle state. + * @param htim TIM handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM Input Capture handle state. + * @param htim TIM IC handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM One Pulse Mode handle state. + * @param htim TIM OPM handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM Encoder Mode handle state. + * @param htim TIM Encoder Interface handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM Encoder Mode handle state. + * @param htim TIM handle + * @retval Active channel + */ +HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim) +{ + return htim->Channel; +} + +/** + * @brief Return actual state of the TIM channel. + * @param htim TIM handle + * @param Channel TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @arg TIM_CHANNEL_5: TIM Channel 5 + * @arg TIM_CHANNEL_6: TIM Channel 6 + * @retval TIM Channel state + */ +HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_TIM_ChannelStateTypeDef channel_state; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + + return channel_state; +} + +/** + * @brief Return actual state of a DMA burst operation. + * @param htim TIM handle + * @retval DMA burst state + */ +HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); + + return htim->DMABurstState; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup TIM_Private_Functions TIM Private Functions + * @{ + */ + +/** + * @brief TIM DMA error callback + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMAError(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + htim->State = HAL_TIM_STATE_READY; + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->ErrorCallback(htim); +#else + HAL_TIM_ErrorCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Delay Pulse complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Delay Pulse half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PWM_PulseFinishedHalfCpltCallback(htim); +#else + HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Capture complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Capture half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureHalfCpltCallback(htim); +#else + HAL_TIM_IC_CaptureHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Period Elapse complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedCallback(htim); +#else + HAL_TIM_PeriodElapsedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Period Elapse half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedHalfCpltCallback(htim); +#else + HAL_TIM_PeriodElapsedHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Trigger callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerCallback(htim); +#else + HAL_TIM_TriggerCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Trigger half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerHalfCpltCallback(htim); +#else + HAL_TIM_TriggerHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief Time Base configuration + * @param TIMx TIM peripheral + * @param Structure TIM Base configuration structure + * @retval None + */ +void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) +{ + uint32_t tmpcr1; + tmpcr1 = TIMx->CR1; + + /* Set TIM Time Base Unit parameters ---------------------------------------*/ + if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) + { + /* Select the Counter Mode */ + tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); + tmpcr1 |= Structure->CounterMode; + } + + if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) + { + /* Set the clock division */ + tmpcr1 &= ~TIM_CR1_CKD; + tmpcr1 |= (uint32_t)Structure->ClockDivision; + } + + /* Set the auto-reload preload */ + MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); + + TIMx->CR1 = tmpcr1; + + /* Set the Autoreload value */ + TIMx->ARR = (uint32_t)Structure->Period ; + + /* Set the Prescaler value */ + TIMx->PSC = Structure->Prescaler; + + if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) + { + /* Set the Repetition Counter value */ + TIMx->RCR = Structure->RepetitionCounter; + } + + /* Generate an update event to reload the Prescaler + and the repetition counter (only for advanced timer) value immediately */ + TIMx->EGR = TIM_EGR_UG; + + /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */ + if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE)) + { + /* Clear the update flag */ + CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE); + } +} + +/** + * @brief Timer Output Compare 1 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= ~TIM_CCER_CC1E; + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= ~TIM_CCMR1_OC1M; + tmpccmrx &= ~TIM_CCMR1_CC1S; + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC1P; + /* Set the Output Compare Polarity */ + tmpccer |= OC_Config->OCPolarity; + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) + { + /* Check parameters */ + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC1NP; + /* Set the Output N Polarity */ + tmpccer |= OC_Config->OCNPolarity; + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC1NE; + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS1; + tmpcr2 &= ~TIM_CR2_OIS1N; + /* Set the Output Idle state */ + tmpcr2 |= OC_Config->OCIdleState; + /* Set the Output N Idle state */ + tmpcr2 |= OC_Config->OCNIdleState; + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR1 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 2 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC2E; + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR1_OC2M; + tmpccmrx &= ~TIM_CCMR1_CC2S; + + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC2P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 4U); + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) + { + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC2NP; + /* Set the Output N Polarity */ + tmpccer |= (OC_Config->OCNPolarity << 4U); + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC2NE; + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS2; + tmpcr2 &= ~TIM_CR2_OIS2N; + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 2U); + /* Set the Output N Idle state */ + tmpcr2 |= (OC_Config->OCNIdleState << 2U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR2 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 3 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + + /* Disable the Channel 3: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC3E; + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR2_OC3M; + tmpccmrx &= ~TIM_CCMR2_CC3S; + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC3P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 8U); + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) + { + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC3NP; + /* Set the Output N Polarity */ + tmpccer |= (OC_Config->OCNPolarity << 8U); + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC3NE; + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS3; + tmpcr2 &= ~TIM_CR2_OIS3N; + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 4U); + /* Set the Output N Idle state */ + tmpcr2 |= (OC_Config->OCNIdleState << 4U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR3 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 4 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= ~TIM_CCER_CC4E; + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR2_OC4M; + tmpccmrx &= ~TIM_CCMR2_CC4S; + + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC4P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 12U); + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_4)) + { + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC4NP; + /* Set the Output N Polarity */ + tmpccer |= (OC_Config->OCNPolarity << 12U); + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC4NE; + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS4; + /* Reset the Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS4N; + + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 6U); + /* Set the Output N Idle state */ + tmpcr2 |= (OC_Config->OCNIdleState << 6U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR4 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 5 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, + const TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + + /* Disable the output: Reset the CCxE Bit */ + TIMx->CCER &= ~TIM_CCER_CC5E; + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR3; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= ~(TIM_CCMR3_OC5M); + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC5P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 16U); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Reset the Output Compare IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS5; + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 8U); + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR3 */ + TIMx->CCMR3 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR5 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 6 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, + const TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + + /* Disable the output: Reset the CCxE Bit */ + TIMx->CCER &= ~TIM_CCER_CC6E; + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR3; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= ~(TIM_CCMR3_OC6M); + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + + /* Reset the Output Polarity level */ + tmpccer &= (uint32_t)~TIM_CCER_CC6P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 20U); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Reset the Output Compare IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS6; + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 10U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR3 */ + TIMx->CCMR3 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR6 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Slave Timer configuration function + * @param htim TIM handle + * @param sSlaveConfig Slave timer configuration + * @retval None + */ +static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, + const TIM_SlaveConfigTypeDef *sSlaveConfig) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* Reset the Trigger Selection Bits */ + tmpsmcr &= ~TIM_SMCR_TS; + /* Set the Input Trigger source */ + tmpsmcr |= sSlaveConfig->InputTrigger; + + /* Reset the slave mode Bits */ + tmpsmcr &= ~TIM_SMCR_SMS; + /* Set the slave mode */ + tmpsmcr |= sSlaveConfig->SlaveMode; + + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + + /* Configure the trigger prescaler, filter, and polarity */ + switch (sSlaveConfig->InputTrigger) + { + case TIM_TS_ETRF: + { + /* Check the parameters */ + assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + /* Configure the ETR Trigger source */ + TIM_ETR_SetConfig(htim->Instance, + sSlaveConfig->TriggerPrescaler, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + break; + } + + case TIM_TS_TI1F_ED: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + if ((sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED) || \ + (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_COMBINED_GATEDRESET)) + { + return HAL_ERROR; + } + + /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = htim->Instance->CCER; + htim->Instance->CCER &= ~TIM_CCER_CC1E; + tmpccmr1 = htim->Instance->CCMR1; + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U); + + /* Write to TIMx CCMR1 and CCER registers */ + htim->Instance->CCMR1 = tmpccmr1; + htim->Instance->CCER = tmpccer; + break; + } + + case TIM_TS_TI1FP1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + /* Configure TI1 Filter and Polarity */ + TIM_TI1_ConfigInputStage(htim->Instance, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + break; + } + + case TIM_TS_TI2FP2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + /* Configure TI2 Filter and Polarity */ + TIM_TI2_ConfigInputStage(htim->Instance, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + break; + } + + case TIM_TS_ITR0: + case TIM_TS_ITR1: + case TIM_TS_ITR2: + case TIM_TS_ITR7: + case TIM_TS_ITR8: + { + /* Check the parameter */ + assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE((htim->Instance), sSlaveConfig->InputTrigger)); + break; + } + + default: + status = HAL_ERROR; + break; + } + + return status; +} + +/** + * @brief Configure the TI1 as Input. + * @param TIMx to select the TIM peripheral. + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2. + * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 + * (on channel2 path) is used as the input signal. Therefore CCMR1 must be + * protected against un-initialized filter and polarity values. + */ +void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = TIMx->CCER; + TIMx->CCER &= ~TIM_CCER_CC1E; + tmpccmr1 = TIMx->CCMR1; + + /* Select the Input */ + if (IS_TIM_CC2_INSTANCE(TIMx) != RESET) + { + tmpccmr1 &= ~TIM_CCMR1_CC1S; + tmpccmr1 |= TIM_ICSelection; + } + else + { + tmpccmr1 |= TIM_CCMR1_CC1S_0; + } + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F); + + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); + tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP)); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the Polarity and Filter for TI1. + * @param TIMx to select the TIM peripheral. + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = TIMx->CCER; + TIMx->CCER &= ~TIM_CCER_CC1E; + tmpccmr1 = TIMx->CCMR1; + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + tmpccmr1 |= (TIM_ICFilter << 4U); + + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); + tmpccer |= TIM_ICPolarity; + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI2 as Input. + * @param TIMx to select the TIM peripheral + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1. + * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 + * (on channel1 path) is used as the input signal. Therefore CCMR1 must be + * protected against un-initialized filter and polarity values. + */ +static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 2: Reset the CC2E Bit */ + tmpccer = TIMx->CCER; + TIMx->CCER &= ~TIM_CCER_CC2E; + tmpccmr1 = TIMx->CCMR1; + + /* Select the Input */ + tmpccmr1 &= ~TIM_CCMR1_CC2S; + tmpccmr1 |= (TIM_ICSelection << 8U); + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC2F; + tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F); + + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); + tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP)); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the Polarity and Filter for TI2. + * @param TIMx to select the TIM peripheral. + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 2: Reset the CC2E Bit */ + tmpccer = TIMx->CCER; + TIMx->CCER &= ~TIM_CCER_CC2E; + tmpccmr1 = TIMx->CCMR1; + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC2F; + tmpccmr1 |= (TIM_ICFilter << 12U); + + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); + tmpccer |= (TIM_ICPolarity << 4U); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI3 as Input. + * @param TIMx to select the TIM peripheral + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4. + * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 + * (on channel1 path) is used as the input signal. Therefore CCMR2 must be + * protected against un-initialized filter and polarity values. + */ +static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr2; + uint32_t tmpccer; + + /* Disable the Channel 3: Reset the CC3E Bit */ + tmpccer = TIMx->CCER; + TIMx->CCER &= ~TIM_CCER_CC3E; + tmpccmr2 = TIMx->CCMR2; + + /* Select the Input */ + tmpccmr2 &= ~TIM_CCMR2_CC3S; + tmpccmr2 |= TIM_ICSelection; + + /* Set the filter */ + tmpccmr2 &= ~TIM_CCMR2_IC3F; + tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F); + + /* Select the Polarity and set the CC3E Bit */ + tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP); + tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP)); + + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI4 as Input. + * @param TIMx to select the TIM peripheral + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3. + * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 + * (on channel1 path) is used as the input signal. Therefore CCMR2 must be + * protected against un-initialized filter and polarity values. + * @retval None + */ +static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr2; + uint32_t tmpccer; + + /* Disable the Channel 4: Reset the CC4E Bit */ + tmpccer = TIMx->CCER; + TIMx->CCER &= ~TIM_CCER_CC4E; + tmpccmr2 = TIMx->CCMR2; + + /* Select the Input */ + tmpccmr2 &= ~TIM_CCMR2_CC4S; + tmpccmr2 |= (TIM_ICSelection << 8U); + + /* Set the filter */ + tmpccmr2 &= ~TIM_CCMR2_IC4F; + tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F); + + /* Select the Polarity and set the CC4E Bit */ + tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP); + tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP)); + + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer ; +} + +/** + * @brief Selects the Input Trigger source + * @param TIMx to select the TIM peripheral + * @param InputTriggerSource The Input Trigger source. + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal Trigger 0 + * @arg TIM_TS_ITR1: Internal Trigger 1 + * @arg TIM_TS_ITR2: Internal Trigger 2 + * @arg TIM_TS_ITR7: Internal Trigger 7 + * @arg TIM_TS_ITR8: Internal Trigger 8 + * @arg TIM_TS_TI1F_ED: TI1 Edge Detector + * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 + * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 + * @arg TIM_TS_ETRF: External Trigger input + * @retval None + */ +static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) +{ + uint32_t tmpsmcr; + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + /* Reset the TS Bits */ + tmpsmcr &= ~TIM_SMCR_TS; + /* Set the Input Trigger source and the slave mode*/ + tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} +/** + * @brief Configures the TIMx External Trigger (ETR). + * @param TIMx to select the TIM peripheral + * @param TIM_ExtTRGPrescaler The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF. + * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2. + * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4. + * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active. + * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active. + * @param ExtTRGFilter External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, + uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) +{ + uint32_t tmpsmcr; + + tmpsmcr = TIMx->SMCR; + + /* Reset the ETR Bits */ + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + + /* Set the Prescaler, the Filter value and the Polarity */ + tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); + + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel x. + * @param TIMx to select the TIM peripheral + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @param ChannelState specifies the TIM Channel CCxE bit new state. + * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. + * @retval None + */ +void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) +{ + uint32_t tmp; + + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(TIMx)); + assert_param(IS_TIM_CHANNELS(Channel)); + + tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ + + /* Reset the CCxE Bit */ + TIMx->CCER &= ~tmp; + + /* Set or reset the CCxE Bit */ + TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ +} + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +/** + * @brief Reset interrupt callbacks to the legacy weak callbacks. + * @param htim pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @retval None + */ +void TIM_ResetCallback(TIM_HandleTypeDef *htim) +{ + /* Reset the TIM callback to the legacy weak callbacks */ + htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; + htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; + htim->TriggerCallback = HAL_TIM_TriggerCallback; + htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; + htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; + htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; + htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; + htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; + htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; + htim->ErrorCallback = HAL_TIM_ErrorCallback; + htim->CommutationCallback = HAL_TIMEx_CommutCallback; + htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; + htim->BreakCallback = HAL_TIMEx_BreakCallback; + htim->Break2Callback = HAL_TIMEx_Break2Callback; + htim->EncoderIndexCallback = HAL_TIMEx_EncoderIndexCallback; + htim->DirectionChangeCallback = HAL_TIMEx_DirectionChangeCallback; + htim->IndexErrorCallback = HAL_TIMEx_IndexErrorCallback; + htim->TransitionErrorCallback = HAL_TIMEx_TransitionErrorCallback; +} +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +#endif /* HAL_TIM_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_tim_ex.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_tim_ex.c new file mode 100644 index 0000000000..7145249607 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_tim_ex.c @@ -0,0 +1,3314 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_tim_ex.c + * @author MCD Application Team + * @brief TIM HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Timer Extended peripheral: + * + Time Hall Sensor Interface Initialization + * + Time Hall Sensor Interface Start + * + Time Complementary signal break and dead time configuration + * + Time Master and Slave synchronization configuration + * + Time Output Compare/PWM Channel Configuration (for channels 5 and 6) + * + Time OCRef clear configuration + * + Timer remapping capabilities configuration + * + Timer encoder index configuration + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### TIMER Extended features ##### + ============================================================================== + [..] + The Timer Extended features include: + (#) Complementary outputs with programmable dead-time for : + (++) Output Compare + (++) PWM generation (Edge and Center-aligned Mode) + (++) One-pulse mode output + (#) Synchronization circuit to control the timer with external signals and to + interconnect several timers together. + (#) Break input to put the timer output signals in reset state or in a known state. + (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for + positioning purposes + (#) In case of Pulse on compare, configure pulse length and delay + (#) Encoder index configuration + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Initialize the TIM low level resources by implementing the following functions + depending on the selected feature: + (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit() + + (#) Initialize the TIM low level resources : + (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); + (##) TIM pins configuration + (+++) Enable the clock for the TIM GPIOs using the following function: + __HAL_RCC_GPIOx_CLK_ENABLE(); + (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); + + (#) The external Clock can be configured, if needed (the default clock is the + internal clock from the APBx), using the following function: + HAL_TIM_ConfigClockSource, the clock configuration should be done before + any start function. + + (#) Configure the TIM in the desired functioning mode using one of the + initialization function of this driver: + (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the + Timer Hall Sensor Interface and the commutation event with the corresponding + Interrupt and DMA request if needed (Note that One Timer is used to interface + with the Hall sensor Interface and another Timer should be used to use + the commutation event). + (#) In case of Pulse On Compare: + (++) HAL_TIMEx_OC_ConfigPulseOnCompare(): to configure pulse width and prescaler + + + (#) Activate the TIM peripheral using one of the start functions: + (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), + HAL_TIMEx_OCN_Start_IT() + (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), + HAL_TIMEx_PWMN_Start_IT() + (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT() + (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), + HAL_TIMEx_HallSensor_Start_IT(). + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @defgroup TIMEx TIMEx + * @brief TIM Extended HAL module driver + * @{ + */ + +#ifdef HAL_TIM_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup TIMEx_Private_Constants TIM Extended Private Constants + * @{ + */ +/* Timeout for break input rearm */ +#define TIM_BREAKINPUT_REARM_TIMEOUT 5UL /* 5 milliseconds */ +/** + * @} + */ +/* End of private constants --------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma); +static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState); + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions + * @{ + */ + +/** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions + * @brief Timer Hall Sensor functions + * +@verbatim + ============================================================================== + ##### Timer Hall Sensor functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure TIM HAL Sensor. + (+) De-initialize TIM HAL Sensor. + (+) Start the Hall Sensor Interface. + (+) Stop the Hall Sensor Interface. + (+) Start the Hall Sensor Interface and enable interrupts. + (+) Stop the Hall Sensor Interface and disable interrupts. + (+) Start the Hall Sensor Interface and enable DMA transfers. + (+) Stop the Hall Sensor Interface and disable DMA transfers. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle. + * @note When the timer instance is initialized in Hall Sensor Interface mode, + * timer channels 1 and channel 2 are reserved and cannot be used for + * other purpose. + * @param htim TIM Hall Sensor Interface handle + * @param sConfig TIM Hall Sensor configuration structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig) +{ + TIM_OC_InitTypeDef OC_Config; + + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy week callbacks */ + TIM_ResetCallback(htim); + + if (htim->HallSensor_MspInitCallback == NULL) + { + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->HallSensor_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIMEx_HallSensor_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Configure the Time base in the Encoder Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */ + TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter); + + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + /* Set the IC1PSC value */ + htim->Instance->CCMR1 |= sConfig->IC1Prescaler; + + /* Enable the Hall sensor interface (XOR function of the three inputs) */ + htim->Instance->CR2 |= TIM_CR2_TI1S; + + /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI1F_ED; + + /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_RESET; + + /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/ + OC_Config.OCFastMode = TIM_OCFAST_DISABLE; + OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET; + OC_Config.OCMode = TIM_OCMODE_PWM2; + OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET; + OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH; + OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH; + OC_Config.Pulse = sConfig->Commutation_Delay; + + TIM_OC2_SetConfig(htim->Instance, &OC_Config); + + /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2 + register to 101 */ + htim->Instance->CR2 &= ~TIM_CR2_MMS; + htim->Instance->CR2 |= TIM_TRGO_OC2REF; + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM Hall Sensor interface + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->HallSensor_MspDeInitCallback == NULL) + { + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; + } + /* DeInit the low level hardware */ + htim->HallSensor_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIMEx_HallSensor_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Hall Sensor MSP. + * @param htim TIM Hall Sensor Interface handle + * @retval None + */ +__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Hall Sensor MSP. + * @param htim TIM Hall Sensor Interface handle + * @retval None + */ +__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Hall Sensor Interface. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Hall sensor Interface. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1, 2 and 3 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Hall Sensor Interface in interrupt mode. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the capture compare Interrupts 1 event */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Hall Sensor Interface in interrupt mode. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts event */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Hall Sensor Interface in DMA mode. + * @param htim TIM Hall Sensor Interface handle + * @param pData The destination Buffer address. + * @param Length The length of data to be transferred from TIM peripheral to memory. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Set the TIM channel state */ + if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Set the DMA Input Capture 1 Callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA channel for Capture 1*/ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the capture compare 1 Interrupt */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Hall Sensor Interface in DMA mode. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + + /* Disable the capture compare Interrupts 1 event */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions + * @brief Timer Complementary Output Compare functions + * +@verbatim + ============================================================================== + ##### Timer Complementary Output Compare functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Complementary Output Compare/PWM. + (+) Stop the Complementary Output Compare/PWM. + (+) Start the Complementary Output Compare/PWM and enable interrupts. + (+) Stop the Complementary Output Compare/PWM and disable interrupts. + (+) Start the Complementary Output Compare/PWM and enable DMA transfers. + (+) Stop the Complementary Output Compare/PWM and disable DMA transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Starts the TIM Output Compare signal generation on the complementary + * output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation on the complementary + * output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Output Compare signal generation in interrupt mode + * on the complementary output. + * @param htim TIM OC handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Output Compare interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Output Compare interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Output Compare interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + + case TIM_CHANNEL_4: + { + /* Enable the TIM Output Compare interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the TIM Break interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); + + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM Output Compare signal generation in interrupt mode + * on the complementary output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpccer; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the TIM Break interrupt (only if no more channel is active) */ + tmpccer = htim->Instance->CCER; + if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET) + { + __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); + } + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @brief Starts the TIM Output Compare signal generation in DMA mode + * on the complementary output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Set the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) + { + return HAL_BUSY; + } + else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) + { + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM Output Compare signal generation in DMA mode + * on the complementary output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Output Compare DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Output Compare DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Output Compare DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions + * @brief Timer Complementary PWM functions + * +@verbatim + ============================================================================== + ##### Timer Complementary PWM functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Complementary PWM. + (+) Stop the Complementary PWM. + (+) Start the Complementary PWM and enable interrupts. + (+) Stop the Complementary PWM and disable interrupts. + (+) Start the Complementary PWM and enable DMA transfers. + (+) Stop the Complementary PWM and disable DMA transfers. +@endverbatim + * @{ + */ + +/** + * @brief Starts the PWM signal generation on the complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the PWM signal generation on the complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the PWM signal generation in interrupt mode on the + * complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the TIM Break interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); + + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the PWM signal generation in interrupt mode on the + * complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpccer; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the TIM Break interrupt (only if no more channel is active) */ + tmpccer = htim->Instance->CCER; + if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET) + { + __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); + } + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @brief Starts the TIM PWM signal generation in DMA mode on the + * complementary output + * @param htim TIM handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Set the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) + { + return HAL_BUSY; + } + else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) + { + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA channel */ + if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM PWM signal generation in DMA mode on the complementary + * output + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions + * @brief Timer Complementary One Pulse functions + * +@verbatim + ============================================================================== + ##### Timer Complementary One Pulse functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Complementary One Pulse generation. + (+) Stop the Complementary One Pulse. + (+) Start the Complementary One Pulse and enable interrupts. + (+) Stop the Complementary One Pulse and disable interrupts. + +@endverbatim + * @{ + */ + +/** + * @brief Starts the TIM One Pulse signal generation on the complementary + * output. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel pulse output channel to enable + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the complementary One Pulse output channel and the Input Capture channel */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation on the complementary + * output. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel pulse output channel to disable + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Disable the complementary One Pulse output channel and the Input Capture channel */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM One Pulse signal generation in interrupt mode on the + * complementary channel. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel pulse output channel to enable + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + + /* Enable the complementary One Pulse output channel and the Input Capture channel */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation in interrupt mode on the + * complementary channel. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel pulse output channel to disable + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + + /* Disable the complementary One Pulse output channel and the Input Capture channel */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Configure the commutation event in case of use of the Hall sensor interface. + (+) Configure Output channels for OC and PWM mode. + + (+) Configure Complementary channels, break features and dead time. + (+) Configure Master synchronization. + (+) Configure timer remapping capabilities. + (+) Select timer input source. + (+) Enable or disable channel grouping. + (+) Configure Pulse on compare. + (+) Configure Encoder index. + +@endverbatim + * @{ + */ + +/** + * @brief Configure the TIM commutation event sequence. + * @note This function is mandatory to use the commutation event in order to + * update the configuration at each commutation detection on the TRGI input of the Timer, + * the typical use of this feature is with the use of another Timer(interface Timer) + * configured in Hall sensor interface, this interface Timer will generate the + * commutation at its TRGO output (connected to Timer used in this function) each time + * the TI1 of the Interface Timer detect a commutation at its input TI1. + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal trigger 0 selected + * @arg TIM_TS_ITR1: Internal trigger 1 selected + * @arg TIM_TS_ITR2: Internal trigger 2 selected + * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_NONE: No trigger is needed + * @param CommutationSource the Commutation Event source + * This parameter can be one of the following values: + * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer + * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); + assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(htim->Instance, InputTrigger)); + + __HAL_LOCK(htim); + + { + /* Select the Input trigger */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= InputTrigger; + } + + /* Select the Capture Compare preload feature */ + htim->Instance->CR2 |= TIM_CR2_CCPC; + /* Select the Commutation event source */ + htim->Instance->CR2 &= ~TIM_CR2_CCUS; + htim->Instance->CR2 |= CommutationSource; + + /* Disable Commutation Interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM); + + /* Disable Commutation DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configure the TIM commutation event sequence with interrupt. + * @note This function is mandatory to use the commutation event in order to + * update the configuration at each commutation detection on the TRGI input of the Timer, + * the typical use of this feature is with the use of another Timer(interface Timer) + * configured in Hall sensor interface, this interface Timer will generate the + * commutation at its TRGO output (connected to Timer used in this function) each time + * the TI1 of the Interface Timer detect a commutation at its input TI1. + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal trigger 0 selected + * @arg TIM_TS_ITR1: Internal trigger 1 selected + * @arg TIM_TS_ITR2: Internal trigger 2 selected + * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_NONE: No trigger is needed + * @param CommutationSource the Commutation Event source + * This parameter can be one of the following values: + * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer + * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); + assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(htim->Instance, InputTrigger)); + + __HAL_LOCK(htim); + + { + /* Select the Input trigger */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= InputTrigger; + } + + /* Select the Capture Compare preload feature */ + htim->Instance->CR2 |= TIM_CR2_CCPC; + /* Select the Commutation event source */ + htim->Instance->CR2 &= ~TIM_CR2_CCUS; + htim->Instance->CR2 |= CommutationSource; + + /* Disable Commutation DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM); + + /* Enable the Commutation Interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configure the TIM commutation event sequence with DMA. + * @note This function is mandatory to use the commutation event in order to + * update the configuration at each commutation detection on the TRGI input of the Timer, + * the typical use of this feature is with the use of another Timer(interface Timer) + * configured in Hall sensor interface, this interface Timer will generate the + * commutation at its TRGO output (connected to Timer used in this function) each time + * the TI1 of the Interface Timer detect a commutation at its input TI1. + * @note The user should configure the DMA in his own software, in This function only the COMDE bit is set + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal trigger 0 selected + * @arg TIM_TS_ITR1: Internal trigger 1 selected + * @arg TIM_TS_ITR2: Internal trigger 2 selected + * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_NONE: No trigger is needed + * @param CommutationSource the Commutation Event source + * This parameter can be one of the following values: + * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer + * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); + assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(htim->Instance, InputTrigger)); + + __HAL_LOCK(htim); + + { + /* Select the Input trigger */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= InputTrigger; + } + + /* Select the Capture Compare preload feature */ + htim->Instance->CR2 |= TIM_CR2_CCPC; + /* Select the Commutation event source */ + htim->Instance->CR2 &= ~TIM_CR2_CCUS; + htim->Instance->CR2 |= CommutationSource; + + /* Enable the Commutation DMA Request */ + /* Set the DMA Commutation Callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError; + + /* Disable Commutation Interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM); + + /* Enable the Commutation DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the TIM in master mode. + * @param htim TIM handle. + * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that + * contains the selected trigger output (TRGO) and the Master/Slave + * mode. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, + const TIM_MasterConfigTypeDef *sMasterConfig) +{ + uint32_t tmpcr2; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); + assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); + + /* Check input state */ + __HAL_LOCK(htim); + + /* Change the handler state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Get the TIMx CR2 register value */ + tmpcr2 = htim->Instance->CR2; + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */ + if (IS_TIM_TRGO2_INSTANCE(htim->Instance)) + { + /* Check the parameters */ + assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2)); + + /* Clear the MMS2 bits */ + tmpcr2 &= ~TIM_CR2_MMS2; + /* Select the TRGO2 source*/ + tmpcr2 |= sMasterConfig->MasterOutputTrigger2; + } + + /* Reset the MMS Bits */ + tmpcr2 &= ~TIM_CR2_MMS; + /* Select the TRGO source */ + tmpcr2 |= sMasterConfig->MasterOutputTrigger; + + /* Update TIMx CR2 */ + htim->Instance->CR2 = tmpcr2; + + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + /* Reset the MSM Bit */ + tmpsmcr &= ~TIM_SMCR_MSM; + /* Set master mode */ + tmpsmcr |= sMasterConfig->MasterSlaveMode; + + /* Update TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + } + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State + * and the AOE(automatic output enable). + * @param htim TIM handle + * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that + * contains the BDTR Register configuration information for the TIM peripheral. + * @note Interrupts can be generated when an active level is detected on the + * break input, the break 2 input or the system break input. Break + * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, + const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) +{ + /* Keep this variable initialized to 0 as it is used to configure BDTR register */ + uint32_t tmpbdtr = 0U; + + /* Check the parameters */ + assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); + assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode)); + assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode)); + assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel)); + assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime)); + assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState)); + assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity)); + assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter)); + assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput)); + assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode)); + + /* Check input state */ + __HAL_LOCK(htim); + + /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, + the OSSI State, the dead time value and the Automatic Output Enable Bit */ + + /* Set the BDTR bits */ + MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); + MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); + MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos)); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode); + + if (IS_TIM_BKIN2_INSTANCE(htim->Instance)) + { + /* Check the parameters */ + assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State)); + assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity)); + assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter)); + assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode)); + + /* Set the BREAK2 input related BDTR bits */ + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos)); + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State); + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity); + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode); + } + + /* Set TIMx_BDTR */ + htim->Instance->BDTR = tmpbdtr; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the break input source. + * @param htim TIM handle. + * @param BreakInput Break input to configure + * This parameter can be one of the following values: + * @arg TIM_BREAKINPUT_BRK: Timer break input + * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input + * @param sBreakInputConfig Break input source configuration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, + uint32_t BreakInput, + const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmporx; + uint32_t bkin_enable_mask; + uint32_t bkin_polarity_mask; + uint32_t bkin_enable_bitpos; + uint32_t bkin_polarity_bitpos; + + /* Check the parameters */ + assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); + assert_param(IS_TIM_BREAKINPUT(BreakInput)); + assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source)); + assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable)); + assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity)); + + /* Check input state */ + __HAL_LOCK(htim); + + switch (sBreakInputConfig->Source) + { + case TIM_BREAKINPUTSOURCE_BKIN: + { + bkin_enable_mask = TIM_AF1_BKINE; + bkin_enable_bitpos = TIM_AF1_BKINE_Pos; + bkin_polarity_mask = TIM_AF1_BKINP; + bkin_polarity_bitpos = TIM_AF1_BKINP_Pos; + break; + } + case TIM_BREAKINPUTSOURCE_COMP1: + { + bkin_enable_mask = TIM_AF1_BKCMP1E; + bkin_enable_bitpos = TIM_AF1_BKCMP1E_Pos; + bkin_polarity_mask = TIM_AF1_BKCMP1P; + bkin_polarity_bitpos = TIM_AF1_BKCMP1P_Pos; + break; + } + case TIM_BREAKINPUTSOURCE_COMP2: + { + bkin_enable_mask = TIM_AF1_BKCMP2E; + bkin_enable_bitpos = TIM_AF1_BKCMP2E_Pos; + bkin_polarity_mask = TIM_AF1_BKCMP2P; + bkin_polarity_bitpos = TIM_AF1_BKCMP2P_Pos; + break; + } + + default: + { + bkin_enable_mask = 0U; + bkin_polarity_mask = 0U; + bkin_enable_bitpos = 0U; + bkin_polarity_bitpos = 0U; + break; + } + } + + switch (BreakInput) + { + case TIM_BREAKINPUT_BRK: + { + /* Get the TIMx_AF1 register value */ + tmporx = htim->Instance->AF1; + + /* Enable the break input */ + tmporx &= ~bkin_enable_mask; + tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask; + + /* Set the break input polarity */ + tmporx &= ~bkin_polarity_mask; + tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask; + + /* Set TIMx_AF1 */ + htim->Instance->AF1 = tmporx; + break; + } + case TIM_BREAKINPUT_BRK2: + { + /* Get the TIMx_AF2 register value */ + tmporx = htim->Instance->AF2; + + /* Enable the break input */ + tmporx &= ~bkin_enable_mask; + tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask; + + /* Set the break input polarity */ + tmporx &= ~bkin_polarity_mask; + tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask; + + /* Set TIMx_AF2 */ + htim->Instance->AF2 = tmporx; + break; + } + default: + status = HAL_ERROR; + break; + } + + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Configures the TIMx Remapping input capabilities. + * @param htim TIM handle. + * @param Remap specifies the TIM remapping source. + * For TIM1, the parameter can take one of the following values: + * @arg TIM_TIM1_ETR_GPIO TIM1_ETR is not connected to I/O + * @arg TIM_TIM1_ETR_COMP1 TIM1_ETR is connected to COMP1 output + * @arg TIM_TIM1_ETR_COMP2 TIM1_ETR is connected to COMP2 output + * @arg TIM_TIM1_ETR_HSI TIM1_ETR is connected to HSI + * @arg TIM_TIM1_ETR_ADC4_AWD1 TIM1_ETR is connected to ADC4 AWD1 + * @arg TIM_TIM1_ETR_ADC4_AWD2 TIM1_ETR is connected to ADC4 AWD2 + * @arg TIM_TIM1_ETR_ADC4_AWD3 TIM1_ETR is connected to ADC4 AWD3 + * + * For TIM2, the parameter can take one of the following values: + * @arg TIM_TIM2_ETR_GPIO TIM2_ETR is not connected to I/O + * @arg TIM_TIM2_ETR_COMP1 TIM2_ETR is connected to COMP1 output + * @arg TIM_TIM2_ETR_COMP2 TIM2_ETR is connected to COMP2 output + * @arg TIM_TIM2_ETR_HSI TIM2_ETR is connected to HSI + * @arg TIM_TIM2_ETR_TIM3_ETR TIM2_ETR is connected to TIM3 ETR + * @arg TIM_TIM2_ETR_LSE TIM2_ETR is connected to LSE + * + * For TIM3, the parameter can take one of the following values: + * @arg TIM_TIM3_ETR_GPIO TIM3_ETR is not connected to I/O + * @arg TIM_TIM3_ETR_COMP1 TIM3_ETR is connected to COMP1 output + * @arg TIM_TIM3_ETR_COMP2 TIM3_ETR is connected to COMP2 output + * @arg TIM_TIM3_ETR_HSI TIM3_ETR is connected to HSI + * @arg TIM_TIM3_ETR_TIM2_ETR TIM3_ETR is connected to TIM2 ETR + * @arg TIM_TIM3_ETR_ADC4_AWD2 TIM3_ETR is connected to ADC4 AWD2 + * @arg TIM_TIM3_ETR_ADC4_AWD3 TIM3_ETR is connected to ADC4 AWD3 + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) +{ + /* Check parameters */ + assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance)); + assert_param(IS_TIM_REMAP(Remap)); + + __HAL_LOCK(htim); + + MODIFY_REG(htim->Instance->AF1, TIM_AF1_ETRSEL_Msk, Remap); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Select the timer input source + * @param htim TIM handle. + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TI1 input channel + * @arg TIM_CHANNEL_2: TI2 input channel + * @arg TIM_CHANNEL_4: TI4 input channel + * @param TISelection parameter of the TIM_TISelectionStruct structure is detailed as follows: + * For TIM1, the parameter is one of the following values: + * @arg TIM_TIM1_TI1_GPIO: TIM1 TI1 is connected to GPIO + * @arg TIM_TIM1_TI1_COMP1: TIM1 TI1 is connected to COMP1 output + * @arg TIM_TIM1_TI1_COMP2: TIM1 TI1 is connected to COMP2 output + * + * For TIM2, the parameter is one of the following values: + * @arg TIM_TIM2_TI1_GPIO: TIM2 TI1 is connected to GPIO + * @arg TIM_TIM2_TI1_COMP1: TIM2 TI1 is connected to COMP1 output + * @arg TIM_TIM2_TI1_COMP2: TIM2 TI1 is connected to COMP1 output + * @arg TIM_TIM2_TI2_GPIO: TIM2 TI2 is connected to GPIO + * @arg TIM_TIM2_TI2_COMP1: TIM2 TI2 is connected to COMP1 output + * @arg TIM_TIM2_TI2_COMP2: TIM2 TI2 is connected to COMP1 output + * @arg TIM_TIM2_TI4_GPIO: TIM2 TI4 is connected to GPIO + * @arg TIM_TIM2_TI4_COMP1: TIM2 TI4 is connected to COMP1 output + * @arg TIM_TIM2_TI4_COMP2: TIM2 TI4 is connected to COMP2 output + * + * For TIM3, the parameter is one of the following values: + * @arg TIM_TIM3_TI1_GPIO: TIM3 TI1 is connected to GPIO + * @arg TIM_TIM3_TI1_COMP1: TIM3 TI1 is connected to COMP1 output + * @arg TIM_TIM3_TI1_COMP2: TIM3 TI1 is connected to COMP2 output + * @arg TIM_TIM3_TI2_GPIO: TIM3 TI2 is connected to GPIO + * @arg TIM_TIM3_TI2_COMP1: TIM3 TI2 is connected to COMP1 output + * @arg TIM_TIM3_TI2_COMP2: TIM3 TI2 is connected to COMP1 output + * + * For TIM16, the parameter can have the following values: + * @arg TIM_TIM16_TI1_GPIO: TIM16 TI1 is connected to GPIO + * @arg TIM_TIM16_TI1_MCO: TIM16 TI1 is connected to MCO + * @arg TIM_TIM16_TI1_LSI: TIM16 TI1 is connected to LSI + * @arg TIM_TIM16_TI1_LSE: TIM16 TI1 is connected to LSE + * @arg TIM_TIM16_TI1_RTC_WKUP: TIM16 TI1 is connected to RTC wakeup interrupt + * @arg TIM_TIM16_TI1_HSE_DIV32: TIM16 TI1 is connected to HSE/32 + * + * For TIM17, the parameter can have the following values: + * @arg TIM_TIM17_TI1_GPIO: TIM17 TI1 is connected to GPIO + * @arg TIM_TIM17_TI1_MCO: TIM17 TI1 is connected to MCO + * @arg TIM_TIM17_TI1_LSI: TIM17 TI1 is connected to LSI + * @arg TIM_TIM17_TI1_LSE: TIM17 TI1 is connected to LSE + * @arg TIM_TIM17_TI1_RTC_WKUP: TIM17 TI1 is connected to RTC wakeup interrupt + * @arg TIM_TIM17_TI1_HSE_DIV32: TIM17 TI1 is connected to HSE/32 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check parameters */ + assert_param(IS_TIM_TISEL_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TISEL(TISelection)); + + __HAL_LOCK(htim); + + switch (Channel) + { + case TIM_CHANNEL_1: + MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI1SEL, TISelection); + + /* If required, set OR bit to request HSE/32 clock */ + if (IS_TIM_HSE32_INSTANCE(htim->Instance)) + { + SET_BIT(htim->Instance->OR, TIM_OR_HSE32EN); + } + else + { + CLEAR_BIT(htim->Instance->OR, TIM_OR_HSE32EN); + } + break; + case TIM_CHANNEL_2: + MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI2SEL, TISelection); + break; + case TIM_CHANNEL_4: + MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI4SEL, TISelection); + break; + default: + status = HAL_ERROR; + break; + } + + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Group channel 5 and channel 1, 2 or 3 + * @param htim TIM handle. + * @param Channels specifies the reference signal(s) the OC5REF is combined with. + * This parameter can be any combination of the following values: + * TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC + * TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF + * TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF + * TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels) +{ + /* Check parameters */ + assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_GROUPCH5(Channels)); + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Clear GC5Cx bit fields */ + htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1); + + /* Set GC5Cx bit fields */ + htim->Instance->CCR5 |= Channels; + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Disarm the designated break input (when it operates in bidirectional mode). + * @param htim TIM handle. + * @param BreakInput Break input to disarm + * This parameter can be one of the following values: + * @arg TIM_BREAKINPUT_BRK: Timer break input + * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input + * @note The break input can be disarmed only when it is configured in + * bidirectional mode and when when MOE is reset. + * @note Purpose is to be able to have the input voltage back to high-state, + * whatever the time constant on the output . + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpbdtr; + + /* Check the parameters */ + assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); + assert_param(IS_TIM_BREAKINPUT(BreakInput)); + + switch (BreakInput) + { + case TIM_BREAKINPUT_BRK: + { + /* Check initial conditions */ + tmpbdtr = READ_REG(htim->Instance->BDTR); + if ((READ_BIT(tmpbdtr, TIM_BDTR_BKBID) == TIM_BDTR_BKBID) && + (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U)) + { + /* Break input BRK is disarmed */ + SET_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM); + } + break; + } + case TIM_BREAKINPUT_BRK2: + { + /* Check initial conditions */ + tmpbdtr = READ_REG(htim->Instance->BDTR); + if ((READ_BIT(tmpbdtr, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID) && + (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U)) + { + /* Break input BRK is disarmed */ + SET_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM); + } + break; + } + default: + status = HAL_ERROR; + break; + } + + return status; +} + +/** + * @brief Arm the designated break input (when it operates in bidirectional mode). + * @param htim TIM handle. + * @param BreakInput Break input to arm + * This parameter can be one of the following values: + * @arg TIM_BREAKINPUT_BRK: Timer break input + * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input + * @note Arming is possible at anytime, even if fault is present. + * @note Break input is automatically armed as soon as MOE bit is set. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(const TIM_HandleTypeDef *htim, uint32_t BreakInput) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); + assert_param(IS_TIM_BREAKINPUT(BreakInput)); + + switch (BreakInput) + { + case TIM_BREAKINPUT_BRK: + { + /* Check initial conditions */ + if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKBID) == TIM_BDTR_BKBID) + { + /* Break input BRK is re-armed automatically by hardware. Poll to check whether fault condition disappeared */ + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL) + { + if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT) + { + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL) + { + return HAL_TIMEOUT; + } + } + } + } + break; + } + + case TIM_BREAKINPUT_BRK2: + { + /* Check initial conditions */ + if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID) + { + /* Break input BRK2 is re-armed automatically by hardware. Poll to check whether fault condition disappeared */ + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL) + { + if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT) + { + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL) + { + return HAL_TIMEOUT; + } + } + } + } + break; + } + default: + status = HAL_ERROR; + break; + } + + return status; +} + +/** + * @brief Enable dithering + * @param htim TIM handle + * @note Main usage is PWM mode + * @note This function must be called when timer is stopped or disabled (CEN =0) + * @note If dithering is activated, pay attention to ARR, CCRx, CNT interpretation: + * - CNT: only CNT[11:0] holds the non-dithered part for 16b timers (or CNT[26:0] for 32b timers) + * - ARR: ARR[15:4] holds the non-dithered part, and ARR[3:0] the dither part for 16b timers + * - CCRx: CCRx[15:4] holds the non-dithered part, and CCRx[3:0] the dither part for 16b timers + * - ARR and CCRx values are limited to 0xFFEF in dithering mode for 16b timers + * (corresponds to 4094 for the integer part and 15 for the dithered part). + * @note Macros @ref __HAL_TIM_CALC_PERIOD_DITHER() __HAL_TIM_CALC_DELAY_DITHER() __HAL_TIM_CALC_PULSE_DITHER() + * can be used to calculate period (ARR) and delay (CCRx) value. + * @note Enabling dithering, modifies automatically values of registers ARR/CCRx to keep the same integer part. + * @note Enabling dithering, modifies automatically values of registers ARR/CCRx to keep the same integer part. + * So it may be necessary to read ARR value or CCRx value with macros @ref __HAL_TIM_GET_AUTORELOAD() + * __HAL_TIM_GET_COMPARE() and if necessary update Init structure field htim->Init.Period . + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_DitheringEnable(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + SET_BIT(htim->Instance->CR1, TIM_CR1_DITHEN); + return HAL_OK; +} + +/** + * @brief Disable dithering + * @param htim TIM handle + * @note This function must be called when timer is stopped or disabled (CEN =0) + * @note If dithering is activated, pay attention to ARR, CCRx, CNT interpretation: + * - CNT: only CNT[11:0] holds the non-dithered part for 16b timers (or CNT[26:0] for 32b timers) + * - ARR: ARR[15:4] holds the non-dithered part, and ARR[3:0] the dither part for 16b timers + * - CCRx: CCRx[15:4] holds the non-dithered part, and CCRx[3:0] the dither part for 16b timers + * - ARR and CCRx values are limited to 0xFFEF in dithering mode + * (corresponds to 4094 for the integer part and 15 for the dithered part). + * @note Disabling dithering, modifies automatically values of registers ARR/CCRx to keep the same integer part. + * So it may be necessary to read ARR value or CCRx value with macros @ref __HAL_TIM_GET_AUTORELOAD() + * __HAL_TIM_GET_COMPARE() and if necessary update Init structure field htim->Init.Period . + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_DitheringDisable(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + CLEAR_BIT(htim->Instance->CR1, TIM_CR1_DITHEN); + return HAL_OK; +} + +/** + * @brief Initializes the pulse on compare pulse width and pulse prescaler + * @param htim TIM Output Compare handle + * @param PulseWidthPrescaler Pulse width prescaler + * This parameter can be a number between Min_Data = 0x0 and Max_Data = 0x7 + * @param PulseWidth Pulse width + * This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OC_ConfigPulseOnCompare(TIM_HandleTypeDef *htim, + uint32_t PulseWidthPrescaler, + uint32_t PulseWidth) +{ + uint32_t tmpecr; + + /* Check the parameters */ + assert_param(IS_TIM_PULSEONCOMPARE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_PULSEONCOMPARE_WIDTH(PulseWidth)); + assert_param(IS_TIM_PULSEONCOMPARE_WIDTHPRESCALER(PulseWidthPrescaler)); + + /* Process Locked */ + __HAL_LOCK(htim); + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Get the TIMx ECR register value */ + tmpecr = htim->Instance->ECR; + /* Reset the Pulse width prescaler and the Pulse width */ + tmpecr &= ~(TIM_ECR_PWPRSC | TIM_ECR_PW); + /* Set the Pulse width prescaler and Pulse width*/ + tmpecr |= PulseWidthPrescaler << TIM_ECR_PWPRSC_Pos; + tmpecr |= PulseWidth << TIM_ECR_PW_Pos; + /* Write to TIMx ECR */ + htim->Instance->ECR = tmpecr; + + /* Change the TIM state */ + htim->State = HAL_TIM_STATE_READY; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configure preload source of Slave Mode Selection bitfield (SMS in SMCR register) + * @param htim TIM handle + * @param Source Source of slave mode selection preload + * This parameter can be one of the following values: + * @arg TIM_SMS_PRELOAD_SOURCE_UPDATE: Timer update event is used as source of Slave Mode Selection preload + * @arg TIM_SMS_PRELOAD_SOURCE_INDEX: Timer index event is used as source of Slave Mode Selection preload + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigSlaveModePreload(TIM_HandleTypeDef *htim, uint32_t Source) +{ + /* Check the parameters */ + assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_SLAVE_PRELOAD_SOURCE(Source)); + + MODIFY_REG(htim->Instance->SMCR, TIM_SMCR_SMSPS, Source); + return HAL_OK; +} + +/** + * @brief Enable preload of Slave Mode Selection bitfield (SMS in SMCR register) + * @param htim TIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_EnableSlaveModePreload(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); + + SET_BIT(htim->Instance->SMCR, TIM_SMCR_SMSPE); + return HAL_OK; +} + +/** + * @brief Disable preload of Slave Mode Selection bitfield (SMS in SMCR register) + * @param htim TIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_DisableSlaveModePreload(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); + + CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_SMSPE); + return HAL_OK; +} + +/** + * @brief Enable deadtime preload + * @param htim TIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_EnableDeadTimePreload(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); + + SET_BIT(htim->Instance->DTR2, TIM_DTR2_DTPE); + return HAL_OK; +} + +/** + * @brief Disable deadtime preload + * @param htim TIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_DisableDeadTimePreload(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); + + CLEAR_BIT(htim->Instance->DTR2, TIM_DTR2_DTPE); + return HAL_OK; +} + +/** + * @brief Configure deadtime + * @param htim TIM handle + * @param Deadtime Deadtime value + * @note This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigDeadTime(TIM_HandleTypeDef *htim, uint32_t Deadtime) +{ + /* Check the parameters */ + assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); + assert_param(IS_TIM_DEADTIME(Deadtime)); + + MODIFY_REG(htim->Instance->BDTR, TIM_BDTR_DTG, Deadtime); + return HAL_OK; +} + +/** + * @brief Configure asymmetrical deadtime + * @param htim TIM handle + * @param FallingDeadtime Falling edge deadtime value + * @note This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigAsymmetricalDeadTime(TIM_HandleTypeDef *htim, uint32_t FallingDeadtime) +{ + /* Check the parameters */ + assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); + assert_param(IS_TIM_DEADTIME(FallingDeadtime)); + + MODIFY_REG(htim->Instance->DTR2, TIM_DTR2_DTGF, FallingDeadtime); + return HAL_OK; +} + +/** + * @brief Enable asymmetrical deadtime + * @param htim TIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_EnableAsymmetricalDeadTime(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); + + SET_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE); + return HAL_OK; +} + +/** + * @brief Disable asymmetrical deadtime + * @param htim TIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_DisableAsymmetricalDeadTime(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); + + CLEAR_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE); + return HAL_OK; +} + +/** + * @brief Configures the encoder index. + * @note warning in case of encoder mode clock plus direction + * @ref TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1 or @ref TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2 + * Direction must be set to @ref TIM_ENCODERINDEX_DIRECTION_UP_DOWN + * @param htim TIM handle. + * @param sEncoderIndexConfig Encoder index configuration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigEncoderIndex(TIM_HandleTypeDef *htim, + TIMEx_EncoderIndexConfigTypeDef *sEncoderIndexConfig) +{ + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_ENCODERINDEX_POLARITY(sEncoderIndexConfig->Polarity)); + assert_param(IS_TIM_ENCODERINDEX_PRESCALER(sEncoderIndexConfig->Prescaler)); + assert_param(IS_TIM_ENCODERINDEX_FILTER(sEncoderIndexConfig->Filter)); + assert_param(IS_TIM_ENCODERINDEX_BLANKING(sEncoderIndexConfig->Blanking)); + assert_param(IS_FUNCTIONAL_STATE(sEncoderIndexConfig->FirstIndexEnable)); + assert_param(IS_TIM_ENCODERINDEX_POSITION(sEncoderIndexConfig->Position)); + assert_param(IS_TIM_ENCODERINDEX_DIRECTION(sEncoderIndexConfig->Direction)); + + /* Process Locked */ + __HAL_LOCK(htim); + + /* Configures the TIMx External Trigger (ETR) which is used as Index input */ + TIM_ETR_SetConfig(htim->Instance, + sEncoderIndexConfig->Prescaler, + sEncoderIndexConfig->Polarity, + sEncoderIndexConfig->Filter); + + /* Configures the encoder index */ + MODIFY_REG(htim->Instance->ECR, + TIM_ECR_IDIR_Msk | TIM_ECR_IBLK_Msk | TIM_ECR_FIDX_Msk | TIM_ECR_IPOS_Msk, + (sEncoderIndexConfig->Direction | + (sEncoderIndexConfig->Blanking) | + ((sEncoderIndexConfig->FirstIndexEnable == ENABLE) ? (0x1U << TIM_ECR_FIDX_Pos) : 0U) | + sEncoderIndexConfig->Position | + TIM_ECR_IE)); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Enable encoder index + * @param htim TIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_EnableEncoderIndex(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + SET_BIT(htim->Instance->ECR, TIM_ECR_IE); + return HAL_OK; +} + +/** + * @brief Disable encoder index + * @param htim TIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_DisableEncoderIndex(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + CLEAR_BIT(htim->Instance->ECR, TIM_ECR_IE); + return HAL_OK; +} + +/** + * @brief Enable encoder first index + * @param htim TIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_EnableEncoderFirstIndex(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + SET_BIT(htim->Instance->ECR, TIM_ECR_FIDX); + return HAL_OK; +} + +/** + * @brief Disable encoder first index + * @param htim TIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_DisableEncoderFirstIndex(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + CLEAR_BIT(htim->Instance->ECR, TIM_ECR_FIDX); + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions + * @brief Extended Callbacks functions + * +@verbatim + ============================================================================== + ##### Extended Callbacks functions ##### + ============================================================================== + [..] + This section provides Extended TIM callback functions: + (+) Timer Commutation callback + (+) Timer Break callback + +@endverbatim + * @{ + */ + +/** + * @brief Commutation callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_CommutCallback could be implemented in the user file + */ +} +/** + * @brief Commutation half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Break detection callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_BreakCallback could be implemented in the user file + */ +} + +/** + * @brief Break2 detection callback in non blocking mode + * @param htim: TIM handle + * @retval None + */ +__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIMEx_Break2Callback could be implemented in the user file + */ +} + +/** + * @brief Encoder index callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_EncoderIndexCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_EncoderIndexCallback could be implemented in the user file + */ +} + +/** + * @brief Direction change callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_DirectionChangeCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_DirectionChangeCallback could be implemented in the user file + */ +} + +/** + * @brief Index error callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_IndexErrorCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_IndexErrorCallback could be implemented in the user file + */ +} + +/** + * @brief Transition error callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_TransitionErrorCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_TransitionErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions + * @brief Extended Peripheral State functions + * +@verbatim + ============================================================================== + ##### Extended Peripheral State functions ##### + ============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the TIM Hall Sensor interface handle state. + * @param htim TIM Hall Sensor handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return actual state of the TIM complementary channel. + * @param htim TIM handle + * @param ChannelN TIM Complementary channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @retval TIM Complementary channel state + */ +HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim, uint32_t ChannelN) +{ + HAL_TIM_ChannelStateTypeDef channel_state; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN)); + + channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN); + + return channel_state; +} +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup TIMEx_Private_Functions TIM Extended Private Functions + * @{ + */ + +/** + * @brief TIM DMA Commutation callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->CommutationCallback(htim); +#else + HAL_TIMEx_CommutCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Commutation half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->CommutationHalfCpltCallback(htim); +#else + HAL_TIMEx_CommutHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + + +/** + * @brief TIM DMA Delay Pulse complete callback (complementary channel). + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA error callback (complementary channel) + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->ErrorCallback(htim); +#else + HAL_TIM_ErrorCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel xN. + * @param TIMx to select the TIM peripheral + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @param ChannelNState specifies the TIM Channel CCxNE bit new state. + * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable. + * @retval None + */ +static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState) +{ + uint32_t tmp; + + tmp = TIM_CCER_CC1NE << (Channel & 0xFU); /* 0xFU = 15 bits max shift */ + + /* Reset the CCxNE Bit */ + TIMx->CCER &= ~tmp; + + /* Set or reset the CCxNE Bit */ + TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0xFU)); /* 0xFU = 15 bits max shift */ +} +/** + * @} + */ + +#endif /* HAL_TIM_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_timebase_rtc_wakeup_template.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_timebase_rtc_wakeup_template.c new file mode 100644 index 0000000000..569c3d834d --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_timebase_rtc_wakeup_template.c @@ -0,0 +1,268 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_timebase_rtc_wakeup_template.c + * @author MCD Application Team + * @brief HAL time base based on the hardware RTC_WAKEUP Template. + * + * This file overrides the native HAL time base functions (defined as weak) + * to use the RTC WAKEUP for the time base generation: + * + Initializes the RTC peripheral and configures the wakeup timer to be + * incremented each 1ms + * + The wakeup feature is configured to assert an interrupt each 1ms + * + HAL_IncTick is called inside the HAL_RTCEx_WakeUpTimerEventCallback + * + HSE (default), LSE or LSI can be selected as RTC clock source + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + This file must be copied to the application folder and modified as follows: + (#) Rename it to 'stm32wbaxx_hal_timebase_rtc_wakeup.c' + (#) Add this file and the RTC HAL drivers to your project and uncomment + HAL_RTC_MODULE_ENABLED define in stm32wbaxx_hal_conf.h + + [..] + (@) HAL RTC alarm and HAL RTC wakeup drivers can not be used with low power modes: + The wake up capability of the RTC may be intrusive in case of prior low power mode + configuration requiring different wake up sources. + Application/Example behavior is no more guaranteed + (@) The stm32wbaxx_hal_timebase_tim use is recommended for the Applications/Examples + requiring low power modes + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal.h" +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @defgroup HAL_TimeBase_RTC_WKUP HAL TimeBase RTC Wakeup + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* Uncomment the line below to select the appropriate RTC Clock source for your application: + + RTC_CLOCK_SOURCE_HSE: can be selected for applications requiring timing precision. + + RTC_CLOCK_SOURCE_LSE: can be selected for applications with low constraint on timing + precision. + + RTC_CLOCK_SOURCE_LSI: can be selected for applications with low constraint on timing + precision. + */ +/* #define RTC_CLOCK_SOURCE_HSE */ +/* #define RTC_CLOCK_SOURCE_LSE */ +#define RTC_CLOCK_SOURCE_LSI + +/* The time base should be 1ms + Time base = ((RTC_ASYNCH_PREDIV + 1) * (RTC_SYNCH_PREDIV + 1)) / RTC_CLOCK + HSE as RTC clock + Time base = ((99 + 1) * (9 + 1)) / 1MHz + = 1ms + LSE as RTC clock + Time base = ((32 + 1) * (0 + 1)) / 32.768kHz + = ~1ms + LSI as RTC clock + Time base = ((31 + 1) * (0 + 1)) / 32kHz + = 1ms +*/ +#if defined (RTC_CLOCK_SOURCE_HSE) +#define RTC_ASYNCH_PREDIV 99U +#define RTC_SYNCH_PREDIV 9U +#elif defined (RTC_CLOCK_SOURCE_LSE) +#define RTC_ASYNCH_PREDIV 0U +#define RTC_SYNCH_PREDIV 32U +#elif defined (RTC_CLOCK_SOURCE_LSI) +#define RTC_ASYNCH_PREDIV 0U +#define RTC_SYNCH_PREDIV 31U +#else +#error Please select the RTC Clock source +#endif /* RTC_CLOCK_SOURCE_LSE */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +static RTC_HandleTypeDef hRTC_Handle; + +/* Private function prototypes -----------------------------------------------*/ +void RTC_IRQHandler(void); +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1U) +void TimeBase_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc); +#endif +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief This function configures the RTC_ALARMA as a time base source. + * The time source is configured to have 1ms time base with a dedicated + * Tick interrupt priority. + * @note This function is called automatically at the beginning of program after + * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). + * @param TickPriority Tick interrupt priority. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + HAL_StatusTypeDef Status; + + RCC_OscInitTypeDef RCC_OscInitStruct; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; + + /* Disable bkup domain protection */ + __HAL_RCC_PWR_CLK_ENABLE(); + HAL_PWR_EnableBkUpAccess(); + + /* Force and Release the Backup domain reset */ + __HAL_RCC_BACKUPRESET_FORCE(); + __HAL_RCC_BACKUPRESET_RELEASE(); + + /* Enable RTC Clock */ + __HAL_RCC_RTCAPB_CLK_ENABLE(); + +#if defined (RTC_CLOCK_SOURCE_LSE) + /* Configure LSE as RTC clock source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; + RCC_OscInitStruct.PLL1.PLLState = RCC_PLL_NONE; + RCC_OscInitStruct.LSEState = RCC_LSE_ON_RTC_ONLY; + PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; +#elif defined (RTC_CLOCK_SOURCE_LSI) + /* Configure LSI as RTC clock source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI; + RCC_OscInitStruct.PLL1.PLLState = RCC_PLL_NONE; + RCC_OscInitStruct.LSIState = RCC_LSI1_ON; + PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI; +#elif defined (RTC_CLOCK_SOURCE_HSE) + /* Configure HSE as RTC clock source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.PLL1.PLLState = RCC_PLL_NONE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_HSE_DIV32; +#else +#error Please select the RTC Clock source +#endif /* RTC_CLOCK_SOURCE_LSE */ + + Status = HAL_RCC_OscConfig(&RCC_OscInitStruct); + + if (Status == HAL_OK) + { + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC; + Status = HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); + } + + if (Status == HAL_OK) + { + hRTC_Handle.Instance = RTC; + hRTC_Handle.Init.HourFormat = RTC_HOURFORMAT_24; + hRTC_Handle.Init.AsynchPrediv = RTC_ASYNCH_PREDIV; + hRTC_Handle.Init.SynchPrediv = RTC_SYNCH_PREDIV; + hRTC_Handle.Init.OutPut = RTC_OUTPUT_DISABLE; + hRTC_Handle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH; + hRTC_Handle.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN; + hRTC_Handle.Init.BinMode = RTC_BINARY_NONE; + + Status = HAL_RTC_Init(&hRTC_Handle); + +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1U) + HAL_RTC_RegisterCallback(&hRTC_Handle, HAL_RTC_WAKEUPTIMER_EVENT_CB_ID, TimeBase_RTCEx_WakeUpTimerEventCallback); +#endif + } + + if (Status == HAL_OK) + { + Status = HAL_RTCEx_SetWakeUpTimer_IT(&hRTC_Handle, 0, RTC_WAKEUPCLOCK_CK_SPRE_16BITS, 0); + } + + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + { + /* Enable the RTC global Interrupt */ + HAL_NVIC_SetPriority(RTC_IRQn, TickPriority, 0U); + uwTickPrio = TickPriority; + } + else + { + Status = HAL_ERROR; + } + + HAL_NVIC_EnableIRQ(RTC_IRQn); + + return Status; +} + +/** + * @brief Suspend Tick increment. + * @note Disable the tick increment by disabling RTC_WKUP interrupt. + * @retval None + */ +void HAL_SuspendTick(void) +{ + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle); + /* Disable WAKE UP TIMER Interrupt */ + __HAL_RTC_WAKEUPTIMER_DISABLE_IT(&hRTC_Handle, RTC_IT_WUT); + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle); +} + +/** + * @brief Resume Tick increment. + * @note Enable the tick increment by Enabling RTC_WKUP interrupt. + * @retval None + */ +void HAL_ResumeTick(void) +{ + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle); + /* Enable WAKE UP TIMER interrupt */ + __HAL_RTC_WAKEUPTIMER_ENABLE_IT(&hRTC_Handle, RTC_IT_WUT); + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle); +} + +/** + * @brief Wake Up Timer Event Callback in non blocking mode + * @note This function is called when RTC_WKUP interrupt took place, inside + * RTC_WKUP_IRQHandler(). It makes a direct call to HAL_IncTick() to increment + * a global variable "uwTick" used as application time base. + * @param hrtc RTC handle + * @retval None + */ +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1U) +void TimeBase_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc) +#else +void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc) +#endif +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + + HAL_IncTick(); +} + +/** + * @brief This function handles WAKE UP TIMER interrupt request. + * @retval None + */ +void RTC_IRQHandler(void) +{ + HAL_RTCEx_WakeUpTimerIRQHandler(&hRTC_Handle); +} + +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_timebase_tim_template.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_timebase_tim_template.c new file mode 100644 index 0000000000..78fdd37467 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_timebase_tim_template.c @@ -0,0 +1,205 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_timebase_tim_template.c + * @author MCD Application Team + * @brief HAL time base based on the hardware TIM. + * + * This file overrides the native HAL time base functions (defined as weak) + * the TIM time base: + * + Initializes the TIM peripheral to generate a Period elapsed Event each 1ms + * + HAL_IncTick is called inside HAL_TIM_PeriodElapsedCallback ie each 1ms + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + This file must be copied to the application folder and modified as follows: + (#) Rename it to 'stm32wbaxx_hal_timebase_tim.c' + (#) Add this file and the TIM HAL drivers to your project and uncomment + HAL_TIM_MODULE_ENABLED define in stm32wbaxx_hal_conf.h + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @addtogroup HAL_TimeBase + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define TIM_CNT_FREQ 1000000U /* Timer frequency counter : 1 MHz */ +#define TIM_FREQ 1000U /* Timer frequency : 1 kHz => to have 1 ms interrupt */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +static TIM_HandleTypeDef TimHandle; + +/* Private function prototypes -----------------------------------------------*/ +void TIM16_IRQHandler(void); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1U) +void TimeBase_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); +#endif +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief This function configures the TIM16 as a time base source. + * The time source is configured to have 1ms time base with a dedicated + * Tick interrupt priority. + * @note This function is called automatically at the beginning of program after + * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). + * @param TickPriority Tick interrupt priority. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + RCC_ClkInitTypeDef clkconfig; + uint32_t uwTimclock, uwAPB2Prescaler; + uint32_t uwPrescalerValue; + uint32_t pFLatency; + HAL_StatusTypeDef Status; + + /* Enable TIM16 clock */ + __HAL_RCC_TIM16_CLK_ENABLE(); + + /* Get clock configuration */ + HAL_RCC_GetClockConfig(&clkconfig, &pFLatency); + + /* Get APB2 prescaler */ + uwAPB2Prescaler = clkconfig.APB2CLKDivider; + + /* Compute TIM16 clock */ + if (uwAPB2Prescaler == RCC_HCLK_DIV1) + { + uwTimclock = HAL_RCC_GetPCLK2Freq(); + } + else + { + uwTimclock = 2UL * HAL_RCC_GetPCLK2Freq(); + } + + /* Compute the prescaler value to have TIM16 counter clock equal to TIM_CNT_FREQ */ + uwPrescalerValue = (uint32_t)((uwTimclock / TIM_CNT_FREQ) - 1U); + + /* Initialize TIM16 */ + TimHandle.Instance = TIM16; + + /* Initialize TIMx peripheral as follow: + + Period = [(TIM_CNT_FREQ/TIM_FREQ) - 1]. to have a (1/TIM_FREQ) s time base. + + Prescaler = (uwTimclock/TIM_CNT_FREQ - 1) to have a TIM_CNT_FREQ counter clock. + + ClockDivision = 0 + + Counter direction = Up + */ + TimHandle.Init.Period = (TIM_CNT_FREQ / TIM_FREQ) - 1U; + TimHandle.Init.Prescaler = uwPrescalerValue; + TimHandle.Init.ClockDivision = 0; + TimHandle.Init.CounterMode = TIM_COUNTERMODE_UP; + Status = HAL_TIM_Base_Init(&TimHandle); + if (Status == HAL_OK) + { + /* Start the TIM time Base generation in interrupt mode */ + Status = HAL_TIM_Base_Start_IT(&TimHandle); + if (Status == HAL_OK) + { + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + { + /* Enable the TIM16 global Interrupt */ + HAL_NVIC_SetPriority(TIM16_IRQn, TickPriority, 0); + uwTickPrio = TickPriority; + } + else + { + Status = HAL_ERROR; + } + } + } +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1U) + HAL_TIM_RegisterCallback(&TimHandle, HAL_TIM_PERIOD_ELAPSED_CB_ID, TimeBase_TIM_PeriodElapsedCallback); +#endif + + HAL_NVIC_EnableIRQ(TIM16_IRQn); + + /* Return function Status */ + return Status; +} + +/** + * @brief Suspend Tick increment. + * @note Disable the tick increment by disabling TIM16 update interrupt. + * @param None + * @retval None + */ +void HAL_SuspendTick(void) +{ + /* Disable TIM16 update Interrupt */ + __HAL_TIM_DISABLE_IT(&TimHandle, TIM_IT_UPDATE); +} + +/** + * @brief Resume Tick increment. + * @note Enable the tick increment by Enabling TIM16 update interrupt. + * @param None + * @retval None + */ +void HAL_ResumeTick(void) +{ + /* Enable TIM16 Update interrupt */ + __HAL_TIM_ENABLE_IT(&TimHandle, TIM_IT_UPDATE); +} + +/** + * @brief Period elapsed callback in non blocking mode + * @note This function is called when TIM2 interrupt took place, inside + * HAL_TIM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment + * a global variable "uwTick" used as application time base. + * @param htim TIM handle + * @retval None + */ +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1U) +void TimeBase_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) +#else +void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) +#endif +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + HAL_IncTick(); +} + +/** + * @brief This function handles TIM interrupt request. + * @param None + * @retval None + */ +void TIM16_IRQHandler(void) +{ + HAL_TIM_IRQHandler(&TimHandle); +} + +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_tsc.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_tsc.c new file mode 100644 index 0000000000..d484dc17e7 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_tsc.c @@ -0,0 +1,1111 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_tsc.c + * @author MCD Application Team + * @brief This file provides firmware functions to manage the following + * functionalities of the Touch Sensing Controller (TSC) peripheral: + * + Initialization and De-initialization + * + Channel IOs, Shield IOs and Sampling IOs configuration + * + Start and Stop an acquisition + * + Read acquisition result + * + Interrupts and flags management + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim +================================================================================ + ##### TSC specific features ##### +================================================================================ + [..] + (#) Proven and robust surface charge transfer acquisition principle + + (#) Supports up to 3 capacitive sensing channels per group + + (#) Capacitive sensing channels can be acquired in parallel offering a very good + response time + + (#) Spread spectrum feature to improve system robustness in noisy environments + + (#) Full hardware management of the charge transfer acquisition sequence + + (#) Programmable charge transfer frequency + + (#) Programmable sampling capacitor I/O pin + + (#) Programmable channel I/O pin + + (#) Programmable max count value to avoid long acquisition when a channel is faulty + + (#) Dedicated end of acquisition and max count error flags with interrupt capability + + (#) One sampling capacitor for up to 3 capacitive sensing channels to reduce the system + components + + (#) Compatible with proximity, touchkey, linear and rotary touch sensor implementation + + ##### How to use this driver ##### +================================================================================ + [..] + (#) Enable the TSC interface clock using __HAL_RCC_TSC_CLK_ENABLE() macro. + + (#) GPIO pins configuration + (++) Enable the clock for the TSC GPIOs using __HAL_RCC_GPIOx_CLK_ENABLE() macro. + (++) Configure the TSC pins used as sampling IOs in alternate function output Open-Drain mode, + and TSC pins used as channel/shield IOs in alternate function output Push-Pull mode + using HAL_GPIO_Init() function. + + (#) Interrupts configuration + (++) Configure the NVIC (if the interrupt model is used) using HAL_NVIC_SetPriority() + and HAL_NVIC_EnableIRQ() and function. + + (#) TSC configuration + (++) Configure all TSC parameters and used TSC IOs using HAL_TSC_Init() function. + + [..] TSC peripheral alternate functions are mapped on AF9. + + *** Acquisition sequence *** + =================================== + [..] + (+) Discharge all IOs using HAL_TSC_IODischarge() function. + (+) Wait a certain time allowing a good discharge of all capacitors. This delay depends + of the sampling capacitor and electrodes design. + (+) Select the channel IOs to be acquired using HAL_TSC_IOConfig() function. + (+) Launch the acquisition using either HAL_TSC_Start() or HAL_TSC_Start_IT() function. + If the synchronized mode is selected, the acquisition will start as soon as the signal + is received on the synchro pin. + (+) Wait the end of acquisition using either HAL_TSC_PollForAcquisition() or + HAL_TSC_GetState() function or using WFI instruction for example. + (+) Check the group acquisition status using HAL_TSC_GroupGetStatus() function. + (+) Read the acquisition value using HAL_TSC_GroupGetValue() function. + + *** Callback registration *** + ============================================= + + [..] + The compilation flag USE_HAL_TSC_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use Functions HAL_TSC_RegisterCallback() to register an interrupt callback. + + [..] + Function HAL_TSC_RegisterCallback() allows to register following callbacks: + (+) ConvCpltCallback : callback for conversion complete process. + (+) ErrorCallback : callback for error detection. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + [..] + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + [..] + Use function HAL_TSC_UnRegisterCallback to reset a callback to the default + weak function. + HAL_TSC_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + [..] + This function allows to reset following callbacks: + (+) ConvCpltCallback : callback for conversion complete process. + (+) ErrorCallback : callback for error detection. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + + [..] + By default, after the HAL_TSC_Init() and when the state is HAL_TSC_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples HAL_TSC_ConvCpltCallback(), HAL_TSC_ErrorCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak functions in the HAL_TSC_Init()/ HAL_TSC_DeInit() only when + these callbacks are null (not registered beforehand). + If MspInit or MspDeInit are not null, the HAL_TSC_Init()/ HAL_TSC_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + + [..] + Callbacks can be registered/unregistered in HAL_TSC_STATE_READY state only. + Exception done MspInit/MspDeInit functions that can be registered/unregistered + in HAL_TSC_STATE_READY or HAL_TSC_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + Then, the user first registers the MspInit/MspDeInit user callbacks + using HAL_TSC_RegisterCallback() before calling HAL_TSC_DeInit() + or HAL_TSC_Init() function. + + [..] + When the compilation flag USE_HAL_TSC_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + @endverbatim + ****************************************************************************** + + Table 1. IOs for the STM32WBAxx devices + +--------------------------------+ + | IOs | TSC functions | + |--------------|-----------------| + | PA8 (AF9) | TSC_G1_IO1 | + | PA7 (AF9) | TSC_G1_IO2 | + | PA6 (AF9) | TSC_G1_IO3 | + | PA5 (AF9) | TSC_G1_IO4 | + |--------------|-----------------| + | PA1 (AF9) | TSC_G2_IO1 | + | PA0 (AF9) | TSC_G2_IO2 | + | PB9 (AF9) | TSC_G2_IO3 | + | PB8 (AF9) | TSC_G2_IO4 | + |--------------|-----------------| + | PB4 (AF9) | TSC_G3_IO1 | + | PB3 (AF9) | TSC_G3_IO2 | + | PA15 (AF9) | TSC_G3_IO3 | + | PA12 (AF9) | TSC_G3_IO4 | + |--------------|-----------------| + | PA4 (AF9) | TSC_G4_IO1 | + | PA3 (AF9) | TSC_G4_IO2 | + | PB10 (AF9) | TSC_G4_IO3 | + | PA2 (AF9) | TSC_G4_IO4 | + |--------------|-----------------| + | PC13 (AF9) | TSC_G5_IO1 | + | PB7 (AF9) | TSC_G5_IO2 | + | PB6 (AF9) | TSC_G5_IO3 | + | PB5 (AF9) | TSC_G5_IO4 | + |--------------|-----------------| + | PB14 (AF9) | TSC_G6_IO1 | + | PB13 (AF9) | TSC_G6_IO2 | + |--------------|-----------------| + | PB12 (AF9) | TSC_SYNC | + +--------------------------------+ + + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @defgroup TSC TSC + * @brief HAL TSC module driver + * @{ + */ + +#ifdef HAL_TSC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static uint32_t TSC_extract_groups(uint32_t iomask); + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup TSC_Exported_Functions TSC Exported Functions + * @{ + */ + +/** @defgroup TSC_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the TSC. + (+) De-initialize the TSC. +@endverbatim + * @{ + */ + +/** + * @brief Initialize the TSC peripheral according to the specified parameters + * in the TSC_InitTypeDef structure and initialize the associated handle. + * @param htsc TSC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef *htsc) +{ + /* Check TSC handle allocation */ + if (htsc == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance)); + assert_param(IS_TSC_CTPH(htsc->Init.CTPulseHighLength)); + assert_param(IS_TSC_CTPL(htsc->Init.CTPulseLowLength)); + assert_param(IS_TSC_SS(htsc->Init.SpreadSpectrum)); + assert_param(IS_TSC_SSD(htsc->Init.SpreadSpectrumDeviation)); + assert_param(IS_TSC_SS_PRESC(htsc->Init.SpreadSpectrumPrescaler)); + assert_param(IS_TSC_PG_PRESC(htsc->Init.PulseGeneratorPrescaler)); + assert_param(IS_TSC_PG_PRESC_VS_CTPL(htsc->Init.PulseGeneratorPrescaler, htsc->Init.CTPulseLowLength)); + assert_param(IS_TSC_MCV(htsc->Init.MaxCountValue)); + assert_param(IS_TSC_IODEF(htsc->Init.IODefaultMode)); + assert_param(IS_TSC_SYNC_POL(htsc->Init.SynchroPinPolarity)); + assert_param(IS_TSC_ACQ_MODE(htsc->Init.AcquisitionMode)); + assert_param(IS_TSC_MCE_IT(htsc->Init.MaxCountInterrupt)); + assert_param(IS_TSC_GROUP(htsc->Init.ChannelIOs)); + assert_param(IS_TSC_GROUP(htsc->Init.ShieldIOs)); + assert_param(IS_TSC_GROUP(htsc->Init.SamplingIOs)); + + if (htsc->State == HAL_TSC_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htsc->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) + /* Init the TSC Callback settings */ + htsc->ConvCpltCallback = HAL_TSC_ConvCpltCallback; /* Legacy weak ConvCpltCallback */ + htsc->ErrorCallback = HAL_TSC_ErrorCallback; /* Legacy weak ErrorCallback */ + + if (htsc->MspInitCallback == NULL) + { + htsc->MspInitCallback = HAL_TSC_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + htsc->MspInitCallback(htsc); +#else + /* Init the low level hardware : GPIO, CLOCK, CORTEX */ + HAL_TSC_MspInit(htsc); +#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ + } + + /* Initialize the TSC state */ + htsc->State = HAL_TSC_STATE_BUSY; + + /*--------------------------------------------------------------------------*/ + /* Set TSC parameters */ + + /* Enable TSC */ + htsc->Instance->CR = TSC_CR_TSCE; + + /* Set all functions */ + htsc->Instance->CR |= (htsc->Init.CTPulseHighLength | + htsc->Init.CTPulseLowLength | + (htsc->Init.SpreadSpectrumDeviation << TSC_CR_SSD_Pos) | + htsc->Init.SpreadSpectrumPrescaler | + htsc->Init.PulseGeneratorPrescaler | + htsc->Init.MaxCountValue | + htsc->Init.SynchroPinPolarity | + htsc->Init.AcquisitionMode); + + /* Spread spectrum */ + if (htsc->Init.SpreadSpectrum == ENABLE) + { + htsc->Instance->CR |= TSC_CR_SSE; + } + + /* Disable Schmitt trigger hysteresis on all used TSC IOs */ + htsc->Instance->IOHCR = (~(htsc->Init.ChannelIOs | htsc->Init.ShieldIOs | htsc->Init.SamplingIOs)); + + /* Set channel and shield IOs */ + htsc->Instance->IOCCR = (htsc->Init.ChannelIOs | htsc->Init.ShieldIOs); + + /* Set sampling IOs */ + htsc->Instance->IOSCR = htsc->Init.SamplingIOs; + + /* Set the groups to be acquired */ + htsc->Instance->IOGCSR = TSC_extract_groups(htsc->Init.ChannelIOs); + + /* Disable interrupts */ + htsc->Instance->IER &= (~(TSC_IT_EOA | TSC_IT_MCE)); + + /* Clear flags */ + htsc->Instance->ICR = (TSC_FLAG_EOA | TSC_FLAG_MCE); + + /*--------------------------------------------------------------------------*/ + + /* Initialize the TSC state */ + htsc->State = HAL_TSC_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Deinitialize the TSC peripheral registers to their default reset values. + * @param htsc TSC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef *htsc) +{ + /* Check TSC handle allocation */ + if (htsc == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance)); + + /* Change TSC state */ + htsc->State = HAL_TSC_STATE_BUSY; + +#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) + if (htsc->MspDeInitCallback == NULL) + { + htsc->MspDeInitCallback = HAL_TSC_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + htsc->MspDeInitCallback(htsc); +#else + /* DeInit the low level hardware */ + HAL_TSC_MspDeInit(htsc); +#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ + + /* Change TSC state */ + htsc->State = HAL_TSC_STATE_RESET; + + /* Process unlocked */ + __HAL_UNLOCK(htsc); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initialize the TSC MSP. + * @param htsc Pointer to a TSC_HandleTypeDef structure that contains + * the configuration information for the specified TSC. + * @retval None + */ +__weak void HAL_TSC_MspInit(TSC_HandleTypeDef *htsc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htsc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TSC_MspInit could be implemented in the user file. + */ +} + +/** + * @brief DeInitialize the TSC MSP. + * @param htsc Pointer to a TSC_HandleTypeDef structure that contains + * the configuration information for the specified TSC. + * @retval None + */ +__weak void HAL_TSC_MspDeInit(TSC_HandleTypeDef *htsc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htsc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TSC_MspDeInit could be implemented in the user file. + */ +} + +#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User TSC Callback + * To be used instead of the weak predefined callback + * @param htsc Pointer to a TSC_HandleTypeDef structure that contains + * the configuration information for the specified TSC. + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_TSC_CONV_COMPLETE_CB_ID Conversion completed callback ID + * @arg @ref HAL_TSC_ERROR_CB_ID Error callback ID + * @arg @ref HAL_TSC_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_TSC_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TSC_RegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID, + pTSC_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + htsc->ErrorCode |= HAL_TSC_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(htsc); + + if (HAL_TSC_STATE_READY == htsc->State) + { + switch (CallbackID) + { + case HAL_TSC_CONV_COMPLETE_CB_ID : + htsc->ConvCpltCallback = pCallback; + break; + + case HAL_TSC_ERROR_CB_ID : + htsc->ErrorCallback = pCallback; + break; + + case HAL_TSC_MSPINIT_CB_ID : + htsc->MspInitCallback = pCallback; + break; + + case HAL_TSC_MSPDEINIT_CB_ID : + htsc->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + htsc->ErrorCode |= HAL_TSC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_TSC_STATE_RESET == htsc->State) + { + switch (CallbackID) + { + case HAL_TSC_MSPINIT_CB_ID : + htsc->MspInitCallback = pCallback; + break; + + case HAL_TSC_MSPDEINIT_CB_ID : + htsc->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + htsc->ErrorCode |= HAL_TSC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + htsc->ErrorCode |= HAL_TSC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(htsc); + return status; +} + +/** + * @brief Unregister an TSC Callback + * TSC callback is redirected to the weak predefined callback + * @param htsc Pointer to a TSC_HandleTypeDef structure that contains + * the configuration information for the specified TSC. + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * This parameter can be one of the following values: + * @arg @ref HAL_TSC_CONV_COMPLETE_CB_ID Conversion completed callback ID + * @arg @ref HAL_TSC_ERROR_CB_ID Error callback ID + * @arg @ref HAL_TSC_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_TSC_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TSC_UnRegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(htsc); + + if (HAL_TSC_STATE_READY == htsc->State) + { + switch (CallbackID) + { + case HAL_TSC_CONV_COMPLETE_CB_ID : + htsc->ConvCpltCallback = HAL_TSC_ConvCpltCallback; /* Legacy weak ConvCpltCallback */ + break; + + case HAL_TSC_ERROR_CB_ID : + htsc->ErrorCallback = HAL_TSC_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_TSC_MSPINIT_CB_ID : + htsc->MspInitCallback = HAL_TSC_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_TSC_MSPDEINIT_CB_ID : + htsc->MspDeInitCallback = HAL_TSC_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + htsc->ErrorCode |= HAL_TSC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_TSC_STATE_RESET == htsc->State) + { + switch (CallbackID) + { + case HAL_TSC_MSPINIT_CB_ID : + htsc->MspInitCallback = HAL_TSC_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_TSC_MSPDEINIT_CB_ID : + htsc->MspDeInitCallback = HAL_TSC_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + htsc->ErrorCode |= HAL_TSC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + htsc->ErrorCode |= HAL_TSC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(htsc); + return status; +} + +#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup TSC_Exported_Functions_Group2 Input and Output operation functions + * @brief Input and Output operation functions + * +@verbatim + =============================================================================== + ##### IO Operation functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Start acquisition in polling mode. + (+) Start acquisition in interrupt mode. + (+) Stop conversion in polling mode. + (+) Stop conversion in interrupt mode. + (+) Poll for acquisition completed. + (+) Get group acquisition status. + (+) Get group acquisition value. +@endverbatim + * @{ + */ + +/** + * @brief Start the acquisition. + * @param htsc Pointer to a TSC_HandleTypeDef structure that contains + * the configuration information for the specified TSC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef *htsc) +{ + /* Check the parameters */ + assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance)); + + /* Process locked */ + __HAL_LOCK(htsc); + + /* Change TSC state */ + htsc->State = HAL_TSC_STATE_BUSY; + + /* Clear interrupts */ + __HAL_TSC_DISABLE_IT(htsc, (TSC_IT_EOA | TSC_IT_MCE)); + + /* Clear flags */ + __HAL_TSC_CLEAR_FLAG(htsc, (TSC_FLAG_EOA | TSC_FLAG_MCE)); + + /* Set touch sensing IOs not acquired to the specified IODefaultMode */ + if (htsc->Init.IODefaultMode == TSC_IODEF_OUT_PP_LOW) + { + __HAL_TSC_SET_IODEF_OUTPPLOW(htsc); + } + else + { + __HAL_TSC_SET_IODEF_INFLOAT(htsc); + } + + /* Launch the acquisition */ + __HAL_TSC_START_ACQ(htsc); + + /* Process unlocked */ + __HAL_UNLOCK(htsc); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Start the acquisition in interrupt mode. + * @param htsc Pointer to a TSC_HandleTypeDef structure that contains + * the configuration information for the specified TSC. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef *htsc) +{ + /* Check the parameters */ + assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance)); + assert_param(IS_TSC_MCE_IT(htsc->Init.MaxCountInterrupt)); + + /* Process locked */ + __HAL_LOCK(htsc); + + /* Change TSC state */ + htsc->State = HAL_TSC_STATE_BUSY; + + /* Enable end of acquisition interrupt */ + __HAL_TSC_ENABLE_IT(htsc, TSC_IT_EOA); + + /* Enable max count error interrupt (optional) */ + if (htsc->Init.MaxCountInterrupt == ENABLE) + { + __HAL_TSC_ENABLE_IT(htsc, TSC_IT_MCE); + } + else + { + __HAL_TSC_DISABLE_IT(htsc, TSC_IT_MCE); + } + + /* Clear flags */ + __HAL_TSC_CLEAR_FLAG(htsc, (TSC_FLAG_EOA | TSC_FLAG_MCE)); + + /* Set touch sensing IOs not acquired to the specified IODefaultMode */ + if (htsc->Init.IODefaultMode == TSC_IODEF_OUT_PP_LOW) + { + __HAL_TSC_SET_IODEF_OUTPPLOW(htsc); + } + else + { + __HAL_TSC_SET_IODEF_INFLOAT(htsc); + } + + /* Launch the acquisition */ + __HAL_TSC_START_ACQ(htsc); + + /* Process unlocked */ + __HAL_UNLOCK(htsc); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stop the acquisition previously launched in polling mode. + * @param htsc Pointer to a TSC_HandleTypeDef structure that contains + * the configuration information for the specified TSC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef *htsc) +{ + /* Check the parameters */ + assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance)); + + /* Process locked */ + __HAL_LOCK(htsc); + + /* Stop the acquisition */ + __HAL_TSC_STOP_ACQ(htsc); + + /* Set touch sensing IOs in low power mode (output push-pull) */ + __HAL_TSC_SET_IODEF_OUTPPLOW(htsc); + + /* Clear flags */ + __HAL_TSC_CLEAR_FLAG(htsc, (TSC_FLAG_EOA | TSC_FLAG_MCE)); + + /* Change TSC state */ + htsc->State = HAL_TSC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(htsc); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stop the acquisition previously launched in interrupt mode. + * @param htsc Pointer to a TSC_HandleTypeDef structure that contains + * the configuration information for the specified TSC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef *htsc) +{ + /* Check the parameters */ + assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance)); + + /* Process locked */ + __HAL_LOCK(htsc); + + /* Stop the acquisition */ + __HAL_TSC_STOP_ACQ(htsc); + + /* Set touch sensing IOs in low power mode (output push-pull) */ + __HAL_TSC_SET_IODEF_OUTPPLOW(htsc); + + /* Disable interrupts */ + __HAL_TSC_DISABLE_IT(htsc, (TSC_IT_EOA | TSC_IT_MCE)); + + /* Clear flags */ + __HAL_TSC_CLEAR_FLAG(htsc, (TSC_FLAG_EOA | TSC_FLAG_MCE)); + + /* Change TSC state */ + htsc->State = HAL_TSC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(htsc); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Start acquisition and wait until completion. + * @note There is no need of a timeout parameter as the max count error is already + * managed by the TSC peripheral. + * @param htsc Pointer to a TSC_HandleTypeDef structure that contains + * the configuration information for the specified TSC. + * @retval HAL state + */ +HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef *htsc) +{ + /* Check the parameters */ + assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance)); + + /* Process locked */ + __HAL_LOCK(htsc); + + /* Check end of acquisition */ + while (HAL_TSC_GetState(htsc) == HAL_TSC_STATE_BUSY) + { + /* The timeout (max count error) is managed by the TSC peripheral itself. */ + } + + /* Process unlocked */ + __HAL_UNLOCK(htsc); + + return HAL_OK; +} + +/** + * @brief Get the acquisition status for a group. + * @param htsc Pointer to a TSC_HandleTypeDef structure that contains + * the configuration information for the specified TSC. + * @param gx_index Index of the group + * @retval Group status + */ +TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(const TSC_HandleTypeDef *htsc, uint32_t gx_index) +{ + /* Check the parameters */ + assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance)); + assert_param(IS_TSC_GROUP_INDEX(gx_index)); + + /* Return the group status */ + return (__HAL_TSC_GET_GROUP_STATUS(htsc, gx_index)); +} + +/** + * @brief Get the acquisition measure for a group. + * @param htsc Pointer to a TSC_HandleTypeDef structure that contains + * the configuration information for the specified TSC. + * @param gx_index Index of the group + * @retval Acquisition measure + */ +uint32_t HAL_TSC_GroupGetValue(const TSC_HandleTypeDef *htsc, uint32_t gx_index) +{ + /* Check the parameters */ + assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance)); + assert_param(IS_TSC_GROUP_INDEX(gx_index)); + + /* Return the group acquisition counter */ + return htsc->Instance->IOGXCR[gx_index]; +} + +/** + * @} + */ + +/** @defgroup TSC_Exported_Functions_Group3 Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure TSC IOs + (+) Discharge TSC IOs +@endverbatim + * @{ + */ + +/** + * @brief Configure TSC IOs. + * @param htsc Pointer to a TSC_HandleTypeDef structure that contains + * the configuration information for the specified TSC. + * @param config Pointer to the configuration structure. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef *htsc, const TSC_IOConfigTypeDef *config) +{ + /* Check the parameters */ + assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance)); + assert_param(IS_TSC_GROUP(config->ChannelIOs)); + assert_param(IS_TSC_GROUP(config->ShieldIOs)); + assert_param(IS_TSC_GROUP(config->SamplingIOs)); + + /* Process locked */ + __HAL_LOCK(htsc); + + /* Stop acquisition */ + __HAL_TSC_STOP_ACQ(htsc); + + /* Disable Schmitt trigger hysteresis on all used TSC IOs */ + htsc->Instance->IOHCR = (~(config->ChannelIOs | config->ShieldIOs | config->SamplingIOs)); + + /* Set channel and shield IOs */ + htsc->Instance->IOCCR = (config->ChannelIOs | config->ShieldIOs); + + /* Set sampling IOs */ + htsc->Instance->IOSCR = config->SamplingIOs; + + /* Set groups to be acquired */ + htsc->Instance->IOGCSR = TSC_extract_groups(config->ChannelIOs); + + /* Process unlocked */ + __HAL_UNLOCK(htsc); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Discharge TSC IOs. + * @param htsc Pointer to a TSC_HandleTypeDef structure that contains + * the configuration information for the specified TSC. + * @param choice This parameter can be set to ENABLE or DISABLE. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef *htsc, FunctionalState choice) +{ + /* Check the parameters */ + assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance)); + + /* Process locked */ + __HAL_LOCK(htsc); + + if (choice == ENABLE) + { + __HAL_TSC_SET_IODEF_OUTPPLOW(htsc); + } + else + { + __HAL_TSC_SET_IODEF_INFLOAT(htsc); + } + + /* Process unlocked */ + __HAL_UNLOCK(htsc); + + /* Return the group acquisition counter */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TSC_Exported_Functions_Group4 Peripheral State and Errors functions + * @brief Peripheral State and Errors functions + * +@verbatim + =============================================================================== + ##### State and Errors functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Get TSC state. + +@endverbatim + * @{ + */ + +/** + * @brief Return the TSC handle state. + * @param htsc Pointer to a TSC_HandleTypeDef structure that contains + * the configuration information for the specified TSC. + * @retval HAL state + */ +HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef *htsc) +{ + /* Check the parameters */ + assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance)); + + if (htsc->State == HAL_TSC_STATE_BUSY) + { + /* Check end of acquisition flag */ + if (__HAL_TSC_GET_FLAG(htsc, TSC_FLAG_EOA) != RESET) + { + /* Check max count error flag */ + if (__HAL_TSC_GET_FLAG(htsc, TSC_FLAG_MCE) != RESET) + { + /* Change TSC state */ + htsc->State = HAL_TSC_STATE_ERROR; + } + else + { + /* Change TSC state */ + htsc->State = HAL_TSC_STATE_READY; + } + } + } + + /* Return TSC state */ + return htsc->State; +} + +/** + * @} + */ + +/** @defgroup TSC_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks + * @{ + */ + +/** + * @brief Handle TSC interrupt request. + * @param htsc Pointer to a TSC_HandleTypeDef structure that contains + * the configuration information for the specified TSC. + * @retval None + */ +void HAL_TSC_IRQHandler(TSC_HandleTypeDef *htsc) +{ + /* Check the parameters */ + assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance)); + + /* Check if the end of acquisition occurred */ + if (__HAL_TSC_GET_FLAG(htsc, TSC_FLAG_EOA) != RESET) + { + /* Clear EOA flag */ + __HAL_TSC_CLEAR_FLAG(htsc, TSC_FLAG_EOA); + } + + /* Check if max count error occurred */ + if (__HAL_TSC_GET_FLAG(htsc, TSC_FLAG_MCE) != RESET) + { + /* Clear MCE flag */ + __HAL_TSC_CLEAR_FLAG(htsc, TSC_FLAG_MCE); + /* Change TSC state */ + htsc->State = HAL_TSC_STATE_ERROR; +#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) + htsc->ErrorCallback(htsc); +#else + /* Conversion completed callback */ + HAL_TSC_ErrorCallback(htsc); +#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ + } + else + { + /* Change TSC state */ + htsc->State = HAL_TSC_STATE_READY; +#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1) + htsc->ConvCpltCallback(htsc); +#else + /* Conversion completed callback */ + HAL_TSC_ConvCpltCallback(htsc); +#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */ + } +} + +/** + * @brief Acquisition completed callback in non-blocking mode. + * @param htsc Pointer to a TSC_HandleTypeDef structure that contains + * the configuration information for the specified TSC. + * @retval None + */ +__weak void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef *htsc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htsc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TSC_ConvCpltCallback could be implemented in the user file. + */ +} + +/** + * @brief Error callback in non-blocking mode. + * @param htsc Pointer to a TSC_HandleTypeDef structure that contains + * the configuration information for the specified TSC. + * @retval None + */ +__weak void HAL_TSC_ErrorCallback(TSC_HandleTypeDef *htsc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htsc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TSC_ErrorCallback could be implemented in the user file. + */ +} + +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup TSC_Private_Functions TSC Private Functions + * @{ + */ + +/** + * @brief Utility function used to set the acquired groups mask. + * @param iomask Channels IOs mask + * @retval Acquired groups mask + */ +static uint32_t TSC_extract_groups(uint32_t iomask) +{ + uint32_t groups = 0UL; + uint32_t idx; + + for (idx = 0UL; idx < (uint32_t)TSC_NB_OF_GROUPS; idx++) + { + if ((iomask & (0x0FUL << (idx * 4UL))) != 0UL) + { + groups |= (1UL << idx); + } + } + + return groups; +} + +/** + * @} + */ + +#endif /* HAL_TSC_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_uart.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_uart.c new file mode 100644 index 0000000000..ba0d43cc7a --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_uart.c @@ -0,0 +1,4804 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_uart.c + * @author MCD Application Team + * @brief UART HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + The UART HAL driver can be used as follows: + + (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart). + (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API: + (++) Enable the USARTx interface clock. + (++) UART pins configuration: + (+++) Enable the clock for the UART GPIOs. + (+++) Configure these UART pins as alternate function pull-up. + (++) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT() + and HAL_UART_Receive_IT() APIs): + (+++) Configure the USARTx interrupt priority. + (+++) Enable the NVIC USART IRQ handle. + (++) UART interrupts handling: + -@@- The specific UART interrupts (Transmission complete interrupt, + RXNE interrupt, RX/TX FIFOs related interrupts and Error Interrupts) + are managed using the macros __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() + inside the transmit and receive processes. + (++) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA() + and HAL_UART_Receive_DMA() APIs): + (+++) Declare a DMA handle structure for the Tx/Rx channel. + (+++) Enable the DMAx interface clock. + (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. + (+++) Configure the DMA Tx/Rx channel. + (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle. + (+++) Configure the priority and enable the NVIC for the transfer complete + interrupt on the DMA Tx/Rx channel. + + (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Prescaler value , Hardware + flow control and Mode (Receiver/Transmitter) in the huart handle Init structure. + + (#) If required, program UART advanced features (TX/RX pins swap, auto Baud rate detection,...) + in the huart handle AdvancedInit structure. + + (#) For the UART asynchronous mode, initialize the UART registers by calling + the HAL_UART_Init() API. + + (#) For the UART Half duplex mode, initialize the UART registers by calling + the HAL_HalfDuplex_Init() API. + + (#) For the UART LIN (Local Interconnection Network) mode, initialize the UART registers + by calling the HAL_LIN_Init() API. + + (#) For the UART Multiprocessor mode, initialize the UART registers + by calling the HAL_MultiProcessor_Init() API. + + (#) For the UART RS485 Driver Enabled mode, initialize the UART registers + by calling the HAL_RS485Ex_Init() API. + + [..] + (@) These API's (HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), + also configure the low level Hardware GPIO, CLOCK, CORTEX...etc) by + calling the customized HAL_UART_MspInit() API. + + ##### Callback registration ##### + ================================== + + [..] + The compilation define USE_HAL_UART_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + [..] + Use Function HAL_UART_RegisterCallback() to register a user callback. + Function HAL_UART_RegisterCallback() allows to register following callbacks: + (+) TxHalfCpltCallback : Tx Half Complete Callback. + (+) TxCpltCallback : Tx Complete Callback. + (+) RxHalfCpltCallback : Rx Half Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) AbortCpltCallback : Abort Complete Callback. + (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. + (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. + (+) WakeupCallback : Wakeup Callback. + (+) RxFifoFullCallback : Rx Fifo Full Callback. + (+) TxFifoEmptyCallback : Tx Fifo Empty Callback. + (+) MspInitCallback : UART MspInit. + (+) MspDeInitCallback : UART MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + [..] + Use function HAL_UART_UnRegisterCallback() to reset a callback to the default + weak function. + HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) TxHalfCpltCallback : Tx Half Complete Callback. + (+) TxCpltCallback : Tx Complete Callback. + (+) RxHalfCpltCallback : Rx Half Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) AbortCpltCallback : Abort Complete Callback. + (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. + (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. + (+) WakeupCallback : Wakeup Callback. + (+) RxFifoFullCallback : Rx Fifo Full Callback. + (+) TxFifoEmptyCallback : Tx Fifo Empty Callback. + (+) MspInitCallback : UART MspInit. + (+) MspDeInitCallback : UART MspDeInit. + + [..] + For specific callback RxEventCallback, use dedicated registration/reset functions: + respectively HAL_UART_RegisterRxEventCallback() , HAL_UART_UnRegisterRxEventCallback(). + + [..] + By default, after the HAL_UART_Init() and when the state is HAL_UART_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples HAL_UART_TxCpltCallback(), HAL_UART_RxHalfCpltCallback(). + Exception done for MspInit and MspDeInit functions that are respectively + reset to the legacy weak functions in the HAL_UART_Init() + and HAL_UART_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_UART_Init() and HAL_UART_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand). + + [..] + Callbacks can be registered/unregistered in HAL_UART_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_UART_STATE_READY or HAL_UART_STATE_RESET state, thus registered (user) + MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_UART_RegisterCallback() before calling HAL_UART_DeInit() + or HAL_UART_Init() function. + + [..] + When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available + and weak callbacks are used. + + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @defgroup UART UART + * @brief HAL UART module driver + * @{ + */ + +#ifdef HAL_UART_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup UART_Private_Constants UART Private Constants + * @{ + */ +#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | \ + USART_CR1_OVER8 | USART_CR1_FIFOEN)) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */ + +#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT | USART_CR3_TXFTCFG | \ + USART_CR3_RXFTCFG)) /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */ + +#define LPUART_BRR_MIN 0x00000300U /* LPUART BRR minimum authorized value */ +#define LPUART_BRR_MAX 0x000FFFFFU /* LPUART BRR maximum authorized value */ + +#define UART_BRR_MIN 0x10U /* UART BRR minimum authorized value */ +#define UART_BRR_MAX 0x0000FFFFU /* UART BRR maximum authorized value */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup UART_Private_Functions + * @{ + */ +static void UART_EndRxTransfer(UART_HandleTypeDef *huart); +#if defined(HAL_DMA_MODULE_ENABLED) +static void UART_EndTxTransfer(UART_HandleTypeDef *huart); +static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma); +static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma); +static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma); +static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma); +static void UART_DMAError(DMA_HandleTypeDef *hdma); +static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma); +static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma); +static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma); +static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma); +static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma); +#endif /* HAL_DMA_MODULE_ENABLED */ +static void UART_TxISR_8BIT(UART_HandleTypeDef *huart); +static void UART_TxISR_16BIT(UART_HandleTypeDef *huart); +static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart); +static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart); +static void UART_EndTransmit_IT(UART_HandleTypeDef *huart); +static void UART_RxISR_8BIT(UART_HandleTypeDef *huart); +static void UART_RxISR_16BIT(UART_HandleTypeDef *huart); +static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart); +static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart); +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @addtogroup UART_Private_variables + * @{ + */ +const uint16_t UARTPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U}; +/** + * @} + */ + +/* Exported Constants --------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup UART_Exported_Functions UART Exported Functions + * @{ + */ + +/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim +=============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to initialize the USARTx or the UARTy + in asynchronous mode. + (+) For the asynchronous mode the parameters below can be configured: + (++) Baud Rate + (++) Word Length + (++) Stop Bit + (++) Parity: If the parity is enabled, then the MSB bit of the data written + in the data register is transmitted but is changed by the parity bit. + (++) Hardware flow control + (++) Receiver/transmitter modes + (++) Over Sampling Method + (++) One-Bit Sampling Method + (+) For the asynchronous mode, the following advanced features can be configured as well: + (++) TX and/or RX pin level inversion + (++) data logical level inversion + (++) RX and TX pins swap + (++) RX overrun detection disabling + (++) DMA disabling on RX error + (++) MSB first on communication line + (++) auto Baud rate detection + [..] + The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init()and HAL_MultiProcessor_Init()API + follow respectively the UART asynchronous, UART Half duplex, UART LIN mode + and UART multiprocessor mode configuration procedures (details for the procedures + are available in reference manual). + +@endverbatim + + Depending on the frame length defined by the M1 and M0 bits (7-bit, + 8-bit or 9-bit), the possible UART formats are listed in the + following table. + + Table 1. UART frame format. + +-----------------------------------------------------------------------+ + | M1 bit | M0 bit | PCE bit | UART frame | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 0 | | SB | 8 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 0 | | SB | 9 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 0 | | SB | 7 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | + +-----------------------------------------------------------------------+ + + * @{ + */ + +/** + * @brief Initialize the UART mode according to the specified + * parameters in the UART_InitTypeDef and initialize the associated handle. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + if (huart->Init.HwFlowCtl != UART_HWCONTROL_NONE) + { + /* Check the parameters */ + assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance)); + } + else + { + /* Check the parameters */ + assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance))); + } + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + __HAL_UART_DISABLE(huart); + + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + { + return HAL_ERROR; + } + + /* In asynchronous mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); + + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); +} + +/** + * @brief Initialize the half-duplex mode according to the specified + * parameters in the UART_InitTypeDef and creates the associated handle. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check UART instance */ + assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance)); + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + __HAL_UART_DISABLE(huart); + + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + { + return HAL_ERROR; + } + + /* In half-duplex mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN)); + + /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ + SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL); + + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); +} + + +/** + * @brief Initialize the LIN mode according to the specified + * parameters in the UART_InitTypeDef and creates the associated handle. + * @param huart UART handle. + * @param BreakDetectLength Specifies the LIN break detection length. + * This parameter can be one of the following values: + * @arg @ref UART_LINBREAKDETECTLENGTH_10B 10-bit break detection + * @arg @ref UART_LINBREAKDETECTLENGTH_11B 11-bit break detection + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the LIN UART instance */ + assert_param(IS_UART_LIN_INSTANCE(huart->Instance)); + /* Check the Break detection length parameter */ + assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength)); + + /* LIN mode limited to 16-bit oversampling only */ + if (huart->Init.OverSampling == UART_OVERSAMPLING_8) + { + return HAL_ERROR; + } + /* LIN mode limited to 8-bit data length */ + if (huart->Init.WordLength != UART_WORDLENGTH_8B) + { + return HAL_ERROR; + } + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + __HAL_UART_DISABLE(huart); + + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + { + return HAL_ERROR; + } + + /* In LIN mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN)); + + /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ + SET_BIT(huart->Instance->CR2, USART_CR2_LINEN); + + /* Set the USART LIN Break detection length. */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength); + + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); +} + + +/** + * @brief Initialize the multiprocessor mode according to the specified + * parameters in the UART_InitTypeDef and initialize the associated handle. + * @param huart UART handle. + * @param Address UART node address (4-, 6-, 7- or 8-bit long). + * @param WakeUpMethod Specifies the UART wakeup method. + * This parameter can be one of the following values: + * @arg @ref UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection + * @arg @ref UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark + * @note If the user resorts to idle line detection wake up, the Address parameter + * is useless and ignored by the initialization function. + * @note If the user resorts to address mark wake up, the address length detection + * is configured by default to 4 bits only. For the UART to be able to + * manage 6-, 7- or 8-bit long addresses detection, the API + * HAL_MultiProcessorEx_AddressLength_Set() must be called after + * HAL_MultiProcessor_Init(). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the wake up method parameter */ + assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod)); + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + __HAL_UART_DISABLE(huart); + + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + { + return HAL_ERROR; + } + + /* In multiprocessor mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN, HDSEL and IREN bits in the USART_CR3 register. */ + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); + + if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK) + { + /* If address mark wake up method is chosen, set the USART address node */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)Address << UART_CR2_ADDRESS_LSB_POS)); + } + + /* Set the wake up method by setting the WAKE bit in the CR1 register */ + MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod); + + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); +} + + +/** + * @brief DeInitialize the UART peripheral. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance))); + + huart->gState = HAL_UART_STATE_BUSY; + + __HAL_UART_DISABLE(huart); + + huart->Instance->CR1 = 0x0U; + huart->Instance->CR2 = 0x0U; + huart->Instance->CR3 = 0x0U; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + if (huart->MspDeInitCallback == NULL) + { + huart->MspDeInitCallback = HAL_UART_MspDeInit; + } + /* DeInit the low level hardware */ + huart->MspDeInitCallback(huart); +#else + /* DeInit the low level hardware */ + HAL_UART_MspDeInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_RESET; + huart->RxState = HAL_UART_STATE_RESET; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + huart->RxEventType = HAL_UART_RXEVENT_TC; + + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Initialize the UART MSP. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_MspInit can be implemented in the user file + */ +} + +/** + * @brief DeInitialize the UART MSP. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_MspDeInit can be implemented in the user file + */ +} + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User UART Callback + * To be used to override the weak predefined callback + * @note The HAL_UART_RegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(), + * HAL_LIN_Init(), HAL_MultiProcessor_Init() or HAL_RS485Ex_Init() in HAL_UART_STATE_RESET to register + * callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID + * @param huart uart handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID + * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID + * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID + * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID + * @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID + * @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID + * @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID + * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID + * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, + pUART_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (huart->gState == HAL_UART_STATE_READY) + { + switch (CallbackID) + { + case HAL_UART_TX_HALFCOMPLETE_CB_ID : + huart->TxHalfCpltCallback = pCallback; + break; + + case HAL_UART_TX_COMPLETE_CB_ID : + huart->TxCpltCallback = pCallback; + break; + + case HAL_UART_RX_HALFCOMPLETE_CB_ID : + huart->RxHalfCpltCallback = pCallback; + break; + + case HAL_UART_RX_COMPLETE_CB_ID : + huart->RxCpltCallback = pCallback; + break; + + case HAL_UART_ERROR_CB_ID : + huart->ErrorCallback = pCallback; + break; + + case HAL_UART_ABORT_COMPLETE_CB_ID : + huart->AbortCpltCallback = pCallback; + break; + + case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID : + huart->AbortTransmitCpltCallback = pCallback; + break; + + case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID : + huart->AbortReceiveCpltCallback = pCallback; + break; + + case HAL_UART_RX_FIFO_FULL_CB_ID : + huart->RxFifoFullCallback = pCallback; + break; + + case HAL_UART_TX_FIFO_EMPTY_CB_ID : + huart->TxFifoEmptyCallback = pCallback; + break; + + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = pCallback; + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = pCallback; + break; + + default : + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + break; + } + } + else if (huart->gState == HAL_UART_STATE_RESET) + { + switch (CallbackID) + { + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = pCallback; + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = pCallback; + break; + + default : + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + break; + } + } + else + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister an UART Callback + * UART callaback is redirected to the weak predefined callback + * @note The HAL_UART_UnRegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(), + * HAL_LIN_Init(), HAL_MultiProcessor_Init() or HAL_RS485Ex_Init() in HAL_UART_STATE_RESET to un-register + * callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID + * @param huart uart handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID + * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID + * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID + * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID + * @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID + * @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID + * @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID + * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID + * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (HAL_UART_STATE_READY == huart->gState) + { + switch (CallbackID) + { + case HAL_UART_TX_HALFCOMPLETE_CB_ID : + huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + break; + + case HAL_UART_TX_COMPLETE_CB_ID : + huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */ + break; + + case HAL_UART_RX_HALFCOMPLETE_CB_ID : + huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + break; + + case HAL_UART_RX_COMPLETE_CB_ID : + huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */ + break; + + case HAL_UART_ERROR_CB_ID : + huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_UART_ABORT_COMPLETE_CB_ID : + huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + break; + + case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID : + huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak + AbortTransmitCpltCallback */ + break; + + case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID : + huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak + AbortReceiveCpltCallback */ + break; + + case HAL_UART_RX_FIFO_FULL_CB_ID : + huart->RxFifoFullCallback = HAL_UARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */ + break; + + case HAL_UART_TX_FIFO_EMPTY_CB_ID : + huart->TxFifoEmptyCallback = HAL_UARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ + break; + + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = HAL_UART_MspInit; /* Legacy weak MspInitCallback */ + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = HAL_UART_MspDeInit; /* Legacy weak MspDeInitCallback */ + break; + + default : + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + break; + } + } + else if (HAL_UART_STATE_RESET == huart->gState) + { + switch (CallbackID) + { + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = HAL_UART_MspInit; + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = HAL_UART_MspDeInit; + break; + + default : + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + break; + } + } + else + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Register a User UART Rx Event Callback + * To be used instead of the weak predefined callback + * @param huart Uart handle + * @param pCallback Pointer to the Rx Event Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (huart->RxState == HAL_UART_STATE_READY) + { + huart->RxEventCallback = pCallback; + } + else + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief UnRegister the UART Rx Event Callback + * UART Rx Event Callback is redirected to the weak HAL_UARTEx_RxEventCallback() predefined callback + * @param huart Uart handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (huart->RxState == HAL_UART_STATE_READY) + { + huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak UART Rx Event Callback */ + } + else + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + } + + return status; +} + +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup UART_Exported_Functions_Group2 IO operation functions + * @brief UART Transmit/Receive functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + This subsection provides a set of functions allowing to manage the UART asynchronous + and Half duplex data transfers. + + (#) There are two mode of transfer: + (+) Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (+) Non-Blocking mode: The communication is performed using Interrupts + or DMA, These API's return the HAL status. + The end of the data processing will be indicated through the + dedicated UART IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks + will be executed respectively at the end of the transmit or Receive process + The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected + + (#) Blocking mode API's are : + (+) HAL_UART_Transmit() + (+) HAL_UART_Receive() + + (#) Non-Blocking mode API's with Interrupt are : + (+) HAL_UART_Transmit_IT() + (+) HAL_UART_Receive_IT() + (+) HAL_UART_IRQHandler() + + (#) Non-Blocking mode API's with DMA are : + (+) HAL_UART_Transmit_DMA() + (+) HAL_UART_Receive_DMA() + (+) HAL_UART_DMAPause() + (+) HAL_UART_DMAResume() + (+) HAL_UART_DMAStop() + + (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode: + (+) HAL_UART_TxHalfCpltCallback() + (+) HAL_UART_TxCpltCallback() + (+) HAL_UART_RxHalfCpltCallback() + (+) HAL_UART_RxCpltCallback() + (+) HAL_UART_ErrorCallback() + + (#) Non-Blocking mode transfers could be aborted using Abort API's : + (+) HAL_UART_Abort() + (+) HAL_UART_AbortTransmit() + (+) HAL_UART_AbortReceive() + (+) HAL_UART_Abort_IT() + (+) HAL_UART_AbortTransmit_IT() + (+) HAL_UART_AbortReceive_IT() + + (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided: + (+) HAL_UART_AbortCpltCallback() + (+) HAL_UART_AbortTransmitCpltCallback() + (+) HAL_UART_AbortReceiveCpltCallback() + + (#) A Rx Event Reception Callback (Rx event notification) is available for Non_Blocking modes of enhanced + reception services: + (+) HAL_UARTEx_RxEventCallback() + + (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. + Errors are handled as follows : + (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is + to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error + in Interrupt mode reception . + Received character is then retrieved and stored in Rx buffer, Error code is set to allow user + to identify error type, and HAL_UART_ErrorCallback() user callback is executed. + Transfer is kept ongoing on UART side. + If user wants to abort it, Abort services should be called by user. + (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted. + This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. + Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() + user callback is executed. + + -@- In the Half duplex communication, it is forbidden to run the transmit + and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful. + +@endverbatim + * @{ + */ + +/** + * @brief Send an amount of data in blocking mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pData. + * @note When FIFO mode is enabled, writing a data in the TDR register adds one + * data to the TXFIFO. Write operations to the TDR register are performed + * when TXFNF flag is set. From hardware perspective, TXFNF flag and + * TXE are mapped on the same bit-field. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. + * @param Timeout Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + const uint8_t *pdata8bits; + const uint16_t *pdata16bits; + uint32_t tickstart; + + /* Check that a Tx process is not already ongoing */ + if (huart->gState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_BUSY_TX; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + huart->TxXferSize = Size; + huart->TxXferCount = Size; + + /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + pdata8bits = NULL; + pdata16bits = (const uint16_t *) pData; + } + else + { + pdata8bits = pData; + pdata16bits = NULL; + } + + while (huart->TxXferCount > 0U) + { + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + { + + huart->gState = HAL_UART_STATE_READY; + + return HAL_TIMEOUT; + } + if (pdata8bits == NULL) + { + huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU); + pdata16bits++; + } + else + { + huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU); + pdata8bits++; + } + huart->TxXferCount--; + } + + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) + { + huart->gState = HAL_UART_STATE_READY; + + return HAL_TIMEOUT; + } + + /* At end of Tx process, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in blocking mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pData. + * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO + * is not empty. Read operations from the RDR register are performed when + * RXFNE flag is set. From hardware perspective, RXFNE flag and + * RXNE are mapped on the same bit-field. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @param Timeout Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint8_t *pdata8bits; + uint16_t *pdata16bits; + uint16_t uhMask; + uint32_t tickstart; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + huart->RxXferSize = Size; + huart->RxXferCount = Size; + + /* Computation of UART mask to apply to RDR register */ + UART_MASK_COMPUTATION(huart); + uhMask = huart->Mask; + + /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + pdata8bits = NULL; + pdata16bits = (uint16_t *) pData; + } + else + { + pdata8bits = pData; + pdata16bits = NULL; + } + + /* as long as data have to be received */ + while (huart->RxXferCount > 0U) + { + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) + { + huart->RxState = HAL_UART_STATE_READY; + + return HAL_TIMEOUT; + } + if (pdata8bits == NULL) + { + *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask); + pdata16bits++; + } + else + { + *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); + pdata8bits++; + } + huart->RxXferCount--; + } + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Send an amount of data in interrupt mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) +{ + /* Check that a Tx process is not already ongoing */ + if (huart->gState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + huart->pTxBuffPtr = pData; + huart->TxXferSize = Size; + huart->TxXferCount = Size; + huart->TxISR = NULL; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_BUSY_TX; + + /* Configure Tx interrupt processing */ + if (huart->FifoMode == UART_FIFOMODE_ENABLE) + { + /* Set the Tx ISR function pointer according to the data word length */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + huart->TxISR = UART_TxISR_16BIT_FIFOEN; + } + else + { + huart->TxISR = UART_TxISR_8BIT_FIFOEN; + } + + /* Enable the TX FIFO threshold interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); + } + else + { + /* Set the Tx ISR function pointer according to the data word length */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + huart->TxISR = UART_TxISR_16BIT; + } + else + { + huart->TxISR = UART_TxISR_8BIT; + } + + /* Enable the Transmit Data Register Empty interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in interrupt mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Set Reception type to Standard reception */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + } + + return (UART_Start_Receive_IT(huart, pData, Size)); + } + else + { + return HAL_BUSY; + } +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Send an amount of data in DMA mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef status; + uint16_t nbByte = Size; + + /* Check that a Tx process is not already ongoing */ + if (huart->gState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + huart->pTxBuffPtr = pData; + huart->TxXferSize = Size; + huart->TxXferCount = Size; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_BUSY_TX; + + if (huart->hdmatx != NULL) + { + /* Set the UART DMA transfer complete callback */ + huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt; + + /* Set the UART DMA Half transfer complete callback */ + huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt; + + /* Set the DMA error callback */ + huart->hdmatx->XferErrorCallback = UART_DMAError; + + /* Set the DMA abort callback */ + huart->hdmatx->XferAbortCallback = NULL; + + /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter + should be aligned on a u16 frontier, so nbByte should be equal to Size * 2 */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + nbByte = Size * 2U; + } + + /* Check linked list mode */ + if ((huart->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if ((huart->hdmatx->LinkedListQueue != NULL) && (huart->hdmatx->LinkedListQueue->Head != NULL)) + { + /* Set DMA data size */ + huart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = nbByte; + + /* Set DMA source address */ + huart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)huart->pTxBuffPtr; + + /* Set DMA destination address */ + huart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = + (uint32_t)&huart->Instance->TDR; + + /* Enable the UART transmit DMA channel */ + status = HAL_DMAEx_List_Start_IT(huart->hdmatx); + } + else + { + /* Update status */ + status = HAL_ERROR; + } + } + else + { + /* Enable the UART transmit DMA channel */ + status = HAL_DMA_Start_IT(huart->hdmatx, (uint32_t)huart->pTxBuffPtr, (uint32_t)&huart->Instance->TDR, nbByte); + } + + if (status != HAL_OK) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + /* Restore huart->gState to ready */ + huart->gState = HAL_UART_STATE_READY; + + return HAL_ERROR; + } + } + /* Clear the TC flag in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF); + + /* Enable the DMA transfer for transmit request by setting the DMAT bit + in the UART CR3 register */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in DMA mode. + * @note When the UART parity is enabled (PCE = 1), the received data contain + * the parity bit (MSB position). + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Set Reception type to Standard reception */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + } + + return (UART_Start_Receive_DMA(huart, pData, Size)); + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Pause the DMA Transfer. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) +{ + const HAL_UART_StateTypeDef gstate = huart->gState; + const HAL_UART_StateTypeDef rxstate = huart->RxState; + + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && + (gstate == HAL_UART_STATE_BUSY_TX)) + { + /* Suspend the UART DMA Tx channel : use blocking DMA Suspend API (no callback) */ + if (huart->hdmatx != NULL) + { + /* Set the UART DMA Suspend callback to Null. + No call back execution at end of DMA Suspend procedure */ + huart->hdmatx->XferSuspendCallback = NULL; + + if (HAL_DMAEx_Suspend(huart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && + (rxstate == HAL_UART_STATE_BUSY_RX)) + { + /* Suspend the UART DMA Rx channel : use blocking DMA Suspend API (no callback) */ + if (huart->hdmarx != NULL) + { + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Set the UART DMA Suspend callback to Null. + No call back execution at end of DMA Suspend procedure */ + huart->hdmarx->XferSuspendCallback = NULL; + + if (HAL_DMAEx_Suspend(huart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + + return HAL_OK; +} + +/** + * @brief Resume the DMA Transfer. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) +{ + if (huart->gState == HAL_UART_STATE_BUSY_TX) + { + /* Resume the UART DMA Tx channel */ + if (huart->hdmatx != NULL) + { + if (HAL_DMAEx_Resume(huart->hdmatx) != HAL_OK) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_ERROR; + } + } + } + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + /* Clear the Overrun flag before resuming the Rx transfer */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); + + /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */ + if (huart->Init.Parity != UART_PARITY_NONE) + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + } + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Resume the UART DMA Rx channel */ + if (huart->hdmarx != NULL) + { + if (HAL_DMAEx_Resume(huart->hdmarx) != HAL_OK) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_ERROR; + } + } + } + + return HAL_OK; +} + +/** + * @brief Stop the DMA Transfer. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) +{ + /* The Lock is not implemented on this API to allow the user application + to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() / + HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback: + indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete + interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of + the stream and the corresponding call back is executed. */ + + const HAL_UART_StateTypeDef gstate = huart->gState; + const HAL_UART_StateTypeDef rxstate = huart->RxState; + + /* Stop UART DMA Tx request if ongoing */ + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && + (gstate == HAL_UART_STATE_BUSY_TX)) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx channel */ + if (huart->hdmatx != NULL) + { + if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + + UART_EndTxTransfer(huart); + } + + /* Stop UART DMA Rx request if ongoing */ + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && + (rxstate == HAL_UART_STATE_BUSY_RX)) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel */ + if (huart->hdmarx != NULL) + { + if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + + UART_EndRxTransfer(huart); + } + + return HAL_OK; +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Abort ongoing transfers (blocking mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx and Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) +{ + /* Disable TXE, TC, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | + USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE); + + /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + } + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Abort the UART DMA Tx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + /* Disable the UART DMA Tx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ + if (huart->hdmatx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmatx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + + /* Abort the UART DMA Rx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + /* Disable the UART DMA Rx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ + if (huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } +#endif /* HAL_DMA_MODULE_ENABLED */ + + /* Reset Tx and Rx transfer counters */ + huart->TxXferCount = 0U; + huart->RxXferCount = 0U; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Flush the whole TX FIFO (if needed) */ + if (huart->FifoMode == UART_FIFOMODE_ENABLE) + { + __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); + } + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + + return HAL_OK; +} + +/** + * @brief Abort ongoing Transmit transfer (blocking mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) +{ + /* Disable TCIE, TXEIE and TXFTIE interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Abort the UART DMA Tx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + /* Disable the UART DMA Tx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ + if (huart->hdmatx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmatx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } +#endif /* HAL_DMA_MODULE_ENABLED */ + + /* Reset Tx transfer counter */ + huart->TxXferCount = 0U; + + /* Flush the whole TX FIFO (if needed) */ + if (huart->FifoMode == UART_FIFOMODE_ENABLE) + { + __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); + } + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Abort ongoing Receive transfer (blocking mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) +{ + /* Disable PEIE, EIE, RXNEIE and RXFTIE interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE); + + /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + } + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Abort the UART DMA Rx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + /* Disable the UART DMA Rx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ + if (huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } +#endif /* HAL_DMA_MODULE_ENABLED */ + + /* Reset Rx transfer counter */ + huart->RxXferCount = 0U; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + return HAL_OK; +} + +/** + * @brief Abort ongoing transfers (Interrupt mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx and Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) +{ + uint32_t abortcplt = 1U; + + /* Disable interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_TCIE | USART_CR1_RXNEIE_RXFNEIE | + USART_CR1_TXEIE_TXFNFIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); + + /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + } + +#if defined(HAL_DMA_MODULE_ENABLED) + /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised + before any call to DMA Abort functions */ + /* DMA Tx Handle is valid */ + if (huart->hdmatx != NULL) + { + /* Set DMA Abort Complete callback if UART DMA Tx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback; + } + else + { + huart->hdmatx->XferAbortCallback = NULL; + } + } + /* DMA Rx Handle is valid */ + if (huart->hdmarx != NULL) + { + /* Set DMA Abort Complete callback if UART DMA Rx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback; + } + else + { + huart->hdmarx->XferAbortCallback = NULL; + } + } + + /* Abort the UART DMA Tx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + /* Disable DMA Tx at UART level */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ + if (huart->hdmatx != NULL) + { + /* UART Tx DMA Abort callback has already been initialised : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) + { + huart->hdmatx->XferAbortCallback = NULL; + } + else + { + abortcplt = 0U; + } + } + } + + /* Abort the UART DMA Rx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + /* Disable the UART DMA Rx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ + if (huart->hdmarx != NULL) + { + /* UART Rx DMA Abort callback has already been initialised : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + { + huart->hdmarx->XferAbortCallback = NULL; + abortcplt = 1U; + } + else + { + abortcplt = 0U; + } + } + } +#endif /* HAL_DMA_MODULE_ENABLED */ + + /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ + if (abortcplt == 1U) + { + /* Reset Tx and Rx transfer counters */ + huart->TxXferCount = 0U; + huart->RxXferCount = 0U; + + /* Clear ISR function pointers */ + huart->RxISR = NULL; + huart->TxISR = NULL; + + /* Reset errorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Flush the whole TX FIFO (if needed) */ + if (huart->FifoMode == UART_FIFOMODE_ENABLE) + { + __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); + } + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + huart->AbortCpltCallback(huart); +#else + /* Call legacy weak Abort complete callback */ + HAL_UART_AbortCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} + +/** + * @brief Abort ongoing Transmit transfer (Interrupt mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) +{ + /* Disable interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Abort the UART DMA Tx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + /* Disable the UART DMA Tx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ + if (huart->hdmatx != NULL) + { + /* Set the UART DMA Abort callback : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) + { + /* Call Directly huart->hdmatx->XferAbortCallback function in case of error */ + huart->hdmatx->XferAbortCallback(huart->hdmatx); + } + } + else + { + /* Reset Tx transfer counter */ + huart->TxXferCount = 0U; + + /* Clear TxISR function pointers */ + huart->TxISR = NULL; + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + huart->AbortTransmitCpltCallback(huart); +#else + /* Call legacy weak Abort Transmit Complete Callback */ + HAL_UART_AbortTransmitCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + else +#endif /* HAL_DMA_MODULE_ENABLED */ + { + /* Reset Tx transfer counter */ + huart->TxXferCount = 0U; + + /* Clear TxISR function pointers */ + huart->TxISR = NULL; + + /* Flush the whole TX FIFO (if needed) */ + if (huart->FifoMode == UART_FIFOMODE_ENABLE) + { + __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); + } + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + huart->AbortTransmitCpltCallback(huart); +#else + /* Call legacy weak Abort Transmit Complete Callback */ + HAL_UART_AbortTransmitCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} + +/** + * @brief Abort ongoing Receive transfer (Interrupt mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) +{ + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + + /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + } + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Abort the UART DMA Rx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + /* Disable the UART DMA Rx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ + if (huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + { + /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ + huart->hdmarx->XferAbortCallback(huart->hdmarx); + } + } + else + { + /* Reset Rx transfer counter */ + huart->RxXferCount = 0U; + + /* Clear RxISR function pointer */ + huart->pRxBuffPtr = NULL; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + huart->AbortReceiveCpltCallback(huart); +#else + /* Call legacy weak Abort Receive Complete Callback */ + HAL_UART_AbortReceiveCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + else +#endif /* HAL_DMA_MODULE_ENABLED */ + { + /* Reset Rx transfer counter */ + huart->RxXferCount = 0U; + + /* Clear RxISR function pointer */ + huart->pRxBuffPtr = NULL; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + huart->AbortReceiveCpltCallback(huart); +#else + /* Call legacy weak Abort Receive Complete Callback */ + HAL_UART_AbortReceiveCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} + +/** + * @brief Handle UART interrupt request. + * @param huart UART handle. + * @retval None + */ +void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) +{ + uint32_t isrflags = READ_REG(huart->Instance->ISR); + uint32_t cr1its = READ_REG(huart->Instance->CR1); + uint32_t cr3its = READ_REG(huart->Instance->CR3); + + uint32_t errorflags; + uint32_t errorcode; + + /* If no error occurs */ + errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF)); + if (errorflags == 0U) + { + /* UART in mode Receiver ---------------------------------------------------*/ + if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) + || ((cr3its & USART_CR3_RXFTIE) != 0U))) + { + if (huart->RxISR != NULL) + { + huart->RxISR(huart); + } + return; + } + } + + /* If some errors occur */ + if ((errorflags != 0U) + && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U) + || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U)))) + { + /* UART parity error interrupt occurred -------------------------------------*/ + if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); + + huart->ErrorCode |= HAL_UART_ERROR_PE; + } + + /* UART frame error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); + + huart->ErrorCode |= HAL_UART_ERROR_FE; + } + + /* UART noise error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); + + huart->ErrorCode |= HAL_UART_ERROR_NE; + } + + /* UART Over-Run interrupt occurred -----------------------------------------*/ + if (((isrflags & USART_ISR_ORE) != 0U) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || + ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U))) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); + + huart->ErrorCode |= HAL_UART_ERROR_ORE; + } + + /* UART Receiver Timeout interrupt occurred ---------------------------------*/ + if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); + + huart->ErrorCode |= HAL_UART_ERROR_RTO; + } + + /* Call UART Error Call back function if need be ----------------------------*/ + if (huart->ErrorCode != HAL_UART_ERROR_NONE) + { + /* UART in mode Receiver --------------------------------------------------*/ + if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) + || ((cr3its & USART_CR3_RXFTIE) != 0U))) + { + if (huart->RxISR != NULL) + { + huart->RxISR(huart); + } + } + + /* If Error is to be considered as blocking : + - Receiver Timeout error in Reception + - Overrun error in Reception + - any error occurs in DMA mode reception + */ + errorcode = huart->ErrorCode; + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || + ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U)) + { + /* Blocking error : transfer is aborted + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ + UART_EndRxTransfer(huart); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Abort the UART DMA Rx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + /* Disable the UART DMA Rx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel */ + if (huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback : + will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + { + /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ + huart->hdmarx->XferAbortCallback(huart->hdmarx); + } + } + else + { + /* Call user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + + } + } + else +#endif /* HAL_DMA_MODULE_ENABLED */ + { + /* Call user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + else + { + /* Non Blocking error : transfer could go on. + Error is notified to user through user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + } + } + return; + + } /* End if some error occurs */ + + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + && ((isrflags & USART_ISR_IDLE) != 0U) + && ((cr1its & USART_ISR_IDLE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Check if DMA mode is enabled in UART */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + /* DMA mode enabled */ + /* Check received length : If all expected data are received, do nothing, + (DMA cplt callback will be called). + Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ + uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); + if ((nb_remaining_rx_data > 0U) + && (nb_remaining_rx_data < huart->RxXferSize)) + { + /* Reception is not complete */ + huart->RxXferCount = nb_remaining_rx_data; + + /* In Normal mode, end DMA xfer and HAL UART Rx process*/ + if (huart->hdmarx->Mode != DMA_LINKEDLIST_CIRCULAR) + { + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Disable the DMA transfer for the receiver request by resetting the DMAR bit + in the UART CR3 register */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + /* Last bytes received, so no need as the abort is immediate */ + (void)HAL_DMA_Abort(huart->hdmarx); + } + + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Idle Event */ + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + return; + } + else + { +#endif /* HAL_DMA_MODULE_ENABLED */ + /* DMA mode not enabled */ + /* Check received length : If all expected data are received, do nothing. + Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ + uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; + if ((huart->RxXferCount > 0U) + && (nb_rx_data > 0U)) + { + /* Disable the UART Parity Error Interrupt and RXNE interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + + /* Disable the UART Error Interrupt:(Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Idle Event */ + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxEventCallback(huart, nb_rx_data); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, nb_rx_data); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + return; +#if defined(HAL_DMA_MODULE_ENABLED) + } +#endif /* HAL_DMA_MODULE_ENABLED */ + } + + /* UART in mode Transmitter ------------------------------------------------*/ + if (((isrflags & USART_ISR_TXE_TXFNF) != 0U) + && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U) + || ((cr3its & USART_CR3_TXFTIE) != 0U))) + { + if (huart->TxISR != NULL) + { + huart->TxISR(huart); + } + return; + } + + /* UART in mode Transmitter (transmission end) -----------------------------*/ + if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U)) + { + UART_EndTransmit_IT(huart); + return; + } + + /* UART TX Fifo Empty occurred ----------------------------------------------*/ + if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U)) + { +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Fifo Empty Callback */ + huart->TxFifoEmptyCallback(huart); +#else + /* Call legacy weak Tx Fifo Empty Callback */ + HAL_UARTEx_TxFifoEmptyCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + return; + } + + /* UART RX Fifo Full occurred ----------------------------------------------*/ + if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U)) + { +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Fifo Full Callback */ + huart->RxFifoFullCallback(huart); +#else + /* Call legacy weak Rx Fifo Full Callback */ + HAL_UARTEx_RxFifoFullCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + return; + } +} + +/** + * @brief Tx Transfer completed callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_TxCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Tx Half Transfer completed callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_TxHalfCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Rx Transfer completed callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_RxCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Rx Half Transfer completed callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_RxHalfCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief UART error callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_ErrorCallback can be implemented in the user file. + */ +} + +/** + * @brief UART Abort Complete callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_AbortCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief UART Abort Complete callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_AbortTransmitCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief UART Abort Receive Complete callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Reception Event Callback (Rx event notification called after use of advanced reception service). + * @param huart UART handle + * @param Size Number of data available in application reception buffer (indicates a position in + * reception buffer until which, data are available) + * @retval None + */ +__weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + UNUSED(Size); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UARTEx_RxEventCallback can be implemented in the user file. + */ +} + +/** + * @} + */ + +/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions + * @brief UART control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the UART. + (+) HAL_UART_ReceiverTimeout_Config() API allows to configure the receiver timeout value on the fly + (+) HAL_UART_EnableReceiverTimeout() API enables the receiver timeout feature + (+) HAL_UART_DisableReceiverTimeout() API disables the receiver timeout feature + (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode + (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode + (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode + (+) UART_SetConfig() API configures the UART peripheral + (+) UART_AdvFeatureConfig() API optionally configures the UART advanced features + (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization + (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter + (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver + (+) HAL_LIN_SendBreak() API transmits the break characters +@endverbatim + * @{ + */ + +/** + * @brief Update on the fly the receiver timeout value in RTOR register. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @param TimeoutValue receiver timeout value in number of baud blocks. The timeout + * value must be less or equal to 0x0FFFFFFFF. + * @retval None + */ +void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue) +{ + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + assert_param(IS_UART_RECEIVER_TIMEOUT_VALUE(TimeoutValue)); + MODIFY_REG(huart->Instance->RTOR, USART_RTOR_RTO, TimeoutValue); + } +} + +/** + * @brief Enable the UART receiver timeout feature. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart) +{ + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + if (huart->gState == HAL_UART_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Set the USART RTOEN bit */ + SET_BIT(huart->Instance->CR2, USART_CR2_RTOEN); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Disable the UART receiver timeout feature. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart) +{ + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + if (huart->gState == HAL_UART_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Clear the USART RTOEN bit */ + CLEAR_BIT(huart->Instance->CR2, USART_CR2_RTOEN); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Enable UART in mute mode (does not mean UART enters mute mode; + * to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called). + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart) +{ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Enable USART mute mode by setting the MME bit in the CR1 register */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_MME); + + huart->gState = HAL_UART_STATE_READY; + + return (UART_CheckIdleState(huart)); +} + +/** + * @brief Disable UART mute mode (does not mean the UART actually exits mute mode + * as it may not have been in mute mode at this very moment). + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart) +{ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable USART mute mode by clearing the MME bit in the CR1 register */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME); + + huart->gState = HAL_UART_STATE_READY; + + return (UART_CheckIdleState(huart)); +} + +/** + * @brief Enter UART mute mode (means UART actually enters mute mode). + * @note To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called. + * @param huart UART handle. + * @retval None + */ +void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart) +{ + __HAL_UART_SEND_REQ(huart, UART_MUTE_MODE_REQUEST); +} + +/** + * @brief Enable the UART transmitter and disable the UART receiver. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) +{ + __HAL_LOCK(huart); + huart->gState = HAL_UART_STATE_BUSY; + + /* Clear TE and RE bits */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); + + /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TE); + + huart->gState = HAL_UART_STATE_READY; + + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Enable the UART receiver and disable the UART transmitter. + * @param huart UART handle. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) +{ + __HAL_LOCK(huart); + huart->gState = HAL_UART_STATE_BUSY; + + /* Clear TE and RE bits */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); + + /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RE); + + huart->gState = HAL_UART_STATE_READY; + + __HAL_UNLOCK(huart); + + return HAL_OK; +} + + +/** + * @brief Transmit break characters. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) +{ + /* Check the parameters */ + assert_param(IS_UART_LIN_INSTANCE(huart->Instance)); + + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Send break characters */ + __HAL_UART_SEND_REQ(huart, UART_SENDBREAK_REQUEST); + + huart->gState = HAL_UART_STATE_READY; + + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Error functions + * @brief UART Peripheral State functions + * +@verbatim + ============================================================================== + ##### Peripheral State and Error functions ##### + ============================================================================== + [..] + This subsection provides functions allowing to : + (+) Return the UART handle state. + (+) Return the UART handle error code + +@endverbatim + * @{ + */ + +/** + * @brief Return the UART handle state. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART. + * @retval HAL state + */ +HAL_UART_StateTypeDef HAL_UART_GetState(const UART_HandleTypeDef *huart) +{ + uint32_t temp1; + uint32_t temp2; + temp1 = huart->gState; + temp2 = huart->RxState; + + return (HAL_UART_StateTypeDef)(temp1 | temp2); +} + +/** + * @brief Return the UART handle error code. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART. + * @retval UART Error Code + */ +uint32_t HAL_UART_GetError(const UART_HandleTypeDef *huart) +{ + return huart->ErrorCode; +} +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup UART_Private_Functions UART Private Functions + * @{ + */ + +/** + * @brief Initialize the callbacks to their default values. + * @param huart UART handle. + * @retval none + */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart) +{ + /* Init the UART Callback settings */ + huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */ + huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */ + huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */ + huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */ + huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */ + huart->RxFifoFullCallback = HAL_UARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */ + huart->TxFifoEmptyCallback = HAL_UARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ + huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak RxEventCallback */ + +} +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @brief Configure the UART peripheral. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) +{ + uint32_t tmpreg; + uint16_t brrtemp; + UART_ClockSourceTypeDef clocksource; + uint32_t usartdiv; + HAL_StatusTypeDef ret = HAL_OK; + uint32_t lpuart_ker_ck_pres; + uint32_t pclk; + + /* Check the parameters */ + assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate)); + assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); + if (UART_INSTANCE_LOWPOWER(huart)) + { + assert_param(IS_LPUART_STOPBITS(huart->Init.StopBits)); + } + else + { + assert_param(IS_UART_STOPBITS(huart->Init.StopBits)); + assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling)); + } + + assert_param(IS_UART_PARITY(huart->Init.Parity)); + assert_param(IS_UART_MODE(huart->Init.Mode)); + assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl)); + assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); + assert_param(IS_UART_PRESCALER(huart->Init.ClockPrescaler)); + + /*-------------------------- USART CR1 Configuration -----------------------*/ + /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure + * the UART Word Length, Parity, Mode and oversampling: + * set the M bits according to huart->Init.WordLength value + * set PCE and PS bits according to huart->Init.Parity value + * set TE and RE bits according to huart->Init.Mode value + * set OVER8 bit according to huart->Init.OverSampling value */ + tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; + MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); + + /*-------------------------- USART CR2 Configuration -----------------------*/ + /* Configure the UART Stop Bits: Set STOP[13:12] bits according + * to huart->Init.StopBits value */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); + + /*-------------------------- USART CR3 Configuration -----------------------*/ + /* Configure + * - UART HardWare Flow Control: set CTSE and RTSE bits according + * to huart->Init.HwFlowCtl value + * - one-bit sampling method versus three samples' majority rule according + * to huart->Init.OneBitSampling (not applicable to LPUART) */ + tmpreg = (uint32_t)huart->Init.HwFlowCtl; + + if (!(UART_INSTANCE_LOWPOWER(huart))) + { + tmpreg |= huart->Init.OneBitSampling; + } + MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); + + /*-------------------------- USART PRESC Configuration -----------------------*/ + /* Configure + * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */ + MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler); + + /*-------------------------- USART BRR Configuration -----------------------*/ + UART_GETCLOCKSOURCE(huart, clocksource); + + /* Check LPUART instance */ + if (UART_INSTANCE_LOWPOWER(huart)) + { + /* Retrieve frequency clock */ + switch (clocksource) + { + case UART_CLOCKSOURCE_PCLK7: + pclk = HAL_RCC_GetPCLK7Freq(); + break; + case UART_CLOCKSOURCE_HSI: + pclk = (uint32_t) HSI_VALUE; + break; + case UART_CLOCKSOURCE_SYSCLK: + pclk = HAL_RCC_GetSysClockFreq(); + break; + case UART_CLOCKSOURCE_LSE: + pclk = (uint32_t) LSE_VALUE; + break; + default: + pclk = 0U; + ret = HAL_ERROR; + break; + } + + /* If proper clock source reported */ + if (pclk != 0U) + { + /* Compute clock after Prescaler */ + lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]); + + /* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */ + if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) || + (lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate))) + { + ret = HAL_ERROR; + } + else + { + /* Check computed UsartDiv value is in allocated range + (it is forbidden to write values lower than 0x300 in the LPUART_BRR register) */ + usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX)) + { + huart->Instance->BRR = usartdiv; + } + else + { + ret = HAL_ERROR; + } + } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) || + (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */ + } /* if (pclk != 0) */ + } + /* Check UART Over Sampling to set Baud Rate Register */ + else if (huart->Init.OverSampling == UART_OVERSAMPLING_8) + { + switch (clocksource) + { +#if defined(USART2) + case UART_CLOCKSOURCE_PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + break; +#endif /* USART2 */ + case UART_CLOCKSOURCE_PCLK2: + pclk = HAL_RCC_GetPCLK2Freq(); + break; + case UART_CLOCKSOURCE_HSI: + pclk = (uint32_t) HSI_VALUE; + break; + case UART_CLOCKSOURCE_SYSCLK: + pclk = HAL_RCC_GetSysClockFreq(); + break; + case UART_CLOCKSOURCE_LSE: + pclk = (uint32_t) LSE_VALUE; + break; + default: + pclk = 0U; + ret = HAL_ERROR; + break; + } + + /* USARTDIV must be greater than or equal to 0d16 */ + if (pclk != 0U) + { + usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + { + brrtemp = (uint16_t)(usartdiv & 0xFFF0U); + brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); + huart->Instance->BRR = brrtemp; + } + else + { + ret = HAL_ERROR; + } + } + } + else + { + switch (clocksource) + { +#if defined(USART2) + case UART_CLOCKSOURCE_PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + break; +#endif /* USART2 */ + case UART_CLOCKSOURCE_PCLK2: + pclk = HAL_RCC_GetPCLK2Freq(); + break; + case UART_CLOCKSOURCE_HSI: + pclk = (uint32_t) HSI_VALUE; + break; + case UART_CLOCKSOURCE_SYSCLK: + pclk = HAL_RCC_GetSysClockFreq(); + break; + case UART_CLOCKSOURCE_LSE: + pclk = (uint32_t) LSE_VALUE; + break; + default: + pclk = 0U; + ret = HAL_ERROR; + break; + } + + if (pclk != 0U) + { + /* USARTDIV must be greater than or equal to 0d16 */ + usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + { + huart->Instance->BRR = (uint16_t)usartdiv; + } + else + { + ret = HAL_ERROR; + } + } + } + + /* Initialize the number of data to process during RX/TX ISR execution */ + huart->NbTxDataToProcess = 1; + huart->NbRxDataToProcess = 1; + + /* Clear ISR function pointers */ + huart->RxISR = NULL; + huart->TxISR = NULL; + + return ret; +} + +/** + * @brief Configure the UART peripheral advanced features. + * @param huart UART handle. + * @retval None + */ +void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) +{ + /* Check whether the set of advanced features to configure is properly set */ + assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); + + /* if required, configure RX/TX pins swap */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) + { + assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); + } + + /* if required, configure TX pin active level inversion */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) + { + assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); + } + + /* if required, configure RX pin active level inversion */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) + { + assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); + } + + /* if required, configure data inversion */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) + { + assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); + } + + /* if required, configure RX overrun detection disabling */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) + { + assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); + MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); + } + +#if defined(HAL_DMA_MODULE_ENABLED) + /* if required, configure DMA disabling on reception error */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) + { + assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); + MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); + } +#endif /* HAL_DMA_MODULE_ENABLED */ + + /* if required, configure auto Baud rate detection scheme */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) + { + assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance)); + assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); + /* set auto Baudrate detection parameters if detection is enabled */ + if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) + { + assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); + } + } + + /* if required, configure MSB first on communication line */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) + { + assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); + } +} + +/** + * @brief Check the UART Idle State. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) +{ + uint32_t tickstart; + + /* Initialize the UART ErrorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + /* Check if the Transmitter is enabled */ + if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) + { + /* Wait until TEACK flag is set */ + if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) + { + /* Disable TXE interrupt for the interrupt process */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE)); + + huart->gState = HAL_UART_STATE_READY; + + __HAL_UNLOCK(huart); + + /* Timeout occurred */ + return HAL_TIMEOUT; + } + } + + /* Check if the Receiver is enabled */ + if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) + { + /* Wait until REACK flag is set */ + if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) + { + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) + interrupts for the interrupt process */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + huart->RxState = HAL_UART_STATE_READY; + + __HAL_UNLOCK(huart); + + /* Timeout occurred */ + return HAL_TIMEOUT; + } + } + + /* Initialize the UART State */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + huart->RxEventType = HAL_UART_RXEVENT_TC; + + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief This function handles UART Communication Timeout. It waits + * until a flag is no longer in the specified status. + * @param huart UART handle. + * @param Flag Specifies the UART flag to check + * @param Status The actual Flag status (SET or RESET) + * @param Tickstart Tick start value + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout) +{ + /* Wait until flag is set */ + while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + + return HAL_TIMEOUT; + } + + if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC)) + { + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET) + { + /* Clear Overrun Error flag*/ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); + + /* Blocking error : transfer is aborted + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts if ongoing */ + UART_EndRxTransfer(huart); + + huart->ErrorCode = HAL_UART_ERROR_ORE; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_ERROR; + } + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) + { + /* Clear Receiver Timeout flag*/ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); + + /* Blocking error : transfer is aborted + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts if ongoing */ + UART_EndRxTransfer(huart); + + huart->ErrorCode = HAL_UART_ERROR_RTO; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_TIMEOUT; + } + } + } + } + return HAL_OK; +} + +/** + * @brief Start Receive operation in interrupt mode. + * @note This function could be called by all HAL UART API providing reception in Interrupt mode. + * @note When calling this function, parameters validity is considered as already checked, + * i.e. Rx State, buffer address, ... + * UART Handle is assumed as Locked. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + huart->pRxBuffPtr = pData; + huart->RxXferSize = Size; + huart->RxXferCount = Size; + huart->RxISR = NULL; + + /* Computation of UART mask to apply to RDR register */ + UART_MASK_COMPUTATION(huart); + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Configure Rx interrupt processing */ + if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess)) + { + /* Set the Rx ISR function pointer according to the data word length */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + huart->RxISR = UART_RxISR_16BIT_FIFOEN; + } + else + { + huart->RxISR = UART_RxISR_8BIT_FIFOEN; + } + + /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */ + if (huart->Init.Parity != UART_PARITY_NONE) + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + } + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); + } + else + { + /* Set the Rx ISR function pointer according to the data word length */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + huart->RxISR = UART_RxISR_16BIT; + } + else + { + huart->RxISR = UART_RxISR_8BIT; + } + + /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */ + if (huart->Init.Parity != UART_PARITY_NONE) + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); + } + else + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + } + } + return HAL_OK; +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Start Receive operation in DMA mode. + * @note This function could be called by all HAL UART API providing reception in DMA mode. + * @note When calling this function, parameters validity is considered as already checked, + * i.e. Rx State, buffer address, ... + * UART Handle is assumed as Locked. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef status; + uint16_t nbByte = Size; + + huart->pRxBuffPtr = pData; + huart->RxXferSize = Size; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + + if (huart->hdmarx != NULL) + { + /* Set the UART DMA transfer complete callback */ + huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; + + /* Set the UART DMA Half transfer complete callback */ + huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt; + + /* Set the DMA error callback */ + huart->hdmarx->XferErrorCallback = UART_DMAError; + + /* Set the DMA abort callback */ + huart->hdmarx->XferAbortCallback = NULL; + + /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter + should be aligned on a u16 frontier, so nbByte should be equal to Size * 2 */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + nbByte = Size * 2U; + } + + /* Check linked list mode */ + if ((huart->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if ((huart->hdmarx->LinkedListQueue != NULL) && (huart->hdmarx->LinkedListQueue->Head != NULL)) + { + /* Set DMA data size */ + huart->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = nbByte; + + /* Set DMA source address */ + huart->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = + (uint32_t)&huart->Instance->RDR; + + /* Set DMA destination address */ + huart->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)huart->pRxBuffPtr; + + /* Enable the UART receive DMA channel */ + status = HAL_DMAEx_List_Start_IT(huart->hdmarx); + } + else + { + /* Update status */ + status = HAL_ERROR; + } + } + else + { + /* Enable the UART receive DMA channel */ + status = HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, nbByte); + } + + if (status != HAL_OK) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + /* Restore huart->RxState to ready */ + huart->RxState = HAL_UART_STATE_READY; + + return HAL_ERROR; + } + } + + /* Enable the UART Parity Error Interrupt */ + if (huart->Init.Parity != UART_PARITY_NONE) + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + } + + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Enable the DMA transfer for the receiver request by setting the DMAR bit + in the UART CR3 register */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + return HAL_OK; +} + + +/** + * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion). + * @param huart UART handle. + * @retval None + */ +static void UART_EndTxTransfer(UART_HandleTypeDef *huart) +{ + /* Disable TXEIE, TCIE, TXFT interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_TXFTIE)); + + /* At end of Tx process, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; +} +#endif /* HAL_DMA_MODULE_ENABLED */ + + +/** + * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). + * @param huart UART handle. + * @retval None + */ +static void UART_EndRxTransfer(UART_HandleTypeDef *huart) +{ + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + + /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Reset RxIsr function pointer */ + huart->RxISR = NULL; +} + + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief DMA UART transmit process complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + /* Check if DMA in circular mode */ + if (hdma->Mode != DMA_LINKEDLIST_CIRCULAR) + { + huart->TxXferCount = 0U; + + /* Disable the DMA transfer for transmit request by resetting the DMAT bit + in the UART CR3 register */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Enable the UART Transmit Complete Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + } + /* DMA Circular mode */ + else + { +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Tx complete callback*/ + huart->TxCpltCallback(huart); +#else + /*Call legacy weak Tx complete callback*/ + HAL_UART_TxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } +} + +/** + * @brief DMA UART transmit process half complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Tx Half complete callback*/ + huart->TxHalfCpltCallback(huart); +#else + /*Call legacy weak Tx Half complete callback*/ + HAL_UART_TxHalfCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART receive process complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + /* Check if DMA in circular mode */ + if (hdma->Mode != DMA_LINKEDLIST_CIRCULAR) + { + huart->RxXferCount = 0U; + + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Disable the DMA transfer for the receiver request by resetting the DMAR bit + in the UART CR3 register */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* If Reception till IDLE event has been selected, Disable IDLE Interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } + } + + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + + /* Check current reception Mode : + If Reception till IDLE event has been selected : use Rx Event callback */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + else + { + /* In other cases : use Rx Complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } +} + +/** + * @brief DMA UART receive process half complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Half Transfer */ + huart->RxEventType = HAL_UART_RXEVENT_HT; + + /* Check current reception Mode : + If Reception till IDLE event has been selected : use Rx Event callback */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize / 2U); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize / 2U); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + else + { + /* In other cases : use Rx Half Complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Half complete callback*/ + huart->RxHalfCpltCallback(huart); +#else + /*Call legacy weak Rx Half complete callback*/ + HAL_UART_RxHalfCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } +} + +/** + * @brief DMA UART communication error callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMAError(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + const HAL_UART_StateTypeDef gstate = huart->gState; + const HAL_UART_StateTypeDef rxstate = huart->RxState; + + /* Stop UART DMA Tx request if ongoing */ + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && + (gstate == HAL_UART_STATE_BUSY_TX)) + { + huart->TxXferCount = 0U; + UART_EndTxTransfer(huart); + } + + /* Stop UART DMA Rx request if ongoing */ + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && + (rxstate == HAL_UART_STATE_BUSY_RX)) + { + huart->RxXferCount = 0U; + UART_EndRxTransfer(huart); + } + + huart->ErrorCode |= HAL_UART_ERROR_DMA; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART communication abort callback, when initiated by HAL services on Error + * (To be called at end of DMA Abort procedure following error occurrence). + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + huart->RxXferCount = 0U; + huart->TxXferCount = 0U; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART Tx communication abort callback, when initiated by user + * (To be called at end of DMA Tx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Rx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + huart->hdmatx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if (huart->hdmarx != NULL) + { + if (huart->hdmarx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + huart->TxXferCount = 0U; + huart->RxXferCount = 0U; + + /* Reset errorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Flush the whole TX FIFO (if needed) */ + if (huart->FifoMode == UART_FIFOMODE_ENABLE) + { + __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); + } + + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + huart->AbortCpltCallback(huart); +#else + /* Call legacy weak Abort complete callback */ + HAL_UART_AbortCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + + +/** + * @brief DMA UART Rx communication abort callback, when initiated by user + * (To be called at end of DMA Rx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Tx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + huart->hdmarx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if (huart->hdmatx != NULL) + { + if (huart->hdmatx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + huart->TxXferCount = 0U; + huart->RxXferCount = 0U; + + /* Reset errorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + huart->AbortCpltCallback(huart); +#else + /* Call legacy weak Abort complete callback */ + HAL_UART_AbortCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + + +/** + * @brief DMA UART Tx communication abort callback, when initiated by user by a call to + * HAL_UART_AbortTransmit_IT API (Abort only Tx transfer) + * (This callback is executed at end of DMA Tx Abort procedure following user abort request, + * and leads to user Tx Abort Complete callback execution). + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + huart->TxXferCount = 0U; + + /* Flush the whole TX FIFO (if needed) */ + if (huart->FifoMode == UART_FIFOMODE_ENABLE) + { + __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); + } + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + huart->AbortTransmitCpltCallback(huart); +#else + /* Call legacy weak Abort Transmit Complete Callback */ + HAL_UART_AbortTransmitCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART Rx communication abort callback, when initiated by user by a call to + * HAL_UART_AbortReceive_IT API (Abort only Rx transfer) + * (This callback is executed at end of DMA Rx Abort procedure following user abort request, + * and leads to user Rx Abort Complete callback execution). + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + huart->RxXferCount = 0U; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + huart->AbortReceiveCpltCallback(huart); +#else + /* Call legacy weak Abort Receive Complete Callback */ + HAL_UART_AbortReceiveCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief TX interrupt handler for 7 or 8 bits data word length . + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Transmit_IT(). + * @param huart UART handle. + * @retval None + */ +static void UART_TxISR_8BIT(UART_HandleTypeDef *huart) +{ + /* Check that a Tx process is ongoing */ + if (huart->gState == HAL_UART_STATE_BUSY_TX) + { + if (huart->TxXferCount == 0U) + { + /* Disable the UART Transmit Data Register Empty Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); + + /* Enable the UART Transmit Complete Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + } + else + { + huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF); + huart->pTxBuffPtr++; + huart->TxXferCount--; + } + } +} + +/** + * @brief TX interrupt handler for 9 bits data word length. + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Transmit_IT(). + * @param huart UART handle. + * @retval None + */ +static void UART_TxISR_16BIT(UART_HandleTypeDef *huart) +{ + const uint16_t *tmp; + + /* Check that a Tx process is ongoing */ + if (huart->gState == HAL_UART_STATE_BUSY_TX) + { + if (huart->TxXferCount == 0U) + { + /* Disable the UART Transmit Data Register Empty Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); + + /* Enable the UART Transmit Complete Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + } + else + { + tmp = (const uint16_t *) huart->pTxBuffPtr; + huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); + huart->pTxBuffPtr += 2U; + huart->TxXferCount--; + } + } +} + +/** + * @brief TX interrupt handler for 7 or 8 bits data word length and FIFO mode is enabled. + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Transmit_IT(). + * @param huart UART handle. + * @retval None + */ +static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) +{ + uint16_t nb_tx_data; + + /* Check that a Tx process is ongoing */ + if (huart->gState == HAL_UART_STATE_BUSY_TX) + { + for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) + { + if (huart->TxXferCount == 0U) + { + /* Disable the TX FIFO threshold interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); + + /* Enable the UART Transmit Complete Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + + break; /* force exit loop */ + } + else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U) + { + huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF); + huart->pTxBuffPtr++; + huart->TxXferCount--; + } + else + { + /* Nothing to do */ + } + } + } +} + +/** + * @brief TX interrupt handler for 9 bits data word length and FIFO mode is enabled. + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Transmit_IT(). + * @param huart UART handle. + * @retval None + */ +static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) +{ + const uint16_t *tmp; + uint16_t nb_tx_data; + + /* Check that a Tx process is ongoing */ + if (huart->gState == HAL_UART_STATE_BUSY_TX) + { + for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) + { + if (huart->TxXferCount == 0U) + { + /* Disable the TX FIFO threshold interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); + + /* Enable the UART Transmit Complete Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + + break; /* force exit loop */ + } + else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U) + { + tmp = (const uint16_t *) huart->pTxBuffPtr; + huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); + huart->pTxBuffPtr += 2U; + huart->TxXferCount--; + } + else + { + /* Nothing to do */ + } + } + } +} + +/** + * @brief Wrap up transmission in non-blocking mode. + * @param huart pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +static void UART_EndTransmit_IT(UART_HandleTypeDef *huart) +{ + /* Disable the UART Transmit Complete Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE); + + /* Tx process is ended, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + /* Cleat TxISR function pointer */ + huart->TxISR = NULL; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Tx complete callback*/ + huart->TxCpltCallback(huart); +#else + /*Call legacy weak Tx complete callback*/ + HAL_UART_TxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief RX interrupt handler for 7 or 8 bits data word length . + * @param huart UART handle. + * @retval None + */ +static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) +{ + uint16_t uhMask = huart->Mask; + uint16_t uhdata; + + /* Check that a Rx process is ongoing */ + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + uhdata = (uint16_t) READ_REG(huart->Instance->RDR); + *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); + huart->pRxBuffPtr++; + huart->RxXferCount--; + + if (huart->RxXferCount == 0U) + { + /* Disable the UART Parity Error Interrupt and RXNE interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + + /* Initialize type of RxEvent to Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + } + + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + /* Set reception type to Standard */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Disable IDLE interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) + { + /* Clear IDLE Flag */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + } + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + else + { + /* Standard reception API called */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + } + else + { + /* Clear RXNE interrupt flag */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + } +} + +/** + * @brief RX interrupt handler for 9 bits data word length . + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Receive_IT() + * @param huart UART handle. + * @retval None + */ +static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) +{ + uint16_t *tmp; + uint16_t uhMask = huart->Mask; + uint16_t uhdata; + + /* Check that a Rx process is ongoing */ + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + uhdata = (uint16_t) READ_REG(huart->Instance->RDR); + tmp = (uint16_t *) huart->pRxBuffPtr ; + *tmp = (uint16_t)(uhdata & uhMask); + huart->pRxBuffPtr += 2U; + huart->RxXferCount--; + + if (huart->RxXferCount == 0U) + { + /* Disable the UART Parity Error Interrupt and RXNE interrupt*/ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + + /* Initialize type of RxEvent to Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + } + + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + /* Set reception type to Standard */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Disable IDLE interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) + { + /* Clear IDLE Flag */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + } + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + else + { + /* Standard reception API called */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + } + else + { + /* Clear RXNE interrupt flag */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + } +} + +/** + * @brief RX interrupt handler for 7 or 8 bits data word length and FIFO mode is enabled. + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Receive_IT() + * @param huart UART handle. + * @retval None + */ +static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) +{ + uint16_t uhMask = huart->Mask; + uint16_t uhdata; + uint16_t nb_rx_data; + uint16_t rxdatacount; + uint32_t isrflags = READ_REG(huart->Instance->ISR); + uint32_t cr1its = READ_REG(huart->Instance->CR1); + uint32_t cr3its = READ_REG(huart->Instance->CR3); + + /* Check that a Rx process is ongoing */ + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + nb_rx_data = huart->NbRxDataToProcess; + while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) + { + uhdata = (uint16_t) READ_REG(huart->Instance->RDR); + *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); + huart->pRxBuffPtr++; + huart->RxXferCount--; + isrflags = READ_REG(huart->Instance->ISR); + + /* If some non blocking errors occurred */ + if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U) + { + /* UART parity error interrupt occurred -------------------------------------*/ + if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); + + huart->ErrorCode |= HAL_UART_ERROR_PE; + } + + /* UART frame error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); + + huart->ErrorCode |= HAL_UART_ERROR_FE; + } + + /* UART noise error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); + + huart->ErrorCode |= HAL_UART_ERROR_NE; + } + + /* Call UART Error Call back function if need be ----------------------------*/ + if (huart->ErrorCode != HAL_UART_ERROR_NONE) + { + /* Non Blocking error : transfer could go on. + Error is notified to user through user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + } + } + + if (huart->RxXferCount == 0U) + { + /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) + and RX FIFO Threshold interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + + /* Initialize type of RxEvent to Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + } + + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + /* Set reception type to Standard */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Disable IDLE interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) + { + /* Clear IDLE Flag */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + } + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + else + { + /* Standard reception API called */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + } + + /* When remaining number of bytes to receive is less than the RX FIFO + threshold, next incoming frames are processed as if FIFO mode was + disabled (i.e. one interrupt per received frame). + */ + rxdatacount = huart->RxXferCount; + if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) + { + /* Disable the UART RXFT interrupt*/ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); + + /* Update the RxISR function pointer */ + huart->RxISR = UART_RxISR_8BIT; + + /* Enable the UART Data Register Not Empty interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + } + } + else + { + /* Clear RXNE interrupt flag */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + } +} + +/** + * @brief RX interrupt handler for 9 bits data word length and FIFO mode is enabled. + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Receive_IT() + * @param huart UART handle. + * @retval None + */ +static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) +{ + uint16_t *tmp; + uint16_t uhMask = huart->Mask; + uint16_t uhdata; + uint16_t nb_rx_data; + uint16_t rxdatacount; + uint32_t isrflags = READ_REG(huart->Instance->ISR); + uint32_t cr1its = READ_REG(huart->Instance->CR1); + uint32_t cr3its = READ_REG(huart->Instance->CR3); + + /* Check that a Rx process is ongoing */ + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + nb_rx_data = huart->NbRxDataToProcess; + while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) + { + uhdata = (uint16_t) READ_REG(huart->Instance->RDR); + tmp = (uint16_t *) huart->pRxBuffPtr ; + *tmp = (uint16_t)(uhdata & uhMask); + huart->pRxBuffPtr += 2U; + huart->RxXferCount--; + isrflags = READ_REG(huart->Instance->ISR); + + /* If some non blocking errors occurred */ + if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U) + { + /* UART parity error interrupt occurred -------------------------------------*/ + if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); + + huart->ErrorCode |= HAL_UART_ERROR_PE; + } + + /* UART frame error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); + + huart->ErrorCode |= HAL_UART_ERROR_FE; + } + + /* UART noise error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); + + huart->ErrorCode |= HAL_UART_ERROR_NE; + } + + /* Call UART Error Call back function if need be ----------------------------*/ + if (huart->ErrorCode != HAL_UART_ERROR_NONE) + { + /* Non Blocking error : transfer could go on. + Error is notified to user through user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + } + } + + if (huart->RxXferCount == 0U) + { + /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) + and RX FIFO Threshold interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + + /* Initialize type of RxEvent to Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + } + + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + /* Set reception type to Standard */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Disable IDLE interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) + { + /* Clear IDLE Flag */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + } + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + else + { + /* Standard reception API called */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + } + + /* When remaining number of bytes to receive is less than the RX FIFO + threshold, next incoming frames are processed as if FIFO mode was + disabled (i.e. one interrupt per received frame). + */ + rxdatacount = huart->RxXferCount; + if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) + { + /* Disable the UART RXFT interrupt*/ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); + + /* Update the RxISR function pointer */ + huart->RxISR = UART_RxISR_16BIT; + + /* Enable the UART Data Register Not Empty interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + } + } + else + { + /* Clear RXNE interrupt flag */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + } +} + +/** + * @} + */ + +#endif /* HAL_UART_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_uart_ex.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_uart_ex.c new file mode 100644 index 0000000000..266673617c --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_uart_ex.c @@ -0,0 +1,1144 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_uart_ex.c + * @author MCD Application Team + * @brief Extended UART HAL module driver. + * This file provides firmware functions to manage the following extended + * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### UART peripheral extended features ##### + ============================================================================== + + (#) Declare a UART_HandleTypeDef handle structure. + + (#) For the UART RS485 Driver Enable mode, initialize the UART registers + by calling the HAL_RS485Ex_Init() API. + + (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming. + + -@- When UART operates in FIFO mode, FIFO mode must be enabled prior + starting RX/TX transfers. Also RX/TX FIFO thresholds must be + configured prior starting RX/TX transfers. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @defgroup UARTEx UARTEx + * @brief UART Extended HAL module driver + * @{ + */ + +#ifdef HAL_UART_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup UARTEX_Private_Constants UARTEx Private Constants + * @{ + */ +/* UART RX FIFO depth */ +#define RX_FIFO_DEPTH 8U + +/* UART TX FIFO depth */ +#define TX_FIFO_DEPTH 8U +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup UARTEx_Private_Functions UARTEx Private Functions + * @{ + */ +static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection); +static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup UARTEx_Exported_Functions UARTEx Exported Functions + * @{ + */ + +/** @defgroup UARTEx_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Extended Initialization and Configuration Functions + * +@verbatim +=============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to initialize the USARTx or the UARTy + in asynchronous mode. + (+) For the asynchronous mode the parameters below can be configured: + (++) Baud Rate + (++) Word Length + (++) Stop Bit + (++) Parity: If the parity is enabled, then the MSB bit of the data written + in the data register is transmitted but is changed by the parity bit. + (++) Hardware flow control + (++) Receiver/transmitter modes + (++) Over Sampling Method + (++) One-Bit Sampling Method + (+) For the asynchronous mode, the following advanced features can be configured as well: + (++) TX and/or RX pin level inversion + (++) data logical level inversion + (++) RX and TX pins swap + (++) RX overrun detection disabling + (++) DMA disabling on RX error + (++) MSB first on communication line + (++) auto Baud rate detection + [..] + The HAL_RS485Ex_Init() API follows the UART RS485 mode configuration + procedures (details for the procedures are available in reference manual). + +@endverbatim + + Depending on the frame length defined by the M1 and M0 bits (7-bit, + 8-bit or 9-bit), the possible UART formats are listed in the + following table. + + Table 1. UART frame format. + +-----------------------------------------------------------------------+ + | M1 bit | M0 bit | PCE bit | UART frame | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 0 | | SB | 8 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 0 | | SB | 9 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 0 | | SB | 7 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | + +-----------------------------------------------------------------------+ + + * @{ + */ + +/** + * @brief Initialize the RS485 Driver enable feature according to the specified + * parameters in the UART_InitTypeDef and creates the associated handle. + * @param huart UART handle. + * @param Polarity Select the driver enable polarity. + * This parameter can be one of the following values: + * @arg @ref UART_DE_POLARITY_HIGH DE signal is active high + * @arg @ref UART_DE_POLARITY_LOW DE signal is active low + * @param AssertionTime Driver Enable assertion time: + * 5-bit value defining the time between the activation of the DE (Driver Enable) + * signal and the beginning of the start bit. It is expressed in sample time + * units (1/8 or 1/16 bit time, depending on the oversampling rate) + * @param DeassertionTime Driver Enable deassertion time: + * 5-bit value defining the time between the end of the last stop bit, in a + * transmitted message, and the de-activation of the DE (Driver Enable) signal. + * It is expressed in sample time units (1/8 or 1/16 bit time, depending on the + * oversampling rate). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, + uint32_t DeassertionTime) +{ + uint32_t temp; + + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + /* Check the Driver Enable UART instance */ + assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance)); + + /* Check the Driver Enable polarity */ + assert_param(IS_UART_DE_POLARITY(Polarity)); + + /* Check the Driver Enable assertion time */ + assert_param(IS_UART_ASSERTIONTIME(AssertionTime)); + + /* Check the Driver Enable deassertion time */ + assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime)); + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK, CORTEX */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_UART_DISABLE(huart); + + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + { + return HAL_ERROR; + } + + /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */ + SET_BIT(huart->Instance->CR3, USART_CR3_DEM); + + /* Set the Driver Enable polarity */ + MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity); + + /* Set the Driver Enable assertion and deassertion times */ + temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS); + temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS); + MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp); + + /* Enable the Peripheral */ + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); +} + +/** + * @} + */ + +/** @defgroup UARTEx_Exported_Functions_Group2 IO operation functions + * @brief Extended functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + This subsection provides a set of Wakeup and FIFO mode related callback functions. + + (#) TX/RX Fifos Callbacks: + (+) HAL_UARTEx_RxFifoFullCallback() + (+) HAL_UARTEx_TxFifoEmptyCallback() + +@endverbatim + * @{ + */ + +/** + * @brief UART RX Fifo full callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UARTEx_RxFifoFullCallback can be implemented in the user file. + */ +} + +/** + * @brief UART TX Fifo empty callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UARTEx_TxFifoEmptyCallback can be implemented in the user file. + */ +} + +/** + * @} + */ + +/** @defgroup UARTEx_Exported_Functions_Group3 Peripheral Control functions + * @brief Extended Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] This section provides the following functions: + (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address + detection length to more than 4 bits for multiprocessor address mark wake up. + (+) HAL_UARTEx_StopModeWakeUpSourceConfig() API defines the wake-up from stop mode + trigger: address match, Start Bit detection or RXNE bit status. + (+) HAL_UARTEx_EnableStopMode() API enables the UART to wake up the MCU from stop mode + (+) HAL_UARTEx_DisableStopMode() API disables the above functionality + (+) HAL_UARTEx_EnableFifoMode() API enables the FIFO mode + (+) HAL_UARTEx_DisableFifoMode() API disables the FIFO mode + (+) HAL_UARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold + (+) HAL_UARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold + + [..] This subsection also provides a set of additional functions providing enhanced reception + services to user. (For example, these functions allow application to handle use cases + where number of data to be received is unknown). + + (#) Compared to standard reception services which only consider number of received + data elements as reception completion criteria, these functions also consider additional events + as triggers for updating reception status to caller : + (+) Detection of inactivity period (RX line has not been active for a given period). + (++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state) + for 1 frame time, after last received byte. + (++) RX inactivity detected by RTO, i.e. line has been in idle state + for a programmable time, after last received byte. + (+) Detection that a specific character has been received. + + (#) There are two mode of transfer: + (+) Blocking mode: The reception is performed in polling mode, until either expected number of data is received, + or till IDLE event occurs. Reception is handled only during function execution. + When function exits, no data reception could occur. HAL status and number of actually received data elements, + are returned by function after finishing transfer. + (+) Non-Blocking mode: The reception is performed using Interrupts or DMA. + These API's return the HAL status. + The end of the data processing will be indicated through the + dedicated UART IRQ when using Interrupt mode or the DMA IRQ when using DMA mode. + The HAL_UARTEx_RxEventCallback() user callback will be executed during Receive process + The HAL_UART_ErrorCallback()user callback will be executed when a reception error is detected. + + (#) Blocking mode API: + (+) HAL_UARTEx_ReceiveToIdle() + + (#) Non-Blocking mode API with Interrupt: + (+) HAL_UARTEx_ReceiveToIdle_IT() + + (#) Non-Blocking mode API with DMA: + (+) HAL_UARTEx_ReceiveToIdle_DMA() + +@endverbatim + * @{ + */ + +/** + * @brief By default in multiprocessor mode, when the wake up method is set + * to address mark, the UART handles only 4-bit long addresses detection; + * this API allows to enable longer addresses detection (6-, 7- or 8-bit + * long). + * @note Addresses detection lengths are: 6-bit address detection in 7-bit data mode, + * 7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode. + * @param huart UART handle. + * @param AddressLength This parameter can be one of the following values: + * @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address + * @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the address length parameter */ + assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength)); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_UART_DISABLE(huart); + + /* Set the address length */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength); + + /* Enable the Peripheral */ + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState to Ready */ + return (UART_CheckIdleState(huart)); +} + +/** + * @brief Set Wakeup from Stop mode interrupt flag selection. + * @note It is the application responsibility to enable the interrupt used as + * usart_wkup interrupt source before entering low-power mode. + * @param huart UART handle. + * @param WakeUpSelection Address match, Start Bit detection or RXNE/RXFNE bit status. + * This parameter can be one of the following values: + * @arg @ref UART_WAKEUP_ON_ADDRESS + * @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tickstart; + + /* check the wake-up from stop mode UART instance */ + assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance)); + /* check the wake-up selection parameter */ + assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_UART_DISABLE(huart); + + + if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS) + { + UARTEx_Wakeup_AddressConfig(huart, WakeUpSelection); + } + + /* Enable the Peripheral */ + __HAL_UART_ENABLE(huart); + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + /* Wait until REACK flag is set */ + if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) + { + status = HAL_TIMEOUT; + } + else + { + /* Initialize the UART State */ + huart->gState = HAL_UART_STATE_READY; + } + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return status; +} + +/** + * @brief Enable UART Stop Mode. + * @note The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart) +{ + /* Process Locked */ + __HAL_LOCK(huart); + + /* Set UESM bit */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_UESM); + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Disable UART Stop Mode. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart) +{ + /* Process Locked */ + __HAL_LOCK(huart); + + /* Clear UESM bit */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM); + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Enable the FIFO mode. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart) +{ + uint32_t tmpcr1; + + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Save actual UART configuration */ + tmpcr1 = READ_REG(huart->Instance->CR1); + + /* Disable UART */ + __HAL_UART_DISABLE(huart); + + /* Enable FIFO mode */ + SET_BIT(tmpcr1, USART_CR1_FIFOEN); + huart->FifoMode = UART_FIFOMODE_ENABLE; + + /* Restore UART configuration */ + WRITE_REG(huart->Instance->CR1, tmpcr1); + + /* Determine the number of data to process during RX/TX ISR execution */ + UARTEx_SetNbDataToProcess(huart); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Disable the FIFO mode. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart) +{ + uint32_t tmpcr1; + + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Save actual UART configuration */ + tmpcr1 = READ_REG(huart->Instance->CR1); + + /* Disable UART */ + __HAL_UART_DISABLE(huart); + + /* Enable FIFO mode */ + CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); + huart->FifoMode = UART_FIFOMODE_DISABLE; + + /* Restore UART configuration */ + WRITE_REG(huart->Instance->CR1, tmpcr1); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Set the TXFIFO threshold. + * @param huart UART handle. + * @param Threshold TX FIFO threshold value + * This parameter can be one of the following values: + * @arg @ref UART_TXFIFO_THRESHOLD_1_8 + * @arg @ref UART_TXFIFO_THRESHOLD_1_4 + * @arg @ref UART_TXFIFO_THRESHOLD_1_2 + * @arg @ref UART_TXFIFO_THRESHOLD_3_4 + * @arg @ref UART_TXFIFO_THRESHOLD_7_8 + * @arg @ref UART_TXFIFO_THRESHOLD_8_8 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) +{ + uint32_t tmpcr1; + + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); + assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Save actual UART configuration */ + tmpcr1 = READ_REG(huart->Instance->CR1); + + /* Disable UART */ + __HAL_UART_DISABLE(huart); + + /* Update TX threshold configuration */ + MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold); + + /* Determine the number of data to process during RX/TX ISR execution */ + UARTEx_SetNbDataToProcess(huart); + + /* Restore UART configuration */ + WRITE_REG(huart->Instance->CR1, tmpcr1); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Set the RXFIFO threshold. + * @param huart UART handle. + * @param Threshold RX FIFO threshold value + * This parameter can be one of the following values: + * @arg @ref UART_RXFIFO_THRESHOLD_1_8 + * @arg @ref UART_RXFIFO_THRESHOLD_1_4 + * @arg @ref UART_RXFIFO_THRESHOLD_1_2 + * @arg @ref UART_RXFIFO_THRESHOLD_3_4 + * @arg @ref UART_RXFIFO_THRESHOLD_7_8 + * @arg @ref UART_RXFIFO_THRESHOLD_8_8 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) +{ + uint32_t tmpcr1; + + /* Check the parameters */ + assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); + assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Save actual UART configuration */ + tmpcr1 = READ_REG(huart->Instance->CR1); + + /* Disable UART */ + __HAL_UART_DISABLE(huart); + + /* Update RX threshold configuration */ + MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold); + + /* Determine the number of data to process during RX/TX ISR execution */ + UARTEx_SetNbDataToProcess(huart); + + /* Restore UART configuration */ + WRITE_REG(huart->Instance->CR1, tmpcr1); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Receive an amount of data in blocking mode till either the expected number of data + * is received or an IDLE event occurs. + * @note HAL_OK is returned if reception is completed (expected number of data has been received) + * or if reception is stopped after IDLE event (less than the expected number of data has been received) + * In this case, RxLen output parameter indicates number of data available in reception buffer. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of uint16_t. In this case, Size must indicate the number + * of uint16_t available through pData. + * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO + * is not empty. Read operations from the RDR register are performed when + * RXFNE flag is set. From hardware perspective, RXFNE flag and + * RXNE are mapped on the same bit-field. + * @param huart UART handle. + * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). + * @param Size Amount of data elements (uint8_t or uint16_t) to be received. + * @param RxLen Number of data elements finally received + * (could be lower than Size, in case reception ends on IDLE event) + * @param Timeout Timeout duration expressed in ms (covers the whole reception sequence). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, + uint32_t Timeout) +{ + uint8_t *pdata8bits; + uint16_t *pdata16bits; + uint16_t uhMask; + uint32_t tickstart; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + huart->RxEventType = HAL_UART_RXEVENT_TC; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + huart->RxXferSize = Size; + huart->RxXferCount = Size; + + /* Computation of UART mask to apply to RDR register */ + UART_MASK_COMPUTATION(huart); + uhMask = huart->Mask; + + /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + pdata8bits = NULL; + pdata16bits = (uint16_t *) pData; + } + else + { + pdata8bits = pData; + pdata16bits = NULL; + } + + /* Initialize output number of received elements */ + *RxLen = 0U; + + /* as long as data have to be received */ + while (huart->RxXferCount > 0U) + { + /* Check if IDLE flag is set */ + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE)) + { + /* Clear IDLE flag in ISR */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + + /* If Set, but no data ever received, clear flag without exiting loop */ + /* If Set, and data has already been received, this means Idle Event is valid : End reception */ + if (*RxLen > 0U) + { + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + huart->RxState = HAL_UART_STATE_READY; + + return HAL_OK; + } + } + + /* Check if RXNE flag is set */ + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE)) + { + if (pdata8bits == NULL) + { + *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask); + pdata16bits++; + } + else + { + *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); + pdata8bits++; + } + /* Increment number of received elements */ + *RxLen += 1U; + huart->RxXferCount--; + } + + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + huart->RxState = HAL_UART_STATE_READY; + + return HAL_TIMEOUT; + } + } + } + + /* Set number of received elements in output parameter : RxLen */ + *RxLen = huart->RxXferSize - huart->RxXferCount; + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in interrupt mode till either the expected number of data + * is received or an IDLE event occurs. + * @note Reception is initiated by this function call. Further progress of reception is achieved thanks + * to UART interrupts raised by RXNE and IDLE events. Callback is called at end of reception indicating + * number of received data elements. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of uint16_t. In this case, Size must indicate the number + * of uint16_t available through pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). + * @param Size Amount of data elements (uint8_t or uint16_t) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Set Reception type to reception till IDLE Event*/ + huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + huart->RxEventType = HAL_UART_RXEVENT_TC; + + (void)UART_Start_Receive_IT(huart, pData, Size); + + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } + else + { + /* In case of errors already pending when reception is started, + Interrupts may have already been raised and lead to reception abortion. + (Overrun error for instance). + In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ + status = HAL_ERROR; + } + + return status; + } + else + { + return HAL_BUSY; + } +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Receive an amount of data in DMA mode till either the expected number + * of data is received or an IDLE event occurs. + * @note Reception is initiated by this function call. Further progress of reception is achieved thanks + * to DMA services, transferring automatically received data elements in user reception buffer and + * calling registered callbacks at half/end of reception. UART IDLE events are also used to consider + * reception phase as ended. In all cases, callback execution will indicate number of received data elements. + * @note When the UART parity is enabled (PCE = 1), the received data contain + * the parity bit (MSB position). + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of uint16_t. In this case, Size must indicate the number + * of uint16_t available through pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). + * @param Size Amount of data elements (uint8_t or uint16_t) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef status; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Set Reception type to reception till IDLE Event*/ + huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + huart->RxEventType = HAL_UART_RXEVENT_TC; + + status = UART_Start_Receive_DMA(huart, pData, Size); + + /* Check Rx process has been successfully started */ + if (status == HAL_OK) + { + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } + else + { + /* In case of errors already pending when reception is started, + Interrupts may have already been raised and lead to reception abortion. + (Overrun error for instance). + In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ + status = HAL_ERROR; + } + } + + return status; + } + else + { + return HAL_BUSY; + } +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Provide Rx Event type that has lead to RxEvent callback execution. + * @note When HAL_UARTEx_ReceiveToIdle_IT() or HAL_UARTEx_ReceiveToIdle_DMA() API are called, progress + * of reception process is provided to application through calls of Rx Event callback (either default one + * HAL_UARTEx_RxEventCallback() or user registered one). As several types of events could occur (IDLE event, + * Half Transfer, or Transfer Complete), this function allows to retrieve the Rx Event type that has lead + * to Rx Event callback execution. + * @note This function is expected to be called within the user implementation of Rx Event Callback, + * in order to provide the accurate value : + * In Interrupt Mode : + * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received) + * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of + * received data is lower than expected one) + * In DMA Mode : + * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received) + * - HAL_UART_RXEVENT_HT : when half of expected nb of data has been received + * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of + * received data is lower than expected one). + * In DMA mode, RxEvent callback could be called several times; + * When DMA is configured in Normal Mode, HT event does not stop Reception process; + * When DMA is configured in Circular Mode, HT, TC or IDLE events don't stop Reception process; + * @param huart UART handle. + * @retval Rx Event Type (return vale will be a value of @ref UART_RxEvent_Type_Values) + */ +HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart) +{ + /* Return Rx Event type value, as stored in UART handle */ + return (huart->RxEventType); +} + +/** + * @brief Set autonomous mode Configuration. + * @param huart UART handle. + * @param sConfig Autonomous mode structure parameters. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_SetConfigAutonomousMode(UART_HandleTypeDef *huart, + const UART_AutonomousModeConfTypeDef *sConfig) +{ + uint32_t tmpreg; + + if (huart->gState == HAL_UART_STATE_READY) + { + /* Check the parameters */ + assert_param(IS_UART_TRIGGER_POLARITY(sConfig->TriggerPolarity)); + assert_param(IS_UART_IDLE_FRAME_TRANSMIT(sConfig->IdleFrame)); + assert_param(IS_UART_TX_DATA_SIZE(sConfig->DataSize)); + if (IS_LPUART_INSTANCE(huart->Instance)) + { + assert_param(IS_LPUART_TRIGGER_SELECTION(sConfig->TriggerSelection)); + } + else + { + assert_param(IS_UART_TRIGGER_SELECTION(sConfig->TriggerSelection)); + } + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable UART */ + __HAL_UART_DISABLE(huart); + + /* Disable Transmitter */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_TE); + + /* Clear AUTOCR register */ + CLEAR_REG(huart->Instance->AUTOCR); + + /* UART AUTOCR Configuration */ + tmpreg = ((sConfig->DataSize << USART_AUTOCR_TDN_Pos) | (sConfig->TriggerPolarity) | \ + (sConfig->AutonomousModeState) | (sConfig->IdleFrame) | \ + (sConfig->TriggerSelection << USART_AUTOCR_TRIGSEL_Pos)); + + WRITE_REG(huart->Instance->AUTOCR, tmpreg); + + /* Enable UART */ + __HAL_UART_ENABLE(huart); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Get autonomous mode Configuration. + * @param huart UART handle. + * @param sConfig Autonomous mode structure parameters. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_GetConfigAutonomousMode(const UART_HandleTypeDef *huart, + UART_AutonomousModeConfTypeDef *sConfig) +{ + uint32_t tmpreg; + + /* Read AUTOCR register */ + tmpreg = READ_REG(huart->Instance->AUTOCR); + + /* Fill Autonomous structure parameter */ + sConfig->AutonomousModeState = (tmpreg & USART_AUTOCR_TRIGEN); + sConfig->TriggerSelection = ((tmpreg & USART_AUTOCR_TRIGSEL) >> USART_AUTOCR_TRIGSEL_Pos); + sConfig->TriggerPolarity = (tmpreg & USART_AUTOCR_TRIGPOL); + sConfig->IdleFrame = (tmpreg & USART_AUTOCR_IDLEDIS); + sConfig->DataSize = (tmpreg & USART_AUTOCR_TDN); + + return HAL_OK; +} + +/** + * @brief Clear autonomous mode Configuration. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_ClearConfigAutonomousMode(UART_HandleTypeDef *huart) +{ + if (huart->gState == HAL_UART_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable UART */ + __HAL_UART_DISABLE(huart); + + /* Clear AUTOCR register */ + CLEAR_REG(huart->Instance->AUTOCR); + + /* Enable UART */ + __HAL_UART_ENABLE(huart); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup UARTEx_Private_Functions + * @{ + */ + +/** + * @brief Initialize the UART wake-up from stop mode parameters when triggered by address detection. + * @param huart UART handle. + * @param WakeUpSelection UART wake up from stop mode parameters. + * @retval None + */ +static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection) +{ + assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength)); + + /* Set the USART address length */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength); + + /* Set the USART address node */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS)); +} + +/** + * @brief Calculate the number of data to process in RX/TX ISR. + * @note The RX FIFO depth and the TX FIFO depth is extracted from + * the UART configuration registers. + * @param huart UART handle. + * @retval None + */ +static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart) +{ + uint8_t rx_fifo_depth; + uint8_t tx_fifo_depth; + uint8_t rx_fifo_threshold; + uint8_t tx_fifo_threshold; + static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; + static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; + + if (huart->FifoMode == UART_FIFOMODE_DISABLE) + { + huart->NbTxDataToProcess = 1U; + huart->NbRxDataToProcess = 1U; + } + else + { + rx_fifo_depth = RX_FIFO_DEPTH; + tx_fifo_depth = TX_FIFO_DEPTH; + rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); + tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); + huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / + (uint16_t)denominator[tx_fifo_threshold]; + huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / + (uint16_t)denominator[rx_fifo_threshold]; + } +} +/** + * @} + */ + +#endif /* HAL_UART_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_usart.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_usart.c new file mode 100644 index 0000000000..2cc064b0fa --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_usart.c @@ -0,0 +1,3943 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_usart.c + * @author MCD Application Team + * @brief USART HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Universal Synchronous/Asynchronous Receiver Transmitter + * Peripheral (USART). + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State and Error functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + The USART HAL driver can be used as follows: + + (#) Declare a USART_HandleTypeDef handle structure (eg. USART_HandleTypeDef husart). + (#) Initialize the USART low level resources by implementing the HAL_USART_MspInit() API: + (++) Enable the USARTx interface clock. + (++) USART pins configuration: + (+++) Enable the clock for the USART GPIOs. + (+++) Configure these USART pins as alternate function pull-up. + (++) NVIC configuration if you need to use interrupt process (HAL_USART_Transmit_IT(), + HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs): + (+++) Configure the USARTx interrupt priority. + (+++) Enable the NVIC USART IRQ handle. + (++) USART interrupts handling: + -@@- The specific USART interrupts (Transmission complete interrupt, + RXNE interrupt and Error Interrupts) will be managed using the macros + __HAL_USART_ENABLE_IT() and __HAL_USART_DISABLE_IT() inside the transmit and receive process. + (++) DMA Configuration if you need to use DMA process (HAL_USART_Transmit_DMA() + HAL_USART_Receive_DMA() and HAL_USART_TransmitReceive_DMA() APIs): + (+++) Declare a DMA handle structure for the Tx/Rx channel. + (+++) Enable the DMAx interface clock. + (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. + (+++) Configure the DMA Tx/Rx channel. + (+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle. + (+++) Configure the priority and enable the NVIC for the transfer + complete interrupt on the DMA Tx/Rx channel. + + (#) Program the Baud Rate, Word Length, Stop Bit, Parity, and Mode + (Receiver/Transmitter) in the husart handle Init structure. + + (#) Initialize the USART registers by calling the HAL_USART_Init() API: + (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) + by calling the customized HAL_USART_MspInit(&husart) API. + + [..] + (@) To configure and enable/disable the USART to wake up the MCU from stop mode, resort to UART API's + HAL_UARTEx_StopModeWakeUpSourceConfig(), HAL_UARTEx_EnableStopMode() and + HAL_UARTEx_DisableStopMode() in casting the USART handle to UART type UART_HandleTypeDef. + + ##### Callback registration ##### + ================================== + + [..] + The compilation define USE_HAL_USART_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + [..] + Use Function HAL_USART_RegisterCallback() to register a user callback. + Function HAL_USART_RegisterCallback() allows to register following callbacks: + (+) TxHalfCpltCallback : Tx Half Complete Callback. + (+) TxCpltCallback : Tx Complete Callback. + (+) RxHalfCpltCallback : Rx Half Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) TxRxCpltCallback : Tx Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) AbortCpltCallback : Abort Complete Callback. + (+) RxFifoFullCallback : Rx Fifo Full Callback. + (+) TxFifoEmptyCallback : Tx Fifo Empty Callback. + (+) MspInitCallback : USART MspInit. + (+) MspDeInitCallback : USART MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + [..] + Use function HAL_USART_UnRegisterCallback() to reset a callback to the default + weak function. + HAL_USART_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) TxHalfCpltCallback : Tx Half Complete Callback. + (+) TxCpltCallback : Tx Complete Callback. + (+) RxHalfCpltCallback : Rx Half Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) TxRxCpltCallback : Tx Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) AbortCpltCallback : Abort Complete Callback. + (+) RxFifoFullCallback : Rx Fifo Full Callback. + (+) TxFifoEmptyCallback : Tx Fifo Empty Callback. + (+) MspInitCallback : USART MspInit. + (+) MspDeInitCallback : USART MspDeInit. + + [..] + By default, after the HAL_USART_Init() and when the state is HAL_USART_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples HAL_USART_TxCpltCallback(), HAL_USART_RxHalfCpltCallback(). + Exception done for MspInit and MspDeInit functions that are respectively + reset to the legacy weak functions in the HAL_USART_Init() + and HAL_USART_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_USART_Init() and HAL_USART_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand). + + [..] + Callbacks can be registered/unregistered in HAL_USART_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_USART_STATE_READY or HAL_USART_STATE_RESET state, thus registered (user) + MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_USART_RegisterCallback() before calling HAL_USART_DeInit() + or HAL_USART_Init() function. + + [..] + When The compilation define USE_HAL_USART_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available + and weak callbacks are used. + + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @defgroup USART USART + * @brief HAL USART Synchronous module driver + * @{ + */ + +#ifdef HAL_USART_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup USART_Private_Constants USART Private Constants + * @{ + */ +#define USART_DUMMY_DATA ((uint16_t) 0xFFFF) /*!< USART transmitted dummy data */ +#define USART_TEACK_REACK_TIMEOUT 1000U /*!< USART TX or RX enable acknowledge time-out value */ +#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ + USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8 | \ + USART_CR1_FIFOEN )) /*!< USART CR1 fields of parameters set by USART_SetConfig API */ + +#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | \ + USART_CR2_LBCL | USART_CR2_STOP | USART_CR2_SLVEN | \ + USART_CR2_DIS_NSS)) /*!< USART CR2 fields of parameters set by USART_SetConfig API */ + +#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_TXFTCFG | USART_CR3_RXFTCFG )) /*!< USART or USART CR3 fields of parameters set by USART_SetConfig API */ + +#define USART_BRR_MIN 0x10U /* USART BRR minimum authorized value */ +#define USART_BRR_MAX 0xFFFFU /* USART BRR maximum authorized value */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup USART_Private_Functions + * @{ + */ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) +void USART_InitCallbacksToDefault(USART_HandleTypeDef *husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ +static void USART_EndTransfer(USART_HandleTypeDef *husart); +#if defined(HAL_DMA_MODULE_ENABLED) +static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma); +static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma); +static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma); +static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma); +static void USART_DMAError(DMA_HandleTypeDef *hdma); +static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma); +static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma); +static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma); +#endif /* HAL_DMA_MODULE_ENABLED */ +static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout); +static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart); +static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart); +static void USART_TxISR_8BIT(USART_HandleTypeDef *husart); +static void USART_TxISR_16BIT(USART_HandleTypeDef *husart); +static void USART_TxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart); +static void USART_TxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart); +static void USART_EndTransmit_IT(USART_HandleTypeDef *husart); +static void USART_RxISR_8BIT(USART_HandleTypeDef *husart); +static void USART_RxISR_16BIT(USART_HandleTypeDef *husart); +static void USART_RxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart); +static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart); + + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup USART_Exported_Functions USART Exported Functions + * @{ + */ + +/** @defgroup USART_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to initialize the USART + in asynchronous and in synchronous modes. + (+) For the asynchronous mode only these parameters can be configured: + (++) Baud Rate + (++) Word Length + (++) Stop Bit + (++) Parity: If the parity is enabled, then the MSB bit of the data written + in the data register is transmitted but is changed by the parity bit. + (++) USART polarity + (++) USART phase + (++) USART LastBit + (++) Receiver/transmitter modes + + [..] + The HAL_USART_Init() function follows the USART synchronous configuration + procedure (details for the procedure are available in reference manual). + +@endverbatim + + Depending on the frame length defined by the M1 and M0 bits (7-bit, + 8-bit or 9-bit), the possible USART formats are listed in the + following table. + + Table 1. USART frame format. + +-----------------------------------------------------------------------+ + | M1 bit | M0 bit | PCE bit | USART frame | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 0 | | SB | 8 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 0 | | SB | 9 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 0 | | SB | 7 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | + +-----------------------------------------------------------------------+ + + * @{ + */ + +/** + * @brief Initialize the USART mode according to the specified + * parameters in the USART_InitTypeDef and initialize the associated handle. + * @param husart USART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart) +{ + /* Check the USART handle allocation */ + if (husart == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_USART_INSTANCE(husart->Instance)); + + if (husart->State == HAL_USART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + husart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + USART_InitCallbacksToDefault(husart); + + if (husart->MspInitCallback == NULL) + { + husart->MspInitCallback = HAL_USART_MspInit; + } + + /* Init the low level hardware */ + husart->MspInitCallback(husart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_USART_MspInit(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + + husart->State = HAL_USART_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_USART_DISABLE(husart); + + /* Set the Usart Communication parameters */ + if (USART_SetConfig(husart) == HAL_ERROR) + { + return HAL_ERROR; + } + + /* In Synchronous mode, the following bits must be kept cleared: + - LINEN bit in the USART_CR2 register + - HDSEL, SCEN and IREN bits in the USART_CR3 register. + */ + husart->Instance->CR2 &= ~USART_CR2_LINEN; + husart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN); + + /* Enable the Peripheral */ + __HAL_USART_ENABLE(husart); + + /* TEACK and/or REACK to check before moving husart->State to Ready */ + return (USART_CheckIdleState(husart)); +} + +/** + * @brief DeInitialize the USART peripheral. + * @param husart USART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart) +{ + /* Check the USART handle allocation */ + if (husart == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_USART_INSTANCE(husart->Instance)); + + husart->State = HAL_USART_STATE_BUSY; + + husart->Instance->CR1 = 0x0U; + husart->Instance->CR2 = 0x0U; + husart->Instance->CR3 = 0x0U; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + if (husart->MspDeInitCallback == NULL) + { + husart->MspDeInitCallback = HAL_USART_MspDeInit; + } + /* DeInit the low level hardware */ + husart->MspDeInitCallback(husart); +#else + /* DeInit the low level hardware */ + HAL_USART_MspDeInit(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + + husart->ErrorCode = HAL_USART_ERROR_NONE; + husart->State = HAL_USART_STATE_RESET; + + /* Process Unlock */ + __HAL_UNLOCK(husart); + + return HAL_OK; +} + +/** + * @brief Initialize the USART MSP. + * @param husart USART handle. + * @retval None + */ +__weak void HAL_USART_MspInit(USART_HandleTypeDef *husart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(husart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_USART_MspInit can be implemented in the user file + */ +} + +/** + * @brief DeInitialize the USART MSP. + * @param husart USART handle. + * @retval None + */ +__weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(husart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_USART_MspDeInit can be implemented in the user file + */ +} + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User USART Callback + * To be used to override the weak predefined callback + * @note The HAL_USART_RegisterCallback() may be called before HAL_USART_Init() in HAL_USART_STATE_RESET + * to register callbacks for HAL_USART_MSPINIT_CB_ID and HAL_USART_MSPDEINIT_CB_ID + * @param husart usart handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_USART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID + * @arg @ref HAL_USART_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_USART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID + * @arg @ref HAL_USART_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_USART_TX_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_USART_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_USART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + * @arg @ref HAL_USART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID + * @arg @ref HAL_USART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID + * @arg @ref HAL_USART_MSPINIT_CB_ID MspInit Callback ID + * @arg @ref HAL_USART_MSPDEINIT_CB_ID MspDeInit Callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status ++ */ +HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, + pUSART_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (husart->State == HAL_USART_STATE_READY) + { + switch (CallbackID) + { + case HAL_USART_TX_HALFCOMPLETE_CB_ID : + husart->TxHalfCpltCallback = pCallback; + break; + + case HAL_USART_TX_COMPLETE_CB_ID : + husart->TxCpltCallback = pCallback; + break; + + case HAL_USART_RX_HALFCOMPLETE_CB_ID : + husart->RxHalfCpltCallback = pCallback; + break; + + case HAL_USART_RX_COMPLETE_CB_ID : + husart->RxCpltCallback = pCallback; + break; + + case HAL_USART_TX_RX_COMPLETE_CB_ID : + husart->TxRxCpltCallback = pCallback; + break; + + case HAL_USART_ERROR_CB_ID : + husart->ErrorCallback = pCallback; + break; + + case HAL_USART_ABORT_COMPLETE_CB_ID : + husart->AbortCpltCallback = pCallback; + break; + + case HAL_USART_RX_FIFO_FULL_CB_ID : + husart->RxFifoFullCallback = pCallback; + break; + + case HAL_USART_TX_FIFO_EMPTY_CB_ID : + husart->TxFifoEmptyCallback = pCallback; + break; + + case HAL_USART_MSPINIT_CB_ID : + husart->MspInitCallback = pCallback; + break; + + case HAL_USART_MSPDEINIT_CB_ID : + husart->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (husart->State == HAL_USART_STATE_RESET) + { + switch (CallbackID) + { + case HAL_USART_MSPINIT_CB_ID : + husart->MspInitCallback = pCallback; + break; + + case HAL_USART_MSPDEINIT_CB_ID : + husart->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister an USART Callback + * USART callaback is redirected to the weak predefined callback + * @note The HAL_USART_UnRegisterCallback() may be called before HAL_USART_Init() in HAL_USART_STATE_RESET + * to un-register callbacks for HAL_USART_MSPINIT_CB_ID and HAL_USART_MSPDEINIT_CB_ID + * @param husart usart handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_USART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID + * @arg @ref HAL_USART_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_USART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID + * @arg @ref HAL_USART_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_USART_TX_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_USART_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_USART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + * @arg @ref HAL_USART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID + * @arg @ref HAL_USART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID + * @arg @ref HAL_USART_MSPINIT_CB_ID MspInit Callback ID + * @arg @ref HAL_USART_MSPDEINIT_CB_ID MspDeInit Callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (HAL_USART_STATE_READY == husart->State) + { + switch (CallbackID) + { + case HAL_USART_TX_HALFCOMPLETE_CB_ID : + husart->TxHalfCpltCallback = HAL_USART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + break; + + case HAL_USART_TX_COMPLETE_CB_ID : + husart->TxCpltCallback = HAL_USART_TxCpltCallback; /* Legacy weak TxCpltCallback */ + break; + + case HAL_USART_RX_HALFCOMPLETE_CB_ID : + husart->RxHalfCpltCallback = HAL_USART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + break; + + case HAL_USART_RX_COMPLETE_CB_ID : + husart->RxCpltCallback = HAL_USART_RxCpltCallback; /* Legacy weak RxCpltCallback */ + break; + + case HAL_USART_TX_RX_COMPLETE_CB_ID : + husart->TxRxCpltCallback = HAL_USART_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */ + break; + + case HAL_USART_ERROR_CB_ID : + husart->ErrorCallback = HAL_USART_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_USART_ABORT_COMPLETE_CB_ID : + husart->AbortCpltCallback = HAL_USART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + break; + + case HAL_USART_RX_FIFO_FULL_CB_ID : + husart->RxFifoFullCallback = HAL_USARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */ + break; + + case HAL_USART_TX_FIFO_EMPTY_CB_ID : + husart->TxFifoEmptyCallback = HAL_USARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ + break; + + case HAL_USART_MSPINIT_CB_ID : + husart->MspInitCallback = HAL_USART_MspInit; /* Legacy weak MspInitCallback */ + break; + + case HAL_USART_MSPDEINIT_CB_ID : + husart->MspDeInitCallback = HAL_USART_MspDeInit; /* Legacy weak MspDeInitCallback */ + break; + + default : + /* Update the error code */ + husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_USART_STATE_RESET == husart->State) + { + switch (CallbackID) + { + case HAL_USART_MSPINIT_CB_ID : + husart->MspInitCallback = HAL_USART_MspInit; + break; + + case HAL_USART_MSPDEINIT_CB_ID : + husart->MspDeInitCallback = HAL_USART_MspDeInit; + break; + + default : + /* Update the error code */ + husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + + +/** + * @} + */ + +/** @defgroup USART_Exported_Functions_Group2 IO operation functions + * @brief USART Transmit and Receive functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to manage the USART synchronous + data transfers. + + [..] The USART supports master mode only: it cannot receive or send data related to an input + clock (SCLK is always an output). + + [..] + + (#) There are two modes of transfer: + (++) Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode: The communication is performed using Interrupts + or DMA, These API's return the HAL status. + The end of the data processing will be indicated through the + dedicated USART IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback() user callbacks + will be executed respectively at the end of the transmit or Receive process + The HAL_USART_ErrorCallback()user callback will be executed when a communication error is detected + + (#) Blocking mode API's are : + (++) HAL_USART_Transmit() in simplex mode + (++) HAL_USART_Receive() in full duplex receive only + (++) HAL_USART_TransmitReceive() in full duplex mode + + (#) Non-Blocking mode API's with Interrupt are : + (++) HAL_USART_Transmit_IT() in simplex mode + (++) HAL_USART_Receive_IT() in full duplex receive only + (++) HAL_USART_TransmitReceive_IT() in full duplex mode + (++) HAL_USART_IRQHandler() + + (#) No-Blocking mode API's with DMA are : + (++) HAL_USART_Transmit_DMA() in simplex mode + (++) HAL_USART_Receive_DMA() in full duplex receive only + (++) HAL_USART_TransmitReceive_DMA() in full duplex mode + (++) HAL_USART_DMAPause() + (++) HAL_USART_DMAResume() + (++) HAL_USART_DMAStop() + + (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode: + (++) HAL_USART_TxCpltCallback() + (++) HAL_USART_RxCpltCallback() + (++) HAL_USART_TxHalfCpltCallback() + (++) HAL_USART_RxHalfCpltCallback() + (++) HAL_USART_ErrorCallback() + (++) HAL_USART_TxRxCpltCallback() + + (#) Non-Blocking mode transfers could be aborted using Abort API's : + (++) HAL_USART_Abort() + (++) HAL_USART_Abort_IT() + + (#) For Abort services based on interrupts (HAL_USART_Abort_IT), a Abort Complete Callbacks is provided: + (++) HAL_USART_AbortCpltCallback() + + (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. + Errors are handled as follows : + (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is + to be evaluated by user : this concerns Frame Error, + Parity Error or Noise Error in Interrupt mode reception . + Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify + error type, and HAL_USART_ErrorCallback() user callback is executed. + Transfer is kept ongoing on USART side. + If user wants to abort it, Abort services should be called by user. + (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted. + This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. + Error code is set to allow user to identify error type, + and HAL_USART_ErrorCallback() user callback is executed. + +@endverbatim + * @{ + */ + +/** + * @brief Simplex send an amount of data in blocking mode. + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pTxData. + * @param husart USART handle. + * @param pTxData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. + * @param Timeout Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size, + uint32_t Timeout) +{ + const uint8_t *ptxdata8bits; + const uint16_t *ptxdata16bits; + uint32_t tickstart; + + if (husart->State == HAL_USART_STATE_READY) + { + if ((pTxData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->ErrorCode = HAL_USART_ERROR_NONE; + husart->State = HAL_USART_STATE_BUSY_TX; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + husart->TxXferSize = Size; + husart->TxXferCount = Size; + + /* In case of 9bits/No Parity transfer, pTxData needs to be handled as a uint16_t pointer */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + ptxdata8bits = NULL; + ptxdata16bits = (const uint16_t *) pTxData; + } + else + { + ptxdata8bits = pTxData; + ptxdata16bits = NULL; + } + + /* Check the remaining data to be sent */ + while (husart->TxXferCount > 0U) + { + if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + if (ptxdata8bits == NULL) + { + husart->Instance->TDR = (uint16_t)(*ptxdata16bits & 0x01FFU); + ptxdata16bits++; + } + else + { + husart->Instance->TDR = (uint8_t)(*ptxdata8bits & 0xFFU); + ptxdata8bits++; + } + + husart->TxXferCount--; + } + + if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Clear Transmission Complete Flag */ + __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF); + + /* Clear overrun flag and discard the received data */ + __HAL_USART_CLEAR_OREFLAG(husart); + __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST); + __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST); + + /* At end of Tx process, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in blocking mode. + * @note To receive synchronous data, dummy data are simultaneously transmitted. + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pRxData. + * @param husart USART handle. + * @param pRxData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @param Timeout Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) +{ + uint8_t *prxdata8bits; + uint16_t *prxdata16bits; + uint16_t uhMask; + uint32_t tickstart; + + if (husart->State == HAL_USART_STATE_READY) + { + if ((pRxData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->ErrorCode = HAL_USART_ERROR_NONE; + husart->State = HAL_USART_STATE_BUSY_RX; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + husart->RxXferSize = Size; + husart->RxXferCount = Size; + + /* Computation of USART mask to apply to RDR register */ + USART_MASK_COMPUTATION(husart); + uhMask = husart->Mask; + + /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + prxdata8bits = NULL; + prxdata16bits = (uint16_t *) pRxData; + } + else + { + prxdata8bits = pRxData; + prxdata16bits = NULL; + } + + /* as long as data have to be received */ + while (husart->RxXferCount > 0U) + { + if (husart->SlaveMode == USART_SLAVEMODE_DISABLE) + { + /* Wait until TXE flag is set to send dummy byte in order to generate the + * clock for the slave to send data. + * Whatever the frame length (7, 8 or 9-bit long), the same dummy value + * can be written for all the cases. */ + if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x0FF); + } + + /* Wait for RXNE Flag */ + if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + if (prxdata8bits == NULL) + { + *prxdata16bits = (uint16_t)(husart->Instance->RDR & uhMask); + prxdata16bits++; + } + else + { + *prxdata8bits = (uint8_t)(husart->Instance->RDR & (uint8_t)(uhMask & 0xFFU)); + prxdata8bits++; + } + + husart->RxXferCount--; + + } + + /* Clear SPI slave underrun flag and discard transmit data */ + if (husart->SlaveMode == USART_SLAVEMODE_ENABLE) + { + __HAL_USART_CLEAR_UDRFLAG(husart); + __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST); + } + + /* At end of Rx process, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Full-Duplex Send and Receive an amount of data in blocking mode. + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number + * of u16 available through pTxData and through pRxData. + * @param husart USART handle. + * @param pTxData pointer to TX data buffer (u8 or u16 data elements). + * @param pRxData pointer to RX data buffer (u8 or u16 data elements). + * @param Size amount of data elements (u8 or u16) to be sent (same amount to be received). + * @param Timeout Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size, uint32_t Timeout) +{ + uint8_t *prxdata8bits; + uint16_t *prxdata16bits; + const uint8_t *ptxdata8bits; + const uint16_t *ptxdata16bits; + uint16_t uhMask; + uint16_t rxdatacount; + uint32_t tickstart; + + if (husart->State == HAL_USART_STATE_READY) + { + if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->ErrorCode = HAL_USART_ERROR_NONE; + husart->State = HAL_USART_STATE_BUSY_RX; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + husart->RxXferSize = Size; + husart->TxXferSize = Size; + husart->TxXferCount = Size; + husart->RxXferCount = Size; + + /* Computation of USART mask to apply to RDR register */ + USART_MASK_COMPUTATION(husart); + uhMask = husart->Mask; + + /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + prxdata8bits = NULL; + ptxdata8bits = NULL; + ptxdata16bits = (const uint16_t *) pTxData; + prxdata16bits = (uint16_t *) pRxData; + } + else + { + prxdata8bits = pRxData; + ptxdata8bits = pTxData; + ptxdata16bits = NULL; + prxdata16bits = NULL; + } + + if ((husart->TxXferCount == 0x01U) || (husart->SlaveMode == USART_SLAVEMODE_ENABLE)) + { + /* Wait until TXE flag is set to send data */ + if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + if (ptxdata8bits == NULL) + { + husart->Instance->TDR = (uint16_t)(*ptxdata16bits & uhMask); + ptxdata16bits++; + } + else + { + husart->Instance->TDR = (uint8_t)(*ptxdata8bits & (uint8_t)(uhMask & 0xFFU)); + ptxdata8bits++; + } + + husart->TxXferCount--; + } + + /* Check the remain data to be sent */ + /* rxdatacount is a temporary variable for MISRAC2012-Rule-13.5 */ + rxdatacount = husart->RxXferCount; + while ((husart->TxXferCount > 0U) || (rxdatacount > 0U)) + { + if (husart->TxXferCount > 0U) + { + /* Wait until TXE flag is set to send data */ + if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + if (ptxdata8bits == NULL) + { + husart->Instance->TDR = (uint16_t)(*ptxdata16bits & uhMask); + ptxdata16bits++; + } + else + { + husart->Instance->TDR = (uint8_t)(*ptxdata8bits & (uint8_t)(uhMask & 0xFFU)); + ptxdata8bits++; + } + + husart->TxXferCount--; + } + + if (husart->RxXferCount > 0U) + { + /* Wait for RXNE Flag */ + if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + if (prxdata8bits == NULL) + { + *prxdata16bits = (uint16_t)(husart->Instance->RDR & uhMask); + prxdata16bits++; + } + else + { + *prxdata8bits = (uint8_t)(husart->Instance->RDR & (uint8_t)(uhMask & 0xFFU)); + prxdata8bits++; + } + + husart->RxXferCount--; + } + rxdatacount = husart->RxXferCount; + } + + /* At end of TxRx process, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Send an amount of data in interrupt mode. + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pTxData. + * @param husart USART handle. + * @param pTxData pointer to data buffer (u8 or u16 data elements). + * @param Size amount of data elements (u8 or u16) to be sent. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size) +{ + if (husart->State == HAL_USART_STATE_READY) + { + if ((pTxData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->pTxBuffPtr = pTxData; + husart->TxXferSize = Size; + husart->TxXferCount = Size; + husart->TxISR = NULL; + + husart->ErrorCode = HAL_USART_ERROR_NONE; + husart->State = HAL_USART_STATE_BUSY_TX; + + /* The USART Error Interrupts: (Frame error, noise error, overrun error) + are not managed by the USART Transmit Process to avoid the overrun interrupt + when the usart mode is configured for transmit and receive "USART_MODE_TX_RX" + to benefit for the frame error and noise interrupts the usart mode should be + configured only for transmit "USART_MODE_TX" */ + + /* Configure Tx interrupt processing */ + if (husart->FifoMode == USART_FIFOMODE_ENABLE) + { + /* Set the Tx ISR function pointer according to the data word length */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + husart->TxISR = USART_TxISR_16BIT_FIFOEN; + } + else + { + husart->TxISR = USART_TxISR_8BIT_FIFOEN; + } + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + /* Enable the TX FIFO threshold interrupt */ + __HAL_USART_ENABLE_IT(husart, USART_IT_TXFT); + } + else + { + /* Set the Tx ISR function pointer according to the data word length */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + husart->TxISR = USART_TxISR_16BIT; + } + else + { + husart->TxISR = USART_TxISR_8BIT; + } + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + /* Enable the USART Transmit Data Register Empty Interrupt */ + __HAL_USART_ENABLE_IT(husart, USART_IT_TXE); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in interrupt mode. + * @note To receive synchronous data, dummy data are simultaneously transmitted. + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pRxData. + * @param husart USART handle. + * @param pRxData pointer to data buffer (u8 or u16 data elements). + * @param Size amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size) +{ + uint16_t nb_dummy_data; + + if (husart->State == HAL_USART_STATE_READY) + { + if ((pRxData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->pRxBuffPtr = pRxData; + husart->RxXferSize = Size; + husart->RxXferCount = Size; + husart->RxISR = NULL; + + USART_MASK_COMPUTATION(husart); + + husart->ErrorCode = HAL_USART_ERROR_NONE; + husart->State = HAL_USART_STATE_BUSY_RX; + + /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(husart->Instance->CR3, USART_CR3_EIE); + + /* Configure Rx interrupt processing */ + if ((husart->FifoMode == USART_FIFOMODE_ENABLE) && (Size >= husart->NbRxDataToProcess)) + { + /* Set the Rx ISR function pointer according to the data word length */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + husart->RxISR = USART_RxISR_16BIT_FIFOEN; + } + else + { + husart->RxISR = USART_RxISR_8BIT_FIFOEN; + } + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + /* Enable the USART Parity Error interrupt and RX FIFO Threshold interrupt */ + if (husart->Init.Parity != USART_PARITY_NONE) + { + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + } + SET_BIT(husart->Instance->CR3, USART_CR3_RXFTIE); + } + else + { + /* Set the Rx ISR function pointer according to the data word length */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + husart->RxISR = USART_RxISR_16BIT; + } + else + { + husart->RxISR = USART_RxISR_8BIT; + } + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + /* Enable the USART Parity Error and Data Register not empty Interrupts */ + if (husart->Init.Parity != USART_PARITY_NONE) + { + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); + } + else + { + SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + } + } + + if (husart->SlaveMode == USART_SLAVEMODE_DISABLE) + { + /* Send dummy data in order to generate the clock for the Slave to send the next data. + When FIFO mode is disabled only one data must be transferred. + When FIFO mode is enabled data must be transmitted until the RX FIFO reaches its threshold. + */ + if ((husart->FifoMode == USART_FIFOMODE_ENABLE) && (Size >= husart->NbRxDataToProcess)) + { + for (nb_dummy_data = husart->NbRxDataToProcess ; nb_dummy_data > 0U ; nb_dummy_data--) + { + husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); + } + } + else + { + husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); + } + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Full-Duplex Send and Receive an amount of data in interrupt mode. + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number + * of u16 available through pTxData and through pRxData. + * @param husart USART handle. + * @param pTxData pointer to TX data buffer (u8 or u16 data elements). + * @param pRxData pointer to RX data buffer (u8 or u16 data elements). + * @param Size amount of data elements (u8 or u16) to be sent (same amount to be received). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size) +{ + + if (husart->State == HAL_USART_STATE_READY) + { + if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->pRxBuffPtr = pRxData; + husart->RxXferSize = Size; + husart->RxXferCount = Size; + husart->pTxBuffPtr = pTxData; + husart->TxXferSize = Size; + husart->TxXferCount = Size; + + /* Computation of USART mask to apply to RDR register */ + USART_MASK_COMPUTATION(husart); + + husart->ErrorCode = HAL_USART_ERROR_NONE; + husart->State = HAL_USART_STATE_BUSY_TX_RX; + + /* Configure TxRx interrupt processing */ + if ((husart->FifoMode == USART_FIFOMODE_ENABLE) && (Size >= husart->NbRxDataToProcess)) + { + /* Set the Rx ISR function pointer according to the data word length */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + husart->TxISR = USART_TxISR_16BIT_FIFOEN; + husart->RxISR = USART_RxISR_16BIT_FIFOEN; + } + else + { + husart->TxISR = USART_TxISR_8BIT_FIFOEN; + husart->RxISR = USART_RxISR_8BIT_FIFOEN; + } + + /* Process Locked */ + __HAL_UNLOCK(husart); + + /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(husart->Instance->CR3, USART_CR3_EIE); + + if (husart->Init.Parity != USART_PARITY_NONE) + { + /* Enable the USART Parity Error interrupt */ + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + } + + /* Enable the TX and RX FIFO Threshold interrupts */ + SET_BIT(husart->Instance->CR3, (USART_CR3_TXFTIE | USART_CR3_RXFTIE)); + } + else + { + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + husart->TxISR = USART_TxISR_16BIT; + husart->RxISR = USART_RxISR_16BIT; + } + else + { + husart->TxISR = USART_TxISR_8BIT; + husart->RxISR = USART_RxISR_8BIT; + } + + /* Process Locked */ + __HAL_UNLOCK(husart); + + /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(husart->Instance->CR3, USART_CR3_EIE); + + /* Enable the USART Parity Error and USART Data Register not empty Interrupts */ + if (husart->Init.Parity != USART_PARITY_NONE) + { + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); + } + else + { + SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + } + + /* Enable the USART Transmit Data Register Empty Interrupt */ + SET_BIT(husart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Send an amount of data in DMA mode. + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pTxData. + * @param husart USART handle. + * @param pTxData pointer to data buffer (u8 or u16 data elements). + * @param Size amount of data elements (u8 or u16) to be sent. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size) +{ + HAL_StatusTypeDef status = HAL_OK; + const uint32_t *tmp; + uint16_t nbByte = Size; + + if (husart->State == HAL_USART_STATE_READY) + { + if ((pTxData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->pTxBuffPtr = pTxData; + husart->TxXferSize = Size; + husart->TxXferCount = Size; + + husart->ErrorCode = HAL_USART_ERROR_NONE; + husart->State = HAL_USART_STATE_BUSY_TX; + + if (husart->hdmatx != NULL) + { + /* Set the USART DMA transfer complete callback */ + husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt; + + /* Set the USART DMA Half transfer complete callback */ + husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt; + + /* Set the DMA error callback */ + husart->hdmatx->XferErrorCallback = USART_DMAError; + + /* In case of 9bits/No Parity transfer, pTxData buffer provided as input parameter + should be aligned on a u16 frontier, so nbByte should be equal to Size multiplied by 2 */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + nbByte = Size * 2U; + } + + tmp = (const uint32_t *)&pTxData; + + /* Check linked list mode */ + if ((husart->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if ((husart->hdmatx->LinkedListQueue != NULL) && (husart->hdmatx->LinkedListQueue->Head != NULL)) + { + /* Set DMA data size */ + husart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = nbByte; + + /* Set DMA source address */ + husart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = *(const uint32_t *)tmp; + + /* Set DMA destination address */ + husart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = + (uint32_t)&husart->Instance->TDR; + + /* Enable the USART transmit DMA channel */ + status = HAL_DMAEx_List_Start_IT(husart->hdmatx); + } + else + { + /* Update status */ + status = HAL_ERROR; + } + } + else + { + /* Enable the USART transmit DMA channel */ + status = HAL_DMA_Start_IT(husart->hdmatx, *(const uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, nbByte); + } + } + + if (status == HAL_OK) + { + /* Clear the TC flag in the ICR register */ + __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF); + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + /* Enable the DMA transfer for transmit request by setting the DMAT bit + in the USART CR3 register */ + SET_BIT(husart->Instance->CR3, USART_CR3_DMAT); + + return HAL_OK; + } + else + { + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + /* Restore husart->State to ready */ + husart->State = HAL_USART_STATE_READY; + + return HAL_ERROR; + } + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in DMA mode. + * @note When the USART parity is enabled (PCE = 1), the received data contain + * the parity bit (MSB position). + * @note The USART DMA transmit channel must be configured in order to generate the clock for the slave. + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pRxData. + * @param husart USART handle. + * @param pRxData pointer to data buffer (u8 or u16 data elements). + * @param Size amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t *tmp = (uint32_t *)&pRxData; + uint16_t nbByte = Size; + + /* Check that a Rx process is not already ongoing */ + if (husart->State == HAL_USART_STATE_READY) + { + if ((pRxData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->pRxBuffPtr = pRxData; + husart->RxXferSize = Size; + husart->pTxBuffPtr = pRxData; + husart->TxXferSize = Size; + + husart->ErrorCode = HAL_USART_ERROR_NONE; + husart->State = HAL_USART_STATE_BUSY_RX; + + if (husart->hdmarx != NULL) + { + /* Set the USART DMA Rx transfer complete callback */ + husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt; + + /* Set the USART DMA Half transfer complete callback */ + husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt; + + /* Set the USART DMA Rx transfer error callback */ + husart->hdmarx->XferErrorCallback = USART_DMAError; + + /* In case of 9bits/No Parity transfer, pTxData buffer provided as input parameter + should be aligned on a u16 frontier, so nbByte should be equal to Size multiplied by 2 */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + nbByte = Size * 2U; + } + + /* Check linked list mode */ + if ((husart->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if ((husart->hdmarx->LinkedListQueue != NULL) && (husart->hdmarx->LinkedListQueue->Head != NULL)) + { + /* Set DMA data size */ + husart->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = nbByte; + + /* Set DMA source address */ + husart->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = + (uint32_t)&husart->Instance->RDR; + + /* Set DMA destination address */ + husart->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = *(uint32_t *)tmp; + + /* Enable the USART receive DMA channel */ + status = HAL_DMAEx_List_Start_IT(husart->hdmarx); + } + else + { + /* Update status */ + status = HAL_ERROR; + } + } + else + { + /* Enable the USART receive DMA channel */ + status = HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t *)tmp, nbByte); + } + } + + if ((status == HAL_OK) && + (husart->SlaveMode == USART_SLAVEMODE_DISABLE)) + { + /* Enable the USART transmit DMA channel: the transmit channel is used in order + to generate in the non-blocking mode the clock to the slave device, + this mode isn't a simplex receive mode but a full-duplex receive mode */ + + /* Set the USART DMA Tx Complete and Error callback to Null */ + if (husart->hdmatx != NULL) + { + husart->hdmatx->XferErrorCallback = NULL; + husart->hdmatx->XferHalfCpltCallback = NULL; + husart->hdmatx->XferCpltCallback = NULL; + + /* Check linked list mode */ + if ((husart->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if ((husart->hdmatx->LinkedListQueue != NULL) && (husart->hdmatx->LinkedListQueue->Head != NULL)) + { + /* Set DMA data size */ + husart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = nbByte; + + /* Set DMA source address */ + husart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = *(uint32_t *)tmp; + + /* Set DMA destination address */ + husart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = + (uint32_t)&husart->Instance->TDR; + + /* Enable the USART transmit DMA channel */ + status = HAL_DMAEx_List_Start_IT(husart->hdmatx); + } + else + { + /* Update status */ + status = HAL_ERROR; + } + } + else + { + status = HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, nbByte); + } + } + } + + if (status == HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + if (husart->Init.Parity != USART_PARITY_NONE) + { + /* Enable the USART Parity Error Interrupt */ + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + } + + /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(husart->Instance->CR3, USART_CR3_EIE); + + /* Enable the DMA transfer for the receiver request by setting the DMAR bit + in the USART CR3 register */ + SET_BIT(husart->Instance->CR3, USART_CR3_DMAR); + + /* Enable the DMA transfer for transmit request by setting the DMAT bit + in the USART CR3 register */ + SET_BIT(husart->Instance->CR3, USART_CR3_DMAT); + + return HAL_OK; + } + else + { + if ((husart->hdmarx != NULL) && ((husart->hdmarx->Mode & DMA_LINKEDLIST) != DMA_LINKEDLIST)) + { + status = HAL_DMA_Abort(husart->hdmarx); + } + + /* No need to check on error code */ + UNUSED(status); + + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + /* Restore husart->State to ready */ + husart->State = HAL_USART_STATE_READY; + + return HAL_ERROR; + } + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode. + * @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit. + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number + * of u16 available through pTxData and through pRxData. + * @param husart USART handle. + * @param pTxData pointer to TX data buffer (u8 or u16 data elements). + * @param pRxData pointer to RX data buffer (u8 or u16 data elements). + * @param Size amount of data elements (u8 or u16) to be received/sent. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size) +{ + HAL_StatusTypeDef status; + const uint32_t *tmp; + uint16_t nbByte = Size; + + if (husart->State == HAL_USART_STATE_READY) + { + if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->pRxBuffPtr = pRxData; + husart->RxXferSize = Size; + husart->pTxBuffPtr = pTxData; + husart->TxXferSize = Size; + + husart->ErrorCode = HAL_USART_ERROR_NONE; + husart->State = HAL_USART_STATE_BUSY_TX_RX; + + if ((husart->hdmarx != NULL) && (husart->hdmatx != NULL)) + { + /* Set the USART DMA Rx transfer complete callback */ + husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt; + + /* Set the USART DMA Half transfer complete callback */ + husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt; + + /* Set the USART DMA Tx transfer complete callback */ + husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt; + + /* Set the USART DMA Half transfer complete callback */ + husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt; + + /* Set the USART DMA Tx transfer error callback */ + husart->hdmatx->XferErrorCallback = USART_DMAError; + + /* Set the USART DMA Rx transfer error callback */ + husart->hdmarx->XferErrorCallback = USART_DMAError; + + /* In case of 9bits/No Parity transfer, pTxData buffer provided as input parameter + should be aligned on a u16 frontier, so nbByte should be equal to Size multiplied by 2 */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + nbByte = Size * 2U; + } + + /* Check linked list mode */ + tmp = (uint32_t *)&pRxData; + if ((husart->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if ((husart->hdmarx->LinkedListQueue != NULL) && (husart->hdmarx->LinkedListQueue->Head != NULL)) + { + /* Set DMA data size */ + husart->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = nbByte; + + /* Set DMA source address */ + husart->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = + (uint32_t)&husart->Instance->RDR; + + /* Set DMA destination address */ + husart->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = *(const uint32_t *)tmp; + + /* Enable the USART receive DMA channel */ + status = HAL_DMAEx_List_Start_IT(husart->hdmarx); + } + else + { + /* Update status */ + status = HAL_ERROR; + } + } + else + { + /* Enable the USART receive DMA channel */ + status = HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(const uint32_t *)tmp, nbByte); + } + + /* Enable the USART transmit DMA channel */ + if (status == HAL_OK) + { + tmp = (const uint32_t *)&pTxData; + + /* Check linked list mode */ + if ((husart->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if ((husart->hdmatx->LinkedListQueue != NULL) && (husart->hdmatx->LinkedListQueue->Head != NULL)) + { + /* Set DMA data size */ + husart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = nbByte; + + /* Set DMA source address */ + husart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = *(const uint32_t *)tmp; + + /* Set DMA destination address */ + husart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = + (uint32_t)&husart->Instance->TDR; + + /* Enable the USART transmit DMA channel */ + status = HAL_DMAEx_List_Start_IT(husart->hdmatx); + } + else + { + /* Update status */ + status = HAL_ERROR; + } + } + else + { + status = HAL_DMA_Start_IT(husart->hdmatx, *(const uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, nbByte); + } + } + } + else + { + status = HAL_ERROR; + } + + if (status == HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + if (husart->Init.Parity != USART_PARITY_NONE) + { + /* Enable the USART Parity Error Interrupt */ + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + } + + /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(husart->Instance->CR3, USART_CR3_EIE); + + /* Clear the TC flag in the ICR register */ + __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF); + + /* Enable the DMA transfer for the receiver request by setting the DMAR bit + in the USART CR3 register */ + SET_BIT(husart->Instance->CR3, USART_CR3_DMAR); + + /* Enable the DMA transfer for transmit request by setting the DMAT bit + in the USART CR3 register */ + SET_BIT(husart->Instance->CR3, USART_CR3_DMAT); + + return HAL_OK; + } + else + { + if ((husart->hdmarx != NULL) && ((husart->hdmarx->Mode & DMA_LINKEDLIST) != DMA_LINKEDLIST)) + { + status = HAL_DMA_Abort(husart->hdmarx); + } + + /* No need to check on error code */ + UNUSED(status); + + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + /* Restore husart->State to ready */ + husart->State = HAL_USART_STATE_READY; + + return HAL_ERROR; + } + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Pause the DMA Transfer. + * @param husart USART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart) +{ + const HAL_USART_StateTypeDef state = husart->State; + + /* Process Locked */ + __HAL_LOCK(husart); + + if ((HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) && + (state == HAL_USART_STATE_BUSY_TX)) + { + /* Suspend the USART DMA Tx channel : use blocking DMA Suspend API (no callback) */ + if (husart->hdmatx != NULL) + { + /* Set the USART DMA Suspend callback to Null. + No call back execution at end of DMA Suspend procedure */ + husart->hdmatx->XferSuspendCallback = NULL; + + if (HAL_DMAEx_Suspend(husart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(husart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + else if ((state == HAL_USART_STATE_BUSY_RX) || + (state == HAL_USART_STATE_BUSY_TX_RX)) + { + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE); + CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); + + /* Set the USART DMA Suspend callback to Null. + No call back execution at end of DMA Suspend procedure */ + husart->hdmarx->XferSuspendCallback = NULL; + + if (HAL_DMAEx_Suspend(husart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(husart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + + if (state == HAL_USART_STATE_BUSY_TX_RX) + { + /* Set the USART DMA Suspend callback to Null. + No call back execution at end of DMA Suspend procedure */ + husart->hdmatx->XferSuspendCallback = NULL; + + if (HAL_DMAEx_Suspend(husart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(husart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + else + { + /* Nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; +} + +/** + * @brief Resume the DMA Transfer. + * @param husart USART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart) +{ + const HAL_USART_StateTypeDef state = husart->State; + + /* Process Locked */ + __HAL_LOCK(husart); + + if (state == HAL_USART_STATE_BUSY_TX) + { + /* Resume the USART DMA Tx channel */ + if (husart->hdmatx != NULL) + { + if (HAL_DMAEx_Resume(husart->hdmatx) != HAL_OK) + { + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + return HAL_ERROR; + } + } + } + else if ((state == HAL_USART_STATE_BUSY_RX) || + (state == HAL_USART_STATE_BUSY_TX_RX)) + { + /* Clear the Overrun flag before resuming the Rx transfer*/ + __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF); + + /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */ + if (husart->Init.Parity != USART_PARITY_NONE) + { + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + } + SET_BIT(husart->Instance->CR3, USART_CR3_EIE); + + /* Resume the USART DMA Rx channel */ + if (husart->hdmarx != NULL) + { + if (HAL_DMAEx_Resume(husart->hdmarx) != HAL_OK) + { + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + return HAL_ERROR; + } + } + + if (state == HAL_USART_STATE_BUSY_TX_RX) + { + /* Resume the USART DMA Tx channel */ + if (husart->hdmatx != NULL) + { + if (HAL_DMAEx_Resume(husart->hdmatx) != HAL_OK) + { + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + return HAL_ERROR; + } + } + } + } + else + { + /* Nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; +} + +/** + * @brief Stop the DMA Transfer. + * @param husart USART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart) +{ + /* The Lock is not implemented on this API to allow the user application + to call the HAL USART API under callbacks HAL_USART_TxCpltCallback() / HAL_USART_RxCpltCallback() / + HAL_USART_TxHalfCpltCallback / HAL_USART_RxHalfCpltCallback: + indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete + interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of + the stream and the corresponding call back is executed. */ + + /* Disable the USART Tx/Rx DMA requests */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the USART DMA tx channel */ + if (husart->hdmatx != NULL) + { + if (HAL_DMA_Abort(husart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(husart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + /* Abort the USART DMA rx channel */ + if (husart->hdmarx != NULL) + { + if (HAL_DMA_Abort(husart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(husart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + + USART_EndTransfer(husart); + husart->State = HAL_USART_STATE_READY; + + return HAL_OK; +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Abort ongoing transfers (blocking mode). + * @param husart USART handle. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable USART Interrupts (Tx and Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart) +{ + /* Disable TXEIE, TCIE, RXNE, RXFT, TXFT, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | + USART_CR1_TCIE)); + CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Abort the USART DMA Tx channel if enabled */ + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) + { + /* Disable the USART DMA Tx request if enabled */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the USART DMA Tx channel : use blocking DMA Abort API (no callback) */ + if (husart->hdmatx != NULL) + { + /* Set the USART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + husart->hdmatx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(husart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(husart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + + /* Abort the USART DMA Rx channel if enabled */ + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) + { + /* Disable the USART DMA Rx request if enabled */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the USART DMA Rx channel : use blocking DMA Abort API (no callback) */ + if (husart->hdmarx != NULL) + { + /* Set the USART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + husart->hdmarx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(husart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(husart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } +#endif /* HAL_DMA_MODULE_ENABLED */ + + /* Reset Tx and Rx transfer counters */ + husart->TxXferCount = 0U; + husart->RxXferCount = 0U; + + /* Clear the Error flags in the ICR register */ + __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF); + + /* Flush the whole TX FIFO (if needed) */ + if (husart->FifoMode == USART_FIFOMODE_ENABLE) + { + __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST); + } + + /* Discard the received data */ + __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST); + + /* Restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + + /* Reset Handle ErrorCode to No Error */ + husart->ErrorCode = HAL_USART_ERROR_NONE; + + return HAL_OK; +} + +/** + * @brief Abort ongoing transfers (Interrupt mode). + * @param husart USART handle. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable USART Interrupts (Tx and Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart) +{ + uint32_t abortcplt = 1U; + + /* Disable TXEIE, TCIE, RXNE, RXFT, TXFT, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | + USART_CR1_TCIE)); + CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* If DMA Tx and/or DMA Rx Handles are associated to USART Handle, DMA Abort complete callbacks should be initialised + before any call to DMA Abort functions */ + /* DMA Tx Handle is valid */ + if (husart->hdmatx != NULL) + { + /* Set DMA Abort Complete callback if USART DMA Tx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) + { + husart->hdmatx->XferAbortCallback = USART_DMATxAbortCallback; + } + else + { + husart->hdmatx->XferAbortCallback = NULL; + } + } + /* DMA Rx Handle is valid */ + if (husart->hdmarx != NULL) + { + /* Set DMA Abort Complete callback if USART DMA Rx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) + { + husart->hdmarx->XferAbortCallback = USART_DMARxAbortCallback; + } + else + { + husart->hdmarx->XferAbortCallback = NULL; + } + } + + /* Abort the USART DMA Tx channel if enabled */ + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) + { + /* Disable DMA Tx at USART level */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the USART DMA Tx channel : use non blocking DMA Abort API (callback) */ + if (husart->hdmatx != NULL) + { + /* USART Tx DMA Abort callback has already been initialised : + will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */ + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(husart->hdmatx) != HAL_OK) + { + husart->hdmatx->XferAbortCallback = NULL; + } + else + { + abortcplt = 0U; + } + } + } + + /* Abort the USART DMA Rx channel if enabled */ + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) + { + /* Disable the USART DMA Rx request if enabled */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the USART DMA Rx channel : use non blocking DMA Abort API (callback) */ + if (husart->hdmarx != NULL) + { + /* USART Rx DMA Abort callback has already been initialised : + will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */ + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK) + { + husart->hdmarx->XferAbortCallback = NULL; + abortcplt = 1U; + } + else + { + abortcplt = 0U; + } + } + } +#endif /* HAL_DMA_MODULE_ENABLED */ + + /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ + if (abortcplt == 1U) + { + /* Reset Tx and Rx transfer counters */ + husart->TxXferCount = 0U; + husart->RxXferCount = 0U; + + /* Reset errorCode */ + husart->ErrorCode = HAL_USART_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF); + + /* Flush the whole TX FIFO (if needed) */ + if (husart->FifoMode == USART_FIFOMODE_ENABLE) + { + __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST); + } + + /* Discard the received data */ + __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST); + + /* Restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Complete Callback */ + husart->AbortCpltCallback(husart); +#else + /* Call legacy weak Abort Complete Callback */ + HAL_USART_AbortCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} + +/** + * @brief Handle USART interrupt request. + * @param husart USART handle. + * @retval None + */ +void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) +{ + uint32_t isrflags = READ_REG(husart->Instance->ISR); + uint32_t cr1its = READ_REG(husart->Instance->CR1); + uint32_t cr3its = READ_REG(husart->Instance->CR3); + + uint32_t errorflags; + uint32_t errorcode; + + /* If no error occurs */ + errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF | + USART_ISR_UDR)); + if (errorflags == 0U) + { + /* USART in mode Receiver ---------------------------------------------------*/ + if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) + || ((cr3its & USART_CR3_RXFTIE) != 0U))) + { + if (husart->RxISR != NULL) + { + husart->RxISR(husart); + } + return; + } + } + + /* If some errors occur */ + if ((errorflags != 0U) + && (((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U) + || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)) != 0U))) + { + /* USART parity error interrupt occurred -------------------------------------*/ + if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) + { + __HAL_USART_CLEAR_IT(husart, USART_CLEAR_PEF); + + husart->ErrorCode |= HAL_USART_ERROR_PE; + } + + /* USART frame error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_USART_CLEAR_IT(husart, USART_CLEAR_FEF); + + husart->ErrorCode |= HAL_USART_ERROR_FE; + } + + /* USART noise error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_USART_CLEAR_IT(husart, USART_CLEAR_NEF); + + husart->ErrorCode |= HAL_USART_ERROR_NE; + } + + /* USART Over-Run interrupt occurred -----------------------------------------*/ + if (((isrflags & USART_ISR_ORE) != 0U) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || + ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U))) + { + __HAL_USART_CLEAR_IT(husart, USART_CLEAR_OREF); + + husart->ErrorCode |= HAL_USART_ERROR_ORE; + } + + /* USART Receiver Timeout interrupt occurred ---------------------------------*/ + if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U)) + { + __HAL_USART_CLEAR_IT(husart, USART_CLEAR_RTOF); + + husart->ErrorCode |= HAL_USART_ERROR_RTO; + } + + /* USART SPI slave underrun error interrupt occurred -------------------------*/ + if (((isrflags & USART_ISR_UDR) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + /* Ignore SPI slave underrun errors when reception is going on */ + if (husart->State == HAL_USART_STATE_BUSY_RX) + { + __HAL_USART_CLEAR_UDRFLAG(husart); + return; + } + else + { + __HAL_USART_CLEAR_UDRFLAG(husart); + husart->ErrorCode |= HAL_USART_ERROR_UDR; + } + } + + /* Call USART Error Call back function if need be --------------------------*/ + if (husart->ErrorCode != HAL_USART_ERROR_NONE) + { + /* USART in mode Receiver ---------------------------------------------------*/ + if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) + || ((cr3its & USART_CR3_RXFTIE) != 0U))) + { + if (husart->RxISR != NULL) + { + husart->RxISR(husart); + } + } + + /* If Overrun error occurs, or if any error occurs in DMA mode reception, + consider error as blocking */ + errorcode = husart->ErrorCode & HAL_USART_ERROR_ORE; + if ((HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) || + (errorcode != 0U)) + { + /* Blocking error : transfer is aborted + Set the USART state ready to be able to start again the process, + Disable Interrupts, and disable DMA requests, if ongoing */ + USART_EndTransfer(husart); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Abort the USART DMA Rx channel if enabled */ + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) + { + /* Disable the USART DMA Rx request if enabled */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR | USART_CR3_DMAR); + + /* Abort the USART DMA Tx channel */ + if (husart->hdmatx != NULL) + { + /* Set the USART Tx DMA Abort callback to NULL : no callback + executed at end of DMA abort procedure */ + husart->hdmatx->XferAbortCallback = NULL; + + /* Abort DMA TX */ + (void)HAL_DMA_Abort_IT(husart->hdmatx); + } + + /* Abort the USART DMA Rx channel */ + if (husart->hdmarx != NULL) + { + /* Set the USART Rx DMA Abort callback : + will lead to call HAL_USART_ErrorCallback() at end of DMA abort procedure */ + husart->hdmarx->XferAbortCallback = USART_DMAAbortOnError; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK) + { + /* Call Directly husart->hdmarx->XferAbortCallback function in case of error */ + husart->hdmarx->XferAbortCallback(husart->hdmarx); + } + } + else + { + /* Call user error callback */ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Error Callback */ + husart->ErrorCallback(husart); +#else + /* Call legacy weak Error Callback */ + HAL_USART_ErrorCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + } + else +#endif /* HAL_DMA_MODULE_ENABLED */ + { + /* Call user error callback */ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Error Callback */ + husart->ErrorCallback(husart); +#else + /* Call legacy weak Error Callback */ + HAL_USART_ErrorCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + } + else + { + /* Non Blocking error : transfer could go on. + Error is notified to user through user error callback */ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Error Callback */ + husart->ErrorCallback(husart); +#else + /* Call legacy weak Error Callback */ + HAL_USART_ErrorCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + husart->ErrorCode = HAL_USART_ERROR_NONE; + } + } + return; + + } /* End if some error occurs */ + + + /* USART in mode Transmitter ------------------------------------------------*/ + if (((isrflags & USART_ISR_TXE_TXFNF) != 0U) + && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U) + || ((cr3its & USART_CR3_TXFTIE) != 0U))) + { + if (husart->TxISR != NULL) + { + husart->TxISR(husart); + } + return; + } + + /* USART in mode Transmitter (transmission end) -----------------------------*/ + if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U)) + { + USART_EndTransmit_IT(husart); + return; + } + + /* USART TX Fifo Empty occurred ----------------------------------------------*/ + if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U)) + { +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Fifo Empty Callback */ + husart->TxFifoEmptyCallback(husart); +#else + /* Call legacy weak Tx Fifo Empty Callback */ + HAL_USARTEx_TxFifoEmptyCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + return; + } + + /* USART RX Fifo Full occurred ----------------------------------------------*/ + if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U)) + { +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Fifo Full Callback */ + husart->RxFifoFullCallback(husart); +#else + /* Call legacy weak Rx Fifo Full Callback */ + HAL_USARTEx_RxFifoFullCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + return; + } +} + +/** + * @brief Tx Transfer completed callback. + * @param husart USART handle. + * @retval None + */ +__weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(husart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_USART_TxCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Tx Half Transfer completed callback. + * @param husart USART handle. + * @retval None + */ +__weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(husart); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_USART_TxHalfCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Rx Transfer completed callback. + * @param husart USART handle. + * @retval None + */ +__weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(husart); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_USART_RxCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Rx Half Transfer completed callback. + * @param husart USART handle. + * @retval None + */ +__weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(husart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_USART_RxHalfCpltCallback can be implemented in the user file + */ +} + +/** + * @brief Tx/Rx Transfers completed callback for the non-blocking process. + * @param husart USART handle. + * @retval None + */ +__weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(husart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_USART_TxRxCpltCallback can be implemented in the user file + */ +} + +/** + * @brief USART error callback. + * @param husart USART handle. + * @retval None + */ +__weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(husart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_USART_ErrorCallback can be implemented in the user file. + */ +} + +/** + * @brief USART Abort Complete callback. + * @param husart USART handle. + * @retval None + */ +__weak void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(husart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_USART_AbortCpltCallback can be implemented in the user file. + */ +} + +/** + * @} + */ + +/** @defgroup USART_Exported_Functions_Group4 Peripheral State and Error functions + * @brief USART Peripheral State and Error functions + * +@verbatim + ============================================================================== + ##### Peripheral State and Error functions ##### + ============================================================================== + [..] + This subsection provides functions allowing to : + (+) Return the USART handle state + (+) Return the USART handle error code + +@endverbatim + * @{ + */ + + +/** + * @brief Return the USART handle state. + * @param husart pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART. + * @retval USART handle state + */ +HAL_USART_StateTypeDef HAL_USART_GetState(const USART_HandleTypeDef *husart) +{ + return husart->State; +} + +/** + * @brief Return the USART error code. + * @param husart pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART. + * @retval USART handle Error Code + */ +uint32_t HAL_USART_GetError(const USART_HandleTypeDef *husart) +{ + return husart->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup USART_Private_Functions USART Private Functions + * @{ + */ + +/** + * @brief Initialize the callbacks to their default values. + * @param husart USART handle. + * @retval none + */ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) +void USART_InitCallbacksToDefault(USART_HandleTypeDef *husart) +{ + /* Init the USART Callback settings */ + husart->TxHalfCpltCallback = HAL_USART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + husart->TxCpltCallback = HAL_USART_TxCpltCallback; /* Legacy weak TxCpltCallback */ + husart->RxHalfCpltCallback = HAL_USART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + husart->RxCpltCallback = HAL_USART_RxCpltCallback; /* Legacy weak RxCpltCallback */ + husart->TxRxCpltCallback = HAL_USART_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */ + husart->ErrorCallback = HAL_USART_ErrorCallback; /* Legacy weak ErrorCallback */ + husart->AbortCpltCallback = HAL_USART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + husart->RxFifoFullCallback = HAL_USARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */ + husart->TxFifoEmptyCallback = HAL_USARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ +} +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + +/** + * @brief End ongoing transfer on USART peripheral (following error detection or Transfer completion). + * @param husart USART handle. + * @retval None + */ +static void USART_EndTransfer(USART_HandleTypeDef *husart) +{ + /* Disable TXEIE, TCIE, RXNE, RXFT, TXFT, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | + USART_CR1_TCIE)); + CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); + + /* At end of process, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief DMA USART transmit process complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma) +{ + USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent); + + /* Check if DMA in circular mode */ + if (hdma->Mode != DMA_LINKEDLIST_CIRCULAR) + { + husart->TxXferCount = 0U; + + if (husart->State == HAL_USART_STATE_BUSY_TX) + { + /* Disable the DMA transfer for transmit request by resetting the DMAT bit + in the USART CR3 register */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); + + /* Enable the USART Transmit Complete Interrupt */ + __HAL_USART_ENABLE_IT(husart, USART_IT_TC); + } + } + /* DMA Circular mode */ + else + { + if (husart->State == HAL_USART_STATE_BUSY_TX) + { +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Complete Callback */ + husart->TxCpltCallback(husart); +#else + /* Call legacy weak Tx Complete Callback */ + HAL_USART_TxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + } +} + +/** + * @brief DMA USART transmit process half complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) +{ + USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent); + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Half Complete Callback */ + husart->TxHalfCpltCallback(husart); +#else + /* Call legacy weak Tx Half Complete Callback */ + HAL_USART_TxHalfCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA USART receive process complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +{ + USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent); + + /* Check if DMA in circular mode*/ + if (hdma->Mode != DMA_LINKEDLIST_CIRCULAR) + { + husart->RxXferCount = 0U; + + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE); + CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); + + /* Disable the DMA RX transfer for the receiver request by resetting the DMAR bit + in USART CR3 register */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); + /* similarly, disable the DMA TX transfer that was started to provide the + clock to the slave device */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); + + if (husart->State == HAL_USART_STATE_BUSY_RX) + { +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Complete Callback */ + husart->RxCpltCallback(husart); +#else + /* Call legacy weak Rx Complete Callback */ + HAL_USART_RxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + /* The USART state is HAL_USART_STATE_BUSY_TX_RX */ + else + { +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Rx Complete Callback */ + husart->TxRxCpltCallback(husart); +#else + /* Call legacy weak Tx Rx Complete Callback */ + HAL_USART_TxRxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + husart->State = HAL_USART_STATE_READY; + } + /* DMA circular mode */ + else + { + if (husart->State == HAL_USART_STATE_BUSY_RX) + { +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Complete Callback */ + husart->RxCpltCallback(husart); +#else + /* Call legacy weak Rx Complete Callback */ + HAL_USART_RxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + /* The USART state is HAL_USART_STATE_BUSY_TX_RX */ + else + { +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Rx Complete Callback */ + husart->TxRxCpltCallback(husart); +#else + /* Call legacy weak Tx Rx Complete Callback */ + HAL_USART_TxRxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + } +} + +/** + * @brief DMA USART receive process half complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) +{ + USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent); + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Half Complete Callback */ + husart->RxHalfCpltCallback(husart); +#else + /* Call legacy weak Rx Half Complete Callback */ + HAL_USART_RxHalfCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA USART communication error callback. + * @param hdma DMA handle. + * @retval None + */ +static void USART_DMAError(DMA_HandleTypeDef *hdma) +{ + USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent); + + husart->RxXferCount = 0U; + husart->TxXferCount = 0U; + USART_EndTransfer(husart); + + husart->ErrorCode |= HAL_USART_ERROR_DMA; + husart->State = HAL_USART_STATE_READY; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Error Callback */ + husart->ErrorCallback(husart); +#else + /* Call legacy weak Error Callback */ + HAL_USART_ErrorCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA USART communication abort callback, when initiated by HAL services on Error + * (To be called at end of DMA Abort procedure following error occurrence). + * @param hdma DMA handle. + * @retval None + */ +static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma) +{ + USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent); + husart->RxXferCount = 0U; + husart->TxXferCount = 0U; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Error Callback */ + husart->ErrorCallback(husart); +#else + /* Call legacy weak Error Callback */ + HAL_USART_ErrorCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA USART Tx communication abort callback, when initiated by user + * (To be called at end of DMA Tx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Rx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) +{ + USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent); + + husart->hdmatx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if (husart->hdmarx != NULL) + { + if (husart->hdmarx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + husart->TxXferCount = 0U; + husart->RxXferCount = 0U; + + /* Reset errorCode */ + husart->ErrorCode = HAL_USART_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF); + + /* Restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Complete Callback */ + husart->AbortCpltCallback(husart); +#else + /* Call legacy weak Abort Complete Callback */ + HAL_USART_AbortCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + +} + + +/** + * @brief DMA USART Rx communication abort callback, when initiated by user + * (To be called at end of DMA Rx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Tx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) +{ + USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent); + + husart->hdmarx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if (husart->hdmatx != NULL) + { + if (husart->hdmatx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + husart->TxXferCount = 0U; + husart->RxXferCount = 0U; + + /* Reset errorCode */ + husart->ErrorCode = HAL_USART_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF); + + /* Restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Complete Callback */ + husart->AbortCpltCallback(husart); +#else + /* Call legacy weak Abort Complete Callback */ + HAL_USART_AbortCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ +} + +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Handle USART Communication Timeout. It waits + * until a flag is no longer in the specified status. + * @param husart USART handle. + * @param Flag Specifies the USART flag to check. + * @param Status the actual Flag status (SET or RESET). + * @param Tickstart Tick start value + * @param Timeout timeout duration. + * @retval HAL status + */ +static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout) +{ + /* Wait until flag is set */ + while ((__HAL_USART_GET_FLAG(husart, Flag) ? SET : RESET) == Status) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_TIMEOUT; + } + } + } + return HAL_OK; +} + +/** + * @brief Configure the USART peripheral. + * @param husart USART handle. + * @retval HAL status + */ +static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart) +{ + uint32_t tmpreg; + USART_ClockSourceTypeDef clocksource; + HAL_StatusTypeDef ret = HAL_OK; + uint16_t brrtemp; + uint32_t usartdiv = 0x00000000; + uint32_t pclk; + + /* Check the parameters */ + assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity)); + assert_param(IS_USART_PHASE(husart->Init.CLKPhase)); + assert_param(IS_USART_LASTBIT(husart->Init.CLKLastBit)); + assert_param(IS_USART_BAUDRATE(husart->Init.BaudRate)); + assert_param(IS_USART_WORD_LENGTH(husart->Init.WordLength)); + assert_param(IS_USART_STOPBITS(husart->Init.StopBits)); + assert_param(IS_USART_PARITY(husart->Init.Parity)); + assert_param(IS_USART_MODE(husart->Init.Mode)); + assert_param(IS_USART_PRESCALER(husart->Init.ClockPrescaler)); + + /*-------------------------- USART CR1 Configuration -----------------------*/ + /* Clear M, PCE, PS, TE and RE bits and configure + * the USART Word Length, Parity and Mode: + * set the M bits according to husart->Init.WordLength value + * set PCE and PS bits according to husart->Init.Parity value + * set TE and RE bits according to husart->Init.Mode value + * force OVER8 to 1 to allow to reach the maximum speed (Fclock/8) */ + tmpreg = (uint32_t)husart->Init.WordLength | husart->Init.Parity | husart->Init.Mode | USART_CR1_OVER8; + MODIFY_REG(husart->Instance->CR1, USART_CR1_FIELDS, tmpreg); + + /*---------------------------- USART CR2 Configuration ---------------------*/ + /* Clear and configure the USART Clock, CPOL, CPHA, LBCL STOP and SLVEN bits: + * set CPOL bit according to husart->Init.CLKPolarity value + * set CPHA bit according to husart->Init.CLKPhase value + * set LBCL bit according to husart->Init.CLKLastBit value (used in SPI master mode only) + * set STOP[13:12] bits according to husart->Init.StopBits value */ + tmpreg = (uint32_t)(USART_CLOCK_ENABLE); + tmpreg |= (uint32_t)husart->Init.CLKLastBit; + tmpreg |= ((uint32_t)husart->Init.CLKPolarity | (uint32_t)husart->Init.CLKPhase); + tmpreg |= (uint32_t)husart->Init.StopBits; + MODIFY_REG(husart->Instance->CR2, USART_CR2_FIELDS, tmpreg); + + /*-------------------------- USART PRESC Configuration -----------------------*/ + /* Configure + * - USART Clock Prescaler : set PRESCALER according to husart->Init.ClockPrescaler value */ + MODIFY_REG(husart->Instance->PRESC, USART_PRESC_PRESCALER, husart->Init.ClockPrescaler); + + /*-------------------------- USART BRR Configuration -----------------------*/ + /* BRR is filled-up according to OVER8 bit setting which is forced to 1 */ + USART_GETCLOCKSOURCE(husart, clocksource); + + switch (clocksource) + { + case USART_CLOCKSOURCE_PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pclk, husart->Init.BaudRate, husart->Init.ClockPrescaler)); + break; + case USART_CLOCKSOURCE_PCLK2: + pclk = HAL_RCC_GetPCLK2Freq(); + usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pclk, husart->Init.BaudRate, husart->Init.ClockPrescaler)); + break; + case USART_CLOCKSOURCE_HSI: + usartdiv = (uint32_t)(USART_DIV_SAMPLING8(HSI_VALUE, husart->Init.BaudRate, husart->Init.ClockPrescaler)); + break; + case USART_CLOCKSOURCE_SYSCLK: + pclk = HAL_RCC_GetSysClockFreq(); + usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pclk, husart->Init.BaudRate, husart->Init.ClockPrescaler)); + break; + case USART_CLOCKSOURCE_LSE: + usartdiv = (uint32_t)(USART_DIV_SAMPLING8(LSE_VALUE, husart->Init.BaudRate, husart->Init.ClockPrescaler)); + break; + default: + ret = HAL_ERROR; + break; + } + + /* USARTDIV must be greater than or equal to 0d16 and smaller than or equal to ffff */ + if ((usartdiv >= USART_BRR_MIN) && (usartdiv <= USART_BRR_MAX)) + { + brrtemp = (uint16_t)(usartdiv & 0xFFF0U); + brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); + husart->Instance->BRR = brrtemp; + } + else + { + ret = HAL_ERROR; + } + + /* Initialize the number of data to process during RX/TX ISR execution */ + husart->NbTxDataToProcess = 1U; + husart->NbRxDataToProcess = 1U; + + /* Clear ISR function pointers */ + husart->RxISR = NULL; + husart->TxISR = NULL; + + return ret; +} + +/** + * @brief Check the USART Idle State. + * @param husart USART handle. + * @retval HAL status + */ +static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart) +{ + uint32_t tickstart; + + /* Initialize the USART ErrorCode */ + husart->ErrorCode = HAL_USART_ERROR_NONE; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + /* Check if the Transmitter is enabled */ + if ((husart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) + { + /* Wait until TEACK flag is set */ + if (USART_WaitOnFlagUntilTimeout(husart, USART_ISR_TEACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK) + { + /* Timeout occurred */ + return HAL_TIMEOUT; + } + } + /* Check if the Receiver is enabled */ + if ((husart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) + { + /* Wait until REACK flag is set */ + if (USART_WaitOnFlagUntilTimeout(husart, USART_ISR_REACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK) + { + /* Timeout occurred */ + return HAL_TIMEOUT; + } + } + + /* Initialize the USART state*/ + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; +} + +/** + * @brief Simplex send an amount of data in non-blocking mode. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_USART_Transmit_IT(). + * @note The USART errors are not managed to avoid the overrun error. + * @note ISR function executed when FIFO mode is disabled and when the + * data word length is less than 9 bits long. + * @param husart USART handle. + * @retval None + */ +static void USART_TxISR_8BIT(USART_HandleTypeDef *husart) +{ + const HAL_USART_StateTypeDef state = husart->State; + + /* Check that a Tx process is ongoing */ + if ((state == HAL_USART_STATE_BUSY_TX) || + (state == HAL_USART_STATE_BUSY_TX_RX)) + { + if (husart->TxXferCount == 0U) + { + /* Disable the USART Transmit data register empty interrupt */ + __HAL_USART_DISABLE_IT(husart, USART_IT_TXE); + + /* Enable the USART Transmit Complete Interrupt */ + __HAL_USART_ENABLE_IT(husart, USART_IT_TC); + } + else + { + husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr & (uint8_t)0xFF); + husart->pTxBuffPtr++; + husart->TxXferCount--; + } + } +} + +/** + * @brief Simplex send an amount of data in non-blocking mode. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_USART_Transmit_IT(). + * @note The USART errors are not managed to avoid the overrun error. + * @note ISR function executed when FIFO mode is disabled and when the + * data word length is 9 bits long. + * @param husart USART handle. + * @retval None + */ +static void USART_TxISR_16BIT(USART_HandleTypeDef *husart) +{ + const HAL_USART_StateTypeDef state = husart->State; + const uint16_t *tmp; + + if ((state == HAL_USART_STATE_BUSY_TX) || + (state == HAL_USART_STATE_BUSY_TX_RX)) + { + if (husart->TxXferCount == 0U) + { + /* Disable the USART Transmit data register empty interrupt */ + __HAL_USART_DISABLE_IT(husart, USART_IT_TXE); + + /* Enable the USART Transmit Complete Interrupt */ + __HAL_USART_ENABLE_IT(husart, USART_IT_TC); + } + else + { + tmp = (const uint16_t *) husart->pTxBuffPtr; + husart->Instance->TDR = (uint16_t)(*tmp & 0x01FFU); + husart->pTxBuffPtr += 2U; + husart->TxXferCount--; + } + } +} + +/** + * @brief Simplex send an amount of data in non-blocking mode. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_USART_Transmit_IT(). + * @note The USART errors are not managed to avoid the overrun error. + * @note ISR function executed when FIFO mode is enabled and when the + * data word length is less than 9 bits long. + * @param husart USART handle. + * @retval None + */ +static void USART_TxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart) +{ + const HAL_USART_StateTypeDef state = husart->State; + uint16_t nb_tx_data; + + /* Check that a Tx process is ongoing */ + if ((state == HAL_USART_STATE_BUSY_TX) || + (state == HAL_USART_STATE_BUSY_TX_RX)) + { + for (nb_tx_data = husart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) + { + if (husart->TxXferCount == 0U) + { + /* Disable the TX FIFO threshold interrupt */ + __HAL_USART_DISABLE_IT(husart, USART_IT_TXFT); + + /* Enable the USART Transmit Complete Interrupt */ + __HAL_USART_ENABLE_IT(husart, USART_IT_TC); + + break; /* force exit loop */ + } + else if (__HAL_USART_GET_FLAG(husart, USART_FLAG_TXFNF) == SET) + { + husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr & (uint8_t)0xFF); + husart->pTxBuffPtr++; + husart->TxXferCount--; + } + else + { + /* Nothing to do */ + } + } + } +} + +/** + * @brief Simplex send an amount of data in non-blocking mode. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_USART_Transmit_IT(). + * @note The USART errors are not managed to avoid the overrun error. + * @note ISR function executed when FIFO mode is enabled and when the + * data word length is 9 bits long. + * @param husart USART handle. + * @retval None + */ +static void USART_TxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart) +{ + const HAL_USART_StateTypeDef state = husart->State; + const uint16_t *tmp; + uint16_t nb_tx_data; + + /* Check that a Tx process is ongoing */ + if ((state == HAL_USART_STATE_BUSY_TX) || + (state == HAL_USART_STATE_BUSY_TX_RX)) + { + for (nb_tx_data = husart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) + { + if (husart->TxXferCount == 0U) + { + /* Disable the TX FIFO threshold interrupt */ + __HAL_USART_DISABLE_IT(husart, USART_IT_TXFT); + + /* Enable the USART Transmit Complete Interrupt */ + __HAL_USART_ENABLE_IT(husart, USART_IT_TC); + + break; /* force exit loop */ + } + else if (__HAL_USART_GET_FLAG(husart, USART_FLAG_TXFNF) == SET) + { + tmp = (const uint16_t *) husart->pTxBuffPtr; + husart->Instance->TDR = (uint16_t)(*tmp & 0x01FFU); + husart->pTxBuffPtr += 2U; + husart->TxXferCount--; + } + else + { + /* Nothing to do */ + } + } + } +} + +/** + * @brief Wraps up transmission in non-blocking mode. + * @param husart Pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART module. + * @retval None + */ +static void USART_EndTransmit_IT(USART_HandleTypeDef *husart) +{ + /* Disable the USART Transmit Complete Interrupt */ + __HAL_USART_DISABLE_IT(husart, USART_IT_TC); + + /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + __HAL_USART_DISABLE_IT(husart, USART_IT_ERR); + + /* Clear TxISR function pointer */ + husart->TxISR = NULL; + + if (husart->State == HAL_USART_STATE_BUSY_TX) + { + /* Clear overrun flag and discard the received data */ + __HAL_USART_CLEAR_OREFLAG(husart); + __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST); + + /* Tx process is completed, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Complete Callback */ + husart->TxCpltCallback(husart); +#else + /* Call legacy weak Tx Complete Callback */ + HAL_USART_TxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + else if (husart->RxXferCount == 0U) + { + /* TxRx process is completed, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Rx Complete Callback */ + husart->TxRxCpltCallback(husart); +#else + /* Call legacy weak Tx Rx Complete Callback */ + HAL_USART_TxRxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + else + { + /* Nothing to do */ + } +} + + +/** + * @brief Simplex receive an amount of data in non-blocking mode. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_USART_Receive_IT(). + * @note ISR function executed when FIFO mode is disabled and when the + * data word length is less than 9 bits long. + * @param husart USART handle + * @retval None + */ +static void USART_RxISR_8BIT(USART_HandleTypeDef *husart) +{ + const HAL_USART_StateTypeDef state = husart->State; + uint16_t txdatacount; + uint16_t uhMask = husart->Mask; + uint32_t txftie; + + if ((state == HAL_USART_STATE_BUSY_RX) || + (state == HAL_USART_STATE_BUSY_TX_RX)) + { + *husart->pRxBuffPtr = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask); + husart->pRxBuffPtr++; + husart->RxXferCount--; + + if (husart->RxXferCount == 0U) + { + /* Disable the USART Parity Error Interrupt and RXNE interrupt*/ + CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + + /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); + + /* Clear RxISR function pointer */ + husart->RxISR = NULL; + + /* txftie and txdatacount are temporary variables for MISRAC2012-Rule-13.5 */ + txftie = READ_BIT(husart->Instance->CR3, USART_CR3_TXFTIE); + txdatacount = husart->TxXferCount; + + if (state == HAL_USART_STATE_BUSY_RX) + { + /* Clear SPI slave underrun flag and discard transmit data */ + if (husart->SlaveMode == USART_SLAVEMODE_ENABLE) + { + __HAL_USART_CLEAR_UDRFLAG(husart); + __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST); + } + + /* Rx process is completed, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Complete Callback */ + husart->RxCpltCallback(husart); +#else + /* Call legacy weak Rx Complete Callback */ + HAL_USART_RxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) && + (txftie != USART_CR3_TXFTIE) && + (txdatacount == 0U)) + { + /* TxRx process is completed, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Rx Complete Callback */ + husart->TxRxCpltCallback(husart); +#else + /* Call legacy weak Tx Rx Complete Callback */ + HAL_USART_TxRxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + else + { + /* Nothing to do */ + } + } + else if ((state == HAL_USART_STATE_BUSY_RX) && + (husart->SlaveMode == USART_SLAVEMODE_DISABLE)) + { + /* Send dummy byte in order to generate the clock for the Slave to Send the next data */ + husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); + } + else + { + /* Nothing to do */ + } + } +} + +/** + * @brief Simplex receive an amount of data in non-blocking mode. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_USART_Receive_IT(). + * @note ISR function executed when FIFO mode is disabled and when the + * data word length is 9 bits long. + * @param husart USART handle + * @retval None + */ +static void USART_RxISR_16BIT(USART_HandleTypeDef *husart) +{ + const HAL_USART_StateTypeDef state = husart->State; + uint16_t txdatacount; + uint16_t *tmp; + uint16_t uhMask = husart->Mask; + uint32_t txftie; + + if ((state == HAL_USART_STATE_BUSY_RX) || + (state == HAL_USART_STATE_BUSY_TX_RX)) + { + tmp = (uint16_t *) husart->pRxBuffPtr; + *tmp = (uint16_t)(husart->Instance->RDR & uhMask); + husart->pRxBuffPtr += 2U; + husart->RxXferCount--; + + if (husart->RxXferCount == 0U) + { + /* Disable the USART Parity Error Interrupt and RXNE interrupt*/ + CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + + /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); + + /* Clear RxISR function pointer */ + husart->RxISR = NULL; + + /* txftie and txdatacount are temporary variables for MISRAC2012-Rule-13.5 */ + txftie = READ_BIT(husart->Instance->CR3, USART_CR3_TXFTIE); + txdatacount = husart->TxXferCount; + + if (state == HAL_USART_STATE_BUSY_RX) + { + /* Clear SPI slave underrun flag and discard transmit data */ + if (husart->SlaveMode == USART_SLAVEMODE_ENABLE) + { + __HAL_USART_CLEAR_UDRFLAG(husart); + __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST); + } + + /* Rx process is completed, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Complete Callback */ + husart->RxCpltCallback(husart); +#else + /* Call legacy weak Rx Complete Callback */ + HAL_USART_RxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) && + (txftie != USART_CR3_TXFTIE) && + (txdatacount == 0U)) + { + /* TxRx process is completed, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Rx Complete Callback */ + husart->TxRxCpltCallback(husart); +#else + /* Call legacy weak Tx Rx Complete Callback */ + HAL_USART_TxRxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + else + { + /* Nothing to do */ + } + } + else if ((state == HAL_USART_STATE_BUSY_RX) && + (husart->SlaveMode == USART_SLAVEMODE_DISABLE)) + { + /* Send dummy byte in order to generate the clock for the Slave to Send the next data */ + husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); + } + else + { + /* Nothing to do */ + } + } +} + +/** + * @brief Simplex receive an amount of data in non-blocking mode. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_USART_Receive_IT(). + * @note ISR function executed when FIFO mode is enabled and when the + * data word length is less than 9 bits long. + * @param husart USART handle + * @retval None + */ +static void USART_RxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart) +{ + HAL_USART_StateTypeDef state = husart->State; + uint16_t txdatacount; + uint16_t rxdatacount; + uint16_t uhMask = husart->Mask; + uint16_t nb_rx_data; + uint32_t txftie; + + /* Check that a Rx process is ongoing */ + if ((state == HAL_USART_STATE_BUSY_RX) || + (state == HAL_USART_STATE_BUSY_TX_RX)) + { + for (nb_rx_data = husart->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--) + { + if (__HAL_USART_GET_FLAG(husart, USART_FLAG_RXFNE) == SET) + { + *husart->pRxBuffPtr = (uint8_t)(husart->Instance->RDR & (uint8_t)(uhMask & 0xFFU)); + husart->pRxBuffPtr++; + husart->RxXferCount--; + + if (husart->RxXferCount == 0U) + { + /* Disable the USART Parity Error Interrupt */ + CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE); + + /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) + and RX FIFO Threshold interrupt */ + CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + + /* Clear RxISR function pointer */ + husart->RxISR = NULL; + + /* txftie and txdatacount are temporary variables for MISRAC2012-Rule-13.5 */ + txftie = READ_BIT(husart->Instance->CR3, USART_CR3_TXFTIE); + txdatacount = husart->TxXferCount; + + if (state == HAL_USART_STATE_BUSY_RX) + { + /* Clear SPI slave underrun flag and discard transmit data */ + if (husart->SlaveMode == USART_SLAVEMODE_ENABLE) + { + __HAL_USART_CLEAR_UDRFLAG(husart); + __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST); + } + + /* Rx process is completed, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + state = HAL_USART_STATE_READY; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Complete Callback */ + husart->RxCpltCallback(husart); +#else + /* Call legacy weak Rx Complete Callback */ + HAL_USART_RxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) && + (txftie != USART_CR3_TXFTIE) && + (txdatacount == 0U)) + { + /* TxRx process is completed, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + state = HAL_USART_STATE_READY; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Rx Complete Callback */ + husart->TxRxCpltCallback(husart); +#else + /* Call legacy weak Tx Rx Complete Callback */ + HAL_USART_TxRxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + else + { + /* Nothing to do */ + } + } + else if ((state == HAL_USART_STATE_BUSY_RX) && + (husart->SlaveMode == USART_SLAVEMODE_DISABLE)) + { + /* Send dummy byte in order to generate the clock for the Slave to Send the next data */ + husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); + } + else + { + /* Nothing to do */ + } + } + } + + /* When remaining number of bytes to receive is less than the RX FIFO + threshold, next incoming frames are processed as if FIFO mode was + disabled (i.e. one interrupt per received frame). + */ + rxdatacount = husart->RxXferCount; + if (((rxdatacount != 0U)) && (rxdatacount < husart->NbRxDataToProcess)) + { + /* Disable the USART RXFT interrupt*/ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_RXFTIE); + + /* Update the RxISR function pointer */ + husart->RxISR = USART_RxISR_8BIT; + + /* Enable the USART Data Register Not Empty interrupt */ + SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + + if ((husart->TxXferCount == 0U) && + (state == HAL_USART_STATE_BUSY_TX_RX) && + (husart->SlaveMode == USART_SLAVEMODE_DISABLE)) + { + /* Send dummy byte in order to generate the clock for the Slave to Send the next data */ + husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); + } + } + } + else + { + /* Clear RXNE interrupt flag */ + __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST); + } +} + +/** + * @brief Simplex receive an amount of data in non-blocking mode. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_USART_Receive_IT(). + * @note ISR function executed when FIFO mode is enabled and when the + * data word length is 9 bits long. + * @param husart USART handle + * @retval None + */ +static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart) +{ + HAL_USART_StateTypeDef state = husart->State; + uint16_t txdatacount; + uint16_t rxdatacount; + uint16_t *tmp; + uint16_t uhMask = husart->Mask; + uint16_t nb_rx_data; + uint32_t txftie; + + /* Check that a Tx process is ongoing */ + if ((state == HAL_USART_STATE_BUSY_RX) || + (state == HAL_USART_STATE_BUSY_TX_RX)) + { + for (nb_rx_data = husart->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--) + { + if (__HAL_USART_GET_FLAG(husart, USART_FLAG_RXFNE) == SET) + { + tmp = (uint16_t *) husart->pRxBuffPtr; + *tmp = (uint16_t)(husart->Instance->RDR & uhMask); + husart->pRxBuffPtr += 2U; + husart->RxXferCount--; + + if (husart->RxXferCount == 0U) + { + /* Disable the USART Parity Error Interrupt */ + CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE); + + /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) + and RX FIFO Threshold interrupt */ + CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + + /* Clear RxISR function pointer */ + husart->RxISR = NULL; + + /* txftie and txdatacount are temporary variables for MISRAC2012-Rule-13.5 */ + txftie = READ_BIT(husart->Instance->CR3, USART_CR3_TXFTIE); + txdatacount = husart->TxXferCount; + + if (state == HAL_USART_STATE_BUSY_RX) + { + /* Clear SPI slave underrun flag and discard transmit data */ + if (husart->SlaveMode == USART_SLAVEMODE_ENABLE) + { + __HAL_USART_CLEAR_UDRFLAG(husart); + __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST); + } + + /* Rx process is completed, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + state = HAL_USART_STATE_READY; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Complete Callback */ + husart->RxCpltCallback(husart); +#else + /* Call legacy weak Rx Complete Callback */ + HAL_USART_RxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) && + (txftie != USART_CR3_TXFTIE) && + (txdatacount == 0U)) + { + /* TxRx process is completed, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + state = HAL_USART_STATE_READY; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Rx Complete Callback */ + husart->TxRxCpltCallback(husart); +#else + /* Call legacy weak Tx Rx Complete Callback */ + HAL_USART_TxRxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + else + { + /* Nothing to do */ + } + } + else if ((state == HAL_USART_STATE_BUSY_RX) && + (husart->SlaveMode == USART_SLAVEMODE_DISABLE)) + { + /* Send dummy byte in order to generate the clock for the Slave to Send the next data */ + husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); + } + else + { + /* Nothing to do */ + } + } + } + + /* When remaining number of bytes to receive is less than the RX FIFO + threshold, next incoming frames are processed as if FIFO mode was + disabled (i.e. one interrupt per received frame). + */ + rxdatacount = husart->RxXferCount; + if (((rxdatacount != 0U)) && (rxdatacount < husart->NbRxDataToProcess)) + { + /* Disable the USART RXFT interrupt*/ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_RXFTIE); + + /* Update the RxISR function pointer */ + husart->RxISR = USART_RxISR_16BIT; + + /* Enable the USART Data Register Not Empty interrupt */ + SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + + if ((husart->TxXferCount == 0U) && + (state == HAL_USART_STATE_BUSY_TX_RX) && + (husart->SlaveMode == USART_SLAVEMODE_DISABLE)) + { + /* Send dummy byte in order to generate the clock for the Slave to Send the next data */ + husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); + } + } + } + else + { + /* Clear RXNE interrupt flag */ + __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST); + } +} + +/** + * @} + */ + +#endif /* HAL_USART_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_usart_ex.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_usart_ex.c new file mode 100644 index 0000000000..2132f70a1f --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_usart_ex.c @@ -0,0 +1,656 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_usart_ex.c + * @author MCD Application Team + * @brief Extended USART HAL module driver. + * This file provides firmware functions to manage the following extended + * functionalities of the Universal Synchronous Receiver Transmitter Peripheral (USART). + * + Peripheral Control functions + * + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### USART peripheral extended features ##### + ============================================================================== + + (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming. + + -@- When USART operates in FIFO mode, FIFO mode must be enabled prior + starting RX/TX transfers. Also RX/TX FIFO thresholds must be + configured prior starting RX/TX transfers. + + (#) Slave mode enabling/disabling and NSS pin configuration. + + -@- When USART operates in Slave mode, Slave mode must be enabled prior + starting RX/TX transfers. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +/** @defgroup USARTEx USARTEx + * @brief USART Extended HAL module driver + * @{ + */ + +#ifdef HAL_USART_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/** @defgroup USARTEx_Private_Constants USARTEx Private Constants + * @{ + */ +/* USART RX FIFO depth */ +#define RX_FIFO_DEPTH 8U + +/* USART TX FIFO depth */ +#define TX_FIFO_DEPTH 8U +/** + * @} + */ + +/* Private define ------------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup USARTEx_Private_Functions USARTEx Private Functions + * @{ + */ +static void USARTEx_SetNbDataToProcess(USART_HandleTypeDef *husart); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup USARTEx_Exported_Functions USARTEx Exported Functions + * @{ + */ + +/** @defgroup USARTEx_Exported_Functions_Group1 IO operation functions + * @brief Extended USART Transmit/Receive functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + This subsection provides a set of FIFO mode related callback functions. + + (#) TX/RX Fifos Callbacks: + (+) HAL_USARTEx_RxFifoFullCallback() + (+) HAL_USARTEx_TxFifoEmptyCallback() + +@endverbatim + * @{ + */ + +/** + * @brief USART RX Fifo full callback. + * @param husart USART handle. + * @retval None + */ +__weak void HAL_USARTEx_RxFifoFullCallback(USART_HandleTypeDef *husart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(husart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_USARTEx_RxFifoFullCallback can be implemented in the user file. + */ +} + +/** + * @brief USART TX Fifo empty callback. + * @param husart USART handle. + * @retval None + */ +__weak void HAL_USARTEx_TxFifoEmptyCallback(USART_HandleTypeDef *husart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(husart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_USARTEx_TxFifoEmptyCallback can be implemented in the user file. + */ +} + +/** + * @} + */ + +/** @defgroup USARTEx_Exported_Functions_Group2 Peripheral Control functions + * @brief Extended Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] This section provides the following functions: + (+) HAL_USARTEx_EnableSPISlaveMode() API enables the SPI slave mode + (+) HAL_USARTEx_DisableSPISlaveMode() API disables the SPI slave mode + (+) HAL_USARTEx_ConfigNSS API configures the Slave Select input pin (NSS) + (+) HAL_USARTEx_EnableFifoMode() API enables the FIFO mode + (+) HAL_USARTEx_DisableFifoMode() API disables the FIFO mode + (+) HAL_USARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold + (+) HAL_USARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold + + +@endverbatim + * @{ + */ + +/** + * @brief Enable the SPI slave mode. + * @note When the USART operates in SPI slave mode, it handles data flow using + * the serial interface clock derived from the external SCLK signal + * provided by the external master SPI device. + * @note In SPI slave mode, the USART must be enabled before starting the master + * communications (or between frames while the clock is stable). Otherwise, + * if the USART slave is enabled while the master is in the middle of a + * frame, it will become desynchronized with the master. + * @note The data register of the slave needs to be ready before the first edge + * of the communication clock or before the end of the ongoing communication, + * otherwise the SPI slave will transmit zeros. + * @param husart USART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USARTEx_EnableSlaveMode(USART_HandleTypeDef *husart) +{ + uint32_t tmpcr1; + + /* Check parameters */ + assert_param(IS_UART_SPI_SLAVE_INSTANCE(husart->Instance)); + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->State = HAL_USART_STATE_BUSY; + + /* Save actual USART configuration */ + tmpcr1 = READ_REG(husart->Instance->CR1); + + /* Disable USART */ + __HAL_USART_DISABLE(husart); + + /* In SPI slave mode mode, the following bits must be kept cleared: + - LINEN and CLKEN bit in the USART_CR2 register + - HDSEL, SCEN and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(husart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(husart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); + + /* Enable SPI slave mode */ + SET_BIT(husart->Instance->CR2, USART_CR2_SLVEN); + + /* Restore USART configuration */ + WRITE_REG(husart->Instance->CR1, tmpcr1); + + husart->SlaveMode = USART_SLAVEMODE_ENABLE; + + husart->State = HAL_USART_STATE_READY; + + /* Enable USART */ + __HAL_USART_ENABLE(husart); + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; +} + +/** + * @brief Disable the SPI slave mode. + * @param husart USART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USARTEx_DisableSlaveMode(USART_HandleTypeDef *husart) +{ + uint32_t tmpcr1; + + /* Check parameters */ + assert_param(IS_UART_SPI_SLAVE_INSTANCE(husart->Instance)); + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->State = HAL_USART_STATE_BUSY; + + /* Save actual USART configuration */ + tmpcr1 = READ_REG(husart->Instance->CR1); + + /* Disable USART */ + __HAL_USART_DISABLE(husart); + + /* Disable SPI slave mode */ + CLEAR_BIT(husart->Instance->CR2, USART_CR2_SLVEN); + + /* Restore USART configuration */ + WRITE_REG(husart->Instance->CR1, tmpcr1); + + husart->SlaveMode = USART_SLAVEMODE_DISABLE; + + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; +} + +/** + * @brief Configure the Slave Select input pin (NSS). + * @note Software NSS management: SPI slave will always be selected and NSS + * input pin will be ignored. + * @note Hardware NSS management: the SPI slave selection depends on NSS + * input pin. The slave is selected when NSS is low and deselected when + * NSS is high. + * @param husart USART handle. + * @param NSSConfig NSS configuration. + * This parameter can be one of the following values: + * @arg @ref USART_NSS_HARD + * @arg @ref USART_NSS_SOFT + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USARTEx_ConfigNSS(USART_HandleTypeDef *husart, uint32_t NSSConfig) +{ + uint32_t tmpcr1; + + /* Check parameters */ + assert_param(IS_UART_SPI_SLAVE_INSTANCE(husart->Instance)); + assert_param(IS_USART_NSS(NSSConfig)); + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->State = HAL_USART_STATE_BUSY; + + /* Save actual USART configuration */ + tmpcr1 = READ_REG(husart->Instance->CR1); + + /* Disable USART */ + __HAL_USART_DISABLE(husart); + + /* Program DIS_NSS bit in the USART_CR2 register */ + MODIFY_REG(husart->Instance->CR2, USART_CR2_DIS_NSS, NSSConfig); + + /* Restore USART configuration */ + WRITE_REG(husart->Instance->CR1, tmpcr1); + + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; +} + +/** + * @brief Enable the FIFO mode. + * @param husart USART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USARTEx_EnableFifoMode(USART_HandleTypeDef *husart) +{ + uint32_t tmpcr1; + + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(husart->Instance)); + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->State = HAL_USART_STATE_BUSY; + + /* Save actual USART configuration */ + tmpcr1 = READ_REG(husart->Instance->CR1); + + /* Disable USART */ + __HAL_USART_DISABLE(husart); + + /* Enable FIFO mode */ + SET_BIT(tmpcr1, USART_CR1_FIFOEN); + husart->FifoMode = USART_FIFOMODE_ENABLE; + + /* Restore USART configuration */ + WRITE_REG(husart->Instance->CR1, tmpcr1); + + /* Determine the number of data to process during RX/TX ISR execution */ + USARTEx_SetNbDataToProcess(husart); + + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; +} + +/** + * @brief Disable the FIFO mode. + * @param husart USART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USARTEx_DisableFifoMode(USART_HandleTypeDef *husart) +{ + uint32_t tmpcr1; + + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(husart->Instance)); + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->State = HAL_USART_STATE_BUSY; + + /* Save actual USART configuration */ + tmpcr1 = READ_REG(husart->Instance->CR1); + + /* Disable USART */ + __HAL_USART_DISABLE(husart); + + /* Enable FIFO mode */ + CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); + husart->FifoMode = USART_FIFOMODE_DISABLE; + + /* Restore USART configuration */ + WRITE_REG(husart->Instance->CR1, tmpcr1); + + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; +} + +/** + * @brief Set the TXFIFO threshold. + * @param husart USART handle. + * @param Threshold TX FIFO threshold value + * This parameter can be one of the following values: + * @arg @ref USART_TXFIFO_THRESHOLD_1_8 + * @arg @ref USART_TXFIFO_THRESHOLD_1_4 + * @arg @ref USART_TXFIFO_THRESHOLD_1_2 + * @arg @ref USART_TXFIFO_THRESHOLD_3_4 + * @arg @ref USART_TXFIFO_THRESHOLD_7_8 + * @arg @ref USART_TXFIFO_THRESHOLD_8_8 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USARTEx_SetTxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold) +{ + uint32_t tmpcr1; + + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(husart->Instance)); + assert_param(IS_USART_TXFIFO_THRESHOLD(Threshold)); + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->State = HAL_USART_STATE_BUSY; + + /* Save actual USART configuration */ + tmpcr1 = READ_REG(husart->Instance->CR1); + + /* Disable USART */ + __HAL_USART_DISABLE(husart); + + /* Update TX threshold configuration */ + MODIFY_REG(husart->Instance->CR3, USART_CR3_TXFTCFG, Threshold); + + /* Determine the number of data to process during RX/TX ISR execution */ + USARTEx_SetNbDataToProcess(husart); + + /* Restore USART configuration */ + WRITE_REG(husart->Instance->CR1, tmpcr1); + + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; +} + +/** + * @brief Set the RXFIFO threshold. + * @param husart USART handle. + * @param Threshold RX FIFO threshold value + * This parameter can be one of the following values: + * @arg @ref USART_RXFIFO_THRESHOLD_1_8 + * @arg @ref USART_RXFIFO_THRESHOLD_1_4 + * @arg @ref USART_RXFIFO_THRESHOLD_1_2 + * @arg @ref USART_RXFIFO_THRESHOLD_3_4 + * @arg @ref USART_RXFIFO_THRESHOLD_7_8 + * @arg @ref USART_RXFIFO_THRESHOLD_8_8 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USARTEx_SetRxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold) +{ + uint32_t tmpcr1; + + /* Check the parameters */ + assert_param(IS_UART_FIFO_INSTANCE(husart->Instance)); + assert_param(IS_USART_RXFIFO_THRESHOLD(Threshold)); + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->State = HAL_USART_STATE_BUSY; + + /* Save actual USART configuration */ + tmpcr1 = READ_REG(husart->Instance->CR1); + + /* Disable USART */ + __HAL_USART_DISABLE(husart); + + /* Update RX threshold configuration */ + MODIFY_REG(husart->Instance->CR3, USART_CR3_RXFTCFG, Threshold); + + /* Determine the number of data to process during RX/TX ISR execution */ + USARTEx_SetNbDataToProcess(husart); + + /* Restore USART configuration */ + WRITE_REG(husart->Instance->CR1, tmpcr1); + + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; +} + +/** + * @brief Set autonomous mode Configuration. + * @param husart USART handle. + * @param sConfig Autonomous mode structure parameters. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USARTEx_SetConfigAutonomousMode(USART_HandleTypeDef *husart, + const USART_AutonomousModeConfTypeDef *sConfig) +{ + uint32_t tmpreg; + + if (husart->State == HAL_USART_STATE_READY) + { + /* Check the parameters */ + assert_param(IS_USART_TRIGGER_POLARITY(sConfig->TriggerPolarity)); + assert_param(IS_USART_IDLE_FRAME_TRANSMIT(sConfig->IdleFrame)); + assert_param(IS_USART_TX_DATA_SIZE(sConfig->DataSize)); + assert_param(IS_USART_TRIGGER_SELECTION(sConfig->TriggerSelection)); + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->State = HAL_USART_STATE_BUSY; + + /* Disable USART */ + __HAL_USART_DISABLE(husart); + + /* Disable Transmitter */ + CLEAR_BIT(husart->Instance->CR1, USART_CR1_TE); + + /* Clear AUTOCR register */ + CLEAR_REG(husart->Instance->AUTOCR); + + /* USART AUTOCR Configuration */ + tmpreg = ((sConfig->DataSize << USART_AUTOCR_TDN_Pos) | (sConfig->TriggerPolarity) | + (sConfig->AutonomousModeState) | (sConfig->IdleFrame) | + (sConfig->TriggerSelection << USART_AUTOCR_TRIGSEL_Pos)); + + WRITE_REG(husart->Instance->AUTOCR, tmpreg); + + /* Enable USART */ + __HAL_USART_ENABLE(husart); + + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Get autonomous mode Configuration. + * @param husart USART handle. + * @param sConfig Autonomous mode structure parameters. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USARTEx_GetConfigAutonomousMode(const USART_HandleTypeDef *husart, + USART_AutonomousModeConfTypeDef *sConfig) +{ + uint32_t tmpreg; + + /* Read AUTOCR register */ + tmpreg = READ_REG(husart->Instance->AUTOCR); + + /* Fill Autonomous structure parameter */ + sConfig->AutonomousModeState = (tmpreg & USART_AUTOCR_TRIGEN); + sConfig->TriggerSelection = ((tmpreg & USART_AUTOCR_TRIGSEL) >> USART_AUTOCR_TRIGSEL_Pos); + sConfig->TriggerPolarity = (tmpreg & USART_AUTOCR_TRIGPOL); + sConfig->IdleFrame = (tmpreg & USART_AUTOCR_IDLEDIS); + sConfig->DataSize = (tmpreg & USART_AUTOCR_TDN); + + return HAL_OK; +} + +/** + * @brief Clear autonomous mode Configuration. + * @param husart USART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USARTEx_ClearConfigAutonomousMode(USART_HandleTypeDef *husart) +{ + if (husart->State == HAL_USART_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(husart); + + husart->State = HAL_USART_STATE_BUSY; + + /* Disable USART */ + __HAL_USART_DISABLE(husart); + + /* Clear AUTOCR register */ + CLEAR_REG(husart->Instance->AUTOCR); + + /* Enable USART */ + __HAL_USART_ENABLE(husart); + + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup USARTEx_Private_Functions + * @{ + */ + +/** + * @brief Calculate the number of data to process in RX/TX ISR. + * @note The RX FIFO depth and the TX FIFO depth is extracted from + * the USART configuration registers. + * @param husart USART handle. + * @retval None + */ +static void USARTEx_SetNbDataToProcess(USART_HandleTypeDef *husart) +{ + uint8_t rx_fifo_depth; + uint8_t tx_fifo_depth; + uint8_t rx_fifo_threshold; + uint8_t tx_fifo_threshold; + /* 2 0U/1U added for MISRAC2012-Rule-18.1_b and MISRAC2012-Rule-18.1_d */ + static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; + static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; + + if (husart->FifoMode == USART_FIFOMODE_DISABLE) + { + husart->NbTxDataToProcess = 1U; + husart->NbRxDataToProcess = 1U; + } + else + { + rx_fifo_depth = RX_FIFO_DEPTH; + tx_fifo_depth = TX_FIFO_DEPTH; + rx_fifo_threshold = (uint8_t)((READ_BIT(husart->Instance->CR3, + USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos) & 0xFFU); + tx_fifo_threshold = (uint8_t)((READ_BIT(husart->Instance->CR3, + USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos) & 0xFFU); + husart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / + (uint16_t)denominator[tx_fifo_threshold]; + husart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / + (uint16_t)denominator[rx_fifo_threshold]; + } +} +/** + * @} + */ + +#endif /* HAL_USART_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_wwdg.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_wwdg.c new file mode 100644 index 0000000000..4c25d94668 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_hal_wwdg.c @@ -0,0 +1,419 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_wwdg.c + * @author MCD Application Team + * @brief WWDG HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Window Watchdog (WWDG) peripheral: + * + Initialization and Configuration functions + * + IO operation functions + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### WWDG Specific features ##### + ============================================================================== + [..] + Once enabled the WWDG generates a system reset on expiry of a programmed + time period, unless the program refreshes the counter (T[6;0] downcounter) + before reaching 0x3F value (i.e. a reset is generated when the counter + value rolls down from 0x40 to 0x3F). + + (+) An MCU reset is also generated if the counter value is refreshed + before the counter has reached the refresh window value. This + implies that the counter must be refreshed in a limited window. + (+) Once enabled the WWDG cannot be disabled except by a system reset. + (+) If required by application, an Early Wakeup Interrupt can be triggered + in order to be warned before WWDG expiration. The Early Wakeup Interrupt + (EWI) can be used if specific safety operations or data logging must + be performed before the actual reset is generated. When the downcounter + reaches 0x40, interrupt occurs. This mechanism requires WWDG interrupt + line to be enabled in NVIC. Once enabled, EWI interrupt cannot be + disabled except by a system reset. + (+) WWDGRST flag in RCC CSR register can be used to inform when a WWDG + reset occurs. + (+) The WWDG counter input clock is derived from the APB clock divided + by a programmable prescaler. + (+) WWDG clock (Hz) = PCLK1 / (4096 * Prescaler) + (+) WWDG timeout (mS) = 1000 * (T[5;0] + 1) / WWDG clock (Hz) + where T[5;0] are the lowest 6 bits of Counter. + (+) WWDG Counter refresh is allowed between the following limits : + (++) min time (mS) = 1000 * (Counter - Window) / WWDG clock + (++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock + (+) Typical values: + (++) Counter min (T[5;0] = 0x00) at 56MHz (PCLK1) with zero prescaler: + max timeout before reset: approximately 73.14us + (++) Counter max (T[5;0] = 0x3F) at 56MHz (PCLK1) with prescaler + dividing by 128: + max timeout before reset: approximately 599.18ms + + ##### How to use this driver ##### + ============================================================================== + + *** Common driver usage *** + =========================== + + [..] + (+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE(). + (+) Configure the WWDG prescaler, refresh window value, counter value and early + interrupt status using HAL_WWDG_Init() function. This will automatically + enable WWDG and start its downcounter. Time reference can be taken from + function exit. Care must be taken to provide a counter value + greater than 0x40 to prevent generation of immediate reset. + (+) If the Early Wakeup Interrupt (EWI) feature is enabled, an interrupt is + generated when the counter reaches 0x40. When HAL_WWDG_IRQHandler is + triggered by the interrupt service routine, flag will be automatically + cleared and HAL_WWDG_WakeupCallback user callback will be executed. User + can add his own code by customization of callback HAL_WWDG_WakeupCallback. + (+) Then the application program must refresh the WWDG counter at regular + intervals during normal operation to prevent an MCU reset, using + HAL_WWDG_Refresh() function. This operation must occur only when + the counter is lower than the refresh window value already programmed. + + *** Callback registration *** + ============================= + + [..] + The compilation define USE_HAL_WWDG_REGISTER_CALLBACKS when set to 1 allows + the user to configure dynamically the driver callbacks. Use Functions + HAL_WWDG_RegisterCallback() to register a user callback. + + (+) Function HAL_WWDG_RegisterCallback() allows to register following + callbacks: + (++) EwiCallback : callback for Early WakeUp Interrupt. + (++) MspInitCallback : WWDG MspInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + (+) Use function HAL_WWDG_UnRegisterCallback() to reset a callback to + the default weak (surcharged) function. HAL_WWDG_UnRegisterCallback() + takes as parameters the HAL peripheral handle and the Callback ID. + This function allows to reset following callbacks: + (++) EwiCallback : callback for Early WakeUp Interrupt. + (++) MspInitCallback : WWDG MspInit. + + [..] + When calling HAL_WWDG_Init function, callbacks are reset to the + corresponding legacy weak (surcharged) functions: + HAL_WWDG_EarlyWakeupCallback() and HAL_WWDG_MspInit() only if they have + not been registered before. + + [..] + When compilation define USE_HAL_WWDG_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (surcharged) callbacks are used. + + *** WWDG HAL driver macros list *** + =================================== + [..] + Below the list of available macros in WWDG HAL driver. + (+) __HAL_WWDG_ENABLE: Enable the WWDG peripheral + (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status + (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags + (+) __HAL_WWDG_ENABLE_IT: Enable the WWDG early wakeup interrupt + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_hal.h" + +/** @addtogroup STM32WBAxx_HAL_Driver + * @{ + */ + +#ifdef HAL_WWDG_MODULE_ENABLED +/** @defgroup WWDG WWDG + * @brief WWDG HAL module driver. + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup WWDG_Exported_Functions WWDG Exported Functions + * @{ + */ + +/** @defgroup WWDG_Exported_Functions_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions. + * +@verbatim + ============================================================================== + ##### Initialization and Configuration functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and start the WWDG according to the specified parameters + in the WWDG_InitTypeDef of associated handle. + (+) Initialize the WWDG MSP. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the WWDG according to the specified. + * parameters in the WWDG_InitTypeDef of associated handle. + * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains + * the configuration information for the specified WWDG module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg) +{ + /* Check the WWDG handle allocation */ + if (hwwdg == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance)); + assert_param(IS_WWDG_PRESCALER(hwwdg->Init.Prescaler)); + assert_param(IS_WWDG_WINDOW(hwwdg->Init.Window)); + assert_param(IS_WWDG_COUNTER(hwwdg->Init.Counter)); + assert_param(IS_WWDG_EWI_MODE(hwwdg->Init.EWIMode)); + +#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1) + /* Reset Callback pointers */ + if (hwwdg->EwiCallback == NULL) + { + hwwdg->EwiCallback = HAL_WWDG_EarlyWakeupCallback; + } + + if (hwwdg->MspInitCallback == NULL) + { + hwwdg->MspInitCallback = HAL_WWDG_MspInit; + } + + /* Init the low level hardware */ + hwwdg->MspInitCallback(hwwdg); +#else + /* Init the low level hardware */ + HAL_WWDG_MspInit(hwwdg); +#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */ + + /* Set WWDG Counter */ + WRITE_REG(hwwdg->Instance->CR, (WWDG_CR_WDGA | hwwdg->Init.Counter)); + + /* Set WWDG Prescaler and Window */ + WRITE_REG(hwwdg->Instance->CFR, (hwwdg->Init.EWIMode | hwwdg->Init.Prescaler | hwwdg->Init.Window)); + + /* Return function status */ + return HAL_OK; +} + + +/** + * @brief Initialize the WWDG MSP. + * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains + * the configuration information for the specified WWDG module. + * @note When rewriting this function in user file, mechanism may be added + * to avoid multiple initialize when HAL_WWDG_Init function is called + * again to change parameters. + * @retval None + */ +__weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hwwdg); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_WWDG_MspInit could be implemented in the user file + */ +} + + +#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User WWDG Callback + * To be used instead of the weak (surcharged) predefined callback + * @param hwwdg WWDG handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_WWDG_EWI_CB_ID Early WakeUp Interrupt Callback ID + * @arg @ref HAL_WWDG_MSPINIT_CB_ID MspInit callback ID + * @param pCallback pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, + pWWDG_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + status = HAL_ERROR; + } + else + { + switch (CallbackID) + { + case HAL_WWDG_EWI_CB_ID: + hwwdg->EwiCallback = pCallback; + break; + + case HAL_WWDG_MSPINIT_CB_ID: + hwwdg->MspInitCallback = pCallback; + break; + + default: + status = HAL_ERROR; + break; + } + } + + return status; +} + + +/** + * @brief Unregister a WWDG Callback + * WWDG Callback is redirected to the weak (surcharged) predefined callback + * @param hwwdg WWDG handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_WWDG_EWI_CB_ID Early WakeUp Interrupt Callback ID + * @arg @ref HAL_WWDG_MSPINIT_CB_ID MspInit callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + switch (CallbackID) + { + case HAL_WWDG_EWI_CB_ID: + hwwdg->EwiCallback = HAL_WWDG_EarlyWakeupCallback; + break; + + case HAL_WWDG_MSPINIT_CB_ID: + hwwdg->MspInitCallback = HAL_WWDG_MspInit; + break; + + default: + status = HAL_ERROR; + break; + } + + return status; +} +#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup WWDG_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * +@verbatim + ============================================================================== + ##### IO operation functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Refresh the WWDG. + (+) Handle WWDG interrupt request and associated function callback. + +@endverbatim + * @{ + */ + +/** + * @brief Refresh the WWDG. + * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains + * the configuration information for the specified WWDG module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg) +{ + /* Write to WWDG CR the WWDG Counter value to refresh with */ + WRITE_REG(hwwdg->Instance->CR, (hwwdg->Init.Counter)); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Handle WWDG interrupt request. + * @note The Early Wakeup Interrupt (EWI) can be used if specific safety operations + * or data logging must be performed before the actual reset is generated. + * The EWI interrupt is enabled by calling HAL_WWDG_Init function with + * EWIMode set to WWDG_EWI_ENABLE. + * When the downcounter reaches the value 0x40, and EWI interrupt is + * generated and the corresponding Interrupt Service Routine (ISR) can + * be used to trigger specific actions (such as communications or data + * logging), before resetting the device. + * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains + * the configuration information for the specified WWDG module. + * @retval None + */ +void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg) +{ + /* Check if Early Wakeup Interrupt is enable */ + if (__HAL_WWDG_GET_IT_SOURCE(hwwdg, WWDG_IT_EWI) != RESET) + { + /* Check if WWDG Early Wakeup Interrupt occurred */ + if (__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET) + { + /* Clear the WWDG Early Wakeup flag */ + __HAL_WWDG_CLEAR_FLAG(hwwdg, WWDG_FLAG_EWIF); + +#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1) + /* Early Wakeup registered callback */ + hwwdg->EwiCallback(hwwdg); +#else + /* Early Wakeup callback */ + HAL_WWDG_EarlyWakeupCallback(hwwdg); +#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */ + } + } +} + + +/** + * @brief WWDG Early Wakeup callback. + * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains + * the configuration information for the specified WWDG module. + * @retval None + */ +__weak void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef *hwwdg) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hwwdg); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_WWDG_EarlyWakeupCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_WWDG_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_adc.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_adc.c new file mode 100644 index 0000000000..3ae9761b20 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_adc.c @@ -0,0 +1,697 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_ll_adc.c + * @author MCD Application Team + * @brief ADC LL module driver + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_ll_adc.h" +#include "stm32wbaxx_ll_bus.h" + +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +/** @addtogroup STM32WBAxx_LL_Driver + * @{ + */ + +#if defined (ADC4) + +/** @addtogroup ADC_LL ADC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup ADC_LL_Private_Constants + * @{ + */ + +/* Definitions of ADC hardware constraints delays */ +/* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */ +/* not timeout values: */ +/* Timeout values for ADC operations are dependent to device clock */ +/* configuration (system clock versus ADC clock), */ +/* and therefore must be defined in user application. */ +/* Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout */ +/* values definition. */ +/* Note: ADC timeout values are defined here in CPU cycles to be independent */ +/* of device clock setting. */ +/* In user application, ADC timeout values should be defined with */ +/* temporal values, in function of device clock settings. */ +/* Highest ratio CPU clock frequency vs ADC clock frequency: */ +/* - ADC clock from asynchronous clock with prescaler 512, */ +/* with highest ratio CPU clock frequency vs HSI clock frequency: */ +/* CPU clock frequency max 100MHz, HSI frequency 16MHz: ratio 7. */ +/* Unit: CPU cycles. */ +#define ADC_CLOCK_RATIO_VS_CPU_HIGHEST (512UL * 7UL) +#define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL) +#define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL) + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ + +/** @addtogroup ADC_LL_Private_Macros + * @{ + */ + +/* Check of parameters for configuration of ADC hierarchical scope: */ +/* common to several ADC instances. */ +#define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \ + (((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1) \ + || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV2) \ + || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV4) \ + || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV6) \ + || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV8) \ + || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV10) \ + || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV12) \ + || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV16) \ + || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV32) \ + || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV64) \ + || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV128) \ + || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV256) \ + ) + +#define IS_LL_ADC_CLOCK_FREQ_MODE(__CLOCK_FREQ_MODE__) \ + (((__CLOCK_FREQ_MODE__) == LL_ADC_CLOCK_FREQ_MODE_HIGH) \ + || ((__CLOCK_FREQ_MODE__) == LL_ADC_CLOCK_FREQ_MODE_LOW) \ + ) + +/* Check of parameters for configuration of ADC hierarchical scope: */ +/* ADC instance. */ +#define IS_LL_ADC_CLOCK(__CLOCK__) \ + (((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \ + || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \ + || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1) \ + || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC) \ + ) + +#define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \ + (((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \ + || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \ + || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \ + || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \ + ) + +#define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \ + (((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \ + || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \ + ) + +/* Check of parameters for configuration of ADC hierarchical scope: */ +/* ADC group regular */ +#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \ + (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH4 ) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM1_CH1) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE15) \ + ) + +#define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \ + (((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \ + || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \ + ) + +#define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \ + (((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \ + || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \ + || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \ + ) + +#define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__) \ + (((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED) \ + || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN) \ + ) + +#define IS_LL_ADC_REG_SEQ_MODE(__REG_SEQ_MODE__) \ + (((__REG_SEQ_MODE__) == LL_ADC_REG_SEQ_FIXED) \ + || ((__REG_SEQ_MODE__) == LL_ADC_REG_SEQ_CONFIGURABLE) \ + ) + +#define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \ + (((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \ + ) + +#define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \ + (((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \ + || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \ + ) + +/** + * @} + */ + + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup ADC_LL_Exported_Functions + * @{ + */ + +/** @addtogroup ADC_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize registers of all ADC instances belonging to + * the same ADC common instance to their default reset values. + * @note This function is performing a hard reset, using high level + * clock source RCC ADC reset. + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval An ErrorStatus enumeration value: + * - SUCCESS: ADC common registers are de-initialized + * - ERROR: not applicable + */ +ErrorStatus LL_ADC_CommonDeInit(const ADC_Common_TypeDef *ADCxy_COMMON) +{ + /* Check the parameters */ + assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); + + /* Prevent unused argument(s) compilation warning if no assert_param check */ + (void)(ADCxy_COMMON); + + /* Force reset of ADC clock (core clock) */ + SET_BIT(RCC->AHB4RSTR, RCC_AHB4ENR_ADC4EN); + + /* Release reset of ADC clock (core clock) */ + CLEAR_BIT(RCC->AHB4RSTR, RCC_AHB4ENR_ADC4EN); + + return SUCCESS; +} + +/** + * @brief Initialize some features of ADC common parameters + * (all ADC instances belonging to the same ADC common instance) + * and multimode (for devices with several ADC instances available). + * @note The setting of ADC common parameters is conditioned to + * ADC instances state: + * All ADC instances belonging to the same ADC common instance + * must be disabled. + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @param pADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: ADC common registers are initialized + * - ERROR: ADC common registers are not initialized + */ +ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, const LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct) +{ + ErrorStatus status = SUCCESS; + + /* Check the parameters */ + assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); + assert_param(IS_LL_ADC_COMMON_CLOCK(pADC_CommonInitStruct->CommonClock)); + + /* Note: Hardware constraint (refer to description of functions */ + /* "LL_ADC_SetCommonXXX()": */ + /* On this STM32 series, setting of these features is conditioned to */ + /* ADC state: */ + /* All ADC instances of the ADC common group must be disabled. */ + if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0UL) + { + /* Configuration of ADC hierarchical scope: */ + /* - common to several ADC */ + /* (all ADC instances belonging to the same ADC common instance) */ + /* - Set ADC clock (conversion clock) */ + LL_ADC_SetCommonClock(ADCxy_COMMON, pADC_CommonInitStruct->CommonClock); + } + else + { + /* Initialization error: One or several ADC instances belonging to */ + /* the same ADC common instance are not disabled. */ + status = ERROR; + } + + return status; +} + +/** + * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value. + * @param pADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ +void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct) +{ + /* Set pADC_CommonInitStruct fields to default values */ + /* Set fields of ADC common */ + /* (all ADC instances belonging to the same ADC common instance) */ + pADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_ASYNC_DIV2; + +} + +/** + * @brief De-initialize registers of the selected ADC instance + * to their default reset values. + * @note To reset all ADC instances quickly (perform a hard reset), + * use function @ref LL_ADC_CommonDeInit(). + * @note If this functions returns error status, it means that ADC instance + * is in an unknown state. + * In this case, perform a hard reset using high level + * clock source RCC ADC reset. + * Refer to function @ref LL_ADC_CommonDeInit(). + * @param ADCx ADC instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: ADC registers are de-initialized + * - ERROR: ADC registers are not de-initialized + */ +ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) +{ + ErrorStatus status = SUCCESS; + + __IO uint32_t timeout_cpu_cycles = 0UL; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(ADCx)); + + /* Disable ADC instance if not already disabled. */ + if (LL_ADC_IsEnabled(ADCx) == 1UL) + { + /* Stop potential ADC conversion on going on ADC group regular. */ + LL_ADC_REG_StopConversion(ADCx); + + /* Wait for ADC conversions are effectively stopped */ + timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES; + while (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 1UL) + { + timeout_cpu_cycles--; + if (timeout_cpu_cycles == 0UL) + { + /* Time-out error */ + status = ERROR; + break; + } + } + + /* Disable the ADC instance */ + LL_ADC_Disable(ADCx); + + /* Wait for ADC instance is effectively disabled */ + timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES; + while (LL_ADC_IsDisableOngoing(ADCx) == 1UL) + { + timeout_cpu_cycles--; + if (timeout_cpu_cycles == 0UL) + { + /* Time-out error */ + status = ERROR; + break; + } + } + } + + /* Check whether ADC state is compliant with expected state */ + if (READ_BIT(ADCx->CR, + (ADC_CR_ADSTP | ADC_CR_ADSTART + | ADC_CR_ADDIS | ADC_CR_ADEN) + ) + == 0UL) + { + /* ========== Reset ADC registers ========== */ + /* Reset register IER */ + CLEAR_BIT(ADCx->IER, + (LL_ADC_IT_ADRDY + | LL_ADC_IT_EOC + | LL_ADC_IT_EOS + | LL_ADC_IT_OVR + | LL_ADC_IT_EOSMP + | LL_ADC_IT_AWD1 + | LL_ADC_IT_AWD2 + | LL_ADC_IT_AWD3 + | LL_ADC_IT_EOCAL + ) + ); + + /* Reset register ISR */ + SET_BIT(ADCx->ISR, + (LL_ADC_FLAG_ADRDY + | LL_ADC_FLAG_EOC + | LL_ADC_FLAG_EOS + | LL_ADC_FLAG_OVR + | LL_ADC_FLAG_EOSMP + | LL_ADC_FLAG_AWD1 + | LL_ADC_FLAG_AWD2 + | LL_ADC_FLAG_AWD3 + | LL_ADC_FLAG_EOCAL + ) + ); + + /* Reset register CR */ + /* Bits ADC_CR_ADCAL, ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode */ + /* "read-set": no direct reset applicable. */ + CLEAR_BIT(ADCx->CR, ADC_CR_ADVREGEN); + + /* Reset register CFGR1 */ + CLEAR_BIT(ADCx->CFGR1, + (ADC_CFGR1_AWD1CH | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL | ADC_CFGR1_DISCEN + | ADC_CFGR1_CHSELRMOD | ADC_CFGR1_WAIT | ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD + | ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL | ADC_CFGR1_ALIGN | ADC_CFGR1_RES + | ADC_CFGR1_SCANDIR | ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN) + ); + + /* Reset register CFGR2 */ + CLEAR_BIT(ADCx->CFGR2, + (ADC_CFGR2_TOVS | ADC_CFGR2_OVSS | ADC_CFGR2_OVSR + | ADC_CFGR2_OVSE) + ); + + /* Reset register SMPR */ + CLEAR_BIT(ADCx->SMPR, ADC_SMPR_SMP1 | ADC_SMPR_SMP2 | ADC_SMPR_SMPSEL); + + /* Reset register AWD1TR */ + MODIFY_REG(ADCx->AWD1TR, ADC_AWD1TR_LT1 | ADC_AWD1TR_HT1, ADC_AWD1TR_HT1); + + /* Reset register AWD2TR */ + MODIFY_REG(ADCx->AWD2TR, ADC_AWD2TR_LT2 | ADC_AWD2TR_HT2, ADC_AWD2TR_HT2); + + /* Reset register AWD3TR */ + MODIFY_REG(ADCx->AWD3TR, ADC_AWD3TR_LT3 | ADC_AWD3TR_HT3, ADC_AWD3TR_HT3); + + /* Reset register CHSELR */ + CLEAR_BIT(ADCx->CHSELR, + (ADC_CHSELR_CHSEL13 | ADC_CHSELR_CHSEL12 + | ADC_CHSELR_CHSEL11 | ADC_CHSELR_CHSEL10 | ADC_CHSELR_CHSEL9 | ADC_CHSELR_CHSEL8 + | ADC_CHSELR_CHSEL7 | ADC_CHSELR_CHSEL6 | ADC_CHSELR_CHSEL5 | ADC_CHSELR_CHSEL4 + | ADC_CHSELR_CHSEL3 | ADC_CHSELR_CHSEL2 | ADC_CHSELR_CHSEL1 | ADC_CHSELR_CHSEL0) + ); + + /* Reset register DR */ + /* bits in access mode read only, no direct reset applicable */ + + /* Reset register CALFACT */ + CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT); + + } + else + { + /* ADC instance is in an unknown state */ + /* Need to performing a hard reset of ADC instance, using high level */ + /* clock source RCC ADC reset. */ + /* Caution: On this STM32 series, if several ADC instances are available */ + /* on the selected device, RCC ADC reset will reset */ + /* all ADC instances belonging to the common ADC instance. */ + status = ERROR; + } + + return status; +} + +/** + * @brief Initialize some features of ADC instance. + * @note These parameters have an impact on ADC scope: ADC instance. + * Refer to corresponding unitary functions into + * @ref ADC_LL_EF_Configuration_ADC_Instance . + * @note The setting of these parameters by function @ref LL_ADC_Init() + * is conditioned to ADC state: + * ADC instance must be disabled. + * This condition is applied to all ADC features, for efficiency + * and compatibility over all STM32 series. However, the different + * features can be set under different ADC state conditions + * (setting possible with ADC enabled without conversion on going, + * ADC enabled with conversion on going, ...) + * Each feature can be updated afterwards with a unitary function + * and potentially with ADC in a different state than disabled, + * refer to description of each function for setting + * conditioned to ADC state. + * @note After using this function, some other features must be configured + * using LL unitary functions. + * The minimum configuration remaining to be done is: + * - Set ADC group regular sequencer: + * Depending on the sequencer mode (refer to + * function @ref LL_ADC_REG_SetSequencerConfigurable() ): + * - map channel on the selected sequencer rank. + * Refer to function @ref LL_ADC_REG_SetSequencerRanks(); + * - map channel on rank corresponding to channel number. + * Refer to function @ref LL_ADC_REG_SetSequencerChannels(); + * - Set ADC channel sampling time + * Refer to function LL_ADC_SetSamplingTimeCommonChannels(); + * Refer to function LL_ADC_SetChannelSamplingTime(); + * @param ADCx ADC instance + * @param pADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: ADC registers are initialized + * - ERROR: ADC registers are not initialized + */ +ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, const LL_ADC_InitTypeDef *pADC_InitStruct) +{ + ErrorStatus status = SUCCESS; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(ADCx)); + + assert_param(IS_LL_ADC_RESOLUTION(pADC_InitStruct->Resolution)); + assert_param(IS_LL_ADC_DATA_ALIGN(pADC_InitStruct->DataAlignment)); + + /* Note: Hardware constraint (refer to description of this function): */ + /* ADC instance must be disabled. */ + if (LL_ADC_IsEnabled(ADCx) == 0UL) + { + /* Configuration of ADC hierarchical scope: */ + /* - ADC instance */ + /* - Set ADC data resolution */ + /* - Set ADC conversion data alignment */ + /* - Set ADC low power mode */ + MODIFY_REG(ADCx->CFGR1, + ADC_CFGR1_RES + | ADC_CFGR1_ALIGN + , + pADC_InitStruct->Resolution + | pADC_InitStruct->DataAlignment + ); + } + else + { + /* Initialization error: ADC instance is not disabled. */ + status = ERROR; + } + + return status; +} + +/** + * @brief Set each @ref LL_ADC_InitTypeDef field to default value. + * @param pADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ +void LL_ADC_StructInit(LL_ADC_InitTypeDef *pADC_InitStruct) +{ + /* Set pADC_InitStruct fields to default values */ + /* Set fields of ADC instance */ + pADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B; + pADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT; + +} + +/** + * @brief Initialize some features of ADC group regular. + * @note These parameters have an impact on ADC scope: ADC group regular. + * Refer to corresponding unitary functions into + * @ref ADC_LL_EF_Configuration_ADC_Group_Regular + * (functions with prefix "REG"). + * @note The setting of these parameters by function @ref LL_ADC_Init() + * is conditioned to ADC state: + * ADC instance must be disabled. + * This condition is applied to all ADC features, for efficiency + * and compatibility over all STM32 series. However, the different + * features can be set under different ADC state conditions + * (setting possible with ADC enabled without conversion on going, + * ADC enabled with conversion on going, ...) + * Each feature can be updated afterwards with a unitary function + * and potentially with ADC in a different state than disabled, + * refer to description of each function for setting + * conditioned to ADC state. + * @note Before using this function, ADC group regular sequencer + * must be configured: refer to function + * @ref LL_ADC_REG_SetSequencerConfigurable(). + * @note After using this function, other features must be configured + * using LL unitary functions. + * The minimum configuration remaining to be done is: + * - Set ADC group regular sequencer: + * Depending on the sequencer mode (refer to + * function @ref LL_ADC_REG_SetSequencerConfigurable() ): + * - map channel on the selected sequencer rank. + * Refer to function @ref LL_ADC_REG_SetSequencerRanks(); + * - map channel on rank corresponding to channel number. + * Refer to function @ref LL_ADC_REG_SetSequencerChannels(); + * - Set ADC channel sampling time + * Refer to function LL_ADC_SetSamplingTimeCommonChannels(); + * Refer to function LL_ADC_SetChannelSamplingTime(); + * @param ADCx ADC instance + * @param pADC_RegInitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: ADC registers are initialized + * - ERROR: ADC registers are not initialized + */ +ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, const LL_ADC_REG_InitTypeDef *pADC_RegInitStruct) +{ + ErrorStatus status = SUCCESS; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(ADCx)); + assert_param(IS_LL_ADC_REG_TRIG_SOURCE(pADC_RegInitStruct->TriggerSource)); + assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(pADC_RegInitStruct->ContinuousMode)); + assert_param(IS_LL_ADC_REG_DMA_TRANSFER(pADC_RegInitStruct->DMATransfer)); + assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(pADC_RegInitStruct->Overrun)); + + if (LL_ADC_REG_GetSequencerConfigurable(ADCx) != LL_ADC_REG_SEQ_FIXED) + { + assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(pADC_RegInitStruct->SequencerLength)); + } + + if ((LL_ADC_REG_GetSequencerConfigurable(ADCx) == LL_ADC_REG_SEQ_FIXED) + || (pADC_RegInitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) + ) + { + assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(pADC_RegInitStruct->SequencerDiscont)); + + /* ADC group regular continuous mode and discontinuous mode */ + /* can not be enabled simultenaeously */ + assert_param((pADC_RegInitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE) + || (pADC_RegInitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE)); + } + + /* Note: Hardware constraint (refer to description of this function): */ + /* ADC instance must be disabled. */ + if (LL_ADC_IsEnabled(ADCx) == 0UL) + { + /* Configuration of ADC hierarchical scope: */ + /* - ADC group regular */ + /* - Set ADC group regular trigger source */ + /* - Set ADC group regular sequencer length */ + /* - Set ADC group regular sequencer discontinuous mode */ + /* - Set ADC group regular continuous mode */ + /* - Set ADC group regular conversion data transfer: no transfer or */ + /* transfer by DMA, and DMA requests mode */ + /* - Set ADC group regular overrun behavior */ + /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */ + /* setting of trigger source to SW start. */ + if ((LL_ADC_REG_GetSequencerConfigurable(ADCx) == LL_ADC_REG_SEQ_FIXED) + || (pADC_RegInitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) + ) + { + /* Case of sequencer mode fixed + or sequencer length >= 2 ranks with sequencer mode fully configurable: + discontinuous mode configured */ + MODIFY_REG(ADCx->CFGR1, + ADC_CFGR1_EXTSEL + | ADC_CFGR1_EXTEN + | ADC_CFGR1_DISCEN + | ADC_CFGR1_CONT + | ADC_CFGR1_DMAEN + | ADC_CFGR1_DMACFG + | ADC_CFGR1_OVRMOD + , + pADC_RegInitStruct->TriggerSource + | pADC_RegInitStruct->SequencerDiscont + | pADC_RegInitStruct->ContinuousMode + | pADC_RegInitStruct->DMATransfer + | pADC_RegInitStruct->Overrun + ); + } + else + { + /* Case of sequencer mode fully configurable + and sequencer length 1 rank (sequencer disabled): + discontinuous mode discarded (fixed to disable) */ + MODIFY_REG(ADCx->CFGR1, + ADC_CFGR1_EXTSEL + | ADC_CFGR1_EXTEN + | ADC_CFGR1_DISCEN + | ADC_CFGR1_CONT + | ADC_CFGR1_DMAEN + | ADC_CFGR1_DMACFG + | ADC_CFGR1_OVRMOD + , + pADC_RegInitStruct->TriggerSource + | LL_ADC_REG_SEQ_DISCONT_DISABLE + | pADC_RegInitStruct->ContinuousMode + | pADC_RegInitStruct->DMATransfer + | pADC_RegInitStruct->Overrun + ); + } + + /* Set ADC group regular sequencer length */ + if (LL_ADC_REG_GetSequencerConfigurable(ADCx) != LL_ADC_REG_SEQ_FIXED) + { + LL_ADC_REG_SetSequencerLength(ADCx, pADC_RegInitStruct->SequencerLength); + } + } + else + { + /* Initialization error: ADC instance is not disabled. */ + status = ERROR; + } + return status; +} + +/** + * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value. + * @param pADC_RegInitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ +void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *pADC_RegInitStruct) +{ + /* Set pADC_RegInitStruct fields to default values */ + /* Set fields of ADC group regular */ + /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */ + /* setting of trigger source to SW start. */ + pADC_RegInitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE; + pADC_RegInitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE; + pADC_RegInitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE; + pADC_RegInitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE; + pADC_RegInitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE; + pADC_RegInitStruct->Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* ADC4 */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_comp.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_comp.c new file mode 100644 index 0000000000..45afaeb9bf --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_comp.c @@ -0,0 +1,249 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_ll_comp.c + * @author MCD Application Team + * @brief COMP LL module driver + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_ll_comp.h" + +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +/** @addtogroup STM32WBAxx_LL_Driver + * @{ + */ + +#if defined (COMP1) || defined (COMP2) + +/** @addtogroup COMP_LL COMP + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ + +/** @addtogroup COMP_LL_Private_Macros + * @{ + */ + +/* Check of parameters for configuration of COMP hierarchical scope: */ +/* COMP instance. */ + +#define IS_LL_COMP_POWER_MODE(__POWER_MODE__) \ + (((__POWER_MODE__) == LL_COMP_POWERMODE_HIGHSPEED) \ + || ((__POWER_MODE__) == LL_COMP_POWERMODE_MEDIUMSPEED) \ + ) + +/* Note: On this STM32 series, comparator input plus parameters are */ +/* the same on all COMP instances. */ +/* However, comparator instance kept as macro parameter for */ +/* compatibility with other STM32 series. */ +#define IS_LL_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) \ + (((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO1) \ + ) + +/* Note: On this STM32 series, comparator input minus parameters are */ +/* the same on all COMP instances. */ +/* However, comparator instance kept as macro parameter for */ +/* compatibility with other STM32 series. */ +#define IS_LL_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) \ + (((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_4VREFINT) \ + || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_1_2VREFINT) \ + || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_3_4VREFINT) \ + || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_VREFINT) \ + || ((__INPUT_MINUS__) == LL_COMP_INPUT_MINUS_IO1) \ + ) + +#define IS_LL_COMP_INPUT_HYSTERESIS(__INPUT_HYSTERESIS__) \ + (((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_NONE) \ + || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_LOW) \ + || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_MEDIUM) \ + || ((__INPUT_HYSTERESIS__) == LL_COMP_HYSTERESIS_HIGH) \ + ) + +#define IS_LL_COMP_OUTPUT_POLARITY(__POLARITY__) \ + (((__POLARITY__) == LL_COMP_OUTPUTPOL_NONINVERTED) \ + || ((__POLARITY__) == LL_COMP_OUTPUTPOL_INVERTED) \ + ) + +#define IS_LL_COMP_OUTPUT_BLANKING_SOURCE(__COMP_INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \ + ((((__COMP_INSTANCE__) == COMP1) && \ + (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1))) \ + || \ + (((__COMP_INSTANCE__) == COMP2) && \ + (((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_NONE) || \ + ((__OUTPUT_BLANKING_SOURCE__) == LL_COMP_BLANKINGSRC_TIM3_OC4_COMP2))) \ + ) +/** + * @} + */ + + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup COMP_LL_Exported_Functions + * @{ + */ + +/** @addtogroup COMP_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize registers of the selected COMP instance + * to their default reset values. + * @note If comparator is locked, de-initialization by software is + * not possible. + * The only way to unlock the comparator is a device hardware reset. + * @param COMPx COMP instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: COMP registers are de-initialized + * - ERROR: COMP registers are not de-initialized + */ +ErrorStatus LL_COMP_DeInit(COMP_TypeDef *COMPx) +{ + ErrorStatus status = SUCCESS; + + /* Check the parameters */ + assert_param(IS_COMP_ALL_INSTANCE(COMPx)); + + /* Note: Hardware constraint (refer to description of this function): */ + /* COMP instance must not be locked. */ + if (LL_COMP_IsLocked(COMPx) == 0UL) + { + LL_COMP_WriteReg(COMPx, CSR, 0x00000000UL); + + } + else + { + /* Comparator instance is locked: de-initialization by software is */ + /* not possible. */ + /* The only way to unlock the comparator is a device hardware reset. */ + status = ERROR; + } + + return status; +} + +/** + * @brief Initialize some features of COMP instance. + * @note This function configures features of the selected COMP instance. + * Some features are also available at scope COMP common instance + * (common to several COMP instances). + * Refer to functions having argument "COMPxy_COMMON" as parameter. + * @param COMPx COMP instance + * @param COMP_InitStruct Pointer to a @ref LL_COMP_InitTypeDef structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: COMP registers are initialized + * - ERROR: COMP registers are not initialized + */ +ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, const LL_COMP_InitTypeDef *COMP_InitStruct) +{ + ErrorStatus status = SUCCESS; + + /* Check the parameters */ + assert_param(IS_COMP_ALL_INSTANCE(COMPx)); + assert_param(IS_LL_COMP_POWER_MODE(COMP_InitStruct->PowerMode)); + assert_param(IS_LL_COMP_INPUT_PLUS(COMPx, COMP_InitStruct->InputPlus)); + assert_param(IS_LL_COMP_INPUT_MINUS(COMPx, COMP_InitStruct->InputMinus)); + assert_param(IS_LL_COMP_INPUT_HYSTERESIS(COMP_InitStruct->InputHysteresis)); + assert_param(IS_LL_COMP_OUTPUT_POLARITY(COMP_InitStruct->OutputPolarity)); + assert_param(IS_LL_COMP_OUTPUT_BLANKING_SOURCE(COMPx, COMP_InitStruct->OutputBlankingSource)); + + /* Note: Hardware constraint (refer to description of this function) */ + /* COMP instance must not be locked. */ + if (LL_COMP_IsLocked(COMPx) == 0UL) + { + /* Configuration of comparator instance : */ + /* - PowerMode */ + /* - InputPlus */ + /* - InputMinus */ + /* - InputHysteresis */ + /* - OutputPolarity */ + /* - OutputBlankingSource */ + MODIFY_REG(COMPx->CSR, + COMP_CSR_PWRMODE + | COMP_CSR_INPSEL + | COMP_CSR_INMSEL + | COMP_CSR_HYST + | COMP_CSR_POLARITY + | COMP_CSR_BLANKSEL + , + COMP_InitStruct->PowerMode + | COMP_InitStruct->InputPlus + | COMP_InitStruct->InputMinus + | COMP_InitStruct->InputHysteresis + | COMP_InitStruct->OutputPolarity + | COMP_InitStruct->OutputBlankingSource + ); + + } + else + { + /* Initialization error: COMP instance is locked. */ + status = ERROR; + } + + return status; +} + +/** + * @brief Set each @ref LL_COMP_InitTypeDef field to default value. + * @param COMP_InitStruct Pointer to a @ref LL_COMP_InitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ +void LL_COMP_StructInit(LL_COMP_InitTypeDef *COMP_InitStruct) +{ + /* Set COMP_InitStruct fields to default values */ + COMP_InitStruct->PowerMode = LL_COMP_POWERMODE_MEDIUMSPEED; + COMP_InitStruct->InputPlus = LL_COMP_INPUT_PLUS_IO1; + COMP_InitStruct->InputMinus = LL_COMP_INPUT_MINUS_VREFINT; + COMP_InitStruct->InputHysteresis = LL_COMP_HYSTERESIS_NONE; + COMP_InitStruct->OutputPolarity = LL_COMP_OUTPUTPOL_NONINVERTED; + COMP_InitStruct->OutputBlankingSource = LL_COMP_BLANKINGSRC_NONE; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* COMP1 || COMP2 */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_crc.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_crc.c new file mode 100644 index 0000000000..e596c4943e --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_crc.c @@ -0,0 +1,103 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_ll_crc.c + * @author MCD Application Team + * @brief CRC LL module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_ll_crc.h" +#include "stm32wbaxx_ll_bus.h" + +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +/** @addtogroup STM32WBAxx_LL_Driver + * @{ + */ + +#if defined (CRC) + +/** @addtogroup CRC_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup CRC_LL_Exported_Functions + * @{ + */ + +/** @addtogroup CRC_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize CRC registers (Registers restored to their default values). + * @param CRCx CRC Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: CRC registers are de-initialized + * - ERROR: CRC registers are not de-initialized + */ +ErrorStatus LL_CRC_DeInit(const CRC_TypeDef *CRCx) +{ + ErrorStatus status = SUCCESS; + + /* Check the parameters */ + assert_param(IS_CRC_ALL_INSTANCE(CRCx)); + + if (CRCx == CRC) + { + /* Force CRC reset */ + LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_CRC); + + /* Release CRC reset */ + LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_CRC); + } + else + { + status = ERROR; + } + + return (status); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (CRC) */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_dma.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_dma.c new file mode 100644 index 0000000000..1f13c6cdcd --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_dma.c @@ -0,0 +1,909 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_ll_dma.c + * @author MCD Application Team + * @brief DMA LL module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### LL DMA driver acronyms ##### + ============================================================================== + [..] Acronyms table : + ========================================= + || Acronym || || + ========================================= + || SRC || Source || + || DEST || Destination || + || ADDR || Address || + || ADDRS || Addresses || + || INC || Increment / Incremented || + || DEC || Decrement / Decremented || + || BLK || Block || + || RPT || Repeat / Repeated || + || TRIG || Trigger || + ========================================= + @endverbatim + ****************************************************************************** + */ + +#if defined (USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_ll_dma.h" +#include "stm32wbaxx_ll_bus.h" +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +/** @addtogroup STM32WBAxx_LL_Driver + * @{ + */ + +#if defined (GPDMA1) + +/** @addtogroup DMA_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ + +/** @addtogroup DMA_LL_Private_Macros + * @{ + */ +#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, Channel) (((INSTANCE) == GPDMA1) && \ + (((Channel) == LL_DMA_CHANNEL_0) || \ + ((Channel) == LL_DMA_CHANNEL_1) || \ + ((Channel) == LL_DMA_CHANNEL_2) || \ + ((Channel) == LL_DMA_CHANNEL_3) || \ + ((Channel) == LL_DMA_CHANNEL_4) || \ + ((Channel) == LL_DMA_CHANNEL_5) || \ + ((Channel) == LL_DMA_CHANNEL_6) || \ + ((Channel) == LL_DMA_CHANNEL_7) || \ + ((Channel) == LL_DMA_CHANNEL_ALL))) + +#define IS_LL_GPDMA_CHANNEL_INSTANCE(INSTANCE, Channel) (((INSTANCE) == GPDMA1) && \ + (((Channel) == LL_DMA_CHANNEL_0) || \ + ((Channel) == LL_DMA_CHANNEL_1) || \ + ((Channel) == LL_DMA_CHANNEL_2) || \ + ((Channel) == LL_DMA_CHANNEL_3) || \ + ((Channel) == LL_DMA_CHANNEL_4) || \ + ((Channel) == LL_DMA_CHANNEL_5) || \ + ((Channel) == LL_DMA_CHANNEL_6) || \ + ((Channel) == LL_DMA_CHANNEL_7))) + +#define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY) || \ + ((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \ + ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)) + +#define IS_LL_DMA_DATA_ALIGNMENT(__VALUE__) (((__VALUE__) == LL_DMA_DATA_ALIGN_ZEROPADD) || \ + ((__VALUE__) == LL_DMA_DATA_ALIGN_SIGNEXTPADD) || \ + ((__VALUE__) == LL_DMA_DATA_PACK_UNPACK)) + +#define IS_LL_DMA_BURST_LENGTH(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= 64U)) + +#define IS_LL_DMA_SRC_DATA_WIDTH(__VALUE__) (((__VALUE__) == LL_DMA_SRC_DATAWIDTH_BYTE) || \ + ((__VALUE__) == LL_DMA_SRC_DATAWIDTH_HALFWORD) || \ + ((__VALUE__) == LL_DMA_SRC_DATAWIDTH_WORD)) + +#define IS_LL_DMA_DEST_DATA_WIDTH(__VALUE__) (((__VALUE__) == LL_DMA_DEST_DATAWIDTH_BYTE) || \ + ((__VALUE__) == LL_DMA_DEST_DATAWIDTH_HALFWORD) || \ + ((__VALUE__) == LL_DMA_DEST_DATAWIDTH_WORD)) + +#define IS_LL_DMA_SRC_INCREMENT_MODE(__VALUE__) (((__VALUE__) == LL_DMA_SRC_FIXED) || \ + ((__VALUE__) == LL_DMA_SRC_INCREMENT)) + +#define IS_LL_DMA_DEST_INCREMENT_MODE(__VALUE__) (((__VALUE__) == LL_DMA_DEST_FIXED) || \ + ((__VALUE__) == LL_DMA_DEST_INCREMENT)) + +#define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_LOW_PRIORITY_LOW_WEIGHT) || \ + ((__VALUE__) == LL_DMA_LOW_PRIORITY_MID_WEIGHT) || \ + ((__VALUE__) == LL_DMA_LOW_PRIORITY_HIGH_WEIGHT) || \ + ((__VALUE__) == LL_DMA_HIGH_PRIORITY)) + +#define IS_LL_DMA_BLK_DATALENGTH(__VALUE__) ((__VALUE__) <= 0xFFFFU) + +#define IS_LL_DMA_BLK_REPEATCOUNT(__VALUE__) ((__VALUE__) <= 0x0EFFU) + +#define IS_LL_DMA_TRIGGER_MODE(__VALUE__) (((__VALUE__) == LL_DMA_TRIGM_BLK_TRANSFER) || \ + ((__VALUE__) == LL_DMA_TRIGM_RPT_BLK_TRANSFER) || \ + ((__VALUE__) == LL_DMA_TRIGM_LLI_LINK_TRANSFER) || \ + ((__VALUE__) == LL_DMA_TRIGM_SINGLBURST_TRANSFER )) + +#define IS_LL_DMA_TRIGGER_POLARITY(__VALUE__) (((__VALUE__) == LL_DMA_TRIG_POLARITY_MASKED) || \ + ((__VALUE__) == LL_DMA_TRIG_POLARITY_RISING) || \ + ((__VALUE__) == LL_DMA_TRIG_POLARITY_FALLING)) + +#define IS_LL_DMA_BLKHW_REQUEST(__VALUE__) (((__VALUE__) == LL_DMA_HWREQUEST_SINGLEBURST) || \ + ((__VALUE__) == LL_DMA_HWREQUEST_BLK)) + +#if defined (TIM3) +#define IS_LL_DMA_TRIGGER_SELECTION(__VALUE__) ((__VALUE__) <= LL_GPDMA1_TRIGGER_TIM3_TRGO) +#else +#define IS_LL_DMA_TRIGGER_SELECTION(__VALUE__) ((__VALUE__) <= LL_GPDMA1_TRIGGER_ADC4_AWD1) +#endif /* TIM3 */ + +#if defined (LPTIM2) +#define IS_LL_DMA_REQUEST_SELECTION(__VALUE__) ((__VALUE__) <= LL_GPDMA1_REQUEST_LPTIM2_UE) +#else +#define IS_LL_DMA_REQUEST_SELECTION(__VALUE__) ((__VALUE__) <= LL_GPDMA1_REQUEST_LPTIM1_UE) +#endif /* LPTIM2 */ + +#define IS_LL_DMA_TRANSFER_EVENT_MODE(__VALUE__) (((__VALUE__) == LL_DMA_TCEM_BLK_TRANSFER) || \ + ((__VALUE__) == LL_DMA_TCEM_RPT_BLK_TRANSFER) || \ + ((__VALUE__) == LL_DMA_TCEM_EACH_LLITEM_TRANSFER) || \ + ((__VALUE__) == LL_DMA_TCEM_LAST_LLITEM_TRANSFER)) + +#define IS_LL_DMA_DEST_HALFWORD_EXCHANGE(__VALUE__) (((__VALUE__) == LL_DMA_DEST_HALFWORD_PRESERVE) || \ + ((__VALUE__) == LL_DMA_DEST_HALFWORD_EXCHANGE)) + +#define IS_LL_DMA_DEST_BYTE_EXCHANGE(__VALUE__) (((__VALUE__) == LL_DMA_DEST_BYTE_PRESERVE) || \ + ((__VALUE__) == LL_DMA_DEST_BYTE_EXCHANGE)) + +#define IS_LL_DMA_SRC_BYTE_EXCHANGE(__VALUE__) (((__VALUE__) == LL_DMA_SRC_BYTE_PRESERVE) || \ + ((__VALUE__) == LL_DMA_SRC_BYTE_EXCHANGE)) + +#define IS_LL_DMA_LINK_ALLOCATED_PORT(__VALUE__) (((__VALUE__) == LL_DMA_LINK_ALLOCATED_PORT0) || \ + ((__VALUE__) == LL_DMA_LINK_ALLOCATED_PORT1)) + +#define IS_LL_DMA_SRC_ALLOCATED_PORT(__VALUE__) (((__VALUE__) == LL_DMA_SRC_ALLOCATED_PORT0) || \ + ((__VALUE__) == LL_DMA_SRC_ALLOCATED_PORT1)) + +#define IS_LL_DMA_DEST_ALLOCATED_PORT(__VALUE__) (((__VALUE__) == LL_DMA_DEST_ALLOCATED_PORT0) || \ + ((__VALUE__) == LL_DMA_DEST_ALLOCATED_PORT1)) + +#define IS_LL_DMA_LINK_STEP_MODE(__VALUE__) (((__VALUE__) == LL_DMA_LSM_FULL_EXECUTION) || \ + ((__VALUE__) == LL_DMA_LSM_1LINK_EXECUTION)) + +#define IS_LL_DMA_BURST_SRC_ADDR_UPDATE(__VALUE__) (((__VALUE__) == LL_DMA_BURST_SRC_ADDR_INCREMENT) || \ + ((__VALUE__) == LL_DMA_BURST_SRC_ADDR_DECREMENT)) + +#define IS_LL_DMA_BURST_DEST_ADDR_UPDATE(__VALUE__) (((__VALUE__) == LL_DMA_BURST_DEST_ADDR_INCREMENT) || \ + ((__VALUE__) == LL_DMA_BURST_DEST_ADDR_DECREMENT)) + +#define IS_LL_DMA_BURST_ADDR_UPDATE_VALUE(__VALUE__) ((__VALUE__) <= 0x1FFFU) + +#define IS_LL_DMA_BLKRPT_SRC_ADDR_UPDATE(__VALUE__) (((__VALUE__) == LL_DMA_BLKRPT_SRC_ADDR_INCREMENT) || \ + ((__VALUE__) == LL_DMA_BLKRPT_SRC_ADDR_DECREMENT)) + +#define IS_LL_DMA_BLKRPT_DEST_ADDR_UPDATE(__VALUE__) (((__VALUE__) == LL_DMA_BLKRPT_DEST_ADDR_INCREMENT) || \ + ((__VALUE__) == LL_DMA_BLKRPT_DEST_ADDR_DECREMENT)) + +#define IS_LL_DMA_BLKRPT_ADDR_UPDATE_VALUE(__VALUE__) ((__VALUE__) <= 0xFFFFU) + +#define IS_LL_DMA_LINK_BASEADDR(__VALUE__) (((__VALUE__) & 0xFFFFU) == 0U) + +#define IS_LL_DMA_LINK_ADDR_OFFSET(__VALUE__) (((__VALUE__) & 0x03U) == 0U) + +#define IS_LL_DMA_LINK_UPDATE_REGISTERS(__VALUE__) ((((__VALUE__) & 0x01FE0000U) == 0U) && ((__VALUE__) != 0U)) + +#define IS_LL_DMA_LINK_NODETYPE(__VALUE__) ((__VALUE__) == LL_DMA_GPDMA_LINEAR_NODE) + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define IS_LL_DMA_CHANNEL_SRC_SEC(__VALUE__) (((__VALUE__) == LL_DMA_CHANNEL_SRC_NSEC) || \ + ((__VALUE__) == LL_DMA_CHANNEL_SRC_SEC)) + +#define IS_LL_DMA_CHANNEL_DEST_SEC(__VALUE__) (((__VALUE__) == LL_DMA_CHANNEL_DEST_NSEC) || \ + ((__VALUE__) == LL_DMA_CHANNEL_DEST_SEC)) + +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup DMA_LL_Exported_Functions + * @{ + */ + +/** @addtogroup DMA_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize the DMA registers to their default reset values. + * @note This API is used for all available DMA channels. + * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use + * helper macros : + * @arg @ref LL_DMA_GET_INSTANCE + * @arg @ref LL_DMA_GET_CHANNEL + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval An ErrorStatus enumeration value: + * - SUCCESS : DMA registers are de-initialized. + * - ERROR : DMA registers are not de-initialized. + */ +uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel) +{ + DMA_Channel_TypeDef *tmp; + ErrorStatus status = SUCCESS; + + /* Check the DMA Instance DMAx and Channel parameters */ + assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel)); + + if (Channel == LL_DMA_CHANNEL_ALL) + { + /* Force reset of DMA clock */ + LL_AHB2_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPDMA1); + + /* Release reset of DMA clock */ + LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPDMA1); + } + else + { + /* Get the DMA Channel Instance */ + tmp = (DMA_Channel_TypeDef *)(LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel)); + + /* Suspend DMA channel */ + LL_DMA_SuspendChannel(DMAx, Channel); + + /* Disable the selected Channel */ + LL_DMA_ResetChannel(DMAx, Channel); + + /* Reset DMAx_Channely control register */ + LL_DMA_WriteReg(tmp, CLBAR, 0U); + + /* Reset DMAx_Channely control register */ + LL_DMA_WriteReg(tmp, CCR, 0U); + + /* Reset DMAx_Channely Configuration register */ + LL_DMA_WriteReg(tmp, CTR1, 0U); + + /* Reset DMAx_Channely transfer register 2 */ + LL_DMA_WriteReg(tmp, CTR2, 0U); + + /* Reset DMAx_Channely block number of data register */ + LL_DMA_WriteReg(tmp, CBR1, 0U); + + /* Reset DMAx_Channely source address register */ + LL_DMA_WriteReg(tmp, CSAR, 0U); + + /* Reset DMAx_Channely destination address register */ + LL_DMA_WriteReg(tmp, CDAR, 0U); + + + /* Reset DMAx_Channely Linked list address register */ + LL_DMA_WriteReg(tmp, CLLR, 0U); + + /* Reset DMAx_Channely pending flags */ + LL_DMA_WriteReg(tmp, CFCR, 0x00003F00U); +#if defined (DMA_PRIVCFGR_PRIV0) + /* Reset DMAx_Channely attribute */ + LL_DMA_DisableChannelPrivilege(DMAx, Channel); +#endif /* DMA_PRIVCFGR_PRIV0 */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + LL_DMA_DisableChannelSecure(DMAx, Channel); +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + } + + return (uint32_t)status; +} + +/** + * @brief Initialize the DMA registers according to the specified parameters + * in DMA_InitStruct. + * @note This API is used for all available DMA channels. + * @note A software request transfer can be done once programming the direction + * field in memory to memory value. + * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use + * helper macros : + * @arg @ref LL_DMA_GET_INSTANCE + * @arg @ref LL_DMA_GET_CHANNEL + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure. + * @retval An ErrorStatus enumeration value: + * - SUCCESS : DMA registers are initialized. + * - ERROR : Not applicable. + */ +uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct) +{ + /* Check the DMA Instance DMAx and Channel parameters*/ + assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel)); + + /* Check the DMA parameters from DMA_InitStruct */ + assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction)); + + /* Check direction */ + if (DMA_InitStruct->Direction != LL_DMA_DIRECTION_MEMORY_TO_MEMORY) + { + assert_param(IS_LL_DMA_REQUEST_SELECTION(DMA_InitStruct->Request)); + } + + assert_param(IS_LL_DMA_DATA_ALIGNMENT(DMA_InitStruct->DataAlignment)); + assert_param(IS_LL_DMA_SRC_DATA_WIDTH(DMA_InitStruct->SrcDataWidth)); + assert_param(IS_LL_DMA_DEST_DATA_WIDTH(DMA_InitStruct->DestDataWidth)); + assert_param(IS_LL_DMA_SRC_INCREMENT_MODE(DMA_InitStruct->SrcIncMode)); + assert_param(IS_LL_DMA_DEST_INCREMENT_MODE(DMA_InitStruct->DestIncMode)); + assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority)); + assert_param(IS_LL_DMA_BLK_DATALENGTH(DMA_InitStruct->BlkDataLength)); + assert_param(IS_LL_DMA_TRIGGER_POLARITY(DMA_InitStruct->TriggerPolarity)); + assert_param(IS_LL_DMA_BLKHW_REQUEST(DMA_InitStruct->BlkHWRequest)); + assert_param(IS_LL_DMA_TRANSFER_EVENT_MODE(DMA_InitStruct->TransferEventMode)); + assert_param(IS_LL_DMA_LINK_STEP_MODE(DMA_InitStruct->LinkStepMode)); + assert_param(IS_LL_DMA_LINK_BASEADDR(DMA_InitStruct->LinkedListBaseAddr)); + assert_param(IS_LL_DMA_LINK_ADDR_OFFSET(DMA_InitStruct->LinkedListAddrOffset)); + + /* Check DMA instance */ + if (IS_LL_GPDMA_CHANNEL_INSTANCE(DMAx, Channel) != 0U) + { + assert_param(IS_LL_DMA_BURST_LENGTH(DMA_InitStruct->SrcBurstLength)); + assert_param(IS_LL_DMA_BURST_LENGTH(DMA_InitStruct->DestBurstLength)); + assert_param(IS_LL_DMA_DEST_HALFWORD_EXCHANGE(DMA_InitStruct->DestHWordExchange)); + assert_param(IS_LL_DMA_DEST_BYTE_EXCHANGE(DMA_InitStruct->DestByteExchange)); + assert_param(IS_LL_DMA_SRC_BYTE_EXCHANGE(DMA_InitStruct->SrcByteExchange)); + assert_param(IS_LL_DMA_LINK_ALLOCATED_PORT(DMA_InitStruct->LinkAllocatedPort)); + assert_param(IS_LL_DMA_SRC_ALLOCATED_PORT(DMA_InitStruct->SrcAllocatedPort)); + assert_param(IS_LL_DMA_DEST_ALLOCATED_PORT(DMA_InitStruct->DestAllocatedPort)); + } + + /* Check trigger polarity */ + if (DMA_InitStruct->TriggerPolarity != LL_DMA_TRIG_POLARITY_MASKED) + { + assert_param(IS_LL_DMA_TRIGGER_MODE(DMA_InitStruct->TriggerMode)); + assert_param(IS_LL_DMA_TRIGGER_SELECTION(DMA_InitStruct->TriggerSelection)); + } + + + /*-------------------------- DMAx CLBAR Configuration ------------------------ + * Configure the Transfer linked list address with parameter : + * - LinkedListBaseAdd: DMA_CLBAR_LBA[31:16] bits + */ + LL_DMA_SetLinkedListBaseAddr(DMAx, Channel, DMA_InitStruct->LinkedListBaseAddr); + + /*-------------------------- DMAx CCR Configuration -------------------------- + * Configure the control parameter : + * - LinkAllocatedPort: DMA_CCR_LAP bit + * - LinkStepMode: DMA_CCR_LSM bit + * - Priority: DMA_CCR_PRIO [23:22] bits + */ + LL_DMA_ConfigControl(DMAx, Channel, DMA_InitStruct->Priority | \ + DMA_InitStruct->LinkAllocatedPort | \ + DMA_InitStruct->LinkStepMode); + + /*-------------------------- DMAx CTR1 Configuration ------------------------- + * Configure the Data transfer parameter : + * - DestAllocatedPort: DMA_CTR1_DAP bit + * - DestHWordExchange: DMA_CTR1_DHX bit + * - DestByteExchange: DMA_CTR1_DBX bit + * - DestIncMode: DMA_CTR1_DINC bit + * - DestDataWidth: DMA_CTR1_DDW_LOG2 [17:16] bits + * - SrcAllocatedPort: DMA_CTR1_SAP bit + * - SrcByteExchange: DMA_CTR1_SBX bit + * - DataAlignment: DMA_CTR1_PAM [12:11] bits + * - SrcIncMode: DMA_CTR1_SINC bit + * - SrcDataWidth: DMA_CTR1_SDW_LOG2 [1:0] bits + * - SrcBurstLength: DMA_CTR1_SBL_1 [9:4] bits + * - DestBurstLength: DMA_CTR1_DBL_1 [25:20] bits + */ + LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->DestAllocatedPort | \ + DMA_InitStruct->DestHWordExchange | \ + DMA_InitStruct->DestByteExchange | \ + DMA_InitStruct->DestIncMode | \ + DMA_InitStruct->DestDataWidth | \ + DMA_InitStruct->SrcAllocatedPort | \ + DMA_InitStruct->SrcByteExchange | \ + DMA_InitStruct->DataAlignment | \ + DMA_InitStruct->SrcIncMode | \ + DMA_InitStruct->SrcDataWidth); + /* Check DMA instance */ + if (IS_LL_GPDMA_CHANNEL_INSTANCE(DMAx, Channel) != 0U) + { + LL_DMA_ConfigBurstLength(DMAx, Channel, DMA_InitStruct->SrcBurstLength, + DMA_InitStruct->DestBurstLength); + } + + /*-------------------------- DMAx CTR2 Configuration ------------------------- + * Configure the channel transfer parameter : + * - TransferEventMode: DMA_CTR2_TCEM [31:30] bits + * - TriggerPolarity: DMA_CTR2_TRIGPOL [25:24] bits + * - TriggerMode: DMA_CTR2_TRIGM [15:14] bits + * - BlkHWRequest: DMA_CTR2_BREQ bit + * - Direction: DMA_CTR2_DREQ bit + * - Direction: DMA_CTR2_SWREQ bit + * - TriggerSelection: DMA_CTR2_TRIGSEL [21:16] bits + * - Request: DMA_CTR2_REQSEL [6:0] bits + */ + LL_DMA_ConfigChannelTransfer(DMAx, Channel, DMA_InitStruct->TransferEventMode | \ + DMA_InitStruct->TriggerPolarity | \ + DMA_InitStruct->BlkHWRequest | \ + DMA_InitStruct->Direction); + + /* Check direction */ + if (DMA_InitStruct->Direction != LL_DMA_DIRECTION_MEMORY_TO_MEMORY) + { + LL_DMA_SetPeriphRequest(DMAx, Channel, DMA_InitStruct->Request); + } + + /* Check trigger polarity */ + if (DMA_InitStruct->TriggerPolarity != LL_DMA_TRIG_POLARITY_MASKED) + { + LL_DMA_SetHWTrigger(DMAx, Channel, DMA_InitStruct->TriggerSelection); + LL_DMA_SetTriggerMode(DMAx, Channel, DMA_InitStruct->TriggerMode); + } + + /*-------------------------- DMAx CBR1 Configuration ------------------------- + * Configure the Transfer Block counters and update mode with parameter : + * - BlkDataLength: DMA_CBR1_BNDT[15:0] bits + */ + LL_DMA_SetBlkDataLength(DMAx, Channel, DMA_InitStruct->BlkDataLength); + + /*-------------------------- DMAx CSAR and CDAR Configuration ---------------- + * Configure the Transfer source address with parameter : + * - SrcAddress: DMA_CSAR_SA[31:0] bits + * - DestAddress: DMA_CDAR_DA[31:0] bits + */ + LL_DMA_ConfigAddresses(DMAx, Channel, DMA_InitStruct->SrcAddress, DMA_InitStruct->DestAddress); + + /*-------------------------- DMAx CLLR Configuration ------------------------- + * Configure the Transfer linked list address with parameter : + * - DestAddrOffset: DMA_CLLR_LA[15:2] bits + */ + LL_DMA_SetLinkedListAddrOffset(DMAx, Channel, DMA_InitStruct->LinkedListAddrOffset); + + return (uint32_t)SUCCESS; +} + +/** + * @brief Set each @ref LL_DMA_InitTypeDef field to default value. + * @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure. + * @retval None. + */ +void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct) +{ + /* Set DMA_InitStruct fields to default values */ + DMA_InitStruct->SrcAddress = 0x00000000U; + DMA_InitStruct->DestAddress = 0x00000000U; + DMA_InitStruct->Direction = LL_DMA_DIRECTION_MEMORY_TO_MEMORY; + DMA_InitStruct->BlkHWRequest = LL_DMA_HWREQUEST_SINGLEBURST; + DMA_InitStruct->DataAlignment = LL_DMA_DATA_ALIGN_ZEROPADD; + DMA_InitStruct->SrcBurstLength = 1U; + DMA_InitStruct->DestBurstLength = 1U; + DMA_InitStruct->SrcDataWidth = LL_DMA_SRC_DATAWIDTH_BYTE; + DMA_InitStruct->DestDataWidth = LL_DMA_DEST_DATAWIDTH_BYTE; + DMA_InitStruct->SrcIncMode = LL_DMA_SRC_FIXED; + DMA_InitStruct->DestIncMode = LL_DMA_DEST_FIXED; + DMA_InitStruct->Priority = LL_DMA_LOW_PRIORITY_LOW_WEIGHT; + DMA_InitStruct->BlkDataLength = 0x00000000U; + DMA_InitStruct->TriggerMode = LL_DMA_TRIGM_BLK_TRANSFER; + DMA_InitStruct->TriggerPolarity = LL_DMA_TRIG_POLARITY_MASKED; + DMA_InitStruct->TriggerSelection = 0x00000000U; + DMA_InitStruct->Request = 0x00000000U; + DMA_InitStruct->TransferEventMode = LL_DMA_TCEM_BLK_TRANSFER; + DMA_InitStruct->DestHWordExchange = LL_DMA_DEST_HALFWORD_PRESERVE; + DMA_InitStruct->DestByteExchange = LL_DMA_DEST_BYTE_PRESERVE; + DMA_InitStruct->SrcByteExchange = LL_DMA_SRC_BYTE_PRESERVE; + DMA_InitStruct->SrcAllocatedPort = LL_DMA_SRC_ALLOCATED_PORT0; + DMA_InitStruct->DestAllocatedPort = LL_DMA_DEST_ALLOCATED_PORT0; + DMA_InitStruct->LinkAllocatedPort = LL_DMA_LINK_ALLOCATED_PORT0; + DMA_InitStruct->LinkStepMode = LL_DMA_LSM_FULL_EXECUTION; + DMA_InitStruct->LinkedListBaseAddr = 0x00000000U; + DMA_InitStruct->LinkedListAddrOffset = 0x00000000U; +} + +/** + * @brief Set each @ref LL_DMA_InitLinkedListTypeDef field to default value. + * @param DMA_InitLinkedListStruct Pointer to + * a @ref LL_DMA_InitLinkedListTypeDef structure. + * @retval None. + */ +void LL_DMA_ListStructInit(LL_DMA_InitLinkedListTypeDef *DMA_InitLinkedListStruct) +{ + /* Set LL_DMA_InitLinkedListTypeDef fields to default values */ + DMA_InitLinkedListStruct->Priority = LL_DMA_LOW_PRIORITY_LOW_WEIGHT; + DMA_InitLinkedListStruct->LinkStepMode = LL_DMA_LSM_FULL_EXECUTION; + DMA_InitLinkedListStruct->TransferEventMode = LL_DMA_TCEM_LAST_LLITEM_TRANSFER; + DMA_InitLinkedListStruct->LinkAllocatedPort = LL_DMA_LINK_ALLOCATED_PORT0; +} + +/** + * @brief De-initialize the DMA linked list. + * @note This API is used for all available DMA channels. + * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use + * helper macros : + * @arg @ref LL_DMA_GET_INSTANCE + * @arg @ref LL_DMA_GET_CHANNEL + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval An ErrorStatus enumeration value: + * - SUCCESS : DMA registers are de-initialized. + * - ERROR : DMA registers are not de-initialized. + */ +uint32_t LL_DMA_List_DeInit(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return LL_DMA_DeInit(DMAx, Channel); +} + +/** + * @brief Initialize the DMA linked list according to the specified parameters + * in LL_DMA_InitLinkedListTypeDef. + * @note This API is used for all available DMA channels. + * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use + * helper macros : + * @arg @ref LL_DMA_GET_INSTANCE + * @arg @ref LL_DMA_GET_CHANNEL + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param DMA_InitLinkedListStruct pointer to + * a @ref LL_DMA_InitLinkedListTypeDef structure. + * @retval An ErrorStatus enumeration value: + * - SUCCESS : DMA registers are initialized. + * - ERROR : Not applicable. + */ +uint32_t LL_DMA_List_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitLinkedListTypeDef *DMA_InitLinkedListStruct) +{ + /* Check the DMA Instance DMAx and Channel parameters*/ + assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel)); + + /* Check the DMA parameters from DMA_InitLinkedListStruct */ + assert_param(IS_LL_DMA_PRIORITY(DMA_InitLinkedListStruct->Priority)); + assert_param(IS_LL_DMA_LINK_STEP_MODE(DMA_InitLinkedListStruct->LinkStepMode)); + assert_param(IS_LL_DMA_TRANSFER_EVENT_MODE(DMA_InitLinkedListStruct->TransferEventMode)); + /* Check DMA instance */ + if (IS_LL_GPDMA_CHANNEL_INSTANCE(DMAx, Channel) != 0U) + { + assert_param(IS_LL_DMA_LINK_ALLOCATED_PORT(DMA_InitLinkedListStruct->LinkAllocatedPort)); + } + + /*-------------------------- DMAx CCR Configuration -------------------------- + * Configure the control parameter : + * - LinkAllocatedPort: DMA_CCR_LAP bit + * LinkAllocatedPort field is supported only by GPDMA channels. + * - LinkStepMode: DMA_CCR_LSM bit + * - Priority: DMA_CCR_PRIO [23:22] bits + */ + LL_DMA_ConfigControl(DMAx, Channel, DMA_InitLinkedListStruct->Priority | \ + DMA_InitLinkedListStruct->LinkAllocatedPort | \ + DMA_InitLinkedListStruct->LinkStepMode); + + /*-------------------------- DMAx CTR2 Configuration ------------------------- + * Configure the channel transfer parameter : + * - TransferEventMode: DMA_CTR2_TCEM [31:30] bits + */ + LL_DMA_SetTransferEventMode(DMAx, Channel, DMA_InitLinkedListStruct->TransferEventMode); + + return (uint32_t)SUCCESS; +} + +/** + * @brief Set each @ref LL_DMA_InitNodeTypeDef field to default value. + * @param DMA_InitNodeStruct Pointer to a @ref LL_DMA_InitNodeTypeDef + * structure. + * @retval None. + */ +void LL_DMA_NodeStructInit(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct) +{ + /* Set DMA_InitNodeStruct fields to default values */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + DMA_InitNodeStruct->DestSecure = LL_DMA_CHANNEL_DEST_NSEC; +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + DMA_InitNodeStruct->DestAllocatedPort = LL_DMA_DEST_ALLOCATED_PORT0; + DMA_InitNodeStruct->DestHWordExchange = LL_DMA_DEST_HALFWORD_PRESERVE; + DMA_InitNodeStruct->DestByteExchange = LL_DMA_DEST_BYTE_PRESERVE; + DMA_InitNodeStruct->DestBurstLength = 1U; + DMA_InitNodeStruct->DestIncMode = LL_DMA_DEST_FIXED; + DMA_InitNodeStruct->DestDataWidth = LL_DMA_DEST_DATAWIDTH_BYTE; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + DMA_InitNodeStruct->SrcSecure = LL_DMA_CHANNEL_SRC_NSEC; +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + DMA_InitNodeStruct->SrcAllocatedPort = LL_DMA_SRC_ALLOCATED_PORT0; + DMA_InitNodeStruct->SrcByteExchange = LL_DMA_SRC_BYTE_PRESERVE; + DMA_InitNodeStruct->DataAlignment = LL_DMA_DATA_ALIGN_ZEROPADD; + DMA_InitNodeStruct->SrcBurstLength = 1U; + DMA_InitNodeStruct->SrcIncMode = LL_DMA_SRC_FIXED; + DMA_InitNodeStruct->SrcDataWidth = LL_DMA_SRC_DATAWIDTH_BYTE; + DMA_InitNodeStruct->TransferEventMode = LL_DMA_TCEM_BLK_TRANSFER; + DMA_InitNodeStruct->TriggerPolarity = LL_DMA_TRIG_POLARITY_MASKED; + DMA_InitNodeStruct->TriggerSelection = 0x00000000U; + DMA_InitNodeStruct->TriggerMode = LL_DMA_TRIGM_BLK_TRANSFER; + DMA_InitNodeStruct->BlkHWRequest = LL_DMA_HWREQUEST_SINGLEBURST; + DMA_InitNodeStruct->Direction = LL_DMA_DIRECTION_MEMORY_TO_MEMORY; + DMA_InitNodeStruct->Request = 0x00000000U; + DMA_InitNodeStruct->BlkDataLength = 0x00000000U; + DMA_InitNodeStruct->SrcAddress = 0x00000000U; + DMA_InitNodeStruct->DestAddress = 0x00000000U; + DMA_InitNodeStruct->UpdateRegisters = (LL_DMA_UPDATE_CTR1 | LL_DMA_UPDATE_CTR2 | \ + LL_DMA_UPDATE_CBR1 | LL_DMA_UPDATE_CSAR | \ + LL_DMA_UPDATE_CDAR | LL_DMA_UPDATE_CLLR); + DMA_InitNodeStruct->NodeType = LL_DMA_GPDMA_LINEAR_NODE; +} + +/** + * @brief Initializes DMA linked list node according to the specified + * parameters in the DMA_InitNodeStruct. + * @param DMA_InitNodeStruct Pointer to a LL_DMA_InitNodeTypeDef structure + * that contains linked list node + * registers configurations. + * @param pNode Pointer to linked list node to fill according to + * LL_DMA_LinkNodeTypeDef parameters. + * @retval None + */ +uint32_t LL_DMA_CreateLinkNode(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct, LL_DMA_LinkNodeTypeDef *pNode) +{ + uint32_t reg_counter = 0U; + + /* Check the DMA Node type */ + assert_param(IS_LL_DMA_LINK_NODETYPE(DMA_InitNodeStruct->NodeType)); + + /* Check the DMA parameters from DMA_InitNodeStruct */ + assert_param(IS_LL_DMA_DIRECTION(DMA_InitNodeStruct->Direction)); + + /* Check direction */ + if (DMA_InitNodeStruct->Direction != LL_DMA_DIRECTION_MEMORY_TO_MEMORY) + { + assert_param(IS_LL_DMA_REQUEST_SELECTION(DMA_InitNodeStruct->Request)); + } + + assert_param(IS_LL_DMA_DATA_ALIGNMENT(DMA_InitNodeStruct->DataAlignment)); + assert_param(IS_LL_DMA_SRC_DATA_WIDTH(DMA_InitNodeStruct->SrcDataWidth)); + assert_param(IS_LL_DMA_DEST_DATA_WIDTH(DMA_InitNodeStruct->DestDataWidth)); + assert_param(IS_LL_DMA_SRC_INCREMENT_MODE(DMA_InitNodeStruct->SrcIncMode)); + assert_param(IS_LL_DMA_DEST_INCREMENT_MODE(DMA_InitNodeStruct->DestIncMode)); + assert_param(IS_LL_DMA_BLK_DATALENGTH(DMA_InitNodeStruct->BlkDataLength)); + assert_param(IS_LL_DMA_TRIGGER_POLARITY(DMA_InitNodeStruct->TriggerPolarity)); + assert_param(IS_LL_DMA_BLKHW_REQUEST(DMA_InitNodeStruct->BlkHWRequest)); + assert_param(IS_LL_DMA_TRANSFER_EVENT_MODE(DMA_InitNodeStruct->TransferEventMode)); + assert_param(IS_LL_DMA_LINK_UPDATE_REGISTERS(DMA_InitNodeStruct->UpdateRegisters)); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + assert_param(IS_LL_DMA_CHANNEL_SRC_SEC(DMA_InitNodeStruct->SrcSecure)); + assert_param(IS_LL_DMA_CHANNEL_DEST_SEC(DMA_InitNodeStruct->DestSecure)); +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + /* Check trigger polarity */ + if (DMA_InitNodeStruct->TriggerPolarity != LL_DMA_TRIG_POLARITY_MASKED) + { + assert_param(IS_LL_DMA_TRIGGER_MODE(DMA_InitNodeStruct->TriggerMode)); + assert_param(IS_LL_DMA_TRIGGER_SELECTION(DMA_InitNodeStruct->TriggerSelection)); + } + + /* Check node type */ + if (DMA_InitNodeStruct->NodeType == LL_DMA_GPDMA_LINEAR_NODE) + { + assert_param(IS_LL_DMA_DEST_HALFWORD_EXCHANGE(DMA_InitNodeStruct->DestHWordExchange)); + assert_param(IS_LL_DMA_DEST_BYTE_EXCHANGE(DMA_InitNodeStruct->DestByteExchange)); + assert_param(IS_LL_DMA_SRC_BYTE_EXCHANGE(DMA_InitNodeStruct->SrcByteExchange)); + assert_param(IS_LL_DMA_SRC_ALLOCATED_PORT(DMA_InitNodeStruct->SrcAllocatedPort)); + assert_param(IS_LL_DMA_DEST_ALLOCATED_PORT(DMA_InitNodeStruct->DestAllocatedPort)); + } + + + /* Check if CTR1 register update is enabled */ + if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CTR1) == LL_DMA_UPDATE_CTR1) + { + /*-------------------------- DMAx CTR1 Configuration ----------------------- + * Configure the Data transfer parameter : + * - DestAllocatedPort: DMA_CTR1_DAP bit + * - DestHWordExchange: DMA_CTR1_DHX bit + * - DestByteExchange: DMA_CTR1_DBX bit + * - DestIncMode: DMA_CTR1_DINC bit + * - DestDataWidth: DMA_CTR1_DDW_LOG2 [17:16] bits + * - SrcAllocatedPort: DMA_CTR1_SAP bit + * - SrcByteExchange: DMA_CTR1_SBX bit + * - DataAlignment: DMA_CTR1_PAM [12:11] bits + * - SrcIncMode: DMA_CTR1_SINC bit + * - SrcDataWidth: DMA_CTR1_SDW_LOG2 [1:0] bits + * - SrcBurstLength: DMA_CTR1_SBL_1 [9:4] bits + * - DestBurstLength: DMA_CTR1_DBL_1 [25:20] bits + */ + + pNode->LinkRegisters[reg_counter] = (DMA_InitNodeStruct->DestIncMode | \ + DMA_InitNodeStruct->DestDataWidth | \ + DMA_InitNodeStruct->DataAlignment | \ + DMA_InitNodeStruct->SrcIncMode | \ + DMA_InitNodeStruct->SrcDataWidth); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + pNode->LinkRegisters[reg_counter] |= (DMA_InitNodeStruct->DestSecure | \ + DMA_InitNodeStruct->SrcSecure); +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + /* Update CTR1 register fields */ + pNode->LinkRegisters[reg_counter] |= (DMA_InitNodeStruct->DestAllocatedPort | \ + DMA_InitNodeStruct->DestHWordExchange | \ + DMA_InitNodeStruct->DestByteExchange | \ + ((DMA_InitNodeStruct->DestBurstLength - 1U) << DMA_CTR1_DBL_1_Pos) | \ + DMA_InitNodeStruct->SrcAllocatedPort | \ + DMA_InitNodeStruct->SrcByteExchange | \ + ((DMA_InitNodeStruct->SrcBurstLength - 1U) << DMA_CTR1_SBL_1_Pos)); + + /* Increment counter for the next register */ + reg_counter++; + } + + + /* Check if CTR2 register update is enabled */ + if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CTR2) == LL_DMA_UPDATE_CTR2) + { + /*-------------------------- DMAx CTR2 Configuration ----------------------- + * Configure the channel transfer parameter : + * - TransferEventMode: DMA_CTR2_TCEM [31:30] bits + * - TriggerPolarity: DMA_CTR2_TRIGPOL [25:24] bits + * - TriggerMode: DMA_CTR2_TRIGM [15:14] bits + * - BlkHWRequest: DMA_CTR2_BREQ bit + * - Direction: DMA_CTR2_DREQ bit + * - Direction: DMA_CTR2_SWREQ bit + * - TriggerSelection: DMA_CTR2_TRIGSEL [21:16] bits + * - Request: DMA_CTR2_REQSEL [6:0] bits + */ + pNode->LinkRegisters[reg_counter] = (DMA_InitNodeStruct->TransferEventMode | \ + DMA_InitNodeStruct->TriggerPolarity | \ + DMA_InitNodeStruct->BlkHWRequest | \ + DMA_InitNodeStruct->Direction); + + /* Check direction */ + if (DMA_InitNodeStruct->Direction != LL_DMA_DIRECTION_MEMORY_TO_MEMORY) + { + pNode->LinkRegisters[reg_counter] |= DMA_InitNodeStruct->Request & DMA_CTR2_REQSEL; + } + + /* Check trigger polarity */ + if (DMA_InitNodeStruct->TriggerPolarity != LL_DMA_TRIG_POLARITY_MASKED) + { + pNode->LinkRegisters[reg_counter] |= (((DMA_InitNodeStruct->TriggerSelection << DMA_CTR2_TRIGSEL_Pos) & \ + DMA_CTR2_TRIGSEL) | DMA_InitNodeStruct->TriggerMode); + } + + + /* Increment counter for the next register */ + reg_counter++; + } + /* Check if CBR1 register update is enabled */ + if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CBR1) == LL_DMA_UPDATE_CBR1) + { + /*-------------------------- DMAx CBR1 Configuration ----------------------- + * Configure the Transfer Block counters and update mode with parameter : + * - BlkDataLength: DMA_CBR1_BNDT[15:0] bits + */ + pNode->LinkRegisters[reg_counter] = DMA_InitNodeStruct->BlkDataLength; + + /* Increment counter for the next register */ + reg_counter++; + } + /* Check if CSAR register update is enabled */ + if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CSAR) == LL_DMA_UPDATE_CSAR) + { + /*-------------------------- DMAx CSAR Configuration ----------------------- + * Configure the Transfer Block counters and update mode with parameter : + * - SrcAddress: DMA_CSAR_SA[31:0] bits + */ + pNode->LinkRegisters[reg_counter] = DMA_InitNodeStruct->SrcAddress; + + /* Increment counter for the next register */ + reg_counter++; + } + + + /* Check if CDAR register update is enabled */ + if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CDAR) == LL_DMA_UPDATE_CDAR) + { + /*-------------------------- DMAx CDAR Configuration ----------------------- + * Configure the Transfer Block counters and update mode with parameter : + * - DestAddress: DMA_CDAR_DA[31:0] bits + */ + pNode->LinkRegisters[reg_counter] = DMA_InitNodeStruct->DestAddress; + + /* Increment counter for the next register */ + reg_counter++; + } + + + + /* Check if CLLR register update is enabled */ + if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CLLR) == LL_DMA_UPDATE_CLLR) + { + /*-------------------------- DMAx CLLR Configuration ----------------------- + * Configure the Transfer Block counters and update mode with parameter : + * - UpdateRegisters DMA_CLLR_UT1 bit + * - UpdateRegisters DMA_CLLR_UT2 bit + * - UpdateRegisters DMA_CLLR_UB1 bit + * - UpdateRegisters DMA_CLLR_USA bit + * - UpdateRegisters DMA_CLLR_UDA bit + * - UpdateRegisters DMA_CLLR_ULL bit + */ + pNode->LinkRegisters[reg_counter] = ((DMA_InitNodeStruct->UpdateRegisters & (DMA_CLLR_UT1 | DMA_CLLR_UT2 | \ + DMA_CLLR_UB1 | DMA_CLLR_USA | \ + DMA_CLLR_UDA | DMA_CLLR_ULL))); + + } + + return (uint32_t)SUCCESS; +} + +/** + * @brief Connect Linked list Nodes. + * @param pPrevLinkNode Pointer to previous linked list node to be connected to new Linked list node. + * @param PrevNodeCLLRIdx Offset of Previous Node CLLR register. + * This parameter can be a value of @ref DMA_LL_EC_CLLR_OFFSET. + * @param pNewLinkNode Pointer to new Linked list. + * @param NewNodeCLLRIdx Offset of New Node CLLR register. + * This parameter can be a value of @ref DMA_LL_EC_CLLR_OFFSET. + * @retval None + */ +void LL_DMA_ConnectLinkNode(LL_DMA_LinkNodeTypeDef *pPrevLinkNode, uint32_t PrevNodeCLLRIdx, + LL_DMA_LinkNodeTypeDef *pNewLinkNode, uint32_t NewNodeCLLRIdx) +{ + pPrevLinkNode->LinkRegisters[PrevNodeCLLRIdx] = (((uint32_t)pNewLinkNode & DMA_CLLR_LA) | \ + (pNewLinkNode->LinkRegisters[NewNodeCLLRIdx] & (DMA_CLLR_UT1 | \ + DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | \ + DMA_CLLR_ULL))); +} + +/** + * @brief Disconnect the next linked list node. + * @param pLinkNode Pointer to linked list node to be disconnected from the next one. + * @param LinkNodeCLLRIdx Offset of Link Node CLLR register. + * @retval None. + */ +void LL_DMA_DisconnectNextLinkNode(LL_DMA_LinkNodeTypeDef *pLinkNode, uint32_t LinkNodeCLLRIdx) +{ + pLinkNode->LinkRegisters[LinkNodeCLLRIdx] = 0; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* GPDMA1 */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_exti.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_exti.c new file mode 100644 index 0000000000..e47e04738e --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_exti.c @@ -0,0 +1,219 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_ll_exti.c + * @author MCD Application Team + * @brief EXTI LL module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_ll_exti.h" +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +/** @addtogroup STM32WBAxx_LL_Driver + * @{ + */ + +#if defined (EXTI) + +/** @defgroup EXTI_LL EXTI + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup EXTI_LL_Private_Macros + * @{ + */ + +#define IS_LL_EXTI_LINE_0_31(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U) + +#define IS_LL_EXTI_MODE(__VALUE__) (((__VALUE__) == LL_EXTI_MODE_IT) \ + || ((__VALUE__) == LL_EXTI_MODE_EVENT) \ + || ((__VALUE__) == LL_EXTI_MODE_IT_EVENT)) + + +#define IS_LL_EXTI_TRIGGER(__VALUE__) (((__VALUE__) == LL_EXTI_TRIGGER_NONE) \ + || ((__VALUE__) == LL_EXTI_TRIGGER_RISING) \ + || ((__VALUE__) == LL_EXTI_TRIGGER_FALLING) \ + || ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING)) + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup EXTI_LL_Exported_Functions + * @{ + */ + +/** @addtogroup EXTI_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize the EXTI registers to their default reset values. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: EXTI registers are de-initialized + * - ERROR: not applicable + */ +ErrorStatus LL_EXTI_DeInit(void) +{ + /* Interrupt mask register set to default reset values */ + LL_EXTI_WriteReg(IMR1, 0xFF9E0000U); + /* Event mask register set to default reset values */ + LL_EXTI_WriteReg(EMR1, 0x00000000U); + /* Rising Trigger selection register set to default reset values */ + LL_EXTI_WriteReg(RTSR1, 0x00000000U); + /* Falling Trigger selection register set to default reset values */ + LL_EXTI_WriteReg(FTSR1, 0x00000000U); + /* Software interrupt event register set to default reset values */ + LL_EXTI_WriteReg(SWIER1, 0x00000000U); + /* Pending register set to default reset values */ + LL_EXTI_WriteReg(RPR1, 0xFFFFFFFFU); + LL_EXTI_WriteReg(FPR1, 0xFFFFFFFFU); +#if defined(EXTI_PRIVCFGR1_PRIV0) + /* Privilege register set to default reset values */ + LL_EXTI_WriteReg(PRIVCFGR1, 0x00000000U); +#endif /* EXTI_PRIVCFGR1_PRIV0 */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + /* Secure register set to default reset values */ + LL_EXTI_WriteReg(SECCFGR1, 0x00000000U); +#endif /* __ARM_FEATURE_CMSE */ + return SUCCESS; +} + +/** + * @brief Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct. + * @param EXTI_InitStruct pointer to a @ref LL_EXTI_InitTypeDef structure. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: EXTI registers are initialized + * - ERROR: not applicable + */ +ErrorStatus LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct) +{ + ErrorStatus status = SUCCESS; + /* Check the parameters */ + assert_param(IS_LL_EXTI_LINE_0_31(EXTI_InitStruct->Line_0_31)); + assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->LineCommand)); + assert_param(IS_LL_EXTI_MODE(EXTI_InitStruct->Mode)); + + /* ENABLE LineCommand */ + if (EXTI_InitStruct->LineCommand != DISABLE) + { + assert_param(IS_LL_EXTI_TRIGGER(EXTI_InitStruct->Trigger)); + + /* Configure EXTI Lines in range from 0 to 31 */ + if (EXTI_InitStruct->Line_0_31 != LL_EXTI_LINE_NONE) + { + switch (EXTI_InitStruct->Mode) + { + case LL_EXTI_MODE_IT: + /* First Disable Event on provided Lines */ + LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31); + /* Then Enable IT on provided Lines */ + LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31); + break; + case LL_EXTI_MODE_EVENT: + /* First Disable IT on provided Lines */ + LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31); + /* Then Enable Event on provided Lines */ + LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31); + break; + case LL_EXTI_MODE_IT_EVENT: + /* Directly Enable IT & Event on provided Lines */ + LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31); + LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31); + break; + default: + status = ERROR; + break; + } + if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE) + { + switch (EXTI_InitStruct->Trigger) + { + case LL_EXTI_TRIGGER_RISING: + /* First Disable Falling Trigger on provided Lines */ + LL_EXTI_DisableFallingTrig_0_31(EXTI_InitStruct->Line_0_31); + /* Then Enable Rising Trigger on provided Lines */ + LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31); + break; + case LL_EXTI_TRIGGER_FALLING: + /* First Disable Rising Trigger on provided Lines */ + LL_EXTI_DisableRisingTrig_0_31(EXTI_InitStruct->Line_0_31); + /* Then Enable Falling Trigger on provided Lines */ + LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31); + break; + case LL_EXTI_TRIGGER_RISING_FALLING: + LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31); + LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31); + break; + default: + status = ERROR; + break; + } + } + } + } + /* DISABLE LineCommand */ + else + { + /* De-configure EXTI Lines in range from 0 to 31 */ + LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31); + LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31); + } + return status; +} + +/** + * @brief Set each @ref LL_EXTI_InitTypeDef field to default value. + * @param EXTI_InitStruct Pointer to a @ref LL_EXTI_InitTypeDef structure. + * @retval None + */ +void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct) +{ + EXTI_InitStruct->Line_0_31 = LL_EXTI_LINE_NONE; + EXTI_InitStruct->LineCommand = DISABLE; + EXTI_InitStruct->Mode = LL_EXTI_MODE_IT; + EXTI_InitStruct->Trigger = LL_EXTI_TRIGGER_FALLING; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (EXTI) */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_gpio.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_gpio.c new file mode 100644 index 0000000000..8661f1a656 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_gpio.c @@ -0,0 +1,254 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_ll_gpio.c + * @author MCD Application Team + * @brief GPIO LL module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_ll_gpio.h" +#include "stm32wbaxx_ll_bus.h" +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +/** @addtogroup STM32WBAxx_LL_Driver + * @{ + */ + +#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOH) + +/** @addtogroup GPIO_LL + * @{ + */ +/** MISRA C:2012 deviation rule has been granted for following rules: + * Rule-12.2 - Medium: RHS argument is in interval [0,INF] which is out of + * range of the shift operator in following API : + * LL_GPIO_Init + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup GPIO_LL_Private_Macros + * @{ + */ +#define IS_LL_GPIO_PIN(__VALUE__) (((0x00u) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL))) + +#define IS_LL_GPIO_MODE(__VALUE__) (((__VALUE__) == LL_GPIO_MODE_INPUT) ||\ + ((__VALUE__) == LL_GPIO_MODE_OUTPUT) ||\ + ((__VALUE__) == LL_GPIO_MODE_ALTERNATE) ||\ + ((__VALUE__) == LL_GPIO_MODE_ANALOG)) + +#define IS_LL_GPIO_OUTPUT_TYPE(__VALUE__) (((__VALUE__) == LL_GPIO_OUTPUT_PUSHPULL) ||\ + ((__VALUE__) == LL_GPIO_OUTPUT_OPENDRAIN)) + +#define IS_LL_GPIO_SPEED(__VALUE__) (((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW) ||\ + ((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM) ||\ + ((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH)) + +#define IS_LL_GPIO_PULL(__VALUE__) (((__VALUE__) == LL_GPIO_PULL_NO) ||\ + ((__VALUE__) == LL_GPIO_PULL_UP) ||\ + ((__VALUE__) == LL_GPIO_PULL_DOWN)) + +#define IS_LL_GPIO_ALTERNATE(__VALUE__) (((__VALUE__) == LL_GPIO_AF_0 ) ||\ + ((__VALUE__) == LL_GPIO_AF_1 ) ||\ + ((__VALUE__) == LL_GPIO_AF_2 ) ||\ + ((__VALUE__) == LL_GPIO_AF_3 ) ||\ + ((__VALUE__) == LL_GPIO_AF_4 ) ||\ + ((__VALUE__) == LL_GPIO_AF_5 ) ||\ + ((__VALUE__) == LL_GPIO_AF_6 ) ||\ + ((__VALUE__) == LL_GPIO_AF_7 ) ||\ + ((__VALUE__) == LL_GPIO_AF_8 ) ||\ + ((__VALUE__) == LL_GPIO_AF_9 ) ||\ + ((__VALUE__) == LL_GPIO_AF_10 ) ||\ + ((__VALUE__) == LL_GPIO_AF_11 ) ||\ + ((__VALUE__) == LL_GPIO_AF_12 ) ||\ + ((__VALUE__) == LL_GPIO_AF_13 ) ||\ + ((__VALUE__) == LL_GPIO_AF_14 ) ||\ + ((__VALUE__) == LL_GPIO_AF_15 )) +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup GPIO_LL_Exported_Functions + * @{ + */ + +/** @addtogroup GPIO_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize GPIO registers (Registers restored to their default values). + * @param GPIOx GPIO Port + * @retval An ErrorStatus enumeration value: + * - SUCCESS: GPIO registers are de-initialized + * - ERROR: Wrong GPIO Port + */ +ErrorStatus LL_GPIO_DeInit(const GPIO_TypeDef *GPIOx) +{ + ErrorStatus status = SUCCESS; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + + /* Force and Release reset on clock of GPIOx Port */ + if (GPIOx == GPIOA) + { + LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOA); + LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOA); + } + else if (GPIOx == GPIOB) + { + LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOB); + LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOB); + } + else if (GPIOx == GPIOC) + { + LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOC); + LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOC); + } + else if (GPIOx == GPIOH) + { + LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOH); + LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOH); + } + else + { + status = ERROR; + } + + return (status); +} + +/** + * @brief Initialize GPIO registers according to the specified parameters in GPIO_InitStruct. + * @param GPIOx GPIO Port + * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure + * that contains the configuration information for the specified GPIO peripheral. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content + * - ERROR: Not applicable + */ +ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct) +{ + uint32_t pinpos; + uint32_t currentpin; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_LL_GPIO_PIN(GPIO_InitStruct->Pin)); + assert_param(IS_LL_GPIO_MODE(GPIO_InitStruct->Mode)); + assert_param(IS_LL_GPIO_PULL(GPIO_InitStruct->Pull)); + + /* ------------------------- Configure the port pins ---------------- */ + /* Initialize pinpos on first pin set */ + pinpos = POSITION_VAL(GPIO_InitStruct->Pin); + + /* Configure the port pins */ + while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00u) + { + /* Get current io position */ + currentpin = (GPIO_InitStruct->Pin) & (0x00000001uL << pinpos); + + if (currentpin != 0x00u) + { + if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)) + { + /* Check Speed mode parameters */ + assert_param(IS_LL_GPIO_SPEED(GPIO_InitStruct->Speed)); + + /* Speed mode configuration */ + LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed); + + /* Check Output mode parameters */ + assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType)); + + /* Output mode configuration*/ + LL_GPIO_SetPinOutputType(GPIOx, currentpin, GPIO_InitStruct->OutputType); + } + + /* Pull-up Pull down resistor configuration*/ + LL_GPIO_SetPinPull(GPIOx, currentpin, GPIO_InitStruct->Pull); + + if (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE) + { + /* Check Alternate parameter */ + assert_param(IS_LL_GPIO_ALTERNATE(GPIO_InitStruct->Alternate)); + + /* Speed mode configuration */ + if (currentpin < LL_GPIO_PIN_8) + { + LL_GPIO_SetAFPin_0_7(GPIOx, currentpin, GPIO_InitStruct->Alternate); + } + else + { + LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate); + } + } + + /* Pin Mode configuration */ + LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode); + } + pinpos++; + } + + return (SUCCESS); +} + +/** + * @brief Set each @ref LL_GPIO_InitTypeDef field to default value. + * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ + +void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct) +{ + /* Reset GPIO init structure parameters values */ + GPIO_InitStruct->Pin = LL_GPIO_PIN_ALL; + GPIO_InitStruct->Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct->Speed = LL_GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct->OutputType = LL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct->Pull = LL_GPIO_PULL_NO; + GPIO_InitStruct->Alternate = LL_GPIO_AF_0; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOH) */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_i2c.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_i2c.c new file mode 100644 index 0000000000..2dedda0a2f --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_i2c.c @@ -0,0 +1,225 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_ll_i2c.c + * @author MCD Application Team + * @brief I2C LL module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_ll_i2c.h" +#include "stm32wbaxx_ll_bus.h" +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +/** @addtogroup STM32WBAxx_LL_Driver + * @{ + */ + +#if defined (I2C1) || defined (I2C3) + +/** @defgroup I2C_LL I2C + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup I2C_LL_Private_Macros + * @{ + */ + +#define IS_LL_I2C_PERIPHERAL_MODE(__VALUE__) (((__VALUE__) == LL_I2C_MODE_I2C) || \ + ((__VALUE__) == LL_I2C_MODE_SMBUS_HOST) || \ + ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE) || \ + ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE_ARP)) + +#define IS_LL_I2C_ANALOG_FILTER(__VALUE__) (((__VALUE__) == LL_I2C_ANALOGFILTER_ENABLE) || \ + ((__VALUE__) == LL_I2C_ANALOGFILTER_DISABLE)) + +#define IS_LL_I2C_DIGITAL_FILTER(__VALUE__) ((__VALUE__) <= 0x0000000FU) + +#define IS_LL_I2C_OWN_ADDRESS1(__VALUE__) ((__VALUE__) <= 0x000003FFU) + +#define IS_LL_I2C_TYPE_ACKNOWLEDGE(__VALUE__) (((__VALUE__) == LL_I2C_ACK) || \ + ((__VALUE__) == LL_I2C_NACK)) + +#define IS_LL_I2C_OWN_ADDRSIZE(__VALUE__) (((__VALUE__) == LL_I2C_OWNADDRESS1_7BIT) || \ + ((__VALUE__) == LL_I2C_OWNADDRESS1_10BIT)) +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup I2C_LL_Exported_Functions + * @{ + */ + +/** @addtogroup I2C_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize the I2C registers to their default reset values. + * @param I2Cx I2C Instance. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: I2C registers are de-initialized + * - ERROR: I2C registers are not de-initialized + */ +ErrorStatus LL_I2C_DeInit(const I2C_TypeDef *I2Cx) +{ + ErrorStatus status = SUCCESS; + + /* Check the I2C Instance I2Cx */ + assert_param(IS_I2C_ALL_INSTANCE(I2Cx)); + + if (I2Cx == I2C3) + { + /* Force reset of I2C clock */ + LL_APB7_GRP1_ForceReset(LL_APB7_GRP1_PERIPH_I2C3); + + /* Release reset of I2C clock */ + LL_APB7_GRP1_ReleaseReset(LL_APB7_GRP1_PERIPH_I2C3); + } +#if defined(I2C1) + else if (I2Cx == I2C1) + { + /* Force reset of I2C clock */ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C1); + + /* Release reset of I2C clock */ + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C1); + } +#endif /* I2C1 */ + else + { + status = ERROR; + } + + return status; +} + +/** + * @brief Initialize the I2C registers according to the specified parameters in I2C_InitStruct. + * @param I2Cx I2C Instance. + * @param I2C_InitStruct pointer to a @ref LL_I2C_InitTypeDef structure. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: I2C registers are initialized + * - ERROR: Not applicable + */ +ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, const LL_I2C_InitTypeDef *I2C_InitStruct) +{ + /* Check the I2C Instance I2Cx */ + assert_param(IS_I2C_ALL_INSTANCE(I2Cx)); + + /* Check the I2C parameters from I2C_InitStruct */ + assert_param(IS_LL_I2C_PERIPHERAL_MODE(I2C_InitStruct->PeripheralMode)); + assert_param(IS_LL_I2C_ANALOG_FILTER(I2C_InitStruct->AnalogFilter)); + assert_param(IS_LL_I2C_DIGITAL_FILTER(I2C_InitStruct->DigitalFilter)); + assert_param(IS_LL_I2C_OWN_ADDRESS1(I2C_InitStruct->OwnAddress1)); + assert_param(IS_LL_I2C_TYPE_ACKNOWLEDGE(I2C_InitStruct->TypeAcknowledge)); + assert_param(IS_LL_I2C_OWN_ADDRSIZE(I2C_InitStruct->OwnAddrSize)); + + /* Disable the selected I2Cx Peripheral */ + LL_I2C_Disable(I2Cx); + + /*---------------------------- I2Cx CR1 Configuration ------------------------ + * Configure the analog and digital noise filters with parameters : + * - AnalogFilter: I2C_CR1_ANFOFF bit + * - DigitalFilter: I2C_CR1_DNF[3:0] bits + */ + LL_I2C_ConfigFilters(I2Cx, I2C_InitStruct->AnalogFilter, I2C_InitStruct->DigitalFilter); + + /*---------------------------- I2Cx TIMINGR Configuration -------------------- + * Configure the SDA setup, hold time and the SCL high, low period with parameter : + * - Timing: I2C_TIMINGR_PRESC[3:0], I2C_TIMINGR_SCLDEL[3:0], I2C_TIMINGR_SDADEL[3:0], + * I2C_TIMINGR_SCLH[7:0] and I2C_TIMINGR_SCLL[7:0] bits + */ + LL_I2C_SetTiming(I2Cx, I2C_InitStruct->Timing); + + /* Enable the selected I2Cx Peripheral */ + LL_I2C_Enable(I2Cx); + + /*---------------------------- I2Cx OAR1 Configuration ----------------------- + * Disable, Configure and Enable I2Cx device own address 1 with parameters : + * - OwnAddress1: I2C_OAR1_OA1[9:0] bits + * - OwnAddrSize: I2C_OAR1_OA1MODE bit + */ + LL_I2C_DisableOwnAddress1(I2Cx); + LL_I2C_SetOwnAddress1(I2Cx, I2C_InitStruct->OwnAddress1, I2C_InitStruct->OwnAddrSize); + + /* OwnAdress1 == 0 is reserved for General Call address */ + if (I2C_InitStruct->OwnAddress1 != 0U) + { + LL_I2C_EnableOwnAddress1(I2Cx); + } + + /*---------------------------- I2Cx MODE Configuration ----------------------- + * Configure I2Cx peripheral mode with parameter : + * - PeripheralMode: I2C_CR1_SMBDEN and I2C_CR1_SMBHEN bits + */ + LL_I2C_SetMode(I2Cx, I2C_InitStruct->PeripheralMode); + + /*---------------------------- I2Cx CR2 Configuration ------------------------ + * Configure the ACKnowledge or Non ACKnowledge condition + * after the address receive match code or next received byte with parameter : + * - TypeAcknowledge: I2C_CR2_NACK bit + */ + LL_I2C_AcknowledgeNextData(I2Cx, I2C_InitStruct->TypeAcknowledge); + + return SUCCESS; +} + +/** + * @brief Set each @ref LL_I2C_InitTypeDef field to default value. + * @param I2C_InitStruct Pointer to a @ref LL_I2C_InitTypeDef structure. + * @retval None + */ +void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct) +{ + /* Set I2C_InitStruct fields to default values */ + I2C_InitStruct->PeripheralMode = LL_I2C_MODE_I2C; + I2C_InitStruct->Timing = 0U; + I2C_InitStruct->AnalogFilter = LL_I2C_ANALOGFILTER_ENABLE; + I2C_InitStruct->DigitalFilter = 0U; + I2C_InitStruct->OwnAddress1 = 0U; + I2C_InitStruct->TypeAcknowledge = LL_I2C_NACK; + I2C_InitStruct->OwnAddrSize = LL_I2C_OWNADDRESS1_7BIT; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* I2C1 || I2C3 */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_icache.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_icache.c new file mode 100644 index 0000000000..70c30f611f --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_icache.c @@ -0,0 +1,139 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_ll_icache.c + * @author MCD Application Team + * @brief ICACHE LL module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_ll_icache.h" +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +/** @addtogroup STM32WBAxx_LL_Driver + * @{ + */ + +#if defined(ICACHE) + +/** @defgroup ICACHE_LL ICACHE + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup ICACHE_LL_Private_Macros ICACHE Private Macros + * @{ + */ + +#define IS_LL_ICACHE_REGION(__VALUE__) (((__VALUE__) == LL_ICACHE_REGION_0) || \ + ((__VALUE__) == LL_ICACHE_REGION_1) || \ + ((__VALUE__) == LL_ICACHE_REGION_2) || \ + ((__VALUE__) == LL_ICACHE_REGION_3)) + +#define IS_LL_ICACHE_REGION_SIZE(__VALUE__) (((__VALUE__) == LL_ICACHE_REGIONSIZE_2MB) || \ + ((__VALUE__) == LL_ICACHE_REGIONSIZE_4MB) || \ + ((__VALUE__) == LL_ICACHE_REGIONSIZE_8MB) || \ + ((__VALUE__) == LL_ICACHE_REGIONSIZE_16MB) || \ + ((__VALUE__) == LL_ICACHE_REGIONSIZE_32MB) || \ + ((__VALUE__) == LL_ICACHE_REGIONSIZE_64MB) || \ + ((__VALUE__) == LL_ICACHE_REGIONSIZE_128MB)) + +#define IS_LL_ICACHE_MASTER_PORT(__VALUE__) (((__VALUE__) == LL_ICACHE_MASTER1_PORT) || \ + ((__VALUE__) == LL_ICACHE_MASTER2_PORT)) + +#define IS_LL_ICACHE_OUTPUT_BURST(__VALUE__) (((__VALUE__) == LL_ICACHE_OUTPUT_BURST_WRAP) || \ + ((__VALUE__) == LL_ICACHE_OUTPUT_BURST_INCR)) + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup ICACHE_LL_Exported_Functions + * @{ + */ + +/** @addtogroup ICACHE_LL_EF_REGION_Init + * @{ + */ + +/** + * @brief Configure and enable the memory remapped region. + * @note The Instruction Cache and corresponding region must be disabled. + * @param Region This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGION_0 + * @arg @ref LL_ICACHE_REGION_1 + * @arg @ref LL_ICACHE_REGION_2 + * @arg @ref LL_ICACHE_REGION_3 + * @param pICACHE_RegionStruct pointer to a @ref LL_ICACHE_RegionTypeDef structure. + * @retval None + */ +void LL_ICACHE_ConfigRegion(uint32_t Region, const LL_ICACHE_RegionTypeDef *const pICACHE_RegionStruct) +{ + __IO uint32_t *p_reg; + uint32_t value; + + /* Check the parameters */ + assert_param(IS_LL_ICACHE_REGION(Region)); + assert_param(IS_LL_ICACHE_REGION_SIZE(pICACHE_RegionStruct->Size)); + assert_param(IS_LL_ICACHE_MASTER_PORT(pICACHE_RegionStruct->TrafficRoute)); + assert_param(IS_LL_ICACHE_OUTPUT_BURST(pICACHE_RegionStruct->OutputBurstType)); + + /* Get region control register address */ + p_reg = &(ICACHE->CRR0) + (1U * Region); + + /* Region 2MB: BaseAddress size 8 bits, RemapAddress size 11 bits */ + /* Region 4MB: BaseAddress size 7 bits, RemapAddress size 10 bits */ + /* Region 8MB: BaseAddress size 6 bits, RemapAddress size 9 bits */ + /* Region 16MB: BaseAddress size 5 bits, RemapAddress size 8 bits */ + /* Region 32MB: BaseAddress size 4 bits, RemapAddress size 7 bits */ + /* Region 64MB: BaseAddress size 3 bits, RemapAddress size 6 bits */ + /* Region 128MB: BaseAddress size 2 bits, RemapAddress size 5 bits */ + value = ((pICACHE_RegionStruct->BaseAddress & 0x1FFFFFFFU) >> 21U) & \ + (0xFFU & ~(pICACHE_RegionStruct->Size - 1U)); + value |= ((pICACHE_RegionStruct->RemapAddress >> 5U) & \ + ((uint32_t)(0x7FFU & ~(pICACHE_RegionStruct->Size - 1U)) << ICACHE_CRRx_REMAPADDR_Pos)); + value |= (pICACHE_RegionStruct->Size << ICACHE_CRRx_RSIZE_Pos) | pICACHE_RegionStruct->TrafficRoute | \ + pICACHE_RegionStruct->OutputBurstType; + *p_reg = (value | ICACHE_CRRx_REN); /* Configure and enable region */ +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* ICACHE */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_lptim.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_lptim.c new file mode 100644 index 0000000000..2ef152c1c2 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_lptim.c @@ -0,0 +1,193 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_ll_lptim.c + * @author MCD Application Team + * @brief LPTIM LL module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_ll_lptim.h" +#include "stm32wbaxx_ll_bus.h" +#include "stm32wbaxx_ll_rcc.h" + + +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +/** @addtogroup STM32WBAxx_LL_Driver + * @{ + */ + +#if defined (LPTIM1) || defined (LPTIM2) + +/** @addtogroup LPTIM_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup LPTIM_LL_Private_Macros + * @{ + */ +#define IS_LL_LPTIM_CLOCK_SOURCE(__VALUE__) (((__VALUE__) == LL_LPTIM_CLK_SOURCE_INTERNAL) \ + || ((__VALUE__) == LL_LPTIM_CLK_SOURCE_EXTERNAL)) + +#define IS_LL_LPTIM_CLOCK_PRESCALER(__VALUE__) (((__VALUE__) == LL_LPTIM_PRESCALER_DIV1) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV2) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV4) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV8) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV16) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV32) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV64) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV128)) + +#define IS_LL_LPTIM_WAVEFORM(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_PWM) \ + || ((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_SETONCE)) + +/** + * @} + */ + + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/** @defgroup LPTIM_Private_Functions LPTIM Private Functions + * @{ + */ +/** + * @} + */ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup LPTIM_LL_Exported_Functions + * @{ + */ + +/** @addtogroup LPTIM_LL_EF_Init + * @{ + */ + +/** + * @brief Set LPTIMx registers to their reset values. + * @param LPTIMx LP Timer instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: LPTIMx registers are de-initialized + * - ERROR: invalid LPTIMx instance + */ +ErrorStatus LL_LPTIM_DeInit(const LPTIM_TypeDef *LPTIMx) +{ + ErrorStatus result = SUCCESS; + + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(LPTIMx)); + + if (LPTIMx == LPTIM1) + { + LL_APB7_GRP1_ForceReset(LL_APB7_GRP1_PERIPH_LPTIM1); + LL_APB7_GRP1_ReleaseReset(LL_APB7_GRP1_PERIPH_LPTIM1); + } +#if defined(LPTIM2) + else if (LPTIMx == LPTIM2) + { + LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_LPTIM2); + LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_LPTIM2); + } +#endif /* LPTIM2 */ + else + { + result = ERROR; + } + + return result; +} + +/** + * @brief Set each fields of the LPTIM_InitStruct structure to its default + * value. + * @param LPTIM_InitStruct pointer to a @ref LL_LPTIM_InitTypeDef structure + * @retval None + */ +void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct) +{ + /* Set the default configuration */ + LPTIM_InitStruct->ClockSource = LL_LPTIM_CLK_SOURCE_INTERNAL; + LPTIM_InitStruct->Prescaler = LL_LPTIM_PRESCALER_DIV1; + LPTIM_InitStruct->Waveform = LL_LPTIM_OUTPUT_WAVEFORM_PWM; +} + +/** + * @brief Configure the LPTIMx peripheral according to the specified parameters. + * @note LL_LPTIM_Init can only be called when the LPTIM instance is disabled. + * @note LPTIMx can be disabled using unitary function @ref LL_LPTIM_Disable(). + * @param LPTIMx LP Timer Instance + * @param LPTIM_InitStruct pointer to a @ref LL_LPTIM_InitTypeDef structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: LPTIMx instance has been initialized + * - ERROR: LPTIMx instance hasn't been initialized + */ +ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, const LL_LPTIM_InitTypeDef *LPTIM_InitStruct) +{ + ErrorStatus result = SUCCESS; + /* Check the parameters */ + assert_param(IS_LPTIM_INSTANCE(LPTIMx)); + assert_param(IS_LL_LPTIM_CLOCK_SOURCE(LPTIM_InitStruct->ClockSource)); + assert_param(IS_LL_LPTIM_CLOCK_PRESCALER(LPTIM_InitStruct->Prescaler)); + assert_param(IS_LL_LPTIM_WAVEFORM(LPTIM_InitStruct->Waveform)); + + /* The LPTIMx_CFGR register must only be modified when the LPTIM is disabled + (ENABLE bit is reset to 0). + */ + if (LL_LPTIM_IsEnabled(LPTIMx) == 1UL) + { + result = ERROR; + } + else + { + /* Set CKSEL bitfield according to ClockSource value */ + /* Set PRESC bitfield according to Prescaler value */ + /* Set WAVE bitfield according to Waveform value */ + MODIFY_REG(LPTIMx->CFGR, + (LPTIM_CFGR_CKSEL | LPTIM_CFGR_PRESC | LPTIM_CFGR_WAVE), + LPTIM_InitStruct->ClockSource | \ + LPTIM_InitStruct->Prescaler | \ + LPTIM_InitStruct->Waveform); + } + + return result; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* LPTIM1 || LPTIM2 */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_lpuart.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_lpuart.c new file mode 100644 index 0000000000..f871dec901 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_lpuart.c @@ -0,0 +1,285 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_ll_lpuart.c + * @author MCD Application Team + * @brief LPUART LL module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_ll_lpuart.h" +#include "stm32wbaxx_ll_rcc.h" +#include "stm32wbaxx_ll_bus.h" +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +/** @addtogroup STM32WBAxx_LL_Driver + * @{ + */ + +#if defined (LPUART1) + +/** @addtogroup LPUART_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup LPUART_LL_Private_Constants + * @{ + */ + +/* Definition of default baudrate value used for LPUART initialisation */ +#define LPUART_DEFAULT_BAUDRATE (9600U) + +/** + * @} + */ + + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup LPUART_LL_Private_Macros + * @{ + */ + +/* Check of parameters for configuration of LPUART registers */ + +#define IS_LL_LPUART_PRESCALER(__VALUE__) (((__VALUE__) == LL_LPUART_PRESCALER_DIV1) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV2) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV4) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV6) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV8) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV10) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV12) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV16) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV32) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV64) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV128) \ + || ((__VALUE__) == LL_LPUART_PRESCALER_DIV256)) + +/* __BAUDRATE__ Depending on constraints applicable for LPUART BRR register */ +/* value : */ +/* - fck must be in the range [3 x baudrate, 4096 x baudrate] */ +/* - LPUART_BRR register value should be >= 0x300 */ +/* - LPUART_BRR register value should be <= 0xFFFFF (20 bits) */ +/* Baudrate specified by the user should belong to [8, 33000000].*/ +#define IS_LL_LPUART_BAUDRATE(__BAUDRATE__) (((__BAUDRATE__) <= 33000000U) && ((__BAUDRATE__) >= 8U)) + +/* __VALUE__ BRR content must be greater than or equal to 0x300. */ +#define IS_LL_LPUART_BRR_MIN(__VALUE__) ((__VALUE__) >= 0x300U) + +/* __VALUE__ BRR content must be lower than or equal to 0xFFFFF. */ +#define IS_LL_LPUART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x000FFFFFU) + +#define IS_LL_LPUART_DIRECTION(__VALUE__) (((__VALUE__) == LL_LPUART_DIRECTION_NONE) \ + || ((__VALUE__) == LL_LPUART_DIRECTION_RX) \ + || ((__VALUE__) == LL_LPUART_DIRECTION_TX) \ + || ((__VALUE__) == LL_LPUART_DIRECTION_TX_RX)) + +#define IS_LL_LPUART_PARITY(__VALUE__) (((__VALUE__) == LL_LPUART_PARITY_NONE) \ + || ((__VALUE__) == LL_LPUART_PARITY_EVEN) \ + || ((__VALUE__) == LL_LPUART_PARITY_ODD)) + +#define IS_LL_LPUART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_LPUART_DATAWIDTH_7B) \ + || ((__VALUE__) == LL_LPUART_DATAWIDTH_8B) \ + || ((__VALUE__) == LL_LPUART_DATAWIDTH_9B)) + +#define IS_LL_LPUART_STOPBITS(__VALUE__) (((__VALUE__) == LL_LPUART_STOPBITS_1) \ + || ((__VALUE__) == LL_LPUART_STOPBITS_2)) + +#define IS_LL_LPUART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_LPUART_HWCONTROL_NONE) \ + || ((__VALUE__) == LL_LPUART_HWCONTROL_RTS) \ + || ((__VALUE__) == LL_LPUART_HWCONTROL_CTS) \ + || ((__VALUE__) == LL_LPUART_HWCONTROL_RTS_CTS)) + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup LPUART_LL_Exported_Functions + * @{ + */ + +/** @addtogroup LPUART_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize LPUART registers (Registers restored to their default values). + * @param LPUARTx LPUART Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: LPUART registers are de-initialized + * - ERROR: not applicable + */ +ErrorStatus LL_LPUART_DeInit(const USART_TypeDef *LPUARTx) +{ + ErrorStatus status = SUCCESS; + + /* Check the parameters */ + assert_param(IS_LPUART_INSTANCE(LPUARTx)); + + if (LPUARTx == LPUART1) + { + /* Force reset of LPUART peripheral */ + LL_APB7_GRP1_ForceReset(LL_APB7_GRP1_PERIPH_LPUART1); + + /* Release reset of LPUART peripheral */ + LL_APB7_GRP1_ReleaseReset(LL_APB7_GRP1_PERIPH_LPUART1); + } + else + { + status = ERROR; + } + + return (status); +} + +/** + * @brief Initialize LPUART registers according to the specified + * parameters in LPUART_InitStruct. + * @note As some bits in LPUART configuration registers can only be written when + * the LPUART is disabled (USART_CR1_UE bit =0), + * LPUART Peripheral should be in disabled state prior calling this function. + * Otherwise, ERROR result will be returned. + * @note Baud rate value stored in LPUART_InitStruct BaudRate field, should be valid (different from 0). + * @param LPUARTx LPUART Instance + * @param LPUART_InitStruct pointer to a @ref LL_LPUART_InitTypeDef structure + * that contains the configuration information for the specified LPUART peripheral. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: LPUART registers are initialized according to LPUART_InitStruct content + * - ERROR: Problem occurred during LPUART Registers initialization + */ +ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, const LL_LPUART_InitTypeDef *LPUART_InitStruct) +{ + ErrorStatus status = ERROR; + uint32_t periphclk; + + /* Check the parameters */ + assert_param(IS_LPUART_INSTANCE(LPUARTx)); + assert_param(IS_LL_LPUART_PRESCALER(LPUART_InitStruct->PrescalerValue)); + assert_param(IS_LL_LPUART_BAUDRATE(LPUART_InitStruct->BaudRate)); + assert_param(IS_LL_LPUART_DATAWIDTH(LPUART_InitStruct->DataWidth)); + assert_param(IS_LL_LPUART_STOPBITS(LPUART_InitStruct->StopBits)); + assert_param(IS_LL_LPUART_PARITY(LPUART_InitStruct->Parity)); + assert_param(IS_LL_LPUART_DIRECTION(LPUART_InitStruct->TransferDirection)); + assert_param(IS_LL_LPUART_HWCONTROL(LPUART_InitStruct->HardwareFlowControl)); + + /* LPUART needs to be in disabled state, in order to be able to configure some bits in + CRx registers. Otherwise (LPUART not in Disabled state) => return ERROR */ + if (LL_LPUART_IsEnabled(LPUARTx) == 0U) + { + /*---------------------------- LPUART CR1 Configuration ----------------------- + * Configure LPUARTx CR1 (LPUART Word Length, Parity and Transfer Direction bits) with parameters: + * - DataWidth: USART_CR1_M bits according to LPUART_InitStruct->DataWidth value + * - Parity: USART_CR1_PCE, USART_CR1_PS bits according to LPUART_InitStruct->Parity value + * - TransferDirection: USART_CR1_TE, USART_CR1_RE bits according to LPUART_InitStruct->TransferDirection value + */ + MODIFY_REG(LPUARTx->CR1, + (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE), + (LPUART_InitStruct->DataWidth | LPUART_InitStruct->Parity | LPUART_InitStruct->TransferDirection)); + + /*---------------------------- LPUART CR2 Configuration ----------------------- + * Configure LPUARTx CR2 (Stop bits) with parameters: + * - Stop Bits: USART_CR2_STOP bits according to LPUART_InitStruct->StopBits value. + */ + LL_LPUART_SetStopBitsLength(LPUARTx, LPUART_InitStruct->StopBits); + + /*---------------------------- LPUART CR3 Configuration ----------------------- + * Configure LPUARTx CR3 (Hardware Flow Control) with parameters: + * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according + * to LPUART_InitStruct->HardwareFlowControl value. + */ + LL_LPUART_SetHWFlowCtrl(LPUARTx, LPUART_InitStruct->HardwareFlowControl); + + /*---------------------------- LPUART BRR Configuration ----------------------- + * Retrieve Clock frequency used for LPUART Peripheral + */ + periphclk = LL_RCC_GetLPUARTClockFreq(LL_RCC_LPUART1_CLKSOURCE); + + /* Configure the LPUART Baud Rate : + - prescaler value is required + - valid baud rate value (different from 0) is required + - Peripheral clock as returned by RCC service, should be valid (different from 0). + */ + if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO) + && (LPUART_InitStruct->BaudRate != 0U)) + { + status = SUCCESS; + LL_LPUART_SetBaudRate(LPUARTx, + periphclk, + LPUART_InitStruct->PrescalerValue, + LPUART_InitStruct->BaudRate); + + /* Check BRR is greater than or equal to 0x300 */ + assert_param(IS_LL_LPUART_BRR_MIN(LPUARTx->BRR)); + + /* Check BRR is lower than or equal to 0xFFFFF */ + assert_param(IS_LL_LPUART_BRR_MAX(LPUARTx->BRR)); + } + + /*---------------------------- LPUART PRESC Configuration ----------------------- + * Configure LPUARTx PRESC (Prescaler) with parameters: + * - PrescalerValue: LPUART_PRESC_PRESCALER bits according to LPUART_InitStruct->PrescalerValue value. + */ + LL_LPUART_SetPrescaler(LPUARTx, LPUART_InitStruct->PrescalerValue); + } + + return (status); +} + +/** + * @brief Set each @ref LL_LPUART_InitTypeDef field to default value. + * @param LPUART_InitStruct pointer to a @ref LL_LPUART_InitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ + +void LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct) +{ + /* Set LPUART_InitStruct fields to default values */ + LPUART_InitStruct->PrescalerValue = LL_LPUART_PRESCALER_DIV1; + LPUART_InitStruct->BaudRate = LPUART_DEFAULT_BAUDRATE; + LPUART_InitStruct->DataWidth = LL_LPUART_DATAWIDTH_8B; + LPUART_InitStruct->StopBits = LL_LPUART_STOPBITS_1; + LPUART_InitStruct->Parity = LL_LPUART_PARITY_NONE ; + LPUART_InitStruct->TransferDirection = LL_LPUART_DIRECTION_TX_RX; + LPUART_InitStruct->HardwareFlowControl = LL_LPUART_HWCONTROL_NONE; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* LPUART1 */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_pka.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_pka.c new file mode 100644 index 0000000000..62476ef9d6 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_pka.c @@ -0,0 +1,163 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_ll_pka.c + * @author MCD Application Team + * @brief PKA LL module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_ll_pka.h" +#include "stm32wbaxx_ll_bus.h" + +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +/** @addtogroup STM32WBAxx_LL_Driver + * @{ + */ + +#if defined(PKA) + +/** @addtogroup PKA_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup PKA_LL_Private_Macros PKA Private Constants + * @{ + */ +#define IS_LL_PKA_MODE(__VALUE__) (((__VALUE__)== LL_PKA_MODE_MODULAR_EXP) ||\ + ((__VALUE__) == LL_PKA_MODE_MONTGOMERY_PARAM) ||\ + ((__VALUE__) == LL_PKA_MODE_MODULAR_EXP_FAST) ||\ + ((__VALUE__) == LL_PKA_MODE_MODULAR_EXP_PROTECT) ||\ + ((__VALUE__) == LL_PKA_MODE_ECC_MUL) ||\ + ((__VALUE__) == LL_PKA_MODE_ECC_COMPLETE_ADD) ||\ + ((__VALUE__) == LL_PKA_MODE_ECDSA_SIGNATURE) ||\ + ((__VALUE__) == LL_PKA_MODE_ECDSA_VERIFICATION) ||\ + ((__VALUE__) == LL_PKA_MODE_POINT_CHECK) ||\ + ((__VALUE__) == LL_PKA_MODE_RSA_CRT_EXP) ||\ + ((__VALUE__) == LL_PKA_MODE_MODULAR_INV) ||\ + ((__VALUE__) == LL_PKA_MODE_ARITHMETIC_ADD) ||\ + ((__VALUE__) == LL_PKA_MODE_ARITHMETIC_SUB) ||\ + ((__VALUE__) == LL_PKA_MODE_ARITHMETIC_MUL) ||\ + ((__VALUE__) == LL_PKA_MODE_COMPARISON) ||\ + ((__VALUE__) == LL_PKA_MODE_MODULAR_REDUC) ||\ + ((__VALUE__) == LL_PKA_MODE_MODULAR_ADD) ||\ + ((__VALUE__) == LL_PKA_MODE_MODULAR_SUB) ||\ + ((__VALUE__) == LL_PKA_MODE_MONTGOMERY_MUL) ||\ + ((__VALUE__) == LL_PKA_MODE_DOUBLE_BASE_LADDER) ||\ + ((__VALUE__) == LL_PKA_MODE_ECC_PROJECTIVE_AFF)) +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup PKA_LL_Exported_Functions + * @{ + */ + +/** @addtogroup PKA_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize PKA registers (Registers restored to their default values). + * @param PKAx PKA Instance. + * @retval ErrorStatus + * - SUCCESS: PKA registers are de-initialized + * - ERROR: PKA registers are not de-initialized + */ +ErrorStatus LL_PKA_DeInit(const PKA_TypeDef *PKAx) +{ + ErrorStatus status = SUCCESS; + + /* Check the parameters */ + assert_param(IS_PKA_ALL_INSTANCE(PKAx)); + + if (PKAx == PKA) + { + /* Force PKA reset */ + LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_PKA); + + /* Release PKA reset */ + LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_PKA); + } + else + { + status = ERROR; + } + + return (status); +} + +/** + * @brief Initialize PKA registers according to the specified parameters in PKA_InitStruct. + * @param PKAx PKA Instance. + * @param PKA_InitStruct pointer to a @ref LL_PKA_InitTypeDef structure + * that contains the configuration information for the specified PKA peripheral. + * @retval ErrorStatus + * - SUCCESS: PKA registers are initialized according to PKA_InitStruct content + * - ERROR: Not applicable + */ +ErrorStatus LL_PKA_Init(PKA_TypeDef *PKAx, LL_PKA_InitTypeDef *PKA_InitStruct) +{ + assert_param(IS_PKA_ALL_INSTANCE(PKAx)); + assert_param(IS_LL_PKA_MODE(PKA_InitStruct->Mode)); + + LL_PKA_Config(PKAx, PKA_InitStruct->Mode); + + return (SUCCESS); +} + +/** + * @brief Set each @ref LL_PKA_InitTypeDef field to default value. + * @param PKA_InitStruct pointer to a @ref LL_PKA_InitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ + +void LL_PKA_StructInit(LL_PKA_InitTypeDef *PKA_InitStruct) +{ + /* Reset PKA init structure parameters values */ + PKA_InitStruct->Mode = LL_PKA_MODE_MODULAR_EXP; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (PKA) */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_pwr.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_pwr.c new file mode 100644 index 0000000000..00af734f9d --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_pwr.c @@ -0,0 +1,93 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_ll_pwr.c + * @author MCD Application Team + * @brief PWR LL module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#if defined (USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_ll_pwr.h" + +/** @addtogroup STM32WBAxx_LL_Driver + * @{ + */ + +#if defined (PWR) + +/** @defgroup PWR_LL PWR + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup PWR_LL_Exported_Functions + * @{ + */ + +/** @addtogroup PWR_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize the PWR registers to their default reset values. + * @retval An ErrorStatus enumeration value: + * - SUCCESS : PWR registers are de-initialized. + * - ERROR : not applicable. + */ +ErrorStatus LL_PWR_DeInit(void) +{ + /* Clear PWR low power flags */ + LL_PWR_ClearFlag_STOP(); + + /* Clear PWR wake up flags */ + LL_PWR_ClearFlag_WU(); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + /* Reset privilege attribute for nsecure attribute */ + LL_PWR_DisableNSecurePrivilege(); + + /* Reset privilege attribute for nsecure attribute */ + LL_PWR_DisableSecurePrivilege(); + + /* Reset secure attribute */ + LL_PWR_ConfigSecure(0); +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + return SUCCESS; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* defined(PWR) */ +/** + * @} + */ + +#endif /* defined (USE_FULL_LL_DRIVER) */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_rcc.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_rcc.c new file mode 100644 index 0000000000..49addc56d6 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_rcc.c @@ -0,0 +1,1035 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_ll_rcc.c + * @author MCD Application Team + * @brief RCC LL module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 20223 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_ll_rcc.h" +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif +/** @addtogroup STM32WBAxx_LL_Driver + * @{ + */ + +#if defined(RCC) + +/** @addtogroup RCC_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup RCC_LL_Private_Macros + * @{ + */ +#if defined(USART2) +#define IS_LL_RCC_USART2_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) +#else +#define IS_LL_RCC_USART2_CLKSOURCE(__VALUE__) (0) +#endif + +#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \ + || IS_LL_RCC_USART2_CLKSOURCE(__VALUE__)) + +#if defined(I2C1) +#define IS_LL_RCC_I2C1_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) +#else +#define IS_LL_RCC_I2C1_CLKSOURCE(__VALUE__) (0) +#endif + +#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C3_CLKSOURCE) \ + || IS_LL_RCC_I2C1_CLKSOURCE(__VALUE__)) + +#if defined(SPI1) +#define IS_LL_RCC_SPI1_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_SPI1_CLKSOURCE) +#else +#define IS_LL_RCC_SPI1_CLKSOURCE(__VALUE__) (0) +#endif + +#define IS_LL_RCC_SPI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SPI3_CLKSOURCE) \ + || IS_LL_RCC_SPI1_CLKSOURCE(__VALUE__)) + +#if defined(LPTIM2) +#define IS_LL_RCC_LPTIM2_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_LPTIM2_CLKSOURCE) +#else +#define IS_LL_RCC_LPTIM2_CLKSOURCE(__VALUE__) (0) +#endif + +#define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE) \ + || IS_LL_RCC_LPTIM2_CLKSOURCE(__VALUE__)) + +#define IS_LL_RCC_LPUART_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_LPUART1_CLKSOURCE) + +#if defined(SAI1) +#define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) +#endif /* SAI1 */ + +#define IS_LL_RCC_RNG_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_RNG_CLKSOURCE) + +#define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_ADC_CLKSOURCE) + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup RCC_LL_Private_Functions RCC Private functions + * @{ + */ +uint32_t RCC_GetSystemClockFreq(void); +uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency); +uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency); +uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency); +uint32_t RCC_GetPCLK7ClockFreq(uint32_t HCLK_Frequency); +uint32_t RCC_PLL1R_GetFreqDomain(void); +uint32_t RCC_PLL1P_GetFreqDomain(void); +uint32_t RCC_PLL1Q_GetFreqDomain(void); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RCC_LL_Exported_Functions + * @{ + */ + +/** @addtogroup RCC_LL_EF_Init + * @{ + */ + +/** + * @brief Reset the RCC clock configuration to the default reset state. + * @note The default reset state of the clock configuration is given below: + * - MSI ON and used as system clock source + * - HSE, HSI, PLL1, PLL2 and PLL3 OFF + * - AHB, APB1, APB2 and APB3 prescaler set to 1. + * - CSS, MCO OFF + * - All interrupts disabled + * @note This function doesn't modify the configuration of the + * - Peripheral clocks + * - LSI, LSE and RTC clocks + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RCC registers are de-initialized + * - ERROR: not applicable + */ +ErrorStatus LL_RCC_DeInit(void) +{ + uint32_t vl_mask; + + /* Set HSION bit */ + LL_RCC_HSI_Enable(); + + /* Insure HSIRDY bit is set */ + while (LL_RCC_HSI_IsReady() == 0U) + { + } + + /* Set HSITRIM bits to the reset value*/ + LL_RCC_HSI_SetCalibTrimming(0x20U); + + /* Reset CFGR register */ + LL_RCC_WriteReg(CFGR1, 0x00000000U); + LL_RCC_WriteReg(CFGR2, 0x00000000U); + + while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI) + { + } + + /* Read CR register */ + vl_mask = LL_RCC_ReadReg(CR); + + /* Reset HSION, HSIKERON, HSEON and PLL1ON bits */ + CLEAR_BIT(vl_mask, (RCC_CR_HSION | RCC_CR_HSIKERON | RCC_CR_HSEON | RCC_CR_PLL1ON)); + + /* Write new mask in CR register */ + LL_RCC_WriteReg(CR, vl_mask); + + /* Wait for PLL1RDY, PLL2RDY and PLL3RDY bits to be reset */ + while (READ_BIT(RCC->CR, RCC_CR_PLL1RDY) != 0U) + { + } + + /* Reset PLL1CFGR register */ + LL_RCC_WriteReg(PLL1CFGR, 0x0U); + + /* Reset PLL1DIVR register */ + LL_RCC_WriteReg(PLL1DIVR, 0x01010280U); + + /* Disable all interrupts */ + LL_RCC_WriteReg(CIER, 0x00000000U); + + /* Clear all interrupt flags */ +#if defined(RCC_LSI2_SUPPORT) + vl_mask = RCC_CICR_LSI1RDYC | RCC_CICR_LSI2RDYC | RCC_CICR_LSERDYC | RCC_CICR_HSIRDYC | \ + RCC_CICR_HSERDYC | RCC_CICR_PLL1RDYC | RCC_CICR_HSECSSC; +#else + vl_mask = RCC_CICR_LSI1RDYC | RCC_CICR_LSERDYC | RCC_CICR_HSIRDYC | \ + RCC_CICR_HSERDYC | RCC_CICR_PLL1RDYC | RCC_CICR_HSECSSC; +#endif + LL_RCC_WriteReg(CICR, vl_mask); + + /* Clear reset flags */ + LL_RCC_ClearResetFlags(); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + /* Reset secure configuration */ + LL_RCC_ConfigSecure(LL_RCC_ALL_NSEC); +#endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */ + + return SUCCESS; +} + +/** + * @} + */ + +/** @addtogroup RCC_LL_EF_Get_Freq + * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks + * and different peripheral clocks available on the device. + * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**) + * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***) + * @note If SYSCLK source is PLL1, function returns values based on HSE_VALUE(***) + * or HSI_VALUE(**) multiplied/divided by the PLL1 factors. + * @note (**) HSI_VALUE is a constant defined in this file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * @note (***) HSE_VALUE is a constant defined in this file (default value + * 32 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * @note The result of this function could be incorrect when using fractional + * value for HSE crystal. + * @note This function can be used by the user application to compute the + * baud-rate for the communication peripherals or configure other parameters. + * @{ + */ + +/** + * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks + * @note Each time SYSCLK, HCLK and/or PCLK1, PCLK2 and/or PCLK7 clock changes, this function + * must be called to update structure fields. Otherwise, any + * configuration based on this function will be incorrect. + * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies + * @retval None + */ +void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks) +{ + /* Get SYSCLK frequency */ + RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq(); + + /* HCLK clock frequency */ + RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency); + + /* PCLK1 clock frequency */ + RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency); + + /* PCLK2 clock frequency */ + RCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency); + + /* PCLK7 clock frequency */ + RCC_Clocks->PCLK7_Frequency = RCC_GetPCLK7ClockFreq(RCC_Clocks->HCLK_Frequency); +} + +/** + * @brief Return USARTx clock frequency + * @param USARTxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_USART1_CLKSOURCE + * @arg @ref LL_RCC_USART2_CLKSOURCE + * @retval USART clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready + */ +uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource) +{ + uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource)); + + if (USARTxSource == LL_RCC_USART1_CLKSOURCE) + { + /* USART1CLK clock frequency */ + switch (LL_RCC_GetUSARTClockSource(USARTxSource)) + { + case LL_RCC_USART1_CLKSOURCE_SYSCLK: /* USART1 Clock is System Clock */ + usart_frequency = RCC_GetSystemClockFreq(); + break; + + case LL_RCC_USART1_CLKSOURCE_HSI: /* USART1 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady() != 0U) + { + usart_frequency = HSI_VALUE; + } + break; + + case LL_RCC_USART1_CLKSOURCE_LSE: /* USART1 Clock is LSE Osc. */ + if (LL_RCC_LSE_IsReady() != 0U) + { + usart_frequency = LSE_VALUE; + } + break; + + case LL_RCC_USART1_CLKSOURCE_PCLK2: /* USART1 Clock is PCLK2 */ + usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + break; + + default: + /* unreachable code */ + break; + } + } +#if defined(USART2) + else if (USARTxSource == LL_RCC_USART2_CLKSOURCE) + { + /* USART2CLK clock frequency */ + switch (LL_RCC_GetUSARTClockSource(USARTxSource)) + { + case LL_RCC_USART2_CLKSOURCE_SYSCLK: /* USART2 Clock is System Clock */ + usart_frequency = RCC_GetSystemClockFreq(); + break; + + case LL_RCC_USART2_CLKSOURCE_HSI: /* USART2 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady() != 0U) + { + usart_frequency = HSI_VALUE; + } + break; + + case LL_RCC_USART2_CLKSOURCE_LSE: /* USART2 Clock is LSE Osc. */ + if (LL_RCC_LSE_IsReady() != 0U) + { + usart_frequency = LSE_VALUE; + } + break; + + case LL_RCC_USART2_CLKSOURCE_PCLK1: /* USART2 Clock is PCLK1 */ + usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + break; + + default: + /* unreachable code */ + break; + } + } +#endif /* USART2 */ + else + { + /* nothing to do */ + } + + return usart_frequency; +} + +/** + * @brief Return SPIx clock frequency + * @param SPIxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_SPI1_CLKSOURCE + * @arg @ref LL_RCC_SPI3_CLKSOURCE + * @retval SPI clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI) is not ready + */ +uint32_t LL_RCC_GetSPIClockFreq(uint32_t SPIxSource) +{ + uint32_t SPI_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_SPI_CLKSOURCE(SPIxSource)); + + if (SPIxSource == LL_RCC_SPI3_CLKSOURCE) + { + /* SPI3 CLK clock frequency */ + switch (LL_RCC_GetSPIClockSource(SPIxSource)) + { + case LL_RCC_SPI3_CLKSOURCE_SYSCLK: /* SPI3 Clock is System Clock */ + SPI_frequency = RCC_GetSystemClockFreq(); + break; + + case LL_RCC_SPI3_CLKSOURCE_HSI: /* SPI3 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady() != 0U) + { + SPI_frequency = HSI_VALUE; + } + break; + + case LL_RCC_SPI3_CLKSOURCE_PCLK7: /* SPI3 Clock is PCLK7 */ + SPI_frequency = RCC_GetPCLK7ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + break; + + default: + /* unreachable code */ + break; + } + } +#if defined(SPI1) + else if (SPIxSource == LL_RCC_SPI1_CLKSOURCE) + { + /* SPI1 CLK clock frequency */ + switch (LL_RCC_GetSPIClockSource(SPIxSource)) + { + case LL_RCC_SPI1_CLKSOURCE_SYSCLK: /* SPI1 Clock is System Clock */ + SPI_frequency = RCC_GetSystemClockFreq(); + break; + + case LL_RCC_SPI1_CLKSOURCE_HSI: /* SPI1 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady() != 0U) + { + SPI_frequency = HSI_VALUE; + } + break; + + case LL_RCC_SPI1_CLKSOURCE_PCLK2: /* SPI1 Clock is PCLK2 */ + SPI_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + break; + + default: + /* unreachable code */ + break; + } + } +#endif /* SPI1 */ + else + { + /* nothing to do */ + } + + return SPI_frequency; +} + +/** + * @brief Return I2Cx clock frequency + * @param I2CxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_I2C1_CLKSOURCE + * @arg @ref LL_RCC_I2C3_CLKSOURCE + * @retval I2C clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI) is not ready + */ +uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource) +{ + uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource)); + + if (I2CxSource == LL_RCC_I2C3_CLKSOURCE) + { + /* I2C3 CLK clock frequency */ + switch (LL_RCC_GetI2CClockSource(I2CxSource)) + { + case LL_RCC_I2C3_CLKSOURCE_SYSCLK: /* I2C3 Clock is System Clock */ + i2c_frequency = RCC_GetSystemClockFreq(); + break; + + case LL_RCC_I2C3_CLKSOURCE_HSI: /* I2C3 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady() != 0U) + { + i2c_frequency = HSI_VALUE; + } + break; + + case LL_RCC_I2C3_CLKSOURCE_PCLK7: /* I2C3 Clock is PCLK7 */ + i2c_frequency = RCC_GetPCLK7ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + break; + + default: + /* unreachable code */ + break; + } + } +#if defined(I2C1) + else if (I2CxSource == LL_RCC_I2C1_CLKSOURCE) + { + /* I2C1 CLK clock frequency */ + switch (LL_RCC_GetI2CClockSource(I2CxSource)) + { + case LL_RCC_I2C1_CLKSOURCE_SYSCLK: /* I2C1 Clock is System Clock */ + i2c_frequency = RCC_GetSystemClockFreq(); + break; + + case LL_RCC_I2C1_CLKSOURCE_HSI: /* I2C1 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady() != 0U) + { + i2c_frequency = HSI_VALUE; + } + break; + + case LL_RCC_I2C1_CLKSOURCE_PCLK1: /* I2C1 Clock is PCLK1 */ + i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + break; + + default: + /* unreachable code */ + break; + } + } +#endif /* I2C1 */ + else + { + /* nothing to do */ + } + + return i2c_frequency; +} + +/** + * @brief Return LPUARTx clock frequency + * @param LPUARTxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_LPUART1_CLKSOURCE + * @retval LPUART clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready + */ +uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource) +{ + uint32_t lpuart_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_LPUART_CLKSOURCE(LPUARTxSource)); + + /* LPUART1CLK clock frequency */ + switch (LL_RCC_GetLPUARTClockSource(LPUARTxSource)) + { + case LL_RCC_LPUART1_CLKSOURCE_SYSCLK: /* LPUART1 Clock is System Clock */ + lpuart_frequency = RCC_GetSystemClockFreq(); + break; + + case LL_RCC_LPUART1_CLKSOURCE_HSI: /* LPUART1 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady() != 0U) + { + lpuart_frequency = HSI_VALUE; + } + break; + + case LL_RCC_LPUART1_CLKSOURCE_LSE: /* LPUART1 Clock is LSE Osc. */ + if (LL_RCC_LSE_IsReady() != 0U) + { + lpuart_frequency = LSE_VALUE; + } + break; + + case LL_RCC_LPUART1_CLKSOURCE_PCLK7: /* LPUART1 Clock is PCLK7 */ + lpuart_frequency = RCC_GetPCLK7ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + break; + + default: + /* unreachable code */ + break; + } + + return lpuart_frequency; +} + +/** + * @brief Return LPTIMx clock frequency + * @param LPTIMxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE + * @arg @ref LL_RCC_LPTIM2_CLKSOURCE + * @retval LPTIM clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI, LSI or LSE) is not ready + */ +uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource) +{ + uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMxSource)); + + if (LPTIMxSource == LL_RCC_LPTIM1_CLKSOURCE) + { + /* LPTIM1CLK clock frequency */ + switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource)) + { + case LL_RCC_LPTIM1_CLKSOURCE_LSI: /* LPTIM1 Clock is LSI Osc. */ +#if defined(RCC_LSI2_SUPPORT) + if ((RCC->BDCR1& (RCC_BDCR1_LSI1ON | RCC_BDCR1_LSI2ON)) != 0U) +#else + if (LL_RCC_LSI1_IsReady() != 0U) +#endif + { + lptim_frequency = LSI_VALUE; + } + break; + + case LL_RCC_LPTIM1_CLKSOURCE_HSI: /* LPTIM1 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady() != 0U) + { + lptim_frequency = HSI_VALUE; + } + break; + + case LL_RCC_LPTIM1_CLKSOURCE_LSE: /* LPTIM1 Clock is LSE Osc. */ + if (LL_RCC_LSE_IsReady() != 0U) + { + lptim_frequency = LSE_VALUE; + } + break; + + case LL_RCC_LPTIM1_CLKSOURCE_PCLK7: /* LPTIM1 Clock is PCLK7 */ + lptim_frequency = RCC_GetPCLK7ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + break; + + default: + /* unreachable code */ + break; + } + } +#if defined(LPTIM2) + else if (LPTIMxSource == LL_RCC_LPTIM2_CLKSOURCE) + { + /* LPTIM2CLK clock frequency */ + switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource)) + { + case LL_RCC_LPTIM2_CLKSOURCE_LSI: /* LPTIM2 Clock is LSI Osc. */ +#if defined(RCC_LSI2_SUPPORT) + if ((RCC->BDCR1& (RCC_BDCR1_LSI1ON | RCC_BDCR1_LSI2ON)) != 0U) +#else + if (LL_RCC_LSI1_IsReady() != 0U) +#endif + { + lptim_frequency = LSI_VALUE; + } + break; + + case LL_RCC_LPTIM2_CLKSOURCE_HSI: /* LPTIM2 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady() != 0U) + { + lptim_frequency = HSI_VALUE; + } + break; + + case LL_RCC_LPTIM2_CLKSOURCE_LSE: /* LPTIM2 Clock is LSE Osc. */ + if (LL_RCC_LSE_IsReady() != 0U) + { + lptim_frequency = LSE_VALUE; + } + break; + + case LL_RCC_LPTIM2_CLKSOURCE_PCLK1: /* LPTIM2 Clock is PCLK1 */ + lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + break; + + default: + /* unreachable code */ + break; + } + } +#endif /* LPTIM2 */ + else + { + /* nothing to do */ + } + + return lptim_frequency; +} + +#if defined(SAI1) +/** + * @brief Return SAIx clock frequency + * @param SAIxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_SAI1_CLKSOURCE + * @retval SAI clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that PLL1 is not ready + */ +uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource) +{ + uint32_t sai_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_SAI_CLKSOURCE(SAIxSource)); + + if (SAIxSource == LL_RCC_SAI1_CLKSOURCE) + { + /* SAI1CLK clock frequency */ + switch (LL_RCC_GetSAIClockSource(SAIxSource)) + { + case LL_RCC_SAI1_CLKSOURCE_PLL1P: /* PLL1P clock used as SAI1 clock source */ + if (LL_RCC_PLL1_IsReady() != 0U) + { + if (LL_RCC_PLL1_IsEnabledDomain_PLL1P() != 0U) + { + sai_frequency = RCC_PLL1P_GetFreqDomain(); + } + } + break; + + case LL_RCC_SAI1_CLKSOURCE_PLL1Q: /* PLL1Q clock used as SAI1 clock source */ + if (LL_RCC_PLL1_IsReady() != 0U) + { + if (LL_RCC_PLL1_IsEnabledDomain_PLL1Q() != 0U) + { + sai_frequency = RCC_PLL1Q_GetFreqDomain(); + } + } + break; + + case LL_RCC_SAI1_CLKSOURCE_SYSCLK: /* System clock used as SAI1 clock source */ + sai_frequency = RCC_GetSystemClockFreq(); + break; + + case LL_RCC_SAI1_CLKSOURCE_PIN: /* External input clock used as SAI1 clock source */ + sai_frequency = EXTERNAL_SAI1_CLOCK_VALUE; + break; + + case LL_RCC_SAI1_CLKSOURCE_HSI: /* SAI Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady() != 0U) + { + sai_frequency = HSI_VALUE; + } + break; + + default: + /* unreachable code */ + break; + } + } + else + { + /* nothing to do */ + } + + return sai_frequency; +} +#endif /* SAI1 */ + +/** + * @brief Return RNGx clock frequency + * @param RNGxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_RNG_CLKSOURCE + * @retval RNG clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (MSI or HSI48) or PLL1 is not ready + */ +uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource) +{ + uint32_t rng_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_RNG_CLKSOURCE(RNGxSource)); + + /* RNGCLK clock frequency */ + switch (LL_RCC_GetRNGClockSource(RNGxSource)) + { + case LL_RCC_RNG_CLKSOURCE_HSI: /* HSI clock used as RNG clock source */ + if (LL_RCC_HSI_IsReady() != 0U) + { + rng_frequency = HSI_VALUE; + } + break; + + case LL_RCC_RNG_CLKSOURCE_LSI: /* LSI clock used as RNG clock source */ +#if defined(RCC_LSI2_SUPPORT) + if ((RCC->BDCR1& (RCC_BDCR1_LSI1ON | RCC_BDCR1_LSI2ON)) != 0U) +#else + if (LL_RCC_LSI1_IsReady() != 0U) +#endif + { + rng_frequency = LSI_VALUE; + } + break; + + case LL_RCC_RNG_CLKSOURCE_LSE: /* LSE clock used as RNG clock source */ + if (LL_RCC_LSE_IsReady() != 0U) + { + rng_frequency = LSE_VALUE; + } + break; + + case LL_RCC_RNG_CLKSOURCE_PLL1Q_DIV2: /* PLL1Q/2 clock used as RNG clock source */ + if (LL_RCC_PLL1_IsReady() != 0U) + { + if (LL_RCC_PLL1_IsEnabledDomain_PLL1Q() != 0U) + { + rng_frequency = RCC_PLL1Q_GetFreqDomain()/2U; + } + } + break; + default: + /* unreachable code */ + break; + + } + + return rng_frequency; +} + +/** + * @brief Return ADCx clock frequency + * @param ADCxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_ADC_CLKSOURCE + * @retval ADC clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSE / HSI) or PLL1 is not ready + */ +uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource) +{ + uint32_t adc_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_ADC_CLKSOURCE(ADCxSource)); + + /* ADCCLK clock frequency */ + switch (LL_RCC_GetADCClockSource(ADCxSource)) + { + case LL_RCC_ADC_CLKSOURCE_HCLK: /* ADC Clock is SYSCLK */ + adc_frequency = RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()); + break; + + case LL_RCC_ADC_CLKSOURCE_SYSCLK: /* SYSCLK clock used as ADC clock source */ + adc_frequency = RCC_GetSystemClockFreq(); + break; + + case LL_RCC_ADC_CLKSOURCE_PLL1P: /* PLL1P clock used as ADC clock source */ + if (LL_RCC_PLL1_IsReady() != 0U) + { + if (LL_RCC_PLL1_IsEnabledDomain_PLL1P() != 0U) + { + adc_frequency = RCC_PLL1P_GetFreqDomain(); + } + } + break; + + case LL_RCC_ADC_CLKSOURCE_HSI: /*HSI clock used as ADC clock source */ + if (LL_RCC_HSI_IsReady() != 0U) + { + adc_frequency = HSI_VALUE; + } + break; + + case LL_RCC_ADC_CLKSOURCE_HSE: /*HSE clock used as ADC clock source */ + if (LL_RCC_HSE_IsReady() != 0U) + { + adc_frequency = HSE_VALUE; + } + break; + + default: + /* unreachable code */ + break; + } + + return adc_frequency; +} + + + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup RCC_LL_Private_Functions + * @{ + */ + +/** + * @brief Return SYSTEM clock frequency + * @retval SYSTEM clock frequency (in Hz) + */ +uint32_t RCC_GetSystemClockFreq(void) +{ + uint32_t frequency; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (LL_RCC_GetSysClkSource()) + { + case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ + frequency = HSI_VALUE; + break; + + case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */ + frequency = HSE_VALUE; + break; + + case LL_RCC_SYS_CLKSOURCE_STATUS_PLL1R: /* PLL1 used as system clock source */ + frequency = RCC_PLL1R_GetFreqDomain(); + break; + + default: + frequency = HSI_VALUE; + break; + } + + return frequency; +} + +/** + * @brief Return HCLK clock frequency + * @param SYSCLK_Frequency SYSCLK clock frequency + * @retval HCLK clock frequency (in Hz) + */ +uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency) +{ + /* HCLK clock frequency */ + return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler()); +} + +/** + * @brief Return PCLK1 clock frequency + * @param HCLK_Frequency HCLK clock frequency + * @retval PCLK1 clock frequency (in Hz) + */ +uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency) +{ + /* PCLK1 clock frequency */ + return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler()); +} + +/** + * @brief Return PCLK2 clock frequency + * @param HCLK_Frequency HCLK clock frequency + * @retval PCLK2 clock frequency (in Hz) + */ +uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency) +{ + /* PCLK2 clock frequency */ + return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler()); +} + + +/** + * @brief Return PCLK7 clock frequency + * @param HCLK_Frequency HCLK clock frequency + * @retval PCLK7 clock frequency (in Hz) + */ +uint32_t RCC_GetPCLK7ClockFreq(uint32_t HCLK_Frequency) +{ + /* PCLK7 clock frequency */ + return __LL_RCC_CALC_PCLK7_FREQ(HCLK_Frequency, LL_RCC_GetAPB7Prescaler()); +} + +/** + * @brief Return PLL1R clock frequency used for system domain + * @retval PLL1R clock frequency (in Hz) + */ +uint32_t RCC_PLL1R_GetFreqDomain(void) +{ + uint32_t pllinputfreq, pllsource; + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE/ PLLM) * PLLN + SYSCLK = PLL_VCO / PLLR + */ + pllsource = LL_RCC_PLL1_GetMainSource(); + + switch (pllsource) + { + case LL_RCC_PLL1SOURCE_HSI: /* HSI used as PLL1 clock source */ + pllinputfreq = HSI_VALUE; + break; + + case LL_RCC_PLL1SOURCE_HSE: /* HSE used as PLL1 clock source */ + pllinputfreq = HSE_VALUE; + break; + + default: + pllinputfreq = HSI_VALUE; + break; + } + return __LL_RCC_CALC_PLL1RCLK_FREQ(pllinputfreq, LL_RCC_PLL1_GetDivider(), + LL_RCC_PLL1_GetN(), LL_RCC_PLL1_GetR()); +} +/** + * @brief Return PLL1P clock frequency used for ADC and SAI domains + * @retval PLL1P clock frequency (in Hz) + */ +uint32_t RCC_PLL1P_GetFreqDomain(void) +{ + uint32_t pll1inputfreq, pll1outputfreq, pll1source; + uint32_t pll1n, pll1pdiv; + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN + Domain clock = PLL_VCO / PLL1P + */ + pll1source = LL_RCC_PLL1_GetMainSource(); + + switch (pll1source) + { + case LL_RCC_PLL1SOURCE_HSI: /* HSI used as PLL1 clock source */ + pll1inputfreq = HSI_VALUE; + break; + + case LL_RCC_PLL1SOURCE_HSE: /* HSE used as PLL1 clock source */ + pll1inputfreq = HSE_VALUE; + break; + + default: + pll1inputfreq = HSI_VALUE; + break; + } + + pll1n = LL_RCC_PLL1_GetN(); + pll1pdiv = LL_RCC_PLL1_GetP(); + if ((pll1n >= 8U) && (pll1pdiv >= 2U)) + { + pll1outputfreq = __LL_RCC_CALC_PLL1PCLK_FREQ(pll1inputfreq, LL_RCC_PLL1_GetDivider(), + pll1n, pll1pdiv); + } + else + { + pll1outputfreq = 0; /* Invalid PLL1N or PLL1PDIV value */ + } + return pll1outputfreq; +} + +/** + * @brief Return PLL1Q clock frequency used for RNG and SAI domains + * @retval PLL1Q clock frequency (in Hz) + */ +uint32_t RCC_PLL1Q_GetFreqDomain(void) +{ + uint32_t pll1inputfreq, pll1source; + + /* PLL1_VCO = (HSE_VALUE or HSI_VALUE / PLL1M) * PLL1N + Domain clock = PLL1_VCO / PLL1Q + */ + pll1source = LL_RCC_PLL1_GetMainSource(); + + switch (pll1source) + { + case LL_RCC_PLL1SOURCE_HSI: /* HSI used as PLL1 clock source */ + pll1inputfreq = HSI_VALUE; + break; + + case LL_RCC_PLL1SOURCE_HSE: /* HSE used as PLL1 clock source */ + pll1inputfreq = HSE_VALUE; + break; + + default: + pll1inputfreq = HSI_VALUE; + break; + } + return __LL_RCC_CALC_PLL1QCLK_FREQ(pll1inputfreq, LL_RCC_PLL1_GetDivider(), + LL_RCC_PLL1_GetN(), LL_RCC_PLL1_GetQ()); +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(RCC) */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_rng.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_rng.c new file mode 100644 index 0000000000..9acccbf857 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_rng.c @@ -0,0 +1,157 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_ll_rng.c + * @author MCD Application Team + * @brief RNG LL module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_ll_rng.h" +#include "stm32wbaxx_ll_bus.h" + +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +/** @addtogroup STM32WBAxx_LL_Driver + * @{ + */ + +#if defined (RNG) + +/** @addtogroup RNG_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup RNG_LL_Private_Macros RNG Private Macros + * @{ + */ +#define IS_LL_RNG_CED(__MODE__) (((__MODE__) == LL_RNG_CED_ENABLE) || \ + ((__MODE__) == LL_RNG_CED_DISABLE)) + +#define IS_LL_RNG_CLOCK_DIVIDER(__CLOCK_DIV__) ((__CLOCK_DIV__) <=0x0Fu) + + +#define IS_LL_RNG_NIST_COMPLIANCE(__NIST_COMPLIANCE__) (((__NIST_COMPLIANCE__) == LL_RNG_NIST_COMPLIANT) || \ + ((__NIST_COMPLIANCE__) == LL_RNG_NOTNIST_COMPLIANT)) + +#define IS_LL_RNG_CONFIG1 (__CONFIG1__) ((__CONFIG1__) <= 0x3FUL) + +#define IS_LL_RNG_CONFIG2 (__CONFIG2__) ((__CONFIG2__) <= 0x07UL) + +#define IS_LL_RNG_CONFIG3 (__CONFIG3__) ((__CONFIG3__) <= 0xFUL) +/** + * @} + */ +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RNG_LL_Exported_Functions + * @{ + */ + +/** @addtogroup RNG_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize RNG registers (Registers restored to their default values). + * @param RNGx RNG Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RNG registers are de-initialized + * - ERROR: not applicable + */ +ErrorStatus LL_RNG_DeInit(const RNG_TypeDef *RNGx) +{ + ErrorStatus status = SUCCESS; + + /* Check the parameters */ + assert_param(IS_RNG_ALL_INSTANCE(RNGx)); + if (RNGx == RNG) + { + /* Enable RNG reset state */ + LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_RNG); + + /* Release RNG from reset state */ + LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_RNG); + } + else + { + status = ERROR; + } + + return status; +} + +/** + * @brief Initialize RNG registers according to the specified parameters in RNG_InitStruct. + * @param RNGx RNG Instance + * @param RNG_InitStruct pointer to a LL_RNG_InitTypeDef structure + * that contains the configuration information for the specified RNG peripheral. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RNG registers are initialized according to RNG_InitStruct content + * - ERROR: not applicable + */ +ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct) +{ + /* Check the parameters */ + assert_param(IS_RNG_ALL_INSTANCE(RNGx)); + assert_param(IS_LL_RNG_CED(RNG_InitStruct->ClockErrorDetection)); + + /* Clock Error Detection Configuration when CONDRT bit is set to 1 */ + MODIFY_REG(RNGx->CR, RNG_CR_CED | RNG_CR_CONDRST, RNG_InitStruct->ClockErrorDetection | RNG_CR_CONDRST); + /* Writing bits CONDRST=0*/ + CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); + + return (SUCCESS); +} + +/** + * @brief Set each @ref LL_RNG_InitTypeDef field to default value. + * @param RNG_InitStruct pointer to a @ref LL_RNG_InitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ +void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct) +{ + /* Set RNG_InitStruct fields to default values */ + RNG_InitStruct->ClockErrorDetection = LL_RNG_CED_ENABLE; + +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* RNG */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_rtc.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_rtc.c new file mode 100644 index 0000000000..186bb215c9 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_rtc.c @@ -0,0 +1,858 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_ll_rtc.c + * @author MCD Application Team + * @brief RTC LL module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_ll_rtc.h" +#include "stm32wbaxx_ll_cortex.h" +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +/** @addtogroup STM32WBAxx_LL_Driver + * @{ + */ + +#if defined(RTC) + +/** @addtogroup RTC_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup RTC_LL_Private_Constants + * @{ + */ +/* Default values used for prescaler */ +#define RTC_ASYNCH_PRESC_DEFAULT ((uint32_t) 0x0000007FU) +#define RTC_SYNCH_PRESC_DEFAULT ((uint32_t) 0x000000FFU) + +/* Values used for timeout */ +#define RTC_INITMODE_TIMEOUT ((uint32_t) 1000U) /* 1s when tick set to 1ms */ +#define RTC_SYNCHRO_TIMEOUT ((uint32_t) 1000U) /* 1s when tick set to 1ms */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup RTC_LL_Private_Macros + * @{ + */ + +#define IS_LL_RTC_HOURFORMAT(__VALUE__) (((__VALUE__) == LL_RTC_HOURFORMAT_24HOUR) \ + || ((__VALUE__) == LL_RTC_HOURFORMAT_AMPM)) + +#define IS_LL_RTC_ASYNCH_PREDIV(__VALUE__) ((__VALUE__) <= 0x7FU) + +#define IS_LL_RTC_SYNCH_PREDIV(__VALUE__) ((__VALUE__) <= 0x7FFFU) + +#define IS_LL_RTC_FORMAT(__VALUE__) (((__VALUE__) == LL_RTC_FORMAT_BIN) \ + || ((__VALUE__) == LL_RTC_FORMAT_BCD)) + +#define IS_LL_RTC_TIME_FORMAT(__VALUE__) (((__VALUE__) == LL_RTC_TIME_FORMAT_AM_OR_24) \ + || ((__VALUE__) == LL_RTC_TIME_FORMAT_PM)) + +#define IS_LL_RTC_HOUR12(__HOUR__) (((__HOUR__) > 0U) && ((__HOUR__) <= 12U)) +#define IS_LL_RTC_HOUR24(__HOUR__) ((__HOUR__) <= 23U) +#define IS_LL_RTC_MINUTES(__MINUTES__) ((__MINUTES__) <= 59U) +#define IS_LL_RTC_SECONDS(__SECONDS__) ((__SECONDS__) <= 59U) + +#define IS_LL_RTC_WEEKDAY(__VALUE__) (((__VALUE__) == LL_RTC_WEEKDAY_MONDAY) \ + || ((__VALUE__) == LL_RTC_WEEKDAY_TUESDAY) \ + || ((__VALUE__) == LL_RTC_WEEKDAY_WEDNESDAY) \ + || ((__VALUE__) == LL_RTC_WEEKDAY_THURSDAY) \ + || ((__VALUE__) == LL_RTC_WEEKDAY_FRIDAY) \ + || ((__VALUE__) == LL_RTC_WEEKDAY_SATURDAY) \ + || ((__VALUE__) == LL_RTC_WEEKDAY_SUNDAY)) + +#define IS_LL_RTC_DAY(__DAY__) (((__DAY__) >= (uint32_t)1U) && ((__DAY__) <= (uint32_t)31U)) + +#define IS_LL_RTC_MONTH(__MONTH__) (((__MONTH__) >= 1U) && ((__MONTH__) <= 12U)) + +#define IS_LL_RTC_YEAR(__YEAR__) ((__YEAR__) <= 99U) + +#define IS_LL_RTC_ALMA_MASK(__VALUE__) (((__VALUE__) == LL_RTC_ALMA_MASK_NONE) \ + || ((__VALUE__) == LL_RTC_ALMA_MASK_DATEWEEKDAY) \ + || ((__VALUE__) == LL_RTC_ALMA_MASK_HOURS) \ + || ((__VALUE__) == LL_RTC_ALMA_MASK_MINUTES) \ + || ((__VALUE__) == LL_RTC_ALMA_MASK_SECONDS) \ + || ((__VALUE__) == LL_RTC_ALMA_MASK_ALL)) + +#define IS_LL_RTC_ALMB_MASK(__VALUE__) (((__VALUE__) == LL_RTC_ALMB_MASK_NONE) \ + || ((__VALUE__) == LL_RTC_ALMB_MASK_DATEWEEKDAY) \ + || ((__VALUE__) == LL_RTC_ALMB_MASK_HOURS) \ + || ((__VALUE__) == LL_RTC_ALMB_MASK_MINUTES) \ + || ((__VALUE__) == LL_RTC_ALMB_MASK_SECONDS) \ + || ((__VALUE__) == LL_RTC_ALMB_MASK_ALL)) + + +#define IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE) || \ + ((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY)) + +#define IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE) || \ + ((__SEL__) == LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY)) + + +/** + * @} + */ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RTC_LL_Exported_Functions + * @{ + */ + +/** @addtogroup RTC_LL_EF_Init + * @{ + */ + +/** + * @brief De-Initializes the RTC registers to their default reset values. + * @note This function does not reset the RTC Clock source and RTC Backup Data + * registers. + * @param RTCx RTC Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC registers are de-initialized + * - ERROR: RTC registers are not de-initialized + */ +ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx) +{ + ErrorStatus status = ERROR; + + /* Check the parameter */ + assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + + /* Disable the write protection for RTC registers */ + LL_RTC_DisableWriteProtection(RTCx); + + /* Set Initialization mode */ + if (LL_RTC_EnterInitMode(RTCx) != ERROR) + { + WRITE_REG(RTCx->TR, 0U); + WRITE_REG(RTCx->DR, (RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0)); + WRITE_REG(RTCx->CR, 0U); + WRITE_REG(RTCx->WUTR, RTC_WUTR_WUT); + WRITE_REG(RTCx->PRER, (RTC_PRER_PREDIV_A | RTC_SYNCH_PRESC_DEFAULT)); + WRITE_REG(RTCx->ALRMAR, 0U); + WRITE_REG(RTCx->ALRMBR, 0U); + WRITE_REG(RTCx->SHIFTR, 0U); + WRITE_REG(RTCx->CALR, 0U); + WRITE_REG(RTCx->ALRMASSR, 0U); + WRITE_REG(RTCx->ALRMBSSR, 0U); +#if defined (RTC_PRIVCFGR_PRIV) + WRITE_REG(RTCx->PRIVCFGR, 0U); +#endif /* RTC_PRIVCFGR_PRIV */ +#if defined (RTC_SECCFGR_SEC) + WRITE_REG(RTCx->SECCFGR, 0U); +#endif /* RTC_SECCFGR_SEC */ + + /* Clear some bits of RTC_ICSR and exit Initialization mode */ + CLEAR_BIT(RTCx->ICSR, RTC_ICSR_BCDU_Msk | RTC_ICSR_BIN_Msk | RTC_ICSR_INIT); + + /* Wait till the RTC RSF flag is set */ + status = LL_RTC_WaitForSynchro(RTCx); + } + + /* Enable the write protection for RTC registers */ + LL_RTC_EnableWriteProtection(RTCx); + + /* DeInitialization of the TAMP registers */ + WRITE_REG(TAMP->CR1, 0U); + WRITE_REG(TAMP->CR2, 0U); + WRITE_REG(TAMP->CR3, 0U); +#if defined (TAMP_SECCFGR_TAMPSEC) + WRITE_REG(TAMP->SECCFGR, 0U); +#endif /* TAMP_SECCFGR_TAMPSEC */ +#if defined (TAMP_PRIVCFGR_TAMPPRIV) + WRITE_REG(TAMP->PRIVCFGR, 0U); +#endif /* TAMP_PRIVCFGR_TAMPPRIV */ + WRITE_REG(TAMP->FLTCR, 0U); + WRITE_REG(TAMP->ATCR1, 0x00070000U); + WRITE_REG(TAMP->ATCR2, 0U); + WRITE_REG(TAMP->IER, 0U); + WRITE_REG(TAMP->SCR, 0xFFFFFFFFU); + + return status; +} + +/** + * @brief Initializes the RTC registers according to the specified parameters + * in RTC_InitStruct. + * @param RTCx RTC Instance + * @param RTC_InitStruct pointer to a @ref LL_RTC_InitTypeDef structure that contains + * the configuration information for the RTC peripheral. + * @note The RTC Prescaler register is write protected and can be written in + * initialization mode only. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC registers are initialized + * - ERROR: RTC registers are not initialized + */ +ErrorStatus LL_RTC_Init(RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct) +{ + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + assert_param(IS_LL_RTC_HOURFORMAT(RTC_InitStruct->HourFormat)); + assert_param(IS_LL_RTC_ASYNCH_PREDIV(RTC_InitStruct->AsynchPrescaler)); + assert_param(IS_LL_RTC_SYNCH_PREDIV(RTC_InitStruct->SynchPrescaler)); + + /* Disable the write protection for RTC registers */ + LL_RTC_DisableWriteProtection(RTCx); + + /* Set Initialization mode */ + if (LL_RTC_EnterInitMode(RTCx) != ERROR) + { + /* Set Hour Format */ + LL_RTC_SetHourFormat(RTCx, RTC_InitStruct->HourFormat); + + /* Configure Synchronous and Asynchronous prescaler factor */ + LL_RTC_SetSynchPrescaler(RTCx, RTC_InitStruct->SynchPrescaler); + LL_RTC_SetAsynchPrescaler(RTCx, RTC_InitStruct->AsynchPrescaler); + + /* Exit Initialization mode */ + LL_RTC_DisableInitMode(RTCx); + + status = SUCCESS; + } + /* Enable the write protection for RTC registers */ + LL_RTC_EnableWriteProtection(RTCx); + + return status; +} + +/** + * @brief Set each @ref LL_RTC_InitTypeDef field to default value. + * @param RTC_InitStruct pointer to a @ref LL_RTC_InitTypeDef structure which will be initialized. + * @retval None + */ +void LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct) +{ + /* Set RTC_InitStruct fields to default values */ + RTC_InitStruct->HourFormat = LL_RTC_HOURFORMAT_24HOUR; + RTC_InitStruct->AsynchPrescaler = RTC_ASYNCH_PRESC_DEFAULT; + RTC_InitStruct->SynchPrescaler = RTC_SYNCH_PRESC_DEFAULT; +} + +/** + * @brief Set the RTC current time. + * @param RTCx RTC Instance + * @param RTC_Format This parameter can be one of the following values: + * @arg @ref LL_RTC_FORMAT_BIN + * @arg @ref LL_RTC_FORMAT_BCD + * @param RTC_TimeStruct pointer to a RTC_TimeTypeDef structure that contains + * the time configuration information for the RTC. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC Time register is configured + * - ERROR: RTC Time register is not configured + */ +ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct) +{ + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + assert_param(IS_LL_RTC_FORMAT(RTC_Format)); + + if (RTC_Format == LL_RTC_FORMAT_BIN) + { + if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR) + { + assert_param(IS_LL_RTC_HOUR12(RTC_TimeStruct->Hours)); + assert_param(IS_LL_RTC_TIME_FORMAT(RTC_TimeStruct->TimeFormat)); + } + else + { + RTC_TimeStruct->TimeFormat = 0x00U; + assert_param(IS_LL_RTC_HOUR24(RTC_TimeStruct->Hours)); + } + assert_param(IS_LL_RTC_MINUTES(RTC_TimeStruct->Minutes)); + assert_param(IS_LL_RTC_SECONDS(RTC_TimeStruct->Seconds)); + } + else + { + if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR) + { + assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Hours))); + assert_param(IS_LL_RTC_TIME_FORMAT(RTC_TimeStruct->TimeFormat)); + } + else + { + RTC_TimeStruct->TimeFormat = 0U; + assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Hours))); + } + assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Minutes))); + assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Seconds))); + } + + /* Disable the write protection for RTC registers */ + LL_RTC_DisableWriteProtection(RTCx); + + /* Set Initialization mode */ + if (LL_RTC_EnterInitMode(RTCx) != ERROR) + { + /* Check the input parameters format */ + if (RTC_Format != LL_RTC_FORMAT_BIN) + { + LL_RTC_TIME_Config(RTCx, RTC_TimeStruct->TimeFormat, RTC_TimeStruct->Hours, + RTC_TimeStruct->Minutes, RTC_TimeStruct->Seconds); + } + else + { + LL_RTC_TIME_Config(RTCx, RTC_TimeStruct->TimeFormat, __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Hours), + __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Minutes), + __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Seconds)); + } + + /* Exit Initialization mode */ + LL_RTC_DisableInitMode(RTCx); + + /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ + if (LL_RTC_IsShadowRegBypassEnabled(RTCx) == 0U) + { + status = LL_RTC_WaitForSynchro(RTCx); + } + else + { + status = SUCCESS; + } + } + /* Enable the write protection for RTC registers */ + LL_RTC_EnableWriteProtection(RTCx); + + return status; +} + +/** + * @brief Set each @ref LL_RTC_TimeTypeDef field to default value (Time = 00h:00min:00sec). + * @param RTC_TimeStruct pointer to a @ref LL_RTC_TimeTypeDef structure which will be initialized. + * @retval None + */ +void LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct) +{ + /* Time = 00h:00min:00sec */ + RTC_TimeStruct->TimeFormat = LL_RTC_TIME_FORMAT_AM_OR_24; + RTC_TimeStruct->Hours = 0U; + RTC_TimeStruct->Minutes = 0U; + RTC_TimeStruct->Seconds = 0U; +} + +/** + * @brief Set the RTC current date. + * @param RTCx RTC Instance + * @param RTC_Format This parameter can be one of the following values: + * @arg @ref LL_RTC_FORMAT_BIN + * @arg @ref LL_RTC_FORMAT_BCD + * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that contains + * the date configuration information for the RTC. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC Day register is configured + * - ERROR: RTC Day register is not configured + */ +ErrorStatus LL_RTC_DATE_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct) +{ + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + assert_param(IS_LL_RTC_FORMAT(RTC_Format)); + + if ((RTC_Format == LL_RTC_FORMAT_BIN) && ((RTC_DateStruct->Month & 0x10U) == 0x10U)) + { + RTC_DateStruct->Month = (uint8_t)((uint32_t) RTC_DateStruct->Month & (uint32_t)~(0x10U)) + 0x0AU; + } + if (RTC_Format == LL_RTC_FORMAT_BIN) + { + assert_param(IS_LL_RTC_YEAR(RTC_DateStruct->Year)); + assert_param(IS_LL_RTC_MONTH(RTC_DateStruct->Month)); + assert_param(IS_LL_RTC_DAY(RTC_DateStruct->Day)); + } + else + { + assert_param(IS_LL_RTC_YEAR(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Year))); + assert_param(IS_LL_RTC_MONTH(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Month))); + assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Day))); + } + assert_param(IS_LL_RTC_WEEKDAY(RTC_DateStruct->WeekDay)); + + /* Disable the write protection for RTC registers */ + LL_RTC_DisableWriteProtection(RTCx); + + /* Set Initialization mode */ + if (LL_RTC_EnterInitMode(RTCx) != ERROR) + { + /* Check the input parameters format */ + if (RTC_Format != LL_RTC_FORMAT_BIN) + { + LL_RTC_DATE_Config(RTCx, RTC_DateStruct->WeekDay, RTC_DateStruct->Day, RTC_DateStruct->Month, + RTC_DateStruct->Year); + } + else + { + LL_RTC_DATE_Config(RTCx, RTC_DateStruct->WeekDay, __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Day), + __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Month), + __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Year)); + } + + /* Exit Initialization mode */ + LL_RTC_DisableInitMode(RTCx); + + /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ + if (LL_RTC_IsShadowRegBypassEnabled(RTCx) == 0U) + { + status = LL_RTC_WaitForSynchro(RTCx); + } + else + { + status = SUCCESS; + } + } + /* Enable the write protection for RTC registers */ + LL_RTC_EnableWriteProtection(RTCx); + + return status; +} + +/** + * @brief Set each @ref LL_RTC_DateTypeDef field to default value (date = Monday, January 01 xx00) + * @param RTC_DateStruct pointer to a @ref LL_RTC_DateTypeDef structure which will be initialized. + * @retval None + */ +void LL_RTC_DATE_StructInit(LL_RTC_DateTypeDef *RTC_DateStruct) +{ + /* Monday, January 01 xx00 */ + RTC_DateStruct->WeekDay = LL_RTC_WEEKDAY_MONDAY; + RTC_DateStruct->Day = 1U; + RTC_DateStruct->Month = LL_RTC_MONTH_JANUARY; + RTC_DateStruct->Year = 0U; +} + +/** + * @brief Set the RTC Alarm A. + * @note The Alarm register can only be written when the corresponding Alarm + * is disabled (Use @ref LL_RTC_ALMA_Disable function). + * @param RTCx RTC Instance + * @param RTC_Format This parameter can be one of the following values: + * @arg @ref LL_RTC_FORMAT_BIN + * @arg @ref LL_RTC_FORMAT_BCD + * @param RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure that + * contains the alarm configuration parameters. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: ALARMA registers are configured + * - ERROR: ALARMA registers are not configured + */ +ErrorStatus LL_RTC_ALMA_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct) +{ + /* Check the parameters */ + assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + assert_param(IS_LL_RTC_FORMAT(RTC_Format)); + assert_param(IS_LL_RTC_ALMA_MASK(RTC_AlarmStruct->AlarmMask)); + assert_param(IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL(RTC_AlarmStruct->AlarmDateWeekDaySel)); + + if (RTC_Format == LL_RTC_FORMAT_BIN) + { + if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR) + { + assert_param(IS_LL_RTC_HOUR12(RTC_AlarmStruct->AlarmTime.Hours)); + assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat)); + } + else + { + RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U; + assert_param(IS_LL_RTC_HOUR24(RTC_AlarmStruct->AlarmTime.Hours)); + } + assert_param(IS_LL_RTC_MINUTES(RTC_AlarmStruct->AlarmTime.Minutes)); + assert_param(IS_LL_RTC_SECONDS(RTC_AlarmStruct->AlarmTime.Seconds)); + + if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE) + { + assert_param(IS_LL_RTC_DAY(RTC_AlarmStruct->AlarmDateWeekDay)); + } + else + { + assert_param(IS_LL_RTC_WEEKDAY(RTC_AlarmStruct->AlarmDateWeekDay)); + } + } + else + { + if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR) + { + assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours))); + assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat)); + } + else + { + RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U; + assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours))); + } + + assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Minutes))); + assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Seconds))); + + if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE) + { + assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay))); + } + else + { + assert_param(IS_LL_RTC_WEEKDAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay))); + } + } + + /* Disable the write protection for RTC registers */ + LL_RTC_DisableWriteProtection(RTCx); + + /* Select weekday selection */ + if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE) + { + /* Set the date for ALARM */ + LL_RTC_ALMA_DisableWeekday(RTCx); + if (RTC_Format != LL_RTC_FORMAT_BIN) + { + LL_RTC_ALMA_SetDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay); + } + else + { + LL_RTC_ALMA_SetDay(RTCx, __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmDateWeekDay)); + } + } + else + { + /* Set the week day for ALARM */ + LL_RTC_ALMA_EnableWeekday(RTCx); + LL_RTC_ALMA_SetWeekDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay); + } + + /* Configure the Alarm register */ + if (RTC_Format != LL_RTC_FORMAT_BIN) + { + LL_RTC_ALMA_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat, RTC_AlarmStruct->AlarmTime.Hours, + RTC_AlarmStruct->AlarmTime.Minutes, RTC_AlarmStruct->AlarmTime.Seconds); + } + else + { + LL_RTC_ALMA_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat, + __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Hours), + __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Minutes), + __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Seconds)); + } + /* Set ALARM mask */ + LL_RTC_ALMA_SetMask(RTCx, RTC_AlarmStruct->AlarmMask); + + /* Enable the write protection for RTC registers */ + LL_RTC_EnableWriteProtection(RTCx); + + return SUCCESS; +} + +/** + * @brief Set the RTC Alarm B. + * @note The Alarm register can only be written when the corresponding Alarm + * is disabled (@ref LL_RTC_ALMB_Disable function). + * @param RTCx RTC Instance + * @param RTC_Format This parameter can be one of the following values: + * @arg @ref LL_RTC_FORMAT_BIN + * @arg @ref LL_RTC_FORMAT_BCD + * @param RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure that + * contains the alarm configuration parameters. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: ALARMB registers are configured + * - ERROR: ALARMB registers are not configured + */ +ErrorStatus LL_RTC_ALMB_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct) +{ + /* Check the parameters */ + assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + assert_param(IS_LL_RTC_FORMAT(RTC_Format)); + assert_param(IS_LL_RTC_ALMB_MASK(RTC_AlarmStruct->AlarmMask)); + assert_param(IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL(RTC_AlarmStruct->AlarmDateWeekDaySel)); + + if (RTC_Format == LL_RTC_FORMAT_BIN) + { + if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR) + { + assert_param(IS_LL_RTC_HOUR12(RTC_AlarmStruct->AlarmTime.Hours)); + assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat)); + } + else + { + RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U; + assert_param(IS_LL_RTC_HOUR24(RTC_AlarmStruct->AlarmTime.Hours)); + } + assert_param(IS_LL_RTC_MINUTES(RTC_AlarmStruct->AlarmTime.Minutes)); + assert_param(IS_LL_RTC_SECONDS(RTC_AlarmStruct->AlarmTime.Seconds)); + + if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE) + { + assert_param(IS_LL_RTC_DAY(RTC_AlarmStruct->AlarmDateWeekDay)); + } + else + { + assert_param(IS_LL_RTC_WEEKDAY(RTC_AlarmStruct->AlarmDateWeekDay)); + } + } + else + { + if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR) + { + assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours))); + assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat)); + } + else + { + RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U; + assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours))); + } + + assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Minutes))); + assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Seconds))); + + if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE) + { + assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay))); + } + else + { + assert_param(IS_LL_RTC_WEEKDAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay))); + } + } + + /* Disable the write protection for RTC registers */ + LL_RTC_DisableWriteProtection(RTCx); + + /* Select weekday selection */ + if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE) + { + /* Set the date for ALARM */ + LL_RTC_ALMB_DisableWeekday(RTCx); + if (RTC_Format != LL_RTC_FORMAT_BIN) + { + LL_RTC_ALMB_SetDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay); + } + else + { + LL_RTC_ALMB_SetDay(RTCx, __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmDateWeekDay)); + } + } + else + { + /* Set the week day for ALARM */ + LL_RTC_ALMB_EnableWeekday(RTCx); + LL_RTC_ALMB_SetWeekDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay); + } + + /* Configure the Alarm register */ + if (RTC_Format != LL_RTC_FORMAT_BIN) + { + LL_RTC_ALMB_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat, RTC_AlarmStruct->AlarmTime.Hours, + RTC_AlarmStruct->AlarmTime.Minutes, RTC_AlarmStruct->AlarmTime.Seconds); + } + else + { + LL_RTC_ALMB_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat, + __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Hours), + __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Minutes), + __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Seconds)); + } + /* Set ALARM mask */ + LL_RTC_ALMB_SetMask(RTCx, RTC_AlarmStruct->AlarmMask); + + /* Enable the write protection for RTC registers */ + LL_RTC_EnableWriteProtection(RTCx); + + return SUCCESS; +} + +/** + * @brief Set each @ref LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec / + * Day = 1st day of the month/Mask = all fields are masked). + * @param RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure which will be initialized. + * @retval None + */ +void LL_RTC_ALMA_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct) +{ + /* Alarm Time Settings : Time = 00h:00mn:00sec */ + RTC_AlarmStruct->AlarmTime.TimeFormat = LL_RTC_ALMA_TIME_FORMAT_AM; + RTC_AlarmStruct->AlarmTime.Hours = 0U; + RTC_AlarmStruct->AlarmTime.Minutes = 0U; + RTC_AlarmStruct->AlarmTime.Seconds = 0U; + + /* Alarm Day Settings : Day = 1st day of the month */ + RTC_AlarmStruct->AlarmDateWeekDaySel = LL_RTC_ALMA_DATEWEEKDAYSEL_DATE; + RTC_AlarmStruct->AlarmDateWeekDay = 1U; + + /* Alarm Masks Settings : Mask = all fields are not masked */ + RTC_AlarmStruct->AlarmMask = LL_RTC_ALMA_MASK_NONE; +} + +/** + * @brief Set each @ref LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec / + * Day = 1st day of the month/Mask = all fields are masked). + * @param RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure which will be initialized. + * @retval None + */ +void LL_RTC_ALMB_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct) +{ + /* Alarm Time Settings : Time = 00h:00mn:00sec */ + RTC_AlarmStruct->AlarmTime.TimeFormat = LL_RTC_ALMB_TIME_FORMAT_AM; + RTC_AlarmStruct->AlarmTime.Hours = 0U; + RTC_AlarmStruct->AlarmTime.Minutes = 0U; + RTC_AlarmStruct->AlarmTime.Seconds = 0U; + + /* Alarm Day Settings : Day = 1st day of the month */ + RTC_AlarmStruct->AlarmDateWeekDaySel = LL_RTC_ALMB_DATEWEEKDAYSEL_DATE; + RTC_AlarmStruct->AlarmDateWeekDay = 1U; + + /* Alarm Masks Settings : Mask = all fields are not masked */ + RTC_AlarmStruct->AlarmMask = LL_RTC_ALMB_MASK_NONE; +} + +/** + * @brief Enters the RTC Initialization mode. + * @note The RTC Initialization mode is write protected, use the + * @ref LL_RTC_DisableWriteProtection before calling this function. + * @param RTCx RTC Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC is in Init mode + * - ERROR: RTC is not in Init mode + */ +ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx) +{ + __IO uint32_t timeout = RTC_INITMODE_TIMEOUT; + ErrorStatus status = SUCCESS; + uint32_t tmp; + + /* Check the parameter */ + assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + + /* Check if the Initialization mode is set */ + if (LL_RTC_IsActiveFlag_INIT(RTCx) == 0U) + { + /* Set the Initialization mode */ + LL_RTC_EnableInitMode(RTCx); + + /* Wait till RTC is in INIT state and if Time out is reached exit */ + tmp = LL_RTC_IsActiveFlag_INIT(RTCx); + while ((timeout != 0U) && (tmp != 1U)) + { + if (LL_SYSTICK_IsActiveCounterFlag() == 1U) + { + timeout --; + } + tmp = LL_RTC_IsActiveFlag_INIT(RTCx); + if (timeout == 0U) + { + status = ERROR; + } + } + } + return status; +} + +/** + * @brief Exit the RTC Initialization mode. + * @note When the initialization sequence is complete, the calendar restarts + * counting after 4 RTCCLK cycles. + * @note The RTC Initialization mode is write protected, use the + * @ref LL_RTC_DisableWriteProtection before calling this function. + * @param RTCx RTC Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC exited from in Init mode + * - ERROR: Not applicable + */ +ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx) +{ + /* Check the parameter */ + assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + + /* Disable initialization mode */ + LL_RTC_DisableInitMode(RTCx); + + return SUCCESS; +} + +/** + * @brief Waits until the RTC Time and Day registers (RTC_TR and RTC_DR) are + * synchronized with RTC APB clock. + * @note The RTC Resynchronization mode is write protected, use the + * @ref LL_RTC_DisableWriteProtection before calling this function. + * @note To read the calendar through the shadow registers after Calendar + * initialization, calendar update or after wakeup from low power modes + * the software must first clear the RSF flag. + * The software must then wait until it is set again before reading + * the calendar, which means that the calendar registers have been + * correctly copied into the RTC_TR and RTC_DR shadow registers. + * @param RTCx RTC Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC registers are synchronised + * - ERROR: RTC registers are not synchronised + */ +ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx) +{ + __IO uint32_t timeout = RTC_SYNCHRO_TIMEOUT; + uint32_t tmp; + ErrorStatus status = SUCCESS; + + /* Check the parameter */ + assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + + /* Clear RSF flag */ + LL_RTC_ClearFlag_RS(RTCx); + + /* Wait the registers to be synchronised */ + tmp = LL_RTC_IsActiveFlag_RS(RTCx); + while ((timeout != 0U) && (tmp != 1U)) + { + if (LL_SYSTICK_IsActiveCounterFlag() == 1U) + { + timeout--; + } + tmp = LL_RTC_IsActiveFlag_RS(RTCx); + } + + if (timeout == 0U) + { + status = ERROR; + } + + return status; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(RTC) */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_spi.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_spi.c new file mode 100644 index 0000000000..4b59360326 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_spi.c @@ -0,0 +1,408 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_ll_spi.c + * @author MCD Application Team + * @brief SPI LL module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_ll_spi.h" +#include "stm32wbaxx_ll_bus.h" +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +/** @addtogroup STM32WBAxx_LL_Driver + * @{ + */ + +#if defined(SPI1) || defined(SPI3) + +/** @addtogroup SPI_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup SPI_LL_Private_Macros + * @{ + */ + +#define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) || \ + ((__VALUE__) == LL_SPI_MODE_SLAVE)) + +#define IS_LL_SPI_SS_IDLENESS(__VALUE__) (((__VALUE__) == LL_SPI_SS_IDLENESS_00CYCLE) || \ + ((__VALUE__) == LL_SPI_SS_IDLENESS_01CYCLE) || \ + ((__VALUE__) == LL_SPI_SS_IDLENESS_02CYCLE) || \ + ((__VALUE__) == LL_SPI_SS_IDLENESS_03CYCLE) || \ + ((__VALUE__) == LL_SPI_SS_IDLENESS_04CYCLE) || \ + ((__VALUE__) == LL_SPI_SS_IDLENESS_05CYCLE) || \ + ((__VALUE__) == LL_SPI_SS_IDLENESS_06CYCLE) || \ + ((__VALUE__) == LL_SPI_SS_IDLENESS_07CYCLE) || \ + ((__VALUE__) == LL_SPI_SS_IDLENESS_08CYCLE) || \ + ((__VALUE__) == LL_SPI_SS_IDLENESS_09CYCLE) || \ + ((__VALUE__) == LL_SPI_SS_IDLENESS_10CYCLE) || \ + ((__VALUE__) == LL_SPI_SS_IDLENESS_11CYCLE) || \ + ((__VALUE__) == LL_SPI_SS_IDLENESS_12CYCLE) || \ + ((__VALUE__) == LL_SPI_SS_IDLENESS_13CYCLE) || \ + ((__VALUE__) == LL_SPI_SS_IDLENESS_14CYCLE) || \ + ((__VALUE__) == LL_SPI_SS_IDLENESS_15CYCLE)) + +#define IS_LL_SPI_ID_IDLENESS(__VALUE__) (((__VALUE__) == LL_SPI_ID_IDLENESS_00CYCLE) || \ + ((__VALUE__) == LL_SPI_ID_IDLENESS_01CYCLE) || \ + ((__VALUE__) == LL_SPI_ID_IDLENESS_02CYCLE) || \ + ((__VALUE__) == LL_SPI_ID_IDLENESS_03CYCLE) || \ + ((__VALUE__) == LL_SPI_ID_IDLENESS_04CYCLE) || \ + ((__VALUE__) == LL_SPI_ID_IDLENESS_05CYCLE) || \ + ((__VALUE__) == LL_SPI_ID_IDLENESS_06CYCLE) || \ + ((__VALUE__) == LL_SPI_ID_IDLENESS_07CYCLE) || \ + ((__VALUE__) == LL_SPI_ID_IDLENESS_08CYCLE) || \ + ((__VALUE__) == LL_SPI_ID_IDLENESS_09CYCLE) || \ + ((__VALUE__) == LL_SPI_ID_IDLENESS_10CYCLE) || \ + ((__VALUE__) == LL_SPI_ID_IDLENESS_11CYCLE) || \ + ((__VALUE__) == LL_SPI_ID_IDLENESS_12CYCLE) || \ + ((__VALUE__) == LL_SPI_ID_IDLENESS_13CYCLE) || \ + ((__VALUE__) == LL_SPI_ID_IDLENESS_14CYCLE) || \ + ((__VALUE__) == LL_SPI_ID_IDLENESS_15CYCLE)) + +#define IS_LL_SPI_TXCRCINIT_PATTERN(__VALUE__) (((__VALUE__) == LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN) || \ + ((__VALUE__) == LL_SPI_TXCRCINIT_ALL_ONES_PATTERN)) + +#define IS_LL_SPI_RXCRCINIT_PATTERN(__VALUE__) (((__VALUE__) == LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN) || \ + ((__VALUE__) == LL_SPI_RXCRCINIT_ALL_ONES_PATTERN)) + +#define IS_LL_SPI_UDR_CONFIG_REGISTER(__VALUE__) (((__VALUE__) == LL_SPI_UDR_CONFIG_REGISTER_PATTERN) || \ + ((__VALUE__) == LL_SPI_UDR_CONFIG_LAST_RECEIVED) || \ + ((__VALUE__) == LL_SPI_UDR_CONFIG_LAST_TRANSMITTED)) + +#define IS_LL_SPI_UDR_DETECT_BEGIN_DATA(__VALUE__) (((__VALUE__) == LL_SPI_UDR_DETECT_BEGIN_DATA_FRAME) || \ + ((__VALUE__) == LL_SPI_UDR_DETECT_END_DATA_FRAME) || \ + ((__VALUE__) == LL_SPI_UDR_DETECT_BEGIN_ACTIVE_NSS)) + +#define IS_LL_SPI_PROTOCOL(__VALUE__) (((__VALUE__) == LL_SPI_PROTOCOL_MOTOROLA) || \ + ((__VALUE__) == LL_SPI_PROTOCOL_TI)) + +#define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) || \ + ((__VALUE__) == LL_SPI_PHASE_2EDGE)) + +#define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) || \ + ((__VALUE__) == LL_SPI_POLARITY_HIGH)) + +#define IS_LL_SPI_BAUDRATEPRESCALER(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_BYPASS) || \ + ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) || \ + ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) || \ + ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) || \ + ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) || \ + ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) || \ + ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) || \ + ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) || \ + ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256)) + +#define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) || \ + ((__VALUE__) == LL_SPI_MSB_FIRST)) + +#define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) || \ + ((__VALUE__) == LL_SPI_SIMPLEX_TX) || \ + ((__VALUE__) == LL_SPI_SIMPLEX_RX) || \ + ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) || \ + ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX)) + +#define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_4BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_17BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_18BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_19BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_20BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_21BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_22BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_23BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_24BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_25BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_26BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_27BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_28BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_29BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_30BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_31BIT) || \ + ((__VALUE__) == LL_SPI_DATAWIDTH_32BIT)) + +#define IS_LL_SPI_FIFO_TH(__VALUE__) (((__VALUE__) == LL_SPI_FIFO_TH_01DATA) || \ + ((__VALUE__) == LL_SPI_FIFO_TH_02DATA) || \ + ((__VALUE__) == LL_SPI_FIFO_TH_03DATA) || \ + ((__VALUE__) == LL_SPI_FIFO_TH_04DATA) || \ + ((__VALUE__) == LL_SPI_FIFO_TH_05DATA) || \ + ((__VALUE__) == LL_SPI_FIFO_TH_06DATA) || \ + ((__VALUE__) == LL_SPI_FIFO_TH_07DATA) || \ + ((__VALUE__) == LL_SPI_FIFO_TH_08DATA) || \ + ((__VALUE__) == LL_SPI_FIFO_TH_09DATA) || \ + ((__VALUE__) == LL_SPI_FIFO_TH_10DATA) || \ + ((__VALUE__) == LL_SPI_FIFO_TH_11DATA) || \ + ((__VALUE__) == LL_SPI_FIFO_TH_12DATA) || \ + ((__VALUE__) == LL_SPI_FIFO_TH_13DATA) || \ + ((__VALUE__) == LL_SPI_FIFO_TH_14DATA) || \ + ((__VALUE__) == LL_SPI_FIFO_TH_15DATA) || \ + ((__VALUE__) == LL_SPI_FIFO_TH_16DATA)) + +#define IS_LL_SPI_CRC(__VALUE__) (((__VALUE__) == LL_SPI_CRC_4BIT) || \ + ((__VALUE__) == LL_SPI_CRC_5BIT) || \ + ((__VALUE__) == LL_SPI_CRC_6BIT) || \ + ((__VALUE__) == LL_SPI_CRC_7BIT) || \ + ((__VALUE__) == LL_SPI_CRC_8BIT) || \ + ((__VALUE__) == LL_SPI_CRC_9BIT) || \ + ((__VALUE__) == LL_SPI_CRC_10BIT) || \ + ((__VALUE__) == LL_SPI_CRC_11BIT) || \ + ((__VALUE__) == LL_SPI_CRC_12BIT) || \ + ((__VALUE__) == LL_SPI_CRC_13BIT) || \ + ((__VALUE__) == LL_SPI_CRC_14BIT) || \ + ((__VALUE__) == LL_SPI_CRC_15BIT) || \ + ((__VALUE__) == LL_SPI_CRC_16BIT) || \ + ((__VALUE__) == LL_SPI_CRC_17BIT) || \ + ((__VALUE__) == LL_SPI_CRC_18BIT) || \ + ((__VALUE__) == LL_SPI_CRC_19BIT) || \ + ((__VALUE__) == LL_SPI_CRC_20BIT) || \ + ((__VALUE__) == LL_SPI_CRC_21BIT) || \ + ((__VALUE__) == LL_SPI_CRC_22BIT) || \ + ((__VALUE__) == LL_SPI_CRC_23BIT) || \ + ((__VALUE__) == LL_SPI_CRC_24BIT) || \ + ((__VALUE__) == LL_SPI_CRC_25BIT) || \ + ((__VALUE__) == LL_SPI_CRC_26BIT) || \ + ((__VALUE__) == LL_SPI_CRC_27BIT) || \ + ((__VALUE__) == LL_SPI_CRC_28BIT) || \ + ((__VALUE__) == LL_SPI_CRC_29BIT) || \ + ((__VALUE__) == LL_SPI_CRC_30BIT) || \ + ((__VALUE__) == LL_SPI_CRC_31BIT) || \ + ((__VALUE__) == LL_SPI_CRC_32BIT)) + +#define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) || \ + ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) || \ + ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT)) + +#define IS_LL_SPI_RX_FIFO(__VALUE__) (((__VALUE__) == LL_SPI_RX_FIFO_0PACKET) || \ + ((__VALUE__) == LL_SPI_RX_FIFO_1PACKET) || \ + ((__VALUE__) == LL_SPI_RX_FIFO_2PACKET) || \ + ((__VALUE__) == LL_SPI_RX_FIFO_3PACKET)) + +#define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) || \ + ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE)) + +#define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1UL) + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SPI_LL_Exported_Functions + * @{ + */ + +/** @addtogroup SPI_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize the SPI registers to their default reset values. + * @param SPIx SPI Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: SPI registers are de-initialized + * - ERROR: SPI registers are not de-initialized + */ +ErrorStatus LL_SPI_DeInit(const SPI_TypeDef *SPIx) +{ + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_SPI_ALL_INSTANCE(SPIx)); + +#if defined(SPI1) + if (SPIx == SPI1) + { + /* Force reset of SPI clock */ + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1); + + /* Release reset of SPI clock */ + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1); + + /* Update the return status */ + status = SUCCESS; + } +#endif /* SPI1 */ +#if defined(SPI3) + if (SPIx == SPI3) + { + /* Force reset of SPI clock */ + LL_APB7_GRP1_ForceReset(LL_APB7_GRP1_PERIPH_SPI3); + + /* Release reset of SPI clock */ + LL_APB7_GRP1_ReleaseReset(LL_APB7_GRP1_PERIPH_SPI3); + + /* Update the return status */ + status = SUCCESS; + } +#endif /* SPI3 */ + + return status; +} + +/** + * @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct. + * @note As some bits in SPI configuration registers can only be written when the SPI is disabled + * (SPI_CR1_SPE bit =0), SPI IP should be in disabled state prior calling this function. + * Otherwise, ERROR result will be returned. + * @param SPIx SPI Instance + * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure + * @retval An ErrorStatus enumeration value. (Return always SUCCESS) + */ +ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct) +{ + ErrorStatus status = ERROR; + uint32_t tmp_nss; + uint32_t tmp_mode; + uint32_t tmp_nss_polarity; + + /* Check the SPI Instance SPIx*/ + assert_param(IS_SPI_ALL_INSTANCE(SPIx)); + + /* Check the SPI parameters from SPI_InitStruct*/ + assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection)); + assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode)); + assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth)); + assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity)); + assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase)); + assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS)); + assert_param(IS_LL_SPI_BAUDRATEPRESCALER(SPI_InitStruct->BaudRate)); + assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder)); + assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation)); + + /* Check the SPI instance is not enabled */ + if (LL_SPI_IsEnabled(SPIx) == 0x00000000UL) + { + /*---------------------------- SPIx CFG1 Configuration ------------------------ + * Configure SPIx CFG1 with parameters: + * - Master Baud Rate : SPI_CFG1_MBR[2:0] bits & SPI_CFG1_BPASS bit + * - CRC Computation Enable : SPI_CFG1_CRCEN bit + * - Length of data frame : SPI_CFG1_DSIZE[4:0] bits + */ + MODIFY_REG(SPIx->CFG1, SPI_CFG1_BPASS | SPI_CFG1_MBR | SPI_CFG1_CRCEN | SPI_CFG1_DSIZE, + SPI_InitStruct->BaudRate | SPI_InitStruct->CRCCalculation | SPI_InitStruct->DataWidth); + + tmp_nss = SPI_InitStruct->NSS; + tmp_mode = SPI_InitStruct->Mode; + tmp_nss_polarity = LL_SPI_GetNSSPolarity(SPIx); + + /* Checks to setup Internal SS signal level and avoid a MODF Error */ + if ((tmp_nss == LL_SPI_NSS_SOFT) && (((tmp_nss_polarity == LL_SPI_NSS_POLARITY_LOW) && \ + (tmp_mode == LL_SPI_MODE_MASTER)) || \ + ((tmp_nss_polarity == LL_SPI_NSS_POLARITY_HIGH) && \ + (tmp_mode == LL_SPI_MODE_SLAVE)))) + { + LL_SPI_SetInternalSSLevel(SPIx, LL_SPI_SS_LEVEL_HIGH); + } + + /*---------------------------- SPIx CFG2 Configuration ------------------------ + * Configure SPIx CFG2 with parameters: + * - NSS management : SPI_CFG2_SSM, SPI_CFG2_SSOE bits + * - ClockPolarity : SPI_CFG2_CPOL bit + * - ClockPhase : SPI_CFG2_CPHA bit + * - BitOrder : SPI_CFG2_LSBFRST bit + * - Master/Slave Mode : SPI_CFG2_MASTER bit + * - SPI Mode : SPI_CFG2_COMM[1:0] bits + */ + MODIFY_REG(SPIx->CFG2, SPI_CFG2_SSM | SPI_CFG2_SSOE | + SPI_CFG2_CPOL | SPI_CFG2_CPHA | + SPI_CFG2_LSBFRST | SPI_CFG2_MASTER | SPI_CFG2_COMM, + SPI_InitStruct->NSS | SPI_InitStruct->ClockPolarity | + SPI_InitStruct->ClockPhase | SPI_InitStruct->BitOrder | + SPI_InitStruct->Mode | (SPI_InitStruct->TransferDirection & SPI_CFG2_COMM)); + + /*---------------------------- SPIx CR1 Configuration ------------------------ + * Configure SPIx CR1 with parameter: + * - Half Duplex Direction : SPI_CR1_HDDIR bit + */ + MODIFY_REG(SPIx->CR1, SPI_CR1_HDDIR, SPI_InitStruct->TransferDirection & SPI_CR1_HDDIR); + + /*---------------------------- SPIx CRCPOLY Configuration ---------------------- + * Configure SPIx CRCPOLY with parameter: + * - CRCPoly : CRCPOLY[31:0] bits + */ + if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE) + { + assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly)); + LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly); + } + + + status = SUCCESS; + } + + return status; +} + +/** + * @brief Set each @ref LL_SPI_InitTypeDef field to default value. + * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ +void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct) +{ + /* Set SPI_InitStruct fields to default values */ + SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX; + SPI_InitStruct->Mode = LL_SPI_MODE_SLAVE; + SPI_InitStruct->DataWidth = LL_SPI_DATAWIDTH_8BIT; + SPI_InitStruct->ClockPolarity = LL_SPI_POLARITY_LOW; + SPI_InitStruct->ClockPhase = LL_SPI_PHASE_1EDGE; + SPI_InitStruct->NSS = LL_SPI_NSS_HARD_INPUT; + SPI_InitStruct->BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV2; + SPI_InitStruct->BitOrder = LL_SPI_MSB_FIRST; + SPI_InitStruct->CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; + SPI_InitStruct->CRCPoly = 7UL; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(SPI1) || defined(SPI3) */ + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_tim.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_tim.c new file mode 100644 index 0000000000..c347ac2c95 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_tim.c @@ -0,0 +1,1346 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_ll_tim.c + * @author MCD Application Team + * @brief TIM LL module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_ll_tim.h" +#include "stm32wbaxx_ll_bus.h" + +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +/** @addtogroup STM32WBAxx_LL_Driver + * @{ + */ + +#if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM16) || defined (TIM17) + +/** @addtogroup TIM_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup TIM_LL_Private_Macros + * @{ + */ +#define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \ + || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \ + || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \ + || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \ + || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN)) + +#define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \ + || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \ + || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4)) + +#define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \ + || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \ + || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \ + || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \ + || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \ + || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \ + || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \ + || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \ + || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \ + || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \ + || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \ + || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \ + || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \ + || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2) \ + || ((__VALUE__) == LL_TIM_OCMODE_PULSE_ON_COMPARE) \ + || ((__VALUE__) == LL_TIM_OCMODE_DIRECTION_OUTPUT)) + +#define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \ + || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE)) + +#define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \ + || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW)) + +#define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \ + || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH)) + +#define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \ + || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \ + || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC)) + +#define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \ + || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \ + || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \ + || ((__VALUE__) == LL_TIM_ICPSC_DIV8)) + +#define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8)) + +#define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \ + || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \ + || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE)) + +#define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \ + || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \ + || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12) \ + || ((__VALUE__) == LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2) \ + || ((__VALUE__) == LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1) \ + || ((__VALUE__) == LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X2) \ + || ((__VALUE__) == LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12) \ + || ((__VALUE__) == LL_TIM_ENCODERMODE_X1_TI1) \ + || ((__VALUE__) == LL_TIM_ENCODERMODE_X1_TI2)) + +#define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \ + || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING)) + +#define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \ + || ((__VALUE__) == LL_TIM_OSSR_ENABLE)) + +#define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \ + || ((__VALUE__) == LL_TIM_OSSI_ENABLE)) + +#define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \ + || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \ + || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \ + || ((__VALUE__) == LL_TIM_LOCKLEVEL_3)) + +#define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \ + || ((__VALUE__) == LL_TIM_BREAK_ENABLE)) + +#define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \ + || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH)) + +#define IS_LL_TIM_BREAK_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \ + || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8)) + +#define IS_LL_TIM_BREAK_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_AFMODE_INPUT) \ + || ((__VALUE__) == LL_TIM_BREAK_AFMODE_BIDIRECTIONAL)) + +#define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \ + || ((__VALUE__) == LL_TIM_BREAK2_ENABLE)) + +#define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \ + || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH)) + +#define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \ + || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8)) + +#define IS_LL_TIM_BREAK2_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_AFMODE_INPUT) \ + || ((__VALUE__) == LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL)) + +#define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \ + || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE)) +/** + * @} + */ + + +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup TIM_LL_Private_Functions TIM Private Functions + * @{ + */ +static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); +static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); +static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); +static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup TIM_LL_Exported_Functions + * @{ + */ + +/** @addtogroup TIM_LL_EF_Init + * @{ + */ + +/** + * @brief Set TIMx registers to their reset values. + * @param TIMx Timer instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: invalid TIMx instance + */ +ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx) +{ + ErrorStatus result = SUCCESS; + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(TIMx)); + + if (TIMx == TIM1) + { + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1); + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1); + } + else if (TIMx == TIM2) + { + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2); + } +#if defined(TIM3) + else if (TIMx == TIM3) + { + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3); + } +#endif /* TIM3 */ + else if (TIMx == TIM16) + { + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16); + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16); + } +#if defined(TIM17) + else if (TIMx == TIM17) + { + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17); + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17); + } +#endif /* TIM17 */ + else + { + result = ERROR; + } + + return result; +} + +/** + * @brief Set the fields of the time base unit configuration data structure + * to their default values. + * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure) + * @retval None + */ +void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct) +{ + /* Set the default configuration */ + TIM_InitStruct->Prescaler = (uint16_t)0x0000; + TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP; + TIM_InitStruct->Autoreload = 0xFFFFFFFFU; + TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; + TIM_InitStruct->RepetitionCounter = 0x00000000U; +} + +/** + * @brief Configure the TIMx time base unit. + * @param TIMx Timer Instance + * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure + * (TIMx time base unit configuration data structure) + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct) +{ + uint32_t tmpcr1; + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode)); + assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision)); + + tmpcr1 = LL_TIM_ReadReg(TIMx, CR1); + + if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) + { + /* Select the Counter Mode */ + MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode); + } + + if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) + { + /* Set the clock division */ + MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision); + } + + /* Write to TIMx CR1 */ + LL_TIM_WriteReg(TIMx, CR1, tmpcr1); + + /* Set the Autoreload value */ + LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload); + + /* Set the Prescaler value */ + LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler); + + if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) + { + /* Set the Repetition Counter value */ + LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter); + } + + /* Generate an update event to reload the Prescaler + and the repetition counter value (if applicable) immediately */ + LL_TIM_GenerateEvent_UPDATE(TIMx); + + return SUCCESS; +} + +/** + * @brief Set the fields of the TIMx output channel configuration data + * structure to their default values. + * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure + * (the output channel configuration data structure) + * @retval None + */ +void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct) +{ + /* Set the default configuration */ + TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN; + TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE; + TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE; + TIM_OC_InitStruct->CompareValue = 0x00000000U; + TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH; + TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH; + TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW; + TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW; +} + +/** + * @brief Configure the TIMx output channel. + * @param TIMx Timer Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration + * data structure) + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx output channel is initialized + * - ERROR: TIMx output channel is not initialized + */ +ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct) +{ + ErrorStatus result = ERROR; + + switch (Channel) + { + case LL_TIM_CHANNEL_CH1: + result = OC1Config(TIMx, TIM_OC_InitStruct); + break; + case LL_TIM_CHANNEL_CH2: + result = OC2Config(TIMx, TIM_OC_InitStruct); + break; + case LL_TIM_CHANNEL_CH3: + result = OC3Config(TIMx, TIM_OC_InitStruct); + break; + case LL_TIM_CHANNEL_CH4: + result = OC4Config(TIMx, TIM_OC_InitStruct); + break; + case LL_TIM_CHANNEL_CH5: + result = OC5Config(TIMx, TIM_OC_InitStruct); + break; + case LL_TIM_CHANNEL_CH6: + result = OC6Config(TIMx, TIM_OC_InitStruct); + break; + default: + break; + } + + return result; +} + +/** + * @brief Set the fields of the TIMx input channel configuration data + * structure to their default values. + * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration + * data structure) + * @retval None + */ +void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) +{ + /* Set the default configuration */ + TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING; + TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI; + TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1; + TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1; +} + +/** + * @brief Configure the TIMx input channel. + * @param TIMx Timer Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data + * structure) + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx output channel is initialized + * - ERROR: TIMx output channel is not initialized + */ +ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct) +{ + ErrorStatus result = ERROR; + + switch (Channel) + { + case LL_TIM_CHANNEL_CH1: + result = IC1Config(TIMx, TIM_IC_InitStruct); + break; + case LL_TIM_CHANNEL_CH2: + result = IC2Config(TIMx, TIM_IC_InitStruct); + break; + case LL_TIM_CHANNEL_CH3: + result = IC3Config(TIMx, TIM_IC_InitStruct); + break; + case LL_TIM_CHANNEL_CH4: + result = IC4Config(TIMx, TIM_IC_InitStruct); + break; + default: + break; + } + + return result; +} + +/** + * @brief Fills each TIM_EncoderInitStruct field with its default value + * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface + * configuration data structure) + * @retval None + */ +void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct) +{ + /* Set the default configuration */ + TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1; + TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING; + TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI; + TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1; + TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1; + TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING; + TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI; + TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1; + TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1; +} + +/** + * @brief Configure the encoder interface of the timer instance. + * @param TIMx Timer Instance + * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface + * configuration data structure) + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode)); + assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity)); + assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput)); + assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler)); + assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter)); + assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity)); + assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput)); + assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler)); + assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter)); + + /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */ + TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E); + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); + + /* Get the TIMx CCER register value */ + tmpccer = LL_TIM_ReadReg(TIMx, CCER); + + /* Configure TI1 */ + tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC); + tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U); + tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U); + tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U); + + /* Configure TI2 */ + tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC); + tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U); + tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U); + tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U); + + /* Set TI1 and TI2 polarity and enable TI1 and TI2 */ + tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP); + tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity); + tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U); + tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E); + + /* Set encoder mode */ + LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode); + + /* Write to TIMx CCMR1 */ + LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); + + /* Write to TIMx CCER */ + LL_TIM_WriteReg(TIMx, CCER, tmpccer); + + return SUCCESS; +} + +/** + * @brief Set the fields of the TIMx Hall sensor interface configuration data + * structure to their default values. + * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface + * configuration data structure) + * @retval None + */ +void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct) +{ + /* Set the default configuration */ + TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING; + TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1; + TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1; + TIM_HallSensorInitStruct->CommutationDelay = 0U; +} + +/** + * @brief Configure the Hall sensor interface of the timer instance. + * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR + * to the TI1 input channel + * @note TIMx slave mode controller is configured in reset mode. + Selected internal trigger is TI1F_ED. + * @note Channel 1 is configured as input, IC1 is mapped on TRC. + * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed + * between 2 changes on the inputs. It gives information about motor speed. + * @note Channel 2 is configured in output PWM 2 mode. + * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay. + * @note OC2REF is selected as trigger output on TRGO. + * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used + * when TIMx operates in Hall sensor interface mode. + * @param TIMx Timer Instance + * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor + * interface configuration data structure) + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct) +{ + uint32_t tmpcr2; + uint32_t tmpccmr1; + uint32_t tmpccer; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity)); + assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler)); + assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter)); + + /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */ + TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E); + + /* Get the TIMx CR2 register value */ + tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); + + /* Get the TIMx CCER register value */ + tmpccer = LL_TIM_ReadReg(TIMx, CCER); + + /* Get the TIMx SMCR register value */ + tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR); + + /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */ + tmpcr2 |= TIM_CR2_TI1S; + + /* OC2REF signal is used as trigger output (TRGO) */ + tmpcr2 |= LL_TIM_TRGO_OC2REF; + + /* Configure the slave mode controller */ + tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS); + tmpsmcr |= LL_TIM_TS_TI1F_ED; + tmpsmcr |= LL_TIM_SLAVEMODE_RESET; + + /* Configure input channel 1 */ + tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC); + tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U); + tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U); + tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U); + + /* Configure input channel 2 */ + tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE | TIM_CCMR1_OC2PE | TIM_CCMR1_OC2CE); + tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U); + + /* Set Channel 1 polarity and enable Channel 1 and Channel2 */ + tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP); + tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity); + tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E); + + /* Write to TIMx CR2 */ + LL_TIM_WriteReg(TIMx, CR2, tmpcr2); + + /* Write to TIMx SMCR */ + LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr); + + /* Write to TIMx CCMR1 */ + LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); + + /* Write to TIMx CCER */ + LL_TIM_WriteReg(TIMx, CCER, tmpccer); + + /* Write to TIMx CCR2 */ + LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay); + + return SUCCESS; +} + +/** + * @brief Set the fields of the Break and Dead Time configuration data structure + * to their default values. + * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration + * data structure) + * @retval None + */ +void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) +{ + /* Set the default configuration */ + TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE; + TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE; + TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF; + TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00; + TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE; + TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW; + TIM_BDTRInitStruct->BreakFilter = LL_TIM_BREAK_FILTER_FDIV1; + TIM_BDTRInitStruct->BreakAFMode = LL_TIM_BREAK_AFMODE_INPUT; + TIM_BDTRInitStruct->Break2State = LL_TIM_BREAK2_DISABLE; + TIM_BDTRInitStruct->Break2Polarity = LL_TIM_BREAK2_POLARITY_LOW; + TIM_BDTRInitStruct->Break2Filter = LL_TIM_BREAK2_FILTER_FDIV1; + TIM_BDTRInitStruct->Break2AFMode = LL_TIM_BREAK2_AFMODE_INPUT; + TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE; +} + +/** + * @brief Configure the Break and Dead Time feature of the timer instance. + * @note As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR + * and DTG[7:0] can be write-locked depending on the LOCK configuration, it + * can be necessary to configure all of them during the first write access to + * the TIMx_BDTR register. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a second break input. + * @param TIMx Timer Instance + * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration + * data structure) + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Break and Dead Time is initialized + * - ERROR: not applicable + */ +ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) +{ + uint32_t tmpbdtr = 0; + + /* Check the parameters */ + assert_param(IS_TIM_BREAK_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState)); + assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState)); + assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel)); + assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState)); + assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity)); + assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput)); + assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter)); + assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode)); + + /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, + the OSSI State, the dead time value and the Automatic Output Enable Bit */ + + /* Set the BDTR bits */ + MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime); + MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel); + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState); + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity); + MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, TIM_BDTRInitStruct->BreakAFMode); + + if (IS_TIM_BKIN2_INSTANCE(TIMx)) + { + assert_param(IS_LL_TIM_BREAK2_STATE(TIM_BDTRInitStruct->Break2State)); + assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity)); + assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter)); + assert_param(IS_LL_TIM_BREAK2_AFMODE(TIM_BDTRInitStruct->Break2AFMode)); + + /* Set the BREAK2 input related BDTR bit-fields */ + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (TIM_BDTRInitStruct->Break2Filter)); + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State); + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity); + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, TIM_BDTRInitStruct->Break2AFMode); + } + + /* Set TIMx_BDTR */ + LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr); + + return SUCCESS; +} +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup TIM_LL_Private_Functions TIM Private Functions + * @brief Private functions + * @{ + */ +/** + * @brief Configure the TIMx output channel 1. + * @param TIMx Timer Instance + * @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); + + /* Disable the Channel 1: Reset the CC1E Bit */ + CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E); + + /* Get the TIMx CCER register value */ + tmpccer = LL_TIM_ReadReg(TIMx, CCER); + + /* Get the TIMx CR2 register value */ + tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); + + /* Reset Capture/Compare selection Bits */ + CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S); + + /* Set the Output Compare Mode */ + MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode); + + /* Set the Output Compare Polarity */ + MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity); + + /* Set the Output State */ + MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); + + /* Set the complementary output Polarity */ + MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U); + + /* Set the complementary output State */ + MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U); + + /* Set the Output Idle state */ + MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState); + + /* Set the complementary output Idle state */ + MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U); + } + + /* Write to TIMx CR2 */ + LL_TIM_WriteReg(TIMx, CR2, tmpcr2); + + /* Write to TIMx CCMR1 */ + LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); + + /* Set the Capture Compare Register value */ + LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue); + + /* Write to TIMx CCER */ + LL_TIM_WriteReg(TIMx, CCER, tmpccer); + + return SUCCESS; +} + +/** + * @brief Configure the TIMx output channel 2. + * @param TIMx Timer Instance + * @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); + + /* Disable the Channel 2: Reset the CC2E Bit */ + CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E); + + /* Get the TIMx CCER register value */ + tmpccer = LL_TIM_ReadReg(TIMx, CCER); + + /* Get the TIMx CR2 register value */ + tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); + + /* Reset Capture/Compare selection Bits */ + CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S); + + /* Select the Output Compare Mode */ + MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U); + + /* Set the Output Compare Polarity */ + MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U); + + /* Set the Output State */ + MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); + + /* Set the complementary output Polarity */ + MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U); + + /* Set the complementary output State */ + MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U); + + /* Set the Output Idle state */ + MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U); + + /* Set the complementary output Idle state */ + MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U); + } + + /* Write to TIMx CR2 */ + LL_TIM_WriteReg(TIMx, CR2, tmpcr2); + + /* Write to TIMx CCMR1 */ + LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); + + /* Set the Capture Compare Register value */ + LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue); + + /* Write to TIMx CCER */ + LL_TIM_WriteReg(TIMx, CCER, tmpccer); + + return SUCCESS; +} + +/** + * @brief Configure the TIMx output channel 3. + * @param TIMx Timer Instance + * @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +{ + uint32_t tmpccmr2; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); + + /* Disable the Channel 3: Reset the CC3E Bit */ + CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E); + + /* Get the TIMx CCER register value */ + tmpccer = LL_TIM_ReadReg(TIMx, CCER); + + /* Get the TIMx CR2 register value */ + tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); + + /* Get the TIMx CCMR2 register value */ + tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); + + /* Reset Capture/Compare selection Bits */ + CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S); + + /* Select the Output Compare Mode */ + MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode); + + /* Set the Output Compare Polarity */ + MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U); + + /* Set the Output State */ + MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); + + /* Set the complementary output Polarity */ + MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U); + + /* Set the complementary output State */ + MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U); + + /* Set the Output Idle state */ + MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U); + + /* Set the complementary output Idle state */ + MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U); + } + + /* Write to TIMx CR2 */ + LL_TIM_WriteReg(TIMx, CR2, tmpcr2); + + /* Write to TIMx CCMR2 */ + LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); + + /* Set the Capture Compare Register value */ + LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue); + + /* Write to TIMx CCER */ + LL_TIM_WriteReg(TIMx, CCER, tmpccer); + + return SUCCESS; +} + +/** + * @brief Configure the TIMx output channel 4. + * @param TIMx Timer Instance + * @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +{ + uint32_t tmpccmr2; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); + + /* Disable the Channel 4: Reset the CC4E Bit */ + CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E); + + /* Get the TIMx CCER register value */ + tmpccer = LL_TIM_ReadReg(TIMx, CCER); + + /* Get the TIMx CR2 register value */ + tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); + + /* Get the TIMx CCMR2 register value */ + tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); + + /* Reset Capture/Compare selection Bits */ + CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S); + + /* Select the Output Compare Mode */ + MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U); + + /* Set the Output Compare Polarity */ + MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U); + + /* Set the Output State */ + MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); + + /* Set the complementary output Polarity */ + MODIFY_REG(tmpccer, TIM_CCER_CC4NP, TIM_OCInitStruct->OCNPolarity << 14U); + + /* Set the complementary output State */ + MODIFY_REG(tmpccer, TIM_CCER_CC4NE, TIM_OCInitStruct->OCNState << 14U); + + /* Set the Output Idle state */ + MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U); + + /* Set the complementary output Idle state */ + MODIFY_REG(tmpcr2, TIM_CR2_OIS4N, TIM_OCInitStruct->OCNIdleState << 7U); + } + + /* Write to TIMx CR2 */ + LL_TIM_WriteReg(TIMx, CR2, tmpcr2); + + /* Write to TIMx CCMR2 */ + LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); + + /* Set the Capture Compare Register value */ + LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue); + + /* Write to TIMx CCER */ + LL_TIM_WriteReg(TIMx, CCER, tmpccer); + + return SUCCESS; +} + +/** + * @brief Configure the TIMx output channel 5. + * @param TIMx Timer Instance + * @param TIM_OCInitStruct pointer to the the TIMx output channel 5 configuration data structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +{ + uint32_t tmpccmr3; + uint32_t tmpccer; + + /* Check the parameters */ + assert_param(IS_TIM_CC5_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + + /* Disable the Channel 5: Reset the CC5E Bit */ + CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E); + + /* Get the TIMx CCER register value */ + tmpccer = LL_TIM_ReadReg(TIMx, CCER); + + /* Get the TIMx CCMR3 register value */ + tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3); + + /* Select the Output Compare Mode */ + MODIFY_REG(tmpccmr3, TIM_CCMR3_OC5M, TIM_OCInitStruct->OCMode); + + /* Set the Output Compare Polarity */ + MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U); + + /* Set the Output State */ + MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + + /* Set the Output Idle state */ + MODIFY_REG(TIMx->CR2, TIM_CR2_OIS5, TIM_OCInitStruct->OCIdleState << 8U); + + } + + /* Write to TIMx CCMR3 */ + LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3); + + /* Set the Capture Compare Register value */ + LL_TIM_OC_SetCompareCH5(TIMx, TIM_OCInitStruct->CompareValue); + + /* Write to TIMx CCER */ + LL_TIM_WriteReg(TIMx, CCER, tmpccer); + + return SUCCESS; +} + +/** + * @brief Configure the TIMx output channel 6. + * @param TIMx Timer Instance + * @param TIM_OCInitStruct pointer to the the TIMx output channel 6 configuration data structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +{ + uint32_t tmpccmr3; + uint32_t tmpccer; + + /* Check the parameters */ + assert_param(IS_TIM_CC6_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + + /* Disable the Channel 5: Reset the CC6E Bit */ + CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E); + + /* Get the TIMx CCER register value */ + tmpccer = LL_TIM_ReadReg(TIMx, CCER); + + /* Get the TIMx CCMR3 register value */ + tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3); + + /* Select the Output Compare Mode */ + MODIFY_REG(tmpccmr3, TIM_CCMR3_OC6M, TIM_OCInitStruct->OCMode << 8U); + + /* Set the Output Compare Polarity */ + MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U); + + /* Set the Output State */ + MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + + /* Set the Output Idle state */ + MODIFY_REG(TIMx->CR2, TIM_CR2_OIS6, TIM_OCInitStruct->OCIdleState << 10U); + } + + /* Write to TIMx CCMR3 */ + LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3); + + /* Set the Capture Compare Register value */ + LL_TIM_OC_SetCompareCH6(TIMx, TIM_OCInitStruct->CompareValue); + + /* Write to TIMx CCER */ + LL_TIM_WriteReg(TIMx, CCER, tmpccer); + + return SUCCESS; +} + +/** + * @brief Configure the TIMx input channel 1. + * @param TIMx Timer Instance + * @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) +{ + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); + assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); + assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); + assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); + + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E; + + /* Select the Input and set the filter and the prescaler value */ + MODIFY_REG(TIMx->CCMR1, + (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC), + (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U); + + /* Select the Polarity and set the CC1E Bit */ + MODIFY_REG(TIMx->CCER, + (TIM_CCER_CC1P | TIM_CCER_CC1NP), + (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E)); + + return SUCCESS; +} + +/** + * @brief Configure the TIMx input channel 2. + * @param TIMx Timer Instance + * @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) +{ + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); + assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); + assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); + assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E; + + /* Select the Input and set the filter and the prescaler value */ + MODIFY_REG(TIMx->CCMR1, + (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC), + (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U); + + /* Select the Polarity and set the CC2E Bit */ + MODIFY_REG(TIMx->CCER, + (TIM_CCER_CC2P | TIM_CCER_CC2NP), + ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E)); + + return SUCCESS; +} + +/** + * @brief Configure the TIMx input channel 3. + * @param TIMx Timer Instance + * @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) +{ + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); + assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); + assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); + assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); + + /* Disable the Channel 3: Reset the CC3E Bit */ + TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E; + + /* Select the Input and set the filter and the prescaler value */ + MODIFY_REG(TIMx->CCMR2, + (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC), + (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U); + + /* Select the Polarity and set the CC3E Bit */ + MODIFY_REG(TIMx->CCER, + (TIM_CCER_CC3P | TIM_CCER_CC3NP), + ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E)); + + return SUCCESS; +} + +/** + * @brief Configure the TIMx input channel 4. + * @param TIMx Timer Instance + * @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) +{ + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); + assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); + assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); + assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E; + + /* Select the Input and set the filter and the prescaler value */ + MODIFY_REG(TIMx->CCMR2, + (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC), + (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U); + + /* Select the Polarity and set the CC4E Bit */ + MODIFY_REG(TIMx->CCER, + (TIM_CCER_CC4P | TIM_CCER_CC4NP), + ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E)); + + return SUCCESS; +} + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* TIM1 || TIM2 || TIM3 || TIM6 || TIM7 */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_usart.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_usart.c new file mode 100644 index 0000000000..d35267a88c --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_usart.c @@ -0,0 +1,392 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_ll_usart.c + * @author MCD Application Team + * @brief USART LL module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_ll_usart.h" +#include "stm32wbaxx_ll_rcc.h" +#include "stm32wbaxx_ll_bus.h" +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +/** @addtogroup STM32WBAxx_LL_Driver + * @{ + */ + +#if defined(USART1) || defined(USART2) + +/** @addtogroup USART_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup USART_LL_Private_Constants + * @{ + */ + +/* Definition of default baudrate value used for USART initialisation */ +#define USART_DEFAULT_BAUDRATE (9600U) + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup USART_LL_Private_Macros + * @{ + */ + +#define IS_LL_USART_PRESCALER(__VALUE__) (((__VALUE__) == LL_USART_PRESCALER_DIV1) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV2) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV4) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV6) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV8) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV10) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV12) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV16) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV32) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV64) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV128) \ + || ((__VALUE__) == LL_USART_PRESCALER_DIV256)) + +/* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available + * divided by the smallest oversampling used on the USART (i.e. 8) */ +#define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 12500000U) + +/* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */ +#define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U) + +#define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \ + || ((__VALUE__) == LL_USART_DIRECTION_RX) \ + || ((__VALUE__) == LL_USART_DIRECTION_TX) \ + || ((__VALUE__) == LL_USART_DIRECTION_TX_RX)) + +#define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \ + || ((__VALUE__) == LL_USART_PARITY_EVEN) \ + || ((__VALUE__) == LL_USART_PARITY_ODD)) + +#define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_7B) \ + || ((__VALUE__) == LL_USART_DATAWIDTH_8B) \ + || ((__VALUE__) == LL_USART_DATAWIDTH_9B)) + +#define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \ + || ((__VALUE__) == LL_USART_OVERSAMPLING_8)) + +#define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \ + || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT)) + +#define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \ + || ((__VALUE__) == LL_USART_PHASE_2EDGE)) + +#define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \ + || ((__VALUE__) == LL_USART_POLARITY_HIGH)) + +#define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \ + || ((__VALUE__) == LL_USART_CLOCK_ENABLE)) + +#define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \ + || ((__VALUE__) == LL_USART_STOPBITS_1) \ + || ((__VALUE__) == LL_USART_STOPBITS_1_5) \ + || ((__VALUE__) == LL_USART_STOPBITS_2)) + +#define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \ + || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \ + || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \ + || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS)) + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup USART_LL_Exported_Functions + * @{ + */ + +/** @addtogroup USART_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize USART registers (Registers restored to their default values). + * @param USARTx USART Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: USART registers are de-initialized + * - ERROR: USART registers are not de-initialized + */ +ErrorStatus LL_USART_DeInit(const USART_TypeDef *USARTx) +{ + ErrorStatus status = SUCCESS; + + /* Check the parameters */ + assert_param(IS_UART_INSTANCE(USARTx)); + + if (USARTx == USART1) + { + /* Force reset of USART clock */ + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1); + + /* Release reset of USART clock */ + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1); + } +#if defined(USART2) + else if (USARTx == USART2) + { + /* Force reset of USART clock */ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2); + + /* Release reset of USART clock */ + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2); + } +#endif /* USART2 */ + else + { + status = ERROR; + } + + return (status); +} + +/** + * @brief Initialize USART registers according to the specified + * parameters in USART_InitStruct. + * @note As some bits in USART configuration registers can only be written when + * the USART is disabled (USART_CR1_UE bit =0), USART Peripheral should be in disabled state prior calling + * this function. Otherwise, ERROR result will be returned. + * @note Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0). + * @param USARTx USART Instance + * @param USART_InitStruct pointer to a LL_USART_InitTypeDef structure + * that contains the configuration information for the specified USART peripheral. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: USART registers are initialized according to USART_InitStruct content + * - ERROR: Problem occurred during USART Registers initialization + */ +ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, const LL_USART_InitTypeDef *USART_InitStruct) +{ + ErrorStatus status = ERROR; + uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check the parameters */ + assert_param(IS_UART_INSTANCE(USARTx)); + assert_param(IS_LL_USART_PRESCALER(USART_InitStruct->PrescalerValue)); + assert_param(IS_LL_USART_BAUDRATE(USART_InitStruct->BaudRate)); + assert_param(IS_LL_USART_DATAWIDTH(USART_InitStruct->DataWidth)); + assert_param(IS_LL_USART_STOPBITS(USART_InitStruct->StopBits)); + assert_param(IS_LL_USART_PARITY(USART_InitStruct->Parity)); + assert_param(IS_LL_USART_DIRECTION(USART_InitStruct->TransferDirection)); + assert_param(IS_LL_USART_HWCONTROL(USART_InitStruct->HardwareFlowControl)); + assert_param(IS_LL_USART_OVERSAMPLING(USART_InitStruct->OverSampling)); + + /* USART needs to be in disabled state, in order to be able to configure some bits in + CRx registers */ + if (LL_USART_IsEnabled(USARTx) == 0U) + { + /*---------------------------- USART CR1 Configuration --------------------- + * Configure USARTx CR1 (USART Word Length, Parity, Mode and Oversampling bits) with parameters: + * - DataWidth: USART_CR1_M bits according to USART_InitStruct->DataWidth value + * - Parity: USART_CR1_PCE, USART_CR1_PS bits according to USART_InitStruct->Parity value + * - TransferDirection: USART_CR1_TE, USART_CR1_RE bits according to USART_InitStruct->TransferDirection value + * - Oversampling: USART_CR1_OVER8 bit according to USART_InitStruct->OverSampling value. + */ + MODIFY_REG(USARTx->CR1, + (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | + USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8), + (USART_InitStruct->DataWidth | USART_InitStruct->Parity | + USART_InitStruct->TransferDirection | USART_InitStruct->OverSampling)); + + /*---------------------------- USART CR2 Configuration --------------------- + * Configure USARTx CR2 (Stop bits) with parameters: + * - Stop Bits: USART_CR2_STOP bits according to USART_InitStruct->StopBits value. + * - CLKEN, CPOL, CPHA and LBCL bits are to be configured using LL_USART_ClockInit(). + */ + LL_USART_SetStopBitsLength(USARTx, USART_InitStruct->StopBits); + + /*---------------------------- USART CR3 Configuration --------------------- + * Configure USARTx CR3 (Hardware Flow Control) with parameters: + * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to + * USART_InitStruct->HardwareFlowControl value. + */ + LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl); + + /*---------------------------- USART BRR Configuration --------------------- + * Retrieve Clock frequency used for USART Peripheral + */ + if (USARTx == USART1) + { + periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART1_CLKSOURCE); + } +#if defined(USART2) + else if (USARTx == USART2) + { + periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART2_CLKSOURCE); + } +#endif /* USART2 */ + else + { + /* Nothing to do, as error code is already assigned to ERROR value */ + } + + /* Configure the USART Baud Rate : + - prescaler value is required + - valid baud rate value (different from 0) is required + - Peripheral clock as returned by RCC service, should be valid (different from 0). + */ + if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO) + && (USART_InitStruct->BaudRate != 0U)) + { + status = SUCCESS; + LL_USART_SetBaudRate(USARTx, + periphclk, + USART_InitStruct->PrescalerValue, + USART_InitStruct->OverSampling, + USART_InitStruct->BaudRate); + + /* Check BRR is greater than or equal to 16d */ + assert_param(IS_LL_USART_BRR_MIN(USARTx->BRR)); + } + + /*---------------------------- USART PRESC Configuration ----------------------- + * Configure USARTx PRESC (Prescaler) with parameters: + * - PrescalerValue: USART_PRESC_PRESCALER bits according to USART_InitStruct->PrescalerValue value. + */ + LL_USART_SetPrescaler(USARTx, USART_InitStruct->PrescalerValue); + } + /* Endif (=> USART not in Disabled state => return ERROR) */ + + return (status); +} + +/** + * @brief Set each @ref LL_USART_InitTypeDef field to default value. + * @param USART_InitStruct pointer to a @ref LL_USART_InitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ + +void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct) +{ + /* Set USART_InitStruct fields to default values */ + USART_InitStruct->PrescalerValue = LL_USART_PRESCALER_DIV1; + USART_InitStruct->BaudRate = USART_DEFAULT_BAUDRATE; + USART_InitStruct->DataWidth = LL_USART_DATAWIDTH_8B; + USART_InitStruct->StopBits = LL_USART_STOPBITS_1; + USART_InitStruct->Parity = LL_USART_PARITY_NONE ; + USART_InitStruct->TransferDirection = LL_USART_DIRECTION_TX_RX; + USART_InitStruct->HardwareFlowControl = LL_USART_HWCONTROL_NONE; + USART_InitStruct->OverSampling = LL_USART_OVERSAMPLING_16; +} + +/** + * @brief Initialize USART Clock related settings according to the + * specified parameters in the USART_ClockInitStruct. + * @note As some bits in USART configuration registers can only be written when + * the USART is disabled (USART_CR1_UE bit =0), USART Peripheral should be in disabled state prior calling + * this function. Otherwise, ERROR result will be returned. + * @param USARTx USART Instance + * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure + * that contains the Clock configuration information for the specified USART peripheral. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: USART registers related to Clock settings are initialized according + * to USART_ClockInitStruct content + * - ERROR: Problem occurred during USART Registers initialization + */ +ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, const LL_USART_ClockInitTypeDef *USART_ClockInitStruct) +{ + ErrorStatus status = SUCCESS; + + /* Check USART Instance and Clock signal output parameters */ + assert_param(IS_UART_INSTANCE(USARTx)); + assert_param(IS_LL_USART_CLOCKOUTPUT(USART_ClockInitStruct->ClockOutput)); + + /* USART needs to be in disabled state, in order to be able to configure some bits in + CRx registers */ + if (LL_USART_IsEnabled(USARTx) == 0U) + { + /* Ensure USART instance is USART capable */ + assert_param(IS_USART_INSTANCE(USARTx)); + + /* Check clock related parameters */ + assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity)); + assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase)); + assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse)); + + /*---------------------------- USART CR2 Configuration ----------------------- + * Configure USARTx CR2 (Clock signal related bits) with parameters: + * - Clock Output: USART_CR2_CLKEN bit according to USART_ClockInitStruct->ClockOutput value + * - Clock Polarity: USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value + * - Clock Phase: USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value + * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value. + */ + MODIFY_REG(USARTx->CR2, + USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, + USART_ClockInitStruct->ClockOutput | USART_ClockInitStruct->ClockPolarity | + USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse); + } + /* Else (USART not in Disabled state => return ERROR */ + else + { + status = ERROR; + } + + return (status); +} + +/** + * @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value. + * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ +void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct) +{ + /* Set LL_USART_ClockInitStruct fields with default values */ + USART_ClockInitStruct->ClockOutput = LL_USART_CLOCK_DISABLE; + USART_ClockInitStruct->ClockPolarity = LL_USART_POLARITY_LOW; /* Not relevant when ClockOutput = + LL_USART_CLOCK_DISABLE */ + USART_ClockInitStruct->ClockPhase = LL_USART_PHASE_1EDGE; /* Not relevant when ClockOutput = + LL_USART_CLOCK_DISABLE */ + USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT; /* Not relevant when ClockOutput = + LL_USART_CLOCK_DISABLE */ +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* USART1 || USART2 */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_utils.c b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_utils.c new file mode 100644 index 0000000000..6ecdcb0a73 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/Src/stm32wbaxx_ll_utils.c @@ -0,0 +1,622 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_ll_utils.c + * @author MCD Application Team + * @brief UTILS LL module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* Includes ------------------------------------------------------------------*/ +#include "stm32wbaxx_ll_utils.h" +#include "stm32wbaxx_ll_rcc.h" +#include "stm32wbaxx_ll_system.h" +#include "stm32wbaxx_ll_pwr.h" +#include +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +/** @addtogroup STM32WBAxx_LL_Driver + * @{ + */ + +/** @addtogroup UTILS_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup UTILS_LL_Private_Constants + * @{ + */ +#define UTILS_MAX_FREQUENCY_SCALE1 100000000U /*!< Maximum frequency for system clock at power scale1, in Hz */ +#define UTILS_MAX_FREQUENCY_SCALE2 16000000U /*!< Maximum frequency for system clock at power scale2, in Hz */ + +/* Defines used for PLL range */ +#define UTILS_PLLVCO_INPUT_MIN 4000000U /*!< Frequency min for PLLVCO input, in Hz */ +#define UTILS_PLLVCO_INPUT_MAX 16000000U /*!< Frequency max for PLLVCO input, in Hz */ +#define UTILS_PLLVCO_OUTPUT_MIN 128000000U /*!< Frequency min for PLLVCO output, in Hz */ +#define UTILS_PLLVCO_OUTPUT_MAX 544000000U /*!< Frequency max for PLLVCO output, in Hz */ + +/* Defines used for FLASH latency according to HCLK Frequency */ +#define UTILS_SCALE1_LATENCY0_FREQ 32000000U /*!< HCLK frequency to set FLASH latency 0 in power scale 1 */ +#define UTILS_SCALE1_LATENCY1_FREQ 64000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */ +#define UTILS_SCALE1_LATENCY2_FREQ 96000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */ +#define UTILS_SCALE1_LATENCY3_FREQ 100000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */ +#define UTILS_SCALE2_LATENCY0_FREQ 8000000U /*!< HCLK frequency to set FLASH latency 0 in power scale 2 */ +#define UTILS_SCALE2_LATENCY1_FREQ 16000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup UTILS_LL_Private_Macros + * @{ + */ +#define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16)) + +#define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \ + || ((__VALUE__) == LL_RCC_APB1_DIV_2) \ + || ((__VALUE__) == LL_RCC_APB1_DIV_4) \ + || ((__VALUE__) == LL_RCC_APB1_DIV_8) \ + || ((__VALUE__) == LL_RCC_APB1_DIV_16)) + +#define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \ + || ((__VALUE__) == LL_RCC_APB2_DIV_2) \ + || ((__VALUE__) == LL_RCC_APB2_DIV_4) \ + || ((__VALUE__) == LL_RCC_APB2_DIV_8) \ + || ((__VALUE__) == LL_RCC_APB2_DIV_16)) + +#define IS_LL_UTILS_APB7_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB7_DIV_1) \ + || ((__VALUE__) == LL_RCC_APB7_DIV_2) \ + || ((__VALUE__) == LL_RCC_APB7_DIV_4) \ + || ((__VALUE__) == LL_RCC_APB7_DIV_8) \ + || ((__VALUE__) == LL_RCC_APB7_DIV_16)) + +#define IS_LL_UTILS_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 16U)) + +#define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((4U <= (__VALUE__)) && ((__VALUE__) <= 512U)) + +#define IS_LL_UTILS_PLLR_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 128U)) + +#define IS_LL_UTILS_PLLVCO_INPUT(__VALUE__) ((UTILS_PLLVCO_INPUT_MIN <= (__VALUE__))\ + && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX)) + +#define IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__) ((UTILS_PLLVCO_OUTPUT_MIN <= (__VALUE__))\ + && ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_MAX)) + +#define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? \ + ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \ + ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2)) + +#define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) ((__FREQUENCY__) == 32000000U) +/** + * @} + */ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup UTILS_LL_Private_Functions UTILS Private functions + * @{ + */ +static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, + const LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct); +static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, + LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); +static ErrorStatus UTILS_PLL_IsBusy(void); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup UTILS_LL_Exported_Functions + * @{ + */ + +/** @addtogroup UTILS_LL_EF_DELAY + * @{ + */ + +/** + * @brief This function configures the Cortex-M SysTick source to have 1ms time base with HCLK as SysTick clock source. + * @note When a RTOS is used, it is recommended to avoid changing the Systick + * configuration by calling this function, for a delay use rather osDelay RTOS service. + * @param HCLKFrequency HCLK frequency in Hz + * @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq + * @retval None + */ +void LL_Init1msTick(uint32_t HCLKFrequency) +{ + /* Use frequency provided in argument */ + LL_InitTick(HCLKFrequency, 1000U); +} + +/** + * @brief This function configures the Cortex-M SysTick source to have 1ms time base with HCLK/8 as SysTick clock source. + * @note When a RTOS is used, it is recommended to avoid changing the Systick + * configuration by calling this function, for a delay use rather osDelay RTOS service. + * @param HCLKFrequency HCLK frequency in Hz + * @retval None + */ +void LL_Init1msTick_HCLK_Div8(uint32_t HCLKFrequency) +{ + /* Configure the SysTick to have 1ms time base with HCLK/8 as SysTick clock source */ + SysTick->LOAD = (uint32_t)((HCLKFrequency / 8000U) - 1UL); + SysTick->VAL = 0UL; + SysTick->CTRL = SysTick_CTRL_ENABLE_Msk; +} + +/** + * @brief This function configures the Cortex-M SysTick source to have 1ms time base with LSE as SysTick clock source. + * @note When a RTOS is used, it is recommended to avoid changing the Systick + * configuration by calling this function, for a delay use rather osDelay RTOS service. + * @retval None + */ +void LL_Init1msTick_LSE(void) +{ + /* Configure the SysTick to have 1ms time base with LSE as SysTick clock source */ + SysTick->LOAD = (uint32_t)((LSE_VALUE / 1000U) - 1UL); + SysTick->VAL = 0UL; + SysTick->CTRL = SysTick_CTRL_ENABLE_Msk; +} + +/** + * @brief This function configures the Cortex-M SysTick source to have 1ms time base with LSI as SysTick clock source. + * @note When a RTOS is used, it is recommended to avoid changing the Systick + * configuration by calling this function, for a delay use rather osDelay RTOS service. + * @retval None + */ +void LL_Init1msTick_LSI(void) +{ + /* Configure the SysTick to have 1ms time base with LSI as SysTick clock source */ + SysTick->LOAD = (uint32_t)((LSI_VALUE / 1000U) - 1UL); + SysTick->VAL = 0UL; + SysTick->CTRL = SysTick_CTRL_ENABLE_Msk; +} + +/** + * @brief This function provides minimum delay (in milliseconds) based + * on SysTick counter flag + * @note When a RTOS is used, it is recommended to avoid using blocking delay + * and use rather osDelay service. + * @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which + * will configure Systick to 1ms + * @param Delay specifies the minimum delay time length, in milliseconds. + * @retval None + */ +void LL_mDelay(uint32_t Delay) +{ + __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */ + uint32_t tmpDelay = Delay; + + /* Add this code to indicate that local variable is not used */ + ((void)tmp); + + /* Add a period to guaranty minimum wait */ + if (tmpDelay < LL_MAX_DELAY) + { + tmpDelay++; + } + + while (tmpDelay != 0U) + { + if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U) + { + tmpDelay--; + } + } +} + +/** + * @} + */ + +/** @addtogroup UTILS_EF_SYSTEM + * @brief System Configuration functions + * + @verbatim + =============================================================================== + ##### System Configuration functions ##### + =============================================================================== + [..] + System, AHB and APB buses clocks configuration + + (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2, PCLK7 is + 100000000 Hz. + @endverbatim + @internal + Depending on the device voltage range, the maximum frequency should be + adapted accordingly: + + (++) Table 1. HCLK clock frequency for STM32WBA devices + (++) +----------------------------------------------------------+ + (++) | Latency | HCLK clock frequency (MHz) | + (++) | |--------------------------------------| + (++) | | voltage range 1 | voltage range 2 | + (++) | | 1.2 V | 1.1 V | + (++) |-------------------|-------------------|------------------| + (++) |0 WS (1 CPU cycles)| 0 < HCLK <= 32 | 0 < HCLK <= 8 | + (++) |-------------------|-------------------|------------------| + (++) |1 WS (2 CPU cycles)| 32 < HCLK <= 64 | 25 < HCLK <= 16 | + (++) |-------------------|-------------------|------------------| + (++) |2 WS (3 CPU cycles)| 64 < HCLK <= 96 | 50 < HCLK <= 24 | + (++) |-------------------|-------------------|------------------| + (++) |3 WS (4 CPU cycles)| 96 < HCLK <= 100 | + (++) |-------------------|-------------------| + + + @endinternal + * @{ + */ + +/** + * @brief This function sets directly SystemCoreClock CMSIS variable. + * @note Variable can be calculated also through SystemCoreClockUpdate function. + * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro) + * @retval None + */ +void LL_SetSystemCoreClock(uint32_t HCLKFrequency) +{ + /* HCLK clock frequency */ + SystemCoreClock = HCLKFrequency; +} + + + +/** + * @brief This function configures system clock at maximum frequency with HSI as clock source of the PLL + * @note The application need to ensure that PLL1, PLL2 and/or PLL3 are disabled. + * @note Function is based on the following formula: + * - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLR) + * - PLL1M: ensure that the VCO input frequency ranges from 4 to 16 MHz (PLL1VCO_input = HSI frequency / PLL1M) + * - PLL1N: ensure that the VCO output frequency is between 128 and 544 MHz + (PLL1VCO_output = PLL1VCO_input * PLL1N) + * - PLL1R: ensure that max frequency at 100 MHz is reached (PLL1VCO_output / PLL1R) + * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains + * the configuration information for the PLL. + * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains + * the configuration information for the BUS prescalers. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Max frequency configuration done + * - ERROR: Max frequency configuration not done + */ +ErrorStatus LL_PLL1_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, + LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) +{ + ErrorStatus status; + uint32_t pllfreq; + + /* Check if one of the PLL is enabled */ + if (UTILS_PLL_IsBusy() == SUCCESS) + { + /* Calculate the new PLL output frequency */ + pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct); + + /* Enable HSI if not enabled */ + if (LL_RCC_HSI_IsReady() != 1U) + { + LL_RCC_HSI_Enable(); + while (LL_RCC_HSI_IsReady() != 1U) + { + /* Wait for HSI ready */ + } + } + + /* Configure PLL */ + LL_RCC_PLL1_ConfigDomain_SYS(LL_RCC_PLL1SOURCE_HSI, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, + UTILS_PLLInitStruct->PLLR); + + /* Enable PLL and switch system clock to PLL */ + status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); + } + else + { + /* Current PLL configuration cannot be modified */ + status = ERROR; + } + + return status; +} + +/** + * @brief This function configures system clock with HSE as clock source of the PLL + * @note The application need to ensure that PLL, PLLSAI1 and/or PLLSAI2 are disabled. + * @note Function is based on the following formula: + * - PLL output frequency = (((HSE frequency / PLLM) * PLLN) / PLLR) + * - PLL1M: ensure that the VCO input frequency ranges from 4 to 16 MHz (PLL1VCO_input = HSE frequency / PLL1M) + * - PLL1N: ensure that the VCO output frequency is between 128 and 544 MHz + (PLL1VCO_output = PLL1VCO_input * PLL1N) + * - PLL1R: ensure that max frequency at 100 MHz is reached (PLL1VCO_output / PLL1R) + * @param HSEFrequency Value at 32000000 + * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains + * the configuration information for the PLL. + * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains + * the configuration information for the BUS prescalers. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Max frequency configuration done + * - ERROR: Max frequency configuration not done + */ +ErrorStatus LL_PLL1_ConfigSystemClock_HSE(uint32_t HSEFrequency, + LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, + LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) +{ + ErrorStatus status; + uint32_t pllfreq; + + /* Check the parameters */ + assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency)); + + /* Check if one of the PLL is enabled */ + if (UTILS_PLL_IsBusy() == SUCCESS) + { + /* Calculate the new PLL output frequency */ + pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct); + + /* Enable HSE if not enabled */ + if (LL_RCC_HSE_IsReady() != 1U) + { + /* Enable HSE */ + LL_RCC_HSE_Enable(); + while (LL_RCC_HSE_IsReady() != 1U) + { + /* Wait for HSE ready */ + } + } + + /* Configure PLL */ + LL_RCC_PLL1_ConfigDomain_SYS(LL_RCC_PLL1SOURCE_HSE, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, + UTILS_PLLInitStruct->PLLR); + + /* Enable PLL and switch system clock to PLL */ + status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); + } + else + { + /* Current PLL configuration cannot be modified */ + status = ERROR; + } + + return status; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @brief Update number of Flash wait states in line with new frequency and current + voltage range. + * @param HCLK_Frequency HCLK frequency + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Latency has been modified + * - ERROR: Latency cannot be modified + */ +ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency) +{ + ErrorStatus status = SUCCESS; + uint32_t latency; + + /* Frequency cannot be equal to 0 */ + if (HCLK_Frequency == 0U) + { + status = ERROR; + } + else + { + if (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) + { + if ((HCLK_Frequency > UTILS_SCALE1_LATENCY2_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY3_FREQ)) + { + /* 96MHz < HCLK <= 100MHz => 3WS (4 CPU cycles) */ + latency = LL_FLASH_LATENCY_3; + } + else if ((HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY2_FREQ)) + { + /* 64MHz < HCLK <= 96MHz => 2WS (3 CPU cycles) */ + latency = LL_FLASH_LATENCY_2; + } + else if ((HCLK_Frequency > UTILS_SCALE1_LATENCY0_FREQ) && (HCLK_Frequency <= UTILS_SCALE1_LATENCY1_FREQ)) + { + /* 32MHz < HCLK <= 64MHz => 1WS (2 CPU cycles) */ + latency = LL_FLASH_LATENCY_1; + } + else if (HCLK_Frequency <= UTILS_SCALE1_LATENCY0_FREQ) + { + /* HCLK <= 32MHz => 0WS (1 CPU cycle) */ + latency = LL_FLASH_LATENCY_0; + } + else + { + status = ERROR; + } + } + else /* LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2 */ + { + if ((HCLK_Frequency > UTILS_SCALE2_LATENCY0_FREQ) && (HCLK_Frequency <= UTILS_SCALE2_LATENCY1_FREQ)) + { + /* 8MHz < HCLK <= 16MHz => 1WS (2 CPU cycles) */ + latency = LL_FLASH_LATENCY_1; + } + else if (HCLK_Frequency <= UTILS_SCALE2_LATENCY0_FREQ) + { + /* HCLK <= 8MHz => 0WS (1 CPU cycle) */ + latency = LL_FLASH_LATENCY_0; + } + else + { + status = ERROR; + } + } + } + + if (status == SUCCESS) + { + LL_FLASH_SetLatency(latency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if (LL_FLASH_GetLatency() != latency) + { + status = ERROR; + } + } + + return status; +} + +/** @addtogroup UTILS_LL_Private_Functions + * @{ + */ +/** + * @brief Function to check that PLL can be modified + * @param PLL_InputFrequency PLL input frequency (in Hz) + * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains + * the configuration information for the PLL. + * @retval PLL output frequency (in Hz) + */ +static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, const LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct) +{ + uint32_t pllfreq; + + /* Check the parameters */ + assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM)); + assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN)); + assert_param(IS_LL_UTILS_PLLR_VALUE(UTILS_PLLInitStruct->PLLR)); + + /* Check different PLL parameters according to RM */ + /* - PLLM: ensure that the VCO input frequency ranges from 4 to 16 MHz. */ + pllfreq = PLL_InputFrequency / (UTILS_PLLInitStruct->PLLM); + assert_param(IS_LL_UTILS_PLLVCO_INPUT(pllfreq)); + + /* - PLLN: ensure that the VCO output frequency is between 128 and 544 MHz.*/ + pllfreq = pllfreq * (UTILS_PLLInitStruct->PLLN); + assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(pllfreq)); + + /* - PLLR: ensure that max frequency at 100 MHz is reached */ + pllfreq = pllfreq / (UTILS_PLLInitStruct->PLLR); + assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq)); + + return pllfreq; +} + +/** + * @brief Function to check that PLL can be modified + * @retval An ErrorStatus enumeration value: + * - SUCCESS: PLL modification can be done + * - ERROR: PLL is busy + */ +static ErrorStatus UTILS_PLL_IsBusy(void) +{ + ErrorStatus status = SUCCESS; + + /* Check if PLL1 is busy*/ + if (LL_RCC_PLL1_IsReady() != 0U) + { + /* PLL configuration cannot be modified */ + status = ERROR; + } + + return status; +} + +/** + * @brief Function to enable PLL and switch system clock to PLL + * @param SYSCLK_Frequency SYSCLK frequency + * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains + * the configuration information for the BUS prescalers. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: No problem to switch system to PLL + * - ERROR: Problem to switch system to PLL + */ +static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, + LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) +{ + ErrorStatus status = SUCCESS; + uint32_t hclk_frequency; + + assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider)); + assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider)); + assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider)); + assert_param(IS_LL_UTILS_APB7_DIV(UTILS_ClkInitStruct->APB7CLKDivider)); + + /* Calculate HCLK frequency */ + hclk_frequency = __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider); + + /* Increasing the number of wait states because of higher CPU frequency */ + if (SystemCoreClock < hclk_frequency) + { + /* Set FLASH latency to highest latency */ + status = LL_SetFlashLatency(hclk_frequency); + } + + /* Update system clock configuration */ + if (status == SUCCESS) + { + /* Enable PLL1 */ + LL_RCC_PLL1_Enable(); + LL_RCC_PLL1_EnableDomain_PLL1R(); + while (LL_RCC_PLL1_IsReady() != 1U) + { + /* Wait for PLL ready */ + } + + /* Sysclk activation on the main PLL */ + LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider); + LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL1R); + while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL1R) + { + /* Wait for system clock switch to PLL */ + } + + /* Set APB1, APB2 & APB7 prescaler*/ + LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider); + LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider); + LL_RCC_SetAPB7Prescaler(UTILS_ClkInitStruct->APB7CLKDivider); + } + + /* Decreasing the number of wait states because of lower CPU frequency */ + if (SystemCoreClock > hclk_frequency) + { + /* Set FLASH latency to lowest latency */ + status = LL_SetFlashLatency(hclk_frequency); + } + + /* Update SystemCoreClock variable */ + if (status == SUCCESS) + { + LL_SetSystemCoreClock(hclk_frequency); + } + + return status; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/_htmresc/Add button.svg b/system/Drivers/STM32WBAxx_HAL_Driver/_htmresc/Add button.svg new file mode 100644 index 0000000000..c211545dad --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/_htmresc/Add button.svg @@ -0,0 +1,2 @@ + + diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/_htmresc/Update.svg b/system/Drivers/STM32WBAxx_HAL_Driver/_htmresc/Update.svg new file mode 100644 index 0000000000..f88381f1e6 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/_htmresc/Update.svg @@ -0,0 +1,2 @@ + + diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/_htmresc/favicon.png b/system/Drivers/STM32WBAxx_HAL_Driver/_htmresc/favicon.png new file mode 100644 index 0000000000000000000000000000000000000000..06713eec4974e141c6e9b4156d34e61e89f282ca GIT binary patch literal 4126 zcmV+(5aI8MP)ZIGU@QfPy~$kHP}Vz9c$a)g>fT6hB^OaK4>c|MGS0000HbW%=J|NsC0|NsC0 z|NsC0|NsC0041%NVgLXD!bwCyRCwCllie1CAP9sJ&9ooo{hxLjw5@YC+xxf~%TE}{ zNd5%935b--eKa7{Q8)vZ;eI6pGFH>rL)887WOA={e(b_&0g-g6to#Hm2B3vqWV>1u z@z7*I(bdWdx-Y=OT@|og)oZEgAbc7ep|Gf{$7j1Oa#T&r4>0xv(+}tR_4biWa z1Q-BfcsgeLIJPbT0000rV&neh&#Q1i z007~1e$oCcFS8neI|hJl{-P!B1ZZ9hpmq0)X0i`JwE&>$+E?>%_LC6RbVIkUx0b+_+BaR3cnT7Zv!AJxW zizFb)h!jyGOOZ85F;a?DAXP{m@;!0_IfqH8(HlgRxt7s3}k3K`kFu>>-2Q$QMFfPW!La{h336o>X zu_CMttHv6zR;&ZNiS=X8v3CR#fknUxHUxJ0uoBa_M6WNWeqIg~6QE69c9o#eyhGvpiOA@W-aonk<7r1(?fC{oI5N*U!4 zfg=2N-7=cNnjjOr{yriy6mMFgG#l znCF=fnQv8CDz++o6_Lscl}eQ+l^ZHARH>?_s@|##Rr6KLRFA1%Q+=*RRWnoLsR`7U zt5vFIcfW3@?wFpwUVxrVZ>QdQz32KIeJ}k~{cZZE^+ya? z2D1z#2HOnI7(B%_ac?{wFUQ;QQA1tBKtrWrm0_3Rgps+?Jfqb{jYbcQX~taRB;#$y zZN{S}1|}gUOHJxc?wV3fxuz+mJ4`!F$IZ;mqRrNsHJd##*D~ju=bP7?-?v~|cv>vB zsJ6IeNwVZxrdjT`yl#bBIa#GxRa#xMMy;K#CDyyGyQdMSxlWT#tDe?p!?5wT$+oGt z8L;Kp2HUQ-ZMJ=3XJQv;x5ci*?vuTfeY$;({XGW_huIFR9a(?@3)XSs8O^N5RyOM=TTmp(3=8^+zpz2r)C z^>JO{deZfso3oq3?Wo(Y?l$ge?uXo;%ru`Vo>?<<(8I_>;8Eq#KMS9gFl*neeosSB zfoHYnBQIkwkyowPu(zdms`p{<7e4kra-ZWq<2*OsGTvEV%s0Td$hXT+!*8Bnh2KMe zBmZRodjHV?r+_5^X9J0WL4jKW`}lf%A-|44I@@LTvf1rHjG(ze6+w@Jt%Bvjts!X0 z?2xS?_ve_-kiKB_KiJlZ$9G`c^=E@oNG)mWWaNo-3TIW8)$Hg0Ub-~8?KhvJ>$ z3*&nim@mj(aCxE5!t{lw7O5^0EIO7zOo&c6l<+|iDySBWCGrz@C5{St!X3hAA}`T4 z(TLbXTq+(;@<=L8dXnssyft|w#WSTW<++3>sgS%(4NTpeI-VAqb|7ssJvzNHgOZVu zaYCvgO_R1~>SyL=cFU|~g|hy|Zi}}s9+d~lYqOB71z9Z$wnC=pR9Yz4DhIM>Wmjgu z&56o6maCpC&F##y%G;1PobR9i?GnNg;gYtchD%p19a!eQtZF&3JaKv33gZ<8D~47E ztUS1iwkmDaPpj=$m#%)jCVEY4fnLGNg2A-`YwHVD3gv};>)hAvT~AmqS>Lr``i7kw zJ{5_It`yrBmlc25DBO7E8;5VoznR>Ww5hAaxn$2~(q`%A-YuS64wkBy=9dm`4cXeX z4c}I@?e+FW+b@^RDBHV(wnMq2zdX3SWv9u`%{xC-q*U}&`cyXV(%rRT*Z6MH?i+i& z_B8C(+grT%{XWUQ+f@NoP1R=AW&26{v-dx)iK^-Nmiuj8txj!m?Z*Ss1N{dh4z}01 z)YTo*JycSU)+_5r4#yw9{+;i4Ee$peRgIj+;v;ZGdF1K$3E%e~4LaI(jC-u%2h$&R z9cLXcYC@Xwnns&bn)_Q~Te?roKGD|d-g^8;+aC{{G(1^(O7m37Y1-+6)01cN&y1aw zoqc{T`P^XJqPBbIW6s}d4{z_f5Om?vMgNQEJG?v2T=KYd^0M3I6IZxbny)%vZR&LD zJpPl@Psh8QyPB@KTx+@RdcC!KX7}kEo;S|j^u2lU7XQ}Oo;f|;z4Ll+_r>@1-xl3| zawq-H%e&ckC+@AhPrP6BKT#_XdT7&;F71j}Joy zkC~6lh7E@6o;W@^IpRNZ{ptLtL(gQ-CY~4mqW;US7Zxvm_|@yz&e53Bp_lTPlfP|z zrTyx_>lv@x#=^!PzR7qqF<$gm`|ZJZ+;<)Cqu&ot2z=0000WV@Og>004R=004l4008;_004mL004C`008P>0026e000+nl3&F} z000F^NklQWRUVq~pvFslpiNq83Yr*1(ELa!!kppKfxQKEkPzz^I>0W)!71xam z(B64`)5a~kHf9SBOp*Wvo{xA*e4|Kv3g6TCo+fF8q^C$|g>#NlXyY$%lmkmCh$x1Z zFbJ_hiDG`37w>KPVB83d7E3>R@-M9$`|}|QFF}1qSk!nanPdVd3K38edo3y+D*=Uo zfOWCwj(F@GSjPG&B<0O;H!Zm0g>eDeK09{b@xB};mEy; z;Gp5H_Cr65qKM1uYIu6x&16!Ei=BHfJLe)1IUnFqc6d#D=ZVQmV9C73vy1=x$SK;s z=*CYZP+Ei1D5Vjl#u88v5dv#jId?iu)8mM}{mD`GcMXtAC5ap?ZoKr&iYuqTKHe$t zTR%R$ZZwxec?l+0r_LIVbe-mzH+D0*ZYsu4BE~~JA2A+AD?BAArO=g8ZfvXtU~o9c zZ(Bd-RFK5jh*DvM1v6^41HB@0K0qn7E8E&Xz1mk6hvmx?*|WB_H!dcO;5R$=<4b~s z5zr3N4zxlkMKOrDeny(PGpEM6^hGyc7lhg>MWtM!af*pn%&q_PxI(n^(-Zd{ICPAp z(WE@Zz5|EZyt{MEDy&l5$Cba^zU!9k&;Vs7lk$@o02LOwb#e2{#3%Cn2>kQF(RKUU z+tW!;FT0@d+TX^L;>@3RytlTP&ts$pqA}TwENBlg9?$-D zF9Sn4URZx8)hVBw<~NY=h3=so7{jEhG%Zc_0QBSvY~K4BS|W5MAem5XSb6m}VDN$f zy+b3n9qjIJoHM5pqYa`IPH9AIoM=!AE1Er>r|3E}#Jq-S)cTrfD&TZjAuN@+V}3mi zlhOce+q<8>Y?i93G=*Z3Web`ri!Q%p%LR*(bB?;|)B`&=J&ab0Z(UKpbzyZV5o*#& z0FLzzaI$v*-#WB)+`n>BoJ*1AwU0XSu;@w&Hu1WYXVR#!8itC%68CzMeiXhL#`9W$9J30NB-Wg!ex`hBlg9F5u@&o4>hd`TWPv z{r{JbyvQGZzbyvPS}zAifbhF49z~X|@9v|!=No>qsF|P~vf=g>7#%0yk<U?Ha8*Z4HW>#8w>z$A3 z>^uQlk;$a-6CQ(uc@RM)Cbss!xuPVl2@c1u-5tEUw}U8OfP_J+QYhfu$B<0Cj3xm7 c?*aZZ00ulYFs-m=@&Et;07*qoM6N<$f~=14i~s-t literal 0 HcmV?d00001 diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/_htmresc/mini-st_2020.css b/system/Drivers/STM32WBAxx_HAL_Driver/_htmresc/mini-st_2020.css new file mode 100644 index 0000000000..db8b406aa4 --- /dev/null +++ b/system/Drivers/STM32WBAxx_HAL_Driver/_htmresc/mini-st_2020.css @@ -0,0 +1,1711 @@ +@charset "UTF-8"; +/* + Flavor name: Custom (mini-custom) + Generated online - https://minicss.org/flavors + mini.css version: v3.0.1 +*/ +/* + Browsers resets and base typography. +*/ +/* Core module CSS variable definitions */ +:root { + --fore-color: #03234b; + --secondary-fore-color: #03234b; + --back-color: #ffffff; + --secondary-back-color: #ffffff; + --blockquote-color: #e6007e; + --pre-color: #e6007e; + --border-color: #3cb4e6; + --secondary-border-color: #3cb4e6; + --heading-ratio: 1.2; + --universal-margin: 0.5rem; + --universal-padding: 0.25rem; + --universal-border-radius: 0.075rem; + --background-margin: 1.5%; + --a-link-color: #3cb4e6; + --a-visited-color: #8c0078; } + +html { + font-size: 13.5px; } + +a, b, del, em, i, ins, q, span, strong, u { + font-size: 1em; } + +html, * { + font-family: -apple-system, BlinkMacSystemFont, Helvetica, arial, sans-serif; + line-height: 1.25; + -webkit-text-size-adjust: 100%; } + +* { + font-size: 1rem; } + +body { + margin: 0; + color: var(--fore-color); + @background: var(--back-color); + background: var(--back-color) linear-gradient(#ffd200, #ffd200) repeat-y left top; + background-size: var(--background-margin); + } + +details { + display: block; } + +summary { + display: list-item; } + +abbr[title] { + border-bottom: none; + text-decoration: underline dotted; } + +input { + overflow: visible; } + +img { + max-width: 100%; + height: auto; } + +h1, h2, h3, h4, h5, h6 { + line-height: 1.25; + margin: calc(1.5 * var(--universal-margin)) var(--universal-margin); + font-weight: 400; } + h1 small, h2 small, h3 small, h4 small, h5 small, h6 small { + color: var(--secondary-fore-color); + display: block; + margin-top: -0.25rem; } + +h1 { + font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) * var(--heading-ratio)); } + +h2 { + font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) ); + border-style: none none solid none ; + border-width: thin; + border-color: var(--border-color); } +h3 { + font-size: calc(1rem * var(--heading-ratio) ); } + +h4 { + font-size: calc(1rem * var(--heading-ratio)); } + +h5 { + font-size: 1rem; } + +h6 { + font-size: calc(1rem / var(--heading-ratio)); } + +p { + margin: var(--universal-margin); } + +ol, ul { + margin: var(--universal-margin); + padding-left: calc(3 * var(--universal-margin)); } + +b, strong { + font-weight: 700; } + +hr { + box-sizing: content-box; + border: 0; + line-height: 1.25em; + margin: var(--universal-margin); + height: 0.0714285714rem; + background: linear-gradient(to right, transparent, var(--border-color) 20%, var(--border-color) 80%, transparent); } + +blockquote { + display: block; + position: relative; + font-style: italic; + color: var(--secondary-fore-color); + margin: var(--universal-margin); + padding: calc(3 * var(--universal-padding)); + border: 0.0714285714rem solid var(--secondary-border-color); + border-left: 0.3rem solid var(--blockquote-color); + border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; } + blockquote:before { + position: absolute; + top: calc(0rem - var(--universal-padding)); + left: 0; + font-family: sans-serif; + font-size: 2rem; + font-weight: 800; + content: "\201c"; + color: var(--blockquote-color); } + blockquote[cite]:after { + font-style: normal; + font-size: 0.75em; + font-weight: 700; + content: "\a— " attr(cite); + white-space: pre; } + +code, kbd, pre, samp { + font-family: Menlo, Consolas, monospace; + font-size: 0.85em; } + +code { + background: var(--secondary-back-color); + border-radius: var(--universal-border-radius); + padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); } + +kbd { + background: var(--fore-color); + color: var(--back-color); + border-radius: var(--universal-border-radius); + padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); } + +pre { + overflow: auto; + background: var(--secondary-back-color); + padding: calc(1.5 * var(--universal-padding)); + margin: var(--universal-margin); + border: 0.0714285714rem solid var(--secondary-border-color); + border-left: 0.2857142857rem solid var(--pre-color); + border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; } + +sup, sub, code, kbd { + line-height: 0; + position: relative; + vertical-align: baseline; } + +small, sup, sub, figcaption { + font-size: 0.75em; } + +sup { + top: -0.5em; } + +sub { + bottom: -0.25em; } + +figure { + margin: var(--universal-margin); } + +figcaption { + color: var(--secondary-fore-color); } + +a { + text-decoration: none; } + a:link { + color: var(--a-link-color); } + a:visited { + color: var(--a-visited-color); } + a:hover, a:focus { + text-decoration: underline; } + +/* + Definitions for the grid system, cards and containers. +*/ +.container { + margin: 0 auto; + padding: 0 calc(1.5 * var(--universal-padding)); } + +.row { + box-sizing: border-box; + display: flex; + flex: 0 1 auto; + flex-flow: row wrap; + margin: 0 0 0 var(--background-margin); } + +.col-sm, +[class^='col-sm-'], +[class^='col-sm-offset-'], +.row[class*='cols-sm-'] > * { + box-sizing: border-box; + flex: 0 0 auto; + padding: 0 calc(var(--universal-padding) / 2); } + +.col-sm, +.row.cols-sm > * { + max-width: 100%; + flex-grow: 1; + flex-basis: 0; } + +.col-sm-1, +.row.cols-sm-1 > * { + max-width: 8.3333333333%; + flex-basis: 8.3333333333%; } + +.col-sm-offset-0 { + margin-left: 0; } + +.col-sm-2, +.row.cols-sm-2 > * { + max-width: 16.6666666667%; + flex-basis: 16.6666666667%; } + +.col-sm-offset-1 { + margin-left: 8.3333333333%; } + +.col-sm-3, +.row.cols-sm-3 > * { + max-width: 25%; + flex-basis: 25%; } + +.col-sm-offset-2 { + margin-left: 16.6666666667%; } + +.col-sm-4, +.row.cols-sm-4 > * { + max-width: 33.3333333333%; + flex-basis: 33.3333333333%; } + +.col-sm-offset-3 { + margin-left: 25%; } + +.col-sm-5, +.row.cols-sm-5 > * { + max-width: 41.6666666667%; + flex-basis: 41.6666666667%; } + +.col-sm-offset-4 { + margin-left: 33.3333333333%; } + +.col-sm-6, +.row.cols-sm-6 > * { + max-width: 50%; + flex-basis: 50%; } + +.col-sm-offset-5 { + margin-left: 41.6666666667%; } + +.col-sm-7, +.row.cols-sm-7 > * { + max-width: 58.3333333333%; + flex-basis: 58.3333333333%; } + +.col-sm-offset-6 { + margin-left: 50%; } + +.col-sm-8, +.row.cols-sm-8 > * { + max-width: 66.6666666667%; + flex-basis: 66.6666666667%; } + +.col-sm-offset-7 { + margin-left: 58.3333333333%; } + +.col-sm-9, +.row.cols-sm-9 > * { + max-width: 75%; + flex-basis: 75%; } + +.col-sm-offset-8 { + margin-left: 66.6666666667%; } + +.col-sm-10, +.row.cols-sm-10 > * { + max-width: 83.3333333333%; + flex-basis: 83.3333333333%; } + +.col-sm-offset-9 { + margin-left: 75%; } + +.col-sm-11, +.row.cols-sm-11 > * { + max-width: 91.6666666667%; + flex-basis: 91.6666666667%; } + +.col-sm-offset-10 { + margin-left: 83.3333333333%; } + +.col-sm-12, +.row.cols-sm-12 > * { + max-width: 100%; + flex-basis: 100%; } + +.col-sm-offset-11 { + margin-left: 91.6666666667%; } + +.col-sm-normal { + order: initial; } + +.col-sm-first { + order: -999; } + +.col-sm-last { + order: 999; } + +@media screen and (min-width: 500px) { + .col-md, + [class^='col-md-'], + [class^='col-md-offset-'], + .row[class*='cols-md-'] > * { + box-sizing: border-box; + flex: 0 0 auto; + padding: 0 calc(var(--universal-padding) / 2); } + + .col-md, + .row.cols-md > * { + max-width: 100%; + flex-grow: 1; + flex-basis: 0; } + + .col-md-1, + .row.cols-md-1 > * { + max-width: 8.3333333333%; + flex-basis: 8.3333333333%; } + + .col-md-offset-0 { + margin-left: 0; } + + .col-md-2, + .row.cols-md-2 > * { + max-width: 16.6666666667%; + flex-basis: 16.6666666667%; } + + .col-md-offset-1 { + margin-left: 8.3333333333%; } + + .col-md-3, + .row.cols-md-3 > * { + max-width: 25%; + flex-basis: 25%; } + + .col-md-offset-2 { + margin-left: 16.6666666667%; } + + .col-md-4, + .row.cols-md-4 > * { + max-width: 33.3333333333%; + flex-basis: 33.3333333333%; } + + .col-md-offset-3 { + margin-left: 25%; } + + .col-md-5, + .row.cols-md-5 > * { + max-width: 41.6666666667%; + flex-basis: 41.6666666667%; } + + .col-md-offset-4 { + margin-left: 33.3333333333%; } + + .col-md-6, + .row.cols-md-6 > * { + max-width: 50%; + flex-basis: 50%; } + + .col-md-offset-5 { + margin-left: 41.6666666667%; } + + .col-md-7, + .row.cols-md-7 > * { + max-width: 58.3333333333%; + flex-basis: 58.3333333333%; } + + .col-md-offset-6 { + margin-left: 50%; } + + .col-md-8, + .row.cols-md-8 > * { + max-width: 66.6666666667%; + flex-basis: 66.6666666667%; } + + .col-md-offset-7 { + margin-left: 58.3333333333%; } + + .col-md-9, + .row.cols-md-9 > * { + max-width: 75%; + flex-basis: 75%; } + + .col-md-offset-8 { + margin-left: 66.6666666667%; } + + .col-md-10, + .row.cols-md-10 > * { + max-width: 83.3333333333%; + flex-basis: 83.3333333333%; } + + .col-md-offset-9 { + margin-left: 75%; } + + .col-md-11, + .row.cols-md-11 > * { + max-width: 91.6666666667%; + flex-basis: 91.6666666667%; } + + .col-md-offset-10 { + margin-left: 83.3333333333%; } + + .col-md-12, + .row.cols-md-12 > * { + max-width: 100%; + flex-basis: 100%; } + + .col-md-offset-11 { + margin-left: 91.6666666667%; } + + .col-md-normal { + order: initial; } + + .col-md-first { + order: -999; } + + .col-md-last { + order: 999; } } +@media screen and (min-width: 1280px) { + .col-lg, + [class^='col-lg-'], + [class^='col-lg-offset-'], + .row[class*='cols-lg-'] > * { + box-sizing: border-box; + flex: 0 0 auto; + padding: 0 calc(var(--universal-padding) / 2); } + + .col-lg, + .row.cols-lg > * { + max-width: 100%; + flex-grow: 1; + flex-basis: 0; } + + .col-lg-1, + .row.cols-lg-1 > * { + max-width: 8.3333333333%; + flex-basis: 8.3333333333%; } + + .col-lg-offset-0 { + margin-left: 0; } + + .col-lg-2, + .row.cols-lg-2 > * { + max-width: 16.6666666667%; + flex-basis: 16.6666666667%; } + + .col-lg-offset-1 { + margin-left: 8.3333333333%; } + + .col-lg-3, + .row.cols-lg-3 > * { + max-width: 25%; + flex-basis: 25%; } + + .col-lg-offset-2 { + margin-left: 16.6666666667%; } + + .col-lg-4, + .row.cols-lg-4 > * { + max-width: 33.3333333333%; + flex-basis: 33.3333333333%; } + + .col-lg-offset-3 { + margin-left: 25%; } + + .col-lg-5, + .row.cols-lg-5 > * { + max-width: 41.6666666667%; + flex-basis: 41.6666666667%; } + + .col-lg-offset-4 { + margin-left: 33.3333333333%; } + + .col-lg-6, + .row.cols-lg-6 > * { + max-width: 50%; + flex-basis: 50%; } + + .col-lg-offset-5 { + margin-left: 41.6666666667%; } + + .col-lg-7, + .row.cols-lg-7 > * { + max-width: 58.3333333333%; + flex-basis: 58.3333333333%; } + + .col-lg-offset-6 { + margin-left: 50%; } + + .col-lg-8, + .row.cols-lg-8 > * { + max-width: 66.6666666667%; + flex-basis: 66.6666666667%; } + + .col-lg-offset-7 { + margin-left: 58.3333333333%; } + + .col-lg-9, + .row.cols-lg-9 > * { + max-width: 75%; + flex-basis: 75%; } + + .col-lg-offset-8 { + margin-left: 66.6666666667%; } + + .col-lg-10, + .row.cols-lg-10 > * { + max-width: 83.3333333333%; + flex-basis: 83.3333333333%; } + + .col-lg-offset-9 { + margin-left: 75%; } + + .col-lg-11, + .row.cols-lg-11 > * { + max-width: 91.6666666667%; + flex-basis: 91.6666666667%; } + + .col-lg-offset-10 { + margin-left: 83.3333333333%; } + + .col-lg-12, + .row.cols-lg-12 > * { + max-width: 100%; + flex-basis: 100%; } + + .col-lg-offset-11 { + margin-left: 91.6666666667%; } + + .col-lg-normal { + order: initial; } + + .col-lg-first { + order: -999; } + + .col-lg-last { + order: 999; } } +/* Card component CSS variable definitions */ +:root { + --card-back-color: #3cb4e6; + --card-fore-color: #03234b; + --card-border-color: #03234b; } + +.card { + display: flex; + flex-direction: column; + justify-content: space-between; + align-self: center; + position: relative; + width: 100%; + background: var(--card-back-color); + color: var(--card-fore-color); + border: 0.0714285714rem solid var(--card-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); + overflow: hidden; } + @media screen and (min-width: 320px) { + .card { + max-width: 320px; } } + .card > .sectione { + background: var(--card-back-color); + color: var(--card-fore-color); + box-sizing: border-box; + margin: 0; + border: 0; + border-radius: 0; + border-bottom: 0.0714285714rem solid var(--card-border-color); + padding: var(--universal-padding); + width: 100%; } + .card > .sectione.media { + height: 200px; + padding: 0; + -o-object-fit: cover; + object-fit: cover; } + .card > .sectione:last-child { + border-bottom: 0; } + +/* + Custom elements for card elements. +*/ +@media screen and (min-width: 240px) { + .card.small { + max-width: 240px; } } +@media screen and (min-width: 480px) { + .card.large { + max-width: 480px; } } +.card.fluid { + max-width: 100%; + width: auto; } + +.card.warning { + --card-back-color: #e5b8b7; + --card-fore-color: #3b234b; + --card-border-color: #8c0078; } + +.card.error { + --card-back-color: #464650; + --card-fore-color: #ffffff; + --card-border-color: #8c0078; } + +.card > .sectione.dark { + --card-back-color: #3b234b; + --card-fore-color: #ffffff; } + +.card > .sectione.double-padded { + padding: calc(1.5 * var(--universal-padding)); } + +/* + Definitions for forms and input elements. +*/ +/* Input_control module CSS variable definitions */ +:root { + --form-back-color: #ffe97f; + --form-fore-color: #03234b; + --form-border-color: #3cb4e6; + --input-back-color: #ffffff; + --input-fore-color: #03234b; + --input-border-color: #3cb4e6; + --input-focus-color: #0288d1; + --input-invalid-color: #d32f2f; + --button-back-color: #e2e2e2; + --button-hover-back-color: #dcdcdc; + --button-fore-color: #212121; + --button-border-color: transparent; + --button-hover-border-color: transparent; + --button-group-border-color: rgba(124, 124, 124, 0.54); } + +form { + background: var(--form-back-color); + color: var(--form-fore-color); + border: 0.0714285714rem solid var(--form-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); + padding: calc(2 * var(--universal-padding)) var(--universal-padding); } + +fieldset { + border: 0.0714285714rem solid var(--form-border-color); + border-radius: var(--universal-border-radius); + margin: calc(var(--universal-margin) / 4); + padding: var(--universal-padding); } + +legend { + box-sizing: border-box; + display: table; + max-width: 100%; + white-space: normal; + font-weight: 500; + padding: calc(var(--universal-padding) / 2); } + +label { + padding: calc(var(--universal-padding) / 2) var(--universal-padding); } + +.input-group { + display: inline-block; } + .input-group.fluid { + display: flex; + align-items: center; + justify-content: center; } + .input-group.fluid > input { + max-width: 100%; + flex-grow: 1; + flex-basis: 0px; } + @media screen and (max-width: 499px) { + .input-group.fluid { + align-items: stretch; + flex-direction: column; } } + .input-group.vertical { + display: flex; + align-items: stretch; + flex-direction: column; } + .input-group.vertical > input { + max-width: 100%; + flex-grow: 1; + flex-basis: 0px; } + +[type="number"]::-webkit-inner-spin-button, [type="number"]::-webkit-outer-spin-button { + height: auto; } + +[type="search"] { + -webkit-appearance: textfield; + outline-offset: -2px; } + +[type="search"]::-webkit-search-cancel-button, +[type="search"]::-webkit-search-decoration { + -webkit-appearance: none; } + +input:not([type]), [type="text"], [type="email"], [type="number"], [type="search"], +[type="password"], [type="url"], [type="tel"], [type="checkbox"], [type="radio"], textarea, select { + box-sizing: border-box; + background: var(--input-back-color); + color: var(--input-fore-color); + border: 0.0714285714rem solid var(--input-border-color); + border-radius: var(--universal-border-radius); + margin: calc(var(--universal-margin) / 2); + padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); } + +input:not([type="button"]):not([type="submit"]):not([type="reset"]):hover, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus, textarea:hover, textarea:focus, select:hover, select:focus { + border-color: var(--input-focus-color); + box-shadow: none; } +input:not([type="button"]):not([type="submit"]):not([type="reset"]):invalid, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus:invalid, textarea:invalid, textarea:focus:invalid, select:invalid, select:focus:invalid { + border-color: var(--input-invalid-color); + box-shadow: none; } +input:not([type="button"]):not([type="submit"]):not([type="reset"])[readonly], textarea[readonly], select[readonly] { + background: var(--secondary-back-color); } + +select { + max-width: 100%; } + +option { + overflow: hidden; + text-overflow: ellipsis; } + +[type="checkbox"], [type="radio"] { + -webkit-appearance: none; + -moz-appearance: none; + appearance: none; + position: relative; + height: calc(1rem + var(--universal-padding) / 2); + width: calc(1rem + var(--universal-padding) / 2); + vertical-align: text-bottom; + padding: 0; + flex-basis: calc(1rem + var(--universal-padding) / 2) !important; + flex-grow: 0 !important; } + [type="checkbox"]:checked:before, [type="radio"]:checked:before { + position: absolute; } + +[type="checkbox"]:checked:before { + content: '\2713'; + font-family: sans-serif; + font-size: calc(1rem + var(--universal-padding) / 2); + top: calc(0rem - var(--universal-padding)); + left: calc(var(--universal-padding) / 4); } + +[type="radio"] { + border-radius: 100%; } + [type="radio"]:checked:before { + border-radius: 100%; + content: ''; + top: calc(0.0714285714rem + var(--universal-padding) / 2); + left: calc(0.0714285714rem + var(--universal-padding) / 2); + background: var(--input-fore-color); + width: 0.5rem; + height: 0.5rem; } + +:placeholder-shown { + color: var(--input-fore-color); } + +::-ms-placeholder { + color: var(--input-fore-color); + opacity: 0.54; } + +button::-moz-focus-inner, [type="button"]::-moz-focus-inner, [type="reset"]::-moz-focus-inner, [type="submit"]::-moz-focus-inner { + border-style: none; + padding: 0; } + +button, html [type="button"], [type="reset"], [type="submit"] { + -webkit-appearance: button; } + +button { + overflow: visible; + text-transform: none; } + +button, [type="button"], [type="submit"], [type="reset"], +a.button, label.button, .button, +a[role="button"], label[role="button"], [role="button"] { + display: inline-block; + background: var(--button-back-color); + color: var(--button-fore-color); + border: 0.0714285714rem solid var(--button-border-color); + border-radius: var(--universal-border-radius); + padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); + margin: var(--universal-margin); + text-decoration: none; + cursor: pointer; + transition: background 0.3s; } + button:hover, button:focus, [type="button"]:hover, [type="button"]:focus, [type="submit"]:hover, [type="submit"]:focus, [type="reset"]:hover, [type="reset"]:focus, + a.button:hover, + a.button:focus, label.button:hover, label.button:focus, .button:hover, .button:focus, + a[role="button"]:hover, + a[role="button"]:focus, label[role="button"]:hover, label[role="button"]:focus, [role="button"]:hover, [role="button"]:focus { + background: var(--button-hover-back-color); + border-color: var(--button-hover-border-color); } + +input:disabled, input[disabled], textarea:disabled, textarea[disabled], select:disabled, select[disabled], button:disabled, button[disabled], .button:disabled, .button[disabled], [role="button"]:disabled, [role="button"][disabled] { + cursor: not-allowed; + opacity: 0.75; } + +.button-group { + display: flex; + border: 0.0714285714rem solid var(--button-group-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); } + .button-group > button, .button-group [type="button"], .button-group > [type="submit"], .button-group > [type="reset"], .button-group > .button, .button-group > [role="button"] { + margin: 0; + max-width: 100%; + flex: 1 1 auto; + text-align: center; + border: 0; + border-radius: 0; + box-shadow: none; } + .button-group > :not(:first-child) { + border-left: 0.0714285714rem solid var(--button-group-border-color); } + @media screen and (max-width: 499px) { + .button-group { + flex-direction: column; } + .button-group > :not(:first-child) { + border: 0; + border-top: 0.0714285714rem solid var(--button-group-border-color); } } + +/* + Custom elements for forms and input elements. +*/ +button.primary, [type="button"].primary, [type="submit"].primary, [type="reset"].primary, .button.primary, [role="button"].primary { + --button-back-color: #1976d2; + --button-fore-color: #f8f8f8; } + button.primary:hover, button.primary:focus, [type="button"].primary:hover, [type="button"].primary:focus, [type="submit"].primary:hover, [type="submit"].primary:focus, [type="reset"].primary:hover, [type="reset"].primary:focus, .button.primary:hover, .button.primary:focus, [role="button"].primary:hover, [role="button"].primary:focus { + --button-hover-back-color: #1565c0; } + +button.secondary, [type="button"].secondary, [type="submit"].secondary, [type="reset"].secondary, .button.secondary, [role="button"].secondary { + --button-back-color: #d32f2f; + --button-fore-color: #f8f8f8; } + button.secondary:hover, button.secondary:focus, [type="button"].secondary:hover, [type="button"].secondary:focus, [type="submit"].secondary:hover, [type="submit"].secondary:focus, [type="reset"].secondary:hover, [type="reset"].secondary:focus, .button.secondary:hover, .button.secondary:focus, [role="button"].secondary:hover, [role="button"].secondary:focus { + --button-hover-back-color: #c62828; } + +button.tertiary, [type="button"].tertiary, [type="submit"].tertiary, [type="reset"].tertiary, .button.tertiary, [role="button"].tertiary { + --button-back-color: #308732; + --button-fore-color: #f8f8f8; } + button.tertiary:hover, button.tertiary:focus, [type="button"].tertiary:hover, [type="button"].tertiary:focus, [type="submit"].tertiary:hover, [type="submit"].tertiary:focus, [type="reset"].tertiary:hover, [type="reset"].tertiary:focus, .button.tertiary:hover, .button.tertiary:focus, [role="button"].tertiary:hover, [role="button"].tertiary:focus { + --button-hover-back-color: #277529; } + +button.inverse, [type="button"].inverse, [type="submit"].inverse, [type="reset"].inverse, .button.inverse, [role="button"].inverse { + --button-back-color: #212121; + --button-fore-color: #f8f8f8; } + button.inverse:hover, button.inverse:focus, [type="button"].inverse:hover, [type="button"].inverse:focus, [type="submit"].inverse:hover, [type="submit"].inverse:focus, [type="reset"].inverse:hover, [type="reset"].inverse:focus, .button.inverse:hover, .button.inverse:focus, [role="button"].inverse:hover, [role="button"].inverse:focus { + --button-hover-back-color: #111; } + +button.small, [type="button"].small, [type="submit"].small, [type="reset"].small, .button.small, [role="button"].small { + padding: calc(0.5 * var(--universal-padding)) calc(0.75 * var(--universal-padding)); + margin: var(--universal-margin); } + +button.large, [type="button"].large, [type="submit"].large, [type="reset"].large, .button.large, [role="button"].large { + padding: calc(1.5 * var(--universal-padding)) calc(2 * var(--universal-padding)); + margin: var(--universal-margin); } + +/* + Definitions for navigation elements. +*/ +/* Navigation module CSS variable definitions */ +:root { + --header-back-color: #03234b; + --header-hover-back-color: #ffd200; + --header-fore-color: #ffffff; + --header-border-color: #3cb4e6; + --nav-back-color: #ffffff; + --nav-hover-back-color: #ffe97f; + --nav-fore-color: #e6007e; + --nav-border-color: #3cb4e6; + --nav-link-color: #3cb4e6; + --footer-fore-color: #ffffff; + --footer-back-color: #03234b; + --footer-border-color: #3cb4e6; + --footer-link-color: #3cb4e6; + --drawer-back-color: #ffffff; + --drawer-hover-back-color: #ffe97f; + --drawer-border-color: #3cb4e6; + --drawer-close-color: #e6007e; } + +header { + height: 2.75rem; + background: var(--header-back-color); + color: var(--header-fore-color); + border-bottom: 0.0714285714rem solid var(--header-border-color); + padding: calc(var(--universal-padding) / 4) 0; + white-space: nowrap; + overflow-x: auto; + overflow-y: hidden; } + header.row { + box-sizing: content-box; } + header .logo { + color: var(--header-fore-color); + font-size: 1.75rem; + padding: var(--universal-padding) calc(2 * var(--universal-padding)); + text-decoration: none; } + header button, header [type="button"], header .button, header [role="button"] { + box-sizing: border-box; + position: relative; + top: calc(0rem - var(--universal-padding) / 4); + height: calc(3.1875rem + var(--universal-padding) / 2); + background: var(--header-back-color); + line-height: calc(3.1875rem - var(--universal-padding) * 1.5); + text-align: center; + color: var(--header-fore-color); + border: 0; + border-radius: 0; + margin: 0; + text-transform: uppercase; } + header button:hover, header button:focus, header [type="button"]:hover, header [type="button"]:focus, header .button:hover, header .button:focus, header [role="button"]:hover, header [role="button"]:focus { + background: var(--header-hover-back-color); } + +nav { + background: var(--nav-back-color); + color: var(--nav-fore-color); + border: 0.0714285714rem solid var(--nav-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); } + nav * { + padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); } + nav a, nav a:visited { + display: block; + color: var(--nav-link-color); + border-radius: var(--universal-border-radius); + transition: background 0.3s; } + nav a:hover, nav a:focus, nav a:visited:hover, nav a:visited:focus { + text-decoration: none; + background: var(--nav-hover-back-color); } + nav .sublink-1 { + position: relative; + margin-left: calc(2 * var(--universal-padding)); } + nav .sublink-1:before { + position: absolute; + left: calc(var(--universal-padding) - 1 * var(--universal-padding)); + top: -0.0714285714rem; + content: ''; + height: 100%; + border: 0.0714285714rem solid var(--nav-border-color); + border-left: 0; } + nav .sublink-2 { + position: relative; + margin-left: calc(4 * var(--universal-padding)); } + nav .sublink-2:before { + position: absolute; + left: calc(var(--universal-padding) - 3 * var(--universal-padding)); + top: -0.0714285714rem; + content: ''; + height: 100%; + border: 0.0714285714rem solid var(--nav-border-color); + border-left: 0; } + +footer { + background: var(--footer-back-color); + color: var(--footer-fore-color); + border-top: 0.0714285714rem solid var(--footer-border-color); + padding: calc(2 * var(--universal-padding)) var(--universal-padding); + font-size: 0.875rem; } + footer a, footer a:visited { + color: var(--footer-link-color); } + +header.sticky { + position: -webkit-sticky; + position: sticky; + z-index: 1101; + top: 0; } + +footer.sticky { + position: -webkit-sticky; + position: sticky; + z-index: 1101; + bottom: 0; } + +.drawer-toggle:before { + display: inline-block; + position: relative; + vertical-align: bottom; + content: '\00a0\2261\00a0'; + font-family: sans-serif; + font-size: 1.5em; } +@media screen and (min-width: 500px) { + .drawer-toggle:not(.persistent) { + display: none; } } + +[type="checkbox"].drawer { + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + [type="checkbox"].drawer + * { + display: block; + box-sizing: border-box; + position: fixed; + top: 0; + width: 320px; + height: 100vh; + overflow-y: auto; + background: var(--drawer-back-color); + border: 0.0714285714rem solid var(--drawer-border-color); + border-radius: 0; + margin: 0; + z-index: 1110; + right: -320px; + transition: right 0.3s; } + [type="checkbox"].drawer + * .drawer-close { + position: absolute; + top: var(--universal-margin); + right: var(--universal-margin); + z-index: 1111; + width: 2rem; + height: 2rem; + border-radius: var(--universal-border-radius); + padding: var(--universal-padding); + margin: 0; + cursor: pointer; + transition: background 0.3s; } + [type="checkbox"].drawer + * .drawer-close:before { + display: block; + content: '\00D7'; + color: var(--drawer-close-color); + position: relative; + font-family: sans-serif; + font-size: 2rem; + line-height: 1; + text-align: center; } + [type="checkbox"].drawer + * .drawer-close:hover, [type="checkbox"].drawer + * .drawer-close:focus { + background: var(--drawer-hover-back-color); } + @media screen and (max-width: 320px) { + [type="checkbox"].drawer + * { + width: 100%; } } + [type="checkbox"].drawer:checked + * { + right: 0; } + @media screen and (min-width: 500px) { + [type="checkbox"].drawer:not(.persistent) + * { + position: static; + height: 100%; + z-index: 1100; } + [type="checkbox"].drawer:not(.persistent) + * .drawer-close { + display: none; } } + +/* + Definitions for the responsive table component. +*/ +/* Table module CSS variable definitions. */ +:root { + --table-border-color: #03234b; + --table-border-separator-color: #03234b; + --table-head-back-color: #03234b; + --table-head-fore-color: #ffffff; + --table-body-back-color: #ffffff; + --table-body-fore-color: #03234b; + --table-body-alt-back-color: #f4f4f4; } + +table { + border-collapse: separate; + border-spacing: 0; + margin: 0; + display: flex; + flex: 0 1 auto; + flex-flow: row wrap; + padding: var(--universal-padding); + padding-top: 0; } + table caption { + font-size: 1rem; + margin: calc(2 * var(--universal-margin)) 0; + max-width: 100%; + flex: 0 0 100%; } + table thead, table tbody { + display: flex; + flex-flow: row wrap; + border: 0.0714285714rem solid var(--table-border-color); } + table thead { + z-index: 999; + border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0; + border-bottom: 0.0714285714rem solid var(--table-border-separator-color); } + table tbody { + border-top: 0; + margin-top: calc(0 - var(--universal-margin)); + border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } + table tr { + display: flex; + padding: 0; } + table th, table td { + padding: calc(0.5 * var(--universal-padding)); + font-size: 0.9rem; } + table th { + text-align: left; + background: var(--table-head-back-color); + color: var(--table-head-fore-color); } + table td { + background: var(--table-body-back-color); + color: var(--table-body-fore-color); + border-top: 0.0714285714rem solid var(--table-border-color); } + +table:not(.horizontal) { + overflow: auto; + max-height: 100%; } + table:not(.horizontal) thead, table:not(.horizontal) tbody { + max-width: 100%; + flex: 0 0 100%; } + table:not(.horizontal) tr { + flex-flow: row wrap; + flex: 0 0 100%; } + table:not(.horizontal) th, table:not(.horizontal) td { + flex: 1 0 0%; + overflow: hidden; + text-overflow: ellipsis; } + table:not(.horizontal) thead { + position: sticky; + top: 0; } + table:not(.horizontal) tbody tr:first-child td { + border-top: 0; } + +table.horizontal { + border: 0; } + table.horizontal thead, table.horizontal tbody { + border: 0; + flex: .2 0 0; + flex-flow: row nowrap; } + table.horizontal tbody { + overflow: auto; + justify-content: space-between; + flex: .8 0 0; + margin-left: 0; + padding-bottom: calc(var(--universal-padding) / 4); } + table.horizontal tr { + flex-direction: column; + flex: 1 0 auto; } + table.horizontal th, table.horizontal td { + width: auto; + border: 0; + border-bottom: 0.0714285714rem solid var(--table-border-color); } + table.horizontal th:not(:first-child), table.horizontal td:not(:first-child) { + border-top: 0; } + table.horizontal th { + text-align: right; + border-left: 0.0714285714rem solid var(--table-border-color); + border-right: 0.0714285714rem solid var(--table-border-separator-color); } + table.horizontal thead tr:first-child { + padding-left: 0; } + table.horizontal th:first-child, table.horizontal td:first-child { + border-top: 0.0714285714rem solid var(--table-border-color); } + table.horizontal tbody tr:last-child td { + border-right: 0.0714285714rem solid var(--table-border-color); } + table.horizontal tbody tr:last-child td:first-child { + border-top-right-radius: 0.25rem; } + table.horizontal tbody tr:last-child td:last-child { + border-bottom-right-radius: 0.25rem; } + table.horizontal thead tr:first-child th:first-child { + border-top-left-radius: 0.25rem; } + table.horizontal thead tr:first-child th:last-child { + border-bottom-left-radius: 0.25rem; } + +@media screen and (max-width: 499px) { + table, table.horizontal { + border-collapse: collapse; + border: 0; + width: 100%; + display: table; } + table thead, table th, table.horizontal thead, table.horizontal th { + border: 0; + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + padding: 0; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + table tbody, table.horizontal tbody { + border: 0; + display: table-row-group; } + table tr, table.horizontal tr { + display: block; + border: 0.0714285714rem solid var(--table-border-color); + border-radius: var(--universal-border-radius); + background: #ffffff; + padding: var(--universal-padding); + margin: var(--universal-margin); + margin-bottom: calc(1 * var(--universal-margin)); } + table th, table td, table.horizontal th, table.horizontal td { + width: auto; } + table td, table.horizontal td { + display: block; + border: 0; + text-align: right; } + table td:before, table.horizontal td:before { + content: attr(data-label); + float: left; + font-weight: 600; } + table th:first-child, table td:first-child, table.horizontal th:first-child, table.horizontal td:first-child { + border-top: 0; } + table tbody tr:last-child td, table.horizontal tbody tr:last-child td { + border-right: 0; } } +table tr:nth-of-type(2n) > td { + background: var(--table-body-alt-back-color); } + +@media screen and (max-width: 500px) { + table tr:nth-of-type(2n) { + background: var(--table-body-alt-back-color); } } +:root { + --table-body-hover-back-color: #90caf9; } + +table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td { + background: var(--table-body-hover-back-color); } + +@media screen and (max-width: 500px) { + table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td { + background: var(--table-body-hover-back-color); } } +/* + Definitions for contextual background elements, toasts and tooltips. +*/ +/* Contextual module CSS variable definitions */ +:root { + --mark-back-color: #3cb4e6; + --mark-fore-color: #ffffff; } + +mark { + background: var(--mark-back-color); + color: var(--mark-fore-color); + font-size: 0.95em; + line-height: 1em; + border-radius: var(--universal-border-radius); + padding: calc(var(--universal-padding) / 4) var(--universal-padding); } + mark.inline-block { + display: inline-block; + font-size: 1em; + line-height: 1.4; + padding: calc(var(--universal-padding) / 2) var(--universal-padding); } + +:root { + --toast-back-color: #424242; + --toast-fore-color: #fafafa; } + +.toast { + position: fixed; + bottom: calc(var(--universal-margin) * 3); + left: 50%; + transform: translate(-50%, -50%); + z-index: 1111; + color: var(--toast-fore-color); + background: var(--toast-back-color); + border-radius: calc(var(--universal-border-radius) * 16); + padding: var(--universal-padding) calc(var(--universal-padding) * 3); } + +:root { + --tooltip-back-color: #212121; + --tooltip-fore-color: #fafafa; } + +.tooltip { + position: relative; + display: inline-block; } + .tooltip:before, .tooltip:after { + position: absolute; + opacity: 0; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); + transition: all 0.3s; + z-index: 1010; + left: 50%; } + .tooltip:not(.bottom):before, .tooltip:not(.bottom):after { + bottom: 75%; } + .tooltip.bottom:before, .tooltip.bottom:after { + top: 75%; } + .tooltip:hover:before, .tooltip:hover:after, .tooltip:focus:before, .tooltip:focus:after { + opacity: 1; + clip: auto; + -webkit-clip-path: inset(0%); + clip-path: inset(0%); } + .tooltip:before { + content: ''; + background: transparent; + border: var(--universal-margin) solid transparent; + left: calc(50% - var(--universal-margin)); } + .tooltip:not(.bottom):before { + border-top-color: #212121; } + .tooltip.bottom:before { + border-bottom-color: #212121; } + .tooltip:after { + content: attr(aria-label); + color: var(--tooltip-fore-color); + background: var(--tooltip-back-color); + border-radius: var(--universal-border-radius); + padding: var(--universal-padding); + white-space: nowrap; + transform: translateX(-50%); } + .tooltip:not(.bottom):after { + margin-bottom: calc(2 * var(--universal-margin)); } + .tooltip.bottom:after { + margin-top: calc(2 * var(--universal-margin)); } + +:root { + --modal-overlay-color: rgba(0, 0, 0, 0.45); + --modal-close-color: #e6007e; + --modal-close-hover-color: #ffe97f; } + +[type="checkbox"].modal { + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + [type="checkbox"].modal + div { + position: fixed; + top: 0; + left: 0; + display: none; + width: 100vw; + height: 100vh; + background: var(--modal-overlay-color); } + [type="checkbox"].modal + div .card { + margin: 0 auto; + max-height: 50vh; + overflow: auto; } + [type="checkbox"].modal + div .card .modal-close { + position: absolute; + top: 0; + right: 0; + width: 1.75rem; + height: 1.75rem; + border-radius: var(--universal-border-radius); + padding: var(--universal-padding); + margin: 0; + cursor: pointer; + transition: background 0.3s; } + [type="checkbox"].modal + div .card .modal-close:before { + display: block; + content: '\00D7'; + color: var(--modal-close-color); + position: relative; + font-family: sans-serif; + font-size: 1.75rem; + line-height: 1; + text-align: center; } + [type="checkbox"].modal + div .card .modal-close:hover, [type="checkbox"].modal + div .card .modal-close:focus { + background: var(--modal-close-hover-color); } + [type="checkbox"].modal:checked + div { + display: flex; + flex: 0 1 auto; + z-index: 1200; } + [type="checkbox"].modal:checked + div .card .modal-close { + z-index: 1211; } + +:root { + --collapse-label-back-color: #03234b; + --collapse-label-fore-color: #ffffff; + --collapse-label-hover-back-color: #3cb4e6; + --collapse-selected-label-back-color: #3cb4e6; + --collapse-border-color: var(--collapse-label-back-color); + --collapse-selected-border-color: #ceecf8; + --collapse-content-back-color: #ffffff; + --collapse-selected-label-border-color: #3cb4e6; } + +.collapse { + width: calc(100% - 2 * var(--universal-margin)); + opacity: 1; + display: flex; + flex-direction: column; + margin: var(--universal-margin); + border-radius: var(--universal-border-radius); } + .collapse > [type="radio"], .collapse > [type="checkbox"] { + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + .collapse > label { + flex-grow: 1; + display: inline-block; + height: 1.25rem; + cursor: pointer; + transition: background 0.2s; + color: var(--collapse-label-fore-color); + background: var(--collapse-label-back-color); + border: 0.0714285714rem solid var(--collapse-selected-border-color); + padding: calc(1.25 * var(--universal-padding)); } + .collapse > label:hover, .collapse > label:focus { + background: var(--collapse-label-hover-back-color); } + .collapse > label + div { + flex-basis: auto; + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); + transition: max-height 0.3s; + max-height: 1px; } + .collapse > :checked + label { + background: var(--collapse-selected-label-back-color); + border-color: var(--collapse-selected-label-border-color); } + .collapse > :checked + label + div { + box-sizing: border-box; + position: relative; + width: 100%; + height: auto; + overflow: auto; + margin: 0; + background: var(--collapse-content-back-color); + border: 0.0714285714rem solid var(--collapse-selected-border-color); + border-top: 0; + padding: var(--universal-padding); + clip: auto; + -webkit-clip-path: inset(0%); + clip-path: inset(0%); + max-height: 100%; } + .collapse > label:not(:first-of-type) { + border-top: 0; } + .collapse > label:first-of-type { + border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0; } + .collapse > label:last-of-type:not(:first-of-type) { + border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } + .collapse > label:last-of-type:first-of-type { + border-radius: var(--universal-border-radius); } + .collapse > :checked:last-of-type:not(:first-of-type) + label { + border-radius: 0; } + .collapse > :checked:last-of-type + label + div { + border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } + +/* + Custom elements for contextual background elements, toasts and tooltips. +*/ +mark.tertiary { + --mark-back-color: #3cb4e6; } + +mark.tag { + padding: calc(var(--universal-padding)/2) var(--universal-padding); + border-radius: 1em; } + +/* + Definitions for progress elements and spinners. +*/ +/* Progress module CSS variable definitions */ +:root { + --progress-back-color: #3cb4e6; + --progress-fore-color: #555; } + +progress { + display: block; + vertical-align: baseline; + -webkit-appearance: none; + -moz-appearance: none; + appearance: none; + height: 0.75rem; + width: calc(100% - 2 * var(--universal-margin)); + margin: var(--universal-margin); + border: 0; + border-radius: calc(2 * var(--universal-border-radius)); + background: var(--progress-back-color); + color: var(--progress-fore-color); } + progress::-webkit-progress-value { + background: var(--progress-fore-color); + border-top-left-radius: calc(2 * var(--universal-border-radius)); + border-bottom-left-radius: calc(2 * var(--universal-border-radius)); } + progress::-webkit-progress-bar { + background: var(--progress-back-color); } + progress::-moz-progress-bar { + background: var(--progress-fore-color); + border-top-left-radius: calc(2 * var(--universal-border-radius)); + border-bottom-left-radius: calc(2 * var(--universal-border-radius)); } + progress[value="1000"]::-webkit-progress-value { + border-radius: calc(2 * var(--universal-border-radius)); } + progress[value="1000"]::-moz-progress-bar { + border-radius: calc(2 * var(--universal-border-radius)); } + progress.inline { + display: inline-block; + vertical-align: middle; + width: 60%; } + +:root { + --spinner-back-color: #ddd; + --spinner-fore-color: #555; } + +@keyframes spinner-donut-anim { + 0% { + transform: rotate(0deg); } + 100% { + transform: rotate(360deg); } } +.spinner { + display: inline-block; + margin: var(--universal-margin); + border: 0.25rem solid var(--spinner-back-color); + border-left: 0.25rem solid var(--spinner-fore-color); + border-radius: 50%; + width: 1.25rem; + height: 1.25rem; + animation: spinner-donut-anim 1.2s linear infinite; } + +/* + Custom elements for progress bars and spinners. +*/ +progress.primary { + --progress-fore-color: #1976d2; } + +progress.secondary { + --progress-fore-color: #d32f2f; } + +progress.tertiary { + --progress-fore-color: #308732; } + +.spinner.primary { + --spinner-fore-color: #1976d2; } + +.spinner.secondary { + --spinner-fore-color: #d32f2f; } + +.spinner.tertiary { + --spinner-fore-color: #308732; } + +/* + Definitions for icons - powered by Feather (https://feathericons.com/). +*/ +span[class^='icon-'] { + display: inline-block; + height: 1em; + width: 1em; + vertical-align: -0.125em; + background-size: contain; + margin: 0 calc(var(--universal-margin) / 4); } + span[class^='icon-'].secondary { + -webkit-filter: invert(25%); + filter: invert(25%); } + span[class^='icon-'].inverse { + -webkit-filter: invert(100%); + filter: invert(100%); } + +span.icon-alert { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='8' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='16' x2='12' y2='16'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-bookmark { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M19 21l-7-5-7 5V5a2 2 0 0 1 2-2h10a2 2 0 0 1 2 2z'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-calendar { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='4' width='18' height='18' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='16' y1='2' x2='16' y2='6'%3E%3C/line%3E%3Cline x1='8' y1='2' x2='8' y2='6'%3E%3C/line%3E%3Cline x1='3' y1='10' x2='21' y2='10'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-credit { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='1' y='4' width='22' height='16' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='1' y1='10' x2='23' y2='10'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-edit { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 14.66V20a2 2 0 0 1-2 2H4a2 2 0 0 1-2-2V6a2 2 0 0 1 2-2h5.34'%3E%3C/path%3E%3Cpolygon points='18 2 22 6 12 16 8 16 8 12 18 2'%3E%3C/polygon%3E%3C/svg%3E"); } +span.icon-link { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M18 13v6a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2V8a2 2 0 0 1 2-2h6'%3E%3C/path%3E%3Cpolyline points='15 3 21 3 21 9'%3E%3C/polyline%3E%3Cline x1='10' y1='14' x2='21' y2='3'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-help { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M9.09 9a3 3 0 0 1 5.83 1c0 2-3 3-3 3'%3E%3C/path%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='17' x2='12' y2='17'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-home { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M3 9l9-7 9 7v11a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2z'%3E%3C/path%3E%3Cpolyline points='9 22 9 12 15 12 15 22'%3E%3C/polyline%3E%3C/svg%3E"); } +span.icon-info { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='16' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='8' x2='12' y2='8'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-lock { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='11' width='18' height='11' rx='2' ry='2'%3E%3C/rect%3E%3Cpath d='M7 11V7a5 5 0 0 1 10 0v4'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-mail { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 4h16c1.1 0 2 .9 2 2v12c0 1.1-.9 2-2 2H4c-1.1 0-2-.9-2-2V6c0-1.1.9-2 2-2z'%3E%3C/path%3E%3Cpolyline points='22,6 12,13 2,6'%3E%3C/polyline%3E%3C/svg%3E"); } +span.icon-location { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 10c0 7-9 13-9 13s-9-6-9-13a9 9 0 0 1 18 0z'%3E%3C/path%3E%3Ccircle cx='12' cy='10' r='3'%3E%3C/circle%3E%3C/svg%3E"); } +span.icon-phone { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M22 16.92v3a2 2 0 0 1-2.18 2 19.79 19.79 0 0 1-8.63-3.07 19.5 19.5 0 0 1-6-6 19.79 19.79 0 0 1-3.07-8.67A2 2 0 0 1 4.11 2h3a2 2 0 0 1 2 1.72 12.84 12.84 0 0 0 .7 2.81 2 2 0 0 1-.45 2.11L8.09 9.91a16 16 0 0 0 6 6l1.27-1.27a2 2 0 0 1 2.11-.45 12.84 12.84 0 0 0 2.81.7A2 2 0 0 1 22 16.92z'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-rss { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 11a9 9 0 0 1 9 9'%3E%3C/path%3E%3Cpath d='M4 4a16 16 0 0 1 16 16'%3E%3C/path%3E%3Ccircle cx='5' cy='19' r='1'%3E%3C/circle%3E%3C/svg%3E"); } +span.icon-search { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='11' cy='11' r='8'%3E%3C/circle%3E%3Cline x1='21' y1='21' x2='16.65' y2='16.65'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-settings { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='3'%3E%3C/circle%3E%3Cpath d='M19.4 15a1.65 1.65 0 0 0 .33 1.82l.06.06a2 2 0 0 1 0 2.83 2 2 0 0 1-2.83 0l-.06-.06a1.65 1.65 0 0 0-1.82-.33 1.65 1.65 0 0 0-1 1.51V21a2 2 0 0 1-2 2 2 2 0 0 1-2-2v-.09A1.65 1.65 0 0 0 9 19.4a1.65 1.65 0 0 0-1.82.33l-.06.06a2 2 0 0 1-2.83 0 2 2 0 0 1 0-2.83l.06-.06a1.65 1.65 0 0 0 .33-1.82 1.65 1.65 0 0 0-1.51-1H3a2 2 0 0 1-2-2 2 2 0 0 1 2-2h.09A1.65 1.65 0 0 0 4.6 9a1.65 1.65 0 0 0-.33-1.82l-.06-.06a2 2 0 0 1 0-2.83 2 2 0 0 1 2.83 0l.06.06a1.65 1.65 0 0 0 1.82.33H9a1.65 1.65 0 0 0 1-1.51V3a2 2 0 0 1 2-2 2 2 0 0 1 2 2v.09a1.65 1.65 0 0 0 1 1.51 1.65 1.65 0 0 0 1.82-.33l.06-.06a2 2 0 0 1 2.83 0 2 2 0 0 1 0 2.83l-.06.06a1.65 1.65 0 0 0-.33 1.82V9a1.65 1.65 0 0 0 1.51 1H21a2 2 0 0 1 2 2 2 2 0 0 1-2 2h-.09a1.65 1.65 0 0 0-1.51 1z'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-share { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='18' cy='5' r='3'%3E%3C/circle%3E%3Ccircle cx='6' cy='12' r='3'%3E%3C/circle%3E%3Ccircle cx='18' cy='19' r='3'%3E%3C/circle%3E%3Cline x1='8.59' y1='13.51' x2='15.42' y2='17.49'%3E%3C/line%3E%3Cline x1='15.41' y1='6.51' x2='8.59' y2='10.49'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-cart { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='9' cy='21' r='1'%3E%3C/circle%3E%3Ccircle cx='20' cy='21' r='1'%3E%3C/circle%3E%3Cpath d='M1 1h4l2.68 13.39a2 2 0 0 0 2 1.61h9.72a2 2 0 0 0 2-1.61L23 6H6'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-upload { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 15v4a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2v-4'%3E%3C/path%3E%3Cpolyline points='17 8 12 3 7 8'%3E%3C/polyline%3E%3Cline x1='12' y1='3' x2='12' y2='15'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-user { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 21v-2a4 4 0 0 0-4-4H8a4 4 0 0 0-4 4v2'%3E%3C/path%3E%3Ccircle cx='12' cy='7' r='4'%3E%3C/circle%3E%3C/svg%3E"); } + +/* + Definitions for STMicroelectronics icons (https://brandportal.st.com/document/26). +*/ +span.icon-st-update { + background-image: url("Update.svg"); } +span.icon-st-add { + background-image: url("Add button.svg"); } + +/* + Definitions for utilities and helper classes. +*/ +/* Utility module CSS variable definitions */ +:root { + --generic-border-color: rgba(0, 0, 0, 0.3); + --generic-box-shadow: 0 0.2857142857rem 0.2857142857rem 0 rgba(0, 0, 0, 0.125), 0 0.1428571429rem 0.1428571429rem -0.1428571429rem rgba(0, 0, 0, 0.125); } + +.hidden { + display: none !important; } + +.visually-hidden { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } + +.bordered { + border: 0.0714285714rem solid var(--generic-border-color) !important; } + +.rounded { + border-radius: var(--universal-border-radius) !important; } + +.circular { + border-radius: 50% !important; } + +.shadowed { + box-shadow: var(--generic-box-shadow) !important; } + +.responsive-margin { + margin: calc(var(--universal-margin) / 4) !important; } + @media screen and (min-width: 500px) { + .responsive-margin { + margin: calc(var(--universal-margin) / 2) !important; } } + @media screen and (min-width: 1280px) { + .responsive-margin { + margin: var(--universal-margin) !important; } } + +.responsive-padding { + padding: calc(var(--universal-padding) / 4) !important; } + @media screen and (min-width: 500px) { + .responsive-padding { + padding: calc(var(--universal-padding) / 2) !important; } } + @media screen and (min-width: 1280px) { + .responsive-padding { + padding: var(--universal-padding) !important; } } + +@media screen and (max-width: 499px) { + .hidden-sm { + display: none !important; } } +@media screen and (min-width: 500px) and (max-width: 1279px) { + .hidden-md { + display: none !important; } } +@media screen and (min-width: 1280px) { + .hidden-lg { + display: none !important; } } +@media screen and (max-width: 499px) { + .visually-hidden-sm { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } } +@media screen and (min-width: 500px) and (max-width: 1279px) { + .visually-hidden-md { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } } +@media screen and (min-width: 1280px) { + .visually-hidden-lg { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } } + +/*# sourceMappingURL=mini-custom.css.map */ + +img[alt="ST logo"] { display: block; margin: auto; width: 75%; max-width: 250px; min-width: 71px; } +img[alt="Cube logo"] { float: right; width: 30%; max-width: 10rem; min-width: 8rem; padding-right: 1rem;} + +.figure { + display: block; + margin-left: auto; + margin-right: auto; + text-align: center; +} \ No newline at end of file diff --git a/system/Drivers/STM32WBAxx_HAL_Driver/_htmresc/st_logo_2020.png b/system/Drivers/STM32WBAxx_HAL_Driver/_htmresc/st_logo_2020.png new file mode 100644 index 0000000000000000000000000000000000000000..d6cebb5ac70e0594cbe37a6b60036a80ef3bed37 GIT binary patch literal 7520 zcmcI|WmKC@*KTl!K!Z~t6qn*&DDF_CK%q#B6QmH_DHL}I6b%;K-J$eBN|2xh0+bea zmtyV5bG|?CpZBcu=iF<}z4q*xz1LhL*PcBwx;m;Pgmi=e0DweYO-UaBz)*UWZ}4#+ zCC-V!SC16}H#HLv0Dy?%--0o{5_}H;Jf%=ql7H=+dziOk_)KzUSaiQ9L<^g!49k}} z?4y$V zrsn3Ul^TY`00G_J_8;F7Sr5c3Y)f-yOYl{fS0avfKJg7R%r!y-ohcBkr6XBZBkE)( z_t+tVV2}G1_CN!)yWes*wa-AGwk31N_T1`)4COlfz+o(9S90e?6jHV4)!>`j+oRqp z)gb?rtSdw<#&c?q!OKB+Ncn!kr5JR2EYan8HAPXBw*Oh-F(6GmaC!`$p7fl!_Cdu> z5@PUMR_K5&jgevDepWqepZVdMHR$q>ga=7k0ltW$HHVn>HRa!#(+BW_jN$5rx^MtR zzWT7tNWQeFzEp+86jOYI=I)*GZYEiXlf-Mw%tJ^ptL%2)%#PmUjxC4wx@%KxQ)8kO?|7E1 zd@5gd9_$*6nx?fj*iF_EJT*PYLFP}d8*Fw>cu3@&nm%V_C}V7HMmg|Nl#1J1^#)uz zZag|X>{6j-myvL}3(H8o3resNBq_jcuJuyT!QuXnNN&zG^tG? z>y*dy1#XfwyCE#UiLT(~LYAVwp)epErJLsHBA|l0xo)kxLAPob+7tFlr{7x8(#v|O zknK}QC6|~=cTJ0;x9MWMKua;LdTKIHX>35a@7{5y0MQ|zqsP64mM~`gJ&&R{pSUBA zf3Y>k>d|xdzBFztjtO~{y%@LUdwSgzEj=69hH3-NNWx7<|49%2%lvTEeE3_|$~iDd zlktnxf|NB>Bui)yY;%TXgWA;rhODxR!-4GzxKd473I)3;j zS4-Vun<^vqZ4)HbwVzq%5%)S!>Q(Y&PkF ze1ab_oy?_$PZT-mKJ3K^;6MrB*Wc$lkYJ_460AFYEq{AjlDxm;5GRwOsm>doJy3Z;a$FSu-q`X)Hw&o~?_`Dnpx4dOj6#)bGOdZbj4hD`l|&#v~K+WrGO zpLCVQg=*h=4H1sK)D*Pxtb#p`c+g-eK65k!CEZjLIrfm}5<4@KVqZ#8(S$vs{?Xv) zN(}CKeeLR%I)W!p(l-`utKmBbJk-On{)ciqUN5%?TS8uwKU(8}Mxhsb&qHL~DDcB@qi} z4z%efV#K69a#lShPt5}*7ME@^xunFR{k;|qp z`_Hgdj_Qle?%Ydlr3f^SdRkUncIj7qTiu85tA$v`#419Nlof8tjqUjO z!Rwyq$Krfh`(@MiE+)yie&jU^crprYV&?zN!2b33S2qtW+zB$nahDhVZiQ12bmcwYBcT8KS>v`jsuI@X zy^k^7>TM5Ndp@}pSl6vmkk*u`@C`z(gq||K2>y=Y#w1i`Nk2zAP7{_^ACq;bQmT<4 z;b~K3=?mhZX#~jQnZjdU={NFp^HRr~;^PXQ*UIHzkq}Xsn!56*ZCOOEt|^ zawUwGqs;zCEGKTz&(a(@h#0sCE+@`3Y<&}9!(;Pw&`C+d#D?`##&!@*ERaH0fksrh zfk2svh3!d~h{SC6BNKN2j6(lzC>S^_*eh{@gR zP$rV4$nqV1y|zYpd;nQr-`Vlp(5sQXx9AibC?xc7pUV)v2cWfHu3{KLbfP;;;`I&)mWqLcXt6s+5fps9R?K>hGR$5;=( zo#;zzQ5!w+(99p1_gh^?F#$tpMd+4%G|K`XG_#@A>30WD2L9!0a>wRASg`M?^z#)| zifb$d^KUD&3qLsr-@}r_7p${gdmRqhy819bj?yI-v({I?0o3_8d>CZmCzqH4{{QtD z|6dvgm<^~668G`6wLw4C4y-o9E9ZG3RiH^&;rrKSBT@bMR+!TlYo*9P;?Z>xORMV3ndQp9EyNn!!~j&x&$gDVke|t#!{QoegHm+sT7cSjwSu z)jZlx1pHrrx0&YCZWJ4xC&U%r_IwfJOxnYqYMcZn&_hgnKuls z>(Y$qjIhcweo^A_VVq_#UR&urF%UbI^><5L5zbV9owMQviM*_{@i|dke!!v8a_yG! zl%#ay{(6U_N3-)yeif3tx6>aQSf1r zO~OuNW<8a~bi6Xby0@tKw0@f1R!@+3S2nf#F&j~l0mrNCtjoZdPYob?g!Vx4F-uA2 z4uS>8eR?dA9i>C|cm-m5lO0m@$f(DB6Z<9Pe07xR`l4$ks3eZ@v5}1?^YNQy-tB(` zgUNZrGVf#b~`}jew;MQG1O~VDk_i*<)p9DfFfd;vLy4QZT zMYh|DxJg3-!{szUN*uo&`&DUkzq4qG2`Lj;Ar46DYUymcviS{Unhzmx z=LwZ-Lr{t1z?9Oip%!z{j+Z%_@u?C78I`V4fC`icG1c|2;`EoLK$ z)9|wrAV&V1Vgts~tQCw0X?X{74W"NJQ zW3BP!5c~4zzHJScwQK9L_%m%L`*q{1aW_3rObki~B~=Dwp`;@w`>xZ6;L_6oR^ecEcmup`yb}lgsmv zQByrxc)Qqm(Hwmq%fLjqcrJ5QR?z_*vb~Iy~RXUY8u-D8AqTzetwNNA8~N z$j&1>#IrkSslUqXW|l}q_TlTVKAjRI@~7(GLf4M>GM!3u_)y6ORe6BQUmrQ16%OdZKo(?AYXK$u@=)TPUi1EZaLBu zuEB(5GX2vcoHS%zMUW!DZ)&xRo@mhouk|hMgHIG>cO-Ah(0AMNlq@?cPpy==-!#qR zBov7l3G?P*KM(vU;Apo-(-Bw;sdQJkh~r)W$KRQKd!#(A8M34^MhD10Ra={AqSvjy z3>PkgA}f^@Rg1$dX=jaEB_V%_vn(W<111_s!g>CYrcwJTJ63Eeg6{_C`aMQIgKctR zHMjkr+y6gK!v6=6;CGl#?PqmiX`A@dmmvZ}-X$*q8}G(xq|voo`=$YZuQAa8f9ApK z1VQiEUQC=OO{|Nc8ZrXH208X|XCzIRO?+Nb55Jt@va9hqBpv)uY6ma-csvSlJoJOC zK;w~s?#r)K@gm*;((JsWHU-KvFTF)q>AzwPq)I+}OrSpxh!-CM1VEMfw1fpfVL7p{ z)I$rNp5kPYDsvXL>8nV{#0fa*lm`Z;0Z=c^1qveY2uk&7nhMRl`0EsvUuvwdF&o)PCVN3wmFBPegWzooF6y~b} zY>X2;LO~&rbvx59?(4^aR+s1C6hI4r&x9Q9jL9);KZEw_x%TWZXaMzK6|2XG9$IU% zkEq}t^YOaa4s`%7F31X-#SfMgNp+4R=g2G|O^W)6^2fEsmkTTaVhKCip+3qWuN8?y zaSD_k6%-@Ifhm`z02=ZWA-pi5`A=7ztHWpP2K5rCW{>!wIUOYrH``#bz>qVSH76=8 zyJ!sNBxt;dMTn}yzUTCq1!w;N7pzb?WJrQ50W+`meL{k8i0VhFsPUz(07k`l` zg1Ifl1fc-^p^MQCpK~Jk&L!*mWfNA!&MSu`sPmti>K-;I5Dk00nB3vOl4!JwjEx^X zWQsIp2Ea_>`9f@%zGl4i3FAO9=e$2^b_>_I*dqiLJ=@TejStM?^yX$9dW`#ha)PEF zPr0zUJX!j-juYK*olG_9axQniXhF|E}oSTG_S)FZ3sN4T@q zy{l;!{UGc};YVaT97tx3s7P$WsW2^*I+Hy;vqndG!9S?tZtDIRif1=bBsqtW-n7$O zWy}Z%jKSkgLX#1p>|#4l-!$c+kA`++Ixv(Rm`;Ilb3q3tD|QjaPQ8)BJ=8R*15?nL zJR{yuqOG&!JrSZ${#NY#b!k)yDajQ$A}fUQhe7ueN6h2Pj3wY5eo|7$PaJD zM69(ee1qlSyLn)Ln6)o53Lj)elqG}gb^c}qd(q&$8B5N%nSvEjUIoEXO^obv=A7QGZzNzjO*H=*b2!86Wnqdy~8ePkq@1D1)Q^O)JG;fUCV z`rgD}dJ{7BUyBbgoTL91w^q-CfBpDr?0R38`L%p9&Q#%r*@=9p-Ioqy+WscLq?jq5 zfyYNkxr7w)-(!c85mt!FjNJ4UE6P8p8sc#Kb4L1N3!yaCo9@t3n8s}K)1!w8x77xU zo-NY3SR*Pgt#~7F;y^J&Y%z^+C9wu;hN|TC7dqSHOB&kE)Q)6Ad(l&+tA@$@w0bhJ z6xc6EJ6nm{=|V7Vo&qcXc4i)D?X0Uk$p7~iI#ci?#fxvM z78`u%m5S@^_F;_foidufzP z&ueh-zU1yM&8~0lmOfkio-gBex`)?hCJcI8Jv*R0c|WUqSq z?RU?Rmm=3t_2C%%UW9c*D%T{T{EjryCKnsz9-*Bs0}M*xS&-odhCK5eS_Eqi&c6J4o|f&;uUT=p7Fedw#EUl4%Jv{w zq-cCF^otBvw~~$yj6O>>;VqU)3Ml&Atm$B(Ht8=+&x2VS5aWD&t*+04{@k^Gn~yHY zWYC%@ld;g_qz=k*;Iv&xs5M85cEZCU&n2Baf>R6*bN>V|!)eF&l#C93eAMLD=ZF7= zOISFfB5P;F!ngWD3jfMJE_53F&dFc{h2TwSbT*(h6!c}_5_UFeB_*DiyCrtQ7Byr@ z-aCWVt?J}YP7-lfelbrCgZ5mdv(^W&Yf^OvpI}#NbS1Lc`r4&t#3kM!utm&#a;?GR z-1FusfX7&?a9h`%8wf-ub7UXp44xm4w04)S$}}_hPqn-#IabO^bo6$K07>?%G5Xs( zA$*lz_K>lAJ_o<;fsP-*-%~O(716KRqVq+X@=5J~Z~bba(yWL`;EN`@Mr2it&Lkgb z&I|R5!`ZSk%)xFX*FYDaAh=5qWSY@rx1Du9J$$=lh#!~NcFJM&aOv)eqg_@`i^zJCR9a%_{k_i%msw5q z*3!~#Xx3r|VaAwiG}~9M#c`=$Uk6~xe)47ymW+;0DD_lV67L#ouJBa7mF{)X^?eIvPdOMu4ksr`jUP$~{x@?ev2 zdX#ite2RMim01PEg`;qfwg^;v8nx9F!CtNCvz)V{PVgCs*;_@_Rk*oLx@f7hJ7^^1 zu66b)mb!ZMXLZ%8dj-+JCMoWS-Wji-Q-~U7Pt~UiXMej8JcNjk<6?Wk9eLBIhu&Vo^0;AH> z;Q5^a!NZhP(vDfBv&?jdnQavv#8N0E{ZEgs>|1)qYo^t5 zIV$g~`C2%g$*(z4)8hJlK2mF-MJW#3%Cs6`uAvsgRtTo8n!Et)1pZx@_9I18 zw7ER9v~DyrC*R$do9aEw5r@B)YzHOLB^-c9Eu9D!sFmI8^VljVKE89{zY_8PTSF+J b^}%0^qYmp2WD(pA|JtZ4>nPPKybJpu3@X?! literal 0 HcmV?d00001 diff --git a/system/Drivers/STM32YYxx_HAL_Driver_version.md b/system/Drivers/STM32YYxx_HAL_Driver_version.md index ac1a8e75ff..101a5722e8 100644 --- a/system/Drivers/STM32YYxx_HAL_Driver_version.md +++ b/system/Drivers/STM32YYxx_HAL_Driver_version.md @@ -18,6 +18,7 @@ * STM32MP1: 1.6.0 * STM32U5: 1.4.0 * STM32WB: 1.14.1 + * STM32WBA: 1.2.0 * STM32WL: 1.3.0 Release notes of each STM32YYxx HAL Drivers available here: From af7aca69b8d673f3b3e67353f758aa0e48dbb8f6 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Fri, 9 Feb 2024 16:07:26 +0100 Subject: [PATCH 02/21] system(WBA): add STM32WBAxx CMSIS Drivers to v1.2.0 Included in STM32CubeWBA FW v1.2.0 Signed-off-by: Frederic Pillon --- .../Templates/partition_stm32wba52xx.h | 590 + .../Templates/partition_stm32wba54xx.h | 593 + .../Templates/partition_stm32wba55xx.h | 593 + .../STM32WBAxx/Include/partition_stm32wbaxx.h | 70 + .../ST/STM32WBAxx/Include/stm32wba50xx.h | 10396 ++++++++++ .../ST/STM32WBAxx/Include/stm32wba52xx.h | 15093 +++++++++++++++ .../ST/STM32WBAxx/Include/stm32wba54xx.h | 15801 +++++++++++++++ .../ST/STM32WBAxx/Include/stm32wba55xx.h | 15819 ++++++++++++++++ .../Device/ST/STM32WBAxx/Include/stm32wbaxx.h | 235 + .../ST/STM32WBAxx/Include/system_stm32wbaxx.h | 108 + .../CMSIS/Device/ST/STM32WBAxx/LICENSE.md | 201 + .../CMSIS/Device/ST/STM32WBAxx/README.md | 36 + .../Device/ST/STM32WBAxx/Release_Notes.html | 145 + .../gcc/linker/STM32WBA50xx_FLASH.ld | 185 + .../Templates/gcc/linker/STM32WBA50xx_RAM.ld | 185 + .../gcc/linker/STM32WBA52xx_FLASH.ld | 185 + .../gcc/linker/STM32WBA52xx_FLASH_ns.ld | 185 + .../gcc/linker/STM32WBA52xx_FLASH_s.ld | 193 + .../Templates/gcc/linker/STM32WBA52xx_RAM.ld | 185 + .../gcc/linker/STM32WBA52xx_RAM_ns.ld | 185 + .../gcc/linker/STM32WBA52xx_RAM_s.ld | 193 + .../gcc/linker/STM32WBA54xx_FLASH.ld | 185 + .../gcc/linker/STM32WBA54xx_FLASH_ns.ld | 185 + .../gcc/linker/STM32WBA54xx_FLASH_s.ld | 193 + .../Templates/gcc/linker/STM32WBA54xx_RAM.ld | 185 + .../gcc/linker/STM32WBA54xx_RAM_ns.ld | 185 + .../gcc/linker/STM32WBA54xx_RAM_s.ld | 193 + .../gcc/linker/STM32WBA55xx_FLASH.ld | 185 + .../gcc/linker/STM32WBA55xx_FLASH_ns.ld | 185 + .../gcc/linker/STM32WBA55xx_FLASH_s.ld | 193 + .../Templates/gcc/linker/STM32WBA55xx_RAM.ld | 185 + .../gcc/linker/STM32WBA55xx_RAM_ns.ld | 185 + .../gcc/linker/STM32WBA55xx_RAM_s.ld | 193 + .../Templates/gcc/startup_stm32wba50xx.s | 423 + .../Templates/gcc/startup_stm32wba52xx.s | 464 + .../Templates/gcc/startup_stm32wba54xx.s | 474 + .../Templates/gcc/startup_stm32wba55xx.s | 474 + .../Source/Templates/system_stm32wbaxx.c | 381 + .../Source/Templates/system_stm32wbaxx_ns.c | 233 + .../Source/Templates/system_stm32wbaxx_s.c | 418 + .../ST/STM32WBAxx/_htmresc/Add button.svg | 2 + .../Device/ST/STM32WBAxx/_htmresc/Update.svg | 2 + .../Device/ST/STM32WBAxx/_htmresc/favicon.png | Bin 0 -> 4126 bytes .../ST/STM32WBAxx/_htmresc/mini-st_2020.css | 1711 ++ .../ST/STM32WBAxx/_htmresc/st_logo_2020.png | Bin 0 -> 7520 bytes .../Device/ST/STM32YYxx_CMSIS_version.md | 1 + 46 files changed, 68011 insertions(+) create mode 100644 system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/Templates/partition_stm32wba52xx.h create mode 100644 system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/Templates/partition_stm32wba54xx.h create mode 100644 system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/Templates/partition_stm32wba55xx.h create mode 100644 system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/partition_stm32wbaxx.h create mode 100644 system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba50xx.h create mode 100644 system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba52xx.h create mode 100644 system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba54xx.h create mode 100644 system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba55xx.h create mode 100644 system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wbaxx.h create mode 100644 system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/system_stm32wbaxx.h create mode 100644 system/Drivers/CMSIS/Device/ST/STM32WBAxx/LICENSE.md create mode 100644 system/Drivers/CMSIS/Device/ST/STM32WBAxx/README.md create mode 100644 system/Drivers/CMSIS/Device/ST/STM32WBAxx/Release_Notes.html create mode 100644 system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA50xx_FLASH.ld create mode 100644 system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA50xx_RAM.ld create mode 100644 system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA52xx_FLASH.ld create mode 100644 system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA52xx_FLASH_ns.ld create mode 100644 system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA52xx_FLASH_s.ld create mode 100644 system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA52xx_RAM.ld create mode 100644 system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA52xx_RAM_ns.ld create mode 100644 system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA52xx_RAM_s.ld create mode 100644 system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA54xx_FLASH.ld create mode 100644 system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA54xx_FLASH_ns.ld create mode 100644 system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA54xx_FLASH_s.ld create mode 100644 system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA54xx_RAM.ld create mode 100644 system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA54xx_RAM_ns.ld create mode 100644 system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA54xx_RAM_s.ld create mode 100644 system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA55xx_FLASH.ld create mode 100644 system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA55xx_FLASH_ns.ld create mode 100644 system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA55xx_FLASH_s.ld create mode 100644 system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA55xx_RAM.ld create mode 100644 system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA55xx_RAM_ns.ld create mode 100644 system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA55xx_RAM_s.ld create mode 100644 system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/startup_stm32wba50xx.s create mode 100644 system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/startup_stm32wba52xx.s create mode 100644 system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/startup_stm32wba54xx.s create mode 100644 system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/startup_stm32wba55xx.s create mode 100644 system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/system_stm32wbaxx.c create mode 100644 system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/system_stm32wbaxx_ns.c create mode 100644 system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/system_stm32wbaxx_s.c create mode 100644 system/Drivers/CMSIS/Device/ST/STM32WBAxx/_htmresc/Add button.svg create mode 100644 system/Drivers/CMSIS/Device/ST/STM32WBAxx/_htmresc/Update.svg create mode 100644 system/Drivers/CMSIS/Device/ST/STM32WBAxx/_htmresc/favicon.png create mode 100644 system/Drivers/CMSIS/Device/ST/STM32WBAxx/_htmresc/mini-st_2020.css create mode 100644 system/Drivers/CMSIS/Device/ST/STM32WBAxx/_htmresc/st_logo_2020.png diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/Templates/partition_stm32wba52xx.h b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/Templates/partition_stm32wba52xx.h new file mode 100644 index 0000000000..ade3f2dbe0 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/Templates/partition_stm32wba52xx.h @@ -0,0 +1,590 @@ +/** + ****************************************************************************** + * @file partition_stm32wba52xx.h + * @author MCD Application Team + * @brief CMSIS STM32WBA52xx Device Initial Setup for Secure / Non-Secure Zones + * for ARMCM33 based on CMSIS CORE V5.4.0 partition_ARMCM33.h Template. + * + * This file contains: + * - Initialize Security Attribution Unit (SAU) CTRL register + * - Setup behavior of Sleep and Exception Handling + * - Setup behavior of Floating Point Unit + * - Setup Interrupt Target + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * Copyright (c) 2022 STMicroelectronics. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ****************************************************************************** + */ + +#ifndef PARTITION_STM32WBA52XX_H +#define PARTITION_STM32WBA52XX_H + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +*/ + +/* +// Initialize Security Attribution Unit (SAU) CTRL register +*/ +#define SAU_INIT_CTRL 1 + +/* +// Enable SAU +// Value for SAU->CTRL register bit ENABLE +*/ +#define SAU_INIT_CTRL_ENABLE 1 + +/* +// When SAU is disabled +// <0=> All Memory is Secure +// <1=> All Memory is Non-Secure +// Value for SAU->CTRL register bit ALLNS +// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. +*/ +#define SAU_INIT_CTRL_ALLNS 0 + +/* +// +*/ + +/* +// Initialize Security Attribution Unit (SAU) Address Regions +// SAU configuration specifies regions to be one of: +// - Secure and Non-Secure Callable +// - Non-Secure +// Note: All memory regions not configured by SAU are Secure +*/ +#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ + +/* +// Initialize SAU Region 0 +// Setup SAU Region 0 memory attributes +*/ +#define SAU_INIT_REGION0 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START0 0x08080000 /* start address of SAU region 0 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END0 0x080FFFFF /* end address of SAU region 0 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC0 0 +/* +// +*/ + +/* +// Initialize SAU Region 1 +// Setup SAU Region 1 memory attributes +*/ +#define SAU_INIT_REGION1 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START1 0x0BF88000 /* start address of SAU region 1 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END1 0x0BF97FFF /* end address of SAU region 1 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC1 0 +/* +// +*/ + +/* +// Initialize SAU Region 2 +// Setup SAU Region 2 memory attributes +*/ +#define SAU_INIT_REGION2 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START2 0x0C07E000 /* start address of SAU region 2 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END2 0x0C07FFFF /* end address of SAU region 2 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC2 1 +/* +// +*/ + +/* +// Initialize SAU Region 3 +// Setup SAU Region 3 memory attributes +*/ +#define SAU_INIT_REGION3 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START3 0x20010000 /* start address of SAU region 3 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END3 0x2001FFFF /* end address of SAU region 3 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC3 0 +/* +// +*/ + +/* +// Initialize SAU Region 4 +// Setup SAU Region 4 memory attributes +*/ +#define SAU_INIT_REGION4 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START4 0x40000000 /* start address of SAU region 4 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END4 0x4FFFFFFF /* end address of SAU region 4 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC4 0 +/* +// +*/ + +/* +// Initialize SAU Region 5 +// Setup SAU Region 5 memory attributes +*/ +#define SAU_INIT_REGION5 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START5 0x00000000 /* start address of SAU region 5 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END5 0x00000000 /* end address of SAU region 5 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC5 0 +/* +// +*/ + +/* +// Initialize SAU Region 6 +// Setup SAU Region 6 memory attributes +*/ +#define SAU_INIT_REGION6 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START6 0x00000000 /* start address of SAU region 6 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END6 0x00000000 /* end address of SAU region 6 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC6 0 +/* +// +*/ + +/* +// Initialize SAU Region 7 +// Setup SAU Region 7 memory attributes +*/ +#define SAU_INIT_REGION7 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START7 0x00000000 /* start address of SAU region 7 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END7 0x00000000 /* end address of SAU region 7 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC7 0 +/* +// +*/ + +/* +// +*/ + +/* +// Setup behaviour of Sleep and Exception Handling +*/ +#define SCB_CSR_AIRCR_INIT 0 + +/* +// Deep Sleep can be enabled by +// <0=>Secure and Non-Secure state +// <1=>Secure state only +// Value for SCB->CSR register bit DEEPSLEEPS +*/ +#define SCB_CSR_DEEPSLEEPS_VAL 0 + +/* +// System reset request accessible from +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for SCB->AIRCR register bit SYSRESETREQS +*/ +#define SCB_AIRCR_SYSRESETREQS_VAL 0 + +/* +// Priority of Non-Secure exceptions is +// <0=> Not altered +// <1=> Lowered to 0x04-0x07 +// Value for SCB->AIRCR register bit PRIS +*/ +#define SCB_AIRCR_PRIS_VAL 0 + +/* +// BusFault, HardFault, and NMI target +// <0=> Secure state +// <1=> Non-Secure state +// Value for SCB->AIRCR register bit BFHFNMINS +*/ +#define SCB_AIRCR_BFHFNMINS_VAL 0 + +/* +// +*/ + +/* +// Setup behaviour of Floating Point Unit +*/ +#define TZ_FPU_NS_USAGE 1 + +/* +// Floating Point Unit usage +// <0=> Secure state only +// <3=> Secure and Non-Secure state +// Value for SCB->NSACR register bits CP10, CP11 +*/ +#define SCB_NSACR_CP10_11_VAL 3 + +/* +// Treat floating-point registers as Secure +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit TS +*/ +#define FPU_FPCCR_TS_VAL 0 + +/* +// Clear on return (CLRONRET) accessibility +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for FPU->FPCCR register bit CLRONRETS +*/ +#define FPU_FPCCR_CLRONRETS_VAL 0 + +/* +// Clear floating-point caller saved registers on exception return +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit CLRONRET +*/ +#define FPU_FPCCR_CLRONRET_VAL 1 + +/* +// +*/ + +/* +// Setup Interrupt Target +*/ + +/* +// Initialize ITNS 0 (Interrupts 0..31) +*/ +#define NVIC_INIT_ITNS0 1 + +/* +// Interrupts 0..31 +// WWDG_IRQn <0=> Secure state <1=> Non-Secure state +// PVD_IRQn <0=> Secure state <1=> Non-Secure state +// RTC_IRQn <0=> Secure state <1=> Non-Secure state +// RTC_S_IRQn <0=> Secure state <1=> Non-Secure state +// TAMP_IRQn <0=> Secure state <1=> Non-Secure state +// RAMCFG_IRQn <0=> Secure state <1=> Non-Secure state +// FLASH_IRQn <0=> Secure state <1=> Non-Secure state +// FLASH_S_IRQn <0=> Secure state <1=> Non-Secure state +// GTZC_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_S_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI0_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI1_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI2_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI3_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI4_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI5_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI6_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI7_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI8_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI9_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI10_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI11_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI12_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI13_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI14_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI15_IRQn <0=> Secure state <1=> Non-Secure state +// IWDG_IRQn <0=> Secure state <1=> Non-Secure state +// SAES_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA_Channel0_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA_Channel1_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA_Channel2_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS0_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 1 (Interrupts 32..63) +*/ +#define NVIC_INIT_ITNS1 1 + +/* +// Interrupts 32..63 +// GPDMA_Channel3_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA_Channel4_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA_Channel5_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA_Channel6_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA_Channel7_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_UP_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_CC_IRQn <0=> Secure state <1=> Non-Secure state +// TIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM3_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_ER_IRQn <0=> Secure state <1=> Non-Secure state +// SPI1_IRQn <0=> Secure state <1=> Non-Secure state +// USART1_IRQn <0=> Secure state <1=> Non-Secure state +// USART2_IRQn <0=> Secure state <1=> Non-Secure state +// LPUART1_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM1_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM16_IRQn <0=> Secure state <1=> Non-Secure state +// TIM17_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_ER_IRQn <0=> Secure state <1=> Non-Secure state +// TSC_IRQn <0=> Secure state <1=> Non-Secure state +// AES_IRQn <0=> Secure state <1=> Non-Secure state +// RNG_IRQn <0=> Secure state <1=> Non-Secure state +// FPU_IRQn <0=> Secure state <1=> Non-Secure state +// HASH_IRQn <0=> Secure state <1=> Non-Secure state +// PKA_IRQn <0=> Secure state <1=> Non-Secure state +// SPI3_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS1_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 2 (Interrupts 64..95) +*/ +#define NVIC_INIT_ITNS2 1 + +/* +// Interrupts 64..95 +// ICACHE_IRQn <0=> Secure state <1=> Non-Secure state +// ADC4_IRQn <0=> Secure state <1=> Non-Secure state +// RADIO_IRQn <0=> Secure state <1=> Non-Secure state +// WKUP_IRQn <0=> Secure state <1=> Non-Secure state +// HSEM_IRQn <0=> Secure state <1=> Non-Secure state +// HSEM_S_IRQn <0=> Secure state <1=> Non-Secure state +// WKUP_S_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS2_VAL 0x00000000 + +/* +// +*/ + +/* +// +*/ + +/* + max 8 SAU regions. + SAU regions are defined in partition.h + */ + +#define SAU_INIT_REGION(n) \ + SAU->RNR = (n & SAU_RNR_REGION_Msk); \ + SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ + SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ + ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U + +/** + \brief Setup a SAU Region + \details Writes the region information contained in SAU_Region to the + registers SAU_RNR, SAU_RBAR, and SAU_RLAR + */ +__STATIC_INLINE void TZ_SAU_Setup (void) +{ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + + #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) + SAU_INIT_REGION(0); + #endif + + #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) + SAU_INIT_REGION(1); + #endif + + #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) + SAU_INIT_REGION(2); + #endif + + #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) + SAU_INIT_REGION(3); + #endif + + #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) + SAU_INIT_REGION(4); + #endif + + #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) + SAU_INIT_REGION(5); + #endif + + #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) + SAU_INIT_REGION(6); + #endif + + #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) + SAU_INIT_REGION(7); + #endif + + /* repeat this for all possible SAU regions */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + + + #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) + SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | + ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; + #endif + + #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) + SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | + ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); + + SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | + SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) | + ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | + ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | + ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | + ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); + #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ + + #if defined (__FPU_USED) && (__FPU_USED == 1U) && \ + defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) + + SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | + ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); + + FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | + ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | + ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | + ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); + #endif + + #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) + NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; + #endif + + #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) + NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; + #endif + + #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) + NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; + #endif + +} + +#endif /* PARTITION_STM32WBA52XX_H */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/Templates/partition_stm32wba54xx.h b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/Templates/partition_stm32wba54xx.h new file mode 100644 index 0000000000..30b3a85f9d --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/Templates/partition_stm32wba54xx.h @@ -0,0 +1,593 @@ +/** + ****************************************************************************** + * @file partition_stm32wba54xx.h + * @author MCD Application Team + * @brief CMSIS STM32WBA54xx Device Initial Setup for Secure / Non-Secure Zones + * for ARMCM33 based on CMSIS CORE V5.4.0 partition_ARMCM33.h Template. + * + * This file contains: + * - Initialize Security Attribution Unit (SAU) CTRL register + * - Setup behavior of Sleep and Exception Handling + * - Setup behavior of Floating Point Unit + * - Setup Interrupt Target + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * Copyright (c) 2022 STMicroelectronics. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ****************************************************************************** + */ + +#ifndef PARTITION_STM32WBA54XX_H +#define PARTITION_STM32WBA54XX_H + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +*/ + +/* +// Initialize Security Attribution Unit (SAU) CTRL register +*/ +#define SAU_INIT_CTRL 1 + +/* +// Enable SAU +// Value for SAU->CTRL register bit ENABLE +*/ +#define SAU_INIT_CTRL_ENABLE 1 + +/* +// When SAU is disabled +// <0=> All Memory is Secure +// <1=> All Memory is Non-Secure +// Value for SAU->CTRL register bit ALLNS +// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. +*/ +#define SAU_INIT_CTRL_ALLNS 0 + +/* +// +*/ + +/* +// Initialize Security Attribution Unit (SAU) Address Regions +// SAU configuration specifies regions to be one of: +// - Secure and Non-Secure Callable +// - Non-Secure +// Note: All memory regions not configured by SAU are Secure +*/ +#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ + +/* +// Initialize SAU Region 0 +// Setup SAU Region 0 memory attributes +*/ +#define SAU_INIT_REGION0 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START0 0x08080000 /* start address of SAU region 0 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END0 0x080FFFFF /* end address of SAU region 0 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC0 0 +/* +// +*/ + +/* +// Initialize SAU Region 1 +// Setup SAU Region 1 memory attributes +*/ +#define SAU_INIT_REGION1 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START1 0x0BF88000 /* start address of SAU region 1 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END1 0x0BF97FFF /* end address of SAU region 1 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC1 0 +/* +// +*/ + +/* +// Initialize SAU Region 2 +// Setup SAU Region 2 memory attributes +*/ +#define SAU_INIT_REGION2 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START2 0x0C07E000 /* start address of SAU region 2 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END2 0x0C07FFFF /* end address of SAU region 2 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC2 1 +/* +// +*/ + +/* +// Initialize SAU Region 3 +// Setup SAU Region 3 memory attributes +*/ +#define SAU_INIT_REGION3 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START3 0x20010000 /* start address of SAU region 3 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END3 0x2001FFFF /* end address of SAU region 3 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC3 0 +/* +// +*/ + +/* +// Initialize SAU Region 4 +// Setup SAU Region 4 memory attributes +*/ +#define SAU_INIT_REGION4 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START4 0x40000000 /* start address of SAU region 4 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END4 0x4FFFFFFF /* end address of SAU region 4 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC4 0 +/* +// +*/ + +/* +// Initialize SAU Region 5 +// Setup SAU Region 5 memory attributes +*/ +#define SAU_INIT_REGION5 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START5 0x00000000 /* start address of SAU region 5 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END5 0x00000000 /* end address of SAU region 5 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC5 0 +/* +// +*/ + +/* +// Initialize SAU Region 6 +// Setup SAU Region 6 memory attributes +*/ +#define SAU_INIT_REGION6 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START6 0x00000000 /* start address of SAU region 6 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END6 0x00000000 /* end address of SAU region 6 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC6 0 +/* +// +*/ + +/* +// Initialize SAU Region 7 +// Setup SAU Region 7 memory attributes +*/ +#define SAU_INIT_REGION7 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START7 0x00000000 /* start address of SAU region 7 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END7 0x00000000 /* end address of SAU region 7 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC7 0 +/* +// +*/ + +/* +// +*/ + +/* +// Setup behaviour of Sleep and Exception Handling +*/ +#define SCB_CSR_AIRCR_INIT 0 + +/* +// Deep Sleep can be enabled by +// <0=>Secure and Non-Secure state +// <1=>Secure state only +// Value for SCB->CSR register bit DEEPSLEEPS +*/ +#define SCB_CSR_DEEPSLEEPS_VAL 0 + +/* +// System reset request accessible from +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for SCB->AIRCR register bit SYSRESETREQS +*/ +#define SCB_AIRCR_SYSRESETREQS_VAL 0 + +/* +// Priority of Non-Secure exceptions is +// <0=> Not altered +// <1=> Lowered to 0x04-0x07 +// Value for SCB->AIRCR register bit PRIS +*/ +#define SCB_AIRCR_PRIS_VAL 0 + +/* +// BusFault, HardFault, and NMI target +// <0=> Secure state +// <1=> Non-Secure state +// Value for SCB->AIRCR register bit BFHFNMINS +*/ +#define SCB_AIRCR_BFHFNMINS_VAL 0 + +/* +// +*/ + +/* +// Setup behaviour of Floating Point Unit +*/ +#define TZ_FPU_NS_USAGE 1 + +/* +// Floating Point Unit usage +// <0=> Secure state only +// <3=> Secure and Non-Secure state +// Value for SCB->NSACR register bits CP10, CP11 +*/ +#define SCB_NSACR_CP10_11_VAL 3 + +/* +// Treat floating-point registers as Secure +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit TS +*/ +#define FPU_FPCCR_TS_VAL 0 + +/* +// Clear on return (CLRONRET) accessibility +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for FPU->FPCCR register bit CLRONRETS +*/ +#define FPU_FPCCR_CLRONRETS_VAL 0 + +/* +// Clear floating-point caller saved registers on exception return +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit CLRONRET +*/ +#define FPU_FPCCR_CLRONRET_VAL 1 + +/* +// +*/ + +/* +// Setup Interrupt Target +*/ + +/* +// Initialize ITNS 0 (Interrupts 0..31) +*/ +#define NVIC_INIT_ITNS0 1 + +/* +// Interrupts 0..31 +// WWDG_IRQn <0=> Secure state <1=> Non-Secure state +// PVD_IRQn <0=> Secure state <1=> Non-Secure state +// RTC_IRQn <0=> Secure state <1=> Non-Secure state +// RTC_S_IRQn <0=> Secure state <1=> Non-Secure state +// TAMP_IRQn <0=> Secure state <1=> Non-Secure state +// RAMCFG_IRQn <0=> Secure state <1=> Non-Secure state +// FLASH_IRQn <0=> Secure state <1=> Non-Secure state +// FLASH_S_IRQn <0=> Secure state <1=> Non-Secure state +// GTZC_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_S_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI0_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI1_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI2_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI3_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI4_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI5_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI6_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI7_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI8_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI9_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI10_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI11_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI12_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI13_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI14_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI15_IRQn <0=> Secure state <1=> Non-Secure state +// IWDG_IRQn <0=> Secure state <1=> Non-Secure state +// SAES_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA_Channel0_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA_Channel1_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA_Channel2_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS0_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 1 (Interrupts 32..63) +*/ +#define NVIC_INIT_ITNS1 1 + +/* +// Interrupts 32..63 +// GPDMA_Channel3_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA_Channel4_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA_Channel5_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA_Channel6_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA_Channel7_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_UP_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_CC_IRQn <0=> Secure state <1=> Non-Secure state +// TIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM3_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_ER_IRQn <0=> Secure state <1=> Non-Secure state +// SPI1_IRQn <0=> Secure state <1=> Non-Secure state +// USART1_IRQn <0=> Secure state <1=> Non-Secure state +// USART2_IRQn <0=> Secure state <1=> Non-Secure state +// LPUART1_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM1_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM16_IRQn <0=> Secure state <1=> Non-Secure state +// TIM17_IRQn <0=> Secure state <1=> Non-Secure state +// COMP_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_ER_IRQn <0=> Secure state <1=> Non-Secure state +// SAI1_IRQn <0=> Secure state <1=> Non-Secure state +// TSC_IRQn <0=> Secure state <1=> Non-Secure state +// AES_IRQn <0=> Secure state <1=> Non-Secure state +// RNG_IRQn <0=> Secure state <1=> Non-Secure state +// FPU_IRQn <0=> Secure state <1=> Non-Secure state +// HASH_IRQn <0=> Secure state <1=> Non-Secure state +// PKA_IRQn <0=> Secure state <1=> Non-Secure state +// SPI3_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS1_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 2 (Interrupts 64..95) +*/ +#define NVIC_INIT_ITNS2 1 + +/* +// Interrupts 64..95 +// ICACHE_IRQn <0=> Secure state <1=> Non-Secure state +// ADC4_IRQn <0=> Secure state <1=> Non-Secure state +// RADIO_IRQn <0=> Secure state <1=> Non-Secure state +// WKUP_IRQn <0=> Secure state <1=> Non-Secure state +// HSEM_IRQn <0=> Secure state <1=> Non-Secure state +// HSEM_S_IRQn <0=> Secure state <1=> Non-Secure state +// WKUP_S_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_AUDIOSYNC_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS2_VAL 0x00000000 + +/* +// +*/ + +/* +// +*/ + +/* + max 8 SAU regions. + SAU regions are defined in partition.h + */ + +#define SAU_INIT_REGION(n) \ + SAU->RNR = (n & SAU_RNR_REGION_Msk); \ + SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ + SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ + ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U + +/** + \brief Setup a SAU Region + \details Writes the region information contained in SAU_Region to the + registers SAU_RNR, SAU_RBAR, and SAU_RLAR + */ +__STATIC_INLINE void TZ_SAU_Setup (void) +{ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + + #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) + SAU_INIT_REGION(0); + #endif + + #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) + SAU_INIT_REGION(1); + #endif + + #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) + SAU_INIT_REGION(2); + #endif + + #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) + SAU_INIT_REGION(3); + #endif + + #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) + SAU_INIT_REGION(4); + #endif + + #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) + SAU_INIT_REGION(5); + #endif + + #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) + SAU_INIT_REGION(6); + #endif + + #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) + SAU_INIT_REGION(7); + #endif + + /* repeat this for all possible SAU regions */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + + + #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) + SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | + ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; + #endif + + #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) + SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | + ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); + + SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | + SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) | + ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | + ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | + ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | + ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); + #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ + + #if defined (__FPU_USED) && (__FPU_USED == 1U) && \ + defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) + + SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | + ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); + + FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | + ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | + ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | + ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); + #endif + + #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) + NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; + #endif + + #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) + NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; + #endif + + #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) + NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; + #endif + +} + +#endif /* PARTITION_STM32WBA54XX_H */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/Templates/partition_stm32wba55xx.h b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/Templates/partition_stm32wba55xx.h new file mode 100644 index 0000000000..07ac11b168 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/Templates/partition_stm32wba55xx.h @@ -0,0 +1,593 @@ +/** + ****************************************************************************** + * @file partition_stm32wba55xx.h + * @author MCD Application Team + * @brief CMSIS STM32WBA55xx Device Initial Setup for Secure / Non-Secure Zones + * for ARMCM33 based on CMSIS CORE V5.4.0 partition_ARMCM33.h Template. + * + * This file contains: + * - Initialize Security Attribution Unit (SAU) CTRL register + * - Setup behavior of Sleep and Exception Handling + * - Setup behavior of Floating Point Unit + * - Setup Interrupt Target + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * Copyright (c) 2022 STMicroelectronics. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ****************************************************************************** + */ + +#ifndef PARTITION_STM32WBA55XX_H +#define PARTITION_STM32WBA55XX_H + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +*/ + +/* +// Initialize Security Attribution Unit (SAU) CTRL register +*/ +#define SAU_INIT_CTRL 1 + +/* +// Enable SAU +// Value for SAU->CTRL register bit ENABLE +*/ +#define SAU_INIT_CTRL_ENABLE 1 + +/* +// When SAU is disabled +// <0=> All Memory is Secure +// <1=> All Memory is Non-Secure +// Value for SAU->CTRL register bit ALLNS +// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. +*/ +#define SAU_INIT_CTRL_ALLNS 0 + +/* +// +*/ + +/* +// Initialize Security Attribution Unit (SAU) Address Regions +// SAU configuration specifies regions to be one of: +// - Secure and Non-Secure Callable +// - Non-Secure +// Note: All memory regions not configured by SAU are Secure +*/ +#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ + +/* +// Initialize SAU Region 0 +// Setup SAU Region 0 memory attributes +*/ +#define SAU_INIT_REGION0 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START0 0x08080000 /* start address of SAU region 0 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END0 0x080FFFFF /* end address of SAU region 0 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC0 0 +/* +// +*/ + +/* +// Initialize SAU Region 1 +// Setup SAU Region 1 memory attributes +*/ +#define SAU_INIT_REGION1 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START1 0x0BF88000 /* start address of SAU region 1 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END1 0x0BF97FFF /* end address of SAU region 1 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC1 0 +/* +// +*/ + +/* +// Initialize SAU Region 2 +// Setup SAU Region 2 memory attributes +*/ +#define SAU_INIT_REGION2 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START2 0x0C07E000 /* start address of SAU region 2 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END2 0x0C07FFFF /* end address of SAU region 2 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC2 1 +/* +// +*/ + +/* +// Initialize SAU Region 3 +// Setup SAU Region 3 memory attributes +*/ +#define SAU_INIT_REGION3 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START3 0x20010000 /* start address of SAU region 3 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END3 0x2001FFFF /* end address of SAU region 3 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC3 0 +/* +// +*/ + +/* +// Initialize SAU Region 4 +// Setup SAU Region 4 memory attributes +*/ +#define SAU_INIT_REGION4 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START4 0x40000000 /* start address of SAU region 4 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END4 0x4FFFFFFF /* end address of SAU region 4 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC4 0 +/* +// +*/ + +/* +// Initialize SAU Region 5 +// Setup SAU Region 5 memory attributes +*/ +#define SAU_INIT_REGION5 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START5 0x00000000 /* start address of SAU region 5 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END5 0x00000000 /* end address of SAU region 5 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC5 0 +/* +// +*/ + +/* +// Initialize SAU Region 6 +// Setup SAU Region 6 memory attributes +*/ +#define SAU_INIT_REGION6 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START6 0x00000000 /* start address of SAU region 6 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END6 0x00000000 /* end address of SAU region 6 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC6 0 +/* +// +*/ + +/* +// Initialize SAU Region 7 +// Setup SAU Region 7 memory attributes +*/ +#define SAU_INIT_REGION7 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START7 0x00000000 /* start address of SAU region 7 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END7 0x00000000 /* end address of SAU region 7 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC7 0 +/* +// +*/ + +/* +// +*/ + +/* +// Setup behaviour of Sleep and Exception Handling +*/ +#define SCB_CSR_AIRCR_INIT 0 + +/* +// Deep Sleep can be enabled by +// <0=>Secure and Non-Secure state +// <1=>Secure state only +// Value for SCB->CSR register bit DEEPSLEEPS +*/ +#define SCB_CSR_DEEPSLEEPS_VAL 0 + +/* +// System reset request accessible from +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for SCB->AIRCR register bit SYSRESETREQS +*/ +#define SCB_AIRCR_SYSRESETREQS_VAL 0 + +/* +// Priority of Non-Secure exceptions is +// <0=> Not altered +// <1=> Lowered to 0x04-0x07 +// Value for SCB->AIRCR register bit PRIS +*/ +#define SCB_AIRCR_PRIS_VAL 0 + +/* +// BusFault, HardFault, and NMI target +// <0=> Secure state +// <1=> Non-Secure state +// Value for SCB->AIRCR register bit BFHFNMINS +*/ +#define SCB_AIRCR_BFHFNMINS_VAL 0 + +/* +// +*/ + +/* +// Setup behaviour of Floating Point Unit +*/ +#define TZ_FPU_NS_USAGE 1 + +/* +// Floating Point Unit usage +// <0=> Secure state only +// <3=> Secure and Non-Secure state +// Value for SCB->NSACR register bits CP10, CP11 +*/ +#define SCB_NSACR_CP10_11_VAL 3 + +/* +// Treat floating-point registers as Secure +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit TS +*/ +#define FPU_FPCCR_TS_VAL 0 + +/* +// Clear on return (CLRONRET) accessibility +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for FPU->FPCCR register bit CLRONRETS +*/ +#define FPU_FPCCR_CLRONRETS_VAL 0 + +/* +// Clear floating-point caller saved registers on exception return +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit CLRONRET +*/ +#define FPU_FPCCR_CLRONRET_VAL 1 + +/* +// +*/ + +/* +// Setup Interrupt Target +*/ + +/* +// Initialize ITNS 0 (Interrupts 0..31) +*/ +#define NVIC_INIT_ITNS0 1 + +/* +// Interrupts 0..31 +// WWDG_IRQn <0=> Secure state <1=> Non-Secure state +// PVD_IRQn <0=> Secure state <1=> Non-Secure state +// RTC_IRQn <0=> Secure state <1=> Non-Secure state +// RTC_S_IRQn <0=> Secure state <1=> Non-Secure state +// TAMP_IRQn <0=> Secure state <1=> Non-Secure state +// RAMCFG_IRQn <0=> Secure state <1=> Non-Secure state +// FLASH_IRQn <0=> Secure state <1=> Non-Secure state +// FLASH_S_IRQn <0=> Secure state <1=> Non-Secure state +// GTZC_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_S_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI0_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI1_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI2_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI3_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI4_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI5_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI6_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI7_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI8_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI9_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI10_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI11_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI12_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI13_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI14_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI15_IRQn <0=> Secure state <1=> Non-Secure state +// IWDG_IRQn <0=> Secure state <1=> Non-Secure state +// SAES_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA_Channel0_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA_Channel1_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA_Channel2_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS0_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 1 (Interrupts 32..63) +*/ +#define NVIC_INIT_ITNS1 1 + +/* +// Interrupts 32..63 +// GPDMA_Channel3_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA_Channel4_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA_Channel5_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA_Channel6_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA_Channel7_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_UP_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_CC_IRQn <0=> Secure state <1=> Non-Secure state +// TIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM3_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_ER_IRQn <0=> Secure state <1=> Non-Secure state +// SPI1_IRQn <0=> Secure state <1=> Non-Secure state +// USART1_IRQn <0=> Secure state <1=> Non-Secure state +// USART2_IRQn <0=> Secure state <1=> Non-Secure state +// LPUART1_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM1_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM16_IRQn <0=> Secure state <1=> Non-Secure state +// TIM17_IRQn <0=> Secure state <1=> Non-Secure state +// COMP_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_ER_IRQn <0=> Secure state <1=> Non-Secure state +// SAI1_IRQn <0=> Secure state <1=> Non-Secure state +// TSC_IRQn <0=> Secure state <1=> Non-Secure state +// AES_IRQn <0=> Secure state <1=> Non-Secure state +// RNG_IRQn <0=> Secure state <1=> Non-Secure state +// FPU_IRQn <0=> Secure state <1=> Non-Secure state +// HASH_IRQn <0=> Secure state <1=> Non-Secure state +// PKA_IRQn <0=> Secure state <1=> Non-Secure state +// SPI3_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS1_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 2 (Interrupts 64..95) +*/ +#define NVIC_INIT_ITNS2 1 + +/* +// Interrupts 64..95 +// ICACHE_IRQn <0=> Secure state <1=> Non-Secure state +// ADC4_IRQn <0=> Secure state <1=> Non-Secure state +// RADIO_IRQn <0=> Secure state <1=> Non-Secure state +// WKUP_IRQn <0=> Secure state <1=> Non-Secure state +// HSEM_IRQn <0=> Secure state <1=> Non-Secure state +// HSEM_S_IRQn <0=> Secure state <1=> Non-Secure state +// WKUP_S_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_AUDIOSYNC_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS2_VAL 0x00000000 + +/* +// +*/ + +/* +// +*/ + +/* + max 8 SAU regions. + SAU regions are defined in partition.h + */ + +#define SAU_INIT_REGION(n) \ + SAU->RNR = (n & SAU_RNR_REGION_Msk); \ + SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ + SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ + ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U + +/** + \brief Setup a SAU Region + \details Writes the region information contained in SAU_Region to the + registers SAU_RNR, SAU_RBAR, and SAU_RLAR + */ +__STATIC_INLINE void TZ_SAU_Setup (void) +{ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + + #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) + SAU_INIT_REGION(0); + #endif + + #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) + SAU_INIT_REGION(1); + #endif + + #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) + SAU_INIT_REGION(2); + #endif + + #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) + SAU_INIT_REGION(3); + #endif + + #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) + SAU_INIT_REGION(4); + #endif + + #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) + SAU_INIT_REGION(5); + #endif + + #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) + SAU_INIT_REGION(6); + #endif + + #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) + SAU_INIT_REGION(7); + #endif + + /* repeat this for all possible SAU regions */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + + + #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) + SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | + ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; + #endif + + #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) + SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | + ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); + + SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | + SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) | + ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | + ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | + ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | + ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); + #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ + + #if defined (__FPU_USED) && (__FPU_USED == 1U) && \ + defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) + + SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | + ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); + + FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | + ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | + ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | + ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); + #endif + + #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) + NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; + #endif + + #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) + NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; + #endif + + #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) + NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; + #endif + +} + +#endif /* PARTITION_STM32WBA55XX_H */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/partition_stm32wbaxx.h b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/partition_stm32wbaxx.h new file mode 100644 index 0000000000..cd6c267c5b --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/partition_stm32wbaxx.h @@ -0,0 +1,70 @@ +/** + ****************************************************************************** + * @file partition_stm32wbaxx.h + * @author MCD Application Team + * @brief CMSIS STM32WBAxx Device Initial Setup for Secure / Non-Secure Zones + * based on CMSIS CORE V5.4.0 partition_ARMCM33.h Template. + * + * The file is included in system_stm32wbaxx_s.c in secure application. + * It includes the configuration section that allows to select the + * STM32WBAxx device partitioning file for system core secure attributes + * and interrupt secure and non-secure assignment. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32wbaxx + * @{ + */ + +#ifndef PARTITION_STM32WBAXX_H +#define PARTITION_STM32WBAXX_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Secure_configuration_section + * @{ + */ + +#if defined(STM32WBA52xx) + #include "partition_stm32wba52xx.h" +#elif defined(STM32WBA54xx) + #include "partition_stm32wba54xx.h" +#elif defined(STM32WBA55xx) + #include "partition_stm32wba55xx.h" +#else + #error "Please select first the target STM32WBAxx device used in your application (in stm32wbaxx.h file)" +#endif + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* PARTITION_STM32WBAXX_H */ +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba50xx.h b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba50xx.h new file mode 100644 index 0000000000..eae81c6a0d --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba50xx.h @@ -0,0 +1,10396 @@ +/** + ****************************************************************************** + * @file stm32wba50xx.h + * @author MCD Application Team + * @brief CMSIS STM32WBA50xx Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral's registers hardware + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef STM32WBA50xx_H +#define STM32WBA50xx_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup ST + * @{ + */ + +/** @addtogroup STM32WBA50xx + * @{ + */ + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ +typedef enum +{ +/* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ======================================= */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation + and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory + related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SecureFault_IRQn = -9, /*!< -9 Secure Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + +/* =========================================== STM32WBA50xx Specific Interrupt Numbers ====================================== */ + WWDG_IRQn = 0, /*!< Window WatchDog interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + RTC_IRQn = 2, /*!< RTC non-secure interrupt */ + TAMP_IRQn = 4, /*!< Tamper global interrupt */ + RAMCFG_IRQn = 5, /*!< RAMCFG global interrupt */ + FLASH_IRQn = 6, /*!< FLASH non-secure global interrupt */ + RCC_IRQn = 9, /*!< RCC non secure global interrupt */ + EXTI0_IRQn = 11, /*!< EXTI Line0 interrupt */ + EXTI1_IRQn = 12, /*!< EXTI Line1 interrupt */ + EXTI2_IRQn = 13, /*!< EXTI Line2 interrupt */ + EXTI3_IRQn = 14, /*!< EXTI Line3 interrupt */ + EXTI4_IRQn = 15, /*!< EXTI Line4 interrupt */ + EXTI5_IRQn = 16, /*!< EXTI Line5 interrupt */ + EXTI6_IRQn = 17, /*!< EXTI Line6 interrupt */ + EXTI7_IRQn = 18, /*!< EXTI Line7 interrupt */ + EXTI8_IRQn = 19, /*!< EXTI Line8 interrupt */ + EXTI9_IRQn = 20, /*!< EXTI Line9 interrupt */ + EXTI10_IRQn = 21, /*!< EXTI Line10 interrupt */ + EXTI11_IRQn = 22, /*!< EXTI Line11 interrupt */ + EXTI12_IRQn = 23, /*!< EXTI Line12 interrupt */ + EXTI13_IRQn = 24, /*!< EXTI Line13 interrupt */ + EXTI14_IRQn = 25, /*!< EXTI Line14 interrupt */ + EXTI15_IRQn = 26, /*!< EXTI Line15 interrupt */ + IWDG_IRQn = 27, /*!< IWDG global interrupt */ + GPDMA1_Channel0_IRQn = 29, /*!< GPDMA1 Channel 0 global interrupt */ + GPDMA1_Channel1_IRQn = 30, /*!< GPDMA1 Channel 1 global interrupt */ + GPDMA1_Channel2_IRQn = 31, /*!< GPDMA1 Channel 2 global interrupt */ + GPDMA1_Channel3_IRQn = 32, /*!< GPDMA1 Channel 3 global interrupt */ + GPDMA1_Channel4_IRQn = 33, /*!< GPDMA1 Channel 4 global interrupt */ + GPDMA1_Channel5_IRQn = 34, /*!< GPDMA1 Channel 5 global interrupt */ + GPDMA1_Channel6_IRQn = 35, /*!< GPDMA1 Channel 6 global interrupt */ + GPDMA1_Channel7_IRQn = 36, /*!< GPDMA1 Channel 7 global interrupt */ + TIM1_BRK_IRQn = 37, /*!< TIM1 Break interrupt */ + TIM1_UP_IRQn = 38, /*!< TIM1 Update interrupt */ + TIM1_TRG_COM_IRQn = 39, /*!< TIM1 Trigger and Commutation interrupt */ + TIM1_CC_IRQn = 40, /*!< TIM1 Capture Compare interrupt */ + TIM2_IRQn = 41, /*!< TIM2 global interrupt */ + USART1_IRQn = 46, /*!< USART1 global interrupt */ + LPUART1_IRQn = 48, /*!< LPUART1 global interrupt */ + LPTIM1_IRQn = 49, /*!< LPTIM1 global interrupt */ + TIM16_IRQn = 51, /*!< TIM16 global interrupt */ + I2C3_EV_IRQn = 54, /*!< I2C3 Event interrupt */ + I2C3_ER_IRQn = 55, /*!< I2C3 Error interrupt */ + TSC_IRQn = 57, /*!< Touch Sense Controller global interrupt */ + AES_IRQn = 58, /*!< AES global interrupt */ + RNG_IRQn = 59, /*!< RNG global interrupt */ + FPU_IRQn = 60, /*!< FPU global interrupt */ + HASH_IRQn = 61, /*!< HASH global interrupt */ + PKA_IRQn = 62, /*!< PKA global interrupt */ + SPI3_IRQn = 63, /*!< SPI3 global interrupt */ + ICACHE_IRQn = 64, /*!< Instruction cache global interrupt */ + ADC4_IRQn = 65, /*!< ADC4 global interrupt */ + RADIO_IRQn = 66, /*!< 2.4GHz RADIO global interrupt */ + WKUP_IRQn = 67, /*!< PWR global WKUP pin interrupt */ + HSEM_IRQn = 68, /*!< HSEM non-secure global interrupt */ +} IRQn_Type; + + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ +/* ------- Start of section using anonymous unions and disabling warnings ------- */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/* -------- Configuration of the STM32WBAxx System On Chip ------ */ + +/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */ +#define __CM33_REV 0x0000U /* Core revision r0p1 */ +#define __SAUREGION_PRESENT 1U /* SAU regions present */ +#define __MPU_PRESENT 1U /* MPU present */ +#define __VTOR_PRESENT 1U /* VTOR present */ +#define __NVIC_PRIO_BITS 4U /* Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /* FPU present */ +#define __DSP_PRESENT 1U /* DSP extension present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include /*!< ARM Cortex-M33 processor and core peripherals */ +#include "system_stm32wbaxx.h" /*!< system_stm32wbaxx System */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ +/** @addtogroup STM32WBAxx_peripherals + * @{ + */ + +/** + * @brief Analog to Digital Converter (ADC) + */ +typedef struct +{ + __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR; /*!< ADC sampling time register, Address offset: 0x14 */ + uint32_t RESERVED0[2]; /*!< Reserved, Address offset: 0x18-0x1C */ + __IO uint32_t AWD1TR; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ + __IO uint32_t AWD2TR; /*!< ADC watchdog threshold register, Address offset: 0x24 */ + __IO uint32_t CHSELR; /*!< ADC channel select register, Address offset: 0x28 */ + __IO uint32_t AWD3TR; /*!< ADC watchdog threshold register, Address offset: 0x02C */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x30-0x3C */ + __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ + __IO uint32_t PWRR; /*!< ADC power register, Address offset: 0x44 */ + uint32_t RESERVED2[22];/*!< Reserved, Address offset: 0x48-0x9C */ + __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 configuration register, Address offset: 0xA4 */ + uint32_t RESERVED3[7]; /*!< Reserved, Address offset: 0xA8-0xC0 */ + __IO uint32_t CALFACT; /*!< ADC Calibration factor register, Address offset: 0xC4 */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: 0x308 */ +} ADC_Common_TypeDef; + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED0; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief AES hardware accelerator + */ +typedef struct +{ + __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */ + __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */ + __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */ + __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */ + __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */ + __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */ + __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */ + __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */ + __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */ + __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */ + __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */ + __IO uint32_t KEYR4; /*!< AES key register 4, Address offset: 0x30 */ + __IO uint32_t KEYR5; /*!< AES key register 5, Address offset: 0x34 */ + __IO uint32_t KEYR6; /*!< AES key register 6, Address offset: 0x38 */ + __IO uint32_t KEYR7; /*!< AES key register 7, Address offset: 0x3C */ + __IO uint32_t SUSP0R; /*!< AES Suspend register 0, Address offset: 0x40 */ + __IO uint32_t SUSP1R; /*!< AES Suspend register 1, Address offset: 0x44 */ + __IO uint32_t SUSP2R; /*!< AES Suspend register 2, Address offset: 0x48 */ + __IO uint32_t SUSP3R; /*!< AES Suspend register 3, Address offset: 0x4C */ + __IO uint32_t SUSP4R; /*!< AES Suspend register 4, Address offset: 0x50 */ + __IO uint32_t SUSP5R; /*!< AES Suspend register 5, Address offset: 0x54 */ + __IO uint32_t SUSP6R; /*!< AES Suspend register 6, Address offset: 0x58 */ + __IO uint32_t SUSP7R; /*!< AES Suspend register 7, Address offset: 0x5C */ + uint32_t RESERVED1[168];/*!< Reserved, Address offset: 0x60 -- 0x2FC */ + __IO uint32_t IER; /*!< AES Interrupt Enable Register, Address offset: 0x300 */ + __IO uint32_t ISR; /*!< AES Interrupt Status Register, Address offset: 0x304 */ + __IO uint32_t ICR; /*!< AES Interrupt Clear Register, Address offset: 0x308 */ +} AES_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t SCR; /*!< Debug MCU status and configuration register, Address offset: 0x04 */ + __IO uint32_t APB1LFZR; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ + __IO uint32_t APB1HFZR; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ + __IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ + uint32_t RESERVED1[4];/*!< Reserved, 0x14 - 0x20 */ + __IO uint32_t APB7FZR; /*!< Debug MCU APB7 freeze register, Address offset: 0x24 */ + __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x28 */ +} DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ +typedef struct +{ + uint32_t RESERVED1[3]; /*!< Reserved, Address offset: 0x00 - 0x8 */ + __IO uint32_t MISR; /*!< DMA non secure masked interrupt status register, Address offset: 0x0C */ + uint32_t RESERVED2[1]; /*!< Reserved, Address offset: 0x10 */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */ + uint32_t RESERVED1[2]; /*!< Reserved 1, Address offset: 0x54 -- 0x58 */ + __IO uint32_t CFCR; /*!< DMA channel x flag clear register, Address offset: 0x5C + (x * 0x80) */ + __IO uint32_t CSR; /*!< DMA channel x flag status register, Address offset: 0x60 + (x * 0x80) */ + __IO uint32_t CCR; /*!< DMA channel x control register, Address offset: 0x64 + (x * 0x80) */ + uint32_t RESERVED2[10]; /*!< Reserved 2, Address offset: 0x68 -- 0x8C */ + __IO uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: 0x90 + (x * 0x80) */ + __IO uint32_t CTR2; /*!< DMA channel x transfer register 2, Address offset: 0x94 + (x * 0x80) */ + __IO uint32_t CBR1; /*!< DMA channel x block register 1, Address offset: 0x98 + (x * 0x80) */ + __IO uint32_t CSAR; /*!< DMA channel x source address register, Address offset: 0x9C + (x * 0x80) */ + __IO uint32_t CDAR; /*!< DMA channel x destination address register, Address offset: 0xA0 + (x * 0x80) */ + uint32_t RESERVED3[10]; /*!< Reserved 3, Address offset: 0xA4 -- 0xC8 */ + __IO uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: 0xCC + (x * 0x80) */ +} DMA_Channel_TypeDef; + +/** + * @brief Asynch Interrupt/Event Controller (EXTI) + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */ + uint32_t RESERVED1[19]; /*!< Reserved 1, 0x14 -- 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXIT External Interrupt Configuration Register, 0x60 -- 0x6C */ + uint32_t RESERVED2[4]; /*!< Reserved 2, 0x70 -- 0x7C */ + __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + uint32_t RESERVED0; /*!< RESERVED1, Address offset: 0x04 */ + __IO uint32_t NSKEYR; /*!< FLASH non-secure key register, Address offset: 0x08 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x0C */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x10 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x14 */ + __IO uint32_t PDKEYR; /*!< FLASH Bank power-down key register, Address offset: 0x18 */ + uint32_t RESERVED3; /*!< Reserved3, Address offset: 0x1C */ + __IO uint32_t NSSR; /*!< FLASH non-secure status register, Address offset: 0x20 */ + uint32_t RESERVED4; /*!< Reserved4, Address offset: 0x24 */ + __IO uint32_t NSCR1; /*!< FLASH non-secure control register, Address offset: 0x28 */ + uint32_t RESERVED5; /*!< Reserved5, Address offset: 0x2C */ + __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x30 */ + __IO uint32_t OPSR; /*!< FLASH OPSR register, Address offset: 0x34 */ + __IO uint32_t NSCR2; /*!< FLASH non-secure control register, Address offset: 0x38 */ + uint32_t RESERVED6; /*!< Reserved6, Address offset: 0x3C */ + __IO uint32_t OPTR; /*!< FLASH option control register, Address offset: 0x40 */ + __IO uint32_t NSBOOTADD0R; /*!< FLASH non-secure boot address 0 register, Address offset: 0x44 */ + __IO uint32_t NSBOOTADD1R; /*!< FLASH non-secure boot address 1 register, Address offset: 0x48 */ + uint32_t RESERVED7[3]; /*!< Reserved7, Address offset: 0x4C-0x54 */ + __IO uint32_t WRPAR; /*!< FLASH WRP area A address register, Address offset: 0x58 */ + __IO uint32_t WRPBR; /*!< FLASH WRP area B address register, Address offset: 0x5C */ + uint32_t RESERVED8[4]; /*!< Reserved3, Address offset: 0x60-0x6C */ + __IO uint32_t OEM1KEYR1; /*!< FLASH OEM1 key register 1, Address offset: 0x70 */ + __IO uint32_t OEM1KEYR2; /*!< FLASH OEM1 key register 2, Address offset: 0x74 */ + __IO uint32_t OEM2KEYR1; /*!< FLASH OEM2 key register 1, Address offset: 0x78 */ + __IO uint32_t OEM2KEYR2; /*!< FLASH OEM2 key register 2, Address offset: 0x7C */ +} FLASH_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ + uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x2C */ +} GPIO_TypeDef; + +/** + * @brief HASH + */ +typedef struct +{ + __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ + __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ + __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ + __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ + __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ + __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ + uint32_t RESERVED0[52]; /*!< Reserved, Address offset: 0x28-0xF4 */ + __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */ +} HASH_TypeDef; + +/** + * @brief HASH_DIGEST + */ +typedef struct +{ + __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */ +} HASH_DIGEST_TypeDef; + +/** + * @brief HW Semaphore HSEM + */ +typedef struct +{ + __IO uint32_t R[16]; /*!< HSEM 2-step write lock and read back registers, Address offset: 00h-3Ch */ + uint32_t Reserved1[16]; /*!< Reserved Address offset: 40h-7Ch */ + __IO uint32_t RLR[16]; /*!< HSEM 1-step read lock registers, Address offset: 80h-BCh */ + uint32_t Reserved2[16]; /*!< Reserved Address offset: C0h-FCh */ + __IO uint32_t IER; /*!< HSEM interrupt enable register, Address offset: 100h */ + __IO uint32_t ICR; /*!< HSEM interrupt clear register, Address offset: 104h */ + __IO uint32_t ISR; /*!< HSEM interrupt status register, Address offset: 108h */ + __IO uint32_t MISR; /*!< HSEM masked interrupt status register, Address offset: 10Ch */ + uint32_t Reserved3[72]; /*!< Reserved Address offset: 110h-22Ch */ + __IO uint32_t CR; /*!< HSEM Semaphore clear register, Address offset: 230h */ + __IO uint32_t KEYR; /*!< HSEM Semaphore clear key register, Address offset: 234h */ +} HSEM_TypeDef; + +typedef struct +{ + __IO uint32_t IER; /*!< HSEM interrupt enable register, Address offset: 0h */ + __IO uint32_t ICR; /*!< HSEM interrupt clear register, Address offset: 4h */ + __IO uint32_t ISR; /*!< HSEM interrupt status register, Address offset: 8h */ + __IO uint32_t MISR; /*!< HSEM masked interrupt status register, Address offset: Ch */ +} HSEM_Common_TypeDef; + +/** + * @brief Instruction Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< ICACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< ICACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< ICACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< ICACHE Flag clear register, Address offset: 0x0C */ + __IO uint32_t HMONR; /*!< ICACHE hit monitor register, Address offset: 0x10 */ + __IO uint32_t MMONR; /*!< ICACHE miss monitor register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t CRR0; /*!< ICACHE region 0 configuration register, Address offset: 0x20 */ + __IO uint32_t CRR1; /*!< ICACHE region 1 configuration register, Address offset: 0x24 */ + __IO uint32_t CRR2; /*!< ICACHE region 2 configuration register, Address offset: 0x28 */ + __IO uint32_t CRR3; /*!< ICACHE region 3 configuration register, Address offset: 0x2C */ +} ICACHE_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ + __IO uint32_t AUTOCR; /*!< I2C Autonomous mode control register, Address offset: 0x2C */ +} I2C_TypeDef; + +/** + * @brief IWDG + */ +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ + __IO uint32_t EWCR; /*!< IWDG Early Wakeup register, Address offset: 0x14 */ +} IWDG_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t DIER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CCR1; /*!< LPTIM Capture/Compare register 1, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ + __IO uint32_t RCR; /*!< LPTIM Repetition register, Address offset: 0x28 */ + __IO uint32_t CCMR1; /*!< LPTIM Capture/Compare mode register, Address offset: 0x2C */ + __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x30 */ + __IO uint32_t CCR2; /*!< LPTIM Capture/Compare register 2, Address offset: 0x34 */ +} LPTIM_TypeDef; + +/** + * @brief PKA + */ +typedef struct +{ + __IO uint32_t CR; /*!< PKA control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< PKA status register, Address offset: 0x04 */ + __IO uint32_t CLRFR; /*!< PKA clear flag register, Address offset: 0x08 */ + uint32_t Reserved[253]; /*!< Reserved memory area Address offset: 0x0C -> 0x03FC */ + __IO uint32_t RAM[1334]; /*!< PKA RAM Address offset: 0x400 -> 0x18D4 */ +} PKA_TypeDef; + +/** + * @brief Power Control + */ +typedef struct +{ + __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */ + __IO uint32_t VOSR; /*!< PWR voltage scaling register, Address offset: 0x0C */ + __IO uint32_t SVMCR; /*!< PWR supply voltage monitoring control register, Address offset: 0x10 */ + __IO uint32_t WUCR1; /*!< PWR wakeup control register 1, Address offset: 0x14 */ + __IO uint32_t WUCR2; /*!< PWR wakeup control register 2, Address offset: 0x18 */ + __IO uint32_t WUCR3; /*!< PWR wakeup control register 3, Address offset: 0x1C */ + __IO uint32_t RESERVED0[2]; /*!< Reserved, Address offset: 0x20 -- 0x24 */ + __IO uint32_t DBPR; /*!< PWR disable backup domain register, Address offset: 0x28 */ + uint32_t RESERVED1[3]; /*!< Reserved, Address offset: 0x2C -- 0x34 */ + __IO uint32_t SR; /*!< PWR status register, Address offset: 0x38 */ + __IO uint32_t SVMSR; /*!< PWR supply voltage monitoring status register, Address offset: 0x3C */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x40 */ + __IO uint32_t WUSR; /*!< PWR wakeup status register, Address offset: 0x44 */ + __IO uint32_t WUSCR; /*!< PWR wakeup status clear register, Address offset: 0x48 */ + __IO uint32_t APCR; /*!< PWR apply pull configuration register, Address offset: 0x4C */ + __IO uint32_t IORETENRA; /*!< PWR Port A IO retention in Standby register, Address offset: 0x50 */ + __IO uint32_t IORETRA; /*!< PWR Port A IO retention status in Standby register, Address offset: 0x54 */ + __IO uint32_t IORETENRB; /*!< PWR Port B IO retention in Standby register, Address offset: 0x58 */ + __IO uint32_t IORETRB; /*!< PWR Port B IO retention status in Standby register, Address offset: 0x5C */ + __IO uint32_t IORETENRC; /*!< PWR Port C IO retention in Standby register, Address offset: 0x60 */ + __IO uint32_t IORETRC; /*!< PWR Port C IO retention status in Standby register, Address offset: 0x64 */ + uint32_t RESERVED3[8]; /*!< Reserved, Address offset: 0x68 -- 0x84 */ + __IO uint32_t IORETENRH; /*!< PWR Port H IO retention in Standby register, Address offset: 0x88 */ + __IO uint32_t IORETRH; /*!< PWR Port H IO retention status in Standby register, Address offset: 0x8C */ + uint32_t RESERVED4[28]; /*!< Reserved, Address offset: 0x90 -- 0xFC */ + __IO uint32_t RADIOSCR; /*!< PWR 2.4 GHZ radio status and control register, Address offset: 0x100 */ +} PWR_TypeDef; + +/** + * @brief SRAMs configuration controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< Control Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< Interrupt enable register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< Interrupt status register, Address offset: 0x08 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x0C */ + __IO uint32_t PEAR; /*!< Parity error address register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< Interrupt clear register, Address offset: 0x14 */ + __IO uint32_t WPR1; /*!< Write protection register 1, Address offset: 0x18 */ + __IO uint32_t WPR2; /*!< Write protection register 2, Address offset: 0x1C */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x20 -- 0x24 */ + __IO uint32_t ERKEYR; /*!< Erase key register, Address offset: 0x28 */ +}RAMCFG_TypeDef; + +/** + * @brief Reset and Clock Control + */ +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register Address offset: 0x000 */ + uint32_t RESERVED0[3]; /*!< Reserved 0x004 -- 0x00C */ + __IO uint32_t ICSCR3; /*!< RCC internal clock sources calibration register 3 Address offset: 0x010 */ + uint32_t RESERVED1[2]; /*!< Reserved 0x014 -- 0x018 */ + __IO uint32_t CFGR1; /*!< RCC clock configuration register 1 Address offset: 0x01C */ + __IO uint32_t CFGR2; /*!< RCC clock configuration register 2 Address offset: 0x020 */ + __IO uint32_t CFGR3; /*!< RCC clock configuration register 3 Address offset: 0x024 */ + __IO uint32_t PLL1CFGR; /*!< PLL1 Configuration Register Address offset: 0x028 */ + uint32_t RESERVED2[2]; /*!< Reserved 0x02C -- 0x030 */ + __IO uint32_t PLL1DIVR; /*!< PLL1 Dividers Configuration Register Address offset: 0x034 */ + __IO uint32_t PLL1FRACR; /*!< PLL1 Fractional Divider Configuration Register Address offset: 0x038 */ + uint32_t RESERVED3[5]; /*!< Reserved 0x03C -- 0x04C */ + __IO uint32_t CIER; /*!< Clock Interrupt Enable Register Address offset: 0x050 */ + __IO uint32_t CIFR; /*!< Clock Interrupt Flag Register Address offset: 0x054 */ + __IO uint32_t CICR; /*!< Clock Interrupt Clear Register Address offset: 0x058 */ + uint32_t RESERVED4; /*!< Reserved Address offset: 0x05C */ + __IO uint32_t AHB1RSTR; /*!< AHB1 Peripherals Reset Register Address offset: 0x060 */ + __IO uint32_t AHB2RSTR; /*!< AHB2 Peripherals Reset Register Address offset: 0x064 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x068 */ + __IO uint32_t AHB4RSTR; /*!< AHB4 Peripherals Reset Register Address offset: 0x06C */ + __IO uint32_t AHB5RSTR; /*!< AHB5 Peripherals Reset Register Address offset: 0x070 */ + __IO uint32_t APB1RSTR1; /*!< APB1 Peripherals Reset Low Register Address offset: 0x074 */ + __IO uint32_t APB1RSTR2; /*!< APB1 Peripherals Reset High Register Address offset: 0x078 */ + __IO uint32_t APB2RSTR; /*!< APB2 Peripherals Reset Register Address offset: 0x07C */ + __IO uint32_t APB7RSTR; /*!< APB7 Peripherals Reset Register Address offset: 0x080 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x084 */ + __IO uint32_t AHB1ENR; /*!< AHB1 Peripherals Clock Enable Register Address offset: 0x088 */ + __IO uint32_t AHB2ENR; /*!< AHB2 Peripherals Clock Enable Register Address offset: 0x08C */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x090 */ + __IO uint32_t AHB4ENR; /*!< AHB4 Peripherals Clock Enable Register Address offset: 0x094 */ + __IO uint32_t AHB5ENR; /*!< AHB5 Peripherals Clock Enable Register Address offset: 0x098 */ + __IO uint32_t APB1ENR1; /*!< APB1 Peripherals Clock Enable Low Register Address offset: 0x09C */ + __IO uint32_t APB1ENR2; /*!< APB1 Peripherals Clock Enable High Register Address offset: 0x0A0 */ + __IO uint32_t APB2ENR; /*!< APB2 Peripherals Clock Enable Register Address offset: 0x0A4 */ + __IO uint32_t APB7ENR; /*!< APB7 Peripherals Clock Enable Register Address offset: 0x0A8 */ + uint32_t RESERVED8; /*!< Reserved Address offset: 0x0AC */ + __IO uint32_t AHB1SMENR; /*!< AHB1 Peripherals Clock Low Power Enable Register Address offset: 0x0B0 */ + __IO uint32_t AHB2SMENR; /*!< AHB2 Peripherals Clock Low Power Enable Register Address offset: 0x0B4 */ + uint32_t RESERVED9; /*!< Reserved Address offset: 0x0B8 */ + __IO uint32_t AHB4SMENR; /*!< AHB4 Peripherals Clock Low Power Enable Register Address offset: 0x0BC */ + __IO uint32_t AHB5SMENR; /*!< AHB5 Peripherals Clock Low Power Enable Register Address offset: 0x0C0 */ + __IO uint32_t APB1SMENR1; /*!< APB1 Peripherals Clock Low Power Enable Low Register Address offset: 0x0C4 */ + __IO uint32_t APB1SMENR2; /*!< APB1 Peripherals Clock Low Power Enable High Register Address offset: 0x0C8 */ + __IO uint32_t APB2SMENR; /*!< APB2 Peripherals Clock Low Power Enable Register Address offset: 0x0CC */ + __IO uint32_t APB7SMENR; /*!< APB7 Peripherals Clock Low Power Enable Register Address offset: 0x0D0 */ + uint32_t RESERVED10[3]; /*!< Reserved 0x0D4 -- 0x0DC */ + __IO uint32_t CCIPR1; /*!< IPs Clocks Configuration Register 1 Address offset: 0x0E0 */ + __IO uint32_t CCIPR2; /*!< IPs Clocks Configuration Register 2 Address offset: 0x0E4 */ + __IO uint32_t CCIPR3; /*!< IPs Clocks Configuration Register 3 Address offset: 0x0E8 */ + uint32_t RESERVED11; /*!< Reserved, Address offset: 0x0EC */ + __IO uint32_t BDCR1; /*!< Backup Domain Control Register 1 Address offset: 0x0F0 */ + __IO uint32_t CSR; /*!< V33 Clock Control & Status Register Address offset: 0x0F4 */ + __IO uint32_t BDCR2; /*!< Backup Domain Control Register 2 Address offset: 0x0F8 */ + uint32_t RESERVED12[5]; /*!< Reserved 0x0FC -- 0x010C */ + __IO uint32_t SECCFGR; /*!< RCC secure configuration register Address offset: 0x110 */ + __IO uint32_t PRIVCFGR; /*!< RCC privilege configuration register Address offset: 0x114 */ + uint32_t RESERVED13[58]; /*!< Reserved 0x118 -- 0x1FC */ + __IO uint32_t CFGR4; /*!< RCC clock configuration register 4 Address offset: 0x200 */ + uint32_t RESERVED15; /*!< Reserved Address offset: 0x204 */ + __IO uint32_t RADIOENR; /*!< RCC RADIO peripheral clock enable register Address offset: 0x208 */ + uint32_t RESERVED16; /*!< Reserved Address offset: 0x20C */ + __IO uint32_t ECSCR1; /*!< RCC external clock sources calibration register 1 Address offset: 0x210 */ +} RCC_TypeDef; + +/** + * @brief RNG + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + uint32_t RESERVED; + __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ +} RNG_TypeDef; + +/* +* @brief RTC Specific device feature definitions +*/ +#define RTC_BKP_NB 32U +#define RTC_BACKUP_NB RTC_BKP_NB + +#define RTC_TAMP_NB 3U + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + uint32_t RESERVED0[2];/*!< Reserved, Address offset: 0x1C-0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x3C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */ + uint32_t RESERVED3[4];/*!< Reserved, Address offset: 0x58 */ + __IO uint32_t ALRABINR; /*!< RTC alarm A binary mode register, Address offset: 0x70 */ + __IO uint32_t ALRBBINR; /*!< RTC alarm B binary mode register, Address offset: 0x74 */ +} RTC_TypeDef; + +/** + * @brief SPI + */ +typedef struct +{ + __IO uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */ + __IO uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */ + __IO uint32_t IER; /*!< SPI Interrupt Enable register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x14 */ + __IO uint32_t IFCR; /*!< SPI Interrupt/Status Flags Clear register, Address offset: 0x18 */ + __IO uint32_t AUTOCR; /*!< SPI Autonomous Mode Control register, Address offset: 0x1C */ + __IO uint32_t TXDR; /*!< SPI Transmit data register, Address offset: 0x20 */ + uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C */ + __IO uint32_t RXDR; /*!< SPI/I2S data register, Address offset: 0x30 */ + uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */ + __IO uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */ + __IO uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */ + __IO uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */ + __IO uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */ +} SPI_TypeDef; + +/** + * @brief System configuration controller + */ +typedef struct +{ + __IO uint32_t SECCFGR; /*!< SYSCFG secure configuration register, Address offset: 0x00 */ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ + __IO uint32_t FPUIMR; /*!< SYSCFG FPU interrupt mask register, Address offset: 0x08 */ + __IO uint32_t CNSLCKR; /*!< SYSCFG CPU non-secure lock register, Address offset: 0x0C */ + __IO uint32_t CSLCKR; /*!< SYSCFG CPU secure lock register, Address offset: 0x10 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x14 */ + __IO uint32_t MESR; /*!< SYSCFG Memory Erase Status register, Address offset: 0x18 */ + __IO uint32_t CCCSR; /*!< SYSCFG Conpensaion Cell Control&Status register, Address offset: 0x1C */ + __IO uint32_t CCVR; /*!< SYSCFG Conpensaion Cell value register, Address offset: 0x20 */ + __IO uint32_t CCCR; /*!< SYSCFG Conpensaion Cell Code register, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x28 */ + __IO uint32_t RSSCMDR; /*!< SYSCFG RSS command mode register, Address offset: 0x2C */ +} SYSCFG_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< TAMP configuration register 3, Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ + __IO uint32_t ATCR1; /*!< TAMP filter control register 1 Address offset: 0x10 */ + __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ + __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ + __IO uint32_t ATCR2; /*!< TAMP filter control register 2, Address offset: 0x1C */ + uint32_t RESERVED0[3];/*!< Reserved, Address offset: 0x20-0x28 */ + __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ + __IO uint32_t COUNT1R; /*!< TAMP monotonic counter 1 register, Address offset: 0x40 */ + uint32_t RESERVED2[47];/*!< Reserved, Address offset: 0x58 -- 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ + __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ + __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ + __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ + __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ + __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ + __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ + __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ + __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ + __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ + __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ + __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ + __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ +} TAMP_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ + __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ + __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + __IO uint32_t OR; /*!< TIM option register, Address offset: 0x68 */ + uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x68-0x3D8 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + +/** + * @brief TSC + */ +typedef struct +{ + __IO uint32_t CR; /*!< TSC Control register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< TSC Interrupt Enable register, Address offset: 0x04 */ + __IO uint32_t ICR; /*!< TSC Interrupt Control register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< TSC Interrupt Status register, Address offset: 0x0C */ + __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x2C */ + __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */ + __IO uint32_t IOGXCR[6]; /*!< TSC I/O group x counter register, Address offset: 0x34-48 */ +} TSC_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ + __IO uint32_t AUTOCR; /*!< USART Autonomous mode control register Address offset: 0x30 */ +} USART_TypeDef; + +/** + * @brief WWDG + */ +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/*@}*/ /* end of group STM32WBA50xx_Peripherals */ + +/* -------- End of section using anonymous unions and disabling warnings -------- */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ +/** @addtogroup STM32WBAxx_Peripheral_peripheralAddr + * @{ + */ + +/* Flash, Peripheral and internal SRAMs base addresses - Non secure */ +#define FLASH_BASE_NS 0x08000000UL /*!< FLASH non-secure base address */ +#define SYSTEM_FLASH_BASE_NS 0x0BF88000UL /*!< System FLASH non-secure base address */ +#define SRAM1_BASE_NS 0x20000000UL /*!< SRAM1 non-secure base address */ +#define SRAM2_BASE_NS 0x20010000UL /*!< SRAM2 non-secure base address */ +#define SRAM6_BASE_NS 0x48028000UL /*!< 2.4 GHz RADIO TXRX SRAM non-secure base address */ +#define SEQSRAM_BASE_NS 0x48021000UL /*!< SRAM Sequence / retention non-secure base address */ +#define PERIPH_BASE_NS 0x40000000UL /*!< Peripheral non-secure base address */ +#define DBGMCU_BASE 0xE0044000UL /*!< Debug MCU registers base address */ + +/*!< Memory sizes */ +/* Internal Flash size */ +#define FLASH_SIZE ((((*((uint16_t *)FLASHSIZE_BASE)) == 0xFFFFU)) ? 0x100000U : \ + ((((*((uint16_t *)FLASHSIZE_BASE)) == 0x0000U)) ? 0x100000U : \ + (((uint32_t)(*((uint16_t *)FLASHSIZE_BASE)) & (0xFFFFU)) << 10U))) + +/* Internal SRAMs size */ +#define SRAM1_SIZE 0x00004000UL /*!< SRAM1 = 16 Kbytes */ +#define SRAM2_SIZE 0x0000C000UL /*!< SRAM2 = 48 Kbytes */ +#define SRAM6_SIZE 0x00004000UL /*!< 2.4 GHz RADIO TXRX SRAM 16 Kbytes */ +#define SEQSRAM_SIZE 0x00000200UL /*!< SRAM Sequence / retention 512 bytes */ + +/*!< OTP, Engineering bytes, Option bytes defines */ +#define FLASH_OTP_BASE (SYSTEM_FLASH_BASE_NS + 0x00008000UL) +#define FLASH_OTP_SIZE 0x00000200U /*!< 512 bytes OTP (one-time programmable) */ + +#define FLASH_ENGY_BASE (SYSTEM_FLASH_BASE_NS + 0x00008500UL) +#define PACKAGE_BASE (FLASH_ENGY_BASE) /*!< Package data register base address */ +#define UID_BASE (FLASH_ENGY_BASE + 0x00000200UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (FLASH_ENGY_BASE + 0x000002A0UL) /*!< Flash size data register base address */ +#define UID64_BASE (FLASH_ENGY_BASE + 0x00000500UL) /*!< 64-bit Unique device Identification */ + +/* Peripheral memory map - Non secure */ +#define APB1PERIPH_BASE_NS PERIPH_BASE_NS +#define APB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00010000UL) +#define AHB1PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00020000UL) +#define AHB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x02020000UL) +#define APB7PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06000000UL) +#define AHB4PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06020000UL) +#define AHB5PERIPH_BASE_NS (PERIPH_BASE_NS + 0x08020000UL) + +/*!< APB1 Non secure peripherals */ +#define TIM2_BASE_NS APB1PERIPH_BASE_NS +#define WWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x2C00UL) +#define IWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x3000UL) + +/*!< APB2 Non secure peripherals */ +#define TIM1_BASE_NS (APB2PERIPH_BASE_NS + 0x2C00UL) +#define USART1_BASE_NS (APB2PERIPH_BASE_NS + 0x3800UL) +#define TIM16_BASE_NS (APB2PERIPH_BASE_NS + 0x4400UL) + +/*!< AHB1 Non secure peripherals */ +#define GPDMA1_BASE_NS AHB1PERIPH_BASE_NS +#define FLASH_R_BASE_NS (AHB1PERIPH_BASE_NS + 0x02000UL) +#define CRC_BASE_NS (AHB1PERIPH_BASE_NS + 0x03000UL) +#define TSC_BASE_NS (AHB1PERIPH_BASE_NS + 0x04000UL) +#define RAMCFG_BASE_NS (AHB1PERIPH_BASE_NS + 0x06000UL) +#define ICACHE_BASE_NS (AHB1PERIPH_BASE_NS + 0x10400UL) + +#define GPDMA1_Channel0_BASE_NS (GPDMA1_BASE_NS + 0x0050UL) +#define GPDMA1_Channel1_BASE_NS (GPDMA1_BASE_NS + 0x00D0UL) +#define GPDMA1_Channel2_BASE_NS (GPDMA1_BASE_NS + 0x0150UL) +#define GPDMA1_Channel3_BASE_NS (GPDMA1_BASE_NS + 0x01D0UL) +#define GPDMA1_Channel4_BASE_NS (GPDMA1_BASE_NS + 0x0250UL) +#define GPDMA1_Channel5_BASE_NS (GPDMA1_BASE_NS + 0x02D0UL) +#define GPDMA1_Channel6_BASE_NS (GPDMA1_BASE_NS + 0x0350UL) +#define GPDMA1_Channel7_BASE_NS (GPDMA1_BASE_NS + 0x03D0UL) + +#define RAMCFG_SRAM1_BASE_NS (RAMCFG_BASE_NS) +#define RAMCFG_SRAM2_BASE_NS (RAMCFG_BASE_NS + 0x0040UL) +#define RAMCFG_SRAM6_BASE_NS (RAMCFG_BASE_NS + 0x0140UL) + +/*!< AHB2 Non secure peripherals */ +#define GPIOA_BASE_NS AHB2PERIPH_BASE_NS +#define GPIOB_BASE_NS (AHB2PERIPH_BASE_NS + 0x00400UL) +#define GPIOC_BASE_NS (AHB2PERIPH_BASE_NS + 0x00800UL) +#define GPIOH_BASE_NS (AHB2PERIPH_BASE_NS + 0x01C00UL) +#define AES_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0000UL) +#define HASH_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0400UL) +#define HASH_DIGEST_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0710UL) +#define RNG_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0800UL) +#define HSEM_BASE_NS (AHB2PERIPH_BASE_NS + 0xA1C00UL) +#define PKA_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2000UL) +#define PKA_RAM_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2400UL) + +/*!< APB7 Non secure peripherals */ +#define SYSCFG_BASE_NS (APB7PERIPH_BASE_NS + 0x0400UL) +#define SPI3_BASE_NS (APB7PERIPH_BASE_NS + 0x2000UL) +#define LPUART1_BASE_NS (APB7PERIPH_BASE_NS + 0x2400UL) +#define I2C3_BASE_NS (APB7PERIPH_BASE_NS + 0x2800UL) +#define LPTIM1_BASE_NS (APB7PERIPH_BASE_NS + 0x4400UL) +#define RTC_BASE_NS (APB7PERIPH_BASE_NS + 0x7800UL) +#define TAMP_BASE_NS (APB7PERIPH_BASE_NS + 0x7C00UL) + +/*!< AHB4 Non secure peripherals */ +#define PWR_BASE_NS (AHB4PERIPH_BASE_NS + 0x0800UL) +#define RCC_BASE_NS (AHB4PERIPH_BASE_NS + 0x0C00UL) +#define ADC4_BASE_NS (AHB4PERIPH_BASE_NS + 0x1000UL) +#define ADC4_COMMON_BASE_NS (AHB4PERIPH_BASE_NS + 0x1308UL) +#define EXTI_BASE_NS (AHB4PERIPH_BASE_NS + 0x2000UL) + +/*!< AHB5 Non secure peripherals */ +#define RADIO_BASE_NS AHB5PERIPH_BASE_NS + + +/** @} */ /* End of group STM32WBAxx_Peripheral_peripheralAddr */ +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ +/** @addtogroup STM32WBAxx_Peripheral_declaration + * @{ + */ +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +#define ADC4_NS ((ADC_TypeDef *) ADC4_BASE_NS) +#define ADC4_COMMON_NS ((ADC_Common_TypeDef *) ADC4_COMMON_BASE_NS) +#define AES_NS ((AES_TypeDef *) AES_BASE_NS) +#define CRC_NS ((CRC_TypeDef *) CRC_BASE_NS) +#define EXTI_NS ((EXTI_TypeDef *) EXTI_BASE_NS) +#define FLASH_NS ((FLASH_TypeDef *) FLASH_R_BASE_NS) +#define GPDMA1_NS ((DMA_TypeDef *) GPDMA1_BASE_NS) +#define GPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_NS) +#define GPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_NS) +#define GPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_NS) +#define GPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_NS) +#define GPDMA1_Channel4_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_NS) +#define GPDMA1_Channel5_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_NS) +#define GPDMA1_Channel6_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_NS) +#define GPDMA1_Channel7_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_NS) +#define GPIOA_NS ((GPIO_TypeDef *) GPIOA_BASE_NS) +#define GPIOB_NS ((GPIO_TypeDef *) GPIOB_BASE_NS) +#define GPIOC_NS ((GPIO_TypeDef *) GPIOC_BASE_NS) +#define GPIOH_NS ((GPIO_TypeDef *) GPIOH_BASE_NS) +#define HASH_NS ((HASH_TypeDef *) HASH_BASE_NS) +#define HASH_DIGEST_NS ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS) +#define HSEM_NS ((HSEM_TypeDef *) HSEM_BASE_NS) +#define HSEM_COMMON_NS ((HSEM_Common_TypeDef *) (HSEM_BASE_NS + 0x100U)) +#define I2C3_NS ((I2C_TypeDef *) I2C3_BASE_NS) +#define ICACHE_NS ((ICACHE_TypeDef *) ICACHE_BASE_NS) +#define IWDG_NS ((IWDG_TypeDef *) IWDG_BASE_NS) +#define LPTIM1_NS ((LPTIM_TypeDef *) LPTIM1_BASE_NS) +#define LPUART1_NS ((USART_TypeDef *) LPUART1_BASE_NS) +#define PKA_NS ((PKA_TypeDef *) PKA_BASE_NS) +#define PWR_NS ((PWR_TypeDef *) PWR_BASE_NS) +#define RAMCFG_SRAM1_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_NS) +#define RAMCFG_SRAM2_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_NS) +#define RAMCFG_SRAM6_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM6_BASE_NS) +#define RCC_NS ((RCC_TypeDef *) RCC_BASE_NS) +#define RNG_NS ((RNG_TypeDef *) RNG_BASE_NS) +#define RTC_NS ((RTC_TypeDef *) RTC_BASE_NS) +#define SPI3_NS ((SPI_TypeDef *) SPI3_BASE_NS) +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_BASE_NS) +#define TAMP_NS ((TAMP_TypeDef *) TAMP_BASE_NS) +#define TIM1_NS ((TIM_TypeDef *) TIM1_BASE_NS) +#define TIM2_NS ((TIM_TypeDef *) TIM2_BASE_NS) +#define TIM16_NS ((TIM_TypeDef *) TIM16_BASE_NS) +#define TSC_NS ((TSC_TypeDef *) TSC_BASE_NS) +#define USART1_NS ((USART_TypeDef *) USART1_BASE_NS) +#define WWDG_NS ((WWDG_TypeDef *) WWDG_BASE_NS) + +/*!< Memory base addresses for Non secure peripherals */ +#define FLASH_BASE FLASH_BASE_NS +#define SRAM1_BASE SRAM1_BASE_NS +#define SRAM2_BASE SRAM2_BASE_NS +#define SRAM6_BASE SRAM6_BASE_NS +#define SEQSRAM_BASE SEQSRAM_BASE_NS + +/*!< Instance aliases and base addresses for Non secure peripherals */ +#define ADC4 ADC4_NS +#define ADC4_BASE ADC4_BASE_NS +#define ADC4_COMMON ADC4_COMMON_NS +#define ADC4_COMMON_BASE ADC4_COMMON_BASE_NS +#define AES AES_NS +#define AES_BASE AES_BASE_NS +#define CRC CRC_NS +#define CRC_BASE CRC_BASE_NS +#define EXTI EXTI_NS +#define EXTI_BASE EXTI_BASE_NS +#define FLASH FLASH_NS +#define FLASH_R_BASE FLASH_R_BASE_NS +#define GPDMA1 GPDMA1_NS +#define GPDMA1_BASE GPDMA1_BASE_NS +#define GPDMA1_Channel0 GPDMA1_Channel0_NS +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_NS +#define GPDMA1_Channel1 GPDMA1_Channel1_NS +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_NS +#define GPDMA1_Channel2 GPDMA1_Channel2_NS +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_NS +#define GPDMA1_Channel3 GPDMA1_Channel3_NS +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_NS +#define GPDMA1_Channel4 GPDMA1_Channel4_NS +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_NS +#define GPDMA1_Channel5 GPDMA1_Channel5_NS +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_NS +#define GPDMA1_Channel6 GPDMA1_Channel6_NS +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_NS +#define GPDMA1_Channel7 GPDMA1_Channel7_NS +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_NS +#define GPIOA GPIOA_NS +#define GPIOA_BASE GPIOA_BASE_NS +#define GPIOB GPIOB_NS +#define GPIOB_BASE GPIOB_BASE_NS +#define GPIOC GPIOC_NS +#define GPIOC_BASE GPIOC_BASE_NS +#define GPIOH GPIOH_NS +#define GPIOH_BASE GPIOH_BASE_NS +#define HASH HASH_NS +#define HASH_BASE HASH_BASE_NS +#define HASH_DIGEST HASH_DIGEST_NS +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_NS +#define HSEM HSEM_NS +#define HSEM_BASE HSEM_BASE_NS +#define HSEM_COMMON HSEM_COMMON_NS +#define I2C3 I2C3_NS +#define I2C3_BASE I2C3_BASE_NS +#define ICACHE ICACHE_NS +#define ICACHE_BASE ICACHE_BASE_NS +#define IWDG IWDG_NS +#define IWDG_BASE IWDG_BASE_NS +#define LPTIM1 LPTIM1_NS +#define LPTIM1_BASE LPTIM1_BASE_NS +#define LPUART1 LPUART1_NS +#define LPUART1_BASE LPUART1_BASE_NS +#define PKA PKA_NS +#define PKA_BASE PKA_BASE_NS +#define PKA_RAM_BASE PKA_RAM_BASE_NS +#define PWR PWR_NS +#define PWR_BASE PWR_BASE_NS +#define RADIO_BASE RADIO_BASE_NS +#define RAMCFG_SRAM1 RAMCFG_SRAM1_NS +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_NS +#define RAMCFG_SRAM2 RAMCFG_SRAM2_NS +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_NS +#define RAMCFG_SRAM6 RAMCFG_SRAM6_NS +#define RAMCFG_SRAM6_BASE RAMCFG_SRAM6_BASE_NS +#define RCC RCC_NS +#define RCC_BASE RCC_BASE_NS +#define RNG RNG_NS +#define RNG_BASE RNG_BASE_NS +#define RTC RTC_NS +#define RTC_BASE RTC_BASE_NS +#define SPI3 SPI3_NS +#define SPI3_BASE SPI3_BASE_NS +#define SYSCFG SYSCFG_NS +#define SYSCFG_BASE SYSCFG_BASE_NS +#define TAMP TAMP_NS +#define TAMP_BASE TAMP_BASE_NS +#define TIM1 TIM1_NS +#define TIM1_BASE TIM1_BASE_NS +#define TIM2 TIM2_NS +#define TIM2_BASE TIM2_BASE_NS +#define TIM16 TIM16_NS +#define TIM16_BASE TIM16_BASE_NS +#define TSC TSC_NS +#define TSC_BASE TSC_BASE_NS +#define USART1 USART1_NS +#define USART1_BASE USART1_BASE_NS +#define WWDG WWDG_NS +#define WWDG_BASE WWDG_BASE_NS + + +/** @addtogroup Exported_constants + * @{ + */ + +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 16000U /*!< LSI Maximum startup time in us : 4 cycles @ 250 Hz = 16 ms */ +/** + * @} + */ + +/** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter (ADC) */ +/* */ +/******************************************************************************/ +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ +#define ADC_ISR_EOCAL_Pos (11U) +#define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */ +#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< ADC end of calibration flag */ +#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC internal voltage regulator ready flag */ + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ +#define ADC_IER_EOCALIE_Pos (11U) +#define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */ +#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< ADC end of calibration interrupt */ +#define ADC_IER_LDORDYIE_Pos (12U) +#define ADC_IER_LDORDYIE_Msk (0x1UL << ADC_IER_LDORDYIE_Pos) /*!< 0x00001000 */ +#define ADC_IER_LDORDYIE ADC_IER_LDORDYIE_Msk /*!< ADC Voltage Regulator Ready interrupt source */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR1 register *****************/ +#define ADC_CFGR1_DMAEN_Pos (0U) +#define ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC_CFGR1_DMACFG_Pos (1U) +#define ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC_CFGR1_RES_Pos (2U) +#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x0000000C */ +#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC Data resolution */ +#define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000004 */ +#define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ + +#define ADC_CFGR1_SCANDIR_Pos (4U) +#define ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000010 */ +#define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */ +#define ADC_CFGR1_ALIGN_Pos (5U) +#define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignment */ + +#define ADC_CFGR1_EXTSEL_Pos (6U) +#define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ +#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR1_EXTEN_Pos (10U) +#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR1_OVRMOD_Pos (12U) +#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR1_CONT_Pos (13U) +#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR1_WAIT_Pos (14U) +#define ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */ +#define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC low power auto wait */ +#define ADC_CFGR1_DISCEN_Pos (16U) +#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ +#define ADC_CFGR1_CHSELRMOD_Pos (21U) +#define ADC_CFGR1_CHSELRMOD_Msk (0x1UL << ADC_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */ +#define ADC_CFGR1_CHSELRMOD ADC_CFGR1_CHSELRMOD_Msk /*!< ADC group regular sequencer mode */ + +#define ADC_CFGR1_AWD1SGL_Pos (22U) +#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR1_AWD1EN_Pos (23U) +#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ + +#define ADC_CFGR1_AWD1CH_Pos (26U) +#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_OVSE_Pos (0U) +#define ADC_CFGR2_OVSE_Msk (0x1UL << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ + +#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TOVS_Pos (9U) +#define ADC_CFGR2_TOVS_Msk (0x1UL << ADC_CFGR2_TOVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ + +#define ADC_CFGR2_LFTRIG_Pos (29U) +#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC low frequency trigger mode */ + +/******************** Bit definition for ADC_SMPR register ******************/ +#define ADC_SMPR_SMP1_Pos (0U) +#define ADC_SMPR_SMP1_Msk (0x7UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000007 */ +#define ADC_SMPR_SMP1 ADC_SMPR_SMP1_Msk /*!< ADC group of channels sampling time 1 */ +#define ADC_SMPR_SMP1_0 (0x1UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000001 */ +#define ADC_SMPR_SMP1_1 (0x2UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000002 */ +#define ADC_SMPR_SMP1_2 (0x4UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR_SMP2_Pos (4U) +#define ADC_SMPR_SMP2_Msk (0x7UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000070 */ +#define ADC_SMPR_SMP2 ADC_SMPR_SMP2_Msk /*!< ADC group of channels sampling time 2 */ +#define ADC_SMPR_SMP2_0 (0x1UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000010 */ +#define ADC_SMPR_SMP2_1 (0x2UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000020 */ +#define ADC_SMPR_SMP2_2 (0x4UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000040 */ + +#define ADC_SMPR_SMPSEL_Pos (8U) +#define ADC_SMPR_SMPSEL_Msk (0x3FFFFUL << ADC_SMPR_SMPSEL_Pos) /*!< 0x03FFFF00 */ +#define ADC_SMPR_SMPSEL ADC_SMPR_SMPSEL_Msk /*!< ADC all channels sampling time selection */ +#define ADC_SMPR_SMPSEL0_Pos (8U) +#define ADC_SMPR_SMPSEL0_Msk (0x1UL << ADC_SMPR_SMPSEL0_Pos) /*!< 0x00000100 */ +#define ADC_SMPR_SMPSEL0 ADC_SMPR_SMPSEL0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR_SMPSEL1_Pos (9U) +#define ADC_SMPR_SMPSEL1_Msk (0x1UL << ADC_SMPR_SMPSEL1_Pos) /*!< 0x00000200 */ +#define ADC_SMPR_SMPSEL1 ADC_SMPR_SMPSEL1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR_SMPSEL2_Pos (10U) +#define ADC_SMPR_SMPSEL2_Msk (0x1UL << ADC_SMPR_SMPSEL2_Pos) /*!< 0x00000400 */ +#define ADC_SMPR_SMPSEL2 ADC_SMPR_SMPSEL2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR_SMPSEL3_Pos (11U) +#define ADC_SMPR_SMPSEL3_Msk (0x1UL << ADC_SMPR_SMPSEL3_Pos) /*!< 0x00000800 */ +#define ADC_SMPR_SMPSEL3 ADC_SMPR_SMPSEL3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR_SMPSEL4_Pos (12U) +#define ADC_SMPR_SMPSEL4_Msk (0x1UL << ADC_SMPR_SMPSEL4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR_SMPSEL4 ADC_SMPR_SMPSEL4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR_SMPSEL5_Pos (13U) +#define ADC_SMPR_SMPSEL5_Msk (0x1UL << ADC_SMPR_SMPSEL5_Pos) /*!< 0x00002000 */ +#define ADC_SMPR_SMPSEL5 ADC_SMPR_SMPSEL5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR_SMPSEL6_Pos (14U) +#define ADC_SMPR_SMPSEL6_Msk (0x1UL << ADC_SMPR_SMPSEL6_Pos) /*!< 0x00004000 */ +#define ADC_SMPR_SMPSEL6 ADC_SMPR_SMPSEL6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR_SMPSEL7_Pos (15U) +#define ADC_SMPR_SMPSEL7_Msk (0x1UL << ADC_SMPR_SMPSEL7_Pos) /*!< 0x00008000 */ +#define ADC_SMPR_SMPSEL7 ADC_SMPR_SMPSEL7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR_SMPSEL8_Pos (16U) +#define ADC_SMPR_SMPSEL8_Msk (0x1UL << ADC_SMPR_SMPSEL8_Pos) /*!< 0x00010000 */ +#define ADC_SMPR_SMPSEL8 ADC_SMPR_SMPSEL8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR_SMPSEL9_Pos (17U) +#define ADC_SMPR_SMPSEL9_Msk (0x1UL << ADC_SMPR_SMPSEL9_Pos) /*!< 0x00020000 */ +#define ADC_SMPR_SMPSEL9 ADC_SMPR_SMPSEL9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR_SMPSEL10_Pos (18U) +#define ADC_SMPR_SMPSEL10_Msk (0x1UL << ADC_SMPR_SMPSEL10_Pos) /*!< 0x00040000 */ +#define ADC_SMPR_SMPSEL10 ADC_SMPR_SMPSEL10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR_SMPSEL11_Pos (19U) +#define ADC_SMPR_SMPSEL11_Msk (0x1UL << ADC_SMPR_SMPSEL11_Pos) /*!< 0x00080000 */ +#define ADC_SMPR_SMPSEL11 ADC_SMPR_SMPSEL11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR_SMPSEL12_Pos (20U) +#define ADC_SMPR_SMPSEL12_Msk (0x1UL << ADC_SMPR_SMPSEL12_Pos) /*!< 0x00100000 */ +#define ADC_SMPR_SMPSEL12 ADC_SMPR_SMPSEL12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR_SMPSEL13_Pos (21U) +#define ADC_SMPR_SMPSEL13_Msk (0x1UL << ADC_SMPR_SMPSEL13_Pos) /*!< 0x00200000 */ +#define ADC_SMPR_SMPSEL13 ADC_SMPR_SMPSEL13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR_SMPSEL14_Pos (22U) +#define ADC_SMPR_SMPSEL14_Msk (0x1UL << ADC_SMPR_SMPSEL14_Pos) /*!< 0x00400000 */ +#define ADC_SMPR_SMPSEL14 ADC_SMPR_SMPSEL14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR_SMPSEL15_Pos (23U) +#define ADC_SMPR_SMPSEL15_Msk (0x1UL << ADC_SMPR_SMPSEL15_Pos) /*!< 0x00800000 */ +#define ADC_SMPR_SMPSEL15 ADC_SMPR_SMPSEL15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR_SMPSEL16_Pos (24U) +#define ADC_SMPR_SMPSEL16_Msk (0x1UL << ADC_SMPR_SMPSEL16_Pos) /*!< 0x01000000 */ +#define ADC_SMPR_SMPSEL16 ADC_SMPR_SMPSEL16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR_SMPSEL17_Pos (25U) +#define ADC_SMPR_SMPSEL17_Msk (0x1UL << ADC_SMPR_SMPSEL17_Pos) /*!< 0x02000000 */ +#define ADC_SMPR_SMPSEL17 ADC_SMPR_SMPSEL17_Msk /*!< ADC channel 17 sampling time selection */ + +/******************** Bit definition for ADC_AWD1TR register *******************/ +#define ADC_AWD1TR_LT1_Pos (0U) +#define ADC_AWD1TR_LT1_Msk (0xFFFUL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_AWD1TR_LT1 ADC_AWD1TR_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ +#define ADC_AWD1TR_LT1_0 (0x001UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000001 */ +#define ADC_AWD1TR_LT1_1 (0x002UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000002 */ +#define ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000004 */ +#define ADC_AWD1TR_LT1_3 (0x008UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000008 */ +#define ADC_AWD1TR_LT1_4 (0x010UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000010 */ +#define ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000020 */ +#define ADC_AWD1TR_LT1_6 (0x040UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000040 */ +#define ADC_AWD1TR_LT1_7 (0x080UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000080 */ +#define ADC_AWD1TR_LT1_8 (0x100UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000100 */ +#define ADC_AWD1TR_LT1_9 (0x200UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000200 */ +#define ADC_AWD1TR_LT1_10 (0x400UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000400 */ +#define ADC_AWD1TR_LT1_11 (0x800UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000800 */ + +#define ADC_AWD1TR_HT1_Pos (16U) +#define ADC_AWD1TR_HT1_Msk (0xFFFUL << ADC_AWD1TR_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD1TR_HT1 ADC_AWD1TR_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ +#define ADC_AWD1TR_HT1_0 (0x001UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00010000 */ +#define ADC_AWD1TR_HT1_1 (0x002UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00020000 */ +#define ADC_AWD1TR_HT1_2 (0x004UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00040000 */ +#define ADC_AWD1TR_HT1_3 (0x008UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00080000 */ +#define ADC_AWD1TR_HT1_4 (0x010UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00100000 */ +#define ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00200000 */ +#define ADC_AWD1TR_HT1_6 (0x040UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00400000 */ +#define ADC_AWD1TR_HT1_7 (0x080UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00800000 */ +#define ADC_AWD1TR_HT1_8 (0x100UL << ADC_AWD1TR_HT1_Pos) /*!< 0x01000000 */ +#define ADC_AWD1TR_HT1_9 (0x200UL << ADC_AWD1TR_HT1_Pos) /*!< 0x02000000 */ +#define ADC_AWD1TR_HT1_10 (0x400UL << ADC_AWD1TR_HT1_Pos) /*!< 0x04000000 */ +#define ADC_AWD1TR_HT1_11 (0x800UL << ADC_AWD1TR_HT1_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_AWDTR2 register *******************/ +#define ADC_AWD2TR_LT2_Pos (0U) +#define ADC_AWD2TR_LT2_Msk (0xFFFUL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000FFF */ +#define ADC_AWD2TR_LT2 ADC_AWD2TR_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ +#define ADC_AWD2TR_LT2_0 (0x001UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000001 */ +#define ADC_AWD2TR_LT2_1 (0x002UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000002 */ +#define ADC_AWD2TR_LT2_2 (0x004UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000004 */ +#define ADC_AWD2TR_LT2_3 (0x008UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000008 */ +#define ADC_AWD2TR_LT2_4 (0x010UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000010 */ +#define ADC_AWD2TR_LT2_5 (0x020UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000020 */ +#define ADC_AWD2TR_LT2_6 (0x040UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000040 */ +#define ADC_AWD2TR_LT2_7 (0x080UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000080 */ +#define ADC_AWD2TR_LT2_8 (0x100UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000100 */ +#define ADC_AWD2TR_LT2_9 (0x200UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000200 */ +#define ADC_AWD2TR_LT2_10 (0x400UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000400 */ +#define ADC_AWD2TR_LT2_11 (0x800UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000800 */ + +#define ADC_AWD2TR_HT2_Pos (16U) +#define ADC_AWD2TR_HT2_Msk (0xFFFUL << ADC_AWD2TR_HT2_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD2TR_HT2 ADC_AWD2TR_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ +#define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ +#define ADC_AWD2TR_HT2_1 (0x002UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00020000 */ +#define ADC_AWD2TR_HT2_2 (0x004UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00040000 */ +#define ADC_AWD2TR_HT2_3 (0x008UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00080000 */ +#define ADC_AWD2TR_HT2_4 (0x010UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00100000 */ +#define ADC_AWD2TR_HT2_5 (0x020UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00200000 */ +#define ADC_AWD2TR_HT2_6 (0x040UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00400000 */ +#define ADC_AWD2TR_HT2_7 (0x080UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00800000 */ +#define ADC_AWD2TR_HT2_8 (0x100UL << ADC_AWD2TR_HT2_Pos) /*!< 0x01000000 */ +#define ADC_AWD2TR_HT2_9 (0x200UL << ADC_AWD2TR_HT2_Pos) /*!< 0x02000000 */ +#define ADC_AWD2TR_HT2_10 (0x400UL << ADC_AWD2TR_HT2_Pos) /*!< 0x04000000 */ +#define ADC_AWD2TR_HT2_11 (0x800UL << ADC_AWD2TR_HT2_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_CHSELR register ****************/ +#define ADC_CHSELR_CHSEL_Pos (0U) +#define ADC_CHSELR_CHSEL_Msk (0x3FFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0003FFFF */ +#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL17_Pos (17U) +#define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL16_Pos (16U) +#define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL15_Pos (15U) +#define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ +#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL14_Pos (14U) +#define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL13_Pos (13U) +#define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL12_Pos (12U) +#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL11_Pos (11U) +#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ +#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL10_Pos (10U) +#define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL9_Pos (9U) +#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL8_Pos (8U) +#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL7_Pos (7U) +#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ +#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL6_Pos (6U) +#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL5_Pos (5U) +#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL4_Pos (4U) +#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL3_Pos (3U) +#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ +#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL2_Pos (2U) +#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL1_Pos (1U) +#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL0_Pos (0U) +#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */ + +#define ADC_CHSELR_SQ_ALL_Pos (0U) +#define ADC_CHSELR_SQ_ALL_Msk (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CHSELR_SQ_ALL ADC_CHSELR_SQ_ALL_Msk /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */ + +#define ADC_CHSELR_SQ8_Pos (28U) +#define ADC_CHSELR_SQ8_Msk (0xFUL << ADC_CHSELR_SQ8_Pos) /*!< 0xF0000000 */ +#define ADC_CHSELR_SQ8 ADC_CHSELR_SQ8_Msk /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ8_0 (0x1UL << ADC_CHSELR_SQ8_Pos) /*!< 0x10000000 */ +#define ADC_CHSELR_SQ8_1 (0x2UL << ADC_CHSELR_SQ8_Pos) /*!< 0x20000000 */ +#define ADC_CHSELR_SQ8_2 (0x4UL << ADC_CHSELR_SQ8_Pos) /*!< 0x40000000 */ +#define ADC_CHSELR_SQ8_3 (0x8UL << ADC_CHSELR_SQ8_Pos) /*!< 0x80000000 */ + +#define ADC_CHSELR_SQ7_Pos (24U) +#define ADC_CHSELR_SQ7_Msk (0xFUL << ADC_CHSELR_SQ7_Pos) /*!< 0x0F000000 */ +#define ADC_CHSELR_SQ7 ADC_CHSELR_SQ7_Msk /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ7_0 (0x1UL << ADC_CHSELR_SQ7_Pos) /*!< 0x01000000 */ +#define ADC_CHSELR_SQ7_1 (0x2UL << ADC_CHSELR_SQ7_Pos) /*!< 0x02000000 */ +#define ADC_CHSELR_SQ7_2 (0x4UL << ADC_CHSELR_SQ7_Pos) /*!< 0x04000000 */ +#define ADC_CHSELR_SQ7_3 (0x8UL << ADC_CHSELR_SQ7_Pos) /*!< 0x08000000 */ + +#define ADC_CHSELR_SQ6_Pos (20U) +#define ADC_CHSELR_SQ6_Msk (0xFUL << ADC_CHSELR_SQ6_Pos) /*!< 0x00F00000 */ +#define ADC_CHSELR_SQ6 ADC_CHSELR_SQ6_Msk /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ6_0 (0x1UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00100000 */ +#define ADC_CHSELR_SQ6_1 (0x2UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00200000 */ +#define ADC_CHSELR_SQ6_2 (0x4UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00400000 */ +#define ADC_CHSELR_SQ6_3 (0x8UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00800000 */ + +#define ADC_CHSELR_SQ5_Pos (16U) +#define ADC_CHSELR_SQ5_Msk (0xFUL << ADC_CHSELR_SQ5_Pos) /*!< 0x000F0000 */ +#define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ5_0 (0x1UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_SQ5_1 (0x2UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_SQ5_2 (0x4UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_SQ5_3 (0x8UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00080000 */ + +#define ADC_CHSELR_SQ4_Pos (12U) +#define ADC_CHSELR_SQ4_Msk (0xFUL << ADC_CHSELR_SQ4_Pos) /*!< 0x0000F000 */ +#define ADC_CHSELR_SQ4 ADC_CHSELR_SQ4_Msk /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ4_0 (0x1UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_SQ4_1 (0x2UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_SQ4_2 (0x4UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_SQ4_3 (0x8UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00008000 */ + +#define ADC_CHSELR_SQ3_Pos (8U) +#define ADC_CHSELR_SQ3_Msk (0xFUL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000F00 */ +#define ADC_CHSELR_SQ3 ADC_CHSELR_SQ3_Msk /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ3_0 (0x1UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_SQ3_1 (0x2UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_SQ3_2 (0x4UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_SQ3_3 (0x8UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000800 */ + +#define ADC_CHSELR_SQ2_Pos (4U) +#define ADC_CHSELR_SQ2_Msk (0xFUL << ADC_CHSELR_SQ2_Pos) /*!< 0x000000F0 */ +#define ADC_CHSELR_SQ2 ADC_CHSELR_SQ2_Msk /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ2_0 (0x1UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_SQ2_1 (0x2UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_SQ2_2 (0x4UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_SQ2_3 (0x8UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000080 */ + +#define ADC_CHSELR_SQ1_Pos (0U) +#define ADC_CHSELR_SQ1_Msk (0xFUL << ADC_CHSELR_SQ1_Pos) /*!< 0x0000000F */ +#define ADC_CHSELR_SQ1 ADC_CHSELR_SQ1_Msk /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ1_0 (0x1UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_SQ1_1 (0x2UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_SQ1_2 (0x4UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_SQ1_3 (0x8UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000008 */ + +/******************** Bit definition for ADC_AWD3TR register *******************/ +#define ADC_AWD3TR_LT3_Pos (0U) +#define ADC_AWD3TR_LT3_Msk (0xFFFUL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000FFF */ +#define ADC_AWD3TR_LT3 ADC_AWD3TR_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ +#define ADC_AWD3TR_LT3_0 (0x001UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000001 */ +#define ADC_AWD3TR_LT3_1 (0x002UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000002 */ +#define ADC_AWD3TR_LT3_2 (0x004UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000004 */ +#define ADC_AWD3TR_LT3_3 (0x008UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000008 */ +#define ADC_AWD3TR_LT3_4 (0x010UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000010 */ +#define ADC_AWD3TR_LT3_5 (0x020UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000020 */ +#define ADC_AWD3TR_LT3_6 (0x040UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000040 */ +#define ADC_AWD3TR_LT3_7 (0x080UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000080 */ +#define ADC_AWD3TR_LT3_8 (0x100UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000100 */ +#define ADC_AWD3TR_LT3_9 (0x200UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000200 */ +#define ADC_AWD3TR_LT3_10 (0x400UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000400 */ +#define ADC_AWD3TR_LT3_11 (0x800UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000800 */ + +#define ADC_AWD3TR_HT3_Pos (16U) +#define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD3TR_HT3 ADC_AWD3TR_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ +#define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */ +#define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */ +#define ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00040000 */ +#define ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00080000 */ +#define ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00100000 */ +#define ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00200000 */ +#define ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00400000 */ +#define ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00800000 */ +#define ADC_AWD3TR_HT3_8 (0x100UL << ADC_AWD3TR_HT3_Pos) /*!< 0x01000000 */ +#define ADC_AWD3TR_HT3_9 (0x200UL << ADC_AWD3TR_HT3_Pos) /*!< 0x02000000 */ +#define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) /*!< 0x04000000 */ +#define ADC_AWD3TR_HT3_11 (0x800UL << ADC_AWD3TR_HT3_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_DATA_Pos (0U) +#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */ + +/******************** Bit definition for ADC_PWRR register ******************/ +#define ADC_PWRR_AUTOFF_Pos (0U) +#define ADC_PWRR_AUTOFF_Msk (0x1UL << ADC_PWRR_AUTOFF_Pos) /*!< 0x00000001 */ +#define ADC_PWRR_AUTOFF ADC_PWRR_AUTOFF_Msk /*!< ADC auto-off mode */ +#define ADC_PWRR_DPD_Pos (1U) +#define ADC_PWRR_DPD_Msk (0x1UL << ADC_PWRR_DPD_Pos) /*!< 0x00000002 */ +#define ADC_PWRR_DPD ADC_PWRR_DPD_Msk /*!< ADC deep power down mode */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0x3FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0003FFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0x3FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0003FFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_Pos (0U) +#define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_0 (0x01UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_1 (0x02UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_2 (0x04UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_3 (0x08UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_4 (0x10UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_5 (0x20UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_6 (0x40UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000040 */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ + + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + + +/******************************************************************************/ +/* */ +/* Advanced Encryption Standard (AES) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for AES_CR register *********************/ +#define AES_CR_EN_Pos (0U) +#define AES_CR_EN_Msk (0x1UL << AES_CR_EN_Pos) /*!< 0x00000001 */ +#define AES_CR_EN AES_CR_EN_Msk /*!< AES Enable */ +#define AES_CR_DATATYPE_Pos (1U) +#define AES_CR_DATATYPE_Msk (0x3UL << AES_CR_DATATYPE_Pos) /*!< 0x00000006 */ +#define AES_CR_DATATYPE AES_CR_DATATYPE_Msk /*!< Data type selection */ +#define AES_CR_DATATYPE_0 (0x1UL << AES_CR_DATATYPE_Pos) /*!< 0x00000002 */ +#define AES_CR_DATATYPE_1 (0x2UL << AES_CR_DATATYPE_Pos) /*!< 0x00000004 */ +#define AES_CR_MODE_Pos (3U) +#define AES_CR_MODE_Msk (0x3UL << AES_CR_MODE_Pos) /*!< 0x00000018 */ +#define AES_CR_MODE AES_CR_MODE_Msk /*!< AES Mode Of Operation */ +#define AES_CR_MODE_0 (0x1UL << AES_CR_MODE_Pos) /*!< 0x00000008 */ +#define AES_CR_MODE_1 (0x2UL << AES_CR_MODE_Pos) /*!< 0x00000010 */ +#define AES_CR_CHMOD_Pos (5U) +#define AES_CR_CHMOD_Msk (0x803UL << AES_CR_CHMOD_Pos) /*!< 0x00010060 */ +#define AES_CR_CHMOD AES_CR_CHMOD_Msk /*!< AES Chaining Mode */ +#define AES_CR_CHMOD_0 (0x001UL << AES_CR_CHMOD_Pos) /*!< 0x00000020 */ +#define AES_CR_CHMOD_1 (0x002UL << AES_CR_CHMOD_Pos) /*!< 0x00000040 */ +#define AES_CR_CHMOD_2 (0x800UL << AES_CR_CHMOD_Pos) /*!< 0x00010000 */ +#define AES_CR_DMAINEN_Pos (11U) +#define AES_CR_DMAINEN_Msk (0x1UL << AES_CR_DMAINEN_Pos) /*!< 0x00000800 */ +#define AES_CR_DMAINEN AES_CR_DMAINEN_Msk /*!< Enable data input phase DMA management */ +#define AES_CR_DMAOUTEN_Pos (12U) +#define AES_CR_DMAOUTEN_Msk (0x1UL << AES_CR_DMAOUTEN_Pos) /*!< 0x00001000 */ +#define AES_CR_DMAOUTEN AES_CR_DMAOUTEN_Msk /*!< Enable data output phase DMA management */ +#define AES_CR_GCMPH_Pos (13U) +#define AES_CR_GCMPH_Msk (0x3UL << AES_CR_GCMPH_Pos) /*!< 0x00006000 */ +#define AES_CR_GCMPH AES_CR_GCMPH_Msk /*!< GCM Phase */ +#define AES_CR_GCMPH_0 (0x1UL << AES_CR_GCMPH_Pos) /*!< 0x00002000 */ +#define AES_CR_GCMPH_1 (0x2UL << AES_CR_GCMPH_Pos) /*!< 0x00004000 */ +#define AES_CR_KEYSIZE_Pos (18U) +#define AES_CR_KEYSIZE_Msk (0x1UL << AES_CR_KEYSIZE_Pos) /*!< 0x00040000 */ +#define AES_CR_KEYSIZE AES_CR_KEYSIZE_Msk /*!< Key size selection */ +#define AES_CR_NPBLB_Pos (20U) +#define AES_CR_NPBLB_Msk (0xFUL << AES_CR_NPBLB_Pos) /*!< 0x00F00000 */ +#define AES_CR_NPBLB AES_CR_NPBLB_Msk /*!< Number of padding bytes in payload last block */ +#define AES_CR_NPBLB_0 (0x1UL << AES_CR_NPBLB_Pos) /*!< 0x00100000 */ +#define AES_CR_NPBLB_1 (0x2UL << AES_CR_NPBLB_Pos) /*!< 0x00200000 */ +#define AES_CR_NPBLB_2 (0x4UL << AES_CR_NPBLB_Pos) /*!< 0x00400000 */ +#define AES_CR_NPBLB_3 (0x8UL << AES_CR_NPBLB_Pos) /*!< 0x00800000 */ +#define AES_CR_KMOD_Pos (24U) +#define AES_CR_KMOD_Msk (0x3UL << AES_CR_KMOD_Pos) /*!< 0x03000000 */ +#define AES_CR_KMOD AES_CR_KMOD_Msk /*!< Key mode selection */ +#define AES_CR_KMOD_0 (0x1UL << AES_CR_KMOD_Pos) /*!< 0x01000000 */ +#define AES_CR_KMOD_1 (0x2UL << AES_CR_KMOD_Pos) /*!< 0x02000000 */ +#define AES_CR_IPRST_Pos (31U) +#define AES_CR_IPRST_Msk (0x1UL << AES_CR_IPRST_Pos) /*!< 0x80000000 */ +#define AES_CR_IPRST AES_CR_IPRST_Msk /*!< AES IP software reset */ + + +/******************* Bit definition for AES_SR register *********************/ +#define AES_SR_CCF_Pos (0U) +#define AES_SR_CCF_Msk (0x1UL << AES_SR_CCF_Pos) /*!< 0x00000001 */ +#define AES_SR_CCF AES_SR_CCF_Msk /*!< Computation Complete Flag */ +#define AES_SR_RDERR_Pos (1U) +#define AES_SR_RDERR_Msk (0x1UL << AES_SR_RDERR_Pos) /*!< 0x00000002 */ +#define AES_SR_RDERR AES_SR_RDERR_Msk /*!< Read Error Flag */ +#define AES_SR_WRERR_Pos (2U) +#define AES_SR_WRERR_Msk (0x1UL << AES_SR_WRERR_Pos) /*!< 0x00000004 */ +#define AES_SR_WRERR AES_SR_WRERR_Msk /*!< Write Error Flag */ +#define AES_SR_BUSY_Pos (3U) +#define AES_SR_BUSY_Msk (0x1UL << AES_SR_BUSY_Pos) /*!< 0x00000008 */ +#define AES_SR_BUSY AES_SR_BUSY_Msk /*!< Busy Flag */ +#define AES_SR_KEYVALID_Pos (7U) +#define AES_SR_KEYVALID_Msk (0x1UL << AES_SR_KEYVALID_Pos) /*!< 0x00000080 */ +#define AES_SR_KEYVALID AES_SR_KEYVALID_Msk /*!< Key Valid Flag */ + +/******************* Bit definition for AES_DINR register *******************/ +#define AES_DINR_Pos (0U) +#define AES_DINR_Msk (0xFFFFFFFFUL << AES_DINR_Pos) /*!< 0xFFFFFFFF */ +#define AES_DINR AES_DINR_Msk /*!< AES Data Input Register */ + +/******************* Bit definition for AES_DOUTR register ******************/ +#define AES_DOUTR_Pos (0U) +#define AES_DOUTR_Msk (0xFFFFFFFFUL << AES_DOUTR_Pos) /*!< 0xFFFFFFFF */ +#define AES_DOUTR AES_DOUTR_Msk /*!< AES Data Output Register */ + +/******************* Bit definition for AES_KEYR0 register ******************/ +#define AES_KEYR0_Pos (0U) +#define AES_KEYR0_Msk (0xFFFFFFFFUL << AES_KEYR0_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR0 AES_KEYR0_Msk /*!< AES Key Register 0 */ + +/******************* Bit definition for AES_KEYR1 register ******************/ +#define AES_KEYR1_Pos (0U) +#define AES_KEYR1_Msk (0xFFFFFFFFUL << AES_KEYR1_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR1 AES_KEYR1_Msk /*!< AES Key Register 1 */ + +/******************* Bit definition for AES_KEYR2 register ******************/ +#define AES_KEYR2_Pos (0U) +#define AES_KEYR2_Msk (0xFFFFFFFFUL << AES_KEYR2_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR2 AES_KEYR2_Msk /*!< AES Key Register 2 */ + +/******************* Bit definition for AES_KEYR3 register ******************/ +#define AES_KEYR3_Pos (0U) +#define AES_KEYR3_Msk (0xFFFFFFFFUL << AES_KEYR3_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR3 AES_KEYR3_Msk /*!< AES Key Register 3 */ + +/******************* Bit definition for AES_KEYR4 register ******************/ +#define AES_KEYR4_Pos (0U) +#define AES_KEYR4_Msk (0xFFFFFFFFUL << AES_KEYR4_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR4 AES_KEYR4_Msk /*!< AES Key Register 4 */ + +/******************* Bit definition for AES_KEYR5 register ******************/ +#define AES_KEYR5_Pos (0U) +#define AES_KEYR5_Msk (0xFFFFFFFFUL << AES_KEYR5_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR5 AES_KEYR5_Msk /*!< AES Key Register 5 */ + +/******************* Bit definition for AES_KEYR6 register ******************/ +#define AES_KEYR6_Pos (0U) +#define AES_KEYR6_Msk (0xFFFFFFFFUL << AES_KEYR6_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR6 AES_KEYR6_Msk /*!< AES Key Register 6 */ + +/******************* Bit definition for AES_KEYR7 register ******************/ +#define AES_KEYR7_Pos (0U) +#define AES_KEYR7_Msk (0xFFFFFFFFUL << AES_KEYR7_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR7 AES_KEYR7_Msk /*!< AES Key Register 7 */ + +/******************* Bit definition for AES_IVR0 register ******************/ +#define AES_IVR0_Pos (0U) +#define AES_IVR0_Msk (0xFFFFFFFFUL << AES_IVR0_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR0 AES_IVR0_Msk /*!< AES Initialization Vector Register 0 */ + +/******************* Bit definition for AES_IVR1 register ******************/ +#define AES_IVR1_Pos (0U) +#define AES_IVR1_Msk (0xFFFFFFFFUL << AES_IVR1_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR1 AES_IVR1_Msk /*!< AES Initialization Vector Register 1 */ + +/******************* Bit definition for AES_IVR2 register ******************/ +#define AES_IVR2_Pos (0U) +#define AES_IVR2_Msk (0xFFFFFFFFUL << AES_IVR2_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR2 AES_IVR2_Msk /*!< AES Initialization Vector Register 2 */ + +/******************* Bit definition for AES_IVR3 register ******************/ +#define AES_IVR3_Pos (0U) +#define AES_IVR3_Msk (0xFFFFFFFFUL << AES_IVR3_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR3 AES_IVR3_Msk /*!< AES Initialization Vector Register 3 */ + +/******************* Bit definition for AES_SUSP0R register ******************/ +#define AES_SUSP0R_Pos (0U) +#define AES_SUSP0R_Msk (0xFFFFFFFFUL << AES_SUSP0R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP0R AES_SUSP0R_Msk /*!< AES Suspend registers 0 */ + +/******************* Bit definition for AES_SUSP1R register ******************/ +#define AES_SUSP1R_Pos (0U) +#define AES_SUSP1R_Msk (0xFFFFFFFFUL << AES_SUSP1R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP1R AES_SUSP1R_Msk /*!< AES Suspend registers 1 */ + +/******************* Bit definition for AES_SUSP2R register ******************/ +#define AES_SUSP2R_Pos (0U) +#define AES_SUSP2R_Msk (0xFFFFFFFFUL << AES_SUSP2R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP2R AES_SUSP2R_Msk /*!< AES Suspend registers 2 */ + +/******************* Bit definition for AES_SUSP3R register ******************/ +#define AES_SUSP3R_Pos (0U) +#define AES_SUSP3R_Msk (0xFFFFFFFFUL << AES_SUSP3R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP3R AES_SUSP3R_Msk /*!< AES Suspend registers 3 */ + +/******************* Bit definition for AES_SUSP4R register ******************/ +#define AES_SUSP4R_Pos (0U) +#define AES_SUSP4R_Msk (0xFFFFFFFFUL << AES_SUSP4R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP4R AES_SUSP4R_Msk /*!< AES Suspend registers 4 */ + +/******************* Bit definition for AES_SUSP5R register ******************/ +#define AES_SUSP5R_Pos (0U) +#define AES_SUSP5R_Msk (0xFFFFFFFFUL << AES_SUSP5R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP5R AES_SUSP5R_Msk /*!< AES Suspend registers 5 */ + +/******************* Bit definition for AES_SUSP6R register ******************/ +#define AES_SUSP6R_Pos (0U) +#define AES_SUSP6R_Msk (0xFFFFFFFFUL << AES_SUSP6R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP6R AES_SUSP6R_Msk /*!< AES Suspend registers 6 */ + +/******************* Bit definition for AES_SUSP7R register ******************/ +#define AES_SUSP7R_Pos (0U) +#define AES_SUSP7R_Msk (0xFFFFFFFFUL << AES_SUSP7R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP7R AES_SUSP7R_Msk /*!< AES Suspend registers 7 */ + +/******************* Bit definition for AES_IER register ******************/ +#define AES_IER_CCFIE_Pos (0U) +#define AES_IER_CCFIE_Msk (0x1UL << AES_IER_CCFIE_Pos) /*!< 0x00000001 */ +#define AES_IER_CCFIE AES_IER_CCFIE_Msk /*!< Computation complete flag interrupt enable */ +#define AES_IER_RWEIE_Pos (1U) +#define AES_IER_RWEIE_Msk (0x1UL << AES_IER_RWEIE_Pos) /*!< 0x00000002 */ +#define AES_IER_RWEIE AES_IER_RWEIE_Msk /*!< Read or write error Interrupt Enable */ +#define AES_IER_KEIE_Pos (2U) +#define AES_IER_KEIE_Msk (0x1UL << AES_IER_KEIE_Pos) /*!< 0x00000004 */ +#define AES_IER_KEIE AES_IER_KEIE_Msk /*!< Key error interrupt enable */ +#define AES_IER_RNGEIE_Pos (3U) +#define AES_IER_RNGEIE_Msk (0x1UL << AES_IER_RNGEIE_Pos) /*!< 0x00000008 */ +#define AES_IER_RNGEIE AES_IER_RNGEIE_Msk /*!< SAES Rng error interrupt enable */ + +/******************* Bit definition for AES_ISR register ******************/ +#define AES_ISR_CCF_Pos (0U) +#define AES_ISR_CCF_Msk (0x1UL << AES_ISR_CCF_Pos) /*!< 0x00000001 */ +#define AES_ISR_CCF AES_ISR_CCF_Msk /*!< Computation complete flag */ +#define AES_ISR_RWEIF_Pos (1U) +#define AES_ISR_RWEIF_Msk (0x1UL << AES_ISR_RWEIF_Pos) /*!< 0x00000002 */ +#define AES_ISR_RWEIF AES_ISR_RWEIF_Msk /*!< Read or write error Interrupt flag */ +#define AES_ISR_KEIF_Pos (2U) +#define AES_ISR_KEIF_Msk (0x1UL << AES_ISR_KEIF_Pos) /*!< 0x00000004 */ +#define AES_ISR_KEIF AES_ISR_KEIF_Msk /*!< Key error interrupt flag */ +#define AES_ISR_RNGEIF_Pos (3U) +#define AES_ISR_RNGEIF_Msk (0x1UL << AES_ISR_RNGEIF_Pos) /*!< 0x00000008 */ +#define AES_ISR_RNGEIF AES_ISR_RNGEIF_Msk /*!< SAES Rng error interrupt flag */ + +/******************* Bit definition for AES_ICR register ******************/ +#define AES_ICR_CCF_Pos (0U) +#define AES_ICR_CCF_Msk (0x1UL << AES_ICR_CCF_Pos) /*!< 0x00000001 */ +#define AES_ICR_CCF AES_ICR_CCF_Msk /*!< Computation complete flag clear */ +#define AES_ICR_RWEIF_Pos (1U) +#define AES_ICR_RWEIF_Msk (0x1UL << AES_ICR_RWEIF_Pos) /*!< 0x00000002 */ +#define AES_ICR_RWEIF AES_ICR_RWEIF_Msk /*!< Read or write error Interrupt flag clear */ +#define AES_ICR_KEIF_Pos (2U) +#define AES_ICR_KEIF_Msk (0x1UL << AES_ICR_KEIF_Pos) /*!< 0x00000004 */ +#define AES_ICR_KEIF AES_ICR_KEIF_Msk /*!< Key error interrupt flag clear */ +#define AES_ICR_RNGEIF_Pos (3U) +#define AES_ICR_RNGEIF_Msk (0x1UL << AES_ICR_RNGEIF_Pos) /*!< 0x00000008 */ +#define AES_ICR_RNGEIF AES_ICR_RNGEIF_Msk /*!< SAES Rng error interrupt flag clear */ + +/******************************************************************************/ +/* */ +/* Debug MCU */ +/* */ +/******************************************************************************/ +/******************** Bit definition for DBGMCU_IDCODE register *************/ +#define DBGMCU_IDCODE_DEV_ID_Pos (0U) +#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ +#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk +#define DBGMCU_IDCODE_REV_ID_Pos (16U) +#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ +#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk + +/******************** Bit definition for DBGMCU_SCR register *****************/ +#define DBGMCU_SCR_DBG_STOP_Pos (1U) +#define DBGMCU_SCR_DBG_STOP_Msk (0x1UL << DBGMCU_SCR_DBG_STOP_Pos) /*!< 0x00000002 */ +#define DBGMCU_SCR_DBG_STOP DBGMCU_SCR_DBG_STOP_Msk +#define DBGMCU_SCR_DBG_STANDBY_Pos (2U) +#define DBGMCU_SCR_DBG_STANDBY_Msk (0x1UL << DBGMCU_SCR_DBG_STANDBY_Pos) /*!< 0x00000004 */ +#define DBGMCU_SCR_DBG_STANDBY DBGMCU_SCR_DBG_STANDBY_Msk +#define DBGMCU_SCR_DBG_LPMS_Pos (16U) +#define DBGMCU_SCR_DBG_LPMS_Msk (0x7UL << DBGMCU_SCR_DBG_LPMS_Pos) /*!< 0x00070000 */ +#define DBGMCU_SCR_DBG_LPMS DBGMCU_SCR_DBG_LPMS_Msk +#define DBGMCU_SCR_DBG_LPMS_0 (0x1UL << DBGMCU_SCR_DBG_LPMS_Pos) +#define DBGMCU_SCR_DBG_LPMS_1 (0x2UL << DBGMCU_SCR_DBG_LPMS_Pos) +#define DBGMCU_SCR_DBG_LPMS_2 (0x4UL << DBGMCU_SCR_DBG_LPMS_Pos) +#define DBGMCU_SCR_DBG_STOPF_Pos (19U) +#define DBGMCU_SCR_DBG_STOPF_Msk (0x1UL << DBGMCU_SCR_DBG_STOPF_Pos) /*!< 0x00080000 */ +#define DBGMCU_SCR_DBG_STOPF DBGMCU_SCR_DBG_STOPF_Msk +#define DBGMCU_SCR_DBG_SBF_Pos (20U) +#define DBGMCU_SCR_DBG_SBF_Msk (0x1UL << DBGMCU_SCR_DBG_SBF_Pos) /*!< 0x00100000 */ +#define DBGMCU_SCR_DBG_SBF DBGMCU_SCR_DBG_SBF_Msk +#define DBGMCU_SCR_DBG_CS_Pos (24U) +#define DBGMCU_SCR_DBG_CS_Msk (0x1UL << DBGMCU_SCR_DBG_CS_Pos) /*!< 0x01000000 */ +#define DBGMCU_SCR_DBG_CS DBGMCU_SCR_DBG_CS_Msk +#define DBGMCU_SCR_DBG_CDS_Pos (25U) +#define DBGMCU_SCR_DBG_CDS_Msk (0x1UL << DBGMCU_SCR_DBG_CDS_Pos) /*!< 0x02000000 */ +#define DBGMCU_SCR_DBG_CDS DBGMCU_SCR_DBG_CDS_Msk + +/******************** Bit definition for DBGMCU_APB1LFZR register ***********/ +#define DBGMCU_APB1LFZR_DBG_TIM2_STOP_Pos (0U) +#define DBGMCU_APB1LFZR_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_TIM2_STOP_Pos) +#define DBGMCU_APB1LFZR_DBG_TIM2_STOP DBGMCU_APB1LFZR_DBG_TIM2_STOP_Msk +#define DBGMCU_APB1LFZR_DBG_WWDG_STOP_Pos (11U) +#define DBGMCU_APB1LFZR_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_WWDG_STOP_Pos) +#define DBGMCU_APB1LFZR_DBG_WWDG_STOP DBGMCU_APB1LFZR_DBG_WWDG_STOP_Msk +#define DBGMCU_APB1LFZR_DBG_IWDG_STOP_Pos (12U) +#define DBGMCU_APB1LFZR_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_IWDG_STOP_Pos) +#define DBGMCU_APB1LFZR_DBG_IWDG_STOP DBGMCU_APB1LFZR_DBG_IWDG_STOP_Msk + +/******************** Bit definition for DBGMCU_APB2FZR register ***********/ +#define DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos (11U) +#define DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos) +#define DBGMCU_APB2FZR_DBG_TIM1_STOP DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk +#define DBGMCU_APB2FZR_DBG_TIM16_STOP_Pos (17U) +#define DBGMCU_APB2FZR_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM16_STOP_Pos) +#define DBGMCU_APB2FZR_DBG_TIM16_STOP DBGMCU_APB2FZR_DBG_TIM16_STOP_Msk + +/******************** Bit definition for DBGMCU_APB7FZR register ***********/ +#define DBGMCU_APB7FZR_DBG_I2C3_STOP_Pos (10U) +#define DBGMCU_APB7FZR_DBG_I2C3_STOP_Msk (0x1UL << DBGMCU_APB7FZR_DBG_I2C3_STOP_Pos) +#define DBGMCU_APB7FZR_DBG_I2C3_STOP DBGMCU_APB7FZR_DBG_I2C3_STOP_Msk +#define DBGMCU_APB7FZR_DBG_LPTIM1_STOP_Pos (17U) +#define DBGMCU_APB7FZR_DBG_LPTIM1_STOP_Msk (0x1UL << DBGMCU_APB7FZR_DBG_LPTIM1_STOP_Pos) +#define DBGMCU_APB7FZR_DBG_LPTIM1_STOP DBGMCU_APB7FZR_DBG_LPTIM1_STOP_Msk +#define DBGMCU_APB7FZR_DBG_RTC_STOP_Pos (30U) +#define DBGMCU_APB7FZR_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB7FZR_DBG_RTC_STOP_Pos) +#define DBGMCU_APB7FZR_DBG_RTC_STOP DBGMCU_APB7FZR_DBG_RTC_STOP_Msk + +/******************** Bit definition for DBGMCU_AHB1FZR register ***********/ +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP_Pos (0U) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP_Pos) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP_Msk +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP_Pos (1U) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP_Pos) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP_Msk +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP_Pos (2U) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP_Pos) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP_Msk +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP_Pos (3U) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP_Pos) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP_Msk +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP_Pos (4U) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP_Pos) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP_Msk +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP_Pos (5U) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP_Pos) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP_Msk +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP_Pos (6U) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP_Pos) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP_Msk +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP_Pos (7U) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP_Pos) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP_Msk + + +/******************************************************************************/ +/* */ +/* DMA Controller (DMA) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for DMA_MISR register ****************/ +#define DMA_MISR_MIS0_Pos (0U) +#define DMA_MISR_MIS0_Msk (0x1UL << DMA_MISR_MIS0_Pos) /*!< 0x00000001 */ +#define DMA_MISR_MIS0 DMA_MISR_MIS0_Msk /*!< Masked Interrupt State of Non-Secure Channel 0 */ +#define DMA_MISR_MIS1_Pos (1U) +#define DMA_MISR_MIS1_Msk (0x1UL << DMA_MISR_MIS1_Pos) /*!< 0x00000002 */ +#define DMA_MISR_MIS1 DMA_MISR_MIS1_Msk /*!< Masked Interrupt State of Non-Secure Channel 1 */ +#define DMA_MISR_MIS2_Pos (2U) +#define DMA_MISR_MIS2_Msk (0x1UL << DMA_MISR_MIS2_Pos) /*!< 0x00000004 */ +#define DMA_MISR_MIS2 DMA_MISR_MIS2_Msk /*!< Masked Interrupt State of Non-Secure Channel 2 */ +#define DMA_MISR_MIS3_Pos (3U) +#define DMA_MISR_MIS3_Msk (0x1UL << DMA_MISR_MIS3_Pos) /*!< 0x00000008 */ +#define DMA_MISR_MIS3 DMA_MISR_MIS3_Msk /*!< Masked Interrupt State of Non-Secure Channel 3 */ +#define DMA_MISR_MIS4_Pos (4U) +#define DMA_MISR_MIS4_Msk (0x1UL << DMA_MISR_MIS4_Pos) /*!< 0x00000010 */ +#define DMA_MISR_MIS4 DMA_MISR_MIS4_Msk /*!< Masked Interrupt State of Non-Secure Channel 4 */ +#define DMA_MISR_MIS5_Pos (5U) +#define DMA_MISR_MIS5_Msk (0x1UL << DMA_MISR_MIS5_Pos) /*!< 0x00000020 */ +#define DMA_MISR_MIS5 DMA_MISR_MIS5_Msk /*!< Masked Interrupt State of Non-Secure Channel 5 */ +#define DMA_MISR_MIS6_Pos (6U) +#define DMA_MISR_MIS6_Msk (0x1UL << DMA_MISR_MIS6_Pos) /*!< 0x00000040 */ +#define DMA_MISR_MIS6 DMA_MISR_MIS6_Msk /*!< Masked Interrupt State of Non-Secure Channel 6 */ +#define DMA_MISR_MIS7_Pos (7U) +#define DMA_MISR_MIS7_Msk (0x1UL << DMA_MISR_MIS7_Pos) /*!< 0x00000080 */ +#define DMA_MISR_MIS7 DMA_MISR_MIS7_Msk /*!< Masked Interrupt State of Non-Secure Channel 7 */ + +/******************* Bit definition for DMA_SMISR register ****************/ +#define DMA_SMISR_MIS0_Pos (0U) +#define DMA_SMISR_MIS0_Msk (0x1UL << DMA_SMISR_MIS0_Pos) /*!< 0x00000001 */ +#define DMA_SMISR_MIS0 DMA_SMISR_MIS0_Msk /*!< Masked Interrupt State of Secure Channel 0 */ +#define DMA_SMISR_MIS1_Pos (1U) +#define DMA_SMISR_MIS1_Msk (0x1UL << DMA_SMISR_MIS1_Pos) /*!< 0x00000002 */ +#define DMA_SMISR_MIS1 DMA_SMISR_MIS1_Msk /*!< Masked Interrupt State of Secure Channel 1 */ +#define DMA_SMISR_MIS2_Pos (2U) +#define DMA_SMISR_MIS2_Msk (0x1UL << DMA_SMISR_MIS2_Pos) /*!< 0x00000004 */ +#define DMA_SMISR_MIS2 DMA_SMISR_MIS2_Msk /*!< Masked Interrupt State of Secure Channel 2 */ +#define DMA_SMISR_MIS3_Pos (3U) +#define DMA_SMISR_MIS3_Msk (0x1UL << DMA_SMISR_MIS3_Pos) /*!< 0x00000008 */ +#define DMA_SMISR_MIS3 DMA_SMISR_MIS3_Msk /*!< Masked Interrupt State of Secure Channel 3 */ +#define DMA_SMISR_MIS4_Pos (4U) +#define DMA_SMISR_MIS4_Msk (0x1UL << DMA_SMISR_MIS4_Pos) /*!< 0x00000010 */ +#define DMA_SMISR_MIS4 DMA_SMISR_MIS4_Msk /*!< Masked Interrupt State of Secure Channel 4 */ +#define DMA_SMISR_MIS5_Pos (5U) +#define DMA_SMISR_MIS5_Msk (0x1UL << DMA_SMISR_MIS5_Pos) /*!< 0x00000020 */ +#define DMA_SMISR_MIS5 DMA_SMISR_MIS5_Msk /*!< Masked Interrupt State of Secure Channel 5 */ +#define DMA_SMISR_MIS6_Pos (6U) +#define DMA_SMISR_MIS6_Msk (0x1UL << DMA_SMISR_MIS6_Pos) /*!< 0x00000040 */ +#define DMA_SMISR_MIS6 DMA_SMISR_MIS6_Msk /*!< Masked Interrupt State of Secure Channel 6 */ +#define DMA_SMISR_MIS7_Pos (7U) +#define DMA_SMISR_MIS7_Msk (0x1UL << DMA_SMISR_MIS7_Pos) /*!< 0x00000080 */ +#define DMA_SMISR_MIS7 DMA_SMISR_MIS7_Msk /*!< Masked Interrupt State of Secure Channel 7 */ + +/******************* Bit definition for DMA_CLBAR register ****************/ +#define DMA_CLBAR_LBA_Pos (16U) +#define DMA_CLBAR_LBA_Msk (0xFFFFUL << DMA_CLBAR_LBA_Pos) /*!< 0xFFFF0000 */ +#define DMA_CLBAR_LBA DMA_CLBAR_LBA_Msk /*!< Linked-list Base Address of DMA channel x */ + +/******************* Bit definition for DMA_CFCR register *******************/ +#define DMA_CFCR_TCF_Pos (8U) +#define DMA_CFCR_TCF_Msk (0x1UL << DMA_CFCR_TCF_Pos) /*!< 0x00000100 */ +#define DMA_CFCR_TCF DMA_CFCR_TCF_Msk /*!< Transfer complete flag clear */ +#define DMA_CFCR_HTF_Pos (9U) +#define DMA_CFCR_HTF_Msk (0x1UL << DMA_CFCR_HTF_Pos) /*!< 0x00000200 */ +#define DMA_CFCR_HTF DMA_CFCR_HTF_Msk /*!< Half transfer complete flag clear */ +#define DMA_CFCR_DTEF_Pos (10U) +#define DMA_CFCR_DTEF_Msk (0x1UL << DMA_CFCR_DTEF_Pos) /*!< 0x00000400 */ +#define DMA_CFCR_DTEF DMA_CFCR_DTEF_Msk /*!< Data transfer error flag clear */ +#define DMA_CFCR_ULEF_Pos (11U) +#define DMA_CFCR_ULEF_Msk (0x1UL << DMA_CFCR_ULEF_Pos) /*!< 0x00000800 */ +#define DMA_CFCR_ULEF DMA_CFCR_ULEF_Msk /*!< Update linked-list item error flag clear */ +#define DMA_CFCR_USEF_Pos (12U) +#define DMA_CFCR_USEF_Msk (0x1UL << DMA_CFCR_USEF_Pos) /*!< 0x00001000 */ +#define DMA_CFCR_USEF DMA_CFCR_USEF_Msk /*!< User setting error flag clear */ +#define DMA_CFCR_SUSPF_Pos (13U) +#define DMA_CFCR_SUSPF_Msk (0x1UL << DMA_CFCR_SUSPF_Pos) /*!< 0x00002000 */ +#define DMA_CFCR_SUSPF DMA_CFCR_SUSPF_Msk /*!< Completed suspension flag clear */ +#define DMA_CFCR_TOF_Pos (14U) +#define DMA_CFCR_TOF_Msk (0x1UL << DMA_CFCR_TOF_Pos) /*!< 0x00004000 */ +#define DMA_CFCR_TOF DMA_CFCR_TOF_Msk /*!< Trigger overrun flag clear */ + +/******************* Bit definition for DMA_CSR register *******************/ +#define DMA_CSR_IDLEF_Pos (0U) +#define DMA_CSR_IDLEF_Msk (0x1UL << DMA_CSR_IDLEF_Pos) /*!< 0x00000001 */ +#define DMA_CSR_IDLEF DMA_CSR_IDLEF_Msk /*!< Idle flag */ +#define DMA_CSR_TCF_Pos (8U) +#define DMA_CSR_TCF_Msk (0x1UL << DMA_CSR_TCF_Pos) /*!< 0x00000100 */ +#define DMA_CSR_TCF DMA_CSR_TCF_Msk /*!< Transfer complete flag */ +#define DMA_CSR_HTF_Pos (9U) +#define DMA_CSR_HTF_Msk (0x1UL << DMA_CSR_HTF_Pos) /*!< 0x00000200 */ +#define DMA_CSR_HTF DMA_CSR_HTF_Msk /*!< Half transfer complete flag */ +#define DMA_CSR_DTEF_Pos (10U) +#define DMA_CSR_DTEF_Msk (0x1UL << DMA_CSR_DTEF_Pos) /*!< 0x00000400 */ +#define DMA_CSR_DTEF DMA_CSR_DTEF_Msk /*!< Data transfer error flag */ +#define DMA_CSR_ULEF_Pos (11U) +#define DMA_CSR_ULEF_Msk (0x1UL << DMA_CSR_ULEF_Pos) /*!< 0x00000800 */ +#define DMA_CSR_ULEF DMA_CSR_ULEF_Msk /*!< Update linked-list item error flag */ +#define DMA_CSR_USEF_Pos (12U) +#define DMA_CSR_USEF_Msk (0x1UL << DMA_CSR_USEF_Pos) /*!< 0x00001000 */ +#define DMA_CSR_USEF DMA_CSR_USEF_Msk /*!< User setting error flag */ +#define DMA_CSR_SUSPF_Pos (13U) +#define DMA_CSR_SUSPF_Msk (0x1UL << DMA_CSR_SUSPF_Pos) /*!< 0x00002000 */ +#define DMA_CSR_SUSPF DMA_CSR_SUSPF_Msk /*!< User setting error flag */ +#define DMA_CSR_TOF_Pos (14U) +#define DMA_CSR_TOF_Msk (0x1UL << DMA_CSR_TOF_Pos) /*!< 0x00004000 */ +#define DMA_CSR_TOF DMA_CSR_TOF_Msk /*!< Trigger overrun event flag */ +#define DMA_CSR_FIFOL_Pos (16U) +#define DMA_CSR_FIFOL_Msk (0xFFUL << DMA_CSR_FIFOL_Pos) /*!< 0x00FF0000 */ +#define DMA_CSR_FIFOL DMA_CSR_FIFOL_Msk /*!< Monitored FIFO level in bytes */ + +/******************* Bit definition for DMA_CCR register ********************/ +#define DMA_CCR_EN_Pos (0U) +#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */ +#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ +#define DMA_CCR_RESET_Pos (1U) +#define DMA_CCR_RESET_Msk (0x1UL << DMA_CCR_RESET_Pos) /*!< 0x00000002 */ +#define DMA_CCR_RESET DMA_CCR_RESET_Msk /*!< Channel reset */ +#define DMA_CCR_SUSP_Pos (2U) +#define DMA_CCR_SUSP_Msk (0x1UL << DMA_CCR_SUSP_Pos) /*!< 0x00000004 */ +#define DMA_CCR_SUSP DMA_CCR_SUSP_Msk /*!< Channel suspend */ +#define DMA_CCR_TCIE_Pos (8U) +#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000100 */ +#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ +#define DMA_CCR_HTIE_Pos (9U) +#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000200 */ +#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half transfer complete interrupt enable */ +#define DMA_CCR_DTEIE_Pos (10U) +#define DMA_CCR_DTEIE_Msk (0x1UL << DMA_CCR_DTEIE_Pos) /*!< 0x00000400 */ +#define DMA_CCR_DTEIE DMA_CCR_DTEIE_Msk /*!< Data transfer error interrupt enable */ +#define DMA_CCR_ULEIE_Pos (11U) +#define DMA_CCR_ULEIE_Msk (0x1UL << DMA_CCR_ULEIE_Pos) /*!< 0x00000800 */ +#define DMA_CCR_ULEIE DMA_CCR_ULEIE_Msk /*!< Update linked-list item error interrupt enable */ +#define DMA_CCR_USEIE_Pos (12U) +#define DMA_CCR_USEIE_Msk (0x1UL << DMA_CCR_USEIE_Pos) /*!< 0x00001000 */ +#define DMA_CCR_USEIE DMA_CCR_USEIE_Msk /*!< User setting error interrupt enable */ +#define DMA_CCR_SUSPIE_Pos (13U) +#define DMA_CCR_SUSPIE_Msk (0x1UL << DMA_CCR_SUSPIE_Pos) /*!< 0x00002000 */ +#define DMA_CCR_SUSPIE DMA_CCR_SUSPIE_Msk /*!< Completed suspension interrupt enable */ +#define DMA_CCR_TOIE_Pos (14U) +#define DMA_CCR_TOIE_Msk (0x1UL << DMA_CCR_TOIE_Pos) /*!< 0x00004000 */ +#define DMA_CCR_TOIE DMA_CCR_TOIE_Msk /*!< Trigger overrun interrupt enable */ +#define DMA_CCR_LSM_Pos (16U) +#define DMA_CCR_LSM_Msk (0x1UL << DMA_CCR_LSM_Pos) /*!< 0x00010000 */ +#define DMA_CCR_LSM DMA_CCR_LSM_Msk /*!< Link step mode */ +#define DMA_CCR_LAP_Pos (17U) +#define DMA_CCR_LAP_Msk (0x1UL << DMA_CCR_LAP_Pos) /*!< 0x00020000 */ +#define DMA_CCR_LAP DMA_CCR_LAP_Msk /*!< Linked-list allocated port */ +#define DMA_CCR_PRIO_Pos (22U) +#define DMA_CCR_PRIO_Msk (0x3UL << DMA_CCR_PRIO_Pos) /*!< 0x00C00000 */ +#define DMA_CCR_PRIO DMA_CCR_PRIO_Msk /*!< Priority level */ +#define DMA_CCR_PRIO_0 (0x1UL << DMA_CCR_PRIO_Pos) /*!< 0x00400000 */ +#define DMA_CCR_PRIO_1 (0x2UL << DMA_CCR_PRIO_Pos) /*!< 0x00800000 */ + +/******************* Bit definition for DMA_CTR1 register *******************/ +#define DMA_CTR1_SDW_LOG2_Pos (0U) +#define DMA_CTR1_SDW_LOG2_Msk (0x3UL << DMA_CTR1_SDW_LOG2_Pos) /*!< 0x00000003 */ +#define DMA_CTR1_SDW_LOG2 DMA_CTR1_SDW_LOG2_Msk /*!< Binary logarithm of the source data width of a burst */ +#define DMA_CTR1_SDW_LOG2_0 (0x1UL << DMA_CTR1_SDW_LOG2_Pos) /*!< Bit 0 */ +#define DMA_CTR1_SDW_LOG2_1 (0x2UL << DMA_CTR1_SDW_LOG2_Pos) /*!< Bit 1 */ +#define DMA_CTR1_SINC_Pos (3U) +#define DMA_CTR1_SINC_Msk (0x1UL << DMA_CTR1_SINC_Pos) /*!< 0x00000008 */ +#define DMA_CTR1_SINC DMA_CTR1_SINC_Msk /*!< Source incrementing burst */ +#define DMA_CTR1_SBL_1_Pos (4U) +#define DMA_CTR1_SBL_1_Msk (0x3FUL << DMA_CTR1_SBL_1_Pos) /*!< 0x000003F0 */ +#define DMA_CTR1_SBL_1 DMA_CTR1_SBL_1_Msk /*!< Source burst length minus 1 */ +#define DMA_CTR1_PAM_Pos (11U) +#define DMA_CTR1_PAM_Msk (0x3UL << DMA_CTR1_PAM_Pos) /*!< 0x0001800 */ +#define DMA_CTR1_PAM DMA_CTR1_PAM_Msk /*!< Padding / alignment mode */ +#define DMA_CTR1_PAM_0 (0x1UL << DMA_CTR1_PAM_Pos) /*!< Bit 0 */ +#define DMA_CTR1_PAM_1 (0x2UL << DMA_CTR1_PAM_Pos) /*!< Bit 1 */ +#define DMA_CTR1_SBX_Pos (13U) +#define DMA_CTR1_SBX_Msk (0x1UL << DMA_CTR1_SBX_Pos) /*!< 0x00002000 */ +#define DMA_CTR1_SBX DMA_CTR1_SBX_Msk /*!< Source byte exchange within the unaligned half-word of each source word */ +#define DMA_CTR1_SAP_Pos (14U) +#define DMA_CTR1_SAP_Msk (0x1UL << DMA_CTR1_SAP_Pos) /*!< 0x00004000 */ +#define DMA_CTR1_SAP DMA_CTR1_SAP_Msk /*!< Source allocated port */ +#define DMA_CTR1_SSEC_Pos (15U) +#define DMA_CTR1_SSEC_Msk (0x1UL << DMA_CTR1_SSEC_Pos) /*!< 0x00008000 */ +#define DMA_CTR1_SSEC DMA_CTR1_SSEC_Msk /*!< Security attribute of the DMA transfer from the source */ +#define DMA_CTR1_DDW_LOG2_Pos (16U) +#define DMA_CTR1_DDW_LOG2_Msk (0x3UL << DMA_CTR1_DDW_LOG2_Pos) /*!< 0x00030000 */ +#define DMA_CTR1_DDW_LOG2 DMA_CTR1_DDW_LOG2_Msk /*!< Binary logarithm of the destination data width of a burst */ +#define DMA_CTR1_DDW_LOG2_0 (0x1UL << DMA_CTR1_DDW_LOG2_Pos) /*!< Bit 0 */ +#define DMA_CTR1_DDW_LOG2_1 (0x2UL << DMA_CTR1_DDW_LOG2_Pos) /*!< Bit 1 */ +#define DMA_CTR1_DINC_Pos (19U) +#define DMA_CTR1_DINC_Msk (0x1UL << DMA_CTR1_DINC_Pos) /*!< 0x00080000 */ +#define DMA_CTR1_DINC DMA_CTR1_DINC_Msk /*!< Destination incrementing burst */ +#define DMA_CTR1_DBL_1_Pos (20U) +#define DMA_CTR1_DBL_1_Msk (0x3FUL << DMA_CTR1_DBL_1_Pos) /*!< 0x03F00000 */ +#define DMA_CTR1_DBL_1 DMA_CTR1_DBL_1_Msk /*!< Destination burst length minus 1 */ +#define DMA_CTR1_DBX_Pos (26U) +#define DMA_CTR1_DBX_Msk (0x1UL << DMA_CTR1_DBX_Pos) /*!< 0x04000000 */ +#define DMA_CTR1_DBX DMA_CTR1_DBX_Msk /*!< Destination byte exchange */ +#define DMA_CTR1_DHX_Pos (27U) +#define DMA_CTR1_DHX_Msk (0x1UL << DMA_CTR1_DHX_Pos) /*!< 0x08000000 */ +#define DMA_CTR1_DHX DMA_CTR1_DHX_Msk /*!< Destination half-word exchange */ +#define DMA_CTR1_DAP_Pos (30U) +#define DMA_CTR1_DAP_Msk (0x1UL << DMA_CTR1_DAP_Pos) /*!< 0x40000000 */ +#define DMA_CTR1_DAP DMA_CTR1_DAP_Msk /*!< Destination allocated port */ +#define DMA_CTR1_DSEC_Pos (31U) +#define DMA_CTR1_DSEC_Msk (0x1UL << DMA_CTR1_DSEC_Pos) /*!< 0x80000000 */ +#define DMA_CTR1_DSEC DMA_CTR1_DSEC_Msk /*!< Security attribute of the DMA transfer from the destination */ + +/****************** Bit definition for DMA_CTR2 register *******************/ +#define DMA_CTR2_REQSEL_Pos (0U) +#define DMA_CTR2_REQSEL_Msk (0x3FUL << DMA_CTR2_REQSEL_Pos) /*!< 0x0000003F */ +#define DMA_CTR2_REQSEL DMA_CTR2_REQSEL_Msk /*!< DMA hardware request selection */ +#define DMA_CTR2_SWREQ_Pos (9U) +#define DMA_CTR2_SWREQ_Msk (0x1UL << DMA_CTR2_SWREQ_Pos) /*!< 0x00000100 */ +#define DMA_CTR2_SWREQ DMA_CTR2_SWREQ_Msk /*!< Software request */ +#define DMA_CTR2_DREQ_Pos (10U) +#define DMA_CTR2_DREQ_Msk (0x1UL << DMA_CTR2_DREQ_Pos) /*!< 0x00000100 */ +#define DMA_CTR2_DREQ DMA_CTR2_DREQ_Msk /*!< Destination hardware request */ +#define DMA_CTR2_BREQ_Pos (11U) +#define DMA_CTR2_BREQ_Msk (0x1UL << DMA_CTR2_BREQ_Pos) /*!< 0x00000200 */ +#define DMA_CTR2_BREQ DMA_CTR2_BREQ_Msk /*!< Block hardware request */ +#define DMA_CTR2_TRIGM_Pos (14U) +#define DMA_CTR2_TRIGM_Msk (0x3UL << DMA_CTR2_TRIGM_Pos) /*!< 0x0000C000 */ +#define DMA_CTR2_TRIGM DMA_CTR2_TRIGM_Msk /*!< Trigger mode */ +#define DMA_CTR2_TRIGM_0 (0x1UL << DMA_CTR2_TRIGM_Pos) /*!< Bit 0 */ +#define DMA_CTR2_TRIGM_1 (0x2UL << DMA_CTR2_TRIGM_Pos) /*!< Bit 1 */ +#define DMA_CTR2_TRIGSEL_Pos (16U) +#define DMA_CTR2_TRIGSEL_Msk (0x1FUL << DMA_CTR2_TRIGSEL_Pos) /*!< 0x001F0000 */ +#define DMA_CTR2_TRIGSEL DMA_CTR2_TRIGSEL_Msk /*!< Trigger event input selection */ +#define DMA_CTR2_TRIGPOL_Pos (24U) +#define DMA_CTR2_TRIGPOL_Msk (0x3UL << DMA_CTR2_TRIGPOL_Pos) /*!< 0x03000000 */ +#define DMA_CTR2_TRIGPOL DMA_CTR2_TRIGPOL_Msk /*!< Trigger event polarity */ +#define DMA_CTR2_TRIGPOL_0 (0x1UL << DMA_CTR2_TRIGPOL_Pos) /*!< Bit 0 */ +#define DMA_CTR2_TRIGPOL_1 (0x2UL << DMA_CTR2_TRIGPOL_Pos) /*!< Bit 1 */ +#define DMA_CTR2_TCEM_Pos (30U) +#define DMA_CTR2_TCEM_Msk (0x3UL << DMA_CTR2_TCEM_Pos) /*!< 0xC0000000 */ +#define DMA_CTR2_TCEM DMA_CTR2_TCEM_Msk /*!< Transfer complete event mode */ +#define DMA_CTR2_TCEM_0 (0x1UL << DMA_CTR2_TCEM_Pos) /*!< Bit 0 */ +#define DMA_CTR2_TCEM_1 (0x2UL << DMA_CTR2_TCEM_Pos) /*!< Bit 1 */ + +/****************** Bit definition for DMA_CBR1 register *******************/ +#define DMA_CBR1_BNDT_Pos (0U) +#define DMA_CBR1_BNDT_Msk (0xFFFFUL << DMA_CBR1_BNDT_Pos) /*!< 0x0000FFFF */ +#define DMA_CBR1_BNDT DMA_CBR1_BNDT_Msk /*!< Block number of data bytes to transfer from the source */ + +/****************** Bit definition for DMA_CSAR register ********************/ +#define DMA_CSAR_SA_Pos (0U) +#define DMA_CSAR_SA_Msk (0xFFFFFFFFUL << DMA_CSAR_SA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CSAR_SA DMA_CSAR_SA_Msk /*!< Source Address */ + +/****************** Bit definition for DMA_CDAR register *******************/ +#define DMA_CDAR_DA_Pos (0U) +#define DMA_CDAR_DA_Msk (0xFFFFFFFFUL << DMA_CDAR_DA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CDAR_DA DMA_CDAR_DA_Msk /*!< Destination address */ + +/****************** Bit definition for DMA_CLLR register *******************/ +#define DMA_CLLR_LA_Pos (2U) +#define DMA_CLLR_LA_Msk (0x3FFFUL << DMA_CLLR_LA_Pos) /*!< 0x0000FFFC */ +#define DMA_CLLR_LA DMA_CLLR_LA_Msk /*!< Pointer to the next linked-list data structure */ +#define DMA_CLLR_ULL_Pos (16U) +#define DMA_CLLR_ULL_Msk (0x1UL << DMA_CLLR_ULL_Pos) /*!< 0x00010000 */ +#define DMA_CLLR_ULL DMA_CLLR_ULL_Msk /*!< Update link address register from memory */ +#define DMA_CLLR_UDA_Pos (27U) +#define DMA_CLLR_UDA_Msk (0x1UL << DMA_CLLR_UDA_Pos) /*!< 0x08000000 */ +#define DMA_CLLR_UDA DMA_CLLR_UDA_Msk /*!< Update destination address register from SRAM */ +#define DMA_CLLR_USA_Pos (28U) +#define DMA_CLLR_USA_Msk (0x1UL << DMA_CLLR_USA_Pos) /*!< 0x10000000 */ +#define DMA_CLLR_USA DMA_CLLR_USA_Msk /*!< Update source address register from SRAM */ +#define DMA_CLLR_UB1_Pos (29U) +#define DMA_CLLR_UB1_Msk (0x1UL << DMA_CLLR_UB1_Pos) /*!< 0x20000000 */ +#define DMA_CLLR_UB1 DMA_CLLR_UB1_Msk /*!< Update block register 1 from SRAM */ +#define DMA_CLLR_UT2_Pos (30U) +#define DMA_CLLR_UT2_Msk (0x1UL << DMA_CLLR_UT2_Pos) /*!< 0x40000000 */ +#define DMA_CLLR_UT2 DMA_CLLR_UT2_Msk /*!< Update transfer register 2 from SRAM */ +#define DMA_CLLR_UT1_Pos (31U) +#define DMA_CLLR_UT1_Msk (0x1UL << DMA_CLLR_UT1_Pos) /*!< 0x80000000 */ +#define DMA_CLLR_UT1 DMA_CLLR_UT1_Msk /*!< Update transfer register 1 from SRAM */ + +/******************************************************************************/ +/* */ +/* External Interrupt/Event Controller */ +/* */ +/******************************************************************************/ +/****************** Bit definition for EXTI_RTSR1 register ******************/ +#define EXTI_RTSR1_RT0_Pos (0U) +#define EXTI_RTSR1_RT0_Msk (0x1UL << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */ +#define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger configuration for input line 0 */ +#define EXTI_RTSR1_RT1_Pos (1U) +#define EXTI_RTSR1_RT1_Msk (0x1UL << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */ +#define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger configuration for input line 1 */ +#define EXTI_RTSR1_RT2_Pos (2U) +#define EXTI_RTSR1_RT2_Msk (0x1UL << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */ +#define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger configuration for input line 2 */ +#define EXTI_RTSR1_RT3_Pos (3U) +#define EXTI_RTSR1_RT3_Msk (0x1UL << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */ +#define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger configuration for input line 3 */ +#define EXTI_RTSR1_RT4_Pos (4U) +#define EXTI_RTSR1_RT4_Msk (0x1UL << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */ +#define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger configuration for input line 4 */ +#define EXTI_RTSR1_RT5_Pos (5U) +#define EXTI_RTSR1_RT5_Msk (0x1UL << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */ +#define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger configuration for input line 5 */ +#define EXTI_RTSR1_RT6_Pos (6U) +#define EXTI_RTSR1_RT6_Msk (0x1UL << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */ +#define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger configuration for input line 6 */ +#define EXTI_RTSR1_RT7_Pos (7U) +#define EXTI_RTSR1_RT7_Msk (0x1UL << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */ +#define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger configuration for input line 7 */ +#define EXTI_RTSR1_RT8_Pos (8U) +#define EXTI_RTSR1_RT8_Msk (0x1UL << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */ +#define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger configuration for input line 8 */ +#define EXTI_RTSR1_RT9_Pos (9U) +#define EXTI_RTSR1_RT9_Msk (0x1UL << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */ +#define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger configuration for input line 9 */ +#define EXTI_RTSR1_RT12_Pos (12U) +#define EXTI_RTSR1_RT12_Msk (0x1UL << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */ +#define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger configuration for input line 12 */ +#define EXTI_RTSR1_RT13_Pos (13U) +#define EXTI_RTSR1_RT13_Msk (0x1UL << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */ +#define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger configuration for input line 13 */ +#define EXTI_RTSR1_RT14_Pos (14U) +#define EXTI_RTSR1_RT14_Msk (0x1UL << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */ +#define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger configuration for input line 14 */ +#define EXTI_RTSR1_RT15_Pos (15U) +#define EXTI_RTSR1_RT15_Msk (0x1UL << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */ +#define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger configuration for input line 15 */ +#define EXTI_RTSR1_RT18_Pos (18U) +#define EXTI_RTSR1_RT18_Msk (0x1UL << EXTI_RTSR1_RT18_Pos) /*!< 0x00040000 */ +#define EXTI_RTSR1_RT18 EXTI_RTSR1_RT18_Msk /*!< Rising trigger configuration for input line 18 */ + +/****************** Bit definition for EXTI_FTSR1 register ******************/ +#define EXTI_FTSR1_FT0_Pos (0U) +#define EXTI_FTSR1_FT0_Msk (0x1UL << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */ +#define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger configuration for input line 0 */ +#define EXTI_FTSR1_FT1_Pos (1U) +#define EXTI_FTSR1_FT1_Msk (0x1UL << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */ +#define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger configuration for input line 1 */ +#define EXTI_FTSR1_FT2_Pos (2U) +#define EXTI_FTSR1_FT2_Msk (0x1UL << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */ +#define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger configuration for input line 2 */ +#define EXTI_FTSR1_FT3_Pos (3U) +#define EXTI_FTSR1_FT3_Msk (0x1UL << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */ +#define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger configuration for input line 3 */ +#define EXTI_FTSR1_FT4_Pos (4U) +#define EXTI_FTSR1_FT4_Msk (0x1UL << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */ +#define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger configuration for input line 4 */ +#define EXTI_FTSR1_FT5_Pos (5U) +#define EXTI_FTSR1_FT5_Msk (0x1UL << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */ +#define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger configuration for input line 5 */ +#define EXTI_FTSR1_FT6_Pos (6U) +#define EXTI_FTSR1_FT6_Msk (0x1UL << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */ +#define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger configuration for input line 6 */ +#define EXTI_FTSR1_FT7_Pos (7U) +#define EXTI_FTSR1_FT7_Msk (0x1UL << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */ +#define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger configuration for input line 7 */ +#define EXTI_FTSR1_FT8_Pos (8U) +#define EXTI_FTSR1_FT8_Msk (0x1UL << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */ +#define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger configuration for input line 8 */ +#define EXTI_FTSR1_FT9_Pos (9U) +#define EXTI_FTSR1_FT9_Msk (0x1UL << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */ +#define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger configuration for input line 9 */ +#define EXTI_FTSR1_FT12_Pos (12U) +#define EXTI_FTSR1_FT12_Msk (0x1UL << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */ +#define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger configuration for input line 12 */ +#define EXTI_FTSR1_FT13_Pos (13U) +#define EXTI_FTSR1_FT13_Msk (0x1UL << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */ +#define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger configuration for input line 13 */ +#define EXTI_FTSR1_FT14_Pos (14U) +#define EXTI_FTSR1_FT14_Msk (0x1UL << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */ +#define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger configuration for input line 14 */ +#define EXTI_FTSR1_FT15_Pos (15U) +#define EXTI_FTSR1_FT15_Msk (0x1UL << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */ +#define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger configuration for input line 15 */ +#define EXTI_FTSR1_FT18_Pos (18U) +#define EXTI_FTSR1_FT18_Msk (0x1UL << EXTI_FTSR1_FT18_Pos) /*!< 0x00040000 */ +#define EXTI_FTSR1_FT18 EXTI_FTSR1_FT18_Msk /*!< Falling trigger configuration for input line 18 */ + +/****************** Bit definition for EXTI_SWIER1 register *****************/ +#define EXTI_SWIER1_SWI0_Pos (0U) +#define EXTI_SWIER1_SWI0_Msk (0x1UL << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */ +#define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software Interrupt on line 0 */ +#define EXTI_SWIER1_SWI1_Pos (1U) +#define EXTI_SWIER1_SWI1_Msk (0x1UL << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */ +#define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software Interrupt on line 1 */ +#define EXTI_SWIER1_SWI2_Pos (2U) +#define EXTI_SWIER1_SWI2_Msk (0x1UL << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */ +#define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software Interrupt on line 2 */ +#define EXTI_SWIER1_SWI3_Pos (3U) +#define EXTI_SWIER1_SWI3_Msk (0x1UL << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */ +#define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software Interrupt on line 3 */ +#define EXTI_SWIER1_SWI4_Pos (4U) +#define EXTI_SWIER1_SWI4_Msk (0x1UL << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */ +#define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software Interrupt on line 4 */ +#define EXTI_SWIER1_SWI5_Pos (5U) +#define EXTI_SWIER1_SWI5_Msk (0x1UL << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */ +#define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software Interrupt on line 5 */ +#define EXTI_SWIER1_SWI6_Pos (6U) +#define EXTI_SWIER1_SWI6_Msk (0x1UL << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */ +#define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software Interrupt on line 6 */ +#define EXTI_SWIER1_SWI7_Pos (7U) +#define EXTI_SWIER1_SWI7_Msk (0x1UL << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */ +#define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software Interrupt on line 7 */ +#define EXTI_SWIER1_SWI8_Pos (8U) +#define EXTI_SWIER1_SWI8_Msk (0x1UL << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */ +#define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software Interrupt on line 8 */ +#define EXTI_SWIER1_SWI9_Pos (9U) +#define EXTI_SWIER1_SWI9_Msk (0x1UL << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */ +#define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software Interrupt on line 9 */ +#define EXTI_SWIER1_SWI12_Pos (12U) +#define EXTI_SWIER1_SWI12_Msk (0x1UL << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */ +#define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software Interrupt on line 12 */ +#define EXTI_SWIER1_SWI13_Pos (13U) +#define EXTI_SWIER1_SWI13_Msk (0x1UL << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */ +#define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software Interrupt on line 13 */ +#define EXTI_SWIER1_SWI14_Pos (14U) +#define EXTI_SWIER1_SWI14_Msk (0x1UL << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */ +#define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software Interrupt on line 14 */ +#define EXTI_SWIER1_SWI15_Pos (15U) +#define EXTI_SWIER1_SWI15_Msk (0x1UL << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */ +#define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software Interrupt on line 15 */ +#define EXTI_SWIER1_SWI18_Pos (18U) +#define EXTI_SWIER1_SWI18_Msk (0x1UL << EXTI_SWIER1_SWI18_Pos) /*!< 0x00040000 */ +#define EXTI_SWIER1_SWI18 EXTI_SWIER1_SWI18_Msk /*!< Software Interrupt on line 18 */ + +/******************* Bit definition for EXTI_RPR1 register ******************/ +#define EXTI_RPR1_RPIF0_Pos (0U) +#define EXTI_RPR1_RPIF0_Msk (0x1UL << EXTI_RPR1_RPIF0_Pos) /*!< 0x00000001 */ +#define EXTI_RPR1_RPIF0 EXTI_RPR1_RPIF0_Msk /*!< Rising Pending Interrupt Flag on line 0 */ +#define EXTI_RPR1_RPIF1_Pos (1U) +#define EXTI_RPR1_RPIF1_Msk (0x1UL << EXTI_RPR1_RPIF1_Pos) /*!< 0x00000002 */ +#define EXTI_RPR1_RPIF1 EXTI_RPR1_RPIF1_Msk /*!< Rising Pending Interrupt Flag on line 1 */ +#define EXTI_RPR1_RPIF2_Pos (2U) +#define EXTI_RPR1_RPIF2_Msk (0x1UL << EXTI_RPR1_RPIF2_Pos) /*!< 0x00000004 */ +#define EXTI_RPR1_RPIF2 EXTI_RPR1_RPIF2_Msk /*!< Rising Pending Interrupt Flag on line 2 */ +#define EXTI_RPR1_RPIF3_Pos (3U) +#define EXTI_RPR1_RPIF3_Msk (0x1UL << EXTI_RPR1_RPIF3_Pos) /*!< 0x00000008 */ +#define EXTI_RPR1_RPIF3 EXTI_RPR1_RPIF3_Msk /*!< Rising Pending Interrupt Flag on line 3 */ +#define EXTI_RPR1_RPIF4_Pos (4U) +#define EXTI_RPR1_RPIF4_Msk (0x1UL << EXTI_RPR1_RPIF4_Pos) /*!< 0x00000010 */ +#define EXTI_RPR1_RPIF4 EXTI_RPR1_RPIF4_Msk /*!< Rising Pending Interrupt Flag on line 4 */ +#define EXTI_RPR1_RPIF5_Pos (5U) +#define EXTI_RPR1_RPIF5_Msk (0x1UL << EXTI_RPR1_RPIF5_Pos) /*!< 0x00000020 */ +#define EXTI_RPR1_RPIF5 EXTI_RPR1_RPIF5_Msk /*!< Rising Pending Interrupt Flag on line 5 */ +#define EXTI_RPR1_RPIF6_Pos (6U) +#define EXTI_RPR1_RPIF6_Msk (0x1UL << EXTI_RPR1_RPIF6_Pos) /*!< 0x00000040 */ +#define EXTI_RPR1_RPIF6 EXTI_RPR1_RPIF6_Msk /*!< Rising Pending Interrupt Flag on line 6 */ +#define EXTI_RPR1_RPIF7_Pos (7U) +#define EXTI_RPR1_RPIF7_Msk (0x1UL << EXTI_RPR1_RPIF7_Pos) /*!< 0x00000080 */ +#define EXTI_RPR1_RPIF7 EXTI_RPR1_RPIF7_Msk /*!< Rising Pending Interrupt Flag on line 7 */ +#define EXTI_RPR1_RPIF8_Pos (8U) +#define EXTI_RPR1_RPIF8_Msk (0x1UL << EXTI_RPR1_RPIF8_Pos) /*!< 0x00000100 */ +#define EXTI_RPR1_RPIF8 EXTI_RPR1_RPIF8_Msk /*!< Rising Pending Interrupt Flag on line 8 */ +#define EXTI_RPR1_RPIF9_Pos (9U) +#define EXTI_RPR1_RPIF9_Msk (0x1UL << EXTI_RPR1_RPIF9_Pos) /*!< 0x00000200 */ +#define EXTI_RPR1_RPIF9 EXTI_RPR1_RPIF9_Msk /*!< Rising Pending Interrupt Flag on line 9 */ +#define EXTI_RPR1_RPIF12_Pos (12U) +#define EXTI_RPR1_RPIF12_Msk (0x1UL << EXTI_RPR1_RPIF12_Pos) /*!< 0x00001000 */ +#define EXTI_RPR1_RPIF12 EXTI_RPR1_RPIF12_Msk /*!< Rising Pending Interrupt Flag on line 12 */ +#define EXTI_RPR1_RPIF13_Pos (13U) +#define EXTI_RPR1_RPIF13_Msk (0x1UL << EXTI_RPR1_RPIF13_Pos) /*!< 0x00002000 */ +#define EXTI_RPR1_RPIF13 EXTI_RPR1_RPIF13_Msk /*!< Rising Pending Interrupt Flag on line 13 */ +#define EXTI_RPR1_RPIF14_Pos (14U) +#define EXTI_RPR1_RPIF14_Msk (0x1UL << EXTI_RPR1_RPIF14_Pos) /*!< 0x00004000 */ +#define EXTI_RPR1_RPIF14 EXTI_RPR1_RPIF14_Msk /*!< Rising Pending Interrupt Flag on line 14 */ +#define EXTI_RPR1_RPIF15_Pos (15U) +#define EXTI_RPR1_RPIF15_Msk (0x1UL << EXTI_RPR1_RPIF15_Pos) /*!< 0x00008000 */ +#define EXTI_RPR1_RPIF15 EXTI_RPR1_RPIF15_Msk /*!< Rising Pending Interrupt Flag on line 15 */ +#define EXTI_RPR1_RPIF18_Pos (18U) +#define EXTI_RPR1_RPIF18_Msk (0x1UL << EXTI_RPR1_RPIF18_Pos) /*!< 0x00040000 */ +#define EXTI_RPR1_RPIF18 EXTI_RPR1_RPIF18_Msk /*!< Rising Pending Interrupt Flag on line 18 */ + +/******************* Bit definition for EXTI_FPR1 register ******************/ +#define EXTI_FPR1_FPIF0_Pos (0U) +#define EXTI_FPR1_FPIF0_Msk (0x1UL << EXTI_FPR1_FPIF0_Pos) /*!< 0x00000001 */ +#define EXTI_FPR1_FPIF0 EXTI_FPR1_FPIF0_Msk /*!< Falling Pending Interrupt Flag on line 0 */ +#define EXTI_FPR1_FPIF1_Pos (1U) +#define EXTI_FPR1_FPIF1_Msk (0x1UL << EXTI_FPR1_FPIF1_Pos) /*!< 0x00000002 */ +#define EXTI_FPR1_FPIF1 EXTI_FPR1_FPIF1_Msk /*!< Falling Pending Interrupt Flag on line 1 */ +#define EXTI_FPR1_FPIF2_Pos (2U) +#define EXTI_FPR1_FPIF2_Msk (0x1UL << EXTI_FPR1_FPIF2_Pos) /*!< 0x00000004 */ +#define EXTI_FPR1_FPIF2 EXTI_FPR1_FPIF2_Msk /*!< Falling Pending Interrupt Flag on line 2 */ +#define EXTI_FPR1_FPIF3_Pos (3U) +#define EXTI_FPR1_FPIF3_Msk (0x1UL << EXTI_FPR1_FPIF3_Pos) /*!< 0x00000008 */ +#define EXTI_FPR1_FPIF3 EXTI_FPR1_FPIF3_Msk /*!< Falling Pending Interrupt Flag on line 3 */ +#define EXTI_FPR1_FPIF4_Pos (4U) +#define EXTI_FPR1_FPIF4_Msk (0x1UL << EXTI_FPR1_FPIF4_Pos) /*!< 0x00000010 */ +#define EXTI_FPR1_FPIF4 EXTI_FPR1_FPIF4_Msk /*!< Falling Pending Interrupt Flag on line 4 */ +#define EXTI_FPR1_FPIF5_Pos (5U) +#define EXTI_FPR1_FPIF5_Msk (0x1UL << EXTI_FPR1_FPIF5_Pos) /*!< 0x00000020 */ +#define EXTI_FPR1_FPIF5 EXTI_FPR1_FPIF5_Msk /*!< Falling Pending Interrupt Flag on line 5 */ +#define EXTI_FPR1_FPIF6_Pos (6U) +#define EXTI_FPR1_FPIF6_Msk (0x1UL << EXTI_FPR1_FPIF6_Pos) /*!< 0x00000040 */ +#define EXTI_FPR1_FPIF6 EXTI_FPR1_FPIF6_Msk /*!< Falling Pending Interrupt Flag on line 6 */ +#define EXTI_FPR1_FPIF7_Pos (7U) +#define EXTI_FPR1_FPIF7_Msk (0x1UL << EXTI_FPR1_FPIF7_Pos) /*!< 0x00000080 */ +#define EXTI_FPR1_FPIF7 EXTI_FPR1_FPIF7_Msk /*!< Falling Pending Interrupt Flag on line 7 */ +#define EXTI_FPR1_FPIF8_Pos (8U) +#define EXTI_FPR1_FPIF8_Msk (0x1UL << EXTI_FPR1_FPIF8_Pos) /*!< 0x00000100 */ +#define EXTI_FPR1_FPIF8 EXTI_FPR1_FPIF8_Msk /*!< Falling Pending Interrupt Flag on line 8 */ +#define EXTI_FPR1_FPIF9_Pos (9U) +#define EXTI_FPR1_FPIF9_Msk (0x1UL << EXTI_FPR1_FPIF9_Pos) /*!< 0x00000200 */ +#define EXTI_FPR1_FPIF9 EXTI_FPR1_FPIF9_Msk /*!< Falling Pending Interrupt Flag on line 9 */ +#define EXTI_FPR1_FPIF12_Pos (12U) +#define EXTI_FPR1_FPIF12_Msk (0x1UL << EXTI_FPR1_FPIF12_Pos) /*!< 0x00001000 */ +#define EXTI_FPR1_FPIF12 EXTI_FPR1_FPIF12_Msk /*!< Falling Pending Interrupt Flag on line 12 */ +#define EXTI_FPR1_FPIF13_Pos (13U) +#define EXTI_FPR1_FPIF13_Msk (0x1UL << EXTI_FPR1_FPIF13_Pos) /*!< 0x00002000 */ +#define EXTI_FPR1_FPIF13 EXTI_FPR1_FPIF13_Msk /*!< Falling Pending Interrupt Flag on line 13 */ +#define EXTI_FPR1_FPIF14_Pos (14U) +#define EXTI_FPR1_FPIF14_Msk (0x1UL << EXTI_FPR1_FPIF14_Pos) /*!< 0x00004000 */ +#define EXTI_FPR1_FPIF14 EXTI_FPR1_FPIF14_Msk /*!< Falling Pending Interrupt Flag on line 14 */ +#define EXTI_FPR1_FPIF15_Pos (15U) +#define EXTI_FPR1_FPIF15_Msk (0x1UL << EXTI_FPR1_FPIF15_Pos) /*!< 0x00008000 */ +#define EXTI_FPR1_FPIF15 EXTI_FPR1_FPIF15_Msk /*!< Falling Pending Interrupt Flag on line 15 */ +#define EXTI_FPR1_FPIF18_Pos (18U) +#define EXTI_FPR1_FPIF18_Msk (0x1UL << EXTI_FPR1_FPIF18_Pos) /*!< 0x00040000 */ +#define EXTI_FPR1_FPIF18 EXTI_FPR1_FPIF18_Msk /*!< Falling Pending Interrupt Flag on line 18 */ + +/***************** Bit definition for EXTI_EXTICR1 register **************/ +#define EXTI_EXTICR1_EXTI0_Pos (0U) +#define EXTI_EXTICR1_EXTI0_Msk (0xFFUL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x000000FF */ +#define EXTI_EXTICR1_EXTI0 EXTI_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */ +#define EXTI_EXTICR1_EXTI0_0 (0x1UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR1_EXTI0_1 (0x2UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR1_EXTI0_2 (0x4UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR1_EXTI0_3 (0x8UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000008 */ +#define EXTI_EXTICR1_EXTI0_4 (0x10UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000010 */ +#define EXTI_EXTICR1_EXTI0_5 (0x20UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000020 */ +#define EXTI_EXTICR1_EXTI0_6 (0x40UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000040 */ +#define EXTI_EXTICR1_EXTI0_7 (0x80UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000080 */ +#define EXTI_EXTICR1_EXTI1_Pos (8U) +#define EXTI_EXTICR1_EXTI1_Msk (0xFFUL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x0000FF00 */ +#define EXTI_EXTICR1_EXTI1 EXTI_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */ +#define EXTI_EXTICR1_EXTI1_0 (0x1UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR1_EXTI1_1 (0x2UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR1_EXTI1_2 (0x4UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR1_EXTI1_3 (0x8UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000800 */ +#define EXTI_EXTICR1_EXTI1_4 (0x10UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00001000 */ +#define EXTI_EXTICR1_EXTI1_5 (0x20UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00002000 */ +#define EXTI_EXTICR1_EXTI1_6 (0x40UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00004000 */ +#define EXTI_EXTICR1_EXTI1_7 (0x80UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00008000 */ +#define EXTI_EXTICR1_EXTI2_Pos (16U) +#define EXTI_EXTICR1_EXTI2_Msk (0xFFUL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00FF0000 */ +#define EXTI_EXTICR1_EXTI2 EXTI_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */ +#define EXTI_EXTICR1_EXTI2_0 (0x1UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR1_EXTI2_1 (0x2UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR1_EXTI2_2 (0x4UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR1_EXTI2_3 (0x8UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00080000 */ +#define EXTI_EXTICR1_EXTI2_4 (0x10UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00100000 */ +#define EXTI_EXTICR1_EXTI2_5 (0x20UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00200000 */ +#define EXTI_EXTICR1_EXTI2_6 (0x40UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00400000 */ +#define EXTI_EXTICR1_EXTI2_7 (0x80UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00800000 */ +#define EXTI_EXTICR1_EXTI3_Pos (24U) +#define EXTI_EXTICR1_EXTI3_Msk (0xFFUL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0xFF000000 */ +#define EXTI_EXTICR1_EXTI3 EXTI_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */ +#define EXTI_EXTICR1_EXTI3_0 (0x1UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR1_EXTI3_1 (0x2UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR1_EXTI3_2 (0x4UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x04000000 */ +#define EXTI_EXTICR1_EXTI3_3 (0x8UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x08000000 */ +#define EXTI_EXTICR1_EXTI3_4 (0x10UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x10000000 */ +#define EXTI_EXTICR1_EXTI3_5 (0x20UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x20000000 */ +#define EXTI_EXTICR1_EXTI3_6 (0x40UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x40000000 */ +#define EXTI_EXTICR1_EXTI3_7 (0x80UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for EXTI_EXTICR2 register **************/ +#define EXTI_EXTICR2_EXTI4_Pos (0U) +#define EXTI_EXTICR2_EXTI4_Msk (0xFFUL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x000000FF */ +#define EXTI_EXTICR2_EXTI4 EXTI_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */ +#define EXTI_EXTICR2_EXTI4_0 (0x1UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR2_EXTI4_1 (0x2UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR2_EXTI4_2 (0x4UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR2_EXTI4_3 (0x8UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000008 */ +#define EXTI_EXTICR2_EXTI4_4 (0x10UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000010 */ +#define EXTI_EXTICR2_EXTI4_5 (0x20UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000020 */ +#define EXTI_EXTICR2_EXTI4_6 (0x40UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000040 */ +#define EXTI_EXTICR2_EXTI4_7 (0x80UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000080 */ +#define EXTI_EXTICR2_EXTI5_Pos (8U) +#define EXTI_EXTICR2_EXTI5_Msk (0xFFUL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x0000FF00 */ +#define EXTI_EXTICR2_EXTI5 EXTI_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */ +#define EXTI_EXTICR2_EXTI5_0 (0x1UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR2_EXTI5_1 (0x2UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR2_EXTI5_2 (0x4UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR2_EXTI5_3 (0x8UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000800 */ +#define EXTI_EXTICR2_EXTI5_4 (0x10UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00001000 */ +#define EXTI_EXTICR2_EXTI5_5 (0x20UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00002000 */ +#define EXTI_EXTICR2_EXTI5_6 (0x40UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00004000 */ +#define EXTI_EXTICR2_EXTI5_7 (0x80UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00008000 */ +#define EXTI_EXTICR2_EXTI6_Pos (16U) +#define EXTI_EXTICR2_EXTI6_Msk (0xFFUL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00FF0000 */ +#define EXTI_EXTICR2_EXTI6 EXTI_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */ +#define EXTI_EXTICR2_EXTI6_0 (0x1UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR2_EXTI6_1 (0x2UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR2_EXTI6_2 (0x4UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR2_EXTI6_3 (0x8UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00080000 */ +#define EXTI_EXTICR2_EXTI6_4 (0x10UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00100000 */ +#define EXTI_EXTICR2_EXTI6_5 (0x20UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00200000 */ +#define EXTI_EXTICR2_EXTI6_6 (0x40UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00400000 */ +#define EXTI_EXTICR2_EXTI6_7 (0x80UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00800000 */ +#define EXTI_EXTICR2_EXTI7_Pos (24U) +#define EXTI_EXTICR2_EXTI7_Msk (0xFFUL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0xFF000000 */ +#define EXTI_EXTICR2_EXTI7 EXTI_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */ +#define EXTI_EXTICR2_EXTI7_0 (0x1UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR2_EXTI7_1 (0x2UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR2_EXTI7_2 (0x4UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x04000000 */ +#define EXTI_EXTICR2_EXTI7_3 (0x8UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x08000000 */ +#define EXTI_EXTICR2_EXTI7_4 (0x10UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x10000000 */ +#define EXTI_EXTICR2_EXTI7_5 (0x20UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x20000000 */ +#define EXTI_EXTICR2_EXTI7_6 (0x40UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x40000000 */ +#define EXTI_EXTICR2_EXTI7_7 (0x80UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for EXTI_EXTICR3 register **************/ +#define EXTI_EXTICR3_EXTI8_Pos (0U) +#define EXTI_EXTICR3_EXTI8_Msk (0xFFUL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x000000FF */ +#define EXTI_EXTICR3_EXTI8 EXTI_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */ +#define EXTI_EXTICR3_EXTI8_0 (0x1UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR3_EXTI8_1 (0x2UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR3_EXTI8_2 (0x4UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR3_EXTI8_3 (0x8UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000008 */ +#define EXTI_EXTICR3_EXTI8_4 (0x10UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000010 */ +#define EXTI_EXTICR3_EXTI8_5 (0x20UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000020 */ +#define EXTI_EXTICR3_EXTI8_6 (0x40UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000040 */ +#define EXTI_EXTICR3_EXTI8_7 (0x80UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000080 */ +#define EXTI_EXTICR3_EXTI9_Pos (8U) +#define EXTI_EXTICR3_EXTI9_Msk (0xFFUL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x0000FF00 */ +#define EXTI_EXTICR3_EXTI9 EXTI_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */ +#define EXTI_EXTICR3_EXTI9_0 (0x1UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR3_EXTI9_1 (0x2UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR3_EXTI9_2 (0x4UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR3_EXTI9_3 (0x8UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000800 */ +#define EXTI_EXTICR3_EXTI9_4 (0x10UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00001000 */ +#define EXTI_EXTICR3_EXTI9_5 (0x20UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00002000 */ +#define EXTI_EXTICR3_EXTI9_6 (0x40UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00004000 */ +#define EXTI_EXTICR3_EXTI9_7 (0x80UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00008000 */ + +/***************** Bit definition for EXTI_EXTICR4 register **************/ +#define EXTI_EXTICR4_EXTI12_Pos (0U) +#define EXTI_EXTICR4_EXTI12_Msk (0xFFUL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x000000FF */ +#define EXTI_EXTICR4_EXTI12 EXTI_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */ +#define EXTI_EXTICR4_EXTI12_0 (0x1UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR4_EXTI12_1 (0x2UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR4_EXTI12_2 (0x4UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR4_EXTI12_3 (0x8UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000008 */ +#define EXTI_EXTICR4_EXTI12_4 (0x10UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000010 */ +#define EXTI_EXTICR4_EXTI12_5 (0x20UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000020 */ +#define EXTI_EXTICR4_EXTI12_6 (0x40UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000040 */ +#define EXTI_EXTICR4_EXTI12_7 (0x80UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000080 */ +#define EXTI_EXTICR4_EXTI13_Pos (8U) +#define EXTI_EXTICR4_EXTI13_Msk (0xFFUL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x0000FF00 */ +#define EXTI_EXTICR4_EXTI13 EXTI_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */ +#define EXTI_EXTICR4_EXTI13_0 (0x1UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR4_EXTI13_1 (0x2UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR4_EXTI13_2 (0x4UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR4_EXTI13_3 (0x8UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000800 */ +#define EXTI_EXTICR4_EXTI13_4 (0x10UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00001000 */ +#define EXTI_EXTICR4_EXTI13_5 (0x20UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00002000 */ +#define EXTI_EXTICR4_EXTI13_6 (0x40UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00004000 */ +#define EXTI_EXTICR4_EXTI13_7 (0x80UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00008000 */ +#define EXTI_EXTICR4_EXTI14_Pos (16U) +#define EXTI_EXTICR4_EXTI14_Msk (0xFFUL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00FF0000 */ +#define EXTI_EXTICR4_EXTI14 EXTI_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */ +#define EXTI_EXTICR4_EXTI14_0 (0x1UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR4_EXTI14_1 (0x2UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR4_EXTI14_2 (0x4UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR4_EXTI14_3 (0x8UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00080000 */ +#define EXTI_EXTICR4_EXTI14_4 (0x10UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00100000 */ +#define EXTI_EXTICR4_EXTI14_5 (0x20UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00200000 */ +#define EXTI_EXTICR4_EXTI14_6 (0x40UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00400000 */ +#define EXTI_EXTICR4_EXTI14_7 (0x80UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00800000 */ +#define EXTI_EXTICR4_EXTI15_Pos (24U) +#define EXTI_EXTICR4_EXTI15_Msk (0xFFUL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0xFF000000 */ +#define EXTI_EXTICR4_EXTI15 EXTI_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */ +#define EXTI_EXTICR4_EXTI15_0 (0x1UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR4_EXTI15_1 (0x2UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR4_EXTI15_2 (0x4UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x04000000 */ +#define EXTI_EXTICR4_EXTI15_3 (0x8UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x08000000 */ +#define EXTI_EXTICR4_EXTI15_4 (0x10UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x10000000 */ +#define EXTI_EXTICR4_EXTI15_5 (0x20UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x20000000 */ +#define EXTI_EXTICR4_EXTI15_6 (0x40UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x40000000 */ +#define EXTI_EXTICR4_EXTI15_7 (0x80UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x80000000 */ + +/******************* Bit definition for EXTI_IMR1 register ******************/ +#define EXTI_IMR1_IM0_Pos (0U) +#define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */ +#define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< Interrupt Mask on line 0 */ +#define EXTI_IMR1_IM1_Pos (1U) +#define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */ +#define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< Interrupt Mask on line 1 */ +#define EXTI_IMR1_IM2_Pos (2U) +#define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */ +#define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< Interrupt Mask on line 2 */ +#define EXTI_IMR1_IM3_Pos (3U) +#define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */ +#define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< Interrupt Mask on line 3 */ +#define EXTI_IMR1_IM4_Pos (4U) +#define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */ +#define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< Interrupt Mask on line 4 */ +#define EXTI_IMR1_IM5_Pos (5U) +#define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */ +#define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< Interrupt Mask on line 5 */ +#define EXTI_IMR1_IM6_Pos (6U) +#define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */ +#define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< Interrupt Mask on line 6 */ +#define EXTI_IMR1_IM7_Pos (7U) +#define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */ +#define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< Interrupt Mask on line 7 */ +#define EXTI_IMR1_IM8_Pos (8U) +#define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */ +#define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< Interrupt Mask on line 8 */ +#define EXTI_IMR1_IM9_Pos (9U) +#define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */ +#define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< Interrupt Mask on line 9 */ +#define EXTI_IMR1_IM12_Pos (12U) +#define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */ +#define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< Interrupt Mask on line 12 */ +#define EXTI_IMR1_IM13_Pos (13U) +#define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */ +#define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< Interrupt Mask on line 13 */ +#define EXTI_IMR1_IM14_Pos (14U) +#define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */ +#define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< Interrupt Mask on line 14 */ +#define EXTI_IMR1_IM15_Pos (15U) +#define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */ +#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< Interrupt Mask on line 15 */ +#define EXTI_IMR1_IM18_Pos (18U) +#define EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */ +#define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< Interrupt Mask on line 18 */ + +/******************* Bit definition for EXTI_EMR1 register ******************/ +#define EXTI_EMR1_EM0_Pos (0U) +#define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */ +#define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< Event Mask on line 0 */ +#define EXTI_EMR1_EM1_Pos (1U) +#define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */ +#define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< Event Mask on line 1 */ +#define EXTI_EMR1_EM2_Pos (2U) +#define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */ +#define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< Event Mask on line 2 */ +#define EXTI_EMR1_EM3_Pos (3U) +#define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */ +#define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< Event Mask on line 3 */ +#define EXTI_EMR1_EM4_Pos (4U) +#define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */ +#define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< Event Mask on line 4 */ +#define EXTI_EMR1_EM5_Pos (5U) +#define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */ +#define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< Event Mask on line 5 */ +#define EXTI_EMR1_EM6_Pos (6U) +#define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */ +#define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< Event Mask on line 6 */ +#define EXTI_EMR1_EM7_Pos (7U) +#define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */ +#define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< Event Mask on line 7 */ +#define EXTI_EMR1_EM8_Pos (8U) +#define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */ +#define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< Event Mask on line 8 */ +#define EXTI_EMR1_EM9_Pos (9U) +#define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */ +#define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< Event Mask on line 9 */ +#define EXTI_EMR1_EM12_Pos (12U) +#define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */ +#define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< Event Mask on line 12 */ +#define EXTI_EMR1_EM13_Pos (13U) +#define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */ +#define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< Event Mask on line 13 */ +#define EXTI_EMR1_EM14_Pos (14U) +#define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */ +#define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< Event Mask on line 14 */ +#define EXTI_EMR1_EM15_Pos (15U) +#define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */ +#define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< Event Mask on line 15 */ +#define EXTI_EMR1_EM18_Pos (18U) +#define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */ +#define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< Event Mask on line 18 */ + + +/******************************************************************************/ +/* */ +/* FLASH */ +/* */ +/******************************************************************************/ +#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_0 /* FLASH Latency 1 Wait State */ + +/******************* Bits definition for FLASH_ACR register *****************/ +#define FLASH_ACR_LATENCY_Pos (0U) +#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */ +#define FLASH_ACR_LATENCY_0 (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */ +#define FLASH_ACR_LATENCY_1 (0x2UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */ +#define FLASH_ACR_LATENCY_2 (0x4UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000004 */ +#define FLASH_ACR_LATENCY_3 (0x8UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000008 */ +#define FLASH_ACR_PRFTEN_Pos (8U) +#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ +#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch enable */ +#define FLASH_ACR_LPM_Pos (11U) +#define FLASH_ACR_LPM_Msk (0x1UL << FLASH_ACR_LPM_Pos) /*!< 0x00000800 */ +#define FLASH_ACR_LPM FLASH_ACR_LPM_Msk /*!< Low-Power read mode */ +#define FLASH_ACR_PDREQ_Pos (12U) +#define FLASH_ACR_PDREQ_Msk (0x1UL << FLASH_ACR_PDREQ_Pos) /*!< 0x00001000 */ +#define FLASH_ACR_PDREQ FLASH_ACR_PDREQ_Msk /*!< Flash power-down mode request */ +#define FLASH_ACR_SLEEP_PD_Pos (14U) +#define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00004000 */ +#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash power-down mode during sleep */ + +/****************** Bits definition for FLASH_NSKEYR register *****************/ +#define FLASH_NSKEYR_NSKEY_Pos (0U) +#define FLASH_NSKEYR_NSKEY_Msk (0xFFFFFFFFUL << FLASH_NSKEYR_NSKEY_Pos) /*!< 0xFFFFFFFFF */ +#define FLASH_NSKEYR_NSKEY FLASH_NSKEYR_NSKEY_Msk /*!< Flash memory non-secure key */ + + +/****************** Bits definition for FLASH_OPTKEYR register *****************/ +#define FLASH_OPTKEYR_OPTKEY_Pos (0U) +#define FLASH_OPTKEYR_OPTKEY_Msk (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEY_Pos) /*!< 0xFFFFFFFFF */ +#define FLASH_OPTKEYR_OPTKEY FLASH_OPTKEYR_OPTKEY_Msk /*!< Option byte key */ + +/****************** Bits definition for FLASH_PDKEYR register *****************/ +#define FLASH_PDKEYR_PDKEY_Pos (0U) +#define FLASH_PDKEYR_PDKEY_Msk (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEY_Pos) /*!< 0xFFFFFFFFF */ +#define FLASH_PDKEYR_PDKEY FLASH_PDKEYR_PDKEY_Msk /*!< Flash power-down key */ + +/****************** Bits definition for FLASH_NSSR register *****************/ +#define FLASH_NSSR_EOP_Pos (0U) +#define FLASH_NSSR_EOP_Msk (0x1UL << FLASH_NSSR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_NSSR_EOP FLASH_NSSR_EOP_Msk /*!< Non-secure end of operation */ +#define FLASH_NSSR_OPERR_Pos (1U) +#define FLASH_NSSR_OPERR_Msk (0x1UL << FLASH_NSSR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_NSSR_OPERR FLASH_NSSR_OPERR_Msk /*!< Non-secure operation error */ +#define FLASH_NSSR_PROGERR_Pos (3U) +#define FLASH_NSSR_PROGERR_Msk (0x1UL << FLASH_NSSR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_NSSR_PROGERR FLASH_NSSR_PROGERR_Msk /*!< Non-secure programming error */ +#define FLASH_NSSR_WRPERR_Pos (4U) +#define FLASH_NSSR_WRPERR_Msk (0x1UL << FLASH_NSSR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_NSSR_WRPERR FLASH_NSSR_WRPERR_Msk /*!< Non-secure write protection error */ +#define FLASH_NSSR_PGAERR_Pos (5U) +#define FLASH_NSSR_PGAERR_Msk (0x1UL << FLASH_NSSR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_NSSR_PGAERR FLASH_NSSR_PGAERR_Msk /*!< Non-secure programming alignment error */ +#define FLASH_NSSR_SIZERR_Pos (6U) +#define FLASH_NSSR_SIZERR_Msk (0x1UL << FLASH_NSSR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_NSSR_SIZERR FLASH_NSSR_SIZERR_Msk /*!< Non-secure size error */ +#define FLASH_NSSR_PGSERR_Pos (7U) +#define FLASH_NSSR_PGSERR_Msk (0x1UL << FLASH_NSSR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_NSSR_PGSERR FLASH_NSSR_PGSERR_Msk /*!< Non-secure programming sequence error */ +#define FLASH_NSSR_OPTWERR_Pos (13U) +#define FLASH_NSSR_OPTWERR_Msk (0x1UL << FLASH_NSSR_OPTWERR_Pos) /*!< 0x00002000 */ +#define FLASH_NSSR_OPTWERR FLASH_NSSR_OPTWERR_Msk /*!< Option write error */ +#define FLASH_NSSR_BSY_Pos (16U) +#define FLASH_NSSR_BSY_Msk (0x1UL << FLASH_NSSR_BSY_Pos) /*!< 0x00010000 */ +#define FLASH_NSSR_BSY FLASH_NSSR_BSY_Msk /*!< Non-secure busy */ +#define FLASH_NSSR_WDW_Pos (17U) +#define FLASH_NSSR_WDW_Msk (0x1UL << FLASH_NSSR_WDW_Pos) /*!< 0x00020000 */ +#define FLASH_NSSR_WDW FLASH_NSSR_WDW_Msk /*!< Non-secure wait data to write */ +#define FLASH_NSSR_OEM1LOCK_Pos (18U) +#define FLASH_NSSR_OEM1LOCK_Msk (0x1UL << FLASH_NSSR_OEM1LOCK_Pos) /*!< 0x00040000 */ +#define FLASH_NSSR_OEM1LOCK FLASH_NSSR_OEM1LOCK_Msk /*!< OEM1 lock */ +#define FLASH_NSSR_OEM2LOCK_Pos (19U) +#define FLASH_NSSR_OEM2LOCK_Msk (0x1UL << FLASH_NSSR_OEM2LOCK_Pos) /*!< 0x00080000 */ +#define FLASH_NSSR_OEM2LOCK FLASH_NSSR_OEM2LOCK_Msk /*!< OEM2 lock */ +#define FLASH_NSSR_PD_Pos (20U) +#define FLASH_NSSR_PD_Msk (0x1UL << FLASH_NSSR_PD_Pos) /*!< 0x00100000 */ +#define FLASH_NSSR_PD FLASH_NSSR_PD_Msk /*!< Flash in power-down mode */ + + +/****************** Bits definition for FLASH_NSCR1 register *****************/ +#define FLASH_NSCR1_PG_Pos (0U) +#define FLASH_NSCR1_PG_Msk (0x1UL << FLASH_NSCR1_PG_Pos) /*!< 0x00000001 */ +#define FLASH_NSCR1_PG FLASH_NSCR1_PG_Msk /*!< Non-secure Programming */ +#define FLASH_NSCR1_PER_Pos (1U) +#define FLASH_NSCR1_PER_Msk (0x1UL << FLASH_NSCR1_PER_Pos) /*!< 0x00000002 */ +#define FLASH_NSCR1_PER FLASH_NSCR1_PER_Msk /*!< Non-secure Page Erase */ +#define FLASH_NSCR1_MER_Pos (2U) +#define FLASH_NSCR1_MER_Msk (0x1UL << FLASH_NSCR1_MER_Pos) /*!< 0x00000004 */ +#define FLASH_NSCR1_MER FLASH_NSCR1_MER_Msk /*!< Non-secure Mass Erase */ +#define FLASH_NSCR1_PNB_Pos (3U) +#define FLASH_NSCR1_PNB_Msk (0x3FUL << FLASH_NSCR1_PNB_Pos) /*!< 0x000001F8 */ +#define FLASH_NSCR1_PNB FLASH_NSCR1_PNB_Msk /*!< Non-secure Page Number selection */ +#define FLASH_NSCR1_BWR_Pos (14U) +#define FLASH_NSCR1_BWR_Msk (0x1UL << FLASH_NSCR1_BWR_Pos) /*!< 0x00004000 */ +#define FLASH_NSCR1_BWR FLASH_NSCR1_BWR_Msk /*!< Non-secure Burst Write Programming mode */ +#define FLASH_NSCR1_STRT_Pos (16U) +#define FLASH_NSCR1_STRT_Msk (0x1UL << FLASH_NSCR1_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_NSCR1_STRT FLASH_NSCR1_STRT_Msk /*!< Non-secure Start */ +#define FLASH_NSCR1_OPTSTRT_Pos (17U) +#define FLASH_NSCR1_OPTSTRT_Msk (0x1UL << FLASH_NSCR1_OPTSTRT_Pos) /*!< 0x00020000 */ +#define FLASH_NSCR1_OPTSTRT FLASH_NSCR1_OPTSTRT_Msk /*!< Option Modification Start */ +#define FLASH_NSCR1_EOPIE_Pos (24U) +#define FLASH_NSCR1_EOPIE_Msk (0x1UL << FLASH_NSCR1_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_NSCR1_EOPIE FLASH_NSCR1_EOPIE_Msk /*!< Non-secure End of operation interrupt enable */ +#define FLASH_NSCR1_ERRIE_Pos (25U) +#define FLASH_NSCR1_ERRIE_Msk (0x1UL << FLASH_NSCR1_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_NSCR1_ERRIE FLASH_NSCR1_ERRIE_Msk /*!< Non-secure error interrupt enable */ +#define FLASH_NSCR1_OBL_LAUNCH_Pos (27U) +#define FLASH_NSCR1_OBL_LAUNCH_Msk (0x1UL << FLASH_NSCR1_OBL_LAUNCH_Pos) /*!< 0x08000000 */ +#define FLASH_NSCR1_OBL_LAUNCH FLASH_NSCR1_OBL_LAUNCH_Msk /*!< Force the option byte loading */ +#define FLASH_NSCR1_OPTLOCK_Pos (30U) +#define FLASH_NSCR1_OPTLOCK_Msk (0x1UL << FLASH_NSCR1_OPTLOCK_Pos) /*!< 0x40000000 */ +#define FLASH_NSCR1_OPTLOCK FLASH_NSCR1_OPTLOCK_Msk /*!< Option Lock */ +#define FLASH_NSCR1_LOCK_Pos (31U) +#define FLASH_NSCR1_LOCK_Msk (0x1UL << FLASH_NSCR1_LOCK_Pos) /*!< 0x80000000 */ +#define FLASH_NSCR1_LOCK FLASH_NSCR1_LOCK_Msk /*!< Non-secure Lock */ + + +/******************* Bits definition for FLASH_ECCR register ***************/ +#define FLASH_ECCR_ADDR_ECC_Pos (0U) +#define FLASH_ECCR_ADDR_ECC_Msk (0x7FFFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x0007FFFF */ +#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk /*!< ECC fail address */ +#define FLASH_ECCR_SYSF_ECC_Pos (22U) +#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk /*!< System Flash ECC fail */ +#define FLASH_ECCR_ECCIE_Pos (24U) +#define FLASH_ECCR_ECCIE_Msk (0x1UL << FLASH_ECCR_ECCIE_Pos) /*!< 0x01000000 */ +#define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk /*!< ECC correction interrupt enable */ +#define FLASH_ECCR_ECCC_Pos (30U) +#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */ +#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk /*!< ECC correction */ +#define FLASH_ECCR_ECCD_Pos (31U) +#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */ +#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk /*!< ECC detection */ + +/******************* Bits definition for FLASH_OPSR register ***************/ +#define FLASH_OPSR_ADDR_OP_Pos (0U) +#define FLASH_OPSR_ADDR_OP_Msk (0x7FFFFUL << FLASH_OPSR_ADDR_OP_Pos) /*!< 0x0007FFFF */ +#define FLASH_OPSR_ADDR_OP FLASH_OPSR_ADDR_OP_Msk /*!< Interrupted operation address */ +#define FLASH_OPSR_SYSF_OP_Pos (22U) +#define FLASH_OPSR_SYSF_OP_Msk (0x1UL << FLASH_OPSR_SYSF_OP_Pos) /*!< 0x00400000 */ +#define FLASH_OPSR_SYSF_OP FLASH_OPSR_SYSF_OP_Msk /*!< Operation in system Flash memory interrupted */ +#define FLASH_OPSR_CODE_OP_Pos (29U) +#define FLASH_OPSR_CODE_OP_Msk (0x7UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x07000000 */ +#define FLASH_OPSR_CODE_OP FLASH_OPSR_CODE_OP_Msk /*!< Flash memory operation code */ +#define FLASH_OPSR_CODE_OP_0 (0x1UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x01000000 */ +#define FLASH_OPSR_CODE_OP_1 (0x2UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x02000000 */ +#define FLASH_OPSR_CODE_OP_2 (0x4UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x04000000 */ + +/******************* Bits definition for FLASH_NSCR2 register ***************/ +#define FLASH_NSCR2_PS_Pos (0U) +#define FLASH_NSCR2_PS_Msk (0x1UL << FLASH_NSCR2_PS_Pos) /*!< 0x00000001 */ +#define FLASH_NSCR2_PS FLASH_NSCR2_PS_Msk /*!< Program suspend request */ +#define FLASH_NSCR2_ES_Pos (1U) +#define FLASH_NSCR2_ES_Msk (0x1UL << FLASH_NSCR2_ES_Pos) /*!< 0x00000002 */ +#define FLASH_NSCR2_ES FLASH_NSCR2_ES_Msk /*!< Erase suspend request */ + +/******************* Bits definition for FLASH_OPTR register ***************/ +#define FLASH_OPTR_RDP_Pos (0U) +#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */ +#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk /*!< Readout protection level */ +#define FLASH_OPTR_BOR_LEV_Pos (8U) +#define FLASH_OPTR_BOR_LEV_Msk (0x7UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000700 */ +#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR reset Level */ +#define FLASH_OPTR_BOR_LEV_0 (0x1UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000100 */ +#define FLASH_OPTR_BOR_LEV_1 (0x2UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000200 */ +#define FLASH_OPTR_BOR_LEV_2 (0x4UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000400 */ +#define FLASH_OPTR_nRST_STOP_Pos (12U) +#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00001000 */ +#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< nRST_STOP */ +#define FLASH_OPTR_nRST_STDBY_Pos (13U) +#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */ +#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< nRST_STDBY */ +#define FLASH_OPTR_SRAM1_RST_Pos (15U) +#define FLASH_OPTR_SRAM1_RST_Msk (0x1UL << FLASH_OPTR_SRAM1_RST_Pos) /*!< 0x00008000 */ +#define FLASH_OPTR_SRAM1_RST FLASH_OPTR_SRAM1_RST_Msk /*!< SRAM1 erase upon system reset */ +#define FLASH_OPTR_IWDG_SW_Pos (16U) +#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */ +#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< Independent watchdog selection */ +#define FLASH_OPTR_IWDG_STOP_Pos (17U) +#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */ +#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk /*!< Independent watchdog counter freeze in Stop mode */ +#define FLASH_OPTR_IWDG_STDBY_Pos (18U) +#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */ +#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk /*!< Independent watchdog counter freeze in Standby mode */ +#define FLASH_OPTR_WWDG_SW_Pos (19U) +#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */ +#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk /*!< Window watchdog selection */ +#define FLASH_OPTR_SRAM2_PE_Pos (24U) +#define FLASH_OPTR_SRAM2_PE_Msk (0x1UL << FLASH_OPTR_SRAM2_PE_Pos) /*!< 0x01000000 */ +#define FLASH_OPTR_SRAM2_PE FLASH_OPTR_SRAM2_PE_Msk /*!< SRAM2 ECC detection and correction enable*/ +#define FLASH_OPTR_SRAM2_RST_Pos (25U) +#define FLASH_OPTR_SRAM2_RST_Msk (0x1UL << FLASH_OPTR_SRAM2_RST_Pos) /*!< 0x02000000 */ +#define FLASH_OPTR_SRAM2_RST FLASH_OPTR_SRAM2_RST_Msk /*!< SRAM2 erase when system reset */ +#define FLASH_OPTR_nSWBOOT0_Pos (26U) +#define FLASH_OPTR_nSWBOOT0_Msk (0x1UL << FLASH_OPTR_nSWBOOT0_Pos) /*!< 0x04000000 */ +#define FLASH_OPTR_nSWBOOT0 FLASH_OPTR_nSWBOOT0_Msk /*!< Software BOOT0 */ +#define FLASH_OPTR_nBOOT0_Pos (27U) +#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x08000000 */ +#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk /*!< nBOOT0 option bit */ + +/**************** Bits definition for FLASH_NSBOOTADD0R register ************/ +#define FLASH_NSBOOTADD0R_NSBOOTADD0_Pos (7U) +#define FLASH_NSBOOTADD0R_NSBOOTADD0_Msk (0x1FFFFFFUL << FLASH_NSBOOTADD0R_NSBOOTADD0_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_NSBOOTADD0R_NSBOOTADD0 FLASH_NSBOOTADD0R_NSBOOTADD0_Msk /*!< Non-secure boot address 0 */ + +/**************** Bits definition for FLASH_NSBOOTADD1R register ************/ +#define FLASH_NSBOOTADD1R_NSBOOTADD1_Pos (7U) +#define FLASH_NSBOOTADD1R_NSBOOTADD1_Msk (0x1FFFFFFUL << FLASH_NSBOOTADD1R_NSBOOTADD1_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_NSBOOTADD1R_NSBOOTADD1 FLASH_NSBOOTADD1R_NSBOOTADD1_Msk /*!< Non-secure boot address 1 */ + +/****************** Bits definition for FLASH_WRPAR register ***************/ +#define FLASH_WRPAR_WRPA_PSTRT_Pos (0U) +#define FLASH_WRPAR_WRPA_PSTRT_Msk (0x3FUL << FLASH_WRPAR_WRPA_PSTRT_Pos) /*!< 0x0000003F */ +#define FLASH_WRPAR_WRPA_PSTRT FLASH_WRPAR_WRPA_PSTRT_Msk /*!< WPR first area A start page */ +#define FLASH_WRPAR_WRPA_PEND_Pos (16U) +#define FLASH_WRPAR_WRPA_PEND_Msk (0x3FUL << FLASH_WRPAR_WRPA_PEND_Pos) /*!< 0x003F0000 */ +#define FLASH_WRPAR_WRPA_PEND FLASH_WRPAR_WRPA_PEND_Msk /*!< WPR first area A end page */ +#define FLASH_WRPAR_UNLOCK_Pos (31U) +#define FLASH_WRPAR_UNLOCK_Msk (0x1UL << FLASH_WRPAR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRPAR_UNLOCK FLASH_WRPAR_UNLOCK_Msk /*!< WPR first area A unlock */ + +/****************** Bits definition for FLASH_WRPBR register ***************/ +#define FLASH_WRPBR_WRPB_PSTRT_Pos (0U) +#define FLASH_WRPBR_WRPB_PSTRT_Msk (0x3FUL << FLASH_WRPBR_WRPB_PSTRT_Pos) /*!< 0x0000003F */ +#define FLASH_WRPBR_WRPB_PSTRT FLASH_WRPBR_WRPB_PSTRT_Msk /*!< WPR second area B start page */ +#define FLASH_WRPBR_WRPB_PEND_Pos (16U) +#define FLASH_WRPBR_WRPB_PEND_Msk (0x3FUL << FLASH_WRPBR_WRPB_PEND_Pos) /*!< 0x003F0000 */ +#define FLASH_WRPBR_WRPB_PEND FLASH_WRPBR_WRPB_PEND_Msk /*!< WPR second area B end page */ +#define FLASH_WRPBR_UNLOCK_Pos (31U) +#define FLASH_WRPBR_UNLOCK_Msk (0x1UL << FLASH_WRPBR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRPBR_UNLOCK FLASH_WRPBR_UNLOCK_Msk /*!< WPR first area B unlock */ + +/****************** Bits definition for FLASH_OEM1KEYR1 register *****************/ +#define FLASH_OEM1KEYR1_OEM1KEY_Pos (0U) +#define FLASH_OEM1KEYR1_OEM1KEY_Msk (0xFFFFFFFFUL << FLASH_OEM1KEYR1_OEM1KEY_Pos) /*!< 0xFFFFFFFFF */ +#define FLASH_OEM1KEYR1_OEM1KEY FLASH_OEM1KEYR1_OEM1KEY_Msk /*!< OEM1 least significant bytes key */ + +/****************** Bits definition for FLASH_OEM1KEYR2 register *****************/ +#define FLASH_OEM1KEYR2_OEM1KEY_Pos (0U) +#define FLASH_OEM1KEYR2_OEM1KEY_Msk (0xFFFFFFFFUL << FLASH_OEM1KEYR2_OEM1KEY_Pos) /*!< 0xFFFFFFFFF */ +#define FLASH_OEM1KEYR2_OEM1KEY FLASH_OEM1KEYR2_OEM1KEY_Msk /*!< OEM1 most significant bytes key */ + +/****************** Bits definition for FLASH_OEM2KEYR1 register *****************/ +#define FLASH_OEM2KEYR1_OEM2KEY_Pos (0U) +#define FLASH_OEM2KEYR1_OEM2KEY_Msk (0xFFFFFFFFUL << FLASH_OEM2KEYR1_OEM2KEY_Pos) /*!< 0xFFFFFFFFF */ +#define FLASH_OEM2KEYR1_OEM2KEY FLASH_OEM2KEYR1_OEM2KEY_Msk /*!< OEM2 least significant bytes key */ + +/****************** Bits definition for FLASH_OEM2KEYR2 register *****************/ +#define FLASH_OEM2KEYR2_OEM2KEY_Pos (0U) +#define FLASH_OEM2KEYR2_OEM2KEY_Msk (0xFFFFFFFFUL << FLASH_OEM2KEYR2_OEM2KEY_Pos) /*!< 0xFFFFFFFFF */ +#define FLASH_OEM2KEYR2_OEM2KEY FLASH_OEM2KEYR2_OEM2KEY_Msk /*!< OEM2 most significant bytes key */ + +/******************************************************************************/ +/* */ +/* General Purpose IOs (GPIO) */ +/* */ +/******************************************************************************/ +/****************** Bits definition for GPIO_MODER register *****************/ +#define GPIO_MODER_MODE0_Pos (0U) +#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ +#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk +#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ +#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ +#define GPIO_MODER_MODE1_Pos (2U) +#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ +#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk +#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ +#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ +#define GPIO_MODER_MODE2_Pos (4U) +#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ +#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk +#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ +#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ +#define GPIO_MODER_MODE3_Pos (6U) +#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ +#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk +#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ +#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ +#define GPIO_MODER_MODE4_Pos (8U) +#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ +#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk +#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ +#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ +#define GPIO_MODER_MODE5_Pos (10U) +#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ +#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk +#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ +#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ +#define GPIO_MODER_MODE6_Pos (12U) +#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ +#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk +#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ +#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ +#define GPIO_MODER_MODE7_Pos (14U) +#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ +#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk +#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ +#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ +#define GPIO_MODER_MODE8_Pos (16U) +#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ +#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk +#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ +#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ +#define GPIO_MODER_MODE9_Pos (18U) +#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ +#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk +#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ +#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ +#define GPIO_MODER_MODE10_Pos (20U) +#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ +#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk +#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ +#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ +#define GPIO_MODER_MODE11_Pos (22U) +#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ +#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk +#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ +#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ +#define GPIO_MODER_MODE12_Pos (24U) +#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ +#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk +#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ +#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ +#define GPIO_MODER_MODE13_Pos (26U) +#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ +#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk +#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ +#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ +#define GPIO_MODER_MODE14_Pos (28U) +#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ +#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk +#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ +#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ +#define GPIO_MODER_MODE15_Pos (30U) +#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ +#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk +#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ +#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_OTYPER register ****************/ +#define GPIO_OTYPER_OT0_Pos (0U) +#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */ +#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk +#define GPIO_OTYPER_OT1_Pos (1U) +#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */ +#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk +#define GPIO_OTYPER_OT2_Pos (2U) +#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */ +#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk +#define GPIO_OTYPER_OT3_Pos (3U) +#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */ +#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk +#define GPIO_OTYPER_OT4_Pos (4U) +#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */ +#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk +#define GPIO_OTYPER_OT5_Pos (5U) +#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */ +#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk +#define GPIO_OTYPER_OT6_Pos (6U) +#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */ +#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk +#define GPIO_OTYPER_OT7_Pos (7U) +#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */ +#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk +#define GPIO_OTYPER_OT8_Pos (8U) +#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */ +#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk +#define GPIO_OTYPER_OT9_Pos (9U) +#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */ +#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk +#define GPIO_OTYPER_OT10_Pos (10U) +#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */ +#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk +#define GPIO_OTYPER_OT11_Pos (11U) +#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */ +#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk +#define GPIO_OTYPER_OT12_Pos (12U) +#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */ +#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk +#define GPIO_OTYPER_OT13_Pos (13U) +#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */ +#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk +#define GPIO_OTYPER_OT14_Pos (14U) +#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */ +#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk +#define GPIO_OTYPER_OT15_Pos (15U) +#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */ +#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk + +/****************** Bits definition for GPIO_OSPEEDR register ***************/ +#define GPIO_OSPEEDR_OSPEED0_Pos (0U) +#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */ +#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk +#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */ +#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */ +#define GPIO_OSPEEDR_OSPEED1_Pos (2U) +#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */ +#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk +#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */ +#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */ +#define GPIO_OSPEEDR_OSPEED2_Pos (4U) +#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */ +#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk +#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */ +#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */ +#define GPIO_OSPEEDR_OSPEED3_Pos (6U) +#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */ +#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk +#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */ +#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */ +#define GPIO_OSPEEDR_OSPEED4_Pos (8U) +#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */ +#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk +#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */ +#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */ +#define GPIO_OSPEEDR_OSPEED5_Pos (10U) +#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */ +#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk +#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */ +#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */ +#define GPIO_OSPEEDR_OSPEED6_Pos (12U) +#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */ +#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk +#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */ +#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */ +#define GPIO_OSPEEDR_OSPEED7_Pos (14U) +#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */ +#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk +#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */ +#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */ +#define GPIO_OSPEEDR_OSPEED8_Pos (16U) +#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */ +#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk +#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */ +#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */ +#define GPIO_OSPEEDR_OSPEED9_Pos (18U) +#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */ +#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk +#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */ +#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */ +#define GPIO_OSPEEDR_OSPEED10_Pos (20U) +#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */ +#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk +#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */ +#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */ +#define GPIO_OSPEEDR_OSPEED11_Pos (22U) +#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */ +#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk +#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */ +#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */ +#define GPIO_OSPEEDR_OSPEED12_Pos (24U) +#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */ +#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk +#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */ +#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */ +#define GPIO_OSPEEDR_OSPEED13_Pos (26U) +#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */ +#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk +#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */ +#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */ +#define GPIO_OSPEEDR_OSPEED14_Pos (28U) +#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */ +#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk +#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */ +#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */ +#define GPIO_OSPEEDR_OSPEED15_Pos (30U) +#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */ +#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk +#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */ +#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_PUPDR register *****************/ +#define GPIO_PUPDR_PUPD0_Pos (0U) +#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */ +#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk +#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */ +#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */ +#define GPIO_PUPDR_PUPD1_Pos (2U) +#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */ +#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk +#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */ +#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */ +#define GPIO_PUPDR_PUPD2_Pos (4U) +#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */ +#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk +#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */ +#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */ +#define GPIO_PUPDR_PUPD3_Pos (6U) +#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */ +#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk +#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */ +#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */ +#define GPIO_PUPDR_PUPD4_Pos (8U) +#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */ +#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk +#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */ +#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */ +#define GPIO_PUPDR_PUPD5_Pos (10U) +#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */ +#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk +#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */ +#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */ +#define GPIO_PUPDR_PUPD6_Pos (12U) +#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */ +#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk +#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */ +#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */ +#define GPIO_PUPDR_PUPD7_Pos (14U) +#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */ +#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk +#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */ +#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */ +#define GPIO_PUPDR_PUPD8_Pos (16U) +#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */ +#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk +#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */ +#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */ +#define GPIO_PUPDR_PUPD9_Pos (18U) +#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */ +#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk +#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */ +#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */ +#define GPIO_PUPDR_PUPD10_Pos (20U) +#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */ +#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk +#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */ +#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */ +#define GPIO_PUPDR_PUPD11_Pos (22U) +#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */ +#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk +#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */ +#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */ +#define GPIO_PUPDR_PUPD12_Pos (24U) +#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */ +#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk +#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */ +#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */ +#define GPIO_PUPDR_PUPD13_Pos (26U) +#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */ +#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk +#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */ +#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */ +#define GPIO_PUPDR_PUPD14_Pos (28U) +#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */ +#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk +#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */ +#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */ +#define GPIO_PUPDR_PUPD15_Pos (30U) +#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */ +#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk +#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */ +#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_IDR register *******************/ +#define GPIO_IDR_ID0_Pos (0U) +#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk +#define GPIO_IDR_ID1_Pos (1U) +#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk +#define GPIO_IDR_ID2_Pos (2U) +#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk +#define GPIO_IDR_ID3_Pos (3U) +#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk +#define GPIO_IDR_ID4_Pos (4U) +#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk +#define GPIO_IDR_ID5_Pos (5U) +#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk +#define GPIO_IDR_ID6_Pos (6U) +#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk +#define GPIO_IDR_ID7_Pos (7U) +#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk +#define GPIO_IDR_ID8_Pos (8U) +#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk +#define GPIO_IDR_ID9_Pos (9U) +#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk +#define GPIO_IDR_ID10_Pos (10U) +#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk +#define GPIO_IDR_ID11_Pos (11U) +#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk +#define GPIO_IDR_ID12_Pos (12U) +#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk +#define GPIO_IDR_ID13_Pos (13U) +#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk +#define GPIO_IDR_ID14_Pos (14U) +#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk +#define GPIO_IDR_ID15_Pos (15U) +#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk + +/****************** Bits definition for GPIO_ODR register *******************/ +#define GPIO_ODR_OD0_Pos (0U) +#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk +#define GPIO_ODR_OD1_Pos (1U) +#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk +#define GPIO_ODR_OD2_Pos (2U) +#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk +#define GPIO_ODR_OD3_Pos (3U) +#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk +#define GPIO_ODR_OD4_Pos (4U) +#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk +#define GPIO_ODR_OD5_Pos (5U) +#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk +#define GPIO_ODR_OD6_Pos (6U) +#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk +#define GPIO_ODR_OD7_Pos (7U) +#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk +#define GPIO_ODR_OD8_Pos (8U) +#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk +#define GPIO_ODR_OD9_Pos (9U) +#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk +#define GPIO_ODR_OD10_Pos (10U) +#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk +#define GPIO_ODR_OD11_Pos (11U) +#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk +#define GPIO_ODR_OD12_Pos (12U) +#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk +#define GPIO_ODR_OD13_Pos (13U) +#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk +#define GPIO_ODR_OD14_Pos (14U) +#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk +#define GPIO_ODR_OD15_Pos (15U) +#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk + +/****************** Bits definition for GPIO_BSRR register ******************/ +#define GPIO_BSRR_BS0_Pos (0U) +#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ +#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk +#define GPIO_BSRR_BS1_Pos (1U) +#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ +#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk +#define GPIO_BSRR_BS2_Pos (2U) +#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ +#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk +#define GPIO_BSRR_BS3_Pos (3U) +#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ +#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk +#define GPIO_BSRR_BS4_Pos (4U) +#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ +#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk +#define GPIO_BSRR_BS5_Pos (5U) +#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ +#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk +#define GPIO_BSRR_BS6_Pos (6U) +#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ +#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk +#define GPIO_BSRR_BS7_Pos (7U) +#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ +#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk +#define GPIO_BSRR_BS8_Pos (8U) +#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ +#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk +#define GPIO_BSRR_BS9_Pos (9U) +#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ +#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk +#define GPIO_BSRR_BS10_Pos (10U) +#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ +#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk +#define GPIO_BSRR_BS11_Pos (11U) +#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ +#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk +#define GPIO_BSRR_BS12_Pos (12U) +#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ +#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk +#define GPIO_BSRR_BS13_Pos (13U) +#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ +#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk +#define GPIO_BSRR_BS14_Pos (14U) +#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ +#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk +#define GPIO_BSRR_BS15_Pos (15U) +#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ +#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk +#define GPIO_BSRR_BR0_Pos (16U) +#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ +#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk +#define GPIO_BSRR_BR1_Pos (17U) +#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ +#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk +#define GPIO_BSRR_BR2_Pos (18U) +#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ +#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk +#define GPIO_BSRR_BR3_Pos (19U) +#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ +#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk +#define GPIO_BSRR_BR4_Pos (20U) +#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ +#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk +#define GPIO_BSRR_BR5_Pos (21U) +#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ +#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk +#define GPIO_BSRR_BR6_Pos (22U) +#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ +#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk +#define GPIO_BSRR_BR7_Pos (23U) +#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ +#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk +#define GPIO_BSRR_BR8_Pos (24U) +#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ +#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk +#define GPIO_BSRR_BR9_Pos (25U) +#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ +#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk +#define GPIO_BSRR_BR10_Pos (26U) +#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ +#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk +#define GPIO_BSRR_BR11_Pos (27U) +#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ +#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk +#define GPIO_BSRR_BR12_Pos (28U) +#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ +#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk +#define GPIO_BSRR_BR13_Pos (29U) +#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ +#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk +#define GPIO_BSRR_BR14_Pos (30U) +#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ +#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk +#define GPIO_BSRR_BR15_Pos (31U) +#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ +#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk + +/****************** Bit definition for GPIO_LCKR register *********************/ +#define GPIO_LCKR_LCK0_Pos (0U) +#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ +#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk +#define GPIO_LCKR_LCK1_Pos (1U) +#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ +#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk +#define GPIO_LCKR_LCK2_Pos (2U) +#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ +#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk +#define GPIO_LCKR_LCK3_Pos (3U) +#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ +#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk +#define GPIO_LCKR_LCK4_Pos (4U) +#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ +#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk +#define GPIO_LCKR_LCK5_Pos (5U) +#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ +#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk +#define GPIO_LCKR_LCK6_Pos (6U) +#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ +#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk +#define GPIO_LCKR_LCK7_Pos (7U) +#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ +#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk +#define GPIO_LCKR_LCK8_Pos (8U) +#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ +#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk +#define GPIO_LCKR_LCK9_Pos (9U) +#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ +#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk +#define GPIO_LCKR_LCK10_Pos (10U) +#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ +#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk +#define GPIO_LCKR_LCK11_Pos (11U) +#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ +#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk +#define GPIO_LCKR_LCK12_Pos (12U) +#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ +#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk +#define GPIO_LCKR_LCK13_Pos (13U) +#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ +#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk +#define GPIO_LCKR_LCK14_Pos (14U) +#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ +#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk +#define GPIO_LCKR_LCK15_Pos (15U) +#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ +#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk +#define GPIO_LCKR_LCKK_Pos (16U) +#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ +#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk + +/****************** Bit definition for GPIO_AFRL register *********************/ +#define GPIO_AFRL_AFSEL0_Pos (0U) +#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk +#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ +#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ +#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ +#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ +#define GPIO_AFRL_AFSEL1_Pos (4U) +#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk +#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ +#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ +#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ +#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ +#define GPIO_AFRL_AFSEL2_Pos (8U) +#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk +#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ +#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ +#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ +#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ +#define GPIO_AFRL_AFSEL3_Pos (12U) +#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk +#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ +#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ +#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ +#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ +#define GPIO_AFRL_AFSEL4_Pos (16U) +#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk +#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ +#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ +#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ +#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ +#define GPIO_AFRL_AFSEL5_Pos (20U) +#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk +#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ +#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ +#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ +#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ +#define GPIO_AFRL_AFSEL6_Pos (24U) +#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk +#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ +#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ +#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ +#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ +#define GPIO_AFRL_AFSEL7_Pos (28U) +#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk +#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ +#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ +#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ +#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ + +/****************** Bit definition for GPIO_AFRH register *********************/ +#define GPIO_AFRH_AFSEL8_Pos (0U) +#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk +#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ +#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ +#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ +#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ +#define GPIO_AFRH_AFSEL9_Pos (4U) +#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk +#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ +#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ +#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ +#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ +#define GPIO_AFRH_AFSEL10_Pos (8U) +#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk +#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ +#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ +#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ +#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ +#define GPIO_AFRH_AFSEL11_Pos (12U) +#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk +#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ +#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ +#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ +#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ +#define GPIO_AFRH_AFSEL12_Pos (16U) +#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk +#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ +#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ +#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ +#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ +#define GPIO_AFRH_AFSEL13_Pos (20U) +#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk +#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ +#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ +#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ +#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ +#define GPIO_AFRH_AFSEL14_Pos (24U) +#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk +#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ +#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ +#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ +#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ +#define GPIO_AFRH_AFSEL15_Pos (28U) +#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk +#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ +#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ +#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ +#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_BRR register ******************/ +#define GPIO_BRR_BR0_Pos (0U) +#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk +#define GPIO_BRR_BR1_Pos (1U) +#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk +#define GPIO_BRR_BR2_Pos (2U) +#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk +#define GPIO_BRR_BR3_Pos (3U) +#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk +#define GPIO_BRR_BR4_Pos (4U) +#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk +#define GPIO_BRR_BR5_Pos (5U) +#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk +#define GPIO_BRR_BR6_Pos (6U) +#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk +#define GPIO_BRR_BR7_Pos (7U) +#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk +#define GPIO_BRR_BR8_Pos (8U) +#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk +#define GPIO_BRR_BR9_Pos (9U) +#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk +#define GPIO_BRR_BR10_Pos (10U) +#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk +#define GPIO_BRR_BR11_Pos (11U) +#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk +#define GPIO_BRR_BR12_Pos (12U) +#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk +#define GPIO_BRR_BR13_Pos (13U) +#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk +#define GPIO_BRR_BR14_Pos (14U) +#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk +#define GPIO_BRR_BR15_Pos (15U) +#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk + + +/******************************************************************************/ +/* */ +/* HASH */ +/* */ +/******************************************************************************/ +/****************** Bits definition for HASH_CR register ********************/ +#define HASH_CR_INIT_Pos (2U) +#define HASH_CR_INIT_Msk (0x1UL << HASH_CR_INIT_Pos) /*!< 0x00000004 */ +#define HASH_CR_INIT HASH_CR_INIT_Msk +#define HASH_CR_DMAE_Pos (3U) +#define HASH_CR_DMAE_Msk (0x1UL << HASH_CR_DMAE_Pos) /*!< 0x00000008 */ +#define HASH_CR_DMAE HASH_CR_DMAE_Msk +#define HASH_CR_DATATYPE_Pos (4U) +#define HASH_CR_DATATYPE_Msk (0x3UL << HASH_CR_DATATYPE_Pos) /*!< 0x00000030 */ +#define HASH_CR_DATATYPE HASH_CR_DATATYPE_Msk +#define HASH_CR_DATATYPE_0 (0x1UL << HASH_CR_DATATYPE_Pos) /*!< 0x00000010 */ +#define HASH_CR_DATATYPE_1 (0x2UL << HASH_CR_DATATYPE_Pos) /*!< 0x00000020 */ +#define HASH_CR_MODE_Pos (6U) +#define HASH_CR_MODE_Msk (0x1UL << HASH_CR_MODE_Pos) /*!< 0x00000040 */ +#define HASH_CR_MODE HASH_CR_MODE_Msk +#define HASH_CR_NBW_Pos (8U) +#define HASH_CR_NBW_Msk (0xFUL << HASH_CR_NBW_Pos) /*!< 0x00000F00 */ +#define HASH_CR_NBW HASH_CR_NBW_Msk +#define HASH_CR_NBW_0 (0x1UL << HASH_CR_NBW_Pos) /*!< 0x00000100 */ +#define HASH_CR_NBW_1 (0x2UL << HASH_CR_NBW_Pos) /*!< 0x00000200 */ +#define HASH_CR_NBW_2 (0x4UL << HASH_CR_NBW_Pos) /*!< 0x00000400 */ +#define HASH_CR_NBW_3 (0x8UL << HASH_CR_NBW_Pos) /*!< 0x00000800 */ +#define HASH_CR_DINNE_Pos (12U) +#define HASH_CR_DINNE_Msk (0x1UL << HASH_CR_DINNE_Pos) /*!< 0x00001000 */ +#define HASH_CR_DINNE HASH_CR_DINNE_Msk +#define HASH_CR_MDMAT_Pos (13U) +#define HASH_CR_MDMAT_Msk (0x1UL << HASH_CR_MDMAT_Pos) /*!< 0x00002000 */ +#define HASH_CR_MDMAT HASH_CR_MDMAT_Msk +#define HASH_CR_LKEY_Pos (16U) +#define HASH_CR_LKEY_Msk (0x1UL << HASH_CR_LKEY_Pos) /*!< 0x00010000 */ +#define HASH_CR_LKEY HASH_CR_LKEY_Msk +#define HASH_CR_ALGO_Pos (17U) +#define HASH_CR_ALGO_Msk (0x3UL << HASH_CR_ALGO_Pos) /*!< 0x00040080 */ +#define HASH_CR_ALGO HASH_CR_ALGO_Msk +#define HASH_CR_ALGO_0 (0x1UL << HASH_CR_ALGO_Pos) /*!< 0x00000080 */ +#define HASH_CR_ALGO_1 (0x2UL << HASH_CR_ALGO_Pos) /*!< 0x00040000 */ + +/****************** Bits definition for HASH_STR register *******************/ +#define HASH_STR_NBLW_Pos (0U) +#define HASH_STR_NBLW_Msk (0x1FUL << HASH_STR_NBLW_Pos) /*!< 0x0000001F */ +#define HASH_STR_NBLW HASH_STR_NBLW_Msk +#define HASH_STR_NBLW_0 (0x01UL << HASH_STR_NBLW_Pos) /*!< 0x00000001 */ +#define HASH_STR_NBLW_1 (0x02UL << HASH_STR_NBLW_Pos) /*!< 0x00000002 */ +#define HASH_STR_NBLW_2 (0x04UL << HASH_STR_NBLW_Pos) /*!< 0x00000004 */ +#define HASH_STR_NBLW_3 (0x08UL << HASH_STR_NBLW_Pos) /*!< 0x00000008 */ +#define HASH_STR_NBLW_4 (0x10UL << HASH_STR_NBLW_Pos) /*!< 0x00000010 */ +#define HASH_STR_DCAL_Pos (8U) +#define HASH_STR_DCAL_Msk (0x1UL << HASH_STR_DCAL_Pos) /*!< 0x00000100 */ +#define HASH_STR_DCAL HASH_STR_DCAL_Msk + +/****************** Bits definition for HASH_IMR register *******************/ +#define HASH_IMR_DINIE_Pos (0U) +#define HASH_IMR_DINIE_Msk (0x1UL << HASH_IMR_DINIE_Pos) /*!< 0x00000001 */ +#define HASH_IMR_DINIE HASH_IMR_DINIE_Msk +#define HASH_IMR_DCIE_Pos (1U) +#define HASH_IMR_DCIE_Msk (0x1UL << HASH_IMR_DCIE_Pos) /*!< 0x00000002 */ +#define HASH_IMR_DCIE HASH_IMR_DCIE_Msk + +/****************** Bits definition for HASH_SR register ********************/ +#define HASH_SR_DINIS_Pos (0U) +#define HASH_SR_DINIS_Msk (0x1UL << HASH_SR_DINIS_Pos) /*!< 0x00000001 */ +#define HASH_SR_DINIS HASH_SR_DINIS_Msk +#define HASH_SR_DCIS_Pos (1U) +#define HASH_SR_DCIS_Msk (0x1UL << HASH_SR_DCIS_Pos) /*!< 0x00000002 */ +#define HASH_SR_DCIS HASH_SR_DCIS_Msk +#define HASH_SR_DMAS_Pos (2U) +#define HASH_SR_DMAS_Msk (0x1UL << HASH_SR_DMAS_Pos) /*!< 0x00000004 */ +#define HASH_SR_DMAS HASH_SR_DMAS_Msk +#define HASH_SR_BUSY_Pos (3U) +#define HASH_SR_BUSY_Msk (0x1UL << HASH_SR_BUSY_Pos) /*!< 0x00000008 */ +#define HASH_SR_BUSY HASH_SR_BUSY_Msk +#define HASH_SR_NBWE_Pos (16U) +#define HASH_SR_NBWE_Msk (0xFUL << HASH_SR_NBWE_Pos) /*!< 0x000F0000 */ +#define HASH_SR_NBWE HASH_SR_NBWE_Msk +#define HASH_SR_NBWE_0 (0x01UL << HASH_SR_NBWE_Pos) /*!< 0x00010000 */ +#define HASH_SR_NBWE_1 (0x02UL << HASH_SR_NBWE_Pos) /*!< 0x00020000 */ +#define HASH_SR_NBWE_2 (0x04UL << HASH_SR_NBWE_Pos) /*!< 0x00040000 */ +#define HASH_SR_NBWE_3 (0x08UL << HASH_SR_NBWE_Pos) /*!< 0x00080000 */ +#define HASH_SR_DINNE_Pos (15U) +#define HASH_SR_DINNE_Msk (0x1UL << HASH_SR_DINNE_Pos) /*!< 0x00008000 */ +#define HASH_SR_DINNE HASH_SR_DINNE_Msk +#define HASH_SR_NBWP_Pos (9U) +#define HASH_SR_NBWP_Msk (0xFUL << HASH_SR_NBWP_Pos) /*!< 0x000F0000 */ +#define HASH_SR_NBWP HASH_SR_NBWP_Msk +#define HASH_SR_NBWP_0 (0x01UL << HASH_SR_NBWP_Pos) /*!< 0x000O0200 */ +#define HASH_SR_NBWP_1 (0x02UL << HASH_SR_NBWP_Pos) /*!< 0x00000400 */ +#define HASH_SR_NBWP_2 (0x04UL << HASH_SR_NBWP_Pos) /*!< 0x00000800 */ +#define HASH_SR_NBWP_3 (0x08UL << HASH_SR_NBWP_Pos) /*!< 0x00001000 */ + + +/******************************************************************************/ +/* */ +/* HSEM HW Semaphore */ +/* */ +/******************************************************************************/ +/******************** Bit definition for HSEM_R register ********************/ +#define HSEM_R_PROCID_Pos (0U) +#define HSEM_R_PROCID_Msk (0xFFUL << HSEM_R_PROCID_Pos) /*!< 0x000000FF */ +#define HSEM_R_PROCID HSEM_R_PROCID_Msk /*!>2) /*!< Input modulus number of bits */ +#define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Compute Montgomery parameter output data */ +#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output Montgomery parameter */ + +/* Compute modular exponentiation input data */ +#define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ +#define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ +#define PKA_MODULAR_EXP_IN_EXPONENT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process */ +#define PKA_MODULAR_EXP_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE ((0x16C8UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT ((0x14B8UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process protected exponentiation*/ +#define PKA_MODULAR_EXP_PROTECT_IN_MODULUS ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus to process protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_PHI ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input phi to process protected exponentiation */ + +/* Compute modular exponentiation output data */ +#define PKA_MODULAR_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_ERROR ((0x1298UL - PKA_RAM_OFFSET)>>2) /*!< Output error of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Output base of the exponentiation */ + +/* Compute ECC scalar multiplication input data */ +#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input curve prime order n number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_SCALAR_MUL_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' of KP */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input prime order n */ + +/* Compute ECC scalar multiplication output data */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Point check input data */ +#define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_POINT_CHECK_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_POINT_CHECK_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_POINT_CHECK_IN_MOD_GF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_POINT_CHECK_IN_MONTGOMERY_PARAM ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Point check output data */ +#define PKA_POINT_CHECK_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ + +/* ECDSA signature input data */ +#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECDSA_SIGN_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_SIGN_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input k value of the ECDSA */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_SIGN_IN_HASH_E ((0x0FE8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0x0F28UL - PKA_RAM_OFFSET)>>2) /*!< Input d, private key */ +#define PKA_ECDSA_SIGN_IN_ORDER_N ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA signature output data */ +#define PKA_ECDSA_SIGN_OUT_ERROR ((0x0FE0UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Output signature r */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Output signature s */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x1400UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point X coordinate */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1458UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point Y coordinate */ + + +/* ECDSA verification input data */ +#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x0468UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_A_COEFF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_MOD_GF ((0x04D0UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x0678UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x06D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0x12F8UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point X coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0x1350UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point Y coordinate */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x10E0UL - PKA_RAM_OFFSET)>>2) /*!< Input r, part of the signature */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input s, part of the signature */ +#define PKA_ECDSA_VERIF_IN_HASH_E ((0x13A8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_VERIF_IN_ORDER_N ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA verification output data */ +#define PKA_ECDSA_VERIF_OUT_RESULT ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* RSA CRT exponentiation input data */ +#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operands number of bits */ +#define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input Dp CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input Dq CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x0948UL - PKA_RAM_OFFSET)>>2) /*!< Input qInv CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x0B60UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime p */ +#define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime q */ +#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ + +/* RSA CRT exponentiation output data */ +#define PKA_RSA_CRT_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular reduction input data */ +#define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input operand length */ +#define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus length */ +#define PKA_MODULAR_REDUC_IN_OPERAND ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand */ +#define PKA_MODULAR_REDUC_IN_MODULUS ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Modular reduction output data */ +#define PKA_MODULAR_REDUC_OUT_RESULT ((0xE78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic addition input data */ +#define PKA_ARITHMETIC_ADD_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic addition output data */ +#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic subtraction input data */ +#define PKA_ARITHMETIC_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic subtraction output data */ +#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic multiplication input data */ +#define PKA_ARITHMETIC_MUL_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic multiplication output data */ +#define PKA_ARITHMETIC_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Comparison input data */ +#define PKA_COMPARISON_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_COMPARISON_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_COMPARISON_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Comparison output data */ +#define PKA_COMPARISON_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular addition input data */ +#define PKA_MODULAR_ADD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_ADD_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 (modulus) */ + +/* Modular addition output data */ +#define PKA_MODULAR_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular inversion input data */ +#define PKA_MODULAR_INV_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_INV_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_INV_IN_OP2_MOD ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 (modulus) */ + +/* Modular inversion output data */ +#define PKA_MODULAR_INV_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular subtraction input data */ +#define PKA_MODULAR_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_SUB_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ + +/* Modular subtraction output data */ +#define PKA_MODULAR_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Montgomery multiplication input data */ +#define PKA_MONTGOMERY_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MONTGOMERY_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MONTGOMERY_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Montgomery multiplication output data */ +#define PKA_MONTGOMERY_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Generic Arithmetic input data */ +#define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Generic Arithmetic output data */ +#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result for arithmetic operations */ + +/* Compute ECC complete addition input data */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC complete addition output data */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Output result Z coordinate */ + +/* Compute ECC double base ladder input data */ +#define PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input 'm' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC double base ladder output data */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_ERROR ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Compute ECC projective to affine conversion input data */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P X coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Y coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Z coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2 ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Compute ECC projective to affine conversion output data */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result x affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result y affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + + +/******************************************************************************/ +/* */ +/* Power Control */ +/* */ +/******************************************************************************/ +/******************** Bit definition for PWR_CR1 register *******************/ +#define PWR_CR1_LPMS_Pos (0U) +#define PWR_CR1_LPMS_Msk (0x7UL << PWR_CR1_LPMS_Pos) /*!< 0x00000007 */ +#define PWR_CR1_LPMS PWR_CR1_LPMS_Msk /*!< LPMS[2:0] Low-power mode selection field */ +#define PWR_CR1_LPMS_0 (0x1UL << PWR_CR1_LPMS_Pos) /*!< 0x00000001 */ +#define PWR_CR1_LPMS_1 (0x2UL << PWR_CR1_LPMS_Pos) /*!< 0x00000002 */ +#define PWR_CR1_LPMS_2 (0x4UL << PWR_CR1_LPMS_Pos) /*!< 0x00000004 */ +#define PWR_CR1_R2RSB1_Pos (5U) +#define PWR_CR1_R2RSB1_Msk (0x1UL << PWR_CR1_R2RSB1_Pos) /*!< 0x00000020 */ +#define PWR_CR1_R2RSB1 PWR_CR1_R2RSB1_Msk /*!< SRAM2 Retention in Standby */ +#define PWR_CR1_ULPMEN_Pos (7U) +#define PWR_CR1_ULPMEN_Msk (0x1UL << PWR_CR1_ULPMEN_Pos) /*!< 0x00000080 */ +#define PWR_CR1_ULPMEN PWR_CR1_ULPMEN_Msk /*!< BOR ultra-low power mode in Standby/Shutdown */ +#define PWR_CR1_RADIORSB_Pos (9U) +#define PWR_CR1_RADIORSB_Msk (0x1UL << PWR_CR1_RADIORSB_Pos) /*!< 0x00000200 */ +#define PWR_CR1_RADIORSB PWR_CR1_RADIORSB_Msk /*!< 2.4GHz RADIO SRAMs (TXRX and Sequence) and Sleep clock retention in Standby mode */ +#define PWR_CR1_R1RSB1_Pos (12U) +#define PWR_CR1_R1RSB1_Msk (0x1UL << PWR_CR1_R1RSB1_Pos) /*!< 0x00001000 */ +#define PWR_CR1_R1RSB1 PWR_CR1_R1RSB1_Msk /*!< SRAM1 Page 1 Retention in Standby */ + +/******************** Bit definition for PWR_CR2 register *******************/ +#define PWR_CR2_SRAM1PDS1_Pos (0U) +#define PWR_CR2_SRAM1PDS1_Msk (0x1UL << PWR_CR2_SRAM1PDS1_Pos) /*!< 0x00000001 */ +#define PWR_CR2_SRAM1PDS1 PWR_CR2_SRAM1PDS1_Msk /*!< SRAM1 Page 1 power-down in Stop modes */ +#define PWR_CR2_SRAM2PDS1_Pos (4U) +#define PWR_CR2_SRAM2PDS1_Msk (0x1UL << PWR_CR2_SRAM2PDS1_Pos) /*!< 0x00000010 */ +#define PWR_CR2_SRAM2PDS1 PWR_CR2_SRAM2PDS1_Msk /*!< SRAM2 power-down in Stop modes */ +#define PWR_CR2_ICRAMPDS_Pos (8U) +#define PWR_CR2_ICRAMPDS_Msk (0x1UL << PWR_CR2_ICRAMPDS_Pos) /*!< 0x00000100 */ +#define PWR_CR2_ICRAMPDS PWR_CR2_ICRAMPDS_Msk /*!< ICACHE SRAM power-down in Stop modes */ +#define PWR_CR2_FLASHFWU_Pos (14U) +#define PWR_CR2_FLASHFWU_Msk (0x1UL << PWR_CR2_FLASHFWU_Pos) /*!< 0x00004000 */ +#define PWR_CR2_FLASHFWU PWR_CR2_FLASHFWU_Msk /*!< Flash low-power mode in Stop modes */ + +/******************** Bit definition for PWR_CR3 register *******************/ +#define PWR_CR3_FSTEN_Pos (2U) +#define PWR_CR3_FSTEN_Msk (0x1UL << PWR_CR3_FSTEN_Pos) /*!< 0x00000004 */ +#define PWR_CR3_FSTEN PWR_CR3_FSTEN_Msk /*!< Fast soft start */ + +/******************* Bit definition for PWR_VOSR register *******************/ +#define PWR_VOSR_VOSRDY_Pos (15U) +#define PWR_VOSR_VOSRDY_Msk (0x1UL << PWR_VOSR_VOSRDY_Pos) /*!< 0x00008000 */ +#define PWR_VOSR_VOSRDY PWR_VOSR_VOSRDY_Msk /*!< Ready bit for VCORE voltage scaling output selection */ +#define PWR_VOSR_VOS_Pos (16U) +#define PWR_VOSR_VOS_Msk (0x1UL << PWR_VOSR_VOS_Pos) /*!< 0x00010000 */ +#define PWR_VOSR_VOS PWR_VOSR_VOS_Msk /*!< Voltage scaling range selection */ + +/******************* Bit definition for PWR_SVMCR register ******************/ +#define PWR_SVMCR_PVDE_Pos (4U) +#define PWR_SVMCR_PVDE_Msk (0x1UL << PWR_SVMCR_PVDE_Pos) /*!< 0x00000010 */ +#define PWR_SVMCR_PVDE PWR_SVMCR_PVDE_Msk /*!< Power voltage detector enable */ +#define PWR_SVMCR_PVDLS_Pos (5U) +#define PWR_SVMCR_PVDLS_Msk (0x7UL << PWR_SVMCR_PVDLS_Pos) /*!< 0x000000E0 */ +#define PWR_SVMCR_PVDLS PWR_SVMCR_PVDLS_Msk /*!< PVDLS[2:0] Power voltage detector level selection field */ +#define PWR_SVMCR_PVDLS_0 (0x1UL << PWR_SVMCR_PVDLS_Pos) /*!< 0x00000020 */ +#define PWR_SVMCR_PVDLS_1 (0x2UL << PWR_SVMCR_PVDLS_Pos) /*!< 0x00000040 */ +#define PWR_SVMCR_PVDLS_2 (0x4UL << PWR_SVMCR_PVDLS_Pos) /*!< 0x00000080 */ + +/******************* Bit definition for PWR_WUCR1 register ******************/ +#define PWR_WUCR1_WUPEN1_Pos (0U) +#define PWR_WUCR1_WUPEN1_Msk (0x1UL << PWR_WUCR1_WUPEN1_Pos) /*!< 0x00000001 */ +#define PWR_WUCR1_WUPEN1 PWR_WUCR1_WUPEN1_Msk /*!< Wakeup pin WKUP1 enable */ +#define PWR_WUCR1_WUPEN3_Pos (2U) +#define PWR_WUCR1_WUPEN3_Msk (0x1UL << PWR_WUCR1_WUPEN3_Pos) /*!< 0x00000004 */ +#define PWR_WUCR1_WUPEN3 PWR_WUCR1_WUPEN3_Msk /*!< Wakeup pin WKUP3 enable */ +#define PWR_WUCR1_WUPEN4_Pos (3U) +#define PWR_WUCR1_WUPEN4_Msk (0x1UL << PWR_WUCR1_WUPEN4_Pos) /*!< 0x00000008 */ +#define PWR_WUCR1_WUPEN4 PWR_WUCR1_WUPEN4_Msk /*!< Wakeup pin WKUP4 enable */ +#define PWR_WUCR1_WUPEN6_Pos (5U) +#define PWR_WUCR1_WUPEN6_Msk (0x1UL << PWR_WUCR1_WUPEN6_Pos) /*!< 0x00000020 */ +#define PWR_WUCR1_WUPEN6 PWR_WUCR1_WUPEN6_Msk /*!< Wakeup pin WKUP6 enable */ +#define PWR_WUCR1_WUPEN7_Pos (6U) +#define PWR_WUCR1_WUPEN7_Msk (0x1UL << PWR_WUCR1_WUPEN7_Pos) /*!< 0x00000040 */ +#define PWR_WUCR1_WUPEN7 PWR_WUCR1_WUPEN7_Msk /*!< Wakeup pin WKUP7 enable */ +#define PWR_WUCR1_WUPEN8_Pos (7U) +#define PWR_WUCR1_WUPEN8_Msk (0x1UL << PWR_WUCR1_WUPEN8_Pos) /*!< 0x00000080 */ +#define PWR_WUCR1_WUPEN8 PWR_WUCR1_WUPEN8_Msk /*!< Wakeup pin WKUP8 enable */ + +/******************* Bit definition for PWR_WUCR2 register ******************/ +#define PWR_WUCR2_WUPP1_Pos (0U) +#define PWR_WUCR2_WUPP1_Msk (0x1UL << PWR_WUCR2_WUPP1_Pos) /*!< 0x00000001 */ +#define PWR_WUCR2_WUPP1 PWR_WUCR2_WUPP1_Msk /*!< Wakeup pin WKUP1 polarity */ +#define PWR_WUCR2_WUPP3_Pos (2U) +#define PWR_WUCR2_WUPP3_Msk (0x1UL << PWR_WUCR2_WUPP3_Pos) /*!< 0x00000004 */ +#define PWR_WUCR2_WUPP3 PWR_WUCR2_WUPP3_Msk /*!< Wakeup pin WKUP3 polarity */ +#define PWR_WUCR2_WUPP4_Pos (3U) +#define PWR_WUCR2_WUPP4_Msk (0x1UL << PWR_WUCR2_WUPP4_Pos) /*!< 0x00000008 */ +#define PWR_WUCR2_WUPP4 PWR_WUCR2_WUPP4_Msk /*!< Wakeup pin WKUP4 polarity */ +#define PWR_WUCR2_WUPP6_Pos (5U) +#define PWR_WUCR2_WUPP6_Msk (0x1UL << PWR_WUCR2_WUPP6_Pos) /*!< 0x00000020 */ +#define PWR_WUCR2_WUPP6 PWR_WUCR2_WUPP6_Msk /*!< Wakeup pin WKUP6 polarity */ +#define PWR_WUCR2_WUPP7_Pos (6U) +#define PWR_WUCR2_WUPP7_Msk (0x1UL << PWR_WUCR2_WUPP7_Pos) /*!< 0x00000040 */ +#define PWR_WUCR2_WUPP7 PWR_WUCR2_WUPP7_Msk /*!< Wakeup pin WKUP7 polarity */ +#define PWR_WUCR2_WUPP8_Pos (7U) +#define PWR_WUCR2_WUPP8_Msk (0x1UL << PWR_WUCR2_WUPP8_Pos) /*!< 0x00000080 */ +#define PWR_WUCR2_WUPP8 PWR_WUCR2_WUPP8_Msk /*!< Wakeup pin WKUP8 polarity */ + +/******************* Bit definition for PWR_WUCR3 register ******************/ +#define PWR_WUCR3_WUSEL1_Pos (0U) +#define PWR_WUCR3_WUSEL1_Msk (0x3UL << PWR_WUCR3_WUSEL1_Pos) /*!< 0x00000003 */ +#define PWR_WUCR3_WUSEL1 PWR_WUCR3_WUSEL1_Msk /*!< Wakeup pin WKUP1 selection field */ +#define PWR_WUCR3_WUSEL1_0 (0x1UL << PWR_WUCR3_WUSEL1_Pos) /*!< 0x00000001 */ +#define PWR_WUCR3_WUSEL1_1 (0x2UL << PWR_WUCR3_WUSEL1_Pos) /*!< 0x00000002 */ +#define PWR_WUCR3_WUSEL3_Pos (4U) +#define PWR_WUCR3_WUSEL3_Msk (0x3UL << PWR_WUCR3_WUSEL3_Pos) /*!< 0x00000030 */ +#define PWR_WUCR3_WUSEL3 PWR_WUCR3_WUSEL3_Msk /*!< Wakeup pin WKUP3 selection field */ +#define PWR_WUCR3_WUSEL3_0 (0x1UL << PWR_WUCR3_WUSEL3_Pos) /*!< 0x00000010 */ +#define PWR_WUCR3_WUSEL3_1 (0x2UL << PWR_WUCR3_WUSEL3_Pos) /*!< 0x00000020 */ +#define PWR_WUCR3_WUSEL4_Pos (6U) +#define PWR_WUCR3_WUSEL4_Msk (0x3UL << PWR_WUCR3_WUSEL4_Pos) /*!< 0x000000C0 */ +#define PWR_WUCR3_WUSEL4 PWR_WUCR3_WUSEL4_Msk /*!< Wakeup pin WKUP4 selection field */ +#define PWR_WUCR3_WUSEL4_0 (0x1UL << PWR_WUCR3_WUSEL4_Pos) /*!< 0x00000040 */ +#define PWR_WUCR3_WUSEL4_1 (0x2UL << PWR_WUCR3_WUSEL4_Pos) /*!< 0x00000080 */ +#define PWR_WUCR3_WUSEL6_Pos (10U) +#define PWR_WUCR3_WUSEL6_Msk (0x3UL << PWR_WUCR3_WUSEL6_Pos) /*!< 0x00000C00 */ +#define PWR_WUCR3_WUSEL6 PWR_WUCR3_WUSEL6_Msk /*!< Wakeup pin WKUP6 selection field */ +#define PWR_WUCR3_WUSEL6_0 (0x1UL << PWR_WUCR3_WUSEL6_Pos) /*!< 0x00000400 */ +#define PWR_WUCR3_WUSEL6_1 (0x2UL << PWR_WUCR3_WUSEL6_Pos) /*!< 0x00000800 */ +#define PWR_WUCR3_WUSEL7_Pos (12U) +#define PWR_WUCR3_WUSEL7_Msk (0x3UL << PWR_WUCR3_WUSEL7_Pos) /*!< 0x00003000 */ +#define PWR_WUCR3_WUSEL7 PWR_WUCR3_WUSEL7_Msk /*!< Wakeup pin WKUP7 selection field */ +#define PWR_WUCR3_WUSEL7_0 (0x1UL << PWR_WUCR3_WUSEL7_Pos) /*!< 0x00001000 */ +#define PWR_WUCR3_WUSEL7_1 (0x2UL << PWR_WUCR3_WUSEL7_Pos) /*!< 0x00002000 */ +#define PWR_WUCR3_WUSEL8_Pos (14U) +#define PWR_WUCR3_WUSEL8_Msk (0x3UL << PWR_WUCR3_WUSEL8_Pos) /*!< 0x0000C000 */ +#define PWR_WUCR3_WUSEL8 PWR_WUCR3_WUSEL8_Msk /*!< Wakeup pin WKUP8 selection field */ +#define PWR_WUCR3_WUSEL8_0 (0x1UL << PWR_WUCR3_WUSEL8_Pos) /*!< 0x00004000 */ +#define PWR_WUCR3_WUSEL8_1 (0x2UL << PWR_WUCR3_WUSEL8_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for PWR_DBPR register ******************/ +#define PWR_DBPR_DBP_Pos (0U) +#define PWR_DBPR_DBP_Msk (0x1UL << PWR_DBPR_DBP_Pos) /*!< 0x00000001 */ +#define PWR_DBPR_DBP PWR_DBPR_DBP_Msk /*!< Disable backup domain write protection */ + +/********************** Bit definition for PWR_SR register ******************/ +#define PWR_SR_CSSF_Pos (0U) +#define PWR_SR_CSSF_Msk (0x1UL << PWR_SR_CSSF_Pos) /*!< 0x00000001 */ +#define PWR_SR_CSSF PWR_SR_CSSF_Msk /*!< Clear Stop and Standby/Shutdown flags */ +#define PWR_SR_STOPF_Pos (1U) +#define PWR_SR_STOPF_Msk (0x1UL << PWR_SR_STOPF_Pos) /*!< 0x00000002 */ +#define PWR_SR_STOPF PWR_SR_STOPF_Msk /*!< Stop flag */ +#define PWR_SR_SBF_Pos (2U) +#define PWR_SR_SBF_Msk (0x1UL << PWR_SR_SBF_Pos) /*!< 0x00000004 */ +#define PWR_SR_SBF PWR_SR_SBF_Msk /*!< Standby/Shutdown flag */ + +/******************** Bit definition for PWR_SVMSR register *****************/ +#define PWR_SVMSR_PVDO_Pos (4U) +#define PWR_SVMSR_PVDO_Msk (0x1UL << PWR_SVMSR_PVDO_Pos) /*!< 0x00000010 */ +#define PWR_SVMSR_PVDO PWR_SVMSR_PVDO_Msk /*!< VDD voltage detector output */ +#define PWR_SVMSR_ACTVOSRDY_Pos (15U) +#define PWR_SVMSR_ACTVOSRDY_Msk (0x1UL << PWR_SVMSR_ACTVOSRDY_Pos) /*!< 0x00008000 */ +#define PWR_SVMSR_ACTVOSRDY PWR_SVMSR_ACTVOSRDY_Msk /*!< Voltage level ready for currently used VOS */ +#define PWR_SVMSR_ACTVOS_Pos (16U) +#define PWR_SVMSR_ACTVOS_Msk (0x1UL << PWR_SVMSR_ACTVOS_Pos) /*!< 0x00010000 */ +#define PWR_SVMSR_ACTVOS PWR_SVMSR_ACTVOS_Msk /*!< Voltage Output Scaling currently applied to VCORE */ + +/********************* Bit definition for PWR_WUSR register *****************/ +#define PWR_WUSR_WUF1_Pos (0U) +#define PWR_WUSR_WUF1_Msk (0x1UL << PWR_WUSR_WUF1_Pos) /*!< 0x00000001 */ +#define PWR_WUSR_WUF1 PWR_WUSR_WUF1_Msk /*!< Wakeup flag 1 */ +#define PWR_WUSR_WUF3_Pos (2U) +#define PWR_WUSR_WUF3_Msk (0x1UL << PWR_WUSR_WUF3_Pos) /*!< 0x00000004 */ +#define PWR_WUSR_WUF3 PWR_WUSR_WUF3_Msk /*!< Wakeup flag 3 */ +#define PWR_WUSR_WUF4_Pos (3U) +#define PWR_WUSR_WUF4_Msk (0x1UL << PWR_WUSR_WUF4_Pos) /*!< 0x00000008 */ +#define PWR_WUSR_WUF4 PWR_WUSR_WUF4_Msk /*!< Wakeup flag 4 */ +#define PWR_WUSR_WUF6_Pos (5U) +#define PWR_WUSR_WUF6_Msk (0x1UL << PWR_WUSR_WUF6_Pos) /*!< 0x00000020 */ +#define PWR_WUSR_WUF6 PWR_WUSR_WUF6_Msk /*!< Wakeup flag 6 */ +#define PWR_WUSR_WUF7_Pos (6U) +#define PWR_WUSR_WUF7_Msk (0x1UL << PWR_WUSR_WUF7_Pos) /*!< 0x00000040 */ +#define PWR_WUSR_WUF7 PWR_WUSR_WUF7_Msk /*!< Wakeup flag 7 */ +#define PWR_WUSR_WUF8_Pos (7U) +#define PWR_WUSR_WUF8_Msk (0x1UL << PWR_WUSR_WUF8_Pos) /*!< 0x00000080 */ +#define PWR_WUSR_WUF8 PWR_WUSR_WUF8_Msk /*!< Wakeup flag 8 */ +#define PWR_WUSR_WUF_Pos (0U) +#define PWR_WUSR_WUF_Msk (0xFFUL << PWR_WUSR_WUF_Pos) /*!< 0x000000FF */ +#define PWR_WUSR_WUF PWR_WUSR_WUF_Msk /*!< all Wakeup flag */ + +/********************* Bit definition for PWR_WUSCR register ****************/ +#define PWR_WUSCR_CWUF1_Pos (0U) +#define PWR_WUSCR_CWUF1_Msk (0x1UL << PWR_WUSCR_CWUF1_Pos) /*!< 0x00000001*/ +#define PWR_WUSCR_CWUF1 PWR_WUSCR_CWUF1_Msk /*!< Wakeup clear flag 1 */ +#define PWR_WUSCR_CWUF3_Pos (2U) +#define PWR_WUSCR_CWUF3_Msk (0x1UL << PWR_WUSCR_CWUF3_Pos) /*!< 0x00000004 */ +#define PWR_WUSCR_CWUF3 PWR_WUSCR_CWUF3_Msk /*!< Wakeup clear flag 3 */ +#define PWR_WUSCR_CWUF4_Pos (3U) +#define PWR_WUSCR_CWUF4_Msk (0x1UL << PWR_WUSCR_CWUF4_Pos) /*!< 0x00000008 */ +#define PWR_WUSCR_CWUF4 PWR_WUSCR_CWUF4_Msk /*!< Wakeup clear flag 4 */ +#define PWR_WUSCR_CWUF6_Pos (5U) +#define PWR_WUSCR_CWUF6_Msk (0x1UL << PWR_WUSCR_CWUF6_Pos) /*!< 0x00000020 */ +#define PWR_WUSCR_CWUF6 PWR_WUSCR_CWUF6_Msk /*!< Wakeup clear flag 6 */ +#define PWR_WUSCR_CWUF7_Pos (6U) +#define PWR_WUSCR_CWUF7_Msk (0x1UL << PWR_WUSCR_CWUF7_Pos) /*!< 0x00000040 */ +#define PWR_WUSCR_CWUF7 PWR_WUSCR_CWUF7_Msk /*!< Wakeup clear flag 7 */ +#define PWR_WUSCR_CWUF8_Pos (7U) +#define PWR_WUSCR_CWUF8_Msk (0x1UL << PWR_WUSCR_CWUF8_Pos) /*!< 0x00000080 */ +#define PWR_WUSCR_CWUF8 PWR_WUSCR_CWUF8_Msk /*!< Wakeup clear flag 8 */ +#define PWR_WUSCR_CWUF_Pos (0U) +#define PWR_WUSCR_CWUF_Msk (0xFFUL << PWR_WUSCR_CWUF1_Pos) /*!< 0x000000FF */ +#define PWR_WUSCR_CWUF PWR_WUSCR_CWUF_Msk /*!< all Wakeup clear flag */ + +/******************** Bit definition for PWR_IORETENRA register *****************/ +#define PWR_IORETENRA_EN0_Pos (0U) +#define PWR_IORETENRA_EN0_Msk (0x1UL << PWR_IORETENRA_EN0_Pos) /*!< 0x00000001 */ +#define PWR_IORETENRA_EN0 PWR_IORETENRA_EN0_Msk /*!< Standby GPIO retention enable for PA0 */ +#define PWR_IORETENRA_EN1_Pos (1U) +#define PWR_IORETENRA_EN1_Msk (0x1UL << PWR_IORETENRA_EN1_Pos) /*!< 0x00000002 */ +#define PWR_IORETENRA_EN1 PWR_IORETENRA_EN1_Msk /*!< Standby GPIO retention enable for PA1 */ +#define PWR_IORETENRA_EN2_Pos (2U) +#define PWR_IORETENRA_EN2_Msk (0x1UL << PWR_IORETENRA_EN2_Pos) /*!< 0x00000004 */ +#define PWR_IORETENRA_EN2 PWR_IORETENRA_EN2_Msk /*!< Standby GPIO retention enable for PA2 */ +#define PWR_IORETENRA_EN5_Pos (5U) +#define PWR_IORETENRA_EN5_Msk (0x1UL << PWR_IORETENRA_EN5_Pos) /*!< 0x00000020 */ +#define PWR_IORETENRA_EN5 PWR_IORETENRA_EN5_Msk /*!< Standby GPIO retention enable for PA5 */ +#define PWR_IORETENRA_EN6_Pos (6U) +#define PWR_IORETENRA_EN6_Msk (0x1UL << PWR_IORETENRA_EN6_Pos) /*!< 0x00000040 */ +#define PWR_IORETENRA_EN6 PWR_IORETENRA_EN6_Msk /*!< Standby GPIO retention enable for PA6 */ +#define PWR_IORETENRA_EN7_Pos (7U) +#define PWR_IORETENRA_EN7_Msk (0x1UL << PWR_IORETENRA_EN7_Pos) /*!< 0x00000080 */ +#define PWR_IORETENRA_EN7 PWR_IORETENRA_EN7_Msk /*!< Standby GPIO retention enable for PA7 */ +#define PWR_IORETENRA_EN8_Pos (8U) +#define PWR_IORETENRA_EN8_Msk (0x1UL << PWR_IORETENRA_EN8_Pos) /*!< 0x00000100 */ +#define PWR_IORETENRA_EN8 PWR_IORETENRA_EN8_Msk /*!< Standby GPIO retention enable for PA8 */ +#define PWR_IORETENRA_EN12_Pos (12U) +#define PWR_IORETENRA_EN12_Msk (0x1UL << PWR_IORETENRA_EN12_Pos) /*!< 0x00001000 */ +#define PWR_IORETENRA_EN12 PWR_IORETENRA_EN12_Msk /*!< Standby GPIO retention enable for PA12 */ +#define PWR_IORETENRA_EN13_Pos (13U) +#define PWR_IORETENRA_EN13_Msk (0x1UL << PWR_IORETENRA_EN13_Pos) /*!< 0x00002000 */ +#define PWR_IORETENRA_EN13 PWR_IORETENRA_EN13_Msk /*!< Standby GPIO retention enable for PA13 */ +#define PWR_IORETENRA_EN14_Pos (14U) +#define PWR_IORETENRA_EN14_Msk (0x1UL << PWR_IORETENRA_EN14_Pos) /*!< 0x00004000 */ +#define PWR_IORETENRA_EN14 PWR_IORETENRA_EN14_Msk /*!< Standby GPIO retention enable for PA14 */ +#define PWR_IORETENRA_EN15_Pos (15U) +#define PWR_IORETENRA_EN15_Msk (0x1UL << PWR_IORETENRA_EN15_Pos) /*!< 0x00008000 */ +#define PWR_IORETENRA_EN15 PWR_IORETENRA_EN15_Msk /*!< Standby GPIO retention enable for PA15 */ + +/******************** Bit definition for PWR_IORETRA register *****************/ +#define PWR_IORETRA_RET0_Pos (0U) +#define PWR_IORETRA_RET0_Msk (0x1UL << PWR_IORETRA_RET0_Pos) /*!< 0x00000001 */ +#define PWR_IORETRA_RET0 PWR_IORETRA_RET0_Msk /*!< Standby GPIO retention status for PA0 */ +#define PWR_IORETRA_RET1_Pos (1U) +#define PWR_IORETRA_RET1_Msk (0x1UL << PWR_IORETRA_RET1_Pos) /*!< 0x00000002 */ +#define PWR_IORETRA_RET1 PWR_IORETRA_RET1_Msk /*!< Standby GPIO retention status for PA1 */ +#define PWR_IORETRA_RET2_Pos (2U) +#define PWR_IORETRA_RET2_Msk (0x1UL << PWR_IORETRA_RET2_Pos) /*!< 0x00000004 */ +#define PWR_IORETRA_RET2 PWR_IORETRA_RET2_Msk /*!< Standby GPIO retention status for PA2 */ +#define PWR_IORETRA_RET5_Pos (5U) +#define PWR_IORETRA_RET5_Msk (0x1UL << PWR_IORETRA_RET5_Pos) /*!< 0x00000020 */ +#define PWR_IORETRA_RET5 PWR_IORETRA_RET5_Msk /*!< Standby GPIO retention status for PA5 */ +#define PWR_IORETRA_RET6_Pos (6U) +#define PWR_IORETRA_RET6_Msk (0x1UL << PWR_IORETRA_RET6_Pos) /*!< 0x00000040 */ +#define PWR_IORETRA_RET6 PWR_IORETRA_RET6_Msk /*!< Standby GPIO retention status for PA6 */ +#define PWR_IORETRA_RET7_Pos (7U) +#define PWR_IORETRA_RET7_Msk (0x1UL << PWR_IORETRA_RET7_Pos) /*!< 0x00000080 */ +#define PWR_IORETRA_RET7 PWR_IORETRA_RET7_Msk /*!< Standby GPIO retention status for PA7 */ +#define PWR_IORETRA_RET8_Pos (8U) +#define PWR_IORETRA_RET8_Msk (0x1UL << PWR_IORETRA_RET8_Pos) /*!< 0x00000100 */ +#define PWR_IORETRA_RET8 PWR_IORETRA_RET8_Msk /*!< Standby GPIO retention status for PA8 */ +#define PWR_IORETRA_RET12_Pos (12U) +#define PWR_IORETRA_RET12_Msk (0x1UL << PWR_IORETRA_RET12_Pos) /*!< 0x00001000 */ +#define PWR_IORETRA_RET12 PWR_IORETRA_RET12_Msk /*!< Standby GPIO retention status for PA12 */ +#define PWR_IORETRA_RET13_Pos (13U) +#define PWR_IORETRA_RET13_Msk (0x1UL << PWR_IORETRA_RET13_Pos) /*!< 0x00002000 */ +#define PWR_IORETRA_RET13 PWR_IORETRA_RET13_Msk /*!< Standby GPIO retention status for PA13 */ +#define PWR_IORETRA_RET14_Pos (14U) +#define PWR_IORETRA_RET14_Msk (0x1UL << PWR_IORETRA_RET14_Pos) /*!< 0x00004000 */ +#define PWR_IORETRA_RET14 PWR_IORETRA_RET14_Msk /*!< Standby GPIO retention status for PA14 */ +#define PWR_IORETRA_RET15_Pos (15U) +#define PWR_IORETRA_RET15_Msk (0x1UL << PWR_IORETRA_RET15_Pos) /*!< 0x00008000 */ +#define PWR_IORETRA_RET15 PWR_IORETRA_RET15_Msk /*!< Standby GPIO retention status for PA15 */ + +/******************** Bit definition for PWR_IORETENRB register *****************/ +#define PWR_IORETENRB_EN3_Pos (3U) +#define PWR_IORETENRB_EN3_Msk (0x1UL << PWR_IORETENRB_EN3_Pos) /*!< 0x00000008 */ +#define PWR_IORETENRB_EN3 PWR_IORETENRB_EN3_Msk /*!< Standby GPIO retention enable for PB3 */ +#define PWR_IORETENRB_EN4_Pos (4U) +#define PWR_IORETENRB_EN4_Msk (0x1UL << PWR_IORETENRB_EN4_Pos) /*!< 0x00000010 */ +#define PWR_IORETENRB_EN4 PWR_IORETENRB_EN4_Msk /*!< Standby GPIO retention enable for PB4 */ +#define PWR_IORETENRB_EN8_Pos (8U) +#define PWR_IORETENRB_EN8_Msk (0x1UL << PWR_IORETENRB_EN8_Pos) /*!< 0x00000100 */ +#define PWR_IORETENRB_EN8 PWR_IORETENRB_EN8_Msk /*!< Standby GPIO retention enable for PB8 */ +#define PWR_IORETENRB_EN9_Pos (9U) +#define PWR_IORETENRB_EN9_Msk (0x1UL << PWR_IORETENRB_EN9_Pos) /*!< 0x00000200 */ +#define PWR_IORETENRB_EN9 PWR_IORETENRB_EN9_Msk /*!< Standby GPIO retention enable for PB9 */ +#define PWR_IORETENRB_EN12_Pos (12U) +#define PWR_IORETENRB_EN12_Msk (0x1UL << PWR_IORETENRB_EN12_Pos) /*!< 0x00001000 */ +#define PWR_IORETENRB_EN12 PWR_IORETENRB_EN12_Msk /*!< Standby GPIO retention enable for PB12 */ +#define PWR_IORETENRB_EN15_Pos (15U) +#define PWR_IORETENRB_EN15_Msk (0x1UL << PWR_IORETENRB_EN15_Pos) /*!< 0x00008000 */ +#define PWR_IORETENRB_EN15 PWR_IORETENRB_EN15_Msk /*!< Standby GPIO retention enable for PB15 */ + +/******************** Bit definition for PWR_IORETRB register *****************/ +#define PWR_IORETRB_RET3_Pos (3U) +#define PWR_IORETRB_RET3_Msk (0x1UL << PWR_IORETRB_RET3_Pos) /*!< 0x00000008 */ +#define PWR_IORETRB_RET3 PWR_IORETRB_RET3_Msk /*!< Standby GPIO retention status for PB3 */ +#define PWR_IORETRB_RET4_Pos (4U) +#define PWR_IORETRB_RET4_Msk (0x1UL << PWR_IORETRB_RET4_Pos) /*!< 0x00000010 */ +#define PWR_IORETRB_RET4 PWR_IORETRB_RET4_Msk /*!< Standby GPIO retention status for PB4 */ +#define PWR_IORETRB_RET8_Pos (8U) +#define PWR_IORETRB_RET8_Msk (0x1UL << PWR_IORETRB_RET8_Pos) /*!< 0x00000100 */ +#define PWR_IORETRB_RET8 PWR_IORETRB_RET8_Msk /*!< Standby GPIO retention status for PB8 */ +#define PWR_IORETRB_RET9_Pos (9U) +#define PWR_IORETRB_RET9_Msk (0x1UL << PWR_IORETRB_RET9_Pos) /*!< 0x00000200 */ +#define PWR_IORETRB_RET9 PWR_IORETRB_RET9_Msk /*!< Standby GPIO retention status for PB9 */ +#define PWR_IORETRB_RET12_Pos (12U) +#define PWR_IORETRB_RET12_Msk (0x1UL << PWR_IORETRB_RET12_Pos) /*!< 0x00001000 */ +#define PWR_IORETRB_RET12 PWR_IORETRB_RET12_Msk /*!< Standby GPIO retention status for PB12 */ +#define PWR_IORETRB_RET15_Pos (15U) +#define PWR_IORETRB_RET15_Msk (0x1UL << PWR_IORETRB_RET15_Pos) /*!< 0x00008000 */ +#define PWR_IORETRB_RET15 PWR_IORETRB_RET15_Msk /*!< Standby GPIO retention status for PB15 */ + +/******************** Bit definition for PWR_IORETENRC register *****************/ +#define PWR_IORETENRC_EN14_Pos (14U) +#define PWR_IORETENRC_EN14_Msk (0x1UL << PWR_IORETENRC_EN14_Pos) /*!< 0x00004000 */ +#define PWR_IORETENRC_EN14 PWR_IORETENRC_EN14_Msk /*!< Standby GPIO retention enable for PC14 */ +#define PWR_IORETENRC_EN15_Pos (15U) +#define PWR_IORETENRC_EN15_Msk (0x1UL << PWR_IORETENRC_EN15_Pos) /*!< 0x00008000 */ +#define PWR_IORETENRC_EN15 PWR_IORETENRC_EN15_Msk /*!< Standby GPIO retention enable for PC15 */ + +/******************** Bit definition for PWR_IORETRC register *****************/ +#define PWR_IORETRC_RET14_Pos (14U) +#define PWR_IORETRC_RET14_Msk (0x1UL << PWR_IORETRC_RET14_Pos) /*!< 0x00004000 */ +#define PWR_IORETRC_RET14 PWR_IORETRC_RET14_Msk /*!< Standby GPIO retention status for PC14 */ +#define PWR_IORETRC_RET15_Pos (15U) +#define PWR_IORETRC_RET15_Msk (0x1UL << PWR_IORETRC_RET15_Pos) /*!< 0x00008000 */ +#define PWR_IORETRC_RET15 PWR_IORETRC_RET15_Msk /*!< Standby GPIO retention status for PC15 */ + +/******************** Bit definition for PWR_IORETENRH register *****************/ +#define PWR_IORETENRH_EN3_Pos (3U) +#define PWR_IORETENRH_EN3_Msk (0x1UL << PWR_IORETENRH_EN3_Pos) /*!< 0x00000008 */ +#define PWR_IORETENRH_EN3 PWR_IORETENRH_EN3_Msk /*!< Standby GPIO retention enable for PH3 */ + +/******************** Bit definition for PWR_IORETRH register *****************/ +#define PWR_IORETRH_RET3_Pos (3U) +#define PWR_IORETRH_RET3_Msk (0x1UL << PWR_IORETRH_RET3_Pos) /*!< 0x00000008 */ +#define PWR_IORETRH_RET3 PWR_IORETRH_RET3_Msk /*!< Standby GPIO retention status for PH3 */ + +/******************** Bit definition for PWR_RADIOSCR register *****************/ +#define PWR_RADIOSCR_MODE_Pos (0U) +#define PWR_RADIOSCR_MODE_Msk (0x3UL << PWR_RADIOSCR_MODE_Pos) /*!< 0x00000003 */ +#define PWR_RADIOSCR_MODE PWR_RADIOSCR_MODE_Msk /*!< 2.4 GHz RADIO operating mode */ +#define PWR_RADIOSCR_MODE_0 (0x1UL << PWR_RADIOSCR_MODE_Pos) /*!< 0x00000001 */ +#define PWR_RADIOSCR_MODE_1 (0x2UL << PWR_RADIOSCR_MODE_Pos) /*!< 0x00000002 */ +#define PWR_RADIOSCR_PHYMODE_Pos (2U) +#define PWR_RADIOSCR_PHYMODE_Msk (0x1UL << PWR_RADIOSCR_PHYMODE_Pos) /*!< 0x00000004 */ +#define PWR_RADIOSCR_PHYMODE PWR_RADIOSCR_PHYMODE_Msk /*!< 2.4 GHz RADIO PHY operating mode */ +#define PWR_RADIOSCR_ENCMODE_Pos (3U) +#define PWR_RADIOSCR_ENCMODE_Msk (0x1UL << PWR_RADIOSCR_ENCMODE_Pos) /*!< 0x00000008 */ +#define PWR_RADIOSCR_ENCMODE PWR_RADIOSCR_ENCMODE_Msk /*!< 2.4 GHz RADIO encryption function operating mode */ +#define PWR_RADIOSCR_RFVDDHPA_Pos (8U) +#define PWR_RADIOSCR_RFVDDHPA_Msk (0x1FUL << PWR_RADIOSCR_RFVDDHPA_Pos) /*!< 0x00001F00 */ +#define PWR_RADIOSCR_RFVDDHPA PWR_RADIOSCR_RFVDDHPA_Msk /*!< 2.4 GHz RADIO VDDHPA control word */ +#define PWR_RADIOSCR_REGPARDYVDDRFPA_Pos (15U) +#define PWR_RADIOSCR_REGPARDYVDDRFPA_Msk (0x1UL << PWR_RADIOSCR_REGPARDYVDDRFPA_Pos) /*!< 0x00008000 */ +#define PWR_RADIOSCR_REGPARDYVDDRFPA PWR_RADIOSCR_REGPARDYVDDRFPA_Msk /*!< Ready bit for VDDHPA voltage level when selecting VDDRFPA input */ + + +/******************************************************************************/ +/* */ +/* SRAMs configuration controller */ +/* */ +/******************************************************************************/ +/******************* Bit definition for RAMCFG_MxCR register ******************/ +#define RAMCFG_CR_ALE_Pos (4U) +#define RAMCFG_CR_ALE_Msk (0x1UL << RAMCFG_CR_ALE_Pos) /*!< 0x00000010 */ +#define RAMCFG_CR_ALE RAMCFG_CR_ALE_Msk /*!< Address Latching Enable */ +#define RAMCFG_CR_SRAMER_Pos (8U) +#define RAMCFG_CR_SRAMER_Msk (0x1UL << RAMCFG_CR_SRAMER_Pos) /*!< 0x00000100 */ +#define RAMCFG_CR_SRAMER RAMCFG_CR_SRAMER_Msk /*!< Start Erase */ +#define RAMCFG_CR_WSC_Pos (16U) +#define RAMCFG_CR_WSC_Msk (0x7UL << RAMCFG_CR_WSC_Pos) /*!< 0x00070000 */ +#define RAMCFG_CR_WSC RAMCFG_CR_WSC_Msk /*!< WSC[18:16] Wait State Configuration field */ +#define RAMCFG_CR_WSC_0 (0x1UL << RAMCFG_CR_WSC_Pos) /*!< 0x00010000 */ +#define RAMCFG_CR_WSC_1 (0x2UL << RAMCFG_CR_WSC_Pos) /*!< 0x00020000 */ +#define RAMCFG_CR_WSC_2 (0x4UL << RAMCFG_CR_WSC_Pos) /*!< 0x00040000 */ + +/******************* Bit definition for RAMCFG_MxISR register ******************/ +#define RAMCFG_ISR_PED_Pos (1U) +#define RAMCFG_ISR_PED_Msk (0x1UL << RAMCFG_ISR_PED_Pos) /*!< 0x00000002 */ +#define RAMCFG_ISR_PED RAMCFG_ISR_PED_Msk /*!< Parity error detected */ +#define RAMCFG_ISR_SRAMBUSY_Pos (8U) +#define RAMCFG_ISR_SRAMBUSY_Msk (0x1UL << RAMCFG_ISR_SRAMBUSY_Pos) /*!< 0x00000100 */ +#define RAMCFG_ISR_SRAMBUSY RAMCFG_ISR_SRAMBUSY_Msk /*!< SRAM busy with erase operation */ + +/***************** Bit definition for RAMCFG_MxERKEYR register ***************/ +#define RAMCFG_ERKEYR_ERASEKEY_Pos (0U) +#define RAMCFG_ERKEYR_ERASEKEY_Msk (0xFFUL << RAMCFG_ERKEYR_ERASEKEY_Pos) /*!< 0x000000FF */ +#define RAMCFG_ERKEYR_ERASEKEY RAMCFG_ERKEYR_ERASEKEY_Msk /*!< Erase write protection key */ + +/******************* Bit definition for RAMCFG_MxIER register ******************/ +#define RAMCFG_IER_PEIE_Pos (1U) +#define RAMCFG_IER_PEIE_Msk (0x1UL << RAMCFG_IER_PEIE_Pos) /*!< 0x00000001 */ +#define RAMCFG_IER_PEIE RAMCFG_IER_PEIE_Msk /*!< Parity error interrupt enable */ +#define RAMCFG_IER_PENMI_Pos (3U) +#define RAMCFG_IER_PENMI_Msk (0x1UL << RAMCFG_IER_PENMI_Pos) /*!< 0x00000004 */ +#define RAMCFG_IER_PENMI RAMCFG_IER_PENMI_Msk /*!< Parity error NMI */ + +/******************* Bit definition for RAMCFG_MxPEAR register ******************/ +#define RAMCFG_PEAR_PEA_Pos (0U) +#define RAMCFG_PEAR_PEA_Msk (0xFFFFUL << RAMCFG_PEAR_PEA_Pos) /*!< 0x0000FFFF */ +#define RAMCFG_PEAR_PEA RAMCFG_PEAR_PEA_Msk /*!< Parity error SRAM word aligned address offset */ +#define RAMCFG_PEAR_ID_Pos (24U) +#define RAMCFG_PEAR_ID_Msk (0xFUL << RAMCFG_PEAR_ID_Pos) /*!< 0x0F000000 */ +#define RAMCFG_PEAR_ID RAMCFG_PEAR_ID_Msk /*!< Parity error AHB bus master ID */ +#define RAMCFG_PEAR_BYTE_Pos (28U) +#define RAMCFG_PEAR_BYTE_Msk (0xFUL << RAMCFG_PEAR_BYTE_Pos) /*!< 0xF0000000 */ +#define RAMCFG_PEAR_BYTE RAMCFG_PEAR_BYTE_Msk /*!< Byte parity error flag */ + +/******************* Bit definition for RAMCFG_MxICR register *****************/ +#define RAMCFG_ICR_CPED_Pos (1U) +#define RAMCFG_ICR_CPED_Msk (0x1UL << RAMCFG_ICR_CPED_Pos) /*!< 0x00000002 */ +#define RAMCFG_ICR_CPED RAMCFG_ICR_CPED_Msk /*!< Clear parity error detect bit */ + +/****************** Bit definition for RAMCFG_MxWPR1 register *****************/ +#define RAMCFG_WPR1_P0WP_Pos (0U) +#define RAMCFG_WPR1_P0WP_Msk (0x1UL << RAMCFG_WPR1_P0WP_Pos) /*!< 0x00000001 */ +#define RAMCFG_WPR1_P0WP RAMCFG_WPR1_P0WP_Msk /*!< Write Protection Page 00 */ +#define RAMCFG_WPR1_P1WP_Pos (1U) +#define RAMCFG_WPR1_P1WP_Msk (0x1UL << RAMCFG_WPR1_P1WP_Pos) /*!< 0x00000002 */ +#define RAMCFG_WPR1_P1WP RAMCFG_WPR1_P1WP_Msk /*!< Write Protection Page 01 */ +#define RAMCFG_WPR1_P2WP_Pos (2U) +#define RAMCFG_WPR1_P2WP_Msk (0x1UL << RAMCFG_WPR1_P2WP_Pos) /*!< 0x00000004 */ +#define RAMCFG_WPR1_P2WP RAMCFG_WPR1_P2WP_Msk /*!< Write Protection Page 02 */ +#define RAMCFG_WPR1_P3WP_Pos (3U) +#define RAMCFG_WPR1_P3WP_Msk (0x1UL << RAMCFG_WPR1_P3WP_Pos) /*!< 0x00000008 */ +#define RAMCFG_WPR1_P3WP RAMCFG_WPR1_P3WP_Msk /*!< Write Protection Page 03 */ +#define RAMCFG_WPR1_P4WP_Pos (4U) +#define RAMCFG_WPR1_P4WP_Msk (0x1UL << RAMCFG_WPR1_P4WP_Pos) /*!< 0x00000010 */ +#define RAMCFG_WPR1_P4WP RAMCFG_WPR1_P4WP_Msk /*!< Write Protection Page 04 */ +#define RAMCFG_WPR1_P5WP_Pos (5U) +#define RAMCFG_WPR1_P5WP_Msk (0x1UL << RAMCFG_WPR1_P5WP_Pos) /*!< 0x00000020 */ +#define RAMCFG_WPR1_P5WP RAMCFG_WPR1_P5WP_Msk /*!< Write Protection Page 05 */ +#define RAMCFG_WPR1_P6WP_Pos (6U) +#define RAMCFG_WPR1_P6WP_Msk (0x1UL << RAMCFG_WPR1_P6WP_Pos) /*!< 0x00000040 */ +#define RAMCFG_WPR1_P6WP RAMCFG_WPR1_P6WP_Msk /*!< Write Protection Page 06 */ +#define RAMCFG_WPR1_P7WP_Pos (7U) +#define RAMCFG_WPR1_P7WP_Msk (0x1UL << RAMCFG_WPR1_P7WP_Pos) /*!< 0x00000080 */ +#define RAMCFG_WPR1_P7WP RAMCFG_WPR1_P7WP_Msk /*!< Write Protection Page 07 */ +#define RAMCFG_WPR1_P8WP_Pos (8U) +#define RAMCFG_WPR1_P8WP_Msk (0x1UL << RAMCFG_WPR1_P8WP_Pos) /*!< 0x00000100 */ +#define RAMCFG_WPR1_P8WP RAMCFG_WPR1_P8WP_Msk /*!< Write Protection Page 08 */ +#define RAMCFG_WPR1_P9WP_Pos (9U) +#define RAMCFG_WPR1_P9WP_Msk (0x1UL << RAMCFG_WPR1_P9WP_Pos) /*!< 0x00000200 */ +#define RAMCFG_WPR1_P9WP RAMCFG_WPR1_P9WP_Msk /*!< Write Protection Page 09 */ +#define RAMCFG_WPR1_P10WP_Pos (10U) +#define RAMCFG_WPR1_P10WP_Msk (0x1UL << RAMCFG_WPR1_P10WP_Pos) /*!< 0x00000400 */ +#define RAMCFG_WPR1_P10WP RAMCFG_WPR1_P10WP_Msk /*!< Write Protection Page 10 */ +#define RAMCFG_WPR1_P11WP_Pos (11U) +#define RAMCFG_WPR1_P11WP_Msk (0x1UL << RAMCFG_WPR1_P11WP_Pos) /*!< 0x00000800 */ +#define RAMCFG_WPR1_P11WP RAMCFG_WPR1_P11WP_Msk /*!< Write Protection Page 11 */ +#define RAMCFG_WPR1_P12WP_Pos (12U) +#define RAMCFG_WPR1_P12WP_Msk (0x1UL << RAMCFG_WPR1_P12WP_Pos) /*!< 0x00001000 */ +#define RAMCFG_WPR1_P12WP RAMCFG_WPR1_P12WP_Msk /*!< Write Protection Page 12 */ +#define RAMCFG_WPR1_P13WP_Pos (13U) +#define RAMCFG_WPR1_P13WP_Msk (0x1UL << RAMCFG_WPR1_P13WP_Pos) /*!< 0x00002000 */ +#define RAMCFG_WPR1_P13WP RAMCFG_WPR1_P13WP_Msk /*!< Write Protection Page 13 */ +#define RAMCFG_WPR1_P14WP_Pos (14U) +#define RAMCFG_WPR1_P14WP_Msk (0x1UL << RAMCFG_WPR1_P14WP_Pos) /*!< 0x00004000 */ +#define RAMCFG_WPR1_P14WP RAMCFG_WPR1_P14WP_Msk /*!< Write Protection Page 14 */ +#define RAMCFG_WPR1_P15WP_Pos (15U) +#define RAMCFG_WPR1_P15WP_Msk (0x1UL << RAMCFG_WPR1_P15WP_Pos) /*!< 0x00008000 */ +#define RAMCFG_WPR1_P15WP RAMCFG_WPR1_P15WP_Msk /*!< Write Protection Page 15 */ +#define RAMCFG_WPR1_P16WP_Pos (16U) +#define RAMCFG_WPR1_P16WP_Msk (0x1UL << RAMCFG_WPR1_P16WP_Pos) /*!< 0x00010000 */ +#define RAMCFG_WPR1_P16WP RAMCFG_WPR1_P16WP_Msk /*!< Write Protection Page 16 */ +#define RAMCFG_WPR1_P17WP_Pos (17U) +#define RAMCFG_WPR1_P17WP_Msk (0x1UL << RAMCFG_WPR1_P17WP_Pos) /*!< 0x00020000 */ +#define RAMCFG_WPR1_P17WP RAMCFG_WPR1_P17WP_Msk /*!< Write Protection Page 17 */ +#define RAMCFG_WPR1_P18WP_Pos (18U) +#define RAMCFG_WPR1_P18WP_Msk (0x1UL << RAMCFG_WPR1_P18WP_Pos) /*!< 0x00040000 */ +#define RAMCFG_WPR1_P18WP RAMCFG_WPR1_P18WP_Msk /*!< Write Protection Page 18 */ +#define RAMCFG_WPR1_P19WP_Pos (19U) +#define RAMCFG_WPR1_P19WP_Msk (0x1UL << RAMCFG_WPR1_P19WP_Pos) /*!< 0x00080000 */ +#define RAMCFG_WPR1_P19WP RAMCFG_WPR1_P19WP_Msk /*!< Write Protection Page 19 */ +#define RAMCFG_WPR1_P20WP_Pos (20U) +#define RAMCFG_WPR1_P20WP_Msk (0x1UL << RAMCFG_WPR1_P20WP_Pos) /*!< 0x00100000 */ +#define RAMCFG_WPR1_P20WP RAMCFG_WPR1_P20WP_Msk /*!< Write Protection Page 20 */ +#define RAMCFG_WPR1_P21WP_Pos (21U) +#define RAMCFG_WPR1_P21WP_Msk (0x1UL << RAMCFG_WPR1_P21WP_Pos) /*!< 0x00200000 */ +#define RAMCFG_WPR1_P21WP RAMCFG_WPR1_P21WP_Msk /*!< Write Protection Page 21 */ +#define RAMCFG_WPR1_P22WP_Pos (22U) +#define RAMCFG_WPR1_P22WP_Msk (0x1UL << RAMCFG_WPR1_P22WP_Pos) /*!< 0x00400000 */ +#define RAMCFG_WPR1_P22WP RAMCFG_WPR1_P22WP_Msk /*!< Write Protection Page 22 */ +#define RAMCFG_WPR1_P23WP_Pos (23U) +#define RAMCFG_WPR1_P23WP_Msk (0x1UL << RAMCFG_WPR1_P23WP_Pos) /*!< 0x00800000 */ +#define RAMCFG_WPR1_P23WP RAMCFG_WPR1_P23WP_Msk /*!< Write Protection Page 23 */ +#define RAMCFG_WPR1_P24WP_Pos (24U) +#define RAMCFG_WPR1_P24WP_Msk (0x1UL << RAMCFG_WPR1_P24WP_Pos) /*!< 0x01000000 */ +#define RAMCFG_WPR1_P24WP RAMCFG_WPR1_P24WP_Msk /*!< Write Protection Page 24 */ +#define RAMCFG_WPR1_P25WP_Pos (25U) +#define RAMCFG_WPR1_P25WP_Msk (0x1UL << RAMCFG_WPR1_P25WP_Pos) /*!< 0x02000000 */ +#define RAMCFG_WPR1_P25WP RAMCFG_WPR1_P25WP_Msk /*!< Write Protection Page 25 */ +#define RAMCFG_WPR1_P26WP_Pos (26U) +#define RAMCFG_WPR1_P26WP_Msk (0x1UL << RAMCFG_WPR1_P26WP_Pos) /*!< 0x04000000 */ +#define RAMCFG_WPR1_P26WP RAMCFG_WPR1_P26WP_Msk /*!< Write Protection Page 26 */ +#define RAMCFG_WPR1_P27WP_Pos (27U) +#define RAMCFG_WPR1_P27WP_Msk (0x1UL << RAMCFG_WPR1_P27WP_Pos) /*!< 0x08000000 */ +#define RAMCFG_WPR1_P27WP RAMCFG_WPR1_P27WP_Msk /*!< Write Protection Page 27 */ +#define RAMCFG_WPR1_P28WP_Pos (28U) +#define RAMCFG_WPR1_P28WP_Msk (0x1UL << RAMCFG_WPR1_P28WP_Pos) /*!< 0x10000000 */ +#define RAMCFG_WPR1_P28WP RAMCFG_WPR1_P28WP_Msk /*!< Write Protection Page 28 */ +#define RAMCFG_WPR1_P29WP_Pos (29U) +#define RAMCFG_WPR1_P29WP_Msk (0x1UL << RAMCFG_WPR1_P29WP_Pos) /*!< 0x20000000 */ +#define RAMCFG_WPR1_P29WP RAMCFG_WPR1_P29WP_Msk /*!< Write Protection Page 29 */ +#define RAMCFG_WPR1_P30WP_Pos (30U) +#define RAMCFG_WPR1_P30WP_Msk (0x1UL << RAMCFG_WPR1_P30WP_Pos) /*!< 0x40000000 */ +#define RAMCFG_WPR1_P30WP RAMCFG_WPR1_P30WP_Msk /*!< Write Protection Page 30 */ +#define RAMCFG_WPR1_P31WP_Pos (31U) +#define RAMCFG_WPR1_P31WP_Msk (0x1UL << RAMCFG_WPR1_P31WP_Pos) /*!< 0x80000000 */ +#define RAMCFG_WPR1_P31WP RAMCFG_WPR1_P31WP_Msk /*!< Write Protection Page 31 */ + +/****************** Bit definition for RAMCFG_MxWPR2 register ****************/ +#define RAMCFG_WPR2_P32WP_Pos (0U) +#define RAMCFG_WPR2_P32WP_Msk (0x1UL << RAMCFG_WPR2_P32WP_Pos) /*!< 0x00000001 */ +#define RAMCFG_WPR2_P32WP RAMCFG_WPR2_P32WP_Msk /*!< Write Protection Page 32 */ +#define RAMCFG_WPR2_P33WP_Pos (1U) +#define RAMCFG_WPR2_P33WP_Msk (0x1UL << RAMCFG_WPR2_P33WP_Pos) /*!< 0x00000002 */ +#define RAMCFG_WPR2_P33WP RAMCFG_WPR2_P33WP_Msk /*!< Write Protection Page 33 */ +#define RAMCFG_WPR2_P34WP_Pos (2U) +#define RAMCFG_WPR2_P34WP_Msk (0x1UL << RAMCFG_WPR2_P34WP_Pos) /*!< 0x00000004 */ +#define RAMCFG_WPR2_P34WP RAMCFG_WPR2_P34WP_Msk /*!< Write Protection Page 34 */ +#define RAMCFG_WPR2_P35WP_Pos (3U) +#define RAMCFG_WPR2_P35WP_Msk (0x1UL << RAMCFG_WPR2_P35WP_Pos) /*!< 0x00000008 */ +#define RAMCFG_WPR2_P35WP RAMCFG_WPR2_P35WP_Msk /*!< Write Protection Page 35 */ +#define RAMCFG_WPR2_P36WP_Pos (4U) +#define RAMCFG_WPR2_P36WP_Msk (0x1UL << RAMCFG_WPR2_P36WP_Pos) /*!< 0x00000010 */ +#define RAMCFG_WPR2_P36WP RAMCFG_WPR2_P36WP_Msk /*!< Write Protection Page 36 */ +#define RAMCFG_WPR2_P37WP_Pos (5U) +#define RAMCFG_WPR2_P37WP_Msk (0x1UL << RAMCFG_WPR2_P37WP_Pos) /*!< 0x00000020 */ +#define RAMCFG_WPR2_P37WP RAMCFG_WPR2_P37WP_Msk /*!< Write Protection Page 37 */ +#define RAMCFG_WPR2_P38WP_Pos (6U) +#define RAMCFG_WPR2_P38WP_Msk (0x1UL << RAMCFG_WPR2_P38WP_Pos) /*!< 0x00000040 */ +#define RAMCFG_WPR2_P38WP RAMCFG_WPR2_P38WP_Msk /*!< Write Protection Page 38 */ +#define RAMCFG_WPR2_P39WP_Pos (7U) +#define RAMCFG_WPR2_P39WP_Msk (0x1UL << RAMCFG_WPR2_P39WP_Pos) /*!< 0x00000080 */ +#define RAMCFG_WPR2_P39WP RAMCFG_WPR2_P39WP_Msk /*!< Write Protection Page 39 */ +#define RAMCFG_WPR2_P40WP_Pos (8U) +#define RAMCFG_WPR2_P40WP_Msk (0x1UL << RAMCFG_WPR2_P40WP_Pos) /*!< 0x00000100 */ +#define RAMCFG_WPR2_P40WP RAMCFG_WPR2_P40WP_Msk /*!< Write Protection Page 40 */ +#define RAMCFG_WPR2_P41WP_Pos (9U) +#define RAMCFG_WPR2_P41WP_Msk (0x1UL << RAMCFG_WPR2_P41WP_Pos) /*!< 0x00000200 */ +#define RAMCFG_WPR2_P41WP RAMCFG_WPR2_P41WP_Msk /*!< Write Protection Page 41 */ +#define RAMCFG_WPR2_P42WP_Pos (10U) +#define RAMCFG_WPR2_P42WP_Msk (0x1UL << RAMCFG_WPR2_P42WP_Pos) /*!< 0x00000400 */ +#define RAMCFG_WPR2_P42WP RAMCFG_WPR2_P42WP_Msk /*!< Write Protection Page 42 */ +#define RAMCFG_WPR2_P43WP_Pos (11U) +#define RAMCFG_WPR2_P43WP_Msk (0x1UL << RAMCFG_WPR2_P43WP_Pos) /*!< 0x00000800 */ +#define RAMCFG_WPR2_P43WP RAMCFG_WPR2_P43WP_Msk /*!< Write Protection Page 43 */ +#define RAMCFG_WPR2_P44WP_Pos (12U) +#define RAMCFG_WPR2_P44WP_Msk (0x1UL << RAMCFG_WPR2_P44WP_Pos) /*!< 0x00001000 */ +#define RAMCFG_WPR2_P44WP RAMCFG_WPR2_P44WP_Msk /*!< Write Protection Page 44 */ +#define RAMCFG_WPR2_P45WP_Pos (13U) +#define RAMCFG_WPR2_P45WP_Msk (0x1UL << RAMCFG_WPR2_P45WP_Pos) /*!< 0x00002000 */ +#define RAMCFG_WPR2_P45WP RAMCFG_WPR2_P45WP_Msk /*!< Write Protection Page 45 */ +#define RAMCFG_WPR2_P46WP_Pos (14U) +#define RAMCFG_WPR2_P46WP_Msk (0x1UL << RAMCFG_WPR2_P46WP_Pos) /*!< 0x00004000 */ +#define RAMCFG_WPR2_P46WP RAMCFG_WPR2_P46WP_Msk /*!< Write Protection Page 46 */ +#define RAMCFG_WPR2_P47WP_Pos (15U) +#define RAMCFG_WPR2_P47WP_Msk (0x1UL << RAMCFG_WPR2_P47WP_Pos) /*!< 0x00008000 */ +#define RAMCFG_WPR2_P47WP RAMCFG_WPR2_P47WP_Msk /*!< Write Protection Page 47 */ +#define RAMCFG_WPR2_P48WP_Pos (16U) +#define RAMCFG_WPR2_P48WP_Msk (0x1UL << RAMCFG_WPR2_P48WP_Pos) /*!< 0x00010000 */ +#define RAMCFG_WPR2_P48WP RAMCFG_WPR2_P48WP_Msk /*!< Write Protection Page 48 */ +#define RAMCFG_WPR2_P49WP_Pos (17U) +#define RAMCFG_WPR2_P49WP_Msk (0x1UL << RAMCFG_WPR2_P49WP_Pos) /*!< 0x00020000 */ +#define RAMCFG_WPR2_P49WP RAMCFG_WPR2_P49WP_Msk /*!< Write Protection Page 49 */ +#define RAMCFG_WPR2_P50WP_Pos (18U) +#define RAMCFG_WPR2_P50WP_Msk (0x1UL << RAMCFG_WPR2_P50WP_Pos) /*!< 0x00040000 */ +#define RAMCFG_WPR2_P50WP RAMCFG_WPR2_P50WP_Msk /*!< Write Protection Page 50 */ +#define RAMCFG_WPR2_P51WP_Pos (19U) +#define RAMCFG_WPR2_P51WP_Msk (0x1UL << RAMCFG_WPR2_P51WP_Pos) /*!< 0x00080000 */ +#define RAMCFG_WPR2_P51WP RAMCFG_WPR2_P51WP_Msk /*!< Write Protection Page 51 */ +#define RAMCFG_WPR2_P52WP_Pos (20U) +#define RAMCFG_WPR2_P52WP_Msk (0x1UL << RAMCFG_WPR2_P52WP_Pos) /*!< 0x00100000 */ +#define RAMCFG_WPR2_P52WP RAMCFG_WPR2_P52WP_Msk /*!< Write Protection Page 52 */ +#define RAMCFG_WPR2_P53WP_Pos (21U) +#define RAMCFG_WPR2_P53WP_Msk (0x1UL << RAMCFG_WPR2_P53WP_Pos) /*!< 0x00200000 */ +#define RAMCFG_WPR2_P53WP RAMCFG_WPR2_P53WP_Msk /*!< Write Protection Page 53 */ +#define RAMCFG_WPR2_P54WP_Pos (22U) +#define RAMCFG_WPR2_P54WP_Msk (0x1UL << RAMCFG_WPR2_P54WP_Pos) /*!< 0x00400000 */ +#define RAMCFG_WPR2_P54WP RAMCFG_WPR2_P54WP_Msk /*!< Write Protection Page 54 */ +#define RAMCFG_WPR2_P55WP_Pos (23U) +#define RAMCFG_WPR2_P55WP_Msk (0x1UL << RAMCFG_WPR2_P55WP_Pos) /*!< 0x00800000 */ +#define RAMCFG_WPR2_P55WP RAMCFG_WPR2_P55WP_Msk /*!< Write Protection Page 55 */ +#define RAMCFG_WPR2_P56WP_Pos (25U) +#define RAMCFG_WPR2_P56WP_Msk (0x1UL << RAMCFG_WPR2_P56WP_Pos) /*!< 0x01000000 */ +#define RAMCFG_WPR2_P56WP RAMCFG_WPR2_P56WP_Msk /*!< Write Protection Page 56 */ +#define RAMCFG_WPR2_P57WP_Pos (26U) +#define RAMCFG_WPR2_P57WP_Msk (0x1UL << RAMCFG_WPR2_P57WP_Pos) /*!< 0x02000000 */ +#define RAMCFG_WPR2_P57WP RAMCFG_WPR2_P57WP_Msk /*!< Write Protection Page 57 */ +#define RAMCFG_WPR2_P58WP_Pos (27U) +#define RAMCFG_WPR2_P58WP_Msk (0x1UL << RAMCFG_WPR2_P58WP_Pos) /*!< 0x04000000 */ +#define RAMCFG_WPR2_P58WP RAMCFG_WPR2_P58WP_Msk /*!< Write Protection Page 58 */ +#define RAMCFG_WPR2_P59WP_Pos (28U) +#define RAMCFG_WPR2_P59WP_Msk (0x1UL << RAMCFG_WPR2_P59WP_Pos) /*!< 0x08000000 */ +#define RAMCFG_WPR2_P59WP RAMCFG_WPR2_P59WP_Msk /*!< Write Protection Page 59 */ +#define RAMCFG_WPR2_P60WP_Pos (29U) +#define RAMCFG_WPR2_P60WP_Msk (0x1UL << RAMCFG_WPR2_P60WP_Pos) /*!< 0x10000000 */ +#define RAMCFG_WPR2_P60WP RAMCFG_WPR2_P60WP_Msk /*!< Write Protection Page 60 */ +#define RAMCFG_WPR2_P61WP_Pos (30U) +#define RAMCFG_WPR2_P61WP_Msk (0x1UL << RAMCFG_WPR2_P61WP_Pos) /*!< 0x20000000 */ +#define RAMCFG_WPR2_P61WP RAMCFG_WPR2_P61WP_Msk /*!< Write Protection Page 61 */ +#define RAMCFG_WPR2_P62WP_Pos (31U) +#define RAMCFG_WPR2_P62WP_Msk (0x1UL << RAMCFG_WPR2_P62WP_Pos) /*!< 0x40000000 */ +#define RAMCFG_WPR2_P62WP RAMCFG_WPR2_P62WP_Msk /*!< Write Protection Page 62 */ +#define RAMCFG_WPR2_P63WP_Pos (31U) +#define RAMCFG_WPR2_P63WP_Msk (0x1UL << RAMCFG_WPR2_P63WP_Pos) /*!< 0x80000000 */ +#define RAMCFG_WPR2_P63WP RAMCFG_WPR2_P63WP_Msk /*!< Write Protection Page 63 */ + + +/******************************************************************************/ +/* */ +/* Reset and Clock Control */ +/* */ +/******************************************************************************/ +/******************** Bit definition for RCC_CR register ********************/ +#define RCC_CR_HSION_Pos (8U) +#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000100 */ +#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed oscillator (HSI16) clock enable */ +#define RCC_CR_HSIKERON_Pos (9U) +#define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos) /*!< 0x00000200 */ +#define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel */ +#define RCC_CR_HSIRDY_Pos (10U) +#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000400 */ +#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed oscillator (HSI16) clock ready flag */ +#define RCC_CR_HSEON_Pos (16U) +#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */ +#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed oscillator (HSE) clock enable */ +#define RCC_CR_HSERDY_Pos (17U) +#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */ +#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed oscillator (HSE) clock ready */ +#define RCC_CR_HSECSSON_Pos (19U) +#define RCC_CR_HSECSSON_Msk (0x1UL << RCC_CR_HSECSSON_Pos) /*!< 0x00080000 */ +#define RCC_CR_HSECSSON RCC_CR_HSECSSON_Msk /*!< External High Speed oscillator (HSE) clock security system enable */ +#define RCC_CR_HSEPRE_Pos (20U) +#define RCC_CR_HSEPRE_Msk (0x1UL << RCC_CR_HSEPRE_Pos) /*!< 0x00080000 */ +#define RCC_CR_HSEPRE RCC_CR_HSEPRE_Msk /*!< External High Speed oscillator (HSE) clock for sysclk prescaler */ +#define RCC_CR_PLL1ON_Pos (24U) +#define RCC_CR_PLL1ON_Msk (0x1UL << RCC_CR_PLL1ON_Pos) /*!< 0x01000000 */ +#define RCC_CR_PLL1ON RCC_CR_PLL1ON_Msk /*!< System PLL1 clock enable */ +#define RCC_CR_PLL1RDY_Pos (25U) +#define RCC_CR_PLL1RDY_Msk (0x1UL << RCC_CR_PLL1RDY_Pos) /*!< 0x02000000 */ +#define RCC_CR_PLL1RDY RCC_CR_PLL1RDY_Msk /*!< System PLL1 clock ready */ + +/******************** Bit definition for RCC_ICSCR3 register ***************/ +#define RCC_ICSCR3_HSICAL_Pos (0U) +#define RCC_ICSCR3_HSICAL_Msk (0xFFFUL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000FFF */ +#define RCC_ICSCR3_HSICAL RCC_ICSCR3_HSICAL_Msk /*!< HSICAL[11:0] bits */ +#define RCC_ICSCR3_HSICAL_0 (0x01UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000001 */ +#define RCC_ICSCR3_HSICAL_1 (0x002UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000002 */ +#define RCC_ICSCR3_HSICAL_2 (0x004UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000004 */ +#define RCC_ICSCR3_HSICAL_3 (0x008UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000008 */ +#define RCC_ICSCR3_HSICAL_4 (0x010UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000010 */ +#define RCC_ICSCR3_HSICAL_5 (0x020UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000020 */ +#define RCC_ICSCR3_HSICAL_6 (0x040UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000040 */ +#define RCC_ICSCR3_HSICAL_7 (0x080UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000080 */ +#define RCC_ICSCR3_HSICAL_8 (0x100UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000100 */ +#define RCC_ICSCR3_HSICAL_9 (0x200UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000200 */ +#define RCC_ICSCR3_HSICAL_10 (0x400UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000400 */ +#define RCC_ICSCR3_HSICAL_11 (0x800UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000800 */ +#define RCC_ICSCR3_HSITRIM_Pos (16U) +#define RCC_ICSCR3_HSITRIM_Msk (0x1FUL << RCC_ICSCR3_HSITRIM_Pos) /*!< 0x001F0000 */ +#define RCC_ICSCR3_HSITRIM RCC_ICSCR3_HSITRIM_Msk /*!< HSITRIM[4:0] bits */ +#define RCC_ICSCR3_HSITRIM_0 (0x01UL << RCC_ICSCR3_HSITRIM_Pos) /*!< 0x00010000 */ +#define RCC_ICSCR3_HSITRIM_1 (0x02UL << RCC_ICSCR3_HSITRIM_Pos) /*!< 0x00020000 */ +#define RCC_ICSCR3_HSITRIM_2 (0x04UL << RCC_ICSCR3_HSITRIM_Pos) /*!< 0x00040000 */ +#define RCC_ICSCR3_HSITRIM_3 (0x08UL << RCC_ICSCR3_HSITRIM_Pos) /*!< 0x00080000 */ +#define RCC_ICSCR3_HSITRIM_4 (0x10UL << RCC_ICSCR3_HSITRIM_Pos) /*!< 0x00100000 */ + +/******************** Bit definition for RCC_CFGR1 register *****************/ +#define RCC_CFGR1_SW_Pos (0U) +#define RCC_CFGR1_SW_Msk (0x3UL << RCC_CFGR1_SW_Pos) /*!< 0x00000003 */ +#define RCC_CFGR1_SW RCC_CFGR1_SW_Msk /*!< SW[1:0] bits (System clock Switch) */ +#define RCC_CFGR1_SW_0 (0x1UL << RCC_CFGR1_SW_Pos) /*!< 0x00000001 */ +#define RCC_CFGR1_SW_1 (0x2UL << RCC_CFGR1_SW_Pos) /*!< 0x00000002 */ +#define RCC_CFGR1_SWS_Pos (2U) +#define RCC_CFGR1_SWS_Msk (0x3UL << RCC_CFGR1_SWS_Pos) /*!< 0x0000000C */ +#define RCC_CFGR1_SWS RCC_CFGR1_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */ +#define RCC_CFGR1_SWS_0 (0x1UL << RCC_CFGR1_SWS_Pos) /*!< 0x00000004 */ +#define RCC_CFGR1_SWS_1 (0x2UL << RCC_CFGR1_SWS_Pos) /*!< 0x00000008 */ +#define RCC_CFGR1_MCOSEL_Pos (24U) +#define RCC_CFGR1_MCOSEL_Msk (0xFUL << RCC_CFGR1_MCOSEL_Pos) /*!< 0x0F000000 */ +#define RCC_CFGR1_MCOSEL RCC_CFGR1_MCOSEL_Msk /*!< MCOSEL[3:0] bits (Clock output selection) */ +#define RCC_CFGR1_MCOSEL_0 (0x1UL << RCC_CFGR1_MCOSEL_Pos) /*!< 0x01000000 */ +#define RCC_CFGR1_MCOSEL_1 (0x2UL << RCC_CFGR1_MCOSEL_Pos) /*!< 0x02000000 */ +#define RCC_CFGR1_MCOSEL_2 (0x4UL << RCC_CFGR1_MCOSEL_Pos) /*!< 0x04000000 */ +#define RCC_CFGR1_MCOSEL_3 (0x8UL << RCC_CFGR1_MCOSEL_Pos) /*!< 0x08000000 */ +#define RCC_CFGR1_MCOPRE_Pos (28U) +#define RCC_CFGR1_MCOPRE_Msk (0x7UL << RCC_CFGR1_MCOPRE_Pos) /*!< 0x70000000 */ +#define RCC_CFGR1_MCOPRE RCC_CFGR1_MCOPRE_Msk /*!< MCO[220] (Prescaler) */ +#define RCC_CFGR1_MCOPRE_0 (0x1UL << RCC_CFGR1_MCOPRE_Pos) /*!< 0x10000000 */ +#define RCC_CFGR1_MCOPRE_1 (0x2UL << RCC_CFGR1_MCOPRE_Pos) /*!< 0x20000000 */ +#define RCC_CFGR1_MCOPRE_2 (0x4UL << RCC_CFGR1_MCOPRE_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for RCC_CFGR2 register ******************/ +#define RCC_CFGR2_HPRE_Pos (0U) +#define RCC_CFGR2_HPRE_Msk (0x7UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000007 */ +#define RCC_CFGR2_HPRE RCC_CFGR2_HPRE_Msk /*!< HPRE[2:0] bits (AHB prescaler) */ +#define RCC_CFGR2_HPRE_0 (0x1UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000001 */ +#define RCC_CFGR2_HPRE_1 (0x2UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000002 */ +#define RCC_CFGR2_HPRE_2 (0x4UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000004 */ +#define RCC_CFGR2_PPRE1_Pos (4U) +#define RCC_CFGR2_PPRE1_Msk (0x7UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000070 */ +#define RCC_CFGR2_PPRE1 RCC_CFGR2_PPRE1_Msk /*!< PPRE1[2:0] bits (APB1 prescaler) */ +#define RCC_CFGR2_PPRE1_0 (0x1UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000010 */ +#define RCC_CFGR2_PPRE1_1 (0x2UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000020 */ +#define RCC_CFGR2_PPRE1_2 (0x4UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000040 */ +#define RCC_CFGR2_PPRE2_Pos (8U) +#define RCC_CFGR2_PPRE2_Msk (0x7UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000700 */ +#define RCC_CFGR2_PPRE2 RCC_CFGR2_PPRE2_Msk /*!< PPRE2[2:0] bits (APB2 prescaler) */ +#define RCC_CFGR2_PPRE2_0 (0x1UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000100 */ +#define RCC_CFGR2_PPRE2_1 (0x2UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000200 */ +#define RCC_CFGR2_PPRE2_2 (0x4UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000400 */ + +/******************** Bit definition for RCC_CFGR3 register ******************/ +#define RCC_CFGR3_PPRE7_Pos (4U) +#define RCC_CFGR3_PPRE7_Msk (0x7UL << RCC_CFGR3_PPRE7_Pos) /*!< 0x00000070 */ +#define RCC_CFGR3_PPRE7 RCC_CFGR3_PPRE7_Msk /*!< PPRE7[2:0] bits (APB7 prescaler) */ +#define RCC_CFGR3_PPRE7_0 (0x1UL << RCC_CFGR3_PPRE7_Pos) /*!< 0x00000010 */ +#define RCC_CFGR3_PPRE7_1 (0x2UL << RCC_CFGR3_PPRE7_Pos) /*!< 0x00000020 */ +#define RCC_CFGR3_PPRE7_2 (0x4UL << RCC_CFGR3_PPRE7_Pos) /*!< 0x00000040 */ + +/******************** Bit definition for RCC_PLL1CFGR register ***************/ +#define RCC_PLL1CFGR_PLL1SRC_Pos (0U) +#define RCC_PLL1CFGR_PLL1SRC_Msk (0x3UL << RCC_PLL1CFGR_PLL1SRC_Pos) /*!< 0x00000003 */ +#define RCC_PLL1CFGR_PLL1SRC RCC_PLL1CFGR_PLL1SRC_Msk +#define RCC_PLL1CFGR_PLL1SRC_0 (0x1UL << RCC_PLL1CFGR_PLL1SRC_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CFGR_PLL1SRC_1 (0x2UL << RCC_PLL1CFGR_PLL1SRC_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CFGR_PLL1RGE_Pos (2U) +#define RCC_PLL1CFGR_PLL1RGE_Msk (0x3UL << RCC_PLL1CFGR_PLL1RGE_Pos) /*!< 0x0000000C */ +#define RCC_PLL1CFGR_PLL1RGE RCC_PLL1CFGR_PLL1RGE_Msk +#define RCC_PLL1CFGR_PLL1RGE_0 (0x1UL << RCC_PLL1CFGR_PLL1RGE_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CFGR_PLL1RGE_1 (0x2UL << RCC_PLL1CFGR_PLL1RGE_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CFGR_PLL1FRACEN_Pos (4U) +#define RCC_PLL1CFGR_PLL1FRACEN_Msk (0x1UL << RCC_PLL1CFGR_PLL1FRACEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CFGR_PLL1FRACEN RCC_PLL1CFGR_PLL1FRACEN_Msk +#define RCC_PLL1CFGR_PLL1M_Pos (8U) +#define RCC_PLL1CFGR_PLL1M_Msk (0x7UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00000700 */ +#define RCC_PLL1CFGR_PLL1M RCC_PLL1CFGR_PLL1M_Msk +#define RCC_PLL1CFGR_PLL1M_0 (0x01UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CFGR_PLL1M_1 (0x02UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00000200 */ +#define RCC_PLL1CFGR_PLL1M_2 (0x04UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00000400 */ +#define RCC_PLL1CFGR_PLL1PEN_Pos (16U) +#define RCC_PLL1CFGR_PLL1PEN_Msk (0x1UL << RCC_PLL1CFGR_PLL1PEN_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CFGR_PLL1PEN RCC_PLL1CFGR_PLL1PEN_Msk +#define RCC_PLL1CFGR_PLL1QEN_Pos (17U) +#define RCC_PLL1CFGR_PLL1QEN_Msk (0x1UL << RCC_PLL1CFGR_PLL1QEN_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CFGR_PLL1QEN RCC_PLL1CFGR_PLL1QEN_Msk +#define RCC_PLL1CFGR_PLL1REN_Pos (18U) +#define RCC_PLL1CFGR_PLL1REN_Msk (0x1UL << RCC_PLL1CFGR_PLL1REN_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CFGR_PLL1REN RCC_PLL1CFGR_PLL1REN_Msk +#define RCC_PLL1CFGR_PLL1RCLKPRE_Pos (20U) +#define RCC_PLL1CFGR_PLL1RCLKPRE_Msk (0x1UL << RCC_PLL1CFGR_PLL1RCLKPRE_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CFGR_PLL1RCLKPRE RCC_PLL1CFGR_PLL1RCLKPRE_Msk +#define RCC_PLL1CFGR_PLL1RCLKPRESTEP_Pos (21U) +#define RCC_PLL1CFGR_PLL1RCLKPRESTEP_Msk (0x1UL << RCC_PLL1CFGR_PLL1RCLKPRESTEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL1CFGR_PLL1RCLKPRESTEP RCC_PLL1CFGR_PLL1RCLKPRESTEP_Msk +#define RCC_PLL1CFGR_PLL1RCLKPRERDY_Pos (22U) +#define RCC_PLL1CFGR_PLL1RCLKPRERDY_Msk (0x1UL << RCC_PLL1CFGR_PLL1RCLKPRERDY_Pos) /*!< 0x00400000 */ +#define RCC_PLL1CFGR_PLL1RCLKPRERDY RCC_PLL1CFGR_PLL1RCLKPRERDY_Msk + +/******************** Bit definition for RCC_PLL1DIVR register ***************/ +#define RCC_PLL1DIVR_PLL1N_Pos (0U) +#define RCC_PLL1DIVR_PLL1N_Msk (0x1FFUL << RCC_PLL1DIVR_PLL1N_Pos) /*!< 0x000001FF */ +#define RCC_PLL1DIVR_PLL1N RCC_PLL1DIVR_PLL1N_Msk +#define RCC_PLL1DIVR_PLL1N_0 (0x001UL << RCC_PLL1DIVR_PLL1N_Pos) /*!< 0x00000001 */ +#define RCC_PLL1DIVR_PLL1N_1 (0x002UL << RCC_PLL1DIVR_PLL1N_Pos) /*!< 0x00000002 */ +#define RCC_PLL1DIVR_PLL1N_2 (0x004UL << RCC_PLL1DIVR_PLL1N_Pos) /*!< 0x00000004 */ +#define RCC_PLL1DIVR_PLL1N_3 (0x008UL << RCC_PLL1DIVR_PLL1N_Pos) /*!< 0x00000008 */ +#define RCC_PLL1DIVR_PLL1N_4 (0x010UL << RCC_PLL1DIVR_PLL1N_Pos) /*!< 0x00000010 */ +#define RCC_PLL1DIVR_PLL1N_5 (0x020UL << RCC_PLL1DIVR_PLL1N_Pos) /*!< 0x00000020 */ +#define RCC_PLL1DIVR_PLL1N_6 (0x040UL << RCC_PLL1DIVR_PLL1N_Pos) /*!< 0x00000040 */ +#define RCC_PLL1DIVR_PLL1N_7 (0x080UL << RCC_PLL1DIVR_PLL1N_Pos) /*!< 0x00000080 */ +#define RCC_PLL1DIVR_PLL1N_8 (0x100UL << RCC_PLL1DIVR_PLL1N_Pos) /*!< 0x00000100 */ +#define RCC_PLL1DIVR_PLL1P_Pos (9U) +#define RCC_PLL1DIVR_PLL1P_Msk (0x7FUL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x0000FE00 */ +#define RCC_PLL1DIVR_PLL1P RCC_PLL1DIVR_PLL1P_Msk +#define RCC_PLL1DIVR_PLL1P_0 (0x01UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00000200 */ +#define RCC_PLL1DIVR_PLL1P_1 (0x02UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00000400 */ +#define RCC_PLL1DIVR_PLL1P_2 (0x04UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00000800 */ +#define RCC_PLL1DIVR_PLL1P_3 (0x08UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00001000 */ +#define RCC_PLL1DIVR_PLL1P_4 (0x10UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00002000 */ +#define RCC_PLL1DIVR_PLL1P_5 (0x20UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00004000 */ +#define RCC_PLL1DIVR_PLL1P_6 (0x40UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00008000 */ +#define RCC_PLL1DIVR_PLL1Q_Pos (16U) +#define RCC_PLL1DIVR_PLL1Q_Msk (0x7FUL << RCC_PLL1DIVR_PLL1Q_Pos) /*!< 0x007F0000 */ +#define RCC_PLL1DIVR_PLL1Q RCC_PLL1DIVR_PLL1Q_Msk +#define RCC_PLL1DIVR_PLL1Q_0 (0x01UL << RCC_PLL1DIVR_PLL1Q_Pos) /*!< 0x00010000 */ +#define RCC_PLL1DIVR_PLL1Q_1 (0x02UL << RCC_PLL1DIVR_PLL1Q_Pos) /*!< 0x00020000 */ +#define RCC_PLL1DIVR_PLL1Q_2 (0x04UL << RCC_PLL1DIVR_PLL1Q_Pos) /*!< 0x00040000 */ +#define RCC_PLL1DIVR_PLL1Q_3 (0x08UL << RCC_PLL1DIVR_PLL1Q_Pos) /*!< 0x00080000 */ +#define RCC_PLL1DIVR_PLL1Q_4 (0x10UL << RCC_PLL1DIVR_PLL1Q_Pos) /*!< 0x00100000 */ +#define RCC_PLL1DIVR_PLL1Q_5 (0x20UL << RCC_PLL1DIVR_PLL1Q_Pos) /*!< 0x00200020 */ +#define RCC_PLL1DIVR_PLL1Q_6 (0x40UL << RCC_PLL1DIVR_PLL1Q_Pos) /*!< 0x00400000 */ +#define RCC_PLL1DIVR_PLL1R_Pos (24U) +#define RCC_PLL1DIVR_PLL1R_Msk (0x7FUL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x7F000000 */ +#define RCC_PLL1DIVR_PLL1R RCC_PLL1DIVR_PLL1R_Msk +#define RCC_PLL1DIVR_PLL1R_0 (0x01UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x01000000 */ +#define RCC_PLL1DIVR_PLL1R_1 (0x02UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x02000000 */ +#define RCC_PLL1DIVR_PLL1R_2 (0x04UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x04000000 */ +#define RCC_PLL1DIVR_PLL1R_3 (0x08UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x08000000 */ +#define RCC_PLL1DIVR_PLL1R_4 (0x10UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x10000000 */ +#define RCC_PLL1DIVR_PLL1R_5 (0x20UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x20000000 */ +#define RCC_PLL1DIVR_PLL1R_6 (0x40UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for RCC_PLL1FRACR register ***************/ +#define RCC_PLL1FRACR_PLL1FRACN_Pos (3U) +#define RCC_PLL1FRACR_PLL1FRACN_Msk (0x1FFFUL << RCC_PLL1FRACR_PLL1FRACN_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL1FRACR_PLL1FRACN RCC_PLL1FRACR_PLL1FRACN_Msk + +/******************** Bit definition for RCC_CIER register ******************/ +#define RCC_CIER_LSI1RDYIE_Pos (0U) +#define RCC_CIER_LSI1RDYIE_Msk (0x1UL << RCC_CIER_LSI1RDYIE_Pos) /*!< 0x00000001 */ +#define RCC_CIER_LSI1RDYIE RCC_CIER_LSI1RDYIE_Msk +#define RCC_CIER_LSERDYIE_Pos (1U) +#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk +#define RCC_CIER_HSIRDYIE_Pos (3U) +#define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000008 */ +#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk +#define RCC_CIER_HSERDYIE_Pos (4U) +#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000010 */ +#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk +#define RCC_CIER_PLL1RDYIE_Pos (6U) +#define RCC_CIER_PLL1RDYIE_Msk (0x1UL << RCC_CIER_PLL1RDYIE_Pos) /*!< 0x00000040 */ +#define RCC_CIER_PLL1RDYIE RCC_CIER_PLL1RDYIE_Msk + +/******************** Bit definition for RCC_CIFR register ****************/ +#define RCC_CIFR_LSI1RDYF_Pos (0U) +#define RCC_CIFR_LSI1RDYF_Msk (0x1UL << RCC_CIFR_LSI1RDYF_Pos) /*!< 0x00000001 */ +#define RCC_CIFR_LSI1RDYF RCC_CIFR_LSI1RDYF_Msk +#define RCC_CIFR_LSERDYF_Pos (1U) +#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk +#define RCC_CIFR_HSIRDYF_Pos (3U) +#define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000008 */ +#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk +#define RCC_CIFR_HSERDYF_Pos (4U) +#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000010 */ +#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk +#define RCC_CIFR_PLL1RDYF_Pos (6U) +#define RCC_CIFR_PLL1RDYF_Msk (0x1UL << RCC_CIFR_PLL1RDYF_Pos) /*!< 0x00000040 */ +#define RCC_CIFR_PLL1RDYF RCC_CIFR_PLL1RDYF_Msk +#define RCC_CIFR_HSECSSF_Pos (10U) +#define RCC_CIFR_HSECSSF_Msk (0x1UL << RCC_CIFR_HSECSSF_Pos) /*!< 0x00000400 */ +#define RCC_CIFR_HSECSSF RCC_CIFR_HSECSSF_Msk + +/******************** Bit definition for RCC_CICR register ****************/ +#define RCC_CICR_LSI1RDYC_Pos (0U) +#define RCC_CICR_LSI1RDYC_Msk (0x1UL << RCC_CICR_LSI1RDYC_Pos) /*!< 0x00000001 */ +#define RCC_CICR_LSI1RDYC RCC_CICR_LSI1RDYC_Msk +#define RCC_CICR_LSERDYC_Pos (1U) +#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */ +#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk +#define RCC_CICR_HSIRDYC_Pos (3U) +#define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000008 */ +#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk +#define RCC_CICR_HSERDYC_Pos (4U) +#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000010 */ +#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk +#define RCC_CICR_PLL1RDYC_Pos (6U) +#define RCC_CICR_PLL1RDYC_Msk (0x1UL << RCC_CICR_PLL1RDYC_Pos) /*!< 0x00000040 */ +#define RCC_CICR_PLL1RDYC RCC_CICR_PLL1RDYC_Msk +#define RCC_CICR_HSECSSC_Pos (10U) +#define RCC_CICR_HSECSSC_Msk (0x1UL << RCC_CICR_HSECSSC_Pos) /*!< 0x00000400 */ +#define RCC_CICR_HSECSSC RCC_CICR_HSECSSC_Msk + +/******************** Bit definition for RCC_AHB1RSTR register **************/ +#define RCC_AHB1RSTR_GPDMA1RST_Pos (0U) +#define RCC_AHB1RSTR_GPDMA1RST_Msk (0x1UL << RCC_AHB1RSTR_GPDMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB1RSTR_GPDMA1RST RCC_AHB1RSTR_GPDMA1RST_Msk +#define RCC_AHB1RSTR_CRCRST_Pos (12U) +#define RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk +#define RCC_AHB1RSTR_TSCRST_Pos (16U) +#define RCC_AHB1RSTR_TSCRST_Msk (0x1UL << RCC_AHB1RSTR_TSCRST_Pos) /*!< 0x00010000 */ +#define RCC_AHB1RSTR_TSCRST RCC_AHB1RSTR_TSCRST_Msk + +/******************** Bit definition for RCC_AHB2RSTR register **************/ +#define RCC_AHB2RSTR_GPIOARST_Pos (0U) +#define RCC_AHB2RSTR_GPIOARST_Msk (0x1UL << RCC_AHB2RSTR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB2RSTR_GPIOARST RCC_AHB2RSTR_GPIOARST_Msk +#define RCC_AHB2RSTR_GPIOBRST_Pos (1U) +#define RCC_AHB2RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB2RSTR_GPIOBRST RCC_AHB2RSTR_GPIOBRST_Msk +#define RCC_AHB2RSTR_GPIOCRST_Pos (2U) +#define RCC_AHB2RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB2RSTR_GPIOCRST RCC_AHB2RSTR_GPIOCRST_Msk +#define RCC_AHB2RSTR_GPIOHRST_Pos (7U) +#define RCC_AHB2RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB2RSTR_GPIOHRST RCC_AHB2RSTR_GPIOHRST_Msk +#define RCC_AHB2RSTR_AESRST_Pos (16U) +#define RCC_AHB2RSTR_AESRST_Msk (0x1UL << RCC_AHB2RSTR_AESRST_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTR_AESRST RCC_AHB2RSTR_AESRST_Msk +#define RCC_AHB2RSTR_HASHRST_Pos (17U) +#define RCC_AHB2RSTR_HASHRST_Msk (0x1UL << RCC_AHB2RSTR_HASHRST_Pos) /*!< 0x00020000 */ +#define RCC_AHB2RSTR_HASHRST RCC_AHB2RSTR_HASHRST_Msk +#define RCC_AHB2RSTR_RNGRST_Pos (18U) +#define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00040000 */ +#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk +#define RCC_AHB2RSTR_HSEMRST_Pos (20U) +#define RCC_AHB2RSTR_HSEMRST_Msk (0x1UL << RCC_AHB2RSTR_HSEMRST_Pos) /*!< 0x00100000 */ +#define RCC_AHB2RSTR_HSEMRST RCC_AHB2RSTR_HSEMRST_Msk +#define RCC_AHB2RSTR_PKARST_Pos (21U) +#define RCC_AHB2RSTR_PKARST_Msk (0x1UL << RCC_AHB2RSTR_PKARST_Pos) /*!< 0x00200000 */ +#define RCC_AHB2RSTR_PKARST RCC_AHB2RSTR_PKARST_Msk + +/******************** Bit definition for RCC_AHB4RSTR register **************/ +#define RCC_AHB4RSTR_ADC4RST_Pos (5U) +#define RCC_AHB4RSTR_ADC4RST_Msk (0x1UL << RCC_AHB4RSTR_ADC4RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB4RSTR_ADC4RST RCC_AHB4RSTR_ADC4RST_Msk + +/******************** Bit definition for RCC_AHB5RSTR register **************/ +#define RCC_AHB5RSTR_RADIORST_Pos (0U) +#define RCC_AHB5RSTR_RADIORST_Msk (0x1UL << RCC_AHB5RSTR_RADIORST_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTR_RADIORST RCC_AHB5RSTR_RADIORST_Msk + +/******************** Bit definition for RCC_APB1RSTR1 register **************/ +#define RCC_APB1RSTR1_TIM2RST_Pos (0U) +#define RCC_APB1RSTR1_TIM2RST_Msk (0x1UL << RCC_APB1RSTR1_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTR1_TIM2RST RCC_APB1RSTR1_TIM2RST_Msk + +/******************** Bit definition for RCC_APB2RSTR register **************/ +#define RCC_APB2RSTR_TIM1RST_Pos (11U) +#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */ +#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk +#define RCC_APB2RSTR_USART1RST_Pos (14U) +#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ +#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk +#define RCC_APB2RSTR_TIM16RST_Pos (17U) +#define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk + +/******************** Bit definition for RCC_APB7RSTR register **************/ +#define RCC_APB7RSTR_SYSCFGRST_Pos (1U) +#define RCC_APB7RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB7RSTR_SYSCFGRST_Pos) /*!< 0x00000002 */ +#define RCC_APB7RSTR_SYSCFGRST RCC_APB7RSTR_SYSCFGRST_Msk +#define RCC_APB7RSTR_SPI3RST_Pos (5U) +#define RCC_APB7RSTR_SPI3RST_Msk (0x1UL << RCC_APB7RSTR_SPI3RST_Pos) /*!< 0x00000020 */ +#define RCC_APB7RSTR_SPI3RST RCC_APB7RSTR_SPI3RST_Msk +#define RCC_APB7RSTR_LPUART1RST_Pos (6U) +#define RCC_APB7RSTR_LPUART1RST_Msk (0x1UL << RCC_APB7RSTR_LPUART1RST_Pos) /*!< 0x00000040 */ +#define RCC_APB7RSTR_LPUART1RST RCC_APB7RSTR_LPUART1RST_Msk +#define RCC_APB7RSTR_I2C3RST_Pos (7U) +#define RCC_APB7RSTR_I2C3RST_Msk (0x1UL << RCC_APB7RSTR_I2C3RST_Pos) /*!< 0x00000080 */ +#define RCC_APB7RSTR_I2C3RST RCC_APB7RSTR_I2C3RST_Msk +#define RCC_APB7RSTR_LPTIM1RST_Pos (11U) +#define RCC_APB7RSTR_LPTIM1RST_Msk (0x1UL << RCC_APB7RSTR_LPTIM1RST_Pos) /*!< 0x00000800 */ +#define RCC_APB7RSTR_LPTIM1RST RCC_APB7RSTR_LPTIM1RST_Msk + +/******************** Bit definition for RCC_AHB1ENR register **************/ +#define RCC_AHB1ENR_GPDMA1EN_Pos (0U) +#define RCC_AHB1ENR_GPDMA1EN_Msk (0x1UL << RCC_AHB1ENR_GPDMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_AHB1ENR_GPDMA1EN RCC_AHB1ENR_GPDMA1EN_Msk +#define RCC_AHB1ENR_FLASHEN_Pos (8U) +#define RCC_AHB1ENR_FLASHEN_Msk (0x1UL << RCC_AHB1ENR_FLASHEN_Pos) /*!< 0x00000100 */ +#define RCC_AHB1ENR_FLASHEN RCC_AHB1ENR_FLASHEN_Msk +#define RCC_AHB1ENR_CRCEN_Pos (12U) +#define RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */ +#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk +#define RCC_AHB1ENR_TSCEN_Pos (16U) +#define RCC_AHB1ENR_TSCEN_Msk (0x1UL << RCC_AHB1ENR_TSCEN_Pos) /*!< 0x00010000 */ +#define RCC_AHB1ENR_TSCEN RCC_AHB1ENR_TSCEN_Msk +#define RCC_AHB1ENR_RAMCFGEN_Pos (17U) +#define RCC_AHB1ENR_RAMCFGEN_Msk (0x1UL << RCC_AHB1ENR_RAMCFGEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB1ENR_RAMCFGEN RCC_AHB1ENR_RAMCFGEN_Msk +#define RCC_AHB1ENR_SRAM1EN_Pos (31U) +#define RCC_AHB1ENR_SRAM1EN_Msk (0x1UL << RCC_AHB1ENR_SRAM1EN_Pos) /*!< 0x80000000 */ +#define RCC_AHB1ENR_SRAM1EN RCC_AHB1ENR_SRAM1EN_Msk + +/******************** Bit definition for RCC_AHB2ENR register **************/ +#define RCC_AHB2ENR_GPIOAEN_Pos (0U) +#define RCC_AHB2ENR_GPIOAEN_Msk (0x1UL << RCC_AHB2ENR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB2ENR_GPIOAEN RCC_AHB2ENR_GPIOAEN_Msk +#define RCC_AHB2ENR_GPIOBEN_Pos (1U) +#define RCC_AHB2ENR_GPIOBEN_Msk (0x1UL << RCC_AHB2ENR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB2ENR_GPIOBEN RCC_AHB2ENR_GPIOBEN_Msk +#define RCC_AHB2ENR_GPIOCEN_Pos (2U) +#define RCC_AHB2ENR_GPIOCEN_Msk (0x1UL << RCC_AHB2ENR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB2ENR_GPIOCEN RCC_AHB2ENR_GPIOCEN_Msk +#define RCC_AHB2ENR_GPIOHEN_Pos (7U) +#define RCC_AHB2ENR_GPIOHEN_Msk (0x1UL << RCC_AHB2ENR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_AHB2ENR_GPIOHEN RCC_AHB2ENR_GPIOHEN_Msk +#define RCC_AHB2ENR_AESEN_Pos (16U) +#define RCC_AHB2ENR_AESEN_Msk (0x1UL << RCC_AHB2ENR_AESEN_Pos) /*!< 0x00010000 */ +#define RCC_AHB2ENR_AESEN RCC_AHB2ENR_AESEN_Msk +#define RCC_AHB2ENR_HASHEN_Pos (17U) +#define RCC_AHB2ENR_HASHEN_Msk (0x1UL << RCC_AHB2ENR_HASHEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB2ENR_HASHEN RCC_AHB2ENR_HASHEN_Msk +#define RCC_AHB2ENR_RNGEN_Pos (18U) +#define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00040000 */ +#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk +#define RCC_AHB2ENR_HSEMEN_Pos (20U) +#define RCC_AHB2ENR_HSEMEN_Msk (0x1UL << RCC_AHB2ENR_HSEMEN_Pos) /*!< 0x00100000 */ +#define RCC_AHB2ENR_HSEMEN RCC_AHB2ENR_HSEMEN_Msk +#define RCC_AHB2ENR_PKAEN_Pos (21U) +#define RCC_AHB2ENR_PKAEN_Msk (0x1UL << RCC_AHB2ENR_PKAEN_Pos) /*!< 0x00200000 */ +#define RCC_AHB2ENR_PKAEN RCC_AHB2ENR_PKAEN_Msk +#define RCC_AHB2ENR_SRAM2EN_Pos (30U) +#define RCC_AHB2ENR_SRAM2EN_Msk (0x1UL << RCC_AHB2ENR_SRAM2EN_Pos) /*!< 0x40000000 */ +#define RCC_AHB2ENR_SRAM2EN RCC_AHB2ENR_SRAM2EN_Msk + +/******************** Bit definition for RCC_AHB4ENR register **************/ +#define RCC_AHB4ENR_PWREN_Pos (2U) +#define RCC_AHB4ENR_PWREN_Msk (0x1UL << RCC_AHB4ENR_PWREN_Pos) /*!< 0x00000004 */ +#define RCC_AHB4ENR_PWREN RCC_AHB4ENR_PWREN_Msk +#define RCC_AHB4ENR_ADC4EN_Pos (5U) +#define RCC_AHB4ENR_ADC4EN_Msk (0x1UL << RCC_AHB4ENR_ADC4EN_Pos) /*!< 0x00000020 */ +#define RCC_AHB4ENR_ADC4EN RCC_AHB4ENR_ADC4EN_Msk + +/******************** Bit definition for RCC_AHB5ENR register **************/ +#define RCC_AHB5ENR_RADIOEN_Pos (0U) +#define RCC_AHB5ENR_RADIOEN_Msk (0x1UL << RCC_AHB5ENR_RADIOEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB5ENR_RADIOEN RCC_AHB5ENR_RADIOEN_Msk + +/******************** Bit definition for RCC_APB1ENR1 register **************/ +#define RCC_APB1ENR1_TIM2EN_Pos (0U) +#define RCC_APB1ENR1_TIM2EN_Msk (0x1UL << RCC_APB1ENR1_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_APB1ENR1_TIM2EN RCC_APB1ENR1_TIM2EN_Msk +#define RCC_APB1ENR1_WWDGEN_Pos (11U) +#define RCC_APB1ENR1_WWDGEN_Msk (0x1UL << RCC_APB1ENR1_WWDGEN_Pos) /*!< 0x00000800 */ +#define RCC_APB1ENR1_WWDGEN RCC_APB1ENR1_WWDGEN_Msk + +/******************** Bit definition for RCC_APB2ENR register **************/ +#define RCC_APB2ENR_TIM1EN_Pos (11U) +#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */ +#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk +#define RCC_APB2ENR_USART1EN_Pos (14U) +#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */ +#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk +#define RCC_APB2ENR_TIM16EN_Pos (17U) +#define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */ +#define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk + +/******************** Bit definition for RCC_APB7ENR register **************/ +#define RCC_APB7ENR_SYSCFGEN_Pos (1U) +#define RCC_APB7ENR_SYSCFGEN_Msk (0x1UL << RCC_APB7ENR_SYSCFGEN_Pos) /*!< 0x00000002 */ +#define RCC_APB7ENR_SYSCFGEN RCC_APB7ENR_SYSCFGEN_Msk +#define RCC_APB7ENR_SPI3EN_Pos (5U) +#define RCC_APB7ENR_SPI3EN_Msk (0x1UL << RCC_APB7ENR_SPI3EN_Pos) /*!< 0x00000020 */ +#define RCC_APB7ENR_SPI3EN RCC_APB7ENR_SPI3EN_Msk +#define RCC_APB7ENR_LPUART1EN_Pos (6U) +#define RCC_APB7ENR_LPUART1EN_Msk (0x1UL << RCC_APB7ENR_LPUART1EN_Pos) /*!< 0x00000040 */ +#define RCC_APB7ENR_LPUART1EN RCC_APB7ENR_LPUART1EN_Msk +#define RCC_APB7ENR_I2C3EN_Pos (7U) +#define RCC_APB7ENR_I2C3EN_Msk (0x1UL << RCC_APB7ENR_I2C3EN_Pos) /*!< 0x00000080 */ +#define RCC_APB7ENR_I2C3EN RCC_APB7ENR_I2C3EN_Msk +#define RCC_APB7ENR_LPTIM1EN_Pos (11U) +#define RCC_APB7ENR_LPTIM1EN_Msk (0x1UL << RCC_APB7ENR_LPTIM1EN_Pos) /*!< 0x00000800 */ +#define RCC_APB7ENR_LPTIM1EN RCC_APB7ENR_LPTIM1EN_Msk +#define RCC_APB7ENR_RTCAPBEN_Pos (21U) +#define RCC_APB7ENR_RTCAPBEN_Msk (0x1UL << RCC_APB7ENR_RTCAPBEN_Pos) /*!< 0x00200000 */ +#define RCC_APB7ENR_RTCAPBEN RCC_APB7ENR_RTCAPBEN_Msk + +/******************** Bit definition for RCC_AHB1SMENR register **************/ +#define RCC_AHB1SMENR_GPDMA1SMEN_Pos (0U) +#define RCC_AHB1SMENR_GPDMA1SMEN_Msk (0x1UL << RCC_AHB1SMENR_GPDMA1SMEN_Pos) /*!< 0x00000000*/ +#define RCC_AHB1SMENR_GPDMA1SMEN RCC_AHB1SMENR_GPDMA1SMEN_Msk +#define RCC_AHB1SMENR_FLASHSMEN_Pos (8U) +#define RCC_AHB1SMENR_FLASHSMEN_Msk (0x1UL << RCC_AHB1SMENR_FLASHSMEN_Pos) /*!< 0x00000100 */ +#define RCC_AHB1SMENR_FLASHSMEN RCC_AHB1SMENR_FLASHSMEN_Msk +#define RCC_AHB1SMENR_CRCSMEN_Pos (12U) +#define RCC_AHB1SMENR_CRCSMEN_Msk (0x1UL << RCC_AHB1SMENR_CRCSMEN_Pos) /*!< 0x00001000 */ +#define RCC_AHB1SMENR_CRCSMEN RCC_AHB1SMENR_CRCSMEN_Msk +#define RCC_AHB1SMENR_TSCSMEN_Pos (16U) +#define RCC_AHB1SMENR_TSCSMEN_Msk (0x1UL << RCC_AHB1SMENR_TSCSMEN_Pos) /*!< 0x00010000 */ +#define RCC_AHB1SMENR_TSCSMEN RCC_AHB1SMENR_TSCSMEN_Msk +#define RCC_AHB1SMENR_RAMCFGSMEN_Pos (17U) +#define RCC_AHB1SMENR_RAMCFGSMEN_Msk (0x1UL << RCC_AHB1SMENR_RAMCFGSMEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB1SMENR_RAMCFGSMEN RCC_AHB1SMENR_RAMCFGSMEN_Msk +#define RCC_AHB1SMENR_ICACHESMEN_Pos (29U) +#define RCC_AHB1SMENR_ICACHESMEN_Msk (0x1UL << RCC_AHB1SMENR_ICACHESMEN_Pos) /*!< 0x20000000 */ +#define RCC_AHB1SMENR_ICACHESMEN RCC_AHB1SMENR_ICACHESMEN_Msk +#define RCC_AHB1SMENR_SRAM1SMEN_Pos (31U) +#define RCC_AHB1SMENR_SRAM1SMEN_Msk (0x1UL << RCC_AHB1SMENR_SRAM1SMEN_Pos) /*!< 0x80000000 */ +#define RCC_AHB1SMENR_SRAM1SMEN RCC_AHB1SMENR_SRAM1SMEN_Msk + +/******************** Bit definition for RCC_AHB2SMENR register **************/ +#define RCC_AHB2SMENR_GPIOASMEN_Pos (0U) +#define RCC_AHB2SMENR_GPIOASMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOASMEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB2SMENR_GPIOASMEN RCC_AHB2SMENR_GPIOASMEN_Msk +#define RCC_AHB2SMENR_GPIOBSMEN_Pos (1U) +#define RCC_AHB2SMENR_GPIOBSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOBSMEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB2SMENR_GPIOBSMEN RCC_AHB2SMENR_GPIOBSMEN_Msk +#define RCC_AHB2SMENR_GPIOCSMEN_Pos (2U) +#define RCC_AHB2SMENR_GPIOCSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOCSMEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB2SMENR_GPIOCSMEN RCC_AHB2SMENR_GPIOCSMEN_Msk +#define RCC_AHB2SMENR_GPIOHSMEN_Pos (7U) +#define RCC_AHB2SMENR_GPIOHSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOHSMEN_Pos) /*!< 0x00000080 */ +#define RCC_AHB2SMENR_GPIOHSMEN RCC_AHB2SMENR_GPIOHSMEN_Msk +#define RCC_AHB2SMENR_AESSMEN_Pos (16U) +#define RCC_AHB2SMENR_AESSMEN_Msk (0x1UL << RCC_AHB2SMENR_AESSMEN_Pos) /*!< 0x00010000 */ +#define RCC_AHB2SMENR_AESSMEN RCC_AHB2SMENR_AESSMEN_Msk +#define RCC_AHB2SMENR_HASHSMEN_Pos (17U) +#define RCC_AHB2SMENR_HASHSMEN_Msk (0x1UL << RCC_AHB2SMENR_HASHSMEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB2SMENR_HASHSMEN RCC_AHB2SMENR_HASHSMEN_Msk +#define RCC_AHB2SMENR_RNGSMEN_Pos (18U) +#define RCC_AHB2SMENR_RNGSMEN_Msk (0x1UL << RCC_AHB2SMENR_RNGSMEN_Pos) /*!< 0x00040000 */ +#define RCC_AHB2SMENR_RNGSMEN RCC_AHB2SMENR_RNGSMEN_Msk +#define RCC_AHB2SMENR_PKASMEN_Pos (21U) +#define RCC_AHB2SMENR_PKASMEN_Msk (0x1UL << RCC_AHB2SMENR_PKASMEN_Pos) /*!< 0x00200000 */ +#define RCC_AHB2SMENR_PKASMEN RCC_AHB2SMENR_PKASMEN_Msk +#define RCC_AHB2SMENR_SRAM2SMEN_Pos (30U) +#define RCC_AHB2SMENR_SRAM2SMEN_Msk (0x1UL << RCC_AHB2SMENR_SRAM2SMEN_Pos) /*!< 0x40000000 */ +#define RCC_AHB2SMENR_SRAM2SMEN RCC_AHB2SMENR_SRAM2SMEN_Msk + +/******************** Bit definition for RCC_AHB4SMENR register **************/ +#define RCC_AHB4SMENR_PWRSMEN_Pos (2U) +#define RCC_AHB4SMENR_PWRSMEN_Msk (0x1UL << RCC_AHB4SMENR_PWRSMEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB4SMENR_PWRSMEN RCC_AHB4SMENR_PWRSMEN_Msk +#define RCC_AHB4SMENR_ADC4SMEN_Pos (5U) +#define RCC_AHB4SMENR_ADC4SMEN_Msk (0x1UL << RCC_AHB4SMENR_ADC4SMEN_Pos) /*!< 0x00000040 */ +#define RCC_AHB4SMENR_ADC4SMEN RCC_AHB4SMENR_ADC4SMEN_Msk + +/******************** Bit definition for RCC_AHB5SMENR register **************/ +#define RCC_AHB5SMENR_RADIOSMEN_Pos (0U) +#define RCC_AHB5SMENR_RADIOSMEN_Msk (0x1UL << RCC_AHB5SMENR_RADIOSMEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB5SMENR_RADIOSMEN RCC_AHB5SMENR_RADIOSMEN_Msk + +/******************** Bit definition for RCC_APB1SMENR1 register **************/ +#define RCC_APB1SMENR1_TIM2SMEN_Pos (0U) +#define RCC_APB1SMENR1_TIM2SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM2SMEN_Pos) /*!< 0x00000001 */ +#define RCC_APB1SMENR1_TIM2SMEN RCC_APB1SMENR1_TIM2SMEN_Msk +#define RCC_APB1SMENR1_WWDGSMEN_Pos (11U) +#define RCC_APB1SMENR1_WWDGSMEN_Msk (0x1UL << RCC_APB1SMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */ +#define RCC_APB1SMENR1_WWDGSMEN RCC_APB1SMENR1_WWDGSMEN_Msk + +/******************** Bit definition for RCC_APB2SMENR register **************/ +#define RCC_APB2SMENR_TIM1SMEN_Pos (11U) +#define RCC_APB2SMENR_TIM1SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM1SMEN_Pos) /*!< 0x00000800 */ +#define RCC_APB2SMENR_TIM1SMEN RCC_APB2SMENR_TIM1SMEN_Msk +#define RCC_APB2SMENR_USART1SMEN_Pos (14U) +#define RCC_APB2SMENR_USART1SMEN_Msk (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */ +#define RCC_APB2SMENR_USART1SMEN RCC_APB2SMENR_USART1SMEN_Msk +#define RCC_APB2SMENR_TIM16SMEN_Pos (17U) +#define RCC_APB2SMENR_TIM16SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM16SMEN_Pos) /*!< 0x00020000 */ +#define RCC_APB2SMENR_TIM16SMEN RCC_APB2SMENR_TIM16SMEN_Msk + +/******************** Bit definition for RCC_APB7SMENR register **************/ +#define RCC_APB7SMENR_SYSCFGSMEN_Pos (1U) +#define RCC_APB7SMENR_SYSCFGSMEN_Msk (0x1UL << RCC_APB7SMENR_SYSCFGSMEN_Pos) /*!< 0x00000002 */ +#define RCC_APB7SMENR_SYSCFGSMEN RCC_APB7SMENR_SYSCFGSMEN_Msk +#define RCC_APB7SMENR_SPI3SMEN_Pos (5U) +#define RCC_APB7SMENR_SPI3SMEN_Msk (0x1UL << RCC_APB7SMENR_SPI3SMEN_Pos) /*!< 0x00000020 */ +#define RCC_APB7SMENR_SPI3SMEN RCC_APB7SMENR_SPI3SMEN_Msk +#define RCC_APB7SMENR_LPUART1SMEN_Pos (6U) +#define RCC_APB7SMENR_LPUART1SMEN_Msk (0x1UL << RCC_APB7SMENR_LPUART1SMEN_Pos) /*!< 0x00000040 */ +#define RCC_APB7SMENR_LPUART1SMEN RCC_APB7SMENR_LPUART1SMEN_Msk +#define RCC_APB7SMENR_I2C3SMEN_Pos (7U) +#define RCC_APB7SMENR_I2C3SMEN_Msk (0x1UL << RCC_APB7SMENR_I2C3SMEN_Pos) /*!< 0x00000080 */ +#define RCC_APB7SMENR_I2C3SMEN RCC_APB7SMENR_I2C3SMEN_Msk +#define RCC_APB7SMENR_LPTIM1SMEN_Pos (11U) +#define RCC_APB7SMENR_LPTIM1SMEN_Msk (0x1UL << RCC_APB7SMENR_LPTIM1SMEN_Pos) /*!< 0x00000800 */ +#define RCC_APB7SMENR_LPTIM1SMEN RCC_APB7SMENR_LPTIM1SMEN_Msk +#define RCC_APB7SMENR_RTCAPBSMEN_Pos (21U) +#define RCC_APB7SMENR_RTCAPBSMEN_Msk (0x1UL << RCC_APB7SMENR_RTCAPBSMEN_Pos) /*!< 0x00200000 */ +#define RCC_APB7SMENR_RTCAPBSMEN RCC_APB7SMENR_RTCAPBSMEN_Msk + +/******************** Bit definition for RCC_CCIPR1 register ******************/ +#define RCC_CCIPR1_USART1SEL_Pos (0U) +#define RCC_CCIPR1_USART1SEL_Msk (0x3UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000003 */ +#define RCC_CCIPR1_USART1SEL RCC_CCIPR1_USART1SEL_Msk +#define RCC_CCIPR1_USART1SEL_0 (0x1UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR1_USART1SEL_1 (0x2UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR1_SYSTICKSEL_Pos (22U) +#define RCC_CCIPR1_SYSTICKSEL_Msk (0x3UL << RCC_CCIPR1_SYSTICKSEL_Pos) /*!< 0x00C00000 */ +#define RCC_CCIPR1_SYSTICKSEL RCC_CCIPR1_SYSTICKSEL_Msk +#define RCC_CCIPR1_SYSTICKSEL_0 (0x1UL << RCC_CCIPR1_SYSTICKSEL_Pos) /*!< 0x00400000 */ +#define RCC_CCIPR1_SYSTICKSEL_1 (0x2UL << RCC_CCIPR1_SYSTICKSEL_Pos) /*!< 0x00800000 */ +#define RCC_CCIPR1_TIMICSEL_Pos (31U) +#define RCC_CCIPR1_TIMICSEL_Msk (0x1UL << RCC_CCIPR1_TIMICSEL_Pos) /*!< 0x80000000 */ +#define RCC_CCIPR1_TIMICSEL RCC_CCIPR1_TIMICSEL_Msk + +/******************** Bit definition for RCC_CCIPR2 register ******************/ +#define RCC_CCIPR2_RNGSEL_Pos (12U) +#define RCC_CCIPR2_RNGSEL_Msk (0x3UL << RCC_CCIPR2_RNGSEL_Pos) /*!< 0x00300000 */ +#define RCC_CCIPR2_RNGSEL RCC_CCIPR2_RNGSEL_Msk +#define RCC_CCIPR2_RNGSEL_0 (0x1UL << RCC_CCIPR2_RNGSEL_Pos) /*!< 0x00100000 */ +#define RCC_CCIPR2_RNGSEL_1 (0x2UL << RCC_CCIPR2_RNGSEL_Pos) /*!< 0x00200000 */ + +/******************** Bit definition for RCC_CCIPR3 register ***************/ +#define RCC_CCIPR3_LPUART1SEL_Pos (0U) +#define RCC_CCIPR3_LPUART1SEL_Msk (0x3UL << RCC_CCIPR3_LPUART1SEL_Pos) /*!< 0x00000003 */ +#define RCC_CCIPR3_LPUART1SEL RCC_CCIPR3_LPUART1SEL_Msk +#define RCC_CCIPR3_LPUART1SEL_0 (0x1UL << RCC_CCIPR3_LPUART1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR3_LPUART1SEL_1 (0x2UL << RCC_CCIPR3_LPUART1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR3_SPI3SEL_Pos (3U) +#define RCC_CCIPR3_SPI3SEL_Msk (0x3UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000018 */ +#define RCC_CCIPR3_SPI3SEL RCC_CCIPR3_SPI3SEL_Msk +#define RCC_CCIPR3_SPI3SEL_0 (0x1UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000008 */ +#define RCC_CCIPR3_SPI3SEL_1 (0x2UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR3_I2C3SEL_Pos (6U) +#define RCC_CCIPR3_I2C3SEL_Msk (0x3UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x000000C0 */ +#define RCC_CCIPR3_I2C3SEL RCC_CCIPR3_I2C3SEL_Msk +#define RCC_CCIPR3_I2C3SEL_0 (0x1UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR3_I2C3SEL_1 (0x2UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000080 */ +#define RCC_CCIPR3_LPTIM1SEL_Pos (10U) +#define RCC_CCIPR3_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00000C00 */ +#define RCC_CCIPR3_LPTIM1SEL RCC_CCIPR3_LPTIM1SEL_Msk +#define RCC_CCIPR3_LPTIM1SEL_0 (0x1UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR3_LPTIM1SEL_1 (0x2UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00000800 */ +#define RCC_CCIPR3_ADCSEL_Pos (12U) +#define RCC_CCIPR3_ADCSEL_Msk (0x7UL << RCC_CCIPR3_ADCSEL_Pos) /*!< 0x00007000 */ +#define RCC_CCIPR3_ADCSEL RCC_CCIPR3_ADCSEL_Msk +#define RCC_CCIPR3_ADCSEL_0 (0x1UL << RCC_CCIPR3_ADCSEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR3_ADCSEL_1 (0x2UL << RCC_CCIPR3_ADCSEL_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR3_ADCSEL_2 (0x4UL << RCC_CCIPR3_ADCSEL_Pos) /*!< 0x00004000 */ + +/******************** Bit definition for RCC_BDCR1 register ******************/ +#define RCC_BDCR1_LSEON_Pos (0U) +#define RCC_BDCR1_LSEON_Msk (0x1UL << RCC_BDCR1_LSEON_Pos) /*!< 0x00000001 */ +#define RCC_BDCR1_LSEON RCC_BDCR1_LSEON_Msk +#define RCC_BDCR1_LSERDY_Pos (1U) +#define RCC_BDCR1_LSERDY_Msk (0x1UL << RCC_BDCR1_LSERDY_Pos) /*!< 0x00000002 */ +#define RCC_BDCR1_LSERDY RCC_BDCR1_LSERDY_Msk +#define RCC_BDCR1_LSEBYP_Pos (2U) +#define RCC_BDCR1_LSEBYP_Msk (0x1UL << RCC_BDCR1_LSEBYP_Pos) /*!< 0x00000004 */ +#define RCC_BDCR1_LSEBYP RCC_BDCR1_LSEBYP_Msk +#define RCC_BDCR1_LSEDRV_Pos (3U) +#define RCC_BDCR1_LSEDRV_Msk (0x3UL << RCC_BDCR1_LSEDRV_Pos) /*!< 0x00000018 */ +#define RCC_BDCR1_LSEDRV RCC_BDCR1_LSEDRV_Msk +#define RCC_BDCR1_LSEDRV_0 (0x1UL << RCC_BDCR1_LSEDRV_Pos) /*!< 0x00000008 */ +#define RCC_BDCR1_LSEDRV_1 (0x2UL << RCC_BDCR1_LSEDRV_Pos) /*!< 0x00000010 */ +#define RCC_BDCR1_LSECSSON_Pos (5U) +#define RCC_BDCR1_LSECSSON_Msk (0x1UL << RCC_BDCR1_LSECSSON_Pos) /*!< 0x00000020 */ +#define RCC_BDCR1_LSECSSON RCC_BDCR1_LSECSSON_Msk +#define RCC_BDCR1_LSECSSD_Pos (6U) +#define RCC_BDCR1_LSECSSD_Msk (0x1UL << RCC_BDCR1_LSECSSD_Pos) /*!< 0x00000040 */ +#define RCC_BDCR1_LSECSSD RCC_BDCR1_LSECSSD_Msk +#define RCC_BDCR1_LSESYSEN_Pos (7U) +#define RCC_BDCR1_LSESYSEN_Msk (0x1UL << RCC_BDCR1_LSESYSEN_Pos) /*!< 0x00000080 */ +#define RCC_BDCR1_LSESYSEN RCC_BDCR1_LSESYSEN_Msk +#define RCC_BDCR1_RTCSEL_Pos (8U) +#define RCC_BDCR1_RTCSEL_Msk (0x3UL << RCC_BDCR1_RTCSEL_Pos) /*!< 0x00000300 */ +#define RCC_BDCR1_RTCSEL RCC_BDCR1_RTCSEL_Msk +#define RCC_BDCR1_RTCSEL_0 (0x1UL << RCC_BDCR1_RTCSEL_Pos) /*!< 0x00000100 */ +#define RCC_BDCR1_RTCSEL_1 (0x2UL << RCC_BDCR1_RTCSEL_Pos) /*!< 0x00000200 */ +#define RCC_BDCR1_LSESYSRDY_Pos (11U) +#define RCC_BDCR1_LSESYSRDY_Msk (0x1UL << RCC_BDCR1_LSESYSRDY_Pos) /*!< 0x00000800 */ +#define RCC_BDCR1_LSESYSRDY RCC_BDCR1_LSESYSRDY_Msk +#define RCC_BDCR1_LSEGFON_Pos (12U) +#define RCC_BDCR1_LSEGFON_Msk (0x1UL << RCC_BDCR1_LSEGFON_Pos) /*!< 0x00001000 */ +#define RCC_BDCR1_LSEGFON RCC_BDCR1_LSEGFON_Msk +#define RCC_BDCR1_LSETRIM_Pos (13U) +#define RCC_BDCR1_LSETRIM_Msk (0x3UL << RCC_BDCR1_LSETRIM_Pos) /*!< 0x00006000 */ +#define RCC_BDCR1_LSETRIM RCC_BDCR1_LSETRIM_Msk +#define RCC_BDCR1_LSETRIM_0 (0x1UL << RCC_BDCR1_LSETRIM_Pos) /*!< 0x00002000 */ +#define RCC_BDCR1_LSETRIM_1 (0x2UL << RCC_BDCR1_LSETRIM_Pos) /*!< 0x00004000 */ +#define RCC_BDCR1_BDRST_Pos (16U) +#define RCC_BDCR1_BDRST_Msk (0x1UL << RCC_BDCR1_BDRST_Pos) /*!< 0x00010000 */ +#define RCC_BDCR1_BDRST RCC_BDCR1_BDRST_Msk +#define RCC_BDCR1_RADIOSTSEL_Pos (18U) +#define RCC_BDCR1_RADIOSTSEL_Msk (0x3UL << RCC_BDCR1_RADIOSTSEL_Pos) /*!< 0x000C0000 */ +#define RCC_BDCR1_RADIOSTSEL RCC_BDCR1_RADIOSTSEL_Msk +#define RCC_BDCR1_RADIOSTSEL_0 (0x1UL << RCC_BDCR1_RADIOSTSEL_Pos) /*!< 0x00040000 */ +#define RCC_BDCR1_RADIOSTSEL_1 (0x2UL << RCC_BDCR1_RADIOSTSEL_Pos) /*!< 0x00080000 */ +#define RCC_BDCR1_LSCOEN_Pos (24U) +#define RCC_BDCR1_LSCOEN_Msk (0x1UL << RCC_BDCR1_LSCOEN_Pos) /*!< 0x01000000 */ +#define RCC_BDCR1_LSCOEN RCC_BDCR1_LSCOEN_Msk +#define RCC_BDCR1_LSCOSEL_Pos (25U) +#define RCC_BDCR1_LSCOSEL_Msk (0x1UL << RCC_BDCR1_LSCOSEL_Pos) /*!< 0x02000000 */ +#define RCC_BDCR1_LSCOSEL RCC_BDCR1_LSCOSEL_Msk +#define RCC_BDCR1_LSI1ON_Pos (26U) +#define RCC_BDCR1_LSI1ON_Msk (0x1UL << RCC_BDCR1_LSI1ON_Pos) /*!< 0x04000000 */ +#define RCC_BDCR1_LSI1ON RCC_BDCR1_LSI1ON_Msk +#define RCC_BDCR1_LSI1RDY_Pos (27U) +#define RCC_BDCR1_LSI1RDY_Msk (0x1UL << RCC_BDCR1_LSI1RDY_Pos) /*!< 0x08000000 */ +#define RCC_BDCR1_LSI1RDY RCC_BDCR1_LSI1RDY_Msk +#define RCC_BDCR1_LSI1PREDIV_Pos (28U) +#define RCC_BDCR1_LSI1PREDIV_Msk (0x1UL << RCC_BDCR1_LSI1PREDIV_Pos) /*!< 0x10000000 */ +#define RCC_BDCR1_LSI1PREDIV RCC_BDCR1_LSI1PREDIV_Msk + +/******************** Bit definition for RCC_CSR register *******************/ +#define RCC_CSR_RMVF_Pos (23U) +#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */ +#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk +#define RCC_CSR_OBLRSTF_Pos (25U) +#define RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */ +#define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk +#define RCC_CSR_PINRSTF_Pos (26U) +#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */ +#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk +#define RCC_CSR_BORRSTF_Pos (27U) +#define RCC_CSR_BORRSTF_Msk (0x1UL << RCC_CSR_BORRSTF_Pos) /*!< 0x08000000 */ +#define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk +#define RCC_CSR_SFTRSTF_Pos (28U) +#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */ +#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk +#define RCC_CSR_IWDGRSTF_Pos (29U) +#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */ +#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk +#define RCC_CSR_WWDGRSTF_Pos (30U) +#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */ +#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk +#define RCC_CSR_LPWRRSTF_Pos (31U) +#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */ +#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk + + + +/******************** Bit definition for RCC_CFGR4 register *******************/ +#define RCC_CFGR4_HPRE5_Pos (0U) +#define RCC_CFGR4_HPRE5_Msk (0x7UL << RCC_CFGR4_HPRE5_Pos) /*!< 0x00000007 */ +#define RCC_CFGR4_HPRE5 RCC_CFGR4_HPRE5_Msk +#define RCC_CFGR4_HPRE5_0 (0x1UL << RCC_CFGR4_HPRE5_Pos) /*!< 0x00000001 */ +#define RCC_CFGR4_HPRE5_1 (0x2UL << RCC_CFGR4_HPRE5_Pos) /*!< 0x00000002 */ +#define RCC_CFGR4_HPRE5_2 (0x4UL << RCC_CFGR4_HPRE5_Pos) /*!< 0x00000004 */ +#define RCC_CFGR4_HDIV5_Pos (4U) +#define RCC_CFGR4_HDIV5_Msk (0x1UL << RCC_CFGR4_HDIV5_Pos) /*!< 0x00000080 */ +#define RCC_CFGR4_HDIV5 RCC_CFGR4_HDIV5_Msk + +/******************** Bit definition for RCC_RADIOENR register **************/ +#define RCC_RADIOENR_BBCLKEN_Pos (1U) +#define RCC_RADIOENR_BBCLKEN_Msk (0x1UL << RCC_RADIOENR_BBCLKEN_Pos) /*!< 0x00000002 */ +#define RCC_RADIOENR_BBCLKEN RCC_RADIOENR_BBCLKEN_Msk +#define RCC_RADIOENR_STRADIOCLKON_Pos (16U) +#define RCC_RADIOENR_STRADIOCLKON_Msk (0x1UL << RCC_RADIOENR_STRADIOCLKON_Pos) /*!< 0x00010000 */ +#define RCC_RADIOENR_STRADIOCLKON RCC_RADIOENR_STRADIOCLKON_Msk +#define RCC_RADIOENR_RADIOCLKRDY_Pos (17U) +#define RCC_RADIOENR_RADIOCLKRDY_Msk (0x1UL << RCC_RADIOENR_RADIOCLKRDY_Pos) /*!< 0x00020000 */ +#define RCC_RADIOENR_RADIOCLKRDY RCC_RADIOENR_RADIOCLKRDY_Msk + +/******************** Bit definition for RCC_ECSCR1 register *******************/ +#define RCC_ECSCR1_HSETRIM_Pos (16U) +#define RCC_ECSCR1_HSETRIM_Msk (0x3FUL << RCC_ECSCR1_HSETRIM_Pos) /*!< 0x003F0000 */ +#define RCC_ECSCR1_HSETRIM RCC_ECSCR1_HSETRIM_Msk +#define RCC_ECSCR1_HSETRIM_0 (0x1UL << RCC_ECSCR1_HSETRIM_Pos) /*!< 0x00010000 */ +#define RCC_ECSCR1_HSETRIM_1 (0x2UL << RCC_ECSCR1_HSETRIM_Pos) /*!< 0x00020000 */ +#define RCC_ECSCR1_HSETRIM_2 (0x4UL << RCC_ECSCR1_HSETRIM_Pos) /*!< 0x00040000 */ +#define RCC_ECSCR1_HSETRIM_3 (0x8UL << RCC_ECSCR1_HSETRIM_Pos) /*!< 0x00080000 */ +#define RCC_ECSCR1_HSETRIM_4 (0x10UL << RCC_ECSCR1_HSETRIM_Pos) /*!< 0x00100000 */ +#define RCC_ECSCR1_HSETRIM_5 (0x20UL << RCC_ECSCR1_HSETRIM_Pos) /*!< 0x00200000 */ + + +/******************************************************************************/ +/* */ +/* RNG */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RNG_CR register *******************/ +#define RNG_CR_RNGEN_Pos (2U) +#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_IE_Pos (3U) +#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_CED_Pos (5U) +#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ +#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_ARDIS_Pos (7U) +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_RNG_CONFIG3_Pos (8U) +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_NISTC_Pos (12U) +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) +#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_RNG_CONFIG2_Pos (13U) +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_CLKDIV_Pos (16U) +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_RNG_CONFIG1_Pos (20U) +#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_CONDRST_Pos (30U) +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONFIGLOCK_Pos (31U) +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk + +/******************** Bits definition for RNG_SR register *******************/ +#define RNG_SR_DRDY_Pos (0U) +#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ +#define RNG_SR_DRDY RNG_SR_DRDY_Msk +#define RNG_SR_CECS_Pos (1U) +#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ +#define RNG_SR_CECS RNG_SR_CECS_Msk +#define RNG_SR_SECS_Pos (2U) +#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ +#define RNG_SR_SECS RNG_SR_SECS_Msk +#define RNG_SR_CEIS_Pos (5U) +#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ +#define RNG_SR_CEIS RNG_SR_CEIS_Msk +#define RNG_SR_SEIS_Pos (6U) +#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ +#define RNG_SR_SEIS RNG_SR_SEIS_Msk + +/******************** Bits definition for RNG_DR register *******************/ +#define RNG_DR_RNDATA_Pos (0U) +#define RNG_DR_RNDATA_Msk (0xFFFFFFFFUL << RNG_DR_RNDATA_Pos) /*!< 0xFFFFFFFF */ +#define RNG_DR_RNDATA RNG_DR_RNDATA_Msk + +/******************** Bits definition for RNG_HTCR register *******************/ +#define RNG_HTCR_HTCFG_Pos (0U) +#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk + + +/******************************************************************************/ +/* */ +/* Real-Time Clock (RTC) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RTC_TR register *******************/ +#define RTC_TR_SU_Pos (0U) +#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */ +#define RTC_TR_SU RTC_TR_SU_Msk +#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */ +#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */ +#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */ +#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */ +#define RTC_TR_ST_Pos (4U) +#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */ +#define RTC_TR_ST RTC_TR_ST_Msk +#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */ +#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */ +#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */ +#define RTC_TR_MNU_Pos (8U) +#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_TR_MNU RTC_TR_MNU_Msk +#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_TR_MNT_Pos (12U) +#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_TR_MNT RTC_TR_MNT_Msk +#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_TR_HU_Pos (16U) +#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_TR_HU RTC_TR_HU_Msk +#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */ +#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */ +#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */ +#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */ +#define RTC_TR_HT_Pos (20U) +#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */ +#define RTC_TR_HT RTC_TR_HT_Msk +#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */ +#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */ +#define RTC_TR_PM_Pos (22U) +#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */ +#define RTC_TR_PM RTC_TR_PM_Msk + +/******************** Bits definition for RTC_DR register *******************/ +#define RTC_DR_DU_Pos (0U) +#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */ +#define RTC_DR_DU RTC_DR_DU_Msk +#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */ +#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */ +#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */ +#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */ +#define RTC_DR_DT_Pos (4U) +#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */ +#define RTC_DR_DT RTC_DR_DT_Msk +#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */ +#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */ +#define RTC_DR_MU_Pos (8U) +#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */ +#define RTC_DR_MU RTC_DR_MU_Msk +#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */ +#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */ +#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */ +#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */ +#define RTC_DR_MT_Pos (12U) +#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */ +#define RTC_DR_MT RTC_DR_MT_Msk +#define RTC_DR_WDU_Pos (13U) +#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */ +#define RTC_DR_WDU RTC_DR_WDU_Msk +#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */ +#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */ +#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */ +#define RTC_DR_YU_Pos (16U) +#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */ +#define RTC_DR_YU RTC_DR_YU_Msk +#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */ +#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */ +#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */ +#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */ +#define RTC_DR_YT_Pos (20U) +#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */ +#define RTC_DR_YT RTC_DR_YT_Msk +#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */ +#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */ +#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */ +#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */ + +/******************** Bits definition for RTC_SSR register ******************/ +#define RTC_SSR_SS_Pos (0U) +#define RTC_SSR_SS_Msk (0xFFFFFFFFUL << RTC_SSR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_SSR_SS RTC_SSR_SS_Msk + +/******************** Bits definition for RTC_ICSR register ******************/ +#define RTC_ICSR_WUTWF_Pos (2U) +#define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */ +#define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk +#define RTC_ICSR_SHPF_Pos (3U) +#define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */ +#define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk +#define RTC_ICSR_INITS_Pos (4U) +#define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */ +#define RTC_ICSR_INITS RTC_ICSR_INITS_Msk +#define RTC_ICSR_RSF_Pos (5U) +#define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */ +#define RTC_ICSR_RSF RTC_ICSR_RSF_Msk +#define RTC_ICSR_INITF_Pos (6U) +#define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */ +#define RTC_ICSR_INITF RTC_ICSR_INITF_Msk +#define RTC_ICSR_INIT_Pos (7U) +#define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */ +#define RTC_ICSR_INIT RTC_ICSR_INIT_Msk +#define RTC_ICSR_BIN_Pos (8U) +#define RTC_ICSR_BIN_Msk (0x3UL << RTC_ICSR_BIN_Pos) /*!< 0x00000300 */ +#define RTC_ICSR_BIN RTC_ICSR_BIN_Msk +#define RTC_ICSR_BIN_0 (0x1UL << RTC_ICSR_BIN_Pos) /*!< 0x00000100 */ +#define RTC_ICSR_BIN_1 (0x2UL << RTC_ICSR_BIN_Pos) /*!< 0x00000200 */ +#define RTC_ICSR_BCDU_Pos (10U) +#define RTC_ICSR_BCDU_Msk (0x7UL << RTC_ICSR_BCDU_Pos) /*!< 0x00001C00 */ +#define RTC_ICSR_BCDU RTC_ICSR_BCDU_Msk +#define RTC_ICSR_BCDU_0 (0x1UL << RTC_ICSR_BCDU_Pos) /*!< 0x00000400 */ +#define RTC_ICSR_BCDU_1 (0x2UL << RTC_ICSR_BCDU_Pos) /*!< 0x00000800 */ +#define RTC_ICSR_BCDU_2 (0x4UL << RTC_ICSR_BCDU_Pos) /*!< 0x00001000 */ +#define RTC_ICSR_RECALPF_Pos (16U) +#define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */ +#define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk + +/******************** Bits definition for RTC_PRER register *****************/ +#define RTC_PRER_PREDIV_S_Pos (0U) +#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */ +#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk +#define RTC_PRER_PREDIV_A_Pos (16U) +#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ +#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk + +/******************** Bits definition for RTC_WUTR register *****************/ +#define RTC_WUTR_WUT_Pos (0U) +#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk +#define RTC_WUTR_WUTOCLR_Pos (16U) +#define RTC_WUTR_WUTOCLR_Msk (0xFFFFUL << RTC_WUTR_WUTOCLR_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUTOCLR RTC_WUTR_WUTOCLR_Msk + +/******************** Bits definition for RTC_CR register *******************/ +#define RTC_CR_WUCKSEL_Pos (0U) +#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */ +#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk +#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */ +#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ +#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ +#define RTC_CR_BYPSHAD_Pos (5U) +#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ +#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk +#define RTC_CR_FMT_Pos (6U) +#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */ +#define RTC_CR_FMT RTC_CR_FMT_Msk +#define RTC_CR_SSRUIE_Pos (7U) +#define RTC_CR_SSRUIE_Msk (0x1UL << RTC_CR_SSRUIE_Pos) /*!< 0x00000080 */ +#define RTC_CR_SSRUIE RTC_CR_SSRUIE_Msk +#define RTC_CR_ALRAE_Pos (8U) +#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ +#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk +#define RTC_CR_ALRBE_Pos (9U) +#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */ +#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk +#define RTC_CR_WUTE_Pos (10U) +#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */ +#define RTC_CR_WUTE RTC_CR_WUTE_Msk +#define RTC_CR_ALRAIE_Pos (12U) +#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ +#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk +#define RTC_CR_ALRBIE_Pos (13U) +#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */ +#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk +#define RTC_CR_WUTIE_Pos (14U) +#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */ +#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk +#define RTC_CR_TSIE_Pos (15U) +#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */ +#define RTC_CR_TSIE RTC_CR_TSIE_Msk +#define RTC_CR_ADD1H_Pos (16U) +#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */ +#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk +#define RTC_CR_SUB1H_Pos (17U) +#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ +#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk +#define RTC_CR_BKP_Pos (18U) +#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk +#define RTC_CR_TAMPTS_Pos (25U) +#define RTC_CR_TAMPTS_Msk (0x1UL << RTC_CR_TAMPTS_Pos) /*!< 0x02000000 */ +#define RTC_CR_TAMPTS RTC_CR_TAMPTS_Msk /*! */ + +/******************** Bits definition for RTC_ALRMAR register ***************/ +#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk +#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk +#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk +#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk +#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk +#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk +#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk +#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk +#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk +#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk +#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk +#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk +#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk +#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk +#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Msk (0x3FUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x3F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_MASKSS_4 (0x10UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x10000000 */ +#define RTC_ALRMASSR_MASKSS_5 (0x20UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x20000000 */ +#define RTC_ALRMASSR_SSCLR_Pos (31U) +#define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk + +/******************** Bits definition for RTC_ALRMBR register ***************/ +#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk +#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk +#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk +#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk +#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk +#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk +#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk +#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk +#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk +#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk +#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk +#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk +#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk +#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMBSSR register *************/ +#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk +#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Msk (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x3F000000 */ +#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk +#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBSSR_MASKSS_4 (0x10UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBSSR_MASKSS_5 (0x20UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBSSR_SSCLR_Pos (31U) +#define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk + +/******************** Bits definition for RTC_SR register *******************/ +#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk +#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk +#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ +#define RTC_SR_WUTF RTC_SR_WUTF_Msk +#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ +#define RTC_SR_TSF RTC_SR_TSF_Msk +#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk +#define RTC_SR_SSRUF_Pos (6U) +#define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SR_SSRUF RTC_SR_SSRUF_Msk + +/******************** Bits definition for RTC_MISR register *****************/ +#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk +#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk +#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk +#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk +#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk +#define RTC_MISR_SSRUMF_Pos (6U) +#define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SCR register ******************/ +#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk +#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk +#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ +#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk +#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ +#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk +#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk +#define RTC_SCR_CSSRUF_Pos (6U) +#define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk + +/******************** Bits definition for RTC_ALRABINR register ******************/ +#define RTC_ALRABINR_SS_Pos (0U) +#define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk + +/******************** Bits definition for RTC_ALRBBINR register ******************/ +#define RTC_ALRBBINR_SS_Pos (0U) +#define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk + + +/******************************************************************************/ +/* */ +/* Serial Peripheral Interface (SPI) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for SPI_CR1 register ********************/ +#define SPI_CR1_SPE_Pos (0U) +#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000001 */ +#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!> HSEM_CR_LOCKID_Pos)/* Semaphore Lock ID */ + +#define HSEM_SEMID_MIN (0U) /* HSEM ID Min*/ +#define HSEM_SEMID_MAX (15U) /* HSEM ID Max */ + +#define HSEM_PROCESSID_MIN (0U) /* HSEM Process ID Min */ +#define HSEM_PROCESSID_MAX (255U) /* HSEM Process ID Max */ + +#define HSEM_CLEAR_KEY_MIN (0U) /* HSEM clear Key Min value */ +#define HSEM_CLEAR_KEY_MAX (0xFFFFU) /* HSEM clear Key Max value */ + +/******************************** I2C Instances *******************************/ +#define IS_I2C_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C3_NS) + +/******************* I2C Instances : Group belongingness *********************/ +#define IS_I2C_GRP1_INSTANCE(INSTANCE) (0) + +#define IS_I2C_GRP2_INSTANCE(INSTANCE) ((INSTANCE) == I2C3_NS) + +/****************** I2C Instances : wakeup capability from stop modes *********/ +#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) + +/******************************* AES Instances ********************************/ +#define IS_PKA_ALL_INSTANCE(INSTANCE) ((INSTANCE) == PKA_NS) + +/******************************* RNG Instances ********************************/ +#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG_NS) + +/****************************** RTC Instances *********************************/ +#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC_NS) + +/****************************** SMBUS Instances *******************************/ +#define IS_SMBUS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C3_NS) + +/******************* SMBUS Instances : Group belongingness *********************/ +#define IS_SMBUS_GRP1_INSTANCE(INSTANCE) (0) + +#define IS_SMBUS_GRP2_INSTANCE(INSTANCE) ((INSTANCE) == I2C3_NS) + +/******************************** SPI Instances *******************************/ +#define IS_SPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI3_NS) + +#define IS_SPI_LIMITED_INSTANCE(INSTANCE) ((INSTANCE) == SPI3_NS) + +#define IS_SPI_FULL_INSTANCE(INSTANCE) (0) + +/******************* SPI Instances : Group belongingness *********************/ +#define IS_SPI_GRP1_INSTANCE(INSTANCE) (0) + +#define IS_SPI_GRP2_INSTANCE(INSTANCE) ((INSTANCE) == SPI3_NS) + +/******************************** LPTIM Instances *******************************/ +#define IS_LPTIM_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1_NS) + +/****************** LPTIM Instances : DMA supported instances *****************/ +#define IS_LPTIM_DMA_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1_NS) + +/************* LPTIM Instances : at least 1 capture/compare channel ***********/ +#define IS_LPTIM_CC1_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1_NS) + +/************* LPTIM Instances : at least 2 capture/compare channel ***********/ +#define IS_LPTIM_CC2_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1_NS) + +/****************** LPTIM Instances : supporting encoder interface **************/ +#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1_NS) + +/****************** LPTIM Instances : supporting Input Capture **************/ +#define IS_LPTIM_INPUT_CAPTURE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1_NS) + +/****************** TIM Instances : All supported instances *******************/ +#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM16_NS)) + +/****************** TIM Instances : supporting 32 bits counter ****************/ +#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM2_NS) + +/****************** TIM Instances : supporting the break function *************/ +#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM16_NS)) + +/************** TIM Instances : supporting Break source selection *************/ +#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM16_NS)) + +/****************** TIM Instances : supporting 2 break inputs *****************/ +#define IS_TIM_BKIN2_INSTANCE(INSTANCE) ((INSTANCE) == TIM1_NS) + +/************* TIM Instances : at least 1 capture/compare channel *************/ +#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM16_NS)) + +/************ TIM Instances : at least 2 capture/compare channels *************/ +#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS)) + +/************ TIM Instances : at least 3 capture/compare channels *************/ +#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS)) + +/************ TIM Instances : at least 4 capture/compare channels *************/ +#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS)) + +/****************** TIM Instances : at least 5 capture/compare channels *******/ +#define IS_TIM_CC5_INSTANCE(INSTANCE) ((INSTANCE) == TIM1_NS) + +/****************** TIM Instances : at least 6 capture/compare channels *******/ +#define IS_TIM_CC6_INSTANCE(INSTANCE) ((INSTANCE) == TIM1_NS) + +/************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/ +#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM16_NS)) + +/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/ +#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM16_NS)) + +/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/ +#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM16_NS)) + +/******************** TIM Instances : DMA burst feature ***********************/ +#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM16_NS)) + +/******************* TIM Instances : output(s) available **********************/ +#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ + ((((INSTANCE) == TIM1_NS) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4) || \ + ((CHANNEL) == TIM_CHANNEL_5) || \ + ((CHANNEL) == TIM_CHANNEL_6))) \ + || \ + (((INSTANCE) == TIM2_NS) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + (((INSTANCE) == TIM16_NS) && \ + (((CHANNEL) == TIM_CHANNEL_1)))) + +/****************** TIM Instances : supporting complementary output(s) ********/ +#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ + ((((INSTANCE) == TIM1_NS) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + (((INSTANCE) == TIM16_NS) && \ + ((CHANNEL) == TIM_CHANNEL_1))) + +/****************** TIM Instances : supporting clock division *****************/ +#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM16_NS)) + +/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS)) + +/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS)) + +/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/ +#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS)) + +/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/ +#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS)) + +/****************** TIM Instances : supporting combined 3-phase PWM mode ******/ +#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) ((INSTANCE) == TIM1_NS) + +/****************** TIM Instances : supporting commutation event generation ***/ +#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM16_NS)) + +/****************** TIM Instances : supporting counting mode selection ********/ +#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS)) + +/****************** TIM Instances : supporting encoder interface **************/ +#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS)) + +/****************** TIM Instances : supporting Hall sensor interface **********/ +#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS)) + +/**************** TIM Instances : external trigger input available ************/ +#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS)) + +/************* TIM Instances : supporting ETR source selection ***************/ +#define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS)) + +/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/ +#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS)) + +/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/ +#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS)) + +/****************** TIM Instances : supporting OCxREF clear *******************/ +#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS)) + +/****************** TIM Instances : remapping capability **********************/ +#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS)) + +/****************** TIM Instances : supporting repetition counter *************/ +#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM16_NS)) + +/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/ +#define IS_TIM_TRGO2_INSTANCE(INSTANCE) ((INSTANCE) == TIM1_NS) + +/******************* TIM Instances : Timer input XOR function *****************/ +#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS)) + +/******************* TIM Instances : Timer input selection ********************/ +#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM16_NS)) + +/******************* TIM Instances : supporting HSE32 as input ********************/ +#define IS_TIM_HSE32_INSTANCE(INSTANCE) ((INSTANCE) == TIM16_NS) + +/****************** TIM Instances : Advanced timer instances *******************/ +#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1_NS) + +/****************** TIM Instances : supporting synchronization ****************/ +#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS)) + +/****************************** TSC Instances *********************************/ +#define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC_NS) + +/******************** USART Instances : Synchronous mode **********************/ +#define IS_USART_INSTANCE(INSTANCE) ((INSTANCE) == USART1_NS) + +/******************** UART Instances : Asynchronous mode **********************/ +#define IS_UART_INSTANCE(INSTANCE) ((INSTANCE) == USART1_NS) + +/*********************** UART Instances : FIFO mode ***************************/ +#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \ + ((INSTANCE) == LPUART1_NS)) + +/*********************** UART Instances : SPI Slave mode **********************/ +#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) ((INSTANCE) == USART1_NS) + +/****************** UART Instances : Auto Baud Rate detection ****************/ +#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART1_NS) + +/****************** UART Instances : Driver Enable *****************/ +#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \ + ((INSTANCE) == LPUART1_NS)) + +/******************** UART Instances : Half-Duplex mode **********************/ +#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \ + ((INSTANCE) == LPUART1_NS)) + +/****************** UART Instances : Hardware Flow control ********************/ +#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \ + ((INSTANCE) == LPUART1_NS)) + +/******************** UART Instances : LIN mode **********************/ +#define IS_UART_LIN_INSTANCE(INSTANCE) ((INSTANCE) == USART1_NS) + +/******************** UART Instances : Wake-up from Stop mode **********************/ +#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \ + ((INSTANCE) == LPUART1_NS)) + +/*********************** UART Instances : IRDA mode ***************************/ +#define IS_IRDA_INSTANCE(INSTANCE) ((INSTANCE) == USART1_NS) + +/********************* USART Instances : Smard card mode ***********************/ +#define IS_SMARTCARD_INSTANCE(INSTANCE) ((INSTANCE) == USART1_NS) + +/*********************** UART Instances : AUTONOMOUS mode ***************************/ +#define IS_UART_AUTONOMOUS_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \ + ((INSTANCE) == LPUART1_NS)) + +/******************** LPUART Instance *****************************************/ +#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1_NS) + +/****************************** IWDG Instances ********************************/ +#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG_NS) + +/****************************** WWDG Instances ********************************/ +#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG_NS) + + +/** @} */ /* End of group STM32WBAxx_Peripheral_Exported_macros */ + +/** @} */ /* End of group STM32WBA50xx */ + +/** @} */ /* End of group ST */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WBA50xx_H */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba52xx.h b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba52xx.h new file mode 100644 index 0000000000..fb49c5ea64 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba52xx.h @@ -0,0 +1,15093 @@ +/** + ****************************************************************************** + * @file stm32wba52xx.h + * @author MCD Application Team + * @brief CMSIS STM32WBA52xx Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral's registers hardware + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef STM32WBA52xx_H +#define STM32WBA52xx_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup ST + * @{ + */ + +/** @addtogroup STM32WBA52xx + * @{ + */ + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ +typedef enum +{ +/* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ======================================= */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation + and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory + related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SecureFault_IRQn = -9, /*!< -9 Secure Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + +/* =========================================== STM32WBA52xx Specific Interrupt Numbers ====================================== */ + WWDG_IRQn = 0, /*!< Window WatchDog interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + RTC_IRQn = 2, /*!< RTC non-secure interrupt */ + RTC_S_IRQn = 3, /*!< RTC secure interrupt */ + TAMP_IRQn = 4, /*!< Tamper global interrupt */ + RAMCFG_IRQn = 5, /*!< RAMCFG global interrupt */ + FLASH_IRQn = 6, /*!< FLASH non-secure global interrupt */ + FLASH_S_IRQn = 7, /*!< FLASH secure global interrupt */ + GTZC_IRQn = 8, /*!< Global TrustZone Controller interrupt */ + RCC_IRQn = 9, /*!< RCC non secure global interrupt */ + RCC_S_IRQn = 10, /*!< RCC secure global interrupt */ + EXTI0_IRQn = 11, /*!< EXTI Line0 interrupt */ + EXTI1_IRQn = 12, /*!< EXTI Line1 interrupt */ + EXTI2_IRQn = 13, /*!< EXTI Line2 interrupt */ + EXTI3_IRQn = 14, /*!< EXTI Line3 interrupt */ + EXTI4_IRQn = 15, /*!< EXTI Line4 interrupt */ + EXTI5_IRQn = 16, /*!< EXTI Line5 interrupt */ + EXTI6_IRQn = 17, /*!< EXTI Line6 interrupt */ + EXTI7_IRQn = 18, /*!< EXTI Line7 interrupt */ + EXTI8_IRQn = 19, /*!< EXTI Line8 interrupt */ + EXTI9_IRQn = 20, /*!< EXTI Line9 interrupt */ + EXTI10_IRQn = 21, /*!< EXTI Line10 interrupt */ + EXTI11_IRQn = 22, /*!< EXTI Line11 interrupt */ + EXTI12_IRQn = 23, /*!< EXTI Line12 interrupt */ + EXTI13_IRQn = 24, /*!< EXTI Line13 interrupt */ + EXTI14_IRQn = 25, /*!< EXTI Line14 interrupt */ + EXTI15_IRQn = 26, /*!< EXTI Line15 interrupt */ + IWDG_IRQn = 27, /*!< IWDG global interrupt */ + SAES_IRQn = 28, /*!< Secure AES global interrupt */ + GPDMA1_Channel0_IRQn = 29, /*!< GPDMA1 Channel 0 global interrupt */ + GPDMA1_Channel1_IRQn = 30, /*!< GPDMA1 Channel 1 global interrupt */ + GPDMA1_Channel2_IRQn = 31, /*!< GPDMA1 Channel 2 global interrupt */ + GPDMA1_Channel3_IRQn = 32, /*!< GPDMA1 Channel 3 global interrupt */ + GPDMA1_Channel4_IRQn = 33, /*!< GPDMA1 Channel 4 global interrupt */ + GPDMA1_Channel5_IRQn = 34, /*!< GPDMA1 Channel 5 global interrupt */ + GPDMA1_Channel6_IRQn = 35, /*!< GPDMA1 Channel 6 global interrupt */ + GPDMA1_Channel7_IRQn = 36, /*!< GPDMA1 Channel 7 global interrupt */ + TIM1_BRK_IRQn = 37, /*!< TIM1 Break interrupt */ + TIM1_UP_IRQn = 38, /*!< TIM1 Update interrupt */ + TIM1_TRG_COM_IRQn = 39, /*!< TIM1 Trigger and Commutation interrupt */ + TIM1_CC_IRQn = 40, /*!< TIM1 Capture Compare interrupt */ + TIM2_IRQn = 41, /*!< TIM2 global interrupt */ + TIM3_IRQn = 42, /*!< TIM3 global interrupt */ + I2C1_EV_IRQn = 43, /*!< I2C1 Event interrupt */ + I2C1_ER_IRQn = 44, /*!< I2C1 Error interrupt */ + SPI1_IRQn = 45, /*!< SPI1 global interrupt */ + USART1_IRQn = 46, /*!< USART1 global interrupt */ + USART2_IRQn = 47, /*!< USART2 global interrupt */ + LPUART1_IRQn = 48, /*!< LPUART1 global interrupt */ + LPTIM1_IRQn = 49, /*!< LPTIM1 global interrupt */ + LPTIM2_IRQn = 50, /*!< LPTIM2 global interrupt */ + TIM16_IRQn = 51, /*!< TIM16 global interrupt */ + TIM17_IRQn = 52, /*!< TIM17 global interrupt */ + I2C3_EV_IRQn = 54, /*!< I2C3 Event interrupt */ + I2C3_ER_IRQn = 55, /*!< I2C3 Error interrupt */ + TSC_IRQn = 57, /*!< Touch Sense Controller global interrupt */ + AES_IRQn = 58, /*!< AES global interrupt */ + RNG_IRQn = 59, /*!< RNG global interrupt */ + FPU_IRQn = 60, /*!< FPU global interrupt */ + HASH_IRQn = 61, /*!< HASH global interrupt */ + PKA_IRQn = 62, /*!< PKA global interrupt */ + SPI3_IRQn = 63, /*!< SPI3 global interrupt */ + ICACHE_IRQn = 64, /*!< Instruction cache global interrupt */ + ADC4_IRQn = 65, /*!< ADC4 global interrupt */ + RADIO_IRQn = 66, /*!< 2.4GHz RADIO global interrupt */ + WKUP_IRQn = 67, /*!< PWR global WKUP pin interrupt */ + HSEM_IRQn = 68, /*!< HSEM non-secure global interrupt */ + HSEM_S_IRQn = 69, /*!< HSEM secure global interrupt */ + WKUP_S_IRQn = 70, /*!< PWR secure global WKUP pin interrupt */ +} IRQn_Type; + + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ +/* ------- Start of section using anonymous unions and disabling warnings ------- */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/* -------- Configuration of the STM32WBAxx System On Chip ------ */ + +/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */ +#define __CM33_REV 0x0000U /* Core revision r0p1 */ +#define __SAUREGION_PRESENT 1U /* SAU regions present */ +#define __MPU_PRESENT 1U /* MPU present */ +#define __VTOR_PRESENT 1U /* VTOR present */ +#define __NVIC_PRIO_BITS 4U /* Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /* FPU present */ +#define __DSP_PRESENT 1U /* DSP extension present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include /*!< ARM Cortex-M33 processor and core peripherals */ +#include "system_stm32wbaxx.h" /*!< system_stm32wbaxx System */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ +/** @addtogroup STM32WBAxx_peripherals + * @{ + */ + +/** + * @brief Analog to Digital Converter (ADC) + */ +typedef struct +{ + __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR; /*!< ADC sampling time register, Address offset: 0x14 */ + uint32_t RESERVED0[2]; /*!< Reserved, Address offset: 0x18-0x1C */ + __IO uint32_t AWD1TR; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ + __IO uint32_t AWD2TR; /*!< ADC watchdog threshold register, Address offset: 0x24 */ + __IO uint32_t CHSELR; /*!< ADC channel select register, Address offset: 0x28 */ + __IO uint32_t AWD3TR; /*!< ADC watchdog threshold register, Address offset: 0x02C */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x30-0x3C */ + __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ + __IO uint32_t PWRR; /*!< ADC power register, Address offset: 0x44 */ + uint32_t RESERVED2[22];/*!< Reserved, Address offset: 0x48-0x9C */ + __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 configuration register, Address offset: 0xA4 */ + uint32_t RESERVED3[7]; /*!< Reserved, Address offset: 0xA8-0xC0 */ + __IO uint32_t CALFACT; /*!< ADC Calibration factor register, Address offset: 0xC4 */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: 0x308 */ +} ADC_Common_TypeDef; + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED0; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief AES hardware accelerator + */ +typedef struct +{ + __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */ + __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */ + __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */ + __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */ + __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */ + __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */ + __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */ + __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */ + __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */ + __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */ + __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */ + __IO uint32_t KEYR4; /*!< AES key register 4, Address offset: 0x30 */ + __IO uint32_t KEYR5; /*!< AES key register 5, Address offset: 0x34 */ + __IO uint32_t KEYR6; /*!< AES key register 6, Address offset: 0x38 */ + __IO uint32_t KEYR7; /*!< AES key register 7, Address offset: 0x3C */ + __IO uint32_t SUSP0R; /*!< AES Suspend register 0, Address offset: 0x40 */ + __IO uint32_t SUSP1R; /*!< AES Suspend register 1, Address offset: 0x44 */ + __IO uint32_t SUSP2R; /*!< AES Suspend register 2, Address offset: 0x48 */ + __IO uint32_t SUSP3R; /*!< AES Suspend register 3, Address offset: 0x4C */ + __IO uint32_t SUSP4R; /*!< AES Suspend register 4, Address offset: 0x50 */ + __IO uint32_t SUSP5R; /*!< AES Suspend register 5, Address offset: 0x54 */ + __IO uint32_t SUSP6R; /*!< AES Suspend register 6, Address offset: 0x58 */ + __IO uint32_t SUSP7R; /*!< AES Suspend register 7, Address offset: 0x5C */ + uint32_t RESERVED1[168];/*!< Reserved, Address offset: 0x60 -- 0x2FC */ + __IO uint32_t IER; /*!< AES Interrupt Enable Register, Address offset: 0x300 */ + __IO uint32_t ISR; /*!< AES Interrupt Status Register, Address offset: 0x304 */ + __IO uint32_t ICR; /*!< AES Interrupt Clear Register, Address offset: 0x308 */ +} AES_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t SCR; /*!< Debug MCU status and configuration register, Address offset: 0x04 */ + __IO uint32_t APB1LFZR; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ + __IO uint32_t APB1HFZR; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ + __IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ + uint32_t RESERVED1[4];/*!< Reserved, 0x14 - 0x20 */ + __IO uint32_t APB7FZR; /*!< Debug MCU APB7 freeze register, Address offset: 0x24 */ + __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x28 */ +} DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ +typedef struct +{ + __IO uint32_t SECCFGR; /*!< DMA secure configuration register, Address offset: 0x00 */ + __IO uint32_t PRIVCFGR; /*!< DMA privileged configuration register, Address offset: 0x04 */ + __IO uint32_t RCFGLOCKR; /*!< DMA secure and privilege lock register, Address offset: 0x08 */ + __IO uint32_t MISR; /*!< DMA non secure masked interrupt status register, Address offset: 0x0C */ + __IO uint32_t SMISR; /*!< DMA secure masked interrupt status register, Address offset: 0x10 */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */ + uint32_t RESERVED1[2]; /*!< Reserved 1, Address offset: 0x54 -- 0x58 */ + __IO uint32_t CFCR; /*!< DMA channel x flag clear register, Address offset: 0x5C + (x * 0x80) */ + __IO uint32_t CSR; /*!< DMA channel x flag status register, Address offset: 0x60 + (x * 0x80) */ + __IO uint32_t CCR; /*!< DMA channel x control register, Address offset: 0x64 + (x * 0x80) */ + uint32_t RESERVED2[10]; /*!< Reserved 2, Address offset: 0x68 -- 0x8C */ + __IO uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: 0x90 + (x * 0x80) */ + __IO uint32_t CTR2; /*!< DMA channel x transfer register 2, Address offset: 0x94 + (x * 0x80) */ + __IO uint32_t CBR1; /*!< DMA channel x block register 1, Address offset: 0x98 + (x * 0x80) */ + __IO uint32_t CSAR; /*!< DMA channel x source address register, Address offset: 0x9C + (x * 0x80) */ + __IO uint32_t CDAR; /*!< DMA channel x destination address register, Address offset: 0xA0 + (x * 0x80) */ + uint32_t RESERVED3[10]; /*!< Reserved 3, Address offset: 0xA4 -- 0xC8 */ + __IO uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: 0xCC + (x * 0x80) */ +} DMA_Channel_TypeDef; + +/** + * @brief Asynch Interrupt/Event Controller (EXTI) + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR1; /*!< EXTI Security Configuration Register 1, Address offset: 0x14 */ + __IO uint32_t PRIVCFGR1; /*!< EXTI Privilege Configuration Register 1, Address offset: 0x18 */ + uint32_t RESERVED1[17]; /*!< Reserved 1, 0x1C -- 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXIT External Interrupt Configuration Register, 0x60 -- 0x6C */ + __IO uint32_t LOCKR; /*!< EXTI Lock Register, Address offset: 0x70 */ + uint32_t RESERVED2[3]; /*!< Reserved 2, 0x74 -- 0x7C */ + __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + uint32_t RESERVED0; /*!< RESERVED1, Address offset: 0x04 */ + __IO uint32_t NSKEYR; /*!< FLASH non-secure key register, Address offset: 0x08 */ + __IO uint32_t SECKEYR; /*!< FLASH secure key register, Address offset: 0x0C */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x10 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x14 */ + __IO uint32_t PDKEYR; /*!< FLASH Bank power-down key register, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ + __IO uint32_t NSSR; /*!< FLASH non-secure status register, Address offset: 0x20 */ + __IO uint32_t SECSR; /*!< FLASH secure status register, Address offset: 0x24 */ + __IO uint32_t NSCR1; /*!< FLASH non-secure control register, Address offset: 0x28 */ + __IO uint32_t SECCR1; /*!< FLASH secure control register, Address offset: 0x2C */ + __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x30 */ + __IO uint32_t OPSR; /*!< FLASH OPSR register, Address offset: 0x34 */ + __IO uint32_t NSCR2; /*!< FLASH non-secure control register, Address offset: 0x38 */ + __IO uint32_t SECCR2; /*!< FLASH secure control register, Address offset: 0x3C */ + __IO uint32_t OPTR; /*!< FLASH option control register, Address offset: 0x40 */ + __IO uint32_t NSBOOTADD0R; /*!< FLASH non-secure boot address 0 register, Address offset: 0x44 */ + __IO uint32_t NSBOOTADD1R; /*!< FLASH non-secure boot address 1 register, Address offset: 0x48 */ + __IO uint32_t SECBOOTADD0R; /*!< FLASH secure boot address 0 register, Address offset: 0x4C */ + __IO uint32_t SECWMR1; /*!< FLASH secure watermark1 register 1, Address offset: 0x50 */ + __IO uint32_t SECWMR2; /*!< FLASH secure watermark1 register 2, Address offset: 0x54 */ + __IO uint32_t WRPAR; /*!< FLASH WRP area A address register, Address offset: 0x58 */ + __IO uint32_t WRPBR; /*!< FLASH WRP area B address register, Address offset: 0x5C */ + uint32_t RESERVED3[4]; /*!< Reserved3, Address offset: 0x60-0x6C */ + __IO uint32_t OEM1KEYR1; /*!< FLASH OEM1 key register 1, Address offset: 0x70 */ + __IO uint32_t OEM1KEYR2; /*!< FLASH OEM1 key register 2, Address offset: 0x74 */ + __IO uint32_t OEM2KEYR1; /*!< FLASH OEM2 key register 1, Address offset: 0x78 */ + __IO uint32_t OEM2KEYR2; /*!< FLASH OEM2 key register 2, Address offset: 0x7C */ + __IO uint32_t SECBBR1; /*!< FLASH secure block-based bank register 1, Address offset: 0x80 */ + __IO uint32_t SECBBR2; /*!< FLASH secure block-based bank register 2, Address offset: 0x84 */ + __IO uint32_t SECBBR3; /*!< FLASH secure block-based bank register 3, Address offset: 0x88 */ + __IO uint32_t SECBBR4; /*!< FLASH secure block-based bank register 4, Address offset: 0x8C */ + uint32_t RESERVED4[12]; /*!< Reserved4, Address offset: 0x90-0xBC */ + __IO uint32_t SECHDPCR; /*!< FLASH secure HDP control register, Address offset: 0xC0 */ + __IO uint32_t PRIVCFGR; /*!< FLASH privilege configuration register, Address offset: 0xC4 */ + uint32_t RESERVED5[2]; /*!< Reserved5, Address offset: 0xC8-0xCC */ + __IO uint32_t PRIVBBR1; /*!< FLASH privilege block-based bank register 1, Address offset: 0xD0 */ + __IO uint32_t PRIVBBR2; /*!< FLASH privilege block-based bank register 2, Address offset: 0xD4 */ + __IO uint32_t PRIVBBR3; /*!< FLASH privilege block-based bank register 3, Address offset: 0xD8 */ + __IO uint32_t PRIVBBR4; /*!< FLASH privilege block-based bank register 4, Address offset: 0xDC */ +} FLASH_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ + uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register, Address offset: 0x30 */ +} GPIO_TypeDef; + +/** + * @brief Global TrustZone Controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< TZSC control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t SECCFGR1; /*!< TZSC secure configuration register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR2; /*!< TZSC secure configuration register 2, Address offset: 0x14 */ + __IO uint32_t SECCFGR3; /*!< TZSC secure configuration register 3, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ + __IO uint32_t PRIVCFGR1; /*!< TZSC privilege configuration register 1, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR2; /*!< TZSC privilege configuration register 2, Address offset: 0x24 */ + __IO uint32_t PRIVCFGR3; /*!< TZSC privilege configuration register 3, Address offset: 0x28 */ +} GTZC_TZSC_TypeDef; + +typedef struct +{ + __IO uint32_t CR; /*!< MPCBBx control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t CFGLOCK; /*!< MPCBBx lock register, Address offset: 0x10 */ + uint32_t RESERVED2[59]; /*!< Reserved2, Address offset: 0x14-0xFC */ + __IO uint32_t SECCFGR[4]; /*!< MPCBBx security configuration registers, Address offset: 0x100-0x10C */ + uint32_t RESERVED3[60]; /*!< Reserved3, Address offset: 0x110-0x1FC */ + __IO uint32_t PRIVCFGR[4]; /*!< MPCBBx privilege configuration registers, Address offset: 0x200-0x20C */ +} GTZC_MPCBB_TypeDef; + +typedef struct +{ + __IO uint32_t IER1; /*!< TZIC interrupt enable register 1, Address offset: 0x00 */ + __IO uint32_t IER2; /*!< TZIC interrupt enable register 2, Address offset: 0x04 */ + __IO uint32_t IER3; /*!< TZIC interrupt enable register 3, Address offset: 0x08 */ + __IO uint32_t IER4; /*!< TZIC interrupt enable register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< TZIC status register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< TZIC status register 2, Address offset: 0x14 */ + __IO uint32_t SR3; /*!< TZIC status register 3, Address offset: 0x18 */ + __IO uint32_t SR4; /*!< TZIC status register 4, Address offset: 0x1C */ + __IO uint32_t FCR1; /*!< TZIC flag clear register 1, Address offset: 0x20 */ + __IO uint32_t FCR2; /*!< TZIC flag clear register 2, Address offset: 0x24 */ + __IO uint32_t FCR3; /*!< TZIC flag clear register 3, Address offset: 0x28 */ + __IO uint32_t FCR4; /*!< TZIC flag clear register 3, Address offset: 0x2C */ +} GTZC_TZIC_TypeDef; + +/** + * @brief HASH + */ +typedef struct +{ + __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ + __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ + __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ + __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ + __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ + __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ + uint32_t RESERVED0[52]; /*!< Reserved, Address offset: 0x28-0xF4 */ + __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */ +} HASH_TypeDef; + +/** + * @brief HASH_DIGEST + */ +typedef struct +{ + __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */ +} HASH_DIGEST_TypeDef; + +/** + * @brief HW Semaphore HSEM + */ +typedef struct +{ + __IO uint32_t R[16]; /*!< HSEM 2-step write lock and read back registers, Address offset: 00h-3Ch */ + uint32_t Reserved1[16]; /*!< Reserved Address offset: 40h-7Ch */ + __IO uint32_t RLR[16]; /*!< HSEM 1-step read lock registers, Address offset: 80h-BCh */ + uint32_t Reserved2[16]; /*!< Reserved Address offset: C0h-FCh */ + __IO uint32_t IER; /*!< HSEM interrupt enable register, Address offset: 100h */ + __IO uint32_t ICR; /*!< HSEM interrupt clear register, Address offset: 104h */ + __IO uint32_t ISR; /*!< HSEM interrupt status register, Address offset: 108h */ + __IO uint32_t MISR; /*!< HSEM masked interrupt status register, Address offset: 10Ch */ + uint32_t Reserved3[28]; /*!< Reserved Address offset: 110h-17Ch */ + __IO uint32_t SIER; /*!< HSEM secure interrupt enable register, Address offset: 180h */ + __IO uint32_t SICR; /*!< HSEM secure interrupt clear register, Address offset: 184h */ + __IO uint32_t SISR; /*!< HSEM secure interrupt status register, Address offset: 188h */ + __IO uint32_t SMISR; /*!< HSEM secure masked interrupt status register, Address offset: 18Ch */ + uint32_t Reserved4[28]; /*!< Reserved Address offset: 190h-1FCh */ + __IO uint32_t SECCFGR; /*!< HSEM security configuration register, Address offset: 200h */ + uint32_t Reserved5[3]; /*!< Reserved Address offset: 204h-20Ch */ + __IO uint32_t PRIVCFGR; /*!< HSEM privilege configuration register, Address offset: 210h */ + uint32_t Reserved6[7]; /*!< Reserved Address offset: 214h-22Ch */ + __IO uint32_t CR; /*!< HSEM Semaphore clear register, Address offset: 230h */ + __IO uint32_t KEYR; /*!< HSEM Semaphore clear key register, Address offset: 234h */ +} HSEM_TypeDef; + +typedef struct +{ + __IO uint32_t IER; /*!< HSEM interrupt enable register, Address offset: 0h */ + __IO uint32_t ICR; /*!< HSEM interrupt clear register, Address offset: 4h */ + __IO uint32_t ISR; /*!< HSEM interrupt status register, Address offset: 8h */ + __IO uint32_t MISR; /*!< HSEM masked interrupt status register, Address offset: Ch */ + uint32_t Reserved3[28]; /*!< Reserved Address offset: 10h-7Ch */ + __IO uint32_t SIER; /*!< HSEM secure interrupt enable register, Address offset: 80h */ + __IO uint32_t SICR; /*!< HSEM secure interrupt clear register, Address offset: 84h */ + __IO uint32_t SISR; /*!< HSEM secure interrupt status register, Address offset: 88h */ + __IO uint32_t SMISR; /*!< HSEM secure masked interrupt status register, Address offset: 8Ch */ +} HSEM_Common_TypeDef; + +/** + * @brief Instruction Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< ICACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< ICACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< ICACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< ICACHE Flag clear register, Address offset: 0x0C */ + __IO uint32_t HMONR; /*!< ICACHE hit monitor register, Address offset: 0x10 */ + __IO uint32_t MMONR; /*!< ICACHE miss monitor register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t CRR0; /*!< ICACHE region 0 configuration register, Address offset: 0x20 */ + __IO uint32_t CRR1; /*!< ICACHE region 1 configuration register, Address offset: 0x24 */ + __IO uint32_t CRR2; /*!< ICACHE region 2 configuration register, Address offset: 0x28 */ + __IO uint32_t CRR3; /*!< ICACHE region 3 configuration register, Address offset: 0x2C */ +} ICACHE_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ + __IO uint32_t AUTOCR; /*!< I2C Autonomous mode control register, Address offset: 0x2C */ +} I2C_TypeDef; + +/** + * @brief IWDG + */ +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ + __IO uint32_t EWCR; /*!< IWDG Early Wakeup register, Address offset: 0x14 */ +} IWDG_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t DIER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CCR1; /*!< LPTIM Capture/Compare register 1, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ + __IO uint32_t RCR; /*!< LPTIM Repetition register, Address offset: 0x28 */ + __IO uint32_t CCMR1; /*!< LPTIM Capture/Compare mode register, Address offset: 0x2C */ + __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x30 */ + __IO uint32_t CCR2; /*!< LPTIM Capture/Compare register 2, Address offset: 0x34 */ +} LPTIM_TypeDef; + +/** + * @brief PKA + */ +typedef struct +{ + __IO uint32_t CR; /*!< PKA control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< PKA status register, Address offset: 0x04 */ + __IO uint32_t CLRFR; /*!< PKA clear flag register, Address offset: 0x08 */ + uint32_t Reserved[253]; /*!< Reserved memory area Address offset: 0x0C -> 0x03FC */ + __IO uint32_t RAM[1334]; /*!< PKA RAM Address offset: 0x400 -> 0x18D4 */ +} PKA_TypeDef; + +/** + * @brief Power Control + */ +typedef struct +{ + __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */ + __IO uint32_t VOSR; /*!< PWR voltage scaling register, Address offset: 0x0C */ + __IO uint32_t SVMCR; /*!< PWR supply voltage monitoring control register, Address offset: 0x10 */ + __IO uint32_t WUCR1; /*!< PWR wakeup control register 1, Address offset: 0x14 */ + __IO uint32_t WUCR2; /*!< PWR wakeup control register 2, Address offset: 0x18 */ + __IO uint32_t WUCR3; /*!< PWR wakeup control register 3, Address offset: 0x1C */ + __IO uint32_t RESERVED0[2]; /*!< Reserved, Address offset: 0x20 -- 0x24 */ + __IO uint32_t DBPR; /*!< PWR disable backup domain register, Address offset: 0x28 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< PWR Security configuration register, Address offset: 0x30 */ + __IO uint32_t PRIVCFGR; /*!< PWR privilege control register, Address offset: 0x34 */ + __IO uint32_t SR; /*!< PWR status register, Address offset: 0x38 */ + __IO uint32_t SVMSR; /*!< PWR supply voltage monitoring status register, Address offset: 0x3C */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x40 */ + __IO uint32_t WUSR; /*!< PWR wakeup status register, Address offset: 0x44 */ + __IO uint32_t WUSCR; /*!< PWR wakeup status clear register, Address offset: 0x48 */ + __IO uint32_t APCR; /*!< PWR apply pull configuration register, Address offset: 0x4C */ + __IO uint32_t IORETENRA; /*!< PWR Port A IO retention in Standby register, Address offset: 0x50 */ + __IO uint32_t IORETRA; /*!< PWR Port A IO retention status in Standby register, Address offset: 0x54 */ + __IO uint32_t IORETENRB; /*!< PWR Port B IO retention in Standby register, Address offset: 0x58 */ + __IO uint32_t IORETRB; /*!< PWR Port B IO retention status in Standby register, Address offset: 0x5C */ + __IO uint32_t IORETENRC; /*!< PWR Port C IO retention in Standby register, Address offset: 0x60 */ + __IO uint32_t IORETRC; /*!< PWR Port C IO retention status in Standby register, Address offset: 0x64 */ + uint32_t RESERVED3[8]; /*!< Reserved, Address offset: 0x68 -- 0x84 */ + __IO uint32_t IORETENRH; /*!< PWR Port H IO retention in Standby register, Address offset: 0x88 */ + __IO uint32_t IORETRH; /*!< PWR Port H IO retention status in Standby register, Address offset: 0x8C */ + uint32_t RESERVED4[28]; /*!< Reserved, Address offset: 0x90 -- 0xFC */ + __IO uint32_t RADIOSCR; /*!< PWR 2.4 GHZ radio status and control register, Address offset: 0x100 */ +} PWR_TypeDef; + +/** + * @brief SRAMs configuration controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< Control Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< Interrupt enable register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< Interrupt status register, Address offset: 0x08 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x0C */ + __IO uint32_t PEAR; /*!< Parity error address register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< Interrupt clear register, Address offset: 0x14 */ + __IO uint32_t WPR1; /*!< Write protection register 1, Address offset: 0x18 */ + __IO uint32_t WPR2; /*!< Write protection register 2, Address offset: 0x1C */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x20 -- 0x24 */ + __IO uint32_t ERKEYR; /*!< Erase key register, Address offset: 0x28 */ +}RAMCFG_TypeDef; + +/** + * @brief Reset and Clock Control + */ +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register Address offset: 0x000 */ + uint32_t RESERVED0[3]; /*!< Reserved 0x004 -- 0x00C */ + __IO uint32_t ICSCR3; /*!< RCC internal clock sources calibration register 3 Address offset: 0x010 */ + uint32_t RESERVED1[2]; /*!< Reserved 0x014 -- 0x018 */ + __IO uint32_t CFGR1; /*!< RCC clock configuration register 1 Address offset: 0x01C */ + __IO uint32_t CFGR2; /*!< RCC clock configuration register 2 Address offset: 0x020 */ + __IO uint32_t CFGR3; /*!< RCC clock configuration register 3 Address offset: 0x024 */ + __IO uint32_t PLL1CFGR; /*!< PLL1 Configuration Register Address offset: 0x028 */ + uint32_t RESERVED2[2]; /*!< Reserved 0x02C -- 0x030 */ + __IO uint32_t PLL1DIVR; /*!< PLL1 Dividers Configuration Register Address offset: 0x034 */ + __IO uint32_t PLL1FRACR; /*!< PLL1 Fractional Divider Configuration Register Address offset: 0x038 */ + uint32_t RESERVED3[5]; /*!< Reserved 0x03C -- 0x04C */ + __IO uint32_t CIER; /*!< Clock Interrupt Enable Register Address offset: 0x050 */ + __IO uint32_t CIFR; /*!< Clock Interrupt Flag Register Address offset: 0x054 */ + __IO uint32_t CICR; /*!< Clock Interrupt Clear Register Address offset: 0x058 */ + uint32_t RESERVED4; /*!< Reserved Address offset: 0x05C */ + __IO uint32_t AHB1RSTR; /*!< AHB1 Peripherals Reset Register Address offset: 0x060 */ + __IO uint32_t AHB2RSTR; /*!< AHB2 Peripherals Reset Register Address offset: 0x064 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x068 */ + __IO uint32_t AHB4RSTR; /*!< AHB4 Peripherals Reset Register Address offset: 0x06C */ + __IO uint32_t AHB5RSTR; /*!< AHB5 Peripherals Reset Register Address offset: 0x070 */ + __IO uint32_t APB1RSTR1; /*!< APB1 Peripherals Reset Low Register Address offset: 0x074 */ + __IO uint32_t APB1RSTR2; /*!< APB1 Peripherals Reset High Register Address offset: 0x078 */ + __IO uint32_t APB2RSTR; /*!< APB2 Peripherals Reset Register Address offset: 0x07C */ + __IO uint32_t APB7RSTR; /*!< APB7 Peripherals Reset Register Address offset: 0x080 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x084 */ + __IO uint32_t AHB1ENR; /*!< AHB1 Peripherals Clock Enable Register Address offset: 0x088 */ + __IO uint32_t AHB2ENR; /*!< AHB2 Peripherals Clock Enable Register Address offset: 0x08C */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x090 */ + __IO uint32_t AHB4ENR; /*!< AHB4 Peripherals Clock Enable Register Address offset: 0x094 */ + __IO uint32_t AHB5ENR; /*!< AHB5 Peripherals Clock Enable Register Address offset: 0x098 */ + __IO uint32_t APB1ENR1; /*!< APB1 Peripherals Clock Enable Low Register Address offset: 0x09C */ + __IO uint32_t APB1ENR2; /*!< APB1 Peripherals Clock Enable High Register Address offset: 0x0A0 */ + __IO uint32_t APB2ENR; /*!< APB2 Peripherals Clock Enable Register Address offset: 0x0A4 */ + __IO uint32_t APB7ENR; /*!< APB7 Peripherals Clock Enable Register Address offset: 0x0A8 */ + uint32_t RESERVED8; /*!< Reserved Address offset: 0x0AC */ + __IO uint32_t AHB1SMENR; /*!< AHB1 Peripherals Clock Low Power Enable Register Address offset: 0x0B0 */ + __IO uint32_t AHB2SMENR; /*!< AHB2 Peripherals Clock Low Power Enable Register Address offset: 0x0B4 */ + uint32_t RESERVED9; /*!< Reserved Address offset: 0x0B8 */ + __IO uint32_t AHB4SMENR; /*!< AHB4 Peripherals Clock Low Power Enable Register Address offset: 0x0BC */ + __IO uint32_t AHB5SMENR; /*!< AHB5 Peripherals Clock Low Power Enable Register Address offset: 0x0C0 */ + __IO uint32_t APB1SMENR1; /*!< APB1 Peripherals Clock Low Power Enable Low Register Address offset: 0x0C4 */ + __IO uint32_t APB1SMENR2; /*!< APB1 Peripherals Clock Low Power Enable High Register Address offset: 0x0C8 */ + __IO uint32_t APB2SMENR; /*!< APB2 Peripherals Clock Low Power Enable Register Address offset: 0x0CC */ + __IO uint32_t APB7SMENR; /*!< APB7 Peripherals Clock Low Power Enable Register Address offset: 0x0D0 */ + uint32_t RESERVED10[3]; /*!< Reserved 0x0D4 -- 0x0DC */ + __IO uint32_t CCIPR1; /*!< IPs Clocks Configuration Register 1 Address offset: 0x0E0 */ + __IO uint32_t CCIPR2; /*!< IPs Clocks Configuration Register 2 Address offset: 0x0E4 */ + __IO uint32_t CCIPR3; /*!< IPs Clocks Configuration Register 3 Address offset: 0x0E8 */ + uint32_t RESERVED11; /*!< Reserved, Address offset: 0x0EC */ + __IO uint32_t BDCR1; /*!< Backup Domain Control Register 1 Address offset: 0x0F0 */ + __IO uint32_t CSR; /*!< V33 Clock Control & Status Register Address offset: 0x0F4 */ + __IO uint32_t BDCR2; /*!< Backup Domain Control Register 2 Address offset: 0x0F8 */ + uint32_t RESERVED12[5]; /*!< Reserved 0x0FC -- 0x010C */ + __IO uint32_t SECCFGR; /*!< RCC secure configuration register Address offset: 0x110 */ + __IO uint32_t PRIVCFGR; /*!< RCC privilege configuration register Address offset: 0x114 */ + uint32_t RESERVED13[58]; /*!< Reserved 0x118 -- 0x1FC */ + __IO uint32_t CFGR4; /*!< RCC clock configuration register 4 Address offset: 0x200 */ + uint32_t RESERVED15; /*!< Reserved Address offset: 0x204 */ + __IO uint32_t RADIOENR; /*!< RCC RADIO peripheral clock enable register Address offset: 0x208 */ + uint32_t RESERVED16; /*!< Reserved Address offset: 0x20C */ + __IO uint32_t ECSCR1; /*!< RCC external clock sources calibration register 1 Address offset: 0x210 */ +} RCC_TypeDef; + +/** + * @brief RNG + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + uint32_t RESERVED; + __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ +} RNG_TypeDef; + +/* +* @brief RTC Specific device feature definitions +*/ +#define RTC_BKP_NB 32U +#define RTC_BACKUP_NB RTC_BKP_NB + +#define RTC_TAMP_NB 6U + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + __IO uint32_t PRIVCFGR; /*!< RTC privilege mode control register, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< RTC secure mode control register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x3C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */ + uint32_t RESERVED3[4];/*!< Reserved, Address offset: 0x58 */ + __IO uint32_t ALRABINR; /*!< RTC alarm A binary mode register, Address offset: 0x70 */ + __IO uint32_t ALRBBINR; /*!< RTC alarm B binary mode register, Address offset: 0x74 */ +} RTC_TypeDef; + +/** + * @brief SPI + */ +typedef struct +{ + __IO uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */ + __IO uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */ + __IO uint32_t IER; /*!< SPI Interrupt Enable register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x14 */ + __IO uint32_t IFCR; /*!< SPI Interrupt/Status Flags Clear register, Address offset: 0x18 */ + __IO uint32_t AUTOCR; /*!< SPI Autonomous Mode Control register, Address offset: 0x1C */ + __IO uint32_t TXDR; /*!< SPI Transmit data register, Address offset: 0x20 */ + uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C */ + __IO uint32_t RXDR; /*!< SPI/I2S data register, Address offset: 0x30 */ + uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */ + __IO uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */ + __IO uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */ + __IO uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */ + __IO uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */ +} SPI_TypeDef; + +/** + * @brief System configuration controller + */ +typedef struct +{ + __IO uint32_t SECCFGR; /*!< SYSCFG secure configuration register, Address offset: 0x00 */ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ + __IO uint32_t FPUIMR; /*!< SYSCFG FPU interrupt mask register, Address offset: 0x08 */ + __IO uint32_t CNSLCKR; /*!< SYSCFG CPU non-secure lock register, Address offset: 0x0C */ + __IO uint32_t CSLCKR; /*!< SYSCFG CPU secure lock register, Address offset: 0x10 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x14 */ + __IO uint32_t MESR; /*!< SYSCFG Memory Erase Status register, Address offset: 0x18 */ + __IO uint32_t CCCSR; /*!< SYSCFG Conpensaion Cell Control&Status register, Address offset: 0x1C */ + __IO uint32_t CCVR; /*!< SYSCFG Conpensaion Cell value register, Address offset: 0x20 */ + __IO uint32_t CCCR; /*!< SYSCFG Conpensaion Cell Code register, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x28 */ + __IO uint32_t RSSCMDR; /*!< SYSCFG RSS command mode register, Address offset: 0x2C */ +} SYSCFG_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< TAMP configuration register 3, Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ + __IO uint32_t ATCR1; /*!< TAMP filter control register 1 Address offset: 0x10 */ + __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ + __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ + __IO uint32_t ATCR2; /*!< TAMP filter control register 2, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< TAMP secure mode control register, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR; /*!< TAMP privilege mode control register, Address offset: 0x24 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x28 */ + __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */ + __IO uint32_t SMISR; /*!< TAMP secure masked interrupt status register, Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ + __IO uint32_t COUNT1R; /*!< TAMP monotonic counter 1 register, Address offset: 0x40 */ + uint32_t RESERVED2[4];/*!< Reserved, Address offset: 0x44 -- 0x50 */ + __IO uint32_t RPCFGR; /*!< TAMP resources protection configuration register, Address offset: 0x54 */ + uint32_t RESERVED3[42];/*!< Reserved, Address offset: 0x58 -- 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ + __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ + __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ + __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ + __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ + __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ + __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ + __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ + __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ + __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ + __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ + __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ + __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ +} TAMP_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ + __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ + __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + __IO uint32_t OR; /*!< TIM option register, Address offset: 0x68 */ + uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x68-0x3D8 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + +/** + * @brief TSC + */ +typedef struct +{ + __IO uint32_t CR; /*!< TSC Control register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< TSC Interrupt Enable register, Address offset: 0x04 */ + __IO uint32_t ICR; /*!< TSC Interrupt Control register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< TSC Interrupt Status register, Address offset: 0x0C */ + __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x2C */ + __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */ + __IO uint32_t IOGXCR[6]; /*!< TSC I/O group x counter register, Address offset: 0x34-48 */ +} TSC_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ + __IO uint32_t AUTOCR; /*!< USART Autonomous mode control register Address offset: 0x30 */ +} USART_TypeDef; + +/** + * @brief WWDG + */ +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/*@}*/ /* end of group STM32WBA52xx_Peripherals */ + +/* -------- End of section using anonymous unions and disabling warnings -------- */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ +/** @addtogroup STM32WBAxx_Peripheral_peripheralAddr + * @{ + */ + +/* Flash, Peripheral and internal SRAMs base addresses - Non secure */ +#define FLASH_BASE_NS 0x08000000UL /*!< FLASH non-secure base address */ +#define SYSTEM_FLASH_BASE_NS 0x0BF88000UL /*!< System FLASH non-secure base address */ +#define SRAM1_BASE_NS 0x20000000UL /*!< SRAM1 non-secure base address */ +#define SRAM2_BASE_NS 0x20010000UL /*!< SRAM2 non-secure base address */ +#define SRAM6_BASE_NS 0x48028000UL /*!< 2.4 GHz RADIO TXRX SRAM non-secure base address */ +#define SEQSRAM_BASE_NS 0x48021000UL /*!< SRAM Sequence / retention non-secure base address */ +#define PERIPH_BASE_NS 0x40000000UL /*!< Peripheral non-secure base address */ +#define DBGMCU_BASE 0xE0044000UL /*!< Debug MCU registers base address */ + +/*!< Memory sizes */ +/* Internal Flash size */ +#define FLASH_SIZE ((((*((uint16_t *)FLASHSIZE_BASE)) == 0xFFFFU)) ? 0x100000U : \ + ((((*((uint16_t *)FLASHSIZE_BASE)) == 0x0000U)) ? 0x100000U : \ + (((uint32_t)(*((uint16_t *)FLASHSIZE_BASE)) & (0xFFFFU)) << 10U))) + +/* Internal SRAMs size */ +#define SRAM1_SIZE 0x00010000UL /*!< SRAM1 = 64 Kbytes */ +#define SRAM2_SIZE 0x00010000UL /*!< SRAM2 = 64 Kbytes */ +#define SRAM6_SIZE 0x00004000UL /*!< 2.4 GHz RADIO TXRX SRAM 16 Kbytes */ +#define SEQSRAM_SIZE 0x00000200UL /*!< SRAM Sequence / retention 512 bytes */ + +/*!< OTP, Engineering bytes, Option bytes defines */ +#define FLASH_OTP_BASE (SYSTEM_FLASH_BASE_NS + 0x00008000UL) +#define FLASH_OTP_SIZE 0x00000200U /*!< 512 bytes OTP (one-time programmable) */ + +#define FLASH_ENGY_BASE (SYSTEM_FLASH_BASE_NS + 0x00008500UL) +#define PACKAGE_BASE (FLASH_ENGY_BASE) /*!< Package data register base address */ +#define UID_BASE (FLASH_ENGY_BASE + 0x00000200UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (FLASH_ENGY_BASE + 0x000002A0UL) /*!< Flash size data register base address */ +#define UID64_BASE (FLASH_ENGY_BASE + 0x00000500UL) /*!< 64-bit Unique device Identification */ + +/* Peripheral memory map - Non secure */ +#define APB1PERIPH_BASE_NS PERIPH_BASE_NS +#define APB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00010000UL) +#define AHB1PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00020000UL) +#define AHB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x02020000UL) +#define APB7PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06000000UL) +#define AHB4PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06020000UL) +#define AHB5PERIPH_BASE_NS (PERIPH_BASE_NS + 0x08020000UL) + +/*!< APB1 Non secure peripherals */ +#define TIM2_BASE_NS APB1PERIPH_BASE_NS +#define TIM3_BASE_NS (APB1PERIPH_BASE_NS + 0x0400UL) +#define WWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x2C00UL) +#define IWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x3000UL) +#define USART2_BASE_NS (APB1PERIPH_BASE_NS + 0x4400UL) +#define I2C1_BASE_NS (APB1PERIPH_BASE_NS + 0x5400UL) +#define LPTIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x9400UL) + +/*!< APB2 Non secure peripherals */ +#define TIM1_BASE_NS (APB2PERIPH_BASE_NS + 0x2C00UL) +#define SPI1_BASE_NS (APB2PERIPH_BASE_NS + 0x3000UL) +#define USART1_BASE_NS (APB2PERIPH_BASE_NS + 0x3800UL) +#define TIM16_BASE_NS (APB2PERIPH_BASE_NS + 0x4400UL) +#define TIM17_BASE_NS (APB2PERIPH_BASE_NS + 0x4800UL) + +/*!< AHB1 Non secure peripherals */ +#define GPDMA1_BASE_NS AHB1PERIPH_BASE_NS +#define FLASH_R_BASE_NS (AHB1PERIPH_BASE_NS + 0x02000UL) +#define CRC_BASE_NS (AHB1PERIPH_BASE_NS + 0x03000UL) +#define TSC_BASE_NS (AHB1PERIPH_BASE_NS + 0x04000UL) +#define RAMCFG_BASE_NS (AHB1PERIPH_BASE_NS + 0x06000UL) +#define ICACHE_BASE_NS (AHB1PERIPH_BASE_NS + 0x10400UL) +#define GTZC_TZSC_BASE_NS (AHB1PERIPH_BASE_NS + 0x12400UL) +#define GTZC_MPCBB1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12C00UL) +#define GTZC_MPCBB2_BASE_NS (AHB1PERIPH_BASE_NS + 0x13000UL) +#define GTZC_MPCBB6_BASE_NS (AHB1PERIPH_BASE_NS + 0x14000UL) + +#define GPDMA1_Channel0_BASE_NS (GPDMA1_BASE_NS + 0x0050UL) +#define GPDMA1_Channel1_BASE_NS (GPDMA1_BASE_NS + 0x00D0UL) +#define GPDMA1_Channel2_BASE_NS (GPDMA1_BASE_NS + 0x0150UL) +#define GPDMA1_Channel3_BASE_NS (GPDMA1_BASE_NS + 0x01D0UL) +#define GPDMA1_Channel4_BASE_NS (GPDMA1_BASE_NS + 0x0250UL) +#define GPDMA1_Channel5_BASE_NS (GPDMA1_BASE_NS + 0x02D0UL) +#define GPDMA1_Channel6_BASE_NS (GPDMA1_BASE_NS + 0x0350UL) +#define GPDMA1_Channel7_BASE_NS (GPDMA1_BASE_NS + 0x03D0UL) + +#define RAMCFG_SRAM1_BASE_NS (RAMCFG_BASE_NS) +#define RAMCFG_SRAM2_BASE_NS (RAMCFG_BASE_NS + 0x0040UL) +#define RAMCFG_SRAM6_BASE_NS (RAMCFG_BASE_NS + 0x0140UL) + +/*!< AHB2 Non secure peripherals */ +#define GPIOA_BASE_NS AHB2PERIPH_BASE_NS +#define GPIOB_BASE_NS (AHB2PERIPH_BASE_NS + 0x00400UL) +#define GPIOC_BASE_NS (AHB2PERIPH_BASE_NS + 0x00800UL) +#define GPIOH_BASE_NS (AHB2PERIPH_BASE_NS + 0x01C00UL) +#define AES_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0000UL) +#define HASH_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0400UL) +#define HASH_DIGEST_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0710UL) +#define RNG_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0800UL) +#define SAES_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0C00UL) +#define HSEM_BASE_NS (AHB2PERIPH_BASE_NS + 0xA1C00UL) +#define PKA_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2000UL) +#define PKA_RAM_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2400UL) + +/*!< APB7 Non secure peripherals */ +#define SYSCFG_BASE_NS (APB7PERIPH_BASE_NS + 0x0400UL) +#define SPI3_BASE_NS (APB7PERIPH_BASE_NS + 0x2000UL) +#define LPUART1_BASE_NS (APB7PERIPH_BASE_NS + 0x2400UL) +#define I2C3_BASE_NS (APB7PERIPH_BASE_NS + 0x2800UL) +#define LPTIM1_BASE_NS (APB7PERIPH_BASE_NS + 0x4400UL) +#define RTC_BASE_NS (APB7PERIPH_BASE_NS + 0x7800UL) +#define TAMP_BASE_NS (APB7PERIPH_BASE_NS + 0x7C00UL) + +/*!< AHB4 Non secure peripherals */ +#define PWR_BASE_NS (AHB4PERIPH_BASE_NS + 0x0800UL) +#define RCC_BASE_NS (AHB4PERIPH_BASE_NS + 0x0C00UL) +#define ADC4_BASE_NS (AHB4PERIPH_BASE_NS + 0x1000UL) +#define ADC4_COMMON_BASE_NS (AHB4PERIPH_BASE_NS + 0x1308UL) +#define EXTI_BASE_NS (AHB4PERIPH_BASE_NS + 0x2000UL) + +/*!< AHB5 Non secure peripherals */ +#define RADIO_BASE_NS AHB5PERIPH_BASE_NS + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/* Flash, Peripheral and internal SRAMs base addresses - Secure */ +#define FLASH_BASE_S 0x0C000000UL /*!< FLASH secure base address */ +#define SYSTEM_FLASH_BASE_S 0x0FF80000UL /*!< System FLASH non-secure base address */ +#define SRAM1_BASE_S 0x30000000UL /*!< SRAM1 secure base address */ +#define SRAM2_BASE_S 0x30010000UL /*!< SRAM2 secure base address */ +#define SRAM6_BASE_S 0x58028000UL /*!< 2.4 GHz RADIO TXRX SRAM secure base address */ +#define SEQSRAM_BASE_S 0x58021000UL /*!< SRAM Sequence / retention non-secure base address */ +#define PERIPH_BASE_S 0x50000000UL /*!< Peripheral secure base address */ + +/* Peripheral memory map - Secure */ +#define APB1PERIPH_BASE_S PERIPH_BASE_S +#define APB2PERIPH_BASE_S (PERIPH_BASE_S + 0x00010000UL) +#define AHB1PERIPH_BASE_S (PERIPH_BASE_S + 0x00020000UL) +#define AHB2PERIPH_BASE_S (PERIPH_BASE_S + 0x02020000UL) +#define APB7PERIPH_BASE_S (PERIPH_BASE_S + 0x06000000UL) +#define AHB4PERIPH_BASE_S (PERIPH_BASE_S + 0x06020000UL) +#define AHB5PERIPH_BASE_S (PERIPH_BASE_S + 0x08020000UL) + +/*!< APB1 Secure peripherals */ +#define TIM2_BASE_S APB1PERIPH_BASE_S +#define TIM3_BASE_S (APB1PERIPH_BASE_S + 0x0400UL) +#define WWDG_BASE_S (APB1PERIPH_BASE_S + 0x2C00UL) +#define IWDG_BASE_S (APB1PERIPH_BASE_S + 0x3000UL) +#define USART2_BASE_S (APB1PERIPH_BASE_S + 0x4400UL) +#define I2C1_BASE_S (APB1PERIPH_BASE_S + 0x5400UL) +#define LPTIM2_BASE_S (APB1PERIPH_BASE_S + 0x9400UL) + +/*!< APB2 Secure peripherals */ +#define TIM1_BASE_S (APB2PERIPH_BASE_S + 0x2C00UL) +#define SPI1_BASE_S (APB2PERIPH_BASE_S + 0x3000UL) +#define USART1_BASE_S (APB2PERIPH_BASE_S + 0x3800UL) +#define TIM16_BASE_S (APB2PERIPH_BASE_S + 0x4400UL) +#define TIM17_BASE_S (APB2PERIPH_BASE_S + 0x4800UL) + +/*!< AHB1 Secure peripherals */ +#define GPDMA1_BASE_S AHB1PERIPH_BASE_S +#define FLASH_R_BASE_S (AHB1PERIPH_BASE_S + 0x02000UL) +#define CRC_BASE_S (AHB1PERIPH_BASE_S + 0x03000UL) +#define TSC_BASE_S (AHB1PERIPH_BASE_S + 0x04000UL) +#define RAMCFG_BASE_S (AHB1PERIPH_BASE_S + 0x06000UL) +#define ICACHE_BASE_S (AHB1PERIPH_BASE_S + 0x10400UL) +#define GTZC_TZSC_BASE_S (AHB1PERIPH_BASE_S + 0x12400UL) +#define GTZC_TZIC_BASE_S (AHB1PERIPH_BASE_S + 0x12800UL) +#define GTZC_MPCBB1_BASE_S (AHB1PERIPH_BASE_S + 0x12C00UL) +#define GTZC_MPCBB2_BASE_S (AHB1PERIPH_BASE_S + 0x13000UL) +#define GTZC_MPCBB6_BASE_S (AHB1PERIPH_BASE_S + 0x14000UL) + +#define GPDMA1_Channel0_BASE_S (GPDMA1_BASE_S + 0x0050UL) +#define GPDMA1_Channel1_BASE_S (GPDMA1_BASE_S + 0x00D0UL) +#define GPDMA1_Channel2_BASE_S (GPDMA1_BASE_S + 0x0150UL) +#define GPDMA1_Channel3_BASE_S (GPDMA1_BASE_S + 0x01D0UL) +#define GPDMA1_Channel4_BASE_S (GPDMA1_BASE_S + 0x0250UL) +#define GPDMA1_Channel5_BASE_S (GPDMA1_BASE_S + 0x02D0UL) +#define GPDMA1_Channel6_BASE_S (GPDMA1_BASE_S + 0x0350UL) +#define GPDMA1_Channel7_BASE_S (GPDMA1_BASE_S + 0x03D0UL) + +#define RAMCFG_SRAM1_BASE_S (RAMCFG_BASE_S) +#define RAMCFG_SRAM2_BASE_S (RAMCFG_BASE_S + 0x0040UL) +#define RAMCFG_SRAM6_BASE_S (RAMCFG_BASE_S + 0x0140UL) + +/*!< AHB2 Secure peripherals */ +#define GPIOA_BASE_S AHB2PERIPH_BASE_S +#define GPIOB_BASE_S (AHB2PERIPH_BASE_S + 0x00400UL) +#define GPIOC_BASE_S (AHB2PERIPH_BASE_S + 0x00800UL) +#define GPIOH_BASE_S (AHB2PERIPH_BASE_S + 0x01C00UL) +#define AES_BASE_S (AHB2PERIPH_BASE_S + 0xA0000UL) +#define HASH_BASE_S (AHB2PERIPH_BASE_S + 0xA0400UL) +#define HASH_DIGEST_BASE_S (AHB2PERIPH_BASE_S + 0xA0710UL) +#define RNG_BASE_S (AHB2PERIPH_BASE_S + 0xA0800UL) +#define SAES_BASE_S (AHB2PERIPH_BASE_S + 0xA0C00UL) +#define HSEM_BASE_S (AHB2PERIPH_BASE_S + 0xA1C00UL) +#define PKA_BASE_S (AHB2PERIPH_BASE_S + 0xA2000UL) +#define PKA_RAM_BASE_S (AHB2PERIPH_BASE_S + 0xA2400UL) + +/*!< APB7 Secure peripherals */ +#define SYSCFG_BASE_S (APB7PERIPH_BASE_S + 0x0400UL) +#define SPI3_BASE_S (APB7PERIPH_BASE_S + 0x2000UL) +#define LPUART1_BASE_S (APB7PERIPH_BASE_S + 0x2400UL) +#define I2C3_BASE_S (APB7PERIPH_BASE_S + 0x2800UL) +#define LPTIM1_BASE_S (APB7PERIPH_BASE_S + 0x4400UL) +#define RTC_BASE_S (APB7PERIPH_BASE_S + 0x7800UL) +#define TAMP_BASE_S (APB7PERIPH_BASE_S + 0x7C00UL) + +/*!< AHB4 Secure peripherals */ +#define PWR_BASE_S (AHB4PERIPH_BASE_S + 0x0800UL) +#define RCC_BASE_S (AHB4PERIPH_BASE_S + 0x0C00UL) +#define ADC4_BASE_S (AHB4PERIPH_BASE_S + 0x1000UL) +#define ADC4_COMMON_BASE_S (AHB4PERIPH_BASE_S + 0x1308UL) +#define EXTI_BASE_S (AHB4PERIPH_BASE_S + 0x2000UL) + +/*!< AHB5 Secure peripherals */ +#define RADIO_BASE_S AHB5PERIPH_BASE_S +#endif + +/************ RSSLIB SAU system Flash region definition constants *************/ +#define RSSLIB_SYS_FLASH_NS_PFUNC_START (SYSTEM_FLASH_BASE_NS + 0x00007E40UL) +#define RSSLIB_SYS_FLASH_NS_PFUNC_END (SYSTEM_FLASH_BASE_NS + 0x00007E6BUL) + +/************ RSSLIB function return constants ********************************/ +#define RSSLIB_ERROR 0xF5F5F5F5UL +#define RSSLIB_SUCCESS 0xEAEAEAEAUL + +/*!< RSSLIB pointer function structure address definition */ +#define RSSLIB_PFUNC_BASE RSSLIB_SYS_FLASH_NS_PFUNC_START +#define RSSLIB_PFUNC ((RSSLIB_pFunc_TypeDef *)RSSLIB_PFUNC_BASE) + +/*!< HDP Area constant definition */ +#define RSSLIB_HDP_AREA_Pos (0U) +#define RSSLIB_HDP_AREA_Msk (0x1UL << RSSLIB_HDP_AREA_Pos ) + +/** + * @brief Prototype of RSSLIB Close and exit HDP Function + * @detail This function close the requested hdp area passed in input + * parameter and jump to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param HdpArea notifies which hdp area to close, can be a combination of + * hdpa area 1 and hdp area 2 + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t ( *RSSLIB_S_CloseExitHDP_TypeDef)( uint32_t HdpArea, uint32_t VectorTableAddr ); + +/** + * @brief RSSLib non-secure callable function pointer structure + */ +typedef struct +{ + __IM uint32_t Reserved[8]; +}NSC_pFuncTypeDef; + +/** + * @brief RSSLib secure callable function pointer structure + */ +typedef struct +{ + __IM uint32_t Reserved2[2]; + __IM RSSLIB_S_CloseExitHDP_TypeDef CloseExitHDP; /*!< RSSLIB Bootloader Close and exit HDP Address offset: 0x28 */ +}S_pFuncTypeDef; + +/** + * @brief RSSLib function pointer structure + */ +typedef struct +{ + NSC_pFuncTypeDef NSC; + S_pFuncTypeDef S; +}RSSLIB_pFunc_TypeDef; + + +/** @} */ /* End of group STM32WBAxx_Peripheral_peripheralAddr */ +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ +/** @addtogroup STM32WBAxx_Peripheral_declaration + * @{ + */ +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +#define ADC4_NS ((ADC_TypeDef *) ADC4_BASE_NS) +#define ADC4_COMMON_NS ((ADC_Common_TypeDef *) ADC4_COMMON_BASE_NS) +#define AES_NS ((AES_TypeDef *) AES_BASE_NS) +#define CRC_NS ((CRC_TypeDef *) CRC_BASE_NS) +#define EXTI_NS ((EXTI_TypeDef *) EXTI_BASE_NS) +#define FLASH_NS ((FLASH_TypeDef *) FLASH_R_BASE_NS) +#define GPDMA1_NS ((DMA_TypeDef *) GPDMA1_BASE_NS) +#define GPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_NS) +#define GPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_NS) +#define GPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_NS) +#define GPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_NS) +#define GPDMA1_Channel4_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_NS) +#define GPDMA1_Channel5_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_NS) +#define GPDMA1_Channel6_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_NS) +#define GPDMA1_Channel7_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_NS) +#define GPIOA_NS ((GPIO_TypeDef *) GPIOA_BASE_NS) +#define GPIOB_NS ((GPIO_TypeDef *) GPIOB_BASE_NS) +#define GPIOC_NS ((GPIO_TypeDef *) GPIOC_BASE_NS) +#define GPIOH_NS ((GPIO_TypeDef *) GPIOH_BASE_NS) +#define GTZC_MPCBB1_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_NS) +#define GTZC_MPCBB2_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_NS) +#define GTZC_MPCBB6_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB6_BASE_NS) +#define GTZC_TZSC_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC_BASE_NS) +#define HASH_NS ((HASH_TypeDef *) HASH_BASE_NS) +#define HASH_DIGEST_NS ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS) +#define HSEM_NS ((HSEM_TypeDef *) HSEM_BASE_NS) +#define HSEM_COMMON_NS ((HSEM_Common_TypeDef *) (HSEM_BASE_NS + 0x100U)) +#define I2C1_NS ((I2C_TypeDef *) I2C1_BASE_NS) +#define I2C3_NS ((I2C_TypeDef *) I2C3_BASE_NS) +#define ICACHE_NS ((ICACHE_TypeDef *) ICACHE_BASE_NS) +#define IWDG_NS ((IWDG_TypeDef *) IWDG_BASE_NS) +#define LPTIM1_NS ((LPTIM_TypeDef *) LPTIM1_BASE_NS) +#define LPTIM2_NS ((LPTIM_TypeDef *) LPTIM2_BASE_NS) +#define LPUART1_NS ((USART_TypeDef *) LPUART1_BASE_NS) +#define PKA_NS ((PKA_TypeDef *) PKA_BASE_NS) +#define PWR_NS ((PWR_TypeDef *) PWR_BASE_NS) +#define RAMCFG_SRAM1_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_NS) +#define RAMCFG_SRAM2_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_NS) +#define RAMCFG_SRAM6_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM6_BASE_NS) +#define RCC_NS ((RCC_TypeDef *) RCC_BASE_NS) +#define RNG_NS ((RNG_TypeDef *) RNG_BASE_NS) +#define RTC_NS ((RTC_TypeDef *) RTC_BASE_NS) +#define SAES_NS ((AES_TypeDef *) SAES_BASE_NS) +#define SPI1_NS ((SPI_TypeDef *) SPI1_BASE_NS) +#define SPI3_NS ((SPI_TypeDef *) SPI3_BASE_NS) +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_BASE_NS) +#define TAMP_NS ((TAMP_TypeDef *) TAMP_BASE_NS) +#define TIM1_NS ((TIM_TypeDef *) TIM1_BASE_NS) +#define TIM2_NS ((TIM_TypeDef *) TIM2_BASE_NS) +#define TIM3_NS ((TIM_TypeDef *) TIM3_BASE_NS) +#define TIM16_NS ((TIM_TypeDef *) TIM16_BASE_NS) +#define TIM17_NS ((TIM_TypeDef *) TIM17_BASE_NS) +#define TSC_NS ((TSC_TypeDef *) TSC_BASE_NS) +#define USART1_NS ((USART_TypeDef *) USART1_BASE_NS) +#define USART2_NS ((USART_TypeDef *) USART2_BASE_NS) +#define WWDG_NS ((WWDG_TypeDef *) WWDG_BASE_NS) + +/*!< Memory & Instance aliases and base addresses for Non-Secure/Secure peripherals */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define ADC4_S ((ADC_TypeDef *) ADC4_BASE_S) +#define ADC4_COMMON_S ((ADC_Common_TypeDef *) ADC4_COMMON_BASE_S) +#define AES_S ((AES_TypeDef *) AES_BASE_S) +#define CRC_S ((CRC_TypeDef *) CRC_BASE_S) +#define EXTI_S ((EXTI_TypeDef *) EXTI_BASE_S) +#define FLASH_S ((FLASH_TypeDef *) FLASH_R_BASE_S) +#define GPDMA1_S ((DMA_TypeDef *) GPDMA1_BASE_S) +#define GPDMA1_Channel0_S ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_S) +#define GPDMA1_Channel1_S ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_S) +#define GPDMA1_Channel2_S ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_S) +#define GPDMA1_Channel3_S ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_S) +#define GPDMA1_Channel4_S ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_S) +#define GPDMA1_Channel5_S ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_S) +#define GPDMA1_Channel6_S ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_S) +#define GPDMA1_Channel7_S ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_S) +#define GPIOA_S ((GPIO_TypeDef *) GPIOA_BASE_S) +#define GPIOB_S ((GPIO_TypeDef *) GPIOB_BASE_S) +#define GPIOC_S ((GPIO_TypeDef *) GPIOC_BASE_S) +#define GPIOH_S ((GPIO_TypeDef *) GPIOH_BASE_S) +#define GTZC_MPCBB1_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_S) +#define GTZC_MPCBB2_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_S) +#define GTZC_MPCBB6_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB6_BASE_S) +#define GTZC_TZIC_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC_BASE_S) +#define GTZC_TZSC_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC_BASE_S) +#define HASH_S ((HASH_TypeDef *) HASH_BASE_S) +#define HASH_DIGEST_S ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S) +#define HSEM_S ((HSEM_TypeDef *) HSEM_BASE_S) +#define HSEM_COMMON_S ((HSEM_Common_TypeDef *) (HSEM_BASE_S + 0x100U)) +#define I2C1_S ((I2C_TypeDef *) I2C1_BASE_S) +#define I2C3_S ((I2C_TypeDef *) I2C3_BASE_S) +#define ICACHE_S ((ICACHE_TypeDef *) ICACHE_BASE_S) +#define IWDG_S ((IWDG_TypeDef *) IWDG_BASE_S) +#define LPTIM1_S ((LPTIM_TypeDef *) LPTIM1_BASE_S) +#define LPTIM2_S ((LPTIM_TypeDef *) LPTIM2_BASE_S) +#define LPUART1_S ((USART_TypeDef *) LPUART1_BASE_S) +#define PKA_S ((PKA_TypeDef *) PKA_BASE_S) +#define PWR_S ((PWR_TypeDef *) PWR_BASE_S) +#define RAMCFG_SRAM1_S ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_S) +#define RAMCFG_SRAM2_S ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_S) +#define RAMCFG_SRAM6_S ((RAMCFG_TypeDef *) RAMCFG_SRAM6_BASE_S) +#define RCC_S ((RCC_TypeDef *) RCC_BASE_S) +#define RNG_S ((RNG_TypeDef *) RNG_BASE_S) +#define RTC_S ((RTC_TypeDef *) RTC_BASE_S) +#define SAES_S ((AES_TypeDef *) SAES_BASE_S) +#define SPI1_S ((SPI_TypeDef *) SPI1_BASE_S) +#define SPI3_S ((SPI_TypeDef *) SPI3_BASE_S) +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE_S) +#define TAMP_S ((TAMP_TypeDef *) TAMP_BASE_S) +#define TIM1_S ((TIM_TypeDef *) TIM1_BASE_S) +#define TIM2_S ((TIM_TypeDef *) TIM2_BASE_S) +#define TIM3_S ((TIM_TypeDef *) TIM3_BASE_S) +#define TIM16_S ((TIM_TypeDef *) TIM16_BASE_S) +#define TIM17_S ((TIM_TypeDef *) TIM17_BASE_S) +#define TSC_S ((TSC_TypeDef *) TSC_BASE_S) +#define USART1_S ((USART_TypeDef *) USART1_BASE_S) +#define USART2_S ((USART_TypeDef *) USART2_BASE_S) +#define WWDG_S ((WWDG_TypeDef *) WWDG_BASE_S) + + +/*!< Memory base addresses for Secure peripherals */ +#define FLASH_BASE FLASH_BASE_S +#define SRAM1_BASE SRAM1_BASE_S +#define SRAM2_BASE SRAM2_BASE_S +#define SRAM6_BASE SRAM6_BASE_S +#define SEQSRAM_BASE SEQSRAM_BASE_S + +/*!< Instance aliases and base addresses for Secure peripherals */ +#define ADC4 ADC4_S +#define ADC4_BASE ADC4_BASE_S +#define ADC4_COMMON ADC4_COMMON_S +#define ADC4_COMMON_BASE ADC4_COMMON_BASE_S +#define AES AES_S +#define AES_BASE AES_BASE_S +#define CRC CRC_S +#define CRC_BASE CRC_BASE_S +#define EXTI EXTI_S +#define EXTI_BASE EXTI_BASE_S +#define FLASH FLASH_S +#define FLASH_R_BASE FLASH_R_BASE_S +#define GPDMA1 GPDMA1_S +#define GPDMA1_BASE GPDMA1_BASE_S +#define GPDMA1_Channel0 GPDMA1_Channel0_S +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_S +#define GPDMA1_Channel1 GPDMA1_Channel1_S +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_S +#define GPDMA1_Channel2 GPDMA1_Channel2_S +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_S +#define GPDMA1_Channel3 GPDMA1_Channel3_S +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_S +#define GPDMA1_Channel4 GPDMA1_Channel4_S +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_S +#define GPDMA1_Channel5 GPDMA1_Channel5_S +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_S +#define GPDMA1_Channel6 GPDMA1_Channel6_S +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_S +#define GPDMA1_Channel7 GPDMA1_Channel7_S +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_S +#define GPIOA GPIOA_S +#define GPIOA_BASE GPIOA_BASE_S +#define GPIOB GPIOB_S +#define GPIOB_BASE GPIOB_BASE_S +#define GPIOC GPIOC_S +#define GPIOC_BASE GPIOC_BASE_S +#define GPIOH GPIOH_S +#define GPIOH_BASE GPIOH_BASE_S +#define GTZC_MPCBB1 GTZC_MPCBB1_S +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_S +#define GTZC_MPCBB2 GTZC_MPCBB2_S +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_S +#define GTZC_MPCBB6 GTZC_MPCBB6_S +#define GTZC_MPCBB6_BASE GTZC_MPCBB6_BASE_S +#define GTZC_TZIC GTZC_TZIC_S +#define GTZC_TZIC_BASE GTZC_TZIC_BASE_S +#define GTZC_TZSC GTZC_TZSC_S +#define GTZC_TZSC_BASE GTZC_TZSC_BASE_S +#define HASH HASH_S +#define HASH_BASE HASH_BASE_S +#define HASH_DIGEST HASH_DIGEST_S +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_S +#define HSEM HSEM_S +#define HSEM_BASE HSEM_BASE_S +#define HSEM_COMMON HSEM_COMMON_S +#define I2C1 I2C1_S +#define I2C1_BASE I2C1_BASE_S +#define I2C3 I2C3_S +#define I2C3_BASE I2C3_BASE_S +#define ICACHE ICACHE_S +#define ICACHE_BASE ICACHE_BASE_S +#define IWDG IWDG_S +#define IWDG_BASE IWDG_BASE_S +#define LPTIM1 LPTIM1_S +#define LPTIM1_BASE LPTIM1_BASE_S +#define LPTIM2 LPTIM2_S +#define LPTIM2_BASE LPTIM2_BASE_S +#define LPUART1 LPUART1_S +#define LPUART1_BASE LPUART1_BASE_S +#define PKA PKA_S +#define PKA_BASE PKA_BASE_S +#define PKA_RAM_BASE PKA_RAM_BASE_S +#define PWR PWR_S +#define PWR_BASE PWR_BASE_S +#define RADIO_BASE RADIO_BASE_S +#define RAMCFG_SRAM1 RAMCFG_SRAM1_S +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_S +#define RAMCFG_SRAM2 RAMCFG_SRAM2_S +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_S +#define RAMCFG_SRAM6 RAMCFG_SRAM6_S +#define RAMCFG_SRAM6_BASE RAMCFG_SRAM6_BASE_S +#define RCC RCC_S +#define RCC_BASE RCC_BASE_S +#define RNG RNG_S +#define RNG_BASE RNG_BASE_S +#define RTC RTC_S +#define RTC_BASE RTC_BASE_S +#define SAES SAES_S +#define SAES_BASE SAES_BASE_S +#define SPI1 SPI1_S +#define SPI1_BASE SPI1_BASE_S +#define SPI3 SPI3_S +#define SPI3_BASE SPI3_BASE_S +#define SYSCFG SYSCFG_S +#define SYSCFG_BASE SYSCFG_BASE_S +#define TAMP TAMP_S +#define TAMP_BASE TAMP_BASE_S +#define TIM1 TIM1_S +#define TIM1_BASE TIM1_BASE_S +#define TIM2 TIM2_S +#define TIM2_BASE TIM2_BASE_S +#define TIM3 TIM3_S +#define TIM3_BASE TIM3_BASE_S +#define TIM16 TIM16_S +#define TIM16_BASE TIM16_BASE_S +#define TIM17 TIM17_S +#define TIM17_BASE TIM17_BASE_S +#define TSC TSC_S +#define TSC_BASE TSC_BASE_S +#define USART1 USART1_S +#define USART1_BASE USART1_BASE_S +#define USART2 USART2_S +#define USART2_BASE USART2_BASE_S +#define WWDG WWDG_S +#define WWDG_BASE WWDG_BASE_S + +#else +/*!< Memory base addresses for Non secure peripherals */ +#define FLASH_BASE FLASH_BASE_NS +#define SRAM1_BASE SRAM1_BASE_NS +#define SRAM2_BASE SRAM2_BASE_NS +#define SRAM6_BASE SRAM6_BASE_NS +#define SEQSRAM_BASE SEQSRAM_BASE_NS + +/*!< Instance aliases and base addresses for Non secure peripherals */ +#define ADC4 ADC4_NS +#define ADC4_BASE ADC4_BASE_NS +#define ADC4_COMMON ADC4_COMMON_NS +#define ADC4_COMMON_BASE ADC4_COMMON_BASE_NS +#define AES AES_NS +#define AES_BASE AES_BASE_NS +#define CRC CRC_NS +#define CRC_BASE CRC_BASE_NS +#define EXTI EXTI_NS +#define EXTI_BASE EXTI_BASE_NS +#define FLASH FLASH_NS +#define FLASH_R_BASE FLASH_R_BASE_NS +#define GPDMA1 GPDMA1_NS +#define GPDMA1_BASE GPDMA1_BASE_NS +#define GPDMA1_Channel0 GPDMA1_Channel0_NS +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_NS +#define GPDMA1_Channel1 GPDMA1_Channel1_NS +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_NS +#define GPDMA1_Channel2 GPDMA1_Channel2_NS +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_NS +#define GPDMA1_Channel3 GPDMA1_Channel3_NS +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_NS +#define GPDMA1_Channel4 GPDMA1_Channel4_NS +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_NS +#define GPDMA1_Channel5 GPDMA1_Channel5_NS +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_NS +#define GPDMA1_Channel6 GPDMA1_Channel6_NS +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_NS +#define GPDMA1_Channel7 GPDMA1_Channel7_NS +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_NS +#define GPIOA GPIOA_NS +#define GPIOA_BASE GPIOA_BASE_NS +#define GPIOB GPIOB_NS +#define GPIOB_BASE GPIOB_BASE_NS +#define GPIOC GPIOC_NS +#define GPIOC_BASE GPIOC_BASE_NS +#define GPIOH GPIOH_NS +#define GPIOH_BASE GPIOH_BASE_NS +#define GTZC_MPCBB1 GTZC_MPCBB1_NS +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_NS +#define GTZC_MPCBB2 GTZC_MPCBB2_NS +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_NS +#define GTZC_MPCBB6 GTZC_MPCBB6_NS +#define GTZC_MPCBB6_BASE GTZC_MPCBB6_BASE_NS +#define GTZC_TZSC GTZC_TZSC_NS +#define GTZC_TZSC_BASE GTZC_TZSC_BASE_NS +#define HASH HASH_NS +#define HASH_BASE HASH_BASE_NS +#define HASH_DIGEST HASH_DIGEST_NS +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_NS +#define HSEM HSEM_NS +#define HSEM_BASE HSEM_BASE_NS +#define HSEM_COMMON HSEM_COMMON_NS +#define I2C1 I2C1_NS +#define I2C1_BASE I2C1_BASE_NS +#define I2C3 I2C3_NS +#define I2C3_BASE I2C3_BASE_NS +#define ICACHE ICACHE_NS +#define ICACHE_BASE ICACHE_BASE_NS +#define IWDG IWDG_NS +#define IWDG_BASE IWDG_BASE_NS +#define LPTIM1 LPTIM1_NS +#define LPTIM1_BASE LPTIM1_BASE_NS +#define LPTIM2 LPTIM2_NS +#define LPTIM2_BASE LPTIM2_BASE_NS +#define LPUART1 LPUART1_NS +#define LPUART1_BASE LPUART1_BASE_NS +#define PKA PKA_NS +#define PKA_BASE PKA_BASE_NS +#define PKA_RAM_BASE PKA_RAM_BASE_NS +#define PWR PWR_NS +#define PWR_BASE PWR_BASE_NS +#define RADIO_BASE RADIO_BASE_NS +#define RAMCFG_SRAM1 RAMCFG_SRAM1_NS +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_NS +#define RAMCFG_SRAM2 RAMCFG_SRAM2_NS +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_NS +#define RAMCFG_SRAM6 RAMCFG_SRAM6_NS +#define RAMCFG_SRAM6_BASE RAMCFG_SRAM6_BASE_NS +#define RCC RCC_NS +#define RCC_BASE RCC_BASE_NS +#define RNG RNG_NS +#define RNG_BASE RNG_BASE_NS +#define RTC RTC_NS +#define RTC_BASE RTC_BASE_NS +#define SAES SAES_NS +#define SAES_BASE SAES_BASE_NS +#define SPI1 SPI1_NS +#define SPI1_BASE SPI1_BASE_NS +#define SPI3 SPI3_NS +#define SPI3_BASE SPI3_BASE_NS +#define SYSCFG SYSCFG_NS +#define SYSCFG_BASE SYSCFG_BASE_NS +#define TAMP TAMP_NS +#define TAMP_BASE TAMP_BASE_NS +#define TIM1 TIM1_NS +#define TIM1_BASE TIM1_BASE_NS +#define TIM2 TIM2_NS +#define TIM2_BASE TIM2_BASE_NS +#define TIM3 TIM3_NS +#define TIM3_BASE TIM3_BASE_NS +#define TIM16 TIM16_NS +#define TIM16_BASE TIM16_BASE_NS +#define TIM17 TIM17_NS +#define TIM17_BASE TIM17_BASE_NS +#define TSC TSC_NS +#define TSC_BASE TSC_BASE_NS +#define USART1 USART1_NS +#define USART1_BASE USART1_BASE_NS +#define USART2 USART2_NS +#define USART2_BASE USART2_BASE_NS +#define WWDG WWDG_NS +#define WWDG_BASE WWDG_BASE_NS +#endif + + +/** @addtogroup Exported_constants + * @{ + */ + +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 16000U /*!< LSI Maximum startup time in us : 4 cycles @ 250 Hz = 16 ms */ +/** + * @} + */ + +/** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter (ADC) */ +/* */ +/******************************************************************************/ +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ +#define ADC_ISR_EOCAL_Pos (11U) +#define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */ +#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< ADC end of calibration flag */ +#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC internal voltage regulator ready flag */ + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ +#define ADC_IER_EOCALIE_Pos (11U) +#define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */ +#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< ADC end of calibration interrupt */ +#define ADC_IER_LDORDYIE_Pos (12U) +#define ADC_IER_LDORDYIE_Msk (0x1UL << ADC_IER_LDORDYIE_Pos) /*!< 0x00001000 */ +#define ADC_IER_LDORDYIE ADC_IER_LDORDYIE_Msk /*!< ADC Voltage Regulator Ready interrupt source */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR1 register *****************/ +#define ADC_CFGR1_DMAEN_Pos (0U) +#define ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC_CFGR1_DMACFG_Pos (1U) +#define ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC_CFGR1_RES_Pos (2U) +#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x0000000C */ +#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC Data resolution */ +#define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000004 */ +#define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ + +#define ADC_CFGR1_SCANDIR_Pos (4U) +#define ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000010 */ +#define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */ +#define ADC_CFGR1_ALIGN_Pos (5U) +#define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignment */ + +#define ADC_CFGR1_EXTSEL_Pos (6U) +#define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ +#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR1_EXTEN_Pos (10U) +#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR1_OVRMOD_Pos (12U) +#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR1_CONT_Pos (13U) +#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR1_WAIT_Pos (14U) +#define ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */ +#define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC low power auto wait */ +#define ADC_CFGR1_DISCEN_Pos (16U) +#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ +#define ADC_CFGR1_CHSELRMOD_Pos (21U) +#define ADC_CFGR1_CHSELRMOD_Msk (0x1UL << ADC_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */ +#define ADC_CFGR1_CHSELRMOD ADC_CFGR1_CHSELRMOD_Msk /*!< ADC group regular sequencer mode */ + +#define ADC_CFGR1_AWD1SGL_Pos (22U) +#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR1_AWD1EN_Pos (23U) +#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ + +#define ADC_CFGR1_AWD1CH_Pos (26U) +#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_OVSE_Pos (0U) +#define ADC_CFGR2_OVSE_Msk (0x1UL << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ + +#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TOVS_Pos (9U) +#define ADC_CFGR2_TOVS_Msk (0x1UL << ADC_CFGR2_TOVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ + +#define ADC_CFGR2_LFTRIG_Pos (29U) +#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC low frequency trigger mode */ + +/******************** Bit definition for ADC_SMPR register ******************/ +#define ADC_SMPR_SMP1_Pos (0U) +#define ADC_SMPR_SMP1_Msk (0x7UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000007 */ +#define ADC_SMPR_SMP1 ADC_SMPR_SMP1_Msk /*!< ADC group of channels sampling time 1 */ +#define ADC_SMPR_SMP1_0 (0x1UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000001 */ +#define ADC_SMPR_SMP1_1 (0x2UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000002 */ +#define ADC_SMPR_SMP1_2 (0x4UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR_SMP2_Pos (4U) +#define ADC_SMPR_SMP2_Msk (0x7UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000070 */ +#define ADC_SMPR_SMP2 ADC_SMPR_SMP2_Msk /*!< ADC group of channels sampling time 2 */ +#define ADC_SMPR_SMP2_0 (0x1UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000010 */ +#define ADC_SMPR_SMP2_1 (0x2UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000020 */ +#define ADC_SMPR_SMP2_2 (0x4UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000040 */ + +#define ADC_SMPR_SMPSEL_Pos (8U) +#define ADC_SMPR_SMPSEL_Msk (0x3FFFFUL << ADC_SMPR_SMPSEL_Pos) /*!< 0x03FFFF00 */ +#define ADC_SMPR_SMPSEL ADC_SMPR_SMPSEL_Msk /*!< ADC all channels sampling time selection */ +#define ADC_SMPR_SMPSEL0_Pos (8U) +#define ADC_SMPR_SMPSEL0_Msk (0x1UL << ADC_SMPR_SMPSEL0_Pos) /*!< 0x00000100 */ +#define ADC_SMPR_SMPSEL0 ADC_SMPR_SMPSEL0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR_SMPSEL1_Pos (9U) +#define ADC_SMPR_SMPSEL1_Msk (0x1UL << ADC_SMPR_SMPSEL1_Pos) /*!< 0x00000200 */ +#define ADC_SMPR_SMPSEL1 ADC_SMPR_SMPSEL1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR_SMPSEL2_Pos (10U) +#define ADC_SMPR_SMPSEL2_Msk (0x1UL << ADC_SMPR_SMPSEL2_Pos) /*!< 0x00000400 */ +#define ADC_SMPR_SMPSEL2 ADC_SMPR_SMPSEL2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR_SMPSEL3_Pos (11U) +#define ADC_SMPR_SMPSEL3_Msk (0x1UL << ADC_SMPR_SMPSEL3_Pos) /*!< 0x00000800 */ +#define ADC_SMPR_SMPSEL3 ADC_SMPR_SMPSEL3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR_SMPSEL4_Pos (12U) +#define ADC_SMPR_SMPSEL4_Msk (0x1UL << ADC_SMPR_SMPSEL4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR_SMPSEL4 ADC_SMPR_SMPSEL4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR_SMPSEL5_Pos (13U) +#define ADC_SMPR_SMPSEL5_Msk (0x1UL << ADC_SMPR_SMPSEL5_Pos) /*!< 0x00002000 */ +#define ADC_SMPR_SMPSEL5 ADC_SMPR_SMPSEL5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR_SMPSEL6_Pos (14U) +#define ADC_SMPR_SMPSEL6_Msk (0x1UL << ADC_SMPR_SMPSEL6_Pos) /*!< 0x00004000 */ +#define ADC_SMPR_SMPSEL6 ADC_SMPR_SMPSEL6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR_SMPSEL7_Pos (15U) +#define ADC_SMPR_SMPSEL7_Msk (0x1UL << ADC_SMPR_SMPSEL7_Pos) /*!< 0x00008000 */ +#define ADC_SMPR_SMPSEL7 ADC_SMPR_SMPSEL7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR_SMPSEL8_Pos (16U) +#define ADC_SMPR_SMPSEL8_Msk (0x1UL << ADC_SMPR_SMPSEL8_Pos) /*!< 0x00010000 */ +#define ADC_SMPR_SMPSEL8 ADC_SMPR_SMPSEL8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR_SMPSEL9_Pos (17U) +#define ADC_SMPR_SMPSEL9_Msk (0x1UL << ADC_SMPR_SMPSEL9_Pos) /*!< 0x00020000 */ +#define ADC_SMPR_SMPSEL9 ADC_SMPR_SMPSEL9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR_SMPSEL10_Pos (18U) +#define ADC_SMPR_SMPSEL10_Msk (0x1UL << ADC_SMPR_SMPSEL10_Pos) /*!< 0x00040000 */ +#define ADC_SMPR_SMPSEL10 ADC_SMPR_SMPSEL10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR_SMPSEL11_Pos (19U) +#define ADC_SMPR_SMPSEL11_Msk (0x1UL << ADC_SMPR_SMPSEL11_Pos) /*!< 0x00080000 */ +#define ADC_SMPR_SMPSEL11 ADC_SMPR_SMPSEL11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR_SMPSEL12_Pos (20U) +#define ADC_SMPR_SMPSEL12_Msk (0x1UL << ADC_SMPR_SMPSEL12_Pos) /*!< 0x00100000 */ +#define ADC_SMPR_SMPSEL12 ADC_SMPR_SMPSEL12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR_SMPSEL13_Pos (21U) +#define ADC_SMPR_SMPSEL13_Msk (0x1UL << ADC_SMPR_SMPSEL13_Pos) /*!< 0x00200000 */ +#define ADC_SMPR_SMPSEL13 ADC_SMPR_SMPSEL13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR_SMPSEL14_Pos (22U) +#define ADC_SMPR_SMPSEL14_Msk (0x1UL << ADC_SMPR_SMPSEL14_Pos) /*!< 0x00400000 */ +#define ADC_SMPR_SMPSEL14 ADC_SMPR_SMPSEL14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR_SMPSEL15_Pos (23U) +#define ADC_SMPR_SMPSEL15_Msk (0x1UL << ADC_SMPR_SMPSEL15_Pos) /*!< 0x00800000 */ +#define ADC_SMPR_SMPSEL15 ADC_SMPR_SMPSEL15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR_SMPSEL16_Pos (24U) +#define ADC_SMPR_SMPSEL16_Msk (0x1UL << ADC_SMPR_SMPSEL16_Pos) /*!< 0x01000000 */ +#define ADC_SMPR_SMPSEL16 ADC_SMPR_SMPSEL16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR_SMPSEL17_Pos (25U) +#define ADC_SMPR_SMPSEL17_Msk (0x1UL << ADC_SMPR_SMPSEL17_Pos) /*!< 0x02000000 */ +#define ADC_SMPR_SMPSEL17 ADC_SMPR_SMPSEL17_Msk /*!< ADC channel 17 sampling time selection */ + +/******************** Bit definition for ADC_AWD1TR register *******************/ +#define ADC_AWD1TR_LT1_Pos (0U) +#define ADC_AWD1TR_LT1_Msk (0xFFFUL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_AWD1TR_LT1 ADC_AWD1TR_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ +#define ADC_AWD1TR_LT1_0 (0x001UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000001 */ +#define ADC_AWD1TR_LT1_1 (0x002UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000002 */ +#define ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000004 */ +#define ADC_AWD1TR_LT1_3 (0x008UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000008 */ +#define ADC_AWD1TR_LT1_4 (0x010UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000010 */ +#define ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000020 */ +#define ADC_AWD1TR_LT1_6 (0x040UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000040 */ +#define ADC_AWD1TR_LT1_7 (0x080UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000080 */ +#define ADC_AWD1TR_LT1_8 (0x100UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000100 */ +#define ADC_AWD1TR_LT1_9 (0x200UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000200 */ +#define ADC_AWD1TR_LT1_10 (0x400UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000400 */ +#define ADC_AWD1TR_LT1_11 (0x800UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000800 */ + +#define ADC_AWD1TR_HT1_Pos (16U) +#define ADC_AWD1TR_HT1_Msk (0xFFFUL << ADC_AWD1TR_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD1TR_HT1 ADC_AWD1TR_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ +#define ADC_AWD1TR_HT1_0 (0x001UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00010000 */ +#define ADC_AWD1TR_HT1_1 (0x002UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00020000 */ +#define ADC_AWD1TR_HT1_2 (0x004UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00040000 */ +#define ADC_AWD1TR_HT1_3 (0x008UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00080000 */ +#define ADC_AWD1TR_HT1_4 (0x010UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00100000 */ +#define ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00200000 */ +#define ADC_AWD1TR_HT1_6 (0x040UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00400000 */ +#define ADC_AWD1TR_HT1_7 (0x080UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00800000 */ +#define ADC_AWD1TR_HT1_8 (0x100UL << ADC_AWD1TR_HT1_Pos) /*!< 0x01000000 */ +#define ADC_AWD1TR_HT1_9 (0x200UL << ADC_AWD1TR_HT1_Pos) /*!< 0x02000000 */ +#define ADC_AWD1TR_HT1_10 (0x400UL << ADC_AWD1TR_HT1_Pos) /*!< 0x04000000 */ +#define ADC_AWD1TR_HT1_11 (0x800UL << ADC_AWD1TR_HT1_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_AWDTR2 register *******************/ +#define ADC_AWD2TR_LT2_Pos (0U) +#define ADC_AWD2TR_LT2_Msk (0xFFFUL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000FFF */ +#define ADC_AWD2TR_LT2 ADC_AWD2TR_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ +#define ADC_AWD2TR_LT2_0 (0x001UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000001 */ +#define ADC_AWD2TR_LT2_1 (0x002UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000002 */ +#define ADC_AWD2TR_LT2_2 (0x004UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000004 */ +#define ADC_AWD2TR_LT2_3 (0x008UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000008 */ +#define ADC_AWD2TR_LT2_4 (0x010UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000010 */ +#define ADC_AWD2TR_LT2_5 (0x020UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000020 */ +#define ADC_AWD2TR_LT2_6 (0x040UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000040 */ +#define ADC_AWD2TR_LT2_7 (0x080UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000080 */ +#define ADC_AWD2TR_LT2_8 (0x100UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000100 */ +#define ADC_AWD2TR_LT2_9 (0x200UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000200 */ +#define ADC_AWD2TR_LT2_10 (0x400UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000400 */ +#define ADC_AWD2TR_LT2_11 (0x800UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000800 */ + +#define ADC_AWD2TR_HT2_Pos (16U) +#define ADC_AWD2TR_HT2_Msk (0xFFFUL << ADC_AWD2TR_HT2_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD2TR_HT2 ADC_AWD2TR_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ +#define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ +#define ADC_AWD2TR_HT2_1 (0x002UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00020000 */ +#define ADC_AWD2TR_HT2_2 (0x004UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00040000 */ +#define ADC_AWD2TR_HT2_3 (0x008UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00080000 */ +#define ADC_AWD2TR_HT2_4 (0x010UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00100000 */ +#define ADC_AWD2TR_HT2_5 (0x020UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00200000 */ +#define ADC_AWD2TR_HT2_6 (0x040UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00400000 */ +#define ADC_AWD2TR_HT2_7 (0x080UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00800000 */ +#define ADC_AWD2TR_HT2_8 (0x100UL << ADC_AWD2TR_HT2_Pos) /*!< 0x01000000 */ +#define ADC_AWD2TR_HT2_9 (0x200UL << ADC_AWD2TR_HT2_Pos) /*!< 0x02000000 */ +#define ADC_AWD2TR_HT2_10 (0x400UL << ADC_AWD2TR_HT2_Pos) /*!< 0x04000000 */ +#define ADC_AWD2TR_HT2_11 (0x800UL << ADC_AWD2TR_HT2_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_CHSELR register ****************/ +#define ADC_CHSELR_CHSEL_Pos (0U) +#define ADC_CHSELR_CHSEL_Msk (0x3FFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0003FFFF */ +#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL17_Pos (17U) +#define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL16_Pos (16U) +#define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL15_Pos (15U) +#define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ +#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL14_Pos (14U) +#define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL13_Pos (13U) +#define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL12_Pos (12U) +#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL11_Pos (11U) +#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ +#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL10_Pos (10U) +#define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL9_Pos (9U) +#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL8_Pos (8U) +#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL7_Pos (7U) +#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ +#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL6_Pos (6U) +#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL5_Pos (5U) +#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL4_Pos (4U) +#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL3_Pos (3U) +#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ +#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL2_Pos (2U) +#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL1_Pos (1U) +#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL0_Pos (0U) +#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */ + +#define ADC_CHSELR_SQ_ALL_Pos (0U) +#define ADC_CHSELR_SQ_ALL_Msk (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CHSELR_SQ_ALL ADC_CHSELR_SQ_ALL_Msk /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */ + +#define ADC_CHSELR_SQ8_Pos (28U) +#define ADC_CHSELR_SQ8_Msk (0xFUL << ADC_CHSELR_SQ8_Pos) /*!< 0xF0000000 */ +#define ADC_CHSELR_SQ8 ADC_CHSELR_SQ8_Msk /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ8_0 (0x1UL << ADC_CHSELR_SQ8_Pos) /*!< 0x10000000 */ +#define ADC_CHSELR_SQ8_1 (0x2UL << ADC_CHSELR_SQ8_Pos) /*!< 0x20000000 */ +#define ADC_CHSELR_SQ8_2 (0x4UL << ADC_CHSELR_SQ8_Pos) /*!< 0x40000000 */ +#define ADC_CHSELR_SQ8_3 (0x8UL << ADC_CHSELR_SQ8_Pos) /*!< 0x80000000 */ + +#define ADC_CHSELR_SQ7_Pos (24U) +#define ADC_CHSELR_SQ7_Msk (0xFUL << ADC_CHSELR_SQ7_Pos) /*!< 0x0F000000 */ +#define ADC_CHSELR_SQ7 ADC_CHSELR_SQ7_Msk /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ7_0 (0x1UL << ADC_CHSELR_SQ7_Pos) /*!< 0x01000000 */ +#define ADC_CHSELR_SQ7_1 (0x2UL << ADC_CHSELR_SQ7_Pos) /*!< 0x02000000 */ +#define ADC_CHSELR_SQ7_2 (0x4UL << ADC_CHSELR_SQ7_Pos) /*!< 0x04000000 */ +#define ADC_CHSELR_SQ7_3 (0x8UL << ADC_CHSELR_SQ7_Pos) /*!< 0x08000000 */ + +#define ADC_CHSELR_SQ6_Pos (20U) +#define ADC_CHSELR_SQ6_Msk (0xFUL << ADC_CHSELR_SQ6_Pos) /*!< 0x00F00000 */ +#define ADC_CHSELR_SQ6 ADC_CHSELR_SQ6_Msk /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ6_0 (0x1UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00100000 */ +#define ADC_CHSELR_SQ6_1 (0x2UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00200000 */ +#define ADC_CHSELR_SQ6_2 (0x4UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00400000 */ +#define ADC_CHSELR_SQ6_3 (0x8UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00800000 */ + +#define ADC_CHSELR_SQ5_Pos (16U) +#define ADC_CHSELR_SQ5_Msk (0xFUL << ADC_CHSELR_SQ5_Pos) /*!< 0x000F0000 */ +#define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ5_0 (0x1UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_SQ5_1 (0x2UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_SQ5_2 (0x4UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_SQ5_3 (0x8UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00080000 */ + +#define ADC_CHSELR_SQ4_Pos (12U) +#define ADC_CHSELR_SQ4_Msk (0xFUL << ADC_CHSELR_SQ4_Pos) /*!< 0x0000F000 */ +#define ADC_CHSELR_SQ4 ADC_CHSELR_SQ4_Msk /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ4_0 (0x1UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_SQ4_1 (0x2UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_SQ4_2 (0x4UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_SQ4_3 (0x8UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00008000 */ + +#define ADC_CHSELR_SQ3_Pos (8U) +#define ADC_CHSELR_SQ3_Msk (0xFUL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000F00 */ +#define ADC_CHSELR_SQ3 ADC_CHSELR_SQ3_Msk /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ3_0 (0x1UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_SQ3_1 (0x2UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_SQ3_2 (0x4UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_SQ3_3 (0x8UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000800 */ + +#define ADC_CHSELR_SQ2_Pos (4U) +#define ADC_CHSELR_SQ2_Msk (0xFUL << ADC_CHSELR_SQ2_Pos) /*!< 0x000000F0 */ +#define ADC_CHSELR_SQ2 ADC_CHSELR_SQ2_Msk /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ2_0 (0x1UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_SQ2_1 (0x2UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_SQ2_2 (0x4UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_SQ2_3 (0x8UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000080 */ + +#define ADC_CHSELR_SQ1_Pos (0U) +#define ADC_CHSELR_SQ1_Msk (0xFUL << ADC_CHSELR_SQ1_Pos) /*!< 0x0000000F */ +#define ADC_CHSELR_SQ1 ADC_CHSELR_SQ1_Msk /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ1_0 (0x1UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_SQ1_1 (0x2UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_SQ1_2 (0x4UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_SQ1_3 (0x8UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000008 */ + +/******************** Bit definition for ADC_AWD3TR register *******************/ +#define ADC_AWD3TR_LT3_Pos (0U) +#define ADC_AWD3TR_LT3_Msk (0xFFFUL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000FFF */ +#define ADC_AWD3TR_LT3 ADC_AWD3TR_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ +#define ADC_AWD3TR_LT3_0 (0x001UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000001 */ +#define ADC_AWD3TR_LT3_1 (0x002UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000002 */ +#define ADC_AWD3TR_LT3_2 (0x004UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000004 */ +#define ADC_AWD3TR_LT3_3 (0x008UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000008 */ +#define ADC_AWD3TR_LT3_4 (0x010UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000010 */ +#define ADC_AWD3TR_LT3_5 (0x020UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000020 */ +#define ADC_AWD3TR_LT3_6 (0x040UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000040 */ +#define ADC_AWD3TR_LT3_7 (0x080UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000080 */ +#define ADC_AWD3TR_LT3_8 (0x100UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000100 */ +#define ADC_AWD3TR_LT3_9 (0x200UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000200 */ +#define ADC_AWD3TR_LT3_10 (0x400UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000400 */ +#define ADC_AWD3TR_LT3_11 (0x800UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000800 */ + +#define ADC_AWD3TR_HT3_Pos (16U) +#define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD3TR_HT3 ADC_AWD3TR_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ +#define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */ +#define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */ +#define ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00040000 */ +#define ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00080000 */ +#define ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00100000 */ +#define ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00200000 */ +#define ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00400000 */ +#define ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00800000 */ +#define ADC_AWD3TR_HT3_8 (0x100UL << ADC_AWD3TR_HT3_Pos) /*!< 0x01000000 */ +#define ADC_AWD3TR_HT3_9 (0x200UL << ADC_AWD3TR_HT3_Pos) /*!< 0x02000000 */ +#define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) /*!< 0x04000000 */ +#define ADC_AWD3TR_HT3_11 (0x800UL << ADC_AWD3TR_HT3_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_DATA_Pos (0U) +#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */ + +/******************** Bit definition for ADC_PWRR register ******************/ +#define ADC_PWRR_AUTOFF_Pos (0U) +#define ADC_PWRR_AUTOFF_Msk (0x1UL << ADC_PWRR_AUTOFF_Pos) /*!< 0x00000001 */ +#define ADC_PWRR_AUTOFF ADC_PWRR_AUTOFF_Msk /*!< ADC auto-off mode */ +#define ADC_PWRR_DPD_Pos (1U) +#define ADC_PWRR_DPD_Msk (0x1UL << ADC_PWRR_DPD_Pos) /*!< 0x00000002 */ +#define ADC_PWRR_DPD ADC_PWRR_DPD_Msk /*!< ADC deep power down mode */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0x3FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0003FFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0x3FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0003FFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_Pos (0U) +#define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_0 (0x01UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_1 (0x02UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_2 (0x04UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_3 (0x08UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_4 (0x10UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_5 (0x20UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_6 (0x40UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000040 */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ + + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + + +/******************************************************************************/ +/* */ +/* Advanced Encryption Standard (AES) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for AES_CR register *********************/ +#define AES_CR_EN_Pos (0U) +#define AES_CR_EN_Msk (0x1UL << AES_CR_EN_Pos) /*!< 0x00000001 */ +#define AES_CR_EN AES_CR_EN_Msk /*!< AES Enable */ +#define AES_CR_DATATYPE_Pos (1U) +#define AES_CR_DATATYPE_Msk (0x3UL << AES_CR_DATATYPE_Pos) /*!< 0x00000006 */ +#define AES_CR_DATATYPE AES_CR_DATATYPE_Msk /*!< Data type selection */ +#define AES_CR_DATATYPE_0 (0x1UL << AES_CR_DATATYPE_Pos) /*!< 0x00000002 */ +#define AES_CR_DATATYPE_1 (0x2UL << AES_CR_DATATYPE_Pos) /*!< 0x00000004 */ +#define AES_CR_MODE_Pos (3U) +#define AES_CR_MODE_Msk (0x3UL << AES_CR_MODE_Pos) /*!< 0x00000018 */ +#define AES_CR_MODE AES_CR_MODE_Msk /*!< AES Mode Of Operation */ +#define AES_CR_MODE_0 (0x1UL << AES_CR_MODE_Pos) /*!< 0x00000008 */ +#define AES_CR_MODE_1 (0x2UL << AES_CR_MODE_Pos) /*!< 0x00000010 */ +#define AES_CR_CHMOD_Pos (5U) +#define AES_CR_CHMOD_Msk (0x803UL << AES_CR_CHMOD_Pos) /*!< 0x00010060 */ +#define AES_CR_CHMOD AES_CR_CHMOD_Msk /*!< AES Chaining Mode */ +#define AES_CR_CHMOD_0 (0x001UL << AES_CR_CHMOD_Pos) /*!< 0x00000020 */ +#define AES_CR_CHMOD_1 (0x002UL << AES_CR_CHMOD_Pos) /*!< 0x00000040 */ +#define AES_CR_CHMOD_2 (0x800UL << AES_CR_CHMOD_Pos) /*!< 0x00010000 */ +#define AES_CR_DMAINEN_Pos (11U) +#define AES_CR_DMAINEN_Msk (0x1UL << AES_CR_DMAINEN_Pos) /*!< 0x00000800 */ +#define AES_CR_DMAINEN AES_CR_DMAINEN_Msk /*!< Enable data input phase DMA management */ +#define AES_CR_DMAOUTEN_Pos (12U) +#define AES_CR_DMAOUTEN_Msk (0x1UL << AES_CR_DMAOUTEN_Pos) /*!< 0x00001000 */ +#define AES_CR_DMAOUTEN AES_CR_DMAOUTEN_Msk /*!< Enable data output phase DMA management */ +#define AES_CR_GCMPH_Pos (13U) +#define AES_CR_GCMPH_Msk (0x3UL << AES_CR_GCMPH_Pos) /*!< 0x00006000 */ +#define AES_CR_GCMPH AES_CR_GCMPH_Msk /*!< GCM Phase */ +#define AES_CR_GCMPH_0 (0x1UL << AES_CR_GCMPH_Pos) /*!< 0x00002000 */ +#define AES_CR_GCMPH_1 (0x2UL << AES_CR_GCMPH_Pos) /*!< 0x00004000 */ +#define AES_CR_KEYSIZE_Pos (18U) +#define AES_CR_KEYSIZE_Msk (0x1UL << AES_CR_KEYSIZE_Pos) /*!< 0x00040000 */ +#define AES_CR_KEYSIZE AES_CR_KEYSIZE_Msk /*!< Key size selection */ +#define AES_CR_KEYPROT_Pos (19U) +#define AES_CR_KEYPROT_Msk (0x1UL << AES_CR_KEYPROT_Pos) /*!< 0x00080000 */ +#define AES_CR_KEYPROT AES_CR_KEYPROT_Msk /*!< Key protection */ +#define AES_CR_NPBLB_Pos (20U) +#define AES_CR_NPBLB_Msk (0xFUL << AES_CR_NPBLB_Pos) /*!< 0x00F00000 */ +#define AES_CR_NPBLB AES_CR_NPBLB_Msk /*!< Number of padding bytes in payload last block */ +#define AES_CR_NPBLB_0 (0x1UL << AES_CR_NPBLB_Pos) /*!< 0x00100000 */ +#define AES_CR_NPBLB_1 (0x2UL << AES_CR_NPBLB_Pos) /*!< 0x00200000 */ +#define AES_CR_NPBLB_2 (0x4UL << AES_CR_NPBLB_Pos) /*!< 0x00400000 */ +#define AES_CR_NPBLB_3 (0x8UL << AES_CR_NPBLB_Pos) /*!< 0x00800000 */ +#define AES_CR_KMOD_Pos (24U) +#define AES_CR_KMOD_Msk (0x3UL << AES_CR_KMOD_Pos) /*!< 0x03000000 */ +#define AES_CR_KMOD AES_CR_KMOD_Msk /*!< Key mode selection */ +#define AES_CR_KMOD_0 (0x1UL << AES_CR_KMOD_Pos) /*!< 0x01000000 */ +#define AES_CR_KMOD_1 (0x2UL << AES_CR_KMOD_Pos) /*!< 0x02000000 */ +#define AES_CR_KSHAREID_Pos (26U) +#define AES_CR_KSHAREID_Msk (0x3UL << AES_CR_KSHAREID_Pos) /*!< 0x0C000000 */ +#define AES_CR_KSHAREID AES_CR_KSHAREID_Msk /*!< Key Shared ID */ +#define AES_CR_KEYSEL_Pos (28U) +#define AES_CR_KEYSEL_Msk (0x7UL << AES_CR_KEYSEL_Pos) /*!< 0x70000000 */ +#define AES_CR_KEYSEL AES_CR_KEYSEL_Msk /*!< Key Selection */ +#define AES_CR_KEYSEL_0 (0x1UL << AES_CR_KEYSEL_Pos) /*!< 0x10000000 */ +#define AES_CR_KEYSEL_1 (0x2UL << AES_CR_KEYSEL_Pos) /*!< 0x20000000 */ +#define AES_CR_KEYSEL_2 (0x4UL << AES_CR_KEYSEL_Pos) /*!< 0x40000000 */ +#define AES_CR_IPRST_Pos (31U) +#define AES_CR_IPRST_Msk (0x1UL << AES_CR_IPRST_Pos) /*!< 0x80000000 */ +#define AES_CR_IPRST AES_CR_IPRST_Msk /*!< AES IP software reset */ + + +/******************* Bit definition for AES_SR register *********************/ +#define AES_SR_CCF_Pos (0U) +#define AES_SR_CCF_Msk (0x1UL << AES_SR_CCF_Pos) /*!< 0x00000001 */ +#define AES_SR_CCF AES_SR_CCF_Msk /*!< Computation Complete Flag */ +#define AES_SR_RDERR_Pos (1U) +#define AES_SR_RDERR_Msk (0x1UL << AES_SR_RDERR_Pos) /*!< 0x00000002 */ +#define AES_SR_RDERR AES_SR_RDERR_Msk /*!< Read Error Flag */ +#define AES_SR_WRERR_Pos (2U) +#define AES_SR_WRERR_Msk (0x1UL << AES_SR_WRERR_Pos) /*!< 0x00000004 */ +#define AES_SR_WRERR AES_SR_WRERR_Msk /*!< Write Error Flag */ +#define AES_SR_BUSY_Pos (3U) +#define AES_SR_BUSY_Msk (0x1UL << AES_SR_BUSY_Pos) /*!< 0x00000008 */ +#define AES_SR_BUSY AES_SR_BUSY_Msk /*!< Busy Flag */ +#define AES_SR_KEYVALID_Pos (7U) +#define AES_SR_KEYVALID_Msk (0x1UL << AES_SR_KEYVALID_Pos) /*!< 0x00000080 */ +#define AES_SR_KEYVALID AES_SR_KEYVALID_Msk /*!< Key Valid Flag */ + +/******************* Bit definition for AES_DINR register *******************/ +#define AES_DINR_Pos (0U) +#define AES_DINR_Msk (0xFFFFFFFFUL << AES_DINR_Pos) /*!< 0xFFFFFFFF */ +#define AES_DINR AES_DINR_Msk /*!< AES Data Input Register */ + +/******************* Bit definition for AES_DOUTR register ******************/ +#define AES_DOUTR_Pos (0U) +#define AES_DOUTR_Msk (0xFFFFFFFFUL << AES_DOUTR_Pos) /*!< 0xFFFFFFFF */ +#define AES_DOUTR AES_DOUTR_Msk /*!< AES Data Output Register */ + +/******************* Bit definition for AES_KEYR0 register ******************/ +#define AES_KEYR0_Pos (0U) +#define AES_KEYR0_Msk (0xFFFFFFFFUL << AES_KEYR0_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR0 AES_KEYR0_Msk /*!< AES Key Register 0 */ + +/******************* Bit definition for AES_KEYR1 register ******************/ +#define AES_KEYR1_Pos (0U) +#define AES_KEYR1_Msk (0xFFFFFFFFUL << AES_KEYR1_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR1 AES_KEYR1_Msk /*!< AES Key Register 1 */ + +/******************* Bit definition for AES_KEYR2 register ******************/ +#define AES_KEYR2_Pos (0U) +#define AES_KEYR2_Msk (0xFFFFFFFFUL << AES_KEYR2_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR2 AES_KEYR2_Msk /*!< AES Key Register 2 */ + +/******************* Bit definition for AES_KEYR3 register ******************/ +#define AES_KEYR3_Pos (0U) +#define AES_KEYR3_Msk (0xFFFFFFFFUL << AES_KEYR3_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR3 AES_KEYR3_Msk /*!< AES Key Register 3 */ + +/******************* Bit definition for AES_KEYR4 register ******************/ +#define AES_KEYR4_Pos (0U) +#define AES_KEYR4_Msk (0xFFFFFFFFUL << AES_KEYR4_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR4 AES_KEYR4_Msk /*!< AES Key Register 4 */ + +/******************* Bit definition for AES_KEYR5 register ******************/ +#define AES_KEYR5_Pos (0U) +#define AES_KEYR5_Msk (0xFFFFFFFFUL << AES_KEYR5_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR5 AES_KEYR5_Msk /*!< AES Key Register 5 */ + +/******************* Bit definition for AES_KEYR6 register ******************/ +#define AES_KEYR6_Pos (0U) +#define AES_KEYR6_Msk (0xFFFFFFFFUL << AES_KEYR6_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR6 AES_KEYR6_Msk /*!< AES Key Register 6 */ + +/******************* Bit definition for AES_KEYR7 register ******************/ +#define AES_KEYR7_Pos (0U) +#define AES_KEYR7_Msk (0xFFFFFFFFUL << AES_KEYR7_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR7 AES_KEYR7_Msk /*!< AES Key Register 7 */ + +/******************* Bit definition for AES_IVR0 register ******************/ +#define AES_IVR0_Pos (0U) +#define AES_IVR0_Msk (0xFFFFFFFFUL << AES_IVR0_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR0 AES_IVR0_Msk /*!< AES Initialization Vector Register 0 */ + +/******************* Bit definition for AES_IVR1 register ******************/ +#define AES_IVR1_Pos (0U) +#define AES_IVR1_Msk (0xFFFFFFFFUL << AES_IVR1_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR1 AES_IVR1_Msk /*!< AES Initialization Vector Register 1 */ + +/******************* Bit definition for AES_IVR2 register ******************/ +#define AES_IVR2_Pos (0U) +#define AES_IVR2_Msk (0xFFFFFFFFUL << AES_IVR2_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR2 AES_IVR2_Msk /*!< AES Initialization Vector Register 2 */ + +/******************* Bit definition for AES_IVR3 register ******************/ +#define AES_IVR3_Pos (0U) +#define AES_IVR3_Msk (0xFFFFFFFFUL << AES_IVR3_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR3 AES_IVR3_Msk /*!< AES Initialization Vector Register 3 */ + +/******************* Bit definition for AES_SUSP0R register ******************/ +#define AES_SUSP0R_Pos (0U) +#define AES_SUSP0R_Msk (0xFFFFFFFFUL << AES_SUSP0R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP0R AES_SUSP0R_Msk /*!< AES Suspend registers 0 */ + +/******************* Bit definition for AES_SUSP1R register ******************/ +#define AES_SUSP1R_Pos (0U) +#define AES_SUSP1R_Msk (0xFFFFFFFFUL << AES_SUSP1R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP1R AES_SUSP1R_Msk /*!< AES Suspend registers 1 */ + +/******************* Bit definition for AES_SUSP2R register ******************/ +#define AES_SUSP2R_Pos (0U) +#define AES_SUSP2R_Msk (0xFFFFFFFFUL << AES_SUSP2R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP2R AES_SUSP2R_Msk /*!< AES Suspend registers 2 */ + +/******************* Bit definition for AES_SUSP3R register ******************/ +#define AES_SUSP3R_Pos (0U) +#define AES_SUSP3R_Msk (0xFFFFFFFFUL << AES_SUSP3R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP3R AES_SUSP3R_Msk /*!< AES Suspend registers 3 */ + +/******************* Bit definition for AES_SUSP4R register ******************/ +#define AES_SUSP4R_Pos (0U) +#define AES_SUSP4R_Msk (0xFFFFFFFFUL << AES_SUSP4R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP4R AES_SUSP4R_Msk /*!< AES Suspend registers 4 */ + +/******************* Bit definition for AES_SUSP5R register ******************/ +#define AES_SUSP5R_Pos (0U) +#define AES_SUSP5R_Msk (0xFFFFFFFFUL << AES_SUSP5R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP5R AES_SUSP5R_Msk /*!< AES Suspend registers 5 */ + +/******************* Bit definition for AES_SUSP6R register ******************/ +#define AES_SUSP6R_Pos (0U) +#define AES_SUSP6R_Msk (0xFFFFFFFFUL << AES_SUSP6R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP6R AES_SUSP6R_Msk /*!< AES Suspend registers 6 */ + +/******************* Bit definition for AES_SUSP7R register ******************/ +#define AES_SUSP7R_Pos (0U) +#define AES_SUSP7R_Msk (0xFFFFFFFFUL << AES_SUSP7R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP7R AES_SUSP7R_Msk /*!< AES Suspend registers 7 */ + +/******************* Bit definition for AES_IER register ******************/ +#define AES_IER_CCFIE_Pos (0U) +#define AES_IER_CCFIE_Msk (0x1UL << AES_IER_CCFIE_Pos) /*!< 0x00000001 */ +#define AES_IER_CCFIE AES_IER_CCFIE_Msk /*!< Computation complete flag interrupt enable */ +#define AES_IER_RWEIE_Pos (1U) +#define AES_IER_RWEIE_Msk (0x1UL << AES_IER_RWEIE_Pos) /*!< 0x00000002 */ +#define AES_IER_RWEIE AES_IER_RWEIE_Msk /*!< Read or write error Interrupt Enable */ +#define AES_IER_KEIE_Pos (2U) +#define AES_IER_KEIE_Msk (0x1UL << AES_IER_KEIE_Pos) /*!< 0x00000004 */ +#define AES_IER_KEIE AES_IER_KEIE_Msk /*!< Key error interrupt enable */ +#define AES_IER_RNGEIE_Pos (3U) +#define AES_IER_RNGEIE_Msk (0x1UL << AES_IER_RNGEIE_Pos) /*!< 0x00000008 */ +#define AES_IER_RNGEIE AES_IER_RNGEIE_Msk /*!< SAES Rng error interrupt enable */ + +/******************* Bit definition for AES_ISR register ******************/ +#define AES_ISR_CCF_Pos (0U) +#define AES_ISR_CCF_Msk (0x1UL << AES_ISR_CCF_Pos) /*!< 0x00000001 */ +#define AES_ISR_CCF AES_ISR_CCF_Msk /*!< Computation complete flag */ +#define AES_ISR_RWEIF_Pos (1U) +#define AES_ISR_RWEIF_Msk (0x1UL << AES_ISR_RWEIF_Pos) /*!< 0x00000002 */ +#define AES_ISR_RWEIF AES_ISR_RWEIF_Msk /*!< Read or write error Interrupt flag */ +#define AES_ISR_KEIF_Pos (2U) +#define AES_ISR_KEIF_Msk (0x1UL << AES_ISR_KEIF_Pos) /*!< 0x00000004 */ +#define AES_ISR_KEIF AES_ISR_KEIF_Msk /*!< Key error interrupt flag */ +#define AES_ISR_RNGEIF_Pos (3U) +#define AES_ISR_RNGEIF_Msk (0x1UL << AES_ISR_RNGEIF_Pos) /*!< 0x00000008 */ +#define AES_ISR_RNGEIF AES_ISR_RNGEIF_Msk /*!< SAES Rng error interrupt flag */ + +/******************* Bit definition for AES_ICR register ******************/ +#define AES_ICR_CCF_Pos (0U) +#define AES_ICR_CCF_Msk (0x1UL << AES_ICR_CCF_Pos) /*!< 0x00000001 */ +#define AES_ICR_CCF AES_ICR_CCF_Msk /*!< Computation complete flag clear */ +#define AES_ICR_RWEIF_Pos (1U) +#define AES_ICR_RWEIF_Msk (0x1UL << AES_ICR_RWEIF_Pos) /*!< 0x00000002 */ +#define AES_ICR_RWEIF AES_ICR_RWEIF_Msk /*!< Read or write error Interrupt flag clear */ +#define AES_ICR_KEIF_Pos (2U) +#define AES_ICR_KEIF_Msk (0x1UL << AES_ICR_KEIF_Pos) /*!< 0x00000004 */ +#define AES_ICR_KEIF AES_ICR_KEIF_Msk /*!< Key error interrupt flag clear */ +#define AES_ICR_RNGEIF_Pos (3U) +#define AES_ICR_RNGEIF_Msk (0x1UL << AES_ICR_RNGEIF_Pos) /*!< 0x00000008 */ +#define AES_ICR_RNGEIF AES_ICR_RNGEIF_Msk /*!< SAES Rng error interrupt flag clear */ + +/******************************************************************************/ +/* */ +/* Debug MCU */ +/* */ +/******************************************************************************/ +/******************** Bit definition for DBGMCU_IDCODE register *************/ +#define DBGMCU_IDCODE_DEV_ID_Pos (0U) +#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ +#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk +#define DBGMCU_IDCODE_REV_ID_Pos (16U) +#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ +#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk + +/******************** Bit definition for DBGMCU_SCR register *****************/ +#define DBGMCU_SCR_DBG_STOP_Pos (1U) +#define DBGMCU_SCR_DBG_STOP_Msk (0x1UL << DBGMCU_SCR_DBG_STOP_Pos) /*!< 0x00000002 */ +#define DBGMCU_SCR_DBG_STOP DBGMCU_SCR_DBG_STOP_Msk +#define DBGMCU_SCR_DBG_STANDBY_Pos (2U) +#define DBGMCU_SCR_DBG_STANDBY_Msk (0x1UL << DBGMCU_SCR_DBG_STANDBY_Pos) /*!< 0x00000004 */ +#define DBGMCU_SCR_DBG_STANDBY DBGMCU_SCR_DBG_STANDBY_Msk +#define DBGMCU_SCR_DBG_LPMS_Pos (16U) +#define DBGMCU_SCR_DBG_LPMS_Msk (0x7UL << DBGMCU_SCR_DBG_LPMS_Pos) /*!< 0x00070000 */ +#define DBGMCU_SCR_DBG_LPMS DBGMCU_SCR_DBG_LPMS_Msk +#define DBGMCU_SCR_DBG_LPMS_0 (0x1UL << DBGMCU_SCR_DBG_LPMS_Pos) +#define DBGMCU_SCR_DBG_LPMS_1 (0x2UL << DBGMCU_SCR_DBG_LPMS_Pos) +#define DBGMCU_SCR_DBG_LPMS_2 (0x4UL << DBGMCU_SCR_DBG_LPMS_Pos) +#define DBGMCU_SCR_DBG_STOPF_Pos (19U) +#define DBGMCU_SCR_DBG_STOPF_Msk (0x1UL << DBGMCU_SCR_DBG_STOPF_Pos) /*!< 0x00080000 */ +#define DBGMCU_SCR_DBG_STOPF DBGMCU_SCR_DBG_STOPF_Msk +#define DBGMCU_SCR_DBG_SBF_Pos (20U) +#define DBGMCU_SCR_DBG_SBF_Msk (0x1UL << DBGMCU_SCR_DBG_SBF_Pos) /*!< 0x00100000 */ +#define DBGMCU_SCR_DBG_SBF DBGMCU_SCR_DBG_SBF_Msk +#define DBGMCU_SCR_DBG_CS_Pos (24U) +#define DBGMCU_SCR_DBG_CS_Msk (0x1UL << DBGMCU_SCR_DBG_CS_Pos) /*!< 0x01000000 */ +#define DBGMCU_SCR_DBG_CS DBGMCU_SCR_DBG_CS_Msk +#define DBGMCU_SCR_DBG_CDS_Pos (25U) +#define DBGMCU_SCR_DBG_CDS_Msk (0x1UL << DBGMCU_SCR_DBG_CDS_Pos) /*!< 0x02000000 */ +#define DBGMCU_SCR_DBG_CDS DBGMCU_SCR_DBG_CDS_Msk + +/******************** Bit definition for DBGMCU_APB1LFZR register ***********/ +#define DBGMCU_APB1LFZR_DBG_TIM2_STOP_Pos (0U) +#define DBGMCU_APB1LFZR_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_TIM2_STOP_Pos) +#define DBGMCU_APB1LFZR_DBG_TIM2_STOP DBGMCU_APB1LFZR_DBG_TIM2_STOP_Msk +#define DBGMCU_APB1LFZR_DBG_TIM3_STOP_Pos (1U) +#define DBGMCU_APB1LFZR_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_TIM3_STOP_Pos) +#define DBGMCU_APB1LFZR_DBG_TIM3_STOP DBGMCU_APB1LFZR_DBG_TIM3_STOP_Msk +#define DBGMCU_APB1LFZR_DBG_WWDG_STOP_Pos (11U) +#define DBGMCU_APB1LFZR_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_WWDG_STOP_Pos) +#define DBGMCU_APB1LFZR_DBG_WWDG_STOP DBGMCU_APB1LFZR_DBG_WWDG_STOP_Msk +#define DBGMCU_APB1LFZR_DBG_IWDG_STOP_Pos (12U) +#define DBGMCU_APB1LFZR_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_IWDG_STOP_Pos) +#define DBGMCU_APB1LFZR_DBG_IWDG_STOP DBGMCU_APB1LFZR_DBG_IWDG_STOP_Msk +#define DBGMCU_APB1LFZR_DBG_I2C1_STOP_Pos (21U) +#define DBGMCU_APB1LFZR_DBG_I2C1_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_I2C1_STOP_Pos) +#define DBGMCU_APB1LFZR_DBG_I2C1_STOP DBGMCU_APB1LFZR_DBG_I2C1_STOP_Msk + +/******************** Bit definition for DBGMCU_APB1HFZR register ***********/ +#define DBGMCU_APB1HFZR_DBG_LPTIM2_STOP_Pos (5U) +#define DBGMCU_APB1HFZR_DBG_LPTIM2_STOP_Msk (0x1UL << DBGMCU_APB1HFZR_DBG_LPTIM2_STOP_Pos) +#define DBGMCU_APB1HFZR_DBG_LPTIM2_STOP DBGMCU_APB1HFZR_DBG_LPTIM2_STOP_Msk + +/******************** Bit definition for DBGMCU_APB2FZR register ***********/ +#define DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos (11U) +#define DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos) +#define DBGMCU_APB2FZR_DBG_TIM1_STOP DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk +#define DBGMCU_APB2FZR_DBG_TIM16_STOP_Pos (17U) +#define DBGMCU_APB2FZR_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM16_STOP_Pos) +#define DBGMCU_APB2FZR_DBG_TIM16_STOP DBGMCU_APB2FZR_DBG_TIM16_STOP_Msk +#define DBGMCU_APB2FZR_DBG_TIM17_STOP_Pos (18U) +#define DBGMCU_APB2FZR_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM17_STOP_Pos) +#define DBGMCU_APB2FZR_DBG_TIM17_STOP DBGMCU_APB2FZR_DBG_TIM17_STOP_Msk + +/******************** Bit definition for DBGMCU_APB7FZR register ***********/ +#define DBGMCU_APB7FZR_DBG_I2C3_STOP_Pos (10U) +#define DBGMCU_APB7FZR_DBG_I2C3_STOP_Msk (0x1UL << DBGMCU_APB7FZR_DBG_I2C3_STOP_Pos) +#define DBGMCU_APB7FZR_DBG_I2C3_STOP DBGMCU_APB7FZR_DBG_I2C3_STOP_Msk +#define DBGMCU_APB7FZR_DBG_LPTIM1_STOP_Pos (17U) +#define DBGMCU_APB7FZR_DBG_LPTIM1_STOP_Msk (0x1UL << DBGMCU_APB7FZR_DBG_LPTIM1_STOP_Pos) +#define DBGMCU_APB7FZR_DBG_LPTIM1_STOP DBGMCU_APB7FZR_DBG_LPTIM1_STOP_Msk +#define DBGMCU_APB7FZR_DBG_RTC_STOP_Pos (30U) +#define DBGMCU_APB7FZR_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB7FZR_DBG_RTC_STOP_Pos) +#define DBGMCU_APB7FZR_DBG_RTC_STOP DBGMCU_APB7FZR_DBG_RTC_STOP_Msk + +/******************** Bit definition for DBGMCU_AHB1FZR register ***********/ +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP_Pos (0U) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP_Pos) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP_Msk +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP_Pos (1U) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP_Pos) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP_Msk +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP_Pos (2U) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP_Pos) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP_Msk +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP_Pos (3U) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP_Pos) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP_Msk +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP_Pos (4U) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP_Pos) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP_Msk +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP_Pos (5U) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP_Pos) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP_Msk +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP_Pos (6U) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP_Pos) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP_Msk +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP_Pos (7U) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP_Pos) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP_Msk + + +/******************************************************************************/ +/* */ +/* DMA Controller (DMA) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for DMA_SECCFGR register ****************/ +#define DMA_SECCFGR_SEC0_Pos (0U) +#define DMA_SECCFGR_SEC0_Msk (0x1UL << DMA_SECCFGR_SEC0_Pos) /*!< 0x00000001 */ +#define DMA_SECCFGR_SEC0 DMA_SECCFGR_SEC0_Msk /*!< Secure State of Channel 0 */ +#define DMA_SECCFGR_SEC1_Pos (1U) +#define DMA_SECCFGR_SEC1_Msk (0x1UL << DMA_SECCFGR_SEC1_Pos) /*!< 0x00000002 */ +#define DMA_SECCFGR_SEC1 DMA_SECCFGR_SEC1_Msk /*!< Secure State of Channel 1 */ +#define DMA_SECCFGR_SEC2_Pos (2U) +#define DMA_SECCFGR_SEC2_Msk (0x1UL << DMA_SECCFGR_SEC2_Pos) /*!< 0x00000004 */ +#define DMA_SECCFGR_SEC2 DMA_SECCFGR_SEC2_Msk /*!< Secure State of Channel 2 */ +#define DMA_SECCFGR_SEC3_Pos (3U) +#define DMA_SECCFGR_SEC3_Msk (0x1UL << DMA_SECCFGR_SEC3_Pos) /*!< 0x00000008 */ +#define DMA_SECCFGR_SEC3 DMA_SECCFGR_SEC3_Msk /*!< Secure State of Channel 3 */ +#define DMA_SECCFGR_SEC4_Pos (4U) +#define DMA_SECCFGR_SEC4_Msk (0x1UL << DMA_SECCFGR_SEC4_Pos) /*!< 0x00000010 */ +#define DMA_SECCFGR_SEC4 DMA_SECCFGR_SEC4_Msk /*!< Secure State of Channel 4 */ +#define DMA_SECCFGR_SEC5_Pos (5U) +#define DMA_SECCFGR_SEC5_Msk (0x1UL << DMA_SECCFGR_SEC5_Pos) /*!< 0x00000020 */ +#define DMA_SECCFGR_SEC5 DMA_SECCFGR_SEC5_Msk /*!< Secure State of Channel 5 */ +#define DMA_SECCFGR_SEC6_Pos (6U) +#define DMA_SECCFGR_SEC6_Msk (0x1UL << DMA_SECCFGR_SEC6_Pos) /*!< 0x00000040 */ +#define DMA_SECCFGR_SEC6 DMA_SECCFGR_SEC6_Msk /*!< Secure State of Channel 6 */ +#define DMA_SECCFGR_SEC7_Pos (7U) +#define DMA_SECCFGR_SEC7_Msk (0x1UL << DMA_SECCFGR_SEC7_Pos) /*!< 0x00000080 */ +#define DMA_SECCFGR_SEC7 DMA_SECCFGR_SEC7_Msk /*!< Secure State of Channel 7 */ + +/******************* Bit definition for DMA_PRIVCFGR register ****************/ +#define DMA_PRIVCFGR_PRIV0_Pos (0U) +#define DMA_PRIVCFGR_PRIV0_Msk (0x1UL << DMA_PRIVCFGR_PRIV0_Pos) /*!< 0x00000001 */ +#define DMA_PRIVCFGR_PRIV0 DMA_PRIVCFGR_PRIV0_Msk /*!< Privileged State of Channel 0 */ +#define DMA_PRIVCFGR_PRIV1_Pos (1U) +#define DMA_PRIVCFGR_PRIV1_Msk (0x1UL << DMA_PRIVCFGR_PRIV1_Pos) /*!< 0x00000002 */ +#define DMA_PRIVCFGR_PRIV1 DMA_PRIVCFGR_PRIV1_Msk /*!< Privileged State of Channel 1 */ +#define DMA_PRIVCFGR_PRIV2_Pos (2U) +#define DMA_PRIVCFGR_PRIV2_Msk (0x1UL << DMA_PRIVCFGR_PRIV2_Pos) /*!< 0x00000004 */ +#define DMA_PRIVCFGR_PRIV2 DMA_PRIVCFGR_PRIV2_Msk /*!< Privileged State of Channel 2 */ +#define DMA_PRIVCFGR_PRIV3_Pos (3U) +#define DMA_PRIVCFGR_PRIV3_Msk (0x1UL << DMA_PRIVCFGR_PRIV3_Pos) /*!< 0x00000008 */ +#define DMA_PRIVCFGR_PRIV3 DMA_PRIVCFGR_PRIV3_Msk /*!< Privileged State of Channel 3 */ +#define DMA_PRIVCFGR_PRIV4_Pos (4U) +#define DMA_PRIVCFGR_PRIV4_Msk (0x1UL << DMA_PRIVCFGR_PRIV4_Pos) /*!< 0x00000010 */ +#define DMA_PRIVCFGR_PRIV4 DMA_PRIVCFGR_PRIV4_Msk /*!< Privileged State of Channel 4 */ +#define DMA_PRIVCFGR_PRIV5_Pos (5U) +#define DMA_PRIVCFGR_PRIV5_Msk (0x1UL << DMA_PRIVCFGR_PRIV5_Pos) /*!< 0x00000020 */ +#define DMA_PRIVCFGR_PRIV5 DMA_PRIVCFGR_PRIV5_Msk /*!< Privileged State of Channel 5 */ +#define DMA_PRIVCFGR_PRIV6_Pos (6U) +#define DMA_PRIVCFGR_PRIV6_Msk (0x1UL << DMA_PRIVCFGR_PRIV6_Pos) /*!< 0x00000040 */ +#define DMA_PRIVCFGR_PRIV6 DMA_PRIVCFGR_PRIV6_Msk /*!< Privileged State of Channel 6 */ +#define DMA_PRIVCFGR_PRIV7_Pos (7U) +#define DMA_PRIVCFGR_PRIV7_Msk (0x1UL << DMA_PRIVCFGR_PRIV7_Pos) /*!< 0x00000080 */ +#define DMA_PRIVCFGR_PRIV7 DMA_PRIVCFGR_PRIV7_Msk /*!< Privileged State of Channel 7 */ + +/******************* Bit definition for DMA_RCFGLOCKR register ****************/ +#define DMA_RCFGLOCKR_LOCK0_Pos (0U) +#define DMA_RCFGLOCKR_LOCK0_Msk (0x1UL << DMA_RCFGLOCKR_LOCK0_Pos) /*!< 0x00000001 */ +#define DMA_RCFGLOCKR_LOCK0 DMA_RCFGLOCKR_LOCK0_Msk /*!< Privileged and Secure State Lock of Channel 0 */ +#define DMA_RCFGLOCKR_LOCK1_Pos (1U) +#define DMA_RCFGLOCKR_LOCK1_Msk (0x1UL << DMA_RCFGLOCKR_LOCK1_Pos) /*!< 0x00000002 */ +#define DMA_RCFGLOCKR_LOCK1 DMA_RCFGLOCKR_LOCK1_Msk /*!< Privileged and Secure State Lock of Channel 1 */ +#define DMA_RCFGLOCKR_LOCK2_Pos (2U) +#define DMA_RCFGLOCKR_LOCK2_Msk (0x1UL << DMA_RCFGLOCKR_LOCK2_Pos) /*!< 0x00000004 */ +#define DMA_RCFGLOCKR_LOCK2 DMA_RCFGLOCKR_LOCK2_Msk /*!< Privileged and Secure State Lock of Channel 2 */ +#define DMA_RCFGLOCKR_LOCK3_Pos (3U) +#define DMA_RCFGLOCKR_LOCK3_Msk (0x1UL << DMA_RCFGLOCKR_LOCK3_Pos) /*!< 0x00000008 */ +#define DMA_RCFGLOCKR_LOCK3 DMA_RCFGLOCKR_LOCK3_Msk /*!< Privileged and Secure State Lock of Channel 3 */ +#define DMA_RCFGLOCKR_LOCK4_Pos (4U) +#define DMA_RCFGLOCKR_LOCK4_Msk (0x1UL << DMA_RCFGLOCKR_LOCK4_Pos) /*!< 0x00000010 */ +#define DMA_RCFGLOCKR_LOCK4 DMA_RCFGLOCKR_LOCK4_Msk /*!< Privileged and Secure State Lock of Channel 4 */ +#define DMA_RCFGLOCKR_LOCK5_Pos (5U) +#define DMA_RCFGLOCKR_LOCK5_Msk (0x1UL << DMA_RCFGLOCKR_LOCK5_Pos) /*!< 0x00000020 */ +#define DMA_RCFGLOCKR_LOCK5 DMA_RCFGLOCKR_LOCK5_Msk /*!< Privileged and Secure State Lock of Channel 5 */ +#define DMA_RCFGLOCKR_LOCK6_Pos (6U) +#define DMA_RCFGLOCKR_LOCK6_Msk (0x1UL << DMA_RCFGLOCKR_LOCK6_Pos) /*!< 0x00000040 */ +#define DMA_RCFGLOCKR_LOCK6 DMA_RCFGLOCKR_LOCK6_Msk /*!< Privileged and Secure State Lock of Channel 6 */ +#define DMA_RCFGLOCKR_LOCK7_Pos (7U) +#define DMA_RCFGLOCKR_LOCK7_Msk (0x1UL << DMA_RCFGLOCKR_LOCK7_Pos) /*!< 0x00000080 */ +#define DMA_RCFGLOCKR_LOCK7 DMA_RCFGLOCKR_LOCK7_Msk /*!< Privileged and Secure State Lock of Channel 7 */ + +/******************* Bit definition for DMA_MISR register ****************/ +#define DMA_MISR_MIS0_Pos (0U) +#define DMA_MISR_MIS0_Msk (0x1UL << DMA_MISR_MIS0_Pos) /*!< 0x00000001 */ +#define DMA_MISR_MIS0 DMA_MISR_MIS0_Msk /*!< Masked Interrupt State of Non-Secure Channel 0 */ +#define DMA_MISR_MIS1_Pos (1U) +#define DMA_MISR_MIS1_Msk (0x1UL << DMA_MISR_MIS1_Pos) /*!< 0x00000002 */ +#define DMA_MISR_MIS1 DMA_MISR_MIS1_Msk /*!< Masked Interrupt State of Non-Secure Channel 1 */ +#define DMA_MISR_MIS2_Pos (2U) +#define DMA_MISR_MIS2_Msk (0x1UL << DMA_MISR_MIS2_Pos) /*!< 0x00000004 */ +#define DMA_MISR_MIS2 DMA_MISR_MIS2_Msk /*!< Masked Interrupt State of Non-Secure Channel 2 */ +#define DMA_MISR_MIS3_Pos (3U) +#define DMA_MISR_MIS3_Msk (0x1UL << DMA_MISR_MIS3_Pos) /*!< 0x00000008 */ +#define DMA_MISR_MIS3 DMA_MISR_MIS3_Msk /*!< Masked Interrupt State of Non-Secure Channel 3 */ +#define DMA_MISR_MIS4_Pos (4U) +#define DMA_MISR_MIS4_Msk (0x1UL << DMA_MISR_MIS4_Pos) /*!< 0x00000010 */ +#define DMA_MISR_MIS4 DMA_MISR_MIS4_Msk /*!< Masked Interrupt State of Non-Secure Channel 4 */ +#define DMA_MISR_MIS5_Pos (5U) +#define DMA_MISR_MIS5_Msk (0x1UL << DMA_MISR_MIS5_Pos) /*!< 0x00000020 */ +#define DMA_MISR_MIS5 DMA_MISR_MIS5_Msk /*!< Masked Interrupt State of Non-Secure Channel 5 */ +#define DMA_MISR_MIS6_Pos (6U) +#define DMA_MISR_MIS6_Msk (0x1UL << DMA_MISR_MIS6_Pos) /*!< 0x00000040 */ +#define DMA_MISR_MIS6 DMA_MISR_MIS6_Msk /*!< Masked Interrupt State of Non-Secure Channel 6 */ +#define DMA_MISR_MIS7_Pos (7U) +#define DMA_MISR_MIS7_Msk (0x1UL << DMA_MISR_MIS7_Pos) /*!< 0x00000080 */ +#define DMA_MISR_MIS7 DMA_MISR_MIS7_Msk /*!< Masked Interrupt State of Non-Secure Channel 7 */ + +/******************* Bit definition for DMA_SMISR register ****************/ +#define DMA_SMISR_MIS0_Pos (0U) +#define DMA_SMISR_MIS0_Msk (0x1UL << DMA_SMISR_MIS0_Pos) /*!< 0x00000001 */ +#define DMA_SMISR_MIS0 DMA_SMISR_MIS0_Msk /*!< Masked Interrupt State of Secure Channel 0 */ +#define DMA_SMISR_MIS1_Pos (1U) +#define DMA_SMISR_MIS1_Msk (0x1UL << DMA_SMISR_MIS1_Pos) /*!< 0x00000002 */ +#define DMA_SMISR_MIS1 DMA_SMISR_MIS1_Msk /*!< Masked Interrupt State of Secure Channel 1 */ +#define DMA_SMISR_MIS2_Pos (2U) +#define DMA_SMISR_MIS2_Msk (0x1UL << DMA_SMISR_MIS2_Pos) /*!< 0x00000004 */ +#define DMA_SMISR_MIS2 DMA_SMISR_MIS2_Msk /*!< Masked Interrupt State of Secure Channel 2 */ +#define DMA_SMISR_MIS3_Pos (3U) +#define DMA_SMISR_MIS3_Msk (0x1UL << DMA_SMISR_MIS3_Pos) /*!< 0x00000008 */ +#define DMA_SMISR_MIS3 DMA_SMISR_MIS3_Msk /*!< Masked Interrupt State of Secure Channel 3 */ +#define DMA_SMISR_MIS4_Pos (4U) +#define DMA_SMISR_MIS4_Msk (0x1UL << DMA_SMISR_MIS4_Pos) /*!< 0x00000010 */ +#define DMA_SMISR_MIS4 DMA_SMISR_MIS4_Msk /*!< Masked Interrupt State of Secure Channel 4 */ +#define DMA_SMISR_MIS5_Pos (5U) +#define DMA_SMISR_MIS5_Msk (0x1UL << DMA_SMISR_MIS5_Pos) /*!< 0x00000020 */ +#define DMA_SMISR_MIS5 DMA_SMISR_MIS5_Msk /*!< Masked Interrupt State of Secure Channel 5 */ +#define DMA_SMISR_MIS6_Pos (6U) +#define DMA_SMISR_MIS6_Msk (0x1UL << DMA_SMISR_MIS6_Pos) /*!< 0x00000040 */ +#define DMA_SMISR_MIS6 DMA_SMISR_MIS6_Msk /*!< Masked Interrupt State of Secure Channel 6 */ +#define DMA_SMISR_MIS7_Pos (7U) +#define DMA_SMISR_MIS7_Msk (0x1UL << DMA_SMISR_MIS7_Pos) /*!< 0x00000080 */ +#define DMA_SMISR_MIS7 DMA_SMISR_MIS7_Msk /*!< Masked Interrupt State of Secure Channel 7 */ + +/******************* Bit definition for DMA_CLBAR register ****************/ +#define DMA_CLBAR_LBA_Pos (16U) +#define DMA_CLBAR_LBA_Msk (0xFFFFUL << DMA_CLBAR_LBA_Pos) /*!< 0xFFFF0000 */ +#define DMA_CLBAR_LBA DMA_CLBAR_LBA_Msk /*!< Linked-list Base Address of DMA channel x */ + +/******************* Bit definition for DMA_CFCR register *******************/ +#define DMA_CFCR_TCF_Pos (8U) +#define DMA_CFCR_TCF_Msk (0x1UL << DMA_CFCR_TCF_Pos) /*!< 0x00000100 */ +#define DMA_CFCR_TCF DMA_CFCR_TCF_Msk /*!< Transfer complete flag clear */ +#define DMA_CFCR_HTF_Pos (9U) +#define DMA_CFCR_HTF_Msk (0x1UL << DMA_CFCR_HTF_Pos) /*!< 0x00000200 */ +#define DMA_CFCR_HTF DMA_CFCR_HTF_Msk /*!< Half transfer complete flag clear */ +#define DMA_CFCR_DTEF_Pos (10U) +#define DMA_CFCR_DTEF_Msk (0x1UL << DMA_CFCR_DTEF_Pos) /*!< 0x00000400 */ +#define DMA_CFCR_DTEF DMA_CFCR_DTEF_Msk /*!< Data transfer error flag clear */ +#define DMA_CFCR_ULEF_Pos (11U) +#define DMA_CFCR_ULEF_Msk (0x1UL << DMA_CFCR_ULEF_Pos) /*!< 0x00000800 */ +#define DMA_CFCR_ULEF DMA_CFCR_ULEF_Msk /*!< Update linked-list item error flag clear */ +#define DMA_CFCR_USEF_Pos (12U) +#define DMA_CFCR_USEF_Msk (0x1UL << DMA_CFCR_USEF_Pos) /*!< 0x00001000 */ +#define DMA_CFCR_USEF DMA_CFCR_USEF_Msk /*!< User setting error flag clear */ +#define DMA_CFCR_SUSPF_Pos (13U) +#define DMA_CFCR_SUSPF_Msk (0x1UL << DMA_CFCR_SUSPF_Pos) /*!< 0x00002000 */ +#define DMA_CFCR_SUSPF DMA_CFCR_SUSPF_Msk /*!< Completed suspension flag clear */ +#define DMA_CFCR_TOF_Pos (14U) +#define DMA_CFCR_TOF_Msk (0x1UL << DMA_CFCR_TOF_Pos) /*!< 0x00004000 */ +#define DMA_CFCR_TOF DMA_CFCR_TOF_Msk /*!< Trigger overrun flag clear */ + +/******************* Bit definition for DMA_CSR register *******************/ +#define DMA_CSR_IDLEF_Pos (0U) +#define DMA_CSR_IDLEF_Msk (0x1UL << DMA_CSR_IDLEF_Pos) /*!< 0x00000001 */ +#define DMA_CSR_IDLEF DMA_CSR_IDLEF_Msk /*!< Idle flag */ +#define DMA_CSR_TCF_Pos (8U) +#define DMA_CSR_TCF_Msk (0x1UL << DMA_CSR_TCF_Pos) /*!< 0x00000100 */ +#define DMA_CSR_TCF DMA_CSR_TCF_Msk /*!< Transfer complete flag */ +#define DMA_CSR_HTF_Pos (9U) +#define DMA_CSR_HTF_Msk (0x1UL << DMA_CSR_HTF_Pos) /*!< 0x00000200 */ +#define DMA_CSR_HTF DMA_CSR_HTF_Msk /*!< Half transfer complete flag */ +#define DMA_CSR_DTEF_Pos (10U) +#define DMA_CSR_DTEF_Msk (0x1UL << DMA_CSR_DTEF_Pos) /*!< 0x00000400 */ +#define DMA_CSR_DTEF DMA_CSR_DTEF_Msk /*!< Data transfer error flag */ +#define DMA_CSR_ULEF_Pos (11U) +#define DMA_CSR_ULEF_Msk (0x1UL << DMA_CSR_ULEF_Pos) /*!< 0x00000800 */ +#define DMA_CSR_ULEF DMA_CSR_ULEF_Msk /*!< Update linked-list item error flag */ +#define DMA_CSR_USEF_Pos (12U) +#define DMA_CSR_USEF_Msk (0x1UL << DMA_CSR_USEF_Pos) /*!< 0x00001000 */ +#define DMA_CSR_USEF DMA_CSR_USEF_Msk /*!< User setting error flag */ +#define DMA_CSR_SUSPF_Pos (13U) +#define DMA_CSR_SUSPF_Msk (0x1UL << DMA_CSR_SUSPF_Pos) /*!< 0x00002000 */ +#define DMA_CSR_SUSPF DMA_CSR_SUSPF_Msk /*!< User setting error flag */ +#define DMA_CSR_TOF_Pos (14U) +#define DMA_CSR_TOF_Msk (0x1UL << DMA_CSR_TOF_Pos) /*!< 0x00004000 */ +#define DMA_CSR_TOF DMA_CSR_TOF_Msk /*!< Trigger overrun event flag */ +#define DMA_CSR_FIFOL_Pos (16U) +#define DMA_CSR_FIFOL_Msk (0xFFUL << DMA_CSR_FIFOL_Pos) /*!< 0x00FF0000 */ +#define DMA_CSR_FIFOL DMA_CSR_FIFOL_Msk /*!< Monitored FIFO level in bytes */ + +/******************* Bit definition for DMA_CCR register ********************/ +#define DMA_CCR_EN_Pos (0U) +#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */ +#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ +#define DMA_CCR_RESET_Pos (1U) +#define DMA_CCR_RESET_Msk (0x1UL << DMA_CCR_RESET_Pos) /*!< 0x00000002 */ +#define DMA_CCR_RESET DMA_CCR_RESET_Msk /*!< Channel reset */ +#define DMA_CCR_SUSP_Pos (2U) +#define DMA_CCR_SUSP_Msk (0x1UL << DMA_CCR_SUSP_Pos) /*!< 0x00000004 */ +#define DMA_CCR_SUSP DMA_CCR_SUSP_Msk /*!< Channel suspend */ +#define DMA_CCR_TCIE_Pos (8U) +#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000100 */ +#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ +#define DMA_CCR_HTIE_Pos (9U) +#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000200 */ +#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half transfer complete interrupt enable */ +#define DMA_CCR_DTEIE_Pos (10U) +#define DMA_CCR_DTEIE_Msk (0x1UL << DMA_CCR_DTEIE_Pos) /*!< 0x00000400 */ +#define DMA_CCR_DTEIE DMA_CCR_DTEIE_Msk /*!< Data transfer error interrupt enable */ +#define DMA_CCR_ULEIE_Pos (11U) +#define DMA_CCR_ULEIE_Msk (0x1UL << DMA_CCR_ULEIE_Pos) /*!< 0x00000800 */ +#define DMA_CCR_ULEIE DMA_CCR_ULEIE_Msk /*!< Update linked-list item error interrupt enable */ +#define DMA_CCR_USEIE_Pos (12U) +#define DMA_CCR_USEIE_Msk (0x1UL << DMA_CCR_USEIE_Pos) /*!< 0x00001000 */ +#define DMA_CCR_USEIE DMA_CCR_USEIE_Msk /*!< User setting error interrupt enable */ +#define DMA_CCR_SUSPIE_Pos (13U) +#define DMA_CCR_SUSPIE_Msk (0x1UL << DMA_CCR_SUSPIE_Pos) /*!< 0x00002000 */ +#define DMA_CCR_SUSPIE DMA_CCR_SUSPIE_Msk /*!< Completed suspension interrupt enable */ +#define DMA_CCR_TOIE_Pos (14U) +#define DMA_CCR_TOIE_Msk (0x1UL << DMA_CCR_TOIE_Pos) /*!< 0x00004000 */ +#define DMA_CCR_TOIE DMA_CCR_TOIE_Msk /*!< Trigger overrun interrupt enable */ +#define DMA_CCR_LSM_Pos (16U) +#define DMA_CCR_LSM_Msk (0x1UL << DMA_CCR_LSM_Pos) /*!< 0x00010000 */ +#define DMA_CCR_LSM DMA_CCR_LSM_Msk /*!< Link step mode */ +#define DMA_CCR_LAP_Pos (17U) +#define DMA_CCR_LAP_Msk (0x1UL << DMA_CCR_LAP_Pos) /*!< 0x00020000 */ +#define DMA_CCR_LAP DMA_CCR_LAP_Msk /*!< Linked-list allocated port */ +#define DMA_CCR_PRIO_Pos (22U) +#define DMA_CCR_PRIO_Msk (0x3UL << DMA_CCR_PRIO_Pos) /*!< 0x00C00000 */ +#define DMA_CCR_PRIO DMA_CCR_PRIO_Msk /*!< Priority level */ +#define DMA_CCR_PRIO_0 (0x1UL << DMA_CCR_PRIO_Pos) /*!< 0x00400000 */ +#define DMA_CCR_PRIO_1 (0x2UL << DMA_CCR_PRIO_Pos) /*!< 0x00800000 */ + +/******************* Bit definition for DMA_CTR1 register *******************/ +#define DMA_CTR1_SDW_LOG2_Pos (0U) +#define DMA_CTR1_SDW_LOG2_Msk (0x3UL << DMA_CTR1_SDW_LOG2_Pos) /*!< 0x00000003 */ +#define DMA_CTR1_SDW_LOG2 DMA_CTR1_SDW_LOG2_Msk /*!< Binary logarithm of the source data width of a burst */ +#define DMA_CTR1_SDW_LOG2_0 (0x1UL << DMA_CTR1_SDW_LOG2_Pos) /*!< Bit 0 */ +#define DMA_CTR1_SDW_LOG2_1 (0x2UL << DMA_CTR1_SDW_LOG2_Pos) /*!< Bit 1 */ +#define DMA_CTR1_SINC_Pos (3U) +#define DMA_CTR1_SINC_Msk (0x1UL << DMA_CTR1_SINC_Pos) /*!< 0x00000008 */ +#define DMA_CTR1_SINC DMA_CTR1_SINC_Msk /*!< Source incrementing burst */ +#define DMA_CTR1_SBL_1_Pos (4U) +#define DMA_CTR1_SBL_1_Msk (0x3FUL << DMA_CTR1_SBL_1_Pos) /*!< 0x000003F0 */ +#define DMA_CTR1_SBL_1 DMA_CTR1_SBL_1_Msk /*!< Source burst length minus 1 */ +#define DMA_CTR1_PAM_Pos (11U) +#define DMA_CTR1_PAM_Msk (0x3UL << DMA_CTR1_PAM_Pos) /*!< 0x0001800 */ +#define DMA_CTR1_PAM DMA_CTR1_PAM_Msk /*!< Padding / alignment mode */ +#define DMA_CTR1_PAM_0 (0x1UL << DMA_CTR1_PAM_Pos) /*!< Bit 0 */ +#define DMA_CTR1_PAM_1 (0x2UL << DMA_CTR1_PAM_Pos) /*!< Bit 1 */ +#define DMA_CTR1_SBX_Pos (13U) +#define DMA_CTR1_SBX_Msk (0x1UL << DMA_CTR1_SBX_Pos) /*!< 0x00002000 */ +#define DMA_CTR1_SBX DMA_CTR1_SBX_Msk /*!< Source byte exchange within the unaligned half-word of each source word */ +#define DMA_CTR1_SAP_Pos (14U) +#define DMA_CTR1_SAP_Msk (0x1UL << DMA_CTR1_SAP_Pos) /*!< 0x00004000 */ +#define DMA_CTR1_SAP DMA_CTR1_SAP_Msk /*!< Source allocated port */ +#define DMA_CTR1_SSEC_Pos (15U) +#define DMA_CTR1_SSEC_Msk (0x1UL << DMA_CTR1_SSEC_Pos) /*!< 0x00008000 */ +#define DMA_CTR1_SSEC DMA_CTR1_SSEC_Msk /*!< Security attribute of the DMA transfer from the source */ +#define DMA_CTR1_DDW_LOG2_Pos (16U) +#define DMA_CTR1_DDW_LOG2_Msk (0x3UL << DMA_CTR1_DDW_LOG2_Pos) /*!< 0x00030000 */ +#define DMA_CTR1_DDW_LOG2 DMA_CTR1_DDW_LOG2_Msk /*!< Binary logarithm of the destination data width of a burst */ +#define DMA_CTR1_DDW_LOG2_0 (0x1UL << DMA_CTR1_DDW_LOG2_Pos) /*!< Bit 0 */ +#define DMA_CTR1_DDW_LOG2_1 (0x2UL << DMA_CTR1_DDW_LOG2_Pos) /*!< Bit 1 */ +#define DMA_CTR1_DINC_Pos (19U) +#define DMA_CTR1_DINC_Msk (0x1UL << DMA_CTR1_DINC_Pos) /*!< 0x00080000 */ +#define DMA_CTR1_DINC DMA_CTR1_DINC_Msk /*!< Destination incrementing burst */ +#define DMA_CTR1_DBL_1_Pos (20U) +#define DMA_CTR1_DBL_1_Msk (0x3FUL << DMA_CTR1_DBL_1_Pos) /*!< 0x03F00000 */ +#define DMA_CTR1_DBL_1 DMA_CTR1_DBL_1_Msk /*!< Destination burst length minus 1 */ +#define DMA_CTR1_DBX_Pos (26U) +#define DMA_CTR1_DBX_Msk (0x1UL << DMA_CTR1_DBX_Pos) /*!< 0x04000000 */ +#define DMA_CTR1_DBX DMA_CTR1_DBX_Msk /*!< Destination byte exchange */ +#define DMA_CTR1_DHX_Pos (27U) +#define DMA_CTR1_DHX_Msk (0x1UL << DMA_CTR1_DHX_Pos) /*!< 0x08000000 */ +#define DMA_CTR1_DHX DMA_CTR1_DHX_Msk /*!< Destination half-word exchange */ +#define DMA_CTR1_DAP_Pos (30U) +#define DMA_CTR1_DAP_Msk (0x1UL << DMA_CTR1_DAP_Pos) /*!< 0x40000000 */ +#define DMA_CTR1_DAP DMA_CTR1_DAP_Msk /*!< Destination allocated port */ +#define DMA_CTR1_DSEC_Pos (31U) +#define DMA_CTR1_DSEC_Msk (0x1UL << DMA_CTR1_DSEC_Pos) /*!< 0x80000000 */ +#define DMA_CTR1_DSEC DMA_CTR1_DSEC_Msk /*!< Security attribute of the DMA transfer from the destination */ + +/****************** Bit definition for DMA_CTR2 register *******************/ +#define DMA_CTR2_REQSEL_Pos (0U) +#define DMA_CTR2_REQSEL_Msk (0x3FUL << DMA_CTR2_REQSEL_Pos) /*!< 0x0000003F */ +#define DMA_CTR2_REQSEL DMA_CTR2_REQSEL_Msk /*!< DMA hardware request selection */ +#define DMA_CTR2_SWREQ_Pos (9U) +#define DMA_CTR2_SWREQ_Msk (0x1UL << DMA_CTR2_SWREQ_Pos) /*!< 0x00000100 */ +#define DMA_CTR2_SWREQ DMA_CTR2_SWREQ_Msk /*!< Software request */ +#define DMA_CTR2_DREQ_Pos (10U) +#define DMA_CTR2_DREQ_Msk (0x1UL << DMA_CTR2_DREQ_Pos) /*!< 0x00000100 */ +#define DMA_CTR2_DREQ DMA_CTR2_DREQ_Msk /*!< Destination hardware request */ +#define DMA_CTR2_BREQ_Pos (11U) +#define DMA_CTR2_BREQ_Msk (0x1UL << DMA_CTR2_BREQ_Pos) /*!< 0x00000200 */ +#define DMA_CTR2_BREQ DMA_CTR2_BREQ_Msk /*!< Block hardware request */ +#define DMA_CTR2_TRIGM_Pos (14U) +#define DMA_CTR2_TRIGM_Msk (0x3UL << DMA_CTR2_TRIGM_Pos) /*!< 0x0000C000 */ +#define DMA_CTR2_TRIGM DMA_CTR2_TRIGM_Msk /*!< Trigger mode */ +#define DMA_CTR2_TRIGM_0 (0x1UL << DMA_CTR2_TRIGM_Pos) /*!< Bit 0 */ +#define DMA_CTR2_TRIGM_1 (0x2UL << DMA_CTR2_TRIGM_Pos) /*!< Bit 1 */ +#define DMA_CTR2_TRIGSEL_Pos (16U) +#define DMA_CTR2_TRIGSEL_Msk (0x1FUL << DMA_CTR2_TRIGSEL_Pos) /*!< 0x001F0000 */ +#define DMA_CTR2_TRIGSEL DMA_CTR2_TRIGSEL_Msk /*!< Trigger event input selection */ +#define DMA_CTR2_TRIGPOL_Pos (24U) +#define DMA_CTR2_TRIGPOL_Msk (0x3UL << DMA_CTR2_TRIGPOL_Pos) /*!< 0x03000000 */ +#define DMA_CTR2_TRIGPOL DMA_CTR2_TRIGPOL_Msk /*!< Trigger event polarity */ +#define DMA_CTR2_TRIGPOL_0 (0x1UL << DMA_CTR2_TRIGPOL_Pos) /*!< Bit 0 */ +#define DMA_CTR2_TRIGPOL_1 (0x2UL << DMA_CTR2_TRIGPOL_Pos) /*!< Bit 1 */ +#define DMA_CTR2_TCEM_Pos (30U) +#define DMA_CTR2_TCEM_Msk (0x3UL << DMA_CTR2_TCEM_Pos) /*!< 0xC0000000 */ +#define DMA_CTR2_TCEM DMA_CTR2_TCEM_Msk /*!< Transfer complete event mode */ +#define DMA_CTR2_TCEM_0 (0x1UL << DMA_CTR2_TCEM_Pos) /*!< Bit 0 */ +#define DMA_CTR2_TCEM_1 (0x2UL << DMA_CTR2_TCEM_Pos) /*!< Bit 1 */ + +/****************** Bit definition for DMA_CBR1 register *******************/ +#define DMA_CBR1_BNDT_Pos (0U) +#define DMA_CBR1_BNDT_Msk (0xFFFFUL << DMA_CBR1_BNDT_Pos) /*!< 0x0000FFFF */ +#define DMA_CBR1_BNDT DMA_CBR1_BNDT_Msk /*!< Block number of data bytes to transfer from the source */ + +/****************** Bit definition for DMA_CSAR register ********************/ +#define DMA_CSAR_SA_Pos (0U) +#define DMA_CSAR_SA_Msk (0xFFFFFFFFUL << DMA_CSAR_SA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CSAR_SA DMA_CSAR_SA_Msk /*!< Source Address */ + +/****************** Bit definition for DMA_CDAR register *******************/ +#define DMA_CDAR_DA_Pos (0U) +#define DMA_CDAR_DA_Msk (0xFFFFFFFFUL << DMA_CDAR_DA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CDAR_DA DMA_CDAR_DA_Msk /*!< Destination address */ + +/****************** Bit definition for DMA_CLLR register *******************/ +#define DMA_CLLR_LA_Pos (2U) +#define DMA_CLLR_LA_Msk (0x3FFFUL << DMA_CLLR_LA_Pos) /*!< 0x0000FFFC */ +#define DMA_CLLR_LA DMA_CLLR_LA_Msk /*!< Pointer to the next linked-list data structure */ +#define DMA_CLLR_ULL_Pos (16U) +#define DMA_CLLR_ULL_Msk (0x1UL << DMA_CLLR_ULL_Pos) /*!< 0x00010000 */ +#define DMA_CLLR_ULL DMA_CLLR_ULL_Msk /*!< Update link address register from memory */ +#define DMA_CLLR_UDA_Pos (27U) +#define DMA_CLLR_UDA_Msk (0x1UL << DMA_CLLR_UDA_Pos) /*!< 0x08000000 */ +#define DMA_CLLR_UDA DMA_CLLR_UDA_Msk /*!< Update destination address register from SRAM */ +#define DMA_CLLR_USA_Pos (28U) +#define DMA_CLLR_USA_Msk (0x1UL << DMA_CLLR_USA_Pos) /*!< 0x10000000 */ +#define DMA_CLLR_USA DMA_CLLR_USA_Msk /*!< Update source address register from SRAM */ +#define DMA_CLLR_UB1_Pos (29U) +#define DMA_CLLR_UB1_Msk (0x1UL << DMA_CLLR_UB1_Pos) /*!< 0x20000000 */ +#define DMA_CLLR_UB1 DMA_CLLR_UB1_Msk /*!< Update block register 1 from SRAM */ +#define DMA_CLLR_UT2_Pos (30U) +#define DMA_CLLR_UT2_Msk (0x1UL << DMA_CLLR_UT2_Pos) /*!< 0x40000000 */ +#define DMA_CLLR_UT2 DMA_CLLR_UT2_Msk /*!< Update transfer register 2 from SRAM */ +#define DMA_CLLR_UT1_Pos (31U) +#define DMA_CLLR_UT1_Msk (0x1UL << DMA_CLLR_UT1_Pos) /*!< 0x80000000 */ +#define DMA_CLLR_UT1 DMA_CLLR_UT1_Msk /*!< Update transfer register 1 from SRAM */ + +/******************************************************************************/ +/* */ +/* External Interrupt/Event Controller */ +/* */ +/******************************************************************************/ +/****************** Bit definition for EXTI_RTSR1 register ******************/ +#define EXTI_RTSR1_RT0_Pos (0U) +#define EXTI_RTSR1_RT0_Msk (0x1UL << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */ +#define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger configuration for input line 0 */ +#define EXTI_RTSR1_RT1_Pos (1U) +#define EXTI_RTSR1_RT1_Msk (0x1UL << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */ +#define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger configuration for input line 1 */ +#define EXTI_RTSR1_RT2_Pos (2U) +#define EXTI_RTSR1_RT2_Msk (0x1UL << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */ +#define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger configuration for input line 2 */ +#define EXTI_RTSR1_RT3_Pos (3U) +#define EXTI_RTSR1_RT3_Msk (0x1UL << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */ +#define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger configuration for input line 3 */ +#define EXTI_RTSR1_RT4_Pos (4U) +#define EXTI_RTSR1_RT4_Msk (0x1UL << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */ +#define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger configuration for input line 4 */ +#define EXTI_RTSR1_RT5_Pos (5U) +#define EXTI_RTSR1_RT5_Msk (0x1UL << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */ +#define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger configuration for input line 5 */ +#define EXTI_RTSR1_RT6_Pos (6U) +#define EXTI_RTSR1_RT6_Msk (0x1UL << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */ +#define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger configuration for input line 6 */ +#define EXTI_RTSR1_RT7_Pos (7U) +#define EXTI_RTSR1_RT7_Msk (0x1UL << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */ +#define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger configuration for input line 7 */ +#define EXTI_RTSR1_RT8_Pos (8U) +#define EXTI_RTSR1_RT8_Msk (0x1UL << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */ +#define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger configuration for input line 8 */ +#define EXTI_RTSR1_RT9_Pos (9U) +#define EXTI_RTSR1_RT9_Msk (0x1UL << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */ +#define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger configuration for input line 9 */ +#define EXTI_RTSR1_RT10_Pos (10U) +#define EXTI_RTSR1_RT10_Msk (0x1UL << EXTI_RTSR1_RT10_Pos) /*!< 0x00000400 */ +#define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk /*!< Rising trigger configuration for input line 10 */ +#define EXTI_RTSR1_RT11_Pos (11U) +#define EXTI_RTSR1_RT11_Msk (0x1UL << EXTI_RTSR1_RT11_Pos) /*!< 0x00000800 */ +#define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk /*!< Rising trigger configuration for input line 11 */ +#define EXTI_RTSR1_RT12_Pos (12U) +#define EXTI_RTSR1_RT12_Msk (0x1UL << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */ +#define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger configuration for input line 12 */ +#define EXTI_RTSR1_RT13_Pos (13U) +#define EXTI_RTSR1_RT13_Msk (0x1UL << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */ +#define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger configuration for input line 13 */ +#define EXTI_RTSR1_RT14_Pos (14U) +#define EXTI_RTSR1_RT14_Msk (0x1UL << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */ +#define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger configuration for input line 14 */ +#define EXTI_RTSR1_RT15_Pos (15U) +#define EXTI_RTSR1_RT15_Msk (0x1UL << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */ +#define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger configuration for input line 15 */ +#define EXTI_RTSR1_RT16_Pos (16U) +#define EXTI_RTSR1_RT16_Msk (0x1UL << EXTI_RTSR1_RT16_Pos) /*!< 0x00010000 */ +#define EXTI_RTSR1_RT16 EXTI_RTSR1_RT16_Msk /*!< Rising trigger configuration for input line 16 */ +#define EXTI_RTSR1_RT17_Pos (17U) +#define EXTI_RTSR1_RT17_Msk (0x1UL << EXTI_RTSR1_RT17_Pos) /*!< 0x00020000 */ +#define EXTI_RTSR1_RT17 EXTI_RTSR1_RT17_Msk /*!< Rising trigger configuration for input line 17 */ +#define EXTI_RTSR1_RT18_Pos (18U) +#define EXTI_RTSR1_RT18_Msk (0x1UL << EXTI_RTSR1_RT18_Pos) /*!< 0x00040000 */ +#define EXTI_RTSR1_RT18 EXTI_RTSR1_RT18_Msk /*!< Rising trigger configuration for input line 18 */ + +/****************** Bit definition for EXTI_FTSR1 register ******************/ +#define EXTI_FTSR1_FT0_Pos (0U) +#define EXTI_FTSR1_FT0_Msk (0x1UL << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */ +#define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger configuration for input line 0 */ +#define EXTI_FTSR1_FT1_Pos (1U) +#define EXTI_FTSR1_FT1_Msk (0x1UL << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */ +#define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger configuration for input line 1 */ +#define EXTI_FTSR1_FT2_Pos (2U) +#define EXTI_FTSR1_FT2_Msk (0x1UL << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */ +#define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger configuration for input line 2 */ +#define EXTI_FTSR1_FT3_Pos (3U) +#define EXTI_FTSR1_FT3_Msk (0x1UL << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */ +#define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger configuration for input line 3 */ +#define EXTI_FTSR1_FT4_Pos (4U) +#define EXTI_FTSR1_FT4_Msk (0x1UL << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */ +#define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger configuration for input line 4 */ +#define EXTI_FTSR1_FT5_Pos (5U) +#define EXTI_FTSR1_FT5_Msk (0x1UL << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */ +#define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger configuration for input line 5 */ +#define EXTI_FTSR1_FT6_Pos (6U) +#define EXTI_FTSR1_FT6_Msk (0x1UL << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */ +#define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger configuration for input line 6 */ +#define EXTI_FTSR1_FT7_Pos (7U) +#define EXTI_FTSR1_FT7_Msk (0x1UL << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */ +#define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger configuration for input line 7 */ +#define EXTI_FTSR1_FT8_Pos (8U) +#define EXTI_FTSR1_FT8_Msk (0x1UL << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */ +#define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger configuration for input line 8 */ +#define EXTI_FTSR1_FT9_Pos (9U) +#define EXTI_FTSR1_FT9_Msk (0x1UL << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */ +#define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger configuration for input line 9 */ +#define EXTI_FTSR1_FT10_Pos (10U) +#define EXTI_FTSR1_FT10_Msk (0x1UL << EXTI_FTSR1_FT10_Pos) /*!< 0x00000400 */ +#define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk /*!< Falling trigger configuration for input line 10 */ +#define EXTI_FTSR1_FT11_Pos (11U) +#define EXTI_FTSR1_FT11_Msk (0x1UL << EXTI_FTSR1_FT11_Pos) /*!< 0x00000800 */ +#define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk /*!< Falling trigger configuration for input line 11 */ +#define EXTI_FTSR1_FT12_Pos (12U) +#define EXTI_FTSR1_FT12_Msk (0x1UL << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */ +#define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger configuration for input line 12 */ +#define EXTI_FTSR1_FT13_Pos (13U) +#define EXTI_FTSR1_FT13_Msk (0x1UL << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */ +#define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger configuration for input line 13 */ +#define EXTI_FTSR1_FT14_Pos (14U) +#define EXTI_FTSR1_FT14_Msk (0x1UL << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */ +#define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger configuration for input line 14 */ +#define EXTI_FTSR1_FT15_Pos (15U) +#define EXTI_FTSR1_FT15_Msk (0x1UL << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */ +#define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger configuration for input line 15 */ +#define EXTI_FTSR1_FT16_Pos (16U) +#define EXTI_FTSR1_FT16_Msk (0x1UL << EXTI_FTSR1_FT16_Pos) /*!< 0x00010000 */ +#define EXTI_FTSR1_FT16 EXTI_FTSR1_FT16_Msk /*!< Falling trigger configuration for input line 16 */ +#define EXTI_FTSR1_FT17_Pos (17U) +#define EXTI_FTSR1_FT17_Msk (0x1UL << EXTI_FTSR1_FT17_Pos) /*!< 0x00020000 */ +#define EXTI_FTSR1_FT17 EXTI_FTSR1_FT17_Msk /*!< Falling trigger configuration for input line 17 */ +#define EXTI_FTSR1_FT18_Pos (18U) +#define EXTI_FTSR1_FT18_Msk (0x1UL << EXTI_FTSR1_FT18_Pos) /*!< 0x00040000 */ +#define EXTI_FTSR1_FT18 EXTI_FTSR1_FT18_Msk /*!< Falling trigger configuration for input line 18 */ + +/****************** Bit definition for EXTI_SWIER1 register *****************/ +#define EXTI_SWIER1_SWI0_Pos (0U) +#define EXTI_SWIER1_SWI0_Msk (0x1UL << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */ +#define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software Interrupt on line 0 */ +#define EXTI_SWIER1_SWI1_Pos (1U) +#define EXTI_SWIER1_SWI1_Msk (0x1UL << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */ +#define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software Interrupt on line 1 */ +#define EXTI_SWIER1_SWI2_Pos (2U) +#define EXTI_SWIER1_SWI2_Msk (0x1UL << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */ +#define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software Interrupt on line 2 */ +#define EXTI_SWIER1_SWI3_Pos (3U) +#define EXTI_SWIER1_SWI3_Msk (0x1UL << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */ +#define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software Interrupt on line 3 */ +#define EXTI_SWIER1_SWI4_Pos (4U) +#define EXTI_SWIER1_SWI4_Msk (0x1UL << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */ +#define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software Interrupt on line 4 */ +#define EXTI_SWIER1_SWI5_Pos (5U) +#define EXTI_SWIER1_SWI5_Msk (0x1UL << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */ +#define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software Interrupt on line 5 */ +#define EXTI_SWIER1_SWI6_Pos (6U) +#define EXTI_SWIER1_SWI6_Msk (0x1UL << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */ +#define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software Interrupt on line 6 */ +#define EXTI_SWIER1_SWI7_Pos (7U) +#define EXTI_SWIER1_SWI7_Msk (0x1UL << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */ +#define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software Interrupt on line 7 */ +#define EXTI_SWIER1_SWI8_Pos (8U) +#define EXTI_SWIER1_SWI8_Msk (0x1UL << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */ +#define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software Interrupt on line 8 */ +#define EXTI_SWIER1_SWI9_Pos (9U) +#define EXTI_SWIER1_SWI9_Msk (0x1UL << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */ +#define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software Interrupt on line 9 */ +#define EXTI_SWIER1_SWI10_Pos (10U) +#define EXTI_SWIER1_SWI10_Msk (0x1UL << EXTI_SWIER1_SWI10_Pos) /*!< 0x00000400 */ +#define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk /*!< Software Interrupt on line 10 */ +#define EXTI_SWIER1_SWI11_Pos (11U) +#define EXTI_SWIER1_SWI11_Msk (0x1UL << EXTI_SWIER1_SWI11_Pos) /*!< 0x00000800 */ +#define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk /*!< Software Interrupt on line 11 */ +#define EXTI_SWIER1_SWI12_Pos (12U) +#define EXTI_SWIER1_SWI12_Msk (0x1UL << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */ +#define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software Interrupt on line 12 */ +#define EXTI_SWIER1_SWI13_Pos (13U) +#define EXTI_SWIER1_SWI13_Msk (0x1UL << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */ +#define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software Interrupt on line 13 */ +#define EXTI_SWIER1_SWI14_Pos (14U) +#define EXTI_SWIER1_SWI14_Msk (0x1UL << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */ +#define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software Interrupt on line 14 */ +#define EXTI_SWIER1_SWI15_Pos (15U) +#define EXTI_SWIER1_SWI15_Msk (0x1UL << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */ +#define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software Interrupt on line 15 */ +#define EXTI_SWIER1_SWI16_Pos (16U) +#define EXTI_SWIER1_SWI16_Msk (0x1UL << EXTI_SWIER1_SWI16_Pos) /*!< 0x00010000 */ +#define EXTI_SWIER1_SWI16 EXTI_SWIER1_SWI16_Msk /*!< Software Interrupt on line 16 */ +#define EXTI_SWIER1_SWI17_Pos (17U) +#define EXTI_SWIER1_SWI17_Msk (0x1UL << EXTI_SWIER1_SWI17_Pos) /*!< 0x00020000 */ +#define EXTI_SWIER1_SWI17 EXTI_SWIER1_SWI17_Msk /*!< Software Interrupt on line 17 */ +#define EXTI_SWIER1_SWI18_Pos (18U) +#define EXTI_SWIER1_SWI18_Msk (0x1UL << EXTI_SWIER1_SWI18_Pos) /*!< 0x00040000 */ +#define EXTI_SWIER1_SWI18 EXTI_SWIER1_SWI18_Msk /*!< Software Interrupt on line 18 */ + +/******************* Bit definition for EXTI_RPR1 register ******************/ +#define EXTI_RPR1_RPIF0_Pos (0U) +#define EXTI_RPR1_RPIF0_Msk (0x1UL << EXTI_RPR1_RPIF0_Pos) /*!< 0x00000001 */ +#define EXTI_RPR1_RPIF0 EXTI_RPR1_RPIF0_Msk /*!< Rising Pending Interrupt Flag on line 0 */ +#define EXTI_RPR1_RPIF1_Pos (1U) +#define EXTI_RPR1_RPIF1_Msk (0x1UL << EXTI_RPR1_RPIF1_Pos) /*!< 0x00000002 */ +#define EXTI_RPR1_RPIF1 EXTI_RPR1_RPIF1_Msk /*!< Rising Pending Interrupt Flag on line 1 */ +#define EXTI_RPR1_RPIF2_Pos (2U) +#define EXTI_RPR1_RPIF2_Msk (0x1UL << EXTI_RPR1_RPIF2_Pos) /*!< 0x00000004 */ +#define EXTI_RPR1_RPIF2 EXTI_RPR1_RPIF2_Msk /*!< Rising Pending Interrupt Flag on line 2 */ +#define EXTI_RPR1_RPIF3_Pos (3U) +#define EXTI_RPR1_RPIF3_Msk (0x1UL << EXTI_RPR1_RPIF3_Pos) /*!< 0x00000008 */ +#define EXTI_RPR1_RPIF3 EXTI_RPR1_RPIF3_Msk /*!< Rising Pending Interrupt Flag on line 3 */ +#define EXTI_RPR1_RPIF4_Pos (4U) +#define EXTI_RPR1_RPIF4_Msk (0x1UL << EXTI_RPR1_RPIF4_Pos) /*!< 0x00000010 */ +#define EXTI_RPR1_RPIF4 EXTI_RPR1_RPIF4_Msk /*!< Rising Pending Interrupt Flag on line 4 */ +#define EXTI_RPR1_RPIF5_Pos (5U) +#define EXTI_RPR1_RPIF5_Msk (0x1UL << EXTI_RPR1_RPIF5_Pos) /*!< 0x00000020 */ +#define EXTI_RPR1_RPIF5 EXTI_RPR1_RPIF5_Msk /*!< Rising Pending Interrupt Flag on line 5 */ +#define EXTI_RPR1_RPIF6_Pos (6U) +#define EXTI_RPR1_RPIF6_Msk (0x1UL << EXTI_RPR1_RPIF6_Pos) /*!< 0x00000040 */ +#define EXTI_RPR1_RPIF6 EXTI_RPR1_RPIF6_Msk /*!< Rising Pending Interrupt Flag on line 6 */ +#define EXTI_RPR1_RPIF7_Pos (7U) +#define EXTI_RPR1_RPIF7_Msk (0x1UL << EXTI_RPR1_RPIF7_Pos) /*!< 0x00000080 */ +#define EXTI_RPR1_RPIF7 EXTI_RPR1_RPIF7_Msk /*!< Rising Pending Interrupt Flag on line 7 */ +#define EXTI_RPR1_RPIF8_Pos (8U) +#define EXTI_RPR1_RPIF8_Msk (0x1UL << EXTI_RPR1_RPIF8_Pos) /*!< 0x00000100 */ +#define EXTI_RPR1_RPIF8 EXTI_RPR1_RPIF8_Msk /*!< Rising Pending Interrupt Flag on line 8 */ +#define EXTI_RPR1_RPIF9_Pos (9U) +#define EXTI_RPR1_RPIF9_Msk (0x1UL << EXTI_RPR1_RPIF9_Pos) /*!< 0x00000200 */ +#define EXTI_RPR1_RPIF9 EXTI_RPR1_RPIF9_Msk /*!< Rising Pending Interrupt Flag on line 9 */ +#define EXTI_RPR1_RPIF10_Pos (10U) +#define EXTI_RPR1_RPIF10_Msk (0x1UL << EXTI_RPR1_RPIF10_Pos) /*!< 0x00000400 */ +#define EXTI_RPR1_RPIF10 EXTI_RPR1_RPIF10_Msk /*!< Rising Pending Interrupt Flag on line 10 */ +#define EXTI_RPR1_RPIF11_Pos (11U) +#define EXTI_RPR1_RPIF11_Msk (0x1UL << EXTI_RPR1_RPIF11_Pos) /*!< 0x00000800 */ +#define EXTI_RPR1_RPIF11 EXTI_RPR1_RPIF11_Msk /*!< Rising Pending Interrupt Flag on line 11 */ +#define EXTI_RPR1_RPIF12_Pos (12U) +#define EXTI_RPR1_RPIF12_Msk (0x1UL << EXTI_RPR1_RPIF12_Pos) /*!< 0x00001000 */ +#define EXTI_RPR1_RPIF12 EXTI_RPR1_RPIF12_Msk /*!< Rising Pending Interrupt Flag on line 12 */ +#define EXTI_RPR1_RPIF13_Pos (13U) +#define EXTI_RPR1_RPIF13_Msk (0x1UL << EXTI_RPR1_RPIF13_Pos) /*!< 0x00002000 */ +#define EXTI_RPR1_RPIF13 EXTI_RPR1_RPIF13_Msk /*!< Rising Pending Interrupt Flag on line 13 */ +#define EXTI_RPR1_RPIF14_Pos (14U) +#define EXTI_RPR1_RPIF14_Msk (0x1UL << EXTI_RPR1_RPIF14_Pos) /*!< 0x00004000 */ +#define EXTI_RPR1_RPIF14 EXTI_RPR1_RPIF14_Msk /*!< Rising Pending Interrupt Flag on line 14 */ +#define EXTI_RPR1_RPIF15_Pos (15U) +#define EXTI_RPR1_RPIF15_Msk (0x1UL << EXTI_RPR1_RPIF15_Pos) /*!< 0x00008000 */ +#define EXTI_RPR1_RPIF15 EXTI_RPR1_RPIF15_Msk /*!< Rising Pending Interrupt Flag on line 15 */ +#define EXTI_RPR1_RPIF16_Pos (16U) +#define EXTI_RPR1_RPIF16_Msk (0x1UL << EXTI_RPR1_RPIF16_Pos) /*!< 0x00010000 */ +#define EXTI_RPR1_RPIF16 EXTI_RPR1_RPIF16_Msk /*!< Rising Pending Interrupt Flag on line 16 */ +#define EXTI_RPR1_RPIF17_Pos (17U) +#define EXTI_RPR1_RPIF17_Msk (0x1UL << EXTI_RPR1_RPIF17_Pos) /*!< 0x00020000 */ +#define EXTI_RPR1_RPIF17 EXTI_RPR1_RPIF17_Msk /*!< Rising Pending Interrupt Flag on line 17 */ +#define EXTI_RPR1_RPIF18_Pos (18U) +#define EXTI_RPR1_RPIF18_Msk (0x1UL << EXTI_RPR1_RPIF18_Pos) /*!< 0x00040000 */ +#define EXTI_RPR1_RPIF18 EXTI_RPR1_RPIF18_Msk /*!< Rising Pending Interrupt Flag on line 18 */ + +/******************* Bit definition for EXTI_FPR1 register ******************/ +#define EXTI_FPR1_FPIF0_Pos (0U) +#define EXTI_FPR1_FPIF0_Msk (0x1UL << EXTI_FPR1_FPIF0_Pos) /*!< 0x00000001 */ +#define EXTI_FPR1_FPIF0 EXTI_FPR1_FPIF0_Msk /*!< Falling Pending Interrupt Flag on line 0 */ +#define EXTI_FPR1_FPIF1_Pos (1U) +#define EXTI_FPR1_FPIF1_Msk (0x1UL << EXTI_FPR1_FPIF1_Pos) /*!< 0x00000002 */ +#define EXTI_FPR1_FPIF1 EXTI_FPR1_FPIF1_Msk /*!< Falling Pending Interrupt Flag on line 1 */ +#define EXTI_FPR1_FPIF2_Pos (2U) +#define EXTI_FPR1_FPIF2_Msk (0x1UL << EXTI_FPR1_FPIF2_Pos) /*!< 0x00000004 */ +#define EXTI_FPR1_FPIF2 EXTI_FPR1_FPIF2_Msk /*!< Falling Pending Interrupt Flag on line 2 */ +#define EXTI_FPR1_FPIF3_Pos (3U) +#define EXTI_FPR1_FPIF3_Msk (0x1UL << EXTI_FPR1_FPIF3_Pos) /*!< 0x00000008 */ +#define EXTI_FPR1_FPIF3 EXTI_FPR1_FPIF3_Msk /*!< Falling Pending Interrupt Flag on line 3 */ +#define EXTI_FPR1_FPIF4_Pos (4U) +#define EXTI_FPR1_FPIF4_Msk (0x1UL << EXTI_FPR1_FPIF4_Pos) /*!< 0x00000010 */ +#define EXTI_FPR1_FPIF4 EXTI_FPR1_FPIF4_Msk /*!< Falling Pending Interrupt Flag on line 4 */ +#define EXTI_FPR1_FPIF5_Pos (5U) +#define EXTI_FPR1_FPIF5_Msk (0x1UL << EXTI_FPR1_FPIF5_Pos) /*!< 0x00000020 */ +#define EXTI_FPR1_FPIF5 EXTI_FPR1_FPIF5_Msk /*!< Falling Pending Interrupt Flag on line 5 */ +#define EXTI_FPR1_FPIF6_Pos (6U) +#define EXTI_FPR1_FPIF6_Msk (0x1UL << EXTI_FPR1_FPIF6_Pos) /*!< 0x00000040 */ +#define EXTI_FPR1_FPIF6 EXTI_FPR1_FPIF6_Msk /*!< Falling Pending Interrupt Flag on line 6 */ +#define EXTI_FPR1_FPIF7_Pos (7U) +#define EXTI_FPR1_FPIF7_Msk (0x1UL << EXTI_FPR1_FPIF7_Pos) /*!< 0x00000080 */ +#define EXTI_FPR1_FPIF7 EXTI_FPR1_FPIF7_Msk /*!< Falling Pending Interrupt Flag on line 7 */ +#define EXTI_FPR1_FPIF8_Pos (8U) +#define EXTI_FPR1_FPIF8_Msk (0x1UL << EXTI_FPR1_FPIF8_Pos) /*!< 0x00000100 */ +#define EXTI_FPR1_FPIF8 EXTI_FPR1_FPIF8_Msk /*!< Falling Pending Interrupt Flag on line 8 */ +#define EXTI_FPR1_FPIF9_Pos (9U) +#define EXTI_FPR1_FPIF9_Msk (0x1UL << EXTI_FPR1_FPIF9_Pos) /*!< 0x00000200 */ +#define EXTI_FPR1_FPIF9 EXTI_FPR1_FPIF9_Msk /*!< Falling Pending Interrupt Flag on line 9 */ +#define EXTI_FPR1_FPIF10_Pos (10U) +#define EXTI_FPR1_FPIF10_Msk (0x1UL << EXTI_FPR1_FPIF10_Pos) /*!< 0x00000400 */ +#define EXTI_FPR1_FPIF10 EXTI_FPR1_FPIF10_Msk /*!< Falling Pending Interrupt Flag on line 10 */ +#define EXTI_FPR1_FPIF11_Pos (11U) +#define EXTI_FPR1_FPIF11_Msk (0x1UL << EXTI_FPR1_FPIF11_Pos) /*!< 0x00000800 */ +#define EXTI_FPR1_FPIF11 EXTI_FPR1_FPIF11_Msk /*!< Falling Pending Interrupt Flag on line 11 */ +#define EXTI_FPR1_FPIF12_Pos (12U) +#define EXTI_FPR1_FPIF12_Msk (0x1UL << EXTI_FPR1_FPIF12_Pos) /*!< 0x00001000 */ +#define EXTI_FPR1_FPIF12 EXTI_FPR1_FPIF12_Msk /*!< Falling Pending Interrupt Flag on line 12 */ +#define EXTI_FPR1_FPIF13_Pos (13U) +#define EXTI_FPR1_FPIF13_Msk (0x1UL << EXTI_FPR1_FPIF13_Pos) /*!< 0x00002000 */ +#define EXTI_FPR1_FPIF13 EXTI_FPR1_FPIF13_Msk /*!< Falling Pending Interrupt Flag on line 13 */ +#define EXTI_FPR1_FPIF14_Pos (14U) +#define EXTI_FPR1_FPIF14_Msk (0x1UL << EXTI_FPR1_FPIF14_Pos) /*!< 0x00004000 */ +#define EXTI_FPR1_FPIF14 EXTI_FPR1_FPIF14_Msk /*!< Falling Pending Interrupt Flag on line 14 */ +#define EXTI_FPR1_FPIF15_Pos (15U) +#define EXTI_FPR1_FPIF15_Msk (0x1UL << EXTI_FPR1_FPIF15_Pos) /*!< 0x00008000 */ +#define EXTI_FPR1_FPIF15 EXTI_FPR1_FPIF15_Msk /*!< Falling Pending Interrupt Flag on line 15 */ +#define EXTI_FPR1_FPIF16_Pos (16U) +#define EXTI_FPR1_FPIF16_Msk (0x1UL << EXTI_FPR1_FPIF16_Pos) /*!< 0x00010000 */ +#define EXTI_FPR1_FPIF16 EXTI_FPR1_FPIF16_Msk /*!< Falling Pending Interrupt Flag on line 16 */ +#define EXTI_FPR1_FPIF17_Pos (17U) +#define EXTI_FPR1_FPIF17_Msk (0x1UL << EXTI_FPR1_FPIF17_Pos) /*!< 0x00020000 */ +#define EXTI_FPR1_FPIF17 EXTI_FPR1_FPIF17_Msk /*!< Falling Pending Interrupt Flag on line 17 */ +#define EXTI_FPR1_FPIF18_Pos (18U) +#define EXTI_FPR1_FPIF18_Msk (0x1UL << EXTI_FPR1_FPIF18_Pos) /*!< 0x00040000 */ +#define EXTI_FPR1_FPIF18 EXTI_FPR1_FPIF18_Msk /*!< Falling Pending Interrupt Flag on line 18 */ + +/******************* Bit definition for EXTI_SECCFGR1 register ******************/ +#define EXTI_SECCFGR1_SEC0_Pos (0U) +#define EXTI_SECCFGR1_SEC0_Msk (0x1UL << EXTI_SECCFGR1_SEC0_Pos) /*!< 0x00000001 */ +#define EXTI_SECCFGR1_SEC0 EXTI_SECCFGR1_SEC0_Msk /*!< Security enable on line 0 */ +#define EXTI_SECCFGR1_SEC1_Pos (1U) +#define EXTI_SECCFGR1_SEC1_Msk (0x1UL << EXTI_SECCFGR1_SEC1_Pos) /*!< 0x00000002 */ +#define EXTI_SECCFGR1_SEC1 EXTI_SECCFGR1_SEC1_Msk /*!< Security enable on line 1 */ +#define EXTI_SECCFGR1_SEC2_Pos (2U) +#define EXTI_SECCFGR1_SEC2_Msk (0x1UL << EXTI_SECCFGR1_SEC2_Pos) /*!< 0x00000004 */ +#define EXTI_SECCFGR1_SEC2 EXTI_SECCFGR1_SEC2_Msk /*!< Security enable on line 2 */ +#define EXTI_SECCFGR1_SEC3_Pos (3U) +#define EXTI_SECCFGR1_SEC3_Msk (0x1UL << EXTI_SECCFGR1_SEC3_Pos) /*!< 0x00000008 */ +#define EXTI_SECCFGR1_SEC3 EXTI_SECCFGR1_SEC3_Msk /*!< Security enable on line 3 */ +#define EXTI_SECCFGR1_SEC4_Pos (4U) +#define EXTI_SECCFGR1_SEC4_Msk (0x1UL << EXTI_SECCFGR1_SEC4_Pos) /*!< 0x00000010 */ +#define EXTI_SECCFGR1_SEC4 EXTI_SECCFGR1_SEC4_Msk /*!< Security enable on line 4 */ +#define EXTI_SECCFGR1_SEC5_Pos (5U) +#define EXTI_SECCFGR1_SEC5_Msk (0x1UL << EXTI_SECCFGR1_SEC5_Pos) /*!< 0x00000020 */ +#define EXTI_SECCFGR1_SEC5 EXTI_SECCFGR1_SEC5_Msk /*!< Security enable on line 5 */ +#define EXTI_SECCFGR1_SEC6_Pos (6U) +#define EXTI_SECCFGR1_SEC6_Msk (0x1UL << EXTI_SECCFGR1_SEC6_Pos) /*!< 0x00000040 */ +#define EXTI_SECCFGR1_SEC6 EXTI_SECCFGR1_SEC6_Msk /*!< Security enable on line 6 */ +#define EXTI_SECCFGR1_SEC7_Pos (7U) +#define EXTI_SECCFGR1_SEC7_Msk (0x1UL << EXTI_SECCFGR1_SEC7_Pos) /*!< 0x00000080 */ +#define EXTI_SECCFGR1_SEC7 EXTI_SECCFGR1_SEC7_Msk /*!< Security enable on line 7 */ +#define EXTI_SECCFGR1_SEC8_Pos (8U) +#define EXTI_SECCFGR1_SEC8_Msk (0x1UL << EXTI_SECCFGR1_SEC8_Pos) /*!< 0x00000100 */ +#define EXTI_SECCFGR1_SEC8 EXTI_SECCFGR1_SEC8_Msk /*!< Security enable on line 8 */ +#define EXTI_SECCFGR1_SEC9_Pos (9U) +#define EXTI_SECCFGR1_SEC9_Msk (0x1UL << EXTI_SECCFGR1_SEC9_Pos) /*!< 0x00000200 */ +#define EXTI_SECCFGR1_SEC9 EXTI_SECCFGR1_SEC9_Msk /*!< Security enable on line 9 */ +#define EXTI_SECCFGR1_SEC10_Pos (10U) +#define EXTI_SECCFGR1_SEC10_Msk (0x1UL << EXTI_SECCFGR1_SEC10_Pos) /*!< 0x00000400 */ +#define EXTI_SECCFGR1_SEC10 EXTI_SECCFGR1_SEC10_Msk /*!< Security enable on line 10 */ +#define EXTI_SECCFGR1_SEC11_Pos (11U) +#define EXTI_SECCFGR1_SEC11_Msk (0x1UL << EXTI_SECCFGR1_SEC11_Pos) /*!< 0x00000800 */ +#define EXTI_SECCFGR1_SEC11 EXTI_SECCFGR1_SEC11_Msk /*!< Security enable on line 11 */ +#define EXTI_SECCFGR1_SEC12_Pos (12U) +#define EXTI_SECCFGR1_SEC12_Msk (0x1UL << EXTI_SECCFGR1_SEC12_Pos) /*!< 0x00001000 */ +#define EXTI_SECCFGR1_SEC12 EXTI_SECCFGR1_SEC12_Msk /*!< Security enable on line 12 */ +#define EXTI_SECCFGR1_SEC13_Pos (13U) +#define EXTI_SECCFGR1_SEC13_Msk (0x1UL << EXTI_SECCFGR1_SEC13_Pos) /*!< 0x00002000 */ +#define EXTI_SECCFGR1_SEC13 EXTI_SECCFGR1_SEC13_Msk /*!< Security enable on line 13 */ +#define EXTI_SECCFGR1_SEC14_Pos (14U) +#define EXTI_SECCFGR1_SEC14_Msk (0x1UL << EXTI_SECCFGR1_SEC14_Pos) /*!< 0x00004000 */ +#define EXTI_SECCFGR1_SEC14 EXTI_SECCFGR1_SEC14_Msk /*!< Security enable on line 14 */ +#define EXTI_SECCFGR1_SEC15_Pos (15U) +#define EXTI_SECCFGR1_SEC15_Msk (0x1UL << EXTI_SECCFGR1_SEC15_Pos) /*!< 0x00008000 */ +#define EXTI_SECCFGR1_SEC15 EXTI_SECCFGR1_SEC15_Msk /*!< Security enable on line 15 */ +#define EXTI_SECCFGR1_SEC16_Pos (16U) +#define EXTI_SECCFGR1_SEC16_Msk (0x1UL << EXTI_SECCFGR1_SEC16_Pos) /*!< 0x00010000 */ +#define EXTI_SECCFGR1_SEC16 EXTI_SECCFGR1_SEC16_Msk /*!< Security enable on line 16 */ +#define EXTI_SECCFGR1_SEC17_Pos (17U) +#define EXTI_SECCFGR1_SEC17_Msk (0x1UL << EXTI_SECCFGR1_SEC17_Pos) /*!< 0x00020000 */ +#define EXTI_SECCFGR1_SEC17 EXTI_SECCFGR1_SEC17_Msk /*!< Security enable on line 17 */ +#define EXTI_SECCFGR1_SEC18_Pos (18U) +#define EXTI_SECCFGR1_SEC18_Msk (0x1UL << EXTI_SECCFGR1_SEC18_Pos) /*!< 0x00040000 */ +#define EXTI_SECCFGR1_SEC18 EXTI_SECCFGR1_SEC18_Msk /*!< Security enable on line 18 */ + +/******************* Bit definition for EXTI_PRIVCFGR1 register ******************/ +#define EXTI_PRIVCFGR1_PRIV0_Pos (0U) +#define EXTI_PRIVCFGR1_PRIV0_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV0_Pos) /*!< 0x00000001 */ +#define EXTI_PRIVCFGR1_PRIV0 EXTI_PRIVCFGR1_PRIV0_Msk /*!< Privilege enable on line 0 */ +#define EXTI_PRIVCFGR1_PRIV1_Pos (1U) +#define EXTI_PRIVCFGR1_PRIV1_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV1_Pos) /*!< 0x00000002 */ +#define EXTI_PRIVCFGR1_PRIV1 EXTI_PRIVCFGR1_PRIV1_Msk /*!< Privilege enable on line 1 */ +#define EXTI_PRIVCFGR1_PRIV2_Pos (2U) +#define EXTI_PRIVCFGR1_PRIV2_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV2_Pos) /*!< 0x00000004 */ +#define EXTI_PRIVCFGR1_PRIV2 EXTI_PRIVCFGR1_PRIV2_Msk /*!< Privilege enable on line 2 */ +#define EXTI_PRIVCFGR1_PRIV3_Pos (3U) +#define EXTI_PRIVCFGR1_PRIV3_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV3_Pos) /*!< 0x00000008 */ +#define EXTI_PRIVCFGR1_PRIV3 EXTI_PRIVCFGR1_PRIV3_Msk /*!< Privilege enable on line 3 */ +#define EXTI_PRIVCFGR1_PRIV4_Pos (4U) +#define EXTI_PRIVCFGR1_PRIV4_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV4_Pos) /*!< 0x00000010 */ +#define EXTI_PRIVCFGR1_PRIV4 EXTI_PRIVCFGR1_PRIV4_Msk /*!< Privilege enable on line 4 */ +#define EXTI_PRIVCFGR1_PRIV5_Pos (5U) +#define EXTI_PRIVCFGR1_PRIV5_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV5_Pos) /*!< 0x00000020 */ +#define EXTI_PRIVCFGR1_PRIV5 EXTI_PRIVCFGR1_PRIV5_Msk /*!< Privilege enable on line 5 */ +#define EXTI_PRIVCFGR1_PRIV6_Pos (6U) +#define EXTI_PRIVCFGR1_PRIV6_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV6_Pos) /*!< 0x00000040 */ +#define EXTI_PRIVCFGR1_PRIV6 EXTI_PRIVCFGR1_PRIV6_Msk /*!< Privilege enable on line 6 */ +#define EXTI_PRIVCFGR1_PRIV7_Pos (7U) +#define EXTI_PRIVCFGR1_PRIV7_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV7_Pos) /*!< 0x00000080 */ +#define EXTI_PRIVCFGR1_PRIV7 EXTI_PRIVCFGR1_PRIV7_Msk /*!< Privilege enable on line 7 */ +#define EXTI_PRIVCFGR1_PRIV8_Pos (8U) +#define EXTI_PRIVCFGR1_PRIV8_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV8_Pos) /*!< 0x00000100 */ +#define EXTI_PRIVCFGR1_PRIV8 EXTI_PRIVCFGR1_PRIV8_Msk /*!< Privilege enable on line 8 */ +#define EXTI_PRIVCFGR1_PRIV9_Pos (9U) +#define EXTI_PRIVCFGR1_PRIV9_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV9_Pos) /*!< 0x00000200 */ +#define EXTI_PRIVCFGR1_PRIV9 EXTI_PRIVCFGR1_PRIV9_Msk /*!< Privilege enable on line 9 */ +#define EXTI_PRIVCFGR1_PRIV10_Pos (10U) +#define EXTI_PRIVCFGR1_PRIV10_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV10_Pos) /*!< 0x00000400 */ +#define EXTI_PRIVCFGR1_PRIV10 EXTI_PRIVCFGR1_PRIV10_Msk /*!< Privilege enable on line 10 */ +#define EXTI_PRIVCFGR1_PRIV11_Pos (11U) +#define EXTI_PRIVCFGR1_PRIV11_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV11_Pos) /*!< 0x00000800 */ +#define EXTI_PRIVCFGR1_PRIV11 EXTI_PRIVCFGR1_PRIV11_Msk /*!< Privilege enable on line 11 */ +#define EXTI_PRIVCFGR1_PRIV12_Pos (12U) +#define EXTI_PRIVCFGR1_PRIV12_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV12_Pos) /*!< 0x00001000 */ +#define EXTI_PRIVCFGR1_PRIV12 EXTI_PRIVCFGR1_PRIV12_Msk /*!< Privilege enable on line 12 */ +#define EXTI_PRIVCFGR1_PRIV13_Pos (13U) +#define EXTI_PRIVCFGR1_PRIV13_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV13_Pos) /*!< 0x00002000 */ +#define EXTI_PRIVCFGR1_PRIV13 EXTI_PRIVCFGR1_PRIV13_Msk /*!< Privilege enable on line 13 */ +#define EXTI_PRIVCFGR1_PRIV14_Pos (14U) +#define EXTI_PRIVCFGR1_PRIV14_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV14_Pos) /*!< 0x00004000 */ +#define EXTI_PRIVCFGR1_PRIV14 EXTI_PRIVCFGR1_PRIV14_Msk /*!< Privilege enable on line 14 */ +#define EXTI_PRIVCFGR1_PRIV15_Pos (15U) +#define EXTI_PRIVCFGR1_PRIV15_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV15_Pos) /*!< 0x00008000 */ +#define EXTI_PRIVCFGR1_PRIV15 EXTI_PRIVCFGR1_PRIV15_Msk /*!< Privilege enable on line 15 */ +#define EXTI_PRIVCFGR1_PRIV16_Pos (16U) +#define EXTI_PRIVCFGR1_PRIV16_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV16_Pos) /*!< 0x00010000 */ +#define EXTI_PRIVCFGR1_PRIV16 EXTI_PRIVCFGR1_PRIV16_Msk /*!< Privilege enable on line 16 */ +#define EXTI_PRIVCFGR1_PRIV17_Pos (17U) +#define EXTI_PRIVCFGR1_PRIV17_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV17_Pos) /*!< 0x00020000 */ +#define EXTI_PRIVCFGR1_PRIV17 EXTI_PRIVCFGR1_PRIV17_Msk /*!< Privilege enable on line 17 */ +#define EXTI_PRIVCFGR1_PRIV18_Pos (18U) +#define EXTI_PRIVCFGR1_PRIV18_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV18_Pos) /*!< 0x00040000 */ +#define EXTI_PRIVCFGR1_PRIV18 EXTI_PRIVCFGR1_PRIV18_Msk /*!< Privilege enable on line 18 */ + +/***************** Bit definition for EXTI_EXTICR1 register **************/ +#define EXTI_EXTICR1_EXTI0_Pos (0U) +#define EXTI_EXTICR1_EXTI0_Msk (0xFFUL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x000000FF */ +#define EXTI_EXTICR1_EXTI0 EXTI_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */ +#define EXTI_EXTICR1_EXTI0_0 (0x1UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR1_EXTI0_1 (0x2UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR1_EXTI0_2 (0x4UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR1_EXTI0_3 (0x8UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000008 */ +#define EXTI_EXTICR1_EXTI0_4 (0x10UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000010 */ +#define EXTI_EXTICR1_EXTI0_5 (0x20UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000020 */ +#define EXTI_EXTICR1_EXTI0_6 (0x40UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000040 */ +#define EXTI_EXTICR1_EXTI0_7 (0x80UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000080 */ +#define EXTI_EXTICR1_EXTI1_Pos (8U) +#define EXTI_EXTICR1_EXTI1_Msk (0xFFUL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x0000FF00 */ +#define EXTI_EXTICR1_EXTI1 EXTI_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */ +#define EXTI_EXTICR1_EXTI1_0 (0x1UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR1_EXTI1_1 (0x2UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR1_EXTI1_2 (0x4UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR1_EXTI1_3 (0x8UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000800 */ +#define EXTI_EXTICR1_EXTI1_4 (0x10UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00001000 */ +#define EXTI_EXTICR1_EXTI1_5 (0x20UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00002000 */ +#define EXTI_EXTICR1_EXTI1_6 (0x40UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00004000 */ +#define EXTI_EXTICR1_EXTI1_7 (0x80UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00008000 */ +#define EXTI_EXTICR1_EXTI2_Pos (16U) +#define EXTI_EXTICR1_EXTI2_Msk (0xFFUL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00FF0000 */ +#define EXTI_EXTICR1_EXTI2 EXTI_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */ +#define EXTI_EXTICR1_EXTI2_0 (0x1UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR1_EXTI2_1 (0x2UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR1_EXTI2_2 (0x4UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR1_EXTI2_3 (0x8UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00080000 */ +#define EXTI_EXTICR1_EXTI2_4 (0x10UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00100000 */ +#define EXTI_EXTICR1_EXTI2_5 (0x20UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00200000 */ +#define EXTI_EXTICR1_EXTI2_6 (0x40UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00400000 */ +#define EXTI_EXTICR1_EXTI2_7 (0x80UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00800000 */ +#define EXTI_EXTICR1_EXTI3_Pos (24U) +#define EXTI_EXTICR1_EXTI3_Msk (0xFFUL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0xFF000000 */ +#define EXTI_EXTICR1_EXTI3 EXTI_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */ +#define EXTI_EXTICR1_EXTI3_0 (0x1UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR1_EXTI3_1 (0x2UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR1_EXTI3_2 (0x4UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x04000000 */ +#define EXTI_EXTICR1_EXTI3_3 (0x8UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x08000000 */ +#define EXTI_EXTICR1_EXTI3_4 (0x10UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x10000000 */ +#define EXTI_EXTICR1_EXTI3_5 (0x20UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x20000000 */ +#define EXTI_EXTICR1_EXTI3_6 (0x40UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x40000000 */ +#define EXTI_EXTICR1_EXTI3_7 (0x80UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for EXTI_EXTICR2 register **************/ +#define EXTI_EXTICR2_EXTI4_Pos (0U) +#define EXTI_EXTICR2_EXTI4_Msk (0xFFUL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x000000FF */ +#define EXTI_EXTICR2_EXTI4 EXTI_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */ +#define EXTI_EXTICR2_EXTI4_0 (0x1UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR2_EXTI4_1 (0x2UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR2_EXTI4_2 (0x4UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR2_EXTI4_3 (0x8UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000008 */ +#define EXTI_EXTICR2_EXTI4_4 (0x10UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000010 */ +#define EXTI_EXTICR2_EXTI4_5 (0x20UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000020 */ +#define EXTI_EXTICR2_EXTI4_6 (0x40UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000040 */ +#define EXTI_EXTICR2_EXTI4_7 (0x80UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000080 */ +#define EXTI_EXTICR2_EXTI5_Pos (8U) +#define EXTI_EXTICR2_EXTI5_Msk (0xFFUL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x0000FF00 */ +#define EXTI_EXTICR2_EXTI5 EXTI_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */ +#define EXTI_EXTICR2_EXTI5_0 (0x1UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR2_EXTI5_1 (0x2UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR2_EXTI5_2 (0x4UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR2_EXTI5_3 (0x8UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000800 */ +#define EXTI_EXTICR2_EXTI5_4 (0x10UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00001000 */ +#define EXTI_EXTICR2_EXTI5_5 (0x20UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00002000 */ +#define EXTI_EXTICR2_EXTI5_6 (0x40UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00004000 */ +#define EXTI_EXTICR2_EXTI5_7 (0x80UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00008000 */ +#define EXTI_EXTICR2_EXTI6_Pos (16U) +#define EXTI_EXTICR2_EXTI6_Msk (0xFFUL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00FF0000 */ +#define EXTI_EXTICR2_EXTI6 EXTI_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */ +#define EXTI_EXTICR2_EXTI6_0 (0x1UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR2_EXTI6_1 (0x2UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR2_EXTI6_2 (0x4UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR2_EXTI6_3 (0x8UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00080000 */ +#define EXTI_EXTICR2_EXTI6_4 (0x10UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00100000 */ +#define EXTI_EXTICR2_EXTI6_5 (0x20UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00200000 */ +#define EXTI_EXTICR2_EXTI6_6 (0x40UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00400000 */ +#define EXTI_EXTICR2_EXTI6_7 (0x80UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00800000 */ +#define EXTI_EXTICR2_EXTI7_Pos (24U) +#define EXTI_EXTICR2_EXTI7_Msk (0xFFUL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0xFF000000 */ +#define EXTI_EXTICR2_EXTI7 EXTI_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */ +#define EXTI_EXTICR2_EXTI7_0 (0x1UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR2_EXTI7_1 (0x2UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR2_EXTI7_2 (0x4UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x04000000 */ +#define EXTI_EXTICR2_EXTI7_3 (0x8UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x08000000 */ +#define EXTI_EXTICR2_EXTI7_4 (0x10UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x10000000 */ +#define EXTI_EXTICR2_EXTI7_5 (0x20UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x20000000 */ +#define EXTI_EXTICR2_EXTI7_6 (0x40UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x40000000 */ +#define EXTI_EXTICR2_EXTI7_7 (0x80UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for EXTI_EXTICR3 register **************/ +#define EXTI_EXTICR3_EXTI8_Pos (0U) +#define EXTI_EXTICR3_EXTI8_Msk (0xFFUL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x000000FF */ +#define EXTI_EXTICR3_EXTI8 EXTI_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */ +#define EXTI_EXTICR3_EXTI8_0 (0x1UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR3_EXTI8_1 (0x2UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR3_EXTI8_2 (0x4UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR3_EXTI8_3 (0x8UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000008 */ +#define EXTI_EXTICR3_EXTI8_4 (0x10UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000010 */ +#define EXTI_EXTICR3_EXTI8_5 (0x20UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000020 */ +#define EXTI_EXTICR3_EXTI8_6 (0x40UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000040 */ +#define EXTI_EXTICR3_EXTI8_7 (0x80UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000080 */ +#define EXTI_EXTICR3_EXTI9_Pos (8U) +#define EXTI_EXTICR3_EXTI9_Msk (0xFFUL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x0000FF00 */ +#define EXTI_EXTICR3_EXTI9 EXTI_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */ +#define EXTI_EXTICR3_EXTI9_0 (0x1UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR3_EXTI9_1 (0x2UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR3_EXTI9_2 (0x4UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR3_EXTI9_3 (0x8UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000800 */ +#define EXTI_EXTICR3_EXTI9_4 (0x10UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00001000 */ +#define EXTI_EXTICR3_EXTI9_5 (0x20UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00002000 */ +#define EXTI_EXTICR3_EXTI9_6 (0x40UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00004000 */ +#define EXTI_EXTICR3_EXTI9_7 (0x80UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00008000 */ +#define EXTI_EXTICR3_EXTI10_Pos (16U) +#define EXTI_EXTICR3_EXTI10_Msk (0xFFUL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00FF0000 */ +#define EXTI_EXTICR3_EXTI10 EXTI_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */ +#define EXTI_EXTICR3_EXTI10_0 (0x1UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR3_EXTI10_1 (0x2UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR3_EXTI10_2 (0x4UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR3_EXTI10_3 (0x8UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00080000 */ +#define EXTI_EXTICR3_EXTI10_4 (0x10UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00100000 */ +#define EXTI_EXTICR3_EXTI10_5 (0x20UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00200000 */ +#define EXTI_EXTICR3_EXTI10_6 (0x40UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00400000 */ +#define EXTI_EXTICR3_EXTI10_7 (0x80UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00800000 */ +#define EXTI_EXTICR3_EXTI11_Pos (24U) +#define EXTI_EXTICR3_EXTI11_Msk (0xFFUL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0xFF000000 */ +#define EXTI_EXTICR3_EXTI11 EXTI_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */ +#define EXTI_EXTICR3_EXTI11_0 (0x1UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR3_EXTI11_1 (0x2UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR3_EXTI11_2 (0x4UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x04000000 */ +#define EXTI_EXTICR3_EXTI11_3 (0x8UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x08000000 */ +#define EXTI_EXTICR3_EXTI11_4 (0x10UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x10000000 */ +#define EXTI_EXTICR3_EXTI11_5 (0x20UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x20000000 */ +#define EXTI_EXTICR3_EXTI11_6 (0x40UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x40000000 */ +#define EXTI_EXTICR3_EXTI11_7 (0x80UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for EXTI_EXTICR4 register **************/ +#define EXTI_EXTICR4_EXTI12_Pos (0U) +#define EXTI_EXTICR4_EXTI12_Msk (0xFFUL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x000000FF */ +#define EXTI_EXTICR4_EXTI12 EXTI_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */ +#define EXTI_EXTICR4_EXTI12_0 (0x1UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR4_EXTI12_1 (0x2UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR4_EXTI12_2 (0x4UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR4_EXTI12_3 (0x8UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000008 */ +#define EXTI_EXTICR4_EXTI12_4 (0x10UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000010 */ +#define EXTI_EXTICR4_EXTI12_5 (0x20UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000020 */ +#define EXTI_EXTICR4_EXTI12_6 (0x40UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000040 */ +#define EXTI_EXTICR4_EXTI12_7 (0x80UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000080 */ +#define EXTI_EXTICR4_EXTI13_Pos (8U) +#define EXTI_EXTICR4_EXTI13_Msk (0xFFUL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x0000FF00 */ +#define EXTI_EXTICR4_EXTI13 EXTI_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */ +#define EXTI_EXTICR4_EXTI13_0 (0x1UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR4_EXTI13_1 (0x2UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR4_EXTI13_2 (0x4UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR4_EXTI13_3 (0x8UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000800 */ +#define EXTI_EXTICR4_EXTI13_4 (0x10UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00001000 */ +#define EXTI_EXTICR4_EXTI13_5 (0x20UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00002000 */ +#define EXTI_EXTICR4_EXTI13_6 (0x40UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00004000 */ +#define EXTI_EXTICR4_EXTI13_7 (0x80UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00008000 */ +#define EXTI_EXTICR4_EXTI14_Pos (16U) +#define EXTI_EXTICR4_EXTI14_Msk (0xFFUL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00FF0000 */ +#define EXTI_EXTICR4_EXTI14 EXTI_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */ +#define EXTI_EXTICR4_EXTI14_0 (0x1UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR4_EXTI14_1 (0x2UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR4_EXTI14_2 (0x4UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR4_EXTI14_3 (0x8UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00080000 */ +#define EXTI_EXTICR4_EXTI14_4 (0x10UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00100000 */ +#define EXTI_EXTICR4_EXTI14_5 (0x20UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00200000 */ +#define EXTI_EXTICR4_EXTI14_6 (0x40UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00400000 */ +#define EXTI_EXTICR4_EXTI14_7 (0x80UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00800000 */ +#define EXTI_EXTICR4_EXTI15_Pos (24U) +#define EXTI_EXTICR4_EXTI15_Msk (0xFFUL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0xFF000000 */ +#define EXTI_EXTICR4_EXTI15 EXTI_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */ +#define EXTI_EXTICR4_EXTI15_0 (0x1UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR4_EXTI15_1 (0x2UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR4_EXTI15_2 (0x4UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x04000000 */ +#define EXTI_EXTICR4_EXTI15_3 (0x8UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x08000000 */ +#define EXTI_EXTICR4_EXTI15_4 (0x10UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x10000000 */ +#define EXTI_EXTICR4_EXTI15_5 (0x20UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x20000000 */ +#define EXTI_EXTICR4_EXTI15_6 (0x40UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x40000000 */ +#define EXTI_EXTICR4_EXTI15_7 (0x80UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x80000000 */ + +/******************* Bit definition for EXTI_LOCKR register ******************/ +#define EXTI_LOCKR_LOCK_Pos (0U) +#define EXTI_LOCKR_LOCK_Msk (0x1UL << EXTI_LOCKR_LOCK_Pos) /*!< 0x00000001 */ +#define EXTI_LOCKR_LOCK EXTI_LOCKR_LOCK_Msk /*!< Security and privilege configuration lock */ + +/******************* Bit definition for EXTI_IMR1 register ******************/ +#define EXTI_IMR1_IM0_Pos (0U) +#define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */ +#define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< Interrupt Mask on line 0 */ +#define EXTI_IMR1_IM1_Pos (1U) +#define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */ +#define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< Interrupt Mask on line 1 */ +#define EXTI_IMR1_IM2_Pos (2U) +#define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */ +#define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< Interrupt Mask on line 2 */ +#define EXTI_IMR1_IM3_Pos (3U) +#define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */ +#define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< Interrupt Mask on line 3 */ +#define EXTI_IMR1_IM4_Pos (4U) +#define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */ +#define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< Interrupt Mask on line 4 */ +#define EXTI_IMR1_IM5_Pos (5U) +#define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */ +#define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< Interrupt Mask on line 5 */ +#define EXTI_IMR1_IM6_Pos (6U) +#define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */ +#define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< Interrupt Mask on line 6 */ +#define EXTI_IMR1_IM7_Pos (7U) +#define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */ +#define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< Interrupt Mask on line 7 */ +#define EXTI_IMR1_IM8_Pos (8U) +#define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */ +#define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< Interrupt Mask on line 8 */ +#define EXTI_IMR1_IM9_Pos (9U) +#define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */ +#define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< Interrupt Mask on line 9 */ +#define EXTI_IMR1_IM10_Pos (10U) +#define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */ +#define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< Interrupt Mask on line 10 */ +#define EXTI_IMR1_IM11_Pos (11U) +#define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */ +#define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< Interrupt Mask on line 11 */ +#define EXTI_IMR1_IM12_Pos (12U) +#define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */ +#define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< Interrupt Mask on line 12 */ +#define EXTI_IMR1_IM13_Pos (13U) +#define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */ +#define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< Interrupt Mask on line 13 */ +#define EXTI_IMR1_IM14_Pos (14U) +#define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */ +#define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< Interrupt Mask on line 14 */ +#define EXTI_IMR1_IM15_Pos (15U) +#define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */ +#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< Interrupt Mask on line 15 */ +#define EXTI_IMR1_IM16_Pos (16U) +#define EXTI_IMR1_IM16_Msk (0x1UL << EXTI_IMR1_IM16_Pos) /*!< 0x00010000 */ +#define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk /*!< Interrupt Mask on line 16 */ +#define EXTI_IMR1_IM17_Pos (17U) +#define EXTI_IMR1_IM17_Msk (0x1UL << EXTI_IMR1_IM17_Pos) /*!< 0x00020000 */ +#define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk /*!< Interrupt Mask on line 17 */ +#define EXTI_IMR1_IM18_Pos (18U) +#define EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */ +#define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< Interrupt Mask on line 18 */ + +/******************* Bit definition for EXTI_EMR1 register ******************/ +#define EXTI_EMR1_EM0_Pos (0U) +#define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */ +#define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< Event Mask on line 0 */ +#define EXTI_EMR1_EM1_Pos (1U) +#define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */ +#define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< Event Mask on line 1 */ +#define EXTI_EMR1_EM2_Pos (2U) +#define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */ +#define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< Event Mask on line 2 */ +#define EXTI_EMR1_EM3_Pos (3U) +#define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */ +#define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< Event Mask on line 3 */ +#define EXTI_EMR1_EM4_Pos (4U) +#define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */ +#define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< Event Mask on line 4 */ +#define EXTI_EMR1_EM5_Pos (5U) +#define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */ +#define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< Event Mask on line 5 */ +#define EXTI_EMR1_EM6_Pos (6U) +#define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */ +#define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< Event Mask on line 6 */ +#define EXTI_EMR1_EM7_Pos (7U) +#define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */ +#define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< Event Mask on line 7 */ +#define EXTI_EMR1_EM8_Pos (8U) +#define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */ +#define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< Event Mask on line 8 */ +#define EXTI_EMR1_EM9_Pos (9U) +#define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */ +#define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< Event Mask on line 9 */ +#define EXTI_EMR1_EM10_Pos (10U) +#define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */ +#define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< Event Mask on line 10 */ +#define EXTI_EMR1_EM11_Pos (11U) +#define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */ +#define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< Event Mask on line 11 */ +#define EXTI_EMR1_EM12_Pos (12U) +#define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */ +#define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< Event Mask on line 12 */ +#define EXTI_EMR1_EM13_Pos (13U) +#define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */ +#define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< Event Mask on line 13 */ +#define EXTI_EMR1_EM14_Pos (14U) +#define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */ +#define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< Event Mask on line 14 */ +#define EXTI_EMR1_EM15_Pos (15U) +#define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */ +#define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< Event Mask on line 15 */ +#define EXTI_EMR1_EM16_Pos (16U) +#define EXTI_EMR1_EM16_Msk (0x1UL << EXTI_EMR1_EM16_Pos) /*!< 0x00010000 */ +#define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk /*!< Event Mask on line 16 */ +#define EXTI_EMR1_EM17_Pos (17U) +#define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */ +#define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< Event Mask on line 17 */ +#define EXTI_EMR1_EM18_Pos (18U) +#define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */ +#define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< Event Mask on line 18 */ + + +/******************************************************************************/ +/* */ +/* FLASH */ +/* */ +/******************************************************************************/ +#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_0 /* FLASH Latency 1 Wait State */ + +/******************* Bits definition for FLASH_ACR register *****************/ +#define FLASH_ACR_LATENCY_Pos (0U) +#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */ +#define FLASH_ACR_LATENCY_0 (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */ +#define FLASH_ACR_LATENCY_1 (0x2UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */ +#define FLASH_ACR_LATENCY_2 (0x4UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000004 */ +#define FLASH_ACR_LATENCY_3 (0x8UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000008 */ +#define FLASH_ACR_PRFTEN_Pos (8U) +#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ +#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch enable */ +#define FLASH_ACR_LPM_Pos (11U) +#define FLASH_ACR_LPM_Msk (0x1UL << FLASH_ACR_LPM_Pos) /*!< 0x00000800 */ +#define FLASH_ACR_LPM FLASH_ACR_LPM_Msk /*!< Low-Power read mode */ +#define FLASH_ACR_PDREQ_Pos (12U) +#define FLASH_ACR_PDREQ_Msk (0x1UL << FLASH_ACR_PDREQ_Pos) /*!< 0x00001000 */ +#define FLASH_ACR_PDREQ FLASH_ACR_PDREQ_Msk /*!< Flash power-down mode request */ +#define FLASH_ACR_SLEEP_PD_Pos (14U) +#define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00004000 */ +#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash power-down mode during sleep */ + +/****************** Bits definition for FLASH_NSKEYR register *****************/ +#define FLASH_NSKEYR_NSKEY_Pos (0U) +#define FLASH_NSKEYR_NSKEY_Msk (0xFFFFFFFFUL << FLASH_NSKEYR_NSKEY_Pos) /*!< 0xFFFFFFFFF */ +#define FLASH_NSKEYR_NSKEY FLASH_NSKEYR_NSKEY_Msk /*!< Flash memory non-secure key */ + +/****************** Bits definition for FLASH_SECKEYR register *****************/ +#define FLASH_SECKEYR_SECKEY_Pos (0U) +#define FLASH_SECKEYR_SECKEY_Msk (0xFFFFFFFFUL << FLASH_SECKEYR_SECKEY_Pos) /*!< 0xFFFFFFFFF */ +#define FLASH_SECKEYR_SECKEY FLASH_SECKEYR_SECKEY_Msk /*!< Flash memory secure key */ + +/****************** Bits definition for FLASH_OPTKEYR register *****************/ +#define FLASH_OPTKEYR_OPTKEY_Pos (0U) +#define FLASH_OPTKEYR_OPTKEY_Msk (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEY_Pos) /*!< 0xFFFFFFFFF */ +#define FLASH_OPTKEYR_OPTKEY FLASH_OPTKEYR_OPTKEY_Msk /*!< Option byte key */ + +/****************** Bits definition for FLASH_PDKEYR register *****************/ +#define FLASH_PDKEYR_PDKEY_Pos (0U) +#define FLASH_PDKEYR_PDKEY_Msk (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEY_Pos) /*!< 0xFFFFFFFFF */ +#define FLASH_PDKEYR_PDKEY FLASH_PDKEYR_PDKEY_Msk /*!< Flash power-down key */ + +/****************** Bits definition for FLASH_NSSR register *****************/ +#define FLASH_NSSR_EOP_Pos (0U) +#define FLASH_NSSR_EOP_Msk (0x1UL << FLASH_NSSR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_NSSR_EOP FLASH_NSSR_EOP_Msk /*!< Non-secure end of operation */ +#define FLASH_NSSR_OPERR_Pos (1U) +#define FLASH_NSSR_OPERR_Msk (0x1UL << FLASH_NSSR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_NSSR_OPERR FLASH_NSSR_OPERR_Msk /*!< Non-secure operation error */ +#define FLASH_NSSR_PROGERR_Pos (3U) +#define FLASH_NSSR_PROGERR_Msk (0x1UL << FLASH_NSSR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_NSSR_PROGERR FLASH_NSSR_PROGERR_Msk /*!< Non-secure programming error */ +#define FLASH_NSSR_WRPERR_Pos (4U) +#define FLASH_NSSR_WRPERR_Msk (0x1UL << FLASH_NSSR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_NSSR_WRPERR FLASH_NSSR_WRPERR_Msk /*!< Non-secure write protection error */ +#define FLASH_NSSR_PGAERR_Pos (5U) +#define FLASH_NSSR_PGAERR_Msk (0x1UL << FLASH_NSSR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_NSSR_PGAERR FLASH_NSSR_PGAERR_Msk /*!< Non-secure programming alignment error */ +#define FLASH_NSSR_SIZERR_Pos (6U) +#define FLASH_NSSR_SIZERR_Msk (0x1UL << FLASH_NSSR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_NSSR_SIZERR FLASH_NSSR_SIZERR_Msk /*!< Non-secure size error */ +#define FLASH_NSSR_PGSERR_Pos (7U) +#define FLASH_NSSR_PGSERR_Msk (0x1UL << FLASH_NSSR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_NSSR_PGSERR FLASH_NSSR_PGSERR_Msk /*!< Non-secure programming sequence error */ +#define FLASH_NSSR_OPTWERR_Pos (13U) +#define FLASH_NSSR_OPTWERR_Msk (0x1UL << FLASH_NSSR_OPTWERR_Pos) /*!< 0x00002000 */ +#define FLASH_NSSR_OPTWERR FLASH_NSSR_OPTWERR_Msk /*!< Option write error */ +#define FLASH_NSSR_BSY_Pos (16U) +#define FLASH_NSSR_BSY_Msk (0x1UL << FLASH_NSSR_BSY_Pos) /*!< 0x00010000 */ +#define FLASH_NSSR_BSY FLASH_NSSR_BSY_Msk /*!< Non-secure busy */ +#define FLASH_NSSR_WDW_Pos (17U) +#define FLASH_NSSR_WDW_Msk (0x1UL << FLASH_NSSR_WDW_Pos) /*!< 0x00020000 */ +#define FLASH_NSSR_WDW FLASH_NSSR_WDW_Msk /*!< Non-secure wait data to write */ +#define FLASH_NSSR_OEM1LOCK_Pos (18U) +#define FLASH_NSSR_OEM1LOCK_Msk (0x1UL << FLASH_NSSR_OEM1LOCK_Pos) /*!< 0x00040000 */ +#define FLASH_NSSR_OEM1LOCK FLASH_NSSR_OEM1LOCK_Msk /*!< OEM1 lock */ +#define FLASH_NSSR_OEM2LOCK_Pos (19U) +#define FLASH_NSSR_OEM2LOCK_Msk (0x1UL << FLASH_NSSR_OEM2LOCK_Pos) /*!< 0x00080000 */ +#define FLASH_NSSR_OEM2LOCK FLASH_NSSR_OEM2LOCK_Msk /*!< OEM2 lock */ +#define FLASH_NSSR_PD_Pos (20U) +#define FLASH_NSSR_PD_Msk (0x1UL << FLASH_NSSR_PD_Pos) /*!< 0x00100000 */ +#define FLASH_NSSR_PD FLASH_NSSR_PD_Msk /*!< Flash in power-down mode */ + +/****************** Bits definition for FLASH_SECSR register ****************/ +#define FLASH_SECSR_EOP_Pos (0U) +#define FLASH_SECSR_EOP_Msk (0x1UL << FLASH_SECSR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_SECSR_EOP FLASH_SECSR_EOP_Msk /*!< Secure end of operation */ +#define FLASH_SECSR_OPERR_Pos (1U) +#define FLASH_SECSR_OPERR_Msk (0x1UL << FLASH_SECSR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_SECSR_OPERR FLASH_SECSR_OPERR_Msk /*!< Secure operation error */ +#define FLASH_SECSR_PROGERR_Pos (3U) +#define FLASH_SECSR_PROGERR_Msk (0x1UL << FLASH_SECSR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_SECSR_PROGERR FLASH_SECSR_PROGERR_Msk /*!< Secure programming error */ +#define FLASH_SECSR_WRPERR_Pos (4U) +#define FLASH_SECSR_WRPERR_Msk (0x1UL << FLASH_SECSR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_SECSR_WRPERR FLASH_SECSR_WRPERR_Msk /*!< Secure write protection error */ +#define FLASH_SECSR_PGAERR_Pos (5U) +#define FLASH_SECSR_PGAERR_Msk (0x1UL << FLASH_SECSR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_SECSR_PGAERR FLASH_SECSR_PGAERR_Msk /*!< Secure programming alignment error */ +#define FLASH_SECSR_SIZERR_Pos (6U) +#define FLASH_SECSR_SIZERR_Msk (0x1UL << FLASH_SECSR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_SECSR_SIZERR FLASH_SECSR_SIZERR_Msk /*!< Secure size error */ +#define FLASH_SECSR_PGSERR_Pos (7U) +#define FLASH_SECSR_PGSERR_Msk (0x1UL << FLASH_SECSR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_SECSR_PGSERR FLASH_SECSR_PGSERR_Msk /*!< Secure programming sequence error */ +#define FLASH_SECSR_BSY_Pos (16U) +#define FLASH_SECSR_BSY_Msk (0x1UL << FLASH_SECSR_BSY_Pos) /*!< 0x00010000 */ +#define FLASH_SECSR_BSY FLASH_SECSR_BSY_Msk /*!< Secure busy */ +#define FLASH_SECSR_WDW_Pos (17U) +#define FLASH_SECSR_WDW_Msk (0x1UL << FLASH_SECSR_WDW_Pos) /*!< 0x00020000 */ +#define FLASH_SECSR_WDW FLASH_SECSR_WDW_Msk /*!< Secure wait data to write */ + +/****************** Bits definition for FLASH_NSCR1 register *****************/ +#define FLASH_NSCR1_PG_Pos (0U) +#define FLASH_NSCR1_PG_Msk (0x1UL << FLASH_NSCR1_PG_Pos) /*!< 0x00000001 */ +#define FLASH_NSCR1_PG FLASH_NSCR1_PG_Msk /*!< Non-secure Programming */ +#define FLASH_NSCR1_PER_Pos (1U) +#define FLASH_NSCR1_PER_Msk (0x1UL << FLASH_NSCR1_PER_Pos) /*!< 0x00000002 */ +#define FLASH_NSCR1_PER FLASH_NSCR1_PER_Msk /*!< Non-secure Page Erase */ +#define FLASH_NSCR1_MER_Pos (2U) +#define FLASH_NSCR1_MER_Msk (0x1UL << FLASH_NSCR1_MER_Pos) /*!< 0x00000004 */ +#define FLASH_NSCR1_MER FLASH_NSCR1_MER_Msk /*!< Non-secure Mass Erase */ +#define FLASH_NSCR1_PNB_Pos (3U) +#define FLASH_NSCR1_PNB_Msk (0x7FUL << FLASH_NSCR1_PNB_Pos) /*!< 0x000003F8 */ +#define FLASH_NSCR1_PNB FLASH_NSCR1_PNB_Msk /*!< Non-secure Page Number selection */ +#define FLASH_NSCR1_BWR_Pos (14U) +#define FLASH_NSCR1_BWR_Msk (0x1UL << FLASH_NSCR1_BWR_Pos) /*!< 0x00004000 */ +#define FLASH_NSCR1_BWR FLASH_NSCR1_BWR_Msk /*!< Non-secure Burst Write Programming mode */ +#define FLASH_NSCR1_STRT_Pos (16U) +#define FLASH_NSCR1_STRT_Msk (0x1UL << FLASH_NSCR1_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_NSCR1_STRT FLASH_NSCR1_STRT_Msk /*!< Non-secure Start */ +#define FLASH_NSCR1_OPTSTRT_Pos (17U) +#define FLASH_NSCR1_OPTSTRT_Msk (0x1UL << FLASH_NSCR1_OPTSTRT_Pos) /*!< 0x00020000 */ +#define FLASH_NSCR1_OPTSTRT FLASH_NSCR1_OPTSTRT_Msk /*!< Option Modification Start */ +#define FLASH_NSCR1_EOPIE_Pos (24U) +#define FLASH_NSCR1_EOPIE_Msk (0x1UL << FLASH_NSCR1_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_NSCR1_EOPIE FLASH_NSCR1_EOPIE_Msk /*!< Non-secure End of operation interrupt enable */ +#define FLASH_NSCR1_ERRIE_Pos (25U) +#define FLASH_NSCR1_ERRIE_Msk (0x1UL << FLASH_NSCR1_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_NSCR1_ERRIE FLASH_NSCR1_ERRIE_Msk /*!< Non-secure error interrupt enable */ +#define FLASH_NSCR1_OBL_LAUNCH_Pos (27U) +#define FLASH_NSCR1_OBL_LAUNCH_Msk (0x1UL << FLASH_NSCR1_OBL_LAUNCH_Pos) /*!< 0x08000000 */ +#define FLASH_NSCR1_OBL_LAUNCH FLASH_NSCR1_OBL_LAUNCH_Msk /*!< Force the option byte loading */ +#define FLASH_NSCR1_OPTLOCK_Pos (30U) +#define FLASH_NSCR1_OPTLOCK_Msk (0x1UL << FLASH_NSCR1_OPTLOCK_Pos) /*!< 0x40000000 */ +#define FLASH_NSCR1_OPTLOCK FLASH_NSCR1_OPTLOCK_Msk /*!< Option Lock */ +#define FLASH_NSCR1_LOCK_Pos (31U) +#define FLASH_NSCR1_LOCK_Msk (0x1UL << FLASH_NSCR1_LOCK_Pos) /*!< 0x80000000 */ +#define FLASH_NSCR1_LOCK FLASH_NSCR1_LOCK_Msk /*!< Non-secure Lock */ + +/****************** Bits definition for FLASH_SECCR1 register ****************/ +#define FLASH_SECCR1_PG_Pos (0U) +#define FLASH_SECCR1_PG_Msk (0x1UL << FLASH_SECCR1_PG_Pos) /*!< 0x00000001 */ +#define FLASH_SECCR1_PG FLASH_SECCR1_PG_Msk /*!< Secure Programming */ +#define FLASH_SECCR1_PER_Pos (1U) +#define FLASH_SECCR1_PER_Msk (0x1UL << FLASH_SECCR1_PER_Pos) /*!< 0x00000002 */ +#define FLASH_SECCR1_PER FLASH_SECCR1_PER_Msk /*!< Secure Page Erase */ +#define FLASH_SECCR1_MER_Pos (2U) +#define FLASH_SECCR1_MER_Msk (0x1UL << FLASH_SECCR1_MER_Pos) /*!< 0x00000004 */ +#define FLASH_SECCR1_MER FLASH_SECCR1_MER_Msk /*!< Secure Bank 1 Mass Erase */ +#define FLASH_SECCR1_PNB_Pos (3U) +#define FLASH_SECCR1_PNB_Msk (0x7FUL << FLASH_SECCR1_PNB_Pos) /*!< 0x000003F8 */ +#define FLASH_SECCR1_PNB FLASH_SECCR1_PNB_Msk /*!< Secure Page Number selection */ +#define FLASH_SECCR1_BWR_Pos (14U) +#define FLASH_SECCR1_BWR_Msk (0x1UL << FLASH_SECCR1_BWR_Pos) /*!< 0x00004000 */ +#define FLASH_SECCR1_BWR FLASH_SECCR1_BWR_Msk /*!< Secure Burst Write programming mode */ +#define FLASH_SECCR1_STRT_Pos (16U) +#define FLASH_SECCR1_STRT_Msk (0x1UL << FLASH_SECCR1_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_SECCR1_STRT FLASH_SECCR1_STRT_Msk /*!< Secure Start */ +#define FLASH_SECCR1_EOPIE_Pos (24U) +#define FLASH_SECCR1_EOPIE_Msk (0x1UL << FLASH_SECCR1_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_SECCR1_EOPIE FLASH_SECCR1_EOPIE_Msk /*!< Secure end of operation interrupt enable */ +#define FLASH_SECCR1_ERRIE_Pos (25U) +#define FLASH_SECCR1_ERRIE_Msk (0x1UL << FLASH_SECCR1_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_SECCR1_ERRIE FLASH_SECCR1_ERRIE_Msk /*!< Secure error interrupt enable */ +#define FLASH_SECCR1_INV_Pos (29U) +#define FLASH_SECCR1_INV_Msk (0x1UL << FLASH_SECCR1_INV_Pos) /*!< 0x20000000 */ +#define FLASH_SECCR1_INV FLASH_SECCR1_INV_Msk /*!< Flash Security State Invert */ +#define FLASH_SECCR1_LOCK_Pos (31U) +#define FLASH_SECCR1_LOCK_Msk (0x1UL << FLASH_SECCR1_LOCK_Pos) /*!< 0x80000000 */ +#define FLASH_SECCR1_LOCK FLASH_SECCR1_LOCK_Msk /*!< Secure Lock */ + +/******************* Bits definition for FLASH_ECCR register ***************/ +#define FLASH_ECCR_ADDR_ECC_Pos (0U) +#define FLASH_ECCR_ADDR_ECC_Msk (0xFFFFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x000FFFFF */ +#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk /*!< ECC fail address */ +#define FLASH_ECCR_SYSF_ECC_Pos (22U) +#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk /*!< System Flash ECC fail */ +#define FLASH_ECCR_ECCIE_Pos (24U) +#define FLASH_ECCR_ECCIE_Msk (0x1UL << FLASH_ECCR_ECCIE_Pos) /*!< 0x01000000 */ +#define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk /*!< ECC correction interrupt enable */ +#define FLASH_ECCR_ECCC_Pos (30U) +#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */ +#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk /*!< ECC correction */ +#define FLASH_ECCR_ECCD_Pos (31U) +#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */ +#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk /*!< ECC detection */ + +/******************* Bits definition for FLASH_OPSR register ***************/ +#define FLASH_OPSR_ADDR_OP_Pos (0U) +#define FLASH_OPSR_ADDR_OP_Msk (0xFFFFFUL << FLASH_OPSR_ADDR_OP_Pos) /*!< 0x000FFFFF */ +#define FLASH_OPSR_ADDR_OP FLASH_OPSR_ADDR_OP_Msk /*!< Interrupted operation address */ +#define FLASH_OPSR_SYSF_OP_Pos (22U) +#define FLASH_OPSR_SYSF_OP_Msk (0x1UL << FLASH_OPSR_SYSF_OP_Pos) /*!< 0x00400000 */ +#define FLASH_OPSR_SYSF_OP FLASH_OPSR_SYSF_OP_Msk /*!< Operation in system Flash memory interrupted */ +#define FLASH_OPSR_CODE_OP_Pos (29U) +#define FLASH_OPSR_CODE_OP_Msk (0x7UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x07000000 */ +#define FLASH_OPSR_CODE_OP FLASH_OPSR_CODE_OP_Msk /*!< Flash memory operation code */ +#define FLASH_OPSR_CODE_OP_0 (0x1UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x01000000 */ +#define FLASH_OPSR_CODE_OP_1 (0x2UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x02000000 */ +#define FLASH_OPSR_CODE_OP_2 (0x4UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x04000000 */ + +/******************* Bits definition for FLASH_NSCR2 register ***************/ +#define FLASH_NSCR2_PS_Pos (0U) +#define FLASH_NSCR2_PS_Msk (0x1UL << FLASH_NSCR2_PS_Pos) /*!< 0x00000001 */ +#define FLASH_NSCR2_PS FLASH_NSCR2_PS_Msk /*!< Program suspend request */ +#define FLASH_NSCR2_ES_Pos (1U) +#define FLASH_NSCR2_ES_Msk (0x1UL << FLASH_NSCR2_ES_Pos) /*!< 0x00000002 */ +#define FLASH_NSCR2_ES FLASH_NSCR2_ES_Msk /*!< Erase suspend request */ + +/******************* Bits definition for FLASH_SECCR2 register ***************/ +#define FLASH_SECCR2_PS_Pos (0U) +#define FLASH_SECCR2_PS_Msk (0x1UL << FLASH_SECCR2_PS_Pos) /*!< 0x00000001 */ +#define FLASH_SECCR2_PS FLASH_SECCR2_PS_Msk /*!< Program suspend request */ +#define FLASH_SECCR2_ES_Pos (1U) +#define FLASH_SECCR2_ES_Msk (0x1UL << FLASH_SECCR2_ES_Pos) /*!< 0x00000002 */ +#define FLASH_SECCR2_ES FLASH_SECCR2_ES_Msk /*!< Erase suspend request */ + +/******************* Bits definition for FLASH_OPTR register ***************/ +#define FLASH_OPTR_RDP_Pos (0U) +#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */ +#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk /*!< Readout protection level */ +#define FLASH_OPTR_BOR_LEV_Pos (8U) +#define FLASH_OPTR_BOR_LEV_Msk (0x7UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000700 */ +#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR reset Level */ +#define FLASH_OPTR_BOR_LEV_0 (0x1UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000100 */ +#define FLASH_OPTR_BOR_LEV_1 (0x2UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000200 */ +#define FLASH_OPTR_BOR_LEV_2 (0x4UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000400 */ +#define FLASH_OPTR_nRST_STOP_Pos (12U) +#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00001000 */ +#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< nRST_STOP */ +#define FLASH_OPTR_nRST_STDBY_Pos (13U) +#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */ +#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< nRST_STDBY */ +#define FLASH_OPTR_SRAM1_RST_Pos (15U) +#define FLASH_OPTR_SRAM1_RST_Msk (0x1UL << FLASH_OPTR_SRAM1_RST_Pos) /*!< 0x00008000 */ +#define FLASH_OPTR_SRAM1_RST FLASH_OPTR_SRAM1_RST_Msk /*!< SRAM1 erase upon system reset */ +#define FLASH_OPTR_IWDG_SW_Pos (16U) +#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */ +#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< Independent watchdog selection */ +#define FLASH_OPTR_IWDG_STOP_Pos (17U) +#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */ +#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk /*!< Independent watchdog counter freeze in Stop mode */ +#define FLASH_OPTR_IWDG_STDBY_Pos (18U) +#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */ +#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk /*!< Independent watchdog counter freeze in Standby mode */ +#define FLASH_OPTR_WWDG_SW_Pos (19U) +#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */ +#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk /*!< Window watchdog selection */ +#define FLASH_OPTR_SRAM2_PE_Pos (24U) +#define FLASH_OPTR_SRAM2_PE_Msk (0x1UL << FLASH_OPTR_SRAM2_PE_Pos) /*!< 0x01000000 */ +#define FLASH_OPTR_SRAM2_PE FLASH_OPTR_SRAM2_PE_Msk /*!< SRAM2 ECC detection and correction enable*/ +#define FLASH_OPTR_SRAM2_RST_Pos (25U) +#define FLASH_OPTR_SRAM2_RST_Msk (0x1UL << FLASH_OPTR_SRAM2_RST_Pos) /*!< 0x02000000 */ +#define FLASH_OPTR_SRAM2_RST FLASH_OPTR_SRAM2_RST_Msk /*!< SRAM2 erase when system reset */ +#define FLASH_OPTR_nSWBOOT0_Pos (26U) +#define FLASH_OPTR_nSWBOOT0_Msk (0x1UL << FLASH_OPTR_nSWBOOT0_Pos) /*!< 0x04000000 */ +#define FLASH_OPTR_nSWBOOT0 FLASH_OPTR_nSWBOOT0_Msk /*!< Software BOOT0 */ +#define FLASH_OPTR_nBOOT0_Pos (27U) +#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x08000000 */ +#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk /*!< nBOOT0 option bit */ +#define FLASH_OPTR_TZEN_Pos (31U) +#define FLASH_OPTR_TZEN_Msk (0x1UL << FLASH_OPTR_TZEN_Pos) /*!< 0x80000000 */ +#define FLASH_OPTR_TZEN FLASH_OPTR_TZEN_Msk /*!< Global TrustZone security enable */ + +/**************** Bits definition for FLASH_NSBOOTADD0R register ************/ +#define FLASH_NSBOOTADD0R_NSBOOTADD0_Pos (7U) +#define FLASH_NSBOOTADD0R_NSBOOTADD0_Msk (0x1FFFFFFUL << FLASH_NSBOOTADD0R_NSBOOTADD0_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_NSBOOTADD0R_NSBOOTADD0 FLASH_NSBOOTADD0R_NSBOOTADD0_Msk /*!< Non-secure boot address 0 */ + +/**************** Bits definition for FLASH_NSBOOTADD1R register ************/ +#define FLASH_NSBOOTADD1R_NSBOOTADD1_Pos (7U) +#define FLASH_NSBOOTADD1R_NSBOOTADD1_Msk (0x1FFFFFFUL << FLASH_NSBOOTADD1R_NSBOOTADD1_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_NSBOOTADD1R_NSBOOTADD1 FLASH_NSBOOTADD1R_NSBOOTADD1_Msk /*!< Non-secure boot address 1 */ + +/**************** Bits definition for FLASH_SECBOOTADD0R register ***********/ +#define FLASH_SECBOOTADD0R_BOOT_LOCK_Pos (0U) +#define FLASH_SECBOOTADD0R_BOOT_LOCK_Msk (0x1UL << FLASH_SECBOOTADD0R_BOOT_LOCK_Pos) /*!< 0x00000001 */ +#define FLASH_SECBOOTADD0R_BOOT_LOCK FLASH_SECBOOTADD0R_BOOT_LOCK_Msk /*!< Boot Lock */ +#define FLASH_SECBOOTADD0R_SECBOOTADD0_Pos (7U) +#define FLASH_SECBOOTADD0R_SECBOOTADD0_Msk (0x1FFFFFFUL << FLASH_SECBOOTADD0R_SECBOOTADD0_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_SECBOOTADD0R_SECBOOTADD0 FLASH_SECBOOTADD0R_SECBOOTADD0_Msk /*!< Secure boot address 0 */ + +/***************** Bits definition for FLASH_SECWMR1 register **************/ +#define FLASH_SECWMR1_SECWM_PSTRT_Pos (0U) +#define FLASH_SECWMR1_SECWM_PSTRT_Msk (0x7FUL << FLASH_SECWMR1_SECWM_PSTRT_Pos) /*!< 0x0000007F */ +#define FLASH_SECWMR1_SECWM_PSTRT FLASH_SECWMR1_SECWM_PSTRT_Msk /*!< Start page of first secure area */ +#define FLASH_SECWMR1_SECWM_PEND_Pos (16U) +#define FLASH_SECWMR1_SECWM_PEND_Msk (0x7FUL << FLASH_SECWMR1_SECWM_PEND_Pos) /*!< 0x007F0000 */ +#define FLASH_SECWMR1_SECWM_PEND FLASH_SECWMR1_SECWM_PEND_Msk /*!< End page of first secure area */ + +/***************** Bits definition for FLASH_SECWMR2 register **************/ +#define FLASH_SECWMR2_HDP_PEND_Pos (16U) +#define FLASH_SECWMR2_HDP_PEND_Msk (0x7FUL << FLASH_SECWMR2_HDP_PEND_Pos) /*!< 0x007F0000 */ +#define FLASH_SECWMR2_HDP_PEND FLASH_SECWMR2_HDP_PEND_Msk /*!< End page of first hide protection area */ +#define FLASH_SECWMR2_HDPEN_Pos (31U) +#define FLASH_SECWMR2_HDPEN_Msk (0x1UL << FLASH_SECWMR2_HDPEN_Pos) /*!< 0x80000000 */ +#define FLASH_SECWMR2_HDPEN FLASH_SECWMR2_HDPEN_Msk /*!< Hide protection first area enable */ + +/****************** Bits definition for FLASH_WRPAR register ***************/ +#define FLASH_WRPAR_WRPA_PSTRT_Pos (0U) +#define FLASH_WRPAR_WRPA_PSTRT_Msk (0x7FUL << FLASH_WRPAR_WRPA_PSTRT_Pos) /*!< 0x0000007F */ +#define FLASH_WRPAR_WRPA_PSTRT FLASH_WRPAR_WRPA_PSTRT_Msk /*!< WPR first area A start page */ +#define FLASH_WRPAR_WRPA_PEND_Pos (16U) +#define FLASH_WRPAR_WRPA_PEND_Msk (0x7FUL << FLASH_WRPAR_WRPA_PEND_Pos) /*!< 0x007F0000 */ +#define FLASH_WRPAR_WRPA_PEND FLASH_WRPAR_WRPA_PEND_Msk /*!< WPR first area A end page */ +#define FLASH_WRPAR_UNLOCK_Pos (31U) +#define FLASH_WRPAR_UNLOCK_Msk (0x1UL << FLASH_WRPAR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRPAR_UNLOCK FLASH_WRPAR_UNLOCK_Msk /*!< WPR first area A unlock */ + +/****************** Bits definition for FLASH_WRPBR register ***************/ +#define FLASH_WRPBR_WRPB_PSTRT_Pos (0U) +#define FLASH_WRPBR_WRPB_PSTRT_Msk (0x7FUL << FLASH_WRPBR_WRPB_PSTRT_Pos) /*!< 0x0000007F */ +#define FLASH_WRPBR_WRPB_PSTRT FLASH_WRPBR_WRPB_PSTRT_Msk /*!< WPR second area B start page */ +#define FLASH_WRPBR_WRPB_PEND_Pos (16U) +#define FLASH_WRPBR_WRPB_PEND_Msk (0x7FUL << FLASH_WRPBR_WRPB_PEND_Pos) /*!< 0x007F0000 */ +#define FLASH_WRPBR_WRPB_PEND FLASH_WRPBR_WRPB_PEND_Msk /*!< WPR second area B end page */ +#define FLASH_WRPBR_UNLOCK_Pos (31U) +#define FLASH_WRPBR_UNLOCK_Msk (0x1UL << FLASH_WRPBR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRPBR_UNLOCK FLASH_WRPBR_UNLOCK_Msk /*!< WPR first area B unlock */ + +/****************** Bits definition for FLASH_OEM1KEYR1 register *****************/ +#define FLASH_OEM1KEYR1_OEM1KEY_Pos (0U) +#define FLASH_OEM1KEYR1_OEM1KEY_Msk (0xFFFFFFFFUL << FLASH_OEM1KEYR1_OEM1KEY_Pos) /*!< 0xFFFFFFFFF */ +#define FLASH_OEM1KEYR1_OEM1KEY FLASH_OEM1KEYR1_OEM1KEY_Msk /*!< OEM1 least significant bytes key */ + +/****************** Bits definition for FLASH_OEM1KEYR2 register *****************/ +#define FLASH_OEM1KEYR2_OEM1KEY_Pos (0U) +#define FLASH_OEM1KEYR2_OEM1KEY_Msk (0xFFFFFFFFUL << FLASH_OEM1KEYR2_OEM1KEY_Pos) /*!< 0xFFFFFFFFF */ +#define FLASH_OEM1KEYR2_OEM1KEY FLASH_OEM1KEYR2_OEM1KEY_Msk /*!< OEM1 most significant bytes key */ + +/****************** Bits definition for FLASH_OEM2KEYR1 register *****************/ +#define FLASH_OEM2KEYR1_OEM2KEY_Pos (0U) +#define FLASH_OEM2KEYR1_OEM2KEY_Msk (0xFFFFFFFFUL << FLASH_OEM2KEYR1_OEM2KEY_Pos) /*!< 0xFFFFFFFFF */ +#define FLASH_OEM2KEYR1_OEM2KEY FLASH_OEM2KEYR1_OEM2KEY_Msk /*!< OEM2 least significant bytes key */ + +/****************** Bits definition for FLASH_OEM2KEYR2 register *****************/ +#define FLASH_OEM2KEYR2_OEM2KEY_Pos (0U) +#define FLASH_OEM2KEYR2_OEM2KEY_Msk (0xFFFFFFFFUL << FLASH_OEM2KEYR2_OEM2KEY_Pos) /*!< 0xFFFFFFFFF */ +#define FLASH_OEM2KEYR2_OEM2KEY FLASH_OEM2KEYR2_OEM2KEY_Msk /*!< OEM2 most significant bytes key */ + +/******************* Bit definition for FLASH_SECBBR1 register ******************/ +#define FLASH_SECBBR1_SECBB0_Pos (0U) +#define FLASH_SECBBR1_SECBB0_Msk (0x1UL << FLASH_SECBBR1_SECBB0_Pos) /*!< 0x00000001 */ +#define FLASH_SECBBR1_SECBB0 FLASH_SECBBR1_SECBB0_Msk /*!< Page 0 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB1_Pos (1U) +#define FLASH_SECBBR1_SECBB1_Msk (0x1UL << FLASH_SECBBR1_SECBB1_Pos) /*!< 0x00000002 */ +#define FLASH_SECBBR1_SECBB1 FLASH_SECBBR1_SECBB1_Msk /*!< Page 1 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB2_Pos (2U) +#define FLASH_SECBBR1_SECBB2_Msk (0x1UL << FLASH_SECBBR1_SECBB2_Pos) /*!< 0x00000004 */ +#define FLASH_SECBBR1_SECBB2 FLASH_SECBBR1_SECBB2_Msk /*!< Page 2 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB3_Pos (3U) +#define FLASH_SECBBR1_SECBB3_Msk (0x1UL << FLASH_SECBBR1_SECBB3_Pos) /*!< 0x00000008 */ +#define FLASH_SECBBR1_SECBB3 FLASH_SECBBR1_SECBB3_Msk /*!< Page 3 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB4_Pos (4U) +#define FLASH_SECBBR1_SECBB4_Msk (0x1UL << FLASH_SECBBR1_SECBB4_Pos) /*!< 0x00000010 */ +#define FLASH_SECBBR1_SECBB4 FLASH_SECBBR1_SECBB4_Msk /*!< Page 4 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB5_Pos (5U) +#define FLASH_SECBBR1_SECBB5_Msk (0x1UL << FLASH_SECBBR1_SECBB5_Pos) /*!< 0x00000020 */ +#define FLASH_SECBBR1_SECBB5 FLASH_SECBBR1_SECBB5_Msk /*!< Page 5 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB6_Pos (6U) +#define FLASH_SECBBR1_SECBB6_Msk (0x1UL << FLASH_SECBBR1_SECBB6_Pos) /*!< 0x00000040 */ +#define FLASH_SECBBR1_SECBB6 FLASH_SECBBR1_SECBB6_Msk /*!< Page 6 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB7_Pos (7U) +#define FLASH_SECBBR1_SECBB7_Msk (0x1UL << FLASH_SECBBR1_SECBB7_Pos) /*!< 0x00000080 */ +#define FLASH_SECBBR1_SECBB7 FLASH_SECBBR1_SECBB7_Msk /*!< Page 7 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB8_Pos (8U) +#define FLASH_SECBBR1_SECBB8_Msk (0x1UL << FLASH_SECBBR1_SECBB8_Pos) /*!< 0x00000100 */ +#define FLASH_SECBBR1_SECBB8 FLASH_SECBBR1_SECBB8_Msk /*!< Page 8 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB9_Pos (9U) +#define FLASH_SECBBR1_SECBB9_Msk (0x1UL << FLASH_SECBBR1_SECBB9_Pos) /*!< 0x00000200 */ +#define FLASH_SECBBR1_SECBB9 FLASH_SECBBR1_SECBB9_Msk /*!< Page 9 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB10_Pos (10U) +#define FLASH_SECBBR1_SECBB10_Msk (0x1UL << FLASH_SECBBR1_SECBB10_Pos) /*!< 0x00000400 */ +#define FLASH_SECBBR1_SECBB10 FLASH_SECBBR1_SECBB10_Msk /*!< Page 10 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB11_Pos (11U) +#define FLASH_SECBBR1_SECBB11_Msk (0x1UL << FLASH_SECBBR1_SECBB11_Pos) /*!< 0x00000800 */ +#define FLASH_SECBBR1_SECBB11 FLASH_SECBBR1_SECBB11_Msk /*!< Page 11 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB12_Pos (12U) +#define FLASH_SECBBR1_SECBB12_Msk (0x1UL << FLASH_SECBBR1_SECBB12_Pos) /*!< 0x00001000 */ +#define FLASH_SECBBR1_SECBB12 FLASH_SECBBR1_SECBB12_Msk /*!< Page 12 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB13_Pos (13U) +#define FLASH_SECBBR1_SECBB13_Msk (0x1UL << FLASH_SECBBR1_SECBB13_Pos) /*!< 0x00002000 */ +#define FLASH_SECBBR1_SECBB13 FLASH_SECBBR1_SECBB13_Msk /*!< Page 13 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB14_Pos (14U) +#define FLASH_SECBBR1_SECBB14_Msk (0x1UL << FLASH_SECBBR1_SECBB14_Pos) /*!< 0x00004000 */ +#define FLASH_SECBBR1_SECBB14 FLASH_SECBBR1_SECBB14_Msk /*!< Page 14 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB15_Pos (15U) +#define FLASH_SECBBR1_SECBB15_Msk (0x1UL << FLASH_SECBBR1_SECBB15_Pos) /*!< 0x00008000 */ +#define FLASH_SECBBR1_SECBB15 FLASH_SECBBR1_SECBB15_Msk /*!< Page 15 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB16_Pos (16U) +#define FLASH_SECBBR1_SECBB16_Msk (0x1UL << FLASH_SECBBR1_SECBB16_Pos) /*!< 0x00010000 */ +#define FLASH_SECBBR1_SECBB16 FLASH_SECBBR1_SECBB16_Msk /*!< Page 16 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB17_Pos (17U) +#define FLASH_SECBBR1_SECBB17_Msk (0x1UL << FLASH_SECBBR1_SECBB17_Pos) /*!< 0x00020000 */ +#define FLASH_SECBBR1_SECBB17 FLASH_SECBBR1_SECBB17_Msk /*!< Page 17 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB18_Pos (18U) +#define FLASH_SECBBR1_SECBB18_Msk (0x1UL << FLASH_SECBBR1_SECBB18_Pos) /*!< 0x00040000 */ +#define FLASH_SECBBR1_SECBB18 FLASH_SECBBR1_SECBB18_Msk /*!< Page 18 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB19_Pos (19U) +#define FLASH_SECBBR1_SECBB19_Msk (0x1UL << FLASH_SECBBR1_SECBB19_Pos) /*!< 0x00080000 */ +#define FLASH_SECBBR1_SECBB19 FLASH_SECBBR1_SECBB19_Msk /*!< Page 19 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB20_Pos (20U) +#define FLASH_SECBBR1_SECBB20_Msk (0x1UL << FLASH_SECBBR1_SECBB20_Pos) /*!< 0x00100000 */ +#define FLASH_SECBBR1_SECBB20 FLASH_SECBBR1_SECBB20_Msk /*!< Page 20 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB21_Pos (21U) +#define FLASH_SECBBR1_SECBB21_Msk (0x1UL << FLASH_SECBBR1_SECBB21_Pos) /*!< 0x00200000 */ +#define FLASH_SECBBR1_SECBB21 FLASH_SECBBR1_SECBB21_Msk /*!< Page 21 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB22_Pos (22U) +#define FLASH_SECBBR1_SECBB22_Msk (0x1UL << FLASH_SECBBR1_SECBB22_Pos) /*!< 0x00400000 */ +#define FLASH_SECBBR1_SECBB22 FLASH_SECBBR1_SECBB22_Msk /*!< Page 22 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB23_Pos (23U) +#define FLASH_SECBBR1_SECBB23_Msk (0x1UL << FLASH_SECBBR1_SECBB23_Pos) /*!< 0x00800000 */ +#define FLASH_SECBBR1_SECBB23 FLASH_SECBBR1_SECBB23_Msk /*!< Page 23 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB24_Pos (24U) +#define FLASH_SECBBR1_SECBB24_Msk (0x1UL << FLASH_SECBBR1_SECBB24_Pos) /*!< 0x01000000 */ +#define FLASH_SECBBR1_SECBB24 FLASH_SECBBR1_SECBB24_Msk /*!< Page 24 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB25_Pos (25U) +#define FLASH_SECBBR1_SECBB25_Msk (0x1UL << FLASH_SECBBR1_SECBB25_Pos) /*!< 0x02000000 */ +#define FLASH_SECBBR1_SECBB25 FLASH_SECBBR1_SECBB25_Msk /*!< Page 25 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB26_Pos (26U) +#define FLASH_SECBBR1_SECBB26_Msk (0x1UL << FLASH_SECBBR1_SECBB26_Pos) /*!< 0x04000000 */ +#define FLASH_SECBBR1_SECBB26 FLASH_SECBBR1_SECBB26_Msk /*!< Page 26 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB27_Pos (27U) +#define FLASH_SECBBR1_SECBB27_Msk (0x1UL << FLASH_SECBBR1_SECBB27_Pos) /*!< 0x08000000 */ +#define FLASH_SECBBR1_SECBB27 FLASH_SECBBR1_SECBB27_Msk /*!< Page 27 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB28_Pos (28U) +#define FLASH_SECBBR1_SECBB28_Msk (0x1UL << FLASH_SECBBR1_SECBB28_Pos) /*!< 0x10000000 */ +#define FLASH_SECBBR1_SECBB28 FLASH_SECBBR1_SECBB28_Msk /*!< Page 28 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB29_Pos (29U) +#define FLASH_SECBBR1_SECBB29_Msk (0x1UL << FLASH_SECBBR1_SECBB29_Pos) /*!< 0x20000000 */ +#define FLASH_SECBBR1_SECBB29 FLASH_SECBBR1_SECBB29_Msk /*!< Page 29 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB30_Pos (30U) +#define FLASH_SECBBR1_SECBB30_Msk (0x1UL << FLASH_SECBBR1_SECBB30_Pos) /*!< 0x40000000 */ +#define FLASH_SECBBR1_SECBB30 FLASH_SECBBR1_SECBB30_Msk /*!< Page 30 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB31_Pos (31U) +#define FLASH_SECBBR1_SECBB31_Msk (0x1UL << FLASH_SECBBR1_SECBB31_Pos) /*!< 0x80000000 */ +#define FLASH_SECBBR1_SECBB31 FLASH_SECBBR1_SECBB31_Msk /*!< Page 31 in Flash block-based secure */ + +/******************* Bit definition for FLASH_SECBBR2 register ******************/ +#define FLASH_SECBBR2_SECBB0_Pos (0U) +#define FLASH_SECBBR2_SECBB0_Msk (0x1UL << FLASH_SECBBR2_SECBB0_Pos) /*!< 0x00000001 */ +#define FLASH_SECBBR2_SECBB0 FLASH_SECBBR2_SECBB0_Msk /*!< Page 32 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB1_Pos (1U) +#define FLASH_SECBBR2_SECBB1_Msk (0x1UL << FLASH_SECBBR2_SECBB1_Pos) /*!< 0x00000002 */ +#define FLASH_SECBBR2_SECBB1 FLASH_SECBBR2_SECBB1_Msk /*!< Page 33 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB2_Pos (2U) +#define FLASH_SECBBR2_SECBB2_Msk (0x1UL << FLASH_SECBBR2_SECBB2_Pos) /*!< 0x00000004 */ +#define FLASH_SECBBR2_SECBB2 FLASH_SECBBR2_SECBB2_Msk /*!< Page 34 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB3_Pos (3U) +#define FLASH_SECBBR2_SECBB3_Msk (0x1UL << FLASH_SECBBR2_SECBB3_Pos) /*!< 0x00000008 */ +#define FLASH_SECBBR2_SECBB3 FLASH_SECBBR2_SECBB3_Msk /*!< Page 35 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB4_Pos (4U) +#define FLASH_SECBBR2_SECBB4_Msk (0x1UL << FLASH_SECBBR2_SECBB4_Pos) /*!< 0x00000010 */ +#define FLASH_SECBBR2_SECBB4 FLASH_SECBBR2_SECBB4_Msk /*!< Page 36 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB5_Pos (5U) +#define FLASH_SECBBR2_SECBB5_Msk (0x1UL << FLASH_SECBBR2_SECBB5_Pos) /*!< 0x00000020 */ +#define FLASH_SECBBR2_SECBB5 FLASH_SECBBR2_SECBB5_Msk /*!< Page 37 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB6_Pos (6U) +#define FLASH_SECBBR2_SECBB6_Msk (0x1UL << FLASH_SECBBR2_SECBB6_Pos) /*!< 0x00000040 */ +#define FLASH_SECBBR2_SECBB6 FLASH_SECBBR2_SECBB6_Msk /*!< Page 38 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB7_Pos (7U) +#define FLASH_SECBBR2_SECBB7_Msk (0x1UL << FLASH_SECBBR2_SECBB7_Pos) /*!< 0x00000080 */ +#define FLASH_SECBBR2_SECBB7 FLASH_SECBBR2_SECBB7_Msk /*!< Page 39 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB8_Pos (8U) +#define FLASH_SECBBR2_SECBB8_Msk (0x1UL << FLASH_SECBBR2_SECBB8_Pos) /*!< 0x00000100 */ +#define FLASH_SECBBR2_SECBB8 FLASH_SECBBR2_SECBB8_Msk /*!< Page 40 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB9_Pos (9U) +#define FLASH_SECBBR2_SECBB9_Msk (0x1UL << FLASH_SECBBR2_SECBB9_Pos) /*!< 0x00000200 */ +#define FLASH_SECBBR2_SECBB9 FLASH_SECBBR2_SECBB9_Msk /*!< Page 41 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB10_Pos (10U) +#define FLASH_SECBBR2_SECBB10_Msk (0x1UL << FLASH_SECBBR2_SECBB10_Pos) /*!< 0x00000400 */ +#define FLASH_SECBBR2_SECBB10 FLASH_SECBBR2_SECBB10_Msk /*!< Page 42 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB11_Pos (11U) +#define FLASH_SECBBR2_SECBB11_Msk (0x1UL << FLASH_SECBBR2_SECBB11_Pos) /*!< 0x00000800 */ +#define FLASH_SECBBR2_SECBB11 FLASH_SECBBR2_SECBB11_Msk /*!< Page 43 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB12_Pos (12U) +#define FLASH_SECBBR2_SECBB12_Msk (0x1UL << FLASH_SECBBR2_SECBB12_Pos) /*!< 0x00001000 */ +#define FLASH_SECBBR2_SECBB12 FLASH_SECBBR2_SECBB12_Msk /*!< Page 44 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB13_Pos (13U) +#define FLASH_SECBBR2_SECBB13_Msk (0x1UL << FLASH_SECBBR2_SECBB13_Pos) /*!< 0x00002000 */ +#define FLASH_SECBBR2_SECBB13 FLASH_SECBBR2_SECBB13_Msk /*!< Page 45 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB14_Pos (14U) +#define FLASH_SECBBR2_SECBB14_Msk (0x1UL << FLASH_SECBBR2_SECBB14_Pos) /*!< 0x00004000 */ +#define FLASH_SECBBR2_SECBB14 FLASH_SECBBR2_SECBB14_Msk /*!< Page 46 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB15_Pos (15U) +#define FLASH_SECBBR2_SECBB15_Msk (0x1UL << FLASH_SECBBR2_SECBB15_Pos) /*!< 0x00008000 */ +#define FLASH_SECBBR2_SECBB15 FLASH_SECBBR2_SECBB15_Msk /*!< Page 47 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB16_Pos (16U) +#define FLASH_SECBBR2_SECBB16_Msk (0x1UL << FLASH_SECBBR2_SECBB16_Pos) /*!< 0x00010000 */ +#define FLASH_SECBBR2_SECBB16 FLASH_SECBBR2_SECBB16_Msk /*!< Page 48 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB17_Pos (17U) +#define FLASH_SECBBR2_SECBB17_Msk (0x1UL << FLASH_SECBBR2_SECBB17_Pos) /*!< 0x00020000 */ +#define FLASH_SECBBR2_SECBB17 FLASH_SECBBR2_SECBB17_Msk /*!< Page 49 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB18_Pos (18U) +#define FLASH_SECBBR2_SECBB18_Msk (0x1UL << FLASH_SECBBR2_SECBB18_Pos) /*!< 0x00040000 */ +#define FLASH_SECBBR2_SECBB18 FLASH_SECBBR2_SECBB18_Msk /*!< Page 50 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB19_Pos (19U) +#define FLASH_SECBBR2_SECBB19_Msk (0x1UL << FLASH_SECBBR2_SECBB19_Pos) /*!< 0x00080000 */ +#define FLASH_SECBBR2_SECBB19 FLASH_SECBBR2_SECBB19_Msk /*!< Page 51 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB20_Pos (20U) +#define FLASH_SECBBR2_SECBB20_Msk (0x1UL << FLASH_SECBBR2_SECBB20_Pos) /*!< 0x00100000 */ +#define FLASH_SECBBR2_SECBB20 FLASH_SECBBR2_SECBB20_Msk /*!< Page 52 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB21_Pos (21U) +#define FLASH_SECBBR2_SECBB21_Msk (0x1UL << FLASH_SECBBR2_SECBB21_Pos) /*!< 0x00200000 */ +#define FLASH_SECBBR2_SECBB21 FLASH_SECBBR2_SECBB21_Msk /*!< Page 53 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB22_Pos (22U) +#define FLASH_SECBBR2_SECBB22_Msk (0x1UL << FLASH_SECBBR2_SECBB22_Pos) /*!< 0x00400000 */ +#define FLASH_SECBBR2_SECBB22 FLASH_SECBBR2_SECBB22_Msk /*!< Page 54 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB23_Pos (23U) +#define FLASH_SECBBR2_SECBB23_Msk (0x1UL << FLASH_SECBBR2_SECBB23_Pos) /*!< 0x00800000 */ +#define FLASH_SECBBR2_SECBB23 FLASH_SECBBR2_SECBB23_Msk /*!< Page 55 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB24_Pos (24U) +#define FLASH_SECBBR2_SECBB24_Msk (0x1UL << FLASH_SECBBR2_SECBB24_Pos) /*!< 0x01000000 */ +#define FLASH_SECBBR2_SECBB24 FLASH_SECBBR2_SECBB24_Msk /*!< Page 56 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB25_Pos (25U) +#define FLASH_SECBBR2_SECBB25_Msk (0x1UL << FLASH_SECBBR2_SECBB25_Pos) /*!< 0x02000000 */ +#define FLASH_SECBBR2_SECBB25 FLASH_SECBBR2_SECBB25_Msk /*!< Page 57 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB26_Pos (26U) +#define FLASH_SECBBR2_SECBB26_Msk (0x1UL << FLASH_SECBBR2_SECBB26_Pos) /*!< 0x04000000 */ +#define FLASH_SECBBR2_SECBB26 FLASH_SECBBR2_SECBB26_Msk /*!< Page 58 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB27_Pos (27U) +#define FLASH_SECBBR2_SECBB27_Msk (0x1UL << FLASH_SECBBR2_SECBB27_Pos) /*!< 0x08000000 */ +#define FLASH_SECBBR2_SECBB27 FLASH_SECBBR2_SECBB27_Msk /*!< Page 59 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB28_Pos (28U) +#define FLASH_SECBBR2_SECBB28_Msk (0x1UL << FLASH_SECBBR2_SECBB28_Pos) /*!< 0x10000000 */ +#define FLASH_SECBBR2_SECBB28 FLASH_SECBBR2_SECBB28_Msk /*!< Page 60 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB29_Pos (29U) +#define FLASH_SECBBR2_SECBB29_Msk (0x1UL << FLASH_SECBBR2_SECBB29_Pos) /*!< 0x20000000 */ +#define FLASH_SECBBR2_SECBB29 FLASH_SECBBR2_SECBB29_Msk /*!< Page 61 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB30_Pos (30U) +#define FLASH_SECBBR2_SECBB30_Msk (0x1UL << FLASH_SECBBR2_SECBB30_Pos) /*!< 0x40000000 */ +#define FLASH_SECBBR2_SECBB30 FLASH_SECBBR2_SECBB30_Msk /*!< Page 62 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB31_Pos (31U) +#define FLASH_SECBBR2_SECBB31_Msk (0x1UL << FLASH_SECBBR2_SECBB31_Pos) /*!< 0x80000000 */ +#define FLASH_SECBBR2_SECBB31 FLASH_SECBBR2_SECBB31_Msk /*!< Page 63 in Flash block-based secure */ + +/******************* Bit definition for FLASH_SECBBR3 register ******************/ +#define FLASH_SECBBR3_SECBB0_Pos (0U) +#define FLASH_SECBBR3_SECBB0_Msk (0x1UL << FLASH_SECBBR3_SECBB0_Pos) /*!< 0x00000001 */ +#define FLASH_SECBBR3_SECBB0 FLASH_SECBBR3_SECBB0_Msk /*!< Page 64 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB1_Pos (1U) +#define FLASH_SECBBR3_SECBB1_Msk (0x1UL << FLASH_SECBBR3_SECBB1_Pos) /*!< 0x00000002 */ +#define FLASH_SECBBR3_SECBB1 FLASH_SECBBR3_SECBB1_Msk /*!< Page 65 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB2_Pos (2U) +#define FLASH_SECBBR3_SECBB2_Msk (0x1UL << FLASH_SECBBR3_SECBB2_Pos) /*!< 0x00000004 */ +#define FLASH_SECBBR3_SECBB2 FLASH_SECBBR3_SECBB2_Msk /*!< Page 66 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB3_Pos (3U) +#define FLASH_SECBBR3_SECBB3_Msk (0x1UL << FLASH_SECBBR3_SECBB3_Pos) /*!< 0x00000008 */ +#define FLASH_SECBBR3_SECBB3 FLASH_SECBBR3_SECBB3_Msk /*!< Page 67 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB4_Pos (4U) +#define FLASH_SECBBR3_SECBB4_Msk (0x1UL << FLASH_SECBBR3_SECBB4_Pos) /*!< 0x00000010 */ +#define FLASH_SECBBR3_SECBB4 FLASH_SECBBR3_SECBB4_Msk /*!< Page 68 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB5_Pos (5U) +#define FLASH_SECBBR3_SECBB5_Msk (0x1UL << FLASH_SECBBR3_SECBB5_Pos) /*!< 0x00000020 */ +#define FLASH_SECBBR3_SECBB5 FLASH_SECBBR3_SECBB5_Msk /*!< Page 69 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB6_Pos (6U) +#define FLASH_SECBBR3_SECBB6_Msk (0x1UL << FLASH_SECBBR3_SECBB6_Pos) /*!< 0x00000040 */ +#define FLASH_SECBBR3_SECBB6 FLASH_SECBBR3_SECBB6_Msk /*!< Page 70 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB7_Pos (7U) +#define FLASH_SECBBR3_SECBB7_Msk (0x1UL << FLASH_SECBBR3_SECBB7_Pos) /*!< 0x00000080 */ +#define FLASH_SECBBR3_SECBB7 FLASH_SECBBR3_SECBB7_Msk /*!< Page 71 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB8_Pos (8U) +#define FLASH_SECBBR3_SECBB8_Msk (0x1UL << FLASH_SECBBR3_SECBB8_Pos) /*!< 0x00000100 */ +#define FLASH_SECBBR3_SECBB8 FLASH_SECBBR3_SECBB8_Msk /*!< Page 72 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB9_Pos (9U) +#define FLASH_SECBBR3_SECBB9_Msk (0x1UL << FLASH_SECBBR3_SECBB9_Pos) /*!< 0x00000200 */ +#define FLASH_SECBBR3_SECBB9 FLASH_SECBBR3_SECBB9_Msk /*!< Page 73 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB10_Pos (10U) +#define FLASH_SECBBR3_SECBB10_Msk (0x1UL << FLASH_SECBBR3_SECBB10_Pos) /*!< 0x00000400 */ +#define FLASH_SECBBR3_SECBB10 FLASH_SECBBR3_SECBB10_Msk /*!< Page 74 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB11_Pos (11U) +#define FLASH_SECBBR3_SECBB11_Msk (0x1UL << FLASH_SECBBR3_SECBB11_Pos) /*!< 0x00000800 */ +#define FLASH_SECBBR3_SECBB11 FLASH_SECBBR3_SECBB11_Msk /*!< Page 75 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB12_Pos (12U) +#define FLASH_SECBBR3_SECBB12_Msk (0x1UL << FLASH_SECBBR3_SECBB12_Pos) /*!< 0x00001000 */ +#define FLASH_SECBBR3_SECBB12 FLASH_SECBBR3_SECBB12_Msk /*!< Page 76 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB13_Pos (13U) +#define FLASH_SECBBR3_SECBB13_Msk (0x1UL << FLASH_SECBBR3_SECBB13_Pos) /*!< 0x00002000 */ +#define FLASH_SECBBR3_SECBB13 FLASH_SECBBR3_SECBB13_Msk /*!< Page 77 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB14_Pos (14U) +#define FLASH_SECBBR3_SECBB14_Msk (0x1UL << FLASH_SECBBR3_SECBB14_Pos) /*!< 0x00004000 */ +#define FLASH_SECBBR3_SECBB14 FLASH_SECBBR3_SECBB14_Msk /*!< Page 78 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB15_Pos (15U) +#define FLASH_SECBBR3_SECBB15_Msk (0x1UL << FLASH_SECBBR3_SECBB15_Pos) /*!< 0x00008000 */ +#define FLASH_SECBBR3_SECBB15 FLASH_SECBBR3_SECBB15_Msk /*!< Page 79 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB16_Pos (16U) +#define FLASH_SECBBR3_SECBB16_Msk (0x1UL << FLASH_SECBBR3_SECBB16_Pos) /*!< 0x00010000 */ +#define FLASH_SECBBR3_SECBB16 FLASH_SECBBR3_SECBB16_Msk /*!< Page 80 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB17_Pos (17U) +#define FLASH_SECBBR3_SECBB17_Msk (0x1UL << FLASH_SECBBR3_SECBB17_Pos) /*!< 0x00020000 */ +#define FLASH_SECBBR3_SECBB17 FLASH_SECBBR3_SECBB17_Msk /*!< Page 81 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB18_Pos (18U) +#define FLASH_SECBBR3_SECBB18_Msk (0x1UL << FLASH_SECBBR3_SECBB18_Pos) /*!< 0x00040000 */ +#define FLASH_SECBBR3_SECBB18 FLASH_SECBBR3_SECBB18_Msk /*!< Page 82 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB19_Pos (19U) +#define FLASH_SECBBR3_SECBB19_Msk (0x1UL << FLASH_SECBBR3_SECBB19_Pos) /*!< 0x00080000 */ +#define FLASH_SECBBR3_SECBB19 FLASH_SECBBR3_SECBB19_Msk /*!< Page 83 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB20_Pos (20U) +#define FLASH_SECBBR3_SECBB20_Msk (0x1UL << FLASH_SECBBR3_SECBB20_Pos) /*!< 0x00100000 */ +#define FLASH_SECBBR3_SECBB20 FLASH_SECBBR3_SECBB20_Msk /*!< Page 84 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB21_Pos (21U) +#define FLASH_SECBBR3_SECBB21_Msk (0x1UL << FLASH_SECBBR3_SECBB21_Pos) /*!< 0x00200000 */ +#define FLASH_SECBBR3_SECBB21 FLASH_SECBBR3_SECBB21_Msk /*!< Page 85 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB22_Pos (22U) +#define FLASH_SECBBR3_SECBB22_Msk (0x1UL << FLASH_SECBBR3_SECBB22_Pos) /*!< 0x00400000 */ +#define FLASH_SECBBR3_SECBB22 FLASH_SECBBR3_SECBB22_Msk /*!< Page 86 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB23_Pos (23U) +#define FLASH_SECBBR3_SECBB23_Msk (0x1UL << FLASH_SECBBR3_SECBB23_Pos) /*!< 0x00800000 */ +#define FLASH_SECBBR3_SECBB23 FLASH_SECBBR3_SECBB23_Msk /*!< Page 87 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB24_Pos (24U) +#define FLASH_SECBBR3_SECBB24_Msk (0x1UL << FLASH_SECBBR3_SECBB24_Pos) /*!< 0x01000000 */ +#define FLASH_SECBBR3_SECBB24 FLASH_SECBBR3_SECBB24_Msk /*!< Page 88 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB25_Pos (25U) +#define FLASH_SECBBR3_SECBB25_Msk (0x1UL << FLASH_SECBBR3_SECBB25_Pos) /*!< 0x02000000 */ +#define FLASH_SECBBR3_SECBB25 FLASH_SECBBR3_SECBB25_Msk /*!< Page 89 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB26_Pos (26U) +#define FLASH_SECBBR3_SECBB26_Msk (0x1UL << FLASH_SECBBR3_SECBB26_Pos) /*!< 0x04000000 */ +#define FLASH_SECBBR3_SECBB26 FLASH_SECBBR3_SECBB26_Msk /*!< Page 90 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB27_Pos (27U) +#define FLASH_SECBBR3_SECBB27_Msk (0x1UL << FLASH_SECBBR3_SECBB27_Pos) /*!< 0x08000000 */ +#define FLASH_SECBBR3_SECBB27 FLASH_SECBBR3_SECBB27_Msk /*!< Page 91 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB28_Pos (28U) +#define FLASH_SECBBR3_SECBB28_Msk (0x1UL << FLASH_SECBBR3_SECBB28_Pos) /*!< 0x10000000 */ +#define FLASH_SECBBR3_SECBB28 FLASH_SECBBR3_SECBB28_Msk /*!< Page 92 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB29_Pos (29U) +#define FLASH_SECBBR3_SECBB29_Msk (0x1UL << FLASH_SECBBR3_SECBB29_Pos) /*!< 0x20000000 */ +#define FLASH_SECBBR3_SECBB29 FLASH_SECBBR3_SECBB29_Msk /*!< Page 93 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB30_Pos (30U) +#define FLASH_SECBBR3_SECBB30_Msk (0x1UL << FLASH_SECBBR3_SECBB30_Pos) /*!< 0x40000000 */ +#define FLASH_SECBBR3_SECBB30 FLASH_SECBBR3_SECBB30_Msk /*!< Page 94 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB31_Pos (31U) +#define FLASH_SECBBR3_SECBB31_Msk (0x1UL << FLASH_SECBBR3_SECBB31_Pos) /*!< 0x80000000 */ +#define FLASH_SECBBR3_SECBB31 FLASH_SECBBR3_SECBB31_Msk /*!< Page 95 in Flash block-based secure */ + +/******************* Bit definition for FLASH_SECBBR4 register ******************/ +#define FLASH_SECBBR4_SECBB0_Pos (0U) +#define FLASH_SECBBR4_SECBB0_Msk (0x1UL << FLASH_SECBBR4_SECBB0_Pos) /*!< 0x00000001 */ +#define FLASH_SECBBR4_SECBB0 FLASH_SECBBR4_SECBB0_Msk /*!< Page 96 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB1_Pos (1U) +#define FLASH_SECBBR4_SECBB1_Msk (0x1UL << FLASH_SECBBR4_SECBB1_Pos) /*!< 0x00000002 */ +#define FLASH_SECBBR4_SECBB1 FLASH_SECBBR4_SECBB1_Msk /*!< Page 97 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB2_Pos (2U) +#define FLASH_SECBBR4_SECBB2_Msk (0x1UL << FLASH_SECBBR4_SECBB2_Pos) /*!< 0x00000004 */ +#define FLASH_SECBBR4_SECBB2 FLASH_SECBBR4_SECBB2_Msk /*!< Page 98 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB3_Pos (3U) +#define FLASH_SECBBR4_SECBB3_Msk (0x1UL << FLASH_SECBBR4_SECBB3_Pos) /*!< 0x00000008 */ +#define FLASH_SECBBR4_SECBB3 FLASH_SECBBR4_SECBB3_Msk /*!< Page 99 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB4_Pos (4U) +#define FLASH_SECBBR4_SECBB4_Msk (0x1UL << FLASH_SECBBR4_SECBB4_Pos) /*!< 0x00000010 */ +#define FLASH_SECBBR4_SECBB4 FLASH_SECBBR4_SECBB4_Msk /*!< Page 100 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB5_Pos (5U) +#define FLASH_SECBBR4_SECBB5_Msk (0x1UL << FLASH_SECBBR4_SECBB5_Pos) /*!< 0x00000020 */ +#define FLASH_SECBBR4_SECBB5 FLASH_SECBBR4_SECBB5_Msk /*!< Page 101 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB6_Pos (6U) +#define FLASH_SECBBR4_SECBB6_Msk (0x1UL << FLASH_SECBBR4_SECBB6_Pos) /*!< 0x00000040 */ +#define FLASH_SECBBR4_SECBB6 FLASH_SECBBR4_SECBB6_Msk /*!< Page 102 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB7_Pos (7U) +#define FLASH_SECBBR4_SECBB7_Msk (0x1UL << FLASH_SECBBR4_SECBB7_Pos) /*!< 0x00000080 */ +#define FLASH_SECBBR4_SECBB7 FLASH_SECBBR4_SECBB7_Msk /*!< Page 103 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB8_Pos (8U) +#define FLASH_SECBBR4_SECBB8_Msk (0x1UL << FLASH_SECBBR4_SECBB8_Pos) /*!< 0x00000100 */ +#define FLASH_SECBBR4_SECBB8 FLASH_SECBBR4_SECBB8_Msk /*!< Page 104 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB9_Pos (9U) +#define FLASH_SECBBR4_SECBB9_Msk (0x1UL << FLASH_SECBBR4_SECBB9_Pos) /*!< 0x00000200 */ +#define FLASH_SECBBR4_SECBB9 FLASH_SECBBR4_SECBB9_Msk /*!< Page 105 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB10_Pos (10U) +#define FLASH_SECBBR4_SECBB10_Msk (0x1UL << FLASH_SECBBR4_SECBB10_Pos) /*!< 0x00000400 */ +#define FLASH_SECBBR4_SECBB10 FLASH_SECBBR4_SECBB10_Msk /*!< Page 106 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB11_Pos (11U) +#define FLASH_SECBBR4_SECBB11_Msk (0x1UL << FLASH_SECBBR4_SECBB11_Pos) /*!< 0x00000800 */ +#define FLASH_SECBBR4_SECBB11 FLASH_SECBBR4_SECBB11_Msk /*!< Page 107 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB12_Pos (12U) +#define FLASH_SECBBR4_SECBB12_Msk (0x1UL << FLASH_SECBBR4_SECBB12_Pos) /*!< 0x00001000 */ +#define FLASH_SECBBR4_SECBB12 FLASH_SECBBR4_SECBB12_Msk /*!< Page 108 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB13_Pos (13U) +#define FLASH_SECBBR4_SECBB13_Msk (0x1UL << FLASH_SECBBR4_SECBB13_Pos) /*!< 0x00002000 */ +#define FLASH_SECBBR4_SECBB13 FLASH_SECBBR4_SECBB13_Msk /*!< Page 109 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB14_Pos (14U) +#define FLASH_SECBBR4_SECBB14_Msk (0x1UL << FLASH_SECBBR4_SECBB14_Pos) /*!< 0x00004000 */ +#define FLASH_SECBBR4_SECBB14 FLASH_SECBBR4_SECBB14_Msk /*!< Page 110 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB15_Pos (15U) +#define FLASH_SECBBR4_SECBB15_Msk (0x1UL << FLASH_SECBBR4_SECBB15_Pos) /*!< 0x00008000 */ +#define FLASH_SECBBR4_SECBB15 FLASH_SECBBR4_SECBB15_Msk /*!< Page 111 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB16_Pos (16U) +#define FLASH_SECBBR4_SECBB16_Msk (0x1UL << FLASH_SECBBR4_SECBB16_Pos) /*!< 0x00010000 */ +#define FLASH_SECBBR4_SECBB16 FLASH_SECBBR4_SECBB16_Msk /*!< Page 112 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB17_Pos (17U) +#define FLASH_SECBBR4_SECBB17_Msk (0x1UL << FLASH_SECBBR4_SECBB17_Pos) /*!< 0x00020000 */ +#define FLASH_SECBBR4_SECBB17 FLASH_SECBBR4_SECBB17_Msk /*!< Page 113 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB18_Pos (18U) +#define FLASH_SECBBR4_SECBB18_Msk (0x1UL << FLASH_SECBBR4_SECBB18_Pos) /*!< 0x00040000 */ +#define FLASH_SECBBR4_SECBB18 FLASH_SECBBR4_SECBB18_Msk /*!< Page 114 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB19_Pos (19U) +#define FLASH_SECBBR4_SECBB19_Msk (0x1UL << FLASH_SECBBR4_SECBB19_Pos) /*!< 0x00080000 */ +#define FLASH_SECBBR4_SECBB19 FLASH_SECBBR4_SECBB19_Msk /*!< Page 115 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB20_Pos (20U) +#define FLASH_SECBBR4_SECBB20_Msk (0x1UL << FLASH_SECBBR4_SECBB20_Pos) /*!< 0x00100000 */ +#define FLASH_SECBBR4_SECBB20 FLASH_SECBBR4_SECBB20_Msk /*!< Page 116 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB21_Pos (21U) +#define FLASH_SECBBR4_SECBB21_Msk (0x1UL << FLASH_SECBBR4_SECBB21_Pos) /*!< 0x00200000 */ +#define FLASH_SECBBR4_SECBB21 FLASH_SECBBR4_SECBB21_Msk /*!< Page 117 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB22_Pos (22U) +#define FLASH_SECBBR4_SECBB22_Msk (0x1UL << FLASH_SECBBR4_SECBB22_Pos) /*!< 0x00400000 */ +#define FLASH_SECBBR4_SECBB22 FLASH_SECBBR4_SECBB22_Msk /*!< Page 118 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB23_Pos (23U) +#define FLASH_SECBBR4_SECBB23_Msk (0x1UL << FLASH_SECBBR4_SECBB23_Pos) /*!< 0x00800000 */ +#define FLASH_SECBBR4_SECBB23 FLASH_SECBBR4_SECBB23_Msk /*!< Page 119 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB24_Pos (24U) +#define FLASH_SECBBR4_SECBB24_Msk (0x1UL << FLASH_SECBBR4_SECBB24_Pos) /*!< 0x01000000 */ +#define FLASH_SECBBR4_SECBB24 FLASH_SECBBR4_SECBB24_Msk /*!< Page 120 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB25_Pos (25U) +#define FLASH_SECBBR4_SECBB25_Msk (0x1UL << FLASH_SECBBR4_SECBB25_Pos) /*!< 0x02000000 */ +#define FLASH_SECBBR4_SECBB25 FLASH_SECBBR4_SECBB25_Msk /*!< Page 121 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB26_Pos (26U) +#define FLASH_SECBBR4_SECBB26_Msk (0x1UL << FLASH_SECBBR4_SECBB26_Pos) /*!< 0x04000000 */ +#define FLASH_SECBBR4_SECBB26 FLASH_SECBBR4_SECBB26_Msk /*!< Page 122 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB27_Pos (27U) +#define FLASH_SECBBR4_SECBB27_Msk (0x1UL << FLASH_SECBBR4_SECBB27_Pos) /*!< 0x08000000 */ +#define FLASH_SECBBR4_SECBB27 FLASH_SECBBR4_SECBB27_Msk /*!< Page 123 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB28_Pos (28U) +#define FLASH_SECBBR4_SECBB28_Msk (0x1UL << FLASH_SECBBR4_SECBB28_Pos) /*!< 0x10000000 */ +#define FLASH_SECBBR4_SECBB28 FLASH_SECBBR4_SECBB28_Msk /*!< Page 124 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB29_Pos (29U) +#define FLASH_SECBBR4_SECBB29_Msk (0x1UL << FLASH_SECBBR4_SECBB29_Pos) /*!< 0x20000000 */ +#define FLASH_SECBBR4_SECBB29 FLASH_SECBBR4_SECBB29_Msk /*!< Page 125 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB30_Pos (30U) +#define FLASH_SECBBR4_SECBB30_Msk (0x1UL << FLASH_SECBBR4_SECBB30_Pos) /*!< 0x40000000 */ +#define FLASH_SECBBR4_SECBB30 FLASH_SECBBR4_SECBB30_Msk /*!< Page 126 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB31_Pos (31U) +#define FLASH_SECBBR4_SECBB31_Msk (0x1UL << FLASH_SECBBR4_SECBB31_Pos) /*!< 0x80000000 */ +#define FLASH_SECBBR4_SECBB31 FLASH_SECBBR4_SECBB31_Msk /*!< Page 127 in Flash block-based secure */ + +/****************** Bits definition for FLASH_SECHDPCR register ***********/ +#define FLASH_SECHDPCR_HDP_ACCDIS_Pos (0U) +#define FLASH_SECHDPCR_HDP_ACCDIS_Msk (0x1UL << FLASH_SECHDPCR_HDP_ACCDIS_Pos) /*!< 0x00000001 */ +#define FLASH_SECHDPCR_HDP_ACCDIS FLASH_SECHDPCR_HDP_ACCDIS_Msk /*!< HDP area access disable */ + +/****************** Bits definition for FLASH_PRIVCFGR register ***********/ +#define FLASH_PRIVCFGR_SPRIV_Pos (0U) +#define FLASH_PRIVCFGR_SPRIV_Msk (0x1UL << FLASH_PRIVCFGR_SPRIV_Pos) /*!< 0x00000001 */ +#define FLASH_PRIVCFGR_SPRIV FLASH_PRIVCFGR_SPRIV_Msk /*!< Privilege protection for secure registers */ +#define FLASH_PRIVCFGR_NSPRIV_Pos (1U) +#define FLASH_PRIVCFGR_NSPRIV_Msk (0x1UL << FLASH_PRIVCFGR_NSPRIV_Pos) /*!< 0x00000002 */ +#define FLASH_PRIVCFGR_NSPRIV FLASH_PRIVCFGR_NSPRIV_Msk /*!< Privilege protection for non-secure registers */ + +/******************* Bit definition for FLASH_PRIVBBR1 register ******************/ +#define FLASH_PRIVBBR1_PRIVBB0_Pos (0U) +#define FLASH_PRIVBBR1_PRIVBB0_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB0_Pos) /*!< 0x00000001 */ +#define FLASH_PRIVBBR1_PRIVBB0 FLASH_PRIVBBR1_PRIVBB0_Msk /*!< Page 0 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB1_Pos (1U) +#define FLASH_PRIVBBR1_PRIVBB1_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB1_Pos) /*!< 0x00000002 */ +#define FLASH_PRIVBBR1_PRIVBB1 FLASH_PRIVBBR1_PRIVBB1_Msk /*!< Page 1 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB2_Pos (2U) +#define FLASH_PRIVBBR1_PRIVBB2_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB2_Pos) /*!< 0x00000004 */ +#define FLASH_PRIVBBR1_PRIVBB2 FLASH_PRIVBBR1_PRIVBB2_Msk /*!< Page 2 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB3_Pos (3U) +#define FLASH_PRIVBBR1_PRIVBB3_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB3_Pos) /*!< 0x00000008 */ +#define FLASH_PRIVBBR1_PRIVBB3 FLASH_PRIVBBR1_PRIVBB3_Msk /*!< Page 3 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB4_Pos (4U) +#define FLASH_PRIVBBR1_PRIVBB4_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB4_Pos) /*!< 0x00000010 */ +#define FLASH_PRIVBBR1_PRIVBB4 FLASH_PRIVBBR1_PRIVBB4_Msk /*!< Page 4 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB5_Pos (5U) +#define FLASH_PRIVBBR1_PRIVBB5_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB5_Pos) /*!< 0x00000020 */ +#define FLASH_PRIVBBR1_PRIVBB5 FLASH_PRIVBBR1_PRIVBB5_Msk /*!< Page 5 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB6_Pos (6U) +#define FLASH_PRIVBBR1_PRIVBB6_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB6_Pos) /*!< 0x00000040 */ +#define FLASH_PRIVBBR1_PRIVBB6 FLASH_PRIVBBR1_PRIVBB6_Msk /*!< Page 6 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB7_Pos (7U) +#define FLASH_PRIVBBR1_PRIVBB7_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB7_Pos) /*!< 0x00000080 */ +#define FLASH_PRIVBBR1_PRIVBB7 FLASH_PRIVBBR1_PRIVBB7_Msk /*!< Page 7 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB8_Pos (8U) +#define FLASH_PRIVBBR1_PRIVBB8_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB8_Pos) /*!< 0x00000100 */ +#define FLASH_PRIVBBR1_PRIVBB8 FLASH_PRIVBBR1_PRIVBB8_Msk /*!< Page 8 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB9_Pos (9U) +#define FLASH_PRIVBBR1_PRIVBB9_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB9_Pos) /*!< 0x00000200 */ +#define FLASH_PRIVBBR1_PRIVBB9 FLASH_PRIVBBR1_PRIVBB9_Msk /*!< Page 9 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB10_Pos (10U) +#define FLASH_PRIVBBR1_PRIVBB10_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB10_Pos) /*!< 0x00000400 */ +#define FLASH_PRIVBBR1_PRIVBB10 FLASH_PRIVBBR1_PRIVBB10_Msk /*!< Page 10 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB11_Pos (11U) +#define FLASH_PRIVBBR1_PRIVBB11_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB11_Pos) /*!< 0x00000800 */ +#define FLASH_PRIVBBR1_PRIVBB11 FLASH_PRIVBBR1_PRIVBB11_Msk /*!< Page 11 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB12_Pos (12U) +#define FLASH_PRIVBBR1_PRIVBB12_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB12_Pos) /*!< 0x00001000 */ +#define FLASH_PRIVBBR1_PRIVBB12 FLASH_PRIVBBR1_PRIVBB12_Msk /*!< Page 12 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB13_Pos (13U) +#define FLASH_PRIVBBR1_PRIVBB13_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB13_Pos) /*!< 0x00002000 */ +#define FLASH_PRIVBBR1_PRIVBB13 FLASH_PRIVBBR1_PRIVBB13_Msk /*!< Page 13 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB14_Pos (14U) +#define FLASH_PRIVBBR1_PRIVBB14_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB14_Pos) /*!< 0x00004000 */ +#define FLASH_PRIVBBR1_PRIVBB14 FLASH_PRIVBBR1_PRIVBB14_Msk /*!< Page 14 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB15_Pos (15U) +#define FLASH_PRIVBBR1_PRIVBB15_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB15_Pos) /*!< 0x00008000 */ +#define FLASH_PRIVBBR1_PRIVBB15 FLASH_PRIVBBR1_PRIVBB15_Msk /*!< Page 15 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB16_Pos (16U) +#define FLASH_PRIVBBR1_PRIVBB16_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB16_Pos) /*!< 0x00010000 */ +#define FLASH_PRIVBBR1_PRIVBB16 FLASH_PRIVBBR1_PRIVBB16_Msk /*!< Page 16 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB17_Pos (17U) +#define FLASH_PRIVBBR1_PRIVBB17_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB17_Pos) /*!< 0x00020000 */ +#define FLASH_PRIVBBR1_PRIVBB17 FLASH_PRIVBBR1_PRIVBB17_Msk /*!< Page 17 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB18_Pos (18U) +#define FLASH_PRIVBBR1_PRIVBB18_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB18_Pos) /*!< 0x00040000 */ +#define FLASH_PRIVBBR1_PRIVBB18 FLASH_PRIVBBR1_PRIVBB18_Msk /*!< Page 18 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB19_Pos (19U) +#define FLASH_PRIVBBR1_PRIVBB19_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB19_Pos) /*!< 0x00080000 */ +#define FLASH_PRIVBBR1_PRIVBB19 FLASH_PRIVBBR1_PRIVBB19_Msk /*!< Page 19 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB20_Pos (20U) +#define FLASH_PRIVBBR1_PRIVBB20_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB20_Pos) /*!< 0x00100000 */ +#define FLASH_PRIVBBR1_PRIVBB20 FLASH_PRIVBBR1_PRIVBB20_Msk /*!< Page 20 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB21_Pos (21U) +#define FLASH_PRIVBBR1_PRIVBB21_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB21_Pos) /*!< 0x00200000 */ +#define FLASH_PRIVBBR1_PRIVBB21 FLASH_PRIVBBR1_PRIVBB21_Msk /*!< Page 21 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB22_Pos (22U) +#define FLASH_PRIVBBR1_PRIVBB22_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB22_Pos) /*!< 0x00400000 */ +#define FLASH_PRIVBBR1_PRIVBB22 FLASH_PRIVBBR1_PRIVBB22_Msk /*!< Page 22 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB23_Pos (23U) +#define FLASH_PRIVBBR1_PRIVBB23_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB23_Pos) /*!< 0x00800000 */ +#define FLASH_PRIVBBR1_PRIVBB23 FLASH_PRIVBBR1_PRIVBB23_Msk /*!< Page 23 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB24_Pos (24U) +#define FLASH_PRIVBBR1_PRIVBB24_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB24_Pos) /*!< 0x01000000 */ +#define FLASH_PRIVBBR1_PRIVBB24 FLASH_PRIVBBR1_PRIVBB24_Msk /*!< Page 24 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB25_Pos (25U) +#define FLASH_PRIVBBR1_PRIVBB25_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB25_Pos) /*!< 0x02000000 */ +#define FLASH_PRIVBBR1_PRIVBB25 FLASH_PRIVBBR1_PRIVBB25_Msk /*!< Page 25 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB26_Pos (26U) +#define FLASH_PRIVBBR1_PRIVBB26_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB26_Pos) /*!< 0x04000000 */ +#define FLASH_PRIVBBR1_PRIVBB26 FLASH_PRIVBBR1_PRIVBB26_Msk /*!< Page 26 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB27_Pos (27U) +#define FLASH_PRIVBBR1_PRIVBB27_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB27_Pos) /*!< 0x08000000 */ +#define FLASH_PRIVBBR1_PRIVBB27 FLASH_PRIVBBR1_PRIVBB27_Msk /*!< Page 27 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB28_Pos (28U) +#define FLASH_PRIVBBR1_PRIVBB28_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB28_Pos) /*!< 0x10000000 */ +#define FLASH_PRIVBBR1_PRIVBB28 FLASH_PRIVBBR1_PRIVBB28_Msk /*!< Page 28 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB29_Pos (29U) +#define FLASH_PRIVBBR1_PRIVBB29_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB29_Pos) /*!< 0x20000000 */ +#define FLASH_PRIVBBR1_PRIVBB29 FLASH_PRIVBBR1_PRIVBB29_Msk /*!< Page 29 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB30_Pos (30U) +#define FLASH_PRIVBBR1_PRIVBB30_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB30_Pos) /*!< 0x40000000 */ +#define FLASH_PRIVBBR1_PRIVBB30 FLASH_PRIVBBR1_PRIVBB30_Msk /*!< Page 30 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB31_Pos (31U) +#define FLASH_PRIVBBR1_PRIVBB31_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB31_Pos) /*!< 0x80000000 */ +#define FLASH_PRIVBBR1_PRIVBB31 FLASH_PRIVBBR1_PRIVBB31_Msk /*!< Page 31 in Flash only accessible by privileged access */ + +/******************* Bit definition for FLASH_PRIVBBR2 register ******************/ +#define FLASH_PRIVBBR2_PRIVBB0_Pos (0U) +#define FLASH_PRIVBBR2_PRIVBB0_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB0_Pos) /*!< 0x00000001 */ +#define FLASH_PRIVBBR2_PRIVBB0 FLASH_PRIVBBR2_PRIVBB0_Msk /*!< Page 32 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB1_Pos (1U) +#define FLASH_PRIVBBR2_PRIVBB1_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB1_Pos) /*!< 0x00000002 */ +#define FLASH_PRIVBBR2_PRIVBB1 FLASH_PRIVBBR2_PRIVBB1_Msk /*!< Page 33 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB2_Pos (2U) +#define FLASH_PRIVBBR2_PRIVBB2_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB2_Pos) /*!< 0x00000004 */ +#define FLASH_PRIVBBR2_PRIVBB2 FLASH_PRIVBBR2_PRIVBB2_Msk /*!< Page 34 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB3_Pos (3U) +#define FLASH_PRIVBBR2_PRIVBB3_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB3_Pos) /*!< 0x00000008 */ +#define FLASH_PRIVBBR2_PRIVBB3 FLASH_PRIVBBR2_PRIVBB3_Msk /*!< Page 35 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB4_Pos (4U) +#define FLASH_PRIVBBR2_PRIVBB4_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB4_Pos) /*!< 0x00000010 */ +#define FLASH_PRIVBBR2_PRIVBB4 FLASH_PRIVBBR2_PRIVBB4_Msk /*!< Page 36 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB5_Pos (5U) +#define FLASH_PRIVBBR2_PRIVBB5_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB5_Pos) /*!< 0x00000020 */ +#define FLASH_PRIVBBR2_PRIVBB5 FLASH_PRIVBBR2_PRIVBB5_Msk /*!< Page 37 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB6_Pos (6U) +#define FLASH_PRIVBBR2_PRIVBB6_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB6_Pos) /*!< 0x00000040 */ +#define FLASH_PRIVBBR2_PRIVBB6 FLASH_PRIVBBR2_PRIVBB6_Msk /*!< Page 38 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB7_Pos (7U) +#define FLASH_PRIVBBR2_PRIVBB7_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB7_Pos) /*!< 0x00000080 */ +#define FLASH_PRIVBBR2_PRIVBB7 FLASH_PRIVBBR2_PRIVBB7_Msk /*!< Page 39 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB8_Pos (8U) +#define FLASH_PRIVBBR2_PRIVBB8_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB8_Pos) /*!< 0x00000100 */ +#define FLASH_PRIVBBR2_PRIVBB8 FLASH_PRIVBBR2_PRIVBB8_Msk /*!< Page 40 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB9_Pos (9U) +#define FLASH_PRIVBBR2_PRIVBB9_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB9_Pos) /*!< 0x00000200 */ +#define FLASH_PRIVBBR2_PRIVBB9 FLASH_PRIVBBR2_PRIVBB9_Msk /*!< Page 41 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB10_Pos (10U) +#define FLASH_PRIVBBR2_PRIVBB10_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB10_Pos) /*!< 0x00000400 */ +#define FLASH_PRIVBBR2_PRIVBB10 FLASH_PRIVBBR2_PRIVBB10_Msk /*!< Page 42 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB11_Pos (11U) +#define FLASH_PRIVBBR2_PRIVBB11_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB11_Pos) /*!< 0x00000800 */ +#define FLASH_PRIVBBR2_PRIVBB11 FLASH_PRIVBBR2_PRIVBB11_Msk /*!< Page 43 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB12_Pos (12U) +#define FLASH_PRIVBBR2_PRIVBB12_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB12_Pos) /*!< 0x00001000 */ +#define FLASH_PRIVBBR2_PRIVBB12 FLASH_PRIVBBR2_PRIVBB12_Msk /*!< Page 44 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB13_Pos (13U) +#define FLASH_PRIVBBR2_PRIVBB13_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB13_Pos) /*!< 0x00002000 */ +#define FLASH_PRIVBBR2_PRIVBB13 FLASH_PRIVBBR2_PRIVBB13_Msk /*!< Page 45 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB14_Pos (14U) +#define FLASH_PRIVBBR2_PRIVBB14_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB14_Pos) /*!< 0x00004000 */ +#define FLASH_PRIVBBR2_PRIVBB14 FLASH_PRIVBBR2_PRIVBB14_Msk /*!< Page 46 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB15_Pos (15U) +#define FLASH_PRIVBBR2_PRIVBB15_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB15_Pos) /*!< 0x00008000 */ +#define FLASH_PRIVBBR2_PRIVBB15 FLASH_PRIVBBR2_PRIVBB15_Msk /*!< Page 47 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB16_Pos (16U) +#define FLASH_PRIVBBR2_PRIVBB16_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB16_Pos) /*!< 0x00010000 */ +#define FLASH_PRIVBBR2_PRIVBB16 FLASH_PRIVBBR2_PRIVBB16_Msk /*!< Page 48 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB17_Pos (17U) +#define FLASH_PRIVBBR2_PRIVBB17_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB17_Pos) /*!< 0x00020000 */ +#define FLASH_PRIVBBR2_PRIVBB17 FLASH_PRIVBBR2_PRIVBB17_Msk /*!< Page 49 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB18_Pos (18U) +#define FLASH_PRIVBBR2_PRIVBB18_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB18_Pos) /*!< 0x00040000 */ +#define FLASH_PRIVBBR2_PRIVBB18 FLASH_PRIVBBR2_PRIVBB18_Msk /*!< Page 50 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB19_Pos (19U) +#define FLASH_PRIVBBR2_PRIVBB19_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB19_Pos) /*!< 0x00080000 */ +#define FLASH_PRIVBBR2_PRIVBB19 FLASH_PRIVBBR2_PRIVBB19_Msk /*!< Page 51 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB20_Pos (20U) +#define FLASH_PRIVBBR2_PRIVBB20_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB20_Pos) /*!< 0x00100000 */ +#define FLASH_PRIVBBR2_PRIVBB20 FLASH_PRIVBBR2_PRIVBB20_Msk /*!< Page 52 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB21_Pos (21U) +#define FLASH_PRIVBBR2_PRIVBB21_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB21_Pos) /*!< 0x00200000 */ +#define FLASH_PRIVBBR2_PRIVBB21 FLASH_PRIVBBR2_PRIVBB21_Msk /*!< Page 53 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB22_Pos (22U) +#define FLASH_PRIVBBR2_PRIVBB22_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB22_Pos) /*!< 0x00400000 */ +#define FLASH_PRIVBBR2_PRIVBB22 FLASH_PRIVBBR2_PRIVBB22_Msk /*!< Page 54 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB23_Pos (23U) +#define FLASH_PRIVBBR2_PRIVBB23_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB23_Pos) /*!< 0x00800000 */ +#define FLASH_PRIVBBR2_PRIVBB23 FLASH_PRIVBBR2_PRIVBB23_Msk /*!< Page 55 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB24_Pos (24U) +#define FLASH_PRIVBBR2_PRIVBB24_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB24_Pos) /*!< 0x01000000 */ +#define FLASH_PRIVBBR2_PRIVBB24 FLASH_PRIVBBR2_PRIVBB24_Msk /*!< Page 56 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB25_Pos (25U) +#define FLASH_PRIVBBR2_PRIVBB25_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB25_Pos) /*!< 0x02000000 */ +#define FLASH_PRIVBBR2_PRIVBB25 FLASH_PRIVBBR2_PRIVBB25_Msk /*!< Page 57 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB26_Pos (26U) +#define FLASH_PRIVBBR2_PRIVBB26_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB26_Pos) /*!< 0x04000000 */ +#define FLASH_PRIVBBR2_PRIVBB26 FLASH_PRIVBBR2_PRIVBB26_Msk /*!< Page 58 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB27_Pos (27U) +#define FLASH_PRIVBBR2_PRIVBB27_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB27_Pos) /*!< 0x08000000 */ +#define FLASH_PRIVBBR2_PRIVBB27 FLASH_PRIVBBR2_PRIVBB27_Msk /*!< Page 59 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB28_Pos (28U) +#define FLASH_PRIVBBR2_PRIVBB28_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB28_Pos) /*!< 0x10000000 */ +#define FLASH_PRIVBBR2_PRIVBB28 FLASH_PRIVBBR2_PRIVBB28_Msk /*!< Page 60 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB29_Pos (29U) +#define FLASH_PRIVBBR2_PRIVBB29_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB29_Pos) /*!< 0x20000000 */ +#define FLASH_PRIVBBR2_PRIVBB29 FLASH_PRIVBBR2_PRIVBB29_Msk /*!< Page 61 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB30_Pos (30U) +#define FLASH_PRIVBBR2_PRIVBB30_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB30_Pos) /*!< 0x40000000 */ +#define FLASH_PRIVBBR2_PRIVBB30 FLASH_PRIVBBR2_PRIVBB30_Msk /*!< Page 62 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB31_Pos (31U) +#define FLASH_PRIVBBR2_PRIVBB31_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB31_Pos) /*!< 0x80000000 */ +#define FLASH_PRIVBBR2_PRIVBB31 FLASH_PRIVBBR2_PRIVBB31_Msk /*!< Page 63 in Flash only accessible by privileged access */ + +/******************* Bit definition for FLASH_PRIVBBR3 register ******************/ +#define FLASH_PRIVBBR3_PRIVBB0_Pos (0U) +#define FLASH_PRIVBBR3_PRIVBB0_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB0_Pos) /*!< 0x00000001 */ +#define FLASH_PRIVBBR3_PRIVBB0 FLASH_PRIVBBR3_PRIVBB0_Msk /*!< Page 64 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB1_Pos (1U) +#define FLASH_PRIVBBR3_PRIVBB1_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB1_Pos) /*!< 0x00000002 */ +#define FLASH_PRIVBBR3_PRIVBB1 FLASH_PRIVBBR3_PRIVBB1_Msk /*!< Page 65 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB2_Pos (2U) +#define FLASH_PRIVBBR3_PRIVBB2_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB2_Pos) /*!< 0x00000004 */ +#define FLASH_PRIVBBR3_PRIVBB2 FLASH_PRIVBBR3_PRIVBB2_Msk /*!< Page 66 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB3_Pos (3U) +#define FLASH_PRIVBBR3_PRIVBB3_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB3_Pos) /*!< 0x00000008 */ +#define FLASH_PRIVBBR3_PRIVBB3 FLASH_PRIVBBR3_PRIVBB3_Msk /*!< Page 67 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB4_Pos (4U) +#define FLASH_PRIVBBR3_PRIVBB4_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB4_Pos) /*!< 0x00000010 */ +#define FLASH_PRIVBBR3_PRIVBB4 FLASH_PRIVBBR3_PRIVBB4_Msk /*!< Page 68 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB5_Pos (5U) +#define FLASH_PRIVBBR3_PRIVBB5_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB5_Pos) /*!< 0x00000020 */ +#define FLASH_PRIVBBR3_PRIVBB5 FLASH_PRIVBBR3_PRIVBB5_Msk /*!< Page 69 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB6_Pos (6U) +#define FLASH_PRIVBBR3_PRIVBB6_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB6_Pos) /*!< 0x00000040 */ +#define FLASH_PRIVBBR3_PRIVBB6 FLASH_PRIVBBR3_PRIVBB6_Msk /*!< Page 70 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB7_Pos (7U) +#define FLASH_PRIVBBR3_PRIVBB7_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB7_Pos) /*!< 0x00000080 */ +#define FLASH_PRIVBBR3_PRIVBB7 FLASH_PRIVBBR3_PRIVBB7_Msk /*!< Page 71 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB8_Pos (8U) +#define FLASH_PRIVBBR3_PRIVBB8_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB8_Pos) /*!< 0x00000100 */ +#define FLASH_PRIVBBR3_PRIVBB8 FLASH_PRIVBBR3_PRIVBB8_Msk /*!< Page 72 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB9_Pos (9U) +#define FLASH_PRIVBBR3_PRIVBB9_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB9_Pos) /*!< 0x00000200 */ +#define FLASH_PRIVBBR3_PRIVBB9 FLASH_PRIVBBR3_PRIVBB9_Msk /*!< Page 73 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB10_Pos (10U) +#define FLASH_PRIVBBR3_PRIVBB10_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB10_Pos) /*!< 0x00000400 */ +#define FLASH_PRIVBBR3_PRIVBB10 FLASH_PRIVBBR3_PRIVBB10_Msk /*!< Page 74 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB11_Pos (11U) +#define FLASH_PRIVBBR3_PRIVBB11_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB11_Pos) /*!< 0x00000800 */ +#define FLASH_PRIVBBR3_PRIVBB11 FLASH_PRIVBBR3_PRIVBB11_Msk /*!< Page 75 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB12_Pos (12U) +#define FLASH_PRIVBBR3_PRIVBB12_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB12_Pos) /*!< 0x00001000 */ +#define FLASH_PRIVBBR3_PRIVBB12 FLASH_PRIVBBR3_PRIVBB12_Msk /*!< Page 76 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB13_Pos (13U) +#define FLASH_PRIVBBR3_PRIVBB13_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB13_Pos) /*!< 0x00002000 */ +#define FLASH_PRIVBBR3_PRIVBB13 FLASH_PRIVBBR3_PRIVBB13_Msk /*!< Page 77 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB14_Pos (14U) +#define FLASH_PRIVBBR3_PRIVBB14_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB14_Pos) /*!< 0x00004000 */ +#define FLASH_PRIVBBR3_PRIVBB14 FLASH_PRIVBBR3_PRIVBB14_Msk /*!< Page 78 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB15_Pos (15U) +#define FLASH_PRIVBBR3_PRIVBB15_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB15_Pos) /*!< 0x00008000 */ +#define FLASH_PRIVBBR3_PRIVBB15 FLASH_PRIVBBR3_PRIVBB15_Msk /*!< Page 79 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB16_Pos (16U) +#define FLASH_PRIVBBR3_PRIVBB16_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB16_Pos) /*!< 0x00010000 */ +#define FLASH_PRIVBBR3_PRIVBB16 FLASH_PRIVBBR3_PRIVBB16_Msk /*!< Page 80 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB17_Pos (17U) +#define FLASH_PRIVBBR3_PRIVBB17_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB17_Pos) /*!< 0x00020000 */ +#define FLASH_PRIVBBR3_PRIVBB17 FLASH_PRIVBBR3_PRIVBB17_Msk /*!< Page 81 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB18_Pos (18U) +#define FLASH_PRIVBBR3_PRIVBB18_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB18_Pos) /*!< 0x00040000 */ +#define FLASH_PRIVBBR3_PRIVBB18 FLASH_PRIVBBR3_PRIVBB18_Msk /*!< Page 82 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB19_Pos (19U) +#define FLASH_PRIVBBR3_PRIVBB19_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB19_Pos) /*!< 0x00080000 */ +#define FLASH_PRIVBBR3_PRIVBB19 FLASH_PRIVBBR3_PRIVBB19_Msk /*!< Page 83 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB20_Pos (20U) +#define FLASH_PRIVBBR3_PRIVBB20_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB20_Pos) /*!< 0x00100000 */ +#define FLASH_PRIVBBR3_PRIVBB20 FLASH_PRIVBBR3_PRIVBB20_Msk /*!< Page 84 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB21_Pos (21U) +#define FLASH_PRIVBBR3_PRIVBB21_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB21_Pos) /*!< 0x00200000 */ +#define FLASH_PRIVBBR3_PRIVBB21 FLASH_PRIVBBR3_PRIVBB21_Msk /*!< Page 85 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB22_Pos (22U) +#define FLASH_PRIVBBR3_PRIVBB22_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB22_Pos) /*!< 0x00400000 */ +#define FLASH_PRIVBBR3_PRIVBB22 FLASH_PRIVBBR3_PRIVBB22_Msk /*!< Page 86 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB23_Pos (23U) +#define FLASH_PRIVBBR3_PRIVBB23_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB23_Pos) /*!< 0x00800000 */ +#define FLASH_PRIVBBR3_PRIVBB23 FLASH_PRIVBBR3_PRIVBB23_Msk /*!< Page 87 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB24_Pos (24U) +#define FLASH_PRIVBBR3_PRIVBB24_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB24_Pos) /*!< 0x01000000 */ +#define FLASH_PRIVBBR3_PRIVBB24 FLASH_PRIVBBR3_PRIVBB24_Msk /*!< Page 88 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB25_Pos (25U) +#define FLASH_PRIVBBR3_PRIVBB25_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB25_Pos) /*!< 0x02000000 */ +#define FLASH_PRIVBBR3_PRIVBB25 FLASH_PRIVBBR3_PRIVBB25_Msk /*!< Page 89 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB26_Pos (26U) +#define FLASH_PRIVBBR3_PRIVBB26_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB26_Pos) /*!< 0x04000000 */ +#define FLASH_PRIVBBR3_PRIVBB26 FLASH_PRIVBBR3_PRIVBB26_Msk /*!< Page 90 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB27_Pos (27U) +#define FLASH_PRIVBBR3_PRIVBB27_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB27_Pos) /*!< 0x08000000 */ +#define FLASH_PRIVBBR3_PRIVBB27 FLASH_PRIVBBR3_PRIVBB27_Msk /*!< Page 91 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB28_Pos (28U) +#define FLASH_PRIVBBR3_PRIVBB28_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB28_Pos) /*!< 0x10000000 */ +#define FLASH_PRIVBBR3_PRIVBB28 FLASH_PRIVBBR3_PRIVBB28_Msk /*!< Page 92 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB29_Pos (29U) +#define FLASH_PRIVBBR3_PRIVBB29_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB29_Pos) /*!< 0x20000000 */ +#define FLASH_PRIVBBR3_PRIVBB29 FLASH_PRIVBBR3_PRIVBB29_Msk /*!< Page 93 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB30_Pos (30U) +#define FLASH_PRIVBBR3_PRIVBB30_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB30_Pos) /*!< 0x40000000 */ +#define FLASH_PRIVBBR3_PRIVBB30 FLASH_PRIVBBR3_PRIVBB30_Msk /*!< Page 94 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB31_Pos (31U) +#define FLASH_PRIVBBR3_PRIVBB31_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB31_Pos) /*!< 0x80000000 */ +#define FLASH_PRIVBBR3_PRIVBB31 FLASH_PRIVBBR3_PRIVBB31_Msk /*!< Page 95 in Flash only accessible by privileged access */ + +/******************* Bit definition for FLASH_PRIVBBR4 register ******************/ +#define FLASH_PRIVBBR4_PRIVBB0_Pos (0U) +#define FLASH_PRIVBBR4_PRIVBB0_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB0_Pos) /*!< 0x00000001 */ +#define FLASH_PRIVBBR4_PRIVBB0 FLASH_PRIVBBR4_PRIVBB0_Msk /*!< Page 96 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB1_Pos (1U) +#define FLASH_PRIVBBR4_PRIVBB1_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB1_Pos) /*!< 0x00000002 */ +#define FLASH_PRIVBBR4_PRIVBB1 FLASH_PRIVBBR4_PRIVBB1_Msk /*!< Page 97 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB2_Pos (2U) +#define FLASH_PRIVBBR4_PRIVBB2_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB2_Pos) /*!< 0x00000004 */ +#define FLASH_PRIVBBR4_PRIVBB2 FLASH_PRIVBBR4_PRIVBB2_Msk /*!< Page 98 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB3_Pos (3U) +#define FLASH_PRIVBBR4_PRIVBB3_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB3_Pos) /*!< 0x00000008 */ +#define FLASH_PRIVBBR4_PRIVBB3 FLASH_PRIVBBR4_PRIVBB3_Msk /*!< Page 99 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB4_Pos (4U) +#define FLASH_PRIVBBR4_PRIVBB4_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB4_Pos) /*!< 0x00000010 */ +#define FLASH_PRIVBBR4_PRIVBB4 FLASH_PRIVBBR4_PRIVBB4_Msk /*!< Page 100 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB5_Pos (5U) +#define FLASH_PRIVBBR4_PRIVBB5_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB5_Pos) /*!< 0x00000020 */ +#define FLASH_PRIVBBR4_PRIVBB5 FLASH_PRIVBBR4_PRIVBB5_Msk /*!< Page 101 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB6_Pos (6U) +#define FLASH_PRIVBBR4_PRIVBB6_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB6_Pos) /*!< 0x00000040 */ +#define FLASH_PRIVBBR4_PRIVBB6 FLASH_PRIVBBR4_PRIVBB6_Msk /*!< Page 102 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB7_Pos (7U) +#define FLASH_PRIVBBR4_PRIVBB7_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB7_Pos) /*!< 0x00000080 */ +#define FLASH_PRIVBBR4_PRIVBB7 FLASH_PRIVBBR4_PRIVBB7_Msk /*!< Page 103 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB8_Pos (8U) +#define FLASH_PRIVBBR4_PRIVBB8_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB8_Pos) /*!< 0x00000100 */ +#define FLASH_PRIVBBR4_PRIVBB8 FLASH_PRIVBBR4_PRIVBB8_Msk /*!< Page 104 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB9_Pos (9U) +#define FLASH_PRIVBBR4_PRIVBB9_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB9_Pos) /*!< 0x00000200 */ +#define FLASH_PRIVBBR4_PRIVBB9 FLASH_PRIVBBR4_PRIVBB9_Msk /*!< Page 105 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB10_Pos (10U) +#define FLASH_PRIVBBR4_PRIVBB10_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB10_Pos) /*!< 0x00000400 */ +#define FLASH_PRIVBBR4_PRIVBB10 FLASH_PRIVBBR4_PRIVBB10_Msk /*!< Page 106 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB11_Pos (11U) +#define FLASH_PRIVBBR4_PRIVBB11_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB11_Pos) /*!< 0x00000800 */ +#define FLASH_PRIVBBR4_PRIVBB11 FLASH_PRIVBBR4_PRIVBB11_Msk /*!< Page 107 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB12_Pos (12U) +#define FLASH_PRIVBBR4_PRIVBB12_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB12_Pos) /*!< 0x00001000 */ +#define FLASH_PRIVBBR4_PRIVBB12 FLASH_PRIVBBR4_PRIVBB12_Msk /*!< Page 108 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB13_Pos (13U) +#define FLASH_PRIVBBR4_PRIVBB13_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB13_Pos) /*!< 0x00002000 */ +#define FLASH_PRIVBBR4_PRIVBB13 FLASH_PRIVBBR4_PRIVBB13_Msk /*!< Page 109 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB14_Pos (14U) +#define FLASH_PRIVBBR4_PRIVBB14_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB14_Pos) /*!< 0x00004000 */ +#define FLASH_PRIVBBR4_PRIVBB14 FLASH_PRIVBBR4_PRIVBB14_Msk /*!< Page 110 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB15_Pos (15U) +#define FLASH_PRIVBBR4_PRIVBB15_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB15_Pos) /*!< 0x00008000 */ +#define FLASH_PRIVBBR4_PRIVBB15 FLASH_PRIVBBR4_PRIVBB15_Msk /*!< Page 111 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB16_Pos (16U) +#define FLASH_PRIVBBR4_PRIVBB16_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB16_Pos) /*!< 0x00010000 */ +#define FLASH_PRIVBBR4_PRIVBB16 FLASH_PRIVBBR4_PRIVBB16_Msk /*!< Page 112 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB17_Pos (17U) +#define FLASH_PRIVBBR4_PRIVBB17_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB17_Pos) /*!< 0x00020000 */ +#define FLASH_PRIVBBR4_PRIVBB17 FLASH_PRIVBBR4_PRIVBB17_Msk /*!< Page 113 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB18_Pos (18U) +#define FLASH_PRIVBBR4_PRIVBB18_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB18_Pos) /*!< 0x00040000 */ +#define FLASH_PRIVBBR4_PRIVBB18 FLASH_PRIVBBR4_PRIVBB18_Msk /*!< Page 114 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB19_Pos (19U) +#define FLASH_PRIVBBR4_PRIVBB19_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB19_Pos) /*!< 0x00080000 */ +#define FLASH_PRIVBBR4_PRIVBB19 FLASH_PRIVBBR4_PRIVBB19_Msk /*!< Page 115 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB20_Pos (20U) +#define FLASH_PRIVBBR4_PRIVBB20_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB20_Pos) /*!< 0x00100000 */ +#define FLASH_PRIVBBR4_PRIVBB20 FLASH_PRIVBBR4_PRIVBB20_Msk /*!< Page 116 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB21_Pos (21U) +#define FLASH_PRIVBBR4_PRIVBB21_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB21_Pos) /*!< 0x00200000 */ +#define FLASH_PRIVBBR4_PRIVBB21 FLASH_PRIVBBR4_PRIVBB21_Msk /*!< Page 117 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB22_Pos (22U) +#define FLASH_PRIVBBR4_PRIVBB22_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB22_Pos) /*!< 0x00400000 */ +#define FLASH_PRIVBBR4_PRIVBB22 FLASH_PRIVBBR4_PRIVBB22_Msk /*!< Page 118 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB23_Pos (23U) +#define FLASH_PRIVBBR4_PRIVBB23_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB23_Pos) /*!< 0x00800000 */ +#define FLASH_PRIVBBR4_PRIVBB23 FLASH_PRIVBBR4_PRIVBB23_Msk /*!< Page 119 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB24_Pos (24U) +#define FLASH_PRIVBBR4_PRIVBB24_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB24_Pos) /*!< 0x01000000 */ +#define FLASH_PRIVBBR4_PRIVBB24 FLASH_PRIVBBR4_PRIVBB24_Msk /*!< Page 120 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB25_Pos (25U) +#define FLASH_PRIVBBR4_PRIVBB25_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB25_Pos) /*!< 0x02000000 */ +#define FLASH_PRIVBBR4_PRIVBB25 FLASH_PRIVBBR4_PRIVBB25_Msk /*!< Page 121 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB26_Pos (26U) +#define FLASH_PRIVBBR4_PRIVBB26_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB26_Pos) /*!< 0x04000000 */ +#define FLASH_PRIVBBR4_PRIVBB26 FLASH_PRIVBBR4_PRIVBB26_Msk /*!< Page 122 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB27_Pos (27U) +#define FLASH_PRIVBBR4_PRIVBB27_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB27_Pos) /*!< 0x08000000 */ +#define FLASH_PRIVBBR4_PRIVBB27 FLASH_PRIVBBR4_PRIVBB27_Msk /*!< Page 123 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB28_Pos (28U) +#define FLASH_PRIVBBR4_PRIVBB28_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB28_Pos) /*!< 0x10000000 */ +#define FLASH_PRIVBBR4_PRIVBB28 FLASH_PRIVBBR4_PRIVBB28_Msk /*!< Page 124 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB29_Pos (29U) +#define FLASH_PRIVBBR4_PRIVBB29_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB29_Pos) /*!< 0x20000000 */ +#define FLASH_PRIVBBR4_PRIVBB29 FLASH_PRIVBBR4_PRIVBB29_Msk /*!< Page 125 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB30_Pos (30U) +#define FLASH_PRIVBBR4_PRIVBB30_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB30_Pos) /*!< 0x40000000 */ +#define FLASH_PRIVBBR4_PRIVBB30 FLASH_PRIVBBR4_PRIVBB30_Msk /*!< Page 126 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB31_Pos (31U) +#define FLASH_PRIVBBR4_PRIVBB31_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB31_Pos) /*!< 0x80000000 */ +#define FLASH_PRIVBBR4_PRIVBB31 FLASH_PRIVBBR4_PRIVBB31_Msk /*!< Page 127 in Flash only accessible by privileged access */ + +/******************************************************************************/ +/* */ +/* General Purpose IOs (GPIO) */ +/* */ +/******************************************************************************/ +/****************** Bits definition for GPIO_MODER register *****************/ +#define GPIO_MODER_MODE0_Pos (0U) +#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ +#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk +#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ +#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ +#define GPIO_MODER_MODE1_Pos (2U) +#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ +#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk +#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ +#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ +#define GPIO_MODER_MODE2_Pos (4U) +#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ +#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk +#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ +#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ +#define GPIO_MODER_MODE3_Pos (6U) +#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ +#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk +#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ +#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ +#define GPIO_MODER_MODE4_Pos (8U) +#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ +#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk +#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ +#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ +#define GPIO_MODER_MODE5_Pos (10U) +#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ +#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk +#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ +#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ +#define GPIO_MODER_MODE6_Pos (12U) +#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ +#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk +#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ +#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ +#define GPIO_MODER_MODE7_Pos (14U) +#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ +#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk +#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ +#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ +#define GPIO_MODER_MODE8_Pos (16U) +#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ +#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk +#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ +#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ +#define GPIO_MODER_MODE9_Pos (18U) +#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ +#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk +#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ +#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ +#define GPIO_MODER_MODE10_Pos (20U) +#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ +#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk +#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ +#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ +#define GPIO_MODER_MODE11_Pos (22U) +#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ +#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk +#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ +#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ +#define GPIO_MODER_MODE12_Pos (24U) +#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ +#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk +#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ +#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ +#define GPIO_MODER_MODE13_Pos (26U) +#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ +#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk +#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ +#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ +#define GPIO_MODER_MODE14_Pos (28U) +#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ +#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk +#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ +#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ +#define GPIO_MODER_MODE15_Pos (30U) +#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ +#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk +#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ +#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_OTYPER register ****************/ +#define GPIO_OTYPER_OT0_Pos (0U) +#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */ +#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk +#define GPIO_OTYPER_OT1_Pos (1U) +#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */ +#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk +#define GPIO_OTYPER_OT2_Pos (2U) +#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */ +#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk +#define GPIO_OTYPER_OT3_Pos (3U) +#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */ +#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk +#define GPIO_OTYPER_OT4_Pos (4U) +#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */ +#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk +#define GPIO_OTYPER_OT5_Pos (5U) +#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */ +#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk +#define GPIO_OTYPER_OT6_Pos (6U) +#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */ +#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk +#define GPIO_OTYPER_OT7_Pos (7U) +#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */ +#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk +#define GPIO_OTYPER_OT8_Pos (8U) +#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */ +#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk +#define GPIO_OTYPER_OT9_Pos (9U) +#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */ +#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk +#define GPIO_OTYPER_OT10_Pos (10U) +#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */ +#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk +#define GPIO_OTYPER_OT11_Pos (11U) +#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */ +#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk +#define GPIO_OTYPER_OT12_Pos (12U) +#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */ +#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk +#define GPIO_OTYPER_OT13_Pos (13U) +#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */ +#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk +#define GPIO_OTYPER_OT14_Pos (14U) +#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */ +#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk +#define GPIO_OTYPER_OT15_Pos (15U) +#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */ +#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk + +/****************** Bits definition for GPIO_OSPEEDR register ***************/ +#define GPIO_OSPEEDR_OSPEED0_Pos (0U) +#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */ +#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk +#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */ +#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */ +#define GPIO_OSPEEDR_OSPEED1_Pos (2U) +#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */ +#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk +#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */ +#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */ +#define GPIO_OSPEEDR_OSPEED2_Pos (4U) +#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */ +#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk +#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */ +#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */ +#define GPIO_OSPEEDR_OSPEED3_Pos (6U) +#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */ +#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk +#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */ +#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */ +#define GPIO_OSPEEDR_OSPEED4_Pos (8U) +#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */ +#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk +#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */ +#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */ +#define GPIO_OSPEEDR_OSPEED5_Pos (10U) +#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */ +#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk +#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */ +#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */ +#define GPIO_OSPEEDR_OSPEED6_Pos (12U) +#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */ +#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk +#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */ +#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */ +#define GPIO_OSPEEDR_OSPEED7_Pos (14U) +#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */ +#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk +#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */ +#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */ +#define GPIO_OSPEEDR_OSPEED8_Pos (16U) +#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */ +#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk +#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */ +#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */ +#define GPIO_OSPEEDR_OSPEED9_Pos (18U) +#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */ +#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk +#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */ +#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */ +#define GPIO_OSPEEDR_OSPEED10_Pos (20U) +#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */ +#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk +#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */ +#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */ +#define GPIO_OSPEEDR_OSPEED11_Pos (22U) +#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */ +#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk +#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */ +#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */ +#define GPIO_OSPEEDR_OSPEED12_Pos (24U) +#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */ +#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk +#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */ +#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */ +#define GPIO_OSPEEDR_OSPEED13_Pos (26U) +#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */ +#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk +#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */ +#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */ +#define GPIO_OSPEEDR_OSPEED14_Pos (28U) +#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */ +#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk +#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */ +#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */ +#define GPIO_OSPEEDR_OSPEED15_Pos (30U) +#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */ +#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk +#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */ +#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_PUPDR register *****************/ +#define GPIO_PUPDR_PUPD0_Pos (0U) +#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */ +#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk +#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */ +#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */ +#define GPIO_PUPDR_PUPD1_Pos (2U) +#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */ +#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk +#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */ +#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */ +#define GPIO_PUPDR_PUPD2_Pos (4U) +#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */ +#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk +#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */ +#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */ +#define GPIO_PUPDR_PUPD3_Pos (6U) +#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */ +#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk +#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */ +#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */ +#define GPIO_PUPDR_PUPD4_Pos (8U) +#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */ +#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk +#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */ +#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */ +#define GPIO_PUPDR_PUPD5_Pos (10U) +#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */ +#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk +#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */ +#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */ +#define GPIO_PUPDR_PUPD6_Pos (12U) +#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */ +#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk +#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */ +#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */ +#define GPIO_PUPDR_PUPD7_Pos (14U) +#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */ +#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk +#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */ +#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */ +#define GPIO_PUPDR_PUPD8_Pos (16U) +#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */ +#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk +#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */ +#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */ +#define GPIO_PUPDR_PUPD9_Pos (18U) +#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */ +#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk +#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */ +#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */ +#define GPIO_PUPDR_PUPD10_Pos (20U) +#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */ +#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk +#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */ +#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */ +#define GPIO_PUPDR_PUPD11_Pos (22U) +#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */ +#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk +#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */ +#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */ +#define GPIO_PUPDR_PUPD12_Pos (24U) +#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */ +#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk +#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */ +#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */ +#define GPIO_PUPDR_PUPD13_Pos (26U) +#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */ +#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk +#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */ +#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */ +#define GPIO_PUPDR_PUPD14_Pos (28U) +#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */ +#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk +#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */ +#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */ +#define GPIO_PUPDR_PUPD15_Pos (30U) +#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */ +#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk +#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */ +#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_IDR register *******************/ +#define GPIO_IDR_ID0_Pos (0U) +#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk +#define GPIO_IDR_ID1_Pos (1U) +#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk +#define GPIO_IDR_ID2_Pos (2U) +#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk +#define GPIO_IDR_ID3_Pos (3U) +#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk +#define GPIO_IDR_ID4_Pos (4U) +#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk +#define GPIO_IDR_ID5_Pos (5U) +#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk +#define GPIO_IDR_ID6_Pos (6U) +#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk +#define GPIO_IDR_ID7_Pos (7U) +#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk +#define GPIO_IDR_ID8_Pos (8U) +#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk +#define GPIO_IDR_ID9_Pos (9U) +#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk +#define GPIO_IDR_ID10_Pos (10U) +#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk +#define GPIO_IDR_ID11_Pos (11U) +#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk +#define GPIO_IDR_ID12_Pos (12U) +#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk +#define GPIO_IDR_ID13_Pos (13U) +#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk +#define GPIO_IDR_ID14_Pos (14U) +#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk +#define GPIO_IDR_ID15_Pos (15U) +#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk + +/****************** Bits definition for GPIO_ODR register *******************/ +#define GPIO_ODR_OD0_Pos (0U) +#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk +#define GPIO_ODR_OD1_Pos (1U) +#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk +#define GPIO_ODR_OD2_Pos (2U) +#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk +#define GPIO_ODR_OD3_Pos (3U) +#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk +#define GPIO_ODR_OD4_Pos (4U) +#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk +#define GPIO_ODR_OD5_Pos (5U) +#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk +#define GPIO_ODR_OD6_Pos (6U) +#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk +#define GPIO_ODR_OD7_Pos (7U) +#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk +#define GPIO_ODR_OD8_Pos (8U) +#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk +#define GPIO_ODR_OD9_Pos (9U) +#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk +#define GPIO_ODR_OD10_Pos (10U) +#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk +#define GPIO_ODR_OD11_Pos (11U) +#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk +#define GPIO_ODR_OD12_Pos (12U) +#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk +#define GPIO_ODR_OD13_Pos (13U) +#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk +#define GPIO_ODR_OD14_Pos (14U) +#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk +#define GPIO_ODR_OD15_Pos (15U) +#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk + +/****************** Bits definition for GPIO_BSRR register ******************/ +#define GPIO_BSRR_BS0_Pos (0U) +#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ +#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk +#define GPIO_BSRR_BS1_Pos (1U) +#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ +#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk +#define GPIO_BSRR_BS2_Pos (2U) +#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ +#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk +#define GPIO_BSRR_BS3_Pos (3U) +#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ +#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk +#define GPIO_BSRR_BS4_Pos (4U) +#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ +#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk +#define GPIO_BSRR_BS5_Pos (5U) +#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ +#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk +#define GPIO_BSRR_BS6_Pos (6U) +#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ +#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk +#define GPIO_BSRR_BS7_Pos (7U) +#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ +#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk +#define GPIO_BSRR_BS8_Pos (8U) +#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ +#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk +#define GPIO_BSRR_BS9_Pos (9U) +#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ +#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk +#define GPIO_BSRR_BS10_Pos (10U) +#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ +#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk +#define GPIO_BSRR_BS11_Pos (11U) +#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ +#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk +#define GPIO_BSRR_BS12_Pos (12U) +#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ +#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk +#define GPIO_BSRR_BS13_Pos (13U) +#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ +#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk +#define GPIO_BSRR_BS14_Pos (14U) +#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ +#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk +#define GPIO_BSRR_BS15_Pos (15U) +#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ +#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk +#define GPIO_BSRR_BR0_Pos (16U) +#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ +#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk +#define GPIO_BSRR_BR1_Pos (17U) +#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ +#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk +#define GPIO_BSRR_BR2_Pos (18U) +#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ +#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk +#define GPIO_BSRR_BR3_Pos (19U) +#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ +#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk +#define GPIO_BSRR_BR4_Pos (20U) +#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ +#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk +#define GPIO_BSRR_BR5_Pos (21U) +#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ +#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk +#define GPIO_BSRR_BR6_Pos (22U) +#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ +#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk +#define GPIO_BSRR_BR7_Pos (23U) +#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ +#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk +#define GPIO_BSRR_BR8_Pos (24U) +#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ +#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk +#define GPIO_BSRR_BR9_Pos (25U) +#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ +#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk +#define GPIO_BSRR_BR10_Pos (26U) +#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ +#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk +#define GPIO_BSRR_BR11_Pos (27U) +#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ +#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk +#define GPIO_BSRR_BR12_Pos (28U) +#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ +#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk +#define GPIO_BSRR_BR13_Pos (29U) +#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ +#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk +#define GPIO_BSRR_BR14_Pos (30U) +#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ +#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk +#define GPIO_BSRR_BR15_Pos (31U) +#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ +#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk + +/****************** Bit definition for GPIO_LCKR register *********************/ +#define GPIO_LCKR_LCK0_Pos (0U) +#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ +#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk +#define GPIO_LCKR_LCK1_Pos (1U) +#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ +#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk +#define GPIO_LCKR_LCK2_Pos (2U) +#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ +#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk +#define GPIO_LCKR_LCK3_Pos (3U) +#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ +#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk +#define GPIO_LCKR_LCK4_Pos (4U) +#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ +#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk +#define GPIO_LCKR_LCK5_Pos (5U) +#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ +#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk +#define GPIO_LCKR_LCK6_Pos (6U) +#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ +#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk +#define GPIO_LCKR_LCK7_Pos (7U) +#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ +#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk +#define GPIO_LCKR_LCK8_Pos (8U) +#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ +#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk +#define GPIO_LCKR_LCK9_Pos (9U) +#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ +#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk +#define GPIO_LCKR_LCK10_Pos (10U) +#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ +#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk +#define GPIO_LCKR_LCK11_Pos (11U) +#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ +#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk +#define GPIO_LCKR_LCK12_Pos (12U) +#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ +#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk +#define GPIO_LCKR_LCK13_Pos (13U) +#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ +#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk +#define GPIO_LCKR_LCK14_Pos (14U) +#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ +#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk +#define GPIO_LCKR_LCK15_Pos (15U) +#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ +#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk +#define GPIO_LCKR_LCKK_Pos (16U) +#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ +#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk + +/****************** Bit definition for GPIO_AFRL register *********************/ +#define GPIO_AFRL_AFSEL0_Pos (0U) +#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk +#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ +#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ +#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ +#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ +#define GPIO_AFRL_AFSEL1_Pos (4U) +#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk +#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ +#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ +#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ +#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ +#define GPIO_AFRL_AFSEL2_Pos (8U) +#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk +#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ +#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ +#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ +#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ +#define GPIO_AFRL_AFSEL3_Pos (12U) +#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk +#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ +#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ +#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ +#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ +#define GPIO_AFRL_AFSEL4_Pos (16U) +#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk +#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ +#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ +#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ +#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ +#define GPIO_AFRL_AFSEL5_Pos (20U) +#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk +#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ +#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ +#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ +#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ +#define GPIO_AFRL_AFSEL6_Pos (24U) +#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk +#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ +#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ +#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ +#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ +#define GPIO_AFRL_AFSEL7_Pos (28U) +#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk +#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ +#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ +#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ +#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ + +/****************** Bit definition for GPIO_AFRH register *********************/ +#define GPIO_AFRH_AFSEL8_Pos (0U) +#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk +#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ +#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ +#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ +#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ +#define GPIO_AFRH_AFSEL9_Pos (4U) +#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk +#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ +#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ +#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ +#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ +#define GPIO_AFRH_AFSEL10_Pos (8U) +#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk +#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ +#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ +#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ +#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ +#define GPIO_AFRH_AFSEL11_Pos (12U) +#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk +#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ +#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ +#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ +#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ +#define GPIO_AFRH_AFSEL12_Pos (16U) +#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk +#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ +#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ +#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ +#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ +#define GPIO_AFRH_AFSEL13_Pos (20U) +#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk +#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ +#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ +#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ +#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ +#define GPIO_AFRH_AFSEL14_Pos (24U) +#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk +#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ +#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ +#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ +#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ +#define GPIO_AFRH_AFSEL15_Pos (28U) +#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk +#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ +#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ +#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ +#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_BRR register ******************/ +#define GPIO_BRR_BR0_Pos (0U) +#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk +#define GPIO_BRR_BR1_Pos (1U) +#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk +#define GPIO_BRR_BR2_Pos (2U) +#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk +#define GPIO_BRR_BR3_Pos (3U) +#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk +#define GPIO_BRR_BR4_Pos (4U) +#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk +#define GPIO_BRR_BR5_Pos (5U) +#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk +#define GPIO_BRR_BR6_Pos (6U) +#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk +#define GPIO_BRR_BR7_Pos (7U) +#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk +#define GPIO_BRR_BR8_Pos (8U) +#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk +#define GPIO_BRR_BR9_Pos (9U) +#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk +#define GPIO_BRR_BR10_Pos (10U) +#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk +#define GPIO_BRR_BR11_Pos (11U) +#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk +#define GPIO_BRR_BR12_Pos (12U) +#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk +#define GPIO_BRR_BR13_Pos (13U) +#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk +#define GPIO_BRR_BR14_Pos (14U) +#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk +#define GPIO_BRR_BR15_Pos (15U) +#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk + +/****************** Bits definition for GPIO_SECCFGR register ******************/ +#define GPIO_SECCFGR_SEC0_Pos (0U) +#define GPIO_SECCFGR_SEC0_Msk (0x1UL << GPIO_SECCFGR_SEC0_Pos) /*!< 0x00000001 */ +#define GPIO_SECCFGR_SEC0 GPIO_SECCFGR_SEC0_Msk +#define GPIO_SECCFGR_SEC1_Pos (1U) +#define GPIO_SECCFGR_SEC1_Msk (0x1UL << GPIO_SECCFGR_SEC1_Pos) /*!< 0x00000002 */ +#define GPIO_SECCFGR_SEC1 GPIO_SECCFGR_SEC1_Msk +#define GPIO_SECCFGR_SEC2_Pos (2U) +#define GPIO_SECCFGR_SEC2_Msk (0x1UL << GPIO_SECCFGR_SEC2_Pos) /*!< 0x00000004 */ +#define GPIO_SECCFGR_SEC2 GPIO_SECCFGR_SEC2_Msk +#define GPIO_SECCFGR_SEC3_Pos (3U) +#define GPIO_SECCFGR_SEC3_Msk (0x1UL << GPIO_SECCFGR_SEC3_Pos) /*!< 0x00000008 */ +#define GPIO_SECCFGR_SEC3 GPIO_SECCFGR_SEC3_Msk +#define GPIO_SECCFGR_SEC4_Pos (4U) +#define GPIO_SECCFGR_SEC4_Msk (0x1UL << GPIO_SECCFGR_SEC4_Pos) /*!< 0x00000010 */ +#define GPIO_SECCFGR_SEC4 GPIO_SECCFGR_SEC4_Msk +#define GPIO_SECCFGR_SEC5_Pos (5U) +#define GPIO_SECCFGR_SEC5_Msk (0x1UL << GPIO_SECCFGR_SEC5_Pos) /*!< 0x00000020 */ +#define GPIO_SECCFGR_SEC5 GPIO_SECCFGR_SEC5_Msk +#define GPIO_SECCFGR_SEC6_Pos (6U) +#define GPIO_SECCFGR_SEC6_Msk (0x1UL << GPIO_SECCFGR_SEC6_Pos) /*!< 0x00000040 */ +#define GPIO_SECCFGR_SEC6 GPIO_SECCFGR_SEC6_Msk +#define GPIO_SECCFGR_SEC7_Pos (7U) +#define GPIO_SECCFGR_SEC7_Msk (0x1UL << GPIO_SECCFGR_SEC7_Pos) /*!< 0x00000080 */ +#define GPIO_SECCFGR_SEC7 GPIO_SECCFGR_SEC7_Msk +#define GPIO_SECCFGR_SEC8_Pos (8U) +#define GPIO_SECCFGR_SEC8_Msk (0x1UL << GPIO_SECCFGR_SEC8_Pos) /*!< 0x00000100 */ +#define GPIO_SECCFGR_SEC8 GPIO_SECCFGR_SEC8_Msk +#define GPIO_SECCFGR_SEC9_Pos (9U) +#define GPIO_SECCFGR_SEC9_Msk (0x1UL << GPIO_SECCFGR_SEC9_Pos) /*!< 0x00000200 */ +#define GPIO_SECCFGR_SEC9 GPIO_SECCFGR_SEC9_Msk +#define GPIO_SECCFGR_SEC10_Pos (10U) +#define GPIO_SECCFGR_SEC10_Msk (0x1UL << GPIO_SECCFGR_SEC10_Pos) /*!< 0x00000400 */ +#define GPIO_SECCFGR_SEC10 GPIO_SECCFGR_SEC10_Msk +#define GPIO_SECCFGR_SEC11_Pos (11U) +#define GPIO_SECCFGR_SEC11_Msk (x1UL << GPIO_SECCFGR_SEC11_Pos) /*!< 0x00000800 */ +#define GPIO_SECCFGR_SEC11 GPIO_SECCFGR_SEC11_Msk +#define GPIO_SECCFGR_SEC12_Pos (12U) +#define GPIO_SECCFGR_SEC12_Msk (0x1UL << GPIO_SECCFGR_SEC12_Pos) /*!< 0x00001000 */ +#define GPIO_SECCFGR_SEC12 GPIO_SECCFGR_SEC12_Msk +#define GPIO_SECCFGR_SEC13_Pos (13U) +#define GPIO_SECCFGR_SEC13_Msk (0x1UL << GPIO_SECCFGR_SEC13_Pos) /*!< 0x00002000 */ +#define GPIO_SECCFGR_SEC13 GPIO_SECCFGR_SEC13_Msk +#define GPIO_SECCFGR_SEC14_Pos (14U) +#define GPIO_SECCFGR_SEC14_Msk (0x1UL << GPIO_SECCFGR_SEC14_Pos) /*!< 0x00004000 */ +#define GPIO_SECCFGR_SEC14 GPIO_SECCFGR_SEC14_Msk +#define GPIO_SECCFGR_SEC15_Pos (15U) +#define GPIO_SECCFGR_SEC15_Msk (0x1UL << GPIO_SECCFGR_SEC15_Pos) /*!< 0x00008000 */ +#define GPIO_SECCFGR_SEC15 GPIO_SECCFGR_SEC15_Msk + + +/*****************************************************************************/ +/* */ +/* Global TrustZone Control */ +/* */ +/*****************************************************************************/ +/******************* Bits definition for GTZC_TZSC_CR register ******************/ +#define GTZC_TZSC_CR_LCK_Pos (0U) +#define GTZC_TZSC_CR_LCK_Msk (0x01UL << GTZC_TZSC_CR_LCK_Pos) /*!< 0x00000001 */ +#define GTZC_TZSC_CR_LCK GTZC_TZSC_CR_LCK_Msk /*!< GTZC Secure and privilege configurations lock */ + +/******* Bits definition for GTZC_TZSC_SECCFGRx/_PRIVCFGRx registers *****/ +/******* Bits definition for GTZC_TZIC_IERx/_SRx/_IFCRx registers ********/ + +/******************* Bits definition for GTZC_TZSC_SECCFGR1 register ***************/ +#define GTZC_CFGR1_TIM2_Pos GTZC_TZSC_SECCFGR1_TIM2SEC_Pos +#define GTZC_CFGR1_TIM2_Msk (0x01UL << GTZC_CFGR1_TIM2_Pos) +#define GTZC_CFGR1_TIM3_Pos GTZC_TZSC_SECCFGR1_TIM3SEC_Pos +#define GTZC_CFGR1_TIM3_Msk (0x01UL << GTZC_CFGR1_TIM3_Pos) +#define GTZC_CFGR1_WWDG_Pos GTZC_TZSC_SECCFGR1_WWDGSEC_Pos +#define GTZC_CFGR1_WWDG_Msk (0x01UL << GTZC_CFGR1_WWDG_Pos) +#define GTZC_CFGR1_IWDG_Pos GTZC_TZSC_SECCFGR1_IWDGSEC_Pos +#define GTZC_CFGR1_IWDG_Msk (0x01UL << GTZC_CFGR1_IWDG_Pos) +#define GTZC_CFGR1_USART2_Pos GTZC_TZSC_SECCFGR1_USART2SEC_Pos +#define GTZC_CFGR1_USART2_Msk (0x01UL << GTZC_CFGR1_USART2_Pos) +#define GTZC_CFGR1_I2C1_Pos GTZC_TZSC_SECCFGR1_I2C1SEC_Pos +#define GTZC_CFGR1_I2C1_Msk (0x01UL << GTZC_CFGR1_I2C1_Pos) +#define GTZC_CFGR1_LPTIM2_Pos GTZC_TZSC_SECCFGR1_LPTIM2SEC_Pos +#define GTZC_CFGR1_LPTIM2_Msk (0x01UL << GTZC_CFGR1_LPTIM2_Pos) + +/******************* Bits definition for GTZC_TZSC_SECCFGR2 register ***************/ +#define GTZC_CFGR2_TIM1_Pos GTZC_TZSC_SECCFGR2_TIM1SEC_Pos +#define GTZC_CFGR2_TIM1_Msk (0x01UL << GTZC_CFGR2_TIM1_Pos) +#define GTZC_CFGR2_SPI1_Pos GTZC_TZSC_SECCFGR2_SPI1SEC_Pos +#define GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos) +#define GTZC_CFGR2_USART1_Pos GTZC_TZSC_SECCFGR2_USART1SEC_Pos +#define GTZC_CFGR2_USART1_Msk (0x01UL << GTZC_CFGR2_USART1_Pos) +#define GTZC_CFGR2_TIM16_Pos GTZC_TZSC_SECCFGR2_TIM16SEC_Pos +#define GTZC_CFGR2_TIM16_Msk (0x01UL << GTZC_CFGR2_TIM16_Pos) +#define GTZC_CFGR2_TIM17_Pos GTZC_TZSC_SECCFGR2_TIM17SEC_Pos +#define GTZC_CFGR2_TIM17_Msk (0x01UL << GTZC_CFGR2_TIM17_Pos) +#define GTZC_CFGR2_SPI3_Pos GTZC_TZSC_SECCFGR2_SPI3SEC_Pos +#define GTZC_CFGR2_SPI3_Msk (0x01UL << GTZC_CFGR2_SPI3_Pos) +#define GTZC_CFGR2_LPUART1_Pos GTZC_TZSC_SECCFGR2_LPUART1SEC_Pos +#define GTZC_CFGR2_LPUART1_Msk (0x01UL << GTZC_CFGR2_LPUART1_Pos) +#define GTZC_CFGR2_I2C3_Pos GTZC_TZSC_SECCFGR2_I2C3SEC_Pos +#define GTZC_CFGR2_I2C3_Msk (0x01UL << GTZC_CFGR2_I2C3_Pos) +#define GTZC_CFGR2_LPTIM1_Pos GTZC_TZSC_SECCFGR2_LPTIM1SEC_Pos +#define GTZC_CFGR2_LPTIM1_Msk (0x01UL << GTZC_CFGR2_LPTIM1_Pos) +#define GTZC_CFGR2_ADC4_Pos GTZC_TZSC_SECCFGR2_ADC4SEC_Pos +#define GTZC_CFGR2_ADC4_Msk (0x01UL << GTZC_CFGR2_ADC4_Pos) + +/******************* Bits definition for GTZC_TZSC_SECCFGR3 register ***************/ +#define GTZC_CFGR3_CRC_Pos GTZC_TZSC_SECCFGR3_CRCSEC_Pos +#define GTZC_CFGR3_CRC_Msk (0x01UL << GTZC_CFGR3_CRC_Pos) +#define GTZC_CFGR3_TSC_Pos GTZC_TZSC_SECCFGR3_TSCSEC_Pos +#define GTZC_CFGR3_TSC_Msk (0x01UL << GTZC_CFGR3_TSC_Pos) +#define GTZC_CFGR3_ICACHE_REG_Pos GTZC_TZSC_SECCFGR3_ICACHE_REGSEC_Pos +#define GTZC_CFGR3_ICACHE_REG_Msk (0x01UL << GTZC_CFGR3_ICACHE_REG_Pos) +#define GTZC_CFGR3_AES_Pos GTZC_TZSC_SECCFGR3_AESSEC_Pos +#define GTZC_CFGR3_AES_Msk (0x01UL << GTZC_CFGR3_AES_Pos) +#define GTZC_CFGR3_HASH_Pos GTZC_TZSC_SECCFGR3_HASHSEC_Pos +#define GTZC_CFGR3_HASH_Msk (0x01UL << GTZC_CFGR3_HASH_Pos) +#define GTZC_CFGR3_RNG_Pos GTZC_TZSC_SECCFGR3_RNGSEC_Pos +#define GTZC_CFGR3_RNG_Msk (0x01UL << GTZC_CFGR3_RNG_Pos) +#define GTZC_CFGR3_SAES_Pos GTZC_TZSC_SECCFGR3_SAESSEC_Pos +#define GTZC_CFGR3_SAES_Msk (0x01UL << GTZC_CFGR3_SAES_Pos) +#define GTZC_CFGR3_HSEM_Pos GTZC_TZIC_IER3_HSEMIE_Pos +#define GTZC_CFGR3_HSEM_Msk (0x01UL << GTZC_CFGR3_HSEM_Pos) +#define GTZC_CFGR3_PKA_Pos GTZC_TZSC_SECCFGR3_PKASEC_Pos +#define GTZC_CFGR3_PKA_Msk (0x01UL << GTZC_CFGR3_PKA_Pos) +#define GTZC_CFGR3_RAMCFG_Pos GTZC_TZSC_SECCFGR3_RAMCFGSEC_Pos +#define GTZC_CFGR3_RAMCFG_Msk (0x01UL << GTZC_CFGR3_RAMCFG_Pos) +#define GTZC_CFGR3_RADIO_Pos GTZC_TZSC_SECCFGR3_RADIOSEC_Pos +#define GTZC_CFGR3_RADIO_Msk (0x01UL << GTZC_CFGR3_RADIO_Pos) + +/******************* Bits definition for GTZC_TZIC_IER4 register ***************/ +#define GTZC_CFGR4_GPDMA1_Pos GTZC_TZIC_IER4_GPDMA1IE_Pos +#define GTZC_CFGR4_GPDMA1_Msk (0x01UL << GTZC_CFGR4_GPDMA1_Pos) +#define GTZC_CFGR4_FLASH_Pos GTZC_TZIC_IER4_FLASHIE_Pos +#define GTZC_CFGR4_FLASH_Msk (0x01UL << GTZC_CFGR4_FLASH_Pos) +#define GTZC_CFGR4_FLASH_REG_Pos GTZC_TZIC_IER4_FLASH_REGIE_Pos +#define GTZC_CFGR4_FLASH_REG_Msk (0x01UL << GTZC_CFGR4_FLASH_REG_Pos) +#define GTZC_CFGR4_TZSC_Pos GTZC_TZIC_IER4_TZSCIE_Pos +#define GTZC_CFGR4_TZSC_Msk (0x01UL << GTZC_CFGR4_TZSC_Pos) +#define GTZC_CFGR4_TZIC_Pos GTZC_TZIC_IER4_TZICIE_Pos +#define GTZC_CFGR4_TZIC_Msk (0x01UL << GTZC_CFGR4_TZIC_Pos) +#define GTZC_CFGR4_SYSCFG_Pos GTZC_TZIC_IER4_SYSCFGIE_Pos +#define GTZC_CFGR4_SYSCFG_Msk (0x01UL << GTZC_CFGR4_SYSCFG_Pos) +#define GTZC_CFGR4_RTC_Pos GTZC_TZIC_IER4_RTCIE_Pos +#define GTZC_CFGR4_RTC_Msk (0x01UL << GTZC_CFGR4_RTC_Pos) +#define GTZC_CFGR4_TAMP_Pos GTZC_TZIC_IER4_TAMPIE_Pos +#define GTZC_CFGR4_TAMP_Msk (0x01UL << GTZC_CFGR4_TAMP_Pos) +#define GTZC_CFGR4_PWR_Pos GTZC_TZIC_IER4_PWRIE_Pos +#define GTZC_CFGR4_PWR_Msk (0x01UL << GTZC_CFGR4_PWR_Pos) +#define GTZC_CFGR4_RCC_Pos GTZC_TZIC_IER4_RCCIE_Pos +#define GTZC_CFGR4_RCC_sk (0x01UL << GTZC_CFGR4_RCC_Pos) +#define GTZC_CFGR4_EXTI_Pos GTZC_TZIC_IER4_EXTIIE_Pos +#define GTZC_CFGR4_EXTI_Msk (0x01UL << GTZC_CFGR4_EXTI_Pos) +#define GTZC_CFGR4_SRAM1_Pos GTZC_TZIC_IER4_SRAM1IE_Pos +#define GTZC_CFGR4_SRAM1_Msk (0x01UL << GTZC_CFGR4_SRAM1_Pos) +#define GTZC_CFGR4_MPCBB1_REG_Pos GTZC_TZIC_IER4_MPCBB1IE_Pos +#define GTZC_CFGR4_MPCBB1_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB1_REG_Pos) +#define GTZC_CFGR4_SRAM2_Pos GTZC_TZIC_IER4_SRAM2IE_Pos +#define GTZC_CFGR4_SRAM2_Msk (0x01UL << GTZC_CFGR4_SRAM2_Pos) +#define GTZC_CFGR4_MPCBB2_REG_Pos GTZC_TZIC_IER4_MPCBB2IE_Pos +#define GTZC_CFGR4_MPCBB2_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB2_REG_Pos) +#define GTZC_CFGR4_SRAM6_Pos GTZC_TZIC_IER4_SRAM6IE_Pos +#define GTZC_CFGR4_SRAM6_Msk (0x01UL << GTZC_CFGR4_SRAM6_Pos) +#define GTZC_CFGR4_MPCBB6_REG_Pos GTZC_TZIC_IER4_MPCBB6IE_Pos +#define GTZC_CFGR4_MPCBB6_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB6_REG_Pos) + +/*************** Bits definition for register x=1 (GTZC_TZSC_SECCFGR1) *************/ +#define GTZC_TZSC_SECCFGR1_TIM2SEC_Pos (0U) +#define GTZC_TZSC_SECCFGR1_TIM2SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR1_TIM2SEC_Pos) +#define GTZC_TZSC_SECCFGR1_TIM2SEC GTZC_TZSC_SECCFGR1_TIM2SEC_Msk /*!< secure access mode for TIM2 */ +#define GTZC_TZSC_SECCFGR1_TIM3SEC_Pos (1U) +#define GTZC_TZSC_SECCFGR1_TIM3SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR1_TIM3SEC_Pos) +#define GTZC_TZSC_SECCFGR1_TIM3SEC GTZC_TZSC_SECCFGR1_TIM3SEC_Msk /*!< secure access mode for TIM3 */ +#define GTZC_TZSC_SECCFGR1_WWDGSEC_Pos (6U) +#define GTZC_TZSC_SECCFGR1_WWDGSEC_Msk (0x01UL << GTZC_TZSC_SECCFGR1_WWDGSEC_Pos) +#define GTZC_TZSC_SECCFGR1_WWDGSEC GTZC_TZSC_SECCFGR1_WWDGSEC_Msk /*!< secure access mode for WWDG */ +#define GTZC_TZSC_SECCFGR1_IWDGSEC_Pos (7U) +#define GTZC_TZSC_SECCFGR1_IWDGSEC_Msk (0x01UL << GTZC_TZSC_SECCFGR1_IWDGSEC_Pos) +#define GTZC_TZSC_SECCFGR1_IWDGSEC GTZC_TZSC_SECCFGR1_IWDGSEC_Msk /*!< secure access mode for IWDG */ +#define GTZC_TZSC_SECCFGR1_USART2SEC_Pos (9U) +#define GTZC_TZSC_SECCFGR1_USART2SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR1_USART2SEC_Pos) +#define GTZC_TZSC_SECCFGR1_USART2SEC GTZC_TZSC_SECCFGR1_USART2SEC_Msk /*!< secure access mode for USART2 */ +#define GTZC_TZSC_SECCFGR1_I2C1SEC_Pos (13U) +#define GTZC_TZSC_SECCFGR1_I2C1SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR1_I2C1SEC_Pos) +#define GTZC_TZSC_SECCFGR1_I2C1SEC GTZC_TZSC_SECCFGR1_I2C1SEC_Msk /*!< secure access mode for I2C1 */ +#define GTZC_TZSC_SECCFGR1_LPTIM2SEC_Pos (17U) +#define GTZC_TZSC_SECCFGR1_LPTIM2SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR1_LPTIM2SEC_Pos) +#define GTZC_TZSC_SECCFGR1_LPTIM2SEC GTZC_TZSC_SECCFGR1_LPTIM2SEC_Msk /*!< secure access mode for LPTIM2 */ + +/*************** Bits definition for register x=2 (GTZC_TZSC_SECCFGR2) *************/ +#define GTZC_TZSC_SECCFGR2_TIM1SEC_Pos (0U) +#define GTZC_TZSC_SECCFGR2_TIM1SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR2_TIM1SEC_Pos) +#define GTZC_TZSC_SECCFGR2_TIM1SEC GTZC_TZSC_SECCFGR2_TIM1SEC_Msk /*!< secure access mode for TIM1 */ +#define GTZC_TZSC_SECCFGR2_SPI1SEC_Pos (1U) +#define GTZC_TZSC_SECCFGR2_SPI1SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR2_SPI1SEC_Pos) +#define GTZC_TZSC_SECCFGR2_SPI1SEC GTZC_TZSC_SECCFGR2_SPI1SEC_Msk /*!< secure access mode for SPI1 */ +#define GTZC_TZSC_SECCFGR2_USART1SEC_Pos (3U) +#define GTZC_TZSC_SECCFGR2_USART1SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR2_USART1SEC_Pos) +#define GTZC_TZSC_SECCFGR2_USART1SEC GTZC_TZSC_SECCFGR2_USART1SEC_Msk /*!< secure access mode for USART1 */ +#define GTZC_TZSC_SECCFGR2_TIM16SEC_Pos (5U) +#define GTZC_TZSC_SECCFGR2_TIM16SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR2_TIM16SEC_Pos) +#define GTZC_TZSC_SECCFGR2_TIM16SEC GTZC_TZSC_SECCFGR2_TIM16SEC_Msk /*!< secure access mode for TIM16 */ +#define GTZC_TZSC_SECCFGR2_TIM17SEC_Pos (6U) +#define GTZC_TZSC_SECCFGR2_TIM17SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR2_TIM17SEC_Pos) +#define GTZC_TZSC_SECCFGR2_TIM17SEC GTZC_TZSC_SECCFGR2_TIM17SEC_Msk /*!< secure access mode for TIM17 */ +#define GTZC_TZSC_SECCFGR2_SPI3SEC_Pos (16U) +#define GTZC_TZSC_SECCFGR2_SPI3SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR2_SPI3SEC_Pos) +#define GTZC_TZSC_SECCFGR2_SPI3SEC GTZC_TZSC_SECCFGR2_SPI3SEC_Msk /*!< secure access mode for SPI3 */ +#define GTZC_TZSC_SECCFGR2_LPUART1SEC_Pos (17U) +#define GTZC_TZSC_SECCFGR2_LPUART1SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR2_LPUART1SEC_Pos) +#define GTZC_TZSC_SECCFGR2_LPUART1SEC GTZC_TZSC_SECCFGR2_LPUART1SEC_Msk /*!< secure access mode for LPUART1 */ +#define GTZC_TZSC_SECCFGR2_I2C3SEC_Pos (18U) +#define GTZC_TZSC_SECCFGR2_I2C3SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR2_I2C3SEC_Pos) +#define GTZC_TZSC_SECCFGR2_I2C3SEC GTZC_TZSC_SECCFGR2_I2C3SEC_Msk /*!< secure access mode for I2C3 */ +#define GTZC_TZSC_SECCFGR2_LPTIM1SEC_Pos (19U) +#define GTZC_TZSC_SECCFGR2_LPTIM1SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR2_LPTIM1SEC_Pos) +#define GTZC_TZSC_SECCFGR2_LPTIM1SEC GTZC_TZSC_SECCFGR2_LPTIM1SEC_Msk /*!< secure access mode for LPTIM1 */ +#define GTZC_TZSC_SECCFGR2_ADC4SEC_Pos (24U) +#define GTZC_TZSC_SECCFGR2_ADC4SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR2_ADC4SEC_Pos) +#define GTZC_TZSC_SECCFGR2_ADC4SEC GTZC_TZSC_SECCFGR2_ADC4SEC_Msk /*!< secure access mode for ADC4 */ + +/*************** Bits definition for register x=3 (GTZC_TZSC_SECCFGR3) *************/ +#define GTZC_TZSC_SECCFGR3_CRCSEC_Pos (3U) +#define GTZC_TZSC_SECCFGR3_CRCSEC_Msk (0x01UL << GTZC_TZSC_SECCFGR3_CRCSEC_Pos) +#define GTZC_TZSC_SECCFGR3_CRCSEC GTZC_TZSC_SECCFGR3_CRCSEC_Msk /*!< secure access mode for CRC */ +#define GTZC_TZSC_SECCFGR3_TSCSEC_Pos (4U) +#define GTZC_TZSC_SECCFGR3_TSCSEC_Msk (0x01UL << GTZC_TZSC_SECCFGR3_TSCSEC_Pos) +#define GTZC_TZSC_SECCFGR3_TSCSEC GTZC_TZSC_SECCFGR3_TSCSEC_Msk /*!< secure access mode for TSC */ +#define GTZC_TZSC_SECCFGR3_ICACHE_REGSEC_Pos (6U) +#define GTZC_TZSC_SECCFGR3_ICACHE_REGSEC_Msk (0x01UL << GTZC_TZSC_SECCFGR3_ICACHE_REGSEC_Pos) +#define GTZC_TZSC_SECCFGR3_ICACHE_REGSEC GTZC_TZSC_SECCFGR3_ICACHE_REGSEC_Msk /*!< secure access mode for ICACHE_REG */ +#define GTZC_TZSC_SECCFGR3_AESSEC_Pos (11U) +#define GTZC_TZSC_SECCFGR3_AESSEC_Msk (0x01UL << GTZC_TZSC_SECCFGR3_AESSEC_Pos) +#define GTZC_TZSC_SECCFGR3_AESSEC GTZC_TZSC_SECCFGR3_AESSEC_Msk /*!< secure access mode for AES */ +#define GTZC_TZSC_SECCFGR3_HASHSEC_Pos (12U) +#define GTZC_TZSC_SECCFGR3_HASHSEC_Msk (0x01UL << GTZC_TZSC_SECCFGR3_HASHSEC_Pos) +#define GTZC_TZSC_SECCFGR3_HASHSEC GTZC_TZSC_SECCFGR3_HASHSEC_Msk /*!< secure access mode for HASH */ +#define GTZC_TZSC_SECCFGR3_RNGSEC_Pos (13U) +#define GTZC_TZSC_SECCFGR3_RNGSEC_Msk (0x01UL << GTZC_TZSC_SECCFGR3_RNGSEC_Pos) +#define GTZC_TZSC_SECCFGR3_RNGSEC GTZC_TZSC_SECCFGR3_RNGSEC_Msk /*!< secure access mode for RNG */ +#define GTZC_TZSC_SECCFGR3_SAESSEC_Pos (14U) +#define GTZC_TZSC_SECCFGR3_SAESSEC_Msk (0x01UL << GTZC_TZSC_SECCFGR3_SAESSEC_Pos) +#define GTZC_TZSC_SECCFGR3_SAESSEC GTZC_TZSC_SECCFGR3_SAESSEC_Msk /*!< secure access mode for SAES */ +#define GTZC_TZSC_SECCFGR3_PKASEC_Pos (16U) +#define GTZC_TZSC_SECCFGR3_PKASEC_Msk (0x01UL << GTZC_TZSC_SECCFGR3_PKASEC_Pos) +#define GTZC_TZSC_SECCFGR3_PKASEC GTZC_TZSC_SECCFGR3_PKASEC_Msk /*!< secure access mode for PKA */ +#define GTZC_TZSC_SECCFGR3_RAMCFGSEC_Pos (22U) +#define GTZC_TZSC_SECCFGR3_RAMCFGSEC_Msk (0x01UL << GTZC_TZSC_SECCFGR3_RAMCFGSEC_Pos) +#define GTZC_TZSC_SECCFGR3_RAMCFGSEC GTZC_TZSC_SECCFGR3_RAMCFGSEC_Msk /*!< secure access mode for RAMCFG */ +#define GTZC_TZSC_SECCFGR3_RADIOSEC_Pos (23U) +#define GTZC_TZSC_SECCFGR3_RADIOSEC_Msk (0x01UL << GTZC_TZSC_SECCFGR3_RADIOSEC_Pos) +#define GTZC_TZSC_SECCFGR3_RADIOSEC GTZC_TZSC_SECCFGR3_RADIOSEC_Msk /*!< secure access mode for 2.4 GHz RADIO */ + +/******************* Bits definition for GTZC_TZSC_PRIVCFGR1 register ***************/ +#define GTZC_TZSC_PRIVCFGR1_TIM2PRIV_Pos (0U) +#define GTZC_TZSC_PRIVCFGR1_TIM2PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR1_TIM2PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR1_TIM2PRIV GTZC_TZSC_PRIVCFGR1_TIM2PRIV_Msk /*!< privileged access mode for TIM2 */ +#define GTZC_TZSC_PRIVCFGR1_TIM3PRIV_Pos (1U) +#define GTZC_TZSC_PRIVCFGR1_TIM3PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR1_TIM3PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR1_TIM3PRIV GTZC_TZSC_PRIVCFGR1_TIM3PRIV_Msk /*!< privileged access mode for TIM3 */ +#define GTZC_TZSC_PRIVCFGR1_WWDGPRIV_Pos (6U) +#define GTZC_TZSC_PRIVCFGR1_WWDGPRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR1_WWDGPRIV_Pos) +#define GTZC_TZSC_PRIVCFGR1_WWDGPRIV GTZC_TZSC_PRIVCFGR1_WWDGPRIV_Msk /*!< privileged access mode for WWDG */ +#define GTZC_TZSC_PRIVCFGR1_IWDGPRIV_Pos (7U) +#define GTZC_TZSC_PRIVCFGR1_IWDGPRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR1_IWDGPRIV_Pos) +#define GTZC_TZSC_PRIVCFGR1_IWDGPRIV GTZC_TZSC_PRIVCFGR1_IWDGPRIV_Msk /*!< privileged access mode for IWDG */ +#define GTZC_TZSC_PRIVCFGR1_USART2PRIV_Pos (9U) +#define GTZC_TZSC_PRIVCFGR1_USART2PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR1_USART2PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR1_USART2PRIV GTZC_TZSC_PRIVCFGR1_USART2PRIV_Msk /*!< privileged access mode for USART2 */ +#define GTZC_TZSC_PRIVCFGR1_I2C1PRIV_Pos (13U) +#define GTZC_TZSC_PRIVCFGR1_I2C1PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR1_I2C1PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR1_I2C1PRIV GTZC_TZSC_PRIVCFGR1_I2C1PRIV_Msk /*!< privileged access mode for I2C1 */ +#define GTZC_TZSC_PRIVCFGR1_LPTIM2PRIV_Pos (17U) +#define GTZC_TZSC_PRIVCFGR1_LPTIM2PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR1_LPTIM2PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR1_LPTIM2PRIV GTZC_TZSC_PRIVCFGR1_LPTIM2PRIV_Msk /*!< privileged access mode for LPTIM2 */ + +/******************* Bits definition for GTZC_TZSC_PRIVCFGR2 register ***************/ +#define GTZC_TZSC_PRIVCFGR2_TIM1PRIV_Pos (0U) +#define GTZC_TZSC_PRIVCFGR2_TIM1PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR2_TIM1PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR2_TIM1PRIV GTZC_TZSC_PRIVCFGR2_TIM1PRIV_Msk /*!< privileged access mode for TIM1 */ +#define GTZC_TZSC_PRIVCFGR2_SPI1PRIV_Pos (1U) +#define GTZC_TZSC_PRIVCFGR2_SPI1PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR2_SPI1PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR2_SPI1PRIV GTZC_TZSC_PRIVCFGR2_SPI1PRIV_Msk /*!< privileged access mode for SPI1 */ +#define GTZC_TZSC_PRIVCFGR2_USART1PRIV_Pos (3U) +#define GTZC_TZSC_PRIVCFGR2_USART1PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR2_USART1PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR2_USART1PRIV GTZC_TZSC_PRIVCFGR2_USART1PRIV_Msk /*!< privileged access mode for USART1 */ +#define GTZC_TZSC_PRIVCFGR2_TIM16PRIV_Pos (5U) +#define GTZC_TZSC_PRIVCFGR2_TIM16PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR2_TIM16PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR2_TIM16PRIV GTZC_TZSC_PRIVCFGR2_TIM16PRIV_Msk /*!< privileged access mode for TIM16 */ +#define GTZC_TZSC_PRIVCFGR2_TIM17PRIV_Pos (6U) +#define GTZC_TZSC_PRIVCFGR2_TIM17PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR2_TIM17PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR2_TIM17PRIV GTZC_TZSC_PRIVCFGR2_TIM17PRIV_Msk /*!< privileged access mode for TIM17 */ +#define GTZC_TZSC_PRIVCFGR2_SPI3PRIV_Pos (16U) +#define GTZC_TZSC_PRIVCFGR2_SPI3PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR2_SPI3PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR2_SPI3PRIV GTZC_TZSC_PRIVCFGR2_SPI3PRIV_Msk /*!< privileged access mode for SPI3 */ +#define GTZC_TZSC_PRIVCFGR2_LPUART1PRIV_Pos (17U) +#define GTZC_TZSC_PRIVCFGR2_LPUART1PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR2_LPUART1PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR2_LPUART1PRIV GTZC_TZSC_PRIVCFGR2_LPUART1PRIV_Msk /*!< privileged access mode for LPUART1 */ +#define GTZC_TZSC_PRIVCFGR2_I2C3PRIV_Pos (18U) +#define GTZC_TZSC_PRIVCFGR2_I2C3PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR2_I2C3PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR2_I2C3PRIV GTZC_TZSC_PRIVCFGR2_I2C3PRIV_Msk /*!< privileged access mode for I2C3 */ +#define GTZC_TZSC_PRIVCFGR2_LPTIM1PRIV_Pos (19U) +#define GTZC_TZSC_PRIVCFGR2_LPTIM1PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR2_LPTIM1PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR2_LPTIM1PRIV GTZC_TZSC_PRIVCFGR2_LPTIM1PRIV_Msk /*!< privileged access mode for LPTIM1 */ +#define GTZC_TZSC_PRIVCFGR2_ADC4PRIV_Pos (24U) +#define GTZC_TZSC_PRIVCFGR2_ADC4PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR2_ADC4PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR2_ADC4PRIV GTZC_TZSC_PRIVCFGR2_ADC4PRIV_Msk /*!< privileged access mode for ADC4 */ + +/******************* Bits definition for GTZC_TZSC_PRIVCFGR3 register ***************/ +#define GTZC_TZSC_PRIVCFGR3_CRCPRIV_Pos (3U) +#define GTZC_TZSC_PRIVCFGR3_CRCPRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR3_CRCPRIV_Pos) +#define GTZC_TZSC_PRIVCFGR3_CRCPRIV GTZC_TZSC_PRIVCFGR3_CRCPRIV_Msk /*!< privileged access mode for CRC */ +#define GTZC_TZSC_PRIVCFGR3_TSCPRIV_Pos (4U) +#define GTZC_TZSC_PRIVCFGR3_TSCPRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR3_TSCPRIV_Pos) +#define GTZC_TZSC_PRIVCFGR3_TSCPRIV GTZC_TZSC_PRIVCFGR3_TSCPRIV_Msk /*!< privileged access mode for TSC */ +#define GTZC_TZSC_PRIVCFGR3_ICACHE_REGPRIV_Pos (6U) +#define GTZC_TZSC_PRIVCFGR3_ICACHE_REGPRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR3_ICACHE_REGPRIV_Pos) +#define GTZC_TZSC_PRIVCFGR3_ICACHE_REGPRIV GTZC_TZSC_PRIVCFGR3_ICACHE_REGPRIV_Msk /*!< privileged access mode for ICACHE_REG */ +#define GTZC_TZSC_PRIVCFGR3_AESPRIV_Pos (11U) +#define GTZC_TZSC_PRIVCFGR3_AESPRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR3_AESPRIV_Pos) +#define GTZC_TZSC_PRIVCFGR3_AESPRIV GTZC_TZSC_PRIVCFGR3_AESPRIV_Msk /*!< privileged access mode for AES */ +#define GTZC_TZSC_PRIVCFGR3_HASHPRIV_Pos (12U) +#define GTZC_TZSC_PRIVCFGR3_HASHPRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR3_HASHPRIV_Pos) +#define GTZC_TZSC_PRIVCFGR3_HASHPRIV GTZC_TZSC_PRIVCFGR3_HASHPRIV_Msk /*!< privileged access mode for HASH */ +#define GTZC_TZSC_PRIVCFGR3_RNGPRIV_Pos (13U) +#define GTZC_TZSC_PRIVCFGR3_RNGPRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR3_RNGPRIV_Pos) +#define GTZC_TZSC_PRIVCFGR3_RNGPRIV GTZC_TZSC_PRIVCFGR3_RNGPRIV_Msk /*!< privileged access mode for RNG */ +#define GTZC_TZSC_PRIVCFGR3_SAESPRIV_Pos (14U) +#define GTZC_TZSC_PRIVCFGR3_SAESPRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR3_SAESPRIV_Pos) +#define GTZC_TZSC_PRIVCFGR3_SAESPRIV GTZC_TZSC_PRIVCFGR3_SAESPRIV_Msk /*!< privileged access mode for SAES */ +#define GTZC_TZSC_PRIVCFGR3_PKAPRIV_Pos (16U) +#define GTZC_TZSC_PRIVCFGR3_PKAPRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR3_PKAPRIV_Pos) +#define GTZC_TZSC_PRIVCFGR3_PKAPRIV GTZC_TZSC_PRIVCFGR3_PKAPRIV_Msk /*!< privileged access mode for PKA */ +#define GTZC_TZSC_PRIVCFGR3_RAMCFGPRIV_Pos (22U) +#define GTZC_TZSC_PRIVCFGR3_RAMCFGPRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR3_RAMCFGPRIV_Pos) +#define GTZC_TZSC_PRIVCFGR3_RAMCFGPRIV GTZC_TZSC_PRIVCFGR3_RAMCFGPRIV_Msk /*!< privileged access mode for RAMCFG */ +#define GTZC_TZSC_PRIVCFGR3_RADIOPRIV_Pos (23U) +#define GTZC_TZSC_PRIVCFGR3_RADIOPRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR3_RADIOPRIV_Pos) +#define GTZC_TZSC_PRIVCFGR3_RADIOPRIV GTZC_TZSC_PRIVCFGR3_RADIOPRIV_Msk /*!< privileged access mode for 2.4 GHz RADIO */ + +/******************* Bits definition for GTZC_TZIC_IER1 register ***************/ +#define GTZC_TZIC_IER1_TIM2IE_Pos (0U) +#define GTZC_TZIC_IER1_TIM2IE_Msk (0x01UL << GTZC_TZIC_IER1_TIM2IE_Pos) +#define GTZC_TZIC_IER1_TIM2IE GTZC_TZIC_IER1_TIM2IE_Msk /*!< illegal access interrupt enable for TIM2 */ +#define GTZC_TZIC_IER1_TIM3IE_Pos (1U) +#define GTZC_TZIC_IER1_TIM3IE_Msk (0x01UL << GTZC_TZIC_IER1_TIM3IE_Pos) +#define GTZC_TZIC_IER1_TIM3IE GTZC_TZIC_IER1_TIM3IE_Msk /*!< illegal access interrupt enable for TIM3 */ +#define GTZC_TZIC_IER1_WWDGIE_Pos (6U) +#define GTZC_TZIC_IER1_WWDGIE_Msk (0x01UL << GTZC_TZIC_IER1_WWDGIE_Pos) +#define GTZC_TZIC_IER1_WWDGIE GTZC_TZIC_IER1_WWDGIE_Msk /*!< illegal access interrupt enable for WWDG */ +#define GTZC_TZIC_IER1_IWDGIE_Pos (7U) +#define GTZC_TZIC_IER1_IWDGIE_Msk (0x01UL << GTZC_TZIC_IER1_IWDGIE_Pos) +#define GTZC_TZIC_IER1_IWDGIE GTZC_TZIC_IER1_IWDGIE_Msk /*!< illegal access interrupt enable for IWDG */ +#define GTZC_TZIC_IER1_USART2IE_Pos (9U) +#define GTZC_TZIC_IER1_USART2IE_Msk (0x01UL << GTZC_TZIC_IER1_USART2IE_Pos) +#define GTZC_TZIC_IER1_USART2IE GTZC_TZIC_IER1_USART2IE_Msk /*!< illegal access interrupt enable for USART2 */ +#define GTZC_TZIC_IER1_I2C1IE_Pos (13U) +#define GTZC_TZIC_IER1_I2C1IE_Msk (0x01UL << GTZC_TZIC_IER1_I2C1IE_Pos) +#define GTZC_TZIC_IER1_I2C1IE GTZC_TZIC_IER1_I2C1IE_Msk /*!< illegal access interrupt enable for I2C1 */ +#define GTZC_TZIC_IER1_LPTIM2IE_Pos (17U) +#define GTZC_TZIC_IER1_LPTIM2IE_Msk (0x01UL << GTZC_TZIC_IER1_LPTIM2IE_Pos) +#define GTZC_TZIC_IER1_LPTIM2IE GTZC_TZIC_IER1_LPTIM2IE_Msk /*!< illegal access interrupt enable for LPTIM2 */ + +/******************* Bits definition for GTZC_TZIC_IER2 register ***************/ +#define GTZC_TZIC_IER2_TIM1IE_Pos (0U) +#define GTZC_TZIC_IER2_TIM1IE_Msk (0x01UL << GTZC_TZIC_IER2_TIM1IE_Pos) +#define GTZC_TZIC_IER2_TIM1IE GTZC_TZIC_IER2_TIM1IE_Msk /*!< illegal access interrupt enable for TIM1 */ +#define GTZC_TZIC_IER2_SPI1IE_Pos (1U) +#define GTZC_TZIC_IER2_SPI1IE_Msk (0x01UL << GTZC_TZIC_IER2_SPI1IE_Pos) +#define GTZC_TZIC_IER2_SPI1IE GTZC_TZIC_IER2_SPI1IE_Msk /*!< illegal access interrupt enable for SPI1 */ +#define GTZC_TZIC_IER2_USART1IE_Pos (3U) +#define GTZC_TZIC_IER2_USART1IE_Msk (0x01UL << GTZC_TZIC_IER2_USART1IE_Pos) +#define GTZC_TZIC_IER2_USART1IE GTZC_TZIC_IER2_USART1IE_Msk /*!< illegal access interrupt enable for USART1 */ +#define GTZC_TZIC_IER2_TIM16IE_Pos (5U) +#define GTZC_TZIC_IER2_TIM16IE_Msk (0x01UL << GTZC_TZIC_IER2_TIM16IE_Pos) +#define GTZC_TZIC_IER2_TIM16IE GTZC_TZIC_IER2_TIM16IE_Msk /*!< illegal access interrupt enable for TIM16 */ +#define GTZC_TZIC_IER2_TIM17IE_Pos (6U) +#define GTZC_TZIC_IER2_TIM17IE_Msk (0x01UL << GTZC_TZIC_IER2_TIM17IE_Pos) +#define GTZC_TZIC_IER2_TIM17IE GTZC_TZIC_IER2_TIM17IE_Msk /*!< illegal access interrupt enable for TIM17 */ +#define GTZC_TZIC_IER2_SPI3IE_Pos (16U) +#define GTZC_TZIC_IER2_SPI3IE_Msk (0x01UL << GTZC_TZIC_IER2_SPI3IE_Pos) +#define GTZC_TZIC_IER2_SPI3IE GTZC_TZIC_IER2_SPI3IE_Msk /*!< illegal access interrupt enable for SPI3 */ +#define GTZC_TZIC_IER2_LPUART1IE_Pos (17U) +#define GTZC_TZIC_IER2_LPUART1IE_Msk (0x01UL << GTZC_TZIC_IER2_LPUART1IE_Pos) +#define GTZC_TZIC_IER2_LPUART1IE GTZC_TZIC_IER2_LPUART1IE_Msk /*!< illegal access interrupt enable for LPUART1 */ +#define GTZC_TZIC_IER2_I2C3IE_Pos (18U) +#define GTZC_TZIC_IER2_I2C3IE_Msk (0x01UL << GTZC_TZIC_IER2_I2C3IE_Pos) +#define GTZC_TZIC_IER2_I2C3IE GTZC_TZIC_IER2_I2C3IE_Msk /*!< illegal access interrupt enable for I2C3 */ +#define GTZC_TZIC_IER2_LPTIM1IE_Pos (19U) +#define GTZC_TZIC_IER2_LPTIM1IE_Msk (0x01UL << GTZC_TZIC_IER2_LPTIM1IE_Pos) +#define GTZC_TZIC_IER2_LPTIM1IE GTZC_TZIC_IER2_LPTIM1IE_Msk /*!< illegal access interrupt enable for LPTIM1 */ +#define GTZC_TZIC_IER2_ADC4IE_Pos (24U) +#define GTZC_TZIC_IER2_ADC4IE_Msk (0x01UL << GTZC_TZIC_IER2_ADC4IE_Pos) +#define GTZC_TZIC_IER2_ADC4IE GTZC_TZIC_IER2_ADC4IE_Msk /*!< illegal access interrupt enable for ADC4 */ + +/******************* Bits definition for GTZC_TZIC_IER3 register ***************/ +#define GTZC_TZIC_IER3_CRCIE_Pos (3U) +#define GTZC_TZIC_IER3_CRCIE_Msk (0x01UL << GTZC_TZIC_IER3_CRCIE_Pos) +#define GTZC_TZIC_IER3_CRCIE GTZC_TZIC_IER3_CRCIE_Msk /*!< illegal access interrupt enable for CRC */ +#define GTZC_TZIC_IER3_TSCIE_Pos (4U) +#define GTZC_TZIC_IER3_TSCIE_Msk (0x01UL << GTZC_TZIC_IER3_TSCIE_Pos) +#define GTZC_TZIC_IER3_TSCIE GTZC_TZIC_IER3_TSCIE_Msk /*!< illegal access interrupt enable for TSC */ +#define GTZC_TZIC_IER3_ICACHE_REGIE_Pos (6U) +#define GTZC_TZIC_IER3_ICACHE_REGIE_Msk (0x01UL << GTZC_TZIC_IER3_ICACHE_REGIE_Pos) +#define GTZC_TZIC_IER3_ICACHE_REGIE GTZC_TZIC_IER3_ICACHE_REGIE_Msk /*!< illegal access interrupt enable for ICACHE_REG */ +#define GTZC_TZIC_IER3_AESIE_Pos (11U) +#define GTZC_TZIC_IER3_AESIE_Msk (0x01UL << GTZC_TZIC_IER3_AESIE_Pos) +#define GTZC_TZIC_IER3_AESIE GTZC_TZIC_IER3_AESIE_Msk /*!< illegal access interrupt enable for AES */ +#define GTZC_TZIC_IER3_HASHIE_Pos (12U) +#define GTZC_TZIC_IER3_HASHIE_Msk (0x01UL << GTZC_TZIC_IER3_HASHIE_Pos) +#define GTZC_TZIC_IER3_HASHIE GTZC_TZIC_IER3_HASHIE_Msk /*!< illegal access interrupt enable for HASH */ +#define GTZC_TZIC_IER3_RNGIE_Pos (13U) +#define GTZC_TZIC_IER3_RNGIE_Msk (0x01UL << GTZC_TZIC_IER3_RNGIE_Pos) +#define GTZC_TZIC_IER3_RNGIE GTZC_TZIC_IER3_RNGIE_Msk /*!< illegal access interrupt enable for RNG */ +#define GTZC_TZIC_IER3_SAESIE_Pos (14U) +#define GTZC_TZIC_IER3_SAESIE_Msk (0x01UL << GTZC_TZIC_IER3_SAESIE_Pos) +#define GTZC_TZIC_IER3_SAESIE GTZC_TZIC_IER3_SAESIE_Msk /*!< illegal access interrupt enable for SAES */ +#define GTZC_TZIC_IER3_HSEMIE_Pos (15U) +#define GTZC_TZIC_IER3_HSEMIE_Msk (0x01UL << GTZC_TZIC_IER3_HSEMIE_Pos) +#define GTZC_TZIC_IER3_HSEMIE GTZC_TZIC_IER3_HSEMIE_Msk /*!< illegal access interrupt enable for HSEM */ +#define GTZC_TZIC_IER3_PKAIE_Pos (16U) +#define GTZC_TZIC_IER3_PKAIE_Msk (0x01UL << GTZC_TZIC_IER3_PKAIE_Pos) +#define GTZC_TZIC_IER3_PKAIE GTZC_TZIC_IER3_PKAIE_Msk /*!< illegal access interrupt enable for PKA */ +#define GTZC_TZIC_IER3_RAMCFGIE_Pos (22U) +#define GTZC_TZIC_IER3_RAMCFGIE_Msk (0x01UL << GTZC_TZIC_IER3_RAMCFGIE_Pos) +#define GTZC_TZIC_IER3_RAMCFGIE GTZC_TZIC_IER3_RAMCFGIE_Msk /*!< illegal access interrupt enable for RAMCFG */ +#define GTZC_TZIC_IER3_RADIOIE_Pos (23U) +#define GTZC_TZIC_IER3_RADIOIE_Msk (0x01UL << GTZC_TZIC_IER3_RADIOIE_Pos) +#define GTZC_TZIC_IER3_RADIOIE GTZC_TZIC_IER3_RADIOIE_Msk /*!< illegal access interrupt enable for 2.4 GHz RADIO */ + +/******************* Bits definition for GTZC_TZIC_IER4 register ***************/ +#define GTZC_TZIC_IER4_GPDMA1IE_Pos (0U) +#define GTZC_TZIC_IER4_GPDMA1IE_Msk (0x01UL << GTZC_TZIC_IER4_GPDMA1IE_Pos) +#define GTZC_TZIC_IER4_GPDMA1IE GTZC_TZIC_IER4_GPDMA1IE_Msk /*!< illegal access interrupt enable for GPDMA1 */ +#define GTZC_TZIC_IER4_FLASHIE_Pos (1U) +#define GTZC_TZIC_IER4_FLASHIE_Msk (0x01UL << GTZC_TZIC_IER4_FLASHIE_Pos) +#define GTZC_TZIC_IER4_FLASHIE GTZC_TZIC_IER4_FLASHIE_Msk /*!< illegal access interrupt enable for FLASH memory */ +#define GTZC_TZIC_IER4_FLASH_REGIE_Pos (2U) +#define GTZC_TZIC_IER4_FLASH_REGIE_Msk (0x01UL << GTZC_TZIC_IER4_FLASH_REGIE_Pos) +#define GTZC_TZIC_IER4_FLASH_REGIE GTZC_TZIC_IER4_FLASH_REGIE_Msk /*!< illegal access interrupt enable for FLASH interface */ +#define GTZC_TZIC_IER4_SYSCFGIE_Pos (7U) +#define GTZC_TZIC_IER4_SYSCFGIE_Msk (0x01UL << GTZC_TZIC_IER4_SYSCFGIE_Pos) +#define GTZC_TZIC_IER4_SYSCFGIE GTZC_TZIC_IER4_SYSCFGIE_Msk /*!< illegal access interrupt enable for SYSCFG interface */ +#define GTZC_TZIC_IER4_RTCIE_Pos (8U) +#define GTZC_TZIC_IER4_RTCIE_Msk (0x01UL << GTZC_TZIC_IER4_RTCIE_Pos) +#define GTZC_TZIC_IER4_RTCIE GTZC_TZIC_IER4_RTCIE_Msk /*!< illegal access interrupt enable for RTC interface */ +#define GTZC_TZIC_IER4_TAMPIE_Pos (9U) +#define GTZC_TZIC_IER4_TAMPIE_Msk (0x01UL << GTZC_TZIC_IER4_TAMPIE_Pos) +#define GTZC_TZIC_IER4_TAMPIE GTZC_TZIC_IER4_TAMPIE_Msk /*!< illegal access interrupt enable for TAMP interface */ +#define GTZC_TZIC_IER4_PWRIE_Pos (10U) +#define GTZC_TZIC_IER4_PWRIE_Msk (0x01UL << GTZC_TZIC_IER4_PWRIE_Pos) +#define GTZC_TZIC_IER4_PWRIE GTZC_TZIC_IER4_PWRIE_Msk /*!< illegal access interrupt enable for PWR interface */ +#define GTZC_TZIC_IER4_RCCIE_Pos (11U) +#define GTZC_TZIC_IER4_RCCIE_Msk (0x01UL << GTZC_TZIC_IER4_RCCIE_Pos) +#define GTZC_TZIC_IER4_RCCIE GTZC_TZIC_IER4_RCCIE_Msk /*!< illegal access interrupt enable for RCC interface */ +#define GTZC_TZIC_IER4_EXTIIE_Pos (13U) +#define GTZC_TZIC_IER4_EXTIIE_Msk (0x01UL << GTZC_TZIC_IER4_EXTIIE_Pos) +#define GTZC_TZIC_IER4_EXTIIE GTZC_TZIC_IER4_EXTIIE_Msk /*!< illegal access interrupt enable for EXTI interface */ +#define GTZC_TZIC_IER4_TZSCIE_Pos (14U) +#define GTZC_TZIC_IER4_TZSCIE_Msk (0x01UL << GTZC_TZIC_IER4_TZSCIE_Pos) +#define GTZC_TZIC_IER4_TZSCIE GTZC_TZIC_IER4_TZSCIE_Msk /*!< illegal access interrupt enable for GTZC TZSC */ +#define GTZC_TZIC_IER4_TZICIE_Pos (15U) +#define GTZC_TZIC_IER4_TZICIE_Msk (0x01UL << GTZC_TZIC_IER4_TZICIE_Pos) +#define GTZC_TZIC_IER4_TZICIE GTZC_TZIC_IER4_TZICIE_Msk /*!< illegal access interrupt enable for GTZC TZIC */ +#define GTZC_TZIC_IER4_SRAM1IE_Pos (22U) +#define GTZC_TZIC_IER4_SRAM1IE_Msk (0x01UL << GTZC_TZIC_IER4_SRAM1IE_Pos) +#define GTZC_TZIC_IER4_SRAM1IE GTZC_TZIC_IER4_SRAM1IE_Msk /*!< illegal access interrupt enable for SRAM1 memory */ +#define GTZC_TZIC_IER4_MPCBB1IE_Pos (23U) +#define GTZC_TZIC_IER4_MPCBB1IE_Msk (0x01UL << GTZC_TZIC_IER4_MPCBB1IE_Pos) +#define GTZC_TZIC_IER4_MPCBB1IE GTZC_TZIC_IER4_MPCBB1IE_Msk /*!< illegal access interrupt enable for MPCBB1 */ +#define GTZC_TZIC_IER4_SRAM2IE_Pos (24U) +#define GTZC_TZIC_IER4_SRAM2IE_Msk (0x01UL << GTZC_TZIC_IER4_SRAM2IE_Pos) +#define GTZC_TZIC_IER4_SRAM2IE GTZC_TZIC_IER4_SRAM2IE_Msk /*!< illegal access interrupt enable for SRAM2 memory */ +#define GTZC_TZIC_IER4_MPCBB2IE_Pos (25U) +#define GTZC_TZIC_IER4_MPCBB2IE_Msk (0x01UL << GTZC_TZIC_IER4_MPCBB2IE_Pos) +#define GTZC_TZIC_IER4_MPCBB2IE GTZC_TZIC_IER4_MPCBB2IE_Msk /*!< illegal access interrupt enable for MPCBB2 */ +#define GTZC_TZIC_IER4_SRAM6IE_Pos (30U) +#define GTZC_TZIC_IER4_SRAM6IE_Msk (0x01UL << GTZC_TZIC_IER4_SRAM6IE_Pos) +#define GTZC_TZIC_IER4_SRAM6IE GTZC_TZIC_IER4_SRAM6IE_Msk /*!< illegal access interrupt enable for 2.4GHz TXRX SRAM memory */ +#define GTZC_TZIC_IER4_MPCBB6IE_Pos (31U) +#define GTZC_TZIC_IER4_MPCBB6IE_Msk (0x01UL << GTZC_TZIC_IER4_MPCBB6IE_Pos) +#define GTZC_TZIC_IER4_MPCBB6IE GTZC_TZIC_IER4_MPCBB6IE_Msk /*!< illegal access interrupt enable for MPCBB6 */ + +/******************* Bits definition for GTZC_TZIC_SR1 register **************/ +#define GTZC_TZIC_SR1_TIM2F_Pos (0U) +#define GTZC_TZIC_SR1_TIM2F_Msk (0x01UL << GTZC_TZIC_SR1_TIM2F_Pos) +#define GTZC_TZIC_SR1_TIM2F GTZC_TZIC_SR1_TIM2F_Msk /*!< illegal access flag for TIM2 */ +#define GTZC_TZIC_SR1_TIM3F_Pos (1U) +#define GTZC_TZIC_SR1_TIM3F_Msk (0x01UL << GTZC_TZIC_SR1_TIM3F_Pos) +#define GTZC_TZIC_SR1_TIM3F GTZC_TZIC_SR1_TIM3F_Msk /*!< illegal access flag for TIM3 */ +#define GTZC_TZIC_SR1_WWDGF_Pos (6U) +#define GTZC_TZIC_SR1_WWDGF_Msk (0x01UL << GTZC_TZIC_SR1_WWDGF_Pos) +#define GTZC_TZIC_SR1_WWDGF GTZC_TZIC_SR1_WWDGF_Msk /*!< illegal access flag for WWDG */ +#define GTZC_TZIC_SR1_IWDGF_Pos (7U) +#define GTZC_TZIC_SR1_IWDGF_Msk (0x01UL << GTZC_TZIC_SR1_IWDGF_Pos) +#define GTZC_TZIC_SR1_IWDGF GTZC_TZIC_SR1_IWDGF_Msk /*!< illegal access flag for IWDG */ +#define GTZC_TZIC_SR1_USART2F_Pos (9U) +#define GTZC_TZIC_SR1_USART2F_Msk (0x01UL << GTZC_TZIC_SR1_USART2F_Pos) +#define GTZC_TZIC_SR1_USART2F GTZC_TZIC_SR1_USART2F_Msk /*!< illegal access flag for USART2 */ +#define GTZC_TZIC_SR1_I2C1F_Pos (13U) +#define GTZC_TZIC_SR1_I2C1F_Msk (0x01UL << GTZC_TZIC_SR1_I2C1F_Pos) +#define GTZC_TZIC_SR1_I2C1F GTZC_TZIC_SR1_I2C1F_Msk /*!< illegal access flag for I2C1 */ +#define GTZC_TZIC_SR1_LPTIM2F_Pos (17U) +#define GTZC_TZIC_SR1_LPTIM2F_Msk (0x01UL << GTZC_TZIC_SR1_LPTIM2F_Pos) +#define GTZC_TZIC_SR1_LPTIM2F GTZC_TZIC_SR1_LPTIM2F_Msk /*!< illegal access flag for LPTIM2 */ + +/******************* Bits definition for GTZC_TZIC_SR2 register **************/ +#define GTZC_TZIC_SR2_TIM1F_Pos (0U) +#define GTZC_TZIC_SR2_TIM1F_Msk (0x01UL << GTZC_TZIC_SR2_TIM1F_Pos) +#define GTZC_TZIC_SR2_TIM1F GTZC_TZIC_SR2_TIM1F_Msk /*!< illegal access flag for TIM1 */ +#define GTZC_TZIC_SR2_SPI1F_Pos (1U) +#define GTZC_TZIC_SR2_SPI1F_Msk (0x01UL << GTZC_TZIC_SR2_SPI1F_Pos) +#define GTZC_TZIC_SR2_SPI1F GTZC_TZIC_SR2_SPI1F_Msk /*!< illegal access flag for SPI1 */ +#define GTZC_TZIC_SR2_USART1F_Pos (3U) +#define GTZC_TZIC_SR2_USART1F_Msk (0x01UL << GTZC_TZIC_SR2_USART1F_Pos) +#define GTZC_TZIC_SR2_USART1F GTZC_TZIC_SR2_USART1F_Msk /*!< illegal access flag for USART1 */ +#define GTZC_TZIC_SR2_TIM16F_Pos (5U) +#define GTZC_TZIC_SR2_TIM16F_Msk (0x01UL << GTZC_TZIC_SR2_TIM16F_Pos) +#define GTZC_TZIC_SR2_TIM16F GTZC_TZIC_SR2_TIM16F_Msk /*!< illegal access flag for TIM16 */ +#define GTZC_TZIC_SR2_TIM17F_Pos (6U) +#define GTZC_TZIC_SR2_TIM17F_Msk (0x01UL << GTZC_TZIC_SR2_TIM17F_Pos) +#define GTZC_TZIC_SR2_TIM17F GTZC_TZIC_SR2_TIM17F_Msk /*!< illegal access flag for TIM17 */ +#define GTZC_TZIC_SR2_SPI3F_Pos (16U) +#define GTZC_TZIC_SR2_SPI3F_Msk (0x01UL << GTZC_TZIC_SR2_SPI3F_Pos) +#define GTZC_TZIC_SR2_SPI3F GTZC_TZIC_SR2_SPI3F_Msk /*!< illegal access flag for SPI3 */ +#define GTZC_TZIC_SR2_LPUART1F_Pos (17U) +#define GTZC_TZIC_SR2_LPUART1F_Msk (0x01UL << GTZC_TZIC_SR2_LPUART1F_Pos) +#define GTZC_TZIC_SR2_LPUART1F GTZC_TZIC_SR2_LPUART1F_Msk /*!< illegal access flag for LPUART1 */ +#define GTZC_TZIC_SR2_I2C3F_Pos (18U) +#define GTZC_TZIC_SR2_I2C3F_Msk (0x01UL << GTZC_TZIC_SR2_I2C3F_Pos) +#define GTZC_TZIC_SR2_I2C3F GTZC_TZIC_SR2_I2C3F_Msk /*!< illegal access flag for I2C3 */ +#define GTZC_TZIC_SR2_LPTIM1F_Pos (19U) +#define GTZC_TZIC_SR2_LPTIM1F_Msk (0x01UL << GTZC_TZIC_SR2_LPTIM1F_Pos) +#define GTZC_TZIC_SR2_LPTIM1F GTZC_TZIC_SR2_LPTIM1F_Msk /*!< illegal access flag for LPTIM1 */ +#define GTZC_TZIC_SR2_ADC4F_Pos (24U) +#define GTZC_TZIC_SR2_ADC4F_Msk (0x01UL << GTZC_TZIC_SR2_ADC4F_Pos) +#define GTZC_TZIC_SR2_ADC4F GTZC_TZIC_SR2_ADC4F_Msk /*!< illegal access flag for ADC4 */ + +/******************* Bits definition for GTZC_TZIC_SR3 register **************/ +#define GTZC_TZIC_SR3_CRCF_Pos (3U) +#define GTZC_TZIC_SR3_CRCF_Msk (0x01UL << GTZC_TZIC_SR3_CRCF_Pos) +#define GTZC_TZIC_SR3_CRCF GTZC_TZIC_SR3_CRCF_Msk /*!< illegal access flag for CRC */ +#define GTZC_TZIC_SR3_TSCF_Pos (4U) +#define GTZC_TZIC_SR3_TSCF_Msk (0x01UL << GTZC_TZIC_SR3_TSCF_Pos) +#define GTZC_TZIC_SR3_TSCF GTZC_TZIC_SR3_TSCF_Msk /*!< illegal access flag for TSC */ +#define GTZC_TZIC_SR3_ICACHE_REGF_Pos (6U) +#define GTZC_TZIC_SR3_ICACHE_REGF_Msk (0x01UL << GTZC_TZIC_SR3_ICACHE_REGF_Pos) +#define GTZC_TZIC_SR3_ICACHE_REGF GTZC_TZIC_SR3_ICACHE_REGF_Msk /*!< illegal access flag for ICACHE_REG */ +#define GTZC_TZIC_SR3_AESF_Pos (11U) +#define GTZC_TZIC_SR3_AESF_Msk (0x01UL << GTZC_TZIC_SR3_AESF_Pos) +#define GTZC_TZIC_SR3_AESF GTZC_TZIC_SR3_AESF_Msk /*!< illegal access flag for AES */ +#define GTZC_TZIC_SR3_HASHF_Pos (12U) +#define GTZC_TZIC_SR3_HASHF_Msk (0x01UL << GTZC_TZIC_SR3_HASHF_Pos) +#define GTZC_TZIC_SR3_HASHF GTZC_TZIC_SR3_HASHF_Msk /*!< illegal access flag for HASH */ +#define GTZC_TZIC_SR3_RNGF_Pos (13U) +#define GTZC_TZIC_SR3_RNGF_Msk (0x01UL << GTZC_TZIC_SR3_RNGF_Pos) +#define GTZC_TZIC_SR3_RNGF GTZC_TZIC_SR3_RNGF_Msk /*!< illegal access flag for RNG */ +#define GTZC_TZIC_SR3_SAESF_Pos (14U) +#define GTZC_TZIC_SR3_SAESF_Msk (0x01UL << GTZC_TZIC_SR3_SAESF_Pos) +#define GTZC_TZIC_SR3_SAESF GTZC_TZIC_SR3_SAESF_Msk /*!< illegal access flag for SAES */ +#define GTZC_TZIC_SR3_HSEMF_Pos (15U) +#define GTZC_TZIC_SR3_HSEMF_Msk (0x01UL << GTZC_TZIC_SR3_HSEMF_Pos) +#define GTZC_TZIC_SR3_HSEMF GTZC_TZIC_SR3_HSEMF_Msk /*!< illegal access flag for HSEM */ +#define GTZC_TZIC_SR3_PKAF_Pos (16U) +#define GTZC_TZIC_SR3_PKAF_Msk (0x01UL << GTZC_TZIC_SR3_PKAF_Pos) +#define GTZC_TZIC_SR3_PKAF GTZC_TZIC_SR3_PKAF_Msk /*!< illegal access flag for PKA */ +#define GTZC_TZIC_SR3_RAMCFGF_Pos (22U) +#define GTZC_TZIC_SR3_RAMCFGF_Msk (0x01UL << GTZC_TZIC_SR3_RAMCFGF_Pos) +#define GTZC_TZIC_SR3_RAMCFGF GTZC_TZIC_SR3_RAMCFGF_Msk /*!< illegal access flag for RAMCFG */ +#define GTZC_TZIC_SR3_RADIOF_Pos (23U) +#define GTZC_TZIC_SR3_RADIOF_Msk (0x01UL << GTZC_TZIC_SR3_RADIOF_Pos) +#define GTZC_TZIC_SR3_RADIOF GTZC_TZIC_SR3_RADIOF_Msk /*!< illegal access flag for 2.4 GHz RADIO */ + +/******************* Bits definition for GTZC_TZIC_SR4 register ***************/ +#define GTZC_TZIC_SR4_GPDMA1F_Pos (0U) +#define GTZC_TZIC_SR4_GPDMA1F_Msk (0x01UL << GTZC_TZIC_SR4_GPDMA1F_Pos) +#define GTZC_TZIC_SR4_GPDMA1F GTZC_TZIC_SR4_GPDMA1F_Msk /*!< illegal access flag for GPDMA1 */ +#define GTZC_TZIC_SR4_FLASHF_Pos (1U) +#define GTZC_TZIC_SR4_FLASHF_Msk (0x01UL << GTZC_TZIC_SR4_FLASHF_Pos) +#define GTZC_TZIC_SR4_FLASHF GTZC_TZIC_SR4_FLASHF_Msk /*!< illegal access flag for FLASH memory */ +#define GTZC_TZIC_SR4_FLASH_REGF_Pos (2U) +#define GTZC_TZIC_SR4_FLASH_REGF_Msk (0x01UL << GTZC_TZIC_SR4_FLASH_REGF_Pos) +#define GTZC_TZIC_SR4_FLASH_REGF GTZC_TZIC_SR4_FLASH_REGF_Msk /*!< illegal access flag for FLASH interface */ +#define GTZC_TZIC_SR4_SYSCFGF_Pos (7U) +#define GTZC_TZIC_SR4_SYSCFGF_Msk (0x01UL << GTZC_TZIC_SR4_SYSCFGF_Pos) +#define GTZC_TZIC_SR4_SYSCFGF GTZC_TZIC_SR4_SYSCFGF_Msk /*!< illegal access flag for SYSCFG interface */ +#define GTZC_TZIC_SR4_RTCF_Pos (8U) +#define GTZC_TZIC_SR4_RTCF_Msk (0x01UL << GTZC_TZIC_SR4_RTCF_Pos) +#define GTZC_TZIC_SR4_RTCF GTZC_TZIC_SR4_RTCF_Msk /*!< illegal access flag for RTC interface */ +#define GTZC_TZIC_SR4_TAMPF_Pos (9U) +#define GTZC_TZIC_SR4_TAMPF_Msk (0x01UL << GTZC_TZIC_SR4_TAMPF_Pos) +#define GTZC_TZIC_SR4_TAMPF GTZC_TZIC_SR4_TAMPF_Msk /*!< illegal access flag for TAMP interface */ +#define GTZC_TZIC_SR4_PWRF_Pos (10U) +#define GTZC_TZIC_SR4_PWRF_Msk (0x01UL << GTZC_TZIC_SR4_PWRF_Pos) +#define GTZC_TZIC_SR4_PWRF GTZC_TZIC_SR4_PWRF_Msk /*!< illegal access flag for PWR interface */ +#define GTZC_TZIC_SR4_RCCF_Pos (11U) +#define GTZC_TZIC_SR4_RCCF_Msk (0x01UL << GTZC_TZIC_SR4_RCCF_Pos) +#define GTZC_TZIC_SR4_RCCF GTZC_TZIC_SR4_RCCF_Msk /*!< illegal access flag for RCC interface */ +#define GTZC_TZIC_SR4_EXTIF_Pos (13U) +#define GTZC_TZIC_SR4_EXTIF_Msk (0x01UL << GTZC_TZIC_SR4_EXTIF_Pos) +#define GTZC_TZIC_SR4_EXTIF GTZC_TZIC_SR4_EXTIF_Msk /*!< illegal access flag for EXTI interface */ +#define GTZC_TZIC_SR4_TZSCF_Pos (14U) +#define GTZC_TZIC_SR4_TZSCF_Msk (0x01UL << GTZC_TZIC_SR4_TZSCF_Pos) +#define GTZC_TZIC_SR4_TZSCF GTZC_TZIC_SR4_TZSCF_Msk /*!< illegal access flag for GTZC TZSC */ +#define GTZC_TZIC_SR4_TZICF_Pos (15U) +#define GTZC_TZIC_SR4_TZICF_Msk (0x01UL << GTZC_TZIC_SR4_TZICF_Pos) +#define GTZC_TZIC_SR4_TZICF GTZC_TZIC_SR4_TZICF_Msk /*!< illegal access flag for GTZC TZIC */ +#define GTZC_TZIC_SR4_SRAM1F_Pos (22U) +#define GTZC_TZIC_SR4_SRAM1F_Msk (0x01UL << GTZC_TZIC_SR4_SRAM1F_Pos) +#define GTZC_TZIC_SR4_SRAM1F GTZC_TZIC_SR4_SRAM1F_Msk /*!< illegal access flag for SRAM1 memory */ +#define GTZC_TZIC_SR4_MPCBB1F_Pos (23U) +#define GTZC_TZIC_SR4_MPCBB1F_Msk (0x01UL << GTZC_TZIC_SR4_MPCBB1F_Pos) +#define GTZC_TZIC_SR4_MPCBB1F GTZC_TZIC_SR4_MPCBB1F_Msk /*!< illegal access flag for MPCBB1 */ +#define GTZC_TZIC_SR4_SRAM2F_Pos (24U) +#define GTZC_TZIC_SR4_SRAM2F_Msk (0x01UL << GTZC_TZIC_SR4_SRAM2F_Pos) +#define GTZC_TZIC_SR4_SRAM2F GTZC_TZIC_SR4_SRAM2F_Msk /*!< illegal access flag for SRAM2 memory */ +#define GTZC_TZIC_SR4_MPCBB2F_Pos (25U) +#define GTZC_TZIC_SR4_MPCBB2F_Msk (0x01UL << GTZC_TZIC_SR4_MPCBB2F_Pos) +#define GTZC_TZIC_SR4_MPCBB2F GTZC_TZIC_SR4_MPCBB2F_Msk /*!< illegal access flag for MPCBB2 */ +#define GTZC_TZIC_SR4_SRAM6F_Pos (30U) +#define GTZC_TZIC_SR4_SRAM6F_Msk (0x01UL << GTZC_TZIC_SR4_SRAM6F_Pos) +#define GTZC_TZIC_SR4_SRAM6F GTZC_TZIC_SR4_SRAM6F_Msk /*!< illegal access flag for 2.4GHz TXRX SRAM memory */ +#define GTZC_TZIC_SR4_MPCBB6F_Pos (31U) +#define GTZC_TZIC_SR4_MPCBB6F_Msk (0x01UL << GTZC_TZIC_SR4_MPCBB6F_Pos) +#define GTZC_TZIC_SR4_MPCBB6F GTZC_TZIC_SR4_MPCBB6F_Msk /*!< illegal access flag for MPCBB6 */ + +/****************** Bits definition for GTZC_TZIC_FCR1 register ****************/ +#define GTZC_TZIC_FCR1_CTIM2F_Pos (0U) +#define GTZC_TZIC_FCR1_CTIM2F_Msk (0x01UL << GTZC_TZIC_FCR1_CTIM2F_Pos) +#define GTZC_TZIC_FCR1_CTIM2F GTZC_TZIC_FCR1_CTIM2F_Msk /*!< clear the illegal access flag for TIM2 */ +#define GTZC_TZIC_FCR1_CTIM3F_Pos (1U) +#define GTZC_TZIC_FCR1_CTIM3F_Msk (0x01UL << GTZC_TZIC_FCR1_CTIM3F_Pos) +#define GTZC_TZIC_FCR1_CTIM3F GTZC_TZIC_FCR1_CTIM3F_Msk /*!< clear the illegal access flag for TIM3 */ +#define GTZC_TZIC_FCR1_CWWDGF_Pos (6U) +#define GTZC_TZIC_FCR1_CWWDGF_Msk (0x01UL << GTZC_TZIC_FCR1_CWWDGF_Pos) +#define GTZC_TZIC_FCR1_CWWDGF GTZC_TZIC_FCR1_CWWDGF_Msk /*!< clear the illegal access flag for WWDG */ +#define GTZC_TZIC_FCR1_CIWDGF_Pos (7U) +#define GTZC_TZIC_FCR1_CIWDGF_Msk (0x01UL << GTZC_TZIC_FCR1_CIWDGF_Pos) +#define GTZC_TZIC_FCR1_CIWDGF GTZC_TZIC_FCR1_CIWDGF_Msk /*!< clear the illegal access flag for IWDG */ +#define GTZC_TZIC_FCR1_CUSART2F_Pos (9U) +#define GTZC_TZIC_FCR1_CUSART2F_Msk (0x01UL << GTZC_TZIC_FCR1_CUSART2F_Pos) +#define GTZC_TZIC_FCR1_CUSART2F GTZC_TZIC_FCR1_CUSART2F_Msk /*!< clear the illegal access flag for USART2 */ +#define GTZC_TZIC_FCR1_CI2C1F_Pos (13U) +#define GTZC_TZIC_FCR1_CI2C1F_Msk (0x01UL << GTZC_TZIC_FCR1_CI2C1F_Pos) +#define GTZC_TZIC_FCR1_CI2C1F GTZC_TZIC_FCR1_CI2C1F_Msk /*!< clear the illegal access flag for I2C1 */ +#define GTZC_TZIC_FCR1_CLPTIM2F_Pos (17U) +#define GTZC_TZIC_FCR1_CLPTIM2F_Msk (0x01UL << GTZC_TZIC_FCR1_CLPTIM2F_Pos) +#define GTZC_TZIC_FCR1_CLPTIM2F GTZC_TZIC_FCR1_CLPTIM2F_Msk /*!< clear the illegal access flag for LPTIM2 */ + +/****************** Bits definition for GTZC_TZIC_FCR2 register ****************/ +#define GTZC_TZIC_FCR2_CTIM1F_Pos (0U) +#define GTZC_TZIC_FCR2_CTIM1F_Msk (0x01UL << GTZC_TZIC_FCR2_CTIM1F_Pos) +#define GTZC_TZIC_FCR2_CTIM1F GTZC_TZIC_FCR2_CTIM1F_Msk /*!< clear the illegal access flag for TIM1 */ +#define GTZC_TZIC_FCR2_CSPI1F_Pos (1U) +#define GTZC_TZIC_FCR2_CSPI1F_Msk (0x01UL << GTZC_TZIC_FCR2_CSPI1F_Pos) +#define GTZC_TZIC_FCR2_CSPI1F GTZC_TZIC_FCR2_CSPI1F_Msk /*!< clear the illegal access flag for SPI1 */ +#define GTZC_TZIC_FCR2_CUSART1F_Pos (3U) +#define GTZC_TZIC_FCR2_CUSART1F_Msk (0x01UL << GTZC_TZIC_FCR2_CUSART1F_Pos) +#define GTZC_TZIC_FCR2_CUSART1F GTZC_TZIC_FCR2_CUSART1F_Msk /*!< clear the illegal access flag for USART1 */ +#define GTZC_TZIC_FCR2_CTIM16F_Pos (5U) +#define GTZC_TZIC_FCR2_CTIM16F_Msk (0x01UL << GTZC_TZIC_FCR2_CTIM16F_Pos) +#define GTZC_TZIC_FCR2_CTIM16F GTZC_TZIC_FCR2_CTIM16F_Msk /*!< clear the illegal access flag for TIM16 */ +#define GTZC_TZIC_FCR2_CTIM17F_Pos (6U) +#define GTZC_TZIC_FCR2_CTIM17F_Msk (0x01UL << GTZC_TZIC_FCR2_CTIM17F_Pos) +#define GTZC_TZIC_FCR2_CTIM17F GTZC_TZIC_FCR2_CTIM17F_Msk /*!< clear the illegal access flag for TIM17 */ +#define GTZC_TZIC_FCR2_CSPI3F_Pos (16U) +#define GTZC_TZIC_FCR2_CSPI3F_Msk (0x01UL << GTZC_TZIC_FCR2_CSPI3F_Pos) +#define GTZC_TZIC_FCR2_CSPI3F GTZC_TZIC_FCR2_CSPI3F_Msk /*!< clear the illegal access flag for SPI3 */ +#define GTZC_TZIC_FCR2_CLPUART1F_Pos (17U) +#define GTZC_TZIC_FCR2_CLPUART1F_Msk (0x01UL << GTZC_TZIC_FCR2_CLPUART1F_Pos) +#define GTZC_TZIC_FCR2_CLPUART1F GTZC_TZIC_FCR2_CLPUART1F_Msk /*!< clear the illegal access flag for LPUART1 */ +#define GTZC_TZIC_FCR2_CI2C3F_Pos (18U) +#define GTZC_TZIC_FCR2_CI2C3F_Msk (0x01UL << GTZC_TZIC_FCR2_CI2C3F_Pos) +#define GTZC_TZIC_FCR2_CI2C3F GTZC_TZIC_FCR2_CI2C3F_Msk /*!< clear the illegal access flag for I2C3 */ +#define GTZC_TZIC_FCR2_CLPTIM1F_Pos (19U) +#define GTZC_TZIC_FCR2_CLPTIM1F_Msk (0x01UL << GTZC_TZIC_FCR2_CLPTIM1F_Pos) +#define GTZC_TZIC_FCR2_CLPTIM1F GTZC_TZIC_FCR2_CLPTIM1F_Msk /*!< clear the illegal access flag for LPTIM1 */ +#define GTZC_TZIC_FCR2_CADC4F_Pos (24U) +#define GTZC_TZIC_FCR2_CADC4F_Msk (0x01UL << GTZC_TZIC_FCR2_CADC4F_Pos) +#define GTZC_TZIC_FCR2_CADC4F GTZC_TZIC_FCR2_CADC4F_Msk /*!< clear the illegal access flag for ADC4 */ + +/****************** Bits definition for GTZC_TZIC_FCR3 register ****************/ +#define GTZC_TZIC_FCR3_CCRCF_Pos (3U) +#define GTZC_TZIC_FCR3_CCRCF_Msk (0x01UL << GTZC_TZIC_FCR3_CCRCF_Pos) +#define GTZC_TZIC_FCR3_CCRCF GTZC_TZIC_FCR3_CCRCF_Msk /*!< clear the illegal access flag enable for CRC */ +#define GTZC_TZIC_FCR3_CTSCF_Pos (4U) +#define GTZC_TZIC_FCR3_CTSCF_Msk (0x01UL << GTZC_TZIC_FCR3_CTSCF_Pos) +#define GTZC_TZIC_FCR3_CTSCF GTZC_TZIC_FCR3_CTSCF_Msk /*!< clear the illegal access flag enable for TSC */ +#define GTZC_TZIC_FCR3_CICACHE_REGF_Pos (6U) +#define GTZC_TZIC_FCR3_CICACHE_REGF_Msk (0x01UL << GTZC_TZIC_FCR3_CICACHE_REGF_Pos) +#define GTZC_TZIC_FCR3_CICACHE_REGF GTZC_TZIC_FCR3_CICACHE_REGF_Msk /*!< clear the illegal access flag enable for ICACHE_REG */ +#define GTZC_TZIC_FCR3_CAESF_Pos (11U) +#define GTZC_TZIC_FCR3_CAESF_Msk (0x01UL << GTZC_TZIC_FCR3_CAESF_Pos) +#define GTZC_TZIC_FCR3_CAESF GTZC_TZIC_FCR3_CAESF_Msk /*!< clear the illegal access flag enable for AES */ +#define GTZC_TZIC_FCR3_CHASHF_Pos (12U) +#define GTZC_TZIC_FCR3_CHASHF_Msk (0x01UL << GTZC_TZIC_FCR3_CHASHF_Pos) +#define GTZC_TZIC_FCR3_CHASHF GTZC_TZIC_FCR3_CHASHF_Msk /*!< clear the illegal access flag enable for HASH */ +#define GTZC_TZIC_FCR3_CRNGF_Pos (13U) +#define GTZC_TZIC_FCR3_CRNGF_Msk (0x01UL << GTZC_TZIC_FCR3_CRNGF_Pos) +#define GTZC_TZIC_FCR3_CRNGF GTZC_TZIC_FCR3_CRNGF_Msk /*!< clear the illegal access flag enable for RNG */ +#define GTZC_TZIC_FCR3_CSAESF_Pos (14U) +#define GTZC_TZIC_FCR3_CSAESF_Msk (0x01UL << GTZC_TZIC_FCR3_CSAESF_Pos) +#define GTZC_TZIC_FCR3_CSAESF GTZC_TZIC_FCR3_CSAESF_Msk /*!< clear the illegal access flag enable for SAES */ +#define GTZC_TZIC_FCR3_CHSEMF_Pos (15U) +#define GTZC_TZIC_FCR3_CHSEMF_Msk (0x01UL << GTZC_TZIC_FCR3_CHSEMF_Pos) +#define GTZC_TZIC_FCR3_CHSEMF GTZC_TZIC_FCR3_CHSEMF_Msk /*!< clear the illegal access flag enable for HSEM */ +#define GTZC_TZIC_FCR3_CPKAF_Pos (16U) +#define GTZC_TZIC_FCR3_CPKAF_Msk (0x01UL << GTZC_TZIC_FCR3_CPKAF_Pos) +#define GTZC_TZIC_FCR3_CPKAF GTZC_TZIC_FCR3_CPKAF_Msk /*!< clear the illegal access flag enable for PKA */ +#define GTZC_TZIC_FCR3_CRAMCFGF_Pos (22U) +#define GTZC_TZIC_FCR3_CRAMCFGF_Msk (0x01UL << GTZC_TZIC_FCR3_CRAMCFGF_Pos) +#define GTZC_TZIC_FCR3_CRAMCFGF GTZC_TZIC_FCR3_CRAMCFGF_Msk /*!< clear the illegal access flag enable for RAMCFG */ +#define GTZC_TZIC_FCR3_CRADIOF_Pos (23U) +#define GTZC_TZIC_FCR3_CRADIOF_Msk (0x01UL << GTZC_TZIC_FCR3_CRADIOF_Pos) +#define GTZC_TZIC_FCR3_CRADIOF GTZC_TZIC_FCR3_CRADIOF_Msk /*!< clear the illegal access flag enable for 2.4 GHz RADIO */ + +/****************** Bits definition for GTZC_TZIC_FCR4 register ****************/ +#define GTZC_TZIC_FCR4_CGPDMA1F_Pos (0U) +#define GTZC_TZIC_FCR4_CGPDMA1F_Msk (0x01UL << GTZC_TZIC_FCR4_CGPDMA1F_Pos) +#define GTZC_TZIC_FCR4_CGPDMA1F GTZC_TZIC_FCR4_CGPDMA1F_Msk /*!< clear the illegal access flag enable for GPDMA1 */ +#define GTZC_TZIC_FCR4_CFLASHF_Pos (1U) +#define GTZC_TZIC_FCR4_CFLASHF_Msk (0x01UL << GTZC_TZIC_FCR4_CFLASHF_Pos) +#define GTZC_TZIC_FCR4_CFLASHF GTZC_TZIC_FCR4_CFLASHF_Msk /*!< clear the illegal access flag enable for FLASH memory */ +#define GTZC_TZIC_FCR4_CFLASH_REGF_Pos (2U) +#define GTZC_TZIC_FCR4_CFLASH_REGF_Msk (0x01UL << GTZC_TZIC_FCR4_CFLASH_REGF_Pos) +#define GTZC_TZIC_FCR4_CFLASH_REGF GTZC_TZIC_FCR4_CFLASH_REGF_Msk /*!< clear the illegal access flag enable for FLASH interface */ +#define GTZC_TZIC_FCR4_CSYSCFGF_Pos (7U) +#define GTZC_TZIC_FCR4_CSYSCFGF_Msk (0x01UL << GTZC_TZIC_FCR4_CSYSCFGF_Pos) +#define GTZC_TZIC_FCR4_CSYSCFGF GTZC_TZIC_FCR4_CSYSCFGF_Msk /*!< clear the illegal access flag enable for SYSCFG interface */ +#define GTZC_TZIC_FCR4_CRTCF_Pos (8U) +#define GTZC_TZIC_FCR4_CRTCF_Msk (0x01UL << GTZC_TZIC_FCR4_CRTCF_Pos) +#define GTZC_TZIC_FCR4_CRTCF GTZC_TZIC_FCR4_CRTCF_Msk /*!< clear the illegal access flag enable for RTC interface */ +#define GTZC_TZIC_FCR4_CTAMPF_Pos (9U) +#define GTZC_TZIC_FCR4_CTAMPF_Msk (0x01UL << GTZC_TZIC_FCR4_CTAMPF_Pos) +#define GTZC_TZIC_FCR4_CTAMPF GTZC_TZIC_FCR4_CTAMPF_Msk /*!< clear the illegal access flag enable for TAMP interface */ +#define GTZC_TZIC_FCR4_CPWRF_Pos (10U) +#define GTZC_TZIC_FCR4_CPWRF_Msk (0x01UL << GTZC_TZIC_FCR4_CPWRF_Pos) +#define GTZC_TZIC_FCR4_CPWRF GTZC_TZIC_FCR4_CPWRF_Msk /*!< clear the illegal access flag enable for PWR interface */ +#define GTZC_TZIC_FCR4_CRCCF_Pos (11U) +#define GTZC_TZIC_FCR4_CRCCF_Msk (0x01UL << GTZC_TZIC_FCR4_CRCCF_Pos) +#define GTZC_TZIC_FCR4_CRCCF GTZC_TZIC_FCR4_CRCCF_Msk /*!< clear the illegal access flag enable for RCC interface */ +#define GTZC_TZIC_FCR4_CEXTIF_Pos (13U) +#define GTZC_TZIC_FCR4_CEXTIF_Msk (0x01UL << GTZC_TZIC_FCR4_CEXTIF_Pos) +#define GTZC_TZIC_FCR4_CEXTIF GTZC_TZIC_FCR4_CEXTIF_Msk /*!< clear the illegal access flag enable for EXTI interface */ +#define GTZC_TZIC_FCR4_CTZSCF_Pos (14U) +#define GTZC_TZIC_FCR4_CTZSCF_Msk (0x01UL << GTZC_TZIC_FCR4_CTZSCF_Pos) +#define GTZC_TZIC_FCR4_CTZSCF GTZC_TZIC_FCR4_CTZSCF_Msk /*!< clear the illegal access flag enable for GTZC TZSC */ +#define GTZC_TZIC_FCR4_CTZICF_Pos (15U) +#define GTZC_TZIC_FCR4_CTZICF_Msk (0x01UL << GTZC_TZIC_FCR4_CTZICF_Pos) +#define GTZC_TZIC_FCR4_CTZICF GTZC_TZIC_FCR4_CTZICF_Msk /*!< clear the illegal access flag enable for GTZC TZIC */ +#define GTZC_TZIC_FCR4_CSRAM1F_Pos (22U) +#define GTZC_TZIC_FCR4_CSRAM1F_Msk (0x01UL << GTZC_TZIC_FCR4_CSRAM1F_Pos) +#define GTZC_TZIC_FCR4_CSRAM1F GTZC_TZIC_FCR4_CSRAM1F_Msk /*!< clear the illegal access flag enable for SRAM1 memory */ +#define GTZC_TZIC_FCR4_CMPCBB1F_Pos (23U) +#define GTZC_TZIC_FCR4_CMPCBB1F_Msk (0x01UL << GTZC_TZIC_FCR4_CMPCBB1F_Pos) +#define GTZC_TZIC_FCR4_CMPCBB1F GTZC_TZIC_FCR4_CMPCBB1F_Msk /*!< clear the illegal access flag enable for MPCBB1 */ +#define GTZC_TZIC_FCR4_CSRAM2F_Pos (24U) +#define GTZC_TZIC_FCR4_CSRAM2F_Msk (0x01UL << GTZC_TZIC_FCR4_CSRAM2F_Pos) +#define GTZC_TZIC_FCR4_CSRAM2F GTZC_TZIC_FCR4_CSRAM2F_Msk /*!< clear the illegal access flag enable for SRAM2 memory */ +#define GTZC_TZIC_FCR4_CMPCBB2F_Pos (25U) +#define GTZC_TZIC_FCR4_CMPCBB2F_Msk (0x01UL << GTZC_TZIC_FCR4_CMPCBB2F_Pos) +#define GTZC_TZIC_FCR4_CMPCBB2F GTZC_TZIC_FCR4_CMPCBB2F_Msk /*!< clear the illegal access flag enable for MPCBB2 */ +#define GTZC_TZIC_FCR4_CSRAM6F_Pos (30U) +#define GTZC_TZIC_FCR4_CSRAM6F_Msk (0x01UL << GTZC_TZIC_FCR4_CSRAM6F_Pos) +#define GTZC_TZIC_FCR4_CSRAM6F GTZC_TZIC_FCR4_CSRAM6F_Msk /*!< clear the illegal access flag enable for 2.4GHz TXRX SRAM memory */ +#define GTZC_TZIC_FCR4_CMPCBB6F_Pos (31U) +#define GTZC_TZIC_FCR4_CMPCBB6F_Msk (0x01UL << GTZC_TZIC_FCR4_CMPCBB6F_Pos) +#define GTZC_TZIC_FCR4_CMPCBB6F GTZC_TZIC_FCR4_CMPCBB6F_Msk /*!< clear the illegal access flag enable for MPCBB6 */ + +/******************* Bits definition for GTZC_MPCBB_CR register *****************/ +#define GTZC_MPCBB_CR_GLOCK_Pos (0U) +#define GTZC_MPCBB_CR_GLOCK_Msk (0x01UL << GTZC_MPCBB_CR_GLOCK_Pos) /*!< 0x00000001 */ +#define GTZC_MPCBB_CR_GLOCK GTZC_MPCBB_CR_GLOCK_Msk /*!< lock the control register of the MPCBB until next reset */ +#define GTZC_MPCBB_CR_INVSECSTATE_Pos (30U) +#define GTZC_MPCBB_CR_INVSECSTATE_Msk (0x01UL << GTZC_MPCBB_CR_INVSECSTATE_Pos) /*!< 0x40000000 */ +#define GTZC_MPCBB_CR_INVSECSTATE GTZC_MPCBB_CR_INVSECSTATE_Msk /*!< SRAM clocks security state */ +#define GTZC_MPCBB_CR_SRWILADIS_Pos (31U) +#define GTZC_MPCBB_CR_SRWILADIS_Msk (0x01UL << GTZC_MPCBB_CR_SRWILADIS_Pos) /*!< 0x80000000 */ +#define GTZC_MPCBB_CR_SRWILADIS GTZC_MPCBB_CR_SRWILADIS_Msk /*!< secure read/write illegal access disable */ + +/******************* Bits definition for GTZC_MPCBB_CFGLOCK register ************/ +#define GTZC_MPCBB_CFGLOCK_SPLCK0_Pos (0U) +#define GTZC_MPCBB_CFGLOCK_SPLCK0_Msk (0x01UL << GTZC_MPCBB_CFGLOCK_SPLCK0_Pos) /*!< 0x00000001 */ +#define GTZC_MPCBB_CFGLOCK_SPLCK0 GTZC_MPCBB_CFGLOCK_SPLCK0_Msk /*!< Security/privilege configuration lock super-block 0 */ +#define GTZC_MPCBB_CFGLOCK_SPLCK1_Pos (1U) +#define GTZC_MPCBB_CFGLOCK_SPLCK1_Msk (0x01UL << GTZC_MPCBB_CFGLOCK_SPLCK1_Pos) /*!< 0x00000002 */ +#define GTZC_MPCBB_CFGLOCK_SPLCK1 GTZC_MPCBB_CFGLOCK_SPLCK1_Msk /*!< Security/privilege configuration lock super-block 1 */ +#define GTZC_MPCBB_CFGLOCK_SPLCK2_Pos (2U) +#define GTZC_MPCBB_CFGLOCK_SPLCK2_Msk (0x01UL << GTZC_MPCBB_CFGLOCK_SPLCK2_Pos) /*!< 0x00000004 */ +#define GTZC_MPCBB_CFGLOCK_SPLCK2 GTZC_MPCBB_CFGLOCK_SPLCK2_Msk /*!< Security/privilege configuration lock super-block 2 */ +#define GTZC_MPCBB_CFGLOCK_SPLCK3_Pos (3U) +#define GTZC_MPCBB_CFGLOCK_SPLCK3_Msk (0x01UL << GTZC_MPCBB_CFGLOCK_SPLCK3_Pos) /*!< 0x00000008 */ +#define GTZC_MPCBB_CFGLOCK_SPLCK3 GTZC_MPCBB_CFGLOCK_SPLCK3_Msk /*!< Security/privilege configuration lock super-block 3 */ + +/******************* Bits definition for GTZC_MPCBB_SECCFGR0 register ************/ +#define GTZC_MPCBB_SECCFGR0_SEC0_Pos (0U) +#define GTZC_MPCBB_SECCFGR0_SEC0_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC0_Pos) /*!< 0x00000001 */ +#define GTZC_MPCBB_SECCFGR0_SEC0 GTZC_MPCBB_SECCFGR0_SEC0_Msk /*!< Security configuration for block 0 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC1_Pos (1U) +#define GTZC_MPCBB_SECCFGR0_SEC1_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC1_Pos) /*!< 0x00000002 */ +#define GTZC_MPCBB_SECCFGR0_SEC1 GTZC_MPCBB_SECCFGR0_SEC1_Msk /*!< Security configuration for block 1 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC2_Pos (2U) +#define GTZC_MPCBB_SECCFGR0_SEC2_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC2_Pos) /*!< 0x00000004 */ +#define GTZC_MPCBB_SECCFGR0_SEC2 GTZC_MPCBB_SECCFGR0_SEC2_Msk /*!< Security configuration for block 2 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC3_Pos (3U) +#define GTZC_MPCBB_SECCFGR0_SEC3_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC3_Pos) /*!< 0x00000008 */ +#define GTZC_MPCBB_SECCFGR0_SEC3 GTZC_MPCBB_SECCFGR0_SEC3_Msk /*!< Security configuration for block 3 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC4_Pos (4U) +#define GTZC_MPCBB_SECCFGR0_SEC4_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC4_Pos) /*!< 0x00000010 */ +#define GTZC_MPCBB_SECCFGR0_SEC4 GTZC_MPCBB_SECCFGR0_SEC4_Msk /*!< Security configuration for block 4 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC5_Pos (5U) +#define GTZC_MPCBB_SECCFGR0_SEC5_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC5_Pos) /*!< 0x00000020 */ +#define GTZC_MPCBB_SECCFGR0_SEC5 GTZC_MPCBB_SECCFGR0_SEC5_Msk /*!< Security configuration for block 5 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC6_Pos (6U) +#define GTZC_MPCBB_SECCFGR0_SEC6_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC6_Pos) /*!< 0x00000040 */ +#define GTZC_MPCBB_SECCFGR0_SEC6 GTZC_MPCBB_SECCFGR0_SEC6_Msk /*!< Security configuration for block 6 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC7_Pos (7U) +#define GTZC_MPCBB_SECCFGR0_SEC7_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC7_Pos) /*!< 0x00000080 */ +#define GTZC_MPCBB_SECCFGR0_SEC7 GTZC_MPCBB_SECCFGR0_SEC7_Msk /*!< Security configuration for block 7 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC8_Pos (8U) +#define GTZC_MPCBB_SECCFGR0_SEC8_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC8_Pos) /*!< 0x00000100 */ +#define GTZC_MPCBB_SECCFGR0_SEC8 GTZC_MPCBB_SECCFGR0_SEC8_Msk /*!< Security configuration for block 8 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC9_Pos (9U) +#define GTZC_MPCBB_SECCFGR0_SEC9_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC9_Pos) /*!< 0x00000200 */ +#define GTZC_MPCBB_SECCFGR0_SEC9 GTZC_MPCBB_SECCFGR0_SEC9_Msk /*!< Security configuration for block 9 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC10_Pos (10U) +#define GTZC_MPCBB_SECCFGR0_SEC10_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC10_Pos) /*!< 0x00000400 */ +#define GTZC_MPCBB_SECCFGR0_SEC10 GTZC_MPCBB_SECCFGR0_SEC10_Msk /*!< Security configuration for block 10 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC11_Pos (11U) +#define GTZC_MPCBB_SECCFGR0_SEC11_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC11_Pos) /*!< 0x00000800 */ +#define GTZC_MPCBB_SECCFGR0_SEC11 GTZC_MPCBB_SECCFGR0_SEC11_Msk /*!< Security configuration for block 11 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC12_Pos (12U) +#define GTZC_MPCBB_SECCFGR0_SEC12_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC12_Pos) /*!< 0x00001000 */ +#define GTZC_MPCBB_SECCFGR0_SEC12 GTZC_MPCBB_SECCFGR0_SEC12_Msk /*!< Security configuration for block 12 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC13_Pos (13U) +#define GTZC_MPCBB_SECCFGR0_SEC13_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC13_Pos) /*!< 0x00002000 */ +#define GTZC_MPCBB_SECCFGR0_SEC13 GTZC_MPCBB_SECCFGR0_SEC13_Msk /*!< Security configuration for block 13 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC14_Pos (14U) +#define GTZC_MPCBB_SECCFGR0_SEC14_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC14_Pos) /*!< 0x00004000 */ +#define GTZC_MPCBB_SECCFGR0_SEC14 GTZC_MPCBB_SECCFGR0_SEC14_Msk /*!< Security configuration for block 14 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC15_Pos (15U) +#define GTZC_MPCBB_SECCFGR0_SEC15_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC15_Pos) /*!< 0x00008000 */ +#define GTZC_MPCBB_SECCFGR0_SEC15 GTZC_MPCBB_SECCFGR0_SEC15_Msk /*!< Security configuration for block 15 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC16_Pos (16U) +#define GTZC_MPCBB_SECCFGR0_SEC16_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC16_Pos) /*!< 0x00010000 */ +#define GTZC_MPCBB_SECCFGR0_SEC16 GTZC_MPCBB_SECCFGR0_SEC16_Msk /*!< Security configuration for block 16 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC17_Pos (17U) +#define GTZC_MPCBB_SECCFGR0_SEC17_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC17_Pos) /*!< 0x00020000 */ +#define GTZC_MPCBB_SECCFGR0_SEC17 GTZC_MPCBB_SECCFGR0_SEC17_Msk /*!< Security configuration for block 17 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC18_Pos (18U) +#define GTZC_MPCBB_SECCFGR0_SEC18_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC18_Pos) /*!< 0x00040000 */ +#define GTZC_MPCBB_SECCFGR0_SEC18 GTZC_MPCBB_SECCFGR0_SEC18_Msk /*!< Security configuration for block 18 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC19_Pos (19U) +#define GTZC_MPCBB_SECCFGR0_SEC19_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC19_Pos) /*!< 0x00080000 */ +#define GTZC_MPCBB_SECCFGR0_SEC19 GTZC_MPCBB_SECCFGR0_SEC19_Msk /*!< Security configuration for block 19 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC20_Pos (20U) +#define GTZC_MPCBB_SECCFGR0_SEC20_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC20_Pos) /*!< 0x00100000 */ +#define GTZC_MPCBB_SECCFGR0_SEC20 GTZC_MPCBB_SECCFGR0_SEC20_Msk /*!< Security configuration for block 20 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC21_Pos (21U) +#define GTZC_MPCBB_SECCFGR0_SEC21_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC21_Pos) /*!< 0x00200000 */ +#define GTZC_MPCBB_SECCFGR0_SEC21 GTZC_MPCBB_SECCFGR0_SEC21_Msk /*!< Security configuration for block 21 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC22_Pos (22U) +#define GTZC_MPCBB_SECCFGR0_SEC22_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC22_Pos) /*!< 0x00400000 */ +#define GTZC_MPCBB_SECCFGR0_SEC22 GTZC_MPCBB_SECCFGR0_SEC22_Msk /*!< Security configuration for block 22 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC23_Pos (23U) +#define GTZC_MPCBB_SECCFGR0_SEC23_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC23_Pos) /*!< 0x00800000 */ +#define GTZC_MPCBB_SECCFGR0_SEC23 GTZC_MPCBB_SECCFGR0_SEC23_Msk /*!< Security configuration for block 23 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC24_Pos (24U) +#define GTZC_MPCBB_SECCFGR0_SEC24_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC24_Pos) /*!< 0x01000000 */ +#define GTZC_MPCBB_SECCFGR0_SEC24 GTZC_MPCBB_SECCFGR0_SEC24_Msk /*!< Security configuration for block 24 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC25_Pos (25U) +#define GTZC_MPCBB_SECCFGR0_SEC25_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC25_Pos) /*!< 0x02000000 */ +#define GTZC_MPCBB_SECCFGR0_SEC25 GTZC_MPCBB_SECCFGR0_SEC25_Msk /*!< Security configuration for block 25 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC26_Pos (26U) +#define GTZC_MPCBB_SECCFGR0_SEC26_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC26_Pos) /*!< 0x04000000 */ +#define GTZC_MPCBB_SECCFGR0_SEC26 GTZC_MPCBB_SECCFGR0_SEC26_Msk /*!< Security configuration for block 26 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC27_Pos (27U) +#define GTZC_MPCBB_SECCFGR0_SEC27_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC27_Pos) /*!< 0x08000000 */ +#define GTZC_MPCBB_SECCFGR0_SEC27 GTZC_MPCBB_SECCFGR0_SEC27_Msk /*!< Security configuration for block 27 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC28_Pos (28U) +#define GTZC_MPCBB_SECCFGR0_SEC28_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC28_Pos) /*!< 0x10000000 */ +#define GTZC_MPCBB_SECCFGR0_SEC28 GTZC_MPCBB_SECCFGR0_SEC28_Msk /*!< Security configuration for block 28 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC29_Pos (29U) +#define GTZC_MPCBB_SECCFGR0_SEC29_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC29_Pos) /*!< 0x20000000 */ +#define GTZC_MPCBB_SECCFGR0_SEC29 GTZC_MPCBB_SECCFGR0_SEC29_Msk /*!< Security configuration for block 29 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC30_Pos (30U) +#define GTZC_MPCBB_SECCFGR0_SEC30_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC30_Pos) /*!< 0x40000000 */ +#define GTZC_MPCBB_SECCFGR0_SEC30 GTZC_MPCBB_SECCFGR0_SEC31_Msk /*!< Security configuration for block 30 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC31_Pos (31U) +#define GTZC_MPCBB_SECCFGR0_SEC31_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC31_Pos) /*!< 0x80000000 */ +#define GTZC_MPCBB_SECCFGR0_SEC31 GTZC_MPCBB_SECCFGR0_SEC31_Msk /*!< Security configuration for block 31 in super block 0 */ + +/******************* Bits definition for GTZC_MPCBB_SECCFGR1 register ************/ +#define GTZC_MPCBB_SECCFGR1_SEC0_Pos (0U) +#define GTZC_MPCBB_SECCFGR1_SEC0_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC0_Pos) /*!< 0x00000001 */ +#define GTZC_MPCBB_SECCFGR1_SEC0 GTZC_MPCBB_SECCFGR1_SEC0_Msk /*!< Security configuration for block 0 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC1_Pos (1U) +#define GTZC_MPCBB_SECCFGR1_SEC1_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC1_Pos) /*!< 0x00000002 */ +#define GTZC_MPCBB_SECCFGR1_SEC1 GTZC_MPCBB_SECCFGR1_SEC1_Msk /*!< Security configuration for block 1 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC2_Pos (2U) +#define GTZC_MPCBB_SECCFGR1_SEC2_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC2_Pos) /*!< 0x00000004 */ +#define GTZC_MPCBB_SECCFGR1_SEC2 GTZC_MPCBB_SECCFGR1_SEC2_Msk /*!< Security configuration for block 2 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC3_Pos (3U) +#define GTZC_MPCBB_SECCFGR1_SEC3_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC3_Pos) /*!< 0x00000008 */ +#define GTZC_MPCBB_SECCFGR1_SEC3 GTZC_MPCBB_SECCFGR1_SEC3_Msk /*!< Security configuration for block 3 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC4_Pos (4U) +#define GTZC_MPCBB_SECCFGR1_SEC4_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC4_Pos) /*!< 0x00000010 */ +#define GTZC_MPCBB_SECCFGR1_SEC4 GTZC_MPCBB_SECCFGR1_SEC4_Msk /*!< Security configuration for block 4 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC5_Pos (5U) +#define GTZC_MPCBB_SECCFGR1_SEC5_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC5_Pos) /*!< 0x00000020 */ +#define GTZC_MPCBB_SECCFGR1_SEC5 GTZC_MPCBB_SECCFGR1_SEC5_Msk /*!< Security configuration for block 5 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC6_Pos (6U) +#define GTZC_MPCBB_SECCFGR1_SEC6_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC6_Pos) /*!< 0x00000040 */ +#define GTZC_MPCBB_SECCFGR1_SEC6 GTZC_MPCBB_SECCFGR1_SEC6_Msk /*!< Security configuration for block 6 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC7_Pos (7U) +#define GTZC_MPCBB_SECCFGR1_SEC7_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC7_Pos) /*!< 0x00000080 */ +#define GTZC_MPCBB_SECCFGR1_SEC7 GTZC_MPCBB_SECCFGR1_SEC7_Msk /*!< Security configuration for block 7 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC8_Pos (8U) +#define GTZC_MPCBB_SECCFGR1_SEC8_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC8_Pos) /*!< 0x00000100 */ +#define GTZC_MPCBB_SECCFGR1_SEC8 GTZC_MPCBB_SECCFGR1_SEC8_Msk /*!< Security configuration for block 8 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC9_Pos (9U) +#define GTZC_MPCBB_SECCFGR1_SEC9_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC9_Pos) /*!< 0x00000200 */ +#define GTZC_MPCBB_SECCFGR1_SEC9 GTZC_MPCBB_SECCFGR1_SEC9_Msk /*!< Security configuration for block 9 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC10_Pos (10U) +#define GTZC_MPCBB_SECCFGR1_SEC10_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC10_Pos) /*!< 0x00000400 */ +#define GTZC_MPCBB_SECCFGR1_SEC10 GTZC_MPCBB_SECCFGR1_SEC10_Msk /*!< Security configuration for block 10 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC11_Pos (11U) +#define GTZC_MPCBB_SECCFGR1_SEC11_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC11_Pos) /*!< 0x00000800 */ +#define GTZC_MPCBB_SECCFGR1_SEC11 GTZC_MPCBB_SECCFGR1_SEC11_Msk /*!< Security configuration for block 11 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC12_Pos (12U) +#define GTZC_MPCBB_SECCFGR1_SEC12_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC12_Pos) /*!< 0x00001000 */ +#define GTZC_MPCBB_SECCFGR1_SEC12 GTZC_MPCBB_SECCFGR1_SEC12_Msk /*!< Security configuration for block 12 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC13_Pos (13U) +#define GTZC_MPCBB_SECCFGR1_SEC13_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC13_Pos) /*!< 0x00002000 */ +#define GTZC_MPCBB_SECCFGR1_SEC13 GTZC_MPCBB_SECCFGR1_SEC13_Msk /*!< Security configuration for block 13 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC14_Pos (14U) +#define GTZC_MPCBB_SECCFGR1_SEC14_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC14_Pos) /*!< 0x00004000 */ +#define GTZC_MPCBB_SECCFGR1_SEC14 GTZC_MPCBB_SECCFGR1_SEC14_Msk /*!< Security configuration for block 14 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC15_Pos (15U) +#define GTZC_MPCBB_SECCFGR1_SEC15_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC15_Pos) /*!< 0x00008000 */ +#define GTZC_MPCBB_SECCFGR1_SEC15 GTZC_MPCBB_SECCFGR1_SEC15_Msk /*!< Security configuration for block 15 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC16_Pos (16U) +#define GTZC_MPCBB_SECCFGR1_SEC16_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC16_Pos) /*!< 0x00010000 */ +#define GTZC_MPCBB_SECCFGR1_SEC16 GTZC_MPCBB_SECCFGR1_SEC16_Msk /*!< Security configuration for block 16 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC17_Pos (17U) +#define GTZC_MPCBB_SECCFGR1_SEC17_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC17_Pos) /*!< 0x00020000 */ +#define GTZC_MPCBB_SECCFGR1_SEC17 GTZC_MPCBB_SECCFGR1_SEC17_Msk /*!< Security configuration for block 17 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC18_Pos (18U) +#define GTZC_MPCBB_SECCFGR1_SEC18_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC18_Pos) /*!< 0x00040000 */ +#define GTZC_MPCBB_SECCFGR1_SEC18 GTZC_MPCBB_SECCFGR1_SEC18_Msk /*!< Security configuration for block 18 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC19_Pos (19U) +#define GTZC_MPCBB_SECCFGR1_SEC19_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC19_Pos) /*!< 0x00080000 */ +#define GTZC_MPCBB_SECCFGR1_SEC19 GTZC_MPCBB_SECCFGR1_SEC19_Msk /*!< Security configuration for block 19 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC20_Pos (20U) +#define GTZC_MPCBB_SECCFGR1_SEC20_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC20_Pos) /*!< 0x00100000 */ +#define GTZC_MPCBB_SECCFGR1_SEC20 GTZC_MPCBB_SECCFGR1_SEC20_Msk /*!< Security configuration for block 20 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC21_Pos (21U) +#define GTZC_MPCBB_SECCFGR1_SEC21_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC21_Pos) /*!< 0x00200000 */ +#define GTZC_MPCBB_SECCFGR1_SEC21 GTZC_MPCBB_SECCFGR1_SEC21_Msk /*!< Security configuration for block 21 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC22_Pos (22U) +#define GTZC_MPCBB_SECCFGR1_SEC22_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC22_Pos) /*!< 0x00400000 */ +#define GTZC_MPCBB_SECCFGR1_SEC22 GTZC_MPCBB_SECCFGR1_SEC22_Msk /*!< Security configuration for block 22 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC23_Pos (23U) +#define GTZC_MPCBB_SECCFGR1_SEC23_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC23_Pos) /*!< 0x00800000 */ +#define GTZC_MPCBB_SECCFGR1_SEC23 GTZC_MPCBB_SECCFGR1_SEC23_Msk /*!< Security configuration for block 23 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC24_Pos (24U) +#define GTZC_MPCBB_SECCFGR1_SEC24_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC24_Pos) /*!< 0x01000000 */ +#define GTZC_MPCBB_SECCFGR1_SEC24 GTZC_MPCBB_SECCFGR1_SEC24_Msk /*!< Security configuration for block 24 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC25_Pos (25U) +#define GTZC_MPCBB_SECCFGR1_SEC25_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC25_Pos) /*!< 0x02000000 */ +#define GTZC_MPCBB_SECCFGR1_SEC25 GTZC_MPCBB_SECCFGR1_SEC25_Msk /*!< Security configuration for block 25 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC26_Pos (26U) +#define GTZC_MPCBB_SECCFGR1_SEC26_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC26_Pos) /*!< 0x04000000 */ +#define GTZC_MPCBB_SECCFGR1_SEC26 GTZC_MPCBB_SECCFGR1_SEC26_Msk /*!< Security configuration for block 26 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC27_Pos (27U) +#define GTZC_MPCBB_SECCFGR1_SEC27_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC27_Pos) /*!< 0x08000000 */ +#define GTZC_MPCBB_SECCFGR1_SEC27 GTZC_MPCBB_SECCFGR1_SEC27_Msk /*!< Security configuration for block 27 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC28_Pos (28U) +#define GTZC_MPCBB_SECCFGR1_SEC28_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC28_Pos) /*!< 0x10000000 */ +#define GTZC_MPCBB_SECCFGR1_SEC28 GTZC_MPCBB_SECCFGR1_SEC28_Msk /*!< Security configuration for block 28 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC29_Pos (29U) +#define GTZC_MPCBB_SECCFGR1_SEC29_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC29_Pos) /*!< 0x20000000 */ +#define GTZC_MPCBB_SECCFGR1_SEC29 GTZC_MPCBB_SECCFGR1_SEC29_Msk /*!< Security configuration for block 29 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC30_Pos (30U) +#define GTZC_MPCBB_SECCFGR1_SEC30_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC30_Pos) /*!< 0x40000000 */ +#define GTZC_MPCBB_SECCFGR1_SEC30 GTZC_MPCBB_SECCFGR1_SEC31_Msk /*!< Security configuration for block 30 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC31_Pos (31U) +#define GTZC_MPCBB_SECCFGR1_SEC31_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC31_Pos) /*!< 0x80000000 */ +#define GTZC_MPCBB_SECCFGR1_SEC31 GTZC_MPCBB_SECCFGR1_SEC31_Msk /*!< Security configuration for block 31 in super block 1 */ + +/******************* Bits definition for GTZC_MPCBB_SECCFGR2 register ************/ +#define GTZC_MPCBB_SECCFGR2_SEC0_Pos (0U) +#define GTZC_MPCBB_SECCFGR2_SEC0_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC0_Pos) /*!< 0x00000001 */ +#define GTZC_MPCBB_SECCFGR2_SEC0 GTZC_MPCBB_SECCFGR2_SEC0_Msk /*!< Security configuration for block 0 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC1_Pos (1U) +#define GTZC_MPCBB_SECCFGR2_SEC1_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC1_Pos) /*!< 0x00000002 */ +#define GTZC_MPCBB_SECCFGR2_SEC1 GTZC_MPCBB_SECCFGR2_SEC1_Msk /*!< Security configuration for block 1 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC2_Pos (2U) +#define GTZC_MPCBB_SECCFGR2_SEC2_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC2_Pos) /*!< 0x00000004 */ +#define GTZC_MPCBB_SECCFGR2_SEC2 GTZC_MPCBB_SECCFGR2_SEC2_Msk /*!< Security configuration for block 2 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC3_Pos (3U) +#define GTZC_MPCBB_SECCFGR2_SEC3_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC3_Pos) /*!< 0x00000008 */ +#define GTZC_MPCBB_SECCFGR2_SEC3 GTZC_MPCBB_SECCFGR2_SEC3_Msk /*!< Security configuration for block 3 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC4_Pos (4U) +#define GTZC_MPCBB_SECCFGR2_SEC4_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC4_Pos) /*!< 0x00000010 */ +#define GTZC_MPCBB_SECCFGR2_SEC4 GTZC_MPCBB_SECCFGR2_SEC4_Msk /*!< Security configuration for block 4 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC5_Pos (5U) +#define GTZC_MPCBB_SECCFGR2_SEC5_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC5_Pos) /*!< 0x00000020 */ +#define GTZC_MPCBB_SECCFGR2_SEC5 GTZC_MPCBB_SECCFGR2_SEC5_Msk /*!< Security configuration for block 5 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC6_Pos (6U) +#define GTZC_MPCBB_SECCFGR2_SEC6_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC6_Pos) /*!< 0x00000040 */ +#define GTZC_MPCBB_SECCFGR2_SEC6 GTZC_MPCBB_SECCFGR2_SEC6_Msk /*!< Security configuration for block 6 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC7_Pos (7U) +#define GTZC_MPCBB_SECCFGR2_SEC7_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC7_Pos) /*!< 0x00000080 */ +#define GTZC_MPCBB_SECCFGR2_SEC7 GTZC_MPCBB_SECCFGR2_SEC7_Msk /*!< Security configuration for block 7 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC8_Pos (8U) +#define GTZC_MPCBB_SECCFGR2_SEC8_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC8_Pos) /*!< 0x00000100 */ +#define GTZC_MPCBB_SECCFGR2_SEC8 GTZC_MPCBB_SECCFGR2_SEC8_Msk /*!< Security configuration for block 8 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC9_Pos (9U) +#define GTZC_MPCBB_SECCFGR2_SEC9_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC9_Pos) /*!< 0x00000200 */ +#define GTZC_MPCBB_SECCFGR2_SEC9 GTZC_MPCBB_SECCFGR2_SEC9_Msk /*!< Security configuration for block 9 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC10_Pos (10U) +#define GTZC_MPCBB_SECCFGR2_SEC10_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC10_Pos) /*!< 0x00000400 */ +#define GTZC_MPCBB_SECCFGR2_SEC10 GTZC_MPCBB_SECCFGR2_SEC10_Msk /*!< Security configuration for block 10 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC11_Pos (11U) +#define GTZC_MPCBB_SECCFGR2_SEC11_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC11_Pos) /*!< 0x00000800 */ +#define GTZC_MPCBB_SECCFGR2_SEC11 GTZC_MPCBB_SECCFGR2_SEC11_Msk /*!< Security configuration for block 11 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC12_Pos (12U) +#define GTZC_MPCBB_SECCFGR2_SEC12_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC12_Pos) /*!< 0x00001000 */ +#define GTZC_MPCBB_SECCFGR2_SEC12 GTZC_MPCBB_SECCFGR2_SEC12_Msk /*!< Security configuration for block 12 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC13_Pos (13U) +#define GTZC_MPCBB_SECCFGR2_SEC13_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC13_Pos) /*!< 0x00002000 */ +#define GTZC_MPCBB_SECCFGR2_SEC13 GTZC_MPCBB_SECCFGR2_SEC13_Msk /*!< Security configuration for block 13 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC14_Pos (14U) +#define GTZC_MPCBB_SECCFGR2_SEC14_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC14_Pos) /*!< 0x00004000 */ +#define GTZC_MPCBB_SECCFGR2_SEC14 GTZC_MPCBB_SECCFGR2_SEC14_Msk /*!< Security configuration for block 14 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC15_Pos (15U) +#define GTZC_MPCBB_SECCFGR2_SEC15_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC15_Pos) /*!< 0x00008000 */ +#define GTZC_MPCBB_SECCFGR2_SEC15 GTZC_MPCBB_SECCFGR2_SEC15_Msk /*!< Security configuration for block 15 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC16_Pos (16U) +#define GTZC_MPCBB_SECCFGR2_SEC16_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC16_Pos) /*!< 0x00010000 */ +#define GTZC_MPCBB_SECCFGR2_SEC16 GTZC_MPCBB_SECCFGR2_SEC16_Msk /*!< Security configuration for block 16 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC17_Pos (17U) +#define GTZC_MPCBB_SECCFGR2_SEC17_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC17_Pos) /*!< 0x00020000 */ +#define GTZC_MPCBB_SECCFGR2_SEC17 GTZC_MPCBB_SECCFGR2_SEC17_Msk /*!< Security configuration for block 17 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC18_Pos (18U) +#define GTZC_MPCBB_SECCFGR2_SEC18_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC18_Pos) /*!< 0x00040000 */ +#define GTZC_MPCBB_SECCFGR2_SEC18 GTZC_MPCBB_SECCFGR2_SEC18_Msk /*!< Security configuration for block 18 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC19_Pos (19U) +#define GTZC_MPCBB_SECCFGR2_SEC19_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC19_Pos) /*!< 0x00080000 */ +#define GTZC_MPCBB_SECCFGR2_SEC19 GTZC_MPCBB_SECCFGR2_SEC19_Msk /*!< Security configuration for block 19 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC20_Pos (20U) +#define GTZC_MPCBB_SECCFGR2_SEC20_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC20_Pos) /*!< 0x00100000 */ +#define GTZC_MPCBB_SECCFGR2_SEC20 GTZC_MPCBB_SECCFGR2_SEC20_Msk /*!< Security configuration for block 20 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC21_Pos (21U) +#define GTZC_MPCBB_SECCFGR2_SEC21_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC21_Pos) /*!< 0x00200000 */ +#define GTZC_MPCBB_SECCFGR2_SEC21 GTZC_MPCBB_SECCFGR2_SEC21_Msk /*!< Security configuration for block 21 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC22_Pos (22U) +#define GTZC_MPCBB_SECCFGR2_SEC22_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC22_Pos) /*!< 0x00400000 */ +#define GTZC_MPCBB_SECCFGR2_SEC22 GTZC_MPCBB_SECCFGR2_SEC22_Msk /*!< Security configuration for block 22 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC23_Pos (23U) +#define GTZC_MPCBB_SECCFGR2_SEC23_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC23_Pos) /*!< 0x00800000 */ +#define GTZC_MPCBB_SECCFGR2_SEC23 GTZC_MPCBB_SECCFGR2_SEC23_Msk /*!< Security configuration for block 23 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC24_Pos (24U) +#define GTZC_MPCBB_SECCFGR2_SEC24_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC24_Pos) /*!< 0x01000000 */ +#define GTZC_MPCBB_SECCFGR2_SEC24 GTZC_MPCBB_SECCFGR2_SEC24_Msk /*!< Security configuration for block 24 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC25_Pos (25U) +#define GTZC_MPCBB_SECCFGR2_SEC25_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC25_Pos) /*!< 0x02000000 */ +#define GTZC_MPCBB_SECCFGR2_SEC25 GTZC_MPCBB_SECCFGR2_SEC25_Msk /*!< Security configuration for block 25 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC26_Pos (26U) +#define GTZC_MPCBB_SECCFGR2_SEC26_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC26_Pos) /*!< 0x04000000 */ +#define GTZC_MPCBB_SECCFGR2_SEC26 GTZC_MPCBB_SECCFGR2_SEC26_Msk /*!< Security configuration for block 26 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC27_Pos (27U) +#define GTZC_MPCBB_SECCFGR2_SEC27_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC27_Pos) /*!< 0x08000000 */ +#define GTZC_MPCBB_SECCFGR2_SEC27 GTZC_MPCBB_SECCFGR2_SEC27_Msk /*!< Security configuration for block 27 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC28_Pos (28U) +#define GTZC_MPCBB_SECCFGR2_SEC28_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC28_Pos) /*!< 0x10000000 */ +#define GTZC_MPCBB_SECCFGR2_SEC28 GTZC_MPCBB_SECCFGR2_SEC28_Msk /*!< Security configuration for block 28 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC29_Pos (29U) +#define GTZC_MPCBB_SECCFGR2_SEC29_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC29_Pos) /*!< 0x20000000 */ +#define GTZC_MPCBB_SECCFGR2_SEC29 GTZC_MPCBB_SECCFGR2_SEC29_Msk /*!< Security configuration for block 29 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC30_Pos (30U) +#define GTZC_MPCBB_SECCFGR2_SEC30_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC30_Pos) /*!< 0x40000000 */ +#define GTZC_MPCBB_SECCFGR2_SEC30 GTZC_MPCBB_SECCFGR2_SEC31_Msk /*!< Security configuration for block 30 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC31_Pos (31U) +#define GTZC_MPCBB_SECCFGR2_SEC31_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC31_Pos) /*!< 0x80000000 */ +#define GTZC_MPCBB_SECCFGR2_SEC31 GTZC_MPCBB_SECCFGR2_SEC31_Msk /*!< Security configuration for block 31 in super block 2 */ + +/******************* Bits definition for GTZC_MPCBB_SECCFGR3 register ************/ +#define GTZC_MPCBB_SECCFGR3_SEC0_Pos (0U) +#define GTZC_MPCBB_SECCFGR3_SEC0_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC0_Pos) /*!< 0x00000001 */ +#define GTZC_MPCBB_SECCFGR3_SEC0 GTZC_MPCBB_SECCFGR3_SEC0_Msk /*!< Security configuration for block 0 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC1_Pos (1U) +#define GTZC_MPCBB_SECCFGR3_SEC1_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC1_Pos) /*!< 0x00000002 */ +#define GTZC_MPCBB_SECCFGR3_SEC1 GTZC_MPCBB_SECCFGR3_SEC1_Msk /*!< Security configuration for block 1 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC2_Pos (2U) +#define GTZC_MPCBB_SECCFGR3_SEC2_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC2_Pos) /*!< 0x00000004 */ +#define GTZC_MPCBB_SECCFGR3_SEC2 GTZC_MPCBB_SECCFGR3_SEC2_Msk /*!< Security configuration for block 2 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC3_Pos (3U) +#define GTZC_MPCBB_SECCFGR3_SEC3_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC3_Pos) /*!< 0x00000008 */ +#define GTZC_MPCBB_SECCFGR3_SEC3 GTZC_MPCBB_SECCFGR3_SEC3_Msk /*!< Security configuration for block 3 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC4_Pos (4U) +#define GTZC_MPCBB_SECCFGR3_SEC4_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC4_Pos) /*!< 0x00000010 */ +#define GTZC_MPCBB_SECCFGR3_SEC4 GTZC_MPCBB_SECCFGR3_SEC4_Msk /*!< Security configuration for block 4 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC5_Pos (5U) +#define GTZC_MPCBB_SECCFGR3_SEC5_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC5_Pos) /*!< 0x00000020 */ +#define GTZC_MPCBB_SECCFGR3_SEC5 GTZC_MPCBB_SECCFGR3_SEC5_Msk /*!< Security configuration for block 5 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC6_Pos (6U) +#define GTZC_MPCBB_SECCFGR3_SEC6_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC6_Pos) /*!< 0x00000040 */ +#define GTZC_MPCBB_SECCFGR3_SEC6 GTZC_MPCBB_SECCFGR3_SEC6_Msk /*!< Security configuration for block 6 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC7_Pos (7U) +#define GTZC_MPCBB_SECCFGR3_SEC7_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC7_Pos) /*!< 0x00000080 */ +#define GTZC_MPCBB_SECCFGR3_SEC7 GTZC_MPCBB_SECCFGR3_SEC7_Msk /*!< Security configuration for block 7 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC8_Pos (8U) +#define GTZC_MPCBB_SECCFGR3_SEC8_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC8_Pos) /*!< 0x00000100 */ +#define GTZC_MPCBB_SECCFGR3_SEC8 GTZC_MPCBB_SECCFGR3_SEC8_Msk /*!< Security configuration for block 8 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC9_Pos (9U) +#define GTZC_MPCBB_SECCFGR3_SEC9_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC9_Pos) /*!< 0x00000200 */ +#define GTZC_MPCBB_SECCFGR3_SEC9 GTZC_MPCBB_SECCFGR3_SEC9_Msk /*!< Security configuration for block 9 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC10_Pos (10U) +#define GTZC_MPCBB_SECCFGR3_SEC10_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC10_Pos) /*!< 0x00000400 */ +#define GTZC_MPCBB_SECCFGR3_SEC10 GTZC_MPCBB_SECCFGR3_SEC10_Msk /*!< Security configuration for block 10 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC11_Pos (11U) +#define GTZC_MPCBB_SECCFGR3_SEC11_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC11_Pos) /*!< 0x00000800 */ +#define GTZC_MPCBB_SECCFGR3_SEC11 GTZC_MPCBB_SECCFGR3_SEC11_Msk /*!< Security configuration for block 11 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC12_Pos (12U) +#define GTZC_MPCBB_SECCFGR3_SEC12_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC12_Pos) /*!< 0x00001000 */ +#define GTZC_MPCBB_SECCFGR3_SEC12 GTZC_MPCBB_SECCFGR3_SEC12_Msk /*!< Security configuration for block 12 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC13_Pos (13U) +#define GTZC_MPCBB_SECCFGR3_SEC13_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC13_Pos) /*!< 0x00002000 */ +#define GTZC_MPCBB_SECCFGR3_SEC13 GTZC_MPCBB_SECCFGR3_SEC13_Msk /*!< Security configuration for block 13 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC14_Pos (14U) +#define GTZC_MPCBB_SECCFGR3_SEC14_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC14_Pos) /*!< 0x00004000 */ +#define GTZC_MPCBB_SECCFGR3_SEC14 GTZC_MPCBB_SECCFGR3_SEC14_Msk /*!< Security configuration for block 14 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC15_Pos (15U) +#define GTZC_MPCBB_SECCFGR3_SEC15_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC15_Pos) /*!< 0x00008000 */ +#define GTZC_MPCBB_SECCFGR3_SEC15 GTZC_MPCBB_SECCFGR3_SEC15_Msk /*!< Security configuration for block 15 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC16_Pos (16U) +#define GTZC_MPCBB_SECCFGR3_SEC16_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC16_Pos) /*!< 0x00010000 */ +#define GTZC_MPCBB_SECCFGR3_SEC16 GTZC_MPCBB_SECCFGR3_SEC16_Msk /*!< Security configuration for block 16 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC17_Pos (17U) +#define GTZC_MPCBB_SECCFGR3_SEC17_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC17_Pos) /*!< 0x00020000 */ +#define GTZC_MPCBB_SECCFGR3_SEC17 GTZC_MPCBB_SECCFGR3_SEC17_Msk /*!< Security configuration for block 17 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC18_Pos (18U) +#define GTZC_MPCBB_SECCFGR3_SEC18_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC18_Pos) /*!< 0x00040000 */ +#define GTZC_MPCBB_SECCFGR3_SEC18 GTZC_MPCBB_SECCFGR3_SEC18_Msk /*!< Security configuration for block 18 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC19_Pos (19U) +#define GTZC_MPCBB_SECCFGR3_SEC19_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC19_Pos) /*!< 0x00080000 */ +#define GTZC_MPCBB_SECCFGR3_SEC19 GTZC_MPCBB_SECCFGR3_SEC19_Msk /*!< Security configuration for block 19 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC20_Pos (20U) +#define GTZC_MPCBB_SECCFGR3_SEC20_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC20_Pos) /*!< 0x00100000 */ +#define GTZC_MPCBB_SECCFGR3_SEC20 GTZC_MPCBB_SECCFGR3_SEC20_Msk /*!< Security configuration for block 20 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC21_Pos (21U) +#define GTZC_MPCBB_SECCFGR3_SEC21_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC21_Pos) /*!< 0x00200000 */ +#define GTZC_MPCBB_SECCFGR3_SEC21 GTZC_MPCBB_SECCFGR3_SEC21_Msk /*!< Security configuration for block 21 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC22_Pos (22U) +#define GTZC_MPCBB_SECCFGR3_SEC22_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC22_Pos) /*!< 0x00400000 */ +#define GTZC_MPCBB_SECCFGR3_SEC22 GTZC_MPCBB_SECCFGR3_SEC22_Msk /*!< Security configuration for block 22 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC23_Pos (23U) +#define GTZC_MPCBB_SECCFGR3_SEC23_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC23_Pos) /*!< 0x00800000 */ +#define GTZC_MPCBB_SECCFGR3_SEC23 GTZC_MPCBB_SECCFGR3_SEC23_Msk /*!< Security configuration for block 23 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC24_Pos (24U) +#define GTZC_MPCBB_SECCFGR3_SEC24_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC24_Pos) /*!< 0x01000000 */ +#define GTZC_MPCBB_SECCFGR3_SEC24 GTZC_MPCBB_SECCFGR3_SEC24_Msk /*!< Security configuration for block 24 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC25_Pos (25U) +#define GTZC_MPCBB_SECCFGR3_SEC25_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC25_Pos) /*!< 0x02000000 */ +#define GTZC_MPCBB_SECCFGR3_SEC25 GTZC_MPCBB_SECCFGR3_SEC25_Msk /*!< Security configuration for block 25 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC26_Pos (26U) +#define GTZC_MPCBB_SECCFGR3_SEC26_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC26_Pos) /*!< 0x04000000 */ +#define GTZC_MPCBB_SECCFGR3_SEC26 GTZC_MPCBB_SECCFGR3_SEC26_Msk /*!< Security configuration for block 26 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC27_Pos (27U) +#define GTZC_MPCBB_SECCFGR3_SEC27_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC27_Pos) /*!< 0x08000000 */ +#define GTZC_MPCBB_SECCFGR3_SEC27 GTZC_MPCBB_SECCFGR3_SEC27_Msk /*!< Security configuration for block 27 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC28_Pos (28U) +#define GTZC_MPCBB_SECCFGR3_SEC28_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC28_Pos) /*!< 0x10000000 */ +#define GTZC_MPCBB_SECCFGR3_SEC28 GTZC_MPCBB_SECCFGR3_SEC28_Msk /*!< Security configuration for block 28 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC29_Pos (29U) +#define GTZC_MPCBB_SECCFGR3_SEC29_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC29_Pos) /*!< 0x20000000 */ +#define GTZC_MPCBB_SECCFGR3_SEC29 GTZC_MPCBB_SECCFGR3_SEC29_Msk /*!< Security configuration for block 29 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC30_Pos (30U) +#define GTZC_MPCBB_SECCFGR3_SEC30_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC30_Pos) /*!< 0x40000000 */ +#define GTZC_MPCBB_SECCFGR3_SEC30 GTZC_MPCBB_SECCFGR3_SEC31_Msk /*!< Security configuration for block 30 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC31_Pos (31U) +#define GTZC_MPCBB_SECCFGR3_SEC31_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC31_Pos) /*!< 0x80000000 */ +#define GTZC_MPCBB_SECCFGR3_SEC31 GTZC_MPCBB_SECCFGR3_SEC31_Msk /*!< Security configuration for block 31 in super block 3 */ + +/******************* Bits definition for GTZC_MPCBB_PRIVCFGR0 register ************/ +#define GTZC_MPCBB_PRIVCFGR0_PRIV0_Pos (0U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV0_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV0_Pos) /*!< 0x00000001 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV0 GTZC_MPCBB_PRIVCFGR0_PRIV0_Msk /*!< Privileged configuration for block 0 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV1_Pos (1U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV1_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV1_Pos) /*!< 0x00000002 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV1 GTZC_MPCBB_PRIVCFGR0_PRIV1_Msk /*!< Privileged configuration for block 1 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV2_Pos (2U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV2_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV2_Pos) /*!< 0x00000004 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV2 GTZC_MPCBB_PRIVCFGR0_PRIV2_Msk /*!< Privileged configuration for block 2 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV3_Pos (3U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV3_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV3_Pos) /*!< 0x00000008 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV3 GTZC_MPCBB_PRIVCFGR0_PRIV3_Msk /*!< Privileged configuration for block 3 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV4_Pos (4U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV4_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV4_Pos) /*!< 0x00000010 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV4 GTZC_MPCBB_PRIVCFGR0_PRIV4_Msk /*!< Privileged configuration for block 4 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV5_Pos (5U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV5_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV5_Pos) /*!< 0x00000020 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV5 GTZC_MPCBB_PRIVCFGR0_PRIV5_Msk /*!< Privileged configuration for block 5 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV6_Pos (6U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV6_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV6_Pos) /*!< 0x00000040 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV6 GTZC_MPCBB_PRIVCFGR0_PRIV6_Msk /*!< Privileged configuration for block 6 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV7_Pos (7U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV7_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV7_Pos) /*!< 0x00000080 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV7 GTZC_MPCBB_PRIVCFGR0_PRIV7_Msk /*!< Privileged configuration for block 7 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV8_Pos (8U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV8_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV8_Pos) /*!< 0x00000100 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV8 GTZC_MPCBB_PRIVCFGR0_PRIV8_Msk /*!< Privileged configuration for block 8 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV9_Pos (9U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV9_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV9_Pos) /*!< 0x00000200 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV9 GTZC_MPCBB_PRIVCFGR0_PRIV9_Msk /*!< Privileged configuration for block 9 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV10_Pos (10U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV10_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV10_Pos) /*!< 0x00000400 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV10 GTZC_MPCBB_PRIVCFGR0_PRIV10_Msk /*!< Privileged configuration for block 10 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV11_Pos (11U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV11_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV11_Pos) /*!< 0x00000800 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV11 GTZC_MPCBB_PRIVCFGR0_PRIV11_Msk /*!< Privileged configuration for block 11 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV12_Pos (12U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV12_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV12_Pos) /*!< 0x00001000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV12 GTZC_MPCBB_PRIVCFGR0_PRIV12_Msk /*!< Privileged configuration for block 12 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV13_Pos (13U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV13_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV13_Pos) /*!< 0x00002000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV13 GTZC_MPCBB_PRIVCFGR0_PRIV13_Msk /*!< Privileged configuration for block 13 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV14_Pos (14U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV14_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV14_Pos) /*!< 0x00004000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV14 GTZC_MPCBB_PRIVCFGR0_PRIV14_Msk /*!< Privileged configuration for block 14 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV15_Pos (15U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV15_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV15_Pos) /*!< 0x00008000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV15 GTZC_MPCBB_PRIVCFGR0_PRIV15_Msk /*!< Privileged configuration for block 15 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV16_Pos (16U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV16_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV16_Pos) /*!< 0x00010000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV16 GTZC_MPCBB_PRIVCFGR0_PRIV16_Msk /*!< Privileged configuration for block 16 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV17_Pos (17U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV17_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV17_Pos) /*!< 0x00020000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV17 GTZC_MPCBB_PRIVCFGR0_PRIV17_Msk /*!< Privileged configuration for block 17 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV18_Pos (18U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV18_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV18_Pos) /*!< 0x00040000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV18 GTZC_MPCBB_PRIVCFGR0_PRIV18_Msk /*!< Privileged configuration for block 18 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV19_Pos (19U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV19_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV19_Pos) /*!< 0x00080000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV19 GTZC_MPCBB_PRIVCFGR0_PRIV19_Msk /*!< Privileged configuration for block 19 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV20_Pos (20U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV20_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV20_Pos) /*!< 0x00100000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV20 GTZC_MPCBB_PRIVCFGR0_PRIV20_Msk /*!< Privileged configuration for block 20 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV21_Pos (21U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV21_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV21_Pos) /*!< 0x00200000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV21 GTZC_MPCBB_PRIVCFGR0_PRIV21_Msk /*!< Privileged configuration for block 21 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV22_Pos (22U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV22_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV22_Pos) /*!< 0x00400000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV22 GTZC_MPCBB_PRIVCFGR0_PRIV22_Msk /*!< Privileged configuration for block 22 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV23_Pos (23U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV23_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV23_Pos) /*!< 0x00800000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV23 GTZC_MPCBB_PRIVCFGR0_PRIV23_Msk /*!< Privileged configuration for block 23 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV24_Pos (24U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV24_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV24_Pos) /*!< 0x01000000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV24 GTZC_MPCBB_PRIVCFGR0_PRIV24_Msk /*!< Privileged configuration for block 24 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV25_Pos (25U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV25_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV25_Pos) /*!< 0x02000000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV25 GTZC_MPCBB_PRIVCFGR0_PRIV25_Msk /*!< Privileged configuration for block 25 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV26_Pos (26U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV26_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV26_Pos) /*!< 0x04000000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV26 GTZC_MPCBB_PRIVCFGR0_PRIV26_Msk /*!< Privileged configuration for block 26 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV27_Pos (27U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV27_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV27_Pos) /*!< 0x08000000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV27 GTZC_MPCBB_PRIVCFGR0_PRIV27_Msk /*!< Privileged configuration for block 27 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV28_Pos (28U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV28_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV28_Pos) /*!< 0x10000000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV28 GTZC_MPCBB_PRIVCFGR0_PRIV28_Msk /*!< Privileged configuration for block 28 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV29_Pos (29U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV29_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV29_Pos) /*!< 0x20000000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV29 GTZC_MPCBB_PRIVCFGR0_PRIV29_Msk /*!< Privileged configuration for block 29 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV30_Pos (30U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV30_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV30_Pos) /*!< 0x40000000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV30 GTZC_MPCBB_PRIVCFGR0_PRIV31_Msk /*!< Privileged configuration for block 30 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV31_Pos (31U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV31_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV31_Pos) /*!< 0x80000000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV31 GTZC_MPCBB_PRIVCFGR0_PRIV31_Msk /*!< Privileged configuration for block 31 in super block 0 */ + +/******************* Bits definition for GTZC_MPCBB_PRIVCFGR1 register ************/ +#define GTZC_MPCBB_PRIVCFGR1_PRIV0_Pos (0U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV0_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV0_Pos) /*!< 0x00000001 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV0 GTZC_MPCBB_PRIVCFGR1_PRIV0_Msk /*!< Privileged configuration for block 0 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV1_Pos (1U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV1_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV1_Pos) /*!< 0x00000002 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV1 GTZC_MPCBB_PRIVCFGR1_PRIV1_Msk /*!< Privileged configuration for block 1 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV2_Pos (2U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV2_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV2_Pos) /*!< 0x00000004 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV2 GTZC_MPCBB_PRIVCFGR1_PRIV2_Msk /*!< Privileged configuration for block 2 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV3_Pos (3U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV3_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV3_Pos) /*!< 0x00000008 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV3 GTZC_MPCBB_PRIVCFGR1_PRIV3_Msk /*!< Privileged configuration for block 3 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV4_Pos (4U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV4_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV4_Pos) /*!< 0x00000010 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV4 GTZC_MPCBB_PRIVCFGR1_PRIV4_Msk /*!< Privileged configuration for block 4 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV5_Pos (5U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV5_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV5_Pos) /*!< 0x00000020 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV5 GTZC_MPCBB_PRIVCFGR1_PRIV5_Msk /*!< Privileged configuration for block 5 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV6_Pos (6U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV6_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV6_Pos) /*!< 0x00000040 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV6 GTZC_MPCBB_PRIVCFGR1_PRIV6_Msk /*!< Privileged configuration for block 6 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV7_Pos (7U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV7_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV7_Pos) /*!< 0x00000080 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV7 GTZC_MPCBB_PRIVCFGR1_PRIV7_Msk /*!< Privileged configuration for block 7 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV8_Pos (8U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV8_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV8_Pos) /*!< 0x00000100 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV8 GTZC_MPCBB_PRIVCFGR1_PRIV8_Msk /*!< Privileged configuration for block 8 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV9_Pos (9U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV9_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV9_Pos) /*!< 0x00000200 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV9 GTZC_MPCBB_PRIVCFGR1_PRIV9_Msk /*!< Privileged configuration for block 9 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV10_Pos (10U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV10_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV10_Pos) /*!< 0x00000400 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV10 GTZC_MPCBB_PRIVCFGR1_PRIV10_Msk /*!< Privileged configuration for block 10 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV11_Pos (11U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV11_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV11_Pos) /*!< 0x00000800 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV11 GTZC_MPCBB_PRIVCFGR1_PRIV11_Msk /*!< Privileged configuration for block 11 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV12_Pos (12U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV12_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV12_Pos) /*!< 0x00001000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV12 GTZC_MPCBB_PRIVCFGR1_PRIV12_Msk /*!< Privileged configuration for block 12 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV13_Pos (13U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV13_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV13_Pos) /*!< 0x00002000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV13 GTZC_MPCBB_PRIVCFGR1_PRIV13_Msk /*!< Privileged configuration for block 13 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV14_Pos (14U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV14_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV14_Pos) /*!< 0x00004000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV14 GTZC_MPCBB_PRIVCFGR1_PRIV14_Msk /*!< Privileged configuration for block 14 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV15_Pos (15U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV15_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV15_Pos) /*!< 0x00008000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV15 GTZC_MPCBB_PRIVCFGR1_PRIV15_Msk /*!< Privileged configuration for block 15 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV16_Pos (16U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV16_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV16_Pos) /*!< 0x00010000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV16 GTZC_MPCBB_PRIVCFGR1_PRIV16_Msk /*!< Privileged configuration for block 16 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV17_Pos (17U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV17_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV17_Pos) /*!< 0x00020000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV17 GTZC_MPCBB_PRIVCFGR1_PRIV17_Msk /*!< Privileged configuration for block 17 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV18_Pos (18U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV18_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV18_Pos) /*!< 0x00040000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV18 GTZC_MPCBB_PRIVCFGR1_PRIV18_Msk /*!< Privileged configuration for block 18 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV19_Pos (19U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV19_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV19_Pos) /*!< 0x00080000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV19 GTZC_MPCBB_PRIVCFGR1_PRIV19_Msk /*!< Privileged configuration for block 19 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV20_Pos (20U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV20_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV20_Pos) /*!< 0x00100000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV20 GTZC_MPCBB_PRIVCFGR1_PRIV20_Msk /*!< Privileged configuration for block 20 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV21_Pos (21U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV21_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV21_Pos) /*!< 0x00200000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV21 GTZC_MPCBB_PRIVCFGR1_PRIV21_Msk /*!< Privileged configuration for block 21 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV22_Pos (22U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV22_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV22_Pos) /*!< 0x00400000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV22 GTZC_MPCBB_PRIVCFGR1_PRIV22_Msk /*!< Privileged configuration for block 22 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV23_Pos (23U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV23_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV23_Pos) /*!< 0x00800000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV23 GTZC_MPCBB_PRIVCFGR1_PRIV23_Msk /*!< Privileged configuration for block 23 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV24_Pos (24U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV24_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV24_Pos) /*!< 0x01000000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV24 GTZC_MPCBB_PRIVCFGR1_PRIV24_Msk /*!< Privileged configuration for block 24 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV25_Pos (25U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV25_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV25_Pos) /*!< 0x02000000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV25 GTZC_MPCBB_PRIVCFGR1_PRIV25_Msk /*!< Privileged configuration for block 25 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV26_Pos (26U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV26_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV26_Pos) /*!< 0x04000000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV26 GTZC_MPCBB_PRIVCFGR1_PRIV26_Msk /*!< Privileged configuration for block 26 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV27_Pos (27U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV27_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV27_Pos) /*!< 0x08000000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV27 GTZC_MPCBB_PRIVCFGR1_PRIV27_Msk /*!< Privileged configuration for block 27 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV28_Pos (28U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV28_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV28_Pos) /*!< 0x10000000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV28 GTZC_MPCBB_PRIVCFGR1_PRIV28_Msk /*!< Privileged configuration for block 28 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV29_Pos (29U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV29_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV29_Pos) /*!< 0x20000000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV29 GTZC_MPCBB_PRIVCFGR1_PRIV29_Msk /*!< Privileged configuration for block 29 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV30_Pos (30U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV30_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV30_Pos) /*!< 0x40000000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV30 GTZC_MPCBB_PRIVCFGR1_PRIV31_Msk /*!< Privileged configuration for block 30 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV31_Pos (31U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV31_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV31_Pos) /*!< 0x80000000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV31 GTZC_MPCBB_PRIVCFGR1_PRIV31_Msk /*!< Privileged configuration for block 31 in super block 1 */ + +/******************* Bits definition for GTZC_MPCBB_PRIVCFGR2 register ************/ +#define GTZC_MPCBB_PRIVCFGR2_PRIV0_Pos (0U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV0_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV0_Pos) /*!< 0x00000001 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV0 GTZC_MPCBB_PRIVCFGR2_PRIV0_Msk /*!< Privileged configuration for block 0 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV1_Pos (1U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV1_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV1_Pos) /*!< 0x00000002 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV1 GTZC_MPCBB_PRIVCFGR2_PRIV1_Msk /*!< Privileged configuration for block 1 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV2_Pos (2U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV2_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV2_Pos) /*!< 0x00000004 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV2 GTZC_MPCBB_PRIVCFGR2_PRIV2_Msk /*!< Privileged configuration for block 2 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV3_Pos (3U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV3_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV3_Pos) /*!< 0x00000008 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV3 GTZC_MPCBB_PRIVCFGR2_PRIV3_Msk /*!< Privileged configuration for block 3 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV4_Pos (4U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV4_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV4_Pos) /*!< 0x00000010 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV4 GTZC_MPCBB_PRIVCFGR2_PRIV4_Msk /*!< Privileged configuration for block 4 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV5_Pos (5U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV5_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV5_Pos) /*!< 0x00000020 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV5 GTZC_MPCBB_PRIVCFGR2_PRIV5_Msk /*!< Privileged configuration for block 5 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV6_Pos (6U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV6_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV6_Pos) /*!< 0x00000040 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV6 GTZC_MPCBB_PRIVCFGR2_PRIV6_Msk /*!< Privileged configuration for block 6 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV7_Pos (7U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV7_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV7_Pos) /*!< 0x00000080 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV7 GTZC_MPCBB_PRIVCFGR2_PRIV7_Msk /*!< Privileged configuration for block 7 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV8_Pos (8U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV8_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV8_Pos) /*!< 0x00000100 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV8 GTZC_MPCBB_PRIVCFGR2_PRIV8_Msk /*!< Privileged configuration for block 8 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV9_Pos (9U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV9_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV9_Pos) /*!< 0x00000200 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV9 GTZC_MPCBB_PRIVCFGR2_PRIV9_Msk /*!< Privileged configuration for block 9 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV10_Pos (10U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV10_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV10_Pos) /*!< 0x00000400 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV10 GTZC_MPCBB_PRIVCFGR2_PRIV10_Msk /*!< Privileged configuration for block 10 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV11_Pos (11U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV11_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV11_Pos) /*!< 0x00000800 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV11 GTZC_MPCBB_PRIVCFGR2_PRIV11_Msk /*!< Privileged configuration for block 11 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV12_Pos (12U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV12_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV12_Pos) /*!< 0x00001000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV12 GTZC_MPCBB_PRIVCFGR2_PRIV12_Msk /*!< Privileged configuration for block 12 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV13_Pos (13U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV13_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV13_Pos) /*!< 0x00002000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV13 GTZC_MPCBB_PRIVCFGR2_PRIV13_Msk /*!< Privileged configuration for block 13 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV14_Pos (14U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV14_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV14_Pos) /*!< 0x00004000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV14 GTZC_MPCBB_PRIVCFGR2_PRIV14_Msk /*!< Privileged configuration for block 14 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV15_Pos (15U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV15_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV15_Pos) /*!< 0x00008000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV15 GTZC_MPCBB_PRIVCFGR2_PRIV15_Msk /*!< Privileged configuration for block 15 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV16_Pos (16U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV16_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV16_Pos) /*!< 0x00010000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV16 GTZC_MPCBB_PRIVCFGR2_PRIV16_Msk /*!< Privileged configuration for block 16 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV17_Pos (17U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV17_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV17_Pos) /*!< 0x00020000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV17 GTZC_MPCBB_PRIVCFGR2_PRIV17_Msk /*!< Privileged configuration for block 17 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV18_Pos (18U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV18_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV18_Pos) /*!< 0x00040000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV18 GTZC_MPCBB_PRIVCFGR2_PRIV18_Msk /*!< Privileged configuration for block 18 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV19_Pos (19U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV19_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV19_Pos) /*!< 0x00080000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV19 GTZC_MPCBB_PRIVCFGR2_PRIV19_Msk /*!< Privileged configuration for block 19 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV20_Pos (20U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV20_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV20_Pos) /*!< 0x00100000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV20 GTZC_MPCBB_PRIVCFGR2_PRIV20_Msk /*!< Privileged configuration for block 20 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV21_Pos (21U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV21_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV21_Pos) /*!< 0x00200000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV21 GTZC_MPCBB_PRIVCFGR2_PRIV21_Msk /*!< Privileged configuration for block 21 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV22_Pos (22U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV22_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV22_Pos) /*!< 0x00400000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV22 GTZC_MPCBB_PRIVCFGR2_PRIV22_Msk /*!< Privileged configuration for block 22 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV23_Pos (23U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV23_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV23_Pos) /*!< 0x00800000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV23 GTZC_MPCBB_PRIVCFGR2_PRIV23_Msk /*!< Privileged configuration for block 23 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV24_Pos (24U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV24_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV24_Pos) /*!< 0x01000000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV24 GTZC_MPCBB_PRIVCFGR2_PRIV24_Msk /*!< Privileged configuration for block 24 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV25_Pos (25U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV25_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV25_Pos) /*!< 0x02000000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV25 GTZC_MPCBB_PRIVCFGR2_PRIV25_Msk /*!< Privileged configuration for block 25 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV26_Pos (26U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV26_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV26_Pos) /*!< 0x04000000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV26 GTZC_MPCBB_PRIVCFGR2_PRIV26_Msk /*!< Privileged configuration for block 26 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV27_Pos (27U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV27_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV27_Pos) /*!< 0x08000000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV27 GTZC_MPCBB_PRIVCFGR2_PRIV27_Msk /*!< Privileged configuration for block 27 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV28_Pos (28U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV28_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV28_Pos) /*!< 0x10000000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV28 GTZC_MPCBB_PRIVCFGR2_PRIV28_Msk /*!< Privileged configuration for block 28 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV29_Pos (29U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV29_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV29_Pos) /*!< 0x20000000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV29 GTZC_MPCBB_PRIVCFGR2_PRIV29_Msk /*!< Privileged configuration for block 29 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV30_Pos (30U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV30_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV30_Pos) /*!< 0x40000000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV30 GTZC_MPCBB_PRIVCFGR2_PRIV31_Msk /*!< Privileged configuration for block 30 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV31_Pos (31U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV31_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV31_Pos) /*!< 0x80000000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV31 GTZC_MPCBB_PRIVCFGR2_PRIV31_Msk /*!< Privileged configuration for block 31 in super block 2 */ + +/******************* Bits definition for GTZC_MPCBB_PRIVCFGR3 register ************/ +#define GTZC_MPCBB_PRIVCFGR3_PRIV0_Pos (0U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV0_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV0_Pos) /*!< 0x00000001 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV0 GTZC_MPCBB_PRIVCFGR3_PRIV0_Msk /*!< Privileged configuration for block 0 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV1_Pos (1U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV1_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV1_Pos) /*!< 0x00000002 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV1 GTZC_MPCBB_PRIVCFGR3_PRIV1_Msk /*!< Privileged configuration for block 1 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV2_Pos (2U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV2_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV2_Pos) /*!< 0x00000004 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV2 GTZC_MPCBB_PRIVCFGR3_PRIV2_Msk /*!< Privileged configuration for block 2 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV3_Pos (3U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV3_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV3_Pos) /*!< 0x00000008 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV3 GTZC_MPCBB_PRIVCFGR3_PRIV3_Msk /*!< Privileged configuration for block 3 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV4_Pos (4U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV4_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV4_Pos) /*!< 0x00000010 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV4 GTZC_MPCBB_PRIVCFGR3_PRIV4_Msk /*!< Privileged configuration for block 4 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV5_Pos (5U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV5_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV5_Pos) /*!< 0x00000020 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV5 GTZC_MPCBB_PRIVCFGR3_PRIV5_Msk /*!< Privileged configuration for block 5 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV6_Pos (6U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV6_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV6_Pos) /*!< 0x00000040 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV6 GTZC_MPCBB_PRIVCFGR3_PRIV6_Msk /*!< Privileged configuration for block 6 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV7_Pos (7U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV7_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV7_Pos) /*!< 0x00000080 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV7 GTZC_MPCBB_PRIVCFGR3_PRIV7_Msk /*!< Privileged configuration for block 7 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV8_Pos (8U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV8_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV8_Pos) /*!< 0x00000100 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV8 GTZC_MPCBB_PRIVCFGR3_PRIV8_Msk /*!< Privileged configuration for block 8 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV9_Pos (9U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV9_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV9_Pos) /*!< 0x00000200 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV9 GTZC_MPCBB_PRIVCFGR3_PRIV9_Msk /*!< Privileged configuration for block 9 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV10_Pos (10U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV10_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV10_Pos) /*!< 0x00000400 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV10 GTZC_MPCBB_PRIVCFGR3_PRIV10_Msk /*!< Privileged configuration for block 10 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV11_Pos (11U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV11_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV11_Pos) /*!< 0x00000800 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV11 GTZC_MPCBB_PRIVCFGR3_PRIV11_Msk /*!< Privileged configuration for block 11 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV12_Pos (12U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV12_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV12_Pos) /*!< 0x00001000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV12 GTZC_MPCBB_PRIVCFGR3_PRIV12_Msk /*!< Privileged configuration for block 12 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV13_Pos (13U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV13_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV13_Pos) /*!< 0x00002000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV13 GTZC_MPCBB_PRIVCFGR3_PRIV13_Msk /*!< Privileged configuration for block 13 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV14_Pos (14U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV14_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV14_Pos) /*!< 0x00004000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV14 GTZC_MPCBB_PRIVCFGR3_PRIV14_Msk /*!< Privileged configuration for block 14 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV15_Pos (15U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV15_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV15_Pos) /*!< 0x00008000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV15 GTZC_MPCBB_PRIVCFGR3_PRIV15_Msk /*!< Privileged configuration for block 15 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV16_Pos (16U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV16_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV16_Pos) /*!< 0x00010000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV16 GTZC_MPCBB_PRIVCFGR3_PRIV16_Msk /*!< Privileged configuration for block 16 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV17_Pos (17U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV17_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV17_Pos) /*!< 0x00020000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV17 GTZC_MPCBB_PRIVCFGR3_PRIV17_Msk /*!< Privileged configuration for block 17 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV18_Pos (18U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV18_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV18_Pos) /*!< 0x00040000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV18 GTZC_MPCBB_PRIVCFGR3_PRIV18_Msk /*!< Privileged configuration for block 18 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV19_Pos (19U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV19_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV19_Pos) /*!< 0x00080000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV19 GTZC_MPCBB_PRIVCFGR3_PRIV19_Msk /*!< Privileged configuration for block 19 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV20_Pos (20U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV20_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV20_Pos) /*!< 0x00100000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV20 GTZC_MPCBB_PRIVCFGR3_PRIV20_Msk /*!< Privileged configuration for block 20 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV21_Pos (21U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV21_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV21_Pos) /*!< 0x00200000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV21 GTZC_MPCBB_PRIVCFGR3_PRIV21_Msk /*!< Privileged configuration for block 21 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV22_Pos (22U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV22_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV22_Pos) /*!< 0x00400000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV22 GTZC_MPCBB_PRIVCFGR3_PRIV22_Msk /*!< Privileged configuration for block 22 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV23_Pos (23U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV23_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV23_Pos) /*!< 0x00800000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV23 GTZC_MPCBB_PRIVCFGR3_PRIV23_Msk /*!< Privileged configuration for block 23 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV24_Pos (24U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV24_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV24_Pos) /*!< 0x01000000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV24 GTZC_MPCBB_PRIVCFGR3_PRIV24_Msk /*!< Privileged configuration for block 24 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV25_Pos (25U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV25_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV25_Pos) /*!< 0x02000000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV25 GTZC_MPCBB_PRIVCFGR3_PRIV25_Msk /*!< Privileged configuration for block 25 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV26_Pos (26U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV26_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV26_Pos) /*!< 0x04000000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV26 GTZC_MPCBB_PRIVCFGR3_PRIV26_Msk /*!< Privileged configuration for block 26 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV27_Pos (27U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV27_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV27_Pos) /*!< 0x08000000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV27 GTZC_MPCBB_PRIVCFGR3_PRIV27_Msk /*!< Privileged configuration for block 27 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV28_Pos (28U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV28_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV28_Pos) /*!< 0x10000000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV28 GTZC_MPCBB_PRIVCFGR3_PRIV28_Msk /*!< Privileged configuration for block 28 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV29_Pos (29U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV29_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV29_Pos) /*!< 0x20000000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV29 GTZC_MPCBB_PRIVCFGR3_PRIV29_Msk /*!< Privileged configuration for block 29 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV30_Pos (30U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV30_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV30_Pos) /*!< 0x40000000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV30 GTZC_MPCBB_PRIVCFGR3_PRIV31_Msk /*!< Privileged configuration for block 30 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV31_Pos (31U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV31_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV31_Pos) /*!< 0x80000000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV31 GTZC_MPCBB_PRIVCFGR3_PRIV31_Msk /*!< Privileged configuration for block 31 in super block 3 */ + + +/******************************************************************************/ +/* */ +/* HASH */ +/* */ +/******************************************************************************/ +/****************** Bits definition for HASH_CR register ********************/ +#define HASH_CR_INIT_Pos (2U) +#define HASH_CR_INIT_Msk (0x1UL << HASH_CR_INIT_Pos) /*!< 0x00000004 */ +#define HASH_CR_INIT HASH_CR_INIT_Msk +#define HASH_CR_DMAE_Pos (3U) +#define HASH_CR_DMAE_Msk (0x1UL << HASH_CR_DMAE_Pos) /*!< 0x00000008 */ +#define HASH_CR_DMAE HASH_CR_DMAE_Msk +#define HASH_CR_DATATYPE_Pos (4U) +#define HASH_CR_DATATYPE_Msk (0x3UL << HASH_CR_DATATYPE_Pos) /*!< 0x00000030 */ +#define HASH_CR_DATATYPE HASH_CR_DATATYPE_Msk +#define HASH_CR_DATATYPE_0 (0x1UL << HASH_CR_DATATYPE_Pos) /*!< 0x00000010 */ +#define HASH_CR_DATATYPE_1 (0x2UL << HASH_CR_DATATYPE_Pos) /*!< 0x00000020 */ +#define HASH_CR_MODE_Pos (6U) +#define HASH_CR_MODE_Msk (0x1UL << HASH_CR_MODE_Pos) /*!< 0x00000040 */ +#define HASH_CR_MODE HASH_CR_MODE_Msk +#define HASH_CR_NBW_Pos (8U) +#define HASH_CR_NBW_Msk (0xFUL << HASH_CR_NBW_Pos) /*!< 0x00000F00 */ +#define HASH_CR_NBW HASH_CR_NBW_Msk +#define HASH_CR_NBW_0 (0x1UL << HASH_CR_NBW_Pos) /*!< 0x00000100 */ +#define HASH_CR_NBW_1 (0x2UL << HASH_CR_NBW_Pos) /*!< 0x00000200 */ +#define HASH_CR_NBW_2 (0x4UL << HASH_CR_NBW_Pos) /*!< 0x00000400 */ +#define HASH_CR_NBW_3 (0x8UL << HASH_CR_NBW_Pos) /*!< 0x00000800 */ +#define HASH_CR_DINNE_Pos (12U) +#define HASH_CR_DINNE_Msk (0x1UL << HASH_CR_DINNE_Pos) /*!< 0x00001000 */ +#define HASH_CR_DINNE HASH_CR_DINNE_Msk +#define HASH_CR_MDMAT_Pos (13U) +#define HASH_CR_MDMAT_Msk (0x1UL << HASH_CR_MDMAT_Pos) /*!< 0x00002000 */ +#define HASH_CR_MDMAT HASH_CR_MDMAT_Msk +#define HASH_CR_LKEY_Pos (16U) +#define HASH_CR_LKEY_Msk (0x1UL << HASH_CR_LKEY_Pos) /*!< 0x00010000 */ +#define HASH_CR_LKEY HASH_CR_LKEY_Msk +#define HASH_CR_ALGO_Pos (17U) +#define HASH_CR_ALGO_Msk (0x3UL << HASH_CR_ALGO_Pos) /*!< 0x00040080 */ +#define HASH_CR_ALGO HASH_CR_ALGO_Msk +#define HASH_CR_ALGO_0 (0x1UL << HASH_CR_ALGO_Pos) /*!< 0x00000080 */ +#define HASH_CR_ALGO_1 (0x2UL << HASH_CR_ALGO_Pos) /*!< 0x00040000 */ + +/****************** Bits definition for HASH_STR register *******************/ +#define HASH_STR_NBLW_Pos (0U) +#define HASH_STR_NBLW_Msk (0x1FUL << HASH_STR_NBLW_Pos) /*!< 0x0000001F */ +#define HASH_STR_NBLW HASH_STR_NBLW_Msk +#define HASH_STR_NBLW_0 (0x01UL << HASH_STR_NBLW_Pos) /*!< 0x00000001 */ +#define HASH_STR_NBLW_1 (0x02UL << HASH_STR_NBLW_Pos) /*!< 0x00000002 */ +#define HASH_STR_NBLW_2 (0x04UL << HASH_STR_NBLW_Pos) /*!< 0x00000004 */ +#define HASH_STR_NBLW_3 (0x08UL << HASH_STR_NBLW_Pos) /*!< 0x00000008 */ +#define HASH_STR_NBLW_4 (0x10UL << HASH_STR_NBLW_Pos) /*!< 0x00000010 */ +#define HASH_STR_DCAL_Pos (8U) +#define HASH_STR_DCAL_Msk (0x1UL << HASH_STR_DCAL_Pos) /*!< 0x00000100 */ +#define HASH_STR_DCAL HASH_STR_DCAL_Msk + +/****************** Bits definition for HASH_IMR register *******************/ +#define HASH_IMR_DINIE_Pos (0U) +#define HASH_IMR_DINIE_Msk (0x1UL << HASH_IMR_DINIE_Pos) /*!< 0x00000001 */ +#define HASH_IMR_DINIE HASH_IMR_DINIE_Msk +#define HASH_IMR_DCIE_Pos (1U) +#define HASH_IMR_DCIE_Msk (0x1UL << HASH_IMR_DCIE_Pos) /*!< 0x00000002 */ +#define HASH_IMR_DCIE HASH_IMR_DCIE_Msk + +/****************** Bits definition for HASH_SR register ********************/ +#define HASH_SR_DINIS_Pos (0U) +#define HASH_SR_DINIS_Msk (0x1UL << HASH_SR_DINIS_Pos) /*!< 0x00000001 */ +#define HASH_SR_DINIS HASH_SR_DINIS_Msk +#define HASH_SR_DCIS_Pos (1U) +#define HASH_SR_DCIS_Msk (0x1UL << HASH_SR_DCIS_Pos) /*!< 0x00000002 */ +#define HASH_SR_DCIS HASH_SR_DCIS_Msk +#define HASH_SR_DMAS_Pos (2U) +#define HASH_SR_DMAS_Msk (0x1UL << HASH_SR_DMAS_Pos) /*!< 0x00000004 */ +#define HASH_SR_DMAS HASH_SR_DMAS_Msk +#define HASH_SR_BUSY_Pos (3U) +#define HASH_SR_BUSY_Msk (0x1UL << HASH_SR_BUSY_Pos) /*!< 0x00000008 */ +#define HASH_SR_BUSY HASH_SR_BUSY_Msk +#define HASH_SR_NBWE_Pos (16U) +#define HASH_SR_NBWE_Msk (0xFUL << HASH_SR_NBWE_Pos) /*!< 0x000F0000 */ +#define HASH_SR_NBWE HASH_SR_NBWE_Msk +#define HASH_SR_NBWE_0 (0x01UL << HASH_SR_NBWE_Pos) /*!< 0x00010000 */ +#define HASH_SR_NBWE_1 (0x02UL << HASH_SR_NBWE_Pos) /*!< 0x00020000 */ +#define HASH_SR_NBWE_2 (0x04UL << HASH_SR_NBWE_Pos) /*!< 0x00040000 */ +#define HASH_SR_NBWE_3 (0x08UL << HASH_SR_NBWE_Pos) /*!< 0x00080000 */ +#define HASH_SR_DINNE_Pos (15U) +#define HASH_SR_DINNE_Msk (0x1UL << HASH_SR_DINNE_Pos) /*!< 0x00008000 */ +#define HASH_SR_DINNE HASH_SR_DINNE_Msk +#define HASH_SR_NBWP_Pos (9U) +#define HASH_SR_NBWP_Msk (0xFUL << HASH_SR_NBWP_Pos) /*!< 0x000F0000 */ +#define HASH_SR_NBWP HASH_SR_NBWP_Msk +#define HASH_SR_NBWP_0 (0x01UL << HASH_SR_NBWP_Pos) /*!< 0x000O0200 */ +#define HASH_SR_NBWP_1 (0x02UL << HASH_SR_NBWP_Pos) /*!< 0x00000400 */ +#define HASH_SR_NBWP_2 (0x04UL << HASH_SR_NBWP_Pos) /*!< 0x00000800 */ +#define HASH_SR_NBWP_3 (0x08UL << HASH_SR_NBWP_Pos) /*!< 0x00001000 */ + + +/******************************************************************************/ +/* */ +/* HSEM HW Semaphore */ +/* */ +/******************************************************************************/ +/******************** Bit definition for HSEM_R register ********************/ +#define HSEM_R_PROCID_Pos (0U) +#define HSEM_R_PROCID_Msk (0xFFUL << HSEM_R_PROCID_Pos) /*!< 0x000000FF */ +#define HSEM_R_PROCID HSEM_R_PROCID_Msk /*!>2) /*!< Input modulus number of bits */ +#define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Compute Montgomery parameter output data */ +#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output Montgomery parameter */ + +/* Compute modular exponentiation input data */ +#define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ +#define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ +#define PKA_MODULAR_EXP_IN_EXPONENT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process */ +#define PKA_MODULAR_EXP_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE ((0x16C8UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT ((0x14B8UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process protected exponentiation*/ +#define PKA_MODULAR_EXP_PROTECT_IN_MODULUS ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus to process protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_PHI ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input phi to process protected exponentiation */ + +/* Compute modular exponentiation output data */ +#define PKA_MODULAR_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_ERROR ((0x1298UL - PKA_RAM_OFFSET)>>2) /*!< Output error of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Output base of the exponentiation */ + +/* Compute ECC scalar multiplication input data */ +#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input curve prime order n number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_SCALAR_MUL_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' of KP */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input prime order n */ + +/* Compute ECC scalar multiplication output data */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Point check input data */ +#define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_POINT_CHECK_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_POINT_CHECK_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_POINT_CHECK_IN_MOD_GF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_POINT_CHECK_IN_MONTGOMERY_PARAM ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Point check output data */ +#define PKA_POINT_CHECK_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ + +/* ECDSA signature input data */ +#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECDSA_SIGN_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_SIGN_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input k value of the ECDSA */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_SIGN_IN_HASH_E ((0x0FE8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0x0F28UL - PKA_RAM_OFFSET)>>2) /*!< Input d, private key */ +#define PKA_ECDSA_SIGN_IN_ORDER_N ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA signature output data */ +#define PKA_ECDSA_SIGN_OUT_ERROR ((0x0FE0UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Output signature r */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Output signature s */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x1400UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point X coordinate */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1458UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point Y coordinate */ + + +/* ECDSA verification input data */ +#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x0468UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_A_COEFF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_MOD_GF ((0x04D0UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x0678UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x06D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0x12F8UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point X coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0x1350UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point Y coordinate */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x10E0UL - PKA_RAM_OFFSET)>>2) /*!< Input r, part of the signature */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input s, part of the signature */ +#define PKA_ECDSA_VERIF_IN_HASH_E ((0x13A8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_VERIF_IN_ORDER_N ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA verification output data */ +#define PKA_ECDSA_VERIF_OUT_RESULT ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* RSA CRT exponentiation input data */ +#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operands number of bits */ +#define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input Dp CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input Dq CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x0948UL - PKA_RAM_OFFSET)>>2) /*!< Input qInv CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x0B60UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime p */ +#define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime q */ +#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ + +/* RSA CRT exponentiation output data */ +#define PKA_RSA_CRT_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular reduction input data */ +#define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input operand length */ +#define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus length */ +#define PKA_MODULAR_REDUC_IN_OPERAND ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand */ +#define PKA_MODULAR_REDUC_IN_MODULUS ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Modular reduction output data */ +#define PKA_MODULAR_REDUC_OUT_RESULT ((0xE78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic addition input data */ +#define PKA_ARITHMETIC_ADD_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic addition output data */ +#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic subtraction input data */ +#define PKA_ARITHMETIC_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic subtraction output data */ +#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic multiplication input data */ +#define PKA_ARITHMETIC_MUL_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic multiplication output data */ +#define PKA_ARITHMETIC_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Comparison input data */ +#define PKA_COMPARISON_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_COMPARISON_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_COMPARISON_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Comparison output data */ +#define PKA_COMPARISON_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular addition input data */ +#define PKA_MODULAR_ADD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_ADD_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 (modulus) */ + +/* Modular addition output data */ +#define PKA_MODULAR_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular inversion input data */ +#define PKA_MODULAR_INV_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_INV_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_INV_IN_OP2_MOD ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 (modulus) */ + +/* Modular inversion output data */ +#define PKA_MODULAR_INV_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular subtraction input data */ +#define PKA_MODULAR_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_SUB_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ + +/* Modular subtraction output data */ +#define PKA_MODULAR_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Montgomery multiplication input data */ +#define PKA_MONTGOMERY_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MONTGOMERY_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MONTGOMERY_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Montgomery multiplication output data */ +#define PKA_MONTGOMERY_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Generic Arithmetic input data */ +#define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Generic Arithmetic output data */ +#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result for arithmetic operations */ + +/* Compute ECC complete addition input data */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC complete addition output data */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Output result Z coordinate */ + +/* Compute ECC double base ladder input data */ +#define PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input 'm' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC double base ladder output data */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_ERROR ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Compute ECC projective to affine conversion input data */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P X coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Y coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Z coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2 ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Compute ECC projective to affine conversion output data */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result x affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result y affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + + +/******************************************************************************/ +/* */ +/* Power Control */ +/* */ +/******************************************************************************/ +/******************** Bit definition for PWR_CR1 register *******************/ +#define PWR_CR1_LPMS_Pos (0U) +#define PWR_CR1_LPMS_Msk (0x7UL << PWR_CR1_LPMS_Pos) /*!< 0x00000007 */ +#define PWR_CR1_LPMS PWR_CR1_LPMS_Msk /*!< LPMS[2:0] Low-power mode selection field */ +#define PWR_CR1_LPMS_0 (0x1UL << PWR_CR1_LPMS_Pos) /*!< 0x00000001 */ +#define PWR_CR1_LPMS_1 (0x2UL << PWR_CR1_LPMS_Pos) /*!< 0x00000002 */ +#define PWR_CR1_LPMS_2 (0x4UL << PWR_CR1_LPMS_Pos) /*!< 0x00000004 */ +#define PWR_CR1_R2RSB1_Pos (5U) +#define PWR_CR1_R2RSB1_Msk (0x1UL << PWR_CR1_R2RSB1_Pos) /*!< 0x00000020 */ +#define PWR_CR1_R2RSB1 PWR_CR1_R2RSB1_Msk /*!< SRAM2 Retention in Standby */ +#define PWR_CR1_ULPMEN_Pos (7U) +#define PWR_CR1_ULPMEN_Msk (0x1UL << PWR_CR1_ULPMEN_Pos) /*!< 0x00000080 */ +#define PWR_CR1_ULPMEN PWR_CR1_ULPMEN_Msk /*!< BOR ultra-low power mode in Standby/Shutdown */ +#define PWR_CR1_RADIORSB_Pos (9U) +#define PWR_CR1_RADIORSB_Msk (0x1UL << PWR_CR1_RADIORSB_Pos) /*!< 0x00000200 */ +#define PWR_CR1_RADIORSB PWR_CR1_RADIORSB_Msk /*!< 2.4GHz RADIO SRAMs (TXRX and Sequence) and Sleep clock retention in Standby mode */ +#define PWR_CR1_R1RSB1_Pos (12U) +#define PWR_CR1_R1RSB1_Msk (0x1UL << PWR_CR1_R1RSB1_Pos) /*!< 0x00001000 */ +#define PWR_CR1_R1RSB1 PWR_CR1_R1RSB1_Msk /*!< SRAM1 Page 1 Retention in Standby */ + +/******************** Bit definition for PWR_CR2 register *******************/ +#define PWR_CR2_SRAM1PDS1_Pos (0U) +#define PWR_CR2_SRAM1PDS1_Msk (0x1UL << PWR_CR2_SRAM1PDS1_Pos) /*!< 0x00000001 */ +#define PWR_CR2_SRAM1PDS1 PWR_CR2_SRAM1PDS1_Msk /*!< SRAM1 Page 1 power-down in Stop modes */ +#define PWR_CR2_SRAM2PDS1_Pos (4U) +#define PWR_CR2_SRAM2PDS1_Msk (0x1UL << PWR_CR2_SRAM2PDS1_Pos) /*!< 0x00000010 */ +#define PWR_CR2_SRAM2PDS1 PWR_CR2_SRAM2PDS1_Msk /*!< SRAM2 power-down in Stop modes */ +#define PWR_CR2_ICRAMPDS_Pos (8U) +#define PWR_CR2_ICRAMPDS_Msk (0x1UL << PWR_CR2_ICRAMPDS_Pos) /*!< 0x00000100 */ +#define PWR_CR2_ICRAMPDS PWR_CR2_ICRAMPDS_Msk /*!< ICACHE SRAM power-down in Stop modes */ +#define PWR_CR2_FLASHFWU_Pos (14U) +#define PWR_CR2_FLASHFWU_Msk (0x1UL << PWR_CR2_FLASHFWU_Pos) /*!< 0x00004000 */ +#define PWR_CR2_FLASHFWU PWR_CR2_FLASHFWU_Msk /*!< Flash low-power mode in Stop modes */ + +/******************** Bit definition for PWR_CR3 register *******************/ +#define PWR_CR3_FSTEN_Pos (2U) +#define PWR_CR3_FSTEN_Msk (0x1UL << PWR_CR3_FSTEN_Pos) /*!< 0x00000004 */ +#define PWR_CR3_FSTEN PWR_CR3_FSTEN_Msk /*!< Fast soft start */ + +/******************* Bit definition for PWR_VOSR register *******************/ +#define PWR_VOSR_VOSRDY_Pos (15U) +#define PWR_VOSR_VOSRDY_Msk (0x1UL << PWR_VOSR_VOSRDY_Pos) /*!< 0x00008000 */ +#define PWR_VOSR_VOSRDY PWR_VOSR_VOSRDY_Msk /*!< Ready bit for VCORE voltage scaling output selection */ +#define PWR_VOSR_VOS_Pos (16U) +#define PWR_VOSR_VOS_Msk (0x1UL << PWR_VOSR_VOS_Pos) /*!< 0x00010000 */ +#define PWR_VOSR_VOS PWR_VOSR_VOS_Msk /*!< Voltage scaling range selection */ + +/******************* Bit definition for PWR_SVMCR register ******************/ +#define PWR_SVMCR_PVDE_Pos (4U) +#define PWR_SVMCR_PVDE_Msk (0x1UL << PWR_SVMCR_PVDE_Pos) /*!< 0x00000010 */ +#define PWR_SVMCR_PVDE PWR_SVMCR_PVDE_Msk /*!< Power voltage detector enable */ +#define PWR_SVMCR_PVDLS_Pos (5U) +#define PWR_SVMCR_PVDLS_Msk (0x7UL << PWR_SVMCR_PVDLS_Pos) /*!< 0x000000E0 */ +#define PWR_SVMCR_PVDLS PWR_SVMCR_PVDLS_Msk /*!< PVDLS[2:0] Power voltage detector level selection field */ +#define PWR_SVMCR_PVDLS_0 (0x1UL << PWR_SVMCR_PVDLS_Pos) /*!< 0x00000020 */ +#define PWR_SVMCR_PVDLS_1 (0x2UL << PWR_SVMCR_PVDLS_Pos) /*!< 0x00000040 */ +#define PWR_SVMCR_PVDLS_2 (0x4UL << PWR_SVMCR_PVDLS_Pos) /*!< 0x00000080 */ + +/******************* Bit definition for PWR_WUCR1 register ******************/ +#define PWR_WUCR1_WUPEN1_Pos (0U) +#define PWR_WUCR1_WUPEN1_Msk (0x1UL << PWR_WUCR1_WUPEN1_Pos) /*!< 0x00000001 */ +#define PWR_WUCR1_WUPEN1 PWR_WUCR1_WUPEN1_Msk /*!< Wakeup pin WKUP1 enable */ +#define PWR_WUCR1_WUPEN2_Pos (1U) +#define PWR_WUCR1_WUPEN2_Msk (0x1UL << PWR_WUCR1_WUPEN2_Pos) /*!< 0x00000002 */ +#define PWR_WUCR1_WUPEN2 PWR_WUCR1_WUPEN2_Msk /*!< Wakeup pin WKUP2 enable */ +#define PWR_WUCR1_WUPEN3_Pos (2U) +#define PWR_WUCR1_WUPEN3_Msk (0x1UL << PWR_WUCR1_WUPEN3_Pos) /*!< 0x00000004 */ +#define PWR_WUCR1_WUPEN3 PWR_WUCR1_WUPEN3_Msk /*!< Wakeup pin WKUP3 enable */ +#define PWR_WUCR1_WUPEN4_Pos (3U) +#define PWR_WUCR1_WUPEN4_Msk (0x1UL << PWR_WUCR1_WUPEN4_Pos) /*!< 0x00000008 */ +#define PWR_WUCR1_WUPEN4 PWR_WUCR1_WUPEN4_Msk /*!< Wakeup pin WKUP4 enable */ +#define PWR_WUCR1_WUPEN5_Pos (4U) +#define PWR_WUCR1_WUPEN5_Msk (0x1UL << PWR_WUCR1_WUPEN5_Pos) /*!< 0x00000010 */ +#define PWR_WUCR1_WUPEN5 PWR_WUCR1_WUPEN5_Msk /*!< Wakeup pin WKUP5 enable */ +#define PWR_WUCR1_WUPEN6_Pos (5U) +#define PWR_WUCR1_WUPEN6_Msk (0x1UL << PWR_WUCR1_WUPEN6_Pos) /*!< 0x00000020 */ +#define PWR_WUCR1_WUPEN6 PWR_WUCR1_WUPEN6_Msk /*!< Wakeup pin WKUP6 enable */ +#define PWR_WUCR1_WUPEN7_Pos (6U) +#define PWR_WUCR1_WUPEN7_Msk (0x1UL << PWR_WUCR1_WUPEN7_Pos) /*!< 0x00000040 */ +#define PWR_WUCR1_WUPEN7 PWR_WUCR1_WUPEN7_Msk /*!< Wakeup pin WKUP7 enable */ +#define PWR_WUCR1_WUPEN8_Pos (7U) +#define PWR_WUCR1_WUPEN8_Msk (0x1UL << PWR_WUCR1_WUPEN8_Pos) /*!< 0x00000080 */ +#define PWR_WUCR1_WUPEN8 PWR_WUCR1_WUPEN8_Msk /*!< Wakeup pin WKUP8 enable */ + +/******************* Bit definition for PWR_WUCR2 register ******************/ +#define PWR_WUCR2_WUPP1_Pos (0U) +#define PWR_WUCR2_WUPP1_Msk (0x1UL << PWR_WUCR2_WUPP1_Pos) /*!< 0x00000001 */ +#define PWR_WUCR2_WUPP1 PWR_WUCR2_WUPP1_Msk /*!< Wakeup pin WKUP1 polarity */ +#define PWR_WUCR2_WUPP2_Pos (1U) +#define PWR_WUCR2_WUPP2_Msk (0x1UL << PWR_WUCR2_WUPP2_Pos) /*!< 0x00000002 */ +#define PWR_WUCR2_WUPP2 PWR_WUCR2_WUPP2_Msk /*!< Wakeup pin WKUP2 polarity */ +#define PWR_WUCR2_WUPP3_Pos (2U) +#define PWR_WUCR2_WUPP3_Msk (0x1UL << PWR_WUCR2_WUPP3_Pos) /*!< 0x00000004 */ +#define PWR_WUCR2_WUPP3 PWR_WUCR2_WUPP3_Msk /*!< Wakeup pin WKUP3 polarity */ +#define PWR_WUCR2_WUPP4_Pos (3U) +#define PWR_WUCR2_WUPP4_Msk (0x1UL << PWR_WUCR2_WUPP4_Pos) /*!< 0x00000008 */ +#define PWR_WUCR2_WUPP4 PWR_WUCR2_WUPP4_Msk /*!< Wakeup pin WKUP4 polarity */ +#define PWR_WUCR2_WUPP5_Pos (4U) +#define PWR_WUCR2_WUPP5_Msk (0x1UL << PWR_WUCR2_WUPP5_Pos) /*!< 0x00000010 */ +#define PWR_WUCR2_WUPP5 PWR_WUCR2_WUPP5_Msk /*!< Wakeup pin WKUP5 polarity */ +#define PWR_WUCR2_WUPP6_Pos (5U) +#define PWR_WUCR2_WUPP6_Msk (0x1UL << PWR_WUCR2_WUPP6_Pos) /*!< 0x00000020 */ +#define PWR_WUCR2_WUPP6 PWR_WUCR2_WUPP6_Msk /*!< Wakeup pin WKUP6 polarity */ +#define PWR_WUCR2_WUPP7_Pos (6U) +#define PWR_WUCR2_WUPP7_Msk (0x1UL << PWR_WUCR2_WUPP7_Pos) /*!< 0x00000040 */ +#define PWR_WUCR2_WUPP7 PWR_WUCR2_WUPP7_Msk /*!< Wakeup pin WKUP7 polarity */ +#define PWR_WUCR2_WUPP8_Pos (7U) +#define PWR_WUCR2_WUPP8_Msk (0x1UL << PWR_WUCR2_WUPP8_Pos) /*!< 0x00000080 */ +#define PWR_WUCR2_WUPP8 PWR_WUCR2_WUPP8_Msk /*!< Wakeup pin WKUP8 polarity */ + +/******************* Bit definition for PWR_WUCR3 register ******************/ +#define PWR_WUCR3_WUSEL1_Pos (0U) +#define PWR_WUCR3_WUSEL1_Msk (0x3UL << PWR_WUCR3_WUSEL1_Pos) /*!< 0x00000003 */ +#define PWR_WUCR3_WUSEL1 PWR_WUCR3_WUSEL1_Msk /*!< Wakeup pin WKUP1 selection field */ +#define PWR_WUCR3_WUSEL1_0 (0x1UL << PWR_WUCR3_WUSEL1_Pos) /*!< 0x00000001 */ +#define PWR_WUCR3_WUSEL1_1 (0x2UL << PWR_WUCR3_WUSEL1_Pos) /*!< 0x00000002 */ +#define PWR_WUCR3_WUSEL2_Pos (2U) +#define PWR_WUCR3_WUSEL2_Msk (0x3UL << PWR_WUCR3_WUSEL2_Pos) /*!< 0x0000000C */ +#define PWR_WUCR3_WUSEL2 PWR_WUCR3_WUSEL2_Msk /*!< Wakeup pin WKUP2 selection field */ +#define PWR_WUCR3_WUSEL2_0 (0x1UL << PWR_WUCR3_WUSEL2_Pos) /*!< 0x00000004 */ +#define PWR_WUCR3_WUSEL2_1 (0x2UL << PWR_WUCR3_WUSEL2_Pos) /*!< 0x00000008 */ +#define PWR_WUCR3_WUSEL3_Pos (4U) +#define PWR_WUCR3_WUSEL3_Msk (0x3UL << PWR_WUCR3_WUSEL3_Pos) /*!< 0x00000030 */ +#define PWR_WUCR3_WUSEL3 PWR_WUCR3_WUSEL3_Msk /*!< Wakeup pin WKUP3 selection field */ +#define PWR_WUCR3_WUSEL3_0 (0x1UL << PWR_WUCR3_WUSEL3_Pos) /*!< 0x00000010 */ +#define PWR_WUCR3_WUSEL3_1 (0x2UL << PWR_WUCR3_WUSEL3_Pos) /*!< 0x00000020 */ +#define PWR_WUCR3_WUSEL4_Pos (6U) +#define PWR_WUCR3_WUSEL4_Msk (0x3UL << PWR_WUCR3_WUSEL4_Pos) /*!< 0x000000C0 */ +#define PWR_WUCR3_WUSEL4 PWR_WUCR3_WUSEL4_Msk /*!< Wakeup pin WKUP4 selection field */ +#define PWR_WUCR3_WUSEL4_0 (0x1UL << PWR_WUCR3_WUSEL4_Pos) /*!< 0x00000040 */ +#define PWR_WUCR3_WUSEL4_1 (0x2UL << PWR_WUCR3_WUSEL4_Pos) /*!< 0x00000080 */ +#define PWR_WUCR3_WUSEL5_Pos (8U) +#define PWR_WUCR3_WUSEL5_Msk (0x3UL << PWR_WUCR3_WUSEL5_Pos) /*!< 0x00000300 */ +#define PWR_WUCR3_WUSEL5 PWR_WUCR3_WUSEL5_Msk /*!< Wakeup pin WKUP5 selection field */ +#define PWR_WUCR3_WUSEL5_0 (0x1UL << PWR_WUCR3_WUSEL5_Pos) /*!< 0x00000100 */ +#define PWR_WUCR3_WUSEL5_1 (0x2UL << PWR_WUCR3_WUSEL5_Pos) /*!< 0x00000200 */ +#define PWR_WUCR3_WUSEL6_Pos (10U) +#define PWR_WUCR3_WUSEL6_Msk (0x3UL << PWR_WUCR3_WUSEL6_Pos) /*!< 0x00000C00 */ +#define PWR_WUCR3_WUSEL6 PWR_WUCR3_WUSEL6_Msk /*!< Wakeup pin WKUP6 selection field */ +#define PWR_WUCR3_WUSEL6_0 (0x1UL << PWR_WUCR3_WUSEL6_Pos) /*!< 0x00000400 */ +#define PWR_WUCR3_WUSEL6_1 (0x2UL << PWR_WUCR3_WUSEL6_Pos) /*!< 0x00000800 */ +#define PWR_WUCR3_WUSEL7_Pos (12U) +#define PWR_WUCR3_WUSEL7_Msk (0x3UL << PWR_WUCR3_WUSEL7_Pos) /*!< 0x00003000 */ +#define PWR_WUCR3_WUSEL7 PWR_WUCR3_WUSEL7_Msk /*!< Wakeup pin WKUP7 selection field */ +#define PWR_WUCR3_WUSEL7_0 (0x1UL << PWR_WUCR3_WUSEL7_Pos) /*!< 0x00001000 */ +#define PWR_WUCR3_WUSEL7_1 (0x2UL << PWR_WUCR3_WUSEL7_Pos) /*!< 0x00002000 */ +#define PWR_WUCR3_WUSEL8_Pos (14U) +#define PWR_WUCR3_WUSEL8_Msk (0x3UL << PWR_WUCR3_WUSEL8_Pos) /*!< 0x0000C000 */ +#define PWR_WUCR3_WUSEL8 PWR_WUCR3_WUSEL8_Msk /*!< Wakeup pin WKUP8 selection field */ +#define PWR_WUCR3_WUSEL8_0 (0x1UL << PWR_WUCR3_WUSEL8_Pos) /*!< 0x00004000 */ +#define PWR_WUCR3_WUSEL8_1 (0x2UL << PWR_WUCR3_WUSEL8_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for PWR_DBPR register ******************/ +#define PWR_DBPR_DBP_Pos (0U) +#define PWR_DBPR_DBP_Msk (0x1UL << PWR_DBPR_DBP_Pos) /*!< 0x00000001 */ +#define PWR_DBPR_DBP PWR_DBPR_DBP_Msk /*!< Disable backup domain write protection */ + +/******************* Bit definition for PWR_SECCFGR register ****************/ +#define PWR_SECCFGR_WUP1SEC_Pos (0U) +#define PWR_SECCFGR_WUP1SEC_Msk (0x1UL << PWR_SECCFGR_WUP1SEC_Pos) /*!< 0x00000001 */ +#define PWR_SECCFGR_WUP1SEC PWR_SECCFGR_WUP1SEC_Msk /*!< WUP1 secure protection */ +#define PWR_SECCFGR_WUP2SEC_Pos (1U) +#define PWR_SECCFGR_WUP2SEC_Msk (0x1UL << PWR_SECCFGR_WUP2SEC_Pos) /*!< 0x00000002 */ +#define PWR_SECCFGR_WUP2SEC PWR_SECCFGR_WUP2SEC_Msk /*!< WUP2 secure protection */ +#define PWR_SECCFGR_WUP3SEC_Pos (2U) +#define PWR_SECCFGR_WUP3SEC_Msk (0x1UL << PWR_SECCFGR_WUP3SEC_Pos) /*!< 0x00000004 */ +#define PWR_SECCFGR_WUP3SEC PWR_SECCFGR_WUP3SEC_Msk /*!< WUP3 secure protection */ +#define PWR_SECCFGR_WUP4SEC_Pos (3U) +#define PWR_SECCFGR_WUP4SEC_Msk (0x1UL << PWR_SECCFGR_WUP4SEC_Pos) /*!< 0x00000008 */ +#define PWR_SECCFGR_WUP4SEC PWR_SECCFGR_WUP4SEC_Msk /*!< WUP4 secure protection */ +#define PWR_SECCFGR_WUP5SEC_Pos (4U) +#define PWR_SECCFGR_WUP5SEC_Msk (0x1UL << PWR_SECCFGR_WUP5SEC_Pos) /*!< 0x00000010 */ +#define PWR_SECCFGR_WUP5SEC PWR_SECCFGR_WUP5SEC_Msk /*!< WUP5 secure protection */ +#define PWR_SECCFGR_WUP6SEC_Pos (5U) +#define PWR_SECCFGR_WUP6SEC_Msk (0x1UL << PWR_SECCFGR_WUP6SEC_Pos) /*!< 0x00000020 */ +#define PWR_SECCFGR_WUP6SEC PWR_SECCFGR_WUP6SEC_Msk /*!< WUP6 secure protection */ +#define PWR_SECCFGR_WUP7SEC_Pos (6U) +#define PWR_SECCFGR_WUP7SEC_Msk (0x1UL << PWR_SECCFGR_WUP7SEC_Pos) /*!< 0x00000040 */ +#define PWR_SECCFGR_WUP7SEC PWR_SECCFGR_WUP7SEC_Msk /*!< WUP7 secure protection */ +#define PWR_SECCFGR_WUP8SEC_Pos (7U) +#define PWR_SECCFGR_WUP8SEC_Msk (0x1UL << PWR_SECCFGR_WUP8SEC_Pos) /*!< 0x00000080 */ +#define PWR_SECCFGR_WUP8SEC PWR_SECCFGR_WUP8SEC_Msk /*!< WUP8 secure protection */ +#define PWR_SECCFGR_LPMSEC_Pos (12U) +#define PWR_SECCFGR_LPMSEC_Msk (0x1UL << PWR_SECCFGR_LPMSEC_Pos) /*!< 0x00001000 */ +#define PWR_SECCFGR_LPMSEC PWR_SECCFGR_LPMSEC_Msk /*!< Low-power modes secure protection */ +#define PWR_SECCFGR_VDMSEC_Pos (13U) +#define PWR_SECCFGR_VDMSEC_Msk (0x1UL << PWR_SECCFGR_VDMSEC_Pos) /*!< 0x00002000 */ +#define PWR_SECCFGR_VDMSEC PWR_SECCFGR_VDMSEC_Msk /*!< Voltage detection and monitoring secure protection */ +#define PWR_SECCFGR_VBSEC_Pos (14U) +#define PWR_SECCFGR_VBSEC_Msk (0x1UL << PWR_SECCFGR_VBSEC_Pos) /*!< 0x00004000 */ +#define PWR_SECCFGR_VBSEC PWR_SECCFGR_VBSEC_Msk /*!< Backup domain secure protection */ + +/******************* Bit definition for PWR_PRIVCFGR register ***************/ +#define PWR_PRIVCFGR_SPRIV_Pos (0U) +#define PWR_PRIVCFGR_SPRIV_Msk (0x1UL << PWR_PRIVCFGR_SPRIV_Pos) /*!< 0x00000001 */ +#define PWR_PRIVCFGR_SPRIV PWR_PRIVCFGR_SPRIV_Msk /*!< RCC secure functions privilege configuration */ +#define PWR_PRIVCFGR_NSPRIV_Pos (1U) +#define PWR_PRIVCFGR_NSPRIV_Msk (0x1UL << PWR_PRIVCFGR_NSPRIV_Pos) /*!< 0x00000002 */ +#define PWR_PRIVCFGR_NSPRIV PWR_PRIVCFGR_NSPRIV_Msk /*!< RCC non-secure functions privilege configuration */ + +/********************** Bit definition for PWR_SR register ******************/ +#define PWR_SR_CSSF_Pos (0U) +#define PWR_SR_CSSF_Msk (0x1UL << PWR_SR_CSSF_Pos) /*!< 0x00000001 */ +#define PWR_SR_CSSF PWR_SR_CSSF_Msk /*!< Clear Stop and Standby/Shutdown flags */ +#define PWR_SR_STOPF_Pos (1U) +#define PWR_SR_STOPF_Msk (0x1UL << PWR_SR_STOPF_Pos) /*!< 0x00000002 */ +#define PWR_SR_STOPF PWR_SR_STOPF_Msk /*!< Stop flag */ +#define PWR_SR_SBF_Pos (2U) +#define PWR_SR_SBF_Msk (0x1UL << PWR_SR_SBF_Pos) /*!< 0x00000004 */ +#define PWR_SR_SBF PWR_SR_SBF_Msk /*!< Standby/Shutdown flag */ + +/******************** Bit definition for PWR_SVMSR register *****************/ +#define PWR_SVMSR_PVDO_Pos (4U) +#define PWR_SVMSR_PVDO_Msk (0x1UL << PWR_SVMSR_PVDO_Pos) /*!< 0x00000010 */ +#define PWR_SVMSR_PVDO PWR_SVMSR_PVDO_Msk /*!< VDD voltage detector output */ +#define PWR_SVMSR_ACTVOSRDY_Pos (15U) +#define PWR_SVMSR_ACTVOSRDY_Msk (0x1UL << PWR_SVMSR_ACTVOSRDY_Pos) /*!< 0x00008000 */ +#define PWR_SVMSR_ACTVOSRDY PWR_SVMSR_ACTVOSRDY_Msk /*!< Voltage level ready for currently used VOS */ +#define PWR_SVMSR_ACTVOS_Pos (16U) +#define PWR_SVMSR_ACTVOS_Msk (0x1UL << PWR_SVMSR_ACTVOS_Pos) /*!< 0x00010000 */ +#define PWR_SVMSR_ACTVOS PWR_SVMSR_ACTVOS_Msk /*!< Voltage Output Scaling currently applied to VCORE */ + +/********************* Bit definition for PWR_WUSR register *****************/ +#define PWR_WUSR_WUF1_Pos (0U) +#define PWR_WUSR_WUF1_Msk (0x1UL << PWR_WUSR_WUF1_Pos) /*!< 0x00000001 */ +#define PWR_WUSR_WUF1 PWR_WUSR_WUF1_Msk /*!< Wakeup flag 1 */ +#define PWR_WUSR_WUF2_Pos (1U) +#define PWR_WUSR_WUF2_Msk (0x1UL << PWR_WUSR_WUF2_Pos) /*!< 0x00000002 */ +#define PWR_WUSR_WUF2 PWR_WUSR_WUF2_Msk /*!< Wakeup flag 2 */ +#define PWR_WUSR_WUF3_Pos (2U) +#define PWR_WUSR_WUF3_Msk (0x1UL << PWR_WUSR_WUF3_Pos) /*!< 0x00000004 */ +#define PWR_WUSR_WUF3 PWR_WUSR_WUF3_Msk /*!< Wakeup flag 3 */ +#define PWR_WUSR_WUF4_Pos (3U) +#define PWR_WUSR_WUF4_Msk (0x1UL << PWR_WUSR_WUF4_Pos) /*!< 0x00000008 */ +#define PWR_WUSR_WUF4 PWR_WUSR_WUF4_Msk /*!< Wakeup flag 4 */ +#define PWR_WUSR_WUF5_Pos (4U) +#define PWR_WUSR_WUF5_Msk (0x1UL << PWR_WUSR_WUF5_Pos) /*!< 0x00000010 */ +#define PWR_WUSR_WUF5 PWR_WUSR_WUF5_Msk /*!< Wakeup flag 5 */ +#define PWR_WUSR_WUF6_Pos (5U) +#define PWR_WUSR_WUF6_Msk (0x1UL << PWR_WUSR_WUF6_Pos) /*!< 0x00000020 */ +#define PWR_WUSR_WUF6 PWR_WUSR_WUF6_Msk /*!< Wakeup flag 6 */ +#define PWR_WUSR_WUF7_Pos (6U) +#define PWR_WUSR_WUF7_Msk (0x1UL << PWR_WUSR_WUF7_Pos) /*!< 0x00000040 */ +#define PWR_WUSR_WUF7 PWR_WUSR_WUF7_Msk /*!< Wakeup flag 7 */ +#define PWR_WUSR_WUF8_Pos (7U) +#define PWR_WUSR_WUF8_Msk (0x1UL << PWR_WUSR_WUF8_Pos) /*!< 0x00000080 */ +#define PWR_WUSR_WUF8 PWR_WUSR_WUF8_Msk /*!< Wakeup flag 8 */ +#define PWR_WUSR_WUF_Pos (0U) +#define PWR_WUSR_WUF_Msk (0xFFUL << PWR_WUSR_WUF_Pos) /*!< 0x000000FF */ +#define PWR_WUSR_WUF PWR_WUSR_WUF_Msk /*!< all Wakeup flag */ + +/********************* Bit definition for PWR_WUSCR register ****************/ +#define PWR_WUSCR_CWUF1_Pos (0U) +#define PWR_WUSCR_CWUF1_Msk (0x1UL << PWR_WUSCR_CWUF1_Pos) /*!< 0x00000001*/ +#define PWR_WUSCR_CWUF1 PWR_WUSCR_CWUF1_Msk /*!< Wakeup clear flag 1 */ +#define PWR_WUSCR_CWUF2_Pos (1U) +#define PWR_WUSCR_CWUF2_Msk (0x1UL << PWR_WUSCR_CWUF2_Pos) /*!< 0x00000002 */ +#define PWR_WUSCR_CWUF2 PWR_WUSCR_CWUF2_Msk /*!< Wakeup clear flag 2 */ +#define PWR_WUSCR_CWUF3_Pos (2U) +#define PWR_WUSCR_CWUF3_Msk (0x1UL << PWR_WUSCR_CWUF3_Pos) /*!< 0x00000004 */ +#define PWR_WUSCR_CWUF3 PWR_WUSCR_CWUF3_Msk /*!< Wakeup clear flag 3 */ +#define PWR_WUSCR_CWUF4_Pos (3U) +#define PWR_WUSCR_CWUF4_Msk (0x1UL << PWR_WUSCR_CWUF4_Pos) /*!< 0x00000008 */ +#define PWR_WUSCR_CWUF4 PWR_WUSCR_CWUF4_Msk /*!< Wakeup clear flag 4 */ +#define PWR_WUSCR_CWUF5_Pos (4U) +#define PWR_WUSCR_CWUF5_Msk (0x1UL << PWR_WUSCR_CWUF5_Pos) /*!< 0x00000010 */ +#define PWR_WUSCR_CWUF5 PWR_WUSCR_CWUF5_Msk /*!< Wakeup clear flag 5 */ +#define PWR_WUSCR_CWUF6_Pos (5U) +#define PWR_WUSCR_CWUF6_Msk (0x1UL << PWR_WUSCR_CWUF6_Pos) /*!< 0x00000020 */ +#define PWR_WUSCR_CWUF6 PWR_WUSCR_CWUF6_Msk /*!< Wakeup clear flag 6 */ +#define PWR_WUSCR_CWUF7_Pos (6U) +#define PWR_WUSCR_CWUF7_Msk (0x1UL << PWR_WUSCR_CWUF7_Pos) /*!< 0x00000040 */ +#define PWR_WUSCR_CWUF7 PWR_WUSCR_CWUF7_Msk /*!< Wakeup clear flag 7 */ +#define PWR_WUSCR_CWUF8_Pos (7U) +#define PWR_WUSCR_CWUF8_Msk (0x1UL << PWR_WUSCR_CWUF8_Pos) /*!< 0x00000080 */ +#define PWR_WUSCR_CWUF8 PWR_WUSCR_CWUF8_Msk /*!< Wakeup clear flag 8 */ +#define PWR_WUSCR_CWUF_Pos (0U) +#define PWR_WUSCR_CWUF_Msk (0xFFUL << PWR_WUSCR_CWUF1_Pos) /*!< 0x000000FF */ +#define PWR_WUSCR_CWUF PWR_WUSCR_CWUF_Msk /*!< all Wakeup clear flag */ + +/******************** Bit definition for PWR_IORETENRA register *****************/ +#define PWR_IORETENRA_EN0_Pos (0U) +#define PWR_IORETENRA_EN0_Msk (0x1UL << PWR_IORETENRA_EN0_Pos) /*!< 0x00000001 */ +#define PWR_IORETENRA_EN0 PWR_IORETENRA_EN0_Msk /*!< Standby GPIO retention enable for PA0 */ +#define PWR_IORETENRA_EN1_Pos (1U) +#define PWR_IORETENRA_EN1_Msk (0x1UL << PWR_IORETENRA_EN1_Pos) /*!< 0x00000002 */ +#define PWR_IORETENRA_EN1 PWR_IORETENRA_EN1_Msk /*!< Standby GPIO retention enable for PA1 */ +#define PWR_IORETENRA_EN2_Pos (2U) +#define PWR_IORETENRA_EN2_Msk (0x1UL << PWR_IORETENRA_EN2_Pos) /*!< 0x00000004 */ +#define PWR_IORETENRA_EN2 PWR_IORETENRA_EN2_Msk /*!< Standby GPIO retention enable for PA2 */ +#define PWR_IORETENRA_EN3_Pos (3U) +#define PWR_IORETENRA_EN3_Msk (0x1UL << PWR_IORETENRA_EN3_Pos) /*!< 0x00000008 */ +#define PWR_IORETENRA_EN3 PWR_IORETENRA_EN3_Msk /*!< Standby GPIO retention enable for PA3 */ +#define PWR_IORETENRA_EN4_Pos (4U) +#define PWR_IORETENRA_EN4_Msk (0x1UL << PWR_IORETENRA_EN4_Pos) /*!< 0x00000010 */ +#define PWR_IORETENRA_EN4 PWR_IORETENRA_EN4_Msk /*!< Standby GPIO retention enable for PA4 */ +#define PWR_IORETENRA_EN5_Pos (5U) +#define PWR_IORETENRA_EN5_Msk (0x1UL << PWR_IORETENRA_EN5_Pos) /*!< 0x00000020 */ +#define PWR_IORETENRA_EN5 PWR_IORETENRA_EN5_Msk /*!< Standby GPIO retention enable for PA5 */ +#define PWR_IORETENRA_EN6_Pos (6U) +#define PWR_IORETENRA_EN6_Msk (0x1UL << PWR_IORETENRA_EN6_Pos) /*!< 0x00000040 */ +#define PWR_IORETENRA_EN6 PWR_IORETENRA_EN6_Msk /*!< Standby GPIO retention enable for PA6 */ +#define PWR_IORETENRA_EN7_Pos (7U) +#define PWR_IORETENRA_EN7_Msk (0x1UL << PWR_IORETENRA_EN7_Pos) /*!< 0x00000080 */ +#define PWR_IORETENRA_EN7 PWR_IORETENRA_EN7_Msk /*!< Standby GPIO retention enable for PA7 */ +#define PWR_IORETENRA_EN8_Pos (8U) +#define PWR_IORETENRA_EN8_Msk (0x1UL << PWR_IORETENRA_EN8_Pos) /*!< 0x00000100 */ +#define PWR_IORETENRA_EN8 PWR_IORETENRA_EN8_Msk /*!< Standby GPIO retention enable for PA8 */ +#define PWR_IORETENRA_EN9_Pos (9U) +#define PWR_IORETENRA_EN9_Msk (0x1UL << PWR_IORETENRA_EN9_Pos) /*!< 0x00000200 */ +#define PWR_IORETENRA_EN9 PWR_IORETENRA_EN9_Msk /*!< Standby GPIO retention enable for PA9 */ +#define PWR_IORETENRA_EN10_Pos (10U) +#define PWR_IORETENRA_EN10_Msk (0x1UL << PWR_IORETENRA_EN10_Pos) /*!< 0x00000400 */ +#define PWR_IORETENRA_EN10 PWR_IORETENRA_EN10_Msk /*!< Standby GPIO retention enable for PA10 */ +#define PWR_IORETENRA_EN11_Pos (11U) +#define PWR_IORETENRA_EN11_Msk (0x1UL << PWR_IORETENRA_EN11_Pos) /*!< 0x00000800 */ +#define PWR_IORETENRA_EN11 PWR_IORETENRA_EN11_Msk /*!< Standby GPIO retention enable for PA11 */ +#define PWR_IORETENRA_EN12_Pos (12U) +#define PWR_IORETENRA_EN12_Msk (0x1UL << PWR_IORETENRA_EN12_Pos) /*!< 0x00001000 */ +#define PWR_IORETENRA_EN12 PWR_IORETENRA_EN12_Msk /*!< Standby GPIO retention enable for PA12 */ +#define PWR_IORETENRA_EN13_Pos (13U) +#define PWR_IORETENRA_EN13_Msk (0x1UL << PWR_IORETENRA_EN13_Pos) /*!< 0x00002000 */ +#define PWR_IORETENRA_EN13 PWR_IORETENRA_EN13_Msk /*!< Standby GPIO retention enable for PA13 */ +#define PWR_IORETENRA_EN14_Pos (14U) +#define PWR_IORETENRA_EN14_Msk (0x1UL << PWR_IORETENRA_EN14_Pos) /*!< 0x00004000 */ +#define PWR_IORETENRA_EN14 PWR_IORETENRA_EN14_Msk /*!< Standby GPIO retention enable for PA14 */ +#define PWR_IORETENRA_EN15_Pos (15U) +#define PWR_IORETENRA_EN15_Msk (0x1UL << PWR_IORETENRA_EN15_Pos) /*!< 0x00008000 */ +#define PWR_IORETENRA_EN15 PWR_IORETENRA_EN15_Msk /*!< Standby GPIO retention enable for PA15 */ + +/******************** Bit definition for PWR_IORETRA register *****************/ +#define PWR_IORETRA_RET0_Pos (0U) +#define PWR_IORETRA_RET0_Msk (0x1UL << PWR_IORETRA_RET0_Pos) /*!< 0x00000001 */ +#define PWR_IORETRA_RET0 PWR_IORETRA_RET0_Msk /*!< Standby GPIO retention status for PA0 */ +#define PWR_IORETRA_RET1_Pos (1U) +#define PWR_IORETRA_RET1_Msk (0x1UL << PWR_IORETRA_RET1_Pos) /*!< 0x00000002 */ +#define PWR_IORETRA_RET1 PWR_IORETRA_RET1_Msk /*!< Standby GPIO retention status for PA1 */ +#define PWR_IORETRA_RET2_Pos (2U) +#define PWR_IORETRA_RET2_Msk (0x1UL << PWR_IORETRA_RET2_Pos) /*!< 0x00000004 */ +#define PWR_IORETRA_RET2 PWR_IORETRA_RET2_Msk /*!< Standby GPIO retention status for PA2 */ +#define PWR_IORETRA_RET3_Pos (3U) +#define PWR_IORETRA_RET3_Msk (0x1UL << PWR_IORETRA_RET3_Pos) /*!< 0x00000008 */ +#define PWR_IORETRA_RET3 PWR_IORETRA_RET3_Msk /*!< Standby GPIO retention status for PA3 */ +#define PWR_IORETRA_RET4_Pos (4U) +#define PWR_IORETRA_RET4_Msk (0x1UL << PWR_IORETRA_RET4_Pos) /*!< 0x00000010 */ +#define PWR_IORETRA_RET4 PWR_IORETRA_RET4_Msk /*!< Standby GPIO retention status for PA4 */ +#define PWR_IORETRA_RET5_Pos (5U) +#define PWR_IORETRA_RET5_Msk (0x1UL << PWR_IORETRA_RET5_Pos) /*!< 0x00000020 */ +#define PWR_IORETRA_RET5 PWR_IORETRA_RET5_Msk /*!< Standby GPIO retention status for PA5 */ +#define PWR_IORETRA_RET6_Pos (6U) +#define PWR_IORETRA_RET6_Msk (0x1UL << PWR_IORETRA_RET6_Pos) /*!< 0x00000040 */ +#define PWR_IORETRA_RET6 PWR_IORETRA_RET6_Msk /*!< Standby GPIO retention status for PA6 */ +#define PWR_IORETRA_RET7_Pos (7U) +#define PWR_IORETRA_RET7_Msk (0x1UL << PWR_IORETRA_RET7_Pos) /*!< 0x00000080 */ +#define PWR_IORETRA_RET7 PWR_IORETRA_RET7_Msk /*!< Standby GPIO retention status for PA7 */ +#define PWR_IORETRA_RET8_Pos (8U) +#define PWR_IORETRA_RET8_Msk (0x1UL << PWR_IORETRA_RET8_Pos) /*!< 0x00000100 */ +#define PWR_IORETRA_RET8 PWR_IORETRA_RET8_Msk /*!< Standby GPIO retention status for PA8 */ +#define PWR_IORETRA_RET9_Pos (9U) +#define PWR_IORETRA_RET9_Msk (0x1UL << PWR_IORETRA_RET9_Pos) /*!< 0x00000200 */ +#define PWR_IORETRA_RET9 PWR_IORETRA_RET9_Msk /*!< Standby GPIO retention status for PA9 */ +#define PWR_IORETRA_RET10_Pos (10U) +#define PWR_IORETRA_RET10_Msk (0x1UL << PWR_IORETRA_RET10_Pos) /*!< 0x00000400 */ +#define PWR_IORETRA_RET10 PWR_IORETRA_RET10_Msk /*!< Standby GPIO retention status for PA10 */ +#define PWR_IORETRA_RET11_Pos (11U) +#define PWR_IORETRA_RET11_Msk (0x1UL << PWR_IORETRA_RET11_Pos) /*!< 0x00000800 */ +#define PWR_IORETRA_RET11 PWR_IORETRA_RET11_Msk /*!< Standby GPIO retention status for PA11 */ +#define PWR_IORETRA_RET12_Pos (12U) +#define PWR_IORETRA_RET12_Msk (0x1UL << PWR_IORETRA_RET12_Pos) /*!< 0x00001000 */ +#define PWR_IORETRA_RET12 PWR_IORETRA_RET12_Msk /*!< Standby GPIO retention status for PA12 */ +#define PWR_IORETRA_RET13_Pos (13U) +#define PWR_IORETRA_RET13_Msk (0x1UL << PWR_IORETRA_RET13_Pos) /*!< 0x00002000 */ +#define PWR_IORETRA_RET13 PWR_IORETRA_RET13_Msk /*!< Standby GPIO retention status for PA13 */ +#define PWR_IORETRA_RET14_Pos (14U) +#define PWR_IORETRA_RET14_Msk (0x1UL << PWR_IORETRA_RET14_Pos) /*!< 0x00004000 */ +#define PWR_IORETRA_RET14 PWR_IORETRA_RET14_Msk /*!< Standby GPIO retention status for PA14 */ +#define PWR_IORETRA_RET15_Pos (15U) +#define PWR_IORETRA_RET15_Msk (0x1UL << PWR_IORETRA_RET15_Pos) /*!< 0x00008000 */ +#define PWR_IORETRA_RET15 PWR_IORETRA_RET15_Msk /*!< Standby GPIO retention status for PA15 */ + +/******************** Bit definition for PWR_IORETENRB register *****************/ +#define PWR_IORETENRB_EN0_Pos (0U) +#define PWR_IORETENRB_EN0_Msk (0x1UL << PWR_IORETENRB_EN0_Pos) /*!< 0x00000001 */ +#define PWR_IORETENRB_EN0 PWR_IORETENRB_EN0_Msk /*!< Standby GPIO retention enable for PB0 */ +#define PWR_IORETENRB_EN1_Pos (1U) +#define PWR_IORETENRB_EN1_Msk (0x1UL << PWR_IORETENRB_EN1_Pos) /*!< 0x00000002 */ +#define PWR_IORETENRB_EN1 PWR_IORETENRB_EN1_Msk /*!< Standby GPIO retention enable for PB1 */ +#define PWR_IORETENRB_EN2_Pos (2U) +#define PWR_IORETENRB_EN2_Msk (0x1UL << PWR_IORETENRB_EN2_Pos) /*!< 0x00000004 */ +#define PWR_IORETENRB_EN2 PWR_IORETENRB_EN2_Msk /*!< Standby GPIO retention enable for PB2 */ +#define PWR_IORETENRB_EN3_Pos (3U) +#define PWR_IORETENRB_EN3_Msk (0x1UL << PWR_IORETENRB_EN3_Pos) /*!< 0x00000008 */ +#define PWR_IORETENRB_EN3 PWR_IORETENRB_EN3_Msk /*!< Standby GPIO retention enable for PB3 */ +#define PWR_IORETENRB_EN4_Pos (4U) +#define PWR_IORETENRB_EN4_Msk (0x1UL << PWR_IORETENRB_EN4_Pos) /*!< 0x00000010 */ +#define PWR_IORETENRB_EN4 PWR_IORETENRB_EN4_Msk /*!< Standby GPIO retention enable for PB4 */ +#define PWR_IORETENRB_EN5_Pos (5U) +#define PWR_IORETENRB_EN5_Msk (0x1UL << PWR_IORETENRB_EN5_Pos) /*!< 0x00000020 */ +#define PWR_IORETENRB_EN5 PWR_IORETENRB_EN5_Msk /*!< Standby GPIO retention enable for PB5 */ +#define PWR_IORETENRB_EN6_Pos (6U) +#define PWR_IORETENRB_EN6_Msk (0x1UL << PWR_IORETENRB_EN6_Pos) /*!< 0x00000040 */ +#define PWR_IORETENRB_EN6 PWR_IORETENRB_EN6_Msk /*!< Standby GPIO retention enable for PB6 */ +#define PWR_IORETENRB_EN7_Pos (7U) +#define PWR_IORETENRB_EN7_Msk (0x1UL << PWR_IORETENRB_EN7_Pos) /*!< 0x00000080 */ +#define PWR_IORETENRB_EN7 PWR_IORETENRB_EN7_Msk /*!< Standby GPIO retention enable for PB7 */ +#define PWR_IORETENRB_EN8_Pos (8U) +#define PWR_IORETENRB_EN8_Msk (0x1UL << PWR_IORETENRB_EN8_Pos) /*!< 0x00000100 */ +#define PWR_IORETENRB_EN8 PWR_IORETENRB_EN8_Msk /*!< Standby GPIO retention enable for PB8 */ +#define PWR_IORETENRB_EN9_Pos (9U) +#define PWR_IORETENRB_EN9_Msk (0x1UL << PWR_IORETENRB_EN9_Pos) /*!< 0x00000200 */ +#define PWR_IORETENRB_EN9 PWR_IORETENRB_EN9_Msk /*!< Standby GPIO retention enable for PB9 */ +#define PWR_IORETENRB_EN10_Pos (10U) +#define PWR_IORETENRB_EN10_Msk (0x1UL << PWR_IORETENRB_EN10_Pos) /*!< 0x00000400 */ +#define PWR_IORETENRB_EN10 PWR_IORETENRB_EN10_Msk /*!< Standby GPIO retention enable for PB10 */ +#define PWR_IORETENRB_EN11_Pos (11U) +#define PWR_IORETENRB_EN11_Msk (0x1UL << PWR_IORETENRB_EN11_Pos) /*!< 0x00000800 */ +#define PWR_IORETENRB_EN11 PWR_IORETENRB_EN11_Msk /*!< Standby GPIO retention enable for PB11 */ +#define PWR_IORETENRB_EN12_Pos (12U) +#define PWR_IORETENRB_EN12_Msk (0x1UL << PWR_IORETENRB_EN12_Pos) /*!< 0x00001000 */ +#define PWR_IORETENRB_EN12 PWR_IORETENRB_EN12_Msk /*!< Standby GPIO retention enable for PB12 */ +#define PWR_IORETENRB_EN13_Pos (13U) +#define PWR_IORETENRB_EN13_Msk (0x1UL << PWR_IORETENRB_EN13_Pos) /*!< 0x00002000 */ +#define PWR_IORETENRB_EN13 PWR_IORETENRB_EN13_Msk /*!< Standby GPIO retention enable for PB13 */ +#define PWR_IORETENRB_EN14_Pos (14U) +#define PWR_IORETENRB_EN14_Msk (0x1UL << PWR_IORETENRB_EN14_Pos) /*!< 0x00004000 */ +#define PWR_IORETENRB_EN14 PWR_IORETENRB_EN14_Msk /*!< Standby GPIO retention enable for PB14 */ +#define PWR_IORETENRB_EN15_Pos (15U) +#define PWR_IORETENRB_EN15_Msk (0x1UL << PWR_IORETENRB_EN15_Pos) /*!< 0x00008000 */ +#define PWR_IORETENRB_EN15 PWR_IORETENRB_EN15_Msk /*!< Standby GPIO retention enable for PB15 */ + +/******************** Bit definition for PWR_IORETRB register *****************/ +#define PWR_IORETRB_RET0_Pos (0U) +#define PWR_IORETRB_RET0_Msk (0x1UL << PWR_IORETRB_RET0_Pos) /*!< 0x00000001 */ +#define PWR_IORETRB_RET0 PWR_IORETRB_RET0_Msk /*!< Standby GPIO retention status for PB0 */ +#define PWR_IORETRB_RET1_Pos (1U) +#define PWR_IORETRB_RET1_Msk (0x1UL << PWR_IORETRB_RET1_Pos) /*!< 0x00000002 */ +#define PWR_IORETRB_RET1 PWR_IORETRB_RET1_Msk /*!< Standby GPIO retention status for PB1 */ +#define PWR_IORETRB_RET2_Pos (2U) +#define PWR_IORETRB_RET2_Msk (0x1UL << PWR_IORETRB_RET2_Pos) /*!< 0x00000004 */ +#define PWR_IORETRB_RET2 PWR_IORETRB_RET2_Msk /*!< Standby GPIO retention status for PB2 */ +#define PWR_IORETRB_RET3_Pos (3U) +#define PWR_IORETRB_RET3_Msk (0x1UL << PWR_IORETRB_RET3_Pos) /*!< 0x00000008 */ +#define PWR_IORETRB_RET3 PWR_IORETRB_RET3_Msk /*!< Standby GPIO retention status for PB3 */ +#define PWR_IORETRB_RET4_Pos (4U) +#define PWR_IORETRB_RET4_Msk (0x1UL << PWR_IORETRB_RET4_Pos) /*!< 0x00000010 */ +#define PWR_IORETRB_RET4 PWR_IORETRB_RET4_Msk /*!< Standby GPIO retention status for PB4 */ +#define PWR_IORETRB_RET5_Pos (5U) +#define PWR_IORETRB_RET5_Msk (0x1UL << PWR_IORETRB_RET5_Pos) /*!< 0x00000020 */ +#define PWR_IORETRB_RET5 PWR_IORETRB_RET5_Msk /*!< Standby GPIO retention status for PB5 */ +#define PWR_IORETRB_RET6_Pos (6U) +#define PWR_IORETRB_RET6_Msk (0x1UL << PWR_IORETRB_RET6_Pos) /*!< 0x00000040 */ +#define PWR_IORETRB_RET6 PWR_IORETRB_RET6_Msk /*!< Standby GPIO retention status for PB6 */ +#define PWR_IORETRB_RET7_Pos (7U) +#define PWR_IORETRB_RET7_Msk (0x1UL << PWR_IORETRB_RET7_Pos) /*!< 0x00000080 */ +#define PWR_IORETRB_RET7 PWR_IORETRB_RET7_Msk /*!< Standby GPIO retention status for PB7 */ +#define PWR_IORETRB_RET8_Pos (8U) +#define PWR_IORETRB_RET8_Msk (0x1UL << PWR_IORETRB_RET8_Pos) /*!< 0x00000100 */ +#define PWR_IORETRB_RET8 PWR_IORETRB_RET8_Msk /*!< Standby GPIO retention status for PB8 */ +#define PWR_IORETRB_RET9_Pos (9U) +#define PWR_IORETRB_RET9_Msk (0x1UL << PWR_IORETRB_RET9_Pos) /*!< 0x00000200 */ +#define PWR_IORETRB_RET9 PWR_IORETRB_RET9_Msk /*!< Standby GPIO retention status for PB9 */ +#define PWR_IORETRB_RET10_Pos (10U) +#define PWR_IORETRB_RET10_Msk (0x1UL << PWR_IORETRB_RET10_Pos) /*!< 0x00000400 */ +#define PWR_IORETRB_RET10 PWR_IORETRB_RET10_Msk /*!< Standby GPIO retention status for PB10 */ +#define PWR_IORETRB_RET11_Pos (11U) +#define PWR_IORETRB_RET11_Msk (0x1UL << PWR_IORETRB_RET11_Pos) /*!< 0x00000800 */ +#define PWR_IORETRB_RET11 PWR_IORETRB_RET11_Msk /*!< Standby GPIO retention status for PB11 */ +#define PWR_IORETRB_RET12_Pos (12U) +#define PWR_IORETRB_RET12_Msk (0x1UL << PWR_IORETRB_RET12_Pos) /*!< 0x00001000 */ +#define PWR_IORETRB_RET12 PWR_IORETRB_RET12_Msk /*!< Standby GPIO retention status for PB12 */ +#define PWR_IORETRB_RET13_Pos (13U) +#define PWR_IORETRB_RET13_Msk (0x1UL << PWR_IORETRB_RET13_Pos) /*!< 0x00002000 */ +#define PWR_IORETRB_RET13 PWR_IORETRB_RET13_Msk /*!< Standby GPIO retention status for PB13 */ +#define PWR_IORETRB_RET14_Pos (14U) +#define PWR_IORETRB_RET14_Msk (0x1UL << PWR_IORETRB_RET14_Pos) /*!< 0x00004000 */ +#define PWR_IORETRB_RET14 PWR_IORETRB_RET14_Msk /*!< Standby GPIO retention status for PB14 */ +#define PWR_IORETRB_RET15_Pos (15U) +#define PWR_IORETRB_RET15_Msk (0x1UL << PWR_IORETRB_RET15_Pos) /*!< 0x00008000 */ +#define PWR_IORETRB_RET15 PWR_IORETRB_RET15_Msk /*!< Standby GPIO retention status for PB15 */ + +/******************** Bit definition for PWR_IORETENRC register *****************/ +#define PWR_IORETENRC_EN13_Pos (13U) +#define PWR_IORETENRC_EN13_Msk (0x1UL << PWR_IORETENRC_EN13_Pos) /*!< 0x00002000 */ +#define PWR_IORETENRC_EN13 PWR_IORETENRC_EN13_Msk /*!< Standby GPIO retention enable for PC13 */ +#define PWR_IORETENRC_EN14_Pos (14U) +#define PWR_IORETENRC_EN14_Msk (0x1UL << PWR_IORETENRC_EN14_Pos) /*!< 0x00004000 */ +#define PWR_IORETENRC_EN14 PWR_IORETENRC_EN14_Msk /*!< Standby GPIO retention enable for PC14 */ +#define PWR_IORETENRC_EN15_Pos (15U) +#define PWR_IORETENRC_EN15_Msk (0x1UL << PWR_IORETENRC_EN15_Pos) /*!< 0x00008000 */ +#define PWR_IORETENRC_EN15 PWR_IORETENRC_EN15_Msk /*!< Standby GPIO retention enable for PC15 */ + +/******************** Bit definition for PWR_IORETRC register *****************/ +#define PWR_IORETRC_RET13_Pos (13U) +#define PWR_IORETRC_RET13_Msk (0x1UL << PWR_IORETRC_RET13_Pos) /*!< 0x00002000 */ +#define PWR_IORETRC_RET13 PWR_IORETRC_RET13_Msk /*!< Standby GPIO retention status for PC13 */ +#define PWR_IORETRC_RET14_Pos (14U) +#define PWR_IORETRC_RET14_Msk (0x1UL << PWR_IORETRC_RET14_Pos) /*!< 0x00004000 */ +#define PWR_IORETRC_RET14 PWR_IORETRC_RET14_Msk /*!< Standby GPIO retention status for PC14 */ +#define PWR_IORETRC_RET15_Pos (15U) +#define PWR_IORETRC_RET15_Msk (0x1UL << PWR_IORETRC_RET15_Pos) /*!< 0x00008000 */ +#define PWR_IORETRC_RET15 PWR_IORETRC_RET15_Msk /*!< Standby GPIO retention status for PC15 */ + +/******************** Bit definition for PWR_IORETENRH register *****************/ +#define PWR_IORETENRH_EN3_Pos (3U) +#define PWR_IORETENRH_EN3_Msk (0x1UL << PWR_IORETENRH_EN3_Pos) /*!< 0x00000008 */ +#define PWR_IORETENRH_EN3 PWR_IORETENRH_EN3_Msk /*!< Standby GPIO retention enable for PH3 */ + +/******************** Bit definition for PWR_IORETRH register *****************/ +#define PWR_IORETRH_RET3_Pos (3U) +#define PWR_IORETRH_RET3_Msk (0x1UL << PWR_IORETRH_RET3_Pos) /*!< 0x00000008 */ +#define PWR_IORETRH_RET3 PWR_IORETRH_RET3_Msk /*!< Standby GPIO retention status for PH3 */ + +/******************** Bit definition for PWR_RADIOSCR register *****************/ +#define PWR_RADIOSCR_MODE_Pos (0U) +#define PWR_RADIOSCR_MODE_Msk (0x3UL << PWR_RADIOSCR_MODE_Pos) /*!< 0x00000003 */ +#define PWR_RADIOSCR_MODE PWR_RADIOSCR_MODE_Msk /*!< 2.4 GHz RADIO operating mode */ +#define PWR_RADIOSCR_MODE_0 (0x1UL << PWR_RADIOSCR_MODE_Pos) /*!< 0x00000001 */ +#define PWR_RADIOSCR_MODE_1 (0x2UL << PWR_RADIOSCR_MODE_Pos) /*!< 0x00000002 */ +#define PWR_RADIOSCR_PHYMODE_Pos (2U) +#define PWR_RADIOSCR_PHYMODE_Msk (0x1UL << PWR_RADIOSCR_PHYMODE_Pos) /*!< 0x00000004 */ +#define PWR_RADIOSCR_PHYMODE PWR_RADIOSCR_PHYMODE_Msk /*!< 2.4 GHz RADIO PHY operating mode */ +#define PWR_RADIOSCR_ENCMODE_Pos (3U) +#define PWR_RADIOSCR_ENCMODE_Msk (0x1UL << PWR_RADIOSCR_ENCMODE_Pos) /*!< 0x00000008 */ +#define PWR_RADIOSCR_ENCMODE PWR_RADIOSCR_ENCMODE_Msk /*!< 2.4 GHz RADIO encryption function operating mode */ +#define PWR_RADIOSCR_RFVDDHPA_Pos (8U) +#define PWR_RADIOSCR_RFVDDHPA_Msk (0x1FUL << PWR_RADIOSCR_RFVDDHPA_Pos) /*!< 0x00001F00 */ +#define PWR_RADIOSCR_RFVDDHPA PWR_RADIOSCR_RFVDDHPA_Msk /*!< 2.4 GHz RADIO VDDHPA control word */ +#define PWR_RADIOSCR_REGPARDYVDDRFPA_Pos (15U) +#define PWR_RADIOSCR_REGPARDYVDDRFPA_Msk (0x1UL << PWR_RADIOSCR_REGPARDYVDDRFPA_Pos) /*!< 0x00008000 */ +#define PWR_RADIOSCR_REGPARDYVDDRFPA PWR_RADIOSCR_REGPARDYVDDRFPA_Msk /*!< Ready bit for VDDHPA voltage level when selecting VDDRFPA input */ + + +/******************************************************************************/ +/* */ +/* SRAMs configuration controller */ +/* */ +/******************************************************************************/ +/******************* Bit definition for RAMCFG_MxCR register ******************/ +#define RAMCFG_CR_ALE_Pos (4U) +#define RAMCFG_CR_ALE_Msk (0x1UL << RAMCFG_CR_ALE_Pos) /*!< 0x00000010 */ +#define RAMCFG_CR_ALE RAMCFG_CR_ALE_Msk /*!< Address Latching Enable */ +#define RAMCFG_CR_SRAMER_Pos (8U) +#define RAMCFG_CR_SRAMER_Msk (0x1UL << RAMCFG_CR_SRAMER_Pos) /*!< 0x00000100 */ +#define RAMCFG_CR_SRAMER RAMCFG_CR_SRAMER_Msk /*!< Start Erase */ +#define RAMCFG_CR_WSC_Pos (16U) +#define RAMCFG_CR_WSC_Msk (0x7UL << RAMCFG_CR_WSC_Pos) /*!< 0x00070000 */ +#define RAMCFG_CR_WSC RAMCFG_CR_WSC_Msk /*!< WSC[18:16] Wait State Configuration field */ +#define RAMCFG_CR_WSC_0 (0x1UL << RAMCFG_CR_WSC_Pos) /*!< 0x00010000 */ +#define RAMCFG_CR_WSC_1 (0x2UL << RAMCFG_CR_WSC_Pos) /*!< 0x00020000 */ +#define RAMCFG_CR_WSC_2 (0x4UL << RAMCFG_CR_WSC_Pos) /*!< 0x00040000 */ + +/******************* Bit definition for RAMCFG_MxISR register ******************/ +#define RAMCFG_ISR_PED_Pos (1U) +#define RAMCFG_ISR_PED_Msk (0x1UL << RAMCFG_ISR_PED_Pos) /*!< 0x00000002 */ +#define RAMCFG_ISR_PED RAMCFG_ISR_PED_Msk /*!< Parity error detected */ +#define RAMCFG_ISR_SRAMBUSY_Pos (8U) +#define RAMCFG_ISR_SRAMBUSY_Msk (0x1UL << RAMCFG_ISR_SRAMBUSY_Pos) /*!< 0x00000100 */ +#define RAMCFG_ISR_SRAMBUSY RAMCFG_ISR_SRAMBUSY_Msk /*!< SRAM busy with erase operation */ + +/***************** Bit definition for RAMCFG_MxERKEYR register ***************/ +#define RAMCFG_ERKEYR_ERASEKEY_Pos (0U) +#define RAMCFG_ERKEYR_ERASEKEY_Msk (0xFFUL << RAMCFG_ERKEYR_ERASEKEY_Pos) /*!< 0x000000FF */ +#define RAMCFG_ERKEYR_ERASEKEY RAMCFG_ERKEYR_ERASEKEY_Msk /*!< Erase write protection key */ + +/******************* Bit definition for RAMCFG_MxIER register ******************/ +#define RAMCFG_IER_PEIE_Pos (1U) +#define RAMCFG_IER_PEIE_Msk (0x1UL << RAMCFG_IER_PEIE_Pos) /*!< 0x00000001 */ +#define RAMCFG_IER_PEIE RAMCFG_IER_PEIE_Msk /*!< Parity error interrupt enable */ +#define RAMCFG_IER_PENMI_Pos (3U) +#define RAMCFG_IER_PENMI_Msk (0x1UL << RAMCFG_IER_PENMI_Pos) /*!< 0x00000004 */ +#define RAMCFG_IER_PENMI RAMCFG_IER_PENMI_Msk /*!< Parity error NMI */ + +/******************* Bit definition for RAMCFG_MxPEAR register ******************/ +#define RAMCFG_PEAR_PEA_Pos (0U) +#define RAMCFG_PEAR_PEA_Msk (0xFFFFUL << RAMCFG_PEAR_PEA_Pos) /*!< 0x0000FFFF */ +#define RAMCFG_PEAR_PEA RAMCFG_PEAR_PEA_Msk /*!< Parity error SRAM word aligned address offset */ +#define RAMCFG_PEAR_ID_Pos (24U) +#define RAMCFG_PEAR_ID_Msk (0xFUL << RAMCFG_PEAR_ID_Pos) /*!< 0x0F000000 */ +#define RAMCFG_PEAR_ID RAMCFG_PEAR_ID_Msk /*!< Parity error AHB bus master ID */ +#define RAMCFG_PEAR_BYTE_Pos (28U) +#define RAMCFG_PEAR_BYTE_Msk (0xFUL << RAMCFG_PEAR_BYTE_Pos) /*!< 0xF0000000 */ +#define RAMCFG_PEAR_BYTE RAMCFG_PEAR_BYTE_Msk /*!< Byte parity error flag */ + +/******************* Bit definition for RAMCFG_MxICR register *****************/ +#define RAMCFG_ICR_CPED_Pos (1U) +#define RAMCFG_ICR_CPED_Msk (0x1UL << RAMCFG_ICR_CPED_Pos) /*!< 0x00000002 */ +#define RAMCFG_ICR_CPED RAMCFG_ICR_CPED_Msk /*!< Clear parity error detect bit */ + +/****************** Bit definition for RAMCFG_MxWPR1 register *****************/ +#define RAMCFG_WPR1_P0WP_Pos (0U) +#define RAMCFG_WPR1_P0WP_Msk (0x1UL << RAMCFG_WPR1_P0WP_Pos) /*!< 0x00000001 */ +#define RAMCFG_WPR1_P0WP RAMCFG_WPR1_P0WP_Msk /*!< Write Protection Page 00 */ +#define RAMCFG_WPR1_P1WP_Pos (1U) +#define RAMCFG_WPR1_P1WP_Msk (0x1UL << RAMCFG_WPR1_P1WP_Pos) /*!< 0x00000002 */ +#define RAMCFG_WPR1_P1WP RAMCFG_WPR1_P1WP_Msk /*!< Write Protection Page 01 */ +#define RAMCFG_WPR1_P2WP_Pos (2U) +#define RAMCFG_WPR1_P2WP_Msk (0x1UL << RAMCFG_WPR1_P2WP_Pos) /*!< 0x00000004 */ +#define RAMCFG_WPR1_P2WP RAMCFG_WPR1_P2WP_Msk /*!< Write Protection Page 02 */ +#define RAMCFG_WPR1_P3WP_Pos (3U) +#define RAMCFG_WPR1_P3WP_Msk (0x1UL << RAMCFG_WPR1_P3WP_Pos) /*!< 0x00000008 */ +#define RAMCFG_WPR1_P3WP RAMCFG_WPR1_P3WP_Msk /*!< Write Protection Page 03 */ +#define RAMCFG_WPR1_P4WP_Pos (4U) +#define RAMCFG_WPR1_P4WP_Msk (0x1UL << RAMCFG_WPR1_P4WP_Pos) /*!< 0x00000010 */ +#define RAMCFG_WPR1_P4WP RAMCFG_WPR1_P4WP_Msk /*!< Write Protection Page 04 */ +#define RAMCFG_WPR1_P5WP_Pos (5U) +#define RAMCFG_WPR1_P5WP_Msk (0x1UL << RAMCFG_WPR1_P5WP_Pos) /*!< 0x00000020 */ +#define RAMCFG_WPR1_P5WP RAMCFG_WPR1_P5WP_Msk /*!< Write Protection Page 05 */ +#define RAMCFG_WPR1_P6WP_Pos (6U) +#define RAMCFG_WPR1_P6WP_Msk (0x1UL << RAMCFG_WPR1_P6WP_Pos) /*!< 0x00000040 */ +#define RAMCFG_WPR1_P6WP RAMCFG_WPR1_P6WP_Msk /*!< Write Protection Page 06 */ +#define RAMCFG_WPR1_P7WP_Pos (7U) +#define RAMCFG_WPR1_P7WP_Msk (0x1UL << RAMCFG_WPR1_P7WP_Pos) /*!< 0x00000080 */ +#define RAMCFG_WPR1_P7WP RAMCFG_WPR1_P7WP_Msk /*!< Write Protection Page 07 */ +#define RAMCFG_WPR1_P8WP_Pos (8U) +#define RAMCFG_WPR1_P8WP_Msk (0x1UL << RAMCFG_WPR1_P8WP_Pos) /*!< 0x00000100 */ +#define RAMCFG_WPR1_P8WP RAMCFG_WPR1_P8WP_Msk /*!< Write Protection Page 08 */ +#define RAMCFG_WPR1_P9WP_Pos (9U) +#define RAMCFG_WPR1_P9WP_Msk (0x1UL << RAMCFG_WPR1_P9WP_Pos) /*!< 0x00000200 */ +#define RAMCFG_WPR1_P9WP RAMCFG_WPR1_P9WP_Msk /*!< Write Protection Page 09 */ +#define RAMCFG_WPR1_P10WP_Pos (10U) +#define RAMCFG_WPR1_P10WP_Msk (0x1UL << RAMCFG_WPR1_P10WP_Pos) /*!< 0x00000400 */ +#define RAMCFG_WPR1_P10WP RAMCFG_WPR1_P10WP_Msk /*!< Write Protection Page 10 */ +#define RAMCFG_WPR1_P11WP_Pos (11U) +#define RAMCFG_WPR1_P11WP_Msk (0x1UL << RAMCFG_WPR1_P11WP_Pos) /*!< 0x00000800 */ +#define RAMCFG_WPR1_P11WP RAMCFG_WPR1_P11WP_Msk /*!< Write Protection Page 11 */ +#define RAMCFG_WPR1_P12WP_Pos (12U) +#define RAMCFG_WPR1_P12WP_Msk (0x1UL << RAMCFG_WPR1_P12WP_Pos) /*!< 0x00001000 */ +#define RAMCFG_WPR1_P12WP RAMCFG_WPR1_P12WP_Msk /*!< Write Protection Page 12 */ +#define RAMCFG_WPR1_P13WP_Pos (13U) +#define RAMCFG_WPR1_P13WP_Msk (0x1UL << RAMCFG_WPR1_P13WP_Pos) /*!< 0x00002000 */ +#define RAMCFG_WPR1_P13WP RAMCFG_WPR1_P13WP_Msk /*!< Write Protection Page 13 */ +#define RAMCFG_WPR1_P14WP_Pos (14U) +#define RAMCFG_WPR1_P14WP_Msk (0x1UL << RAMCFG_WPR1_P14WP_Pos) /*!< 0x00004000 */ +#define RAMCFG_WPR1_P14WP RAMCFG_WPR1_P14WP_Msk /*!< Write Protection Page 14 */ +#define RAMCFG_WPR1_P15WP_Pos (15U) +#define RAMCFG_WPR1_P15WP_Msk (0x1UL << RAMCFG_WPR1_P15WP_Pos) /*!< 0x00008000 */ +#define RAMCFG_WPR1_P15WP RAMCFG_WPR1_P15WP_Msk /*!< Write Protection Page 15 */ +#define RAMCFG_WPR1_P16WP_Pos (16U) +#define RAMCFG_WPR1_P16WP_Msk (0x1UL << RAMCFG_WPR1_P16WP_Pos) /*!< 0x00010000 */ +#define RAMCFG_WPR1_P16WP RAMCFG_WPR1_P16WP_Msk /*!< Write Protection Page 16 */ +#define RAMCFG_WPR1_P17WP_Pos (17U) +#define RAMCFG_WPR1_P17WP_Msk (0x1UL << RAMCFG_WPR1_P17WP_Pos) /*!< 0x00020000 */ +#define RAMCFG_WPR1_P17WP RAMCFG_WPR1_P17WP_Msk /*!< Write Protection Page 17 */ +#define RAMCFG_WPR1_P18WP_Pos (18U) +#define RAMCFG_WPR1_P18WP_Msk (0x1UL << RAMCFG_WPR1_P18WP_Pos) /*!< 0x00040000 */ +#define RAMCFG_WPR1_P18WP RAMCFG_WPR1_P18WP_Msk /*!< Write Protection Page 18 */ +#define RAMCFG_WPR1_P19WP_Pos (19U) +#define RAMCFG_WPR1_P19WP_Msk (0x1UL << RAMCFG_WPR1_P19WP_Pos) /*!< 0x00080000 */ +#define RAMCFG_WPR1_P19WP RAMCFG_WPR1_P19WP_Msk /*!< Write Protection Page 19 */ +#define RAMCFG_WPR1_P20WP_Pos (20U) +#define RAMCFG_WPR1_P20WP_Msk (0x1UL << RAMCFG_WPR1_P20WP_Pos) /*!< 0x00100000 */ +#define RAMCFG_WPR1_P20WP RAMCFG_WPR1_P20WP_Msk /*!< Write Protection Page 20 */ +#define RAMCFG_WPR1_P21WP_Pos (21U) +#define RAMCFG_WPR1_P21WP_Msk (0x1UL << RAMCFG_WPR1_P21WP_Pos) /*!< 0x00200000 */ +#define RAMCFG_WPR1_P21WP RAMCFG_WPR1_P21WP_Msk /*!< Write Protection Page 21 */ +#define RAMCFG_WPR1_P22WP_Pos (22U) +#define RAMCFG_WPR1_P22WP_Msk (0x1UL << RAMCFG_WPR1_P22WP_Pos) /*!< 0x00400000 */ +#define RAMCFG_WPR1_P22WP RAMCFG_WPR1_P22WP_Msk /*!< Write Protection Page 22 */ +#define RAMCFG_WPR1_P23WP_Pos (23U) +#define RAMCFG_WPR1_P23WP_Msk (0x1UL << RAMCFG_WPR1_P23WP_Pos) /*!< 0x00800000 */ +#define RAMCFG_WPR1_P23WP RAMCFG_WPR1_P23WP_Msk /*!< Write Protection Page 23 */ +#define RAMCFG_WPR1_P24WP_Pos (24U) +#define RAMCFG_WPR1_P24WP_Msk (0x1UL << RAMCFG_WPR1_P24WP_Pos) /*!< 0x01000000 */ +#define RAMCFG_WPR1_P24WP RAMCFG_WPR1_P24WP_Msk /*!< Write Protection Page 24 */ +#define RAMCFG_WPR1_P25WP_Pos (25U) +#define RAMCFG_WPR1_P25WP_Msk (0x1UL << RAMCFG_WPR1_P25WP_Pos) /*!< 0x02000000 */ +#define RAMCFG_WPR1_P25WP RAMCFG_WPR1_P25WP_Msk /*!< Write Protection Page 25 */ +#define RAMCFG_WPR1_P26WP_Pos (26U) +#define RAMCFG_WPR1_P26WP_Msk (0x1UL << RAMCFG_WPR1_P26WP_Pos) /*!< 0x04000000 */ +#define RAMCFG_WPR1_P26WP RAMCFG_WPR1_P26WP_Msk /*!< Write Protection Page 26 */ +#define RAMCFG_WPR1_P27WP_Pos (27U) +#define RAMCFG_WPR1_P27WP_Msk (0x1UL << RAMCFG_WPR1_P27WP_Pos) /*!< 0x08000000 */ +#define RAMCFG_WPR1_P27WP RAMCFG_WPR1_P27WP_Msk /*!< Write Protection Page 27 */ +#define RAMCFG_WPR1_P28WP_Pos (28U) +#define RAMCFG_WPR1_P28WP_Msk (0x1UL << RAMCFG_WPR1_P28WP_Pos) /*!< 0x10000000 */ +#define RAMCFG_WPR1_P28WP RAMCFG_WPR1_P28WP_Msk /*!< Write Protection Page 28 */ +#define RAMCFG_WPR1_P29WP_Pos (29U) +#define RAMCFG_WPR1_P29WP_Msk (0x1UL << RAMCFG_WPR1_P29WP_Pos) /*!< 0x20000000 */ +#define RAMCFG_WPR1_P29WP RAMCFG_WPR1_P29WP_Msk /*!< Write Protection Page 29 */ +#define RAMCFG_WPR1_P30WP_Pos (30U) +#define RAMCFG_WPR1_P30WP_Msk (0x1UL << RAMCFG_WPR1_P30WP_Pos) /*!< 0x40000000 */ +#define RAMCFG_WPR1_P30WP RAMCFG_WPR1_P30WP_Msk /*!< Write Protection Page 30 */ +#define RAMCFG_WPR1_P31WP_Pos (31U) +#define RAMCFG_WPR1_P31WP_Msk (0x1UL << RAMCFG_WPR1_P31WP_Pos) /*!< 0x80000000 */ +#define RAMCFG_WPR1_P31WP RAMCFG_WPR1_P31WP_Msk /*!< Write Protection Page 31 */ + +/****************** Bit definition for RAMCFG_MxWPR2 register ****************/ +#define RAMCFG_WPR2_P32WP_Pos (0U) +#define RAMCFG_WPR2_P32WP_Msk (0x1UL << RAMCFG_WPR2_P32WP_Pos) /*!< 0x00000001 */ +#define RAMCFG_WPR2_P32WP RAMCFG_WPR2_P32WP_Msk /*!< Write Protection Page 32 */ +#define RAMCFG_WPR2_P33WP_Pos (1U) +#define RAMCFG_WPR2_P33WP_Msk (0x1UL << RAMCFG_WPR2_P33WP_Pos) /*!< 0x00000002 */ +#define RAMCFG_WPR2_P33WP RAMCFG_WPR2_P33WP_Msk /*!< Write Protection Page 33 */ +#define RAMCFG_WPR2_P34WP_Pos (2U) +#define RAMCFG_WPR2_P34WP_Msk (0x1UL << RAMCFG_WPR2_P34WP_Pos) /*!< 0x00000004 */ +#define RAMCFG_WPR2_P34WP RAMCFG_WPR2_P34WP_Msk /*!< Write Protection Page 34 */ +#define RAMCFG_WPR2_P35WP_Pos (3U) +#define RAMCFG_WPR2_P35WP_Msk (0x1UL << RAMCFG_WPR2_P35WP_Pos) /*!< 0x00000008 */ +#define RAMCFG_WPR2_P35WP RAMCFG_WPR2_P35WP_Msk /*!< Write Protection Page 35 */ +#define RAMCFG_WPR2_P36WP_Pos (4U) +#define RAMCFG_WPR2_P36WP_Msk (0x1UL << RAMCFG_WPR2_P36WP_Pos) /*!< 0x00000010 */ +#define RAMCFG_WPR2_P36WP RAMCFG_WPR2_P36WP_Msk /*!< Write Protection Page 36 */ +#define RAMCFG_WPR2_P37WP_Pos (5U) +#define RAMCFG_WPR2_P37WP_Msk (0x1UL << RAMCFG_WPR2_P37WP_Pos) /*!< 0x00000020 */ +#define RAMCFG_WPR2_P37WP RAMCFG_WPR2_P37WP_Msk /*!< Write Protection Page 37 */ +#define RAMCFG_WPR2_P38WP_Pos (6U) +#define RAMCFG_WPR2_P38WP_Msk (0x1UL << RAMCFG_WPR2_P38WP_Pos) /*!< 0x00000040 */ +#define RAMCFG_WPR2_P38WP RAMCFG_WPR2_P38WP_Msk /*!< Write Protection Page 38 */ +#define RAMCFG_WPR2_P39WP_Pos (7U) +#define RAMCFG_WPR2_P39WP_Msk (0x1UL << RAMCFG_WPR2_P39WP_Pos) /*!< 0x00000080 */ +#define RAMCFG_WPR2_P39WP RAMCFG_WPR2_P39WP_Msk /*!< Write Protection Page 39 */ +#define RAMCFG_WPR2_P40WP_Pos (8U) +#define RAMCFG_WPR2_P40WP_Msk (0x1UL << RAMCFG_WPR2_P40WP_Pos) /*!< 0x00000100 */ +#define RAMCFG_WPR2_P40WP RAMCFG_WPR2_P40WP_Msk /*!< Write Protection Page 40 */ +#define RAMCFG_WPR2_P41WP_Pos (9U) +#define RAMCFG_WPR2_P41WP_Msk (0x1UL << RAMCFG_WPR2_P41WP_Pos) /*!< 0x00000200 */ +#define RAMCFG_WPR2_P41WP RAMCFG_WPR2_P41WP_Msk /*!< Write Protection Page 41 */ +#define RAMCFG_WPR2_P42WP_Pos (10U) +#define RAMCFG_WPR2_P42WP_Msk (0x1UL << RAMCFG_WPR2_P42WP_Pos) /*!< 0x00000400 */ +#define RAMCFG_WPR2_P42WP RAMCFG_WPR2_P42WP_Msk /*!< Write Protection Page 42 */ +#define RAMCFG_WPR2_P43WP_Pos (11U) +#define RAMCFG_WPR2_P43WP_Msk (0x1UL << RAMCFG_WPR2_P43WP_Pos) /*!< 0x00000800 */ +#define RAMCFG_WPR2_P43WP RAMCFG_WPR2_P43WP_Msk /*!< Write Protection Page 43 */ +#define RAMCFG_WPR2_P44WP_Pos (12U) +#define RAMCFG_WPR2_P44WP_Msk (0x1UL << RAMCFG_WPR2_P44WP_Pos) /*!< 0x00001000 */ +#define RAMCFG_WPR2_P44WP RAMCFG_WPR2_P44WP_Msk /*!< Write Protection Page 44 */ +#define RAMCFG_WPR2_P45WP_Pos (13U) +#define RAMCFG_WPR2_P45WP_Msk (0x1UL << RAMCFG_WPR2_P45WP_Pos) /*!< 0x00002000 */ +#define RAMCFG_WPR2_P45WP RAMCFG_WPR2_P45WP_Msk /*!< Write Protection Page 45 */ +#define RAMCFG_WPR2_P46WP_Pos (14U) +#define RAMCFG_WPR2_P46WP_Msk (0x1UL << RAMCFG_WPR2_P46WP_Pos) /*!< 0x00004000 */ +#define RAMCFG_WPR2_P46WP RAMCFG_WPR2_P46WP_Msk /*!< Write Protection Page 46 */ +#define RAMCFG_WPR2_P47WP_Pos (15U) +#define RAMCFG_WPR2_P47WP_Msk (0x1UL << RAMCFG_WPR2_P47WP_Pos) /*!< 0x00008000 */ +#define RAMCFG_WPR2_P47WP RAMCFG_WPR2_P47WP_Msk /*!< Write Protection Page 47 */ +#define RAMCFG_WPR2_P48WP_Pos (16U) +#define RAMCFG_WPR2_P48WP_Msk (0x1UL << RAMCFG_WPR2_P48WP_Pos) /*!< 0x00010000 */ +#define RAMCFG_WPR2_P48WP RAMCFG_WPR2_P48WP_Msk /*!< Write Protection Page 48 */ +#define RAMCFG_WPR2_P49WP_Pos (17U) +#define RAMCFG_WPR2_P49WP_Msk (0x1UL << RAMCFG_WPR2_P49WP_Pos) /*!< 0x00020000 */ +#define RAMCFG_WPR2_P49WP RAMCFG_WPR2_P49WP_Msk /*!< Write Protection Page 49 */ +#define RAMCFG_WPR2_P50WP_Pos (18U) +#define RAMCFG_WPR2_P50WP_Msk (0x1UL << RAMCFG_WPR2_P50WP_Pos) /*!< 0x00040000 */ +#define RAMCFG_WPR2_P50WP RAMCFG_WPR2_P50WP_Msk /*!< Write Protection Page 50 */ +#define RAMCFG_WPR2_P51WP_Pos (19U) +#define RAMCFG_WPR2_P51WP_Msk (0x1UL << RAMCFG_WPR2_P51WP_Pos) /*!< 0x00080000 */ +#define RAMCFG_WPR2_P51WP RAMCFG_WPR2_P51WP_Msk /*!< Write Protection Page 51 */ +#define RAMCFG_WPR2_P52WP_Pos (20U) +#define RAMCFG_WPR2_P52WP_Msk (0x1UL << RAMCFG_WPR2_P52WP_Pos) /*!< 0x00100000 */ +#define RAMCFG_WPR2_P52WP RAMCFG_WPR2_P52WP_Msk /*!< Write Protection Page 52 */ +#define RAMCFG_WPR2_P53WP_Pos (21U) +#define RAMCFG_WPR2_P53WP_Msk (0x1UL << RAMCFG_WPR2_P53WP_Pos) /*!< 0x00200000 */ +#define RAMCFG_WPR2_P53WP RAMCFG_WPR2_P53WP_Msk /*!< Write Protection Page 53 */ +#define RAMCFG_WPR2_P54WP_Pos (22U) +#define RAMCFG_WPR2_P54WP_Msk (0x1UL << RAMCFG_WPR2_P54WP_Pos) /*!< 0x00400000 */ +#define RAMCFG_WPR2_P54WP RAMCFG_WPR2_P54WP_Msk /*!< Write Protection Page 54 */ +#define RAMCFG_WPR2_P55WP_Pos (23U) +#define RAMCFG_WPR2_P55WP_Msk (0x1UL << RAMCFG_WPR2_P55WP_Pos) /*!< 0x00800000 */ +#define RAMCFG_WPR2_P55WP RAMCFG_WPR2_P55WP_Msk /*!< Write Protection Page 55 */ +#define RAMCFG_WPR2_P56WP_Pos (25U) +#define RAMCFG_WPR2_P56WP_Msk (0x1UL << RAMCFG_WPR2_P56WP_Pos) /*!< 0x01000000 */ +#define RAMCFG_WPR2_P56WP RAMCFG_WPR2_P56WP_Msk /*!< Write Protection Page 56 */ +#define RAMCFG_WPR2_P57WP_Pos (26U) +#define RAMCFG_WPR2_P57WP_Msk (0x1UL << RAMCFG_WPR2_P57WP_Pos) /*!< 0x02000000 */ +#define RAMCFG_WPR2_P57WP RAMCFG_WPR2_P57WP_Msk /*!< Write Protection Page 57 */ +#define RAMCFG_WPR2_P58WP_Pos (27U) +#define RAMCFG_WPR2_P58WP_Msk (0x1UL << RAMCFG_WPR2_P58WP_Pos) /*!< 0x04000000 */ +#define RAMCFG_WPR2_P58WP RAMCFG_WPR2_P58WP_Msk /*!< Write Protection Page 58 */ +#define RAMCFG_WPR2_P59WP_Pos (28U) +#define RAMCFG_WPR2_P59WP_Msk (0x1UL << RAMCFG_WPR2_P59WP_Pos) /*!< 0x08000000 */ +#define RAMCFG_WPR2_P59WP RAMCFG_WPR2_P59WP_Msk /*!< Write Protection Page 59 */ +#define RAMCFG_WPR2_P60WP_Pos (29U) +#define RAMCFG_WPR2_P60WP_Msk (0x1UL << RAMCFG_WPR2_P60WP_Pos) /*!< 0x10000000 */ +#define RAMCFG_WPR2_P60WP RAMCFG_WPR2_P60WP_Msk /*!< Write Protection Page 60 */ +#define RAMCFG_WPR2_P61WP_Pos (30U) +#define RAMCFG_WPR2_P61WP_Msk (0x1UL << RAMCFG_WPR2_P61WP_Pos) /*!< 0x20000000 */ +#define RAMCFG_WPR2_P61WP RAMCFG_WPR2_P61WP_Msk /*!< Write Protection Page 61 */ +#define RAMCFG_WPR2_P62WP_Pos (31U) +#define RAMCFG_WPR2_P62WP_Msk (0x1UL << RAMCFG_WPR2_P62WP_Pos) /*!< 0x40000000 */ +#define RAMCFG_WPR2_P62WP RAMCFG_WPR2_P62WP_Msk /*!< Write Protection Page 62 */ +#define RAMCFG_WPR2_P63WP_Pos (31U) +#define RAMCFG_WPR2_P63WP_Msk (0x1UL << RAMCFG_WPR2_P63WP_Pos) /*!< 0x80000000 */ +#define RAMCFG_WPR2_P63WP RAMCFG_WPR2_P63WP_Msk /*!< Write Protection Page 63 */ + + +/******************************************************************************/ +/* */ +/* Reset and Clock Control */ +/* */ +/******************************************************************************/ +/******************** Bit definition for RCC_CR register ********************/ +#define RCC_CR_HSION_Pos (8U) +#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000100 */ +#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed oscillator (HSI16) clock enable */ +#define RCC_CR_HSIKERON_Pos (9U) +#define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos) /*!< 0x00000200 */ +#define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel */ +#define RCC_CR_HSIRDY_Pos (10U) +#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000400 */ +#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed oscillator (HSI16) clock ready flag */ +#define RCC_CR_HSEON_Pos (16U) +#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */ +#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed oscillator (HSE) clock enable */ +#define RCC_CR_HSERDY_Pos (17U) +#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */ +#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed oscillator (HSE) clock ready */ +#define RCC_CR_HSECSSON_Pos (19U) +#define RCC_CR_HSECSSON_Msk (0x1UL << RCC_CR_HSECSSON_Pos) /*!< 0x00080000 */ +#define RCC_CR_HSECSSON RCC_CR_HSECSSON_Msk /*!< External High Speed oscillator (HSE) clock security system enable */ +#define RCC_CR_HSEPRE_Pos (20U) +#define RCC_CR_HSEPRE_Msk (0x1UL << RCC_CR_HSEPRE_Pos) /*!< 0x00080000 */ +#define RCC_CR_HSEPRE RCC_CR_HSEPRE_Msk /*!< External High Speed oscillator (HSE) clock for sysclk prescaler */ +#define RCC_CR_PLL1ON_Pos (24U) +#define RCC_CR_PLL1ON_Msk (0x1UL << RCC_CR_PLL1ON_Pos) /*!< 0x01000000 */ +#define RCC_CR_PLL1ON RCC_CR_PLL1ON_Msk /*!< System PLL1 clock enable */ +#define RCC_CR_PLL1RDY_Pos (25U) +#define RCC_CR_PLL1RDY_Msk (0x1UL << RCC_CR_PLL1RDY_Pos) /*!< 0x02000000 */ +#define RCC_CR_PLL1RDY RCC_CR_PLL1RDY_Msk /*!< System PLL1 clock ready */ + +/******************** Bit definition for RCC_ICSCR3 register ***************/ +#define RCC_ICSCR3_HSICAL_Pos (0U) +#define RCC_ICSCR3_HSICAL_Msk (0xFFFUL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000FFF */ +#define RCC_ICSCR3_HSICAL RCC_ICSCR3_HSICAL_Msk /*!< HSICAL[11:0] bits */ +#define RCC_ICSCR3_HSICAL_0 (0x01UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000001 */ +#define RCC_ICSCR3_HSICAL_1 (0x002UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000002 */ +#define RCC_ICSCR3_HSICAL_2 (0x004UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000004 */ +#define RCC_ICSCR3_HSICAL_3 (0x008UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000008 */ +#define RCC_ICSCR3_HSICAL_4 (0x010UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000010 */ +#define RCC_ICSCR3_HSICAL_5 (0x020UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000020 */ +#define RCC_ICSCR3_HSICAL_6 (0x040UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000040 */ +#define RCC_ICSCR3_HSICAL_7 (0x080UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000080 */ +#define RCC_ICSCR3_HSICAL_8 (0x100UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000100 */ +#define RCC_ICSCR3_HSICAL_9 (0x200UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000200 */ +#define RCC_ICSCR3_HSICAL_10 (0x400UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000400 */ +#define RCC_ICSCR3_HSICAL_11 (0x800UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000800 */ +#define RCC_ICSCR3_HSITRIM_Pos (16U) +#define RCC_ICSCR3_HSITRIM_Msk (0x1FUL << RCC_ICSCR3_HSITRIM_Pos) /*!< 0x001F0000 */ +#define RCC_ICSCR3_HSITRIM RCC_ICSCR3_HSITRIM_Msk /*!< HSITRIM[4:0] bits */ +#define RCC_ICSCR3_HSITRIM_0 (0x01UL << RCC_ICSCR3_HSITRIM_Pos) /*!< 0x00010000 */ +#define RCC_ICSCR3_HSITRIM_1 (0x02UL << RCC_ICSCR3_HSITRIM_Pos) /*!< 0x00020000 */ +#define RCC_ICSCR3_HSITRIM_2 (0x04UL << RCC_ICSCR3_HSITRIM_Pos) /*!< 0x00040000 */ +#define RCC_ICSCR3_HSITRIM_3 (0x08UL << RCC_ICSCR3_HSITRIM_Pos) /*!< 0x00080000 */ +#define RCC_ICSCR3_HSITRIM_4 (0x10UL << RCC_ICSCR3_HSITRIM_Pos) /*!< 0x00100000 */ + +/******************** Bit definition for RCC_CFGR1 register *****************/ +#define RCC_CFGR1_SW_Pos (0U) +#define RCC_CFGR1_SW_Msk (0x3UL << RCC_CFGR1_SW_Pos) /*!< 0x00000003 */ +#define RCC_CFGR1_SW RCC_CFGR1_SW_Msk /*!< SW[1:0] bits (System clock Switch) */ +#define RCC_CFGR1_SW_0 (0x1UL << RCC_CFGR1_SW_Pos) /*!< 0x00000001 */ +#define RCC_CFGR1_SW_1 (0x2UL << RCC_CFGR1_SW_Pos) /*!< 0x00000002 */ +#define RCC_CFGR1_SWS_Pos (2U) +#define RCC_CFGR1_SWS_Msk (0x3UL << RCC_CFGR1_SWS_Pos) /*!< 0x0000000C */ +#define RCC_CFGR1_SWS RCC_CFGR1_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */ +#define RCC_CFGR1_SWS_0 (0x1UL << RCC_CFGR1_SWS_Pos) /*!< 0x00000004 */ +#define RCC_CFGR1_SWS_1 (0x2UL << RCC_CFGR1_SWS_Pos) /*!< 0x00000008 */ +#define RCC_CFGR1_MCOSEL_Pos (24U) +#define RCC_CFGR1_MCOSEL_Msk (0xFUL << RCC_CFGR1_MCOSEL_Pos) /*!< 0x0F000000 */ +#define RCC_CFGR1_MCOSEL RCC_CFGR1_MCOSEL_Msk /*!< MCOSEL[3:0] bits (Clock output selection) */ +#define RCC_CFGR1_MCOSEL_0 (0x1UL << RCC_CFGR1_MCOSEL_Pos) /*!< 0x01000000 */ +#define RCC_CFGR1_MCOSEL_1 (0x2UL << RCC_CFGR1_MCOSEL_Pos) /*!< 0x02000000 */ +#define RCC_CFGR1_MCOSEL_2 (0x4UL << RCC_CFGR1_MCOSEL_Pos) /*!< 0x04000000 */ +#define RCC_CFGR1_MCOSEL_3 (0x8UL << RCC_CFGR1_MCOSEL_Pos) /*!< 0x08000000 */ +#define RCC_CFGR1_MCOPRE_Pos (28U) +#define RCC_CFGR1_MCOPRE_Msk (0x7UL << RCC_CFGR1_MCOPRE_Pos) /*!< 0x70000000 */ +#define RCC_CFGR1_MCOPRE RCC_CFGR1_MCOPRE_Msk /*!< MCO[220] (Prescaler) */ +#define RCC_CFGR1_MCOPRE_0 (0x1UL << RCC_CFGR1_MCOPRE_Pos) /*!< 0x10000000 */ +#define RCC_CFGR1_MCOPRE_1 (0x2UL << RCC_CFGR1_MCOPRE_Pos) /*!< 0x20000000 */ +#define RCC_CFGR1_MCOPRE_2 (0x4UL << RCC_CFGR1_MCOPRE_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for RCC_CFGR2 register ******************/ +#define RCC_CFGR2_HPRE_Pos (0U) +#define RCC_CFGR2_HPRE_Msk (0x7UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000007 */ +#define RCC_CFGR2_HPRE RCC_CFGR2_HPRE_Msk /*!< HPRE[2:0] bits (AHB prescaler) */ +#define RCC_CFGR2_HPRE_0 (0x1UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000001 */ +#define RCC_CFGR2_HPRE_1 (0x2UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000002 */ +#define RCC_CFGR2_HPRE_2 (0x4UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000004 */ +#define RCC_CFGR2_PPRE1_Pos (4U) +#define RCC_CFGR2_PPRE1_Msk (0x7UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000070 */ +#define RCC_CFGR2_PPRE1 RCC_CFGR2_PPRE1_Msk /*!< PPRE1[2:0] bits (APB1 prescaler) */ +#define RCC_CFGR2_PPRE1_0 (0x1UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000010 */ +#define RCC_CFGR2_PPRE1_1 (0x2UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000020 */ +#define RCC_CFGR2_PPRE1_2 (0x4UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000040 */ +#define RCC_CFGR2_PPRE2_Pos (8U) +#define RCC_CFGR2_PPRE2_Msk (0x7UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000700 */ +#define RCC_CFGR2_PPRE2 RCC_CFGR2_PPRE2_Msk /*!< PPRE2[2:0] bits (APB2 prescaler) */ +#define RCC_CFGR2_PPRE2_0 (0x1UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000100 */ +#define RCC_CFGR2_PPRE2_1 (0x2UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000200 */ +#define RCC_CFGR2_PPRE2_2 (0x4UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000400 */ + +/******************** Bit definition for RCC_CFGR3 register ******************/ +#define RCC_CFGR3_PPRE7_Pos (4U) +#define RCC_CFGR3_PPRE7_Msk (0x7UL << RCC_CFGR3_PPRE7_Pos) /*!< 0x00000070 */ +#define RCC_CFGR3_PPRE7 RCC_CFGR3_PPRE7_Msk /*!< PPRE7[2:0] bits (APB7 prescaler) */ +#define RCC_CFGR3_PPRE7_0 (0x1UL << RCC_CFGR3_PPRE7_Pos) /*!< 0x00000010 */ +#define RCC_CFGR3_PPRE7_1 (0x2UL << RCC_CFGR3_PPRE7_Pos) /*!< 0x00000020 */ +#define RCC_CFGR3_PPRE7_2 (0x4UL << RCC_CFGR3_PPRE7_Pos) /*!< 0x00000040 */ + +/******************** Bit definition for RCC_PLL1CFGR register ***************/ +#define RCC_PLL1CFGR_PLL1SRC_Pos (0U) +#define RCC_PLL1CFGR_PLL1SRC_Msk (0x3UL << RCC_PLL1CFGR_PLL1SRC_Pos) /*!< 0x00000003 */ +#define RCC_PLL1CFGR_PLL1SRC RCC_PLL1CFGR_PLL1SRC_Msk +#define RCC_PLL1CFGR_PLL1SRC_0 (0x1UL << RCC_PLL1CFGR_PLL1SRC_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CFGR_PLL1SRC_1 (0x2UL << RCC_PLL1CFGR_PLL1SRC_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CFGR_PLL1RGE_Pos (2U) +#define RCC_PLL1CFGR_PLL1RGE_Msk (0x3UL << RCC_PLL1CFGR_PLL1RGE_Pos) /*!< 0x0000000C */ +#define RCC_PLL1CFGR_PLL1RGE RCC_PLL1CFGR_PLL1RGE_Msk +#define RCC_PLL1CFGR_PLL1RGE_0 (0x1UL << RCC_PLL1CFGR_PLL1RGE_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CFGR_PLL1RGE_1 (0x2UL << RCC_PLL1CFGR_PLL1RGE_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CFGR_PLL1FRACEN_Pos (4U) +#define RCC_PLL1CFGR_PLL1FRACEN_Msk (0x1UL << RCC_PLL1CFGR_PLL1FRACEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CFGR_PLL1FRACEN RCC_PLL1CFGR_PLL1FRACEN_Msk +#define RCC_PLL1CFGR_PLL1M_Pos (8U) +#define RCC_PLL1CFGR_PLL1M_Msk (0x7UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00000700 */ +#define RCC_PLL1CFGR_PLL1M RCC_PLL1CFGR_PLL1M_Msk +#define RCC_PLL1CFGR_PLL1M_0 (0x01UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CFGR_PLL1M_1 (0x02UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00000200 */ +#define RCC_PLL1CFGR_PLL1M_2 (0x04UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00000400 */ +#define RCC_PLL1CFGR_PLL1PEN_Pos (16U) +#define RCC_PLL1CFGR_PLL1PEN_Msk (0x1UL << RCC_PLL1CFGR_PLL1PEN_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CFGR_PLL1PEN RCC_PLL1CFGR_PLL1PEN_Msk +#define RCC_PLL1CFGR_PLL1QEN_Pos (17U) +#define RCC_PLL1CFGR_PLL1QEN_Msk (0x1UL << RCC_PLL1CFGR_PLL1QEN_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CFGR_PLL1QEN RCC_PLL1CFGR_PLL1QEN_Msk +#define RCC_PLL1CFGR_PLL1REN_Pos (18U) +#define RCC_PLL1CFGR_PLL1REN_Msk (0x1UL << RCC_PLL1CFGR_PLL1REN_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CFGR_PLL1REN RCC_PLL1CFGR_PLL1REN_Msk +#define RCC_PLL1CFGR_PLL1RCLKPRE_Pos (20U) +#define RCC_PLL1CFGR_PLL1RCLKPRE_Msk (0x1UL << RCC_PLL1CFGR_PLL1RCLKPRE_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CFGR_PLL1RCLKPRE RCC_PLL1CFGR_PLL1RCLKPRE_Msk +#define RCC_PLL1CFGR_PLL1RCLKPRESTEP_Pos (21U) +#define RCC_PLL1CFGR_PLL1RCLKPRESTEP_Msk (0x1UL << RCC_PLL1CFGR_PLL1RCLKPRESTEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL1CFGR_PLL1RCLKPRESTEP RCC_PLL1CFGR_PLL1RCLKPRESTEP_Msk +#define RCC_PLL1CFGR_PLL1RCLKPRERDY_Pos (22U) +#define RCC_PLL1CFGR_PLL1RCLKPRERDY_Msk (0x1UL << RCC_PLL1CFGR_PLL1RCLKPRERDY_Pos) /*!< 0x00400000 */ +#define RCC_PLL1CFGR_PLL1RCLKPRERDY RCC_PLL1CFGR_PLL1RCLKPRERDY_Msk + +/******************** Bit definition for RCC_PLL1DIVR register ***************/ +#define RCC_PLL1DIVR_PLL1N_Pos (0U) +#define RCC_PLL1DIVR_PLL1N_Msk (0x1FFUL << RCC_PLL1DIVR_PLL1N_Pos) /*!< 0x000001FF */ +#define RCC_PLL1DIVR_PLL1N RCC_PLL1DIVR_PLL1N_Msk +#define RCC_PLL1DIVR_PLL1N_0 (0x001UL << RCC_PLL1DIVR_PLL1N_Pos) /*!< 0x00000001 */ +#define RCC_PLL1DIVR_PLL1N_1 (0x002UL << RCC_PLL1DIVR_PLL1N_Pos) /*!< 0x00000002 */ +#define RCC_PLL1DIVR_PLL1N_2 (0x004UL << RCC_PLL1DIVR_PLL1N_Pos) /*!< 0x00000004 */ +#define RCC_PLL1DIVR_PLL1N_3 (0x008UL << RCC_PLL1DIVR_PLL1N_Pos) /*!< 0x00000008 */ +#define RCC_PLL1DIVR_PLL1N_4 (0x010UL << RCC_PLL1DIVR_PLL1N_Pos) /*!< 0x00000010 */ +#define RCC_PLL1DIVR_PLL1N_5 (0x020UL << RCC_PLL1DIVR_PLL1N_Pos) /*!< 0x00000020 */ +#define RCC_PLL1DIVR_PLL1N_6 (0x040UL << RCC_PLL1DIVR_PLL1N_Pos) /*!< 0x00000040 */ +#define RCC_PLL1DIVR_PLL1N_7 (0x080UL << RCC_PLL1DIVR_PLL1N_Pos) /*!< 0x00000080 */ +#define RCC_PLL1DIVR_PLL1N_8 (0x100UL << RCC_PLL1DIVR_PLL1N_Pos) /*!< 0x00000100 */ +#define RCC_PLL1DIVR_PLL1P_Pos (9U) +#define RCC_PLL1DIVR_PLL1P_Msk (0x7FUL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x0000FE00 */ +#define RCC_PLL1DIVR_PLL1P RCC_PLL1DIVR_PLL1P_Msk +#define RCC_PLL1DIVR_PLL1P_0 (0x01UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00000200 */ +#define RCC_PLL1DIVR_PLL1P_1 (0x02UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00000400 */ +#define RCC_PLL1DIVR_PLL1P_2 (0x04UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00000800 */ +#define RCC_PLL1DIVR_PLL1P_3 (0x08UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00001000 */ +#define RCC_PLL1DIVR_PLL1P_4 (0x10UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00002000 */ +#define RCC_PLL1DIVR_PLL1P_5 (0x20UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00004000 */ +#define RCC_PLL1DIVR_PLL1P_6 (0x40UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00008000 */ +#define RCC_PLL1DIVR_PLL1Q_Pos (16U) +#define RCC_PLL1DIVR_PLL1Q_Msk (0x7FUL << RCC_PLL1DIVR_PLL1Q_Pos) /*!< 0x007F0000 */ +#define RCC_PLL1DIVR_PLL1Q RCC_PLL1DIVR_PLL1Q_Msk +#define RCC_PLL1DIVR_PLL1Q_0 (0x01UL << RCC_PLL1DIVR_PLL1Q_Pos) /*!< 0x00010000 */ +#define RCC_PLL1DIVR_PLL1Q_1 (0x02UL << RCC_PLL1DIVR_PLL1Q_Pos) /*!< 0x00020000 */ +#define RCC_PLL1DIVR_PLL1Q_2 (0x04UL << RCC_PLL1DIVR_PLL1Q_Pos) /*!< 0x00040000 */ +#define RCC_PLL1DIVR_PLL1Q_3 (0x08UL << RCC_PLL1DIVR_PLL1Q_Pos) /*!< 0x00080000 */ +#define RCC_PLL1DIVR_PLL1Q_4 (0x10UL << RCC_PLL1DIVR_PLL1Q_Pos) /*!< 0x00100000 */ +#define RCC_PLL1DIVR_PLL1Q_5 (0x20UL << RCC_PLL1DIVR_PLL1Q_Pos) /*!< 0x00200020 */ +#define RCC_PLL1DIVR_PLL1Q_6 (0x40UL << RCC_PLL1DIVR_PLL1Q_Pos) /*!< 0x00400000 */ +#define RCC_PLL1DIVR_PLL1R_Pos (24U) +#define RCC_PLL1DIVR_PLL1R_Msk (0x7FUL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x7F000000 */ +#define RCC_PLL1DIVR_PLL1R RCC_PLL1DIVR_PLL1R_Msk +#define RCC_PLL1DIVR_PLL1R_0 (0x01UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x01000000 */ +#define RCC_PLL1DIVR_PLL1R_1 (0x02UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x02000000 */ +#define RCC_PLL1DIVR_PLL1R_2 (0x04UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x04000000 */ +#define RCC_PLL1DIVR_PLL1R_3 (0x08UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x08000000 */ +#define RCC_PLL1DIVR_PLL1R_4 (0x10UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x10000000 */ +#define RCC_PLL1DIVR_PLL1R_5 (0x20UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x20000000 */ +#define RCC_PLL1DIVR_PLL1R_6 (0x40UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for RCC_PLL1FRACR register ***************/ +#define RCC_PLL1FRACR_PLL1FRACN_Pos (3U) +#define RCC_PLL1FRACR_PLL1FRACN_Msk (0x1FFFUL << RCC_PLL1FRACR_PLL1FRACN_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL1FRACR_PLL1FRACN RCC_PLL1FRACR_PLL1FRACN_Msk + +/******************** Bit definition for RCC_CIER register ******************/ +#define RCC_CIER_LSI1RDYIE_Pos (0U) +#define RCC_CIER_LSI1RDYIE_Msk (0x1UL << RCC_CIER_LSI1RDYIE_Pos) /*!< 0x00000001 */ +#define RCC_CIER_LSI1RDYIE RCC_CIER_LSI1RDYIE_Msk +#define RCC_CIER_LSERDYIE_Pos (1U) +#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk +#define RCC_CIER_HSIRDYIE_Pos (3U) +#define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000008 */ +#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk +#define RCC_CIER_HSERDYIE_Pos (4U) +#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000010 */ +#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk +#define RCC_CIER_PLL1RDYIE_Pos (6U) +#define RCC_CIER_PLL1RDYIE_Msk (0x1UL << RCC_CIER_PLL1RDYIE_Pos) /*!< 0x00000040 */ +#define RCC_CIER_PLL1RDYIE RCC_CIER_PLL1RDYIE_Msk + +/******************** Bit definition for RCC_CIFR register ****************/ +#define RCC_CIFR_LSI1RDYF_Pos (0U) +#define RCC_CIFR_LSI1RDYF_Msk (0x1UL << RCC_CIFR_LSI1RDYF_Pos) /*!< 0x00000001 */ +#define RCC_CIFR_LSI1RDYF RCC_CIFR_LSI1RDYF_Msk +#define RCC_CIFR_LSERDYF_Pos (1U) +#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk +#define RCC_CIFR_HSIRDYF_Pos (3U) +#define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000008 */ +#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk +#define RCC_CIFR_HSERDYF_Pos (4U) +#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000010 */ +#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk +#define RCC_CIFR_PLL1RDYF_Pos (6U) +#define RCC_CIFR_PLL1RDYF_Msk (0x1UL << RCC_CIFR_PLL1RDYF_Pos) /*!< 0x00000040 */ +#define RCC_CIFR_PLL1RDYF RCC_CIFR_PLL1RDYF_Msk +#define RCC_CIFR_HSECSSF_Pos (10U) +#define RCC_CIFR_HSECSSF_Msk (0x1UL << RCC_CIFR_HSECSSF_Pos) /*!< 0x00000400 */ +#define RCC_CIFR_HSECSSF RCC_CIFR_HSECSSF_Msk + +/******************** Bit definition for RCC_CICR register ****************/ +#define RCC_CICR_LSI1RDYC_Pos (0U) +#define RCC_CICR_LSI1RDYC_Msk (0x1UL << RCC_CICR_LSI1RDYC_Pos) /*!< 0x00000001 */ +#define RCC_CICR_LSI1RDYC RCC_CICR_LSI1RDYC_Msk +#define RCC_CICR_LSERDYC_Pos (1U) +#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */ +#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk +#define RCC_CICR_HSIRDYC_Pos (3U) +#define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000008 */ +#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk +#define RCC_CICR_HSERDYC_Pos (4U) +#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000010 */ +#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk +#define RCC_CICR_PLL1RDYC_Pos (6U) +#define RCC_CICR_PLL1RDYC_Msk (0x1UL << RCC_CICR_PLL1RDYC_Pos) /*!< 0x00000040 */ +#define RCC_CICR_PLL1RDYC RCC_CICR_PLL1RDYC_Msk +#define RCC_CICR_HSECSSC_Pos (10U) +#define RCC_CICR_HSECSSC_Msk (0x1UL << RCC_CICR_HSECSSC_Pos) /*!< 0x00000400 */ +#define RCC_CICR_HSECSSC RCC_CICR_HSECSSC_Msk + +/******************** Bit definition for RCC_AHB1RSTR register **************/ +#define RCC_AHB1RSTR_GPDMA1RST_Pos (0U) +#define RCC_AHB1RSTR_GPDMA1RST_Msk (0x1UL << RCC_AHB1RSTR_GPDMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB1RSTR_GPDMA1RST RCC_AHB1RSTR_GPDMA1RST_Msk +#define RCC_AHB1RSTR_CRCRST_Pos (12U) +#define RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk +#define RCC_AHB1RSTR_TSCRST_Pos (16U) +#define RCC_AHB1RSTR_TSCRST_Msk (0x1UL << RCC_AHB1RSTR_TSCRST_Pos) /*!< 0x00010000 */ +#define RCC_AHB1RSTR_TSCRST RCC_AHB1RSTR_TSCRST_Msk + +/******************** Bit definition for RCC_AHB2RSTR register **************/ +#define RCC_AHB2RSTR_GPIOARST_Pos (0U) +#define RCC_AHB2RSTR_GPIOARST_Msk (0x1UL << RCC_AHB2RSTR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB2RSTR_GPIOARST RCC_AHB2RSTR_GPIOARST_Msk +#define RCC_AHB2RSTR_GPIOBRST_Pos (1U) +#define RCC_AHB2RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB2RSTR_GPIOBRST RCC_AHB2RSTR_GPIOBRST_Msk +#define RCC_AHB2RSTR_GPIOCRST_Pos (2U) +#define RCC_AHB2RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB2RSTR_GPIOCRST RCC_AHB2RSTR_GPIOCRST_Msk +#define RCC_AHB2RSTR_GPIOHRST_Pos (7U) +#define RCC_AHB2RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB2RSTR_GPIOHRST RCC_AHB2RSTR_GPIOHRST_Msk +#define RCC_AHB2RSTR_AESRST_Pos (16U) +#define RCC_AHB2RSTR_AESRST_Msk (0x1UL << RCC_AHB2RSTR_AESRST_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTR_AESRST RCC_AHB2RSTR_AESRST_Msk +#define RCC_AHB2RSTR_HASHRST_Pos (17U) +#define RCC_AHB2RSTR_HASHRST_Msk (0x1UL << RCC_AHB2RSTR_HASHRST_Pos) /*!< 0x00020000 */ +#define RCC_AHB2RSTR_HASHRST RCC_AHB2RSTR_HASHRST_Msk +#define RCC_AHB2RSTR_RNGRST_Pos (18U) +#define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00040000 */ +#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk +#define RCC_AHB2RSTR_SAESRST_Pos (19U) +#define RCC_AHB2RSTR_SAESRST_Msk (0x1UL << RCC_AHB2RSTR_SAESRST_Pos) /*!< 0x00080000 */ +#define RCC_AHB2RSTR_SAESRST RCC_AHB2RSTR_SAESRST_Msk +#define RCC_AHB2RSTR_HSEMRST_Pos (20U) +#define RCC_AHB2RSTR_HSEMRST_Msk (0x1UL << RCC_AHB2RSTR_HSEMRST_Pos) /*!< 0x00100000 */ +#define RCC_AHB2RSTR_HSEMRST RCC_AHB2RSTR_HSEMRST_Msk +#define RCC_AHB2RSTR_PKARST_Pos (21U) +#define RCC_AHB2RSTR_PKARST_Msk (0x1UL << RCC_AHB2RSTR_PKARST_Pos) /*!< 0x00200000 */ +#define RCC_AHB2RSTR_PKARST RCC_AHB2RSTR_PKARST_Msk + +/******************** Bit definition for RCC_AHB4RSTR register **************/ +#define RCC_AHB4RSTR_ADC4RST_Pos (5U) +#define RCC_AHB4RSTR_ADC4RST_Msk (0x1UL << RCC_AHB4RSTR_ADC4RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB4RSTR_ADC4RST RCC_AHB4RSTR_ADC4RST_Msk + +/******************** Bit definition for RCC_AHB5RSTR register **************/ +#define RCC_AHB5RSTR_RADIORST_Pos (0U) +#define RCC_AHB5RSTR_RADIORST_Msk (0x1UL << RCC_AHB5RSTR_RADIORST_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTR_RADIORST RCC_AHB5RSTR_RADIORST_Msk + +/******************** Bit definition for RCC_APB1RSTR1 register **************/ +#define RCC_APB1RSTR1_TIM2RST_Pos (0U) +#define RCC_APB1RSTR1_TIM2RST_Msk (0x1UL << RCC_APB1RSTR1_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTR1_TIM2RST RCC_APB1RSTR1_TIM2RST_Msk +#define RCC_APB1RSTR1_TIM3RST_Pos (1U) +#define RCC_APB1RSTR1_TIM3RST_Msk (0x1UL << RCC_APB1RSTR1_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTR1_TIM3RST RCC_APB1RSTR1_TIM3RST_Msk +#define RCC_APB1RSTR1_USART2RST_Pos (17U) +#define RCC_APB1RSTR1_USART2RST_Msk (0x1UL << RCC_APB1RSTR1_USART2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTR1_USART2RST RCC_APB1RSTR1_USART2RST_Msk +#define RCC_APB1RSTR1_I2C1RST_Pos (21U) +#define RCC_APB1RSTR1_I2C1RST_Msk (0x1UL << RCC_APB1RSTR1_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTR1_I2C1RST RCC_APB1RSTR1_I2C1RST_Msk + +/******************** Bit definition for RCC_APB1RSTR2 register **************/ +#define RCC_APB1RSTR2_LPTIM2RST_Pos (5U) +#define RCC_APB1RSTR2_LPTIM2RST_Msk (0x1UL << RCC_APB1RSTR2_LPTIM2RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTR2_LPTIM2RST RCC_APB1RSTR2_LPTIM2RST_Msk + +/******************** Bit definition for RCC_APB2RSTR register **************/ +#define RCC_APB2RSTR_TIM1RST_Pos (11U) +#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */ +#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk +#define RCC_APB2RSTR_SPI1RST_Pos (12U) +#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ +#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk +#define RCC_APB2RSTR_USART1RST_Pos (14U) +#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ +#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk +#define RCC_APB2RSTR_TIM16RST_Pos (17U) +#define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk +#define RCC_APB2RSTR_TIM17RST_Pos (18U) +#define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk + +/******************** Bit definition for RCC_APB7RSTR register **************/ +#define RCC_APB7RSTR_SYSCFGRST_Pos (1U) +#define RCC_APB7RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB7RSTR_SYSCFGRST_Pos) /*!< 0x00000002 */ +#define RCC_APB7RSTR_SYSCFGRST RCC_APB7RSTR_SYSCFGRST_Msk +#define RCC_APB7RSTR_SPI3RST_Pos (5U) +#define RCC_APB7RSTR_SPI3RST_Msk (0x1UL << RCC_APB7RSTR_SPI3RST_Pos) /*!< 0x00000020 */ +#define RCC_APB7RSTR_SPI3RST RCC_APB7RSTR_SPI3RST_Msk +#define RCC_APB7RSTR_LPUART1RST_Pos (6U) +#define RCC_APB7RSTR_LPUART1RST_Msk (0x1UL << RCC_APB7RSTR_LPUART1RST_Pos) /*!< 0x00000040 */ +#define RCC_APB7RSTR_LPUART1RST RCC_APB7RSTR_LPUART1RST_Msk +#define RCC_APB7RSTR_I2C3RST_Pos (7U) +#define RCC_APB7RSTR_I2C3RST_Msk (0x1UL << RCC_APB7RSTR_I2C3RST_Pos) /*!< 0x00000080 */ +#define RCC_APB7RSTR_I2C3RST RCC_APB7RSTR_I2C3RST_Msk +#define RCC_APB7RSTR_LPTIM1RST_Pos (11U) +#define RCC_APB7RSTR_LPTIM1RST_Msk (0x1UL << RCC_APB7RSTR_LPTIM1RST_Pos) /*!< 0x00000800 */ +#define RCC_APB7RSTR_LPTIM1RST RCC_APB7RSTR_LPTIM1RST_Msk + +/******************** Bit definition for RCC_AHB1ENR register **************/ +#define RCC_AHB1ENR_GPDMA1EN_Pos (0U) +#define RCC_AHB1ENR_GPDMA1EN_Msk (0x1UL << RCC_AHB1ENR_GPDMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_AHB1ENR_GPDMA1EN RCC_AHB1ENR_GPDMA1EN_Msk +#define RCC_AHB1ENR_FLASHEN_Pos (8U) +#define RCC_AHB1ENR_FLASHEN_Msk (0x1UL << RCC_AHB1ENR_FLASHEN_Pos) /*!< 0x00000100 */ +#define RCC_AHB1ENR_FLASHEN RCC_AHB1ENR_FLASHEN_Msk +#define RCC_AHB1ENR_CRCEN_Pos (12U) +#define RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */ +#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk +#define RCC_AHB1ENR_TSCEN_Pos (16U) +#define RCC_AHB1ENR_TSCEN_Msk (0x1UL << RCC_AHB1ENR_TSCEN_Pos) /*!< 0x00010000 */ +#define RCC_AHB1ENR_TSCEN RCC_AHB1ENR_TSCEN_Msk +#define RCC_AHB1ENR_RAMCFGEN_Pos (17U) +#define RCC_AHB1ENR_RAMCFGEN_Msk (0x1UL << RCC_AHB1ENR_RAMCFGEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB1ENR_RAMCFGEN RCC_AHB1ENR_RAMCFGEN_Msk +#define RCC_AHB1ENR_GTZC1EN_Pos (24U) +#define RCC_AHB1ENR_GTZC1EN_Msk (0x1UL << RCC_AHB1ENR_GTZC1EN_Pos) /*!< 0x01000000 */ +#define RCC_AHB1ENR_GTZC1EN RCC_AHB1ENR_GTZC1EN_Msk +#define RCC_AHB1ENR_SRAM1EN_Pos (31U) +#define RCC_AHB1ENR_SRAM1EN_Msk (0x1UL << RCC_AHB1ENR_SRAM1EN_Pos) /*!< 0x80000000 */ +#define RCC_AHB1ENR_SRAM1EN RCC_AHB1ENR_SRAM1EN_Msk + +/******************** Bit definition for RCC_AHB2ENR register **************/ +#define RCC_AHB2ENR_GPIOAEN_Pos (0U) +#define RCC_AHB2ENR_GPIOAEN_Msk (0x1UL << RCC_AHB2ENR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB2ENR_GPIOAEN RCC_AHB2ENR_GPIOAEN_Msk +#define RCC_AHB2ENR_GPIOBEN_Pos (1U) +#define RCC_AHB2ENR_GPIOBEN_Msk (0x1UL << RCC_AHB2ENR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB2ENR_GPIOBEN RCC_AHB2ENR_GPIOBEN_Msk +#define RCC_AHB2ENR_GPIOCEN_Pos (2U) +#define RCC_AHB2ENR_GPIOCEN_Msk (0x1UL << RCC_AHB2ENR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB2ENR_GPIOCEN RCC_AHB2ENR_GPIOCEN_Msk +#define RCC_AHB2ENR_GPIOHEN_Pos (7U) +#define RCC_AHB2ENR_GPIOHEN_Msk (0x1UL << RCC_AHB2ENR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_AHB2ENR_GPIOHEN RCC_AHB2ENR_GPIOHEN_Msk +#define RCC_AHB2ENR_AESEN_Pos (16U) +#define RCC_AHB2ENR_AESEN_Msk (0x1UL << RCC_AHB2ENR_AESEN_Pos) /*!< 0x00010000 */ +#define RCC_AHB2ENR_AESEN RCC_AHB2ENR_AESEN_Msk +#define RCC_AHB2ENR_HASHEN_Pos (17U) +#define RCC_AHB2ENR_HASHEN_Msk (0x1UL << RCC_AHB2ENR_HASHEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB2ENR_HASHEN RCC_AHB2ENR_HASHEN_Msk +#define RCC_AHB2ENR_RNGEN_Pos (18U) +#define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00040000 */ +#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk +#define RCC_AHB2ENR_SAESEN_Pos (19U) +#define RCC_AHB2ENR_SAESEN_Msk (0x1UL << RCC_AHB2ENR_SAESEN_Pos) /*!< 0x00080000 */ +#define RCC_AHB2ENR_SAESEN RCC_AHB2ENR_SAESEN_Msk +#define RCC_AHB2ENR_HSEMEN_Pos (20U) +#define RCC_AHB2ENR_HSEMEN_Msk (0x1UL << RCC_AHB2ENR_HSEMEN_Pos) /*!< 0x00100000 */ +#define RCC_AHB2ENR_HSEMEN RCC_AHB2ENR_HSEMEN_Msk +#define RCC_AHB2ENR_PKAEN_Pos (21U) +#define RCC_AHB2ENR_PKAEN_Msk (0x1UL << RCC_AHB2ENR_PKAEN_Pos) /*!< 0x00200000 */ +#define RCC_AHB2ENR_PKAEN RCC_AHB2ENR_PKAEN_Msk +#define RCC_AHB2ENR_SRAM2EN_Pos (30U) +#define RCC_AHB2ENR_SRAM2EN_Msk (0x1UL << RCC_AHB2ENR_SRAM2EN_Pos) /*!< 0x40000000 */ +#define RCC_AHB2ENR_SRAM2EN RCC_AHB2ENR_SRAM2EN_Msk + +/******************** Bit definition for RCC_AHB4ENR register **************/ +#define RCC_AHB4ENR_PWREN_Pos (2U) +#define RCC_AHB4ENR_PWREN_Msk (0x1UL << RCC_AHB4ENR_PWREN_Pos) /*!< 0x00000004 */ +#define RCC_AHB4ENR_PWREN RCC_AHB4ENR_PWREN_Msk +#define RCC_AHB4ENR_ADC4EN_Pos (5U) +#define RCC_AHB4ENR_ADC4EN_Msk (0x1UL << RCC_AHB4ENR_ADC4EN_Pos) /*!< 0x00000020 */ +#define RCC_AHB4ENR_ADC4EN RCC_AHB4ENR_ADC4EN_Msk + +/******************** Bit definition for RCC_AHB5ENR register **************/ +#define RCC_AHB5ENR_RADIOEN_Pos (0U) +#define RCC_AHB5ENR_RADIOEN_Msk (0x1UL << RCC_AHB5ENR_RADIOEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB5ENR_RADIOEN RCC_AHB5ENR_RADIOEN_Msk + +/******************** Bit definition for RCC_APB1ENR1 register **************/ +#define RCC_APB1ENR1_TIM2EN_Pos (0U) +#define RCC_APB1ENR1_TIM2EN_Msk (0x1UL << RCC_APB1ENR1_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_APB1ENR1_TIM2EN RCC_APB1ENR1_TIM2EN_Msk +#define RCC_APB1ENR1_TIM3EN_Pos (1U) +#define RCC_APB1ENR1_TIM3EN_Msk (0x1UL << RCC_APB1ENR1_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_APB1ENR1_TIM3EN RCC_APB1ENR1_TIM3EN_Msk +#define RCC_APB1ENR1_WWDGEN_Pos (11U) +#define RCC_APB1ENR1_WWDGEN_Msk (0x1UL << RCC_APB1ENR1_WWDGEN_Pos) /*!< 0x00000800 */ +#define RCC_APB1ENR1_WWDGEN RCC_APB1ENR1_WWDGEN_Msk +#define RCC_APB1ENR1_USART2EN_Pos (17U) +#define RCC_APB1ENR1_USART2EN_Msk (0x1UL << RCC_APB1ENR1_USART2EN_Pos) /*!< 0x00020000 */ +#define RCC_APB1ENR1_USART2EN RCC_APB1ENR1_USART2EN_Msk +#define RCC_APB1ENR1_I2C1EN_Pos (21U) +#define RCC_APB1ENR1_I2C1EN_Msk (0x1UL << RCC_APB1ENR1_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_APB1ENR1_I2C1EN RCC_APB1ENR1_I2C1EN_Msk + +/******************** Bit definition for RCC_APB1ENR2 register **************/ +#define RCC_APB1ENR2_LPTIM2EN_Pos (5U) +#define RCC_APB1ENR2_LPTIM2EN_Msk (0x1UL << RCC_APB1ENR2_LPTIM2EN_Pos) /*!< 0x00000020 */ +#define RCC_APB1ENR2_LPTIM2EN RCC_APB1ENR2_LPTIM2EN_Msk + +/******************** Bit definition for RCC_APB2ENR register **************/ +#define RCC_APB2ENR_TIM1EN_Pos (11U) +#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */ +#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk +#define RCC_APB2ENR_SPI1EN_Pos (12U) +#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ +#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk +#define RCC_APB2ENR_USART1EN_Pos (14U) +#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */ +#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk +#define RCC_APB2ENR_TIM16EN_Pos (17U) +#define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */ +#define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk +#define RCC_APB2ENR_TIM17EN_Pos (18U) +#define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */ +#define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk + +/******************** Bit definition for RCC_APB7ENR register **************/ +#define RCC_APB7ENR_SYSCFGEN_Pos (1U) +#define RCC_APB7ENR_SYSCFGEN_Msk (0x1UL << RCC_APB7ENR_SYSCFGEN_Pos) /*!< 0x00000002 */ +#define RCC_APB7ENR_SYSCFGEN RCC_APB7ENR_SYSCFGEN_Msk +#define RCC_APB7ENR_SPI3EN_Pos (5U) +#define RCC_APB7ENR_SPI3EN_Msk (0x1UL << RCC_APB7ENR_SPI3EN_Pos) /*!< 0x00000020 */ +#define RCC_APB7ENR_SPI3EN RCC_APB7ENR_SPI3EN_Msk +#define RCC_APB7ENR_LPUART1EN_Pos (6U) +#define RCC_APB7ENR_LPUART1EN_Msk (0x1UL << RCC_APB7ENR_LPUART1EN_Pos) /*!< 0x00000040 */ +#define RCC_APB7ENR_LPUART1EN RCC_APB7ENR_LPUART1EN_Msk +#define RCC_APB7ENR_I2C3EN_Pos (7U) +#define RCC_APB7ENR_I2C3EN_Msk (0x1UL << RCC_APB7ENR_I2C3EN_Pos) /*!< 0x00000080 */ +#define RCC_APB7ENR_I2C3EN RCC_APB7ENR_I2C3EN_Msk +#define RCC_APB7ENR_LPTIM1EN_Pos (11U) +#define RCC_APB7ENR_LPTIM1EN_Msk (0x1UL << RCC_APB7ENR_LPTIM1EN_Pos) /*!< 0x00000800 */ +#define RCC_APB7ENR_LPTIM1EN RCC_APB7ENR_LPTIM1EN_Msk +#define RCC_APB7ENR_RTCAPBEN_Pos (21U) +#define RCC_APB7ENR_RTCAPBEN_Msk (0x1UL << RCC_APB7ENR_RTCAPBEN_Pos) /*!< 0x00200000 */ +#define RCC_APB7ENR_RTCAPBEN RCC_APB7ENR_RTCAPBEN_Msk + +/******************** Bit definition for RCC_AHB1SMENR register **************/ +#define RCC_AHB1SMENR_GPDMA1SMEN_Pos (0U) +#define RCC_AHB1SMENR_GPDMA1SMEN_Msk (0x1UL << RCC_AHB1SMENR_GPDMA1SMEN_Pos) /*!< 0x00000000*/ +#define RCC_AHB1SMENR_GPDMA1SMEN RCC_AHB1SMENR_GPDMA1SMEN_Msk +#define RCC_AHB1SMENR_FLASHSMEN_Pos (8U) +#define RCC_AHB1SMENR_FLASHSMEN_Msk (0x1UL << RCC_AHB1SMENR_FLASHSMEN_Pos) /*!< 0x00000100 */ +#define RCC_AHB1SMENR_FLASHSMEN RCC_AHB1SMENR_FLASHSMEN_Msk +#define RCC_AHB1SMENR_CRCSMEN_Pos (12U) +#define RCC_AHB1SMENR_CRCSMEN_Msk (0x1UL << RCC_AHB1SMENR_CRCSMEN_Pos) /*!< 0x00001000 */ +#define RCC_AHB1SMENR_CRCSMEN RCC_AHB1SMENR_CRCSMEN_Msk +#define RCC_AHB1SMENR_TSCSMEN_Pos (16U) +#define RCC_AHB1SMENR_TSCSMEN_Msk (0x1UL << RCC_AHB1SMENR_TSCSMEN_Pos) /*!< 0x00010000 */ +#define RCC_AHB1SMENR_TSCSMEN RCC_AHB1SMENR_TSCSMEN_Msk +#define RCC_AHB1SMENR_RAMCFGSMEN_Pos (17U) +#define RCC_AHB1SMENR_RAMCFGSMEN_Msk (0x1UL << RCC_AHB1SMENR_RAMCFGSMEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB1SMENR_RAMCFGSMEN RCC_AHB1SMENR_RAMCFGSMEN_Msk +#define RCC_AHB1SMENR_GTZC1SMEN_Pos (24U) +#define RCC_AHB1SMENR_GTZC1SMEN_Msk (0x1UL << RCC_AHB1SMENR_GTZC1SMEN_Pos) /*!< 0x01000000 */ +#define RCC_AHB1SMENR_GTZC1SMEN RCC_AHB1SMENR_GTZC1SMEN_Msk +#define RCC_AHB1SMENR_ICACHESMEN_Pos (29U) +#define RCC_AHB1SMENR_ICACHESMEN_Msk (0x1UL << RCC_AHB1SMENR_ICACHESMEN_Pos) /*!< 0x20000000 */ +#define RCC_AHB1SMENR_ICACHESMEN RCC_AHB1SMENR_ICACHESMEN_Msk +#define RCC_AHB1SMENR_SRAM1SMEN_Pos (31U) +#define RCC_AHB1SMENR_SRAM1SMEN_Msk (0x1UL << RCC_AHB1SMENR_SRAM1SMEN_Pos) /*!< 0x80000000 */ +#define RCC_AHB1SMENR_SRAM1SMEN RCC_AHB1SMENR_SRAM1SMEN_Msk + +/******************** Bit definition for RCC_AHB2SMENR register **************/ +#define RCC_AHB2SMENR_GPIOASMEN_Pos (0U) +#define RCC_AHB2SMENR_GPIOASMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOASMEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB2SMENR_GPIOASMEN RCC_AHB2SMENR_GPIOASMEN_Msk +#define RCC_AHB2SMENR_GPIOBSMEN_Pos (1U) +#define RCC_AHB2SMENR_GPIOBSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOBSMEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB2SMENR_GPIOBSMEN RCC_AHB2SMENR_GPIOBSMEN_Msk +#define RCC_AHB2SMENR_GPIOCSMEN_Pos (2U) +#define RCC_AHB2SMENR_GPIOCSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOCSMEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB2SMENR_GPIOCSMEN RCC_AHB2SMENR_GPIOCSMEN_Msk +#define RCC_AHB2SMENR_GPIOHSMEN_Pos (7U) +#define RCC_AHB2SMENR_GPIOHSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOHSMEN_Pos) /*!< 0x00000080 */ +#define RCC_AHB2SMENR_GPIOHSMEN RCC_AHB2SMENR_GPIOHSMEN_Msk +#define RCC_AHB2SMENR_AESSMEN_Pos (16U) +#define RCC_AHB2SMENR_AESSMEN_Msk (0x1UL << RCC_AHB2SMENR_AESSMEN_Pos) /*!< 0x00010000 */ +#define RCC_AHB2SMENR_AESSMEN RCC_AHB2SMENR_AESSMEN_Msk +#define RCC_AHB2SMENR_HASHSMEN_Pos (17U) +#define RCC_AHB2SMENR_HASHSMEN_Msk (0x1UL << RCC_AHB2SMENR_HASHSMEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB2SMENR_HASHSMEN RCC_AHB2SMENR_HASHSMEN_Msk +#define RCC_AHB2SMENR_RNGSMEN_Pos (18U) +#define RCC_AHB2SMENR_RNGSMEN_Msk (0x1UL << RCC_AHB2SMENR_RNGSMEN_Pos) /*!< 0x00040000 */ +#define RCC_AHB2SMENR_RNGSMEN RCC_AHB2SMENR_RNGSMEN_Msk +#define RCC_AHB2SMENR_SAESSMEN_Pos (19U) +#define RCC_AHB2SMENR_SAESSMEN_Msk (0x1UL << RCC_AHB2SMENR_SAESSMEN_Pos) /*!< 0x00080000 */ +#define RCC_AHB2SMENR_SAESSMEN RCC_AHB2SMENR_SAESSMEN_Msk +#define RCC_AHB2SMENR_PKASMEN_Pos (21U) +#define RCC_AHB2SMENR_PKASMEN_Msk (0x1UL << RCC_AHB2SMENR_PKASMEN_Pos) /*!< 0x00200000 */ +#define RCC_AHB2SMENR_PKASMEN RCC_AHB2SMENR_PKASMEN_Msk +#define RCC_AHB2SMENR_SRAM2SMEN_Pos (30U) +#define RCC_AHB2SMENR_SRAM2SMEN_Msk (0x1UL << RCC_AHB2SMENR_SRAM2SMEN_Pos) /*!< 0x40000000 */ +#define RCC_AHB2SMENR_SRAM2SMEN RCC_AHB2SMENR_SRAM2SMEN_Msk + +/******************** Bit definition for RCC_AHB4SMENR register **************/ +#define RCC_AHB4SMENR_PWRSMEN_Pos (2U) +#define RCC_AHB4SMENR_PWRSMEN_Msk (0x1UL << RCC_AHB4SMENR_PWRSMEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB4SMENR_PWRSMEN RCC_AHB4SMENR_PWRSMEN_Msk +#define RCC_AHB4SMENR_ADC4SMEN_Pos (5U) +#define RCC_AHB4SMENR_ADC4SMEN_Msk (0x1UL << RCC_AHB4SMENR_ADC4SMEN_Pos) /*!< 0x00000040 */ +#define RCC_AHB4SMENR_ADC4SMEN RCC_AHB4SMENR_ADC4SMEN_Msk + +/******************** Bit definition for RCC_AHB5SMENR register **************/ +#define RCC_AHB5SMENR_RADIOSMEN_Pos (0U) +#define RCC_AHB5SMENR_RADIOSMEN_Msk (0x1UL << RCC_AHB5SMENR_RADIOSMEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB5SMENR_RADIOSMEN RCC_AHB5SMENR_RADIOSMEN_Msk + +/******************** Bit definition for RCC_APB1SMENR1 register **************/ +#define RCC_APB1SMENR1_TIM2SMEN_Pos (0U) +#define RCC_APB1SMENR1_TIM2SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM2SMEN_Pos) /*!< 0x00000001 */ +#define RCC_APB1SMENR1_TIM2SMEN RCC_APB1SMENR1_TIM2SMEN_Msk +#define RCC_APB1SMENR1_TIM3SMEN_Pos (1U) +#define RCC_APB1SMENR1_TIM3SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM3SMEN_Pos) /*!< 0x00000002 */ +#define RCC_APB1SMENR1_TIM3SMEN RCC_APB1SMENR1_TIM3SMEN_Msk +#define RCC_APB1SMENR1_WWDGSMEN_Pos (11U) +#define RCC_APB1SMENR1_WWDGSMEN_Msk (0x1UL << RCC_APB1SMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */ +#define RCC_APB1SMENR1_WWDGSMEN RCC_APB1SMENR1_WWDGSMEN_Msk +#define RCC_APB1SMENR1_USART2SMEN_Pos (17U) +#define RCC_APB1SMENR1_USART2SMEN_Msk (0x1UL << RCC_APB1SMENR1_USART2SMEN_Pos) /*!< 0x00020000 */ +#define RCC_APB1SMENR1_USART2SMEN RCC_APB1SMENR1_USART2SMEN_Msk +#define RCC_APB1SMENR1_I2C1SMEN_Pos (21U) +#define RCC_APB1SMENR1_I2C1SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C1SMEN_Pos) /*!< 0x00200000 */ +#define RCC_APB1SMENR1_I2C1SMEN RCC_APB1SMENR1_I2C1SMEN_Msk + +/******************** Bit definition for RCC_APB1SMENR2 register **************/ +#define RCC_APB1SMENR2_LPTIM2SMEN_Pos (5U) +#define RCC_APB1SMENR2_LPTIM2SMEN_Msk (0x1UL << RCC_APB1SMENR2_LPTIM2SMEN_Pos) /*!< 0x00000020 */ +#define RCC_APB1SMENR2_LPTIM2SMEN RCC_APB1SMENR2_LPTIM2SMEN_Msk + +/******************** Bit definition for RCC_APB2SMENR register **************/ +#define RCC_APB2SMENR_TIM1SMEN_Pos (11U) +#define RCC_APB2SMENR_TIM1SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM1SMEN_Pos) /*!< 0x00000800 */ +#define RCC_APB2SMENR_TIM1SMEN RCC_APB2SMENR_TIM1SMEN_Msk +#define RCC_APB2SMENR_SPI1SMEN_Pos (12U) +#define RCC_APB2SMENR_SPI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */ +#define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk +#define RCC_APB2SMENR_USART1SMEN_Pos (14U) +#define RCC_APB2SMENR_USART1SMEN_Msk (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */ +#define RCC_APB2SMENR_USART1SMEN RCC_APB2SMENR_USART1SMEN_Msk +#define RCC_APB2SMENR_TIM16SMEN_Pos (17U) +#define RCC_APB2SMENR_TIM16SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM16SMEN_Pos) /*!< 0x00020000 */ +#define RCC_APB2SMENR_TIM16SMEN RCC_APB2SMENR_TIM16SMEN_Msk +#define RCC_APB2SMENR_TIM17SMEN_Pos (18U) +#define RCC_APB2SMENR_TIM17SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM17SMEN_Pos) /*!< 0x00040000 */ +#define RCC_APB2SMENR_TIM17SMEN RCC_APB2SMENR_TIM17SMEN_Msk + +/******************** Bit definition for RCC_APB7SMENR register **************/ +#define RCC_APB7SMENR_SYSCFGSMEN_Pos (1U) +#define RCC_APB7SMENR_SYSCFGSMEN_Msk (0x1UL << RCC_APB7SMENR_SYSCFGSMEN_Pos) /*!< 0x00000002 */ +#define RCC_APB7SMENR_SYSCFGSMEN RCC_APB7SMENR_SYSCFGSMEN_Msk +#define RCC_APB7SMENR_SPI3SMEN_Pos (5U) +#define RCC_APB7SMENR_SPI3SMEN_Msk (0x1UL << RCC_APB7SMENR_SPI3SMEN_Pos) /*!< 0x00000020 */ +#define RCC_APB7SMENR_SPI3SMEN RCC_APB7SMENR_SPI3SMEN_Msk +#define RCC_APB7SMENR_LPUART1SMEN_Pos (6U) +#define RCC_APB7SMENR_LPUART1SMEN_Msk (0x1UL << RCC_APB7SMENR_LPUART1SMEN_Pos) /*!< 0x00000040 */ +#define RCC_APB7SMENR_LPUART1SMEN RCC_APB7SMENR_LPUART1SMEN_Msk +#define RCC_APB7SMENR_I2C3SMEN_Pos (7U) +#define RCC_APB7SMENR_I2C3SMEN_Msk (0x1UL << RCC_APB7SMENR_I2C3SMEN_Pos) /*!< 0x00000080 */ +#define RCC_APB7SMENR_I2C3SMEN RCC_APB7SMENR_I2C3SMEN_Msk +#define RCC_APB7SMENR_LPTIM1SMEN_Pos (11U) +#define RCC_APB7SMENR_LPTIM1SMEN_Msk (0x1UL << RCC_APB7SMENR_LPTIM1SMEN_Pos) /*!< 0x00000800 */ +#define RCC_APB7SMENR_LPTIM1SMEN RCC_APB7SMENR_LPTIM1SMEN_Msk +#define RCC_APB7SMENR_RTCAPBSMEN_Pos (21U) +#define RCC_APB7SMENR_RTCAPBSMEN_Msk (0x1UL << RCC_APB7SMENR_RTCAPBSMEN_Pos) /*!< 0x00200000 */ +#define RCC_APB7SMENR_RTCAPBSMEN RCC_APB7SMENR_RTCAPBSMEN_Msk + +/******************** Bit definition for RCC_CCIPR1 register ******************/ +#define RCC_CCIPR1_USART1SEL_Pos (0U) +#define RCC_CCIPR1_USART1SEL_Msk (0x3UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000003 */ +#define RCC_CCIPR1_USART1SEL RCC_CCIPR1_USART1SEL_Msk +#define RCC_CCIPR1_USART1SEL_0 (0x1UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR1_USART1SEL_1 (0x2UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR1_USART2SEL_Pos (2U) +#define RCC_CCIPR1_USART2SEL_Msk (0x3UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x0000000C */ +#define RCC_CCIPR1_USART2SEL RCC_CCIPR1_USART2SEL_Msk +#define RCC_CCIPR1_USART2SEL_0 (0x1UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x00000004 */ +#define RCC_CCIPR1_USART2SEL_1 (0x2UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x00000008 */ +#define RCC_CCIPR1_I2C1SEL_Pos (10U) +#define RCC_CCIPR1_I2C1SEL_Msk (0x3UL << RCC_CCIPR1_I2C1SEL_Pos) /*!< 0x00000C00 */ +#define RCC_CCIPR1_I2C1SEL RCC_CCIPR1_I2C1SEL_Msk +#define RCC_CCIPR1_I2C1SEL_0 (0x1UL << RCC_CCIPR1_I2C1SEL_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR1_I2C1SEL_1 (0x2UL << RCC_CCIPR1_I2C1SEL_Pos) /*!< 0x00000800 */ +#define RCC_CCIPR1_LPTIM2SEL_Pos (18U) +#define RCC_CCIPR1_LPTIM2SEL_Msk (0x3UL << RCC_CCIPR1_LPTIM2SEL_Pos) /*!< 0x000C0000 */ +#define RCC_CCIPR1_LPTIM2SEL RCC_CCIPR1_LPTIM2SEL_Msk +#define RCC_CCIPR1_LPTIM2SEL_0 (0x1UL << RCC_CCIPR1_LPTIM2SEL_Pos) /*!< 0x00040000 */ +#define RCC_CCIPR1_LPTIM2SEL_1 (0x2UL << RCC_CCIPR1_LPTIM2SEL_Pos) /*!< 0x00080000 */ +#define RCC_CCIPR1_SPI1SEL_Pos (20U) +#define RCC_CCIPR1_SPI1SEL_Msk (0x3UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x00300000 */ +#define RCC_CCIPR1_SPI1SEL RCC_CCIPR1_SPI1SEL_Msk +#define RCC_CCIPR1_SPI1SEL_0 (0x1UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x00100000 */ +#define RCC_CCIPR1_SPI1SEL_1 (0x2UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x00200000 */ +#define RCC_CCIPR1_SYSTICKSEL_Pos (22U) +#define RCC_CCIPR1_SYSTICKSEL_Msk (0x3UL << RCC_CCIPR1_SYSTICKSEL_Pos) /*!< 0x00C00000 */ +#define RCC_CCIPR1_SYSTICKSEL RCC_CCIPR1_SYSTICKSEL_Msk +#define RCC_CCIPR1_SYSTICKSEL_0 (0x1UL << RCC_CCIPR1_SYSTICKSEL_Pos) /*!< 0x00400000 */ +#define RCC_CCIPR1_SYSTICKSEL_1 (0x2UL << RCC_CCIPR1_SYSTICKSEL_Pos) /*!< 0x00800000 */ +#define RCC_CCIPR1_TIMICSEL_Pos (31U) +#define RCC_CCIPR1_TIMICSEL_Msk (0x1UL << RCC_CCIPR1_TIMICSEL_Pos) /*!< 0x80000000 */ +#define RCC_CCIPR1_TIMICSEL RCC_CCIPR1_TIMICSEL_Msk + +/******************** Bit definition for RCC_CCIPR2 register ******************/ +#define RCC_CCIPR2_RNGSEL_Pos (12U) +#define RCC_CCIPR2_RNGSEL_Msk (0x3UL << RCC_CCIPR2_RNGSEL_Pos) /*!< 0x00300000 */ +#define RCC_CCIPR2_RNGSEL RCC_CCIPR2_RNGSEL_Msk +#define RCC_CCIPR2_RNGSEL_0 (0x1UL << RCC_CCIPR2_RNGSEL_Pos) /*!< 0x00100000 */ +#define RCC_CCIPR2_RNGSEL_1 (0x2UL << RCC_CCIPR2_RNGSEL_Pos) /*!< 0x00200000 */ + +/******************** Bit definition for RCC_CCIPR3 register ***************/ +#define RCC_CCIPR3_LPUART1SEL_Pos (0U) +#define RCC_CCIPR3_LPUART1SEL_Msk (0x3UL << RCC_CCIPR3_LPUART1SEL_Pos) /*!< 0x00000003 */ +#define RCC_CCIPR3_LPUART1SEL RCC_CCIPR3_LPUART1SEL_Msk +#define RCC_CCIPR3_LPUART1SEL_0 (0x1UL << RCC_CCIPR3_LPUART1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR3_LPUART1SEL_1 (0x2UL << RCC_CCIPR3_LPUART1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR3_SPI3SEL_Pos (3U) +#define RCC_CCIPR3_SPI3SEL_Msk (0x3UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000018 */ +#define RCC_CCIPR3_SPI3SEL RCC_CCIPR3_SPI3SEL_Msk +#define RCC_CCIPR3_SPI3SEL_0 (0x1UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000008 */ +#define RCC_CCIPR3_SPI3SEL_1 (0x2UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR3_I2C3SEL_Pos (6U) +#define RCC_CCIPR3_I2C3SEL_Msk (0x3UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x000000C0 */ +#define RCC_CCIPR3_I2C3SEL RCC_CCIPR3_I2C3SEL_Msk +#define RCC_CCIPR3_I2C3SEL_0 (0x1UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR3_I2C3SEL_1 (0x2UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000080 */ +#define RCC_CCIPR3_LPTIM1SEL_Pos (10U) +#define RCC_CCIPR3_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00000C00 */ +#define RCC_CCIPR3_LPTIM1SEL RCC_CCIPR3_LPTIM1SEL_Msk +#define RCC_CCIPR3_LPTIM1SEL_0 (0x1UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR3_LPTIM1SEL_1 (0x2UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00000800 */ +#define RCC_CCIPR3_ADCSEL_Pos (12U) +#define RCC_CCIPR3_ADCSEL_Msk (0x7UL << RCC_CCIPR3_ADCSEL_Pos) /*!< 0x00007000 */ +#define RCC_CCIPR3_ADCSEL RCC_CCIPR3_ADCSEL_Msk +#define RCC_CCIPR3_ADCSEL_0 (0x1UL << RCC_CCIPR3_ADCSEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR3_ADCSEL_1 (0x2UL << RCC_CCIPR3_ADCSEL_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR3_ADCSEL_2 (0x4UL << RCC_CCIPR3_ADCSEL_Pos) /*!< 0x00004000 */ + +/******************** Bit definition for RCC_BDCR1 register ******************/ +#define RCC_BDCR1_LSEON_Pos (0U) +#define RCC_BDCR1_LSEON_Msk (0x1UL << RCC_BDCR1_LSEON_Pos) /*!< 0x00000001 */ +#define RCC_BDCR1_LSEON RCC_BDCR1_LSEON_Msk +#define RCC_BDCR1_LSERDY_Pos (1U) +#define RCC_BDCR1_LSERDY_Msk (0x1UL << RCC_BDCR1_LSERDY_Pos) /*!< 0x00000002 */ +#define RCC_BDCR1_LSERDY RCC_BDCR1_LSERDY_Msk +#define RCC_BDCR1_LSEBYP_Pos (2U) +#define RCC_BDCR1_LSEBYP_Msk (0x1UL << RCC_BDCR1_LSEBYP_Pos) /*!< 0x00000004 */ +#define RCC_BDCR1_LSEBYP RCC_BDCR1_LSEBYP_Msk +#define RCC_BDCR1_LSEDRV_Pos (3U) +#define RCC_BDCR1_LSEDRV_Msk (0x3UL << RCC_BDCR1_LSEDRV_Pos) /*!< 0x00000018 */ +#define RCC_BDCR1_LSEDRV RCC_BDCR1_LSEDRV_Msk +#define RCC_BDCR1_LSEDRV_0 (0x1UL << RCC_BDCR1_LSEDRV_Pos) /*!< 0x00000008 */ +#define RCC_BDCR1_LSEDRV_1 (0x2UL << RCC_BDCR1_LSEDRV_Pos) /*!< 0x00000010 */ +#define RCC_BDCR1_LSECSSON_Pos (5U) +#define RCC_BDCR1_LSECSSON_Msk (0x1UL << RCC_BDCR1_LSECSSON_Pos) /*!< 0x00000020 */ +#define RCC_BDCR1_LSECSSON RCC_BDCR1_LSECSSON_Msk +#define RCC_BDCR1_LSECSSD_Pos (6U) +#define RCC_BDCR1_LSECSSD_Msk (0x1UL << RCC_BDCR1_LSECSSD_Pos) /*!< 0x00000040 */ +#define RCC_BDCR1_LSECSSD RCC_BDCR1_LSECSSD_Msk +#define RCC_BDCR1_LSESYSEN_Pos (7U) +#define RCC_BDCR1_LSESYSEN_Msk (0x1UL << RCC_BDCR1_LSESYSEN_Pos) /*!< 0x00000080 */ +#define RCC_BDCR1_LSESYSEN RCC_BDCR1_LSESYSEN_Msk +#define RCC_BDCR1_RTCSEL_Pos (8U) +#define RCC_BDCR1_RTCSEL_Msk (0x3UL << RCC_BDCR1_RTCSEL_Pos) /*!< 0x00000300 */ +#define RCC_BDCR1_RTCSEL RCC_BDCR1_RTCSEL_Msk +#define RCC_BDCR1_RTCSEL_0 (0x1UL << RCC_BDCR1_RTCSEL_Pos) /*!< 0x00000100 */ +#define RCC_BDCR1_RTCSEL_1 (0x2UL << RCC_BDCR1_RTCSEL_Pos) /*!< 0x00000200 */ +#define RCC_BDCR1_LSESYSRDY_Pos (11U) +#define RCC_BDCR1_LSESYSRDY_Msk (0x1UL << RCC_BDCR1_LSESYSRDY_Pos) /*!< 0x00000800 */ +#define RCC_BDCR1_LSESYSRDY RCC_BDCR1_LSESYSRDY_Msk +#define RCC_BDCR1_LSEGFON_Pos (12U) +#define RCC_BDCR1_LSEGFON_Msk (0x1UL << RCC_BDCR1_LSEGFON_Pos) /*!< 0x00001000 */ +#define RCC_BDCR1_LSEGFON RCC_BDCR1_LSEGFON_Msk +#define RCC_BDCR1_LSETRIM_Pos (13U) +#define RCC_BDCR1_LSETRIM_Msk (0x3UL << RCC_BDCR1_LSETRIM_Pos) /*!< 0x00006000 */ +#define RCC_BDCR1_LSETRIM RCC_BDCR1_LSETRIM_Msk +#define RCC_BDCR1_LSETRIM_0 (0x1UL << RCC_BDCR1_LSETRIM_Pos) /*!< 0x00002000 */ +#define RCC_BDCR1_LSETRIM_1 (0x2UL << RCC_BDCR1_LSETRIM_Pos) /*!< 0x00004000 */ +#define RCC_BDCR1_BDRST_Pos (16U) +#define RCC_BDCR1_BDRST_Msk (0x1UL << RCC_BDCR1_BDRST_Pos) /*!< 0x00010000 */ +#define RCC_BDCR1_BDRST RCC_BDCR1_BDRST_Msk +#define RCC_BDCR1_RADIOSTSEL_Pos (18U) +#define RCC_BDCR1_RADIOSTSEL_Msk (0x3UL << RCC_BDCR1_RADIOSTSEL_Pos) /*!< 0x000C0000 */ +#define RCC_BDCR1_RADIOSTSEL RCC_BDCR1_RADIOSTSEL_Msk +#define RCC_BDCR1_RADIOSTSEL_0 (0x1UL << RCC_BDCR1_RADIOSTSEL_Pos) /*!< 0x00040000 */ +#define RCC_BDCR1_RADIOSTSEL_1 (0x2UL << RCC_BDCR1_RADIOSTSEL_Pos) /*!< 0x00080000 */ +#define RCC_BDCR1_LSCOEN_Pos (24U) +#define RCC_BDCR1_LSCOEN_Msk (0x1UL << RCC_BDCR1_LSCOEN_Pos) /*!< 0x01000000 */ +#define RCC_BDCR1_LSCOEN RCC_BDCR1_LSCOEN_Msk +#define RCC_BDCR1_LSCOSEL_Pos (25U) +#define RCC_BDCR1_LSCOSEL_Msk (0x1UL << RCC_BDCR1_LSCOSEL_Pos) /*!< 0x02000000 */ +#define RCC_BDCR1_LSCOSEL RCC_BDCR1_LSCOSEL_Msk +#define RCC_BDCR1_LSI1ON_Pos (26U) +#define RCC_BDCR1_LSI1ON_Msk (0x1UL << RCC_BDCR1_LSI1ON_Pos) /*!< 0x04000000 */ +#define RCC_BDCR1_LSI1ON RCC_BDCR1_LSI1ON_Msk +#define RCC_BDCR1_LSI1RDY_Pos (27U) +#define RCC_BDCR1_LSI1RDY_Msk (0x1UL << RCC_BDCR1_LSI1RDY_Pos) /*!< 0x08000000 */ +#define RCC_BDCR1_LSI1RDY RCC_BDCR1_LSI1RDY_Msk +#define RCC_BDCR1_LSI1PREDIV_Pos (28U) +#define RCC_BDCR1_LSI1PREDIV_Msk (0x1UL << RCC_BDCR1_LSI1PREDIV_Pos) /*!< 0x10000000 */ +#define RCC_BDCR1_LSI1PREDIV RCC_BDCR1_LSI1PREDIV_Msk + +/******************** Bit definition for RCC_CSR register *******************/ +#define RCC_CSR_RMVF_Pos (23U) +#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */ +#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk +#define RCC_CSR_OBLRSTF_Pos (25U) +#define RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */ +#define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk +#define RCC_CSR_PINRSTF_Pos (26U) +#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */ +#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk +#define RCC_CSR_BORRSTF_Pos (27U) +#define RCC_CSR_BORRSTF_Msk (0x1UL << RCC_CSR_BORRSTF_Pos) /*!< 0x08000000 */ +#define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk +#define RCC_CSR_SFTRSTF_Pos (28U) +#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */ +#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk +#define RCC_CSR_IWDGRSTF_Pos (29U) +#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */ +#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk +#define RCC_CSR_WWDGRSTF_Pos (30U) +#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */ +#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk +#define RCC_CSR_LPWRRSTF_Pos (31U) +#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */ +#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk + + +/******************** Bit definition for RCC_SECCFGR register **************/ +#define RCC_SECCFGR_HSISEC_Pos (0U) +#define RCC_SECCFGR_HSISEC_Msk (0x1UL << RCC_SECCFGR_HSISEC_Pos) /*!< 0x00000001 */ +#define RCC_SECCFGR_HSISEC RCC_SECCFGR_HSISEC_Msk +#define RCC_SECCFGR_HSESEC_Pos (1U) +#define RCC_SECCFGR_HSESEC_Msk (0x1UL << RCC_SECCFGR_HSESEC_Pos) /*!< 0x00000002 */ +#define RCC_SECCFGR_HSESEC RCC_SECCFGR_HSESEC_Msk +#define RCC_SECCFGR_LSISEC_Pos (3U) +#define RCC_SECCFGR_LSISEC_Msk (0x1UL << RCC_SECCFGR_LSISEC_Pos) /*!< 0x00000008 */ +#define RCC_SECCFGR_LSISEC RCC_SECCFGR_LSISEC_Msk +#define RCC_SECCFGR_LSESEC_Pos (4U) +#define RCC_SECCFGR_LSESEC_Msk (0x1UL << RCC_SECCFGR_LSESEC_Pos) /*!< 0x00000010 */ +#define RCC_SECCFGR_LSESEC RCC_SECCFGR_LSESEC_Msk +#define RCC_SECCFGR_SYSCLKSEC_Pos (5U) +#define RCC_SECCFGR_SYSCLKSEC_Msk (0x1UL << RCC_SECCFGR_SYSCLKSEC_Pos) /*!< 0x00000020 */ +#define RCC_SECCFGR_SYSCLKSEC RCC_SECCFGR_SYSCLKSEC_Msk +#define RCC_SECCFGR_PRESCSEC_Pos (6U) +#define RCC_SECCFGR_PRESCSEC_Msk (0x1UL << RCC_SECCFGR_PRESCSEC_Pos) /*!< 0x00000040 */ +#define RCC_SECCFGR_PRESCSEC RCC_SECCFGR_PRESCSEC_Msk +#define RCC_SECCFGR_PLL1SEC_Pos (7U) +#define RCC_SECCFGR_PLL1SEC_Msk (0x1UL << RCC_SECCFGR_PLL1SEC_Pos) /*!< 0x00000080 */ +#define RCC_SECCFGR_PLL1SEC RCC_SECCFGR_PLL1SEC_Msk +#define RCC_SECCFGR_RMVFSEC_Pos (12U) +#define RCC_SECCFGR_RMVFSEC_Msk (0x1UL << RCC_SECCFGR_RMVFSEC_Pos) /*!< 0x00001000 */ +#define RCC_SECCFGR_RMVFSEC RCC_SECCFGR_RMVFSEC_Msk + +/******************** Bit definition for RCC_PRIVCFGR register **************/ +#define RCC_PRIVCFGR_SPRIV_Pos (0U) +#define RCC_PRIVCFGR_SPRIV_Msk (0x1UL << RCC_PRIVCFGR_SPRIV_Pos) /*!< 0x00000001 */ +#define RCC_PRIVCFGR_SPRIV RCC_PRIVCFGR_SPRIV_Msk +#define RCC_PRIVCFGR_NSPRIV_Pos (1U) +#define RCC_PRIVCFGR_NSPRIV_Msk (0x1UL << RCC_PRIVCFGR_NSPRIV_Pos) /*!< 0x00000002 */ +#define RCC_PRIVCFGR_NSPRIV RCC_PRIVCFGR_NSPRIV_Msk + +/******************** Bit definition for RCC_CFGR4 register *******************/ +#define RCC_CFGR4_HPRE5_Pos (0U) +#define RCC_CFGR4_HPRE5_Msk (0x7UL << RCC_CFGR4_HPRE5_Pos) /*!< 0x00000007 */ +#define RCC_CFGR4_HPRE5 RCC_CFGR4_HPRE5_Msk +#define RCC_CFGR4_HPRE5_0 (0x1UL << RCC_CFGR4_HPRE5_Pos) /*!< 0x00000001 */ +#define RCC_CFGR4_HPRE5_1 (0x2UL << RCC_CFGR4_HPRE5_Pos) /*!< 0x00000002 */ +#define RCC_CFGR4_HPRE5_2 (0x4UL << RCC_CFGR4_HPRE5_Pos) /*!< 0x00000004 */ +#define RCC_CFGR4_HDIV5_Pos (4U) +#define RCC_CFGR4_HDIV5_Msk (0x1UL << RCC_CFGR4_HDIV5_Pos) /*!< 0x00000080 */ +#define RCC_CFGR4_HDIV5 RCC_CFGR4_HDIV5_Msk + +/******************** Bit definition for RCC_RADIOENR register **************/ +#define RCC_RADIOENR_BBCLKEN_Pos (1U) +#define RCC_RADIOENR_BBCLKEN_Msk (0x1UL << RCC_RADIOENR_BBCLKEN_Pos) /*!< 0x00000002 */ +#define RCC_RADIOENR_BBCLKEN RCC_RADIOENR_BBCLKEN_Msk +#define RCC_RADIOENR_STRADIOCLKON_Pos (16U) +#define RCC_RADIOENR_STRADIOCLKON_Msk (0x1UL << RCC_RADIOENR_STRADIOCLKON_Pos) /*!< 0x00010000 */ +#define RCC_RADIOENR_STRADIOCLKON RCC_RADIOENR_STRADIOCLKON_Msk +#define RCC_RADIOENR_RADIOCLKRDY_Pos (17U) +#define RCC_RADIOENR_RADIOCLKRDY_Msk (0x1UL << RCC_RADIOENR_RADIOCLKRDY_Pos) /*!< 0x00020000 */ +#define RCC_RADIOENR_RADIOCLKRDY RCC_RADIOENR_RADIOCLKRDY_Msk + +/******************** Bit definition for RCC_ECSCR1 register *******************/ +#define RCC_ECSCR1_HSETRIM_Pos (16U) +#define RCC_ECSCR1_HSETRIM_Msk (0x3FUL << RCC_ECSCR1_HSETRIM_Pos) /*!< 0x003F0000 */ +#define RCC_ECSCR1_HSETRIM RCC_ECSCR1_HSETRIM_Msk +#define RCC_ECSCR1_HSETRIM_0 (0x1UL << RCC_ECSCR1_HSETRIM_Pos) /*!< 0x00010000 */ +#define RCC_ECSCR1_HSETRIM_1 (0x2UL << RCC_ECSCR1_HSETRIM_Pos) /*!< 0x00020000 */ +#define RCC_ECSCR1_HSETRIM_2 (0x4UL << RCC_ECSCR1_HSETRIM_Pos) /*!< 0x00040000 */ +#define RCC_ECSCR1_HSETRIM_3 (0x8UL << RCC_ECSCR1_HSETRIM_Pos) /*!< 0x00080000 */ +#define RCC_ECSCR1_HSETRIM_4 (0x10UL << RCC_ECSCR1_HSETRIM_Pos) /*!< 0x00100000 */ +#define RCC_ECSCR1_HSETRIM_5 (0x20UL << RCC_ECSCR1_HSETRIM_Pos) /*!< 0x00200000 */ + + +/******************************************************************************/ +/* */ +/* RNG */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RNG_CR register *******************/ +#define RNG_CR_RNGEN_Pos (2U) +#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_IE_Pos (3U) +#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_CED_Pos (5U) +#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ +#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_ARDIS_Pos (7U) +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_RNG_CONFIG3_Pos (8U) +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_NISTC_Pos (12U) +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) +#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_RNG_CONFIG2_Pos (13U) +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_CLKDIV_Pos (16U) +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_RNG_CONFIG1_Pos (20U) +#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_CONDRST_Pos (30U) +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONFIGLOCK_Pos (31U) +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk + +/******************** Bits definition for RNG_SR register *******************/ +#define RNG_SR_DRDY_Pos (0U) +#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ +#define RNG_SR_DRDY RNG_SR_DRDY_Msk +#define RNG_SR_CECS_Pos (1U) +#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ +#define RNG_SR_CECS RNG_SR_CECS_Msk +#define RNG_SR_SECS_Pos (2U) +#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ +#define RNG_SR_SECS RNG_SR_SECS_Msk +#define RNG_SR_CEIS_Pos (5U) +#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ +#define RNG_SR_CEIS RNG_SR_CEIS_Msk +#define RNG_SR_SEIS_Pos (6U) +#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ +#define RNG_SR_SEIS RNG_SR_SEIS_Msk + +/******************** Bits definition for RNG_DR register *******************/ +#define RNG_DR_RNDATA_Pos (0U) +#define RNG_DR_RNDATA_Msk (0xFFFFFFFFUL << RNG_DR_RNDATA_Pos) /*!< 0xFFFFFFFF */ +#define RNG_DR_RNDATA RNG_DR_RNDATA_Msk + +/******************** Bits definition for RNG_HTCR register *******************/ +#define RNG_HTCR_HTCFG_Pos (0U) +#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk + + +/******************************************************************************/ +/* */ +/* Real-Time Clock (RTC) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RTC_TR register *******************/ +#define RTC_TR_SU_Pos (0U) +#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */ +#define RTC_TR_SU RTC_TR_SU_Msk +#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */ +#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */ +#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */ +#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */ +#define RTC_TR_ST_Pos (4U) +#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */ +#define RTC_TR_ST RTC_TR_ST_Msk +#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */ +#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */ +#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */ +#define RTC_TR_MNU_Pos (8U) +#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_TR_MNU RTC_TR_MNU_Msk +#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_TR_MNT_Pos (12U) +#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_TR_MNT RTC_TR_MNT_Msk +#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_TR_HU_Pos (16U) +#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_TR_HU RTC_TR_HU_Msk +#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */ +#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */ +#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */ +#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */ +#define RTC_TR_HT_Pos (20U) +#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */ +#define RTC_TR_HT RTC_TR_HT_Msk +#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */ +#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */ +#define RTC_TR_PM_Pos (22U) +#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */ +#define RTC_TR_PM RTC_TR_PM_Msk + +/******************** Bits definition for RTC_DR register *******************/ +#define RTC_DR_DU_Pos (0U) +#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */ +#define RTC_DR_DU RTC_DR_DU_Msk +#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */ +#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */ +#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */ +#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */ +#define RTC_DR_DT_Pos (4U) +#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */ +#define RTC_DR_DT RTC_DR_DT_Msk +#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */ +#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */ +#define RTC_DR_MU_Pos (8U) +#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */ +#define RTC_DR_MU RTC_DR_MU_Msk +#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */ +#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */ +#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */ +#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */ +#define RTC_DR_MT_Pos (12U) +#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */ +#define RTC_DR_MT RTC_DR_MT_Msk +#define RTC_DR_WDU_Pos (13U) +#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */ +#define RTC_DR_WDU RTC_DR_WDU_Msk +#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */ +#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */ +#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */ +#define RTC_DR_YU_Pos (16U) +#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */ +#define RTC_DR_YU RTC_DR_YU_Msk +#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */ +#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */ +#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */ +#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */ +#define RTC_DR_YT_Pos (20U) +#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */ +#define RTC_DR_YT RTC_DR_YT_Msk +#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */ +#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */ +#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */ +#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */ + +/******************** Bits definition for RTC_SSR register ******************/ +#define RTC_SSR_SS_Pos (0U) +#define RTC_SSR_SS_Msk (0xFFFFFFFFUL << RTC_SSR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_SSR_SS RTC_SSR_SS_Msk + +/******************** Bits definition for RTC_ICSR register ******************/ +#define RTC_ICSR_WUTWF_Pos (2U) +#define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */ +#define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk +#define RTC_ICSR_SHPF_Pos (3U) +#define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */ +#define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk +#define RTC_ICSR_INITS_Pos (4U) +#define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */ +#define RTC_ICSR_INITS RTC_ICSR_INITS_Msk +#define RTC_ICSR_RSF_Pos (5U) +#define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */ +#define RTC_ICSR_RSF RTC_ICSR_RSF_Msk +#define RTC_ICSR_INITF_Pos (6U) +#define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */ +#define RTC_ICSR_INITF RTC_ICSR_INITF_Msk +#define RTC_ICSR_INIT_Pos (7U) +#define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */ +#define RTC_ICSR_INIT RTC_ICSR_INIT_Msk +#define RTC_ICSR_BIN_Pos (8U) +#define RTC_ICSR_BIN_Msk (0x3UL << RTC_ICSR_BIN_Pos) /*!< 0x00000300 */ +#define RTC_ICSR_BIN RTC_ICSR_BIN_Msk +#define RTC_ICSR_BIN_0 (0x1UL << RTC_ICSR_BIN_Pos) /*!< 0x00000100 */ +#define RTC_ICSR_BIN_1 (0x2UL << RTC_ICSR_BIN_Pos) /*!< 0x00000200 */ +#define RTC_ICSR_BCDU_Pos (10U) +#define RTC_ICSR_BCDU_Msk (0x7UL << RTC_ICSR_BCDU_Pos) /*!< 0x00001C00 */ +#define RTC_ICSR_BCDU RTC_ICSR_BCDU_Msk +#define RTC_ICSR_BCDU_0 (0x1UL << RTC_ICSR_BCDU_Pos) /*!< 0x00000400 */ +#define RTC_ICSR_BCDU_1 (0x2UL << RTC_ICSR_BCDU_Pos) /*!< 0x00000800 */ +#define RTC_ICSR_BCDU_2 (0x4UL << RTC_ICSR_BCDU_Pos) /*!< 0x00001000 */ +#define RTC_ICSR_RECALPF_Pos (16U) +#define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */ +#define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk + +/******************** Bits definition for RTC_PRER register *****************/ +#define RTC_PRER_PREDIV_S_Pos (0U) +#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */ +#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk +#define RTC_PRER_PREDIV_A_Pos (16U) +#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ +#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk + +/******************** Bits definition for RTC_WUTR register *****************/ +#define RTC_WUTR_WUT_Pos (0U) +#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk +#define RTC_WUTR_WUTOCLR_Pos (16U) +#define RTC_WUTR_WUTOCLR_Msk (0xFFFFUL << RTC_WUTR_WUTOCLR_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUTOCLR RTC_WUTR_WUTOCLR_Msk + +/******************** Bits definition for RTC_CR register *******************/ +#define RTC_CR_WUCKSEL_Pos (0U) +#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */ +#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk +#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */ +#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ +#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ +#define RTC_CR_TSEDGE_Pos (3U) +#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ +#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk +#define RTC_CR_REFCKON_Pos (4U) +#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ +#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk +#define RTC_CR_BYPSHAD_Pos (5U) +#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ +#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk +#define RTC_CR_FMT_Pos (6U) +#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */ +#define RTC_CR_FMT RTC_CR_FMT_Msk +#define RTC_CR_SSRUIE_Pos (7U) +#define RTC_CR_SSRUIE_Msk (0x1UL << RTC_CR_SSRUIE_Pos) /*!< 0x00000080 */ +#define RTC_CR_SSRUIE RTC_CR_SSRUIE_Msk +#define RTC_CR_ALRAE_Pos (8U) +#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ +#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk +#define RTC_CR_ALRBE_Pos (9U) +#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */ +#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk +#define RTC_CR_WUTE_Pos (10U) +#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */ +#define RTC_CR_WUTE RTC_CR_WUTE_Msk +#define RTC_CR_TSE_Pos (11U) +#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */ +#define RTC_CR_TSE RTC_CR_TSE_Msk +#define RTC_CR_ALRAIE_Pos (12U) +#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ +#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk +#define RTC_CR_ALRBIE_Pos (13U) +#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */ +#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk +#define RTC_CR_WUTIE_Pos (14U) +#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */ +#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk +#define RTC_CR_TSIE_Pos (15U) +#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */ +#define RTC_CR_TSIE RTC_CR_TSIE_Msk +#define RTC_CR_ADD1H_Pos (16U) +#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */ +#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk +#define RTC_CR_SUB1H_Pos (17U) +#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ +#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk +#define RTC_CR_BKP_Pos (18U) +#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk +#define RTC_CR_COSEL_Pos (19U) +#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ +#define RTC_CR_COSEL RTC_CR_COSEL_Msk +#define RTC_CR_POL_Pos (20U) +#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */ +#define RTC_CR_POL RTC_CR_POL_Msk +#define RTC_CR_OSEL_Pos (21U) +#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */ +#define RTC_CR_OSEL RTC_CR_OSEL_Msk +#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */ +#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ +#define RTC_CR_COE_Pos (23U) +#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */ +#define RTC_CR_COE RTC_CR_COE_Msk +#define RTC_CR_TAMPTS_Pos (25U) +#define RTC_CR_TAMPTS_Msk (0x1UL << RTC_CR_TAMPTS_Pos) /*!< 0x02000000 */ +#define RTC_CR_TAMPTS RTC_CR_TAMPTS_Msk /*! */ + +/******************** Bits definition for RTC_ALRMAR register ***************/ +#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk +#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk +#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk +#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk +#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk +#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk +#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk +#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk +#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk +#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk +#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk +#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk +#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk +#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk +#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Msk (0x3FUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x3F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_MASKSS_4 (0x10UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x10000000 */ +#define RTC_ALRMASSR_MASKSS_5 (0x20UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x20000000 */ +#define RTC_ALRMASSR_SSCLR_Pos (31U) +#define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk + +/******************** Bits definition for RTC_ALRMBR register ***************/ +#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk +#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk +#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk +#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk +#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk +#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk +#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk +#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk +#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk +#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk +#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk +#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk +#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk +#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMBSSR register *************/ +#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk +#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Msk (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x3F000000 */ +#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk +#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBSSR_MASKSS_4 (0x10UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBSSR_MASKSS_5 (0x20UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBSSR_SSCLR_Pos (31U) +#define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk + +/******************** Bits definition for RTC_SR register *******************/ +#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk +#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk +#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ +#define RTC_SR_WUTF RTC_SR_WUTF_Msk +#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ +#define RTC_SR_TSF RTC_SR_TSF_Msk +#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk +#define RTC_SR_SSRUF_Pos (6U) +#define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SR_SSRUF RTC_SR_SSRUF_Msk + +/******************** Bits definition for RTC_MISR register *****************/ +#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk +#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk +#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk +#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk +#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk +#define RTC_MISR_SSRUMF_Pos (6U) +#define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SMISR register *****************/ +#define RTC_SMISR_ALRAMF_Pos (0U) +#define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk +#define RTC_SMISR_ALRBMF_Pos (1U) +#define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk +#define RTC_SMISR_WUTMF_Pos (2U) +#define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk +#define RTC_SMISR_TSMF_Pos (3U) +#define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk +#define RTC_SMISR_TSOVMF_Pos (4U) +#define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk +#define RTC_SMISR_SSRUMF_Pos (6U) +#define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SCR register ******************/ +#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk +#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk +#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ +#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk +#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ +#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk +#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk +#define RTC_SCR_CSSRUF_Pos (6U) +#define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk + +/******************** Bits definition for RTC_ALRABINR register ******************/ +#define RTC_ALRABINR_SS_Pos (0U) +#define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk + +/******************** Bits definition for RTC_ALRBBINR register ******************/ +#define RTC_ALRBBINR_SS_Pos (0U) +#define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk + + +/******************************************************************************/ +/* */ +/* Serial Peripheral Interface (SPI) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for SPI_CR1 register ********************/ +#define SPI_CR1_SPE_Pos (0U) +#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000001 */ +#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!> HSEM_CR_LOCKID_Pos)/* Semaphore Lock ID */ + +#define HSEM_SEMID_MIN (0U) /* HSEM ID Min*/ +#define HSEM_SEMID_MAX (15U) /* HSEM ID Max */ + +#define HSEM_PROCESSID_MIN (0U) /* HSEM Process ID Min */ +#define HSEM_PROCESSID_MAX (255U) /* HSEM Process ID Max */ + +#define HSEM_CLEAR_KEY_MIN (0U) /* HSEM clear Key Min value */ +#define HSEM_CLEAR_KEY_MAX (0xFFFFU) /* HSEM clear Key Max value */ + +/******************************** I2C Instances *******************************/ +#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S)) + +/****************** I2C Instances : wakeup capability from stop modes *********/ +#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) + +/******************* I2C Instances : Group belongingness *********************/ +#define IS_I2C_GRP1_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S)) + +#define IS_I2C_GRP2_INSTANCE(INSTANCE) (((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S)) + +/******************************* AES Instances ********************************/ +#define IS_PKA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == PKA_NS) || ((INSTANCE) == PKA_S)) + +/******************************* RNG Instances ********************************/ +#define IS_RNG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RNG_NS) || ((INSTANCE) == RNG_S)) + +/****************************** RTC Instances *********************************/ +#define IS_RTC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RTC_NS) || ((INSTANCE) == RTC_S)) + +/******************************** SAI Instances *******************************/ +#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A_NS) || ((INSTANCE) == SAI1_Block_A_S) || \ + ((INSTANCE) == SAI1_Block_B_NS) || ((INSTANCE) == SAI1_Block_B_S)) + +/****************************** SMBUS Instances *******************************/ +#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S)) + +/******************* SMBUS Instances : Group membership ***********************/ +#define IS_SMBUS_GRP1_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S)) + +#define IS_SMBUS_GRP2_INSTANCE(INSTANCE) (((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S)) + +/******************************** SPI Instances *******************************/ +#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \ + ((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S)) + +#define IS_SPI_LIMITED_INSTANCE(INSTANCE) (((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S)) + +#define IS_SPI_FULL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S)) + +/******************* SPI Instances : Group belongingness *********************/ +#define IS_SPI_GRP1_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S)) + +#define IS_SPI_GRP2_INSTANCE(INSTANCE) (((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S)) + +/****************** LPTIM Instances : All supported instances *****************/ +#define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/****************** LPTIM Instances : DMA supported instances *****************/ +#define IS_LPTIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/************* LPTIM Instances : at least 1 capture/compare channel ***********/ +#define IS_LPTIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/************* LPTIM Instances : at least 2 capture/compare channel ***********/ +#define IS_LPTIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/****************** LPTIM Instances : supporting encoder interface **************/ +#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/****************** LPTIM Instances : supporting Input Capture **************/ +#define IS_LPTIM_INPUT_CAPTURE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/****************** TIM Instances : All supported instances *******************/ +#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting 32 bits counter ****************/ +#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S)) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/****************** TIM Instances : supporting the break function *************/ +#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/************** TIM Instances : supporting Break source selection *************/ +#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting 2 break inputs *****************/ +#define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) + +/************* TIM Instances : at least 1 capture/compare channel *************/ +#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/************ TIM Instances : at least 2 capture/compare channels *************/ +#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/************ TIM Instances : at least 3 capture/compare channels *************/ +#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/************ TIM Instances : at least 4 capture/compare channels *************/ +#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/****************** TIM Instances : at least 5 capture/compare channels *******/ +#define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) + +/****************** TIM Instances : at least 6 capture/compare channels *******/ +#define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) + +/************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/ +#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/ +#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/ +#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/******************** TIM Instances : DMA burst feature ***********************/ +#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/******************* TIM Instances : output(s) available **********************/ +#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ + (((((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4) || \ + ((CHANNEL) == TIM_CHANNEL_5) || \ + ((CHANNEL) == TIM_CHANNEL_6))) \ + || \ + ((((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1))) \ + || \ + ((((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1)))) + +/****************** TIM Instances : supporting complementary output(s) ********/ +#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ + (((((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)) && \ + ((CHANNEL) == TIM_CHANNEL_1)) \ + || \ + ((((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) && \ + ((CHANNEL) == TIM_CHANNEL_1))) + +/****************** TIM Instances : supporting clock division *****************/ +#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/ +#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/ +#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/****************** TIM Instances : supporting combined 3-phase PWM mode ******/ +#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) + +/****************** TIM Instances : supporting commutation event generation ***/ +#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting counting mode selection ********/ +#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/****************** TIM Instances : supporting encoder interface **************/ +#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/****************** TIM Instances : supporting Hall sensor interface **********/ +#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/**************** TIM Instances : external trigger input available ************/ +#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/************* TIM Instances : supporting ETR source selection ***************/ +#define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/ +#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/ +#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/****************** TIM Instances : supporting OCxREF clear *******************/ +#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/****************** TIM Instances : remapping capability **********************/ +#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/****************** TIM Instances : supporting repetition counter *************/ +#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/ +#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) + +/******************* TIM Instances : Timer input XOR function *****************/ +#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/******************* TIM Instances : Timer input selection ********************/ +#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) ||\ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) ||\ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) ||\ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)||\ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/******************* TIM Instances : supporting HSE32 as input ********************/ +#define IS_TIM_HSE32_INSTANCE(INSTANCE) (((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) ||\ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : Advanced timer instances *******************/ +#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) + +/****************** TIM Instances : supporting synchronization ****************/ +#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1_NS) || ((__INSTANCE__) == TIM1_S) || \ + ((__INSTANCE__) == TIM2_NS) || ((__INSTANCE__) == TIM2_S) || \ + ((__INSTANCE__) == TIM3_NS) || ((__INSTANCE__) == TIM3_S)) + +/****************************** TSC Instances *********************************/ +#define IS_TSC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == TSC_NS) || ((INSTANCE) == TSC_S)) + +/******************** USART Instances : Synchronous mode **********************/ +#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S)) + +/******************** UART Instances : Asynchronous mode **********************/ +#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S)) + +/*********************** UART Instances : FIFO mode ***************************/ +#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/*********************** UART Instances : SPI Slave mode **********************/ +#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S)) + +/****************** UART Instances : Auto Baud Rate detection ****************/ +#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S)) + +/****************** UART Instances : Driver Enable *****************/ +#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/******************** UART Instances : Half-Duplex mode **********************/ +#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/****************** UART Instances : Hardware Flow control ********************/ +#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/******************** UART Instances : LIN mode **********************/ +#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S)) + +/******************** UART Instances : Wake-up from Stop mode **********************/ +#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/*********************** UART Instances : IRDA mode ***************************/ +#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S)) + +/********************* USART Instances : Smard card mode ***********************/ +#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S)) + +/******************** LPUART Instance *****************************************/ +#define IS_LPUART_INSTANCE(INSTANCE) (((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/*********************** UART Instances : AUTONOMOUS mode ***************************/ +#define IS_UART_AUTONOMOUS_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/****************************** IWDG Instances ********************************/ +#define IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG_NS) || ((INSTANCE) == IWDG_S)) + +/****************************** WWDG Instances ********************************/ +#define IS_WWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == WWDG_NS) || ((INSTANCE) == WWDG_S)) + +#else /* #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/* Instances allowed from Non-Secure state - only alias Non-Secure */ + +/******************************* ADC Instances ********************************/ +#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC4_NS) + +#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC4_COMMON_NS) + +/******************************* AES Instances ********************************/ +#define IS_AES_ALL_INSTANCE(INSTANCE) ((INSTANCE) == AES_NS) + +/******************************** COMP Instances ******************************/ +#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1_NS) || ((INSTANCE) == COMP2_NS)) + +/******************** COMP Instances with window mode capability **************/ +#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) (((INSTANCE) == COMP1_NS) || ((INSTANCE) == COMP2_NS)) + +/******************************* CRC Instances ********************************/ +#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC_NS) + +/******************************** DMA Instances *******************************/ +#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS) || \ + ((INSTANCE) == GPDMA1_Channel1_NS) || \ + ((INSTANCE) == GPDMA1_Channel2_NS) || \ + ((INSTANCE) == GPDMA1_Channel3_NS) || \ + ((INSTANCE) == GPDMA1_Channel4_NS) || \ + ((INSTANCE) == GPDMA1_Channel5_NS) || \ + ((INSTANCE) == GPDMA1_Channel6_NS) || \ + ((INSTANCE) == GPDMA1_Channel7_NS)) + +#define IS_GPDMA_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS) || \ + ((INSTANCE) == GPDMA1_Channel1_NS) || \ + ((INSTANCE) == GPDMA1_Channel2_NS) || \ + ((INSTANCE) == GPDMA1_Channel3_NS) || \ + ((INSTANCE) == GPDMA1_Channel4_NS) || \ + ((INSTANCE) == GPDMA1_Channel5_NS) || \ + ((INSTANCE) == GPDMA1_Channel6_NS) || \ + ((INSTANCE) == GPDMA1_Channel7_NS)) + +/****************************** RAMCFG Instances ********************************/ +#define IS_RAMCFG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM1_NS) || \ + ((INSTANCE) == RAMCFG_SRAM2_NS) || \ + ((INSTANCE) == RAMCFG_SRAM6_NS)) + +/***************************** RAMCFG PED Instances *****************************/ +#define IS_RAMCFG_PED_INSTANCE(INSTANCE) ((INSTANCE) == RAMCFG_SRAM2_NS) + +/***************************** RAMCFG IT Instances ******************************/ +#define IS_RAMCFG_IT_INSTANCE(INSTANCE) ((INSTANCE) == RAMCFG_SRAM2_NS) + +/************************ RAMCFG Write Protection Instances *********************/ +#define IS_RAMCFG_WP_INSTANCE(INSTANCE) ((INSTANCE) == RAMCFG_SRAM2_NS) + +/************************ RAMCFG Erase Instances ********************************/ +#define IS_RAMCFG_ER_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM1_NS) || \ + ((INSTANCE) == RAMCFG_SRAM2_NS)) + +/******************************* GPIO Instances *******************************/ +#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA_NS) || \ + ((INSTANCE) == GPIOB_NS) || \ + ((INSTANCE) == GPIOC_NS) || \ + ((INSTANCE) == GPIOH_NS)) + +/******************************* GPIO AF Instances ****************************/ +/* On WBA, all GPIO Bank support AF */ +#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) + +/**************************** GPIO Lock Instances *****************************/ +/* On WBA, all GPIO Bank support the Lock mechanism */ +#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) + +/**************************** HSEM Lock Instances *****************************/ +#define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM_NS) + +#define HSEM_CPU1_LOCKID (HSEM_CR_LOCKID_CURRENT >> HSEM_CR_LOCKID_Pos)/* Semaphore Lock ID */ + +#define HSEM_SEMID_MIN (0U) /* HSEM ID Min*/ +#define HSEM_SEMID_MAX (15U) /* HSEM ID Max */ + +#define HSEM_PROCESSID_MIN (0U) /* HSEM Process ID Min */ +#define HSEM_PROCESSID_MAX (255U) /* HSEM Process ID Max */ + +#define HSEM_CLEAR_KEY_MIN (0U) /* HSEM clear Key Min value */ +#define HSEM_CLEAR_KEY_MAX (0xFFFFU) /* HSEM clear Key Max value */ + +/******************************** I2C Instances *******************************/ +#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C3_NS)) + +/******************* I2C Instances : Group belongingness *********************/ +#define IS_I2C_GRP1_INSTANCE(INSTANCE) ((INSTANCE) == I2C1_NS) + +#define IS_I2C_GRP2_INSTANCE(INSTANCE) ((INSTANCE) == I2C3_NS) + +/****************** I2C Instances : wakeup capability from stop modes *********/ +#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) + +/******************************* AES Instances ********************************/ +#define IS_PKA_ALL_INSTANCE(INSTANCE) ((INSTANCE) == PKA_NS) + +/******************************* RNG Instances ********************************/ +#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG_NS) + +/****************************** RTC Instances *********************************/ +#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC_NS) + +/******************************** SAI Instances *******************************/ +#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A_NS) || ((INSTANCE) == SAI1_Block_B_NS)) + +/****************************** SMBUS Instances *******************************/ +#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C3_NS)) + +/******************* SMBUS Instances : Group membership ***********************/ +#define IS_SMBUS_GRP1_INSTANCE(INSTANCE) ((INSTANCE) == I2C1_NS) + +#define IS_SMBUS_GRP2_INSTANCE(INSTANCE) ((INSTANCE) == I2C3_NS) + +/******************************** SPI Instances *******************************/ +#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI3_NS)) + +#define IS_SPI_LIMITED_INSTANCE(INSTANCE) ((INSTANCE) == SPI3_NS) + +#define IS_SPI_FULL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1_NS) + +/******************* SPI Instances : Group belongingness *********************/ +#define IS_SPI_GRP1_INSTANCE(INSTANCE) ((INSTANCE) == SPI1_NS) + +#define IS_SPI_GRP2_INSTANCE(INSTANCE) ((INSTANCE) == SPI3_NS) + +/****************** LPTIM Instances : All supported instances *****************/ +#define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM2_NS)) + +/****************** LPTIM Instances : DMA supported instances *****************/ +#define IS_LPTIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM2_NS)) + +/************* LPTIM Instances : at least 1 capture/compare channel ***********/ +#define IS_LPTIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM2_NS)) + +/************* LPTIM Instances : at least 2 capture/compare channel ***********/ +#define IS_LPTIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM2_NS)) + +/****************** LPTIM Instances : supporting encoder interface **************/ +#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM2_NS)) + +/****************** LPTIM Instances : supporting Input Capture **************/ +#define IS_LPTIM_INPUT_CAPTURE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM2_NS)) + +/****************** TIM Instances : All supported instances *******************/ +#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS) || \ + ((INSTANCE) == TIM16_NS) || \ + ((INSTANCE) == TIM17_NS)) + +/****************** TIM Instances : supporting 32 bits counter ****************/ +#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/****************** TIM Instances : supporting the break function *************/ +#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM16_NS) || \ + ((INSTANCE) == TIM17_NS)) + +/************** TIM Instances : supporting Break source selection *************/ +#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM16_NS) || \ + ((INSTANCE) == TIM17_NS)) + +/****************** TIM Instances : supporting 2 break inputs *****************/ +#define IS_TIM_BKIN2_INSTANCE(INSTANCE) ((INSTANCE) == TIM1_NS) + +/************* TIM Instances : at least 1 capture/compare channel *************/ +#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS) || \ + ((INSTANCE) == TIM16_NS) || \ + ((INSTANCE) == TIM17_NS)) + +/************ TIM Instances : at least 2 capture/compare channels *************/ +#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/************ TIM Instances : at least 3 capture/compare channels *************/ +#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/************ TIM Instances : at least 4 capture/compare channels *************/ +#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/****************** TIM Instances : at least 5 capture/compare channels *******/ +#define IS_TIM_CC5_INSTANCE(INSTANCE) ((INSTANCE) == TIM1_NS) + +/****************** TIM Instances : at least 6 capture/compare channels *******/ +#define IS_TIM_CC6_INSTANCE(INSTANCE) ((INSTANCE) == TIM1_NS) + +/************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/ +#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM16_NS) || \ + ((INSTANCE) == TIM17_NS)) + +/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/ +#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS) || \ + ((INSTANCE) == TIM16_NS) || \ + ((INSTANCE) == TIM17_NS)) + +/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/ +#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS) || \ + ((INSTANCE) == TIM16_NS) || \ + ((INSTANCE) == TIM17_NS)) + +/******************** TIM Instances : DMA burst feature ***********************/ +#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS) || \ + ((INSTANCE) == TIM16_NS) || \ + ((INSTANCE) == TIM17_NS)) + +/******************* TIM Instances : output(s) available **********************/ +#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ + ((((INSTANCE) == TIM1_NS) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4) || \ + ((CHANNEL) == TIM_CHANNEL_5) || \ + ((CHANNEL) == TIM_CHANNEL_6))) \ + || \ + (((INSTANCE) == TIM2_NS) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + (((INSTANCE) == TIM3_NS) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + (((INSTANCE) == TIM16_NS) && \ + (((CHANNEL) == TIM_CHANNEL_1))) \ + || \ + (((INSTANCE) == TIM17_NS) && \ + (((CHANNEL) == TIM_CHANNEL_1)))) + +/****************** TIM Instances : supporting complementary output(s) ********/ +#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ + ((((INSTANCE) == TIM1_NS) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + (((INSTANCE) == TIM16_NS) && \ + ((CHANNEL) == TIM_CHANNEL_1)) \ + || \ + (((INSTANCE) == TIM17_NS) && \ + ((CHANNEL) == TIM_CHANNEL_1))) + +/****************** TIM Instances : supporting clock division *****************/ +#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS) || \ + ((INSTANCE) == TIM16_NS) || \ + ((INSTANCE) == TIM17_NS)) + +/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/ +#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/ +#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/****************** TIM Instances : supporting combined 3-phase PWM mode ******/ +#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) ((INSTANCE) == TIM1_NS) + +/****************** TIM Instances : supporting commutation event generation ***/ +#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM16_NS) || \ + ((INSTANCE) == TIM17_NS)) + +/****************** TIM Instances : supporting counting mode selection ********/ +#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/****************** TIM Instances : supporting encoder interface **************/ +#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/****************** TIM Instances : supporting Hall sensor interface **********/ +#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/**************** TIM Instances : external trigger input available ************/ +#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/************* TIM Instances : supporting ETR source selection ***************/ +#define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/ +#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/ +#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/****************** TIM Instances : supporting OCxREF clear *******************/ +#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/****************** TIM Instances : remapping capability **********************/ +#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/****************** TIM Instances : supporting repetition counter *************/ +#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM16_NS) || \ + ((INSTANCE) == TIM17_NS)) + +/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/ +#define IS_TIM_TRGO2_INSTANCE(INSTANCE) ((INSTANCE) == TIM1_NS) + +/******************* TIM Instances : Timer input XOR function *****************/ +#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/******************* TIM Instances : Timer input selection ********************/ +#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS) || \ + ((INSTANCE) == TIM16_NS) || \ + ((INSTANCE) == TIM17_NS)) + +/******************* TIM Instances : supporting HSE32 as input ********************/ +#define IS_TIM_HSE32_INSTANCE(INSTANCE) (((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM17_NS)) + +/****************** TIM Instances : Advanced timer instances *******************/ +#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1_NS) + +/****************** TIM Instances : supporting synchronization ****************/ +#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1_NS) || \ + ((__INSTANCE__) == TIM2_NS) || \ + ((__INSTANCE__) == TIM3_NS)) + +/****************************** TSC Instances *********************************/ +#define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC_NS) + +/******************** USART Instances : Synchronous mode **********************/ +#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART2_NS)) + +/******************** UART Instances : Asynchronous mode **********************/ +#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART2_NS)) + +/*********************** UART Instances : FIFO mode ***************************/ +#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \ + ((INSTANCE) == USART2_NS) || \ + ((INSTANCE) == LPUART1_NS)) + +/*********************** UART Instances : SPI Slave mode **********************/ +#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART2_NS)) + +/****************** UART Instances : Auto Baud Rate detection ****************/ +#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART2_NS)) + +/****************** UART Instances : Driver Enable *****************/ +#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \ + ((INSTANCE) == USART2_NS) || \ + ((INSTANCE) == LPUART1_NS)) + +/******************** UART Instances : Half-Duplex mode **********************/ +#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \ + ((INSTANCE) == USART2_NS) || \ + ((INSTANCE) == LPUART1_NS)) + +/****************** UART Instances : Hardware Flow control ********************/ +#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \ + ((INSTANCE) == USART2_NS) || \ + ((INSTANCE) == LPUART1_NS)) + +/******************** UART Instances : LIN mode **********************/ +#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART2_NS)) + +/******************** UART Instances : Wake-up from Stop mode **********************/ +#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \ + ((INSTANCE) == USART2_NS) || \ + ((INSTANCE) == LPUART1_NS)) + +/*********************** UART Instances : IRDA mode ***************************/ +#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART2_NS)) + +/********************* USART Instances : Smard card mode ***********************/ +#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART2_NS)) + +/*********************** UART Instances : AUTONOMOUS mode ***************************/ +#define IS_UART_AUTONOMOUS_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \ + ((INSTANCE) == USART2_NS) || \ + ((INSTANCE) == LPUART1_NS)) + +/******************** LPUART Instance *****************************************/ +#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1_NS) + +/****************************** IWDG Instances ********************************/ +#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG_NS) + +/****************************** WWDG Instances ********************************/ +#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG_NS) + +#endif /* #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** @} */ /* End of group STM32WBAxx_Peripheral_Exported_macros */ + +/** @} */ /* End of group STM32WBA52xx */ + +/** @} */ /* End of group ST */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WBA52xx_H */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba54xx.h b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba54xx.h new file mode 100644 index 0000000000..3ff8f14394 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba54xx.h @@ -0,0 +1,15801 @@ +/** + ****************************************************************************** + * @file stm32wba54xx.h + * @author MCD Application Team + * @brief CMSIS STM32WBA54xx Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral's registers hardware + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef STM32WBA54xx_H +#define STM32WBA54xx_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup ST + * @{ + */ + +/** @addtogroup STM32WBA54xx + * @{ + */ + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ +typedef enum +{ +/* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ======================================= */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation + and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory + related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SecureFault_IRQn = -9, /*!< -9 Secure Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + +/* =========================================== STM32WBA54xx Specific Interrupt Numbers ====================================== */ + WWDG_IRQn = 0, /*!< Window WatchDog interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + RTC_IRQn = 2, /*!< RTC non-secure interrupt */ + RTC_S_IRQn = 3, /*!< RTC secure interrupt */ + TAMP_IRQn = 4, /*!< Tamper global interrupt */ + RAMCFG_IRQn = 5, /*!< RAMCFG global interrupt */ + FLASH_IRQn = 6, /*!< FLASH non-secure global interrupt */ + FLASH_S_IRQn = 7, /*!< FLASH secure global interrupt */ + GTZC_IRQn = 8, /*!< Global TrustZone Controller interrupt */ + RCC_IRQn = 9, /*!< RCC non secure global interrupt */ + RCC_S_IRQn = 10, /*!< RCC secure global interrupt */ + EXTI0_IRQn = 11, /*!< EXTI Line0 interrupt */ + EXTI1_IRQn = 12, /*!< EXTI Line1 interrupt */ + EXTI2_IRQn = 13, /*!< EXTI Line2 interrupt */ + EXTI3_IRQn = 14, /*!< EXTI Line3 interrupt */ + EXTI4_IRQn = 15, /*!< EXTI Line4 interrupt */ + EXTI5_IRQn = 16, /*!< EXTI Line5 interrupt */ + EXTI6_IRQn = 17, /*!< EXTI Line6 interrupt */ + EXTI7_IRQn = 18, /*!< EXTI Line7 interrupt */ + EXTI8_IRQn = 19, /*!< EXTI Line8 interrupt */ + EXTI9_IRQn = 20, /*!< EXTI Line9 interrupt */ + EXTI10_IRQn = 21, /*!< EXTI Line10 interrupt */ + EXTI11_IRQn = 22, /*!< EXTI Line11 interrupt */ + EXTI12_IRQn = 23, /*!< EXTI Line12 interrupt */ + EXTI13_IRQn = 24, /*!< EXTI Line13 interrupt */ + EXTI14_IRQn = 25, /*!< EXTI Line14 interrupt */ + EXTI15_IRQn = 26, /*!< EXTI Line15 interrupt */ + IWDG_IRQn = 27, /*!< IWDG global interrupt */ + SAES_IRQn = 28, /*!< Secure AES global interrupt */ + GPDMA1_Channel0_IRQn = 29, /*!< GPDMA1 Channel 0 global interrupt */ + GPDMA1_Channel1_IRQn = 30, /*!< GPDMA1 Channel 1 global interrupt */ + GPDMA1_Channel2_IRQn = 31, /*!< GPDMA1 Channel 2 global interrupt */ + GPDMA1_Channel3_IRQn = 32, /*!< GPDMA1 Channel 3 global interrupt */ + GPDMA1_Channel4_IRQn = 33, /*!< GPDMA1 Channel 4 global interrupt */ + GPDMA1_Channel5_IRQn = 34, /*!< GPDMA1 Channel 5 global interrupt */ + GPDMA1_Channel6_IRQn = 35, /*!< GPDMA1 Channel 6 global interrupt */ + GPDMA1_Channel7_IRQn = 36, /*!< GPDMA1 Channel 7 global interrupt */ + TIM1_BRK_IRQn = 37, /*!< TIM1 Break interrupt */ + TIM1_UP_IRQn = 38, /*!< TIM1 Update interrupt */ + TIM1_TRG_COM_IRQn = 39, /*!< TIM1 Trigger and Commutation interrupt */ + TIM1_CC_IRQn = 40, /*!< TIM1 Capture Compare interrupt */ + TIM2_IRQn = 41, /*!< TIM2 global interrupt */ + TIM3_IRQn = 42, /*!< TIM3 global interrupt */ + I2C1_EV_IRQn = 43, /*!< I2C1 Event interrupt */ + I2C1_ER_IRQn = 44, /*!< I2C1 Error interrupt */ + SPI1_IRQn = 45, /*!< SPI1 global interrupt */ + USART1_IRQn = 46, /*!< USART1 global interrupt */ + USART2_IRQn = 47, /*!< USART2 global interrupt */ + LPUART1_IRQn = 48, /*!< LPUART1 global interrupt */ + LPTIM1_IRQn = 49, /*!< LPTIM1 global interrupt */ + LPTIM2_IRQn = 50, /*!< LPTIM2 global interrupt */ + TIM16_IRQn = 51, /*!< TIM16 global interrupt */ + TIM17_IRQn = 52, /*!< TIM17 global interrupt */ + COMP_IRQn = 53, /*!< COMP1 and COMP2 through EXTI Lines interrupts */ + I2C3_EV_IRQn = 54, /*!< I2C3 Event interrupt */ + I2C3_ER_IRQn = 55, /*!< I2C3 Error interrupt */ + SAI1_IRQn = 56, /*!< Serial Audio Interface 1 global interrupt */ + TSC_IRQn = 57, /*!< Touch Sense Controller global interrupt */ + AES_IRQn = 58, /*!< AES global interrupt */ + RNG_IRQn = 59, /*!< RNG global interrupt */ + FPU_IRQn = 60, /*!< FPU global interrupt */ + HASH_IRQn = 61, /*!< HASH global interrupt */ + PKA_IRQn = 62, /*!< PKA global interrupt */ + SPI3_IRQn = 63, /*!< SPI3 global interrupt */ + ICACHE_IRQn = 64, /*!< Instruction cache global interrupt */ + ADC4_IRQn = 65, /*!< ADC4 global interrupt */ + RADIO_IRQn = 66, /*!< 2.4GHz RADIO global interrupt */ + WKUP_IRQn = 67, /*!< PWR global WKUP pin interrupt */ + HSEM_IRQn = 68, /*!< HSEM non-secure global interrupt */ + HSEM_S_IRQn = 69, /*!< HSEM secure global interrupt */ + WKUP_S_IRQn = 70, /*!< PWR secure global WKUP pin interrupt */ + RCC_AUDIOSYNC_IRQn = 71, /*!< RCC audio synchronization interrupt */ +} IRQn_Type; + + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ +/* ------- Start of section using anonymous unions and disabling warnings ------- */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/* -------- Configuration of the STM32WBAxx System On Chip ------ */ + +/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */ +#define __CM33_REV 0x0000U /* Core revision r0p1 */ +#define __SAUREGION_PRESENT 1U /* SAU regions present */ +#define __MPU_PRESENT 1U /* MPU present */ +#define __VTOR_PRESENT 1U /* VTOR present */ +#define __NVIC_PRIO_BITS 4U /* Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /* FPU present */ +#define __DSP_PRESENT 1U /* DSP extension present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include /*!< ARM Cortex-M33 processor and core peripherals */ +#include "system_stm32wbaxx.h" /*!< system_stm32wbaxx System */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ +/** @addtogroup STM32WBAxx_peripherals + * @{ + */ + +/** + * @brief Analog to Digital Converter (ADC) + */ +typedef struct +{ + __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR; /*!< ADC sampling time register, Address offset: 0x14 */ + uint32_t RESERVED0[2]; /*!< Reserved, Address offset: 0x18-0x1C */ + __IO uint32_t AWD1TR; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ + __IO uint32_t AWD2TR; /*!< ADC watchdog threshold register, Address offset: 0x24 */ + __IO uint32_t CHSELR; /*!< ADC channel select register, Address offset: 0x28 */ + __IO uint32_t AWD3TR; /*!< ADC watchdog threshold register, Address offset: 0x02C */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x30-0x3C */ + __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ + __IO uint32_t PWRR; /*!< ADC power register, Address offset: 0x44 */ + uint32_t RESERVED2[22];/*!< Reserved, Address offset: 0x48-0x9C */ + __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 configuration register, Address offset: 0xA4 */ + uint32_t RESERVED3[7]; /*!< Reserved, Address offset: 0xA8-0xC0 */ + __IO uint32_t CALFACT; /*!< ADC Calibration factor register, Address offset: 0xC4 */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: 0x308 */ +} ADC_Common_TypeDef; + +/** + * @brief Analog comparators (COMP) + */ +typedef struct +{ + __IO uint32_t CSR; /*!< Comparator control and status register, Address offset: 0x00 */ +} COMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR_ODD; /*!< COMP control and status register located in register of comparator instance odd, used for bits common to several COMP instances, Address offset: 0x00 */ + __IO uint32_t CSR_EVEN; /*!< COMP control and status register located in register of comparator instance even, used for bits common to several COMP instances, Address offset: 0x04 */ +} COMP_Common_TypeDef; + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED0; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief AES hardware accelerator + */ +typedef struct +{ + __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */ + __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */ + __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */ + __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */ + __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */ + __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */ + __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */ + __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */ + __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */ + __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */ + __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */ + __IO uint32_t KEYR4; /*!< AES key register 4, Address offset: 0x30 */ + __IO uint32_t KEYR5; /*!< AES key register 5, Address offset: 0x34 */ + __IO uint32_t KEYR6; /*!< AES key register 6, Address offset: 0x38 */ + __IO uint32_t KEYR7; /*!< AES key register 7, Address offset: 0x3C */ + __IO uint32_t SUSP0R; /*!< AES Suspend register 0, Address offset: 0x40 */ + __IO uint32_t SUSP1R; /*!< AES Suspend register 1, Address offset: 0x44 */ + __IO uint32_t SUSP2R; /*!< AES Suspend register 2, Address offset: 0x48 */ + __IO uint32_t SUSP3R; /*!< AES Suspend register 3, Address offset: 0x4C */ + __IO uint32_t SUSP4R; /*!< AES Suspend register 4, Address offset: 0x50 */ + __IO uint32_t SUSP5R; /*!< AES Suspend register 5, Address offset: 0x54 */ + __IO uint32_t SUSP6R; /*!< AES Suspend register 6, Address offset: 0x58 */ + __IO uint32_t SUSP7R; /*!< AES Suspend register 7, Address offset: 0x5C */ + uint32_t RESERVED1[168];/*!< Reserved, Address offset: 0x60 -- 0x2FC */ + __IO uint32_t IER; /*!< AES Interrupt Enable Register, Address offset: 0x300 */ + __IO uint32_t ISR; /*!< AES Interrupt Status Register, Address offset: 0x304 */ + __IO uint32_t ICR; /*!< AES Interrupt Clear Register, Address offset: 0x308 */ +} AES_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t SCR; /*!< Debug MCU status and configuration register, Address offset: 0x04 */ + __IO uint32_t APB1LFZR; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ + __IO uint32_t APB1HFZR; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ + __IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ + uint32_t RESERVED1[4];/*!< Reserved, 0x14 - 0x20 */ + __IO uint32_t APB7FZR; /*!< Debug MCU APB7 freeze register, Address offset: 0x24 */ + __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x28 */ +} DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ +typedef struct +{ + __IO uint32_t SECCFGR; /*!< DMA secure configuration register, Address offset: 0x00 */ + __IO uint32_t PRIVCFGR; /*!< DMA privileged configuration register, Address offset: 0x04 */ + __IO uint32_t RCFGLOCKR; /*!< DMA secure and privilege lock register, Address offset: 0x08 */ + __IO uint32_t MISR; /*!< DMA non secure masked interrupt status register, Address offset: 0x0C */ + __IO uint32_t SMISR; /*!< DMA secure masked interrupt status register, Address offset: 0x10 */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */ + uint32_t RESERVED1[2]; /*!< Reserved 1, Address offset: 0x54 -- 0x58 */ + __IO uint32_t CFCR; /*!< DMA channel x flag clear register, Address offset: 0x5C + (x * 0x80) */ + __IO uint32_t CSR; /*!< DMA channel x flag status register, Address offset: 0x60 + (x * 0x80) */ + __IO uint32_t CCR; /*!< DMA channel x control register, Address offset: 0x64 + (x * 0x80) */ + uint32_t RESERVED2[10]; /*!< Reserved 2, Address offset: 0x68 -- 0x8C */ + __IO uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: 0x90 + (x * 0x80) */ + __IO uint32_t CTR2; /*!< DMA channel x transfer register 2, Address offset: 0x94 + (x * 0x80) */ + __IO uint32_t CBR1; /*!< DMA channel x block register 1, Address offset: 0x98 + (x * 0x80) */ + __IO uint32_t CSAR; /*!< DMA channel x source address register, Address offset: 0x9C + (x * 0x80) */ + __IO uint32_t CDAR; /*!< DMA channel x destination address register, Address offset: 0xA0 + (x * 0x80) */ + uint32_t RESERVED3[10]; /*!< Reserved 3, Address offset: 0xA4 -- 0xC8 */ + __IO uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: 0xCC + (x * 0x80) */ +} DMA_Channel_TypeDef; + +/** + * @brief Asynch Interrupt/Event Controller (EXTI) + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR1; /*!< EXTI Security Configuration Register 1, Address offset: 0x14 */ + __IO uint32_t PRIVCFGR1; /*!< EXTI Privilege Configuration Register 1, Address offset: 0x18 */ + uint32_t RESERVED1[17]; /*!< Reserved 1, 0x1C -- 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXIT External Interrupt Configuration Register, 0x60 -- 0x6C */ + __IO uint32_t LOCKR; /*!< EXTI Lock Register, Address offset: 0x70 */ + uint32_t RESERVED2[3]; /*!< Reserved 2, 0x74 -- 0x7C */ + __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + uint32_t RESERVED0; /*!< RESERVED1, Address offset: 0x04 */ + __IO uint32_t NSKEYR; /*!< FLASH non-secure key register, Address offset: 0x08 */ + __IO uint32_t SECKEYR; /*!< FLASH secure key register, Address offset: 0x0C */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x10 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x14 */ + __IO uint32_t PDKEYR; /*!< FLASH Bank power-down key register, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ + __IO uint32_t NSSR; /*!< FLASH non-secure status register, Address offset: 0x20 */ + __IO uint32_t SECSR; /*!< FLASH secure status register, Address offset: 0x24 */ + __IO uint32_t NSCR1; /*!< FLASH non-secure control register, Address offset: 0x28 */ + __IO uint32_t SECCR1; /*!< FLASH secure control register, Address offset: 0x2C */ + __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x30 */ + __IO uint32_t OPSR; /*!< FLASH OPSR register, Address offset: 0x34 */ + __IO uint32_t NSCR2; /*!< FLASH non-secure control register, Address offset: 0x38 */ + __IO uint32_t SECCR2; /*!< FLASH secure control register, Address offset: 0x3C */ + __IO uint32_t OPTR; /*!< FLASH option control register, Address offset: 0x40 */ + __IO uint32_t NSBOOTADD0R; /*!< FLASH non-secure boot address 0 register, Address offset: 0x44 */ + __IO uint32_t NSBOOTADD1R; /*!< FLASH non-secure boot address 1 register, Address offset: 0x48 */ + __IO uint32_t SECBOOTADD0R; /*!< FLASH secure boot address 0 register, Address offset: 0x4C */ + __IO uint32_t SECWMR1; /*!< FLASH secure watermark1 register 1, Address offset: 0x50 */ + __IO uint32_t SECWMR2; /*!< FLASH secure watermark1 register 2, Address offset: 0x54 */ + __IO uint32_t WRPAR; /*!< FLASH WRP area A address register, Address offset: 0x58 */ + __IO uint32_t WRPBR; /*!< FLASH WRP area B address register, Address offset: 0x5C */ + uint32_t RESERVED3[4]; /*!< Reserved3, Address offset: 0x60-0x6C */ + __IO uint32_t OEM1KEYR1; /*!< FLASH OEM1 key register 1, Address offset: 0x70 */ + __IO uint32_t OEM1KEYR2; /*!< FLASH OEM1 key register 2, Address offset: 0x74 */ + __IO uint32_t OEM2KEYR1; /*!< FLASH OEM2 key register 1, Address offset: 0x78 */ + __IO uint32_t OEM2KEYR2; /*!< FLASH OEM2 key register 2, Address offset: 0x7C */ + __IO uint32_t SECBBR1; /*!< FLASH secure block-based bank register 1, Address offset: 0x80 */ + __IO uint32_t SECBBR2; /*!< FLASH secure block-based bank register 2, Address offset: 0x84 */ + __IO uint32_t SECBBR3; /*!< FLASH secure block-based bank register 3, Address offset: 0x88 */ + __IO uint32_t SECBBR4; /*!< FLASH secure block-based bank register 4, Address offset: 0x8C */ + uint32_t RESERVED4[12]; /*!< Reserved4, Address offset: 0x90-0xBC */ + __IO uint32_t SECHDPCR; /*!< FLASH secure HDP control register, Address offset: 0xC0 */ + __IO uint32_t PRIVCFGR; /*!< FLASH privilege configuration register, Address offset: 0xC4 */ + uint32_t RESERVED5[2]; /*!< Reserved5, Address offset: 0xC8-0xCC */ + __IO uint32_t PRIVBBR1; /*!< FLASH privilege block-based bank register 1, Address offset: 0xD0 */ + __IO uint32_t PRIVBBR2; /*!< FLASH privilege block-based bank register 2, Address offset: 0xD4 */ + __IO uint32_t PRIVBBR3; /*!< FLASH privilege block-based bank register 3, Address offset: 0xD8 */ + __IO uint32_t PRIVBBR4; /*!< FLASH privilege block-based bank register 4, Address offset: 0xDC */ +} FLASH_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ + uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register, Address offset: 0x30 */ +} GPIO_TypeDef; + +/** + * @brief Global TrustZone Controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< TZSC control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t SECCFGR1; /*!< TZSC secure configuration register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR2; /*!< TZSC secure configuration register 2, Address offset: 0x14 */ + __IO uint32_t SECCFGR3; /*!< TZSC secure configuration register 3, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ + __IO uint32_t PRIVCFGR1; /*!< TZSC privilege configuration register 1, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR2; /*!< TZSC privilege configuration register 2, Address offset: 0x24 */ + __IO uint32_t PRIVCFGR3; /*!< TZSC privilege configuration register 3, Address offset: 0x28 */ +} GTZC_TZSC_TypeDef; + +typedef struct +{ + __IO uint32_t CR; /*!< MPCBBx control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t CFGLOCK; /*!< MPCBBx lock register, Address offset: 0x10 */ + uint32_t RESERVED2[59]; /*!< Reserved2, Address offset: 0x14-0xFC */ + __IO uint32_t SECCFGR[4]; /*!< MPCBBx security configuration registers, Address offset: 0x100-0x10C */ + uint32_t RESERVED3[60]; /*!< Reserved3, Address offset: 0x110-0x1FC */ + __IO uint32_t PRIVCFGR[4]; /*!< MPCBBx privilege configuration registers, Address offset: 0x200-0x20C */ +} GTZC_MPCBB_TypeDef; + +typedef struct +{ + __IO uint32_t IER1; /*!< TZIC interrupt enable register 1, Address offset: 0x00 */ + __IO uint32_t IER2; /*!< TZIC interrupt enable register 2, Address offset: 0x04 */ + __IO uint32_t IER3; /*!< TZIC interrupt enable register 3, Address offset: 0x08 */ + __IO uint32_t IER4; /*!< TZIC interrupt enable register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< TZIC status register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< TZIC status register 2, Address offset: 0x14 */ + __IO uint32_t SR3; /*!< TZIC status register 3, Address offset: 0x18 */ + __IO uint32_t SR4; /*!< TZIC status register 4, Address offset: 0x1C */ + __IO uint32_t FCR1; /*!< TZIC flag clear register 1, Address offset: 0x20 */ + __IO uint32_t FCR2; /*!< TZIC flag clear register 2, Address offset: 0x24 */ + __IO uint32_t FCR3; /*!< TZIC flag clear register 3, Address offset: 0x28 */ + __IO uint32_t FCR4; /*!< TZIC flag clear register 3, Address offset: 0x2C */ +} GTZC_TZIC_TypeDef; + +/** + * @brief HASH + */ +typedef struct +{ + __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ + __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ + __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ + __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ + __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ + __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ + uint32_t RESERVED0[52]; /*!< Reserved, Address offset: 0x28-0xF4 */ + __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */ +} HASH_TypeDef; + +/** + * @brief HASH_DIGEST + */ +typedef struct +{ + __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */ +} HASH_DIGEST_TypeDef; + +/** + * @brief HW Semaphore HSEM + */ +typedef struct +{ + __IO uint32_t R[16]; /*!< HSEM 2-step write lock and read back registers, Address offset: 00h-3Ch */ + uint32_t Reserved1[16]; /*!< Reserved Address offset: 40h-7Ch */ + __IO uint32_t RLR[16]; /*!< HSEM 1-step read lock registers, Address offset: 80h-BCh */ + uint32_t Reserved2[16]; /*!< Reserved Address offset: C0h-FCh */ + __IO uint32_t IER; /*!< HSEM interrupt enable register, Address offset: 100h */ + __IO uint32_t ICR; /*!< HSEM interrupt clear register, Address offset: 104h */ + __IO uint32_t ISR; /*!< HSEM interrupt status register, Address offset: 108h */ + __IO uint32_t MISR; /*!< HSEM masked interrupt status register, Address offset: 10Ch */ + uint32_t Reserved3[28]; /*!< Reserved Address offset: 110h-17Ch */ + __IO uint32_t SIER; /*!< HSEM secure interrupt enable register, Address offset: 180h */ + __IO uint32_t SICR; /*!< HSEM secure interrupt clear register, Address offset: 184h */ + __IO uint32_t SISR; /*!< HSEM secure interrupt status register, Address offset: 188h */ + __IO uint32_t SMISR; /*!< HSEM secure masked interrupt status register, Address offset: 18Ch */ + uint32_t Reserved4[28]; /*!< Reserved Address offset: 190h-1FCh */ + __IO uint32_t SECCFGR; /*!< HSEM security configuration register, Address offset: 200h */ + uint32_t Reserved5[3]; /*!< Reserved Address offset: 204h-20Ch */ + __IO uint32_t PRIVCFGR; /*!< HSEM privilege configuration register, Address offset: 210h */ + uint32_t Reserved6[7]; /*!< Reserved Address offset: 214h-22Ch */ + __IO uint32_t CR; /*!< HSEM Semaphore clear register, Address offset: 230h */ + __IO uint32_t KEYR; /*!< HSEM Semaphore clear key register, Address offset: 234h */ +} HSEM_TypeDef; + +typedef struct +{ + __IO uint32_t IER; /*!< HSEM interrupt enable register, Address offset: 0h */ + __IO uint32_t ICR; /*!< HSEM interrupt clear register, Address offset: 4h */ + __IO uint32_t ISR; /*!< HSEM interrupt status register, Address offset: 8h */ + __IO uint32_t MISR; /*!< HSEM masked interrupt status register, Address offset: Ch */ + uint32_t Reserved3[28]; /*!< Reserved Address offset: 10h-7Ch */ + __IO uint32_t SIER; /*!< HSEM secure interrupt enable register, Address offset: 80h */ + __IO uint32_t SICR; /*!< HSEM secure interrupt clear register, Address offset: 84h */ + __IO uint32_t SISR; /*!< HSEM secure interrupt status register, Address offset: 88h */ + __IO uint32_t SMISR; /*!< HSEM secure masked interrupt status register, Address offset: 8Ch */ +} HSEM_Common_TypeDef; + +/** + * @brief Instruction Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< ICACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< ICACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< ICACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< ICACHE Flag clear register, Address offset: 0x0C */ + __IO uint32_t HMONR; /*!< ICACHE hit monitor register, Address offset: 0x10 */ + __IO uint32_t MMONR; /*!< ICACHE miss monitor register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t CRR0; /*!< ICACHE region 0 configuration register, Address offset: 0x20 */ + __IO uint32_t CRR1; /*!< ICACHE region 1 configuration register, Address offset: 0x24 */ + __IO uint32_t CRR2; /*!< ICACHE region 2 configuration register, Address offset: 0x28 */ + __IO uint32_t CRR3; /*!< ICACHE region 3 configuration register, Address offset: 0x2C */ +} ICACHE_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ + __IO uint32_t AUTOCR; /*!< I2C Autonomous mode control register, Address offset: 0x2C */ +} I2C_TypeDef; + +/** + * @brief IWDG + */ +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ + __IO uint32_t EWCR; /*!< IWDG Early Wakeup register, Address offset: 0x14 */ +} IWDG_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t DIER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CCR1; /*!< LPTIM Capture/Compare register 1, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ + __IO uint32_t RCR; /*!< LPTIM Repetition register, Address offset: 0x28 */ + __IO uint32_t CCMR1; /*!< LPTIM Capture/Compare mode register, Address offset: 0x2C */ + __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x30 */ + __IO uint32_t CCR2; /*!< LPTIM Capture/Compare register 2, Address offset: 0x34 */ +} LPTIM_TypeDef; + +/** + * @brief PKA + */ +typedef struct +{ + __IO uint32_t CR; /*!< PKA control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< PKA status register, Address offset: 0x04 */ + __IO uint32_t CLRFR; /*!< PKA clear flag register, Address offset: 0x08 */ + uint32_t Reserved[253]; /*!< Reserved memory area Address offset: 0x0C -> 0x03FC */ + __IO uint32_t RAM[1334]; /*!< PKA RAM Address offset: 0x400 -> 0x18D4 */ +} PKA_TypeDef; + +/** + * @brief PTACONV + */ +typedef struct +{ + __IO uint32_t ACTCR; /*!< PTACONV active control register, Address offset: 0x00 */ + __IO uint32_t PRICR; /*!< PTACONV priority control register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< PTACONV control register, Address offset: 0x08 */ +} PTACONV_TypeDef; + +/** + * @brief Power Control + */ +typedef struct +{ + __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */ + __IO uint32_t VOSR; /*!< PWR voltage scaling register, Address offset: 0x0C */ + __IO uint32_t SVMCR; /*!< PWR supply voltage monitoring control register, Address offset: 0x10 */ + __IO uint32_t WUCR1; /*!< PWR wakeup control register 1, Address offset: 0x14 */ + __IO uint32_t WUCR2; /*!< PWR wakeup control register 2, Address offset: 0x18 */ + __IO uint32_t WUCR3; /*!< PWR wakeup control register 3, Address offset: 0x1C */ + __IO uint32_t RESERVED0[2]; /*!< Reserved, Address offset: 0x20 -- 0x24 */ + __IO uint32_t DBPR; /*!< PWR disable backup domain register, Address offset: 0x28 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< PWR Security configuration register, Address offset: 0x30 */ + __IO uint32_t PRIVCFGR; /*!< PWR privilege control register, Address offset: 0x34 */ + __IO uint32_t SR; /*!< PWR status register, Address offset: 0x38 */ + __IO uint32_t SVMSR; /*!< PWR supply voltage monitoring status register, Address offset: 0x3C */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x40 */ + __IO uint32_t WUSR; /*!< PWR wakeup status register, Address offset: 0x44 */ + __IO uint32_t WUSCR; /*!< PWR wakeup status clear register, Address offset: 0x48 */ + __IO uint32_t APCR; /*!< PWR apply pull configuration register, Address offset: 0x4C */ + __IO uint32_t IORETENRA; /*!< PWR Port A IO retention in Standby register, Address offset: 0x50 */ + __IO uint32_t IORETRA; /*!< PWR Port A IO retention status in Standby register, Address offset: 0x54 */ + __IO uint32_t IORETENRB; /*!< PWR Port B IO retention in Standby register, Address offset: 0x58 */ + __IO uint32_t IORETRB; /*!< PWR Port B IO retention status in Standby register, Address offset: 0x5C */ + __IO uint32_t IORETENRC; /*!< PWR Port C IO retention in Standby register, Address offset: 0x60 */ + __IO uint32_t IORETRC; /*!< PWR Port C IO retention status in Standby register, Address offset: 0x64 */ + uint32_t RESERVED3[8]; /*!< Reserved, Address offset: 0x68 -- 0x84 */ + __IO uint32_t IORETENRH; /*!< PWR Port H IO retention in Standby register, Address offset: 0x88 */ + __IO uint32_t IORETRH; /*!< PWR Port H IO retention status in Standby register, Address offset: 0x8C */ + uint32_t RESERVED4[28]; /*!< Reserved, Address offset: 0x90 -- 0xFC */ + __IO uint32_t RADIOSCR; /*!< PWR 2.4 GHZ radio status and control register, Address offset: 0x100 */ +} PWR_TypeDef; + +/** + * @brief SRAMs configuration controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< Control Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< Interrupt enable register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< Interrupt status register, Address offset: 0x08 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x0C */ + __IO uint32_t PEAR; /*!< Parity error address register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< Interrupt clear register, Address offset: 0x14 */ + __IO uint32_t WPR1; /*!< Write protection register 1, Address offset: 0x18 */ + __IO uint32_t WPR2; /*!< Write protection register 2, Address offset: 0x1C */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x20 -- 0x24 */ + __IO uint32_t ERKEYR; /*!< Erase key register, Address offset: 0x28 */ +}RAMCFG_TypeDef; + +/** + * @brief Reset and Clock Control + */ +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register Address offset: 0x000 */ + uint32_t RESERVED0[3]; /*!< Reserved 0x004 -- 0x00C */ + __IO uint32_t ICSCR3; /*!< RCC internal clock sources calibration register 3 Address offset: 0x010 */ + uint32_t RESERVED1[2]; /*!< Reserved 0x014 -- 0x018 */ + __IO uint32_t CFGR1; /*!< RCC clock configuration register 1 Address offset: 0x01C */ + __IO uint32_t CFGR2; /*!< RCC clock configuration register 2 Address offset: 0x020 */ + __IO uint32_t CFGR3; /*!< RCC clock configuration register 3 Address offset: 0x024 */ + __IO uint32_t PLL1CFGR; /*!< PLL1 Configuration Register Address offset: 0x028 */ + uint32_t RESERVED2[2]; /*!< Reserved 0x02C -- 0x030 */ + __IO uint32_t PLL1DIVR; /*!< PLL1 Dividers Configuration Register Address offset: 0x034 */ + __IO uint32_t PLL1FRACR; /*!< PLL1 Fractional Divider Configuration Register Address offset: 0x038 */ + uint32_t RESERVED3[5]; /*!< Reserved 0x03C -- 0x04C */ + __IO uint32_t CIER; /*!< Clock Interrupt Enable Register Address offset: 0x050 */ + __IO uint32_t CIFR; /*!< Clock Interrupt Flag Register Address offset: 0x054 */ + __IO uint32_t CICR; /*!< Clock Interrupt Clear Register Address offset: 0x058 */ + uint32_t RESERVED4; /*!< Reserved Address offset: 0x05C */ + __IO uint32_t AHB1RSTR; /*!< AHB1 Peripherals Reset Register Address offset: 0x060 */ + __IO uint32_t AHB2RSTR; /*!< AHB2 Peripherals Reset Register Address offset: 0x064 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x068 */ + __IO uint32_t AHB4RSTR; /*!< AHB4 Peripherals Reset Register Address offset: 0x06C */ + __IO uint32_t AHB5RSTR; /*!< AHB5 Peripherals Reset Register Address offset: 0x070 */ + __IO uint32_t APB1RSTR1; /*!< APB1 Peripherals Reset Low Register Address offset: 0x074 */ + __IO uint32_t APB1RSTR2; /*!< APB1 Peripherals Reset High Register Address offset: 0x078 */ + __IO uint32_t APB2RSTR; /*!< APB2 Peripherals Reset Register Address offset: 0x07C */ + __IO uint32_t APB7RSTR; /*!< APB7 Peripherals Reset Register Address offset: 0x080 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x084 */ + __IO uint32_t AHB1ENR; /*!< AHB1 Peripherals Clock Enable Register Address offset: 0x088 */ + __IO uint32_t AHB2ENR; /*!< AHB2 Peripherals Clock Enable Register Address offset: 0x08C */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x090 */ + __IO uint32_t AHB4ENR; /*!< AHB4 Peripherals Clock Enable Register Address offset: 0x094 */ + __IO uint32_t AHB5ENR; /*!< AHB5 Peripherals Clock Enable Register Address offset: 0x098 */ + __IO uint32_t APB1ENR1; /*!< APB1 Peripherals Clock Enable Low Register Address offset: 0x09C */ + __IO uint32_t APB1ENR2; /*!< APB1 Peripherals Clock Enable High Register Address offset: 0x0A0 */ + __IO uint32_t APB2ENR; /*!< APB2 Peripherals Clock Enable Register Address offset: 0x0A4 */ + __IO uint32_t APB7ENR; /*!< APB7 Peripherals Clock Enable Register Address offset: 0x0A8 */ + uint32_t RESERVED8; /*!< Reserved Address offset: 0x0AC */ + __IO uint32_t AHB1SMENR; /*!< AHB1 Peripherals Clock Low Power Enable Register Address offset: 0x0B0 */ + __IO uint32_t AHB2SMENR; /*!< AHB2 Peripherals Clock Low Power Enable Register Address offset: 0x0B4 */ + uint32_t RESERVED9; /*!< Reserved Address offset: 0x0B8 */ + __IO uint32_t AHB4SMENR; /*!< AHB4 Peripherals Clock Low Power Enable Register Address offset: 0x0BC */ + __IO uint32_t AHB5SMENR; /*!< AHB5 Peripherals Clock Low Power Enable Register Address offset: 0x0C0 */ + __IO uint32_t APB1SMENR1; /*!< APB1 Peripherals Clock Low Power Enable Low Register Address offset: 0x0C4 */ + __IO uint32_t APB1SMENR2; /*!< APB1 Peripherals Clock Low Power Enable High Register Address offset: 0x0C8 */ + __IO uint32_t APB2SMENR; /*!< APB2 Peripherals Clock Low Power Enable Register Address offset: 0x0CC */ + __IO uint32_t APB7SMENR; /*!< APB7 Peripherals Clock Low Power Enable Register Address offset: 0x0D0 */ + uint32_t RESERVED10[3]; /*!< Reserved 0x0D4 -- 0x0DC */ + __IO uint32_t CCIPR1; /*!< IPs Clocks Configuration Register 1 Address offset: 0x0E0 */ + __IO uint32_t CCIPR2; /*!< IPs Clocks Configuration Register 2 Address offset: 0x0E4 */ + __IO uint32_t CCIPR3; /*!< IPs Clocks Configuration Register 3 Address offset: 0x0E8 */ + uint32_t RESERVED11; /*!< Reserved, Address offset: 0x0EC */ + __IO uint32_t BDCR1; /*!< Backup Domain Control Register 1 Address offset: 0x0F0 */ + __IO uint32_t CSR; /*!< V33 Clock Control & Status Register Address offset: 0x0F4 */ + __IO uint32_t BDCR2; /*!< Backup Domain Control Register 2 Address offset: 0x0F8 */ + uint32_t RESERVED12[5]; /*!< Reserved 0x0FC -- 0x010C */ + __IO uint32_t SECCFGR; /*!< RCC secure configuration register Address offset: 0x110 */ + __IO uint32_t PRIVCFGR; /*!< RCC privilege configuration register Address offset: 0x114 */ +#if !defined (STM32WBAXX_SI_CUT1_0) + uint32_t RESERVED13[42]; /*!< Reserved 0x118 -- 0x1BC */ + __IO uint32_t ASCR; /*!< RCC privilege configuration register Address offset: 0x1C0 */ + __IO uint32_t ASIER; /*!< RCC privilege configuration register Address offset: 0x1C4 */ + __IO uint32_t ASSR; /*!< RCC privilege configuration register Address offset: 0x1C8 */ + __IO uint32_t ASCNTR; /*!< RCC privilege configuration register Address offset: 0x1CC */ + __IO uint32_t ASARR; /*!< RCC privilege configuration register Address offset: 0x1D0 */ + __IO uint32_t ASCAR; /*!< RCC privilege configuration register Address offset: 0x1D4 */ + __IO uint32_t ASCOR; /*!< RCC privilege configuration register Address offset: 0x1D8 */ + uint32_t RESERVED14[9]; /*!< Reserved 0x1DC -- 0x1FC */ +#else + uint32_t RESERVED13[58]; /*!< Reserved 0x118 -- 0x1FC */ +#endif + __IO uint32_t CFGR4; /*!< RCC clock configuration register 4 Address offset: 0x200 */ + uint32_t RESERVED15; /*!< Reserved Address offset: 0x204 */ + __IO uint32_t RADIOENR; /*!< RCC RADIO peripheral clock enable register Address offset: 0x208 */ + uint32_t RESERVED16; /*!< Reserved Address offset: 0x20C */ + __IO uint32_t ECSCR1; /*!< RCC external clock sources calibration register 1 Address offset: 0x210 */ +} RCC_TypeDef; + +/** + * @brief RNG + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + uint32_t RESERVED; + __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ +} RNG_TypeDef; + +/* +* @brief RTC Specific device feature definitions +*/ +#define RTC_BKP_NB 32U +#define RTC_BACKUP_NB RTC_BKP_NB + +#define RTC_TAMP_NB 6U + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + __IO uint32_t PRIVCFGR; /*!< RTC privilege mode control register, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< RTC secure mode control register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x3C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */ + uint32_t RESERVED3[4];/*!< Reserved, Address offset: 0x58 */ + __IO uint32_t ALRABINR; /*!< RTC alarm A binary mode register, Address offset: 0x70 */ + __IO uint32_t ALRBBINR; /*!< RTC alarm B binary mode register, Address offset: 0x74 */ +} RTC_TypeDef; + +/** + * @brief Serial Audio Interface + */ +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ + uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ + __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ + __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief SPI + */ +typedef struct +{ + __IO uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */ + __IO uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */ + __IO uint32_t IER; /*!< SPI Interrupt Enable register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x14 */ + __IO uint32_t IFCR; /*!< SPI Interrupt/Status Flags Clear register, Address offset: 0x18 */ + __IO uint32_t AUTOCR; /*!< SPI Autonomous Mode Control register, Address offset: 0x1C */ + __IO uint32_t TXDR; /*!< SPI Transmit data register, Address offset: 0x20 */ + uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C */ + __IO uint32_t RXDR; /*!< SPI/I2S data register, Address offset: 0x30 */ + uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */ + __IO uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */ + __IO uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */ + __IO uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */ + __IO uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */ +} SPI_TypeDef; + +/** + * @brief System configuration controller + */ +typedef struct +{ + __IO uint32_t SECCFGR; /*!< SYSCFG secure configuration register, Address offset: 0x00 */ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ + __IO uint32_t FPUIMR; /*!< SYSCFG FPU interrupt mask register, Address offset: 0x08 */ + __IO uint32_t CNSLCKR; /*!< SYSCFG CPU non-secure lock register, Address offset: 0x0C */ + __IO uint32_t CSLCKR; /*!< SYSCFG CPU secure lock register, Address offset: 0x10 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x14 */ + __IO uint32_t MESR; /*!< SYSCFG Memory Erase Status register, Address offset: 0x18 */ + __IO uint32_t CCCSR; /*!< SYSCFG Conpensaion Cell Control&Status register, Address offset: 0x1C */ + __IO uint32_t CCVR; /*!< SYSCFG Conpensaion Cell value register, Address offset: 0x20 */ + __IO uint32_t CCCR; /*!< SYSCFG Conpensaion Cell Code register, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x28 */ + __IO uint32_t RSSCMDR; /*!< SYSCFG RSS command mode register, Address offset: 0x2C */ +} SYSCFG_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< TAMP configuration register 3, Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ + __IO uint32_t ATCR1; /*!< TAMP filter control register 1 Address offset: 0x10 */ + __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ + __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ + __IO uint32_t ATCR2; /*!< TAMP filter control register 2, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< TAMP secure mode control register, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR; /*!< TAMP privilege mode control register, Address offset: 0x24 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x28 */ + __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */ + __IO uint32_t SMISR; /*!< TAMP secure masked interrupt status register, Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ + __IO uint32_t COUNT1R; /*!< TAMP monotonic counter 1 register, Address offset: 0x40 */ + uint32_t RESERVED2[4];/*!< Reserved, Address offset: 0x44 -- 0x50 */ + __IO uint32_t RPCFGR; /*!< TAMP resources protection configuration register, Address offset: 0x54 */ + uint32_t RESERVED3[42];/*!< Reserved, Address offset: 0x58 -- 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ + __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ + __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ + __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ + __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ + __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ + __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ + __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ + __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ + __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ + __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ + __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ + __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ +} TAMP_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ + __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ + __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + __IO uint32_t OR; /*!< TIM option register, Address offset: 0x68 */ + uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x68-0x3D8 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + +/** + * @brief TSC + */ +typedef struct +{ + __IO uint32_t CR; /*!< TSC Control register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< TSC Interrupt Enable register, Address offset: 0x04 */ + __IO uint32_t ICR; /*!< TSC Interrupt Control register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< TSC Interrupt Status register, Address offset: 0x0C */ + __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x2C */ + __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */ + __IO uint32_t IOGXCR[6]; /*!< TSC I/O group x counter register, Address offset: 0x34-48 */ +} TSC_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ + __IO uint32_t AUTOCR; /*!< USART Autonomous mode control register Address offset: 0x30 */ +} USART_TypeDef; + +/** + * @brief WWDG + */ +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/*@}*/ /* end of group STM32WBA54xx_Peripherals */ + +/* -------- End of section using anonymous unions and disabling warnings -------- */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ +/** @addtogroup STM32WBAxx_Peripheral_peripheralAddr + * @{ + */ + +/* Flash, Peripheral and internal SRAMs base addresses - Non secure */ +#define FLASH_BASE_NS 0x08000000UL /*!< FLASH non-secure base address */ +#define SYSTEM_FLASH_BASE_NS 0x0BF88000UL /*!< System FLASH non-secure base address */ +#define SRAM1_BASE_NS 0x20000000UL /*!< SRAM1 non-secure base address */ +#define SRAM2_BASE_NS 0x20010000UL /*!< SRAM2 non-secure base address */ +#define SRAM6_BASE_NS 0x48028000UL /*!< 2.4 GHz RADIO TXRX SRAM non-secure base address */ +#define SEQSRAM_BASE_NS 0x48021000UL /*!< SRAM Sequence / retention non-secure base address */ +#define PERIPH_BASE_NS 0x40000000UL /*!< Peripheral non-secure base address */ +#define DBGMCU_BASE 0xE0044000UL /*!< Debug MCU registers base address */ + +/*!< Memory sizes */ +/* Internal Flash size */ +#define FLASH_SIZE ((((*((uint16_t *)FLASHSIZE_BASE)) == 0xFFFFU)) ? 0x100000U : \ + ((((*((uint16_t *)FLASHSIZE_BASE)) == 0x0000U)) ? 0x100000U : \ + (((uint32_t)(*((uint16_t *)FLASHSIZE_BASE)) & (0xFFFFU)) << 10U))) + +/* Internal SRAMs size */ +#define SRAM1_SIZE 0x00010000UL /*!< SRAM1 = 64 Kbytes */ +#define SRAM2_SIZE 0x00010000UL /*!< SRAM2 = 64 Kbytes */ +#define SRAM6_SIZE 0x00004000UL /*!< 2.4 GHz RADIO TXRX SRAM 16 Kbytes */ +#define SEQSRAM_SIZE 0x00000200UL /*!< SRAM Sequence / retention 512 bytes */ + +/*!< OTP, Engineering bytes, Option bytes defines */ +#define FLASH_OTP_BASE (SYSTEM_FLASH_BASE_NS + 0x00008000UL) +#define FLASH_OTP_SIZE 0x00000200U /*!< 512 bytes OTP (one-time programmable) */ + +#define FLASH_ENGY_BASE (SYSTEM_FLASH_BASE_NS + 0x00008500UL) +#define PACKAGE_BASE (FLASH_ENGY_BASE) /*!< Package data register base address */ +#define UID_BASE (FLASH_ENGY_BASE + 0x00000200UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (FLASH_ENGY_BASE + 0x000002A0UL) /*!< Flash size data register base address */ +#define UID64_BASE (FLASH_ENGY_BASE + 0x00000500UL) /*!< 64-bit Unique device Identification */ + +/* Peripheral memory map - Non secure */ +#define APB1PERIPH_BASE_NS PERIPH_BASE_NS +#define APB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00010000UL) +#define AHB1PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00020000UL) +#define AHB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x02020000UL) +#define APB7PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06000000UL) +#define AHB4PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06020000UL) +#define AHB5PERIPH_BASE_NS (PERIPH_BASE_NS + 0x08020000UL) + +/*!< APB1 Non secure peripherals */ +#define TIM2_BASE_NS APB1PERIPH_BASE_NS +#define TIM3_BASE_NS (APB1PERIPH_BASE_NS + 0x0400UL) +#define WWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x2C00UL) +#define IWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x3000UL) +#define USART2_BASE_NS (APB1PERIPH_BASE_NS + 0x4400UL) +#define I2C1_BASE_NS (APB1PERIPH_BASE_NS + 0x5400UL) +#define LPTIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x9400UL) + +/*!< APB2 Non secure peripherals */ +#define TIM1_BASE_NS (APB2PERIPH_BASE_NS + 0x2C00UL) +#define SPI1_BASE_NS (APB2PERIPH_BASE_NS + 0x3000UL) +#define USART1_BASE_NS (APB2PERIPH_BASE_NS + 0x3800UL) +#define TIM16_BASE_NS (APB2PERIPH_BASE_NS + 0x4400UL) +#define TIM17_BASE_NS (APB2PERIPH_BASE_NS + 0x4800UL) +#define SAI1_BASE_NS (APB2PERIPH_BASE_NS + 0x5400UL) +#define SAI1_Block_A_BASE_NS (SAI1_BASE_NS + 0x004UL) +#define SAI1_Block_B_BASE_NS (SAI1_BASE_NS + 0x024UL) + +/*!< AHB1 Non secure peripherals */ +#define GPDMA1_BASE_NS AHB1PERIPH_BASE_NS +#define FLASH_R_BASE_NS (AHB1PERIPH_BASE_NS + 0x02000UL) +#define CRC_BASE_NS (AHB1PERIPH_BASE_NS + 0x03000UL) +#define TSC_BASE_NS (AHB1PERIPH_BASE_NS + 0x04000UL) +#define RAMCFG_BASE_NS (AHB1PERIPH_BASE_NS + 0x06000UL) +#define ICACHE_BASE_NS (AHB1PERIPH_BASE_NS + 0x10400UL) +#define GTZC_TZSC_BASE_NS (AHB1PERIPH_BASE_NS + 0x12400UL) +#define GTZC_MPCBB1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12C00UL) +#define GTZC_MPCBB2_BASE_NS (AHB1PERIPH_BASE_NS + 0x13000UL) +#define GTZC_MPCBB6_BASE_NS (AHB1PERIPH_BASE_NS + 0x14000UL) + +#define GPDMA1_Channel0_BASE_NS (GPDMA1_BASE_NS + 0x0050UL) +#define GPDMA1_Channel1_BASE_NS (GPDMA1_BASE_NS + 0x00D0UL) +#define GPDMA1_Channel2_BASE_NS (GPDMA1_BASE_NS + 0x0150UL) +#define GPDMA1_Channel3_BASE_NS (GPDMA1_BASE_NS + 0x01D0UL) +#define GPDMA1_Channel4_BASE_NS (GPDMA1_BASE_NS + 0x0250UL) +#define GPDMA1_Channel5_BASE_NS (GPDMA1_BASE_NS + 0x02D0UL) +#define GPDMA1_Channel6_BASE_NS (GPDMA1_BASE_NS + 0x0350UL) +#define GPDMA1_Channel7_BASE_NS (GPDMA1_BASE_NS + 0x03D0UL) + +#define RAMCFG_SRAM1_BASE_NS (RAMCFG_BASE_NS) +#define RAMCFG_SRAM2_BASE_NS (RAMCFG_BASE_NS + 0x0040UL) +#define RAMCFG_SRAM6_BASE_NS (RAMCFG_BASE_NS + 0x0140UL) + +/*!< AHB2 Non secure peripherals */ +#define GPIOA_BASE_NS AHB2PERIPH_BASE_NS +#define GPIOB_BASE_NS (AHB2PERIPH_BASE_NS + 0x00400UL) +#define GPIOC_BASE_NS (AHB2PERIPH_BASE_NS + 0x00800UL) +#define GPIOH_BASE_NS (AHB2PERIPH_BASE_NS + 0x01C00UL) +#define AES_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0000UL) +#define HASH_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0400UL) +#define HASH_DIGEST_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0710UL) +#define RNG_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0800UL) +#define SAES_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0C00UL) +#define HSEM_BASE_NS (AHB2PERIPH_BASE_NS + 0xA1C00UL) +#define PKA_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2000UL) +#define PKA_RAM_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2400UL) + +/*!< APB7 Non secure peripherals */ +#define SYSCFG_BASE_NS (APB7PERIPH_BASE_NS + 0x0400UL) +#define SPI3_BASE_NS (APB7PERIPH_BASE_NS + 0x2000UL) +#define LPUART1_BASE_NS (APB7PERIPH_BASE_NS + 0x2400UL) +#define I2C3_BASE_NS (APB7PERIPH_BASE_NS + 0x2800UL) +#define LPTIM1_BASE_NS (APB7PERIPH_BASE_NS + 0x4400UL) +#define COMP12_BASE_NS (APB7PERIPH_BASE_NS + 0x5400UL) +#define COMP1_BASE_NS (COMP12_BASE_NS) +#define COMP2_BASE_NS (COMP12_BASE_NS + 0x04UL) +#define RTC_BASE_NS (APB7PERIPH_BASE_NS + 0x7800UL) +#define TAMP_BASE_NS (APB7PERIPH_BASE_NS + 0x7C00UL) + +/*!< AHB4 Non secure peripherals */ +#define PWR_BASE_NS (AHB4PERIPH_BASE_NS + 0x0800UL) +#define RCC_BASE_NS (AHB4PERIPH_BASE_NS + 0x0C00UL) +#define ADC4_BASE_NS (AHB4PERIPH_BASE_NS + 0x1000UL) +#define ADC4_COMMON_BASE_NS (AHB4PERIPH_BASE_NS + 0x1308UL) +#define EXTI_BASE_NS (AHB4PERIPH_BASE_NS + 0x2000UL) + +/*!< AHB5 Non secure peripherals */ +#define RADIO_BASE_NS AHB5PERIPH_BASE_NS +#define PTACONV_BASE_NS (AHB5PERIPH_BASE_NS + 0x18000UL) + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/* Flash, Peripheral and internal SRAMs base addresses - Secure */ +#define FLASH_BASE_S 0x0C000000UL /*!< FLASH secure base address */ +#define SYSTEM_FLASH_BASE_S 0x0FF80000UL /*!< System FLASH non-secure base address */ +#define SRAM1_BASE_S 0x30000000UL /*!< SRAM1 secure base address */ +#define SRAM2_BASE_S 0x30010000UL /*!< SRAM2 secure base address */ +#define SRAM6_BASE_S 0x58028000UL /*!< 2.4 GHz RADIO TXRX SRAM secure base address */ +#define SEQSRAM_BASE_S 0x58021000UL /*!< SRAM Sequence / retention non-secure base address */ +#define PERIPH_BASE_S 0x50000000UL /*!< Peripheral secure base address */ + +/* Peripheral memory map - Secure */ +#define APB1PERIPH_BASE_S PERIPH_BASE_S +#define APB2PERIPH_BASE_S (PERIPH_BASE_S + 0x00010000UL) +#define AHB1PERIPH_BASE_S (PERIPH_BASE_S + 0x00020000UL) +#define AHB2PERIPH_BASE_S (PERIPH_BASE_S + 0x02020000UL) +#define APB7PERIPH_BASE_S (PERIPH_BASE_S + 0x06000000UL) +#define AHB4PERIPH_BASE_S (PERIPH_BASE_S + 0x06020000UL) +#define AHB5PERIPH_BASE_S (PERIPH_BASE_S + 0x08020000UL) + +/*!< APB1 Secure peripherals */ +#define TIM2_BASE_S APB1PERIPH_BASE_S +#define TIM3_BASE_S (APB1PERIPH_BASE_S + 0x0400UL) +#define WWDG_BASE_S (APB1PERIPH_BASE_S + 0x2C00UL) +#define IWDG_BASE_S (APB1PERIPH_BASE_S + 0x3000UL) +#define USART2_BASE_S (APB1PERIPH_BASE_S + 0x4400UL) +#define I2C1_BASE_S (APB1PERIPH_BASE_S + 0x5400UL) +#define LPTIM2_BASE_S (APB1PERIPH_BASE_S + 0x9400UL) + +/*!< APB2 Secure peripherals */ +#define TIM1_BASE_S (APB2PERIPH_BASE_S + 0x2C00UL) +#define SPI1_BASE_S (APB2PERIPH_BASE_S + 0x3000UL) +#define USART1_BASE_S (APB2PERIPH_BASE_S + 0x3800UL) +#define TIM16_BASE_S (APB2PERIPH_BASE_S + 0x4400UL) +#define TIM17_BASE_S (APB2PERIPH_BASE_S + 0x4800UL) +#define SAI1_BASE_S (APB2PERIPH_BASE_S + 0x5400UL) +#define SAI1_Block_A_BASE_S (SAI1_BASE_S + 0x004UL) +#define SAI1_Block_B_BASE_S (SAI1_BASE_S + 0x024UL) + +/*!< AHB1 Secure peripherals */ +#define GPDMA1_BASE_S AHB1PERIPH_BASE_S +#define FLASH_R_BASE_S (AHB1PERIPH_BASE_S + 0x02000UL) +#define CRC_BASE_S (AHB1PERIPH_BASE_S + 0x03000UL) +#define TSC_BASE_S (AHB1PERIPH_BASE_S + 0x04000UL) +#define RAMCFG_BASE_S (AHB1PERIPH_BASE_S + 0x06000UL) +#define ICACHE_BASE_S (AHB1PERIPH_BASE_S + 0x10400UL) +#define GTZC_TZSC_BASE_S (AHB1PERIPH_BASE_S + 0x12400UL) +#define GTZC_TZIC_BASE_S (AHB1PERIPH_BASE_S + 0x12800UL) +#define GTZC_MPCBB1_BASE_S (AHB1PERIPH_BASE_S + 0x12C00UL) +#define GTZC_MPCBB2_BASE_S (AHB1PERIPH_BASE_S + 0x13000UL) +#define GTZC_MPCBB6_BASE_S (AHB1PERIPH_BASE_S + 0x14000UL) + +#define GPDMA1_Channel0_BASE_S (GPDMA1_BASE_S + 0x0050UL) +#define GPDMA1_Channel1_BASE_S (GPDMA1_BASE_S + 0x00D0UL) +#define GPDMA1_Channel2_BASE_S (GPDMA1_BASE_S + 0x0150UL) +#define GPDMA1_Channel3_BASE_S (GPDMA1_BASE_S + 0x01D0UL) +#define GPDMA1_Channel4_BASE_S (GPDMA1_BASE_S + 0x0250UL) +#define GPDMA1_Channel5_BASE_S (GPDMA1_BASE_S + 0x02D0UL) +#define GPDMA1_Channel6_BASE_S (GPDMA1_BASE_S + 0x0350UL) +#define GPDMA1_Channel7_BASE_S (GPDMA1_BASE_S + 0x03D0UL) + +#define RAMCFG_SRAM1_BASE_S (RAMCFG_BASE_S) +#define RAMCFG_SRAM2_BASE_S (RAMCFG_BASE_S + 0x0040UL) +#define RAMCFG_SRAM6_BASE_S (RAMCFG_BASE_S + 0x0140UL) + +/*!< AHB2 Secure peripherals */ +#define GPIOA_BASE_S AHB2PERIPH_BASE_S +#define GPIOB_BASE_S (AHB2PERIPH_BASE_S + 0x00400UL) +#define GPIOC_BASE_S (AHB2PERIPH_BASE_S + 0x00800UL) +#define GPIOH_BASE_S (AHB2PERIPH_BASE_S + 0x01C00UL) +#define AES_BASE_S (AHB2PERIPH_BASE_S + 0xA0000UL) +#define HASH_BASE_S (AHB2PERIPH_BASE_S + 0xA0400UL) +#define HASH_DIGEST_BASE_S (AHB2PERIPH_BASE_S + 0xA0710UL) +#define RNG_BASE_S (AHB2PERIPH_BASE_S + 0xA0800UL) +#define SAES_BASE_S (AHB2PERIPH_BASE_S + 0xA0C00UL) +#define HSEM_BASE_S (AHB2PERIPH_BASE_S + 0xA1C00UL) +#define PKA_BASE_S (AHB2PERIPH_BASE_S + 0xA2000UL) +#define PKA_RAM_BASE_S (AHB2PERIPH_BASE_S + 0xA2400UL) + +/*!< APB7 Secure peripherals */ +#define SYSCFG_BASE_S (APB7PERIPH_BASE_S + 0x0400UL) +#define SPI3_BASE_S (APB7PERIPH_BASE_S + 0x2000UL) +#define LPUART1_BASE_S (APB7PERIPH_BASE_S + 0x2400UL) +#define I2C3_BASE_S (APB7PERIPH_BASE_S + 0x2800UL) +#define LPTIM1_BASE_S (APB7PERIPH_BASE_S + 0x4400UL) +#define COMP12_BASE_S (APB7PERIPH_BASE_S + 0x5400UL) +#define COMP1_BASE_S (COMP12_BASE_S) +#define COMP2_BASE_S (COMP12_BASE_S + 0x04UL) +#define RTC_BASE_S (APB7PERIPH_BASE_S + 0x7800UL) +#define TAMP_BASE_S (APB7PERIPH_BASE_S + 0x7C00UL) + +/*!< AHB4 Secure peripherals */ +#define PWR_BASE_S (AHB4PERIPH_BASE_S + 0x0800UL) +#define RCC_BASE_S (AHB4PERIPH_BASE_S + 0x0C00UL) +#define ADC4_BASE_S (AHB4PERIPH_BASE_S + 0x1000UL) +#define ADC4_COMMON_BASE_S (AHB4PERIPH_BASE_S + 0x1308UL) +#define EXTI_BASE_S (AHB4PERIPH_BASE_S + 0x2000UL) + +/*!< AHB5 Secure peripherals */ +#define RADIO_BASE_S AHB5PERIPH_BASE_S +#define PTACONV_BASE_S (AHB5PERIPH_BASE_S + 0x18000UL) +#endif + +/************ RSSLIB SAU system Flash region definition constants *************/ +#define RSSLIB_SYS_FLASH_NS_PFUNC_START (SYSTEM_FLASH_BASE_NS + 0x00007E40UL) +#define RSSLIB_SYS_FLASH_NS_PFUNC_END (SYSTEM_FLASH_BASE_NS + 0x00007E6BUL) + +/************ RSSLIB function return constants ********************************/ +#define RSSLIB_ERROR 0xF5F5F5F5UL +#define RSSLIB_SUCCESS 0xEAEAEAEAUL + +/*!< RSSLIB pointer function structure address definition */ +#define RSSLIB_PFUNC_BASE RSSLIB_SYS_FLASH_NS_PFUNC_START +#define RSSLIB_PFUNC ((RSSLIB_pFunc_TypeDef *)RSSLIB_PFUNC_BASE) + +/*!< HDP Area constant definition */ +#define RSSLIB_HDP_AREA_Pos (0U) +#define RSSLIB_HDP_AREA_Msk (0x1UL << RSSLIB_HDP_AREA_Pos ) + +/** + * @brief Prototype of RSSLIB Close and exit HDP Function + * @detail This function close the requested hdp area passed in input + * parameter and jump to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param HdpArea notifies which hdp area to close, can be a combination of + * hdpa area 1 and hdp area 2 + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t ( *RSSLIB_S_CloseExitHDP_TypeDef)( uint32_t HdpArea, uint32_t VectorTableAddr ); + +/** + * @brief RSSLib non-secure callable function pointer structure + */ +typedef struct +{ + __IM uint32_t Reserved[8]; +}NSC_pFuncTypeDef; + +/** + * @brief RSSLib secure callable function pointer structure + */ +typedef struct +{ + __IM uint32_t Reserved2[2]; + __IM RSSLIB_S_CloseExitHDP_TypeDef CloseExitHDP; /*!< RSSLIB Bootloader Close and exit HDP Address offset: 0x28 */ +}S_pFuncTypeDef; + +/** + * @brief RSSLib function pointer structure + */ +typedef struct +{ + NSC_pFuncTypeDef NSC; + S_pFuncTypeDef S; +}RSSLIB_pFunc_TypeDef; + + +/** @} */ /* End of group STM32WBAxx_Peripheral_peripheralAddr */ +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ +/** @addtogroup STM32WBAxx_Peripheral_declaration + * @{ + */ +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +#define ADC4_NS ((ADC_TypeDef *) ADC4_BASE_NS) +#define ADC4_COMMON_NS ((ADC_Common_TypeDef *) ADC4_COMMON_BASE_NS) +#define AES_NS ((AES_TypeDef *) AES_BASE_NS) +#define COMP1_NS ((COMP_TypeDef *) COMP1_BASE_NS) +#define COMP2_NS ((COMP_TypeDef *) COMP2_BASE_NS) +#define COMP12_COMMON_NS ((COMP_Common_TypeDef *) COMP1_BASE_NS) +#define CRC_NS ((CRC_TypeDef *) CRC_BASE_NS) +#define EXTI_NS ((EXTI_TypeDef *) EXTI_BASE_NS) +#define FLASH_NS ((FLASH_TypeDef *) FLASH_R_BASE_NS) +#define GPDMA1_NS ((DMA_TypeDef *) GPDMA1_BASE_NS) +#define GPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_NS) +#define GPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_NS) +#define GPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_NS) +#define GPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_NS) +#define GPDMA1_Channel4_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_NS) +#define GPDMA1_Channel5_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_NS) +#define GPDMA1_Channel6_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_NS) +#define GPDMA1_Channel7_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_NS) +#define GPIOA_NS ((GPIO_TypeDef *) GPIOA_BASE_NS) +#define GPIOB_NS ((GPIO_TypeDef *) GPIOB_BASE_NS) +#define GPIOC_NS ((GPIO_TypeDef *) GPIOC_BASE_NS) +#define GPIOH_NS ((GPIO_TypeDef *) GPIOH_BASE_NS) +#define GTZC_MPCBB1_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_NS) +#define GTZC_MPCBB2_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_NS) +#define GTZC_MPCBB6_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB6_BASE_NS) +#define GTZC_TZSC_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC_BASE_NS) +#define HASH_NS ((HASH_TypeDef *) HASH_BASE_NS) +#define HASH_DIGEST_NS ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS) +#define HSEM_NS ((HSEM_TypeDef *) HSEM_BASE_NS) +#define HSEM_COMMON_NS ((HSEM_Common_TypeDef *) (HSEM_BASE_NS + 0x100U)) +#define I2C1_NS ((I2C_TypeDef *) I2C1_BASE_NS) +#define I2C3_NS ((I2C_TypeDef *) I2C3_BASE_NS) +#define ICACHE_NS ((ICACHE_TypeDef *) ICACHE_BASE_NS) +#define IWDG_NS ((IWDG_TypeDef *) IWDG_BASE_NS) +#define LPTIM1_NS ((LPTIM_TypeDef *) LPTIM1_BASE_NS) +#define LPTIM2_NS ((LPTIM_TypeDef *) LPTIM2_BASE_NS) +#define LPUART1_NS ((USART_TypeDef *) LPUART1_BASE_NS) +#define PKA_NS ((PKA_TypeDef *) PKA_BASE_NS) +#define PTACONV_NS ((PTACONV_TypeDef *) PTACONV_BASE_NS) +#define PWR_NS ((PWR_TypeDef *) PWR_BASE_NS) +#define RAMCFG_SRAM1_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_NS) +#define RAMCFG_SRAM2_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_NS) +#define RAMCFG_SRAM6_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM6_BASE_NS) +#define RCC_NS ((RCC_TypeDef *) RCC_BASE_NS) +#define RNG_NS ((RNG_TypeDef *) RNG_BASE_NS) +#define RTC_NS ((RTC_TypeDef *) RTC_BASE_NS) +#define SAES_NS ((AES_TypeDef *) SAES_BASE_NS) +#define SAI1_NS ((SAI_TypeDef *) SAI1_BASE_NS) +#define SAI1_Block_A_NS ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_NS) +#define SAI1_Block_B_NS ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_NS) +#define SPI1_NS ((SPI_TypeDef *) SPI1_BASE_NS) +#define SPI3_NS ((SPI_TypeDef *) SPI3_BASE_NS) +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_BASE_NS) +#define TAMP_NS ((TAMP_TypeDef *) TAMP_BASE_NS) +#define TIM1_NS ((TIM_TypeDef *) TIM1_BASE_NS) +#define TIM2_NS ((TIM_TypeDef *) TIM2_BASE_NS) +#define TIM3_NS ((TIM_TypeDef *) TIM3_BASE_NS) +#define TIM16_NS ((TIM_TypeDef *) TIM16_BASE_NS) +#define TIM17_NS ((TIM_TypeDef *) TIM17_BASE_NS) +#define TSC_NS ((TSC_TypeDef *) TSC_BASE_NS) +#define USART1_NS ((USART_TypeDef *) USART1_BASE_NS) +#define USART2_NS ((USART_TypeDef *) USART2_BASE_NS) +#define WWDG_NS ((WWDG_TypeDef *) WWDG_BASE_NS) + +/*!< Memory & Instance aliases and base addresses for Non-Secure/Secure peripherals */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define ADC4_S ((ADC_TypeDef *) ADC4_BASE_S) +#define ADC4_COMMON_S ((ADC_Common_TypeDef *) ADC4_COMMON_BASE_S) +#define AES_S ((AES_TypeDef *) AES_BASE_S) +#define COMP1_S ((COMP_TypeDef *) COMP1_BASE_S) +#define COMP2_S ((COMP_TypeDef *) COMP2_BASE_S) +#define COMP12_COMMON_S ((COMP_Common_TypeDef *) COMP1_BASE_S) +#define CRC_S ((CRC_TypeDef *) CRC_BASE_S) +#define EXTI_S ((EXTI_TypeDef *) EXTI_BASE_S) +#define FLASH_S ((FLASH_TypeDef *) FLASH_R_BASE_S) +#define GPDMA1_S ((DMA_TypeDef *) GPDMA1_BASE_S) +#define GPDMA1_Channel0_S ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_S) +#define GPDMA1_Channel1_S ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_S) +#define GPDMA1_Channel2_S ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_S) +#define GPDMA1_Channel3_S ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_S) +#define GPDMA1_Channel4_S ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_S) +#define GPDMA1_Channel5_S ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_S) +#define GPDMA1_Channel6_S ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_S) +#define GPDMA1_Channel7_S ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_S) +#define GPIOA_S ((GPIO_TypeDef *) GPIOA_BASE_S) +#define GPIOB_S ((GPIO_TypeDef *) GPIOB_BASE_S) +#define GPIOC_S ((GPIO_TypeDef *) GPIOC_BASE_S) +#define GPIOH_S ((GPIO_TypeDef *) GPIOH_BASE_S) +#define GTZC_MPCBB1_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_S) +#define GTZC_MPCBB2_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_S) +#define GTZC_MPCBB6_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB6_BASE_S) +#define GTZC_TZIC_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC_BASE_S) +#define GTZC_TZSC_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC_BASE_S) +#define HASH_S ((HASH_TypeDef *) HASH_BASE_S) +#define HASH_DIGEST_S ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S) +#define HSEM_S ((HSEM_TypeDef *) HSEM_BASE_S) +#define HSEM_COMMON_S ((HSEM_Common_TypeDef *) (HSEM_BASE_S + 0x100U)) +#define I2C1_S ((I2C_TypeDef *) I2C1_BASE_S) +#define I2C3_S ((I2C_TypeDef *) I2C3_BASE_S) +#define ICACHE_S ((ICACHE_TypeDef *) ICACHE_BASE_S) +#define IWDG_S ((IWDG_TypeDef *) IWDG_BASE_S) +#define LPTIM1_S ((LPTIM_TypeDef *) LPTIM1_BASE_S) +#define LPTIM2_S ((LPTIM_TypeDef *) LPTIM2_BASE_S) +#define LPUART1_S ((USART_TypeDef *) LPUART1_BASE_S) +#define PKA_S ((PKA_TypeDef *) PKA_BASE_S) +#define PTACONV_S ((PTACONV_TypeDef *) PTACONV_BASE_S) +#define PWR_S ((PWR_TypeDef *) PWR_BASE_S) +#define RAMCFG_SRAM1_S ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_S) +#define RAMCFG_SRAM2_S ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_S) +#define RAMCFG_SRAM6_S ((RAMCFG_TypeDef *) RAMCFG_SRAM6_BASE_S) +#define RCC_S ((RCC_TypeDef *) RCC_BASE_S) +#define RNG_S ((RNG_TypeDef *) RNG_BASE_S) +#define RTC_S ((RTC_TypeDef *) RTC_BASE_S) +#define SAES_S ((AES_TypeDef *) SAES_BASE_S) +#define SAI1_S ((SAI_TypeDef *) SAI1_BASE_S) +#define SAI1_Block_A_S ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_S) +#define SAI1_Block_B_S ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_S) +#define SPI1_S ((SPI_TypeDef *) SPI1_BASE_S) +#define SPI3_S ((SPI_TypeDef *) SPI3_BASE_S) +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE_S) +#define TAMP_S ((TAMP_TypeDef *) TAMP_BASE_S) +#define TIM1_S ((TIM_TypeDef *) TIM1_BASE_S) +#define TIM2_S ((TIM_TypeDef *) TIM2_BASE_S) +#define TIM3_S ((TIM_TypeDef *) TIM3_BASE_S) +#define TIM16_S ((TIM_TypeDef *) TIM16_BASE_S) +#define TIM17_S ((TIM_TypeDef *) TIM17_BASE_S) +#define TSC_S ((TSC_TypeDef *) TSC_BASE_S) +#define USART1_S ((USART_TypeDef *) USART1_BASE_S) +#define USART2_S ((USART_TypeDef *) USART2_BASE_S) +#define WWDG_S ((WWDG_TypeDef *) WWDG_BASE_S) + + +/*!< Memory base addresses for Secure peripherals */ +#define FLASH_BASE FLASH_BASE_S +#define SRAM1_BASE SRAM1_BASE_S +#define SRAM2_BASE SRAM2_BASE_S +#define SRAM6_BASE SRAM6_BASE_S +#define SEQSRAM_BASE SEQSRAM_BASE_S + +/*!< Instance aliases and base addresses for Secure peripherals */ +#define ADC4 ADC4_S +#define ADC4_BASE ADC4_BASE_S +#define ADC4_COMMON ADC4_COMMON_S +#define ADC4_COMMON_BASE ADC4_COMMON_BASE_S +#define AES AES_S +#define AES_BASE AES_BASE_S +#define COMP1 COMP1_S +#define COMP1_BASE COMP1_BASE_S +#define COMP2 COMP2_S +#define COMP2_BASE COMP2_BASE_S +#define COMP12_COMMON COMP12_COMMON_S +#define CRC CRC_S +#define CRC_BASE CRC_BASE_S +#define EXTI EXTI_S +#define EXTI_BASE EXTI_BASE_S +#define FLASH FLASH_S +#define FLASH_R_BASE FLASH_R_BASE_S +#define GPDMA1 GPDMA1_S +#define GPDMA1_BASE GPDMA1_BASE_S +#define GPDMA1_Channel0 GPDMA1_Channel0_S +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_S +#define GPDMA1_Channel1 GPDMA1_Channel1_S +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_S +#define GPDMA1_Channel2 GPDMA1_Channel2_S +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_S +#define GPDMA1_Channel3 GPDMA1_Channel3_S +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_S +#define GPDMA1_Channel4 GPDMA1_Channel4_S +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_S +#define GPDMA1_Channel5 GPDMA1_Channel5_S +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_S +#define GPDMA1_Channel6 GPDMA1_Channel6_S +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_S +#define GPDMA1_Channel7 GPDMA1_Channel7_S +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_S +#define GPIOA GPIOA_S +#define GPIOA_BASE GPIOA_BASE_S +#define GPIOB GPIOB_S +#define GPIOB_BASE GPIOB_BASE_S +#define GPIOC GPIOC_S +#define GPIOC_BASE GPIOC_BASE_S +#define GPIOH GPIOH_S +#define GPIOH_BASE GPIOH_BASE_S +#define GTZC_MPCBB1 GTZC_MPCBB1_S +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_S +#define GTZC_MPCBB2 GTZC_MPCBB2_S +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_S +#define GTZC_MPCBB6 GTZC_MPCBB6_S +#define GTZC_MPCBB6_BASE GTZC_MPCBB6_BASE_S +#define GTZC_TZIC GTZC_TZIC_S +#define GTZC_TZIC_BASE GTZC_TZIC_BASE_S +#define GTZC_TZSC GTZC_TZSC_S +#define GTZC_TZSC_BASE GTZC_TZSC_BASE_S +#define HASH HASH_S +#define HASH_BASE HASH_BASE_S +#define HASH_DIGEST HASH_DIGEST_S +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_S +#define HSEM HSEM_S +#define HSEM_BASE HSEM_BASE_S +#define HSEM_COMMON HSEM_COMMON_S +#define I2C1 I2C1_S +#define I2C1_BASE I2C1_BASE_S +#define I2C3 I2C3_S +#define I2C3_BASE I2C3_BASE_S +#define ICACHE ICACHE_S +#define ICACHE_BASE ICACHE_BASE_S +#define IWDG IWDG_S +#define IWDG_BASE IWDG_BASE_S +#define LPTIM1 LPTIM1_S +#define LPTIM1_BASE LPTIM1_BASE_S +#define LPTIM2 LPTIM2_S +#define LPTIM2_BASE LPTIM2_BASE_S +#define LPUART1 LPUART1_S +#define LPUART1_BASE LPUART1_BASE_S +#define PKA PKA_S +#define PKA_BASE PKA_BASE_S +#define PKA_RAM_BASE PKA_RAM_BASE_S +#define PTACONV_BASE PTACONV_BASE_S +#define PTACONV PTACONV_S +#define PWR PWR_S +#define PWR_BASE PWR_BASE_S +#define RADIO_BASE RADIO_BASE_S +#define RAMCFG_SRAM1 RAMCFG_SRAM1_S +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_S +#define RAMCFG_SRAM2 RAMCFG_SRAM2_S +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_S +#define RAMCFG_SRAM6 RAMCFG_SRAM6_S +#define RAMCFG_SRAM6_BASE RAMCFG_SRAM6_BASE_S +#define RCC RCC_S +#define RCC_BASE RCC_BASE_S +#define RNG RNG_S +#define RNG_BASE RNG_BASE_S +#define RTC RTC_S +#define RTC_BASE RTC_BASE_S +#define SAES SAES_S +#define SAES_BASE SAES_BASE_S +#define SAI1 SAI1_S +#define SAI1_BASE SAI1_BASE_S +#define SAI1_Block_A SAI1_Block_A_S +#define SAI1_Block_A_BASE SAI1_Block_A_BASE_S +#define SAI1_Block_B SAI1_Block_B_S +#define SAI1_Block_B_BASE SAI1_Block_B_BASE_S +#define SPI1 SPI1_S +#define SPI1_BASE SPI1_BASE_S +#define SPI3 SPI3_S +#define SPI3_BASE SPI3_BASE_S +#define SYSCFG SYSCFG_S +#define SYSCFG_BASE SYSCFG_BASE_S +#define TAMP TAMP_S +#define TAMP_BASE TAMP_BASE_S +#define TIM1 TIM1_S +#define TIM1_BASE TIM1_BASE_S +#define TIM2 TIM2_S +#define TIM2_BASE TIM2_BASE_S +#define TIM3 TIM3_S +#define TIM3_BASE TIM3_BASE_S +#define TIM16 TIM16_S +#define TIM16_BASE TIM16_BASE_S +#define TIM17 TIM17_S +#define TIM17_BASE TIM17_BASE_S +#define TSC TSC_S +#define TSC_BASE TSC_BASE_S +#define USART1 USART1_S +#define USART1_BASE USART1_BASE_S +#define USART2 USART2_S +#define USART2_BASE USART2_BASE_S +#define WWDG WWDG_S +#define WWDG_BASE WWDG_BASE_S + +#else +/*!< Memory base addresses for Non secure peripherals */ +#define FLASH_BASE FLASH_BASE_NS +#define SRAM1_BASE SRAM1_BASE_NS +#define SRAM2_BASE SRAM2_BASE_NS +#define SRAM6_BASE SRAM6_BASE_NS +#define SEQSRAM_BASE SEQSRAM_BASE_NS + +/*!< Instance aliases and base addresses for Non secure peripherals */ +#define ADC4 ADC4_NS +#define ADC4_BASE ADC4_BASE_NS +#define ADC4_COMMON ADC4_COMMON_NS +#define ADC4_COMMON_BASE ADC4_COMMON_BASE_NS +#define AES AES_NS +#define AES_BASE AES_BASE_NS +#define COMP1 COMP1_NS +#define COMP1_BASE COMP1_BASE_NS +#define COMP2 COMP2_NS +#define COMP2_BASE COMP2_BASE_NS +#define COMP12_COMMON COMP12_COMMON_NS +#define CRC CRC_NS +#define CRC_BASE CRC_BASE_NS +#define EXTI EXTI_NS +#define EXTI_BASE EXTI_BASE_NS +#define FLASH FLASH_NS +#define FLASH_R_BASE FLASH_R_BASE_NS +#define GPDMA1 GPDMA1_NS +#define GPDMA1_BASE GPDMA1_BASE_NS +#define GPDMA1_Channel0 GPDMA1_Channel0_NS +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_NS +#define GPDMA1_Channel1 GPDMA1_Channel1_NS +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_NS +#define GPDMA1_Channel2 GPDMA1_Channel2_NS +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_NS +#define GPDMA1_Channel3 GPDMA1_Channel3_NS +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_NS +#define GPDMA1_Channel4 GPDMA1_Channel4_NS +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_NS +#define GPDMA1_Channel5 GPDMA1_Channel5_NS +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_NS +#define GPDMA1_Channel6 GPDMA1_Channel6_NS +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_NS +#define GPDMA1_Channel7 GPDMA1_Channel7_NS +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_NS +#define GPIOA GPIOA_NS +#define GPIOA_BASE GPIOA_BASE_NS +#define GPIOB GPIOB_NS +#define GPIOB_BASE GPIOB_BASE_NS +#define GPIOC GPIOC_NS +#define GPIOC_BASE GPIOC_BASE_NS +#define GPIOH GPIOH_NS +#define GPIOH_BASE GPIOH_BASE_NS +#define GTZC_MPCBB1 GTZC_MPCBB1_NS +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_NS +#define GTZC_MPCBB2 GTZC_MPCBB2_NS +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_NS +#define GTZC_MPCBB6 GTZC_MPCBB6_NS +#define GTZC_MPCBB6_BASE GTZC_MPCBB6_BASE_NS +#define GTZC_TZSC GTZC_TZSC_NS +#define GTZC_TZSC_BASE GTZC_TZSC_BASE_NS +#define HASH HASH_NS +#define HASH_BASE HASH_BASE_NS +#define HASH_DIGEST HASH_DIGEST_NS +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_NS +#define HSEM HSEM_NS +#define HSEM_BASE HSEM_BASE_NS +#define HSEM_COMMON HSEM_COMMON_NS +#define I2C1 I2C1_NS +#define I2C1_BASE I2C1_BASE_NS +#define I2C3 I2C3_NS +#define I2C3_BASE I2C3_BASE_NS +#define ICACHE ICACHE_NS +#define ICACHE_BASE ICACHE_BASE_NS +#define IWDG IWDG_NS +#define IWDG_BASE IWDG_BASE_NS +#define LPTIM1 LPTIM1_NS +#define LPTIM1_BASE LPTIM1_BASE_NS +#define LPTIM2 LPTIM2_NS +#define LPTIM2_BASE LPTIM2_BASE_NS +#define LPUART1 LPUART1_NS +#define LPUART1_BASE LPUART1_BASE_NS +#define PKA PKA_NS +#define PKA_BASE PKA_BASE_NS +#define PKA_RAM_BASE PKA_RAM_BASE_NS +#define PTACONV_BASE PTACONV_BASE_NS +#define PTACONV PTACONV_NS +#define PWR PWR_NS +#define PWR_BASE PWR_BASE_NS +#define RADIO_BASE RADIO_BASE_NS +#define RAMCFG_SRAM1 RAMCFG_SRAM1_NS +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_NS +#define RAMCFG_SRAM2 RAMCFG_SRAM2_NS +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_NS +#define RAMCFG_SRAM6 RAMCFG_SRAM6_NS +#define RAMCFG_SRAM6_BASE RAMCFG_SRAM6_BASE_NS +#define RCC RCC_NS +#define RCC_BASE RCC_BASE_NS +#define RNG RNG_NS +#define RNG_BASE RNG_BASE_NS +#define RTC RTC_NS +#define RTC_BASE RTC_BASE_NS +#define SAES SAES_NS +#define SAES_BASE SAES_BASE_NS +#define SAI1 SAI1_NS +#define SAI1_BASE SAI1_BASE_NS +#define SAI1_Block_A SAI1_Block_A_NS +#define SAI1_Block_A_BASE SAI1_Block_A_BASE_NS +#define SAI1_Block_B SAI1_Block_B_NS +#define SAI1_Block_B_BASE SAI1_Block_B_BASE_NS +#define SPI1 SPI1_NS +#define SPI1_BASE SPI1_BASE_NS +#define SPI3 SPI3_NS +#define SPI3_BASE SPI3_BASE_NS +#define SYSCFG SYSCFG_NS +#define SYSCFG_BASE SYSCFG_BASE_NS +#define TAMP TAMP_NS +#define TAMP_BASE TAMP_BASE_NS +#define TIM1 TIM1_NS +#define TIM1_BASE TIM1_BASE_NS +#define TIM2 TIM2_NS +#define TIM2_BASE TIM2_BASE_NS +#define TIM3 TIM3_NS +#define TIM3_BASE TIM3_BASE_NS +#define TIM16 TIM16_NS +#define TIM16_BASE TIM16_BASE_NS +#define TIM17 TIM17_NS +#define TIM17_BASE TIM17_BASE_NS +#define TSC TSC_NS +#define TSC_BASE TSC_BASE_NS +#define USART1 USART1_NS +#define USART1_BASE USART1_BASE_NS +#define USART2 USART2_NS +#define USART2_BASE USART2_BASE_NS +#define WWDG WWDG_NS +#define WWDG_BASE WWDG_BASE_NS +#endif + + +/** @addtogroup Exported_constants + * @{ + */ + +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 16000U /*!< LSI Maximum startup time in us : 4 cycles @ 250 Hz = 16 ms */ +/** + * @} + */ + +/** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter (ADC) */ +/* */ +/******************************************************************************/ +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ +#define ADC_ISR_EOCAL_Pos (11U) +#define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */ +#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< ADC end of calibration flag */ +#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC internal voltage regulator ready flag */ + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ +#define ADC_IER_EOCALIE_Pos (11U) +#define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */ +#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< ADC end of calibration interrupt */ +#define ADC_IER_LDORDYIE_Pos (12U) +#define ADC_IER_LDORDYIE_Msk (0x1UL << ADC_IER_LDORDYIE_Pos) /*!< 0x00001000 */ +#define ADC_IER_LDORDYIE ADC_IER_LDORDYIE_Msk /*!< ADC Voltage Regulator Ready interrupt source */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR1 register *****************/ +#define ADC_CFGR1_DMAEN_Pos (0U) +#define ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC_CFGR1_DMACFG_Pos (1U) +#define ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC_CFGR1_RES_Pos (2U) +#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x0000000C */ +#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC Data resolution */ +#define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000004 */ +#define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ + +#define ADC_CFGR1_SCANDIR_Pos (4U) +#define ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000010 */ +#define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */ +#define ADC_CFGR1_ALIGN_Pos (5U) +#define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignment */ + +#define ADC_CFGR1_EXTSEL_Pos (6U) +#define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ +#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR1_EXTEN_Pos (10U) +#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR1_OVRMOD_Pos (12U) +#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR1_CONT_Pos (13U) +#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR1_WAIT_Pos (14U) +#define ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */ +#define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC low power auto wait */ +#define ADC_CFGR1_DISCEN_Pos (16U) +#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ +#define ADC_CFGR1_CHSELRMOD_Pos (21U) +#define ADC_CFGR1_CHSELRMOD_Msk (0x1UL << ADC_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */ +#define ADC_CFGR1_CHSELRMOD ADC_CFGR1_CHSELRMOD_Msk /*!< ADC group regular sequencer mode */ + +#define ADC_CFGR1_AWD1SGL_Pos (22U) +#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR1_AWD1EN_Pos (23U) +#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ + +#define ADC_CFGR1_AWD1CH_Pos (26U) +#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_OVSE_Pos (0U) +#define ADC_CFGR2_OVSE_Msk (0x1UL << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ + +#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TOVS_Pos (9U) +#define ADC_CFGR2_TOVS_Msk (0x1UL << ADC_CFGR2_TOVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ + +#define ADC_CFGR2_LFTRIG_Pos (29U) +#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC low frequency trigger mode */ + +/******************** Bit definition for ADC_SMPR register ******************/ +#define ADC_SMPR_SMP1_Pos (0U) +#define ADC_SMPR_SMP1_Msk (0x7UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000007 */ +#define ADC_SMPR_SMP1 ADC_SMPR_SMP1_Msk /*!< ADC group of channels sampling time 1 */ +#define ADC_SMPR_SMP1_0 (0x1UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000001 */ +#define ADC_SMPR_SMP1_1 (0x2UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000002 */ +#define ADC_SMPR_SMP1_2 (0x4UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR_SMP2_Pos (4U) +#define ADC_SMPR_SMP2_Msk (0x7UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000070 */ +#define ADC_SMPR_SMP2 ADC_SMPR_SMP2_Msk /*!< ADC group of channels sampling time 2 */ +#define ADC_SMPR_SMP2_0 (0x1UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000010 */ +#define ADC_SMPR_SMP2_1 (0x2UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000020 */ +#define ADC_SMPR_SMP2_2 (0x4UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000040 */ + +#define ADC_SMPR_SMPSEL_Pos (8U) +#define ADC_SMPR_SMPSEL_Msk (0x3FFFFUL << ADC_SMPR_SMPSEL_Pos) /*!< 0x03FFFF00 */ +#define ADC_SMPR_SMPSEL ADC_SMPR_SMPSEL_Msk /*!< ADC all channels sampling time selection */ +#define ADC_SMPR_SMPSEL0_Pos (8U) +#define ADC_SMPR_SMPSEL0_Msk (0x1UL << ADC_SMPR_SMPSEL0_Pos) /*!< 0x00000100 */ +#define ADC_SMPR_SMPSEL0 ADC_SMPR_SMPSEL0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR_SMPSEL1_Pos (9U) +#define ADC_SMPR_SMPSEL1_Msk (0x1UL << ADC_SMPR_SMPSEL1_Pos) /*!< 0x00000200 */ +#define ADC_SMPR_SMPSEL1 ADC_SMPR_SMPSEL1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR_SMPSEL2_Pos (10U) +#define ADC_SMPR_SMPSEL2_Msk (0x1UL << ADC_SMPR_SMPSEL2_Pos) /*!< 0x00000400 */ +#define ADC_SMPR_SMPSEL2 ADC_SMPR_SMPSEL2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR_SMPSEL3_Pos (11U) +#define ADC_SMPR_SMPSEL3_Msk (0x1UL << ADC_SMPR_SMPSEL3_Pos) /*!< 0x00000800 */ +#define ADC_SMPR_SMPSEL3 ADC_SMPR_SMPSEL3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR_SMPSEL4_Pos (12U) +#define ADC_SMPR_SMPSEL4_Msk (0x1UL << ADC_SMPR_SMPSEL4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR_SMPSEL4 ADC_SMPR_SMPSEL4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR_SMPSEL5_Pos (13U) +#define ADC_SMPR_SMPSEL5_Msk (0x1UL << ADC_SMPR_SMPSEL5_Pos) /*!< 0x00002000 */ +#define ADC_SMPR_SMPSEL5 ADC_SMPR_SMPSEL5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR_SMPSEL6_Pos (14U) +#define ADC_SMPR_SMPSEL6_Msk (0x1UL << ADC_SMPR_SMPSEL6_Pos) /*!< 0x00004000 */ +#define ADC_SMPR_SMPSEL6 ADC_SMPR_SMPSEL6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR_SMPSEL7_Pos (15U) +#define ADC_SMPR_SMPSEL7_Msk (0x1UL << ADC_SMPR_SMPSEL7_Pos) /*!< 0x00008000 */ +#define ADC_SMPR_SMPSEL7 ADC_SMPR_SMPSEL7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR_SMPSEL8_Pos (16U) +#define ADC_SMPR_SMPSEL8_Msk (0x1UL << ADC_SMPR_SMPSEL8_Pos) /*!< 0x00010000 */ +#define ADC_SMPR_SMPSEL8 ADC_SMPR_SMPSEL8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR_SMPSEL9_Pos (17U) +#define ADC_SMPR_SMPSEL9_Msk (0x1UL << ADC_SMPR_SMPSEL9_Pos) /*!< 0x00020000 */ +#define ADC_SMPR_SMPSEL9 ADC_SMPR_SMPSEL9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR_SMPSEL10_Pos (18U) +#define ADC_SMPR_SMPSEL10_Msk (0x1UL << ADC_SMPR_SMPSEL10_Pos) /*!< 0x00040000 */ +#define ADC_SMPR_SMPSEL10 ADC_SMPR_SMPSEL10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR_SMPSEL11_Pos (19U) +#define ADC_SMPR_SMPSEL11_Msk (0x1UL << ADC_SMPR_SMPSEL11_Pos) /*!< 0x00080000 */ +#define ADC_SMPR_SMPSEL11 ADC_SMPR_SMPSEL11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR_SMPSEL12_Pos (20U) +#define ADC_SMPR_SMPSEL12_Msk (0x1UL << ADC_SMPR_SMPSEL12_Pos) /*!< 0x00100000 */ +#define ADC_SMPR_SMPSEL12 ADC_SMPR_SMPSEL12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR_SMPSEL13_Pos (21U) +#define ADC_SMPR_SMPSEL13_Msk (0x1UL << ADC_SMPR_SMPSEL13_Pos) /*!< 0x00200000 */ +#define ADC_SMPR_SMPSEL13 ADC_SMPR_SMPSEL13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR_SMPSEL14_Pos (22U) +#define ADC_SMPR_SMPSEL14_Msk (0x1UL << ADC_SMPR_SMPSEL14_Pos) /*!< 0x00400000 */ +#define ADC_SMPR_SMPSEL14 ADC_SMPR_SMPSEL14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR_SMPSEL15_Pos (23U) +#define ADC_SMPR_SMPSEL15_Msk (0x1UL << ADC_SMPR_SMPSEL15_Pos) /*!< 0x00800000 */ +#define ADC_SMPR_SMPSEL15 ADC_SMPR_SMPSEL15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR_SMPSEL16_Pos (24U) +#define ADC_SMPR_SMPSEL16_Msk (0x1UL << ADC_SMPR_SMPSEL16_Pos) /*!< 0x01000000 */ +#define ADC_SMPR_SMPSEL16 ADC_SMPR_SMPSEL16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR_SMPSEL17_Pos (25U) +#define ADC_SMPR_SMPSEL17_Msk (0x1UL << ADC_SMPR_SMPSEL17_Pos) /*!< 0x02000000 */ +#define ADC_SMPR_SMPSEL17 ADC_SMPR_SMPSEL17_Msk /*!< ADC channel 17 sampling time selection */ + +/******************** Bit definition for ADC_AWD1TR register *******************/ +#define ADC_AWD1TR_LT1_Pos (0U) +#define ADC_AWD1TR_LT1_Msk (0xFFFUL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_AWD1TR_LT1 ADC_AWD1TR_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ +#define ADC_AWD1TR_LT1_0 (0x001UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000001 */ +#define ADC_AWD1TR_LT1_1 (0x002UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000002 */ +#define ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000004 */ +#define ADC_AWD1TR_LT1_3 (0x008UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000008 */ +#define ADC_AWD1TR_LT1_4 (0x010UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000010 */ +#define ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000020 */ +#define ADC_AWD1TR_LT1_6 (0x040UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000040 */ +#define ADC_AWD1TR_LT1_7 (0x080UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000080 */ +#define ADC_AWD1TR_LT1_8 (0x100UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000100 */ +#define ADC_AWD1TR_LT1_9 (0x200UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000200 */ +#define ADC_AWD1TR_LT1_10 (0x400UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000400 */ +#define ADC_AWD1TR_LT1_11 (0x800UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000800 */ + +#define ADC_AWD1TR_HT1_Pos (16U) +#define ADC_AWD1TR_HT1_Msk (0xFFFUL << ADC_AWD1TR_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD1TR_HT1 ADC_AWD1TR_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ +#define ADC_AWD1TR_HT1_0 (0x001UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00010000 */ +#define ADC_AWD1TR_HT1_1 (0x002UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00020000 */ +#define ADC_AWD1TR_HT1_2 (0x004UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00040000 */ +#define ADC_AWD1TR_HT1_3 (0x008UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00080000 */ +#define ADC_AWD1TR_HT1_4 (0x010UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00100000 */ +#define ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00200000 */ +#define ADC_AWD1TR_HT1_6 (0x040UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00400000 */ +#define ADC_AWD1TR_HT1_7 (0x080UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00800000 */ +#define ADC_AWD1TR_HT1_8 (0x100UL << ADC_AWD1TR_HT1_Pos) /*!< 0x01000000 */ +#define ADC_AWD1TR_HT1_9 (0x200UL << ADC_AWD1TR_HT1_Pos) /*!< 0x02000000 */ +#define ADC_AWD1TR_HT1_10 (0x400UL << ADC_AWD1TR_HT1_Pos) /*!< 0x04000000 */ +#define ADC_AWD1TR_HT1_11 (0x800UL << ADC_AWD1TR_HT1_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_AWDTR2 register *******************/ +#define ADC_AWD2TR_LT2_Pos (0U) +#define ADC_AWD2TR_LT2_Msk (0xFFFUL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000FFF */ +#define ADC_AWD2TR_LT2 ADC_AWD2TR_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ +#define ADC_AWD2TR_LT2_0 (0x001UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000001 */ +#define ADC_AWD2TR_LT2_1 (0x002UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000002 */ +#define ADC_AWD2TR_LT2_2 (0x004UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000004 */ +#define ADC_AWD2TR_LT2_3 (0x008UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000008 */ +#define ADC_AWD2TR_LT2_4 (0x010UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000010 */ +#define ADC_AWD2TR_LT2_5 (0x020UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000020 */ +#define ADC_AWD2TR_LT2_6 (0x040UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000040 */ +#define ADC_AWD2TR_LT2_7 (0x080UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000080 */ +#define ADC_AWD2TR_LT2_8 (0x100UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000100 */ +#define ADC_AWD2TR_LT2_9 (0x200UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000200 */ +#define ADC_AWD2TR_LT2_10 (0x400UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000400 */ +#define ADC_AWD2TR_LT2_11 (0x800UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000800 */ + +#define ADC_AWD2TR_HT2_Pos (16U) +#define ADC_AWD2TR_HT2_Msk (0xFFFUL << ADC_AWD2TR_HT2_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD2TR_HT2 ADC_AWD2TR_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ +#define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ +#define ADC_AWD2TR_HT2_1 (0x002UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00020000 */ +#define ADC_AWD2TR_HT2_2 (0x004UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00040000 */ +#define ADC_AWD2TR_HT2_3 (0x008UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00080000 */ +#define ADC_AWD2TR_HT2_4 (0x010UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00100000 */ +#define ADC_AWD2TR_HT2_5 (0x020UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00200000 */ +#define ADC_AWD2TR_HT2_6 (0x040UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00400000 */ +#define ADC_AWD2TR_HT2_7 (0x080UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00800000 */ +#define ADC_AWD2TR_HT2_8 (0x100UL << ADC_AWD2TR_HT2_Pos) /*!< 0x01000000 */ +#define ADC_AWD2TR_HT2_9 (0x200UL << ADC_AWD2TR_HT2_Pos) /*!< 0x02000000 */ +#define ADC_AWD2TR_HT2_10 (0x400UL << ADC_AWD2TR_HT2_Pos) /*!< 0x04000000 */ +#define ADC_AWD2TR_HT2_11 (0x800UL << ADC_AWD2TR_HT2_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_CHSELR register ****************/ +#define ADC_CHSELR_CHSEL_Pos (0U) +#define ADC_CHSELR_CHSEL_Msk (0x3FFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0003FFFF */ +#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL17_Pos (17U) +#define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL16_Pos (16U) +#define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL15_Pos (15U) +#define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ +#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL14_Pos (14U) +#define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL13_Pos (13U) +#define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL12_Pos (12U) +#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL11_Pos (11U) +#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ +#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL10_Pos (10U) +#define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL9_Pos (9U) +#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL8_Pos (8U) +#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL7_Pos (7U) +#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ +#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL6_Pos (6U) +#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL5_Pos (5U) +#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL4_Pos (4U) +#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL3_Pos (3U) +#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ +#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL2_Pos (2U) +#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL1_Pos (1U) +#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL0_Pos (0U) +#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */ + +#define ADC_CHSELR_SQ_ALL_Pos (0U) +#define ADC_CHSELR_SQ_ALL_Msk (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CHSELR_SQ_ALL ADC_CHSELR_SQ_ALL_Msk /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */ + +#define ADC_CHSELR_SQ8_Pos (28U) +#define ADC_CHSELR_SQ8_Msk (0xFUL << ADC_CHSELR_SQ8_Pos) /*!< 0xF0000000 */ +#define ADC_CHSELR_SQ8 ADC_CHSELR_SQ8_Msk /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ8_0 (0x1UL << ADC_CHSELR_SQ8_Pos) /*!< 0x10000000 */ +#define ADC_CHSELR_SQ8_1 (0x2UL << ADC_CHSELR_SQ8_Pos) /*!< 0x20000000 */ +#define ADC_CHSELR_SQ8_2 (0x4UL << ADC_CHSELR_SQ8_Pos) /*!< 0x40000000 */ +#define ADC_CHSELR_SQ8_3 (0x8UL << ADC_CHSELR_SQ8_Pos) /*!< 0x80000000 */ + +#define ADC_CHSELR_SQ7_Pos (24U) +#define ADC_CHSELR_SQ7_Msk (0xFUL << ADC_CHSELR_SQ7_Pos) /*!< 0x0F000000 */ +#define ADC_CHSELR_SQ7 ADC_CHSELR_SQ7_Msk /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ7_0 (0x1UL << ADC_CHSELR_SQ7_Pos) /*!< 0x01000000 */ +#define ADC_CHSELR_SQ7_1 (0x2UL << ADC_CHSELR_SQ7_Pos) /*!< 0x02000000 */ +#define ADC_CHSELR_SQ7_2 (0x4UL << ADC_CHSELR_SQ7_Pos) /*!< 0x04000000 */ +#define ADC_CHSELR_SQ7_3 (0x8UL << ADC_CHSELR_SQ7_Pos) /*!< 0x08000000 */ + +#define ADC_CHSELR_SQ6_Pos (20U) +#define ADC_CHSELR_SQ6_Msk (0xFUL << ADC_CHSELR_SQ6_Pos) /*!< 0x00F00000 */ +#define ADC_CHSELR_SQ6 ADC_CHSELR_SQ6_Msk /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ6_0 (0x1UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00100000 */ +#define ADC_CHSELR_SQ6_1 (0x2UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00200000 */ +#define ADC_CHSELR_SQ6_2 (0x4UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00400000 */ +#define ADC_CHSELR_SQ6_3 (0x8UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00800000 */ + +#define ADC_CHSELR_SQ5_Pos (16U) +#define ADC_CHSELR_SQ5_Msk (0xFUL << ADC_CHSELR_SQ5_Pos) /*!< 0x000F0000 */ +#define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ5_0 (0x1UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_SQ5_1 (0x2UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_SQ5_2 (0x4UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_SQ5_3 (0x8UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00080000 */ + +#define ADC_CHSELR_SQ4_Pos (12U) +#define ADC_CHSELR_SQ4_Msk (0xFUL << ADC_CHSELR_SQ4_Pos) /*!< 0x0000F000 */ +#define ADC_CHSELR_SQ4 ADC_CHSELR_SQ4_Msk /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ4_0 (0x1UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_SQ4_1 (0x2UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_SQ4_2 (0x4UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_SQ4_3 (0x8UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00008000 */ + +#define ADC_CHSELR_SQ3_Pos (8U) +#define ADC_CHSELR_SQ3_Msk (0xFUL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000F00 */ +#define ADC_CHSELR_SQ3 ADC_CHSELR_SQ3_Msk /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ3_0 (0x1UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_SQ3_1 (0x2UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_SQ3_2 (0x4UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_SQ3_3 (0x8UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000800 */ + +#define ADC_CHSELR_SQ2_Pos (4U) +#define ADC_CHSELR_SQ2_Msk (0xFUL << ADC_CHSELR_SQ2_Pos) /*!< 0x000000F0 */ +#define ADC_CHSELR_SQ2 ADC_CHSELR_SQ2_Msk /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ2_0 (0x1UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_SQ2_1 (0x2UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_SQ2_2 (0x4UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_SQ2_3 (0x8UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000080 */ + +#define ADC_CHSELR_SQ1_Pos (0U) +#define ADC_CHSELR_SQ1_Msk (0xFUL << ADC_CHSELR_SQ1_Pos) /*!< 0x0000000F */ +#define ADC_CHSELR_SQ1 ADC_CHSELR_SQ1_Msk /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ1_0 (0x1UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_SQ1_1 (0x2UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_SQ1_2 (0x4UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_SQ1_3 (0x8UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000008 */ + +/******************** Bit definition for ADC_AWD3TR register *******************/ +#define ADC_AWD3TR_LT3_Pos (0U) +#define ADC_AWD3TR_LT3_Msk (0xFFFUL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000FFF */ +#define ADC_AWD3TR_LT3 ADC_AWD3TR_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ +#define ADC_AWD3TR_LT3_0 (0x001UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000001 */ +#define ADC_AWD3TR_LT3_1 (0x002UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000002 */ +#define ADC_AWD3TR_LT3_2 (0x004UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000004 */ +#define ADC_AWD3TR_LT3_3 (0x008UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000008 */ +#define ADC_AWD3TR_LT3_4 (0x010UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000010 */ +#define ADC_AWD3TR_LT3_5 (0x020UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000020 */ +#define ADC_AWD3TR_LT3_6 (0x040UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000040 */ +#define ADC_AWD3TR_LT3_7 (0x080UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000080 */ +#define ADC_AWD3TR_LT3_8 (0x100UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000100 */ +#define ADC_AWD3TR_LT3_9 (0x200UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000200 */ +#define ADC_AWD3TR_LT3_10 (0x400UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000400 */ +#define ADC_AWD3TR_LT3_11 (0x800UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000800 */ + +#define ADC_AWD3TR_HT3_Pos (16U) +#define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD3TR_HT3 ADC_AWD3TR_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ +#define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */ +#define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */ +#define ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00040000 */ +#define ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00080000 */ +#define ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00100000 */ +#define ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00200000 */ +#define ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00400000 */ +#define ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00800000 */ +#define ADC_AWD3TR_HT3_8 (0x100UL << ADC_AWD3TR_HT3_Pos) /*!< 0x01000000 */ +#define ADC_AWD3TR_HT3_9 (0x200UL << ADC_AWD3TR_HT3_Pos) /*!< 0x02000000 */ +#define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) /*!< 0x04000000 */ +#define ADC_AWD3TR_HT3_11 (0x800UL << ADC_AWD3TR_HT3_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_DATA_Pos (0U) +#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */ + +/******************** Bit definition for ADC_PWRR register ******************/ +#define ADC_PWRR_AUTOFF_Pos (0U) +#define ADC_PWRR_AUTOFF_Msk (0x1UL << ADC_PWRR_AUTOFF_Pos) /*!< 0x00000001 */ +#define ADC_PWRR_AUTOFF ADC_PWRR_AUTOFF_Msk /*!< ADC auto-off mode */ +#define ADC_PWRR_DPD_Pos (1U) +#define ADC_PWRR_DPD_Msk (0x1UL << ADC_PWRR_DPD_Pos) /*!< 0x00000002 */ +#define ADC_PWRR_DPD ADC_PWRR_DPD_Msk /*!< ADC deep power down mode */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0x3FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0003FFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0x3FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0003FFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_Pos (0U) +#define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_0 (0x01UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_1 (0x02UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_2 (0x04UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_3 (0x08UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_4 (0x10UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_5 (0x20UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_6 (0x40UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000040 */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ + + +/******************************************************************************/ +/* */ +/* Analog comparators (COMP) */ +/* */ +/******************************************************************************/ +/********************** Bit definition for COMP_CSR register ****************/ +#define COMP_CSR_EN_Pos (0U) +#define COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos) /*!< 0x00000001 */ +#define COMP_CSR_EN COMP_CSR_EN_Msk /*!< Comparator enable */ + +#define COMP_CSR_INMSEL_Pos (4U) +#define COMP_CSR_INMSEL_Msk (0xFUL << COMP_CSR_INMSEL_Pos) /*!< 0x000000F0 */ +#define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< Comparator input minus selection */ +#define COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000010 */ +#define COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000020 */ +#define COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000040 */ +#define COMP_CSR_INMSEL_3 (0x8UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000080 */ + +#define COMP_CSR_INPSEL_Pos (8U) +#define COMP_CSR_INPSEL_Msk (0x3UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000300 */ +#define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< Comparator input plus selection */ +#define COMP_CSR_INPSEL_0 (0x1UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000100 */ +#define COMP_CSR_INPSEL_1 (0x2UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000200 */ + +#define COMP_CSR_WINMODE_Pos (11U) +#define COMP_CSR_WINMODE_Msk (0x1UL << COMP_CSR_WINMODE_Pos) /*!< 0x00000800 */ +#define COMP_CSR_WINMODE COMP_CSR_WINMODE_Msk /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */ + +#define COMP_CSR_WINOUT_Pos (14U) +#define COMP_CSR_WINOUT_Msk (0x1UL << COMP_CSR_WINOUT_Pos) /*!< 0x00004000 */ +#define COMP_CSR_WINOUT COMP_CSR_WINOUT_Msk /*!< Pair of comparators window output level. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */ + +#define COMP_CSR_POLARITY_Pos (15U) +#define COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos) /*!< 0x00008000 */ +#define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< Comparator output polarity */ + +#define COMP_CSR_HYST_Pos (16U) +#define COMP_CSR_HYST_Msk (0x3UL << COMP_CSR_HYST_Pos) /*!< 0x00030000 */ +#define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< Comparator input hysteresis */ +#define COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos) /*!< 0x00010000 */ +#define COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos) /*!< 0x00020000 */ + +#define COMP_CSR_PWRMODE_Pos (18U) +#define COMP_CSR_PWRMODE_Msk (0x3UL << COMP_CSR_PWRMODE_Pos) /*!< 0x000C0000 */ +#define COMP_CSR_PWRMODE COMP_CSR_PWRMODE_Msk /*!< Comparator power mode */ +#define COMP_CSR_PWRMODE_0 (0x1UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00001000 */ +#define COMP_CSR_PWRMODE_1 (0x2UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00002000 */ + +#define COMP_CSR_BLANKSEL_Pos (20U) +#define COMP_CSR_BLANKSEL_Msk (0x1FUL << COMP_CSR_BLANKSEL_Pos) /*!< 0x01F00000 */ +#define COMP_CSR_BLANKSEL COMP_CSR_BLANKSEL_Msk /*!< Comparator blanking source */ +#define COMP_CSR_BLANKSEL_0 (0x01UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x00100000 */ +#define COMP_CSR_BLANKSEL_1 (0x02UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x00200000 */ +#define COMP_CSR_BLANKSEL_2 (0x04UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x00400000 */ +#define COMP_CSR_BLANKSEL_3 (0x08UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x00800000 */ +#define COMP_CSR_BLANKSEL_4 (0x10UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x01000000 */ + +#define COMP_CSR_VALUE_Pos (30U) +#define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */ +#define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< Comparator output level */ + +#define COMP_CSR_LOCK_Pos (31U) +#define COMP_CSR_LOCK_Msk (0x1UL << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */ +#define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< Comparator lock */ + + + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + + +/******************************************************************************/ +/* */ +/* Advanced Encryption Standard (AES) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for AES_CR register *********************/ +#define AES_CR_EN_Pos (0U) +#define AES_CR_EN_Msk (0x1UL << AES_CR_EN_Pos) /*!< 0x00000001 */ +#define AES_CR_EN AES_CR_EN_Msk /*!< AES Enable */ +#define AES_CR_DATATYPE_Pos (1U) +#define AES_CR_DATATYPE_Msk (0x3UL << AES_CR_DATATYPE_Pos) /*!< 0x00000006 */ +#define AES_CR_DATATYPE AES_CR_DATATYPE_Msk /*!< Data type selection */ +#define AES_CR_DATATYPE_0 (0x1UL << AES_CR_DATATYPE_Pos) /*!< 0x00000002 */ +#define AES_CR_DATATYPE_1 (0x2UL << AES_CR_DATATYPE_Pos) /*!< 0x00000004 */ +#define AES_CR_MODE_Pos (3U) +#define AES_CR_MODE_Msk (0x3UL << AES_CR_MODE_Pos) /*!< 0x00000018 */ +#define AES_CR_MODE AES_CR_MODE_Msk /*!< AES Mode Of Operation */ +#define AES_CR_MODE_0 (0x1UL << AES_CR_MODE_Pos) /*!< 0x00000008 */ +#define AES_CR_MODE_1 (0x2UL << AES_CR_MODE_Pos) /*!< 0x00000010 */ +#define AES_CR_CHMOD_Pos (5U) +#define AES_CR_CHMOD_Msk (0x803UL << AES_CR_CHMOD_Pos) /*!< 0x00010060 */ +#define AES_CR_CHMOD AES_CR_CHMOD_Msk /*!< AES Chaining Mode */ +#define AES_CR_CHMOD_0 (0x001UL << AES_CR_CHMOD_Pos) /*!< 0x00000020 */ +#define AES_CR_CHMOD_1 (0x002UL << AES_CR_CHMOD_Pos) /*!< 0x00000040 */ +#define AES_CR_CHMOD_2 (0x800UL << AES_CR_CHMOD_Pos) /*!< 0x00010000 */ +#define AES_CR_DMAINEN_Pos (11U) +#define AES_CR_DMAINEN_Msk (0x1UL << AES_CR_DMAINEN_Pos) /*!< 0x00000800 */ +#define AES_CR_DMAINEN AES_CR_DMAINEN_Msk /*!< Enable data input phase DMA management */ +#define AES_CR_DMAOUTEN_Pos (12U) +#define AES_CR_DMAOUTEN_Msk (0x1UL << AES_CR_DMAOUTEN_Pos) /*!< 0x00001000 */ +#define AES_CR_DMAOUTEN AES_CR_DMAOUTEN_Msk /*!< Enable data output phase DMA management */ +#define AES_CR_GCMPH_Pos (13U) +#define AES_CR_GCMPH_Msk (0x3UL << AES_CR_GCMPH_Pos) /*!< 0x00006000 */ +#define AES_CR_GCMPH AES_CR_GCMPH_Msk /*!< GCM Phase */ +#define AES_CR_GCMPH_0 (0x1UL << AES_CR_GCMPH_Pos) /*!< 0x00002000 */ +#define AES_CR_GCMPH_1 (0x2UL << AES_CR_GCMPH_Pos) /*!< 0x00004000 */ +#define AES_CR_KEYSIZE_Pos (18U) +#define AES_CR_KEYSIZE_Msk (0x1UL << AES_CR_KEYSIZE_Pos) /*!< 0x00040000 */ +#define AES_CR_KEYSIZE AES_CR_KEYSIZE_Msk /*!< Key size selection */ +#define AES_CR_KEYPROT_Pos (19U) +#define AES_CR_KEYPROT_Msk (0x1UL << AES_CR_KEYPROT_Pos) /*!< 0x00080000 */ +#define AES_CR_KEYPROT AES_CR_KEYPROT_Msk /*!< Key protection */ +#define AES_CR_NPBLB_Pos (20U) +#define AES_CR_NPBLB_Msk (0xFUL << AES_CR_NPBLB_Pos) /*!< 0x00F00000 */ +#define AES_CR_NPBLB AES_CR_NPBLB_Msk /*!< Number of padding bytes in payload last block */ +#define AES_CR_NPBLB_0 (0x1UL << AES_CR_NPBLB_Pos) /*!< 0x00100000 */ +#define AES_CR_NPBLB_1 (0x2UL << AES_CR_NPBLB_Pos) /*!< 0x00200000 */ +#define AES_CR_NPBLB_2 (0x4UL << AES_CR_NPBLB_Pos) /*!< 0x00400000 */ +#define AES_CR_NPBLB_3 (0x8UL << AES_CR_NPBLB_Pos) /*!< 0x00800000 */ +#define AES_CR_KMOD_Pos (24U) +#define AES_CR_KMOD_Msk (0x3UL << AES_CR_KMOD_Pos) /*!< 0x03000000 */ +#define AES_CR_KMOD AES_CR_KMOD_Msk /*!< Key mode selection */ +#define AES_CR_KMOD_0 (0x1UL << AES_CR_KMOD_Pos) /*!< 0x01000000 */ +#define AES_CR_KMOD_1 (0x2UL << AES_CR_KMOD_Pos) /*!< 0x02000000 */ +#define AES_CR_KSHAREID_Pos (26U) +#define AES_CR_KSHAREID_Msk (0x3UL << AES_CR_KSHAREID_Pos) /*!< 0x0C000000 */ +#define AES_CR_KSHAREID AES_CR_KSHAREID_Msk /*!< Key Shared ID */ +#define AES_CR_KEYSEL_Pos (28U) +#define AES_CR_KEYSEL_Msk (0x7UL << AES_CR_KEYSEL_Pos) /*!< 0x70000000 */ +#define AES_CR_KEYSEL AES_CR_KEYSEL_Msk /*!< Key Selection */ +#define AES_CR_KEYSEL_0 (0x1UL << AES_CR_KEYSEL_Pos) /*!< 0x10000000 */ +#define AES_CR_KEYSEL_1 (0x2UL << AES_CR_KEYSEL_Pos) /*!< 0x20000000 */ +#define AES_CR_KEYSEL_2 (0x4UL << AES_CR_KEYSEL_Pos) /*!< 0x40000000 */ +#define AES_CR_IPRST_Pos (31U) +#define AES_CR_IPRST_Msk (0x1UL << AES_CR_IPRST_Pos) /*!< 0x80000000 */ +#define AES_CR_IPRST AES_CR_IPRST_Msk /*!< AES IP software reset */ + + +/******************* Bit definition for AES_SR register *********************/ +#define AES_SR_CCF_Pos (0U) +#define AES_SR_CCF_Msk (0x1UL << AES_SR_CCF_Pos) /*!< 0x00000001 */ +#define AES_SR_CCF AES_SR_CCF_Msk /*!< Computation Complete Flag */ +#define AES_SR_RDERR_Pos (1U) +#define AES_SR_RDERR_Msk (0x1UL << AES_SR_RDERR_Pos) /*!< 0x00000002 */ +#define AES_SR_RDERR AES_SR_RDERR_Msk /*!< Read Error Flag */ +#define AES_SR_WRERR_Pos (2U) +#define AES_SR_WRERR_Msk (0x1UL << AES_SR_WRERR_Pos) /*!< 0x00000004 */ +#define AES_SR_WRERR AES_SR_WRERR_Msk /*!< Write Error Flag */ +#define AES_SR_BUSY_Pos (3U) +#define AES_SR_BUSY_Msk (0x1UL << AES_SR_BUSY_Pos) /*!< 0x00000008 */ +#define AES_SR_BUSY AES_SR_BUSY_Msk /*!< Busy Flag */ +#define AES_SR_KEYVALID_Pos (7U) +#define AES_SR_KEYVALID_Msk (0x1UL << AES_SR_KEYVALID_Pos) /*!< 0x00000080 */ +#define AES_SR_KEYVALID AES_SR_KEYVALID_Msk /*!< Key Valid Flag */ + +/******************* Bit definition for AES_DINR register *******************/ +#define AES_DINR_Pos (0U) +#define AES_DINR_Msk (0xFFFFFFFFUL << AES_DINR_Pos) /*!< 0xFFFFFFFF */ +#define AES_DINR AES_DINR_Msk /*!< AES Data Input Register */ + +/******************* Bit definition for AES_DOUTR register ******************/ +#define AES_DOUTR_Pos (0U) +#define AES_DOUTR_Msk (0xFFFFFFFFUL << AES_DOUTR_Pos) /*!< 0xFFFFFFFF */ +#define AES_DOUTR AES_DOUTR_Msk /*!< AES Data Output Register */ + +/******************* Bit definition for AES_KEYR0 register ******************/ +#define AES_KEYR0_Pos (0U) +#define AES_KEYR0_Msk (0xFFFFFFFFUL << AES_KEYR0_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR0 AES_KEYR0_Msk /*!< AES Key Register 0 */ + +/******************* Bit definition for AES_KEYR1 register ******************/ +#define AES_KEYR1_Pos (0U) +#define AES_KEYR1_Msk (0xFFFFFFFFUL << AES_KEYR1_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR1 AES_KEYR1_Msk /*!< AES Key Register 1 */ + +/******************* Bit definition for AES_KEYR2 register ******************/ +#define AES_KEYR2_Pos (0U) +#define AES_KEYR2_Msk (0xFFFFFFFFUL << AES_KEYR2_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR2 AES_KEYR2_Msk /*!< AES Key Register 2 */ + +/******************* Bit definition for AES_KEYR3 register ******************/ +#define AES_KEYR3_Pos (0U) +#define AES_KEYR3_Msk (0xFFFFFFFFUL << AES_KEYR3_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR3 AES_KEYR3_Msk /*!< AES Key Register 3 */ + +/******************* Bit definition for AES_KEYR4 register ******************/ +#define AES_KEYR4_Pos (0U) +#define AES_KEYR4_Msk (0xFFFFFFFFUL << AES_KEYR4_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR4 AES_KEYR4_Msk /*!< AES Key Register 4 */ + +/******************* Bit definition for AES_KEYR5 register ******************/ +#define AES_KEYR5_Pos (0U) +#define AES_KEYR5_Msk (0xFFFFFFFFUL << AES_KEYR5_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR5 AES_KEYR5_Msk /*!< AES Key Register 5 */ + +/******************* Bit definition for AES_KEYR6 register ******************/ +#define AES_KEYR6_Pos (0U) +#define AES_KEYR6_Msk (0xFFFFFFFFUL << AES_KEYR6_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR6 AES_KEYR6_Msk /*!< AES Key Register 6 */ + +/******************* Bit definition for AES_KEYR7 register ******************/ +#define AES_KEYR7_Pos (0U) +#define AES_KEYR7_Msk (0xFFFFFFFFUL << AES_KEYR7_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR7 AES_KEYR7_Msk /*!< AES Key Register 7 */ + +/******************* Bit definition for AES_IVR0 register ******************/ +#define AES_IVR0_Pos (0U) +#define AES_IVR0_Msk (0xFFFFFFFFUL << AES_IVR0_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR0 AES_IVR0_Msk /*!< AES Initialization Vector Register 0 */ + +/******************* Bit definition for AES_IVR1 register ******************/ +#define AES_IVR1_Pos (0U) +#define AES_IVR1_Msk (0xFFFFFFFFUL << AES_IVR1_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR1 AES_IVR1_Msk /*!< AES Initialization Vector Register 1 */ + +/******************* Bit definition for AES_IVR2 register ******************/ +#define AES_IVR2_Pos (0U) +#define AES_IVR2_Msk (0xFFFFFFFFUL << AES_IVR2_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR2 AES_IVR2_Msk /*!< AES Initialization Vector Register 2 */ + +/******************* Bit definition for AES_IVR3 register ******************/ +#define AES_IVR3_Pos (0U) +#define AES_IVR3_Msk (0xFFFFFFFFUL << AES_IVR3_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR3 AES_IVR3_Msk /*!< AES Initialization Vector Register 3 */ + +/******************* Bit definition for AES_SUSP0R register ******************/ +#define AES_SUSP0R_Pos (0U) +#define AES_SUSP0R_Msk (0xFFFFFFFFUL << AES_SUSP0R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP0R AES_SUSP0R_Msk /*!< AES Suspend registers 0 */ + +/******************* Bit definition for AES_SUSP1R register ******************/ +#define AES_SUSP1R_Pos (0U) +#define AES_SUSP1R_Msk (0xFFFFFFFFUL << AES_SUSP1R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP1R AES_SUSP1R_Msk /*!< AES Suspend registers 1 */ + +/******************* Bit definition for AES_SUSP2R register ******************/ +#define AES_SUSP2R_Pos (0U) +#define AES_SUSP2R_Msk (0xFFFFFFFFUL << AES_SUSP2R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP2R AES_SUSP2R_Msk /*!< AES Suspend registers 2 */ + +/******************* Bit definition for AES_SUSP3R register ******************/ +#define AES_SUSP3R_Pos (0U) +#define AES_SUSP3R_Msk (0xFFFFFFFFUL << AES_SUSP3R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP3R AES_SUSP3R_Msk /*!< AES Suspend registers 3 */ + +/******************* Bit definition for AES_SUSP4R register ******************/ +#define AES_SUSP4R_Pos (0U) +#define AES_SUSP4R_Msk (0xFFFFFFFFUL << AES_SUSP4R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP4R AES_SUSP4R_Msk /*!< AES Suspend registers 4 */ + +/******************* Bit definition for AES_SUSP5R register ******************/ +#define AES_SUSP5R_Pos (0U) +#define AES_SUSP5R_Msk (0xFFFFFFFFUL << AES_SUSP5R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP5R AES_SUSP5R_Msk /*!< AES Suspend registers 5 */ + +/******************* Bit definition for AES_SUSP6R register ******************/ +#define AES_SUSP6R_Pos (0U) +#define AES_SUSP6R_Msk (0xFFFFFFFFUL << AES_SUSP6R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP6R AES_SUSP6R_Msk /*!< AES Suspend registers 6 */ + +/******************* Bit definition for AES_SUSP7R register ******************/ +#define AES_SUSP7R_Pos (0U) +#define AES_SUSP7R_Msk (0xFFFFFFFFUL << AES_SUSP7R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP7R AES_SUSP7R_Msk /*!< AES Suspend registers 7 */ + +/******************* Bit definition for AES_IER register ******************/ +#define AES_IER_CCFIE_Pos (0U) +#define AES_IER_CCFIE_Msk (0x1UL << AES_IER_CCFIE_Pos) /*!< 0x00000001 */ +#define AES_IER_CCFIE AES_IER_CCFIE_Msk /*!< Computation complete flag interrupt enable */ +#define AES_IER_RWEIE_Pos (1U) +#define AES_IER_RWEIE_Msk (0x1UL << AES_IER_RWEIE_Pos) /*!< 0x00000002 */ +#define AES_IER_RWEIE AES_IER_RWEIE_Msk /*!< Read or write error Interrupt Enable */ +#define AES_IER_KEIE_Pos (2U) +#define AES_IER_KEIE_Msk (0x1UL << AES_IER_KEIE_Pos) /*!< 0x00000004 */ +#define AES_IER_KEIE AES_IER_KEIE_Msk /*!< Key error interrupt enable */ +#define AES_IER_RNGEIE_Pos (3U) +#define AES_IER_RNGEIE_Msk (0x1UL << AES_IER_RNGEIE_Pos) /*!< 0x00000008 */ +#define AES_IER_RNGEIE AES_IER_RNGEIE_Msk /*!< SAES Rng error interrupt enable */ + +/******************* Bit definition for AES_ISR register ******************/ +#define AES_ISR_CCF_Pos (0U) +#define AES_ISR_CCF_Msk (0x1UL << AES_ISR_CCF_Pos) /*!< 0x00000001 */ +#define AES_ISR_CCF AES_ISR_CCF_Msk /*!< Computation complete flag */ +#define AES_ISR_RWEIF_Pos (1U) +#define AES_ISR_RWEIF_Msk (0x1UL << AES_ISR_RWEIF_Pos) /*!< 0x00000002 */ +#define AES_ISR_RWEIF AES_ISR_RWEIF_Msk /*!< Read or write error Interrupt flag */ +#define AES_ISR_KEIF_Pos (2U) +#define AES_ISR_KEIF_Msk (0x1UL << AES_ISR_KEIF_Pos) /*!< 0x00000004 */ +#define AES_ISR_KEIF AES_ISR_KEIF_Msk /*!< Key error interrupt flag */ +#define AES_ISR_RNGEIF_Pos (3U) +#define AES_ISR_RNGEIF_Msk (0x1UL << AES_ISR_RNGEIF_Pos) /*!< 0x00000008 */ +#define AES_ISR_RNGEIF AES_ISR_RNGEIF_Msk /*!< SAES Rng error interrupt flag */ + +/******************* Bit definition for AES_ICR register ******************/ +#define AES_ICR_CCF_Pos (0U) +#define AES_ICR_CCF_Msk (0x1UL << AES_ICR_CCF_Pos) /*!< 0x00000001 */ +#define AES_ICR_CCF AES_ICR_CCF_Msk /*!< Computation complete flag clear */ +#define AES_ICR_RWEIF_Pos (1U) +#define AES_ICR_RWEIF_Msk (0x1UL << AES_ICR_RWEIF_Pos) /*!< 0x00000002 */ +#define AES_ICR_RWEIF AES_ICR_RWEIF_Msk /*!< Read or write error Interrupt flag clear */ +#define AES_ICR_KEIF_Pos (2U) +#define AES_ICR_KEIF_Msk (0x1UL << AES_ICR_KEIF_Pos) /*!< 0x00000004 */ +#define AES_ICR_KEIF AES_ICR_KEIF_Msk /*!< Key error interrupt flag clear */ +#define AES_ICR_RNGEIF_Pos (3U) +#define AES_ICR_RNGEIF_Msk (0x1UL << AES_ICR_RNGEIF_Pos) /*!< 0x00000008 */ +#define AES_ICR_RNGEIF AES_ICR_RNGEIF_Msk /*!< SAES Rng error interrupt flag clear */ + +/******************************************************************************/ +/* */ +/* Debug MCU */ +/* */ +/******************************************************************************/ +/******************** Bit definition for DBGMCU_IDCODE register *************/ +#define DBGMCU_IDCODE_DEV_ID_Pos (0U) +#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ +#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk +#define DBGMCU_IDCODE_REV_ID_Pos (16U) +#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ +#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk + +/******************** Bit definition for DBGMCU_SCR register *****************/ +#define DBGMCU_SCR_DBG_STOP_Pos (1U) +#define DBGMCU_SCR_DBG_STOP_Msk (0x1UL << DBGMCU_SCR_DBG_STOP_Pos) /*!< 0x00000002 */ +#define DBGMCU_SCR_DBG_STOP DBGMCU_SCR_DBG_STOP_Msk +#define DBGMCU_SCR_DBG_STANDBY_Pos (2U) +#define DBGMCU_SCR_DBG_STANDBY_Msk (0x1UL << DBGMCU_SCR_DBG_STANDBY_Pos) /*!< 0x00000004 */ +#define DBGMCU_SCR_DBG_STANDBY DBGMCU_SCR_DBG_STANDBY_Msk +#define DBGMCU_SCR_DBG_LPMS_Pos (16U) +#define DBGMCU_SCR_DBG_LPMS_Msk (0x7UL << DBGMCU_SCR_DBG_LPMS_Pos) /*!< 0x00070000 */ +#define DBGMCU_SCR_DBG_LPMS DBGMCU_SCR_DBG_LPMS_Msk +#define DBGMCU_SCR_DBG_LPMS_0 (0x1UL << DBGMCU_SCR_DBG_LPMS_Pos) +#define DBGMCU_SCR_DBG_LPMS_1 (0x2UL << DBGMCU_SCR_DBG_LPMS_Pos) +#define DBGMCU_SCR_DBG_LPMS_2 (0x4UL << DBGMCU_SCR_DBG_LPMS_Pos) +#define DBGMCU_SCR_DBG_STOPF_Pos (19U) +#define DBGMCU_SCR_DBG_STOPF_Msk (0x1UL << DBGMCU_SCR_DBG_STOPF_Pos) /*!< 0x00080000 */ +#define DBGMCU_SCR_DBG_STOPF DBGMCU_SCR_DBG_STOPF_Msk +#define DBGMCU_SCR_DBG_SBF_Pos (20U) +#define DBGMCU_SCR_DBG_SBF_Msk (0x1UL << DBGMCU_SCR_DBG_SBF_Pos) /*!< 0x00100000 */ +#define DBGMCU_SCR_DBG_SBF DBGMCU_SCR_DBG_SBF_Msk +#define DBGMCU_SCR_DBG_CS_Pos (24U) +#define DBGMCU_SCR_DBG_CS_Msk (0x1UL << DBGMCU_SCR_DBG_CS_Pos) /*!< 0x01000000 */ +#define DBGMCU_SCR_DBG_CS DBGMCU_SCR_DBG_CS_Msk +#define DBGMCU_SCR_DBG_CDS_Pos (25U) +#define DBGMCU_SCR_DBG_CDS_Msk (0x1UL << DBGMCU_SCR_DBG_CDS_Pos) /*!< 0x02000000 */ +#define DBGMCU_SCR_DBG_CDS DBGMCU_SCR_DBG_CDS_Msk + +/******************** Bit definition for DBGMCU_APB1LFZR register ***********/ +#define DBGMCU_APB1LFZR_DBG_TIM2_STOP_Pos (0U) +#define DBGMCU_APB1LFZR_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_TIM2_STOP_Pos) +#define DBGMCU_APB1LFZR_DBG_TIM2_STOP DBGMCU_APB1LFZR_DBG_TIM2_STOP_Msk +#define DBGMCU_APB1LFZR_DBG_TIM3_STOP_Pos (1U) +#define DBGMCU_APB1LFZR_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_TIM3_STOP_Pos) +#define DBGMCU_APB1LFZR_DBG_TIM3_STOP DBGMCU_APB1LFZR_DBG_TIM3_STOP_Msk +#define DBGMCU_APB1LFZR_DBG_WWDG_STOP_Pos (11U) +#define DBGMCU_APB1LFZR_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_WWDG_STOP_Pos) +#define DBGMCU_APB1LFZR_DBG_WWDG_STOP DBGMCU_APB1LFZR_DBG_WWDG_STOP_Msk +#define DBGMCU_APB1LFZR_DBG_IWDG_STOP_Pos (12U) +#define DBGMCU_APB1LFZR_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_IWDG_STOP_Pos) +#define DBGMCU_APB1LFZR_DBG_IWDG_STOP DBGMCU_APB1LFZR_DBG_IWDG_STOP_Msk +#define DBGMCU_APB1LFZR_DBG_I2C1_STOP_Pos (21U) +#define DBGMCU_APB1LFZR_DBG_I2C1_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_I2C1_STOP_Pos) +#define DBGMCU_APB1LFZR_DBG_I2C1_STOP DBGMCU_APB1LFZR_DBG_I2C1_STOP_Msk + +/******************** Bit definition for DBGMCU_APB1HFZR register ***********/ +#define DBGMCU_APB1HFZR_DBG_LPTIM2_STOP_Pos (5U) +#define DBGMCU_APB1HFZR_DBG_LPTIM2_STOP_Msk (0x1UL << DBGMCU_APB1HFZR_DBG_LPTIM2_STOP_Pos) +#define DBGMCU_APB1HFZR_DBG_LPTIM2_STOP DBGMCU_APB1HFZR_DBG_LPTIM2_STOP_Msk + +/******************** Bit definition for DBGMCU_APB2FZR register ***********/ +#define DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos (11U) +#define DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos) +#define DBGMCU_APB2FZR_DBG_TIM1_STOP DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk +#define DBGMCU_APB2FZR_DBG_TIM16_STOP_Pos (17U) +#define DBGMCU_APB2FZR_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM16_STOP_Pos) +#define DBGMCU_APB2FZR_DBG_TIM16_STOP DBGMCU_APB2FZR_DBG_TIM16_STOP_Msk +#define DBGMCU_APB2FZR_DBG_TIM17_STOP_Pos (18U) +#define DBGMCU_APB2FZR_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM17_STOP_Pos) +#define DBGMCU_APB2FZR_DBG_TIM17_STOP DBGMCU_APB2FZR_DBG_TIM17_STOP_Msk + +/******************** Bit definition for DBGMCU_APB7FZR register ***********/ +#define DBGMCU_APB7FZR_DBG_I2C3_STOP_Pos (10U) +#define DBGMCU_APB7FZR_DBG_I2C3_STOP_Msk (0x1UL << DBGMCU_APB7FZR_DBG_I2C3_STOP_Pos) +#define DBGMCU_APB7FZR_DBG_I2C3_STOP DBGMCU_APB7FZR_DBG_I2C3_STOP_Msk +#define DBGMCU_APB7FZR_DBG_LPTIM1_STOP_Pos (17U) +#define DBGMCU_APB7FZR_DBG_LPTIM1_STOP_Msk (0x1UL << DBGMCU_APB7FZR_DBG_LPTIM1_STOP_Pos) +#define DBGMCU_APB7FZR_DBG_LPTIM1_STOP DBGMCU_APB7FZR_DBG_LPTIM1_STOP_Msk +#define DBGMCU_APB7FZR_DBG_RTC_STOP_Pos (30U) +#define DBGMCU_APB7FZR_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB7FZR_DBG_RTC_STOP_Pos) +#define DBGMCU_APB7FZR_DBG_RTC_STOP DBGMCU_APB7FZR_DBG_RTC_STOP_Msk + +/******************** Bit definition for DBGMCU_AHB1FZR register ***********/ +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP_Pos (0U) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP_Pos) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP_Msk +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP_Pos (1U) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP_Pos) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP_Msk +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP_Pos (2U) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP_Pos) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP_Msk +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP_Pos (3U) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP_Pos) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP_Msk +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP_Pos (4U) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP_Pos) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP_Msk +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP_Pos (5U) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP_Pos) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP_Msk +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP_Pos (6U) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP_Pos) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP_Msk +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP_Pos (7U) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP_Pos) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP_Msk + + +/******************************************************************************/ +/* */ +/* DMA Controller (DMA) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for DMA_SECCFGR register ****************/ +#define DMA_SECCFGR_SEC0_Pos (0U) +#define DMA_SECCFGR_SEC0_Msk (0x1UL << DMA_SECCFGR_SEC0_Pos) /*!< 0x00000001 */ +#define DMA_SECCFGR_SEC0 DMA_SECCFGR_SEC0_Msk /*!< Secure State of Channel 0 */ +#define DMA_SECCFGR_SEC1_Pos (1U) +#define DMA_SECCFGR_SEC1_Msk (0x1UL << DMA_SECCFGR_SEC1_Pos) /*!< 0x00000002 */ +#define DMA_SECCFGR_SEC1 DMA_SECCFGR_SEC1_Msk /*!< Secure State of Channel 1 */ +#define DMA_SECCFGR_SEC2_Pos (2U) +#define DMA_SECCFGR_SEC2_Msk (0x1UL << DMA_SECCFGR_SEC2_Pos) /*!< 0x00000004 */ +#define DMA_SECCFGR_SEC2 DMA_SECCFGR_SEC2_Msk /*!< Secure State of Channel 2 */ +#define DMA_SECCFGR_SEC3_Pos (3U) +#define DMA_SECCFGR_SEC3_Msk (0x1UL << DMA_SECCFGR_SEC3_Pos) /*!< 0x00000008 */ +#define DMA_SECCFGR_SEC3 DMA_SECCFGR_SEC3_Msk /*!< Secure State of Channel 3 */ +#define DMA_SECCFGR_SEC4_Pos (4U) +#define DMA_SECCFGR_SEC4_Msk (0x1UL << DMA_SECCFGR_SEC4_Pos) /*!< 0x00000010 */ +#define DMA_SECCFGR_SEC4 DMA_SECCFGR_SEC4_Msk /*!< Secure State of Channel 4 */ +#define DMA_SECCFGR_SEC5_Pos (5U) +#define DMA_SECCFGR_SEC5_Msk (0x1UL << DMA_SECCFGR_SEC5_Pos) /*!< 0x00000020 */ +#define DMA_SECCFGR_SEC5 DMA_SECCFGR_SEC5_Msk /*!< Secure State of Channel 5 */ +#define DMA_SECCFGR_SEC6_Pos (6U) +#define DMA_SECCFGR_SEC6_Msk (0x1UL << DMA_SECCFGR_SEC6_Pos) /*!< 0x00000040 */ +#define DMA_SECCFGR_SEC6 DMA_SECCFGR_SEC6_Msk /*!< Secure State of Channel 6 */ +#define DMA_SECCFGR_SEC7_Pos (7U) +#define DMA_SECCFGR_SEC7_Msk (0x1UL << DMA_SECCFGR_SEC7_Pos) /*!< 0x00000080 */ +#define DMA_SECCFGR_SEC7 DMA_SECCFGR_SEC7_Msk /*!< Secure State of Channel 7 */ + +/******************* Bit definition for DMA_PRIVCFGR register ****************/ +#define DMA_PRIVCFGR_PRIV0_Pos (0U) +#define DMA_PRIVCFGR_PRIV0_Msk (0x1UL << DMA_PRIVCFGR_PRIV0_Pos) /*!< 0x00000001 */ +#define DMA_PRIVCFGR_PRIV0 DMA_PRIVCFGR_PRIV0_Msk /*!< Privileged State of Channel 0 */ +#define DMA_PRIVCFGR_PRIV1_Pos (1U) +#define DMA_PRIVCFGR_PRIV1_Msk (0x1UL << DMA_PRIVCFGR_PRIV1_Pos) /*!< 0x00000002 */ +#define DMA_PRIVCFGR_PRIV1 DMA_PRIVCFGR_PRIV1_Msk /*!< Privileged State of Channel 1 */ +#define DMA_PRIVCFGR_PRIV2_Pos (2U) +#define DMA_PRIVCFGR_PRIV2_Msk (0x1UL << DMA_PRIVCFGR_PRIV2_Pos) /*!< 0x00000004 */ +#define DMA_PRIVCFGR_PRIV2 DMA_PRIVCFGR_PRIV2_Msk /*!< Privileged State of Channel 2 */ +#define DMA_PRIVCFGR_PRIV3_Pos (3U) +#define DMA_PRIVCFGR_PRIV3_Msk (0x1UL << DMA_PRIVCFGR_PRIV3_Pos) /*!< 0x00000008 */ +#define DMA_PRIVCFGR_PRIV3 DMA_PRIVCFGR_PRIV3_Msk /*!< Privileged State of Channel 3 */ +#define DMA_PRIVCFGR_PRIV4_Pos (4U) +#define DMA_PRIVCFGR_PRIV4_Msk (0x1UL << DMA_PRIVCFGR_PRIV4_Pos) /*!< 0x00000010 */ +#define DMA_PRIVCFGR_PRIV4 DMA_PRIVCFGR_PRIV4_Msk /*!< Privileged State of Channel 4 */ +#define DMA_PRIVCFGR_PRIV5_Pos (5U) +#define DMA_PRIVCFGR_PRIV5_Msk (0x1UL << DMA_PRIVCFGR_PRIV5_Pos) /*!< 0x00000020 */ +#define DMA_PRIVCFGR_PRIV5 DMA_PRIVCFGR_PRIV5_Msk /*!< Privileged State of Channel 5 */ +#define DMA_PRIVCFGR_PRIV6_Pos (6U) +#define DMA_PRIVCFGR_PRIV6_Msk (0x1UL << DMA_PRIVCFGR_PRIV6_Pos) /*!< 0x00000040 */ +#define DMA_PRIVCFGR_PRIV6 DMA_PRIVCFGR_PRIV6_Msk /*!< Privileged State of Channel 6 */ +#define DMA_PRIVCFGR_PRIV7_Pos (7U) +#define DMA_PRIVCFGR_PRIV7_Msk (0x1UL << DMA_PRIVCFGR_PRIV7_Pos) /*!< 0x00000080 */ +#define DMA_PRIVCFGR_PRIV7 DMA_PRIVCFGR_PRIV7_Msk /*!< Privileged State of Channel 7 */ + +/******************* Bit definition for DMA_RCFGLOCKR register ****************/ +#define DMA_RCFGLOCKR_LOCK0_Pos (0U) +#define DMA_RCFGLOCKR_LOCK0_Msk (0x1UL << DMA_RCFGLOCKR_LOCK0_Pos) /*!< 0x00000001 */ +#define DMA_RCFGLOCKR_LOCK0 DMA_RCFGLOCKR_LOCK0_Msk /*!< Privileged and Secure State Lock of Channel 0 */ +#define DMA_RCFGLOCKR_LOCK1_Pos (1U) +#define DMA_RCFGLOCKR_LOCK1_Msk (0x1UL << DMA_RCFGLOCKR_LOCK1_Pos) /*!< 0x00000002 */ +#define DMA_RCFGLOCKR_LOCK1 DMA_RCFGLOCKR_LOCK1_Msk /*!< Privileged and Secure State Lock of Channel 1 */ +#define DMA_RCFGLOCKR_LOCK2_Pos (2U) +#define DMA_RCFGLOCKR_LOCK2_Msk (0x1UL << DMA_RCFGLOCKR_LOCK2_Pos) /*!< 0x00000004 */ +#define DMA_RCFGLOCKR_LOCK2 DMA_RCFGLOCKR_LOCK2_Msk /*!< Privileged and Secure State Lock of Channel 2 */ +#define DMA_RCFGLOCKR_LOCK3_Pos (3U) +#define DMA_RCFGLOCKR_LOCK3_Msk (0x1UL << DMA_RCFGLOCKR_LOCK3_Pos) /*!< 0x00000008 */ +#define DMA_RCFGLOCKR_LOCK3 DMA_RCFGLOCKR_LOCK3_Msk /*!< Privileged and Secure State Lock of Channel 3 */ +#define DMA_RCFGLOCKR_LOCK4_Pos (4U) +#define DMA_RCFGLOCKR_LOCK4_Msk (0x1UL << DMA_RCFGLOCKR_LOCK4_Pos) /*!< 0x00000010 */ +#define DMA_RCFGLOCKR_LOCK4 DMA_RCFGLOCKR_LOCK4_Msk /*!< Privileged and Secure State Lock of Channel 4 */ +#define DMA_RCFGLOCKR_LOCK5_Pos (5U) +#define DMA_RCFGLOCKR_LOCK5_Msk (0x1UL << DMA_RCFGLOCKR_LOCK5_Pos) /*!< 0x00000020 */ +#define DMA_RCFGLOCKR_LOCK5 DMA_RCFGLOCKR_LOCK5_Msk /*!< Privileged and Secure State Lock of Channel 5 */ +#define DMA_RCFGLOCKR_LOCK6_Pos (6U) +#define DMA_RCFGLOCKR_LOCK6_Msk (0x1UL << DMA_RCFGLOCKR_LOCK6_Pos) /*!< 0x00000040 */ +#define DMA_RCFGLOCKR_LOCK6 DMA_RCFGLOCKR_LOCK6_Msk /*!< Privileged and Secure State Lock of Channel 6 */ +#define DMA_RCFGLOCKR_LOCK7_Pos (7U) +#define DMA_RCFGLOCKR_LOCK7_Msk (0x1UL << DMA_RCFGLOCKR_LOCK7_Pos) /*!< 0x00000080 */ +#define DMA_RCFGLOCKR_LOCK7 DMA_RCFGLOCKR_LOCK7_Msk /*!< Privileged and Secure State Lock of Channel 7 */ + +/******************* Bit definition for DMA_MISR register ****************/ +#define DMA_MISR_MIS0_Pos (0U) +#define DMA_MISR_MIS0_Msk (0x1UL << DMA_MISR_MIS0_Pos) /*!< 0x00000001 */ +#define DMA_MISR_MIS0 DMA_MISR_MIS0_Msk /*!< Masked Interrupt State of Non-Secure Channel 0 */ +#define DMA_MISR_MIS1_Pos (1U) +#define DMA_MISR_MIS1_Msk (0x1UL << DMA_MISR_MIS1_Pos) /*!< 0x00000002 */ +#define DMA_MISR_MIS1 DMA_MISR_MIS1_Msk /*!< Masked Interrupt State of Non-Secure Channel 1 */ +#define DMA_MISR_MIS2_Pos (2U) +#define DMA_MISR_MIS2_Msk (0x1UL << DMA_MISR_MIS2_Pos) /*!< 0x00000004 */ +#define DMA_MISR_MIS2 DMA_MISR_MIS2_Msk /*!< Masked Interrupt State of Non-Secure Channel 2 */ +#define DMA_MISR_MIS3_Pos (3U) +#define DMA_MISR_MIS3_Msk (0x1UL << DMA_MISR_MIS3_Pos) /*!< 0x00000008 */ +#define DMA_MISR_MIS3 DMA_MISR_MIS3_Msk /*!< Masked Interrupt State of Non-Secure Channel 3 */ +#define DMA_MISR_MIS4_Pos (4U) +#define DMA_MISR_MIS4_Msk (0x1UL << DMA_MISR_MIS4_Pos) /*!< 0x00000010 */ +#define DMA_MISR_MIS4 DMA_MISR_MIS4_Msk /*!< Masked Interrupt State of Non-Secure Channel 4 */ +#define DMA_MISR_MIS5_Pos (5U) +#define DMA_MISR_MIS5_Msk (0x1UL << DMA_MISR_MIS5_Pos) /*!< 0x00000020 */ +#define DMA_MISR_MIS5 DMA_MISR_MIS5_Msk /*!< Masked Interrupt State of Non-Secure Channel 5 */ +#define DMA_MISR_MIS6_Pos (6U) +#define DMA_MISR_MIS6_Msk (0x1UL << DMA_MISR_MIS6_Pos) /*!< 0x00000040 */ +#define DMA_MISR_MIS6 DMA_MISR_MIS6_Msk /*!< Masked Interrupt State of Non-Secure Channel 6 */ +#define DMA_MISR_MIS7_Pos (7U) +#define DMA_MISR_MIS7_Msk (0x1UL << DMA_MISR_MIS7_Pos) /*!< 0x00000080 */ +#define DMA_MISR_MIS7 DMA_MISR_MIS7_Msk /*!< Masked Interrupt State of Non-Secure Channel 7 */ + +/******************* Bit definition for DMA_SMISR register ****************/ +#define DMA_SMISR_MIS0_Pos (0U) +#define DMA_SMISR_MIS0_Msk (0x1UL << DMA_SMISR_MIS0_Pos) /*!< 0x00000001 */ +#define DMA_SMISR_MIS0 DMA_SMISR_MIS0_Msk /*!< Masked Interrupt State of Secure Channel 0 */ +#define DMA_SMISR_MIS1_Pos (1U) +#define DMA_SMISR_MIS1_Msk (0x1UL << DMA_SMISR_MIS1_Pos) /*!< 0x00000002 */ +#define DMA_SMISR_MIS1 DMA_SMISR_MIS1_Msk /*!< Masked Interrupt State of Secure Channel 1 */ +#define DMA_SMISR_MIS2_Pos (2U) +#define DMA_SMISR_MIS2_Msk (0x1UL << DMA_SMISR_MIS2_Pos) /*!< 0x00000004 */ +#define DMA_SMISR_MIS2 DMA_SMISR_MIS2_Msk /*!< Masked Interrupt State of Secure Channel 2 */ +#define DMA_SMISR_MIS3_Pos (3U) +#define DMA_SMISR_MIS3_Msk (0x1UL << DMA_SMISR_MIS3_Pos) /*!< 0x00000008 */ +#define DMA_SMISR_MIS3 DMA_SMISR_MIS3_Msk /*!< Masked Interrupt State of Secure Channel 3 */ +#define DMA_SMISR_MIS4_Pos (4U) +#define DMA_SMISR_MIS4_Msk (0x1UL << DMA_SMISR_MIS4_Pos) /*!< 0x00000010 */ +#define DMA_SMISR_MIS4 DMA_SMISR_MIS4_Msk /*!< Masked Interrupt State of Secure Channel 4 */ +#define DMA_SMISR_MIS5_Pos (5U) +#define DMA_SMISR_MIS5_Msk (0x1UL << DMA_SMISR_MIS5_Pos) /*!< 0x00000020 */ +#define DMA_SMISR_MIS5 DMA_SMISR_MIS5_Msk /*!< Masked Interrupt State of Secure Channel 5 */ +#define DMA_SMISR_MIS6_Pos (6U) +#define DMA_SMISR_MIS6_Msk (0x1UL << DMA_SMISR_MIS6_Pos) /*!< 0x00000040 */ +#define DMA_SMISR_MIS6 DMA_SMISR_MIS6_Msk /*!< Masked Interrupt State of Secure Channel 6 */ +#define DMA_SMISR_MIS7_Pos (7U) +#define DMA_SMISR_MIS7_Msk (0x1UL << DMA_SMISR_MIS7_Pos) /*!< 0x00000080 */ +#define DMA_SMISR_MIS7 DMA_SMISR_MIS7_Msk /*!< Masked Interrupt State of Secure Channel 7 */ + +/******************* Bit definition for DMA_CLBAR register ****************/ +#define DMA_CLBAR_LBA_Pos (16U) +#define DMA_CLBAR_LBA_Msk (0xFFFFUL << DMA_CLBAR_LBA_Pos) /*!< 0xFFFF0000 */ +#define DMA_CLBAR_LBA DMA_CLBAR_LBA_Msk /*!< Linked-list Base Address of DMA channel x */ + +/******************* Bit definition for DMA_CFCR register *******************/ +#define DMA_CFCR_TCF_Pos (8U) +#define DMA_CFCR_TCF_Msk (0x1UL << DMA_CFCR_TCF_Pos) /*!< 0x00000100 */ +#define DMA_CFCR_TCF DMA_CFCR_TCF_Msk /*!< Transfer complete flag clear */ +#define DMA_CFCR_HTF_Pos (9U) +#define DMA_CFCR_HTF_Msk (0x1UL << DMA_CFCR_HTF_Pos) /*!< 0x00000200 */ +#define DMA_CFCR_HTF DMA_CFCR_HTF_Msk /*!< Half transfer complete flag clear */ +#define DMA_CFCR_DTEF_Pos (10U) +#define DMA_CFCR_DTEF_Msk (0x1UL << DMA_CFCR_DTEF_Pos) /*!< 0x00000400 */ +#define DMA_CFCR_DTEF DMA_CFCR_DTEF_Msk /*!< Data transfer error flag clear */ +#define DMA_CFCR_ULEF_Pos (11U) +#define DMA_CFCR_ULEF_Msk (0x1UL << DMA_CFCR_ULEF_Pos) /*!< 0x00000800 */ +#define DMA_CFCR_ULEF DMA_CFCR_ULEF_Msk /*!< Update linked-list item error flag clear */ +#define DMA_CFCR_USEF_Pos (12U) +#define DMA_CFCR_USEF_Msk (0x1UL << DMA_CFCR_USEF_Pos) /*!< 0x00001000 */ +#define DMA_CFCR_USEF DMA_CFCR_USEF_Msk /*!< User setting error flag clear */ +#define DMA_CFCR_SUSPF_Pos (13U) +#define DMA_CFCR_SUSPF_Msk (0x1UL << DMA_CFCR_SUSPF_Pos) /*!< 0x00002000 */ +#define DMA_CFCR_SUSPF DMA_CFCR_SUSPF_Msk /*!< Completed suspension flag clear */ +#define DMA_CFCR_TOF_Pos (14U) +#define DMA_CFCR_TOF_Msk (0x1UL << DMA_CFCR_TOF_Pos) /*!< 0x00004000 */ +#define DMA_CFCR_TOF DMA_CFCR_TOF_Msk /*!< Trigger overrun flag clear */ + +/******************* Bit definition for DMA_CSR register *******************/ +#define DMA_CSR_IDLEF_Pos (0U) +#define DMA_CSR_IDLEF_Msk (0x1UL << DMA_CSR_IDLEF_Pos) /*!< 0x00000001 */ +#define DMA_CSR_IDLEF DMA_CSR_IDLEF_Msk /*!< Idle flag */ +#define DMA_CSR_TCF_Pos (8U) +#define DMA_CSR_TCF_Msk (0x1UL << DMA_CSR_TCF_Pos) /*!< 0x00000100 */ +#define DMA_CSR_TCF DMA_CSR_TCF_Msk /*!< Transfer complete flag */ +#define DMA_CSR_HTF_Pos (9U) +#define DMA_CSR_HTF_Msk (0x1UL << DMA_CSR_HTF_Pos) /*!< 0x00000200 */ +#define DMA_CSR_HTF DMA_CSR_HTF_Msk /*!< Half transfer complete flag */ +#define DMA_CSR_DTEF_Pos (10U) +#define DMA_CSR_DTEF_Msk (0x1UL << DMA_CSR_DTEF_Pos) /*!< 0x00000400 */ +#define DMA_CSR_DTEF DMA_CSR_DTEF_Msk /*!< Data transfer error flag */ +#define DMA_CSR_ULEF_Pos (11U) +#define DMA_CSR_ULEF_Msk (0x1UL << DMA_CSR_ULEF_Pos) /*!< 0x00000800 */ +#define DMA_CSR_ULEF DMA_CSR_ULEF_Msk /*!< Update linked-list item error flag */ +#define DMA_CSR_USEF_Pos (12U) +#define DMA_CSR_USEF_Msk (0x1UL << DMA_CSR_USEF_Pos) /*!< 0x00001000 */ +#define DMA_CSR_USEF DMA_CSR_USEF_Msk /*!< User setting error flag */ +#define DMA_CSR_SUSPF_Pos (13U) +#define DMA_CSR_SUSPF_Msk (0x1UL << DMA_CSR_SUSPF_Pos) /*!< 0x00002000 */ +#define DMA_CSR_SUSPF DMA_CSR_SUSPF_Msk /*!< User setting error flag */ +#define DMA_CSR_TOF_Pos (14U) +#define DMA_CSR_TOF_Msk (0x1UL << DMA_CSR_TOF_Pos) /*!< 0x00004000 */ +#define DMA_CSR_TOF DMA_CSR_TOF_Msk /*!< Trigger overrun event flag */ +#define DMA_CSR_FIFOL_Pos (16U) +#define DMA_CSR_FIFOL_Msk (0xFFUL << DMA_CSR_FIFOL_Pos) /*!< 0x00FF0000 */ +#define DMA_CSR_FIFOL DMA_CSR_FIFOL_Msk /*!< Monitored FIFO level in bytes */ + +/******************* Bit definition for DMA_CCR register ********************/ +#define DMA_CCR_EN_Pos (0U) +#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */ +#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ +#define DMA_CCR_RESET_Pos (1U) +#define DMA_CCR_RESET_Msk (0x1UL << DMA_CCR_RESET_Pos) /*!< 0x00000002 */ +#define DMA_CCR_RESET DMA_CCR_RESET_Msk /*!< Channel reset */ +#define DMA_CCR_SUSP_Pos (2U) +#define DMA_CCR_SUSP_Msk (0x1UL << DMA_CCR_SUSP_Pos) /*!< 0x00000004 */ +#define DMA_CCR_SUSP DMA_CCR_SUSP_Msk /*!< Channel suspend */ +#define DMA_CCR_TCIE_Pos (8U) +#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000100 */ +#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ +#define DMA_CCR_HTIE_Pos (9U) +#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000200 */ +#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half transfer complete interrupt enable */ +#define DMA_CCR_DTEIE_Pos (10U) +#define DMA_CCR_DTEIE_Msk (0x1UL << DMA_CCR_DTEIE_Pos) /*!< 0x00000400 */ +#define DMA_CCR_DTEIE DMA_CCR_DTEIE_Msk /*!< Data transfer error interrupt enable */ +#define DMA_CCR_ULEIE_Pos (11U) +#define DMA_CCR_ULEIE_Msk (0x1UL << DMA_CCR_ULEIE_Pos) /*!< 0x00000800 */ +#define DMA_CCR_ULEIE DMA_CCR_ULEIE_Msk /*!< Update linked-list item error interrupt enable */ +#define DMA_CCR_USEIE_Pos (12U) +#define DMA_CCR_USEIE_Msk (0x1UL << DMA_CCR_USEIE_Pos) /*!< 0x00001000 */ +#define DMA_CCR_USEIE DMA_CCR_USEIE_Msk /*!< User setting error interrupt enable */ +#define DMA_CCR_SUSPIE_Pos (13U) +#define DMA_CCR_SUSPIE_Msk (0x1UL << DMA_CCR_SUSPIE_Pos) /*!< 0x00002000 */ +#define DMA_CCR_SUSPIE DMA_CCR_SUSPIE_Msk /*!< Completed suspension interrupt enable */ +#define DMA_CCR_TOIE_Pos (14U) +#define DMA_CCR_TOIE_Msk (0x1UL << DMA_CCR_TOIE_Pos) /*!< 0x00004000 */ +#define DMA_CCR_TOIE DMA_CCR_TOIE_Msk /*!< Trigger overrun interrupt enable */ +#define DMA_CCR_LSM_Pos (16U) +#define DMA_CCR_LSM_Msk (0x1UL << DMA_CCR_LSM_Pos) /*!< 0x00010000 */ +#define DMA_CCR_LSM DMA_CCR_LSM_Msk /*!< Link step mode */ +#define DMA_CCR_LAP_Pos (17U) +#define DMA_CCR_LAP_Msk (0x1UL << DMA_CCR_LAP_Pos) /*!< 0x00020000 */ +#define DMA_CCR_LAP DMA_CCR_LAP_Msk /*!< Linked-list allocated port */ +#define DMA_CCR_PRIO_Pos (22U) +#define DMA_CCR_PRIO_Msk (0x3UL << DMA_CCR_PRIO_Pos) /*!< 0x00C00000 */ +#define DMA_CCR_PRIO DMA_CCR_PRIO_Msk /*!< Priority level */ +#define DMA_CCR_PRIO_0 (0x1UL << DMA_CCR_PRIO_Pos) /*!< 0x00400000 */ +#define DMA_CCR_PRIO_1 (0x2UL << DMA_CCR_PRIO_Pos) /*!< 0x00800000 */ + +/******************* Bit definition for DMA_CTR1 register *******************/ +#define DMA_CTR1_SDW_LOG2_Pos (0U) +#define DMA_CTR1_SDW_LOG2_Msk (0x3UL << DMA_CTR1_SDW_LOG2_Pos) /*!< 0x00000003 */ +#define DMA_CTR1_SDW_LOG2 DMA_CTR1_SDW_LOG2_Msk /*!< Binary logarithm of the source data width of a burst */ +#define DMA_CTR1_SDW_LOG2_0 (0x1UL << DMA_CTR1_SDW_LOG2_Pos) /*!< Bit 0 */ +#define DMA_CTR1_SDW_LOG2_1 (0x2UL << DMA_CTR1_SDW_LOG2_Pos) /*!< Bit 1 */ +#define DMA_CTR1_SINC_Pos (3U) +#define DMA_CTR1_SINC_Msk (0x1UL << DMA_CTR1_SINC_Pos) /*!< 0x00000008 */ +#define DMA_CTR1_SINC DMA_CTR1_SINC_Msk /*!< Source incrementing burst */ +#define DMA_CTR1_SBL_1_Pos (4U) +#define DMA_CTR1_SBL_1_Msk (0x3FUL << DMA_CTR1_SBL_1_Pos) /*!< 0x000003F0 */ +#define DMA_CTR1_SBL_1 DMA_CTR1_SBL_1_Msk /*!< Source burst length minus 1 */ +#define DMA_CTR1_PAM_Pos (11U) +#define DMA_CTR1_PAM_Msk (0x3UL << DMA_CTR1_PAM_Pos) /*!< 0x0001800 */ +#define DMA_CTR1_PAM DMA_CTR1_PAM_Msk /*!< Padding / alignment mode */ +#define DMA_CTR1_PAM_0 (0x1UL << DMA_CTR1_PAM_Pos) /*!< Bit 0 */ +#define DMA_CTR1_PAM_1 (0x2UL << DMA_CTR1_PAM_Pos) /*!< Bit 1 */ +#define DMA_CTR1_SBX_Pos (13U) +#define DMA_CTR1_SBX_Msk (0x1UL << DMA_CTR1_SBX_Pos) /*!< 0x00002000 */ +#define DMA_CTR1_SBX DMA_CTR1_SBX_Msk /*!< Source byte exchange within the unaligned half-word of each source word */ +#define DMA_CTR1_SAP_Pos (14U) +#define DMA_CTR1_SAP_Msk (0x1UL << DMA_CTR1_SAP_Pos) /*!< 0x00004000 */ +#define DMA_CTR1_SAP DMA_CTR1_SAP_Msk /*!< Source allocated port */ +#define DMA_CTR1_SSEC_Pos (15U) +#define DMA_CTR1_SSEC_Msk (0x1UL << DMA_CTR1_SSEC_Pos) /*!< 0x00008000 */ +#define DMA_CTR1_SSEC DMA_CTR1_SSEC_Msk /*!< Security attribute of the DMA transfer from the source */ +#define DMA_CTR1_DDW_LOG2_Pos (16U) +#define DMA_CTR1_DDW_LOG2_Msk (0x3UL << DMA_CTR1_DDW_LOG2_Pos) /*!< 0x00030000 */ +#define DMA_CTR1_DDW_LOG2 DMA_CTR1_DDW_LOG2_Msk /*!< Binary logarithm of the destination data width of a burst */ +#define DMA_CTR1_DDW_LOG2_0 (0x1UL << DMA_CTR1_DDW_LOG2_Pos) /*!< Bit 0 */ +#define DMA_CTR1_DDW_LOG2_1 (0x2UL << DMA_CTR1_DDW_LOG2_Pos) /*!< Bit 1 */ +#define DMA_CTR1_DINC_Pos (19U) +#define DMA_CTR1_DINC_Msk (0x1UL << DMA_CTR1_DINC_Pos) /*!< 0x00080000 */ +#define DMA_CTR1_DINC DMA_CTR1_DINC_Msk /*!< Destination incrementing burst */ +#define DMA_CTR1_DBL_1_Pos (20U) +#define DMA_CTR1_DBL_1_Msk (0x3FUL << DMA_CTR1_DBL_1_Pos) /*!< 0x03F00000 */ +#define DMA_CTR1_DBL_1 DMA_CTR1_DBL_1_Msk /*!< Destination burst length minus 1 */ +#define DMA_CTR1_DBX_Pos (26U) +#define DMA_CTR1_DBX_Msk (0x1UL << DMA_CTR1_DBX_Pos) /*!< 0x04000000 */ +#define DMA_CTR1_DBX DMA_CTR1_DBX_Msk /*!< Destination byte exchange */ +#define DMA_CTR1_DHX_Pos (27U) +#define DMA_CTR1_DHX_Msk (0x1UL << DMA_CTR1_DHX_Pos) /*!< 0x08000000 */ +#define DMA_CTR1_DHX DMA_CTR1_DHX_Msk /*!< Destination half-word exchange */ +#define DMA_CTR1_DAP_Pos (30U) +#define DMA_CTR1_DAP_Msk (0x1UL << DMA_CTR1_DAP_Pos) /*!< 0x40000000 */ +#define DMA_CTR1_DAP DMA_CTR1_DAP_Msk /*!< Destination allocated port */ +#define DMA_CTR1_DSEC_Pos (31U) +#define DMA_CTR1_DSEC_Msk (0x1UL << DMA_CTR1_DSEC_Pos) /*!< 0x80000000 */ +#define DMA_CTR1_DSEC DMA_CTR1_DSEC_Msk /*!< Security attribute of the DMA transfer from the destination */ + +/****************** Bit definition for DMA_CTR2 register *******************/ +#define DMA_CTR2_REQSEL_Pos (0U) +#define DMA_CTR2_REQSEL_Msk (0x3FUL << DMA_CTR2_REQSEL_Pos) /*!< 0x0000003F */ +#define DMA_CTR2_REQSEL DMA_CTR2_REQSEL_Msk /*!< DMA hardware request selection */ +#define DMA_CTR2_SWREQ_Pos (9U) +#define DMA_CTR2_SWREQ_Msk (0x1UL << DMA_CTR2_SWREQ_Pos) /*!< 0x00000100 */ +#define DMA_CTR2_SWREQ DMA_CTR2_SWREQ_Msk /*!< Software request */ +#define DMA_CTR2_DREQ_Pos (10U) +#define DMA_CTR2_DREQ_Msk (0x1UL << DMA_CTR2_DREQ_Pos) /*!< 0x00000100 */ +#define DMA_CTR2_DREQ DMA_CTR2_DREQ_Msk /*!< Destination hardware request */ +#define DMA_CTR2_BREQ_Pos (11U) +#define DMA_CTR2_BREQ_Msk (0x1UL << DMA_CTR2_BREQ_Pos) /*!< 0x00000200 */ +#define DMA_CTR2_BREQ DMA_CTR2_BREQ_Msk /*!< Block hardware request */ +#define DMA_CTR2_TRIGM_Pos (14U) +#define DMA_CTR2_TRIGM_Msk (0x3UL << DMA_CTR2_TRIGM_Pos) /*!< 0x0000C000 */ +#define DMA_CTR2_TRIGM DMA_CTR2_TRIGM_Msk /*!< Trigger mode */ +#define DMA_CTR2_TRIGM_0 (0x1UL << DMA_CTR2_TRIGM_Pos) /*!< Bit 0 */ +#define DMA_CTR2_TRIGM_1 (0x2UL << DMA_CTR2_TRIGM_Pos) /*!< Bit 1 */ +#define DMA_CTR2_TRIGSEL_Pos (16U) +#define DMA_CTR2_TRIGSEL_Msk (0x1FUL << DMA_CTR2_TRIGSEL_Pos) /*!< 0x001F0000 */ +#define DMA_CTR2_TRIGSEL DMA_CTR2_TRIGSEL_Msk /*!< Trigger event input selection */ +#define DMA_CTR2_TRIGPOL_Pos (24U) +#define DMA_CTR2_TRIGPOL_Msk (0x3UL << DMA_CTR2_TRIGPOL_Pos) /*!< 0x03000000 */ +#define DMA_CTR2_TRIGPOL DMA_CTR2_TRIGPOL_Msk /*!< Trigger event polarity */ +#define DMA_CTR2_TRIGPOL_0 (0x1UL << DMA_CTR2_TRIGPOL_Pos) /*!< Bit 0 */ +#define DMA_CTR2_TRIGPOL_1 (0x2UL << DMA_CTR2_TRIGPOL_Pos) /*!< Bit 1 */ +#define DMA_CTR2_TCEM_Pos (30U) +#define DMA_CTR2_TCEM_Msk (0x3UL << DMA_CTR2_TCEM_Pos) /*!< 0xC0000000 */ +#define DMA_CTR2_TCEM DMA_CTR2_TCEM_Msk /*!< Transfer complete event mode */ +#define DMA_CTR2_TCEM_0 (0x1UL << DMA_CTR2_TCEM_Pos) /*!< Bit 0 */ +#define DMA_CTR2_TCEM_1 (0x2UL << DMA_CTR2_TCEM_Pos) /*!< Bit 1 */ + +/****************** Bit definition for DMA_CBR1 register *******************/ +#define DMA_CBR1_BNDT_Pos (0U) +#define DMA_CBR1_BNDT_Msk (0xFFFFUL << DMA_CBR1_BNDT_Pos) /*!< 0x0000FFFF */ +#define DMA_CBR1_BNDT DMA_CBR1_BNDT_Msk /*!< Block number of data bytes to transfer from the source */ + +/****************** Bit definition for DMA_CSAR register ********************/ +#define DMA_CSAR_SA_Pos (0U) +#define DMA_CSAR_SA_Msk (0xFFFFFFFFUL << DMA_CSAR_SA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CSAR_SA DMA_CSAR_SA_Msk /*!< Source Address */ + +/****************** Bit definition for DMA_CDAR register *******************/ +#define DMA_CDAR_DA_Pos (0U) +#define DMA_CDAR_DA_Msk (0xFFFFFFFFUL << DMA_CDAR_DA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CDAR_DA DMA_CDAR_DA_Msk /*!< Destination address */ + +/****************** Bit definition for DMA_CLLR register *******************/ +#define DMA_CLLR_LA_Pos (2U) +#define DMA_CLLR_LA_Msk (0x3FFFUL << DMA_CLLR_LA_Pos) /*!< 0x0000FFFC */ +#define DMA_CLLR_LA DMA_CLLR_LA_Msk /*!< Pointer to the next linked-list data structure */ +#define DMA_CLLR_ULL_Pos (16U) +#define DMA_CLLR_ULL_Msk (0x1UL << DMA_CLLR_ULL_Pos) /*!< 0x00010000 */ +#define DMA_CLLR_ULL DMA_CLLR_ULL_Msk /*!< Update link address register from memory */ +#define DMA_CLLR_UDA_Pos (27U) +#define DMA_CLLR_UDA_Msk (0x1UL << DMA_CLLR_UDA_Pos) /*!< 0x08000000 */ +#define DMA_CLLR_UDA DMA_CLLR_UDA_Msk /*!< Update destination address register from SRAM */ +#define DMA_CLLR_USA_Pos (28U) +#define DMA_CLLR_USA_Msk (0x1UL << DMA_CLLR_USA_Pos) /*!< 0x10000000 */ +#define DMA_CLLR_USA DMA_CLLR_USA_Msk /*!< Update source address register from SRAM */ +#define DMA_CLLR_UB1_Pos (29U) +#define DMA_CLLR_UB1_Msk (0x1UL << DMA_CLLR_UB1_Pos) /*!< 0x20000000 */ +#define DMA_CLLR_UB1 DMA_CLLR_UB1_Msk /*!< Update block register 1 from SRAM */ +#define DMA_CLLR_UT2_Pos (30U) +#define DMA_CLLR_UT2_Msk (0x1UL << DMA_CLLR_UT2_Pos) /*!< 0x40000000 */ +#define DMA_CLLR_UT2 DMA_CLLR_UT2_Msk /*!< Update transfer register 2 from SRAM */ +#define DMA_CLLR_UT1_Pos (31U) +#define DMA_CLLR_UT1_Msk (0x1UL << DMA_CLLR_UT1_Pos) /*!< 0x80000000 */ +#define DMA_CLLR_UT1 DMA_CLLR_UT1_Msk /*!< Update transfer register 1 from SRAM */ + +/******************************************************************************/ +/* */ +/* External Interrupt/Event Controller */ +/* */ +/******************************************************************************/ +/****************** Bit definition for EXTI_RTSR1 register ******************/ +#define EXTI_RTSR1_RT0_Pos (0U) +#define EXTI_RTSR1_RT0_Msk (0x1UL << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */ +#define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger configuration for input line 0 */ +#define EXTI_RTSR1_RT1_Pos (1U) +#define EXTI_RTSR1_RT1_Msk (0x1UL << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */ +#define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger configuration for input line 1 */ +#define EXTI_RTSR1_RT2_Pos (2U) +#define EXTI_RTSR1_RT2_Msk (0x1UL << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */ +#define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger configuration for input line 2 */ +#define EXTI_RTSR1_RT3_Pos (3U) +#define EXTI_RTSR1_RT3_Msk (0x1UL << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */ +#define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger configuration for input line 3 */ +#define EXTI_RTSR1_RT4_Pos (4U) +#define EXTI_RTSR1_RT4_Msk (0x1UL << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */ +#define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger configuration for input line 4 */ +#define EXTI_RTSR1_RT5_Pos (5U) +#define EXTI_RTSR1_RT5_Msk (0x1UL << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */ +#define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger configuration for input line 5 */ +#define EXTI_RTSR1_RT6_Pos (6U) +#define EXTI_RTSR1_RT6_Msk (0x1UL << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */ +#define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger configuration for input line 6 */ +#define EXTI_RTSR1_RT7_Pos (7U) +#define EXTI_RTSR1_RT7_Msk (0x1UL << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */ +#define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger configuration for input line 7 */ +#define EXTI_RTSR1_RT8_Pos (8U) +#define EXTI_RTSR1_RT8_Msk (0x1UL << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */ +#define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger configuration for input line 8 */ +#define EXTI_RTSR1_RT9_Pos (9U) +#define EXTI_RTSR1_RT9_Msk (0x1UL << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */ +#define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger configuration for input line 9 */ +#define EXTI_RTSR1_RT10_Pos (10U) +#define EXTI_RTSR1_RT10_Msk (0x1UL << EXTI_RTSR1_RT10_Pos) /*!< 0x00000400 */ +#define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk /*!< Rising trigger configuration for input line 10 */ +#define EXTI_RTSR1_RT11_Pos (11U) +#define EXTI_RTSR1_RT11_Msk (0x1UL << EXTI_RTSR1_RT11_Pos) /*!< 0x00000800 */ +#define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk /*!< Rising trigger configuration for input line 11 */ +#define EXTI_RTSR1_RT12_Pos (12U) +#define EXTI_RTSR1_RT12_Msk (0x1UL << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */ +#define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger configuration for input line 12 */ +#define EXTI_RTSR1_RT13_Pos (13U) +#define EXTI_RTSR1_RT13_Msk (0x1UL << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */ +#define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger configuration for input line 13 */ +#define EXTI_RTSR1_RT14_Pos (14U) +#define EXTI_RTSR1_RT14_Msk (0x1UL << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */ +#define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger configuration for input line 14 */ +#define EXTI_RTSR1_RT15_Pos (15U) +#define EXTI_RTSR1_RT15_Msk (0x1UL << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */ +#define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger configuration for input line 15 */ +#define EXTI_RTSR1_RT16_Pos (16U) +#define EXTI_RTSR1_RT16_Msk (0x1UL << EXTI_RTSR1_RT16_Pos) /*!< 0x00010000 */ +#define EXTI_RTSR1_RT16 EXTI_RTSR1_RT16_Msk /*!< Rising trigger configuration for input line 16 */ +#define EXTI_RTSR1_RT17_Pos (17U) +#define EXTI_RTSR1_RT17_Msk (0x1UL << EXTI_RTSR1_RT17_Pos) /*!< 0x00020000 */ +#define EXTI_RTSR1_RT17 EXTI_RTSR1_RT17_Msk /*!< Rising trigger configuration for input line 17 */ +#define EXTI_RTSR1_RT18_Pos (18U) +#define EXTI_RTSR1_RT18_Msk (0x1UL << EXTI_RTSR1_RT18_Pos) /*!< 0x00040000 */ +#define EXTI_RTSR1_RT18 EXTI_RTSR1_RT18_Msk /*!< Rising trigger configuration for input line 18 */ + +/****************** Bit definition for EXTI_FTSR1 register ******************/ +#define EXTI_FTSR1_FT0_Pos (0U) +#define EXTI_FTSR1_FT0_Msk (0x1UL << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */ +#define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger configuration for input line 0 */ +#define EXTI_FTSR1_FT1_Pos (1U) +#define EXTI_FTSR1_FT1_Msk (0x1UL << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */ +#define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger configuration for input line 1 */ +#define EXTI_FTSR1_FT2_Pos (2U) +#define EXTI_FTSR1_FT2_Msk (0x1UL << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */ +#define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger configuration for input line 2 */ +#define EXTI_FTSR1_FT3_Pos (3U) +#define EXTI_FTSR1_FT3_Msk (0x1UL << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */ +#define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger configuration for input line 3 */ +#define EXTI_FTSR1_FT4_Pos (4U) +#define EXTI_FTSR1_FT4_Msk (0x1UL << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */ +#define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger configuration for input line 4 */ +#define EXTI_FTSR1_FT5_Pos (5U) +#define EXTI_FTSR1_FT5_Msk (0x1UL << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */ +#define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger configuration for input line 5 */ +#define EXTI_FTSR1_FT6_Pos (6U) +#define EXTI_FTSR1_FT6_Msk (0x1UL << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */ +#define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger configuration for input line 6 */ +#define EXTI_FTSR1_FT7_Pos (7U) +#define EXTI_FTSR1_FT7_Msk (0x1UL << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */ +#define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger configuration for input line 7 */ +#define EXTI_FTSR1_FT8_Pos (8U) +#define EXTI_FTSR1_FT8_Msk (0x1UL << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */ +#define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger configuration for input line 8 */ +#define EXTI_FTSR1_FT9_Pos (9U) +#define EXTI_FTSR1_FT9_Msk (0x1UL << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */ +#define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger configuration for input line 9 */ +#define EXTI_FTSR1_FT10_Pos (10U) +#define EXTI_FTSR1_FT10_Msk (0x1UL << EXTI_FTSR1_FT10_Pos) /*!< 0x00000400 */ +#define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk /*!< Falling trigger configuration for input line 10 */ +#define EXTI_FTSR1_FT11_Pos (11U) +#define EXTI_FTSR1_FT11_Msk (0x1UL << EXTI_FTSR1_FT11_Pos) /*!< 0x00000800 */ +#define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk /*!< Falling trigger configuration for input line 11 */ +#define EXTI_FTSR1_FT12_Pos (12U) +#define EXTI_FTSR1_FT12_Msk (0x1UL << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */ +#define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger configuration for input line 12 */ +#define EXTI_FTSR1_FT13_Pos (13U) +#define EXTI_FTSR1_FT13_Msk (0x1UL << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */ +#define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger configuration for input line 13 */ +#define EXTI_FTSR1_FT14_Pos (14U) +#define EXTI_FTSR1_FT14_Msk (0x1UL << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */ +#define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger configuration for input line 14 */ +#define EXTI_FTSR1_FT15_Pos (15U) +#define EXTI_FTSR1_FT15_Msk (0x1UL << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */ +#define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger configuration for input line 15 */ +#define EXTI_FTSR1_FT16_Pos (16U) +#define EXTI_FTSR1_FT16_Msk (0x1UL << EXTI_FTSR1_FT16_Pos) /*!< 0x00010000 */ +#define EXTI_FTSR1_FT16 EXTI_FTSR1_FT16_Msk /*!< Falling trigger configuration for input line 16 */ +#define EXTI_FTSR1_FT17_Pos (17U) +#define EXTI_FTSR1_FT17_Msk (0x1UL << EXTI_FTSR1_FT17_Pos) /*!< 0x00020000 */ +#define EXTI_FTSR1_FT17 EXTI_FTSR1_FT17_Msk /*!< Falling trigger configuration for input line 17 */ +#define EXTI_FTSR1_FT18_Pos (18U) +#define EXTI_FTSR1_FT18_Msk (0x1UL << EXTI_FTSR1_FT18_Pos) /*!< 0x00040000 */ +#define EXTI_FTSR1_FT18 EXTI_FTSR1_FT18_Msk /*!< Falling trigger configuration for input line 18 */ + +/****************** Bit definition for EXTI_SWIER1 register *****************/ +#define EXTI_SWIER1_SWI0_Pos (0U) +#define EXTI_SWIER1_SWI0_Msk (0x1UL << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */ +#define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software Interrupt on line 0 */ +#define EXTI_SWIER1_SWI1_Pos (1U) +#define EXTI_SWIER1_SWI1_Msk (0x1UL << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */ +#define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software Interrupt on line 1 */ +#define EXTI_SWIER1_SWI2_Pos (2U) +#define EXTI_SWIER1_SWI2_Msk (0x1UL << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */ +#define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software Interrupt on line 2 */ +#define EXTI_SWIER1_SWI3_Pos (3U) +#define EXTI_SWIER1_SWI3_Msk (0x1UL << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */ +#define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software Interrupt on line 3 */ +#define EXTI_SWIER1_SWI4_Pos (4U) +#define EXTI_SWIER1_SWI4_Msk (0x1UL << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */ +#define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software Interrupt on line 4 */ +#define EXTI_SWIER1_SWI5_Pos (5U) +#define EXTI_SWIER1_SWI5_Msk (0x1UL << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */ +#define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software Interrupt on line 5 */ +#define EXTI_SWIER1_SWI6_Pos (6U) +#define EXTI_SWIER1_SWI6_Msk (0x1UL << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */ +#define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software Interrupt on line 6 */ +#define EXTI_SWIER1_SWI7_Pos (7U) +#define EXTI_SWIER1_SWI7_Msk (0x1UL << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */ +#define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software Interrupt on line 7 */ +#define EXTI_SWIER1_SWI8_Pos (8U) +#define EXTI_SWIER1_SWI8_Msk (0x1UL << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */ +#define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software Interrupt on line 8 */ +#define EXTI_SWIER1_SWI9_Pos (9U) +#define EXTI_SWIER1_SWI9_Msk (0x1UL << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */ +#define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software Interrupt on line 9 */ +#define EXTI_SWIER1_SWI10_Pos (10U) +#define EXTI_SWIER1_SWI10_Msk (0x1UL << EXTI_SWIER1_SWI10_Pos) /*!< 0x00000400 */ +#define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk /*!< Software Interrupt on line 10 */ +#define EXTI_SWIER1_SWI11_Pos (11U) +#define EXTI_SWIER1_SWI11_Msk (0x1UL << EXTI_SWIER1_SWI11_Pos) /*!< 0x00000800 */ +#define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk /*!< Software Interrupt on line 11 */ +#define EXTI_SWIER1_SWI12_Pos (12U) +#define EXTI_SWIER1_SWI12_Msk (0x1UL << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */ +#define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software Interrupt on line 12 */ +#define EXTI_SWIER1_SWI13_Pos (13U) +#define EXTI_SWIER1_SWI13_Msk (0x1UL << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */ +#define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software Interrupt on line 13 */ +#define EXTI_SWIER1_SWI14_Pos (14U) +#define EXTI_SWIER1_SWI14_Msk (0x1UL << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */ +#define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software Interrupt on line 14 */ +#define EXTI_SWIER1_SWI15_Pos (15U) +#define EXTI_SWIER1_SWI15_Msk (0x1UL << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */ +#define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software Interrupt on line 15 */ +#define EXTI_SWIER1_SWI16_Pos (16U) +#define EXTI_SWIER1_SWI16_Msk (0x1UL << EXTI_SWIER1_SWI16_Pos) /*!< 0x00010000 */ +#define EXTI_SWIER1_SWI16 EXTI_SWIER1_SWI16_Msk /*!< Software Interrupt on line 16 */ +#define EXTI_SWIER1_SWI17_Pos (17U) +#define EXTI_SWIER1_SWI17_Msk (0x1UL << EXTI_SWIER1_SWI17_Pos) /*!< 0x00020000 */ +#define EXTI_SWIER1_SWI17 EXTI_SWIER1_SWI17_Msk /*!< Software Interrupt on line 17 */ +#define EXTI_SWIER1_SWI18_Pos (18U) +#define EXTI_SWIER1_SWI18_Msk (0x1UL << EXTI_SWIER1_SWI18_Pos) /*!< 0x00040000 */ +#define EXTI_SWIER1_SWI18 EXTI_SWIER1_SWI18_Msk /*!< Software Interrupt on line 18 */ + +/******************* Bit definition for EXTI_RPR1 register ******************/ +#define EXTI_RPR1_RPIF0_Pos (0U) +#define EXTI_RPR1_RPIF0_Msk (0x1UL << EXTI_RPR1_RPIF0_Pos) /*!< 0x00000001 */ +#define EXTI_RPR1_RPIF0 EXTI_RPR1_RPIF0_Msk /*!< Rising Pending Interrupt Flag on line 0 */ +#define EXTI_RPR1_RPIF1_Pos (1U) +#define EXTI_RPR1_RPIF1_Msk (0x1UL << EXTI_RPR1_RPIF1_Pos) /*!< 0x00000002 */ +#define EXTI_RPR1_RPIF1 EXTI_RPR1_RPIF1_Msk /*!< Rising Pending Interrupt Flag on line 1 */ +#define EXTI_RPR1_RPIF2_Pos (2U) +#define EXTI_RPR1_RPIF2_Msk (0x1UL << EXTI_RPR1_RPIF2_Pos) /*!< 0x00000004 */ +#define EXTI_RPR1_RPIF2 EXTI_RPR1_RPIF2_Msk /*!< Rising Pending Interrupt Flag on line 2 */ +#define EXTI_RPR1_RPIF3_Pos (3U) +#define EXTI_RPR1_RPIF3_Msk (0x1UL << EXTI_RPR1_RPIF3_Pos) /*!< 0x00000008 */ +#define EXTI_RPR1_RPIF3 EXTI_RPR1_RPIF3_Msk /*!< Rising Pending Interrupt Flag on line 3 */ +#define EXTI_RPR1_RPIF4_Pos (4U) +#define EXTI_RPR1_RPIF4_Msk (0x1UL << EXTI_RPR1_RPIF4_Pos) /*!< 0x00000010 */ +#define EXTI_RPR1_RPIF4 EXTI_RPR1_RPIF4_Msk /*!< Rising Pending Interrupt Flag on line 4 */ +#define EXTI_RPR1_RPIF5_Pos (5U) +#define EXTI_RPR1_RPIF5_Msk (0x1UL << EXTI_RPR1_RPIF5_Pos) /*!< 0x00000020 */ +#define EXTI_RPR1_RPIF5 EXTI_RPR1_RPIF5_Msk /*!< Rising Pending Interrupt Flag on line 5 */ +#define EXTI_RPR1_RPIF6_Pos (6U) +#define EXTI_RPR1_RPIF6_Msk (0x1UL << EXTI_RPR1_RPIF6_Pos) /*!< 0x00000040 */ +#define EXTI_RPR1_RPIF6 EXTI_RPR1_RPIF6_Msk /*!< Rising Pending Interrupt Flag on line 6 */ +#define EXTI_RPR1_RPIF7_Pos (7U) +#define EXTI_RPR1_RPIF7_Msk (0x1UL << EXTI_RPR1_RPIF7_Pos) /*!< 0x00000080 */ +#define EXTI_RPR1_RPIF7 EXTI_RPR1_RPIF7_Msk /*!< Rising Pending Interrupt Flag on line 7 */ +#define EXTI_RPR1_RPIF8_Pos (8U) +#define EXTI_RPR1_RPIF8_Msk (0x1UL << EXTI_RPR1_RPIF8_Pos) /*!< 0x00000100 */ +#define EXTI_RPR1_RPIF8 EXTI_RPR1_RPIF8_Msk /*!< Rising Pending Interrupt Flag on line 8 */ +#define EXTI_RPR1_RPIF9_Pos (9U) +#define EXTI_RPR1_RPIF9_Msk (0x1UL << EXTI_RPR1_RPIF9_Pos) /*!< 0x00000200 */ +#define EXTI_RPR1_RPIF9 EXTI_RPR1_RPIF9_Msk /*!< Rising Pending Interrupt Flag on line 9 */ +#define EXTI_RPR1_RPIF10_Pos (10U) +#define EXTI_RPR1_RPIF10_Msk (0x1UL << EXTI_RPR1_RPIF10_Pos) /*!< 0x00000400 */ +#define EXTI_RPR1_RPIF10 EXTI_RPR1_RPIF10_Msk /*!< Rising Pending Interrupt Flag on line 10 */ +#define EXTI_RPR1_RPIF11_Pos (11U) +#define EXTI_RPR1_RPIF11_Msk (0x1UL << EXTI_RPR1_RPIF11_Pos) /*!< 0x00000800 */ +#define EXTI_RPR1_RPIF11 EXTI_RPR1_RPIF11_Msk /*!< Rising Pending Interrupt Flag on line 11 */ +#define EXTI_RPR1_RPIF12_Pos (12U) +#define EXTI_RPR1_RPIF12_Msk (0x1UL << EXTI_RPR1_RPIF12_Pos) /*!< 0x00001000 */ +#define EXTI_RPR1_RPIF12 EXTI_RPR1_RPIF12_Msk /*!< Rising Pending Interrupt Flag on line 12 */ +#define EXTI_RPR1_RPIF13_Pos (13U) +#define EXTI_RPR1_RPIF13_Msk (0x1UL << EXTI_RPR1_RPIF13_Pos) /*!< 0x00002000 */ +#define EXTI_RPR1_RPIF13 EXTI_RPR1_RPIF13_Msk /*!< Rising Pending Interrupt Flag on line 13 */ +#define EXTI_RPR1_RPIF14_Pos (14U) +#define EXTI_RPR1_RPIF14_Msk (0x1UL << EXTI_RPR1_RPIF14_Pos) /*!< 0x00004000 */ +#define EXTI_RPR1_RPIF14 EXTI_RPR1_RPIF14_Msk /*!< Rising Pending Interrupt Flag on line 14 */ +#define EXTI_RPR1_RPIF15_Pos (15U) +#define EXTI_RPR1_RPIF15_Msk (0x1UL << EXTI_RPR1_RPIF15_Pos) /*!< 0x00008000 */ +#define EXTI_RPR1_RPIF15 EXTI_RPR1_RPIF15_Msk /*!< Rising Pending Interrupt Flag on line 15 */ +#define EXTI_RPR1_RPIF16_Pos (16U) +#define EXTI_RPR1_RPIF16_Msk (0x1UL << EXTI_RPR1_RPIF16_Pos) /*!< 0x00010000 */ +#define EXTI_RPR1_RPIF16 EXTI_RPR1_RPIF16_Msk /*!< Rising Pending Interrupt Flag on line 16 */ +#define EXTI_RPR1_RPIF17_Pos (17U) +#define EXTI_RPR1_RPIF17_Msk (0x1UL << EXTI_RPR1_RPIF17_Pos) /*!< 0x00020000 */ +#define EXTI_RPR1_RPIF17 EXTI_RPR1_RPIF17_Msk /*!< Rising Pending Interrupt Flag on line 17 */ +#define EXTI_RPR1_RPIF18_Pos (18U) +#define EXTI_RPR1_RPIF18_Msk (0x1UL << EXTI_RPR1_RPIF18_Pos) /*!< 0x00040000 */ +#define EXTI_RPR1_RPIF18 EXTI_RPR1_RPIF18_Msk /*!< Rising Pending Interrupt Flag on line 18 */ + +/******************* Bit definition for EXTI_FPR1 register ******************/ +#define EXTI_FPR1_FPIF0_Pos (0U) +#define EXTI_FPR1_FPIF0_Msk (0x1UL << EXTI_FPR1_FPIF0_Pos) /*!< 0x00000001 */ +#define EXTI_FPR1_FPIF0 EXTI_FPR1_FPIF0_Msk /*!< Falling Pending Interrupt Flag on line 0 */ +#define EXTI_FPR1_FPIF1_Pos (1U) +#define EXTI_FPR1_FPIF1_Msk (0x1UL << EXTI_FPR1_FPIF1_Pos) /*!< 0x00000002 */ +#define EXTI_FPR1_FPIF1 EXTI_FPR1_FPIF1_Msk /*!< Falling Pending Interrupt Flag on line 1 */ +#define EXTI_FPR1_FPIF2_Pos (2U) +#define EXTI_FPR1_FPIF2_Msk (0x1UL << EXTI_FPR1_FPIF2_Pos) /*!< 0x00000004 */ +#define EXTI_FPR1_FPIF2 EXTI_FPR1_FPIF2_Msk /*!< Falling Pending Interrupt Flag on line 2 */ +#define EXTI_FPR1_FPIF3_Pos (3U) +#define EXTI_FPR1_FPIF3_Msk (0x1UL << EXTI_FPR1_FPIF3_Pos) /*!< 0x00000008 */ +#define EXTI_FPR1_FPIF3 EXTI_FPR1_FPIF3_Msk /*!< Falling Pending Interrupt Flag on line 3 */ +#define EXTI_FPR1_FPIF4_Pos (4U) +#define EXTI_FPR1_FPIF4_Msk (0x1UL << EXTI_FPR1_FPIF4_Pos) /*!< 0x00000010 */ +#define EXTI_FPR1_FPIF4 EXTI_FPR1_FPIF4_Msk /*!< Falling Pending Interrupt Flag on line 4 */ +#define EXTI_FPR1_FPIF5_Pos (5U) +#define EXTI_FPR1_FPIF5_Msk (0x1UL << EXTI_FPR1_FPIF5_Pos) /*!< 0x00000020 */ +#define EXTI_FPR1_FPIF5 EXTI_FPR1_FPIF5_Msk /*!< Falling Pending Interrupt Flag on line 5 */ +#define EXTI_FPR1_FPIF6_Pos (6U) +#define EXTI_FPR1_FPIF6_Msk (0x1UL << EXTI_FPR1_FPIF6_Pos) /*!< 0x00000040 */ +#define EXTI_FPR1_FPIF6 EXTI_FPR1_FPIF6_Msk /*!< Falling Pending Interrupt Flag on line 6 */ +#define EXTI_FPR1_FPIF7_Pos (7U) +#define EXTI_FPR1_FPIF7_Msk (0x1UL << EXTI_FPR1_FPIF7_Pos) /*!< 0x00000080 */ +#define EXTI_FPR1_FPIF7 EXTI_FPR1_FPIF7_Msk /*!< Falling Pending Interrupt Flag on line 7 */ +#define EXTI_FPR1_FPIF8_Pos (8U) +#define EXTI_FPR1_FPIF8_Msk (0x1UL << EXTI_FPR1_FPIF8_Pos) /*!< 0x00000100 */ +#define EXTI_FPR1_FPIF8 EXTI_FPR1_FPIF8_Msk /*!< Falling Pending Interrupt Flag on line 8 */ +#define EXTI_FPR1_FPIF9_Pos (9U) +#define EXTI_FPR1_FPIF9_Msk (0x1UL << EXTI_FPR1_FPIF9_Pos) /*!< 0x00000200 */ +#define EXTI_FPR1_FPIF9 EXTI_FPR1_FPIF9_Msk /*!< Falling Pending Interrupt Flag on line 9 */ +#define EXTI_FPR1_FPIF10_Pos (10U) +#define EXTI_FPR1_FPIF10_Msk (0x1UL << EXTI_FPR1_FPIF10_Pos) /*!< 0x00000400 */ +#define EXTI_FPR1_FPIF10 EXTI_FPR1_FPIF10_Msk /*!< Falling Pending Interrupt Flag on line 10 */ +#define EXTI_FPR1_FPIF11_Pos (11U) +#define EXTI_FPR1_FPIF11_Msk (0x1UL << EXTI_FPR1_FPIF11_Pos) /*!< 0x00000800 */ +#define EXTI_FPR1_FPIF11 EXTI_FPR1_FPIF11_Msk /*!< Falling Pending Interrupt Flag on line 11 */ +#define EXTI_FPR1_FPIF12_Pos (12U) +#define EXTI_FPR1_FPIF12_Msk (0x1UL << EXTI_FPR1_FPIF12_Pos) /*!< 0x00001000 */ +#define EXTI_FPR1_FPIF12 EXTI_FPR1_FPIF12_Msk /*!< Falling Pending Interrupt Flag on line 12 */ +#define EXTI_FPR1_FPIF13_Pos (13U) +#define EXTI_FPR1_FPIF13_Msk (0x1UL << EXTI_FPR1_FPIF13_Pos) /*!< 0x00002000 */ +#define EXTI_FPR1_FPIF13 EXTI_FPR1_FPIF13_Msk /*!< Falling Pending Interrupt Flag on line 13 */ +#define EXTI_FPR1_FPIF14_Pos (14U) +#define EXTI_FPR1_FPIF14_Msk (0x1UL << EXTI_FPR1_FPIF14_Pos) /*!< 0x00004000 */ +#define EXTI_FPR1_FPIF14 EXTI_FPR1_FPIF14_Msk /*!< Falling Pending Interrupt Flag on line 14 */ +#define EXTI_FPR1_FPIF15_Pos (15U) +#define EXTI_FPR1_FPIF15_Msk (0x1UL << EXTI_FPR1_FPIF15_Pos) /*!< 0x00008000 */ +#define EXTI_FPR1_FPIF15 EXTI_FPR1_FPIF15_Msk /*!< Falling Pending Interrupt Flag on line 15 */ +#define EXTI_FPR1_FPIF16_Pos (16U) +#define EXTI_FPR1_FPIF16_Msk (0x1UL << EXTI_FPR1_FPIF16_Pos) /*!< 0x00010000 */ +#define EXTI_FPR1_FPIF16 EXTI_FPR1_FPIF16_Msk /*!< Falling Pending Interrupt Flag on line 16 */ +#define EXTI_FPR1_FPIF17_Pos (17U) +#define EXTI_FPR1_FPIF17_Msk (0x1UL << EXTI_FPR1_FPIF17_Pos) /*!< 0x00020000 */ +#define EXTI_FPR1_FPIF17 EXTI_FPR1_FPIF17_Msk /*!< Falling Pending Interrupt Flag on line 17 */ +#define EXTI_FPR1_FPIF18_Pos (18U) +#define EXTI_FPR1_FPIF18_Msk (0x1UL << EXTI_FPR1_FPIF18_Pos) /*!< 0x00040000 */ +#define EXTI_FPR1_FPIF18 EXTI_FPR1_FPIF18_Msk /*!< Falling Pending Interrupt Flag on line 18 */ + +/******************* Bit definition for EXTI_SECCFGR1 register ******************/ +#define EXTI_SECCFGR1_SEC0_Pos (0U) +#define EXTI_SECCFGR1_SEC0_Msk (0x1UL << EXTI_SECCFGR1_SEC0_Pos) /*!< 0x00000001 */ +#define EXTI_SECCFGR1_SEC0 EXTI_SECCFGR1_SEC0_Msk /*!< Security enable on line 0 */ +#define EXTI_SECCFGR1_SEC1_Pos (1U) +#define EXTI_SECCFGR1_SEC1_Msk (0x1UL << EXTI_SECCFGR1_SEC1_Pos) /*!< 0x00000002 */ +#define EXTI_SECCFGR1_SEC1 EXTI_SECCFGR1_SEC1_Msk /*!< Security enable on line 1 */ +#define EXTI_SECCFGR1_SEC2_Pos (2U) +#define EXTI_SECCFGR1_SEC2_Msk (0x1UL << EXTI_SECCFGR1_SEC2_Pos) /*!< 0x00000004 */ +#define EXTI_SECCFGR1_SEC2 EXTI_SECCFGR1_SEC2_Msk /*!< Security enable on line 2 */ +#define EXTI_SECCFGR1_SEC3_Pos (3U) +#define EXTI_SECCFGR1_SEC3_Msk (0x1UL << EXTI_SECCFGR1_SEC3_Pos) /*!< 0x00000008 */ +#define EXTI_SECCFGR1_SEC3 EXTI_SECCFGR1_SEC3_Msk /*!< Security enable on line 3 */ +#define EXTI_SECCFGR1_SEC4_Pos (4U) +#define EXTI_SECCFGR1_SEC4_Msk (0x1UL << EXTI_SECCFGR1_SEC4_Pos) /*!< 0x00000010 */ +#define EXTI_SECCFGR1_SEC4 EXTI_SECCFGR1_SEC4_Msk /*!< Security enable on line 4 */ +#define EXTI_SECCFGR1_SEC5_Pos (5U) +#define EXTI_SECCFGR1_SEC5_Msk (0x1UL << EXTI_SECCFGR1_SEC5_Pos) /*!< 0x00000020 */ +#define EXTI_SECCFGR1_SEC5 EXTI_SECCFGR1_SEC5_Msk /*!< Security enable on line 5 */ +#define EXTI_SECCFGR1_SEC6_Pos (6U) +#define EXTI_SECCFGR1_SEC6_Msk (0x1UL << EXTI_SECCFGR1_SEC6_Pos) /*!< 0x00000040 */ +#define EXTI_SECCFGR1_SEC6 EXTI_SECCFGR1_SEC6_Msk /*!< Security enable on line 6 */ +#define EXTI_SECCFGR1_SEC7_Pos (7U) +#define EXTI_SECCFGR1_SEC7_Msk (0x1UL << EXTI_SECCFGR1_SEC7_Pos) /*!< 0x00000080 */ +#define EXTI_SECCFGR1_SEC7 EXTI_SECCFGR1_SEC7_Msk /*!< Security enable on line 7 */ +#define EXTI_SECCFGR1_SEC8_Pos (8U) +#define EXTI_SECCFGR1_SEC8_Msk (0x1UL << EXTI_SECCFGR1_SEC8_Pos) /*!< 0x00000100 */ +#define EXTI_SECCFGR1_SEC8 EXTI_SECCFGR1_SEC8_Msk /*!< Security enable on line 8 */ +#define EXTI_SECCFGR1_SEC9_Pos (9U) +#define EXTI_SECCFGR1_SEC9_Msk (0x1UL << EXTI_SECCFGR1_SEC9_Pos) /*!< 0x00000200 */ +#define EXTI_SECCFGR1_SEC9 EXTI_SECCFGR1_SEC9_Msk /*!< Security enable on line 9 */ +#define EXTI_SECCFGR1_SEC10_Pos (10U) +#define EXTI_SECCFGR1_SEC10_Msk (0x1UL << EXTI_SECCFGR1_SEC10_Pos) /*!< 0x00000400 */ +#define EXTI_SECCFGR1_SEC10 EXTI_SECCFGR1_SEC10_Msk /*!< Security enable on line 10 */ +#define EXTI_SECCFGR1_SEC11_Pos (11U) +#define EXTI_SECCFGR1_SEC11_Msk (0x1UL << EXTI_SECCFGR1_SEC11_Pos) /*!< 0x00000800 */ +#define EXTI_SECCFGR1_SEC11 EXTI_SECCFGR1_SEC11_Msk /*!< Security enable on line 11 */ +#define EXTI_SECCFGR1_SEC12_Pos (12U) +#define EXTI_SECCFGR1_SEC12_Msk (0x1UL << EXTI_SECCFGR1_SEC12_Pos) /*!< 0x00001000 */ +#define EXTI_SECCFGR1_SEC12 EXTI_SECCFGR1_SEC12_Msk /*!< Security enable on line 12 */ +#define EXTI_SECCFGR1_SEC13_Pos (13U) +#define EXTI_SECCFGR1_SEC13_Msk (0x1UL << EXTI_SECCFGR1_SEC13_Pos) /*!< 0x00002000 */ +#define EXTI_SECCFGR1_SEC13 EXTI_SECCFGR1_SEC13_Msk /*!< Security enable on line 13 */ +#define EXTI_SECCFGR1_SEC14_Pos (14U) +#define EXTI_SECCFGR1_SEC14_Msk (0x1UL << EXTI_SECCFGR1_SEC14_Pos) /*!< 0x00004000 */ +#define EXTI_SECCFGR1_SEC14 EXTI_SECCFGR1_SEC14_Msk /*!< Security enable on line 14 */ +#define EXTI_SECCFGR1_SEC15_Pos (15U) +#define EXTI_SECCFGR1_SEC15_Msk (0x1UL << EXTI_SECCFGR1_SEC15_Pos) /*!< 0x00008000 */ +#define EXTI_SECCFGR1_SEC15 EXTI_SECCFGR1_SEC15_Msk /*!< Security enable on line 15 */ +#define EXTI_SECCFGR1_SEC16_Pos (16U) +#define EXTI_SECCFGR1_SEC16_Msk (0x1UL << EXTI_SECCFGR1_SEC16_Pos) /*!< 0x00010000 */ +#define EXTI_SECCFGR1_SEC16 EXTI_SECCFGR1_SEC16_Msk /*!< Security enable on line 16 */ +#define EXTI_SECCFGR1_SEC17_Pos (17U) +#define EXTI_SECCFGR1_SEC17_Msk (0x1UL << EXTI_SECCFGR1_SEC17_Pos) /*!< 0x00020000 */ +#define EXTI_SECCFGR1_SEC17 EXTI_SECCFGR1_SEC17_Msk /*!< Security enable on line 17 */ +#define EXTI_SECCFGR1_SEC18_Pos (18U) +#define EXTI_SECCFGR1_SEC18_Msk (0x1UL << EXTI_SECCFGR1_SEC18_Pos) /*!< 0x00040000 */ +#define EXTI_SECCFGR1_SEC18 EXTI_SECCFGR1_SEC18_Msk /*!< Security enable on line 18 */ + +/******************* Bit definition for EXTI_PRIVCFGR1 register ******************/ +#define EXTI_PRIVCFGR1_PRIV0_Pos (0U) +#define EXTI_PRIVCFGR1_PRIV0_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV0_Pos) /*!< 0x00000001 */ +#define EXTI_PRIVCFGR1_PRIV0 EXTI_PRIVCFGR1_PRIV0_Msk /*!< Privilege enable on line 0 */ +#define EXTI_PRIVCFGR1_PRIV1_Pos (1U) +#define EXTI_PRIVCFGR1_PRIV1_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV1_Pos) /*!< 0x00000002 */ +#define EXTI_PRIVCFGR1_PRIV1 EXTI_PRIVCFGR1_PRIV1_Msk /*!< Privilege enable on line 1 */ +#define EXTI_PRIVCFGR1_PRIV2_Pos (2U) +#define EXTI_PRIVCFGR1_PRIV2_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV2_Pos) /*!< 0x00000004 */ +#define EXTI_PRIVCFGR1_PRIV2 EXTI_PRIVCFGR1_PRIV2_Msk /*!< Privilege enable on line 2 */ +#define EXTI_PRIVCFGR1_PRIV3_Pos (3U) +#define EXTI_PRIVCFGR1_PRIV3_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV3_Pos) /*!< 0x00000008 */ +#define EXTI_PRIVCFGR1_PRIV3 EXTI_PRIVCFGR1_PRIV3_Msk /*!< Privilege enable on line 3 */ +#define EXTI_PRIVCFGR1_PRIV4_Pos (4U) +#define EXTI_PRIVCFGR1_PRIV4_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV4_Pos) /*!< 0x00000010 */ +#define EXTI_PRIVCFGR1_PRIV4 EXTI_PRIVCFGR1_PRIV4_Msk /*!< Privilege enable on line 4 */ +#define EXTI_PRIVCFGR1_PRIV5_Pos (5U) +#define EXTI_PRIVCFGR1_PRIV5_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV5_Pos) /*!< 0x00000020 */ +#define EXTI_PRIVCFGR1_PRIV5 EXTI_PRIVCFGR1_PRIV5_Msk /*!< Privilege enable on line 5 */ +#define EXTI_PRIVCFGR1_PRIV6_Pos (6U) +#define EXTI_PRIVCFGR1_PRIV6_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV6_Pos) /*!< 0x00000040 */ +#define EXTI_PRIVCFGR1_PRIV6 EXTI_PRIVCFGR1_PRIV6_Msk /*!< Privilege enable on line 6 */ +#define EXTI_PRIVCFGR1_PRIV7_Pos (7U) +#define EXTI_PRIVCFGR1_PRIV7_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV7_Pos) /*!< 0x00000080 */ +#define EXTI_PRIVCFGR1_PRIV7 EXTI_PRIVCFGR1_PRIV7_Msk /*!< Privilege enable on line 7 */ +#define EXTI_PRIVCFGR1_PRIV8_Pos (8U) +#define EXTI_PRIVCFGR1_PRIV8_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV8_Pos) /*!< 0x00000100 */ +#define EXTI_PRIVCFGR1_PRIV8 EXTI_PRIVCFGR1_PRIV8_Msk /*!< Privilege enable on line 8 */ +#define EXTI_PRIVCFGR1_PRIV9_Pos (9U) +#define EXTI_PRIVCFGR1_PRIV9_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV9_Pos) /*!< 0x00000200 */ +#define EXTI_PRIVCFGR1_PRIV9 EXTI_PRIVCFGR1_PRIV9_Msk /*!< Privilege enable on line 9 */ +#define EXTI_PRIVCFGR1_PRIV10_Pos (10U) +#define EXTI_PRIVCFGR1_PRIV10_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV10_Pos) /*!< 0x00000400 */ +#define EXTI_PRIVCFGR1_PRIV10 EXTI_PRIVCFGR1_PRIV10_Msk /*!< Privilege enable on line 10 */ +#define EXTI_PRIVCFGR1_PRIV11_Pos (11U) +#define EXTI_PRIVCFGR1_PRIV11_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV11_Pos) /*!< 0x00000800 */ +#define EXTI_PRIVCFGR1_PRIV11 EXTI_PRIVCFGR1_PRIV11_Msk /*!< Privilege enable on line 11 */ +#define EXTI_PRIVCFGR1_PRIV12_Pos (12U) +#define EXTI_PRIVCFGR1_PRIV12_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV12_Pos) /*!< 0x00001000 */ +#define EXTI_PRIVCFGR1_PRIV12 EXTI_PRIVCFGR1_PRIV12_Msk /*!< Privilege enable on line 12 */ +#define EXTI_PRIVCFGR1_PRIV13_Pos (13U) +#define EXTI_PRIVCFGR1_PRIV13_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV13_Pos) /*!< 0x00002000 */ +#define EXTI_PRIVCFGR1_PRIV13 EXTI_PRIVCFGR1_PRIV13_Msk /*!< Privilege enable on line 13 */ +#define EXTI_PRIVCFGR1_PRIV14_Pos (14U) +#define EXTI_PRIVCFGR1_PRIV14_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV14_Pos) /*!< 0x00004000 */ +#define EXTI_PRIVCFGR1_PRIV14 EXTI_PRIVCFGR1_PRIV14_Msk /*!< Privilege enable on line 14 */ +#define EXTI_PRIVCFGR1_PRIV15_Pos (15U) +#define EXTI_PRIVCFGR1_PRIV15_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV15_Pos) /*!< 0x00008000 */ +#define EXTI_PRIVCFGR1_PRIV15 EXTI_PRIVCFGR1_PRIV15_Msk /*!< Privilege enable on line 15 */ +#define EXTI_PRIVCFGR1_PRIV16_Pos (16U) +#define EXTI_PRIVCFGR1_PRIV16_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV16_Pos) /*!< 0x00010000 */ +#define EXTI_PRIVCFGR1_PRIV16 EXTI_PRIVCFGR1_PRIV16_Msk /*!< Privilege enable on line 16 */ +#define EXTI_PRIVCFGR1_PRIV17_Pos (17U) +#define EXTI_PRIVCFGR1_PRIV17_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV17_Pos) /*!< 0x00020000 */ +#define EXTI_PRIVCFGR1_PRIV17 EXTI_PRIVCFGR1_PRIV17_Msk /*!< Privilege enable on line 17 */ +#define EXTI_PRIVCFGR1_PRIV18_Pos (18U) +#define EXTI_PRIVCFGR1_PRIV18_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV18_Pos) /*!< 0x00040000 */ +#define EXTI_PRIVCFGR1_PRIV18 EXTI_PRIVCFGR1_PRIV18_Msk /*!< Privilege enable on line 18 */ + +/***************** Bit definition for EXTI_EXTICR1 register **************/ +#define EXTI_EXTICR1_EXTI0_Pos (0U) +#define EXTI_EXTICR1_EXTI0_Msk (0xFFUL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x000000FF */ +#define EXTI_EXTICR1_EXTI0 EXTI_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */ +#define EXTI_EXTICR1_EXTI0_0 (0x1UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR1_EXTI0_1 (0x2UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR1_EXTI0_2 (0x4UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR1_EXTI0_3 (0x8UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000008 */ +#define EXTI_EXTICR1_EXTI0_4 (0x10UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000010 */ +#define EXTI_EXTICR1_EXTI0_5 (0x20UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000020 */ +#define EXTI_EXTICR1_EXTI0_6 (0x40UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000040 */ +#define EXTI_EXTICR1_EXTI0_7 (0x80UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000080 */ +#define EXTI_EXTICR1_EXTI1_Pos (8U) +#define EXTI_EXTICR1_EXTI1_Msk (0xFFUL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x0000FF00 */ +#define EXTI_EXTICR1_EXTI1 EXTI_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */ +#define EXTI_EXTICR1_EXTI1_0 (0x1UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR1_EXTI1_1 (0x2UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR1_EXTI1_2 (0x4UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR1_EXTI1_3 (0x8UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000800 */ +#define EXTI_EXTICR1_EXTI1_4 (0x10UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00001000 */ +#define EXTI_EXTICR1_EXTI1_5 (0x20UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00002000 */ +#define EXTI_EXTICR1_EXTI1_6 (0x40UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00004000 */ +#define EXTI_EXTICR1_EXTI1_7 (0x80UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00008000 */ +#define EXTI_EXTICR1_EXTI2_Pos (16U) +#define EXTI_EXTICR1_EXTI2_Msk (0xFFUL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00FF0000 */ +#define EXTI_EXTICR1_EXTI2 EXTI_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */ +#define EXTI_EXTICR1_EXTI2_0 (0x1UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR1_EXTI2_1 (0x2UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR1_EXTI2_2 (0x4UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR1_EXTI2_3 (0x8UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00080000 */ +#define EXTI_EXTICR1_EXTI2_4 (0x10UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00100000 */ +#define EXTI_EXTICR1_EXTI2_5 (0x20UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00200000 */ +#define EXTI_EXTICR1_EXTI2_6 (0x40UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00400000 */ +#define EXTI_EXTICR1_EXTI2_7 (0x80UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00800000 */ +#define EXTI_EXTICR1_EXTI3_Pos (24U) +#define EXTI_EXTICR1_EXTI3_Msk (0xFFUL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0xFF000000 */ +#define EXTI_EXTICR1_EXTI3 EXTI_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */ +#define EXTI_EXTICR1_EXTI3_0 (0x1UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR1_EXTI3_1 (0x2UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR1_EXTI3_2 (0x4UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x04000000 */ +#define EXTI_EXTICR1_EXTI3_3 (0x8UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x08000000 */ +#define EXTI_EXTICR1_EXTI3_4 (0x10UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x10000000 */ +#define EXTI_EXTICR1_EXTI3_5 (0x20UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x20000000 */ +#define EXTI_EXTICR1_EXTI3_6 (0x40UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x40000000 */ +#define EXTI_EXTICR1_EXTI3_7 (0x80UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for EXTI_EXTICR2 register **************/ +#define EXTI_EXTICR2_EXTI4_Pos (0U) +#define EXTI_EXTICR2_EXTI4_Msk (0xFFUL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x000000FF */ +#define EXTI_EXTICR2_EXTI4 EXTI_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */ +#define EXTI_EXTICR2_EXTI4_0 (0x1UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR2_EXTI4_1 (0x2UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR2_EXTI4_2 (0x4UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR2_EXTI4_3 (0x8UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000008 */ +#define EXTI_EXTICR2_EXTI4_4 (0x10UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000010 */ +#define EXTI_EXTICR2_EXTI4_5 (0x20UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000020 */ +#define EXTI_EXTICR2_EXTI4_6 (0x40UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000040 */ +#define EXTI_EXTICR2_EXTI4_7 (0x80UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000080 */ +#define EXTI_EXTICR2_EXTI5_Pos (8U) +#define EXTI_EXTICR2_EXTI5_Msk (0xFFUL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x0000FF00 */ +#define EXTI_EXTICR2_EXTI5 EXTI_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */ +#define EXTI_EXTICR2_EXTI5_0 (0x1UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR2_EXTI5_1 (0x2UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR2_EXTI5_2 (0x4UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR2_EXTI5_3 (0x8UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000800 */ +#define EXTI_EXTICR2_EXTI5_4 (0x10UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00001000 */ +#define EXTI_EXTICR2_EXTI5_5 (0x20UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00002000 */ +#define EXTI_EXTICR2_EXTI5_6 (0x40UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00004000 */ +#define EXTI_EXTICR2_EXTI5_7 (0x80UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00008000 */ +#define EXTI_EXTICR2_EXTI6_Pos (16U) +#define EXTI_EXTICR2_EXTI6_Msk (0xFFUL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00FF0000 */ +#define EXTI_EXTICR2_EXTI6 EXTI_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */ +#define EXTI_EXTICR2_EXTI6_0 (0x1UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR2_EXTI6_1 (0x2UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR2_EXTI6_2 (0x4UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR2_EXTI6_3 (0x8UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00080000 */ +#define EXTI_EXTICR2_EXTI6_4 (0x10UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00100000 */ +#define EXTI_EXTICR2_EXTI6_5 (0x20UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00200000 */ +#define EXTI_EXTICR2_EXTI6_6 (0x40UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00400000 */ +#define EXTI_EXTICR2_EXTI6_7 (0x80UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00800000 */ +#define EXTI_EXTICR2_EXTI7_Pos (24U) +#define EXTI_EXTICR2_EXTI7_Msk (0xFFUL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0xFF000000 */ +#define EXTI_EXTICR2_EXTI7 EXTI_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */ +#define EXTI_EXTICR2_EXTI7_0 (0x1UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR2_EXTI7_1 (0x2UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR2_EXTI7_2 (0x4UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x04000000 */ +#define EXTI_EXTICR2_EXTI7_3 (0x8UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x08000000 */ +#define EXTI_EXTICR2_EXTI7_4 (0x10UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x10000000 */ +#define EXTI_EXTICR2_EXTI7_5 (0x20UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x20000000 */ +#define EXTI_EXTICR2_EXTI7_6 (0x40UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x40000000 */ +#define EXTI_EXTICR2_EXTI7_7 (0x80UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for EXTI_EXTICR3 register **************/ +#define EXTI_EXTICR3_EXTI8_Pos (0U) +#define EXTI_EXTICR3_EXTI8_Msk (0xFFUL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x000000FF */ +#define EXTI_EXTICR3_EXTI8 EXTI_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */ +#define EXTI_EXTICR3_EXTI8_0 (0x1UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR3_EXTI8_1 (0x2UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR3_EXTI8_2 (0x4UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR3_EXTI8_3 (0x8UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000008 */ +#define EXTI_EXTICR3_EXTI8_4 (0x10UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000010 */ +#define EXTI_EXTICR3_EXTI8_5 (0x20UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000020 */ +#define EXTI_EXTICR3_EXTI8_6 (0x40UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000040 */ +#define EXTI_EXTICR3_EXTI8_7 (0x80UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000080 */ +#define EXTI_EXTICR3_EXTI9_Pos (8U) +#define EXTI_EXTICR3_EXTI9_Msk (0xFFUL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x0000FF00 */ +#define EXTI_EXTICR3_EXTI9 EXTI_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */ +#define EXTI_EXTICR3_EXTI9_0 (0x1UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR3_EXTI9_1 (0x2UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR3_EXTI9_2 (0x4UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR3_EXTI9_3 (0x8UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000800 */ +#define EXTI_EXTICR3_EXTI9_4 (0x10UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00001000 */ +#define EXTI_EXTICR3_EXTI9_5 (0x20UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00002000 */ +#define EXTI_EXTICR3_EXTI9_6 (0x40UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00004000 */ +#define EXTI_EXTICR3_EXTI9_7 (0x80UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00008000 */ +#define EXTI_EXTICR3_EXTI10_Pos (16U) +#define EXTI_EXTICR3_EXTI10_Msk (0xFFUL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00FF0000 */ +#define EXTI_EXTICR3_EXTI10 EXTI_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */ +#define EXTI_EXTICR3_EXTI10_0 (0x1UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR3_EXTI10_1 (0x2UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR3_EXTI10_2 (0x4UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR3_EXTI10_3 (0x8UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00080000 */ +#define EXTI_EXTICR3_EXTI10_4 (0x10UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00100000 */ +#define EXTI_EXTICR3_EXTI10_5 (0x20UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00200000 */ +#define EXTI_EXTICR3_EXTI10_6 (0x40UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00400000 */ +#define EXTI_EXTICR3_EXTI10_7 (0x80UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00800000 */ +#define EXTI_EXTICR3_EXTI11_Pos (24U) +#define EXTI_EXTICR3_EXTI11_Msk (0xFFUL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0xFF000000 */ +#define EXTI_EXTICR3_EXTI11 EXTI_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */ +#define EXTI_EXTICR3_EXTI11_0 (0x1UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR3_EXTI11_1 (0x2UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR3_EXTI11_2 (0x4UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x04000000 */ +#define EXTI_EXTICR3_EXTI11_3 (0x8UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x08000000 */ +#define EXTI_EXTICR3_EXTI11_4 (0x10UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x10000000 */ +#define EXTI_EXTICR3_EXTI11_5 (0x20UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x20000000 */ +#define EXTI_EXTICR3_EXTI11_6 (0x40UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x40000000 */ +#define EXTI_EXTICR3_EXTI11_7 (0x80UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for EXTI_EXTICR4 register **************/ +#define EXTI_EXTICR4_EXTI12_Pos (0U) +#define EXTI_EXTICR4_EXTI12_Msk (0xFFUL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x000000FF */ +#define EXTI_EXTICR4_EXTI12 EXTI_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */ +#define EXTI_EXTICR4_EXTI12_0 (0x1UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR4_EXTI12_1 (0x2UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR4_EXTI12_2 (0x4UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR4_EXTI12_3 (0x8UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000008 */ +#define EXTI_EXTICR4_EXTI12_4 (0x10UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000010 */ +#define EXTI_EXTICR4_EXTI12_5 (0x20UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000020 */ +#define EXTI_EXTICR4_EXTI12_6 (0x40UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000040 */ +#define EXTI_EXTICR4_EXTI12_7 (0x80UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000080 */ +#define EXTI_EXTICR4_EXTI13_Pos (8U) +#define EXTI_EXTICR4_EXTI13_Msk (0xFFUL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x0000FF00 */ +#define EXTI_EXTICR4_EXTI13 EXTI_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */ +#define EXTI_EXTICR4_EXTI13_0 (0x1UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR4_EXTI13_1 (0x2UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR4_EXTI13_2 (0x4UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR4_EXTI13_3 (0x8UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000800 */ +#define EXTI_EXTICR4_EXTI13_4 (0x10UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00001000 */ +#define EXTI_EXTICR4_EXTI13_5 (0x20UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00002000 */ +#define EXTI_EXTICR4_EXTI13_6 (0x40UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00004000 */ +#define EXTI_EXTICR4_EXTI13_7 (0x80UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00008000 */ +#define EXTI_EXTICR4_EXTI14_Pos (16U) +#define EXTI_EXTICR4_EXTI14_Msk (0xFFUL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00FF0000 */ +#define EXTI_EXTICR4_EXTI14 EXTI_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */ +#define EXTI_EXTICR4_EXTI14_0 (0x1UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR4_EXTI14_1 (0x2UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR4_EXTI14_2 (0x4UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR4_EXTI14_3 (0x8UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00080000 */ +#define EXTI_EXTICR4_EXTI14_4 (0x10UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00100000 */ +#define EXTI_EXTICR4_EXTI14_5 (0x20UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00200000 */ +#define EXTI_EXTICR4_EXTI14_6 (0x40UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00400000 */ +#define EXTI_EXTICR4_EXTI14_7 (0x80UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00800000 */ +#define EXTI_EXTICR4_EXTI15_Pos (24U) +#define EXTI_EXTICR4_EXTI15_Msk (0xFFUL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0xFF000000 */ +#define EXTI_EXTICR4_EXTI15 EXTI_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */ +#define EXTI_EXTICR4_EXTI15_0 (0x1UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR4_EXTI15_1 (0x2UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR4_EXTI15_2 (0x4UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x04000000 */ +#define EXTI_EXTICR4_EXTI15_3 (0x8UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x08000000 */ +#define EXTI_EXTICR4_EXTI15_4 (0x10UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x10000000 */ +#define EXTI_EXTICR4_EXTI15_5 (0x20UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x20000000 */ +#define EXTI_EXTICR4_EXTI15_6 (0x40UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x40000000 */ +#define EXTI_EXTICR4_EXTI15_7 (0x80UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x80000000 */ + +/******************* Bit definition for EXTI_LOCKR register ******************/ +#define EXTI_LOCKR_LOCK_Pos (0U) +#define EXTI_LOCKR_LOCK_Msk (0x1UL << EXTI_LOCKR_LOCK_Pos) /*!< 0x00000001 */ +#define EXTI_LOCKR_LOCK EXTI_LOCKR_LOCK_Msk /*!< Security and privilege configuration lock */ + +/******************* Bit definition for EXTI_IMR1 register ******************/ +#define EXTI_IMR1_IM0_Pos (0U) +#define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */ +#define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< Interrupt Mask on line 0 */ +#define EXTI_IMR1_IM1_Pos (1U) +#define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */ +#define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< Interrupt Mask on line 1 */ +#define EXTI_IMR1_IM2_Pos (2U) +#define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */ +#define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< Interrupt Mask on line 2 */ +#define EXTI_IMR1_IM3_Pos (3U) +#define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */ +#define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< Interrupt Mask on line 3 */ +#define EXTI_IMR1_IM4_Pos (4U) +#define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */ +#define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< Interrupt Mask on line 4 */ +#define EXTI_IMR1_IM5_Pos (5U) +#define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */ +#define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< Interrupt Mask on line 5 */ +#define EXTI_IMR1_IM6_Pos (6U) +#define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */ +#define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< Interrupt Mask on line 6 */ +#define EXTI_IMR1_IM7_Pos (7U) +#define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */ +#define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< Interrupt Mask on line 7 */ +#define EXTI_IMR1_IM8_Pos (8U) +#define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */ +#define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< Interrupt Mask on line 8 */ +#define EXTI_IMR1_IM9_Pos (9U) +#define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */ +#define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< Interrupt Mask on line 9 */ +#define EXTI_IMR1_IM10_Pos (10U) +#define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */ +#define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< Interrupt Mask on line 10 */ +#define EXTI_IMR1_IM11_Pos (11U) +#define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */ +#define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< Interrupt Mask on line 11 */ +#define EXTI_IMR1_IM12_Pos (12U) +#define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */ +#define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< Interrupt Mask on line 12 */ +#define EXTI_IMR1_IM13_Pos (13U) +#define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */ +#define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< Interrupt Mask on line 13 */ +#define EXTI_IMR1_IM14_Pos (14U) +#define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */ +#define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< Interrupt Mask on line 14 */ +#define EXTI_IMR1_IM15_Pos (15U) +#define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */ +#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< Interrupt Mask on line 15 */ +#define EXTI_IMR1_IM16_Pos (16U) +#define EXTI_IMR1_IM16_Msk (0x1UL << EXTI_IMR1_IM16_Pos) /*!< 0x00010000 */ +#define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk /*!< Interrupt Mask on line 16 */ +#define EXTI_IMR1_IM17_Pos (17U) +#define EXTI_IMR1_IM17_Msk (0x1UL << EXTI_IMR1_IM17_Pos) /*!< 0x00020000 */ +#define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk /*!< Interrupt Mask on line 17 */ +#define EXTI_IMR1_IM18_Pos (18U) +#define EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */ +#define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< Interrupt Mask on line 18 */ + +/******************* Bit definition for EXTI_EMR1 register ******************/ +#define EXTI_EMR1_EM0_Pos (0U) +#define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */ +#define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< Event Mask on line 0 */ +#define EXTI_EMR1_EM1_Pos (1U) +#define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */ +#define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< Event Mask on line 1 */ +#define EXTI_EMR1_EM2_Pos (2U) +#define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */ +#define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< Event Mask on line 2 */ +#define EXTI_EMR1_EM3_Pos (3U) +#define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */ +#define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< Event Mask on line 3 */ +#define EXTI_EMR1_EM4_Pos (4U) +#define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */ +#define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< Event Mask on line 4 */ +#define EXTI_EMR1_EM5_Pos (5U) +#define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */ +#define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< Event Mask on line 5 */ +#define EXTI_EMR1_EM6_Pos (6U) +#define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */ +#define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< Event Mask on line 6 */ +#define EXTI_EMR1_EM7_Pos (7U) +#define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */ +#define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< Event Mask on line 7 */ +#define EXTI_EMR1_EM8_Pos (8U) +#define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */ +#define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< Event Mask on line 8 */ +#define EXTI_EMR1_EM9_Pos (9U) +#define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */ +#define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< Event Mask on line 9 */ +#define EXTI_EMR1_EM10_Pos (10U) +#define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */ +#define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< Event Mask on line 10 */ +#define EXTI_EMR1_EM11_Pos (11U) +#define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */ +#define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< Event Mask on line 11 */ +#define EXTI_EMR1_EM12_Pos (12U) +#define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */ +#define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< Event Mask on line 12 */ +#define EXTI_EMR1_EM13_Pos (13U) +#define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */ +#define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< Event Mask on line 13 */ +#define EXTI_EMR1_EM14_Pos (14U) +#define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */ +#define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< Event Mask on line 14 */ +#define EXTI_EMR1_EM15_Pos (15U) +#define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */ +#define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< Event Mask on line 15 */ +#define EXTI_EMR1_EM16_Pos (16U) +#define EXTI_EMR1_EM16_Msk (0x1UL << EXTI_EMR1_EM16_Pos) /*!< 0x00010000 */ +#define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk /*!< Event Mask on line 16 */ +#define EXTI_EMR1_EM17_Pos (17U) +#define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */ +#define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< Event Mask on line 17 */ +#define EXTI_EMR1_EM18_Pos (18U) +#define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */ +#define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< Event Mask on line 18 */ + + +/******************************************************************************/ +/* */ +/* FLASH */ +/* */ +/******************************************************************************/ +#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_0 /* FLASH Latency 1 Wait State */ + +/******************* Bits definition for FLASH_ACR register *****************/ +#define FLASH_ACR_LATENCY_Pos (0U) +#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */ +#define FLASH_ACR_LATENCY_0 (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */ +#define FLASH_ACR_LATENCY_1 (0x2UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */ +#define FLASH_ACR_LATENCY_2 (0x4UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000004 */ +#define FLASH_ACR_LATENCY_3 (0x8UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000008 */ +#define FLASH_ACR_PRFTEN_Pos (8U) +#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ +#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch enable */ +#define FLASH_ACR_LPM_Pos (11U) +#define FLASH_ACR_LPM_Msk (0x1UL << FLASH_ACR_LPM_Pos) /*!< 0x00000800 */ +#define FLASH_ACR_LPM FLASH_ACR_LPM_Msk /*!< Low-Power read mode */ +#define FLASH_ACR_PDREQ_Pos (12U) +#define FLASH_ACR_PDREQ_Msk (0x1UL << FLASH_ACR_PDREQ_Pos) /*!< 0x00001000 */ +#define FLASH_ACR_PDREQ FLASH_ACR_PDREQ_Msk /*!< Flash power-down mode request */ +#define FLASH_ACR_SLEEP_PD_Pos (14U) +#define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00004000 */ +#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash power-down mode during sleep */ + +/****************** Bits definition for FLASH_NSKEYR register *****************/ +#define FLASH_NSKEYR_NSKEY_Pos (0U) +#define FLASH_NSKEYR_NSKEY_Msk (0xFFFFFFFFUL << FLASH_NSKEYR_NSKEY_Pos) /*!< 0xFFFFFFFFF */ +#define FLASH_NSKEYR_NSKEY FLASH_NSKEYR_NSKEY_Msk /*!< Flash memory non-secure key */ + +/****************** Bits definition for FLASH_SECKEYR register *****************/ +#define FLASH_SECKEYR_SECKEY_Pos (0U) +#define FLASH_SECKEYR_SECKEY_Msk (0xFFFFFFFFUL << FLASH_SECKEYR_SECKEY_Pos) /*!< 0xFFFFFFFFF */ +#define FLASH_SECKEYR_SECKEY FLASH_SECKEYR_SECKEY_Msk /*!< Flash memory secure key */ + +/****************** Bits definition for FLASH_OPTKEYR register *****************/ +#define FLASH_OPTKEYR_OPTKEY_Pos (0U) +#define FLASH_OPTKEYR_OPTKEY_Msk (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEY_Pos) /*!< 0xFFFFFFFFF */ +#define FLASH_OPTKEYR_OPTKEY FLASH_OPTKEYR_OPTKEY_Msk /*!< Option byte key */ + +/****************** Bits definition for FLASH_PDKEYR register *****************/ +#define FLASH_PDKEYR_PDKEY_Pos (0U) +#define FLASH_PDKEYR_PDKEY_Msk (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEY_Pos) /*!< 0xFFFFFFFFF */ +#define FLASH_PDKEYR_PDKEY FLASH_PDKEYR_PDKEY_Msk /*!< Flash power-down key */ + +/****************** Bits definition for FLASH_NSSR register *****************/ +#define FLASH_NSSR_EOP_Pos (0U) +#define FLASH_NSSR_EOP_Msk (0x1UL << FLASH_NSSR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_NSSR_EOP FLASH_NSSR_EOP_Msk /*!< Non-secure end of operation */ +#define FLASH_NSSR_OPERR_Pos (1U) +#define FLASH_NSSR_OPERR_Msk (0x1UL << FLASH_NSSR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_NSSR_OPERR FLASH_NSSR_OPERR_Msk /*!< Non-secure operation error */ +#define FLASH_NSSR_PROGERR_Pos (3U) +#define FLASH_NSSR_PROGERR_Msk (0x1UL << FLASH_NSSR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_NSSR_PROGERR FLASH_NSSR_PROGERR_Msk /*!< Non-secure programming error */ +#define FLASH_NSSR_WRPERR_Pos (4U) +#define FLASH_NSSR_WRPERR_Msk (0x1UL << FLASH_NSSR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_NSSR_WRPERR FLASH_NSSR_WRPERR_Msk /*!< Non-secure write protection error */ +#define FLASH_NSSR_PGAERR_Pos (5U) +#define FLASH_NSSR_PGAERR_Msk (0x1UL << FLASH_NSSR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_NSSR_PGAERR FLASH_NSSR_PGAERR_Msk /*!< Non-secure programming alignment error */ +#define FLASH_NSSR_SIZERR_Pos (6U) +#define FLASH_NSSR_SIZERR_Msk (0x1UL << FLASH_NSSR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_NSSR_SIZERR FLASH_NSSR_SIZERR_Msk /*!< Non-secure size error */ +#define FLASH_NSSR_PGSERR_Pos (7U) +#define FLASH_NSSR_PGSERR_Msk (0x1UL << FLASH_NSSR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_NSSR_PGSERR FLASH_NSSR_PGSERR_Msk /*!< Non-secure programming sequence error */ +#define FLASH_NSSR_OPTWERR_Pos (13U) +#define FLASH_NSSR_OPTWERR_Msk (0x1UL << FLASH_NSSR_OPTWERR_Pos) /*!< 0x00002000 */ +#define FLASH_NSSR_OPTWERR FLASH_NSSR_OPTWERR_Msk /*!< Option write error */ +#define FLASH_NSSR_BSY_Pos (16U) +#define FLASH_NSSR_BSY_Msk (0x1UL << FLASH_NSSR_BSY_Pos) /*!< 0x00010000 */ +#define FLASH_NSSR_BSY FLASH_NSSR_BSY_Msk /*!< Non-secure busy */ +#define FLASH_NSSR_WDW_Pos (17U) +#define FLASH_NSSR_WDW_Msk (0x1UL << FLASH_NSSR_WDW_Pos) /*!< 0x00020000 */ +#define FLASH_NSSR_WDW FLASH_NSSR_WDW_Msk /*!< Non-secure wait data to write */ +#define FLASH_NSSR_OEM1LOCK_Pos (18U) +#define FLASH_NSSR_OEM1LOCK_Msk (0x1UL << FLASH_NSSR_OEM1LOCK_Pos) /*!< 0x00040000 */ +#define FLASH_NSSR_OEM1LOCK FLASH_NSSR_OEM1LOCK_Msk /*!< OEM1 lock */ +#define FLASH_NSSR_OEM2LOCK_Pos (19U) +#define FLASH_NSSR_OEM2LOCK_Msk (0x1UL << FLASH_NSSR_OEM2LOCK_Pos) /*!< 0x00080000 */ +#define FLASH_NSSR_OEM2LOCK FLASH_NSSR_OEM2LOCK_Msk /*!< OEM2 lock */ +#define FLASH_NSSR_PD_Pos (20U) +#define FLASH_NSSR_PD_Msk (0x1UL << FLASH_NSSR_PD_Pos) /*!< 0x00100000 */ +#define FLASH_NSSR_PD FLASH_NSSR_PD_Msk /*!< Flash in power-down mode */ + +/****************** Bits definition for FLASH_SECSR register ****************/ +#define FLASH_SECSR_EOP_Pos (0U) +#define FLASH_SECSR_EOP_Msk (0x1UL << FLASH_SECSR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_SECSR_EOP FLASH_SECSR_EOP_Msk /*!< Secure end of operation */ +#define FLASH_SECSR_OPERR_Pos (1U) +#define FLASH_SECSR_OPERR_Msk (0x1UL << FLASH_SECSR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_SECSR_OPERR FLASH_SECSR_OPERR_Msk /*!< Secure operation error */ +#define FLASH_SECSR_PROGERR_Pos (3U) +#define FLASH_SECSR_PROGERR_Msk (0x1UL << FLASH_SECSR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_SECSR_PROGERR FLASH_SECSR_PROGERR_Msk /*!< Secure programming error */ +#define FLASH_SECSR_WRPERR_Pos (4U) +#define FLASH_SECSR_WRPERR_Msk (0x1UL << FLASH_SECSR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_SECSR_WRPERR FLASH_SECSR_WRPERR_Msk /*!< Secure write protection error */ +#define FLASH_SECSR_PGAERR_Pos (5U) +#define FLASH_SECSR_PGAERR_Msk (0x1UL << FLASH_SECSR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_SECSR_PGAERR FLASH_SECSR_PGAERR_Msk /*!< Secure programming alignment error */ +#define FLASH_SECSR_SIZERR_Pos (6U) +#define FLASH_SECSR_SIZERR_Msk (0x1UL << FLASH_SECSR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_SECSR_SIZERR FLASH_SECSR_SIZERR_Msk /*!< Secure size error */ +#define FLASH_SECSR_PGSERR_Pos (7U) +#define FLASH_SECSR_PGSERR_Msk (0x1UL << FLASH_SECSR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_SECSR_PGSERR FLASH_SECSR_PGSERR_Msk /*!< Secure programming sequence error */ +#define FLASH_SECSR_BSY_Pos (16U) +#define FLASH_SECSR_BSY_Msk (0x1UL << FLASH_SECSR_BSY_Pos) /*!< 0x00010000 */ +#define FLASH_SECSR_BSY FLASH_SECSR_BSY_Msk /*!< Secure busy */ +#define FLASH_SECSR_WDW_Pos (17U) +#define FLASH_SECSR_WDW_Msk (0x1UL << FLASH_SECSR_WDW_Pos) /*!< 0x00020000 */ +#define FLASH_SECSR_WDW FLASH_SECSR_WDW_Msk /*!< Secure wait data to write */ + +/****************** Bits definition for FLASH_NSCR1 register *****************/ +#define FLASH_NSCR1_PG_Pos (0U) +#define FLASH_NSCR1_PG_Msk (0x1UL << FLASH_NSCR1_PG_Pos) /*!< 0x00000001 */ +#define FLASH_NSCR1_PG FLASH_NSCR1_PG_Msk /*!< Non-secure Programming */ +#define FLASH_NSCR1_PER_Pos (1U) +#define FLASH_NSCR1_PER_Msk (0x1UL << FLASH_NSCR1_PER_Pos) /*!< 0x00000002 */ +#define FLASH_NSCR1_PER FLASH_NSCR1_PER_Msk /*!< Non-secure Page Erase */ +#define FLASH_NSCR1_MER_Pos (2U) +#define FLASH_NSCR1_MER_Msk (0x1UL << FLASH_NSCR1_MER_Pos) /*!< 0x00000004 */ +#define FLASH_NSCR1_MER FLASH_NSCR1_MER_Msk /*!< Non-secure Mass Erase */ +#define FLASH_NSCR1_PNB_Pos (3U) +#define FLASH_NSCR1_PNB_Msk (0x7FUL << FLASH_NSCR1_PNB_Pos) /*!< 0x000003F8 */ +#define FLASH_NSCR1_PNB FLASH_NSCR1_PNB_Msk /*!< Non-secure Page Number selection */ +#define FLASH_NSCR1_BWR_Pos (14U) +#define FLASH_NSCR1_BWR_Msk (0x1UL << FLASH_NSCR1_BWR_Pos) /*!< 0x00004000 */ +#define FLASH_NSCR1_BWR FLASH_NSCR1_BWR_Msk /*!< Non-secure Burst Write Programming mode */ +#define FLASH_NSCR1_STRT_Pos (16U) +#define FLASH_NSCR1_STRT_Msk (0x1UL << FLASH_NSCR1_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_NSCR1_STRT FLASH_NSCR1_STRT_Msk /*!< Non-secure Start */ +#define FLASH_NSCR1_OPTSTRT_Pos (17U) +#define FLASH_NSCR1_OPTSTRT_Msk (0x1UL << FLASH_NSCR1_OPTSTRT_Pos) /*!< 0x00020000 */ +#define FLASH_NSCR1_OPTSTRT FLASH_NSCR1_OPTSTRT_Msk /*!< Option Modification Start */ +#define FLASH_NSCR1_EOPIE_Pos (24U) +#define FLASH_NSCR1_EOPIE_Msk (0x1UL << FLASH_NSCR1_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_NSCR1_EOPIE FLASH_NSCR1_EOPIE_Msk /*!< Non-secure End of operation interrupt enable */ +#define FLASH_NSCR1_ERRIE_Pos (25U) +#define FLASH_NSCR1_ERRIE_Msk (0x1UL << FLASH_NSCR1_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_NSCR1_ERRIE FLASH_NSCR1_ERRIE_Msk /*!< Non-secure error interrupt enable */ +#define FLASH_NSCR1_OBL_LAUNCH_Pos (27U) +#define FLASH_NSCR1_OBL_LAUNCH_Msk (0x1UL << FLASH_NSCR1_OBL_LAUNCH_Pos) /*!< 0x08000000 */ +#define FLASH_NSCR1_OBL_LAUNCH FLASH_NSCR1_OBL_LAUNCH_Msk /*!< Force the option byte loading */ +#define FLASH_NSCR1_OPTLOCK_Pos (30U) +#define FLASH_NSCR1_OPTLOCK_Msk (0x1UL << FLASH_NSCR1_OPTLOCK_Pos) /*!< 0x40000000 */ +#define FLASH_NSCR1_OPTLOCK FLASH_NSCR1_OPTLOCK_Msk /*!< Option Lock */ +#define FLASH_NSCR1_LOCK_Pos (31U) +#define FLASH_NSCR1_LOCK_Msk (0x1UL << FLASH_NSCR1_LOCK_Pos) /*!< 0x80000000 */ +#define FLASH_NSCR1_LOCK FLASH_NSCR1_LOCK_Msk /*!< Non-secure Lock */ + +/****************** Bits definition for FLASH_SECCR1 register ****************/ +#define FLASH_SECCR1_PG_Pos (0U) +#define FLASH_SECCR1_PG_Msk (0x1UL << FLASH_SECCR1_PG_Pos) /*!< 0x00000001 */ +#define FLASH_SECCR1_PG FLASH_SECCR1_PG_Msk /*!< Secure Programming */ +#define FLASH_SECCR1_PER_Pos (1U) +#define FLASH_SECCR1_PER_Msk (0x1UL << FLASH_SECCR1_PER_Pos) /*!< 0x00000002 */ +#define FLASH_SECCR1_PER FLASH_SECCR1_PER_Msk /*!< Secure Page Erase */ +#define FLASH_SECCR1_MER_Pos (2U) +#define FLASH_SECCR1_MER_Msk (0x1UL << FLASH_SECCR1_MER_Pos) /*!< 0x00000004 */ +#define FLASH_SECCR1_MER FLASH_SECCR1_MER_Msk /*!< Secure Bank 1 Mass Erase */ +#define FLASH_SECCR1_PNB_Pos (3U) +#define FLASH_SECCR1_PNB_Msk (0x7FUL << FLASH_SECCR1_PNB_Pos) /*!< 0x000003F8 */ +#define FLASH_SECCR1_PNB FLASH_SECCR1_PNB_Msk /*!< Secure Page Number selection */ +#define FLASH_SECCR1_BWR_Pos (14U) +#define FLASH_SECCR1_BWR_Msk (0x1UL << FLASH_SECCR1_BWR_Pos) /*!< 0x00004000 */ +#define FLASH_SECCR1_BWR FLASH_SECCR1_BWR_Msk /*!< Secure Burst Write programming mode */ +#define FLASH_SECCR1_STRT_Pos (16U) +#define FLASH_SECCR1_STRT_Msk (0x1UL << FLASH_SECCR1_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_SECCR1_STRT FLASH_SECCR1_STRT_Msk /*!< Secure Start */ +#define FLASH_SECCR1_EOPIE_Pos (24U) +#define FLASH_SECCR1_EOPIE_Msk (0x1UL << FLASH_SECCR1_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_SECCR1_EOPIE FLASH_SECCR1_EOPIE_Msk /*!< Secure end of operation interrupt enable */ +#define FLASH_SECCR1_ERRIE_Pos (25U) +#define FLASH_SECCR1_ERRIE_Msk (0x1UL << FLASH_SECCR1_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_SECCR1_ERRIE FLASH_SECCR1_ERRIE_Msk /*!< Secure error interrupt enable */ +#define FLASH_SECCR1_INV_Pos (29U) +#define FLASH_SECCR1_INV_Msk (0x1UL << FLASH_SECCR1_INV_Pos) /*!< 0x20000000 */ +#define FLASH_SECCR1_INV FLASH_SECCR1_INV_Msk /*!< Flash Security State Invert */ +#define FLASH_SECCR1_LOCK_Pos (31U) +#define FLASH_SECCR1_LOCK_Msk (0x1UL << FLASH_SECCR1_LOCK_Pos) /*!< 0x80000000 */ +#define FLASH_SECCR1_LOCK FLASH_SECCR1_LOCK_Msk /*!< Secure Lock */ + +/******************* Bits definition for FLASH_ECCR register ***************/ +#define FLASH_ECCR_ADDR_ECC_Pos (0U) +#define FLASH_ECCR_ADDR_ECC_Msk (0xFFFFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x000FFFFF */ +#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk /*!< ECC fail address */ +#define FLASH_ECCR_SYSF_ECC_Pos (22U) +#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk /*!< System Flash ECC fail */ +#define FLASH_ECCR_ECCIE_Pos (24U) +#define FLASH_ECCR_ECCIE_Msk (0x1UL << FLASH_ECCR_ECCIE_Pos) /*!< 0x01000000 */ +#define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk /*!< ECC correction interrupt enable */ +#define FLASH_ECCR_ECCC_Pos (30U) +#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */ +#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk /*!< ECC correction */ +#define FLASH_ECCR_ECCD_Pos (31U) +#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */ +#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk /*!< ECC detection */ + +/******************* Bits definition for FLASH_OPSR register ***************/ +#define FLASH_OPSR_ADDR_OP_Pos (0U) +#define FLASH_OPSR_ADDR_OP_Msk (0xFFFFFUL << FLASH_OPSR_ADDR_OP_Pos) /*!< 0x000FFFFF */ +#define FLASH_OPSR_ADDR_OP FLASH_OPSR_ADDR_OP_Msk /*!< Interrupted operation address */ +#define FLASH_OPSR_SYSF_OP_Pos (22U) +#define FLASH_OPSR_SYSF_OP_Msk (0x1UL << FLASH_OPSR_SYSF_OP_Pos) /*!< 0x00400000 */ +#define FLASH_OPSR_SYSF_OP FLASH_OPSR_SYSF_OP_Msk /*!< Operation in system Flash memory interrupted */ +#define FLASH_OPSR_CODE_OP_Pos (29U) +#define FLASH_OPSR_CODE_OP_Msk (0x7UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x07000000 */ +#define FLASH_OPSR_CODE_OP FLASH_OPSR_CODE_OP_Msk /*!< Flash memory operation code */ +#define FLASH_OPSR_CODE_OP_0 (0x1UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x01000000 */ +#define FLASH_OPSR_CODE_OP_1 (0x2UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x02000000 */ +#define FLASH_OPSR_CODE_OP_2 (0x4UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x04000000 */ + +/******************* Bits definition for FLASH_NSCR2 register ***************/ +#define FLASH_NSCR2_PS_Pos (0U) +#define FLASH_NSCR2_PS_Msk (0x1UL << FLASH_NSCR2_PS_Pos) /*!< 0x00000001 */ +#define FLASH_NSCR2_PS FLASH_NSCR2_PS_Msk /*!< Program suspend request */ +#define FLASH_NSCR2_ES_Pos (1U) +#define FLASH_NSCR2_ES_Msk (0x1UL << FLASH_NSCR2_ES_Pos) /*!< 0x00000002 */ +#define FLASH_NSCR2_ES FLASH_NSCR2_ES_Msk /*!< Erase suspend request */ + +/******************* Bits definition for FLASH_SECCR2 register ***************/ +#define FLASH_SECCR2_PS_Pos (0U) +#define FLASH_SECCR2_PS_Msk (0x1UL << FLASH_SECCR2_PS_Pos) /*!< 0x00000001 */ +#define FLASH_SECCR2_PS FLASH_SECCR2_PS_Msk /*!< Program suspend request */ +#define FLASH_SECCR2_ES_Pos (1U) +#define FLASH_SECCR2_ES_Msk (0x1UL << FLASH_SECCR2_ES_Pos) /*!< 0x00000002 */ +#define FLASH_SECCR2_ES FLASH_SECCR2_ES_Msk /*!< Erase suspend request */ + +/******************* Bits definition for FLASH_OPTR register ***************/ +#define FLASH_OPTR_RDP_Pos (0U) +#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */ +#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk /*!< Readout protection level */ +#define FLASH_OPTR_BOR_LEV_Pos (8U) +#define FLASH_OPTR_BOR_LEV_Msk (0x7UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000700 */ +#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR reset Level */ +#define FLASH_OPTR_BOR_LEV_0 (0x1UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000100 */ +#define FLASH_OPTR_BOR_LEV_1 (0x2UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000200 */ +#define FLASH_OPTR_BOR_LEV_2 (0x4UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000400 */ +#define FLASH_OPTR_nRST_STOP_Pos (12U) +#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00001000 */ +#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< nRST_STOP */ +#define FLASH_OPTR_nRST_STDBY_Pos (13U) +#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */ +#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< nRST_STDBY */ +#define FLASH_OPTR_SRAM1_RST_Pos (15U) +#define FLASH_OPTR_SRAM1_RST_Msk (0x1UL << FLASH_OPTR_SRAM1_RST_Pos) /*!< 0x00008000 */ +#define FLASH_OPTR_SRAM1_RST FLASH_OPTR_SRAM1_RST_Msk /*!< SRAM1 erase upon system reset */ +#define FLASH_OPTR_IWDG_SW_Pos (16U) +#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */ +#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< Independent watchdog selection */ +#define FLASH_OPTR_IWDG_STOP_Pos (17U) +#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */ +#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk /*!< Independent watchdog counter freeze in Stop mode */ +#define FLASH_OPTR_IWDG_STDBY_Pos (18U) +#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */ +#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk /*!< Independent watchdog counter freeze in Standby mode */ +#define FLASH_OPTR_WWDG_SW_Pos (19U) +#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */ +#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk /*!< Window watchdog selection */ +#define FLASH_OPTR_SRAM2_PE_Pos (24U) +#define FLASH_OPTR_SRAM2_PE_Msk (0x1UL << FLASH_OPTR_SRAM2_PE_Pos) /*!< 0x01000000 */ +#define FLASH_OPTR_SRAM2_PE FLASH_OPTR_SRAM2_PE_Msk /*!< SRAM2 ECC detection and correction enable*/ +#define FLASH_OPTR_SRAM2_RST_Pos (25U) +#define FLASH_OPTR_SRAM2_RST_Msk (0x1UL << FLASH_OPTR_SRAM2_RST_Pos) /*!< 0x02000000 */ +#define FLASH_OPTR_SRAM2_RST FLASH_OPTR_SRAM2_RST_Msk /*!< SRAM2 erase when system reset */ +#define FLASH_OPTR_nSWBOOT0_Pos (26U) +#define FLASH_OPTR_nSWBOOT0_Msk (0x1UL << FLASH_OPTR_nSWBOOT0_Pos) /*!< 0x04000000 */ +#define FLASH_OPTR_nSWBOOT0 FLASH_OPTR_nSWBOOT0_Msk /*!< Software BOOT0 */ +#define FLASH_OPTR_nBOOT0_Pos (27U) +#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x08000000 */ +#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk /*!< nBOOT0 option bit */ +#define FLASH_OPTR_TZEN_Pos (31U) +#define FLASH_OPTR_TZEN_Msk (0x1UL << FLASH_OPTR_TZEN_Pos) /*!< 0x80000000 */ +#define FLASH_OPTR_TZEN FLASH_OPTR_TZEN_Msk /*!< Global TrustZone security enable */ + +/**************** Bits definition for FLASH_NSBOOTADD0R register ************/ +#define FLASH_NSBOOTADD0R_NSBOOTADD0_Pos (7U) +#define FLASH_NSBOOTADD0R_NSBOOTADD0_Msk (0x1FFFFFFUL << FLASH_NSBOOTADD0R_NSBOOTADD0_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_NSBOOTADD0R_NSBOOTADD0 FLASH_NSBOOTADD0R_NSBOOTADD0_Msk /*!< Non-secure boot address 0 */ + +/**************** Bits definition for FLASH_NSBOOTADD1R register ************/ +#define FLASH_NSBOOTADD1R_NSBOOTADD1_Pos (7U) +#define FLASH_NSBOOTADD1R_NSBOOTADD1_Msk (0x1FFFFFFUL << FLASH_NSBOOTADD1R_NSBOOTADD1_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_NSBOOTADD1R_NSBOOTADD1 FLASH_NSBOOTADD1R_NSBOOTADD1_Msk /*!< Non-secure boot address 1 */ + +/**************** Bits definition for FLASH_SECBOOTADD0R register ***********/ +#define FLASH_SECBOOTADD0R_BOOT_LOCK_Pos (0U) +#define FLASH_SECBOOTADD0R_BOOT_LOCK_Msk (0x1UL << FLASH_SECBOOTADD0R_BOOT_LOCK_Pos) /*!< 0x00000001 */ +#define FLASH_SECBOOTADD0R_BOOT_LOCK FLASH_SECBOOTADD0R_BOOT_LOCK_Msk /*!< Boot Lock */ +#define FLASH_SECBOOTADD0R_SECBOOTADD0_Pos (7U) +#define FLASH_SECBOOTADD0R_SECBOOTADD0_Msk (0x1FFFFFFUL << FLASH_SECBOOTADD0R_SECBOOTADD0_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_SECBOOTADD0R_SECBOOTADD0 FLASH_SECBOOTADD0R_SECBOOTADD0_Msk /*!< Secure boot address 0 */ + +/***************** Bits definition for FLASH_SECWMR1 register **************/ +#define FLASH_SECWMR1_SECWM_PSTRT_Pos (0U) +#define FLASH_SECWMR1_SECWM_PSTRT_Msk (0x7FUL << FLASH_SECWMR1_SECWM_PSTRT_Pos) /*!< 0x0000007F */ +#define FLASH_SECWMR1_SECWM_PSTRT FLASH_SECWMR1_SECWM_PSTRT_Msk /*!< Start page of first secure area */ +#define FLASH_SECWMR1_SECWM_PEND_Pos (16U) +#define FLASH_SECWMR1_SECWM_PEND_Msk (0x7FUL << FLASH_SECWMR1_SECWM_PEND_Pos) /*!< 0x007F0000 */ +#define FLASH_SECWMR1_SECWM_PEND FLASH_SECWMR1_SECWM_PEND_Msk /*!< End page of first secure area */ + +/***************** Bits definition for FLASH_SECWMR2 register **************/ +#define FLASH_SECWMR2_HDP_PEND_Pos (16U) +#define FLASH_SECWMR2_HDP_PEND_Msk (0x7FUL << FLASH_SECWMR2_HDP_PEND_Pos) /*!< 0x007F0000 */ +#define FLASH_SECWMR2_HDP_PEND FLASH_SECWMR2_HDP_PEND_Msk /*!< End page of first hide protection area */ +#define FLASH_SECWMR2_HDPEN_Pos (31U) +#define FLASH_SECWMR2_HDPEN_Msk (0x1UL << FLASH_SECWMR2_HDPEN_Pos) /*!< 0x80000000 */ +#define FLASH_SECWMR2_HDPEN FLASH_SECWMR2_HDPEN_Msk /*!< Hide protection first area enable */ + +/****************** Bits definition for FLASH_WRPAR register ***************/ +#define FLASH_WRPAR_WRPA_PSTRT_Pos (0U) +#define FLASH_WRPAR_WRPA_PSTRT_Msk (0x7FUL << FLASH_WRPAR_WRPA_PSTRT_Pos) /*!< 0x0000007F */ +#define FLASH_WRPAR_WRPA_PSTRT FLASH_WRPAR_WRPA_PSTRT_Msk /*!< WPR first area A start page */ +#define FLASH_WRPAR_WRPA_PEND_Pos (16U) +#define FLASH_WRPAR_WRPA_PEND_Msk (0x7FUL << FLASH_WRPAR_WRPA_PEND_Pos) /*!< 0x007F0000 */ +#define FLASH_WRPAR_WRPA_PEND FLASH_WRPAR_WRPA_PEND_Msk /*!< WPR first area A end page */ +#define FLASH_WRPAR_UNLOCK_Pos (31U) +#define FLASH_WRPAR_UNLOCK_Msk (0x1UL << FLASH_WRPAR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRPAR_UNLOCK FLASH_WRPAR_UNLOCK_Msk /*!< WPR first area A unlock */ + +/****************** Bits definition for FLASH_WRPBR register ***************/ +#define FLASH_WRPBR_WRPB_PSTRT_Pos (0U) +#define FLASH_WRPBR_WRPB_PSTRT_Msk (0x7FUL << FLASH_WRPBR_WRPB_PSTRT_Pos) /*!< 0x0000007F */ +#define FLASH_WRPBR_WRPB_PSTRT FLASH_WRPBR_WRPB_PSTRT_Msk /*!< WPR second area B start page */ +#define FLASH_WRPBR_WRPB_PEND_Pos (16U) +#define FLASH_WRPBR_WRPB_PEND_Msk (0x7FUL << FLASH_WRPBR_WRPB_PEND_Pos) /*!< 0x007F0000 */ +#define FLASH_WRPBR_WRPB_PEND FLASH_WRPBR_WRPB_PEND_Msk /*!< WPR second area B end page */ +#define FLASH_WRPBR_UNLOCK_Pos (31U) +#define FLASH_WRPBR_UNLOCK_Msk (0x1UL << FLASH_WRPBR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRPBR_UNLOCK FLASH_WRPBR_UNLOCK_Msk /*!< WPR first area B unlock */ + +/****************** Bits definition for FLASH_OEM1KEYR1 register *****************/ +#define FLASH_OEM1KEYR1_OEM1KEY_Pos (0U) +#define FLASH_OEM1KEYR1_OEM1KEY_Msk (0xFFFFFFFFUL << FLASH_OEM1KEYR1_OEM1KEY_Pos) /*!< 0xFFFFFFFFF */ +#define FLASH_OEM1KEYR1_OEM1KEY FLASH_OEM1KEYR1_OEM1KEY_Msk /*!< OEM1 least significant bytes key */ + +/****************** Bits definition for FLASH_OEM1KEYR2 register *****************/ +#define FLASH_OEM1KEYR2_OEM1KEY_Pos (0U) +#define FLASH_OEM1KEYR2_OEM1KEY_Msk (0xFFFFFFFFUL << FLASH_OEM1KEYR2_OEM1KEY_Pos) /*!< 0xFFFFFFFFF */ +#define FLASH_OEM1KEYR2_OEM1KEY FLASH_OEM1KEYR2_OEM1KEY_Msk /*!< OEM1 most significant bytes key */ + +/****************** Bits definition for FLASH_OEM2KEYR1 register *****************/ +#define FLASH_OEM2KEYR1_OEM2KEY_Pos (0U) +#define FLASH_OEM2KEYR1_OEM2KEY_Msk (0xFFFFFFFFUL << FLASH_OEM2KEYR1_OEM2KEY_Pos) /*!< 0xFFFFFFFFF */ +#define FLASH_OEM2KEYR1_OEM2KEY FLASH_OEM2KEYR1_OEM2KEY_Msk /*!< OEM2 least significant bytes key */ + +/****************** Bits definition for FLASH_OEM2KEYR2 register *****************/ +#define FLASH_OEM2KEYR2_OEM2KEY_Pos (0U) +#define FLASH_OEM2KEYR2_OEM2KEY_Msk (0xFFFFFFFFUL << FLASH_OEM2KEYR2_OEM2KEY_Pos) /*!< 0xFFFFFFFFF */ +#define FLASH_OEM2KEYR2_OEM2KEY FLASH_OEM2KEYR2_OEM2KEY_Msk /*!< OEM2 most significant bytes key */ + +/******************* Bit definition for FLASH_SECBBR1 register ******************/ +#define FLASH_SECBBR1_SECBB0_Pos (0U) +#define FLASH_SECBBR1_SECBB0_Msk (0x1UL << FLASH_SECBBR1_SECBB0_Pos) /*!< 0x00000001 */ +#define FLASH_SECBBR1_SECBB0 FLASH_SECBBR1_SECBB0_Msk /*!< Page 0 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB1_Pos (1U) +#define FLASH_SECBBR1_SECBB1_Msk (0x1UL << FLASH_SECBBR1_SECBB1_Pos) /*!< 0x00000002 */ +#define FLASH_SECBBR1_SECBB1 FLASH_SECBBR1_SECBB1_Msk /*!< Page 1 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB2_Pos (2U) +#define FLASH_SECBBR1_SECBB2_Msk (0x1UL << FLASH_SECBBR1_SECBB2_Pos) /*!< 0x00000004 */ +#define FLASH_SECBBR1_SECBB2 FLASH_SECBBR1_SECBB2_Msk /*!< Page 2 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB3_Pos (3U) +#define FLASH_SECBBR1_SECBB3_Msk (0x1UL << FLASH_SECBBR1_SECBB3_Pos) /*!< 0x00000008 */ +#define FLASH_SECBBR1_SECBB3 FLASH_SECBBR1_SECBB3_Msk /*!< Page 3 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB4_Pos (4U) +#define FLASH_SECBBR1_SECBB4_Msk (0x1UL << FLASH_SECBBR1_SECBB4_Pos) /*!< 0x00000010 */ +#define FLASH_SECBBR1_SECBB4 FLASH_SECBBR1_SECBB4_Msk /*!< Page 4 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB5_Pos (5U) +#define FLASH_SECBBR1_SECBB5_Msk (0x1UL << FLASH_SECBBR1_SECBB5_Pos) /*!< 0x00000020 */ +#define FLASH_SECBBR1_SECBB5 FLASH_SECBBR1_SECBB5_Msk /*!< Page 5 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB6_Pos (6U) +#define FLASH_SECBBR1_SECBB6_Msk (0x1UL << FLASH_SECBBR1_SECBB6_Pos) /*!< 0x00000040 */ +#define FLASH_SECBBR1_SECBB6 FLASH_SECBBR1_SECBB6_Msk /*!< Page 6 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB7_Pos (7U) +#define FLASH_SECBBR1_SECBB7_Msk (0x1UL << FLASH_SECBBR1_SECBB7_Pos) /*!< 0x00000080 */ +#define FLASH_SECBBR1_SECBB7 FLASH_SECBBR1_SECBB7_Msk /*!< Page 7 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB8_Pos (8U) +#define FLASH_SECBBR1_SECBB8_Msk (0x1UL << FLASH_SECBBR1_SECBB8_Pos) /*!< 0x00000100 */ +#define FLASH_SECBBR1_SECBB8 FLASH_SECBBR1_SECBB8_Msk /*!< Page 8 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB9_Pos (9U) +#define FLASH_SECBBR1_SECBB9_Msk (0x1UL << FLASH_SECBBR1_SECBB9_Pos) /*!< 0x00000200 */ +#define FLASH_SECBBR1_SECBB9 FLASH_SECBBR1_SECBB9_Msk /*!< Page 9 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB10_Pos (10U) +#define FLASH_SECBBR1_SECBB10_Msk (0x1UL << FLASH_SECBBR1_SECBB10_Pos) /*!< 0x00000400 */ +#define FLASH_SECBBR1_SECBB10 FLASH_SECBBR1_SECBB10_Msk /*!< Page 10 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB11_Pos (11U) +#define FLASH_SECBBR1_SECBB11_Msk (0x1UL << FLASH_SECBBR1_SECBB11_Pos) /*!< 0x00000800 */ +#define FLASH_SECBBR1_SECBB11 FLASH_SECBBR1_SECBB11_Msk /*!< Page 11 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB12_Pos (12U) +#define FLASH_SECBBR1_SECBB12_Msk (0x1UL << FLASH_SECBBR1_SECBB12_Pos) /*!< 0x00001000 */ +#define FLASH_SECBBR1_SECBB12 FLASH_SECBBR1_SECBB12_Msk /*!< Page 12 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB13_Pos (13U) +#define FLASH_SECBBR1_SECBB13_Msk (0x1UL << FLASH_SECBBR1_SECBB13_Pos) /*!< 0x00002000 */ +#define FLASH_SECBBR1_SECBB13 FLASH_SECBBR1_SECBB13_Msk /*!< Page 13 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB14_Pos (14U) +#define FLASH_SECBBR1_SECBB14_Msk (0x1UL << FLASH_SECBBR1_SECBB14_Pos) /*!< 0x00004000 */ +#define FLASH_SECBBR1_SECBB14 FLASH_SECBBR1_SECBB14_Msk /*!< Page 14 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB15_Pos (15U) +#define FLASH_SECBBR1_SECBB15_Msk (0x1UL << FLASH_SECBBR1_SECBB15_Pos) /*!< 0x00008000 */ +#define FLASH_SECBBR1_SECBB15 FLASH_SECBBR1_SECBB15_Msk /*!< Page 15 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB16_Pos (16U) +#define FLASH_SECBBR1_SECBB16_Msk (0x1UL << FLASH_SECBBR1_SECBB16_Pos) /*!< 0x00010000 */ +#define FLASH_SECBBR1_SECBB16 FLASH_SECBBR1_SECBB16_Msk /*!< Page 16 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB17_Pos (17U) +#define FLASH_SECBBR1_SECBB17_Msk (0x1UL << FLASH_SECBBR1_SECBB17_Pos) /*!< 0x00020000 */ +#define FLASH_SECBBR1_SECBB17 FLASH_SECBBR1_SECBB17_Msk /*!< Page 17 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB18_Pos (18U) +#define FLASH_SECBBR1_SECBB18_Msk (0x1UL << FLASH_SECBBR1_SECBB18_Pos) /*!< 0x00040000 */ +#define FLASH_SECBBR1_SECBB18 FLASH_SECBBR1_SECBB18_Msk /*!< Page 18 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB19_Pos (19U) +#define FLASH_SECBBR1_SECBB19_Msk (0x1UL << FLASH_SECBBR1_SECBB19_Pos) /*!< 0x00080000 */ +#define FLASH_SECBBR1_SECBB19 FLASH_SECBBR1_SECBB19_Msk /*!< Page 19 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB20_Pos (20U) +#define FLASH_SECBBR1_SECBB20_Msk (0x1UL << FLASH_SECBBR1_SECBB20_Pos) /*!< 0x00100000 */ +#define FLASH_SECBBR1_SECBB20 FLASH_SECBBR1_SECBB20_Msk /*!< Page 20 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB21_Pos (21U) +#define FLASH_SECBBR1_SECBB21_Msk (0x1UL << FLASH_SECBBR1_SECBB21_Pos) /*!< 0x00200000 */ +#define FLASH_SECBBR1_SECBB21 FLASH_SECBBR1_SECBB21_Msk /*!< Page 21 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB22_Pos (22U) +#define FLASH_SECBBR1_SECBB22_Msk (0x1UL << FLASH_SECBBR1_SECBB22_Pos) /*!< 0x00400000 */ +#define FLASH_SECBBR1_SECBB22 FLASH_SECBBR1_SECBB22_Msk /*!< Page 22 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB23_Pos (23U) +#define FLASH_SECBBR1_SECBB23_Msk (0x1UL << FLASH_SECBBR1_SECBB23_Pos) /*!< 0x00800000 */ +#define FLASH_SECBBR1_SECBB23 FLASH_SECBBR1_SECBB23_Msk /*!< Page 23 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB24_Pos (24U) +#define FLASH_SECBBR1_SECBB24_Msk (0x1UL << FLASH_SECBBR1_SECBB24_Pos) /*!< 0x01000000 */ +#define FLASH_SECBBR1_SECBB24 FLASH_SECBBR1_SECBB24_Msk /*!< Page 24 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB25_Pos (25U) +#define FLASH_SECBBR1_SECBB25_Msk (0x1UL << FLASH_SECBBR1_SECBB25_Pos) /*!< 0x02000000 */ +#define FLASH_SECBBR1_SECBB25 FLASH_SECBBR1_SECBB25_Msk /*!< Page 25 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB26_Pos (26U) +#define FLASH_SECBBR1_SECBB26_Msk (0x1UL << FLASH_SECBBR1_SECBB26_Pos) /*!< 0x04000000 */ +#define FLASH_SECBBR1_SECBB26 FLASH_SECBBR1_SECBB26_Msk /*!< Page 26 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB27_Pos (27U) +#define FLASH_SECBBR1_SECBB27_Msk (0x1UL << FLASH_SECBBR1_SECBB27_Pos) /*!< 0x08000000 */ +#define FLASH_SECBBR1_SECBB27 FLASH_SECBBR1_SECBB27_Msk /*!< Page 27 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB28_Pos (28U) +#define FLASH_SECBBR1_SECBB28_Msk (0x1UL << FLASH_SECBBR1_SECBB28_Pos) /*!< 0x10000000 */ +#define FLASH_SECBBR1_SECBB28 FLASH_SECBBR1_SECBB28_Msk /*!< Page 28 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB29_Pos (29U) +#define FLASH_SECBBR1_SECBB29_Msk (0x1UL << FLASH_SECBBR1_SECBB29_Pos) /*!< 0x20000000 */ +#define FLASH_SECBBR1_SECBB29 FLASH_SECBBR1_SECBB29_Msk /*!< Page 29 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB30_Pos (30U) +#define FLASH_SECBBR1_SECBB30_Msk (0x1UL << FLASH_SECBBR1_SECBB30_Pos) /*!< 0x40000000 */ +#define FLASH_SECBBR1_SECBB30 FLASH_SECBBR1_SECBB30_Msk /*!< Page 30 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB31_Pos (31U) +#define FLASH_SECBBR1_SECBB31_Msk (0x1UL << FLASH_SECBBR1_SECBB31_Pos) /*!< 0x80000000 */ +#define FLASH_SECBBR1_SECBB31 FLASH_SECBBR1_SECBB31_Msk /*!< Page 31 in Flash block-based secure */ + +/******************* Bit definition for FLASH_SECBBR2 register ******************/ +#define FLASH_SECBBR2_SECBB0_Pos (0U) +#define FLASH_SECBBR2_SECBB0_Msk (0x1UL << FLASH_SECBBR2_SECBB0_Pos) /*!< 0x00000001 */ +#define FLASH_SECBBR2_SECBB0 FLASH_SECBBR2_SECBB0_Msk /*!< Page 32 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB1_Pos (1U) +#define FLASH_SECBBR2_SECBB1_Msk (0x1UL << FLASH_SECBBR2_SECBB1_Pos) /*!< 0x00000002 */ +#define FLASH_SECBBR2_SECBB1 FLASH_SECBBR2_SECBB1_Msk /*!< Page 33 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB2_Pos (2U) +#define FLASH_SECBBR2_SECBB2_Msk (0x1UL << FLASH_SECBBR2_SECBB2_Pos) /*!< 0x00000004 */ +#define FLASH_SECBBR2_SECBB2 FLASH_SECBBR2_SECBB2_Msk /*!< Page 34 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB3_Pos (3U) +#define FLASH_SECBBR2_SECBB3_Msk (0x1UL << FLASH_SECBBR2_SECBB3_Pos) /*!< 0x00000008 */ +#define FLASH_SECBBR2_SECBB3 FLASH_SECBBR2_SECBB3_Msk /*!< Page 35 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB4_Pos (4U) +#define FLASH_SECBBR2_SECBB4_Msk (0x1UL << FLASH_SECBBR2_SECBB4_Pos) /*!< 0x00000010 */ +#define FLASH_SECBBR2_SECBB4 FLASH_SECBBR2_SECBB4_Msk /*!< Page 36 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB5_Pos (5U) +#define FLASH_SECBBR2_SECBB5_Msk (0x1UL << FLASH_SECBBR2_SECBB5_Pos) /*!< 0x00000020 */ +#define FLASH_SECBBR2_SECBB5 FLASH_SECBBR2_SECBB5_Msk /*!< Page 37 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB6_Pos (6U) +#define FLASH_SECBBR2_SECBB6_Msk (0x1UL << FLASH_SECBBR2_SECBB6_Pos) /*!< 0x00000040 */ +#define FLASH_SECBBR2_SECBB6 FLASH_SECBBR2_SECBB6_Msk /*!< Page 38 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB7_Pos (7U) +#define FLASH_SECBBR2_SECBB7_Msk (0x1UL << FLASH_SECBBR2_SECBB7_Pos) /*!< 0x00000080 */ +#define FLASH_SECBBR2_SECBB7 FLASH_SECBBR2_SECBB7_Msk /*!< Page 39 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB8_Pos (8U) +#define FLASH_SECBBR2_SECBB8_Msk (0x1UL << FLASH_SECBBR2_SECBB8_Pos) /*!< 0x00000100 */ +#define FLASH_SECBBR2_SECBB8 FLASH_SECBBR2_SECBB8_Msk /*!< Page 40 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB9_Pos (9U) +#define FLASH_SECBBR2_SECBB9_Msk (0x1UL << FLASH_SECBBR2_SECBB9_Pos) /*!< 0x00000200 */ +#define FLASH_SECBBR2_SECBB9 FLASH_SECBBR2_SECBB9_Msk /*!< Page 41 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB10_Pos (10U) +#define FLASH_SECBBR2_SECBB10_Msk (0x1UL << FLASH_SECBBR2_SECBB10_Pos) /*!< 0x00000400 */ +#define FLASH_SECBBR2_SECBB10 FLASH_SECBBR2_SECBB10_Msk /*!< Page 42 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB11_Pos (11U) +#define FLASH_SECBBR2_SECBB11_Msk (0x1UL << FLASH_SECBBR2_SECBB11_Pos) /*!< 0x00000800 */ +#define FLASH_SECBBR2_SECBB11 FLASH_SECBBR2_SECBB11_Msk /*!< Page 43 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB12_Pos (12U) +#define FLASH_SECBBR2_SECBB12_Msk (0x1UL << FLASH_SECBBR2_SECBB12_Pos) /*!< 0x00001000 */ +#define FLASH_SECBBR2_SECBB12 FLASH_SECBBR2_SECBB12_Msk /*!< Page 44 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB13_Pos (13U) +#define FLASH_SECBBR2_SECBB13_Msk (0x1UL << FLASH_SECBBR2_SECBB13_Pos) /*!< 0x00002000 */ +#define FLASH_SECBBR2_SECBB13 FLASH_SECBBR2_SECBB13_Msk /*!< Page 45 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB14_Pos (14U) +#define FLASH_SECBBR2_SECBB14_Msk (0x1UL << FLASH_SECBBR2_SECBB14_Pos) /*!< 0x00004000 */ +#define FLASH_SECBBR2_SECBB14 FLASH_SECBBR2_SECBB14_Msk /*!< Page 46 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB15_Pos (15U) +#define FLASH_SECBBR2_SECBB15_Msk (0x1UL << FLASH_SECBBR2_SECBB15_Pos) /*!< 0x00008000 */ +#define FLASH_SECBBR2_SECBB15 FLASH_SECBBR2_SECBB15_Msk /*!< Page 47 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB16_Pos (16U) +#define FLASH_SECBBR2_SECBB16_Msk (0x1UL << FLASH_SECBBR2_SECBB16_Pos) /*!< 0x00010000 */ +#define FLASH_SECBBR2_SECBB16 FLASH_SECBBR2_SECBB16_Msk /*!< Page 48 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB17_Pos (17U) +#define FLASH_SECBBR2_SECBB17_Msk (0x1UL << FLASH_SECBBR2_SECBB17_Pos) /*!< 0x00020000 */ +#define FLASH_SECBBR2_SECBB17 FLASH_SECBBR2_SECBB17_Msk /*!< Page 49 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB18_Pos (18U) +#define FLASH_SECBBR2_SECBB18_Msk (0x1UL << FLASH_SECBBR2_SECBB18_Pos) /*!< 0x00040000 */ +#define FLASH_SECBBR2_SECBB18 FLASH_SECBBR2_SECBB18_Msk /*!< Page 50 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB19_Pos (19U) +#define FLASH_SECBBR2_SECBB19_Msk (0x1UL << FLASH_SECBBR2_SECBB19_Pos) /*!< 0x00080000 */ +#define FLASH_SECBBR2_SECBB19 FLASH_SECBBR2_SECBB19_Msk /*!< Page 51 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB20_Pos (20U) +#define FLASH_SECBBR2_SECBB20_Msk (0x1UL << FLASH_SECBBR2_SECBB20_Pos) /*!< 0x00100000 */ +#define FLASH_SECBBR2_SECBB20 FLASH_SECBBR2_SECBB20_Msk /*!< Page 52 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB21_Pos (21U) +#define FLASH_SECBBR2_SECBB21_Msk (0x1UL << FLASH_SECBBR2_SECBB21_Pos) /*!< 0x00200000 */ +#define FLASH_SECBBR2_SECBB21 FLASH_SECBBR2_SECBB21_Msk /*!< Page 53 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB22_Pos (22U) +#define FLASH_SECBBR2_SECBB22_Msk (0x1UL << FLASH_SECBBR2_SECBB22_Pos) /*!< 0x00400000 */ +#define FLASH_SECBBR2_SECBB22 FLASH_SECBBR2_SECBB22_Msk /*!< Page 54 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB23_Pos (23U) +#define FLASH_SECBBR2_SECBB23_Msk (0x1UL << FLASH_SECBBR2_SECBB23_Pos) /*!< 0x00800000 */ +#define FLASH_SECBBR2_SECBB23 FLASH_SECBBR2_SECBB23_Msk /*!< Page 55 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB24_Pos (24U) +#define FLASH_SECBBR2_SECBB24_Msk (0x1UL << FLASH_SECBBR2_SECBB24_Pos) /*!< 0x01000000 */ +#define FLASH_SECBBR2_SECBB24 FLASH_SECBBR2_SECBB24_Msk /*!< Page 56 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB25_Pos (25U) +#define FLASH_SECBBR2_SECBB25_Msk (0x1UL << FLASH_SECBBR2_SECBB25_Pos) /*!< 0x02000000 */ +#define FLASH_SECBBR2_SECBB25 FLASH_SECBBR2_SECBB25_Msk /*!< Page 57 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB26_Pos (26U) +#define FLASH_SECBBR2_SECBB26_Msk (0x1UL << FLASH_SECBBR2_SECBB26_Pos) /*!< 0x04000000 */ +#define FLASH_SECBBR2_SECBB26 FLASH_SECBBR2_SECBB26_Msk /*!< Page 58 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB27_Pos (27U) +#define FLASH_SECBBR2_SECBB27_Msk (0x1UL << FLASH_SECBBR2_SECBB27_Pos) /*!< 0x08000000 */ +#define FLASH_SECBBR2_SECBB27 FLASH_SECBBR2_SECBB27_Msk /*!< Page 59 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB28_Pos (28U) +#define FLASH_SECBBR2_SECBB28_Msk (0x1UL << FLASH_SECBBR2_SECBB28_Pos) /*!< 0x10000000 */ +#define FLASH_SECBBR2_SECBB28 FLASH_SECBBR2_SECBB28_Msk /*!< Page 60 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB29_Pos (29U) +#define FLASH_SECBBR2_SECBB29_Msk (0x1UL << FLASH_SECBBR2_SECBB29_Pos) /*!< 0x20000000 */ +#define FLASH_SECBBR2_SECBB29 FLASH_SECBBR2_SECBB29_Msk /*!< Page 61 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB30_Pos (30U) +#define FLASH_SECBBR2_SECBB30_Msk (0x1UL << FLASH_SECBBR2_SECBB30_Pos) /*!< 0x40000000 */ +#define FLASH_SECBBR2_SECBB30 FLASH_SECBBR2_SECBB30_Msk /*!< Page 62 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB31_Pos (31U) +#define FLASH_SECBBR2_SECBB31_Msk (0x1UL << FLASH_SECBBR2_SECBB31_Pos) /*!< 0x80000000 */ +#define FLASH_SECBBR2_SECBB31 FLASH_SECBBR2_SECBB31_Msk /*!< Page 63 in Flash block-based secure */ + +/******************* Bit definition for FLASH_SECBBR3 register ******************/ +#define FLASH_SECBBR3_SECBB0_Pos (0U) +#define FLASH_SECBBR3_SECBB0_Msk (0x1UL << FLASH_SECBBR3_SECBB0_Pos) /*!< 0x00000001 */ +#define FLASH_SECBBR3_SECBB0 FLASH_SECBBR3_SECBB0_Msk /*!< Page 64 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB1_Pos (1U) +#define FLASH_SECBBR3_SECBB1_Msk (0x1UL << FLASH_SECBBR3_SECBB1_Pos) /*!< 0x00000002 */ +#define FLASH_SECBBR3_SECBB1 FLASH_SECBBR3_SECBB1_Msk /*!< Page 65 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB2_Pos (2U) +#define FLASH_SECBBR3_SECBB2_Msk (0x1UL << FLASH_SECBBR3_SECBB2_Pos) /*!< 0x00000004 */ +#define FLASH_SECBBR3_SECBB2 FLASH_SECBBR3_SECBB2_Msk /*!< Page 66 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB3_Pos (3U) +#define FLASH_SECBBR3_SECBB3_Msk (0x1UL << FLASH_SECBBR3_SECBB3_Pos) /*!< 0x00000008 */ +#define FLASH_SECBBR3_SECBB3 FLASH_SECBBR3_SECBB3_Msk /*!< Page 67 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB4_Pos (4U) +#define FLASH_SECBBR3_SECBB4_Msk (0x1UL << FLASH_SECBBR3_SECBB4_Pos) /*!< 0x00000010 */ +#define FLASH_SECBBR3_SECBB4 FLASH_SECBBR3_SECBB4_Msk /*!< Page 68 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB5_Pos (5U) +#define FLASH_SECBBR3_SECBB5_Msk (0x1UL << FLASH_SECBBR3_SECBB5_Pos) /*!< 0x00000020 */ +#define FLASH_SECBBR3_SECBB5 FLASH_SECBBR3_SECBB5_Msk /*!< Page 69 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB6_Pos (6U) +#define FLASH_SECBBR3_SECBB6_Msk (0x1UL << FLASH_SECBBR3_SECBB6_Pos) /*!< 0x00000040 */ +#define FLASH_SECBBR3_SECBB6 FLASH_SECBBR3_SECBB6_Msk /*!< Page 70 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB7_Pos (7U) +#define FLASH_SECBBR3_SECBB7_Msk (0x1UL << FLASH_SECBBR3_SECBB7_Pos) /*!< 0x00000080 */ +#define FLASH_SECBBR3_SECBB7 FLASH_SECBBR3_SECBB7_Msk /*!< Page 71 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB8_Pos (8U) +#define FLASH_SECBBR3_SECBB8_Msk (0x1UL << FLASH_SECBBR3_SECBB8_Pos) /*!< 0x00000100 */ +#define FLASH_SECBBR3_SECBB8 FLASH_SECBBR3_SECBB8_Msk /*!< Page 72 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB9_Pos (9U) +#define FLASH_SECBBR3_SECBB9_Msk (0x1UL << FLASH_SECBBR3_SECBB9_Pos) /*!< 0x00000200 */ +#define FLASH_SECBBR3_SECBB9 FLASH_SECBBR3_SECBB9_Msk /*!< Page 73 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB10_Pos (10U) +#define FLASH_SECBBR3_SECBB10_Msk (0x1UL << FLASH_SECBBR3_SECBB10_Pos) /*!< 0x00000400 */ +#define FLASH_SECBBR3_SECBB10 FLASH_SECBBR3_SECBB10_Msk /*!< Page 74 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB11_Pos (11U) +#define FLASH_SECBBR3_SECBB11_Msk (0x1UL << FLASH_SECBBR3_SECBB11_Pos) /*!< 0x00000800 */ +#define FLASH_SECBBR3_SECBB11 FLASH_SECBBR3_SECBB11_Msk /*!< Page 75 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB12_Pos (12U) +#define FLASH_SECBBR3_SECBB12_Msk (0x1UL << FLASH_SECBBR3_SECBB12_Pos) /*!< 0x00001000 */ +#define FLASH_SECBBR3_SECBB12 FLASH_SECBBR3_SECBB12_Msk /*!< Page 76 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB13_Pos (13U) +#define FLASH_SECBBR3_SECBB13_Msk (0x1UL << FLASH_SECBBR3_SECBB13_Pos) /*!< 0x00002000 */ +#define FLASH_SECBBR3_SECBB13 FLASH_SECBBR3_SECBB13_Msk /*!< Page 77 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB14_Pos (14U) +#define FLASH_SECBBR3_SECBB14_Msk (0x1UL << FLASH_SECBBR3_SECBB14_Pos) /*!< 0x00004000 */ +#define FLASH_SECBBR3_SECBB14 FLASH_SECBBR3_SECBB14_Msk /*!< Page 78 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB15_Pos (15U) +#define FLASH_SECBBR3_SECBB15_Msk (0x1UL << FLASH_SECBBR3_SECBB15_Pos) /*!< 0x00008000 */ +#define FLASH_SECBBR3_SECBB15 FLASH_SECBBR3_SECBB15_Msk /*!< Page 79 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB16_Pos (16U) +#define FLASH_SECBBR3_SECBB16_Msk (0x1UL << FLASH_SECBBR3_SECBB16_Pos) /*!< 0x00010000 */ +#define FLASH_SECBBR3_SECBB16 FLASH_SECBBR3_SECBB16_Msk /*!< Page 80 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB17_Pos (17U) +#define FLASH_SECBBR3_SECBB17_Msk (0x1UL << FLASH_SECBBR3_SECBB17_Pos) /*!< 0x00020000 */ +#define FLASH_SECBBR3_SECBB17 FLASH_SECBBR3_SECBB17_Msk /*!< Page 81 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB18_Pos (18U) +#define FLASH_SECBBR3_SECBB18_Msk (0x1UL << FLASH_SECBBR3_SECBB18_Pos) /*!< 0x00040000 */ +#define FLASH_SECBBR3_SECBB18 FLASH_SECBBR3_SECBB18_Msk /*!< Page 82 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB19_Pos (19U) +#define FLASH_SECBBR3_SECBB19_Msk (0x1UL << FLASH_SECBBR3_SECBB19_Pos) /*!< 0x00080000 */ +#define FLASH_SECBBR3_SECBB19 FLASH_SECBBR3_SECBB19_Msk /*!< Page 83 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB20_Pos (20U) +#define FLASH_SECBBR3_SECBB20_Msk (0x1UL << FLASH_SECBBR3_SECBB20_Pos) /*!< 0x00100000 */ +#define FLASH_SECBBR3_SECBB20 FLASH_SECBBR3_SECBB20_Msk /*!< Page 84 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB21_Pos (21U) +#define FLASH_SECBBR3_SECBB21_Msk (0x1UL << FLASH_SECBBR3_SECBB21_Pos) /*!< 0x00200000 */ +#define FLASH_SECBBR3_SECBB21 FLASH_SECBBR3_SECBB21_Msk /*!< Page 85 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB22_Pos (22U) +#define FLASH_SECBBR3_SECBB22_Msk (0x1UL << FLASH_SECBBR3_SECBB22_Pos) /*!< 0x00400000 */ +#define FLASH_SECBBR3_SECBB22 FLASH_SECBBR3_SECBB22_Msk /*!< Page 86 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB23_Pos (23U) +#define FLASH_SECBBR3_SECBB23_Msk (0x1UL << FLASH_SECBBR3_SECBB23_Pos) /*!< 0x00800000 */ +#define FLASH_SECBBR3_SECBB23 FLASH_SECBBR3_SECBB23_Msk /*!< Page 87 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB24_Pos (24U) +#define FLASH_SECBBR3_SECBB24_Msk (0x1UL << FLASH_SECBBR3_SECBB24_Pos) /*!< 0x01000000 */ +#define FLASH_SECBBR3_SECBB24 FLASH_SECBBR3_SECBB24_Msk /*!< Page 88 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB25_Pos (25U) +#define FLASH_SECBBR3_SECBB25_Msk (0x1UL << FLASH_SECBBR3_SECBB25_Pos) /*!< 0x02000000 */ +#define FLASH_SECBBR3_SECBB25 FLASH_SECBBR3_SECBB25_Msk /*!< Page 89 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB26_Pos (26U) +#define FLASH_SECBBR3_SECBB26_Msk (0x1UL << FLASH_SECBBR3_SECBB26_Pos) /*!< 0x04000000 */ +#define FLASH_SECBBR3_SECBB26 FLASH_SECBBR3_SECBB26_Msk /*!< Page 90 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB27_Pos (27U) +#define FLASH_SECBBR3_SECBB27_Msk (0x1UL << FLASH_SECBBR3_SECBB27_Pos) /*!< 0x08000000 */ +#define FLASH_SECBBR3_SECBB27 FLASH_SECBBR3_SECBB27_Msk /*!< Page 91 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB28_Pos (28U) +#define FLASH_SECBBR3_SECBB28_Msk (0x1UL << FLASH_SECBBR3_SECBB28_Pos) /*!< 0x10000000 */ +#define FLASH_SECBBR3_SECBB28 FLASH_SECBBR3_SECBB28_Msk /*!< Page 92 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB29_Pos (29U) +#define FLASH_SECBBR3_SECBB29_Msk (0x1UL << FLASH_SECBBR3_SECBB29_Pos) /*!< 0x20000000 */ +#define FLASH_SECBBR3_SECBB29 FLASH_SECBBR3_SECBB29_Msk /*!< Page 93 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB30_Pos (30U) +#define FLASH_SECBBR3_SECBB30_Msk (0x1UL << FLASH_SECBBR3_SECBB30_Pos) /*!< 0x40000000 */ +#define FLASH_SECBBR3_SECBB30 FLASH_SECBBR3_SECBB30_Msk /*!< Page 94 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB31_Pos (31U) +#define FLASH_SECBBR3_SECBB31_Msk (0x1UL << FLASH_SECBBR3_SECBB31_Pos) /*!< 0x80000000 */ +#define FLASH_SECBBR3_SECBB31 FLASH_SECBBR3_SECBB31_Msk /*!< Page 95 in Flash block-based secure */ + +/******************* Bit definition for FLASH_SECBBR4 register ******************/ +#define FLASH_SECBBR4_SECBB0_Pos (0U) +#define FLASH_SECBBR4_SECBB0_Msk (0x1UL << FLASH_SECBBR4_SECBB0_Pos) /*!< 0x00000001 */ +#define FLASH_SECBBR4_SECBB0 FLASH_SECBBR4_SECBB0_Msk /*!< Page 96 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB1_Pos (1U) +#define FLASH_SECBBR4_SECBB1_Msk (0x1UL << FLASH_SECBBR4_SECBB1_Pos) /*!< 0x00000002 */ +#define FLASH_SECBBR4_SECBB1 FLASH_SECBBR4_SECBB1_Msk /*!< Page 97 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB2_Pos (2U) +#define FLASH_SECBBR4_SECBB2_Msk (0x1UL << FLASH_SECBBR4_SECBB2_Pos) /*!< 0x00000004 */ +#define FLASH_SECBBR4_SECBB2 FLASH_SECBBR4_SECBB2_Msk /*!< Page 98 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB3_Pos (3U) +#define FLASH_SECBBR4_SECBB3_Msk (0x1UL << FLASH_SECBBR4_SECBB3_Pos) /*!< 0x00000008 */ +#define FLASH_SECBBR4_SECBB3 FLASH_SECBBR4_SECBB3_Msk /*!< Page 99 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB4_Pos (4U) +#define FLASH_SECBBR4_SECBB4_Msk (0x1UL << FLASH_SECBBR4_SECBB4_Pos) /*!< 0x00000010 */ +#define FLASH_SECBBR4_SECBB4 FLASH_SECBBR4_SECBB4_Msk /*!< Page 100 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB5_Pos (5U) +#define FLASH_SECBBR4_SECBB5_Msk (0x1UL << FLASH_SECBBR4_SECBB5_Pos) /*!< 0x00000020 */ +#define FLASH_SECBBR4_SECBB5 FLASH_SECBBR4_SECBB5_Msk /*!< Page 101 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB6_Pos (6U) +#define FLASH_SECBBR4_SECBB6_Msk (0x1UL << FLASH_SECBBR4_SECBB6_Pos) /*!< 0x00000040 */ +#define FLASH_SECBBR4_SECBB6 FLASH_SECBBR4_SECBB6_Msk /*!< Page 102 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB7_Pos (7U) +#define FLASH_SECBBR4_SECBB7_Msk (0x1UL << FLASH_SECBBR4_SECBB7_Pos) /*!< 0x00000080 */ +#define FLASH_SECBBR4_SECBB7 FLASH_SECBBR4_SECBB7_Msk /*!< Page 103 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB8_Pos (8U) +#define FLASH_SECBBR4_SECBB8_Msk (0x1UL << FLASH_SECBBR4_SECBB8_Pos) /*!< 0x00000100 */ +#define FLASH_SECBBR4_SECBB8 FLASH_SECBBR4_SECBB8_Msk /*!< Page 104 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB9_Pos (9U) +#define FLASH_SECBBR4_SECBB9_Msk (0x1UL << FLASH_SECBBR4_SECBB9_Pos) /*!< 0x00000200 */ +#define FLASH_SECBBR4_SECBB9 FLASH_SECBBR4_SECBB9_Msk /*!< Page 105 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB10_Pos (10U) +#define FLASH_SECBBR4_SECBB10_Msk (0x1UL << FLASH_SECBBR4_SECBB10_Pos) /*!< 0x00000400 */ +#define FLASH_SECBBR4_SECBB10 FLASH_SECBBR4_SECBB10_Msk /*!< Page 106 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB11_Pos (11U) +#define FLASH_SECBBR4_SECBB11_Msk (0x1UL << FLASH_SECBBR4_SECBB11_Pos) /*!< 0x00000800 */ +#define FLASH_SECBBR4_SECBB11 FLASH_SECBBR4_SECBB11_Msk /*!< Page 107 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB12_Pos (12U) +#define FLASH_SECBBR4_SECBB12_Msk (0x1UL << FLASH_SECBBR4_SECBB12_Pos) /*!< 0x00001000 */ +#define FLASH_SECBBR4_SECBB12 FLASH_SECBBR4_SECBB12_Msk /*!< Page 108 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB13_Pos (13U) +#define FLASH_SECBBR4_SECBB13_Msk (0x1UL << FLASH_SECBBR4_SECBB13_Pos) /*!< 0x00002000 */ +#define FLASH_SECBBR4_SECBB13 FLASH_SECBBR4_SECBB13_Msk /*!< Page 109 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB14_Pos (14U) +#define FLASH_SECBBR4_SECBB14_Msk (0x1UL << FLASH_SECBBR4_SECBB14_Pos) /*!< 0x00004000 */ +#define FLASH_SECBBR4_SECBB14 FLASH_SECBBR4_SECBB14_Msk /*!< Page 110 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB15_Pos (15U) +#define FLASH_SECBBR4_SECBB15_Msk (0x1UL << FLASH_SECBBR4_SECBB15_Pos) /*!< 0x00008000 */ +#define FLASH_SECBBR4_SECBB15 FLASH_SECBBR4_SECBB15_Msk /*!< Page 111 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB16_Pos (16U) +#define FLASH_SECBBR4_SECBB16_Msk (0x1UL << FLASH_SECBBR4_SECBB16_Pos) /*!< 0x00010000 */ +#define FLASH_SECBBR4_SECBB16 FLASH_SECBBR4_SECBB16_Msk /*!< Page 112 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB17_Pos (17U) +#define FLASH_SECBBR4_SECBB17_Msk (0x1UL << FLASH_SECBBR4_SECBB17_Pos) /*!< 0x00020000 */ +#define FLASH_SECBBR4_SECBB17 FLASH_SECBBR4_SECBB17_Msk /*!< Page 113 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB18_Pos (18U) +#define FLASH_SECBBR4_SECBB18_Msk (0x1UL << FLASH_SECBBR4_SECBB18_Pos) /*!< 0x00040000 */ +#define FLASH_SECBBR4_SECBB18 FLASH_SECBBR4_SECBB18_Msk /*!< Page 114 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB19_Pos (19U) +#define FLASH_SECBBR4_SECBB19_Msk (0x1UL << FLASH_SECBBR4_SECBB19_Pos) /*!< 0x00080000 */ +#define FLASH_SECBBR4_SECBB19 FLASH_SECBBR4_SECBB19_Msk /*!< Page 115 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB20_Pos (20U) +#define FLASH_SECBBR4_SECBB20_Msk (0x1UL << FLASH_SECBBR4_SECBB20_Pos) /*!< 0x00100000 */ +#define FLASH_SECBBR4_SECBB20 FLASH_SECBBR4_SECBB20_Msk /*!< Page 116 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB21_Pos (21U) +#define FLASH_SECBBR4_SECBB21_Msk (0x1UL << FLASH_SECBBR4_SECBB21_Pos) /*!< 0x00200000 */ +#define FLASH_SECBBR4_SECBB21 FLASH_SECBBR4_SECBB21_Msk /*!< Page 117 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB22_Pos (22U) +#define FLASH_SECBBR4_SECBB22_Msk (0x1UL << FLASH_SECBBR4_SECBB22_Pos) /*!< 0x00400000 */ +#define FLASH_SECBBR4_SECBB22 FLASH_SECBBR4_SECBB22_Msk /*!< Page 118 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB23_Pos (23U) +#define FLASH_SECBBR4_SECBB23_Msk (0x1UL << FLASH_SECBBR4_SECBB23_Pos) /*!< 0x00800000 */ +#define FLASH_SECBBR4_SECBB23 FLASH_SECBBR4_SECBB23_Msk /*!< Page 119 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB24_Pos (24U) +#define FLASH_SECBBR4_SECBB24_Msk (0x1UL << FLASH_SECBBR4_SECBB24_Pos) /*!< 0x01000000 */ +#define FLASH_SECBBR4_SECBB24 FLASH_SECBBR4_SECBB24_Msk /*!< Page 120 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB25_Pos (25U) +#define FLASH_SECBBR4_SECBB25_Msk (0x1UL << FLASH_SECBBR4_SECBB25_Pos) /*!< 0x02000000 */ +#define FLASH_SECBBR4_SECBB25 FLASH_SECBBR4_SECBB25_Msk /*!< Page 121 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB26_Pos (26U) +#define FLASH_SECBBR4_SECBB26_Msk (0x1UL << FLASH_SECBBR4_SECBB26_Pos) /*!< 0x04000000 */ +#define FLASH_SECBBR4_SECBB26 FLASH_SECBBR4_SECBB26_Msk /*!< Page 122 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB27_Pos (27U) +#define FLASH_SECBBR4_SECBB27_Msk (0x1UL << FLASH_SECBBR4_SECBB27_Pos) /*!< 0x08000000 */ +#define FLASH_SECBBR4_SECBB27 FLASH_SECBBR4_SECBB27_Msk /*!< Page 123 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB28_Pos (28U) +#define FLASH_SECBBR4_SECBB28_Msk (0x1UL << FLASH_SECBBR4_SECBB28_Pos) /*!< 0x10000000 */ +#define FLASH_SECBBR4_SECBB28 FLASH_SECBBR4_SECBB28_Msk /*!< Page 124 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB29_Pos (29U) +#define FLASH_SECBBR4_SECBB29_Msk (0x1UL << FLASH_SECBBR4_SECBB29_Pos) /*!< 0x20000000 */ +#define FLASH_SECBBR4_SECBB29 FLASH_SECBBR4_SECBB29_Msk /*!< Page 125 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB30_Pos (30U) +#define FLASH_SECBBR4_SECBB30_Msk (0x1UL << FLASH_SECBBR4_SECBB30_Pos) /*!< 0x40000000 */ +#define FLASH_SECBBR4_SECBB30 FLASH_SECBBR4_SECBB30_Msk /*!< Page 126 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB31_Pos (31U) +#define FLASH_SECBBR4_SECBB31_Msk (0x1UL << FLASH_SECBBR4_SECBB31_Pos) /*!< 0x80000000 */ +#define FLASH_SECBBR4_SECBB31 FLASH_SECBBR4_SECBB31_Msk /*!< Page 127 in Flash block-based secure */ + +/****************** Bits definition for FLASH_SECHDPCR register ***********/ +#define FLASH_SECHDPCR_HDP_ACCDIS_Pos (0U) +#define FLASH_SECHDPCR_HDP_ACCDIS_Msk (0x1UL << FLASH_SECHDPCR_HDP_ACCDIS_Pos) /*!< 0x00000001 */ +#define FLASH_SECHDPCR_HDP_ACCDIS FLASH_SECHDPCR_HDP_ACCDIS_Msk /*!< HDP area access disable */ + +/****************** Bits definition for FLASH_PRIVCFGR register ***********/ +#define FLASH_PRIVCFGR_SPRIV_Pos (0U) +#define FLASH_PRIVCFGR_SPRIV_Msk (0x1UL << FLASH_PRIVCFGR_SPRIV_Pos) /*!< 0x00000001 */ +#define FLASH_PRIVCFGR_SPRIV FLASH_PRIVCFGR_SPRIV_Msk /*!< Privilege protection for secure registers */ +#define FLASH_PRIVCFGR_NSPRIV_Pos (1U) +#define FLASH_PRIVCFGR_NSPRIV_Msk (0x1UL << FLASH_PRIVCFGR_NSPRIV_Pos) /*!< 0x00000002 */ +#define FLASH_PRIVCFGR_NSPRIV FLASH_PRIVCFGR_NSPRIV_Msk /*!< Privilege protection for non-secure registers */ + +/******************* Bit definition for FLASH_PRIVBBR1 register ******************/ +#define FLASH_PRIVBBR1_PRIVBB0_Pos (0U) +#define FLASH_PRIVBBR1_PRIVBB0_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB0_Pos) /*!< 0x00000001 */ +#define FLASH_PRIVBBR1_PRIVBB0 FLASH_PRIVBBR1_PRIVBB0_Msk /*!< Page 0 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB1_Pos (1U) +#define FLASH_PRIVBBR1_PRIVBB1_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB1_Pos) /*!< 0x00000002 */ +#define FLASH_PRIVBBR1_PRIVBB1 FLASH_PRIVBBR1_PRIVBB1_Msk /*!< Page 1 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB2_Pos (2U) +#define FLASH_PRIVBBR1_PRIVBB2_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB2_Pos) /*!< 0x00000004 */ +#define FLASH_PRIVBBR1_PRIVBB2 FLASH_PRIVBBR1_PRIVBB2_Msk /*!< Page 2 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB3_Pos (3U) +#define FLASH_PRIVBBR1_PRIVBB3_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB3_Pos) /*!< 0x00000008 */ +#define FLASH_PRIVBBR1_PRIVBB3 FLASH_PRIVBBR1_PRIVBB3_Msk /*!< Page 3 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB4_Pos (4U) +#define FLASH_PRIVBBR1_PRIVBB4_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB4_Pos) /*!< 0x00000010 */ +#define FLASH_PRIVBBR1_PRIVBB4 FLASH_PRIVBBR1_PRIVBB4_Msk /*!< Page 4 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB5_Pos (5U) +#define FLASH_PRIVBBR1_PRIVBB5_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB5_Pos) /*!< 0x00000020 */ +#define FLASH_PRIVBBR1_PRIVBB5 FLASH_PRIVBBR1_PRIVBB5_Msk /*!< Page 5 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB6_Pos (6U) +#define FLASH_PRIVBBR1_PRIVBB6_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB6_Pos) /*!< 0x00000040 */ +#define FLASH_PRIVBBR1_PRIVBB6 FLASH_PRIVBBR1_PRIVBB6_Msk /*!< Page 6 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB7_Pos (7U) +#define FLASH_PRIVBBR1_PRIVBB7_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB7_Pos) /*!< 0x00000080 */ +#define FLASH_PRIVBBR1_PRIVBB7 FLASH_PRIVBBR1_PRIVBB7_Msk /*!< Page 7 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB8_Pos (8U) +#define FLASH_PRIVBBR1_PRIVBB8_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB8_Pos) /*!< 0x00000100 */ +#define FLASH_PRIVBBR1_PRIVBB8 FLASH_PRIVBBR1_PRIVBB8_Msk /*!< Page 8 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB9_Pos (9U) +#define FLASH_PRIVBBR1_PRIVBB9_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB9_Pos) /*!< 0x00000200 */ +#define FLASH_PRIVBBR1_PRIVBB9 FLASH_PRIVBBR1_PRIVBB9_Msk /*!< Page 9 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB10_Pos (10U) +#define FLASH_PRIVBBR1_PRIVBB10_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB10_Pos) /*!< 0x00000400 */ +#define FLASH_PRIVBBR1_PRIVBB10 FLASH_PRIVBBR1_PRIVBB10_Msk /*!< Page 10 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB11_Pos (11U) +#define FLASH_PRIVBBR1_PRIVBB11_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB11_Pos) /*!< 0x00000800 */ +#define FLASH_PRIVBBR1_PRIVBB11 FLASH_PRIVBBR1_PRIVBB11_Msk /*!< Page 11 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB12_Pos (12U) +#define FLASH_PRIVBBR1_PRIVBB12_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB12_Pos) /*!< 0x00001000 */ +#define FLASH_PRIVBBR1_PRIVBB12 FLASH_PRIVBBR1_PRIVBB12_Msk /*!< Page 12 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB13_Pos (13U) +#define FLASH_PRIVBBR1_PRIVBB13_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB13_Pos) /*!< 0x00002000 */ +#define FLASH_PRIVBBR1_PRIVBB13 FLASH_PRIVBBR1_PRIVBB13_Msk /*!< Page 13 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB14_Pos (14U) +#define FLASH_PRIVBBR1_PRIVBB14_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB14_Pos) /*!< 0x00004000 */ +#define FLASH_PRIVBBR1_PRIVBB14 FLASH_PRIVBBR1_PRIVBB14_Msk /*!< Page 14 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB15_Pos (15U) +#define FLASH_PRIVBBR1_PRIVBB15_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB15_Pos) /*!< 0x00008000 */ +#define FLASH_PRIVBBR1_PRIVBB15 FLASH_PRIVBBR1_PRIVBB15_Msk /*!< Page 15 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB16_Pos (16U) +#define FLASH_PRIVBBR1_PRIVBB16_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB16_Pos) /*!< 0x00010000 */ +#define FLASH_PRIVBBR1_PRIVBB16 FLASH_PRIVBBR1_PRIVBB16_Msk /*!< Page 16 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB17_Pos (17U) +#define FLASH_PRIVBBR1_PRIVBB17_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB17_Pos) /*!< 0x00020000 */ +#define FLASH_PRIVBBR1_PRIVBB17 FLASH_PRIVBBR1_PRIVBB17_Msk /*!< Page 17 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB18_Pos (18U) +#define FLASH_PRIVBBR1_PRIVBB18_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB18_Pos) /*!< 0x00040000 */ +#define FLASH_PRIVBBR1_PRIVBB18 FLASH_PRIVBBR1_PRIVBB18_Msk /*!< Page 18 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB19_Pos (19U) +#define FLASH_PRIVBBR1_PRIVBB19_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB19_Pos) /*!< 0x00080000 */ +#define FLASH_PRIVBBR1_PRIVBB19 FLASH_PRIVBBR1_PRIVBB19_Msk /*!< Page 19 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB20_Pos (20U) +#define FLASH_PRIVBBR1_PRIVBB20_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB20_Pos) /*!< 0x00100000 */ +#define FLASH_PRIVBBR1_PRIVBB20 FLASH_PRIVBBR1_PRIVBB20_Msk /*!< Page 20 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB21_Pos (21U) +#define FLASH_PRIVBBR1_PRIVBB21_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB21_Pos) /*!< 0x00200000 */ +#define FLASH_PRIVBBR1_PRIVBB21 FLASH_PRIVBBR1_PRIVBB21_Msk /*!< Page 21 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB22_Pos (22U) +#define FLASH_PRIVBBR1_PRIVBB22_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB22_Pos) /*!< 0x00400000 */ +#define FLASH_PRIVBBR1_PRIVBB22 FLASH_PRIVBBR1_PRIVBB22_Msk /*!< Page 22 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB23_Pos (23U) +#define FLASH_PRIVBBR1_PRIVBB23_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB23_Pos) /*!< 0x00800000 */ +#define FLASH_PRIVBBR1_PRIVBB23 FLASH_PRIVBBR1_PRIVBB23_Msk /*!< Page 23 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB24_Pos (24U) +#define FLASH_PRIVBBR1_PRIVBB24_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB24_Pos) /*!< 0x01000000 */ +#define FLASH_PRIVBBR1_PRIVBB24 FLASH_PRIVBBR1_PRIVBB24_Msk /*!< Page 24 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB25_Pos (25U) +#define FLASH_PRIVBBR1_PRIVBB25_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB25_Pos) /*!< 0x02000000 */ +#define FLASH_PRIVBBR1_PRIVBB25 FLASH_PRIVBBR1_PRIVBB25_Msk /*!< Page 25 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB26_Pos (26U) +#define FLASH_PRIVBBR1_PRIVBB26_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB26_Pos) /*!< 0x04000000 */ +#define FLASH_PRIVBBR1_PRIVBB26 FLASH_PRIVBBR1_PRIVBB26_Msk /*!< Page 26 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB27_Pos (27U) +#define FLASH_PRIVBBR1_PRIVBB27_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB27_Pos) /*!< 0x08000000 */ +#define FLASH_PRIVBBR1_PRIVBB27 FLASH_PRIVBBR1_PRIVBB27_Msk /*!< Page 27 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB28_Pos (28U) +#define FLASH_PRIVBBR1_PRIVBB28_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB28_Pos) /*!< 0x10000000 */ +#define FLASH_PRIVBBR1_PRIVBB28 FLASH_PRIVBBR1_PRIVBB28_Msk /*!< Page 28 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB29_Pos (29U) +#define FLASH_PRIVBBR1_PRIVBB29_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB29_Pos) /*!< 0x20000000 */ +#define FLASH_PRIVBBR1_PRIVBB29 FLASH_PRIVBBR1_PRIVBB29_Msk /*!< Page 29 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB30_Pos (30U) +#define FLASH_PRIVBBR1_PRIVBB30_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB30_Pos) /*!< 0x40000000 */ +#define FLASH_PRIVBBR1_PRIVBB30 FLASH_PRIVBBR1_PRIVBB30_Msk /*!< Page 30 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB31_Pos (31U) +#define FLASH_PRIVBBR1_PRIVBB31_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB31_Pos) /*!< 0x80000000 */ +#define FLASH_PRIVBBR1_PRIVBB31 FLASH_PRIVBBR1_PRIVBB31_Msk /*!< Page 31 in Flash only accessible by privileged access */ + +/******************* Bit definition for FLASH_PRIVBBR2 register ******************/ +#define FLASH_PRIVBBR2_PRIVBB0_Pos (0U) +#define FLASH_PRIVBBR2_PRIVBB0_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB0_Pos) /*!< 0x00000001 */ +#define FLASH_PRIVBBR2_PRIVBB0 FLASH_PRIVBBR2_PRIVBB0_Msk /*!< Page 32 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB1_Pos (1U) +#define FLASH_PRIVBBR2_PRIVBB1_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB1_Pos) /*!< 0x00000002 */ +#define FLASH_PRIVBBR2_PRIVBB1 FLASH_PRIVBBR2_PRIVBB1_Msk /*!< Page 33 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB2_Pos (2U) +#define FLASH_PRIVBBR2_PRIVBB2_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB2_Pos) /*!< 0x00000004 */ +#define FLASH_PRIVBBR2_PRIVBB2 FLASH_PRIVBBR2_PRIVBB2_Msk /*!< Page 34 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB3_Pos (3U) +#define FLASH_PRIVBBR2_PRIVBB3_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB3_Pos) /*!< 0x00000008 */ +#define FLASH_PRIVBBR2_PRIVBB3 FLASH_PRIVBBR2_PRIVBB3_Msk /*!< Page 35 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB4_Pos (4U) +#define FLASH_PRIVBBR2_PRIVBB4_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB4_Pos) /*!< 0x00000010 */ +#define FLASH_PRIVBBR2_PRIVBB4 FLASH_PRIVBBR2_PRIVBB4_Msk /*!< Page 36 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB5_Pos (5U) +#define FLASH_PRIVBBR2_PRIVBB5_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB5_Pos) /*!< 0x00000020 */ +#define FLASH_PRIVBBR2_PRIVBB5 FLASH_PRIVBBR2_PRIVBB5_Msk /*!< Page 37 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB6_Pos (6U) +#define FLASH_PRIVBBR2_PRIVBB6_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB6_Pos) /*!< 0x00000040 */ +#define FLASH_PRIVBBR2_PRIVBB6 FLASH_PRIVBBR2_PRIVBB6_Msk /*!< Page 38 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB7_Pos (7U) +#define FLASH_PRIVBBR2_PRIVBB7_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB7_Pos) /*!< 0x00000080 */ +#define FLASH_PRIVBBR2_PRIVBB7 FLASH_PRIVBBR2_PRIVBB7_Msk /*!< Page 39 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB8_Pos (8U) +#define FLASH_PRIVBBR2_PRIVBB8_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB8_Pos) /*!< 0x00000100 */ +#define FLASH_PRIVBBR2_PRIVBB8 FLASH_PRIVBBR2_PRIVBB8_Msk /*!< Page 40 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB9_Pos (9U) +#define FLASH_PRIVBBR2_PRIVBB9_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB9_Pos) /*!< 0x00000200 */ +#define FLASH_PRIVBBR2_PRIVBB9 FLASH_PRIVBBR2_PRIVBB9_Msk /*!< Page 41 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB10_Pos (10U) +#define FLASH_PRIVBBR2_PRIVBB10_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB10_Pos) /*!< 0x00000400 */ +#define FLASH_PRIVBBR2_PRIVBB10 FLASH_PRIVBBR2_PRIVBB10_Msk /*!< Page 42 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB11_Pos (11U) +#define FLASH_PRIVBBR2_PRIVBB11_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB11_Pos) /*!< 0x00000800 */ +#define FLASH_PRIVBBR2_PRIVBB11 FLASH_PRIVBBR2_PRIVBB11_Msk /*!< Page 43 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB12_Pos (12U) +#define FLASH_PRIVBBR2_PRIVBB12_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB12_Pos) /*!< 0x00001000 */ +#define FLASH_PRIVBBR2_PRIVBB12 FLASH_PRIVBBR2_PRIVBB12_Msk /*!< Page 44 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB13_Pos (13U) +#define FLASH_PRIVBBR2_PRIVBB13_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB13_Pos) /*!< 0x00002000 */ +#define FLASH_PRIVBBR2_PRIVBB13 FLASH_PRIVBBR2_PRIVBB13_Msk /*!< Page 45 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB14_Pos (14U) +#define FLASH_PRIVBBR2_PRIVBB14_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB14_Pos) /*!< 0x00004000 */ +#define FLASH_PRIVBBR2_PRIVBB14 FLASH_PRIVBBR2_PRIVBB14_Msk /*!< Page 46 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB15_Pos (15U) +#define FLASH_PRIVBBR2_PRIVBB15_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB15_Pos) /*!< 0x00008000 */ +#define FLASH_PRIVBBR2_PRIVBB15 FLASH_PRIVBBR2_PRIVBB15_Msk /*!< Page 47 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB16_Pos (16U) +#define FLASH_PRIVBBR2_PRIVBB16_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB16_Pos) /*!< 0x00010000 */ +#define FLASH_PRIVBBR2_PRIVBB16 FLASH_PRIVBBR2_PRIVBB16_Msk /*!< Page 48 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB17_Pos (17U) +#define FLASH_PRIVBBR2_PRIVBB17_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB17_Pos) /*!< 0x00020000 */ +#define FLASH_PRIVBBR2_PRIVBB17 FLASH_PRIVBBR2_PRIVBB17_Msk /*!< Page 49 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB18_Pos (18U) +#define FLASH_PRIVBBR2_PRIVBB18_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB18_Pos) /*!< 0x00040000 */ +#define FLASH_PRIVBBR2_PRIVBB18 FLASH_PRIVBBR2_PRIVBB18_Msk /*!< Page 50 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB19_Pos (19U) +#define FLASH_PRIVBBR2_PRIVBB19_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB19_Pos) /*!< 0x00080000 */ +#define FLASH_PRIVBBR2_PRIVBB19 FLASH_PRIVBBR2_PRIVBB19_Msk /*!< Page 51 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB20_Pos (20U) +#define FLASH_PRIVBBR2_PRIVBB20_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB20_Pos) /*!< 0x00100000 */ +#define FLASH_PRIVBBR2_PRIVBB20 FLASH_PRIVBBR2_PRIVBB20_Msk /*!< Page 52 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB21_Pos (21U) +#define FLASH_PRIVBBR2_PRIVBB21_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB21_Pos) /*!< 0x00200000 */ +#define FLASH_PRIVBBR2_PRIVBB21 FLASH_PRIVBBR2_PRIVBB21_Msk /*!< Page 53 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB22_Pos (22U) +#define FLASH_PRIVBBR2_PRIVBB22_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB22_Pos) /*!< 0x00400000 */ +#define FLASH_PRIVBBR2_PRIVBB22 FLASH_PRIVBBR2_PRIVBB22_Msk /*!< Page 54 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB23_Pos (23U) +#define FLASH_PRIVBBR2_PRIVBB23_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB23_Pos) /*!< 0x00800000 */ +#define FLASH_PRIVBBR2_PRIVBB23 FLASH_PRIVBBR2_PRIVBB23_Msk /*!< Page 55 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB24_Pos (24U) +#define FLASH_PRIVBBR2_PRIVBB24_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB24_Pos) /*!< 0x01000000 */ +#define FLASH_PRIVBBR2_PRIVBB24 FLASH_PRIVBBR2_PRIVBB24_Msk /*!< Page 56 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB25_Pos (25U) +#define FLASH_PRIVBBR2_PRIVBB25_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB25_Pos) /*!< 0x02000000 */ +#define FLASH_PRIVBBR2_PRIVBB25 FLASH_PRIVBBR2_PRIVBB25_Msk /*!< Page 57 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB26_Pos (26U) +#define FLASH_PRIVBBR2_PRIVBB26_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB26_Pos) /*!< 0x04000000 */ +#define FLASH_PRIVBBR2_PRIVBB26 FLASH_PRIVBBR2_PRIVBB26_Msk /*!< Page 58 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB27_Pos (27U) +#define FLASH_PRIVBBR2_PRIVBB27_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB27_Pos) /*!< 0x08000000 */ +#define FLASH_PRIVBBR2_PRIVBB27 FLASH_PRIVBBR2_PRIVBB27_Msk /*!< Page 59 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB28_Pos (28U) +#define FLASH_PRIVBBR2_PRIVBB28_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB28_Pos) /*!< 0x10000000 */ +#define FLASH_PRIVBBR2_PRIVBB28 FLASH_PRIVBBR2_PRIVBB28_Msk /*!< Page 60 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB29_Pos (29U) +#define FLASH_PRIVBBR2_PRIVBB29_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB29_Pos) /*!< 0x20000000 */ +#define FLASH_PRIVBBR2_PRIVBB29 FLASH_PRIVBBR2_PRIVBB29_Msk /*!< Page 61 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB30_Pos (30U) +#define FLASH_PRIVBBR2_PRIVBB30_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB30_Pos) /*!< 0x40000000 */ +#define FLASH_PRIVBBR2_PRIVBB30 FLASH_PRIVBBR2_PRIVBB30_Msk /*!< Page 62 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB31_Pos (31U) +#define FLASH_PRIVBBR2_PRIVBB31_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB31_Pos) /*!< 0x80000000 */ +#define FLASH_PRIVBBR2_PRIVBB31 FLASH_PRIVBBR2_PRIVBB31_Msk /*!< Page 63 in Flash only accessible by privileged access */ + +/******************* Bit definition for FLASH_PRIVBBR3 register ******************/ +#define FLASH_PRIVBBR3_PRIVBB0_Pos (0U) +#define FLASH_PRIVBBR3_PRIVBB0_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB0_Pos) /*!< 0x00000001 */ +#define FLASH_PRIVBBR3_PRIVBB0 FLASH_PRIVBBR3_PRIVBB0_Msk /*!< Page 64 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB1_Pos (1U) +#define FLASH_PRIVBBR3_PRIVBB1_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB1_Pos) /*!< 0x00000002 */ +#define FLASH_PRIVBBR3_PRIVBB1 FLASH_PRIVBBR3_PRIVBB1_Msk /*!< Page 65 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB2_Pos (2U) +#define FLASH_PRIVBBR3_PRIVBB2_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB2_Pos) /*!< 0x00000004 */ +#define FLASH_PRIVBBR3_PRIVBB2 FLASH_PRIVBBR3_PRIVBB2_Msk /*!< Page 66 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB3_Pos (3U) +#define FLASH_PRIVBBR3_PRIVBB3_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB3_Pos) /*!< 0x00000008 */ +#define FLASH_PRIVBBR3_PRIVBB3 FLASH_PRIVBBR3_PRIVBB3_Msk /*!< Page 67 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB4_Pos (4U) +#define FLASH_PRIVBBR3_PRIVBB4_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB4_Pos) /*!< 0x00000010 */ +#define FLASH_PRIVBBR3_PRIVBB4 FLASH_PRIVBBR3_PRIVBB4_Msk /*!< Page 68 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB5_Pos (5U) +#define FLASH_PRIVBBR3_PRIVBB5_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB5_Pos) /*!< 0x00000020 */ +#define FLASH_PRIVBBR3_PRIVBB5 FLASH_PRIVBBR3_PRIVBB5_Msk /*!< Page 69 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB6_Pos (6U) +#define FLASH_PRIVBBR3_PRIVBB6_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB6_Pos) /*!< 0x00000040 */ +#define FLASH_PRIVBBR3_PRIVBB6 FLASH_PRIVBBR3_PRIVBB6_Msk /*!< Page 70 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB7_Pos (7U) +#define FLASH_PRIVBBR3_PRIVBB7_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB7_Pos) /*!< 0x00000080 */ +#define FLASH_PRIVBBR3_PRIVBB7 FLASH_PRIVBBR3_PRIVBB7_Msk /*!< Page 71 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB8_Pos (8U) +#define FLASH_PRIVBBR3_PRIVBB8_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB8_Pos) /*!< 0x00000100 */ +#define FLASH_PRIVBBR3_PRIVBB8 FLASH_PRIVBBR3_PRIVBB8_Msk /*!< Page 72 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB9_Pos (9U) +#define FLASH_PRIVBBR3_PRIVBB9_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB9_Pos) /*!< 0x00000200 */ +#define FLASH_PRIVBBR3_PRIVBB9 FLASH_PRIVBBR3_PRIVBB9_Msk /*!< Page 73 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB10_Pos (10U) +#define FLASH_PRIVBBR3_PRIVBB10_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB10_Pos) /*!< 0x00000400 */ +#define FLASH_PRIVBBR3_PRIVBB10 FLASH_PRIVBBR3_PRIVBB10_Msk /*!< Page 74 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB11_Pos (11U) +#define FLASH_PRIVBBR3_PRIVBB11_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB11_Pos) /*!< 0x00000800 */ +#define FLASH_PRIVBBR3_PRIVBB11 FLASH_PRIVBBR3_PRIVBB11_Msk /*!< Page 75 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB12_Pos (12U) +#define FLASH_PRIVBBR3_PRIVBB12_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB12_Pos) /*!< 0x00001000 */ +#define FLASH_PRIVBBR3_PRIVBB12 FLASH_PRIVBBR3_PRIVBB12_Msk /*!< Page 76 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB13_Pos (13U) +#define FLASH_PRIVBBR3_PRIVBB13_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB13_Pos) /*!< 0x00002000 */ +#define FLASH_PRIVBBR3_PRIVBB13 FLASH_PRIVBBR3_PRIVBB13_Msk /*!< Page 77 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB14_Pos (14U) +#define FLASH_PRIVBBR3_PRIVBB14_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB14_Pos) /*!< 0x00004000 */ +#define FLASH_PRIVBBR3_PRIVBB14 FLASH_PRIVBBR3_PRIVBB14_Msk /*!< Page 78 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB15_Pos (15U) +#define FLASH_PRIVBBR3_PRIVBB15_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB15_Pos) /*!< 0x00008000 */ +#define FLASH_PRIVBBR3_PRIVBB15 FLASH_PRIVBBR3_PRIVBB15_Msk /*!< Page 79 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB16_Pos (16U) +#define FLASH_PRIVBBR3_PRIVBB16_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB16_Pos) /*!< 0x00010000 */ +#define FLASH_PRIVBBR3_PRIVBB16 FLASH_PRIVBBR3_PRIVBB16_Msk /*!< Page 80 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB17_Pos (17U) +#define FLASH_PRIVBBR3_PRIVBB17_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB17_Pos) /*!< 0x00020000 */ +#define FLASH_PRIVBBR3_PRIVBB17 FLASH_PRIVBBR3_PRIVBB17_Msk /*!< Page 81 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB18_Pos (18U) +#define FLASH_PRIVBBR3_PRIVBB18_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB18_Pos) /*!< 0x00040000 */ +#define FLASH_PRIVBBR3_PRIVBB18 FLASH_PRIVBBR3_PRIVBB18_Msk /*!< Page 82 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB19_Pos (19U) +#define FLASH_PRIVBBR3_PRIVBB19_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB19_Pos) /*!< 0x00080000 */ +#define FLASH_PRIVBBR3_PRIVBB19 FLASH_PRIVBBR3_PRIVBB19_Msk /*!< Page 83 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB20_Pos (20U) +#define FLASH_PRIVBBR3_PRIVBB20_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB20_Pos) /*!< 0x00100000 */ +#define FLASH_PRIVBBR3_PRIVBB20 FLASH_PRIVBBR3_PRIVBB20_Msk /*!< Page 84 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB21_Pos (21U) +#define FLASH_PRIVBBR3_PRIVBB21_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB21_Pos) /*!< 0x00200000 */ +#define FLASH_PRIVBBR3_PRIVBB21 FLASH_PRIVBBR3_PRIVBB21_Msk /*!< Page 85 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB22_Pos (22U) +#define FLASH_PRIVBBR3_PRIVBB22_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB22_Pos) /*!< 0x00400000 */ +#define FLASH_PRIVBBR3_PRIVBB22 FLASH_PRIVBBR3_PRIVBB22_Msk /*!< Page 86 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB23_Pos (23U) +#define FLASH_PRIVBBR3_PRIVBB23_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB23_Pos) /*!< 0x00800000 */ +#define FLASH_PRIVBBR3_PRIVBB23 FLASH_PRIVBBR3_PRIVBB23_Msk /*!< Page 87 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB24_Pos (24U) +#define FLASH_PRIVBBR3_PRIVBB24_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB24_Pos) /*!< 0x01000000 */ +#define FLASH_PRIVBBR3_PRIVBB24 FLASH_PRIVBBR3_PRIVBB24_Msk /*!< Page 88 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB25_Pos (25U) +#define FLASH_PRIVBBR3_PRIVBB25_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB25_Pos) /*!< 0x02000000 */ +#define FLASH_PRIVBBR3_PRIVBB25 FLASH_PRIVBBR3_PRIVBB25_Msk /*!< Page 89 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB26_Pos (26U) +#define FLASH_PRIVBBR3_PRIVBB26_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB26_Pos) /*!< 0x04000000 */ +#define FLASH_PRIVBBR3_PRIVBB26 FLASH_PRIVBBR3_PRIVBB26_Msk /*!< Page 90 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB27_Pos (27U) +#define FLASH_PRIVBBR3_PRIVBB27_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB27_Pos) /*!< 0x08000000 */ +#define FLASH_PRIVBBR3_PRIVBB27 FLASH_PRIVBBR3_PRIVBB27_Msk /*!< Page 91 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB28_Pos (28U) +#define FLASH_PRIVBBR3_PRIVBB28_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB28_Pos) /*!< 0x10000000 */ +#define FLASH_PRIVBBR3_PRIVBB28 FLASH_PRIVBBR3_PRIVBB28_Msk /*!< Page 92 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB29_Pos (29U) +#define FLASH_PRIVBBR3_PRIVBB29_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB29_Pos) /*!< 0x20000000 */ +#define FLASH_PRIVBBR3_PRIVBB29 FLASH_PRIVBBR3_PRIVBB29_Msk /*!< Page 93 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB30_Pos (30U) +#define FLASH_PRIVBBR3_PRIVBB30_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB30_Pos) /*!< 0x40000000 */ +#define FLASH_PRIVBBR3_PRIVBB30 FLASH_PRIVBBR3_PRIVBB30_Msk /*!< Page 94 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB31_Pos (31U) +#define FLASH_PRIVBBR3_PRIVBB31_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB31_Pos) /*!< 0x80000000 */ +#define FLASH_PRIVBBR3_PRIVBB31 FLASH_PRIVBBR3_PRIVBB31_Msk /*!< Page 95 in Flash only accessible by privileged access */ + +/******************* Bit definition for FLASH_PRIVBBR4 register ******************/ +#define FLASH_PRIVBBR4_PRIVBB0_Pos (0U) +#define FLASH_PRIVBBR4_PRIVBB0_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB0_Pos) /*!< 0x00000001 */ +#define FLASH_PRIVBBR4_PRIVBB0 FLASH_PRIVBBR4_PRIVBB0_Msk /*!< Page 96 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB1_Pos (1U) +#define FLASH_PRIVBBR4_PRIVBB1_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB1_Pos) /*!< 0x00000002 */ +#define FLASH_PRIVBBR4_PRIVBB1 FLASH_PRIVBBR4_PRIVBB1_Msk /*!< Page 97 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB2_Pos (2U) +#define FLASH_PRIVBBR4_PRIVBB2_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB2_Pos) /*!< 0x00000004 */ +#define FLASH_PRIVBBR4_PRIVBB2 FLASH_PRIVBBR4_PRIVBB2_Msk /*!< Page 98 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB3_Pos (3U) +#define FLASH_PRIVBBR4_PRIVBB3_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB3_Pos) /*!< 0x00000008 */ +#define FLASH_PRIVBBR4_PRIVBB3 FLASH_PRIVBBR4_PRIVBB3_Msk /*!< Page 99 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB4_Pos (4U) +#define FLASH_PRIVBBR4_PRIVBB4_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB4_Pos) /*!< 0x00000010 */ +#define FLASH_PRIVBBR4_PRIVBB4 FLASH_PRIVBBR4_PRIVBB4_Msk /*!< Page 100 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB5_Pos (5U) +#define FLASH_PRIVBBR4_PRIVBB5_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB5_Pos) /*!< 0x00000020 */ +#define FLASH_PRIVBBR4_PRIVBB5 FLASH_PRIVBBR4_PRIVBB5_Msk /*!< Page 101 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB6_Pos (6U) +#define FLASH_PRIVBBR4_PRIVBB6_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB6_Pos) /*!< 0x00000040 */ +#define FLASH_PRIVBBR4_PRIVBB6 FLASH_PRIVBBR4_PRIVBB6_Msk /*!< Page 102 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB7_Pos (7U) +#define FLASH_PRIVBBR4_PRIVBB7_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB7_Pos) /*!< 0x00000080 */ +#define FLASH_PRIVBBR4_PRIVBB7 FLASH_PRIVBBR4_PRIVBB7_Msk /*!< Page 103 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB8_Pos (8U) +#define FLASH_PRIVBBR4_PRIVBB8_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB8_Pos) /*!< 0x00000100 */ +#define FLASH_PRIVBBR4_PRIVBB8 FLASH_PRIVBBR4_PRIVBB8_Msk /*!< Page 104 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB9_Pos (9U) +#define FLASH_PRIVBBR4_PRIVBB9_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB9_Pos) /*!< 0x00000200 */ +#define FLASH_PRIVBBR4_PRIVBB9 FLASH_PRIVBBR4_PRIVBB9_Msk /*!< Page 105 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB10_Pos (10U) +#define FLASH_PRIVBBR4_PRIVBB10_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB10_Pos) /*!< 0x00000400 */ +#define FLASH_PRIVBBR4_PRIVBB10 FLASH_PRIVBBR4_PRIVBB10_Msk /*!< Page 106 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB11_Pos (11U) +#define FLASH_PRIVBBR4_PRIVBB11_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB11_Pos) /*!< 0x00000800 */ +#define FLASH_PRIVBBR4_PRIVBB11 FLASH_PRIVBBR4_PRIVBB11_Msk /*!< Page 107 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB12_Pos (12U) +#define FLASH_PRIVBBR4_PRIVBB12_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB12_Pos) /*!< 0x00001000 */ +#define FLASH_PRIVBBR4_PRIVBB12 FLASH_PRIVBBR4_PRIVBB12_Msk /*!< Page 108 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB13_Pos (13U) +#define FLASH_PRIVBBR4_PRIVBB13_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB13_Pos) /*!< 0x00002000 */ +#define FLASH_PRIVBBR4_PRIVBB13 FLASH_PRIVBBR4_PRIVBB13_Msk /*!< Page 109 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB14_Pos (14U) +#define FLASH_PRIVBBR4_PRIVBB14_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB14_Pos) /*!< 0x00004000 */ +#define FLASH_PRIVBBR4_PRIVBB14 FLASH_PRIVBBR4_PRIVBB14_Msk /*!< Page 110 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB15_Pos (15U) +#define FLASH_PRIVBBR4_PRIVBB15_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB15_Pos) /*!< 0x00008000 */ +#define FLASH_PRIVBBR4_PRIVBB15 FLASH_PRIVBBR4_PRIVBB15_Msk /*!< Page 111 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB16_Pos (16U) +#define FLASH_PRIVBBR4_PRIVBB16_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB16_Pos) /*!< 0x00010000 */ +#define FLASH_PRIVBBR4_PRIVBB16 FLASH_PRIVBBR4_PRIVBB16_Msk /*!< Page 112 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB17_Pos (17U) +#define FLASH_PRIVBBR4_PRIVBB17_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB17_Pos) /*!< 0x00020000 */ +#define FLASH_PRIVBBR4_PRIVBB17 FLASH_PRIVBBR4_PRIVBB17_Msk /*!< Page 113 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB18_Pos (18U) +#define FLASH_PRIVBBR4_PRIVBB18_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB18_Pos) /*!< 0x00040000 */ +#define FLASH_PRIVBBR4_PRIVBB18 FLASH_PRIVBBR4_PRIVBB18_Msk /*!< Page 114 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB19_Pos (19U) +#define FLASH_PRIVBBR4_PRIVBB19_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB19_Pos) /*!< 0x00080000 */ +#define FLASH_PRIVBBR4_PRIVBB19 FLASH_PRIVBBR4_PRIVBB19_Msk /*!< Page 115 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB20_Pos (20U) +#define FLASH_PRIVBBR4_PRIVBB20_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB20_Pos) /*!< 0x00100000 */ +#define FLASH_PRIVBBR4_PRIVBB20 FLASH_PRIVBBR4_PRIVBB20_Msk /*!< Page 116 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB21_Pos (21U) +#define FLASH_PRIVBBR4_PRIVBB21_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB21_Pos) /*!< 0x00200000 */ +#define FLASH_PRIVBBR4_PRIVBB21 FLASH_PRIVBBR4_PRIVBB21_Msk /*!< Page 117 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB22_Pos (22U) +#define FLASH_PRIVBBR4_PRIVBB22_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB22_Pos) /*!< 0x00400000 */ +#define FLASH_PRIVBBR4_PRIVBB22 FLASH_PRIVBBR4_PRIVBB22_Msk /*!< Page 118 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB23_Pos (23U) +#define FLASH_PRIVBBR4_PRIVBB23_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB23_Pos) /*!< 0x00800000 */ +#define FLASH_PRIVBBR4_PRIVBB23 FLASH_PRIVBBR4_PRIVBB23_Msk /*!< Page 119 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB24_Pos (24U) +#define FLASH_PRIVBBR4_PRIVBB24_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB24_Pos) /*!< 0x01000000 */ +#define FLASH_PRIVBBR4_PRIVBB24 FLASH_PRIVBBR4_PRIVBB24_Msk /*!< Page 120 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB25_Pos (25U) +#define FLASH_PRIVBBR4_PRIVBB25_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB25_Pos) /*!< 0x02000000 */ +#define FLASH_PRIVBBR4_PRIVBB25 FLASH_PRIVBBR4_PRIVBB25_Msk /*!< Page 121 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB26_Pos (26U) +#define FLASH_PRIVBBR4_PRIVBB26_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB26_Pos) /*!< 0x04000000 */ +#define FLASH_PRIVBBR4_PRIVBB26 FLASH_PRIVBBR4_PRIVBB26_Msk /*!< Page 122 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB27_Pos (27U) +#define FLASH_PRIVBBR4_PRIVBB27_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB27_Pos) /*!< 0x08000000 */ +#define FLASH_PRIVBBR4_PRIVBB27 FLASH_PRIVBBR4_PRIVBB27_Msk /*!< Page 123 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB28_Pos (28U) +#define FLASH_PRIVBBR4_PRIVBB28_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB28_Pos) /*!< 0x10000000 */ +#define FLASH_PRIVBBR4_PRIVBB28 FLASH_PRIVBBR4_PRIVBB28_Msk /*!< Page 124 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB29_Pos (29U) +#define FLASH_PRIVBBR4_PRIVBB29_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB29_Pos) /*!< 0x20000000 */ +#define FLASH_PRIVBBR4_PRIVBB29 FLASH_PRIVBBR4_PRIVBB29_Msk /*!< Page 125 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB30_Pos (30U) +#define FLASH_PRIVBBR4_PRIVBB30_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB30_Pos) /*!< 0x40000000 */ +#define FLASH_PRIVBBR4_PRIVBB30 FLASH_PRIVBBR4_PRIVBB30_Msk /*!< Page 126 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB31_Pos (31U) +#define FLASH_PRIVBBR4_PRIVBB31_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB31_Pos) /*!< 0x80000000 */ +#define FLASH_PRIVBBR4_PRIVBB31 FLASH_PRIVBBR4_PRIVBB31_Msk /*!< Page 127 in Flash only accessible by privileged access */ + +/******************************************************************************/ +/* */ +/* General Purpose IOs (GPIO) */ +/* */ +/******************************************************************************/ +/****************** Bits definition for GPIO_MODER register *****************/ +#define GPIO_MODER_MODE0_Pos (0U) +#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ +#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk +#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ +#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ +#define GPIO_MODER_MODE1_Pos (2U) +#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ +#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk +#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ +#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ +#define GPIO_MODER_MODE2_Pos (4U) +#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ +#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk +#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ +#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ +#define GPIO_MODER_MODE3_Pos (6U) +#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ +#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk +#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ +#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ +#define GPIO_MODER_MODE4_Pos (8U) +#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ +#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk +#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ +#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ +#define GPIO_MODER_MODE5_Pos (10U) +#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ +#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk +#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ +#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ +#define GPIO_MODER_MODE6_Pos (12U) +#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ +#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk +#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ +#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ +#define GPIO_MODER_MODE7_Pos (14U) +#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ +#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk +#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ +#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ +#define GPIO_MODER_MODE8_Pos (16U) +#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ +#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk +#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ +#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ +#define GPIO_MODER_MODE9_Pos (18U) +#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ +#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk +#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ +#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ +#define GPIO_MODER_MODE10_Pos (20U) +#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ +#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk +#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ +#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ +#define GPIO_MODER_MODE11_Pos (22U) +#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ +#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk +#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ +#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ +#define GPIO_MODER_MODE12_Pos (24U) +#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ +#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk +#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ +#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ +#define GPIO_MODER_MODE13_Pos (26U) +#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ +#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk +#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ +#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ +#define GPIO_MODER_MODE14_Pos (28U) +#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ +#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk +#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ +#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ +#define GPIO_MODER_MODE15_Pos (30U) +#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ +#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk +#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ +#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_OTYPER register ****************/ +#define GPIO_OTYPER_OT0_Pos (0U) +#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */ +#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk +#define GPIO_OTYPER_OT1_Pos (1U) +#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */ +#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk +#define GPIO_OTYPER_OT2_Pos (2U) +#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */ +#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk +#define GPIO_OTYPER_OT3_Pos (3U) +#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */ +#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk +#define GPIO_OTYPER_OT4_Pos (4U) +#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */ +#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk +#define GPIO_OTYPER_OT5_Pos (5U) +#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */ +#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk +#define GPIO_OTYPER_OT6_Pos (6U) +#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */ +#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk +#define GPIO_OTYPER_OT7_Pos (7U) +#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */ +#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk +#define GPIO_OTYPER_OT8_Pos (8U) +#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */ +#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk +#define GPIO_OTYPER_OT9_Pos (9U) +#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */ +#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk +#define GPIO_OTYPER_OT10_Pos (10U) +#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */ +#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk +#define GPIO_OTYPER_OT11_Pos (11U) +#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */ +#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk +#define GPIO_OTYPER_OT12_Pos (12U) +#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */ +#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk +#define GPIO_OTYPER_OT13_Pos (13U) +#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */ +#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk +#define GPIO_OTYPER_OT14_Pos (14U) +#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */ +#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk +#define GPIO_OTYPER_OT15_Pos (15U) +#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */ +#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk + +/****************** Bits definition for GPIO_OSPEEDR register ***************/ +#define GPIO_OSPEEDR_OSPEED0_Pos (0U) +#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */ +#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk +#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */ +#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */ +#define GPIO_OSPEEDR_OSPEED1_Pos (2U) +#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */ +#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk +#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */ +#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */ +#define GPIO_OSPEEDR_OSPEED2_Pos (4U) +#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */ +#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk +#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */ +#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */ +#define GPIO_OSPEEDR_OSPEED3_Pos (6U) +#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */ +#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk +#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */ +#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */ +#define GPIO_OSPEEDR_OSPEED4_Pos (8U) +#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */ +#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk +#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */ +#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */ +#define GPIO_OSPEEDR_OSPEED5_Pos (10U) +#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */ +#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk +#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */ +#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */ +#define GPIO_OSPEEDR_OSPEED6_Pos (12U) +#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */ +#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk +#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */ +#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */ +#define GPIO_OSPEEDR_OSPEED7_Pos (14U) +#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */ +#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk +#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */ +#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */ +#define GPIO_OSPEEDR_OSPEED8_Pos (16U) +#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */ +#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk +#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */ +#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */ +#define GPIO_OSPEEDR_OSPEED9_Pos (18U) +#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */ +#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk +#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */ +#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */ +#define GPIO_OSPEEDR_OSPEED10_Pos (20U) +#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */ +#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk +#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */ +#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */ +#define GPIO_OSPEEDR_OSPEED11_Pos (22U) +#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */ +#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk +#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */ +#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */ +#define GPIO_OSPEEDR_OSPEED12_Pos (24U) +#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */ +#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk +#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */ +#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */ +#define GPIO_OSPEEDR_OSPEED13_Pos (26U) +#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */ +#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk +#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */ +#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */ +#define GPIO_OSPEEDR_OSPEED14_Pos (28U) +#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */ +#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk +#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */ +#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */ +#define GPIO_OSPEEDR_OSPEED15_Pos (30U) +#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */ +#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk +#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */ +#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_PUPDR register *****************/ +#define GPIO_PUPDR_PUPD0_Pos (0U) +#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */ +#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk +#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */ +#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */ +#define GPIO_PUPDR_PUPD1_Pos (2U) +#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */ +#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk +#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */ +#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */ +#define GPIO_PUPDR_PUPD2_Pos (4U) +#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */ +#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk +#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */ +#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */ +#define GPIO_PUPDR_PUPD3_Pos (6U) +#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */ +#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk +#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */ +#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */ +#define GPIO_PUPDR_PUPD4_Pos (8U) +#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */ +#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk +#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */ +#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */ +#define GPIO_PUPDR_PUPD5_Pos (10U) +#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */ +#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk +#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */ +#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */ +#define GPIO_PUPDR_PUPD6_Pos (12U) +#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */ +#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk +#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */ +#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */ +#define GPIO_PUPDR_PUPD7_Pos (14U) +#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */ +#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk +#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */ +#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */ +#define GPIO_PUPDR_PUPD8_Pos (16U) +#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */ +#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk +#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */ +#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */ +#define GPIO_PUPDR_PUPD9_Pos (18U) +#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */ +#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk +#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */ +#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */ +#define GPIO_PUPDR_PUPD10_Pos (20U) +#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */ +#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk +#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */ +#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */ +#define GPIO_PUPDR_PUPD11_Pos (22U) +#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */ +#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk +#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */ +#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */ +#define GPIO_PUPDR_PUPD12_Pos (24U) +#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */ +#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk +#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */ +#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */ +#define GPIO_PUPDR_PUPD13_Pos (26U) +#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */ +#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk +#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */ +#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */ +#define GPIO_PUPDR_PUPD14_Pos (28U) +#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */ +#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk +#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */ +#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */ +#define GPIO_PUPDR_PUPD15_Pos (30U) +#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */ +#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk +#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */ +#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_IDR register *******************/ +#define GPIO_IDR_ID0_Pos (0U) +#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk +#define GPIO_IDR_ID1_Pos (1U) +#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk +#define GPIO_IDR_ID2_Pos (2U) +#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk +#define GPIO_IDR_ID3_Pos (3U) +#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk +#define GPIO_IDR_ID4_Pos (4U) +#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk +#define GPIO_IDR_ID5_Pos (5U) +#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk +#define GPIO_IDR_ID6_Pos (6U) +#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk +#define GPIO_IDR_ID7_Pos (7U) +#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk +#define GPIO_IDR_ID8_Pos (8U) +#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk +#define GPIO_IDR_ID9_Pos (9U) +#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk +#define GPIO_IDR_ID10_Pos (10U) +#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk +#define GPIO_IDR_ID11_Pos (11U) +#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk +#define GPIO_IDR_ID12_Pos (12U) +#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk +#define GPIO_IDR_ID13_Pos (13U) +#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk +#define GPIO_IDR_ID14_Pos (14U) +#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk +#define GPIO_IDR_ID15_Pos (15U) +#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk + +/****************** Bits definition for GPIO_ODR register *******************/ +#define GPIO_ODR_OD0_Pos (0U) +#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk +#define GPIO_ODR_OD1_Pos (1U) +#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk +#define GPIO_ODR_OD2_Pos (2U) +#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk +#define GPIO_ODR_OD3_Pos (3U) +#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk +#define GPIO_ODR_OD4_Pos (4U) +#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk +#define GPIO_ODR_OD5_Pos (5U) +#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk +#define GPIO_ODR_OD6_Pos (6U) +#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk +#define GPIO_ODR_OD7_Pos (7U) +#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk +#define GPIO_ODR_OD8_Pos (8U) +#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk +#define GPIO_ODR_OD9_Pos (9U) +#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk +#define GPIO_ODR_OD10_Pos (10U) +#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk +#define GPIO_ODR_OD11_Pos (11U) +#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk +#define GPIO_ODR_OD12_Pos (12U) +#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk +#define GPIO_ODR_OD13_Pos (13U) +#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk +#define GPIO_ODR_OD14_Pos (14U) +#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk +#define GPIO_ODR_OD15_Pos (15U) +#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk + +/****************** Bits definition for GPIO_BSRR register ******************/ +#define GPIO_BSRR_BS0_Pos (0U) +#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ +#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk +#define GPIO_BSRR_BS1_Pos (1U) +#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ +#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk +#define GPIO_BSRR_BS2_Pos (2U) +#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ +#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk +#define GPIO_BSRR_BS3_Pos (3U) +#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ +#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk +#define GPIO_BSRR_BS4_Pos (4U) +#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ +#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk +#define GPIO_BSRR_BS5_Pos (5U) +#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ +#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk +#define GPIO_BSRR_BS6_Pos (6U) +#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ +#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk +#define GPIO_BSRR_BS7_Pos (7U) +#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ +#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk +#define GPIO_BSRR_BS8_Pos (8U) +#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ +#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk +#define GPIO_BSRR_BS9_Pos (9U) +#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ +#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk +#define GPIO_BSRR_BS10_Pos (10U) +#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ +#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk +#define GPIO_BSRR_BS11_Pos (11U) +#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ +#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk +#define GPIO_BSRR_BS12_Pos (12U) +#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ +#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk +#define GPIO_BSRR_BS13_Pos (13U) +#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ +#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk +#define GPIO_BSRR_BS14_Pos (14U) +#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ +#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk +#define GPIO_BSRR_BS15_Pos (15U) +#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ +#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk +#define GPIO_BSRR_BR0_Pos (16U) +#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ +#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk +#define GPIO_BSRR_BR1_Pos (17U) +#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ +#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk +#define GPIO_BSRR_BR2_Pos (18U) +#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ +#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk +#define GPIO_BSRR_BR3_Pos (19U) +#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ +#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk +#define GPIO_BSRR_BR4_Pos (20U) +#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ +#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk +#define GPIO_BSRR_BR5_Pos (21U) +#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ +#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk +#define GPIO_BSRR_BR6_Pos (22U) +#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ +#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk +#define GPIO_BSRR_BR7_Pos (23U) +#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ +#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk +#define GPIO_BSRR_BR8_Pos (24U) +#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ +#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk +#define GPIO_BSRR_BR9_Pos (25U) +#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ +#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk +#define GPIO_BSRR_BR10_Pos (26U) +#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ +#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk +#define GPIO_BSRR_BR11_Pos (27U) +#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ +#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk +#define GPIO_BSRR_BR12_Pos (28U) +#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ +#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk +#define GPIO_BSRR_BR13_Pos (29U) +#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ +#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk +#define GPIO_BSRR_BR14_Pos (30U) +#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ +#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk +#define GPIO_BSRR_BR15_Pos (31U) +#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ +#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk + +/****************** Bit definition for GPIO_LCKR register *********************/ +#define GPIO_LCKR_LCK0_Pos (0U) +#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ +#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk +#define GPIO_LCKR_LCK1_Pos (1U) +#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ +#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk +#define GPIO_LCKR_LCK2_Pos (2U) +#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ +#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk +#define GPIO_LCKR_LCK3_Pos (3U) +#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ +#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk +#define GPIO_LCKR_LCK4_Pos (4U) +#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ +#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk +#define GPIO_LCKR_LCK5_Pos (5U) +#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ +#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk +#define GPIO_LCKR_LCK6_Pos (6U) +#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ +#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk +#define GPIO_LCKR_LCK7_Pos (7U) +#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ +#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk +#define GPIO_LCKR_LCK8_Pos (8U) +#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ +#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk +#define GPIO_LCKR_LCK9_Pos (9U) +#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ +#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk +#define GPIO_LCKR_LCK10_Pos (10U) +#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ +#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk +#define GPIO_LCKR_LCK11_Pos (11U) +#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ +#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk +#define GPIO_LCKR_LCK12_Pos (12U) +#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ +#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk +#define GPIO_LCKR_LCK13_Pos (13U) +#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ +#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk +#define GPIO_LCKR_LCK14_Pos (14U) +#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ +#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk +#define GPIO_LCKR_LCK15_Pos (15U) +#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ +#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk +#define GPIO_LCKR_LCKK_Pos (16U) +#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ +#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk + +/****************** Bit definition for GPIO_AFRL register *********************/ +#define GPIO_AFRL_AFSEL0_Pos (0U) +#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk +#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ +#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ +#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ +#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ +#define GPIO_AFRL_AFSEL1_Pos (4U) +#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk +#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ +#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ +#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ +#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ +#define GPIO_AFRL_AFSEL2_Pos (8U) +#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk +#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ +#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ +#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ +#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ +#define GPIO_AFRL_AFSEL3_Pos (12U) +#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk +#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ +#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ +#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ +#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ +#define GPIO_AFRL_AFSEL4_Pos (16U) +#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk +#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ +#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ +#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ +#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ +#define GPIO_AFRL_AFSEL5_Pos (20U) +#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk +#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ +#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ +#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ +#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ +#define GPIO_AFRL_AFSEL6_Pos (24U) +#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk +#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ +#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ +#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ +#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ +#define GPIO_AFRL_AFSEL7_Pos (28U) +#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk +#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ +#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ +#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ +#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ + +/****************** Bit definition for GPIO_AFRH register *********************/ +#define GPIO_AFRH_AFSEL8_Pos (0U) +#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk +#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ +#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ +#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ +#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ +#define GPIO_AFRH_AFSEL9_Pos (4U) +#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk +#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ +#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ +#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ +#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ +#define GPIO_AFRH_AFSEL10_Pos (8U) +#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk +#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ +#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ +#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ +#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ +#define GPIO_AFRH_AFSEL11_Pos (12U) +#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk +#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ +#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ +#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ +#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ +#define GPIO_AFRH_AFSEL12_Pos (16U) +#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk +#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ +#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ +#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ +#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ +#define GPIO_AFRH_AFSEL13_Pos (20U) +#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk +#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ +#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ +#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ +#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ +#define GPIO_AFRH_AFSEL14_Pos (24U) +#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk +#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ +#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ +#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ +#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ +#define GPIO_AFRH_AFSEL15_Pos (28U) +#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk +#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ +#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ +#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ +#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_BRR register ******************/ +#define GPIO_BRR_BR0_Pos (0U) +#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk +#define GPIO_BRR_BR1_Pos (1U) +#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk +#define GPIO_BRR_BR2_Pos (2U) +#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk +#define GPIO_BRR_BR3_Pos (3U) +#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk +#define GPIO_BRR_BR4_Pos (4U) +#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk +#define GPIO_BRR_BR5_Pos (5U) +#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk +#define GPIO_BRR_BR6_Pos (6U) +#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk +#define GPIO_BRR_BR7_Pos (7U) +#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk +#define GPIO_BRR_BR8_Pos (8U) +#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk +#define GPIO_BRR_BR9_Pos (9U) +#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk +#define GPIO_BRR_BR10_Pos (10U) +#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk +#define GPIO_BRR_BR11_Pos (11U) +#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk +#define GPIO_BRR_BR12_Pos (12U) +#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk +#define GPIO_BRR_BR13_Pos (13U) +#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk +#define GPIO_BRR_BR14_Pos (14U) +#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk +#define GPIO_BRR_BR15_Pos (15U) +#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk + +/****************** Bits definition for GPIO_SECCFGR register ******************/ +#define GPIO_SECCFGR_SEC0_Pos (0U) +#define GPIO_SECCFGR_SEC0_Msk (0x1UL << GPIO_SECCFGR_SEC0_Pos) /*!< 0x00000001 */ +#define GPIO_SECCFGR_SEC0 GPIO_SECCFGR_SEC0_Msk +#define GPIO_SECCFGR_SEC1_Pos (1U) +#define GPIO_SECCFGR_SEC1_Msk (0x1UL << GPIO_SECCFGR_SEC1_Pos) /*!< 0x00000002 */ +#define GPIO_SECCFGR_SEC1 GPIO_SECCFGR_SEC1_Msk +#define GPIO_SECCFGR_SEC2_Pos (2U) +#define GPIO_SECCFGR_SEC2_Msk (0x1UL << GPIO_SECCFGR_SEC2_Pos) /*!< 0x00000004 */ +#define GPIO_SECCFGR_SEC2 GPIO_SECCFGR_SEC2_Msk +#define GPIO_SECCFGR_SEC3_Pos (3U) +#define GPIO_SECCFGR_SEC3_Msk (0x1UL << GPIO_SECCFGR_SEC3_Pos) /*!< 0x00000008 */ +#define GPIO_SECCFGR_SEC3 GPIO_SECCFGR_SEC3_Msk +#define GPIO_SECCFGR_SEC4_Pos (4U) +#define GPIO_SECCFGR_SEC4_Msk (0x1UL << GPIO_SECCFGR_SEC4_Pos) /*!< 0x00000010 */ +#define GPIO_SECCFGR_SEC4 GPIO_SECCFGR_SEC4_Msk +#define GPIO_SECCFGR_SEC5_Pos (5U) +#define GPIO_SECCFGR_SEC5_Msk (0x1UL << GPIO_SECCFGR_SEC5_Pos) /*!< 0x00000020 */ +#define GPIO_SECCFGR_SEC5 GPIO_SECCFGR_SEC5_Msk +#define GPIO_SECCFGR_SEC6_Pos (6U) +#define GPIO_SECCFGR_SEC6_Msk (0x1UL << GPIO_SECCFGR_SEC6_Pos) /*!< 0x00000040 */ +#define GPIO_SECCFGR_SEC6 GPIO_SECCFGR_SEC6_Msk +#define GPIO_SECCFGR_SEC7_Pos (7U) +#define GPIO_SECCFGR_SEC7_Msk (0x1UL << GPIO_SECCFGR_SEC7_Pos) /*!< 0x00000080 */ +#define GPIO_SECCFGR_SEC7 GPIO_SECCFGR_SEC7_Msk +#define GPIO_SECCFGR_SEC8_Pos (8U) +#define GPIO_SECCFGR_SEC8_Msk (0x1UL << GPIO_SECCFGR_SEC8_Pos) /*!< 0x00000100 */ +#define GPIO_SECCFGR_SEC8 GPIO_SECCFGR_SEC8_Msk +#define GPIO_SECCFGR_SEC9_Pos (9U) +#define GPIO_SECCFGR_SEC9_Msk (0x1UL << GPIO_SECCFGR_SEC9_Pos) /*!< 0x00000200 */ +#define GPIO_SECCFGR_SEC9 GPIO_SECCFGR_SEC9_Msk +#define GPIO_SECCFGR_SEC10_Pos (10U) +#define GPIO_SECCFGR_SEC10_Msk (0x1UL << GPIO_SECCFGR_SEC10_Pos) /*!< 0x00000400 */ +#define GPIO_SECCFGR_SEC10 GPIO_SECCFGR_SEC10_Msk +#define GPIO_SECCFGR_SEC11_Pos (11U) +#define GPIO_SECCFGR_SEC11_Msk (x1UL << GPIO_SECCFGR_SEC11_Pos) /*!< 0x00000800 */ +#define GPIO_SECCFGR_SEC11 GPIO_SECCFGR_SEC11_Msk +#define GPIO_SECCFGR_SEC12_Pos (12U) +#define GPIO_SECCFGR_SEC12_Msk (0x1UL << GPIO_SECCFGR_SEC12_Pos) /*!< 0x00001000 */ +#define GPIO_SECCFGR_SEC12 GPIO_SECCFGR_SEC12_Msk +#define GPIO_SECCFGR_SEC13_Pos (13U) +#define GPIO_SECCFGR_SEC13_Msk (0x1UL << GPIO_SECCFGR_SEC13_Pos) /*!< 0x00002000 */ +#define GPIO_SECCFGR_SEC13 GPIO_SECCFGR_SEC13_Msk +#define GPIO_SECCFGR_SEC14_Pos (14U) +#define GPIO_SECCFGR_SEC14_Msk (0x1UL << GPIO_SECCFGR_SEC14_Pos) /*!< 0x00004000 */ +#define GPIO_SECCFGR_SEC14 GPIO_SECCFGR_SEC14_Msk +#define GPIO_SECCFGR_SEC15_Pos (15U) +#define GPIO_SECCFGR_SEC15_Msk (0x1UL << GPIO_SECCFGR_SEC15_Pos) /*!< 0x00008000 */ +#define GPIO_SECCFGR_SEC15 GPIO_SECCFGR_SEC15_Msk + + +/*****************************************************************************/ +/* */ +/* Global TrustZone Control */ +/* */ +/*****************************************************************************/ +/******************* Bits definition for GTZC_TZSC_CR register ******************/ +#define GTZC_TZSC_CR_LCK_Pos (0U) +#define GTZC_TZSC_CR_LCK_Msk (0x01UL << GTZC_TZSC_CR_LCK_Pos) /*!< 0x00000001 */ +#define GTZC_TZSC_CR_LCK GTZC_TZSC_CR_LCK_Msk /*!< GTZC Secure and privilege configurations lock */ + +/******* Bits definition for GTZC_TZSC_SECCFGRx/_PRIVCFGRx registers *****/ +/******* Bits definition for GTZC_TZIC_IERx/_SRx/_IFCRx registers ********/ + +/******************* Bits definition for GTZC_TZSC_SECCFGR1 register ***************/ +#define GTZC_CFGR1_TIM2_Pos GTZC_TZSC_SECCFGR1_TIM2SEC_Pos +#define GTZC_CFGR1_TIM2_Msk (0x01UL << GTZC_CFGR1_TIM2_Pos) +#define GTZC_CFGR1_TIM3_Pos GTZC_TZSC_SECCFGR1_TIM3SEC_Pos +#define GTZC_CFGR1_TIM3_Msk (0x01UL << GTZC_CFGR1_TIM3_Pos) +#define GTZC_CFGR1_WWDG_Pos GTZC_TZSC_SECCFGR1_WWDGSEC_Pos +#define GTZC_CFGR1_WWDG_Msk (0x01UL << GTZC_CFGR1_WWDG_Pos) +#define GTZC_CFGR1_IWDG_Pos GTZC_TZSC_SECCFGR1_IWDGSEC_Pos +#define GTZC_CFGR1_IWDG_Msk (0x01UL << GTZC_CFGR1_IWDG_Pos) +#define GTZC_CFGR1_USART2_Pos GTZC_TZSC_SECCFGR1_USART2SEC_Pos +#define GTZC_CFGR1_USART2_Msk (0x01UL << GTZC_CFGR1_USART2_Pos) +#define GTZC_CFGR1_I2C1_Pos GTZC_TZSC_SECCFGR1_I2C1SEC_Pos +#define GTZC_CFGR1_I2C1_Msk (0x01UL << GTZC_CFGR1_I2C1_Pos) +#define GTZC_CFGR1_LPTIM2_Pos GTZC_TZSC_SECCFGR1_LPTIM2SEC_Pos +#define GTZC_CFGR1_LPTIM2_Msk (0x01UL << GTZC_CFGR1_LPTIM2_Pos) + +/******************* Bits definition for GTZC_TZSC_SECCFGR2 register ***************/ +#define GTZC_CFGR2_TIM1_Pos GTZC_TZSC_SECCFGR2_TIM1SEC_Pos +#define GTZC_CFGR2_TIM1_Msk (0x01UL << GTZC_CFGR2_TIM1_Pos) +#define GTZC_CFGR2_SPI1_Pos GTZC_TZSC_SECCFGR2_SPI1SEC_Pos +#define GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos) +#define GTZC_CFGR2_USART1_Pos GTZC_TZSC_SECCFGR2_USART1SEC_Pos +#define GTZC_CFGR2_USART1_Msk (0x01UL << GTZC_CFGR2_USART1_Pos) +#define GTZC_CFGR2_TIM16_Pos GTZC_TZSC_SECCFGR2_TIM16SEC_Pos +#define GTZC_CFGR2_TIM16_Msk (0x01UL << GTZC_CFGR2_TIM16_Pos) +#define GTZC_CFGR2_TIM17_Pos GTZC_TZSC_SECCFGR2_TIM17SEC_Pos +#define GTZC_CFGR2_TIM17_Msk (0x01UL << GTZC_CFGR2_TIM17_Pos) +#define GTZC_CFGR2_SAI1_Pos GTZC_TZSC_SECCFGR2_SAI1SEC_Pos +#define GTZC_CFGR2_SAI1_Msk (0x01UL << GTZC_CFGR2_SAI1_Pos) +#define GTZC_CFGR2_SPI3_Pos GTZC_TZSC_SECCFGR2_SPI3SEC_Pos +#define GTZC_CFGR2_SPI3_Msk (0x01UL << GTZC_CFGR2_SPI3_Pos) +#define GTZC_CFGR2_LPUART1_Pos GTZC_TZSC_SECCFGR2_LPUART1SEC_Pos +#define GTZC_CFGR2_LPUART1_Msk (0x01UL << GTZC_CFGR2_LPUART1_Pos) +#define GTZC_CFGR2_I2C3_Pos GTZC_TZSC_SECCFGR2_I2C3SEC_Pos +#define GTZC_CFGR2_I2C3_Msk (0x01UL << GTZC_CFGR2_I2C3_Pos) +#define GTZC_CFGR2_LPTIM1_Pos GTZC_TZSC_SECCFGR2_LPTIM1SEC_Pos +#define GTZC_CFGR2_LPTIM1_Msk (0x01UL << GTZC_CFGR2_LPTIM1_Pos) +#define GTZC_CFGR2_COMP_Pos GTZC_TZSC_SECCFGR2_COMPSEC_Pos +#define GTZC_CFGR2_COMP_Msk (0x01UL << GTZC_CFGR2_COMP_Pos) +#define GTZC_CFGR2_ADC4_Pos GTZC_TZSC_SECCFGR2_ADC4SEC_Pos +#define GTZC_CFGR2_ADC4_Msk (0x01UL << GTZC_CFGR2_ADC4_Pos) + +/******************* Bits definition for GTZC_TZSC_SECCFGR3 register ***************/ +#define GTZC_CFGR3_CRC_Pos GTZC_TZSC_SECCFGR3_CRCSEC_Pos +#define GTZC_CFGR3_CRC_Msk (0x01UL << GTZC_CFGR3_CRC_Pos) +#define GTZC_CFGR3_TSC_Pos GTZC_TZSC_SECCFGR3_TSCSEC_Pos +#define GTZC_CFGR3_TSC_Msk (0x01UL << GTZC_CFGR3_TSC_Pos) +#define GTZC_CFGR3_ICACHE_REG_Pos GTZC_TZSC_SECCFGR3_ICACHE_REGSEC_Pos +#define GTZC_CFGR3_ICACHE_REG_Msk (0x01UL << GTZC_CFGR3_ICACHE_REG_Pos) +#define GTZC_CFGR3_AES_Pos GTZC_TZSC_SECCFGR3_AESSEC_Pos +#define GTZC_CFGR3_AES_Msk (0x01UL << GTZC_CFGR3_AES_Pos) +#define GTZC_CFGR3_HASH_Pos GTZC_TZSC_SECCFGR3_HASHSEC_Pos +#define GTZC_CFGR3_HASH_Msk (0x01UL << GTZC_CFGR3_HASH_Pos) +#define GTZC_CFGR3_RNG_Pos GTZC_TZSC_SECCFGR3_RNGSEC_Pos +#define GTZC_CFGR3_RNG_Msk (0x01UL << GTZC_CFGR3_RNG_Pos) +#define GTZC_CFGR3_SAES_Pos GTZC_TZSC_SECCFGR3_SAESSEC_Pos +#define GTZC_CFGR3_SAES_Msk (0x01UL << GTZC_CFGR3_SAES_Pos) +#define GTZC_CFGR3_HSEM_Pos GTZC_TZIC_IER3_HSEMIE_Pos +#define GTZC_CFGR3_HSEM_Msk (0x01UL << GTZC_CFGR3_HSEM_Pos) +#define GTZC_CFGR3_PKA_Pos GTZC_TZSC_SECCFGR3_PKASEC_Pos +#define GTZC_CFGR3_PKA_Msk (0x01UL << GTZC_CFGR3_PKA_Pos) +#define GTZC_CFGR3_RAMCFG_Pos GTZC_TZSC_SECCFGR3_RAMCFGSEC_Pos +#define GTZC_CFGR3_RAMCFG_Msk (0x01UL << GTZC_CFGR3_RAMCFG_Pos) +#define GTZC_CFGR3_RADIO_Pos GTZC_TZSC_SECCFGR3_RADIOSEC_Pos +#define GTZC_CFGR3_RADIO_Msk (0x01UL << GTZC_CFGR3_RADIO_Pos) +#define GTZC_CFGR3_PTACONV_Pos GTZC_TZSC_SECCFGR3_PTACONVSEC_Pos +#define GTZC_CFGR3_PTACONV_Msk (0x01UL << GTZC_CFGR3_PTACONV_Pos) + +/******************* Bits definition for GTZC_TZIC_IER4 register ***************/ +#define GTZC_CFGR4_GPDMA1_Pos GTZC_TZIC_IER4_GPDMA1IE_Pos +#define GTZC_CFGR4_GPDMA1_Msk (0x01UL << GTZC_CFGR4_GPDMA1_Pos) +#define GTZC_CFGR4_FLASH_Pos GTZC_TZIC_IER4_FLASHIE_Pos +#define GTZC_CFGR4_FLASH_Msk (0x01UL << GTZC_CFGR4_FLASH_Pos) +#define GTZC_CFGR4_FLASH_REG_Pos GTZC_TZIC_IER4_FLASH_REGIE_Pos +#define GTZC_CFGR4_FLASH_REG_Msk (0x01UL << GTZC_CFGR4_FLASH_REG_Pos) +#define GTZC_CFGR4_TZSC_Pos GTZC_TZIC_IER4_TZSCIE_Pos +#define GTZC_CFGR4_TZSC_Msk (0x01UL << GTZC_CFGR4_TZSC_Pos) +#define GTZC_CFGR4_TZIC_Pos GTZC_TZIC_IER4_TZICIE_Pos +#define GTZC_CFGR4_TZIC_Msk (0x01UL << GTZC_CFGR4_TZIC_Pos) +#define GTZC_CFGR4_SYSCFG_Pos GTZC_TZIC_IER4_SYSCFGIE_Pos +#define GTZC_CFGR4_SYSCFG_Msk (0x01UL << GTZC_CFGR4_SYSCFG_Pos) +#define GTZC_CFGR4_RTC_Pos GTZC_TZIC_IER4_RTCIE_Pos +#define GTZC_CFGR4_RTC_Msk (0x01UL << GTZC_CFGR4_RTC_Pos) +#define GTZC_CFGR4_TAMP_Pos GTZC_TZIC_IER4_TAMPIE_Pos +#define GTZC_CFGR4_TAMP_Msk (0x01UL << GTZC_CFGR4_TAMP_Pos) +#define GTZC_CFGR4_PWR_Pos GTZC_TZIC_IER4_PWRIE_Pos +#define GTZC_CFGR4_PWR_Msk (0x01UL << GTZC_CFGR4_PWR_Pos) +#define GTZC_CFGR4_RCC_Pos GTZC_TZIC_IER4_RCCIE_Pos +#define GTZC_CFGR4_RCC_sk (0x01UL << GTZC_CFGR4_RCC_Pos) +#define GTZC_CFGR4_EXTI_Pos GTZC_TZIC_IER4_EXTIIE_Pos +#define GTZC_CFGR4_EXTI_Msk (0x01UL << GTZC_CFGR4_EXTI_Pos) +#define GTZC_CFGR4_SRAM1_Pos GTZC_TZIC_IER4_SRAM1IE_Pos +#define GTZC_CFGR4_SRAM1_Msk (0x01UL << GTZC_CFGR4_SRAM1_Pos) +#define GTZC_CFGR4_MPCBB1_REG_Pos GTZC_TZIC_IER4_MPCBB1IE_Pos +#define GTZC_CFGR4_MPCBB1_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB1_REG_Pos) +#define GTZC_CFGR4_SRAM2_Pos GTZC_TZIC_IER4_SRAM2IE_Pos +#define GTZC_CFGR4_SRAM2_Msk (0x01UL << GTZC_CFGR4_SRAM2_Pos) +#define GTZC_CFGR4_MPCBB2_REG_Pos GTZC_TZIC_IER4_MPCBB2IE_Pos +#define GTZC_CFGR4_MPCBB2_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB2_REG_Pos) +#define GTZC_CFGR4_SRAM6_Pos GTZC_TZIC_IER4_SRAM6IE_Pos +#define GTZC_CFGR4_SRAM6_Msk (0x01UL << GTZC_CFGR4_SRAM6_Pos) +#define GTZC_CFGR4_MPCBB6_REG_Pos GTZC_TZIC_IER4_MPCBB6IE_Pos +#define GTZC_CFGR4_MPCBB6_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB6_REG_Pos) + +/*************** Bits definition for register x=1 (GTZC_TZSC_SECCFGR1) *************/ +#define GTZC_TZSC_SECCFGR1_TIM2SEC_Pos (0U) +#define GTZC_TZSC_SECCFGR1_TIM2SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR1_TIM2SEC_Pos) +#define GTZC_TZSC_SECCFGR1_TIM2SEC GTZC_TZSC_SECCFGR1_TIM2SEC_Msk /*!< secure access mode for TIM2 */ +#define GTZC_TZSC_SECCFGR1_TIM3SEC_Pos (1U) +#define GTZC_TZSC_SECCFGR1_TIM3SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR1_TIM3SEC_Pos) +#define GTZC_TZSC_SECCFGR1_TIM3SEC GTZC_TZSC_SECCFGR1_TIM3SEC_Msk /*!< secure access mode for TIM3 */ +#define GTZC_TZSC_SECCFGR1_WWDGSEC_Pos (6U) +#define GTZC_TZSC_SECCFGR1_WWDGSEC_Msk (0x01UL << GTZC_TZSC_SECCFGR1_WWDGSEC_Pos) +#define GTZC_TZSC_SECCFGR1_WWDGSEC GTZC_TZSC_SECCFGR1_WWDGSEC_Msk /*!< secure access mode for WWDG */ +#define GTZC_TZSC_SECCFGR1_IWDGSEC_Pos (7U) +#define GTZC_TZSC_SECCFGR1_IWDGSEC_Msk (0x01UL << GTZC_TZSC_SECCFGR1_IWDGSEC_Pos) +#define GTZC_TZSC_SECCFGR1_IWDGSEC GTZC_TZSC_SECCFGR1_IWDGSEC_Msk /*!< secure access mode for IWDG */ +#define GTZC_TZSC_SECCFGR1_USART2SEC_Pos (9U) +#define GTZC_TZSC_SECCFGR1_USART2SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR1_USART2SEC_Pos) +#define GTZC_TZSC_SECCFGR1_USART2SEC GTZC_TZSC_SECCFGR1_USART2SEC_Msk /*!< secure access mode for USART2 */ +#define GTZC_TZSC_SECCFGR1_I2C1SEC_Pos (13U) +#define GTZC_TZSC_SECCFGR1_I2C1SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR1_I2C1SEC_Pos) +#define GTZC_TZSC_SECCFGR1_I2C1SEC GTZC_TZSC_SECCFGR1_I2C1SEC_Msk /*!< secure access mode for I2C1 */ +#define GTZC_TZSC_SECCFGR1_LPTIM2SEC_Pos (17U) +#define GTZC_TZSC_SECCFGR1_LPTIM2SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR1_LPTIM2SEC_Pos) +#define GTZC_TZSC_SECCFGR1_LPTIM2SEC GTZC_TZSC_SECCFGR1_LPTIM2SEC_Msk /*!< secure access mode for LPTIM2 */ + +/*************** Bits definition for register x=2 (GTZC_TZSC_SECCFGR2) *************/ +#define GTZC_TZSC_SECCFGR2_TIM1SEC_Pos (0U) +#define GTZC_TZSC_SECCFGR2_TIM1SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR2_TIM1SEC_Pos) +#define GTZC_TZSC_SECCFGR2_TIM1SEC GTZC_TZSC_SECCFGR2_TIM1SEC_Msk /*!< secure access mode for TIM1 */ +#define GTZC_TZSC_SECCFGR2_SPI1SEC_Pos (1U) +#define GTZC_TZSC_SECCFGR2_SPI1SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR2_SPI1SEC_Pos) +#define GTZC_TZSC_SECCFGR2_SPI1SEC GTZC_TZSC_SECCFGR2_SPI1SEC_Msk /*!< secure access mode for SPI1 */ +#define GTZC_TZSC_SECCFGR2_USART1SEC_Pos (3U) +#define GTZC_TZSC_SECCFGR2_USART1SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR2_USART1SEC_Pos) +#define GTZC_TZSC_SECCFGR2_USART1SEC GTZC_TZSC_SECCFGR2_USART1SEC_Msk /*!< secure access mode for USART1 */ +#define GTZC_TZSC_SECCFGR2_TIM16SEC_Pos (5U) +#define GTZC_TZSC_SECCFGR2_TIM16SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR2_TIM16SEC_Pos) +#define GTZC_TZSC_SECCFGR2_TIM16SEC GTZC_TZSC_SECCFGR2_TIM16SEC_Msk /*!< secure access mode for TIM16 */ +#define GTZC_TZSC_SECCFGR2_TIM17SEC_Pos (6U) +#define GTZC_TZSC_SECCFGR2_TIM17SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR2_TIM17SEC_Pos) +#define GTZC_TZSC_SECCFGR2_TIM17SEC GTZC_TZSC_SECCFGR2_TIM17SEC_Msk /*!< secure access mode for TIM17 */ +#define GTZC_TZSC_SECCFGR2_SAI1SEC_Pos (7U) +#define GTZC_TZSC_SECCFGR2_SAI1SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR2_SAI1SEC_Pos) +#define GTZC_TZSC_SECCFGR2_SAI1SEC GTZC_TZSC_SECCFGR2_SAI1SEC_Msk /*!< secure access mode for SAI1 */ +#define GTZC_TZSC_SECCFGR2_SPI3SEC_Pos (16U) +#define GTZC_TZSC_SECCFGR2_SPI3SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR2_SPI3SEC_Pos) +#define GTZC_TZSC_SECCFGR2_SPI3SEC GTZC_TZSC_SECCFGR2_SPI3SEC_Msk /*!< secure access mode for SPI3 */ +#define GTZC_TZSC_SECCFGR2_LPUART1SEC_Pos (17U) +#define GTZC_TZSC_SECCFGR2_LPUART1SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR2_LPUART1SEC_Pos) +#define GTZC_TZSC_SECCFGR2_LPUART1SEC GTZC_TZSC_SECCFGR2_LPUART1SEC_Msk /*!< secure access mode for LPUART1 */ +#define GTZC_TZSC_SECCFGR2_I2C3SEC_Pos (18U) +#define GTZC_TZSC_SECCFGR2_I2C3SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR2_I2C3SEC_Pos) +#define GTZC_TZSC_SECCFGR2_I2C3SEC GTZC_TZSC_SECCFGR2_I2C3SEC_Msk /*!< secure access mode for I2C3 */ +#define GTZC_TZSC_SECCFGR2_LPTIM1SEC_Pos (19U) +#define GTZC_TZSC_SECCFGR2_LPTIM1SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR2_LPTIM1SEC_Pos) +#define GTZC_TZSC_SECCFGR2_LPTIM1SEC GTZC_TZSC_SECCFGR2_LPTIM1SEC_Msk /*!< secure access mode for LPTIM1 */ +#define GTZC_TZSC_SECCFGR2_COMPSEC_Pos (23U) +#define GTZC_TZSC_SECCFGR2_COMPSEC_Msk (0x01UL << GTZC_TZSC_SECCFGR2_COMPSEC_Pos) +#define GTZC_TZSC_SECCFGR2_COMPSEC GTZC_TZSC_SECCFGR2_COMPSEC_Msk /*!< secure access mode for COMP */ +#define GTZC_TZSC_SECCFGR2_ADC4SEC_Pos (24U) +#define GTZC_TZSC_SECCFGR2_ADC4SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR2_ADC4SEC_Pos) +#define GTZC_TZSC_SECCFGR2_ADC4SEC GTZC_TZSC_SECCFGR2_ADC4SEC_Msk /*!< secure access mode for ADC4 */ + +/*************** Bits definition for register x=3 (GTZC_TZSC_SECCFGR3) *************/ +#define GTZC_TZSC_SECCFGR3_CRCSEC_Pos (3U) +#define GTZC_TZSC_SECCFGR3_CRCSEC_Msk (0x01UL << GTZC_TZSC_SECCFGR3_CRCSEC_Pos) +#define GTZC_TZSC_SECCFGR3_CRCSEC GTZC_TZSC_SECCFGR3_CRCSEC_Msk /*!< secure access mode for CRC */ +#define GTZC_TZSC_SECCFGR3_TSCSEC_Pos (4U) +#define GTZC_TZSC_SECCFGR3_TSCSEC_Msk (0x01UL << GTZC_TZSC_SECCFGR3_TSCSEC_Pos) +#define GTZC_TZSC_SECCFGR3_TSCSEC GTZC_TZSC_SECCFGR3_TSCSEC_Msk /*!< secure access mode for TSC */ +#define GTZC_TZSC_SECCFGR3_ICACHE_REGSEC_Pos (6U) +#define GTZC_TZSC_SECCFGR3_ICACHE_REGSEC_Msk (0x01UL << GTZC_TZSC_SECCFGR3_ICACHE_REGSEC_Pos) +#define GTZC_TZSC_SECCFGR3_ICACHE_REGSEC GTZC_TZSC_SECCFGR3_ICACHE_REGSEC_Msk /*!< secure access mode for ICACHE_REG */ +#define GTZC_TZSC_SECCFGR3_AESSEC_Pos (11U) +#define GTZC_TZSC_SECCFGR3_AESSEC_Msk (0x01UL << GTZC_TZSC_SECCFGR3_AESSEC_Pos) +#define GTZC_TZSC_SECCFGR3_AESSEC GTZC_TZSC_SECCFGR3_AESSEC_Msk /*!< secure access mode for AES */ +#define GTZC_TZSC_SECCFGR3_HASHSEC_Pos (12U) +#define GTZC_TZSC_SECCFGR3_HASHSEC_Msk (0x01UL << GTZC_TZSC_SECCFGR3_HASHSEC_Pos) +#define GTZC_TZSC_SECCFGR3_HASHSEC GTZC_TZSC_SECCFGR3_HASHSEC_Msk /*!< secure access mode for HASH */ +#define GTZC_TZSC_SECCFGR3_RNGSEC_Pos (13U) +#define GTZC_TZSC_SECCFGR3_RNGSEC_Msk (0x01UL << GTZC_TZSC_SECCFGR3_RNGSEC_Pos) +#define GTZC_TZSC_SECCFGR3_RNGSEC GTZC_TZSC_SECCFGR3_RNGSEC_Msk /*!< secure access mode for RNG */ +#define GTZC_TZSC_SECCFGR3_SAESSEC_Pos (14U) +#define GTZC_TZSC_SECCFGR3_SAESSEC_Msk (0x01UL << GTZC_TZSC_SECCFGR3_SAESSEC_Pos) +#define GTZC_TZSC_SECCFGR3_SAESSEC GTZC_TZSC_SECCFGR3_SAESSEC_Msk /*!< secure access mode for SAES */ +#define GTZC_TZSC_SECCFGR3_PKASEC_Pos (16U) +#define GTZC_TZSC_SECCFGR3_PKASEC_Msk (0x01UL << GTZC_TZSC_SECCFGR3_PKASEC_Pos) +#define GTZC_TZSC_SECCFGR3_PKASEC GTZC_TZSC_SECCFGR3_PKASEC_Msk /*!< secure access mode for PKA */ +#define GTZC_TZSC_SECCFGR3_RAMCFGSEC_Pos (22U) +#define GTZC_TZSC_SECCFGR3_RAMCFGSEC_Msk (0x01UL << GTZC_TZSC_SECCFGR3_RAMCFGSEC_Pos) +#define GTZC_TZSC_SECCFGR3_RAMCFGSEC GTZC_TZSC_SECCFGR3_RAMCFGSEC_Msk /*!< secure access mode for RAMCFG */ +#define GTZC_TZSC_SECCFGR3_RADIOSEC_Pos (23U) +#define GTZC_TZSC_SECCFGR3_RADIOSEC_Msk (0x01UL << GTZC_TZSC_SECCFGR3_RADIOSEC_Pos) +#define GTZC_TZSC_SECCFGR3_RADIOSEC GTZC_TZSC_SECCFGR3_RADIOSEC_Msk /*!< secure access mode for 2.4 GHz RADIO */ +#define GTZC_TZSC_SECCFGR3_PTACONVSEC_Pos (24U) +#define GTZC_TZSC_SECCFGR3_PTACONVSEC_Msk (0x01UL << GTZC_TZSC_SECCFGR3_PTACONVSEC_Pos) +#define GTZC_TZSC_SECCFGR3_PTACONVSEC GTZC_TZSC_SECCFGR3_PTACONVSEC_Msk /*!< secure access mode for PTACONV */ + +/******************* Bits definition for GTZC_TZSC_PRIVCFGR1 register ***************/ +#define GTZC_TZSC_PRIVCFGR1_TIM2PRIV_Pos (0U) +#define GTZC_TZSC_PRIVCFGR1_TIM2PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR1_TIM2PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR1_TIM2PRIV GTZC_TZSC_PRIVCFGR1_TIM2PRIV_Msk /*!< privileged access mode for TIM2 */ +#define GTZC_TZSC_PRIVCFGR1_TIM3PRIV_Pos (1U) +#define GTZC_TZSC_PRIVCFGR1_TIM3PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR1_TIM3PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR1_TIM3PRIV GTZC_TZSC_PRIVCFGR1_TIM3PRIV_Msk /*!< privileged access mode for TIM3 */ +#define GTZC_TZSC_PRIVCFGR1_WWDGPRIV_Pos (6U) +#define GTZC_TZSC_PRIVCFGR1_WWDGPRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR1_WWDGPRIV_Pos) +#define GTZC_TZSC_PRIVCFGR1_WWDGPRIV GTZC_TZSC_PRIVCFGR1_WWDGPRIV_Msk /*!< privileged access mode for WWDG */ +#define GTZC_TZSC_PRIVCFGR1_IWDGPRIV_Pos (7U) +#define GTZC_TZSC_PRIVCFGR1_IWDGPRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR1_IWDGPRIV_Pos) +#define GTZC_TZSC_PRIVCFGR1_IWDGPRIV GTZC_TZSC_PRIVCFGR1_IWDGPRIV_Msk /*!< privileged access mode for IWDG */ +#define GTZC_TZSC_PRIVCFGR1_USART2PRIV_Pos (9U) +#define GTZC_TZSC_PRIVCFGR1_USART2PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR1_USART2PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR1_USART2PRIV GTZC_TZSC_PRIVCFGR1_USART2PRIV_Msk /*!< privileged access mode for USART2 */ +#define GTZC_TZSC_PRIVCFGR1_I2C1PRIV_Pos (13U) +#define GTZC_TZSC_PRIVCFGR1_I2C1PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR1_I2C1PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR1_I2C1PRIV GTZC_TZSC_PRIVCFGR1_I2C1PRIV_Msk /*!< privileged access mode for I2C1 */ +#define GTZC_TZSC_PRIVCFGR1_LPTIM2PRIV_Pos (17U) +#define GTZC_TZSC_PRIVCFGR1_LPTIM2PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR1_LPTIM2PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR1_LPTIM2PRIV GTZC_TZSC_PRIVCFGR1_LPTIM2PRIV_Msk /*!< privileged access mode for LPTIM2 */ + +/******************* Bits definition for GTZC_TZSC_PRIVCFGR2 register ***************/ +#define GTZC_TZSC_PRIVCFGR2_TIM1PRIV_Pos (0U) +#define GTZC_TZSC_PRIVCFGR2_TIM1PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR2_TIM1PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR2_TIM1PRIV GTZC_TZSC_PRIVCFGR2_TIM1PRIV_Msk /*!< privileged access mode for TIM1 */ +#define GTZC_TZSC_PRIVCFGR2_SPI1PRIV_Pos (1U) +#define GTZC_TZSC_PRIVCFGR2_SPI1PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR2_SPI1PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR2_SPI1PRIV GTZC_TZSC_PRIVCFGR2_SPI1PRIV_Msk /*!< privileged access mode for SPI1 */ +#define GTZC_TZSC_PRIVCFGR2_USART1PRIV_Pos (3U) +#define GTZC_TZSC_PRIVCFGR2_USART1PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR2_USART1PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR2_USART1PRIV GTZC_TZSC_PRIVCFGR2_USART1PRIV_Msk /*!< privileged access mode for USART1 */ +#define GTZC_TZSC_PRIVCFGR2_TIM16PRIV_Pos (5U) +#define GTZC_TZSC_PRIVCFGR2_TIM16PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR2_TIM16PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR2_TIM16PRIV GTZC_TZSC_PRIVCFGR2_TIM16PRIV_Msk /*!< privileged access mode for TIM16 */ +#define GTZC_TZSC_PRIVCFGR2_TIM17PRIV_Pos (6U) +#define GTZC_TZSC_PRIVCFGR2_TIM17PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR2_TIM17PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR2_TIM17PRIV GTZC_TZSC_PRIVCFGR2_TIM17PRIV_Msk /*!< privileged access mode for TIM17 */ +#define GTZC_TZSC_PRIVCFGR2_SAI1PRIV_Pos (7U) +#define GTZC_TZSC_PRIVCFGR2_SAI1PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR2_SAI1PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR2_SAI1PRIV GTZC_TZSC_PRIVCFGR2_SAI1PRIV_Msk /*!< privileged access mode for SAI1 */ +#define GTZC_TZSC_PRIVCFGR2_SPI3PRIV_Pos (16U) +#define GTZC_TZSC_PRIVCFGR2_SPI3PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR2_SPI3PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR2_SPI3PRIV GTZC_TZSC_PRIVCFGR2_SPI3PRIV_Msk /*!< privileged access mode for SPI3 */ +#define GTZC_TZSC_PRIVCFGR2_LPUART1PRIV_Pos (17U) +#define GTZC_TZSC_PRIVCFGR2_LPUART1PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR2_LPUART1PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR2_LPUART1PRIV GTZC_TZSC_PRIVCFGR2_LPUART1PRIV_Msk /*!< privileged access mode for LPUART1 */ +#define GTZC_TZSC_PRIVCFGR2_I2C3PRIV_Pos (18U) +#define GTZC_TZSC_PRIVCFGR2_I2C3PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR2_I2C3PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR2_I2C3PRIV GTZC_TZSC_PRIVCFGR2_I2C3PRIV_Msk /*!< privileged access mode for I2C3 */ +#define GTZC_TZSC_PRIVCFGR2_LPTIM1PRIV_Pos (19U) +#define GTZC_TZSC_PRIVCFGR2_LPTIM1PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR2_LPTIM1PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR2_LPTIM1PRIV GTZC_TZSC_PRIVCFGR2_LPTIM1PRIV_Msk /*!< privileged access mode for LPTIM1 */ +#define GTZC_TZSC_PRIVCFGR2_COMPPRIV_Pos (23U) +#define GTZC_TZSC_PRIVCFGR2_COMPPRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR2_COMPPRIV_Pos) +#define GTZC_TZSC_PRIVCFGR2_COMPPRIV GTZC_TZSC_PRIVCFGR2_COMPPRIV_Msk /*!< privileged access mode for COMP */ +#define GTZC_TZSC_PRIVCFGR2_ADC4PRIV_Pos (24U) +#define GTZC_TZSC_PRIVCFGR2_ADC4PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR2_ADC4PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR2_ADC4PRIV GTZC_TZSC_PRIVCFGR2_ADC4PRIV_Msk /*!< privileged access mode for ADC4 */ + +/******************* Bits definition for GTZC_TZSC_PRIVCFGR3 register ***************/ +#define GTZC_TZSC_PRIVCFGR3_CRCPRIV_Pos (3U) +#define GTZC_TZSC_PRIVCFGR3_CRCPRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR3_CRCPRIV_Pos) +#define GTZC_TZSC_PRIVCFGR3_CRCPRIV GTZC_TZSC_PRIVCFGR3_CRCPRIV_Msk /*!< privileged access mode for CRC */ +#define GTZC_TZSC_PRIVCFGR3_TSCPRIV_Pos (4U) +#define GTZC_TZSC_PRIVCFGR3_TSCPRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR3_TSCPRIV_Pos) +#define GTZC_TZSC_PRIVCFGR3_TSCPRIV GTZC_TZSC_PRIVCFGR3_TSCPRIV_Msk /*!< privileged access mode for TSC */ +#define GTZC_TZSC_PRIVCFGR3_ICACHE_REGPRIV_Pos (6U) +#define GTZC_TZSC_PRIVCFGR3_ICACHE_REGPRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR3_ICACHE_REGPRIV_Pos) +#define GTZC_TZSC_PRIVCFGR3_ICACHE_REGPRIV GTZC_TZSC_PRIVCFGR3_ICACHE_REGPRIV_Msk /*!< privileged access mode for ICACHE_REG */ +#define GTZC_TZSC_PRIVCFGR3_AESPRIV_Pos (11U) +#define GTZC_TZSC_PRIVCFGR3_AESPRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR3_AESPRIV_Pos) +#define GTZC_TZSC_PRIVCFGR3_AESPRIV GTZC_TZSC_PRIVCFGR3_AESPRIV_Msk /*!< privileged access mode for AES */ +#define GTZC_TZSC_PRIVCFGR3_HASHPRIV_Pos (12U) +#define GTZC_TZSC_PRIVCFGR3_HASHPRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR3_HASHPRIV_Pos) +#define GTZC_TZSC_PRIVCFGR3_HASHPRIV GTZC_TZSC_PRIVCFGR3_HASHPRIV_Msk /*!< privileged access mode for HASH */ +#define GTZC_TZSC_PRIVCFGR3_RNGPRIV_Pos (13U) +#define GTZC_TZSC_PRIVCFGR3_RNGPRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR3_RNGPRIV_Pos) +#define GTZC_TZSC_PRIVCFGR3_RNGPRIV GTZC_TZSC_PRIVCFGR3_RNGPRIV_Msk /*!< privileged access mode for RNG */ +#define GTZC_TZSC_PRIVCFGR3_SAESPRIV_Pos (14U) +#define GTZC_TZSC_PRIVCFGR3_SAESPRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR3_SAESPRIV_Pos) +#define GTZC_TZSC_PRIVCFGR3_SAESPRIV GTZC_TZSC_PRIVCFGR3_SAESPRIV_Msk /*!< privileged access mode for SAES */ +#define GTZC_TZSC_PRIVCFGR3_PKAPRIV_Pos (16U) +#define GTZC_TZSC_PRIVCFGR3_PKAPRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR3_PKAPRIV_Pos) +#define GTZC_TZSC_PRIVCFGR3_PKAPRIV GTZC_TZSC_PRIVCFGR3_PKAPRIV_Msk /*!< privileged access mode for PKA */ +#define GTZC_TZSC_PRIVCFGR3_RAMCFGPRIV_Pos (22U) +#define GTZC_TZSC_PRIVCFGR3_RAMCFGPRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR3_RAMCFGPRIV_Pos) +#define GTZC_TZSC_PRIVCFGR3_RAMCFGPRIV GTZC_TZSC_PRIVCFGR3_RAMCFGPRIV_Msk /*!< privileged access mode for RAMCFG */ +#define GTZC_TZSC_PRIVCFGR3_RADIOPRIV_Pos (23U) +#define GTZC_TZSC_PRIVCFGR3_RADIOPRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR3_RADIOPRIV_Pos) +#define GTZC_TZSC_PRIVCFGR3_RADIOPRIV GTZC_TZSC_PRIVCFGR3_RADIOPRIV_Msk /*!< privileged access mode for 2.4 GHz RADIO */ +#define GTZC_TZSC_PRIVCFGR3_PTACONVPRIV_Pos (24U) +#define GTZC_TZSC_PRIVCFGR3_PTACONVPRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR3_PTACONVPRIV_Pos) +#define GTZC_TZSC_PRIVCFGR3_PTACONVPRIV GTZC_TZSC_PRIVCFGR3_PTACONVPRIV_Msk /*!< privileged access mode for PTACONV */ + +/******************* Bits definition for GTZC_TZIC_IER1 register ***************/ +#define GTZC_TZIC_IER1_TIM2IE_Pos (0U) +#define GTZC_TZIC_IER1_TIM2IE_Msk (0x01UL << GTZC_TZIC_IER1_TIM2IE_Pos) +#define GTZC_TZIC_IER1_TIM2IE GTZC_TZIC_IER1_TIM2IE_Msk /*!< illegal access interrupt enable for TIM2 */ +#define GTZC_TZIC_IER1_TIM3IE_Pos (1U) +#define GTZC_TZIC_IER1_TIM3IE_Msk (0x01UL << GTZC_TZIC_IER1_TIM3IE_Pos) +#define GTZC_TZIC_IER1_TIM3IE GTZC_TZIC_IER1_TIM3IE_Msk /*!< illegal access interrupt enable for TIM3 */ +#define GTZC_TZIC_IER1_WWDGIE_Pos (6U) +#define GTZC_TZIC_IER1_WWDGIE_Msk (0x01UL << GTZC_TZIC_IER1_WWDGIE_Pos) +#define GTZC_TZIC_IER1_WWDGIE GTZC_TZIC_IER1_WWDGIE_Msk /*!< illegal access interrupt enable for WWDG */ +#define GTZC_TZIC_IER1_IWDGIE_Pos (7U) +#define GTZC_TZIC_IER1_IWDGIE_Msk (0x01UL << GTZC_TZIC_IER1_IWDGIE_Pos) +#define GTZC_TZIC_IER1_IWDGIE GTZC_TZIC_IER1_IWDGIE_Msk /*!< illegal access interrupt enable for IWDG */ +#define GTZC_TZIC_IER1_USART2IE_Pos (9U) +#define GTZC_TZIC_IER1_USART2IE_Msk (0x01UL << GTZC_TZIC_IER1_USART2IE_Pos) +#define GTZC_TZIC_IER1_USART2IE GTZC_TZIC_IER1_USART2IE_Msk /*!< illegal access interrupt enable for USART2 */ +#define GTZC_TZIC_IER1_I2C1IE_Pos (13U) +#define GTZC_TZIC_IER1_I2C1IE_Msk (0x01UL << GTZC_TZIC_IER1_I2C1IE_Pos) +#define GTZC_TZIC_IER1_I2C1IE GTZC_TZIC_IER1_I2C1IE_Msk /*!< illegal access interrupt enable for I2C1 */ +#define GTZC_TZIC_IER1_LPTIM2IE_Pos (17U) +#define GTZC_TZIC_IER1_LPTIM2IE_Msk (0x01UL << GTZC_TZIC_IER1_LPTIM2IE_Pos) +#define GTZC_TZIC_IER1_LPTIM2IE GTZC_TZIC_IER1_LPTIM2IE_Msk /*!< illegal access interrupt enable for LPTIM2 */ + +/******************* Bits definition for GTZC_TZIC_IER2 register ***************/ +#define GTZC_TZIC_IER2_TIM1IE_Pos (0U) +#define GTZC_TZIC_IER2_TIM1IE_Msk (0x01UL << GTZC_TZIC_IER2_TIM1IE_Pos) +#define GTZC_TZIC_IER2_TIM1IE GTZC_TZIC_IER2_TIM1IE_Msk /*!< illegal access interrupt enable for TIM1 */ +#define GTZC_TZIC_IER2_SPI1IE_Pos (1U) +#define GTZC_TZIC_IER2_SPI1IE_Msk (0x01UL << GTZC_TZIC_IER2_SPI1IE_Pos) +#define GTZC_TZIC_IER2_SPI1IE GTZC_TZIC_IER2_SPI1IE_Msk /*!< illegal access interrupt enable for SPI1 */ +#define GTZC_TZIC_IER2_USART1IE_Pos (3U) +#define GTZC_TZIC_IER2_USART1IE_Msk (0x01UL << GTZC_TZIC_IER2_USART1IE_Pos) +#define GTZC_TZIC_IER2_USART1IE GTZC_TZIC_IER2_USART1IE_Msk /*!< illegal access interrupt enable for USART1 */ +#define GTZC_TZIC_IER2_TIM16IE_Pos (5U) +#define GTZC_TZIC_IER2_TIM16IE_Msk (0x01UL << GTZC_TZIC_IER2_TIM16IE_Pos) +#define GTZC_TZIC_IER2_TIM16IE GTZC_TZIC_IER2_TIM16IE_Msk /*!< illegal access interrupt enable for TIM16 */ +#define GTZC_TZIC_IER2_TIM17IE_Pos (6U) +#define GTZC_TZIC_IER2_TIM17IE_Msk (0x01UL << GTZC_TZIC_IER2_TIM17IE_Pos) +#define GTZC_TZIC_IER2_TIM17IE GTZC_TZIC_IER2_TIM17IE_Msk /*!< illegal access interrupt enable for TIM17 */ +#define GTZC_TZIC_IER2_SAI1IE_Pos (7U) +#define GTZC_TZIC_IER2_SAI1IE_Msk (0x01UL << GTZC_TZIC_IER2_SAI1IE_Pos) +#define GTZC_TZIC_IER2_SAI1IE GTZC_TZIC_IER2_SAI1IE_Msk /*!< illegal access interrupt enable for SAI1 */ +#define GTZC_TZIC_IER2_SPI3IE_Pos (16U) +#define GTZC_TZIC_IER2_SPI3IE_Msk (0x01UL << GTZC_TZIC_IER2_SPI3IE_Pos) +#define GTZC_TZIC_IER2_SPI3IE GTZC_TZIC_IER2_SPI3IE_Msk /*!< illegal access interrupt enable for SPI3 */ +#define GTZC_TZIC_IER2_LPUART1IE_Pos (17U) +#define GTZC_TZIC_IER2_LPUART1IE_Msk (0x01UL << GTZC_TZIC_IER2_LPUART1IE_Pos) +#define GTZC_TZIC_IER2_LPUART1IE GTZC_TZIC_IER2_LPUART1IE_Msk /*!< illegal access interrupt enable for LPUART1 */ +#define GTZC_TZIC_IER2_I2C3IE_Pos (18U) +#define GTZC_TZIC_IER2_I2C3IE_Msk (0x01UL << GTZC_TZIC_IER2_I2C3IE_Pos) +#define GTZC_TZIC_IER2_I2C3IE GTZC_TZIC_IER2_I2C3IE_Msk /*!< illegal access interrupt enable for I2C3 */ +#define GTZC_TZIC_IER2_LPTIM1IE_Pos (19U) +#define GTZC_TZIC_IER2_LPTIM1IE_Msk (0x01UL << GTZC_TZIC_IER2_LPTIM1IE_Pos) +#define GTZC_TZIC_IER2_LPTIM1IE GTZC_TZIC_IER2_LPTIM1IE_Msk /*!< illegal access interrupt enable for LPTIM1 */ +#define GTZC_TZIC_IER2_COMPIE_Pos (23U) +#define GTZC_TZIC_IER2_COMPIE_Msk (0x01UL << GTZC_TZIC_IER2_COMPIE_Pos) +#define GTZC_TZIC_IER2_COMPIE GTZC_TZIC_IER2_COMPIE_Msk /*!< illegal access interrupt enable for COMP */ +#define GTZC_TZIC_IER2_ADC4IE_Pos (24U) +#define GTZC_TZIC_IER2_ADC4IE_Msk (0x01UL << GTZC_TZIC_IER2_ADC4IE_Pos) +#define GTZC_TZIC_IER2_ADC4IE GTZC_TZIC_IER2_ADC4IE_Msk /*!< illegal access interrupt enable for ADC4 */ + +/******************* Bits definition for GTZC_TZIC_IER3 register ***************/ +#define GTZC_TZIC_IER3_CRCIE_Pos (3U) +#define GTZC_TZIC_IER3_CRCIE_Msk (0x01UL << GTZC_TZIC_IER3_CRCIE_Pos) +#define GTZC_TZIC_IER3_CRCIE GTZC_TZIC_IER3_CRCIE_Msk /*!< illegal access interrupt enable for CRC */ +#define GTZC_TZIC_IER3_TSCIE_Pos (4U) +#define GTZC_TZIC_IER3_TSCIE_Msk (0x01UL << GTZC_TZIC_IER3_TSCIE_Pos) +#define GTZC_TZIC_IER3_TSCIE GTZC_TZIC_IER3_TSCIE_Msk /*!< illegal access interrupt enable for TSC */ +#define GTZC_TZIC_IER3_ICACHE_REGIE_Pos (6U) +#define GTZC_TZIC_IER3_ICACHE_REGIE_Msk (0x01UL << GTZC_TZIC_IER3_ICACHE_REGIE_Pos) +#define GTZC_TZIC_IER3_ICACHE_REGIE GTZC_TZIC_IER3_ICACHE_REGIE_Msk /*!< illegal access interrupt enable for ICACHE_REG */ +#define GTZC_TZIC_IER3_AESIE_Pos (11U) +#define GTZC_TZIC_IER3_AESIE_Msk (0x01UL << GTZC_TZIC_IER3_AESIE_Pos) +#define GTZC_TZIC_IER3_AESIE GTZC_TZIC_IER3_AESIE_Msk /*!< illegal access interrupt enable for AES */ +#define GTZC_TZIC_IER3_HASHIE_Pos (12U) +#define GTZC_TZIC_IER3_HASHIE_Msk (0x01UL << GTZC_TZIC_IER3_HASHIE_Pos) +#define GTZC_TZIC_IER3_HASHIE GTZC_TZIC_IER3_HASHIE_Msk /*!< illegal access interrupt enable for HASH */ +#define GTZC_TZIC_IER3_RNGIE_Pos (13U) +#define GTZC_TZIC_IER3_RNGIE_Msk (0x01UL << GTZC_TZIC_IER3_RNGIE_Pos) +#define GTZC_TZIC_IER3_RNGIE GTZC_TZIC_IER3_RNGIE_Msk /*!< illegal access interrupt enable for RNG */ +#define GTZC_TZIC_IER3_SAESIE_Pos (14U) +#define GTZC_TZIC_IER3_SAESIE_Msk (0x01UL << GTZC_TZIC_IER3_SAESIE_Pos) +#define GTZC_TZIC_IER3_SAESIE GTZC_TZIC_IER3_SAESIE_Msk /*!< illegal access interrupt enable for SAES */ +#define GTZC_TZIC_IER3_HSEMIE_Pos (15U) +#define GTZC_TZIC_IER3_HSEMIE_Msk (0x01UL << GTZC_TZIC_IER3_HSEMIE_Pos) +#define GTZC_TZIC_IER3_HSEMIE GTZC_TZIC_IER3_HSEMIE_Msk /*!< illegal access interrupt enable for HSEM */ +#define GTZC_TZIC_IER3_PKAIE_Pos (16U) +#define GTZC_TZIC_IER3_PKAIE_Msk (0x01UL << GTZC_TZIC_IER3_PKAIE_Pos) +#define GTZC_TZIC_IER3_PKAIE GTZC_TZIC_IER3_PKAIE_Msk /*!< illegal access interrupt enable for PKA */ +#define GTZC_TZIC_IER3_RAMCFGIE_Pos (22U) +#define GTZC_TZIC_IER3_RAMCFGIE_Msk (0x01UL << GTZC_TZIC_IER3_RAMCFGIE_Pos) +#define GTZC_TZIC_IER3_RAMCFGIE GTZC_TZIC_IER3_RAMCFGIE_Msk /*!< illegal access interrupt enable for RAMCFG */ +#define GTZC_TZIC_IER3_RADIOIE_Pos (23U) +#define GTZC_TZIC_IER3_RADIOIE_Msk (0x01UL << GTZC_TZIC_IER3_RADIOIE_Pos) +#define GTZC_TZIC_IER3_RADIOIE GTZC_TZIC_IER3_RADIOIE_Msk /*!< illegal access interrupt enable for 2.4 GHz RADIO */ +#define GTZC_TZIC_IER3_PTACONVIE_Pos (24U) +#define GTZC_TZIC_IER3_PTACONVIE_Msk (0x01UL << GTZC_TZIC_IER3_PTACONVIE_Pos) +#define GTZC_TZIC_IER3_PTACONVIE GTZC_TZIC_IER3_PTACONVIE_Msk /*!< illegal access interrupt enable for PTACONV */ + +/******************* Bits definition for GTZC_TZIC_IER4 register ***************/ +#define GTZC_TZIC_IER4_GPDMA1IE_Pos (0U) +#define GTZC_TZIC_IER4_GPDMA1IE_Msk (0x01UL << GTZC_TZIC_IER4_GPDMA1IE_Pos) +#define GTZC_TZIC_IER4_GPDMA1IE GTZC_TZIC_IER4_GPDMA1IE_Msk /*!< illegal access interrupt enable for GPDMA1 */ +#define GTZC_TZIC_IER4_FLASHIE_Pos (1U) +#define GTZC_TZIC_IER4_FLASHIE_Msk (0x01UL << GTZC_TZIC_IER4_FLASHIE_Pos) +#define GTZC_TZIC_IER4_FLASHIE GTZC_TZIC_IER4_FLASHIE_Msk /*!< illegal access interrupt enable for FLASH memory */ +#define GTZC_TZIC_IER4_FLASH_REGIE_Pos (2U) +#define GTZC_TZIC_IER4_FLASH_REGIE_Msk (0x01UL << GTZC_TZIC_IER4_FLASH_REGIE_Pos) +#define GTZC_TZIC_IER4_FLASH_REGIE GTZC_TZIC_IER4_FLASH_REGIE_Msk /*!< illegal access interrupt enable for FLASH interface */ +#define GTZC_TZIC_IER4_SYSCFGIE_Pos (7U) +#define GTZC_TZIC_IER4_SYSCFGIE_Msk (0x01UL << GTZC_TZIC_IER4_SYSCFGIE_Pos) +#define GTZC_TZIC_IER4_SYSCFGIE GTZC_TZIC_IER4_SYSCFGIE_Msk /*!< illegal access interrupt enable for SYSCFG interface */ +#define GTZC_TZIC_IER4_RTCIE_Pos (8U) +#define GTZC_TZIC_IER4_RTCIE_Msk (0x01UL << GTZC_TZIC_IER4_RTCIE_Pos) +#define GTZC_TZIC_IER4_RTCIE GTZC_TZIC_IER4_RTCIE_Msk /*!< illegal access interrupt enable for RTC interface */ +#define GTZC_TZIC_IER4_TAMPIE_Pos (9U) +#define GTZC_TZIC_IER4_TAMPIE_Msk (0x01UL << GTZC_TZIC_IER4_TAMPIE_Pos) +#define GTZC_TZIC_IER4_TAMPIE GTZC_TZIC_IER4_TAMPIE_Msk /*!< illegal access interrupt enable for TAMP interface */ +#define GTZC_TZIC_IER4_PWRIE_Pos (10U) +#define GTZC_TZIC_IER4_PWRIE_Msk (0x01UL << GTZC_TZIC_IER4_PWRIE_Pos) +#define GTZC_TZIC_IER4_PWRIE GTZC_TZIC_IER4_PWRIE_Msk /*!< illegal access interrupt enable for PWR interface */ +#define GTZC_TZIC_IER4_RCCIE_Pos (11U) +#define GTZC_TZIC_IER4_RCCIE_Msk (0x01UL << GTZC_TZIC_IER4_RCCIE_Pos) +#define GTZC_TZIC_IER4_RCCIE GTZC_TZIC_IER4_RCCIE_Msk /*!< illegal access interrupt enable for RCC interface */ +#define GTZC_TZIC_IER4_EXTIIE_Pos (13U) +#define GTZC_TZIC_IER4_EXTIIE_Msk (0x01UL << GTZC_TZIC_IER4_EXTIIE_Pos) +#define GTZC_TZIC_IER4_EXTIIE GTZC_TZIC_IER4_EXTIIE_Msk /*!< illegal access interrupt enable for EXTI interface */ +#define GTZC_TZIC_IER4_TZSCIE_Pos (14U) +#define GTZC_TZIC_IER4_TZSCIE_Msk (0x01UL << GTZC_TZIC_IER4_TZSCIE_Pos) +#define GTZC_TZIC_IER4_TZSCIE GTZC_TZIC_IER4_TZSCIE_Msk /*!< illegal access interrupt enable for GTZC TZSC */ +#define GTZC_TZIC_IER4_TZICIE_Pos (15U) +#define GTZC_TZIC_IER4_TZICIE_Msk (0x01UL << GTZC_TZIC_IER4_TZICIE_Pos) +#define GTZC_TZIC_IER4_TZICIE GTZC_TZIC_IER4_TZICIE_Msk /*!< illegal access interrupt enable for GTZC TZIC */ +#define GTZC_TZIC_IER4_SRAM1IE_Pos (22U) +#define GTZC_TZIC_IER4_SRAM1IE_Msk (0x01UL << GTZC_TZIC_IER4_SRAM1IE_Pos) +#define GTZC_TZIC_IER4_SRAM1IE GTZC_TZIC_IER4_SRAM1IE_Msk /*!< illegal access interrupt enable for SRAM1 memory */ +#define GTZC_TZIC_IER4_MPCBB1IE_Pos (23U) +#define GTZC_TZIC_IER4_MPCBB1IE_Msk (0x01UL << GTZC_TZIC_IER4_MPCBB1IE_Pos) +#define GTZC_TZIC_IER4_MPCBB1IE GTZC_TZIC_IER4_MPCBB1IE_Msk /*!< illegal access interrupt enable for MPCBB1 */ +#define GTZC_TZIC_IER4_SRAM2IE_Pos (24U) +#define GTZC_TZIC_IER4_SRAM2IE_Msk (0x01UL << GTZC_TZIC_IER4_SRAM2IE_Pos) +#define GTZC_TZIC_IER4_SRAM2IE GTZC_TZIC_IER4_SRAM2IE_Msk /*!< illegal access interrupt enable for SRAM2 memory */ +#define GTZC_TZIC_IER4_MPCBB2IE_Pos (25U) +#define GTZC_TZIC_IER4_MPCBB2IE_Msk (0x01UL << GTZC_TZIC_IER4_MPCBB2IE_Pos) +#define GTZC_TZIC_IER4_MPCBB2IE GTZC_TZIC_IER4_MPCBB2IE_Msk /*!< illegal access interrupt enable for MPCBB2 */ +#define GTZC_TZIC_IER4_SRAM6IE_Pos (30U) +#define GTZC_TZIC_IER4_SRAM6IE_Msk (0x01UL << GTZC_TZIC_IER4_SRAM6IE_Pos) +#define GTZC_TZIC_IER4_SRAM6IE GTZC_TZIC_IER4_SRAM6IE_Msk /*!< illegal access interrupt enable for 2.4GHz TXRX SRAM memory */ +#define GTZC_TZIC_IER4_MPCBB6IE_Pos (31U) +#define GTZC_TZIC_IER4_MPCBB6IE_Msk (0x01UL << GTZC_TZIC_IER4_MPCBB6IE_Pos) +#define GTZC_TZIC_IER4_MPCBB6IE GTZC_TZIC_IER4_MPCBB6IE_Msk /*!< illegal access interrupt enable for MPCBB6 */ + +/******************* Bits definition for GTZC_TZIC_SR1 register **************/ +#define GTZC_TZIC_SR1_TIM2F_Pos (0U) +#define GTZC_TZIC_SR1_TIM2F_Msk (0x01UL << GTZC_TZIC_SR1_TIM2F_Pos) +#define GTZC_TZIC_SR1_TIM2F GTZC_TZIC_SR1_TIM2F_Msk /*!< illegal access flag for TIM2 */ +#define GTZC_TZIC_SR1_TIM3F_Pos (1U) +#define GTZC_TZIC_SR1_TIM3F_Msk (0x01UL << GTZC_TZIC_SR1_TIM3F_Pos) +#define GTZC_TZIC_SR1_TIM3F GTZC_TZIC_SR1_TIM3F_Msk /*!< illegal access flag for TIM3 */ +#define GTZC_TZIC_SR1_WWDGF_Pos (6U) +#define GTZC_TZIC_SR1_WWDGF_Msk (0x01UL << GTZC_TZIC_SR1_WWDGF_Pos) +#define GTZC_TZIC_SR1_WWDGF GTZC_TZIC_SR1_WWDGF_Msk /*!< illegal access flag for WWDG */ +#define GTZC_TZIC_SR1_IWDGF_Pos (7U) +#define GTZC_TZIC_SR1_IWDGF_Msk (0x01UL << GTZC_TZIC_SR1_IWDGF_Pos) +#define GTZC_TZIC_SR1_IWDGF GTZC_TZIC_SR1_IWDGF_Msk /*!< illegal access flag for IWDG */ +#define GTZC_TZIC_SR1_USART2F_Pos (9U) +#define GTZC_TZIC_SR1_USART2F_Msk (0x01UL << GTZC_TZIC_SR1_USART2F_Pos) +#define GTZC_TZIC_SR1_USART2F GTZC_TZIC_SR1_USART2F_Msk /*!< illegal access flag for USART2 */ +#define GTZC_TZIC_SR1_I2C1F_Pos (13U) +#define GTZC_TZIC_SR1_I2C1F_Msk (0x01UL << GTZC_TZIC_SR1_I2C1F_Pos) +#define GTZC_TZIC_SR1_I2C1F GTZC_TZIC_SR1_I2C1F_Msk /*!< illegal access flag for I2C1 */ +#define GTZC_TZIC_SR1_LPTIM2F_Pos (17U) +#define GTZC_TZIC_SR1_LPTIM2F_Msk (0x01UL << GTZC_TZIC_SR1_LPTIM2F_Pos) +#define GTZC_TZIC_SR1_LPTIM2F GTZC_TZIC_SR1_LPTIM2F_Msk /*!< illegal access flag for LPTIM2 */ + +/******************* Bits definition for GTZC_TZIC_SR2 register **************/ +#define GTZC_TZIC_SR2_TIM1F_Pos (0U) +#define GTZC_TZIC_SR2_TIM1F_Msk (0x01UL << GTZC_TZIC_SR2_TIM1F_Pos) +#define GTZC_TZIC_SR2_TIM1F GTZC_TZIC_SR2_TIM1F_Msk /*!< illegal access flag for TIM1 */ +#define GTZC_TZIC_SR2_SPI1F_Pos (1U) +#define GTZC_TZIC_SR2_SPI1F_Msk (0x01UL << GTZC_TZIC_SR2_SPI1F_Pos) +#define GTZC_TZIC_SR2_SPI1F GTZC_TZIC_SR2_SPI1F_Msk /*!< illegal access flag for SPI1 */ +#define GTZC_TZIC_SR2_USART1F_Pos (3U) +#define GTZC_TZIC_SR2_USART1F_Msk (0x01UL << GTZC_TZIC_SR2_USART1F_Pos) +#define GTZC_TZIC_SR2_USART1F GTZC_TZIC_SR2_USART1F_Msk /*!< illegal access flag for USART1 */ +#define GTZC_TZIC_SR2_TIM16F_Pos (5U) +#define GTZC_TZIC_SR2_TIM16F_Msk (0x01UL << GTZC_TZIC_SR2_TIM16F_Pos) +#define GTZC_TZIC_SR2_TIM16F GTZC_TZIC_SR2_TIM16F_Msk /*!< illegal access flag for TIM16 */ +#define GTZC_TZIC_SR2_TIM17F_Pos (6U) +#define GTZC_TZIC_SR2_TIM17F_Msk (0x01UL << GTZC_TZIC_SR2_TIM17F_Pos) +#define GTZC_TZIC_SR2_TIM17F GTZC_TZIC_SR2_TIM17F_Msk /*!< illegal access flag for TIM17 */ +#define GTZC_TZIC_SR2_SAI1F_Pos (7U) +#define GTZC_TZIC_SR2_SAI1F_Msk (0x01UL << GTZC_TZIC_SR2_SAI1F_Pos) +#define GTZC_TZIC_SR2_SAI1F GTZC_TZIC_SR2_SAI1F_Msk /*!< illegal access flag for SAI1 */ +#define GTZC_TZIC_SR2_SPI3F_Pos (16U) +#define GTZC_TZIC_SR2_SPI3F_Msk (0x01UL << GTZC_TZIC_SR2_SPI3F_Pos) +#define GTZC_TZIC_SR2_SPI3F GTZC_TZIC_SR2_SPI3F_Msk /*!< illegal access flag for SPI3 */ +#define GTZC_TZIC_SR2_LPUART1F_Pos (17U) +#define GTZC_TZIC_SR2_LPUART1F_Msk (0x01UL << GTZC_TZIC_SR2_LPUART1F_Pos) +#define GTZC_TZIC_SR2_LPUART1F GTZC_TZIC_SR2_LPUART1F_Msk /*!< illegal access flag for LPUART1 */ +#define GTZC_TZIC_SR2_I2C3F_Pos (18U) +#define GTZC_TZIC_SR2_I2C3F_Msk (0x01UL << GTZC_TZIC_SR2_I2C3F_Pos) +#define GTZC_TZIC_SR2_I2C3F GTZC_TZIC_SR2_I2C3F_Msk /*!< illegal access flag for I2C3 */ +#define GTZC_TZIC_SR2_LPTIM1F_Pos (19U) +#define GTZC_TZIC_SR2_LPTIM1F_Msk (0x01UL << GTZC_TZIC_SR2_LPTIM1F_Pos) +#define GTZC_TZIC_SR2_LPTIM1F GTZC_TZIC_SR2_LPTIM1F_Msk /*!< illegal access flag for LPTIM1 */ +#define GTZC_TZIC_SR2_COMPF_Pos (23U) +#define GTZC_TZIC_SR2_COMPF_Msk (0x01UL << GTZC_TZIC_SR2_COMPF_Pos) +#define GTZC_TZIC_SR2_COMPF GTZC_TZIC_SR2_COMPF_Msk /*!< illegal access flag for COMP */ +#define GTZC_TZIC_SR2_ADC4F_Pos (24U) +#define GTZC_TZIC_SR2_ADC4F_Msk (0x01UL << GTZC_TZIC_SR2_ADC4F_Pos) +#define GTZC_TZIC_SR2_ADC4F GTZC_TZIC_SR2_ADC4F_Msk /*!< illegal access flag for ADC4 */ + +/******************* Bits definition for GTZC_TZIC_SR3 register **************/ +#define GTZC_TZIC_SR3_CRCF_Pos (3U) +#define GTZC_TZIC_SR3_CRCF_Msk (0x01UL << GTZC_TZIC_SR3_CRCF_Pos) +#define GTZC_TZIC_SR3_CRCF GTZC_TZIC_SR3_CRCF_Msk /*!< illegal access flag for CRC */ +#define GTZC_TZIC_SR3_TSCF_Pos (4U) +#define GTZC_TZIC_SR3_TSCF_Msk (0x01UL << GTZC_TZIC_SR3_TSCF_Pos) +#define GTZC_TZIC_SR3_TSCF GTZC_TZIC_SR3_TSCF_Msk /*!< illegal access flag for TSC */ +#define GTZC_TZIC_SR3_ICACHE_REGF_Pos (6U) +#define GTZC_TZIC_SR3_ICACHE_REGF_Msk (0x01UL << GTZC_TZIC_SR3_ICACHE_REGF_Pos) +#define GTZC_TZIC_SR3_ICACHE_REGF GTZC_TZIC_SR3_ICACHE_REGF_Msk /*!< illegal access flag for ICACHE_REG */ +#define GTZC_TZIC_SR3_AESF_Pos (11U) +#define GTZC_TZIC_SR3_AESF_Msk (0x01UL << GTZC_TZIC_SR3_AESF_Pos) +#define GTZC_TZIC_SR3_AESF GTZC_TZIC_SR3_AESF_Msk /*!< illegal access flag for AES */ +#define GTZC_TZIC_SR3_HASHF_Pos (12U) +#define GTZC_TZIC_SR3_HASHF_Msk (0x01UL << GTZC_TZIC_SR3_HASHF_Pos) +#define GTZC_TZIC_SR3_HASHF GTZC_TZIC_SR3_HASHF_Msk /*!< illegal access flag for HASH */ +#define GTZC_TZIC_SR3_RNGF_Pos (13U) +#define GTZC_TZIC_SR3_RNGF_Msk (0x01UL << GTZC_TZIC_SR3_RNGF_Pos) +#define GTZC_TZIC_SR3_RNGF GTZC_TZIC_SR3_RNGF_Msk /*!< illegal access flag for RNG */ +#define GTZC_TZIC_SR3_SAESF_Pos (14U) +#define GTZC_TZIC_SR3_SAESF_Msk (0x01UL << GTZC_TZIC_SR3_SAESF_Pos) +#define GTZC_TZIC_SR3_SAESF GTZC_TZIC_SR3_SAESF_Msk /*!< illegal access flag for SAES */ +#define GTZC_TZIC_SR3_HSEMF_Pos (15U) +#define GTZC_TZIC_SR3_HSEMF_Msk (0x01UL << GTZC_TZIC_SR3_HSEMF_Pos) +#define GTZC_TZIC_SR3_HSEMF GTZC_TZIC_SR3_HSEMF_Msk /*!< illegal access flag for HSEM */ +#define GTZC_TZIC_SR3_PKAF_Pos (16U) +#define GTZC_TZIC_SR3_PKAF_Msk (0x01UL << GTZC_TZIC_SR3_PKAF_Pos) +#define GTZC_TZIC_SR3_PKAF GTZC_TZIC_SR3_PKAF_Msk /*!< illegal access flag for PKA */ +#define GTZC_TZIC_SR3_RAMCFGF_Pos (22U) +#define GTZC_TZIC_SR3_RAMCFGF_Msk (0x01UL << GTZC_TZIC_SR3_RAMCFGF_Pos) +#define GTZC_TZIC_SR3_RAMCFGF GTZC_TZIC_SR3_RAMCFGF_Msk /*!< illegal access flag for RAMCFG */ +#define GTZC_TZIC_SR3_RADIOF_Pos (23U) +#define GTZC_TZIC_SR3_RADIOF_Msk (0x01UL << GTZC_TZIC_SR3_RADIOF_Pos) +#define GTZC_TZIC_SR3_RADIOF GTZC_TZIC_SR3_RADIOF_Msk /*!< illegal access flag for 2.4 GHz RADIO */ +#define GTZC_TZIC_SR3_PTACONVF_Pos (24U) +#define GTZC_TZIC_SR3_PTACONVF_Msk (0x01UL << GTZC_TZIC_SR3_PTACONVF_Pos) +#define GTZC_TZIC_SR3_PTACONVF GTZC_TZIC_SR3_PTACONVF_Msk /*!< illegal access flag for PTACONV */ + +/******************* Bits definition for GTZC_TZIC_SR4 register ***************/ +#define GTZC_TZIC_SR4_GPDMA1F_Pos (0U) +#define GTZC_TZIC_SR4_GPDMA1F_Msk (0x01UL << GTZC_TZIC_SR4_GPDMA1F_Pos) +#define GTZC_TZIC_SR4_GPDMA1F GTZC_TZIC_SR4_GPDMA1F_Msk /*!< illegal access flag for GPDMA1 */ +#define GTZC_TZIC_SR4_FLASHF_Pos (1U) +#define GTZC_TZIC_SR4_FLASHF_Msk (0x01UL << GTZC_TZIC_SR4_FLASHF_Pos) +#define GTZC_TZIC_SR4_FLASHF GTZC_TZIC_SR4_FLASHF_Msk /*!< illegal access flag for FLASH memory */ +#define GTZC_TZIC_SR4_FLASH_REGF_Pos (2U) +#define GTZC_TZIC_SR4_FLASH_REGF_Msk (0x01UL << GTZC_TZIC_SR4_FLASH_REGF_Pos) +#define GTZC_TZIC_SR4_FLASH_REGF GTZC_TZIC_SR4_FLASH_REGF_Msk /*!< illegal access flag for FLASH interface */ +#define GTZC_TZIC_SR4_SYSCFGF_Pos (7U) +#define GTZC_TZIC_SR4_SYSCFGF_Msk (0x01UL << GTZC_TZIC_SR4_SYSCFGF_Pos) +#define GTZC_TZIC_SR4_SYSCFGF GTZC_TZIC_SR4_SYSCFGF_Msk /*!< illegal access flag for SYSCFG interface */ +#define GTZC_TZIC_SR4_RTCF_Pos (8U) +#define GTZC_TZIC_SR4_RTCF_Msk (0x01UL << GTZC_TZIC_SR4_RTCF_Pos) +#define GTZC_TZIC_SR4_RTCF GTZC_TZIC_SR4_RTCF_Msk /*!< illegal access flag for RTC interface */ +#define GTZC_TZIC_SR4_TAMPF_Pos (9U) +#define GTZC_TZIC_SR4_TAMPF_Msk (0x01UL << GTZC_TZIC_SR4_TAMPF_Pos) +#define GTZC_TZIC_SR4_TAMPF GTZC_TZIC_SR4_TAMPF_Msk /*!< illegal access flag for TAMP interface */ +#define GTZC_TZIC_SR4_PWRF_Pos (10U) +#define GTZC_TZIC_SR4_PWRF_Msk (0x01UL << GTZC_TZIC_SR4_PWRF_Pos) +#define GTZC_TZIC_SR4_PWRF GTZC_TZIC_SR4_PWRF_Msk /*!< illegal access flag for PWR interface */ +#define GTZC_TZIC_SR4_RCCF_Pos (11U) +#define GTZC_TZIC_SR4_RCCF_Msk (0x01UL << GTZC_TZIC_SR4_RCCF_Pos) +#define GTZC_TZIC_SR4_RCCF GTZC_TZIC_SR4_RCCF_Msk /*!< illegal access flag for RCC interface */ +#define GTZC_TZIC_SR4_EXTIF_Pos (13U) +#define GTZC_TZIC_SR4_EXTIF_Msk (0x01UL << GTZC_TZIC_SR4_EXTIF_Pos) +#define GTZC_TZIC_SR4_EXTIF GTZC_TZIC_SR4_EXTIF_Msk /*!< illegal access flag for EXTI interface */ +#define GTZC_TZIC_SR4_TZSCF_Pos (14U) +#define GTZC_TZIC_SR4_TZSCF_Msk (0x01UL << GTZC_TZIC_SR4_TZSCF_Pos) +#define GTZC_TZIC_SR4_TZSCF GTZC_TZIC_SR4_TZSCF_Msk /*!< illegal access flag for GTZC TZSC */ +#define GTZC_TZIC_SR4_TZICF_Pos (15U) +#define GTZC_TZIC_SR4_TZICF_Msk (0x01UL << GTZC_TZIC_SR4_TZICF_Pos) +#define GTZC_TZIC_SR4_TZICF GTZC_TZIC_SR4_TZICF_Msk /*!< illegal access flag for GTZC TZIC */ +#define GTZC_TZIC_SR4_SRAM1F_Pos (22U) +#define GTZC_TZIC_SR4_SRAM1F_Msk (0x01UL << GTZC_TZIC_SR4_SRAM1F_Pos) +#define GTZC_TZIC_SR4_SRAM1F GTZC_TZIC_SR4_SRAM1F_Msk /*!< illegal access flag for SRAM1 memory */ +#define GTZC_TZIC_SR4_MPCBB1F_Pos (23U) +#define GTZC_TZIC_SR4_MPCBB1F_Msk (0x01UL << GTZC_TZIC_SR4_MPCBB1F_Pos) +#define GTZC_TZIC_SR4_MPCBB1F GTZC_TZIC_SR4_MPCBB1F_Msk /*!< illegal access flag for MPCBB1 */ +#define GTZC_TZIC_SR4_SRAM2F_Pos (24U) +#define GTZC_TZIC_SR4_SRAM2F_Msk (0x01UL << GTZC_TZIC_SR4_SRAM2F_Pos) +#define GTZC_TZIC_SR4_SRAM2F GTZC_TZIC_SR4_SRAM2F_Msk /*!< illegal access flag for SRAM2 memory */ +#define GTZC_TZIC_SR4_MPCBB2F_Pos (25U) +#define GTZC_TZIC_SR4_MPCBB2F_Msk (0x01UL << GTZC_TZIC_SR4_MPCBB2F_Pos) +#define GTZC_TZIC_SR4_MPCBB2F GTZC_TZIC_SR4_MPCBB2F_Msk /*!< illegal access flag for MPCBB2 */ +#define GTZC_TZIC_SR4_SRAM6F_Pos (30U) +#define GTZC_TZIC_SR4_SRAM6F_Msk (0x01UL << GTZC_TZIC_SR4_SRAM6F_Pos) +#define GTZC_TZIC_SR4_SRAM6F GTZC_TZIC_SR4_SRAM6F_Msk /*!< illegal access flag for 2.4GHz TXRX SRAM memory */ +#define GTZC_TZIC_SR4_MPCBB6F_Pos (31U) +#define GTZC_TZIC_SR4_MPCBB6F_Msk (0x01UL << GTZC_TZIC_SR4_MPCBB6F_Pos) +#define GTZC_TZIC_SR4_MPCBB6F GTZC_TZIC_SR4_MPCBB6F_Msk /*!< illegal access flag for MPCBB6 */ + +/****************** Bits definition for GTZC_TZIC_FCR1 register ****************/ +#define GTZC_TZIC_FCR1_CTIM2F_Pos (0U) +#define GTZC_TZIC_FCR1_CTIM2F_Msk (0x01UL << GTZC_TZIC_FCR1_CTIM2F_Pos) +#define GTZC_TZIC_FCR1_CTIM2F GTZC_TZIC_FCR1_CTIM2F_Msk /*!< clear the illegal access flag for TIM2 */ +#define GTZC_TZIC_FCR1_CTIM3F_Pos (1U) +#define GTZC_TZIC_FCR1_CTIM3F_Msk (0x01UL << GTZC_TZIC_FCR1_CTIM3F_Pos) +#define GTZC_TZIC_FCR1_CTIM3F GTZC_TZIC_FCR1_CTIM3F_Msk /*!< clear the illegal access flag for TIM3 */ +#define GTZC_TZIC_FCR1_CWWDGF_Pos (6U) +#define GTZC_TZIC_FCR1_CWWDGF_Msk (0x01UL << GTZC_TZIC_FCR1_CWWDGF_Pos) +#define GTZC_TZIC_FCR1_CWWDGF GTZC_TZIC_FCR1_CWWDGF_Msk /*!< clear the illegal access flag for WWDG */ +#define GTZC_TZIC_FCR1_CIWDGF_Pos (7U) +#define GTZC_TZIC_FCR1_CIWDGF_Msk (0x01UL << GTZC_TZIC_FCR1_CIWDGF_Pos) +#define GTZC_TZIC_FCR1_CIWDGF GTZC_TZIC_FCR1_CIWDGF_Msk /*!< clear the illegal access flag for IWDG */ +#define GTZC_TZIC_FCR1_CUSART2F_Pos (9U) +#define GTZC_TZIC_FCR1_CUSART2F_Msk (0x01UL << GTZC_TZIC_FCR1_CUSART2F_Pos) +#define GTZC_TZIC_FCR1_CUSART2F GTZC_TZIC_FCR1_CUSART2F_Msk /*!< clear the illegal access flag for USART2 */ +#define GTZC_TZIC_FCR1_CI2C1F_Pos (13U) +#define GTZC_TZIC_FCR1_CI2C1F_Msk (0x01UL << GTZC_TZIC_FCR1_CI2C1F_Pos) +#define GTZC_TZIC_FCR1_CI2C1F GTZC_TZIC_FCR1_CI2C1F_Msk /*!< clear the illegal access flag for I2C1 */ +#define GTZC_TZIC_FCR1_CLPTIM2F_Pos (17U) +#define GTZC_TZIC_FCR1_CLPTIM2F_Msk (0x01UL << GTZC_TZIC_FCR1_CLPTIM2F_Pos) +#define GTZC_TZIC_FCR1_CLPTIM2F GTZC_TZIC_FCR1_CLPTIM2F_Msk /*!< clear the illegal access flag for LPTIM2 */ + +/****************** Bits definition for GTZC_TZIC_FCR2 register ****************/ +#define GTZC_TZIC_FCR2_CTIM1F_Pos (0U) +#define GTZC_TZIC_FCR2_CTIM1F_Msk (0x01UL << GTZC_TZIC_FCR2_CTIM1F_Pos) +#define GTZC_TZIC_FCR2_CTIM1F GTZC_TZIC_FCR2_CTIM1F_Msk /*!< clear the illegal access flag for TIM1 */ +#define GTZC_TZIC_FCR2_CSPI1F_Pos (1U) +#define GTZC_TZIC_FCR2_CSPI1F_Msk (0x01UL << GTZC_TZIC_FCR2_CSPI1F_Pos) +#define GTZC_TZIC_FCR2_CSPI1F GTZC_TZIC_FCR2_CSPI1F_Msk /*!< clear the illegal access flag for SPI1 */ +#define GTZC_TZIC_FCR2_CUSART1F_Pos (3U) +#define GTZC_TZIC_FCR2_CUSART1F_Msk (0x01UL << GTZC_TZIC_FCR2_CUSART1F_Pos) +#define GTZC_TZIC_FCR2_CUSART1F GTZC_TZIC_FCR2_CUSART1F_Msk /*!< clear the illegal access flag for USART1 */ +#define GTZC_TZIC_FCR2_CTIM16F_Pos (5U) +#define GTZC_TZIC_FCR2_CTIM16F_Msk (0x01UL << GTZC_TZIC_FCR2_CTIM16F_Pos) +#define GTZC_TZIC_FCR2_CTIM16F GTZC_TZIC_FCR2_CTIM16F_Msk /*!< clear the illegal access flag for TIM16 */ +#define GTZC_TZIC_FCR2_CTIM17F_Pos (6U) +#define GTZC_TZIC_FCR2_CTIM17F_Msk (0x01UL << GTZC_TZIC_FCR2_CTIM17F_Pos) +#define GTZC_TZIC_FCR2_CTIM17F GTZC_TZIC_FCR2_CTIM17F_Msk /*!< clear the illegal access flag for TIM17 */ +#define GTZC_TZIC_FCR2_CSAI1F_Pos (7U) +#define GTZC_TZIC_FCR2_CSAI1F_Msk (0x01UL << GTZC_TZIC_FCR2_CSAI1F_Pos) +#define GTZC_TZIC_FCR2_CSAI1F GTZC_TZIC_FCR2_CSAI1F_Msk /*!< clear the illegal access flag for SAI1 */ +#define GTZC_TZIC_FCR2_CSPI3F_Pos (16U) +#define GTZC_TZIC_FCR2_CSPI3F_Msk (0x01UL << GTZC_TZIC_FCR2_CSPI3F_Pos) +#define GTZC_TZIC_FCR2_CSPI3F GTZC_TZIC_FCR2_CSPI3F_Msk /*!< clear the illegal access flag for SPI3 */ +#define GTZC_TZIC_FCR2_CLPUART1F_Pos (17U) +#define GTZC_TZIC_FCR2_CLPUART1F_Msk (0x01UL << GTZC_TZIC_FCR2_CLPUART1F_Pos) +#define GTZC_TZIC_FCR2_CLPUART1F GTZC_TZIC_FCR2_CLPUART1F_Msk /*!< clear the illegal access flag for LPUART1 */ +#define GTZC_TZIC_FCR2_CI2C3F_Pos (18U) +#define GTZC_TZIC_FCR2_CI2C3F_Msk (0x01UL << GTZC_TZIC_FCR2_CI2C3F_Pos) +#define GTZC_TZIC_FCR2_CI2C3F GTZC_TZIC_FCR2_CI2C3F_Msk /*!< clear the illegal access flag for I2C3 */ +#define GTZC_TZIC_FCR2_CLPTIM1F_Pos (19U) +#define GTZC_TZIC_FCR2_CLPTIM1F_Msk (0x01UL << GTZC_TZIC_FCR2_CLPTIM1F_Pos) +#define GTZC_TZIC_FCR2_CLPTIM1F GTZC_TZIC_FCR2_CLPTIM1F_Msk /*!< clear the illegal access flag for LPTIM1 */ +#define GTZC_TZIC_FCR2_CCOMPF_Pos (23U) +#define GTZC_TZIC_FCR2_CCOMPF_Msk (0x01UL << GTZC_TZIC_FCR2_CCOMPF_Pos) +#define GTZC_TZIC_FCR2_CCOMPF GTZC_TZIC_FCR2_CCOMPF_Msk /*!< clear the illegal access flag for COMP */ +#define GTZC_TZIC_FCR2_CADC4F_Pos (24U) +#define GTZC_TZIC_FCR2_CADC4F_Msk (0x01UL << GTZC_TZIC_FCR2_CADC4F_Pos) +#define GTZC_TZIC_FCR2_CADC4F GTZC_TZIC_FCR2_CADC4F_Msk /*!< clear the illegal access flag for ADC4 */ + +/****************** Bits definition for GTZC_TZIC_FCR3 register ****************/ +#define GTZC_TZIC_FCR3_CCRCF_Pos (3U) +#define GTZC_TZIC_FCR3_CCRCF_Msk (0x01UL << GTZC_TZIC_FCR3_CCRCF_Pos) +#define GTZC_TZIC_FCR3_CCRCF GTZC_TZIC_FCR3_CCRCF_Msk /*!< clear the illegal access flag enable for CRC */ +#define GTZC_TZIC_FCR3_CTSCF_Pos (4U) +#define GTZC_TZIC_FCR3_CTSCF_Msk (0x01UL << GTZC_TZIC_FCR3_CTSCF_Pos) +#define GTZC_TZIC_FCR3_CTSCF GTZC_TZIC_FCR3_CTSCF_Msk /*!< clear the illegal access flag enable for TSC */ +#define GTZC_TZIC_FCR3_CICACHE_REGF_Pos (6U) +#define GTZC_TZIC_FCR3_CICACHE_REGF_Msk (0x01UL << GTZC_TZIC_FCR3_CICACHE_REGF_Pos) +#define GTZC_TZIC_FCR3_CICACHE_REGF GTZC_TZIC_FCR3_CICACHE_REGF_Msk /*!< clear the illegal access flag enable for ICACHE_REG */ +#define GTZC_TZIC_FCR3_CAESF_Pos (11U) +#define GTZC_TZIC_FCR3_CAESF_Msk (0x01UL << GTZC_TZIC_FCR3_CAESF_Pos) +#define GTZC_TZIC_FCR3_CAESF GTZC_TZIC_FCR3_CAESF_Msk /*!< clear the illegal access flag enable for AES */ +#define GTZC_TZIC_FCR3_CHASHF_Pos (12U) +#define GTZC_TZIC_FCR3_CHASHF_Msk (0x01UL << GTZC_TZIC_FCR3_CHASHF_Pos) +#define GTZC_TZIC_FCR3_CHASHF GTZC_TZIC_FCR3_CHASHF_Msk /*!< clear the illegal access flag enable for HASH */ +#define GTZC_TZIC_FCR3_CRNGF_Pos (13U) +#define GTZC_TZIC_FCR3_CRNGF_Msk (0x01UL << GTZC_TZIC_FCR3_CRNGF_Pos) +#define GTZC_TZIC_FCR3_CRNGF GTZC_TZIC_FCR3_CRNGF_Msk /*!< clear the illegal access flag enable for RNG */ +#define GTZC_TZIC_FCR3_CSAESF_Pos (14U) +#define GTZC_TZIC_FCR3_CSAESF_Msk (0x01UL << GTZC_TZIC_FCR3_CSAESF_Pos) +#define GTZC_TZIC_FCR3_CSAESF GTZC_TZIC_FCR3_CSAESF_Msk /*!< clear the illegal access flag enable for SAES */ +#define GTZC_TZIC_FCR3_CHSEMF_Pos (15U) +#define GTZC_TZIC_FCR3_CHSEMF_Msk (0x01UL << GTZC_TZIC_FCR3_CHSEMF_Pos) +#define GTZC_TZIC_FCR3_CHSEMF GTZC_TZIC_FCR3_CHSEMF_Msk /*!< clear the illegal access flag enable for HSEM */ +#define GTZC_TZIC_FCR3_CPKAF_Pos (16U) +#define GTZC_TZIC_FCR3_CPKAF_Msk (0x01UL << GTZC_TZIC_FCR3_CPKAF_Pos) +#define GTZC_TZIC_FCR3_CPKAF GTZC_TZIC_FCR3_CPKAF_Msk /*!< clear the illegal access flag enable for PKA */ +#define GTZC_TZIC_FCR3_CRAMCFGF_Pos (22U) +#define GTZC_TZIC_FCR3_CRAMCFGF_Msk (0x01UL << GTZC_TZIC_FCR3_CRAMCFGF_Pos) +#define GTZC_TZIC_FCR3_CRAMCFGF GTZC_TZIC_FCR3_CRAMCFGF_Msk /*!< clear the illegal access flag enable for RAMCFG */ +#define GTZC_TZIC_FCR3_CRADIOF_Pos (23U) +#define GTZC_TZIC_FCR3_CRADIOF_Msk (0x01UL << GTZC_TZIC_FCR3_CRADIOF_Pos) +#define GTZC_TZIC_FCR3_CRADIOF GTZC_TZIC_FCR3_CRADIOF_Msk /*!< clear the illegal access flag enable for 2.4 GHz RADIO */ +#define GTZC_TZIC_FCR3_CPTACONVF_Pos (24U) +#define GTZC_TZIC_FCR3_CPTACONVF_Msk (0x01UL << GTZC_TZIC_FCR3_CPTACONVF_Pos) +#define GTZC_TZIC_FCR3_CPTACONVF GTZC_TZIC_FCR3_CPTACONVF_Msk /*!< clear the illegal access flag enable for PTACONV */ + +/****************** Bits definition for GTZC_TZIC_FCR4 register ****************/ +#define GTZC_TZIC_FCR4_CGPDMA1F_Pos (0U) +#define GTZC_TZIC_FCR4_CGPDMA1F_Msk (0x01UL << GTZC_TZIC_FCR4_CGPDMA1F_Pos) +#define GTZC_TZIC_FCR4_CGPDMA1F GTZC_TZIC_FCR4_CGPDMA1F_Msk /*!< clear the illegal access flag enable for GPDMA1 */ +#define GTZC_TZIC_FCR4_CFLASHF_Pos (1U) +#define GTZC_TZIC_FCR4_CFLASHF_Msk (0x01UL << GTZC_TZIC_FCR4_CFLASHF_Pos) +#define GTZC_TZIC_FCR4_CFLASHF GTZC_TZIC_FCR4_CFLASHF_Msk /*!< clear the illegal access flag enable for FLASH memory */ +#define GTZC_TZIC_FCR4_CFLASH_REGF_Pos (2U) +#define GTZC_TZIC_FCR4_CFLASH_REGF_Msk (0x01UL << GTZC_TZIC_FCR4_CFLASH_REGF_Pos) +#define GTZC_TZIC_FCR4_CFLASH_REGF GTZC_TZIC_FCR4_CFLASH_REGF_Msk /*!< clear the illegal access flag enable for FLASH interface */ +#define GTZC_TZIC_FCR4_CSYSCFGF_Pos (7U) +#define GTZC_TZIC_FCR4_CSYSCFGF_Msk (0x01UL << GTZC_TZIC_FCR4_CSYSCFGF_Pos) +#define GTZC_TZIC_FCR4_CSYSCFGF GTZC_TZIC_FCR4_CSYSCFGF_Msk /*!< clear the illegal access flag enable for SYSCFG interface */ +#define GTZC_TZIC_FCR4_CRTCF_Pos (8U) +#define GTZC_TZIC_FCR4_CRTCF_Msk (0x01UL << GTZC_TZIC_FCR4_CRTCF_Pos) +#define GTZC_TZIC_FCR4_CRTCF GTZC_TZIC_FCR4_CRTCF_Msk /*!< clear the illegal access flag enable for RTC interface */ +#define GTZC_TZIC_FCR4_CTAMPF_Pos (9U) +#define GTZC_TZIC_FCR4_CTAMPF_Msk (0x01UL << GTZC_TZIC_FCR4_CTAMPF_Pos) +#define GTZC_TZIC_FCR4_CTAMPF GTZC_TZIC_FCR4_CTAMPF_Msk /*!< clear the illegal access flag enable for TAMP interface */ +#define GTZC_TZIC_FCR4_CPWRF_Pos (10U) +#define GTZC_TZIC_FCR4_CPWRF_Msk (0x01UL << GTZC_TZIC_FCR4_CPWRF_Pos) +#define GTZC_TZIC_FCR4_CPWRF GTZC_TZIC_FCR4_CPWRF_Msk /*!< clear the illegal access flag enable for PWR interface */ +#define GTZC_TZIC_FCR4_CRCCF_Pos (11U) +#define GTZC_TZIC_FCR4_CRCCF_Msk (0x01UL << GTZC_TZIC_FCR4_CRCCF_Pos) +#define GTZC_TZIC_FCR4_CRCCF GTZC_TZIC_FCR4_CRCCF_Msk /*!< clear the illegal access flag enable for RCC interface */ +#define GTZC_TZIC_FCR4_CEXTIF_Pos (13U) +#define GTZC_TZIC_FCR4_CEXTIF_Msk (0x01UL << GTZC_TZIC_FCR4_CEXTIF_Pos) +#define GTZC_TZIC_FCR4_CEXTIF GTZC_TZIC_FCR4_CEXTIF_Msk /*!< clear the illegal access flag enable for EXTI interface */ +#define GTZC_TZIC_FCR4_CTZSCF_Pos (14U) +#define GTZC_TZIC_FCR4_CTZSCF_Msk (0x01UL << GTZC_TZIC_FCR4_CTZSCF_Pos) +#define GTZC_TZIC_FCR4_CTZSCF GTZC_TZIC_FCR4_CTZSCF_Msk /*!< clear the illegal access flag enable for GTZC TZSC */ +#define GTZC_TZIC_FCR4_CTZICF_Pos (15U) +#define GTZC_TZIC_FCR4_CTZICF_Msk (0x01UL << GTZC_TZIC_FCR4_CTZICF_Pos) +#define GTZC_TZIC_FCR4_CTZICF GTZC_TZIC_FCR4_CTZICF_Msk /*!< clear the illegal access flag enable for GTZC TZIC */ +#define GTZC_TZIC_FCR4_CSRAM1F_Pos (22U) +#define GTZC_TZIC_FCR4_CSRAM1F_Msk (0x01UL << GTZC_TZIC_FCR4_CSRAM1F_Pos) +#define GTZC_TZIC_FCR4_CSRAM1F GTZC_TZIC_FCR4_CSRAM1F_Msk /*!< clear the illegal access flag enable for SRAM1 memory */ +#define GTZC_TZIC_FCR4_CMPCBB1F_Pos (23U) +#define GTZC_TZIC_FCR4_CMPCBB1F_Msk (0x01UL << GTZC_TZIC_FCR4_CMPCBB1F_Pos) +#define GTZC_TZIC_FCR4_CMPCBB1F GTZC_TZIC_FCR4_CMPCBB1F_Msk /*!< clear the illegal access flag enable for MPCBB1 */ +#define GTZC_TZIC_FCR4_CSRAM2F_Pos (24U) +#define GTZC_TZIC_FCR4_CSRAM2F_Msk (0x01UL << GTZC_TZIC_FCR4_CSRAM2F_Pos) +#define GTZC_TZIC_FCR4_CSRAM2F GTZC_TZIC_FCR4_CSRAM2F_Msk /*!< clear the illegal access flag enable for SRAM2 memory */ +#define GTZC_TZIC_FCR4_CMPCBB2F_Pos (25U) +#define GTZC_TZIC_FCR4_CMPCBB2F_Msk (0x01UL << GTZC_TZIC_FCR4_CMPCBB2F_Pos) +#define GTZC_TZIC_FCR4_CMPCBB2F GTZC_TZIC_FCR4_CMPCBB2F_Msk /*!< clear the illegal access flag enable for MPCBB2 */ +#define GTZC_TZIC_FCR4_CSRAM6F_Pos (30U) +#define GTZC_TZIC_FCR4_CSRAM6F_Msk (0x01UL << GTZC_TZIC_FCR4_CSRAM6F_Pos) +#define GTZC_TZIC_FCR4_CSRAM6F GTZC_TZIC_FCR4_CSRAM6F_Msk /*!< clear the illegal access flag enable for 2.4GHz TXRX SRAM memory */ +#define GTZC_TZIC_FCR4_CMPCBB6F_Pos (31U) +#define GTZC_TZIC_FCR4_CMPCBB6F_Msk (0x01UL << GTZC_TZIC_FCR4_CMPCBB6F_Pos) +#define GTZC_TZIC_FCR4_CMPCBB6F GTZC_TZIC_FCR4_CMPCBB6F_Msk /*!< clear the illegal access flag enable for MPCBB6 */ + +/******************* Bits definition for GTZC_MPCBB_CR register *****************/ +#define GTZC_MPCBB_CR_GLOCK_Pos (0U) +#define GTZC_MPCBB_CR_GLOCK_Msk (0x01UL << GTZC_MPCBB_CR_GLOCK_Pos) /*!< 0x00000001 */ +#define GTZC_MPCBB_CR_GLOCK GTZC_MPCBB_CR_GLOCK_Msk /*!< lock the control register of the MPCBB until next reset */ +#define GTZC_MPCBB_CR_INVSECSTATE_Pos (30U) +#define GTZC_MPCBB_CR_INVSECSTATE_Msk (0x01UL << GTZC_MPCBB_CR_INVSECSTATE_Pos) /*!< 0x40000000 */ +#define GTZC_MPCBB_CR_INVSECSTATE GTZC_MPCBB_CR_INVSECSTATE_Msk /*!< SRAM clocks security state */ +#define GTZC_MPCBB_CR_SRWILADIS_Pos (31U) +#define GTZC_MPCBB_CR_SRWILADIS_Msk (0x01UL << GTZC_MPCBB_CR_SRWILADIS_Pos) /*!< 0x80000000 */ +#define GTZC_MPCBB_CR_SRWILADIS GTZC_MPCBB_CR_SRWILADIS_Msk /*!< secure read/write illegal access disable */ + +/******************* Bits definition for GTZC_MPCBB_CFGLOCK register ************/ +#define GTZC_MPCBB_CFGLOCK_SPLCK0_Pos (0U) +#define GTZC_MPCBB_CFGLOCK_SPLCK0_Msk (0x01UL << GTZC_MPCBB_CFGLOCK_SPLCK0_Pos) /*!< 0x00000001 */ +#define GTZC_MPCBB_CFGLOCK_SPLCK0 GTZC_MPCBB_CFGLOCK_SPLCK0_Msk /*!< Security/privilege configuration lock super-block 0 */ +#define GTZC_MPCBB_CFGLOCK_SPLCK1_Pos (1U) +#define GTZC_MPCBB_CFGLOCK_SPLCK1_Msk (0x01UL << GTZC_MPCBB_CFGLOCK_SPLCK1_Pos) /*!< 0x00000002 */ +#define GTZC_MPCBB_CFGLOCK_SPLCK1 GTZC_MPCBB_CFGLOCK_SPLCK1_Msk /*!< Security/privilege configuration lock super-block 1 */ +#define GTZC_MPCBB_CFGLOCK_SPLCK2_Pos (2U) +#define GTZC_MPCBB_CFGLOCK_SPLCK2_Msk (0x01UL << GTZC_MPCBB_CFGLOCK_SPLCK2_Pos) /*!< 0x00000004 */ +#define GTZC_MPCBB_CFGLOCK_SPLCK2 GTZC_MPCBB_CFGLOCK_SPLCK2_Msk /*!< Security/privilege configuration lock super-block 2 */ +#define GTZC_MPCBB_CFGLOCK_SPLCK3_Pos (3U) +#define GTZC_MPCBB_CFGLOCK_SPLCK3_Msk (0x01UL << GTZC_MPCBB_CFGLOCK_SPLCK3_Pos) /*!< 0x00000008 */ +#define GTZC_MPCBB_CFGLOCK_SPLCK3 GTZC_MPCBB_CFGLOCK_SPLCK3_Msk /*!< Security/privilege configuration lock super-block 3 */ + +/******************* Bits definition for GTZC_MPCBB_SECCFGR0 register ************/ +#define GTZC_MPCBB_SECCFGR0_SEC0_Pos (0U) +#define GTZC_MPCBB_SECCFGR0_SEC0_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC0_Pos) /*!< 0x00000001 */ +#define GTZC_MPCBB_SECCFGR0_SEC0 GTZC_MPCBB_SECCFGR0_SEC0_Msk /*!< Security configuration for block 0 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC1_Pos (1U) +#define GTZC_MPCBB_SECCFGR0_SEC1_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC1_Pos) /*!< 0x00000002 */ +#define GTZC_MPCBB_SECCFGR0_SEC1 GTZC_MPCBB_SECCFGR0_SEC1_Msk /*!< Security configuration for block 1 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC2_Pos (2U) +#define GTZC_MPCBB_SECCFGR0_SEC2_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC2_Pos) /*!< 0x00000004 */ +#define GTZC_MPCBB_SECCFGR0_SEC2 GTZC_MPCBB_SECCFGR0_SEC2_Msk /*!< Security configuration for block 2 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC3_Pos (3U) +#define GTZC_MPCBB_SECCFGR0_SEC3_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC3_Pos) /*!< 0x00000008 */ +#define GTZC_MPCBB_SECCFGR0_SEC3 GTZC_MPCBB_SECCFGR0_SEC3_Msk /*!< Security configuration for block 3 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC4_Pos (4U) +#define GTZC_MPCBB_SECCFGR0_SEC4_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC4_Pos) /*!< 0x00000010 */ +#define GTZC_MPCBB_SECCFGR0_SEC4 GTZC_MPCBB_SECCFGR0_SEC4_Msk /*!< Security configuration for block 4 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC5_Pos (5U) +#define GTZC_MPCBB_SECCFGR0_SEC5_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC5_Pos) /*!< 0x00000020 */ +#define GTZC_MPCBB_SECCFGR0_SEC5 GTZC_MPCBB_SECCFGR0_SEC5_Msk /*!< Security configuration for block 5 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC6_Pos (6U) +#define GTZC_MPCBB_SECCFGR0_SEC6_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC6_Pos) /*!< 0x00000040 */ +#define GTZC_MPCBB_SECCFGR0_SEC6 GTZC_MPCBB_SECCFGR0_SEC6_Msk /*!< Security configuration for block 6 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC7_Pos (7U) +#define GTZC_MPCBB_SECCFGR0_SEC7_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC7_Pos) /*!< 0x00000080 */ +#define GTZC_MPCBB_SECCFGR0_SEC7 GTZC_MPCBB_SECCFGR0_SEC7_Msk /*!< Security configuration for block 7 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC8_Pos (8U) +#define GTZC_MPCBB_SECCFGR0_SEC8_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC8_Pos) /*!< 0x00000100 */ +#define GTZC_MPCBB_SECCFGR0_SEC8 GTZC_MPCBB_SECCFGR0_SEC8_Msk /*!< Security configuration for block 8 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC9_Pos (9U) +#define GTZC_MPCBB_SECCFGR0_SEC9_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC9_Pos) /*!< 0x00000200 */ +#define GTZC_MPCBB_SECCFGR0_SEC9 GTZC_MPCBB_SECCFGR0_SEC9_Msk /*!< Security configuration for block 9 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC10_Pos (10U) +#define GTZC_MPCBB_SECCFGR0_SEC10_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC10_Pos) /*!< 0x00000400 */ +#define GTZC_MPCBB_SECCFGR0_SEC10 GTZC_MPCBB_SECCFGR0_SEC10_Msk /*!< Security configuration for block 10 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC11_Pos (11U) +#define GTZC_MPCBB_SECCFGR0_SEC11_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC11_Pos) /*!< 0x00000800 */ +#define GTZC_MPCBB_SECCFGR0_SEC11 GTZC_MPCBB_SECCFGR0_SEC11_Msk /*!< Security configuration for block 11 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC12_Pos (12U) +#define GTZC_MPCBB_SECCFGR0_SEC12_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC12_Pos) /*!< 0x00001000 */ +#define GTZC_MPCBB_SECCFGR0_SEC12 GTZC_MPCBB_SECCFGR0_SEC12_Msk /*!< Security configuration for block 12 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC13_Pos (13U) +#define GTZC_MPCBB_SECCFGR0_SEC13_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC13_Pos) /*!< 0x00002000 */ +#define GTZC_MPCBB_SECCFGR0_SEC13 GTZC_MPCBB_SECCFGR0_SEC13_Msk /*!< Security configuration for block 13 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC14_Pos (14U) +#define GTZC_MPCBB_SECCFGR0_SEC14_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC14_Pos) /*!< 0x00004000 */ +#define GTZC_MPCBB_SECCFGR0_SEC14 GTZC_MPCBB_SECCFGR0_SEC14_Msk /*!< Security configuration for block 14 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC15_Pos (15U) +#define GTZC_MPCBB_SECCFGR0_SEC15_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC15_Pos) /*!< 0x00008000 */ +#define GTZC_MPCBB_SECCFGR0_SEC15 GTZC_MPCBB_SECCFGR0_SEC15_Msk /*!< Security configuration for block 15 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC16_Pos (16U) +#define GTZC_MPCBB_SECCFGR0_SEC16_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC16_Pos) /*!< 0x00010000 */ +#define GTZC_MPCBB_SECCFGR0_SEC16 GTZC_MPCBB_SECCFGR0_SEC16_Msk /*!< Security configuration for block 16 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC17_Pos (17U) +#define GTZC_MPCBB_SECCFGR0_SEC17_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC17_Pos) /*!< 0x00020000 */ +#define GTZC_MPCBB_SECCFGR0_SEC17 GTZC_MPCBB_SECCFGR0_SEC17_Msk /*!< Security configuration for block 17 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC18_Pos (18U) +#define GTZC_MPCBB_SECCFGR0_SEC18_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC18_Pos) /*!< 0x00040000 */ +#define GTZC_MPCBB_SECCFGR0_SEC18 GTZC_MPCBB_SECCFGR0_SEC18_Msk /*!< Security configuration for block 18 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC19_Pos (19U) +#define GTZC_MPCBB_SECCFGR0_SEC19_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC19_Pos) /*!< 0x00080000 */ +#define GTZC_MPCBB_SECCFGR0_SEC19 GTZC_MPCBB_SECCFGR0_SEC19_Msk /*!< Security configuration for block 19 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC20_Pos (20U) +#define GTZC_MPCBB_SECCFGR0_SEC20_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC20_Pos) /*!< 0x00100000 */ +#define GTZC_MPCBB_SECCFGR0_SEC20 GTZC_MPCBB_SECCFGR0_SEC20_Msk /*!< Security configuration for block 20 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC21_Pos (21U) +#define GTZC_MPCBB_SECCFGR0_SEC21_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC21_Pos) /*!< 0x00200000 */ +#define GTZC_MPCBB_SECCFGR0_SEC21 GTZC_MPCBB_SECCFGR0_SEC21_Msk /*!< Security configuration for block 21 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC22_Pos (22U) +#define GTZC_MPCBB_SECCFGR0_SEC22_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC22_Pos) /*!< 0x00400000 */ +#define GTZC_MPCBB_SECCFGR0_SEC22 GTZC_MPCBB_SECCFGR0_SEC22_Msk /*!< Security configuration for block 22 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC23_Pos (23U) +#define GTZC_MPCBB_SECCFGR0_SEC23_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC23_Pos) /*!< 0x00800000 */ +#define GTZC_MPCBB_SECCFGR0_SEC23 GTZC_MPCBB_SECCFGR0_SEC23_Msk /*!< Security configuration for block 23 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC24_Pos (24U) +#define GTZC_MPCBB_SECCFGR0_SEC24_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC24_Pos) /*!< 0x01000000 */ +#define GTZC_MPCBB_SECCFGR0_SEC24 GTZC_MPCBB_SECCFGR0_SEC24_Msk /*!< Security configuration for block 24 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC25_Pos (25U) +#define GTZC_MPCBB_SECCFGR0_SEC25_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC25_Pos) /*!< 0x02000000 */ +#define GTZC_MPCBB_SECCFGR0_SEC25 GTZC_MPCBB_SECCFGR0_SEC25_Msk /*!< Security configuration for block 25 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC26_Pos (26U) +#define GTZC_MPCBB_SECCFGR0_SEC26_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC26_Pos) /*!< 0x04000000 */ +#define GTZC_MPCBB_SECCFGR0_SEC26 GTZC_MPCBB_SECCFGR0_SEC26_Msk /*!< Security configuration for block 26 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC27_Pos (27U) +#define GTZC_MPCBB_SECCFGR0_SEC27_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC27_Pos) /*!< 0x08000000 */ +#define GTZC_MPCBB_SECCFGR0_SEC27 GTZC_MPCBB_SECCFGR0_SEC27_Msk /*!< Security configuration for block 27 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC28_Pos (28U) +#define GTZC_MPCBB_SECCFGR0_SEC28_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC28_Pos) /*!< 0x10000000 */ +#define GTZC_MPCBB_SECCFGR0_SEC28 GTZC_MPCBB_SECCFGR0_SEC28_Msk /*!< Security configuration for block 28 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC29_Pos (29U) +#define GTZC_MPCBB_SECCFGR0_SEC29_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC29_Pos) /*!< 0x20000000 */ +#define GTZC_MPCBB_SECCFGR0_SEC29 GTZC_MPCBB_SECCFGR0_SEC29_Msk /*!< Security configuration for block 29 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC30_Pos (30U) +#define GTZC_MPCBB_SECCFGR0_SEC30_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC30_Pos) /*!< 0x40000000 */ +#define GTZC_MPCBB_SECCFGR0_SEC30 GTZC_MPCBB_SECCFGR0_SEC31_Msk /*!< Security configuration for block 30 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC31_Pos (31U) +#define GTZC_MPCBB_SECCFGR0_SEC31_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC31_Pos) /*!< 0x80000000 */ +#define GTZC_MPCBB_SECCFGR0_SEC31 GTZC_MPCBB_SECCFGR0_SEC31_Msk /*!< Security configuration for block 31 in super block 0 */ + +/******************* Bits definition for GTZC_MPCBB_SECCFGR1 register ************/ +#define GTZC_MPCBB_SECCFGR1_SEC0_Pos (0U) +#define GTZC_MPCBB_SECCFGR1_SEC0_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC0_Pos) /*!< 0x00000001 */ +#define GTZC_MPCBB_SECCFGR1_SEC0 GTZC_MPCBB_SECCFGR1_SEC0_Msk /*!< Security configuration for block 0 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC1_Pos (1U) +#define GTZC_MPCBB_SECCFGR1_SEC1_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC1_Pos) /*!< 0x00000002 */ +#define GTZC_MPCBB_SECCFGR1_SEC1 GTZC_MPCBB_SECCFGR1_SEC1_Msk /*!< Security configuration for block 1 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC2_Pos (2U) +#define GTZC_MPCBB_SECCFGR1_SEC2_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC2_Pos) /*!< 0x00000004 */ +#define GTZC_MPCBB_SECCFGR1_SEC2 GTZC_MPCBB_SECCFGR1_SEC2_Msk /*!< Security configuration for block 2 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC3_Pos (3U) +#define GTZC_MPCBB_SECCFGR1_SEC3_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC3_Pos) /*!< 0x00000008 */ +#define GTZC_MPCBB_SECCFGR1_SEC3 GTZC_MPCBB_SECCFGR1_SEC3_Msk /*!< Security configuration for block 3 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC4_Pos (4U) +#define GTZC_MPCBB_SECCFGR1_SEC4_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC4_Pos) /*!< 0x00000010 */ +#define GTZC_MPCBB_SECCFGR1_SEC4 GTZC_MPCBB_SECCFGR1_SEC4_Msk /*!< Security configuration for block 4 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC5_Pos (5U) +#define GTZC_MPCBB_SECCFGR1_SEC5_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC5_Pos) /*!< 0x00000020 */ +#define GTZC_MPCBB_SECCFGR1_SEC5 GTZC_MPCBB_SECCFGR1_SEC5_Msk /*!< Security configuration for block 5 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC6_Pos (6U) +#define GTZC_MPCBB_SECCFGR1_SEC6_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC6_Pos) /*!< 0x00000040 */ +#define GTZC_MPCBB_SECCFGR1_SEC6 GTZC_MPCBB_SECCFGR1_SEC6_Msk /*!< Security configuration for block 6 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC7_Pos (7U) +#define GTZC_MPCBB_SECCFGR1_SEC7_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC7_Pos) /*!< 0x00000080 */ +#define GTZC_MPCBB_SECCFGR1_SEC7 GTZC_MPCBB_SECCFGR1_SEC7_Msk /*!< Security configuration for block 7 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC8_Pos (8U) +#define GTZC_MPCBB_SECCFGR1_SEC8_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC8_Pos) /*!< 0x00000100 */ +#define GTZC_MPCBB_SECCFGR1_SEC8 GTZC_MPCBB_SECCFGR1_SEC8_Msk /*!< Security configuration for block 8 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC9_Pos (9U) +#define GTZC_MPCBB_SECCFGR1_SEC9_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC9_Pos) /*!< 0x00000200 */ +#define GTZC_MPCBB_SECCFGR1_SEC9 GTZC_MPCBB_SECCFGR1_SEC9_Msk /*!< Security configuration for block 9 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC10_Pos (10U) +#define GTZC_MPCBB_SECCFGR1_SEC10_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC10_Pos) /*!< 0x00000400 */ +#define GTZC_MPCBB_SECCFGR1_SEC10 GTZC_MPCBB_SECCFGR1_SEC10_Msk /*!< Security configuration for block 10 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC11_Pos (11U) +#define GTZC_MPCBB_SECCFGR1_SEC11_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC11_Pos) /*!< 0x00000800 */ +#define GTZC_MPCBB_SECCFGR1_SEC11 GTZC_MPCBB_SECCFGR1_SEC11_Msk /*!< Security configuration for block 11 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC12_Pos (12U) +#define GTZC_MPCBB_SECCFGR1_SEC12_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC12_Pos) /*!< 0x00001000 */ +#define GTZC_MPCBB_SECCFGR1_SEC12 GTZC_MPCBB_SECCFGR1_SEC12_Msk /*!< Security configuration for block 12 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC13_Pos (13U) +#define GTZC_MPCBB_SECCFGR1_SEC13_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC13_Pos) /*!< 0x00002000 */ +#define GTZC_MPCBB_SECCFGR1_SEC13 GTZC_MPCBB_SECCFGR1_SEC13_Msk /*!< Security configuration for block 13 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC14_Pos (14U) +#define GTZC_MPCBB_SECCFGR1_SEC14_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC14_Pos) /*!< 0x00004000 */ +#define GTZC_MPCBB_SECCFGR1_SEC14 GTZC_MPCBB_SECCFGR1_SEC14_Msk /*!< Security configuration for block 14 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC15_Pos (15U) +#define GTZC_MPCBB_SECCFGR1_SEC15_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC15_Pos) /*!< 0x00008000 */ +#define GTZC_MPCBB_SECCFGR1_SEC15 GTZC_MPCBB_SECCFGR1_SEC15_Msk /*!< Security configuration for block 15 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC16_Pos (16U) +#define GTZC_MPCBB_SECCFGR1_SEC16_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC16_Pos) /*!< 0x00010000 */ +#define GTZC_MPCBB_SECCFGR1_SEC16 GTZC_MPCBB_SECCFGR1_SEC16_Msk /*!< Security configuration for block 16 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC17_Pos (17U) +#define GTZC_MPCBB_SECCFGR1_SEC17_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC17_Pos) /*!< 0x00020000 */ +#define GTZC_MPCBB_SECCFGR1_SEC17 GTZC_MPCBB_SECCFGR1_SEC17_Msk /*!< Security configuration for block 17 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC18_Pos (18U) +#define GTZC_MPCBB_SECCFGR1_SEC18_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC18_Pos) /*!< 0x00040000 */ +#define GTZC_MPCBB_SECCFGR1_SEC18 GTZC_MPCBB_SECCFGR1_SEC18_Msk /*!< Security configuration for block 18 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC19_Pos (19U) +#define GTZC_MPCBB_SECCFGR1_SEC19_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC19_Pos) /*!< 0x00080000 */ +#define GTZC_MPCBB_SECCFGR1_SEC19 GTZC_MPCBB_SECCFGR1_SEC19_Msk /*!< Security configuration for block 19 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC20_Pos (20U) +#define GTZC_MPCBB_SECCFGR1_SEC20_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC20_Pos) /*!< 0x00100000 */ +#define GTZC_MPCBB_SECCFGR1_SEC20 GTZC_MPCBB_SECCFGR1_SEC20_Msk /*!< Security configuration for block 20 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC21_Pos (21U) +#define GTZC_MPCBB_SECCFGR1_SEC21_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC21_Pos) /*!< 0x00200000 */ +#define GTZC_MPCBB_SECCFGR1_SEC21 GTZC_MPCBB_SECCFGR1_SEC21_Msk /*!< Security configuration for block 21 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC22_Pos (22U) +#define GTZC_MPCBB_SECCFGR1_SEC22_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC22_Pos) /*!< 0x00400000 */ +#define GTZC_MPCBB_SECCFGR1_SEC22 GTZC_MPCBB_SECCFGR1_SEC22_Msk /*!< Security configuration for block 22 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC23_Pos (23U) +#define GTZC_MPCBB_SECCFGR1_SEC23_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC23_Pos) /*!< 0x00800000 */ +#define GTZC_MPCBB_SECCFGR1_SEC23 GTZC_MPCBB_SECCFGR1_SEC23_Msk /*!< Security configuration for block 23 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC24_Pos (24U) +#define GTZC_MPCBB_SECCFGR1_SEC24_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC24_Pos) /*!< 0x01000000 */ +#define GTZC_MPCBB_SECCFGR1_SEC24 GTZC_MPCBB_SECCFGR1_SEC24_Msk /*!< Security configuration for block 24 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC25_Pos (25U) +#define GTZC_MPCBB_SECCFGR1_SEC25_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC25_Pos) /*!< 0x02000000 */ +#define GTZC_MPCBB_SECCFGR1_SEC25 GTZC_MPCBB_SECCFGR1_SEC25_Msk /*!< Security configuration for block 25 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC26_Pos (26U) +#define GTZC_MPCBB_SECCFGR1_SEC26_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC26_Pos) /*!< 0x04000000 */ +#define GTZC_MPCBB_SECCFGR1_SEC26 GTZC_MPCBB_SECCFGR1_SEC26_Msk /*!< Security configuration for block 26 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC27_Pos (27U) +#define GTZC_MPCBB_SECCFGR1_SEC27_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC27_Pos) /*!< 0x08000000 */ +#define GTZC_MPCBB_SECCFGR1_SEC27 GTZC_MPCBB_SECCFGR1_SEC27_Msk /*!< Security configuration for block 27 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC28_Pos (28U) +#define GTZC_MPCBB_SECCFGR1_SEC28_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC28_Pos) /*!< 0x10000000 */ +#define GTZC_MPCBB_SECCFGR1_SEC28 GTZC_MPCBB_SECCFGR1_SEC28_Msk /*!< Security configuration for block 28 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC29_Pos (29U) +#define GTZC_MPCBB_SECCFGR1_SEC29_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC29_Pos) /*!< 0x20000000 */ +#define GTZC_MPCBB_SECCFGR1_SEC29 GTZC_MPCBB_SECCFGR1_SEC29_Msk /*!< Security configuration for block 29 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC30_Pos (30U) +#define GTZC_MPCBB_SECCFGR1_SEC30_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC30_Pos) /*!< 0x40000000 */ +#define GTZC_MPCBB_SECCFGR1_SEC30 GTZC_MPCBB_SECCFGR1_SEC31_Msk /*!< Security configuration for block 30 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC31_Pos (31U) +#define GTZC_MPCBB_SECCFGR1_SEC31_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC31_Pos) /*!< 0x80000000 */ +#define GTZC_MPCBB_SECCFGR1_SEC31 GTZC_MPCBB_SECCFGR1_SEC31_Msk /*!< Security configuration for block 31 in super block 1 */ + +/******************* Bits definition for GTZC_MPCBB_SECCFGR2 register ************/ +#define GTZC_MPCBB_SECCFGR2_SEC0_Pos (0U) +#define GTZC_MPCBB_SECCFGR2_SEC0_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC0_Pos) /*!< 0x00000001 */ +#define GTZC_MPCBB_SECCFGR2_SEC0 GTZC_MPCBB_SECCFGR2_SEC0_Msk /*!< Security configuration for block 0 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC1_Pos (1U) +#define GTZC_MPCBB_SECCFGR2_SEC1_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC1_Pos) /*!< 0x00000002 */ +#define GTZC_MPCBB_SECCFGR2_SEC1 GTZC_MPCBB_SECCFGR2_SEC1_Msk /*!< Security configuration for block 1 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC2_Pos (2U) +#define GTZC_MPCBB_SECCFGR2_SEC2_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC2_Pos) /*!< 0x00000004 */ +#define GTZC_MPCBB_SECCFGR2_SEC2 GTZC_MPCBB_SECCFGR2_SEC2_Msk /*!< Security configuration for block 2 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC3_Pos (3U) +#define GTZC_MPCBB_SECCFGR2_SEC3_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC3_Pos) /*!< 0x00000008 */ +#define GTZC_MPCBB_SECCFGR2_SEC3 GTZC_MPCBB_SECCFGR2_SEC3_Msk /*!< Security configuration for block 3 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC4_Pos (4U) +#define GTZC_MPCBB_SECCFGR2_SEC4_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC4_Pos) /*!< 0x00000010 */ +#define GTZC_MPCBB_SECCFGR2_SEC4 GTZC_MPCBB_SECCFGR2_SEC4_Msk /*!< Security configuration for block 4 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC5_Pos (5U) +#define GTZC_MPCBB_SECCFGR2_SEC5_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC5_Pos) /*!< 0x00000020 */ +#define GTZC_MPCBB_SECCFGR2_SEC5 GTZC_MPCBB_SECCFGR2_SEC5_Msk /*!< Security configuration for block 5 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC6_Pos (6U) +#define GTZC_MPCBB_SECCFGR2_SEC6_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC6_Pos) /*!< 0x00000040 */ +#define GTZC_MPCBB_SECCFGR2_SEC6 GTZC_MPCBB_SECCFGR2_SEC6_Msk /*!< Security configuration for block 6 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC7_Pos (7U) +#define GTZC_MPCBB_SECCFGR2_SEC7_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC7_Pos) /*!< 0x00000080 */ +#define GTZC_MPCBB_SECCFGR2_SEC7 GTZC_MPCBB_SECCFGR2_SEC7_Msk /*!< Security configuration for block 7 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC8_Pos (8U) +#define GTZC_MPCBB_SECCFGR2_SEC8_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC8_Pos) /*!< 0x00000100 */ +#define GTZC_MPCBB_SECCFGR2_SEC8 GTZC_MPCBB_SECCFGR2_SEC8_Msk /*!< Security configuration for block 8 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC9_Pos (9U) +#define GTZC_MPCBB_SECCFGR2_SEC9_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC9_Pos) /*!< 0x00000200 */ +#define GTZC_MPCBB_SECCFGR2_SEC9 GTZC_MPCBB_SECCFGR2_SEC9_Msk /*!< Security configuration for block 9 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC10_Pos (10U) +#define GTZC_MPCBB_SECCFGR2_SEC10_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC10_Pos) /*!< 0x00000400 */ +#define GTZC_MPCBB_SECCFGR2_SEC10 GTZC_MPCBB_SECCFGR2_SEC10_Msk /*!< Security configuration for block 10 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC11_Pos (11U) +#define GTZC_MPCBB_SECCFGR2_SEC11_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC11_Pos) /*!< 0x00000800 */ +#define GTZC_MPCBB_SECCFGR2_SEC11 GTZC_MPCBB_SECCFGR2_SEC11_Msk /*!< Security configuration for block 11 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC12_Pos (12U) +#define GTZC_MPCBB_SECCFGR2_SEC12_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC12_Pos) /*!< 0x00001000 */ +#define GTZC_MPCBB_SECCFGR2_SEC12 GTZC_MPCBB_SECCFGR2_SEC12_Msk /*!< Security configuration for block 12 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC13_Pos (13U) +#define GTZC_MPCBB_SECCFGR2_SEC13_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC13_Pos) /*!< 0x00002000 */ +#define GTZC_MPCBB_SECCFGR2_SEC13 GTZC_MPCBB_SECCFGR2_SEC13_Msk /*!< Security configuration for block 13 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC14_Pos (14U) +#define GTZC_MPCBB_SECCFGR2_SEC14_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC14_Pos) /*!< 0x00004000 */ +#define GTZC_MPCBB_SECCFGR2_SEC14 GTZC_MPCBB_SECCFGR2_SEC14_Msk /*!< Security configuration for block 14 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC15_Pos (15U) +#define GTZC_MPCBB_SECCFGR2_SEC15_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC15_Pos) /*!< 0x00008000 */ +#define GTZC_MPCBB_SECCFGR2_SEC15 GTZC_MPCBB_SECCFGR2_SEC15_Msk /*!< Security configuration for block 15 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC16_Pos (16U) +#define GTZC_MPCBB_SECCFGR2_SEC16_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC16_Pos) /*!< 0x00010000 */ +#define GTZC_MPCBB_SECCFGR2_SEC16 GTZC_MPCBB_SECCFGR2_SEC16_Msk /*!< Security configuration for block 16 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC17_Pos (17U) +#define GTZC_MPCBB_SECCFGR2_SEC17_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC17_Pos) /*!< 0x00020000 */ +#define GTZC_MPCBB_SECCFGR2_SEC17 GTZC_MPCBB_SECCFGR2_SEC17_Msk /*!< Security configuration for block 17 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC18_Pos (18U) +#define GTZC_MPCBB_SECCFGR2_SEC18_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC18_Pos) /*!< 0x00040000 */ +#define GTZC_MPCBB_SECCFGR2_SEC18 GTZC_MPCBB_SECCFGR2_SEC18_Msk /*!< Security configuration for block 18 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC19_Pos (19U) +#define GTZC_MPCBB_SECCFGR2_SEC19_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC19_Pos) /*!< 0x00080000 */ +#define GTZC_MPCBB_SECCFGR2_SEC19 GTZC_MPCBB_SECCFGR2_SEC19_Msk /*!< Security configuration for block 19 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC20_Pos (20U) +#define GTZC_MPCBB_SECCFGR2_SEC20_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC20_Pos) /*!< 0x00100000 */ +#define GTZC_MPCBB_SECCFGR2_SEC20 GTZC_MPCBB_SECCFGR2_SEC20_Msk /*!< Security configuration for block 20 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC21_Pos (21U) +#define GTZC_MPCBB_SECCFGR2_SEC21_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC21_Pos) /*!< 0x00200000 */ +#define GTZC_MPCBB_SECCFGR2_SEC21 GTZC_MPCBB_SECCFGR2_SEC21_Msk /*!< Security configuration for block 21 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC22_Pos (22U) +#define GTZC_MPCBB_SECCFGR2_SEC22_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC22_Pos) /*!< 0x00400000 */ +#define GTZC_MPCBB_SECCFGR2_SEC22 GTZC_MPCBB_SECCFGR2_SEC22_Msk /*!< Security configuration for block 22 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC23_Pos (23U) +#define GTZC_MPCBB_SECCFGR2_SEC23_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC23_Pos) /*!< 0x00800000 */ +#define GTZC_MPCBB_SECCFGR2_SEC23 GTZC_MPCBB_SECCFGR2_SEC23_Msk /*!< Security configuration for block 23 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC24_Pos (24U) +#define GTZC_MPCBB_SECCFGR2_SEC24_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC24_Pos) /*!< 0x01000000 */ +#define GTZC_MPCBB_SECCFGR2_SEC24 GTZC_MPCBB_SECCFGR2_SEC24_Msk /*!< Security configuration for block 24 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC25_Pos (25U) +#define GTZC_MPCBB_SECCFGR2_SEC25_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC25_Pos) /*!< 0x02000000 */ +#define GTZC_MPCBB_SECCFGR2_SEC25 GTZC_MPCBB_SECCFGR2_SEC25_Msk /*!< Security configuration for block 25 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC26_Pos (26U) +#define GTZC_MPCBB_SECCFGR2_SEC26_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC26_Pos) /*!< 0x04000000 */ +#define GTZC_MPCBB_SECCFGR2_SEC26 GTZC_MPCBB_SECCFGR2_SEC26_Msk /*!< Security configuration for block 26 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC27_Pos (27U) +#define GTZC_MPCBB_SECCFGR2_SEC27_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC27_Pos) /*!< 0x08000000 */ +#define GTZC_MPCBB_SECCFGR2_SEC27 GTZC_MPCBB_SECCFGR2_SEC27_Msk /*!< Security configuration for block 27 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC28_Pos (28U) +#define GTZC_MPCBB_SECCFGR2_SEC28_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC28_Pos) /*!< 0x10000000 */ +#define GTZC_MPCBB_SECCFGR2_SEC28 GTZC_MPCBB_SECCFGR2_SEC28_Msk /*!< Security configuration for block 28 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC29_Pos (29U) +#define GTZC_MPCBB_SECCFGR2_SEC29_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC29_Pos) /*!< 0x20000000 */ +#define GTZC_MPCBB_SECCFGR2_SEC29 GTZC_MPCBB_SECCFGR2_SEC29_Msk /*!< Security configuration for block 29 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC30_Pos (30U) +#define GTZC_MPCBB_SECCFGR2_SEC30_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC30_Pos) /*!< 0x40000000 */ +#define GTZC_MPCBB_SECCFGR2_SEC30 GTZC_MPCBB_SECCFGR2_SEC31_Msk /*!< Security configuration for block 30 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC31_Pos (31U) +#define GTZC_MPCBB_SECCFGR2_SEC31_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC31_Pos) /*!< 0x80000000 */ +#define GTZC_MPCBB_SECCFGR2_SEC31 GTZC_MPCBB_SECCFGR2_SEC31_Msk /*!< Security configuration for block 31 in super block 2 */ + +/******************* Bits definition for GTZC_MPCBB_SECCFGR3 register ************/ +#define GTZC_MPCBB_SECCFGR3_SEC0_Pos (0U) +#define GTZC_MPCBB_SECCFGR3_SEC0_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC0_Pos) /*!< 0x00000001 */ +#define GTZC_MPCBB_SECCFGR3_SEC0 GTZC_MPCBB_SECCFGR3_SEC0_Msk /*!< Security configuration for block 0 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC1_Pos (1U) +#define GTZC_MPCBB_SECCFGR3_SEC1_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC1_Pos) /*!< 0x00000002 */ +#define GTZC_MPCBB_SECCFGR3_SEC1 GTZC_MPCBB_SECCFGR3_SEC1_Msk /*!< Security configuration for block 1 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC2_Pos (2U) +#define GTZC_MPCBB_SECCFGR3_SEC2_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC2_Pos) /*!< 0x00000004 */ +#define GTZC_MPCBB_SECCFGR3_SEC2 GTZC_MPCBB_SECCFGR3_SEC2_Msk /*!< Security configuration for block 2 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC3_Pos (3U) +#define GTZC_MPCBB_SECCFGR3_SEC3_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC3_Pos) /*!< 0x00000008 */ +#define GTZC_MPCBB_SECCFGR3_SEC3 GTZC_MPCBB_SECCFGR3_SEC3_Msk /*!< Security configuration for block 3 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC4_Pos (4U) +#define GTZC_MPCBB_SECCFGR3_SEC4_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC4_Pos) /*!< 0x00000010 */ +#define GTZC_MPCBB_SECCFGR3_SEC4 GTZC_MPCBB_SECCFGR3_SEC4_Msk /*!< Security configuration for block 4 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC5_Pos (5U) +#define GTZC_MPCBB_SECCFGR3_SEC5_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC5_Pos) /*!< 0x00000020 */ +#define GTZC_MPCBB_SECCFGR3_SEC5 GTZC_MPCBB_SECCFGR3_SEC5_Msk /*!< Security configuration for block 5 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC6_Pos (6U) +#define GTZC_MPCBB_SECCFGR3_SEC6_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC6_Pos) /*!< 0x00000040 */ +#define GTZC_MPCBB_SECCFGR3_SEC6 GTZC_MPCBB_SECCFGR3_SEC6_Msk /*!< Security configuration for block 6 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC7_Pos (7U) +#define GTZC_MPCBB_SECCFGR3_SEC7_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC7_Pos) /*!< 0x00000080 */ +#define GTZC_MPCBB_SECCFGR3_SEC7 GTZC_MPCBB_SECCFGR3_SEC7_Msk /*!< Security configuration for block 7 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC8_Pos (8U) +#define GTZC_MPCBB_SECCFGR3_SEC8_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC8_Pos) /*!< 0x00000100 */ +#define GTZC_MPCBB_SECCFGR3_SEC8 GTZC_MPCBB_SECCFGR3_SEC8_Msk /*!< Security configuration for block 8 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC9_Pos (9U) +#define GTZC_MPCBB_SECCFGR3_SEC9_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC9_Pos) /*!< 0x00000200 */ +#define GTZC_MPCBB_SECCFGR3_SEC9 GTZC_MPCBB_SECCFGR3_SEC9_Msk /*!< Security configuration for block 9 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC10_Pos (10U) +#define GTZC_MPCBB_SECCFGR3_SEC10_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC10_Pos) /*!< 0x00000400 */ +#define GTZC_MPCBB_SECCFGR3_SEC10 GTZC_MPCBB_SECCFGR3_SEC10_Msk /*!< Security configuration for block 10 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC11_Pos (11U) +#define GTZC_MPCBB_SECCFGR3_SEC11_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC11_Pos) /*!< 0x00000800 */ +#define GTZC_MPCBB_SECCFGR3_SEC11 GTZC_MPCBB_SECCFGR3_SEC11_Msk /*!< Security configuration for block 11 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC12_Pos (12U) +#define GTZC_MPCBB_SECCFGR3_SEC12_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC12_Pos) /*!< 0x00001000 */ +#define GTZC_MPCBB_SECCFGR3_SEC12 GTZC_MPCBB_SECCFGR3_SEC12_Msk /*!< Security configuration for block 12 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC13_Pos (13U) +#define GTZC_MPCBB_SECCFGR3_SEC13_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC13_Pos) /*!< 0x00002000 */ +#define GTZC_MPCBB_SECCFGR3_SEC13 GTZC_MPCBB_SECCFGR3_SEC13_Msk /*!< Security configuration for block 13 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC14_Pos (14U) +#define GTZC_MPCBB_SECCFGR3_SEC14_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC14_Pos) /*!< 0x00004000 */ +#define GTZC_MPCBB_SECCFGR3_SEC14 GTZC_MPCBB_SECCFGR3_SEC14_Msk /*!< Security configuration for block 14 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC15_Pos (15U) +#define GTZC_MPCBB_SECCFGR3_SEC15_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC15_Pos) /*!< 0x00008000 */ +#define GTZC_MPCBB_SECCFGR3_SEC15 GTZC_MPCBB_SECCFGR3_SEC15_Msk /*!< Security configuration for block 15 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC16_Pos (16U) +#define GTZC_MPCBB_SECCFGR3_SEC16_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC16_Pos) /*!< 0x00010000 */ +#define GTZC_MPCBB_SECCFGR3_SEC16 GTZC_MPCBB_SECCFGR3_SEC16_Msk /*!< Security configuration for block 16 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC17_Pos (17U) +#define GTZC_MPCBB_SECCFGR3_SEC17_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC17_Pos) /*!< 0x00020000 */ +#define GTZC_MPCBB_SECCFGR3_SEC17 GTZC_MPCBB_SECCFGR3_SEC17_Msk /*!< Security configuration for block 17 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC18_Pos (18U) +#define GTZC_MPCBB_SECCFGR3_SEC18_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC18_Pos) /*!< 0x00040000 */ +#define GTZC_MPCBB_SECCFGR3_SEC18 GTZC_MPCBB_SECCFGR3_SEC18_Msk /*!< Security configuration for block 18 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC19_Pos (19U) +#define GTZC_MPCBB_SECCFGR3_SEC19_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC19_Pos) /*!< 0x00080000 */ +#define GTZC_MPCBB_SECCFGR3_SEC19 GTZC_MPCBB_SECCFGR3_SEC19_Msk /*!< Security configuration for block 19 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC20_Pos (20U) +#define GTZC_MPCBB_SECCFGR3_SEC20_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC20_Pos) /*!< 0x00100000 */ +#define GTZC_MPCBB_SECCFGR3_SEC20 GTZC_MPCBB_SECCFGR3_SEC20_Msk /*!< Security configuration for block 20 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC21_Pos (21U) +#define GTZC_MPCBB_SECCFGR3_SEC21_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC21_Pos) /*!< 0x00200000 */ +#define GTZC_MPCBB_SECCFGR3_SEC21 GTZC_MPCBB_SECCFGR3_SEC21_Msk /*!< Security configuration for block 21 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC22_Pos (22U) +#define GTZC_MPCBB_SECCFGR3_SEC22_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC22_Pos) /*!< 0x00400000 */ +#define GTZC_MPCBB_SECCFGR3_SEC22 GTZC_MPCBB_SECCFGR3_SEC22_Msk /*!< Security configuration for block 22 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC23_Pos (23U) +#define GTZC_MPCBB_SECCFGR3_SEC23_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC23_Pos) /*!< 0x00800000 */ +#define GTZC_MPCBB_SECCFGR3_SEC23 GTZC_MPCBB_SECCFGR3_SEC23_Msk /*!< Security configuration for block 23 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC24_Pos (24U) +#define GTZC_MPCBB_SECCFGR3_SEC24_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC24_Pos) /*!< 0x01000000 */ +#define GTZC_MPCBB_SECCFGR3_SEC24 GTZC_MPCBB_SECCFGR3_SEC24_Msk /*!< Security configuration for block 24 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC25_Pos (25U) +#define GTZC_MPCBB_SECCFGR3_SEC25_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC25_Pos) /*!< 0x02000000 */ +#define GTZC_MPCBB_SECCFGR3_SEC25 GTZC_MPCBB_SECCFGR3_SEC25_Msk /*!< Security configuration for block 25 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC26_Pos (26U) +#define GTZC_MPCBB_SECCFGR3_SEC26_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC26_Pos) /*!< 0x04000000 */ +#define GTZC_MPCBB_SECCFGR3_SEC26 GTZC_MPCBB_SECCFGR3_SEC26_Msk /*!< Security configuration for block 26 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC27_Pos (27U) +#define GTZC_MPCBB_SECCFGR3_SEC27_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC27_Pos) /*!< 0x08000000 */ +#define GTZC_MPCBB_SECCFGR3_SEC27 GTZC_MPCBB_SECCFGR3_SEC27_Msk /*!< Security configuration for block 27 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC28_Pos (28U) +#define GTZC_MPCBB_SECCFGR3_SEC28_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC28_Pos) /*!< 0x10000000 */ +#define GTZC_MPCBB_SECCFGR3_SEC28 GTZC_MPCBB_SECCFGR3_SEC28_Msk /*!< Security configuration for block 28 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC29_Pos (29U) +#define GTZC_MPCBB_SECCFGR3_SEC29_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC29_Pos) /*!< 0x20000000 */ +#define GTZC_MPCBB_SECCFGR3_SEC29 GTZC_MPCBB_SECCFGR3_SEC29_Msk /*!< Security configuration for block 29 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC30_Pos (30U) +#define GTZC_MPCBB_SECCFGR3_SEC30_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC30_Pos) /*!< 0x40000000 */ +#define GTZC_MPCBB_SECCFGR3_SEC30 GTZC_MPCBB_SECCFGR3_SEC31_Msk /*!< Security configuration for block 30 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC31_Pos (31U) +#define GTZC_MPCBB_SECCFGR3_SEC31_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC31_Pos) /*!< 0x80000000 */ +#define GTZC_MPCBB_SECCFGR3_SEC31 GTZC_MPCBB_SECCFGR3_SEC31_Msk /*!< Security configuration for block 31 in super block 3 */ + +/******************* Bits definition for GTZC_MPCBB_PRIVCFGR0 register ************/ +#define GTZC_MPCBB_PRIVCFGR0_PRIV0_Pos (0U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV0_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV0_Pos) /*!< 0x00000001 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV0 GTZC_MPCBB_PRIVCFGR0_PRIV0_Msk /*!< Privileged configuration for block 0 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV1_Pos (1U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV1_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV1_Pos) /*!< 0x00000002 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV1 GTZC_MPCBB_PRIVCFGR0_PRIV1_Msk /*!< Privileged configuration for block 1 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV2_Pos (2U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV2_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV2_Pos) /*!< 0x00000004 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV2 GTZC_MPCBB_PRIVCFGR0_PRIV2_Msk /*!< Privileged configuration for block 2 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV3_Pos (3U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV3_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV3_Pos) /*!< 0x00000008 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV3 GTZC_MPCBB_PRIVCFGR0_PRIV3_Msk /*!< Privileged configuration for block 3 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV4_Pos (4U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV4_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV4_Pos) /*!< 0x00000010 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV4 GTZC_MPCBB_PRIVCFGR0_PRIV4_Msk /*!< Privileged configuration for block 4 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV5_Pos (5U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV5_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV5_Pos) /*!< 0x00000020 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV5 GTZC_MPCBB_PRIVCFGR0_PRIV5_Msk /*!< Privileged configuration for block 5 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV6_Pos (6U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV6_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV6_Pos) /*!< 0x00000040 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV6 GTZC_MPCBB_PRIVCFGR0_PRIV6_Msk /*!< Privileged configuration for block 6 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV7_Pos (7U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV7_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV7_Pos) /*!< 0x00000080 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV7 GTZC_MPCBB_PRIVCFGR0_PRIV7_Msk /*!< Privileged configuration for block 7 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV8_Pos (8U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV8_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV8_Pos) /*!< 0x00000100 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV8 GTZC_MPCBB_PRIVCFGR0_PRIV8_Msk /*!< Privileged configuration for block 8 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV9_Pos (9U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV9_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV9_Pos) /*!< 0x00000200 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV9 GTZC_MPCBB_PRIVCFGR0_PRIV9_Msk /*!< Privileged configuration for block 9 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV10_Pos (10U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV10_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV10_Pos) /*!< 0x00000400 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV10 GTZC_MPCBB_PRIVCFGR0_PRIV10_Msk /*!< Privileged configuration for block 10 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV11_Pos (11U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV11_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV11_Pos) /*!< 0x00000800 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV11 GTZC_MPCBB_PRIVCFGR0_PRIV11_Msk /*!< Privileged configuration for block 11 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV12_Pos (12U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV12_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV12_Pos) /*!< 0x00001000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV12 GTZC_MPCBB_PRIVCFGR0_PRIV12_Msk /*!< Privileged configuration for block 12 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV13_Pos (13U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV13_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV13_Pos) /*!< 0x00002000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV13 GTZC_MPCBB_PRIVCFGR0_PRIV13_Msk /*!< Privileged configuration for block 13 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV14_Pos (14U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV14_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV14_Pos) /*!< 0x00004000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV14 GTZC_MPCBB_PRIVCFGR0_PRIV14_Msk /*!< Privileged configuration for block 14 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV15_Pos (15U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV15_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV15_Pos) /*!< 0x00008000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV15 GTZC_MPCBB_PRIVCFGR0_PRIV15_Msk /*!< Privileged configuration for block 15 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV16_Pos (16U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV16_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV16_Pos) /*!< 0x00010000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV16 GTZC_MPCBB_PRIVCFGR0_PRIV16_Msk /*!< Privileged configuration for block 16 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV17_Pos (17U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV17_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV17_Pos) /*!< 0x00020000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV17 GTZC_MPCBB_PRIVCFGR0_PRIV17_Msk /*!< Privileged configuration for block 17 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV18_Pos (18U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV18_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV18_Pos) /*!< 0x00040000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV18 GTZC_MPCBB_PRIVCFGR0_PRIV18_Msk /*!< Privileged configuration for block 18 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV19_Pos (19U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV19_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV19_Pos) /*!< 0x00080000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV19 GTZC_MPCBB_PRIVCFGR0_PRIV19_Msk /*!< Privileged configuration for block 19 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV20_Pos (20U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV20_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV20_Pos) /*!< 0x00100000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV20 GTZC_MPCBB_PRIVCFGR0_PRIV20_Msk /*!< Privileged configuration for block 20 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV21_Pos (21U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV21_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV21_Pos) /*!< 0x00200000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV21 GTZC_MPCBB_PRIVCFGR0_PRIV21_Msk /*!< Privileged configuration for block 21 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV22_Pos (22U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV22_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV22_Pos) /*!< 0x00400000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV22 GTZC_MPCBB_PRIVCFGR0_PRIV22_Msk /*!< Privileged configuration for block 22 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV23_Pos (23U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV23_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV23_Pos) /*!< 0x00800000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV23 GTZC_MPCBB_PRIVCFGR0_PRIV23_Msk /*!< Privileged configuration for block 23 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV24_Pos (24U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV24_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV24_Pos) /*!< 0x01000000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV24 GTZC_MPCBB_PRIVCFGR0_PRIV24_Msk /*!< Privileged configuration for block 24 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV25_Pos (25U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV25_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV25_Pos) /*!< 0x02000000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV25 GTZC_MPCBB_PRIVCFGR0_PRIV25_Msk /*!< Privileged configuration for block 25 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV26_Pos (26U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV26_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV26_Pos) /*!< 0x04000000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV26 GTZC_MPCBB_PRIVCFGR0_PRIV26_Msk /*!< Privileged configuration for block 26 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV27_Pos (27U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV27_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV27_Pos) /*!< 0x08000000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV27 GTZC_MPCBB_PRIVCFGR0_PRIV27_Msk /*!< Privileged configuration for block 27 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV28_Pos (28U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV28_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV28_Pos) /*!< 0x10000000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV28 GTZC_MPCBB_PRIVCFGR0_PRIV28_Msk /*!< Privileged configuration for block 28 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV29_Pos (29U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV29_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV29_Pos) /*!< 0x20000000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV29 GTZC_MPCBB_PRIVCFGR0_PRIV29_Msk /*!< Privileged configuration for block 29 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV30_Pos (30U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV30_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV30_Pos) /*!< 0x40000000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV30 GTZC_MPCBB_PRIVCFGR0_PRIV31_Msk /*!< Privileged configuration for block 30 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV31_Pos (31U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV31_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV31_Pos) /*!< 0x80000000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV31 GTZC_MPCBB_PRIVCFGR0_PRIV31_Msk /*!< Privileged configuration for block 31 in super block 0 */ + +/******************* Bits definition for GTZC_MPCBB_PRIVCFGR1 register ************/ +#define GTZC_MPCBB_PRIVCFGR1_PRIV0_Pos (0U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV0_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV0_Pos) /*!< 0x00000001 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV0 GTZC_MPCBB_PRIVCFGR1_PRIV0_Msk /*!< Privileged configuration for block 0 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV1_Pos (1U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV1_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV1_Pos) /*!< 0x00000002 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV1 GTZC_MPCBB_PRIVCFGR1_PRIV1_Msk /*!< Privileged configuration for block 1 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV2_Pos (2U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV2_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV2_Pos) /*!< 0x00000004 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV2 GTZC_MPCBB_PRIVCFGR1_PRIV2_Msk /*!< Privileged configuration for block 2 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV3_Pos (3U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV3_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV3_Pos) /*!< 0x00000008 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV3 GTZC_MPCBB_PRIVCFGR1_PRIV3_Msk /*!< Privileged configuration for block 3 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV4_Pos (4U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV4_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV4_Pos) /*!< 0x00000010 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV4 GTZC_MPCBB_PRIVCFGR1_PRIV4_Msk /*!< Privileged configuration for block 4 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV5_Pos (5U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV5_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV5_Pos) /*!< 0x00000020 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV5 GTZC_MPCBB_PRIVCFGR1_PRIV5_Msk /*!< Privileged configuration for block 5 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV6_Pos (6U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV6_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV6_Pos) /*!< 0x00000040 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV6 GTZC_MPCBB_PRIVCFGR1_PRIV6_Msk /*!< Privileged configuration for block 6 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV7_Pos (7U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV7_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV7_Pos) /*!< 0x00000080 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV7 GTZC_MPCBB_PRIVCFGR1_PRIV7_Msk /*!< Privileged configuration for block 7 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV8_Pos (8U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV8_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV8_Pos) /*!< 0x00000100 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV8 GTZC_MPCBB_PRIVCFGR1_PRIV8_Msk /*!< Privileged configuration for block 8 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV9_Pos (9U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV9_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV9_Pos) /*!< 0x00000200 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV9 GTZC_MPCBB_PRIVCFGR1_PRIV9_Msk /*!< Privileged configuration for block 9 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV10_Pos (10U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV10_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV10_Pos) /*!< 0x00000400 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV10 GTZC_MPCBB_PRIVCFGR1_PRIV10_Msk /*!< Privileged configuration for block 10 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV11_Pos (11U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV11_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV11_Pos) /*!< 0x00000800 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV11 GTZC_MPCBB_PRIVCFGR1_PRIV11_Msk /*!< Privileged configuration for block 11 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV12_Pos (12U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV12_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV12_Pos) /*!< 0x00001000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV12 GTZC_MPCBB_PRIVCFGR1_PRIV12_Msk /*!< Privileged configuration for block 12 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV13_Pos (13U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV13_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV13_Pos) /*!< 0x00002000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV13 GTZC_MPCBB_PRIVCFGR1_PRIV13_Msk /*!< Privileged configuration for block 13 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV14_Pos (14U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV14_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV14_Pos) /*!< 0x00004000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV14 GTZC_MPCBB_PRIVCFGR1_PRIV14_Msk /*!< Privileged configuration for block 14 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV15_Pos (15U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV15_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV15_Pos) /*!< 0x00008000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV15 GTZC_MPCBB_PRIVCFGR1_PRIV15_Msk /*!< Privileged configuration for block 15 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV16_Pos (16U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV16_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV16_Pos) /*!< 0x00010000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV16 GTZC_MPCBB_PRIVCFGR1_PRIV16_Msk /*!< Privileged configuration for block 16 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV17_Pos (17U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV17_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV17_Pos) /*!< 0x00020000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV17 GTZC_MPCBB_PRIVCFGR1_PRIV17_Msk /*!< Privileged configuration for block 17 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV18_Pos (18U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV18_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV18_Pos) /*!< 0x00040000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV18 GTZC_MPCBB_PRIVCFGR1_PRIV18_Msk /*!< Privileged configuration for block 18 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV19_Pos (19U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV19_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV19_Pos) /*!< 0x00080000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV19 GTZC_MPCBB_PRIVCFGR1_PRIV19_Msk /*!< Privileged configuration for block 19 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV20_Pos (20U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV20_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV20_Pos) /*!< 0x00100000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV20 GTZC_MPCBB_PRIVCFGR1_PRIV20_Msk /*!< Privileged configuration for block 20 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV21_Pos (21U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV21_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV21_Pos) /*!< 0x00200000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV21 GTZC_MPCBB_PRIVCFGR1_PRIV21_Msk /*!< Privileged configuration for block 21 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV22_Pos (22U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV22_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV22_Pos) /*!< 0x00400000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV22 GTZC_MPCBB_PRIVCFGR1_PRIV22_Msk /*!< Privileged configuration for block 22 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV23_Pos (23U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV23_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV23_Pos) /*!< 0x00800000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV23 GTZC_MPCBB_PRIVCFGR1_PRIV23_Msk /*!< Privileged configuration for block 23 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV24_Pos (24U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV24_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV24_Pos) /*!< 0x01000000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV24 GTZC_MPCBB_PRIVCFGR1_PRIV24_Msk /*!< Privileged configuration for block 24 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV25_Pos (25U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV25_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV25_Pos) /*!< 0x02000000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV25 GTZC_MPCBB_PRIVCFGR1_PRIV25_Msk /*!< Privileged configuration for block 25 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV26_Pos (26U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV26_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV26_Pos) /*!< 0x04000000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV26 GTZC_MPCBB_PRIVCFGR1_PRIV26_Msk /*!< Privileged configuration for block 26 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV27_Pos (27U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV27_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV27_Pos) /*!< 0x08000000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV27 GTZC_MPCBB_PRIVCFGR1_PRIV27_Msk /*!< Privileged configuration for block 27 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV28_Pos (28U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV28_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV28_Pos) /*!< 0x10000000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV28 GTZC_MPCBB_PRIVCFGR1_PRIV28_Msk /*!< Privileged configuration for block 28 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV29_Pos (29U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV29_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV29_Pos) /*!< 0x20000000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV29 GTZC_MPCBB_PRIVCFGR1_PRIV29_Msk /*!< Privileged configuration for block 29 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV30_Pos (30U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV30_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV30_Pos) /*!< 0x40000000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV30 GTZC_MPCBB_PRIVCFGR1_PRIV31_Msk /*!< Privileged configuration for block 30 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV31_Pos (31U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV31_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV31_Pos) /*!< 0x80000000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV31 GTZC_MPCBB_PRIVCFGR1_PRIV31_Msk /*!< Privileged configuration for block 31 in super block 1 */ + +/******************* Bits definition for GTZC_MPCBB_PRIVCFGR2 register ************/ +#define GTZC_MPCBB_PRIVCFGR2_PRIV0_Pos (0U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV0_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV0_Pos) /*!< 0x00000001 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV0 GTZC_MPCBB_PRIVCFGR2_PRIV0_Msk /*!< Privileged configuration for block 0 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV1_Pos (1U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV1_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV1_Pos) /*!< 0x00000002 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV1 GTZC_MPCBB_PRIVCFGR2_PRIV1_Msk /*!< Privileged configuration for block 1 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV2_Pos (2U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV2_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV2_Pos) /*!< 0x00000004 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV2 GTZC_MPCBB_PRIVCFGR2_PRIV2_Msk /*!< Privileged configuration for block 2 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV3_Pos (3U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV3_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV3_Pos) /*!< 0x00000008 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV3 GTZC_MPCBB_PRIVCFGR2_PRIV3_Msk /*!< Privileged configuration for block 3 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV4_Pos (4U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV4_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV4_Pos) /*!< 0x00000010 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV4 GTZC_MPCBB_PRIVCFGR2_PRIV4_Msk /*!< Privileged configuration for block 4 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV5_Pos (5U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV5_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV5_Pos) /*!< 0x00000020 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV5 GTZC_MPCBB_PRIVCFGR2_PRIV5_Msk /*!< Privileged configuration for block 5 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV6_Pos (6U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV6_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV6_Pos) /*!< 0x00000040 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV6 GTZC_MPCBB_PRIVCFGR2_PRIV6_Msk /*!< Privileged configuration for block 6 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV7_Pos (7U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV7_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV7_Pos) /*!< 0x00000080 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV7 GTZC_MPCBB_PRIVCFGR2_PRIV7_Msk /*!< Privileged configuration for block 7 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV8_Pos (8U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV8_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV8_Pos) /*!< 0x00000100 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV8 GTZC_MPCBB_PRIVCFGR2_PRIV8_Msk /*!< Privileged configuration for block 8 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV9_Pos (9U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV9_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV9_Pos) /*!< 0x00000200 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV9 GTZC_MPCBB_PRIVCFGR2_PRIV9_Msk /*!< Privileged configuration for block 9 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV10_Pos (10U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV10_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV10_Pos) /*!< 0x00000400 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV10 GTZC_MPCBB_PRIVCFGR2_PRIV10_Msk /*!< Privileged configuration for block 10 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV11_Pos (11U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV11_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV11_Pos) /*!< 0x00000800 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV11 GTZC_MPCBB_PRIVCFGR2_PRIV11_Msk /*!< Privileged configuration for block 11 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV12_Pos (12U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV12_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV12_Pos) /*!< 0x00001000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV12 GTZC_MPCBB_PRIVCFGR2_PRIV12_Msk /*!< Privileged configuration for block 12 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV13_Pos (13U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV13_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV13_Pos) /*!< 0x00002000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV13 GTZC_MPCBB_PRIVCFGR2_PRIV13_Msk /*!< Privileged configuration for block 13 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV14_Pos (14U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV14_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV14_Pos) /*!< 0x00004000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV14 GTZC_MPCBB_PRIVCFGR2_PRIV14_Msk /*!< Privileged configuration for block 14 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV15_Pos (15U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV15_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV15_Pos) /*!< 0x00008000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV15 GTZC_MPCBB_PRIVCFGR2_PRIV15_Msk /*!< Privileged configuration for block 15 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV16_Pos (16U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV16_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV16_Pos) /*!< 0x00010000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV16 GTZC_MPCBB_PRIVCFGR2_PRIV16_Msk /*!< Privileged configuration for block 16 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV17_Pos (17U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV17_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV17_Pos) /*!< 0x00020000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV17 GTZC_MPCBB_PRIVCFGR2_PRIV17_Msk /*!< Privileged configuration for block 17 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV18_Pos (18U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV18_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV18_Pos) /*!< 0x00040000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV18 GTZC_MPCBB_PRIVCFGR2_PRIV18_Msk /*!< Privileged configuration for block 18 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV19_Pos (19U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV19_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV19_Pos) /*!< 0x00080000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV19 GTZC_MPCBB_PRIVCFGR2_PRIV19_Msk /*!< Privileged configuration for block 19 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV20_Pos (20U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV20_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV20_Pos) /*!< 0x00100000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV20 GTZC_MPCBB_PRIVCFGR2_PRIV20_Msk /*!< Privileged configuration for block 20 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV21_Pos (21U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV21_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV21_Pos) /*!< 0x00200000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV21 GTZC_MPCBB_PRIVCFGR2_PRIV21_Msk /*!< Privileged configuration for block 21 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV22_Pos (22U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV22_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV22_Pos) /*!< 0x00400000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV22 GTZC_MPCBB_PRIVCFGR2_PRIV22_Msk /*!< Privileged configuration for block 22 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV23_Pos (23U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV23_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV23_Pos) /*!< 0x00800000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV23 GTZC_MPCBB_PRIVCFGR2_PRIV23_Msk /*!< Privileged configuration for block 23 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV24_Pos (24U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV24_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV24_Pos) /*!< 0x01000000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV24 GTZC_MPCBB_PRIVCFGR2_PRIV24_Msk /*!< Privileged configuration for block 24 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV25_Pos (25U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV25_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV25_Pos) /*!< 0x02000000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV25 GTZC_MPCBB_PRIVCFGR2_PRIV25_Msk /*!< Privileged configuration for block 25 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV26_Pos (26U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV26_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV26_Pos) /*!< 0x04000000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV26 GTZC_MPCBB_PRIVCFGR2_PRIV26_Msk /*!< Privileged configuration for block 26 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV27_Pos (27U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV27_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV27_Pos) /*!< 0x08000000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV27 GTZC_MPCBB_PRIVCFGR2_PRIV27_Msk /*!< Privileged configuration for block 27 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV28_Pos (28U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV28_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV28_Pos) /*!< 0x10000000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV28 GTZC_MPCBB_PRIVCFGR2_PRIV28_Msk /*!< Privileged configuration for block 28 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV29_Pos (29U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV29_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV29_Pos) /*!< 0x20000000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV29 GTZC_MPCBB_PRIVCFGR2_PRIV29_Msk /*!< Privileged configuration for block 29 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV30_Pos (30U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV30_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV30_Pos) /*!< 0x40000000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV30 GTZC_MPCBB_PRIVCFGR2_PRIV31_Msk /*!< Privileged configuration for block 30 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV31_Pos (31U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV31_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV31_Pos) /*!< 0x80000000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV31 GTZC_MPCBB_PRIVCFGR2_PRIV31_Msk /*!< Privileged configuration for block 31 in super block 2 */ + +/******************* Bits definition for GTZC_MPCBB_PRIVCFGR3 register ************/ +#define GTZC_MPCBB_PRIVCFGR3_PRIV0_Pos (0U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV0_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV0_Pos) /*!< 0x00000001 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV0 GTZC_MPCBB_PRIVCFGR3_PRIV0_Msk /*!< Privileged configuration for block 0 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV1_Pos (1U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV1_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV1_Pos) /*!< 0x00000002 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV1 GTZC_MPCBB_PRIVCFGR3_PRIV1_Msk /*!< Privileged configuration for block 1 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV2_Pos (2U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV2_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV2_Pos) /*!< 0x00000004 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV2 GTZC_MPCBB_PRIVCFGR3_PRIV2_Msk /*!< Privileged configuration for block 2 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV3_Pos (3U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV3_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV3_Pos) /*!< 0x00000008 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV3 GTZC_MPCBB_PRIVCFGR3_PRIV3_Msk /*!< Privileged configuration for block 3 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV4_Pos (4U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV4_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV4_Pos) /*!< 0x00000010 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV4 GTZC_MPCBB_PRIVCFGR3_PRIV4_Msk /*!< Privileged configuration for block 4 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV5_Pos (5U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV5_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV5_Pos) /*!< 0x00000020 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV5 GTZC_MPCBB_PRIVCFGR3_PRIV5_Msk /*!< Privileged configuration for block 5 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV6_Pos (6U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV6_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV6_Pos) /*!< 0x00000040 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV6 GTZC_MPCBB_PRIVCFGR3_PRIV6_Msk /*!< Privileged configuration for block 6 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV7_Pos (7U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV7_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV7_Pos) /*!< 0x00000080 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV7 GTZC_MPCBB_PRIVCFGR3_PRIV7_Msk /*!< Privileged configuration for block 7 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV8_Pos (8U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV8_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV8_Pos) /*!< 0x00000100 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV8 GTZC_MPCBB_PRIVCFGR3_PRIV8_Msk /*!< Privileged configuration for block 8 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV9_Pos (9U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV9_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV9_Pos) /*!< 0x00000200 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV9 GTZC_MPCBB_PRIVCFGR3_PRIV9_Msk /*!< Privileged configuration for block 9 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV10_Pos (10U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV10_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV10_Pos) /*!< 0x00000400 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV10 GTZC_MPCBB_PRIVCFGR3_PRIV10_Msk /*!< Privileged configuration for block 10 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV11_Pos (11U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV11_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV11_Pos) /*!< 0x00000800 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV11 GTZC_MPCBB_PRIVCFGR3_PRIV11_Msk /*!< Privileged configuration for block 11 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV12_Pos (12U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV12_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV12_Pos) /*!< 0x00001000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV12 GTZC_MPCBB_PRIVCFGR3_PRIV12_Msk /*!< Privileged configuration for block 12 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV13_Pos (13U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV13_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV13_Pos) /*!< 0x00002000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV13 GTZC_MPCBB_PRIVCFGR3_PRIV13_Msk /*!< Privileged configuration for block 13 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV14_Pos (14U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV14_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV14_Pos) /*!< 0x00004000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV14 GTZC_MPCBB_PRIVCFGR3_PRIV14_Msk /*!< Privileged configuration for block 14 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV15_Pos (15U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV15_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV15_Pos) /*!< 0x00008000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV15 GTZC_MPCBB_PRIVCFGR3_PRIV15_Msk /*!< Privileged configuration for block 15 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV16_Pos (16U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV16_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV16_Pos) /*!< 0x00010000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV16 GTZC_MPCBB_PRIVCFGR3_PRIV16_Msk /*!< Privileged configuration for block 16 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV17_Pos (17U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV17_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV17_Pos) /*!< 0x00020000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV17 GTZC_MPCBB_PRIVCFGR3_PRIV17_Msk /*!< Privileged configuration for block 17 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV18_Pos (18U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV18_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV18_Pos) /*!< 0x00040000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV18 GTZC_MPCBB_PRIVCFGR3_PRIV18_Msk /*!< Privileged configuration for block 18 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV19_Pos (19U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV19_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV19_Pos) /*!< 0x00080000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV19 GTZC_MPCBB_PRIVCFGR3_PRIV19_Msk /*!< Privileged configuration for block 19 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV20_Pos (20U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV20_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV20_Pos) /*!< 0x00100000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV20 GTZC_MPCBB_PRIVCFGR3_PRIV20_Msk /*!< Privileged configuration for block 20 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV21_Pos (21U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV21_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV21_Pos) /*!< 0x00200000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV21 GTZC_MPCBB_PRIVCFGR3_PRIV21_Msk /*!< Privileged configuration for block 21 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV22_Pos (22U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV22_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV22_Pos) /*!< 0x00400000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV22 GTZC_MPCBB_PRIVCFGR3_PRIV22_Msk /*!< Privileged configuration for block 22 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV23_Pos (23U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV23_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV23_Pos) /*!< 0x00800000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV23 GTZC_MPCBB_PRIVCFGR3_PRIV23_Msk /*!< Privileged configuration for block 23 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV24_Pos (24U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV24_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV24_Pos) /*!< 0x01000000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV24 GTZC_MPCBB_PRIVCFGR3_PRIV24_Msk /*!< Privileged configuration for block 24 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV25_Pos (25U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV25_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV25_Pos) /*!< 0x02000000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV25 GTZC_MPCBB_PRIVCFGR3_PRIV25_Msk /*!< Privileged configuration for block 25 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV26_Pos (26U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV26_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV26_Pos) /*!< 0x04000000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV26 GTZC_MPCBB_PRIVCFGR3_PRIV26_Msk /*!< Privileged configuration for block 26 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV27_Pos (27U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV27_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV27_Pos) /*!< 0x08000000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV27 GTZC_MPCBB_PRIVCFGR3_PRIV27_Msk /*!< Privileged configuration for block 27 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV28_Pos (28U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV28_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV28_Pos) /*!< 0x10000000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV28 GTZC_MPCBB_PRIVCFGR3_PRIV28_Msk /*!< Privileged configuration for block 28 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV29_Pos (29U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV29_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV29_Pos) /*!< 0x20000000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV29 GTZC_MPCBB_PRIVCFGR3_PRIV29_Msk /*!< Privileged configuration for block 29 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV30_Pos (30U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV30_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV30_Pos) /*!< 0x40000000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV30 GTZC_MPCBB_PRIVCFGR3_PRIV31_Msk /*!< Privileged configuration for block 30 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV31_Pos (31U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV31_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV31_Pos) /*!< 0x80000000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV31 GTZC_MPCBB_PRIVCFGR3_PRIV31_Msk /*!< Privileged configuration for block 31 in super block 3 */ + + +/******************************************************************************/ +/* */ +/* HASH */ +/* */ +/******************************************************************************/ +/****************** Bits definition for HASH_CR register ********************/ +#define HASH_CR_INIT_Pos (2U) +#define HASH_CR_INIT_Msk (0x1UL << HASH_CR_INIT_Pos) /*!< 0x00000004 */ +#define HASH_CR_INIT HASH_CR_INIT_Msk +#define HASH_CR_DMAE_Pos (3U) +#define HASH_CR_DMAE_Msk (0x1UL << HASH_CR_DMAE_Pos) /*!< 0x00000008 */ +#define HASH_CR_DMAE HASH_CR_DMAE_Msk +#define HASH_CR_DATATYPE_Pos (4U) +#define HASH_CR_DATATYPE_Msk (0x3UL << HASH_CR_DATATYPE_Pos) /*!< 0x00000030 */ +#define HASH_CR_DATATYPE HASH_CR_DATATYPE_Msk +#define HASH_CR_DATATYPE_0 (0x1UL << HASH_CR_DATATYPE_Pos) /*!< 0x00000010 */ +#define HASH_CR_DATATYPE_1 (0x2UL << HASH_CR_DATATYPE_Pos) /*!< 0x00000020 */ +#define HASH_CR_MODE_Pos (6U) +#define HASH_CR_MODE_Msk (0x1UL << HASH_CR_MODE_Pos) /*!< 0x00000040 */ +#define HASH_CR_MODE HASH_CR_MODE_Msk +#define HASH_CR_NBW_Pos (8U) +#define HASH_CR_NBW_Msk (0xFUL << HASH_CR_NBW_Pos) /*!< 0x00000F00 */ +#define HASH_CR_NBW HASH_CR_NBW_Msk +#define HASH_CR_NBW_0 (0x1UL << HASH_CR_NBW_Pos) /*!< 0x00000100 */ +#define HASH_CR_NBW_1 (0x2UL << HASH_CR_NBW_Pos) /*!< 0x00000200 */ +#define HASH_CR_NBW_2 (0x4UL << HASH_CR_NBW_Pos) /*!< 0x00000400 */ +#define HASH_CR_NBW_3 (0x8UL << HASH_CR_NBW_Pos) /*!< 0x00000800 */ +#define HASH_CR_DINNE_Pos (12U) +#define HASH_CR_DINNE_Msk (0x1UL << HASH_CR_DINNE_Pos) /*!< 0x00001000 */ +#define HASH_CR_DINNE HASH_CR_DINNE_Msk +#define HASH_CR_MDMAT_Pos (13U) +#define HASH_CR_MDMAT_Msk (0x1UL << HASH_CR_MDMAT_Pos) /*!< 0x00002000 */ +#define HASH_CR_MDMAT HASH_CR_MDMAT_Msk +#define HASH_CR_LKEY_Pos (16U) +#define HASH_CR_LKEY_Msk (0x1UL << HASH_CR_LKEY_Pos) /*!< 0x00010000 */ +#define HASH_CR_LKEY HASH_CR_LKEY_Msk +#define HASH_CR_ALGO_Pos (17U) +#define HASH_CR_ALGO_Msk (0x3UL << HASH_CR_ALGO_Pos) /*!< 0x00040080 */ +#define HASH_CR_ALGO HASH_CR_ALGO_Msk +#define HASH_CR_ALGO_0 (0x1UL << HASH_CR_ALGO_Pos) /*!< 0x00000080 */ +#define HASH_CR_ALGO_1 (0x2UL << HASH_CR_ALGO_Pos) /*!< 0x00040000 */ + +/****************** Bits definition for HASH_STR register *******************/ +#define HASH_STR_NBLW_Pos (0U) +#define HASH_STR_NBLW_Msk (0x1FUL << HASH_STR_NBLW_Pos) /*!< 0x0000001F */ +#define HASH_STR_NBLW HASH_STR_NBLW_Msk +#define HASH_STR_NBLW_0 (0x01UL << HASH_STR_NBLW_Pos) /*!< 0x00000001 */ +#define HASH_STR_NBLW_1 (0x02UL << HASH_STR_NBLW_Pos) /*!< 0x00000002 */ +#define HASH_STR_NBLW_2 (0x04UL << HASH_STR_NBLW_Pos) /*!< 0x00000004 */ +#define HASH_STR_NBLW_3 (0x08UL << HASH_STR_NBLW_Pos) /*!< 0x00000008 */ +#define HASH_STR_NBLW_4 (0x10UL << HASH_STR_NBLW_Pos) /*!< 0x00000010 */ +#define HASH_STR_DCAL_Pos (8U) +#define HASH_STR_DCAL_Msk (0x1UL << HASH_STR_DCAL_Pos) /*!< 0x00000100 */ +#define HASH_STR_DCAL HASH_STR_DCAL_Msk + +/****************** Bits definition for HASH_IMR register *******************/ +#define HASH_IMR_DINIE_Pos (0U) +#define HASH_IMR_DINIE_Msk (0x1UL << HASH_IMR_DINIE_Pos) /*!< 0x00000001 */ +#define HASH_IMR_DINIE HASH_IMR_DINIE_Msk +#define HASH_IMR_DCIE_Pos (1U) +#define HASH_IMR_DCIE_Msk (0x1UL << HASH_IMR_DCIE_Pos) /*!< 0x00000002 */ +#define HASH_IMR_DCIE HASH_IMR_DCIE_Msk + +/****************** Bits definition for HASH_SR register ********************/ +#define HASH_SR_DINIS_Pos (0U) +#define HASH_SR_DINIS_Msk (0x1UL << HASH_SR_DINIS_Pos) /*!< 0x00000001 */ +#define HASH_SR_DINIS HASH_SR_DINIS_Msk +#define HASH_SR_DCIS_Pos (1U) +#define HASH_SR_DCIS_Msk (0x1UL << HASH_SR_DCIS_Pos) /*!< 0x00000002 */ +#define HASH_SR_DCIS HASH_SR_DCIS_Msk +#define HASH_SR_DMAS_Pos (2U) +#define HASH_SR_DMAS_Msk (0x1UL << HASH_SR_DMAS_Pos) /*!< 0x00000004 */ +#define HASH_SR_DMAS HASH_SR_DMAS_Msk +#define HASH_SR_BUSY_Pos (3U) +#define HASH_SR_BUSY_Msk (0x1UL << HASH_SR_BUSY_Pos) /*!< 0x00000008 */ +#define HASH_SR_BUSY HASH_SR_BUSY_Msk +#define HASH_SR_NBWE_Pos (16U) +#define HASH_SR_NBWE_Msk (0xFUL << HASH_SR_NBWE_Pos) /*!< 0x000F0000 */ +#define HASH_SR_NBWE HASH_SR_NBWE_Msk +#define HASH_SR_NBWE_0 (0x01UL << HASH_SR_NBWE_Pos) /*!< 0x00010000 */ +#define HASH_SR_NBWE_1 (0x02UL << HASH_SR_NBWE_Pos) /*!< 0x00020000 */ +#define HASH_SR_NBWE_2 (0x04UL << HASH_SR_NBWE_Pos) /*!< 0x00040000 */ +#define HASH_SR_NBWE_3 (0x08UL << HASH_SR_NBWE_Pos) /*!< 0x00080000 */ +#define HASH_SR_DINNE_Pos (15U) +#define HASH_SR_DINNE_Msk (0x1UL << HASH_SR_DINNE_Pos) /*!< 0x00008000 */ +#define HASH_SR_DINNE HASH_SR_DINNE_Msk +#define HASH_SR_NBWP_Pos (9U) +#define HASH_SR_NBWP_Msk (0xFUL << HASH_SR_NBWP_Pos) /*!< 0x000F0000 */ +#define HASH_SR_NBWP HASH_SR_NBWP_Msk +#define HASH_SR_NBWP_0 (0x01UL << HASH_SR_NBWP_Pos) /*!< 0x000O0200 */ +#define HASH_SR_NBWP_1 (0x02UL << HASH_SR_NBWP_Pos) /*!< 0x00000400 */ +#define HASH_SR_NBWP_2 (0x04UL << HASH_SR_NBWP_Pos) /*!< 0x00000800 */ +#define HASH_SR_NBWP_3 (0x08UL << HASH_SR_NBWP_Pos) /*!< 0x00001000 */ + + +/******************************************************************************/ +/* */ +/* HSEM HW Semaphore */ +/* */ +/******************************************************************************/ +/******************** Bit definition for HSEM_R register ********************/ +#define HSEM_R_PROCID_Pos (0U) +#define HSEM_R_PROCID_Msk (0xFFUL << HSEM_R_PROCID_Pos) /*!< 0x000000FF */ +#define HSEM_R_PROCID HSEM_R_PROCID_Msk /*!>2) /*!< Input modulus number of bits */ +#define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Compute Montgomery parameter output data */ +#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output Montgomery parameter */ + +/* Compute modular exponentiation input data */ +#define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ +#define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ +#define PKA_MODULAR_EXP_IN_EXPONENT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process */ +#define PKA_MODULAR_EXP_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE ((0x16C8UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT ((0x14B8UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process protected exponentiation*/ +#define PKA_MODULAR_EXP_PROTECT_IN_MODULUS ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus to process protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_PHI ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input phi to process protected exponentiation */ + +/* Compute modular exponentiation output data */ +#define PKA_MODULAR_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_ERROR ((0x1298UL - PKA_RAM_OFFSET)>>2) /*!< Output error of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Output base of the exponentiation */ + +/* Compute ECC scalar multiplication input data */ +#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input curve prime order n number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_SCALAR_MUL_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' of KP */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input prime order n */ + +/* Compute ECC scalar multiplication output data */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Point check input data */ +#define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_POINT_CHECK_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_POINT_CHECK_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_POINT_CHECK_IN_MOD_GF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_POINT_CHECK_IN_MONTGOMERY_PARAM ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Point check output data */ +#define PKA_POINT_CHECK_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ + +/* ECDSA signature input data */ +#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECDSA_SIGN_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_SIGN_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input k value of the ECDSA */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_SIGN_IN_HASH_E ((0x0FE8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0x0F28UL - PKA_RAM_OFFSET)>>2) /*!< Input d, private key */ +#define PKA_ECDSA_SIGN_IN_ORDER_N ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA signature output data */ +#define PKA_ECDSA_SIGN_OUT_ERROR ((0x0FE0UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Output signature r */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Output signature s */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x1400UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point X coordinate */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1458UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point Y coordinate */ + + +/* ECDSA verification input data */ +#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x0468UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_A_COEFF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_MOD_GF ((0x04D0UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x0678UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x06D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0x12F8UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point X coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0x1350UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point Y coordinate */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x10E0UL - PKA_RAM_OFFSET)>>2) /*!< Input r, part of the signature */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input s, part of the signature */ +#define PKA_ECDSA_VERIF_IN_HASH_E ((0x13A8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_VERIF_IN_ORDER_N ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA verification output data */ +#define PKA_ECDSA_VERIF_OUT_RESULT ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* RSA CRT exponentiation input data */ +#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operands number of bits */ +#define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input Dp CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input Dq CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x0948UL - PKA_RAM_OFFSET)>>2) /*!< Input qInv CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x0B60UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime p */ +#define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime q */ +#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ + +/* RSA CRT exponentiation output data */ +#define PKA_RSA_CRT_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular reduction input data */ +#define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input operand length */ +#define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus length */ +#define PKA_MODULAR_REDUC_IN_OPERAND ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand */ +#define PKA_MODULAR_REDUC_IN_MODULUS ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Modular reduction output data */ +#define PKA_MODULAR_REDUC_OUT_RESULT ((0xE78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic addition input data */ +#define PKA_ARITHMETIC_ADD_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic addition output data */ +#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic subtraction input data */ +#define PKA_ARITHMETIC_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic subtraction output data */ +#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic multiplication input data */ +#define PKA_ARITHMETIC_MUL_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic multiplication output data */ +#define PKA_ARITHMETIC_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Comparison input data */ +#define PKA_COMPARISON_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_COMPARISON_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_COMPARISON_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Comparison output data */ +#define PKA_COMPARISON_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular addition input data */ +#define PKA_MODULAR_ADD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_ADD_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 (modulus) */ + +/* Modular addition output data */ +#define PKA_MODULAR_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular inversion input data */ +#define PKA_MODULAR_INV_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_INV_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_INV_IN_OP2_MOD ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 (modulus) */ + +/* Modular inversion output data */ +#define PKA_MODULAR_INV_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular subtraction input data */ +#define PKA_MODULAR_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_SUB_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ + +/* Modular subtraction output data */ +#define PKA_MODULAR_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Montgomery multiplication input data */ +#define PKA_MONTGOMERY_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MONTGOMERY_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MONTGOMERY_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Montgomery multiplication output data */ +#define PKA_MONTGOMERY_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Generic Arithmetic input data */ +#define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Generic Arithmetic output data */ +#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result for arithmetic operations */ + +/* Compute ECC complete addition input data */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC complete addition output data */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Output result Z coordinate */ + +/* Compute ECC double base ladder input data */ +#define PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input 'm' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC double base ladder output data */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_ERROR ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Compute ECC projective to affine conversion input data */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P X coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Y coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Z coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2 ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Compute ECC projective to affine conversion output data */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result x affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result y affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + + +/******************************************************************************/ +/* */ +/* PTA Converter */ +/* */ +/******************************************************************************/ +/****************** Bit definition for PTACONV_ACTCR register ***************/ +#define PTACONV_ACTCR_TACTIVE_Pos (0U) +#define PTACONV_ACTCR_TACTIVE_Msk (0xFFUL << PTACONV_ACTCR_TACTIVE_Pos) /*!< 0x000000FF */ +#define PTACONV_ACTCR_TACTIVE PTACONV_ACTCR_TACTIVE_Msk /*!< PTA_ACTIVE setup time in us */ +#define PTACONV_ACTCR_ACTPOL_Pos (15U) +#define PTACONV_ACTCR_ACTPOL_Msk (0x1UL << PTACONV_ACTCR_ACTPOL_Pos) /*!< 0x00008000 */ +#define PTACONV_ACTCR_ACTPOL PTACONV_ACTCR_ACTPOL_Msk /*!< PTA_ACTIVE polarity */ +#define PTACONV_ACTCR_TABORT_Pos (16U) +#define PTACONV_ACTCR_TABORT_Msk (0xFUL << PTACONV_ACTCR_TABORT_Pos) /*!< 0x000F0000 */ +#define PTACONV_ACTCR_TABORT PTACONV_ACTCR_TABORT_Msk /*!< PTA_ACTIVE delay to cease an ongoing transmission in us */ +#define PTACONV_ACTCR_ABORTDIS_Pos (20U) +#define PTACONV_ACTCR_ABORTDIS_Msk (0x1UL << PTACONV_ACTCR_ABORTDIS_Pos) /*!< 0x00100000 */ +#define PTACONV_ACTCR_ABORTDIS PTACONV_ACTCR_ABORTDIS_Msk /*!< Disable PTA_ACTIVE deny to abort an ongoing transmission */ + +/****************** Bit definition for PTACONV_PRICR register ***************/ +#define PTACONV_PRICR_TPRIORITY_Pos (0U) +#define PTACONV_PRICR_TPRIORITY_Msk (0x1FUL << PTACONV_PRICR_TPRIORITY_Pos) /*!< 0x0000001F */ +#define PTACONV_PRICR_TPRIORITY PTACONV_PRICR_TPRIORITY_Msk /*!< Priority valid time in us */ +#define PTACONV_PRICR_PRIPOL_Pos (15U) +#define PTACONV_PRICR_PRIPOL_Msk (0x1UL << PTACONV_PRICR_PRIPOL_Pos) /*!< 0x00008000 */ +#define PTACONV_PRICR_PRIPOL PTACONV_PRICR_PRIPOL_Msk /*!< Priority polarity */ + +/****************** Bit definition for PTACONV_CR register ******************/ +#define PTACONV_CR_TXRXPOL_Pos (15U) +#define PTACONV_CR_TXRXPOL_Msk (0x1UL << PTACONV_CR_TXRXPOL_Pos) /*!< 0x00008000 */ +#define PTACONV_CR_TXRXPOL PTACONV_CR_TXRXPOL_Msk /*!< PTA_STATUS transmit and receive polarity */ +#define PTACONV_CR_GRANTPOL_Pos (31U) +#define PTACONV_CR_GRANTPOL_Msk (0x1UL << PTACONV_CR_GRANTPOL_Pos) /*!< 0x80000000 */ +#define PTACONV_CR_GRANTPOL PTACONV_CR_GRANTPOL_Msk /*!< PTA_GRANT polarity */ + + +/******************************************************************************/ +/* */ +/* Power Control */ +/* */ +/******************************************************************************/ +/******************** Bit definition for PWR_CR1 register *******************/ +#define PWR_CR1_LPMS_Pos (0U) +#define PWR_CR1_LPMS_Msk (0x7UL << PWR_CR1_LPMS_Pos) /*!< 0x00000007 */ +#define PWR_CR1_LPMS PWR_CR1_LPMS_Msk /*!< LPMS[2:0] Low-power mode selection field */ +#define PWR_CR1_LPMS_0 (0x1UL << PWR_CR1_LPMS_Pos) /*!< 0x00000001 */ +#define PWR_CR1_LPMS_1 (0x2UL << PWR_CR1_LPMS_Pos) /*!< 0x00000002 */ +#define PWR_CR1_LPMS_2 (0x4UL << PWR_CR1_LPMS_Pos) /*!< 0x00000004 */ +#define PWR_CR1_R2RSB1_Pos (5U) +#define PWR_CR1_R2RSB1_Msk (0x1UL << PWR_CR1_R2RSB1_Pos) /*!< 0x00000020 */ +#define PWR_CR1_R2RSB1 PWR_CR1_R2RSB1_Msk /*!< SRAM2 Retention in Standby */ +#define PWR_CR1_ULPMEN_Pos (7U) +#define PWR_CR1_ULPMEN_Msk (0x1UL << PWR_CR1_ULPMEN_Pos) /*!< 0x00000080 */ +#define PWR_CR1_ULPMEN PWR_CR1_ULPMEN_Msk /*!< BOR ultra-low power mode in Standby/Shutdown */ +#define PWR_CR1_RADIORSB_Pos (9U) +#define PWR_CR1_RADIORSB_Msk (0x1UL << PWR_CR1_RADIORSB_Pos) /*!< 0x00000200 */ +#define PWR_CR1_RADIORSB PWR_CR1_RADIORSB_Msk /*!< 2.4GHz RADIO SRAMs (TXRX and Sequence) and Sleep clock retention in Standby mode */ +#define PWR_CR1_R1RSB1_Pos (12U) +#define PWR_CR1_R1RSB1_Msk (0x1UL << PWR_CR1_R1RSB1_Pos) /*!< 0x00001000 */ +#define PWR_CR1_R1RSB1 PWR_CR1_R1RSB1_Msk /*!< SRAM1 Page 1 Retention in Standby */ + +/******************** Bit definition for PWR_CR2 register *******************/ +#define PWR_CR2_SRAM1PDS1_Pos (0U) +#define PWR_CR2_SRAM1PDS1_Msk (0x1UL << PWR_CR2_SRAM1PDS1_Pos) /*!< 0x00000001 */ +#define PWR_CR2_SRAM1PDS1 PWR_CR2_SRAM1PDS1_Msk /*!< SRAM1 Page 1 power-down in Stop modes */ +#define PWR_CR2_SRAM2PDS1_Pos (4U) +#define PWR_CR2_SRAM2PDS1_Msk (0x1UL << PWR_CR2_SRAM2PDS1_Pos) /*!< 0x00000010 */ +#define PWR_CR2_SRAM2PDS1 PWR_CR2_SRAM2PDS1_Msk /*!< SRAM2 power-down in Stop modes */ +#define PWR_CR2_ICRAMPDS_Pos (8U) +#define PWR_CR2_ICRAMPDS_Msk (0x1UL << PWR_CR2_ICRAMPDS_Pos) /*!< 0x00000100 */ +#define PWR_CR2_ICRAMPDS PWR_CR2_ICRAMPDS_Msk /*!< ICACHE SRAM power-down in Stop modes */ +#define PWR_CR2_FLASHFWU_Pos (14U) +#define PWR_CR2_FLASHFWU_Msk (0x1UL << PWR_CR2_FLASHFWU_Pos) /*!< 0x00004000 */ +#define PWR_CR2_FLASHFWU PWR_CR2_FLASHFWU_Msk /*!< Flash low-power mode in Stop modes */ + +/******************** Bit definition for PWR_CR3 register *******************/ +#define PWR_CR3_FSTEN_Pos (2U) +#define PWR_CR3_FSTEN_Msk (0x1UL << PWR_CR3_FSTEN_Pos) /*!< 0x00000004 */ +#define PWR_CR3_FSTEN PWR_CR3_FSTEN_Msk /*!< Fast soft start */ + +/******************* Bit definition for PWR_VOSR register *******************/ +#define PWR_VOSR_VOSRDY_Pos (15U) +#define PWR_VOSR_VOSRDY_Msk (0x1UL << PWR_VOSR_VOSRDY_Pos) /*!< 0x00008000 */ +#define PWR_VOSR_VOSRDY PWR_VOSR_VOSRDY_Msk /*!< Ready bit for VCORE voltage scaling output selection */ +#define PWR_VOSR_VOS_Pos (16U) +#define PWR_VOSR_VOS_Msk (0x1UL << PWR_VOSR_VOS_Pos) /*!< 0x00010000 */ +#define PWR_VOSR_VOS PWR_VOSR_VOS_Msk /*!< Voltage scaling range selection */ + +/******************* Bit definition for PWR_SVMCR register ******************/ +#define PWR_SVMCR_PVDE_Pos (4U) +#define PWR_SVMCR_PVDE_Msk (0x1UL << PWR_SVMCR_PVDE_Pos) /*!< 0x00000010 */ +#define PWR_SVMCR_PVDE PWR_SVMCR_PVDE_Msk /*!< Power voltage detector enable */ +#define PWR_SVMCR_PVDLS_Pos (5U) +#define PWR_SVMCR_PVDLS_Msk (0x7UL << PWR_SVMCR_PVDLS_Pos) /*!< 0x000000E0 */ +#define PWR_SVMCR_PVDLS PWR_SVMCR_PVDLS_Msk /*!< PVDLS[2:0] Power voltage detector level selection field */ +#define PWR_SVMCR_PVDLS_0 (0x1UL << PWR_SVMCR_PVDLS_Pos) /*!< 0x00000020 */ +#define PWR_SVMCR_PVDLS_1 (0x2UL << PWR_SVMCR_PVDLS_Pos) /*!< 0x00000040 */ +#define PWR_SVMCR_PVDLS_2 (0x4UL << PWR_SVMCR_PVDLS_Pos) /*!< 0x00000080 */ + +/******************* Bit definition for PWR_WUCR1 register ******************/ +#define PWR_WUCR1_WUPEN1_Pos (0U) +#define PWR_WUCR1_WUPEN1_Msk (0x1UL << PWR_WUCR1_WUPEN1_Pos) /*!< 0x00000001 */ +#define PWR_WUCR1_WUPEN1 PWR_WUCR1_WUPEN1_Msk /*!< Wakeup pin WKUP1 enable */ +#define PWR_WUCR1_WUPEN2_Pos (1U) +#define PWR_WUCR1_WUPEN2_Msk (0x1UL << PWR_WUCR1_WUPEN2_Pos) /*!< 0x00000002 */ +#define PWR_WUCR1_WUPEN2 PWR_WUCR1_WUPEN2_Msk /*!< Wakeup pin WKUP2 enable */ +#define PWR_WUCR1_WUPEN3_Pos (2U) +#define PWR_WUCR1_WUPEN3_Msk (0x1UL << PWR_WUCR1_WUPEN3_Pos) /*!< 0x00000004 */ +#define PWR_WUCR1_WUPEN3 PWR_WUCR1_WUPEN3_Msk /*!< Wakeup pin WKUP3 enable */ +#define PWR_WUCR1_WUPEN4_Pos (3U) +#define PWR_WUCR1_WUPEN4_Msk (0x1UL << PWR_WUCR1_WUPEN4_Pos) /*!< 0x00000008 */ +#define PWR_WUCR1_WUPEN4 PWR_WUCR1_WUPEN4_Msk /*!< Wakeup pin WKUP4 enable */ +#define PWR_WUCR1_WUPEN5_Pos (4U) +#define PWR_WUCR1_WUPEN5_Msk (0x1UL << PWR_WUCR1_WUPEN5_Pos) /*!< 0x00000010 */ +#define PWR_WUCR1_WUPEN5 PWR_WUCR1_WUPEN5_Msk /*!< Wakeup pin WKUP5 enable */ +#define PWR_WUCR1_WUPEN6_Pos (5U) +#define PWR_WUCR1_WUPEN6_Msk (0x1UL << PWR_WUCR1_WUPEN6_Pos) /*!< 0x00000020 */ +#define PWR_WUCR1_WUPEN6 PWR_WUCR1_WUPEN6_Msk /*!< Wakeup pin WKUP6 enable */ +#define PWR_WUCR1_WUPEN7_Pos (6U) +#define PWR_WUCR1_WUPEN7_Msk (0x1UL << PWR_WUCR1_WUPEN7_Pos) /*!< 0x00000040 */ +#define PWR_WUCR1_WUPEN7 PWR_WUCR1_WUPEN7_Msk /*!< Wakeup pin WKUP7 enable */ +#define PWR_WUCR1_WUPEN8_Pos (7U) +#define PWR_WUCR1_WUPEN8_Msk (0x1UL << PWR_WUCR1_WUPEN8_Pos) /*!< 0x00000080 */ +#define PWR_WUCR1_WUPEN8 PWR_WUCR1_WUPEN8_Msk /*!< Wakeup pin WKUP8 enable */ + +/******************* Bit definition for PWR_WUCR2 register ******************/ +#define PWR_WUCR2_WUPP1_Pos (0U) +#define PWR_WUCR2_WUPP1_Msk (0x1UL << PWR_WUCR2_WUPP1_Pos) /*!< 0x00000001 */ +#define PWR_WUCR2_WUPP1 PWR_WUCR2_WUPP1_Msk /*!< Wakeup pin WKUP1 polarity */ +#define PWR_WUCR2_WUPP2_Pos (1U) +#define PWR_WUCR2_WUPP2_Msk (0x1UL << PWR_WUCR2_WUPP2_Pos) /*!< 0x00000002 */ +#define PWR_WUCR2_WUPP2 PWR_WUCR2_WUPP2_Msk /*!< Wakeup pin WKUP2 polarity */ +#define PWR_WUCR2_WUPP3_Pos (2U) +#define PWR_WUCR2_WUPP3_Msk (0x1UL << PWR_WUCR2_WUPP3_Pos) /*!< 0x00000004 */ +#define PWR_WUCR2_WUPP3 PWR_WUCR2_WUPP3_Msk /*!< Wakeup pin WKUP3 polarity */ +#define PWR_WUCR2_WUPP4_Pos (3U) +#define PWR_WUCR2_WUPP4_Msk (0x1UL << PWR_WUCR2_WUPP4_Pos) /*!< 0x00000008 */ +#define PWR_WUCR2_WUPP4 PWR_WUCR2_WUPP4_Msk /*!< Wakeup pin WKUP4 polarity */ +#define PWR_WUCR2_WUPP5_Pos (4U) +#define PWR_WUCR2_WUPP5_Msk (0x1UL << PWR_WUCR2_WUPP5_Pos) /*!< 0x00000010 */ +#define PWR_WUCR2_WUPP5 PWR_WUCR2_WUPP5_Msk /*!< Wakeup pin WKUP5 polarity */ +#define PWR_WUCR2_WUPP6_Pos (5U) +#define PWR_WUCR2_WUPP6_Msk (0x1UL << PWR_WUCR2_WUPP6_Pos) /*!< 0x00000020 */ +#define PWR_WUCR2_WUPP6 PWR_WUCR2_WUPP6_Msk /*!< Wakeup pin WKUP6 polarity */ +#define PWR_WUCR2_WUPP7_Pos (6U) +#define PWR_WUCR2_WUPP7_Msk (0x1UL << PWR_WUCR2_WUPP7_Pos) /*!< 0x00000040 */ +#define PWR_WUCR2_WUPP7 PWR_WUCR2_WUPP7_Msk /*!< Wakeup pin WKUP7 polarity */ +#define PWR_WUCR2_WUPP8_Pos (7U) +#define PWR_WUCR2_WUPP8_Msk (0x1UL << PWR_WUCR2_WUPP8_Pos) /*!< 0x00000080 */ +#define PWR_WUCR2_WUPP8 PWR_WUCR2_WUPP8_Msk /*!< Wakeup pin WKUP8 polarity */ + +/******************* Bit definition for PWR_WUCR3 register ******************/ +#define PWR_WUCR3_WUSEL1_Pos (0U) +#define PWR_WUCR3_WUSEL1_Msk (0x3UL << PWR_WUCR3_WUSEL1_Pos) /*!< 0x00000003 */ +#define PWR_WUCR3_WUSEL1 PWR_WUCR3_WUSEL1_Msk /*!< Wakeup pin WKUP1 selection field */ +#define PWR_WUCR3_WUSEL1_0 (0x1UL << PWR_WUCR3_WUSEL1_Pos) /*!< 0x00000001 */ +#define PWR_WUCR3_WUSEL1_1 (0x2UL << PWR_WUCR3_WUSEL1_Pos) /*!< 0x00000002 */ +#define PWR_WUCR3_WUSEL2_Pos (2U) +#define PWR_WUCR3_WUSEL2_Msk (0x3UL << PWR_WUCR3_WUSEL2_Pos) /*!< 0x0000000C */ +#define PWR_WUCR3_WUSEL2 PWR_WUCR3_WUSEL2_Msk /*!< Wakeup pin WKUP2 selection field */ +#define PWR_WUCR3_WUSEL2_0 (0x1UL << PWR_WUCR3_WUSEL2_Pos) /*!< 0x00000004 */ +#define PWR_WUCR3_WUSEL2_1 (0x2UL << PWR_WUCR3_WUSEL2_Pos) /*!< 0x00000008 */ +#define PWR_WUCR3_WUSEL3_Pos (4U) +#define PWR_WUCR3_WUSEL3_Msk (0x3UL << PWR_WUCR3_WUSEL3_Pos) /*!< 0x00000030 */ +#define PWR_WUCR3_WUSEL3 PWR_WUCR3_WUSEL3_Msk /*!< Wakeup pin WKUP3 selection field */ +#define PWR_WUCR3_WUSEL3_0 (0x1UL << PWR_WUCR3_WUSEL3_Pos) /*!< 0x00000010 */ +#define PWR_WUCR3_WUSEL3_1 (0x2UL << PWR_WUCR3_WUSEL3_Pos) /*!< 0x00000020 */ +#define PWR_WUCR3_WUSEL4_Pos (6U) +#define PWR_WUCR3_WUSEL4_Msk (0x3UL << PWR_WUCR3_WUSEL4_Pos) /*!< 0x000000C0 */ +#define PWR_WUCR3_WUSEL4 PWR_WUCR3_WUSEL4_Msk /*!< Wakeup pin WKUP4 selection field */ +#define PWR_WUCR3_WUSEL4_0 (0x1UL << PWR_WUCR3_WUSEL4_Pos) /*!< 0x00000040 */ +#define PWR_WUCR3_WUSEL4_1 (0x2UL << PWR_WUCR3_WUSEL4_Pos) /*!< 0x00000080 */ +#define PWR_WUCR3_WUSEL5_Pos (8U) +#define PWR_WUCR3_WUSEL5_Msk (0x3UL << PWR_WUCR3_WUSEL5_Pos) /*!< 0x00000300 */ +#define PWR_WUCR3_WUSEL5 PWR_WUCR3_WUSEL5_Msk /*!< Wakeup pin WKUP5 selection field */ +#define PWR_WUCR3_WUSEL5_0 (0x1UL << PWR_WUCR3_WUSEL5_Pos) /*!< 0x00000100 */ +#define PWR_WUCR3_WUSEL5_1 (0x2UL << PWR_WUCR3_WUSEL5_Pos) /*!< 0x00000200 */ +#define PWR_WUCR3_WUSEL6_Pos (10U) +#define PWR_WUCR3_WUSEL6_Msk (0x3UL << PWR_WUCR3_WUSEL6_Pos) /*!< 0x00000C00 */ +#define PWR_WUCR3_WUSEL6 PWR_WUCR3_WUSEL6_Msk /*!< Wakeup pin WKUP6 selection field */ +#define PWR_WUCR3_WUSEL6_0 (0x1UL << PWR_WUCR3_WUSEL6_Pos) /*!< 0x00000400 */ +#define PWR_WUCR3_WUSEL6_1 (0x2UL << PWR_WUCR3_WUSEL6_Pos) /*!< 0x00000800 */ +#define PWR_WUCR3_WUSEL7_Pos (12U) +#define PWR_WUCR3_WUSEL7_Msk (0x3UL << PWR_WUCR3_WUSEL7_Pos) /*!< 0x00003000 */ +#define PWR_WUCR3_WUSEL7 PWR_WUCR3_WUSEL7_Msk /*!< Wakeup pin WKUP7 selection field */ +#define PWR_WUCR3_WUSEL7_0 (0x1UL << PWR_WUCR3_WUSEL7_Pos) /*!< 0x00001000 */ +#define PWR_WUCR3_WUSEL7_1 (0x2UL << PWR_WUCR3_WUSEL7_Pos) /*!< 0x00002000 */ +#define PWR_WUCR3_WUSEL8_Pos (14U) +#define PWR_WUCR3_WUSEL8_Msk (0x3UL << PWR_WUCR3_WUSEL8_Pos) /*!< 0x0000C000 */ +#define PWR_WUCR3_WUSEL8 PWR_WUCR3_WUSEL8_Msk /*!< Wakeup pin WKUP8 selection field */ +#define PWR_WUCR3_WUSEL8_0 (0x1UL << PWR_WUCR3_WUSEL8_Pos) /*!< 0x00004000 */ +#define PWR_WUCR3_WUSEL8_1 (0x2UL << PWR_WUCR3_WUSEL8_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for PWR_DBPR register ******************/ +#define PWR_DBPR_DBP_Pos (0U) +#define PWR_DBPR_DBP_Msk (0x1UL << PWR_DBPR_DBP_Pos) /*!< 0x00000001 */ +#define PWR_DBPR_DBP PWR_DBPR_DBP_Msk /*!< Disable backup domain write protection */ + +/******************* Bit definition for PWR_SECCFGR register ****************/ +#define PWR_SECCFGR_WUP1SEC_Pos (0U) +#define PWR_SECCFGR_WUP1SEC_Msk (0x1UL << PWR_SECCFGR_WUP1SEC_Pos) /*!< 0x00000001 */ +#define PWR_SECCFGR_WUP1SEC PWR_SECCFGR_WUP1SEC_Msk /*!< WUP1 secure protection */ +#define PWR_SECCFGR_WUP2SEC_Pos (1U) +#define PWR_SECCFGR_WUP2SEC_Msk (0x1UL << PWR_SECCFGR_WUP2SEC_Pos) /*!< 0x00000002 */ +#define PWR_SECCFGR_WUP2SEC PWR_SECCFGR_WUP2SEC_Msk /*!< WUP2 secure protection */ +#define PWR_SECCFGR_WUP3SEC_Pos (2U) +#define PWR_SECCFGR_WUP3SEC_Msk (0x1UL << PWR_SECCFGR_WUP3SEC_Pos) /*!< 0x00000004 */ +#define PWR_SECCFGR_WUP3SEC PWR_SECCFGR_WUP3SEC_Msk /*!< WUP3 secure protection */ +#define PWR_SECCFGR_WUP4SEC_Pos (3U) +#define PWR_SECCFGR_WUP4SEC_Msk (0x1UL << PWR_SECCFGR_WUP4SEC_Pos) /*!< 0x00000008 */ +#define PWR_SECCFGR_WUP4SEC PWR_SECCFGR_WUP4SEC_Msk /*!< WUP4 secure protection */ +#define PWR_SECCFGR_WUP5SEC_Pos (4U) +#define PWR_SECCFGR_WUP5SEC_Msk (0x1UL << PWR_SECCFGR_WUP5SEC_Pos) /*!< 0x00000010 */ +#define PWR_SECCFGR_WUP5SEC PWR_SECCFGR_WUP5SEC_Msk /*!< WUP5 secure protection */ +#define PWR_SECCFGR_WUP6SEC_Pos (5U) +#define PWR_SECCFGR_WUP6SEC_Msk (0x1UL << PWR_SECCFGR_WUP6SEC_Pos) /*!< 0x00000020 */ +#define PWR_SECCFGR_WUP6SEC PWR_SECCFGR_WUP6SEC_Msk /*!< WUP6 secure protection */ +#define PWR_SECCFGR_WUP7SEC_Pos (6U) +#define PWR_SECCFGR_WUP7SEC_Msk (0x1UL << PWR_SECCFGR_WUP7SEC_Pos) /*!< 0x00000040 */ +#define PWR_SECCFGR_WUP7SEC PWR_SECCFGR_WUP7SEC_Msk /*!< WUP7 secure protection */ +#define PWR_SECCFGR_WUP8SEC_Pos (7U) +#define PWR_SECCFGR_WUP8SEC_Msk (0x1UL << PWR_SECCFGR_WUP8SEC_Pos) /*!< 0x00000080 */ +#define PWR_SECCFGR_WUP8SEC PWR_SECCFGR_WUP8SEC_Msk /*!< WUP8 secure protection */ +#define PWR_SECCFGR_LPMSEC_Pos (12U) +#define PWR_SECCFGR_LPMSEC_Msk (0x1UL << PWR_SECCFGR_LPMSEC_Pos) /*!< 0x00001000 */ +#define PWR_SECCFGR_LPMSEC PWR_SECCFGR_LPMSEC_Msk /*!< Low-power modes secure protection */ +#define PWR_SECCFGR_VDMSEC_Pos (13U) +#define PWR_SECCFGR_VDMSEC_Msk (0x1UL << PWR_SECCFGR_VDMSEC_Pos) /*!< 0x00002000 */ +#define PWR_SECCFGR_VDMSEC PWR_SECCFGR_VDMSEC_Msk /*!< Voltage detection and monitoring secure protection */ +#define PWR_SECCFGR_VBSEC_Pos (14U) +#define PWR_SECCFGR_VBSEC_Msk (0x1UL << PWR_SECCFGR_VBSEC_Pos) /*!< 0x00004000 */ +#define PWR_SECCFGR_VBSEC PWR_SECCFGR_VBSEC_Msk /*!< Backup domain secure protection */ + +/******************* Bit definition for PWR_PRIVCFGR register ***************/ +#define PWR_PRIVCFGR_SPRIV_Pos (0U) +#define PWR_PRIVCFGR_SPRIV_Msk (0x1UL << PWR_PRIVCFGR_SPRIV_Pos) /*!< 0x00000001 */ +#define PWR_PRIVCFGR_SPRIV PWR_PRIVCFGR_SPRIV_Msk /*!< RCC secure functions privilege configuration */ +#define PWR_PRIVCFGR_NSPRIV_Pos (1U) +#define PWR_PRIVCFGR_NSPRIV_Msk (0x1UL << PWR_PRIVCFGR_NSPRIV_Pos) /*!< 0x00000002 */ +#define PWR_PRIVCFGR_NSPRIV PWR_PRIVCFGR_NSPRIV_Msk /*!< RCC non-secure functions privilege configuration */ + +/********************** Bit definition for PWR_SR register ******************/ +#define PWR_SR_CSSF_Pos (0U) +#define PWR_SR_CSSF_Msk (0x1UL << PWR_SR_CSSF_Pos) /*!< 0x00000001 */ +#define PWR_SR_CSSF PWR_SR_CSSF_Msk /*!< Clear Stop and Standby/Shutdown flags */ +#define PWR_SR_STOPF_Pos (1U) +#define PWR_SR_STOPF_Msk (0x1UL << PWR_SR_STOPF_Pos) /*!< 0x00000002 */ +#define PWR_SR_STOPF PWR_SR_STOPF_Msk /*!< Stop flag */ +#define PWR_SR_SBF_Pos (2U) +#define PWR_SR_SBF_Msk (0x1UL << PWR_SR_SBF_Pos) /*!< 0x00000004 */ +#define PWR_SR_SBF PWR_SR_SBF_Msk /*!< Standby/Shutdown flag */ + +/******************** Bit definition for PWR_SVMSR register *****************/ +#define PWR_SVMSR_PVDO_Pos (4U) +#define PWR_SVMSR_PVDO_Msk (0x1UL << PWR_SVMSR_PVDO_Pos) /*!< 0x00000010 */ +#define PWR_SVMSR_PVDO PWR_SVMSR_PVDO_Msk /*!< VDD voltage detector output */ +#define PWR_SVMSR_ACTVOSRDY_Pos (15U) +#define PWR_SVMSR_ACTVOSRDY_Msk (0x1UL << PWR_SVMSR_ACTVOSRDY_Pos) /*!< 0x00008000 */ +#define PWR_SVMSR_ACTVOSRDY PWR_SVMSR_ACTVOSRDY_Msk /*!< Voltage level ready for currently used VOS */ +#define PWR_SVMSR_ACTVOS_Pos (16U) +#define PWR_SVMSR_ACTVOS_Msk (0x1UL << PWR_SVMSR_ACTVOS_Pos) /*!< 0x00010000 */ +#define PWR_SVMSR_ACTVOS PWR_SVMSR_ACTVOS_Msk /*!< Voltage Output Scaling currently applied to VCORE */ + +/********************* Bit definition for PWR_WUSR register *****************/ +#define PWR_WUSR_WUF1_Pos (0U) +#define PWR_WUSR_WUF1_Msk (0x1UL << PWR_WUSR_WUF1_Pos) /*!< 0x00000001 */ +#define PWR_WUSR_WUF1 PWR_WUSR_WUF1_Msk /*!< Wakeup flag 1 */ +#define PWR_WUSR_WUF2_Pos (1U) +#define PWR_WUSR_WUF2_Msk (0x1UL << PWR_WUSR_WUF2_Pos) /*!< 0x00000002 */ +#define PWR_WUSR_WUF2 PWR_WUSR_WUF2_Msk /*!< Wakeup flag 2 */ +#define PWR_WUSR_WUF3_Pos (2U) +#define PWR_WUSR_WUF3_Msk (0x1UL << PWR_WUSR_WUF3_Pos) /*!< 0x00000004 */ +#define PWR_WUSR_WUF3 PWR_WUSR_WUF3_Msk /*!< Wakeup flag 3 */ +#define PWR_WUSR_WUF4_Pos (3U) +#define PWR_WUSR_WUF4_Msk (0x1UL << PWR_WUSR_WUF4_Pos) /*!< 0x00000008 */ +#define PWR_WUSR_WUF4 PWR_WUSR_WUF4_Msk /*!< Wakeup flag 4 */ +#define PWR_WUSR_WUF5_Pos (4U) +#define PWR_WUSR_WUF5_Msk (0x1UL << PWR_WUSR_WUF5_Pos) /*!< 0x00000010 */ +#define PWR_WUSR_WUF5 PWR_WUSR_WUF5_Msk /*!< Wakeup flag 5 */ +#define PWR_WUSR_WUF6_Pos (5U) +#define PWR_WUSR_WUF6_Msk (0x1UL << PWR_WUSR_WUF6_Pos) /*!< 0x00000020 */ +#define PWR_WUSR_WUF6 PWR_WUSR_WUF6_Msk /*!< Wakeup flag 6 */ +#define PWR_WUSR_WUF7_Pos (6U) +#define PWR_WUSR_WUF7_Msk (0x1UL << PWR_WUSR_WUF7_Pos) /*!< 0x00000040 */ +#define PWR_WUSR_WUF7 PWR_WUSR_WUF7_Msk /*!< Wakeup flag 7 */ +#define PWR_WUSR_WUF8_Pos (7U) +#define PWR_WUSR_WUF8_Msk (0x1UL << PWR_WUSR_WUF8_Pos) /*!< 0x00000080 */ +#define PWR_WUSR_WUF8 PWR_WUSR_WUF8_Msk /*!< Wakeup flag 8 */ +#define PWR_WUSR_WUF_Pos (0U) +#define PWR_WUSR_WUF_Msk (0xFFUL << PWR_WUSR_WUF_Pos) /*!< 0x000000FF */ +#define PWR_WUSR_WUF PWR_WUSR_WUF_Msk /*!< all Wakeup flag */ + +/********************* Bit definition for PWR_WUSCR register ****************/ +#define PWR_WUSCR_CWUF1_Pos (0U) +#define PWR_WUSCR_CWUF1_Msk (0x1UL << PWR_WUSCR_CWUF1_Pos) /*!< 0x00000001*/ +#define PWR_WUSCR_CWUF1 PWR_WUSCR_CWUF1_Msk /*!< Wakeup clear flag 1 */ +#define PWR_WUSCR_CWUF2_Pos (1U) +#define PWR_WUSCR_CWUF2_Msk (0x1UL << PWR_WUSCR_CWUF2_Pos) /*!< 0x00000002 */ +#define PWR_WUSCR_CWUF2 PWR_WUSCR_CWUF2_Msk /*!< Wakeup clear flag 2 */ +#define PWR_WUSCR_CWUF3_Pos (2U) +#define PWR_WUSCR_CWUF3_Msk (0x1UL << PWR_WUSCR_CWUF3_Pos) /*!< 0x00000004 */ +#define PWR_WUSCR_CWUF3 PWR_WUSCR_CWUF3_Msk /*!< Wakeup clear flag 3 */ +#define PWR_WUSCR_CWUF4_Pos (3U) +#define PWR_WUSCR_CWUF4_Msk (0x1UL << PWR_WUSCR_CWUF4_Pos) /*!< 0x00000008 */ +#define PWR_WUSCR_CWUF4 PWR_WUSCR_CWUF4_Msk /*!< Wakeup clear flag 4 */ +#define PWR_WUSCR_CWUF5_Pos (4U) +#define PWR_WUSCR_CWUF5_Msk (0x1UL << PWR_WUSCR_CWUF5_Pos) /*!< 0x00000010 */ +#define PWR_WUSCR_CWUF5 PWR_WUSCR_CWUF5_Msk /*!< Wakeup clear flag 5 */ +#define PWR_WUSCR_CWUF6_Pos (5U) +#define PWR_WUSCR_CWUF6_Msk (0x1UL << PWR_WUSCR_CWUF6_Pos) /*!< 0x00000020 */ +#define PWR_WUSCR_CWUF6 PWR_WUSCR_CWUF6_Msk /*!< Wakeup clear flag 6 */ +#define PWR_WUSCR_CWUF7_Pos (6U) +#define PWR_WUSCR_CWUF7_Msk (0x1UL << PWR_WUSCR_CWUF7_Pos) /*!< 0x00000040 */ +#define PWR_WUSCR_CWUF7 PWR_WUSCR_CWUF7_Msk /*!< Wakeup clear flag 7 */ +#define PWR_WUSCR_CWUF8_Pos (7U) +#define PWR_WUSCR_CWUF8_Msk (0x1UL << PWR_WUSCR_CWUF8_Pos) /*!< 0x00000080 */ +#define PWR_WUSCR_CWUF8 PWR_WUSCR_CWUF8_Msk /*!< Wakeup clear flag 8 */ +#define PWR_WUSCR_CWUF_Pos (0U) +#define PWR_WUSCR_CWUF_Msk (0xFFUL << PWR_WUSCR_CWUF1_Pos) /*!< 0x000000FF */ +#define PWR_WUSCR_CWUF PWR_WUSCR_CWUF_Msk /*!< all Wakeup clear flag */ + +/******************** Bit definition for PWR_IORETENRA register *****************/ +#define PWR_IORETENRA_EN0_Pos (0U) +#define PWR_IORETENRA_EN0_Msk (0x1UL << PWR_IORETENRA_EN0_Pos) /*!< 0x00000001 */ +#define PWR_IORETENRA_EN0 PWR_IORETENRA_EN0_Msk /*!< Standby GPIO retention enable for PA0 */ +#define PWR_IORETENRA_EN1_Pos (1U) +#define PWR_IORETENRA_EN1_Msk (0x1UL << PWR_IORETENRA_EN1_Pos) /*!< 0x00000002 */ +#define PWR_IORETENRA_EN1 PWR_IORETENRA_EN1_Msk /*!< Standby GPIO retention enable for PA1 */ +#define PWR_IORETENRA_EN2_Pos (2U) +#define PWR_IORETENRA_EN2_Msk (0x1UL << PWR_IORETENRA_EN2_Pos) /*!< 0x00000004 */ +#define PWR_IORETENRA_EN2 PWR_IORETENRA_EN2_Msk /*!< Standby GPIO retention enable for PA2 */ +#define PWR_IORETENRA_EN3_Pos (3U) +#define PWR_IORETENRA_EN3_Msk (0x1UL << PWR_IORETENRA_EN3_Pos) /*!< 0x00000008 */ +#define PWR_IORETENRA_EN3 PWR_IORETENRA_EN3_Msk /*!< Standby GPIO retention enable for PA3 */ +#define PWR_IORETENRA_EN4_Pos (4U) +#define PWR_IORETENRA_EN4_Msk (0x1UL << PWR_IORETENRA_EN4_Pos) /*!< 0x00000010 */ +#define PWR_IORETENRA_EN4 PWR_IORETENRA_EN4_Msk /*!< Standby GPIO retention enable for PA4 */ +#define PWR_IORETENRA_EN5_Pos (5U) +#define PWR_IORETENRA_EN5_Msk (0x1UL << PWR_IORETENRA_EN5_Pos) /*!< 0x00000020 */ +#define PWR_IORETENRA_EN5 PWR_IORETENRA_EN5_Msk /*!< Standby GPIO retention enable for PA5 */ +#define PWR_IORETENRA_EN6_Pos (6U) +#define PWR_IORETENRA_EN6_Msk (0x1UL << PWR_IORETENRA_EN6_Pos) /*!< 0x00000040 */ +#define PWR_IORETENRA_EN6 PWR_IORETENRA_EN6_Msk /*!< Standby GPIO retention enable for PA6 */ +#define PWR_IORETENRA_EN7_Pos (7U) +#define PWR_IORETENRA_EN7_Msk (0x1UL << PWR_IORETENRA_EN7_Pos) /*!< 0x00000080 */ +#define PWR_IORETENRA_EN7 PWR_IORETENRA_EN7_Msk /*!< Standby GPIO retention enable for PA7 */ +#define PWR_IORETENRA_EN8_Pos (8U) +#define PWR_IORETENRA_EN8_Msk (0x1UL << PWR_IORETENRA_EN8_Pos) /*!< 0x00000100 */ +#define PWR_IORETENRA_EN8 PWR_IORETENRA_EN8_Msk /*!< Standby GPIO retention enable for PA8 */ +#define PWR_IORETENRA_EN9_Pos (9U) +#define PWR_IORETENRA_EN9_Msk (0x1UL << PWR_IORETENRA_EN9_Pos) /*!< 0x00000200 */ +#define PWR_IORETENRA_EN9 PWR_IORETENRA_EN9_Msk /*!< Standby GPIO retention enable for PA9 */ +#define PWR_IORETENRA_EN10_Pos (10U) +#define PWR_IORETENRA_EN10_Msk (0x1UL << PWR_IORETENRA_EN10_Pos) /*!< 0x00000400 */ +#define PWR_IORETENRA_EN10 PWR_IORETENRA_EN10_Msk /*!< Standby GPIO retention enable for PA10 */ +#define PWR_IORETENRA_EN11_Pos (11U) +#define PWR_IORETENRA_EN11_Msk (0x1UL << PWR_IORETENRA_EN11_Pos) /*!< 0x00000800 */ +#define PWR_IORETENRA_EN11 PWR_IORETENRA_EN11_Msk /*!< Standby GPIO retention enable for PA11 */ +#define PWR_IORETENRA_EN12_Pos (12U) +#define PWR_IORETENRA_EN12_Msk (0x1UL << PWR_IORETENRA_EN12_Pos) /*!< 0x00001000 */ +#define PWR_IORETENRA_EN12 PWR_IORETENRA_EN12_Msk /*!< Standby GPIO retention enable for PA12 */ +#define PWR_IORETENRA_EN13_Pos (13U) +#define PWR_IORETENRA_EN13_Msk (0x1UL << PWR_IORETENRA_EN13_Pos) /*!< 0x00002000 */ +#define PWR_IORETENRA_EN13 PWR_IORETENRA_EN13_Msk /*!< Standby GPIO retention enable for PA13 */ +#define PWR_IORETENRA_EN14_Pos (14U) +#define PWR_IORETENRA_EN14_Msk (0x1UL << PWR_IORETENRA_EN14_Pos) /*!< 0x00004000 */ +#define PWR_IORETENRA_EN14 PWR_IORETENRA_EN14_Msk /*!< Standby GPIO retention enable for PA14 */ +#define PWR_IORETENRA_EN15_Pos (15U) +#define PWR_IORETENRA_EN15_Msk (0x1UL << PWR_IORETENRA_EN15_Pos) /*!< 0x00008000 */ +#define PWR_IORETENRA_EN15 PWR_IORETENRA_EN15_Msk /*!< Standby GPIO retention enable for PA15 */ + +/******************** Bit definition for PWR_IORETRA register *****************/ +#define PWR_IORETRA_RET0_Pos (0U) +#define PWR_IORETRA_RET0_Msk (0x1UL << PWR_IORETRA_RET0_Pos) /*!< 0x00000001 */ +#define PWR_IORETRA_RET0 PWR_IORETRA_RET0_Msk /*!< Standby GPIO retention status for PA0 */ +#define PWR_IORETRA_RET1_Pos (1U) +#define PWR_IORETRA_RET1_Msk (0x1UL << PWR_IORETRA_RET1_Pos) /*!< 0x00000002 */ +#define PWR_IORETRA_RET1 PWR_IORETRA_RET1_Msk /*!< Standby GPIO retention status for PA1 */ +#define PWR_IORETRA_RET2_Pos (2U) +#define PWR_IORETRA_RET2_Msk (0x1UL << PWR_IORETRA_RET2_Pos) /*!< 0x00000004 */ +#define PWR_IORETRA_RET2 PWR_IORETRA_RET2_Msk /*!< Standby GPIO retention status for PA2 */ +#define PWR_IORETRA_RET3_Pos (3U) +#define PWR_IORETRA_RET3_Msk (0x1UL << PWR_IORETRA_RET3_Pos) /*!< 0x00000008 */ +#define PWR_IORETRA_RET3 PWR_IORETRA_RET3_Msk /*!< Standby GPIO retention status for PA3 */ +#define PWR_IORETRA_RET4_Pos (4U) +#define PWR_IORETRA_RET4_Msk (0x1UL << PWR_IORETRA_RET4_Pos) /*!< 0x00000010 */ +#define PWR_IORETRA_RET4 PWR_IORETRA_RET4_Msk /*!< Standby GPIO retention status for PA4 */ +#define PWR_IORETRA_RET5_Pos (5U) +#define PWR_IORETRA_RET5_Msk (0x1UL << PWR_IORETRA_RET5_Pos) /*!< 0x00000020 */ +#define PWR_IORETRA_RET5 PWR_IORETRA_RET5_Msk /*!< Standby GPIO retention status for PA5 */ +#define PWR_IORETRA_RET6_Pos (6U) +#define PWR_IORETRA_RET6_Msk (0x1UL << PWR_IORETRA_RET6_Pos) /*!< 0x00000040 */ +#define PWR_IORETRA_RET6 PWR_IORETRA_RET6_Msk /*!< Standby GPIO retention status for PA6 */ +#define PWR_IORETRA_RET7_Pos (7U) +#define PWR_IORETRA_RET7_Msk (0x1UL << PWR_IORETRA_RET7_Pos) /*!< 0x00000080 */ +#define PWR_IORETRA_RET7 PWR_IORETRA_RET7_Msk /*!< Standby GPIO retention status for PA7 */ +#define PWR_IORETRA_RET8_Pos (8U) +#define PWR_IORETRA_RET8_Msk (0x1UL << PWR_IORETRA_RET8_Pos) /*!< 0x00000100 */ +#define PWR_IORETRA_RET8 PWR_IORETRA_RET8_Msk /*!< Standby GPIO retention status for PA8 */ +#define PWR_IORETRA_RET9_Pos (9U) +#define PWR_IORETRA_RET9_Msk (0x1UL << PWR_IORETRA_RET9_Pos) /*!< 0x00000200 */ +#define PWR_IORETRA_RET9 PWR_IORETRA_RET9_Msk /*!< Standby GPIO retention status for PA9 */ +#define PWR_IORETRA_RET10_Pos (10U) +#define PWR_IORETRA_RET10_Msk (0x1UL << PWR_IORETRA_RET10_Pos) /*!< 0x00000400 */ +#define PWR_IORETRA_RET10 PWR_IORETRA_RET10_Msk /*!< Standby GPIO retention status for PA10 */ +#define PWR_IORETRA_RET11_Pos (11U) +#define PWR_IORETRA_RET11_Msk (0x1UL << PWR_IORETRA_RET11_Pos) /*!< 0x00000800 */ +#define PWR_IORETRA_RET11 PWR_IORETRA_RET11_Msk /*!< Standby GPIO retention status for PA11 */ +#define PWR_IORETRA_RET12_Pos (12U) +#define PWR_IORETRA_RET12_Msk (0x1UL << PWR_IORETRA_RET12_Pos) /*!< 0x00001000 */ +#define PWR_IORETRA_RET12 PWR_IORETRA_RET12_Msk /*!< Standby GPIO retention status for PA12 */ +#define PWR_IORETRA_RET13_Pos (13U) +#define PWR_IORETRA_RET13_Msk (0x1UL << PWR_IORETRA_RET13_Pos) /*!< 0x00002000 */ +#define PWR_IORETRA_RET13 PWR_IORETRA_RET13_Msk /*!< Standby GPIO retention status for PA13 */ +#define PWR_IORETRA_RET14_Pos (14U) +#define PWR_IORETRA_RET14_Msk (0x1UL << PWR_IORETRA_RET14_Pos) /*!< 0x00004000 */ +#define PWR_IORETRA_RET14 PWR_IORETRA_RET14_Msk /*!< Standby GPIO retention status for PA14 */ +#define PWR_IORETRA_RET15_Pos (15U) +#define PWR_IORETRA_RET15_Msk (0x1UL << PWR_IORETRA_RET15_Pos) /*!< 0x00008000 */ +#define PWR_IORETRA_RET15 PWR_IORETRA_RET15_Msk /*!< Standby GPIO retention status for PA15 */ + +/******************** Bit definition for PWR_IORETENRB register *****************/ +#define PWR_IORETENRB_EN0_Pos (0U) +#define PWR_IORETENRB_EN0_Msk (0x1UL << PWR_IORETENRB_EN0_Pos) /*!< 0x00000001 */ +#define PWR_IORETENRB_EN0 PWR_IORETENRB_EN0_Msk /*!< Standby GPIO retention enable for PB0 */ +#define PWR_IORETENRB_EN1_Pos (1U) +#define PWR_IORETENRB_EN1_Msk (0x1UL << PWR_IORETENRB_EN1_Pos) /*!< 0x00000002 */ +#define PWR_IORETENRB_EN1 PWR_IORETENRB_EN1_Msk /*!< Standby GPIO retention enable for PB1 */ +#define PWR_IORETENRB_EN2_Pos (2U) +#define PWR_IORETENRB_EN2_Msk (0x1UL << PWR_IORETENRB_EN2_Pos) /*!< 0x00000004 */ +#define PWR_IORETENRB_EN2 PWR_IORETENRB_EN2_Msk /*!< Standby GPIO retention enable for PB2 */ +#define PWR_IORETENRB_EN3_Pos (3U) +#define PWR_IORETENRB_EN3_Msk (0x1UL << PWR_IORETENRB_EN3_Pos) /*!< 0x00000008 */ +#define PWR_IORETENRB_EN3 PWR_IORETENRB_EN3_Msk /*!< Standby GPIO retention enable for PB3 */ +#define PWR_IORETENRB_EN4_Pos (4U) +#define PWR_IORETENRB_EN4_Msk (0x1UL << PWR_IORETENRB_EN4_Pos) /*!< 0x00000010 */ +#define PWR_IORETENRB_EN4 PWR_IORETENRB_EN4_Msk /*!< Standby GPIO retention enable for PB4 */ +#define PWR_IORETENRB_EN5_Pos (5U) +#define PWR_IORETENRB_EN5_Msk (0x1UL << PWR_IORETENRB_EN5_Pos) /*!< 0x00000020 */ +#define PWR_IORETENRB_EN5 PWR_IORETENRB_EN5_Msk /*!< Standby GPIO retention enable for PB5 */ +#define PWR_IORETENRB_EN6_Pos (6U) +#define PWR_IORETENRB_EN6_Msk (0x1UL << PWR_IORETENRB_EN6_Pos) /*!< 0x00000040 */ +#define PWR_IORETENRB_EN6 PWR_IORETENRB_EN6_Msk /*!< Standby GPIO retention enable for PB6 */ +#define PWR_IORETENRB_EN7_Pos (7U) +#define PWR_IORETENRB_EN7_Msk (0x1UL << PWR_IORETENRB_EN7_Pos) /*!< 0x00000080 */ +#define PWR_IORETENRB_EN7 PWR_IORETENRB_EN7_Msk /*!< Standby GPIO retention enable for PB7 */ +#define PWR_IORETENRB_EN8_Pos (8U) +#define PWR_IORETENRB_EN8_Msk (0x1UL << PWR_IORETENRB_EN8_Pos) /*!< 0x00000100 */ +#define PWR_IORETENRB_EN8 PWR_IORETENRB_EN8_Msk /*!< Standby GPIO retention enable for PB8 */ +#define PWR_IORETENRB_EN9_Pos (9U) +#define PWR_IORETENRB_EN9_Msk (0x1UL << PWR_IORETENRB_EN9_Pos) /*!< 0x00000200 */ +#define PWR_IORETENRB_EN9 PWR_IORETENRB_EN9_Msk /*!< Standby GPIO retention enable for PB9 */ +#define PWR_IORETENRB_EN10_Pos (10U) +#define PWR_IORETENRB_EN10_Msk (0x1UL << PWR_IORETENRB_EN10_Pos) /*!< 0x00000400 */ +#define PWR_IORETENRB_EN10 PWR_IORETENRB_EN10_Msk /*!< Standby GPIO retention enable for PB10 */ +#define PWR_IORETENRB_EN11_Pos (11U) +#define PWR_IORETENRB_EN11_Msk (0x1UL << PWR_IORETENRB_EN11_Pos) /*!< 0x00000800 */ +#define PWR_IORETENRB_EN11 PWR_IORETENRB_EN11_Msk /*!< Standby GPIO retention enable for PB11 */ +#define PWR_IORETENRB_EN12_Pos (12U) +#define PWR_IORETENRB_EN12_Msk (0x1UL << PWR_IORETENRB_EN12_Pos) /*!< 0x00001000 */ +#define PWR_IORETENRB_EN12 PWR_IORETENRB_EN12_Msk /*!< Standby GPIO retention enable for PB12 */ +#define PWR_IORETENRB_EN13_Pos (13U) +#define PWR_IORETENRB_EN13_Msk (0x1UL << PWR_IORETENRB_EN13_Pos) /*!< 0x00002000 */ +#define PWR_IORETENRB_EN13 PWR_IORETENRB_EN13_Msk /*!< Standby GPIO retention enable for PB13 */ +#define PWR_IORETENRB_EN14_Pos (14U) +#define PWR_IORETENRB_EN14_Msk (0x1UL << PWR_IORETENRB_EN14_Pos) /*!< 0x00004000 */ +#define PWR_IORETENRB_EN14 PWR_IORETENRB_EN14_Msk /*!< Standby GPIO retention enable for PB14 */ +#define PWR_IORETENRB_EN15_Pos (15U) +#define PWR_IORETENRB_EN15_Msk (0x1UL << PWR_IORETENRB_EN15_Pos) /*!< 0x00008000 */ +#define PWR_IORETENRB_EN15 PWR_IORETENRB_EN15_Msk /*!< Standby GPIO retention enable for PB15 */ + +/******************** Bit definition for PWR_IORETRB register *****************/ +#define PWR_IORETRB_RET0_Pos (0U) +#define PWR_IORETRB_RET0_Msk (0x1UL << PWR_IORETRB_RET0_Pos) /*!< 0x00000001 */ +#define PWR_IORETRB_RET0 PWR_IORETRB_RET0_Msk /*!< Standby GPIO retention status for PB0 */ +#define PWR_IORETRB_RET1_Pos (1U) +#define PWR_IORETRB_RET1_Msk (0x1UL << PWR_IORETRB_RET1_Pos) /*!< 0x00000002 */ +#define PWR_IORETRB_RET1 PWR_IORETRB_RET1_Msk /*!< Standby GPIO retention status for PB1 */ +#define PWR_IORETRB_RET2_Pos (2U) +#define PWR_IORETRB_RET2_Msk (0x1UL << PWR_IORETRB_RET2_Pos) /*!< 0x00000004 */ +#define PWR_IORETRB_RET2 PWR_IORETRB_RET2_Msk /*!< Standby GPIO retention status for PB2 */ +#define PWR_IORETRB_RET3_Pos (3U) +#define PWR_IORETRB_RET3_Msk (0x1UL << PWR_IORETRB_RET3_Pos) /*!< 0x00000008 */ +#define PWR_IORETRB_RET3 PWR_IORETRB_RET3_Msk /*!< Standby GPIO retention status for PB3 */ +#define PWR_IORETRB_RET4_Pos (4U) +#define PWR_IORETRB_RET4_Msk (0x1UL << PWR_IORETRB_RET4_Pos) /*!< 0x00000010 */ +#define PWR_IORETRB_RET4 PWR_IORETRB_RET4_Msk /*!< Standby GPIO retention status for PB4 */ +#define PWR_IORETRB_RET5_Pos (5U) +#define PWR_IORETRB_RET5_Msk (0x1UL << PWR_IORETRB_RET5_Pos) /*!< 0x00000020 */ +#define PWR_IORETRB_RET5 PWR_IORETRB_RET5_Msk /*!< Standby GPIO retention status for PB5 */ +#define PWR_IORETRB_RET6_Pos (6U) +#define PWR_IORETRB_RET6_Msk (0x1UL << PWR_IORETRB_RET6_Pos) /*!< 0x00000040 */ +#define PWR_IORETRB_RET6 PWR_IORETRB_RET6_Msk /*!< Standby GPIO retention status for PB6 */ +#define PWR_IORETRB_RET7_Pos (7U) +#define PWR_IORETRB_RET7_Msk (0x1UL << PWR_IORETRB_RET7_Pos) /*!< 0x00000080 */ +#define PWR_IORETRB_RET7 PWR_IORETRB_RET7_Msk /*!< Standby GPIO retention status for PB7 */ +#define PWR_IORETRB_RET8_Pos (8U) +#define PWR_IORETRB_RET8_Msk (0x1UL << PWR_IORETRB_RET8_Pos) /*!< 0x00000100 */ +#define PWR_IORETRB_RET8 PWR_IORETRB_RET8_Msk /*!< Standby GPIO retention status for PB8 */ +#define PWR_IORETRB_RET9_Pos (9U) +#define PWR_IORETRB_RET9_Msk (0x1UL << PWR_IORETRB_RET9_Pos) /*!< 0x00000200 */ +#define PWR_IORETRB_RET9 PWR_IORETRB_RET9_Msk /*!< Standby GPIO retention status for PB9 */ +#define PWR_IORETRB_RET10_Pos (10U) +#define PWR_IORETRB_RET10_Msk (0x1UL << PWR_IORETRB_RET10_Pos) /*!< 0x00000400 */ +#define PWR_IORETRB_RET10 PWR_IORETRB_RET10_Msk /*!< Standby GPIO retention status for PB10 */ +#define PWR_IORETRB_RET11_Pos (11U) +#define PWR_IORETRB_RET11_Msk (0x1UL << PWR_IORETRB_RET11_Pos) /*!< 0x00000800 */ +#define PWR_IORETRB_RET11 PWR_IORETRB_RET11_Msk /*!< Standby GPIO retention status for PB11 */ +#define PWR_IORETRB_RET12_Pos (12U) +#define PWR_IORETRB_RET12_Msk (0x1UL << PWR_IORETRB_RET12_Pos) /*!< 0x00001000 */ +#define PWR_IORETRB_RET12 PWR_IORETRB_RET12_Msk /*!< Standby GPIO retention status for PB12 */ +#define PWR_IORETRB_RET13_Pos (13U) +#define PWR_IORETRB_RET13_Msk (0x1UL << PWR_IORETRB_RET13_Pos) /*!< 0x00002000 */ +#define PWR_IORETRB_RET13 PWR_IORETRB_RET13_Msk /*!< Standby GPIO retention status for PB13 */ +#define PWR_IORETRB_RET14_Pos (14U) +#define PWR_IORETRB_RET14_Msk (0x1UL << PWR_IORETRB_RET14_Pos) /*!< 0x00004000 */ +#define PWR_IORETRB_RET14 PWR_IORETRB_RET14_Msk /*!< Standby GPIO retention status for PB14 */ +#define PWR_IORETRB_RET15_Pos (15U) +#define PWR_IORETRB_RET15_Msk (0x1UL << PWR_IORETRB_RET15_Pos) /*!< 0x00008000 */ +#define PWR_IORETRB_RET15 PWR_IORETRB_RET15_Msk /*!< Standby GPIO retention status for PB15 */ + +/******************** Bit definition for PWR_IORETENRC register *****************/ +#define PWR_IORETENRC_EN13_Pos (13U) +#define PWR_IORETENRC_EN13_Msk (0x1UL << PWR_IORETENRC_EN13_Pos) /*!< 0x00002000 */ +#define PWR_IORETENRC_EN13 PWR_IORETENRC_EN13_Msk /*!< Standby GPIO retention enable for PC13 */ +#define PWR_IORETENRC_EN14_Pos (14U) +#define PWR_IORETENRC_EN14_Msk (0x1UL << PWR_IORETENRC_EN14_Pos) /*!< 0x00004000 */ +#define PWR_IORETENRC_EN14 PWR_IORETENRC_EN14_Msk /*!< Standby GPIO retention enable for PC14 */ +#define PWR_IORETENRC_EN15_Pos (15U) +#define PWR_IORETENRC_EN15_Msk (0x1UL << PWR_IORETENRC_EN15_Pos) /*!< 0x00008000 */ +#define PWR_IORETENRC_EN15 PWR_IORETENRC_EN15_Msk /*!< Standby GPIO retention enable for PC15 */ + +/******************** Bit definition for PWR_IORETRC register *****************/ +#define PWR_IORETRC_RET13_Pos (13U) +#define PWR_IORETRC_RET13_Msk (0x1UL << PWR_IORETRC_RET13_Pos) /*!< 0x00002000 */ +#define PWR_IORETRC_RET13 PWR_IORETRC_RET13_Msk /*!< Standby GPIO retention status for PC13 */ +#define PWR_IORETRC_RET14_Pos (14U) +#define PWR_IORETRC_RET14_Msk (0x1UL << PWR_IORETRC_RET14_Pos) /*!< 0x00004000 */ +#define PWR_IORETRC_RET14 PWR_IORETRC_RET14_Msk /*!< Standby GPIO retention status for PC14 */ +#define PWR_IORETRC_RET15_Pos (15U) +#define PWR_IORETRC_RET15_Msk (0x1UL << PWR_IORETRC_RET15_Pos) /*!< 0x00008000 */ +#define PWR_IORETRC_RET15 PWR_IORETRC_RET15_Msk /*!< Standby GPIO retention status for PC15 */ + +/******************** Bit definition for PWR_IORETENRH register *****************/ +#define PWR_IORETENRH_EN3_Pos (3U) +#define PWR_IORETENRH_EN3_Msk (0x1UL << PWR_IORETENRH_EN3_Pos) /*!< 0x00000008 */ +#define PWR_IORETENRH_EN3 PWR_IORETENRH_EN3_Msk /*!< Standby GPIO retention enable for PH3 */ + +/******************** Bit definition for PWR_IORETRH register *****************/ +#define PWR_IORETRH_RET3_Pos (3U) +#define PWR_IORETRH_RET3_Msk (0x1UL << PWR_IORETRH_RET3_Pos) /*!< 0x00000008 */ +#define PWR_IORETRH_RET3 PWR_IORETRH_RET3_Msk /*!< Standby GPIO retention status for PH3 */ + +/******************** Bit definition for PWR_RADIOSCR register *****************/ +#define PWR_RADIOSCR_MODE_Pos (0U) +#define PWR_RADIOSCR_MODE_Msk (0x3UL << PWR_RADIOSCR_MODE_Pos) /*!< 0x00000003 */ +#define PWR_RADIOSCR_MODE PWR_RADIOSCR_MODE_Msk /*!< 2.4 GHz RADIO operating mode */ +#define PWR_RADIOSCR_MODE_0 (0x1UL << PWR_RADIOSCR_MODE_Pos) /*!< 0x00000001 */ +#define PWR_RADIOSCR_MODE_1 (0x2UL << PWR_RADIOSCR_MODE_Pos) /*!< 0x00000002 */ +#define PWR_RADIOSCR_PHYMODE_Pos (2U) +#define PWR_RADIOSCR_PHYMODE_Msk (0x1UL << PWR_RADIOSCR_PHYMODE_Pos) /*!< 0x00000004 */ +#define PWR_RADIOSCR_PHYMODE PWR_RADIOSCR_PHYMODE_Msk /*!< 2.4 GHz RADIO PHY operating mode */ +#define PWR_RADIOSCR_ENCMODE_Pos (3U) +#define PWR_RADIOSCR_ENCMODE_Msk (0x1UL << PWR_RADIOSCR_ENCMODE_Pos) /*!< 0x00000008 */ +#define PWR_RADIOSCR_ENCMODE PWR_RADIOSCR_ENCMODE_Msk /*!< 2.4 GHz RADIO encryption function operating mode */ +#define PWR_RADIOSCR_RFVDDHPA_Pos (8U) +#define PWR_RADIOSCR_RFVDDHPA_Msk (0x1FUL << PWR_RADIOSCR_RFVDDHPA_Pos) /*!< 0x00001F00 */ +#define PWR_RADIOSCR_RFVDDHPA PWR_RADIOSCR_RFVDDHPA_Msk /*!< 2.4 GHz RADIO VDDHPA control word */ +#define PWR_RADIOSCR_REGPARDYVDDRFPA_Pos (15U) +#define PWR_RADIOSCR_REGPARDYVDDRFPA_Msk (0x1UL << PWR_RADIOSCR_REGPARDYVDDRFPA_Pos) /*!< 0x00008000 */ +#define PWR_RADIOSCR_REGPARDYVDDRFPA PWR_RADIOSCR_REGPARDYVDDRFPA_Msk /*!< Ready bit for VDDHPA voltage level when selecting VDDRFPA input */ + + +/******************************************************************************/ +/* */ +/* SRAMs configuration controller */ +/* */ +/******************************************************************************/ +/******************* Bit definition for RAMCFG_MxCR register ******************/ +#define RAMCFG_CR_ALE_Pos (4U) +#define RAMCFG_CR_ALE_Msk (0x1UL << RAMCFG_CR_ALE_Pos) /*!< 0x00000010 */ +#define RAMCFG_CR_ALE RAMCFG_CR_ALE_Msk /*!< Address Latching Enable */ +#define RAMCFG_CR_SRAMER_Pos (8U) +#define RAMCFG_CR_SRAMER_Msk (0x1UL << RAMCFG_CR_SRAMER_Pos) /*!< 0x00000100 */ +#define RAMCFG_CR_SRAMER RAMCFG_CR_SRAMER_Msk /*!< Start Erase */ +#define RAMCFG_CR_WSC_Pos (16U) +#define RAMCFG_CR_WSC_Msk (0x7UL << RAMCFG_CR_WSC_Pos) /*!< 0x00070000 */ +#define RAMCFG_CR_WSC RAMCFG_CR_WSC_Msk /*!< WSC[18:16] Wait State Configuration field */ +#define RAMCFG_CR_WSC_0 (0x1UL << RAMCFG_CR_WSC_Pos) /*!< 0x00010000 */ +#define RAMCFG_CR_WSC_1 (0x2UL << RAMCFG_CR_WSC_Pos) /*!< 0x00020000 */ +#define RAMCFG_CR_WSC_2 (0x4UL << RAMCFG_CR_WSC_Pos) /*!< 0x00040000 */ + +/******************* Bit definition for RAMCFG_MxISR register ******************/ +#define RAMCFG_ISR_PED_Pos (1U) +#define RAMCFG_ISR_PED_Msk (0x1UL << RAMCFG_ISR_PED_Pos) /*!< 0x00000002 */ +#define RAMCFG_ISR_PED RAMCFG_ISR_PED_Msk /*!< Parity error detected */ +#define RAMCFG_ISR_SRAMBUSY_Pos (8U) +#define RAMCFG_ISR_SRAMBUSY_Msk (0x1UL << RAMCFG_ISR_SRAMBUSY_Pos) /*!< 0x00000100 */ +#define RAMCFG_ISR_SRAMBUSY RAMCFG_ISR_SRAMBUSY_Msk /*!< SRAM busy with erase operation */ + +/***************** Bit definition for RAMCFG_MxERKEYR register ***************/ +#define RAMCFG_ERKEYR_ERASEKEY_Pos (0U) +#define RAMCFG_ERKEYR_ERASEKEY_Msk (0xFFUL << RAMCFG_ERKEYR_ERASEKEY_Pos) /*!< 0x000000FF */ +#define RAMCFG_ERKEYR_ERASEKEY RAMCFG_ERKEYR_ERASEKEY_Msk /*!< Erase write protection key */ + +/******************* Bit definition for RAMCFG_MxIER register ******************/ +#define RAMCFG_IER_PEIE_Pos (1U) +#define RAMCFG_IER_PEIE_Msk (0x1UL << RAMCFG_IER_PEIE_Pos) /*!< 0x00000001 */ +#define RAMCFG_IER_PEIE RAMCFG_IER_PEIE_Msk /*!< Parity error interrupt enable */ +#define RAMCFG_IER_PENMI_Pos (3U) +#define RAMCFG_IER_PENMI_Msk (0x1UL << RAMCFG_IER_PENMI_Pos) /*!< 0x00000004 */ +#define RAMCFG_IER_PENMI RAMCFG_IER_PENMI_Msk /*!< Parity error NMI */ + +/******************* Bit definition for RAMCFG_MxPEAR register ******************/ +#define RAMCFG_PEAR_PEA_Pos (0U) +#define RAMCFG_PEAR_PEA_Msk (0xFFFFUL << RAMCFG_PEAR_PEA_Pos) /*!< 0x0000FFFF */ +#define RAMCFG_PEAR_PEA RAMCFG_PEAR_PEA_Msk /*!< Parity error SRAM word aligned address offset */ +#define RAMCFG_PEAR_ID_Pos (24U) +#define RAMCFG_PEAR_ID_Msk (0xFUL << RAMCFG_PEAR_ID_Pos) /*!< 0x0F000000 */ +#define RAMCFG_PEAR_ID RAMCFG_PEAR_ID_Msk /*!< Parity error AHB bus master ID */ +#define RAMCFG_PEAR_BYTE_Pos (28U) +#define RAMCFG_PEAR_BYTE_Msk (0xFUL << RAMCFG_PEAR_BYTE_Pos) /*!< 0xF0000000 */ +#define RAMCFG_PEAR_BYTE RAMCFG_PEAR_BYTE_Msk /*!< Byte parity error flag */ + +/******************* Bit definition for RAMCFG_MxICR register *****************/ +#define RAMCFG_ICR_CPED_Pos (1U) +#define RAMCFG_ICR_CPED_Msk (0x1UL << RAMCFG_ICR_CPED_Pos) /*!< 0x00000002 */ +#define RAMCFG_ICR_CPED RAMCFG_ICR_CPED_Msk /*!< Clear parity error detect bit */ + +/****************** Bit definition for RAMCFG_MxWPR1 register *****************/ +#define RAMCFG_WPR1_P0WP_Pos (0U) +#define RAMCFG_WPR1_P0WP_Msk (0x1UL << RAMCFG_WPR1_P0WP_Pos) /*!< 0x00000001 */ +#define RAMCFG_WPR1_P0WP RAMCFG_WPR1_P0WP_Msk /*!< Write Protection Page 00 */ +#define RAMCFG_WPR1_P1WP_Pos (1U) +#define RAMCFG_WPR1_P1WP_Msk (0x1UL << RAMCFG_WPR1_P1WP_Pos) /*!< 0x00000002 */ +#define RAMCFG_WPR1_P1WP RAMCFG_WPR1_P1WP_Msk /*!< Write Protection Page 01 */ +#define RAMCFG_WPR1_P2WP_Pos (2U) +#define RAMCFG_WPR1_P2WP_Msk (0x1UL << RAMCFG_WPR1_P2WP_Pos) /*!< 0x00000004 */ +#define RAMCFG_WPR1_P2WP RAMCFG_WPR1_P2WP_Msk /*!< Write Protection Page 02 */ +#define RAMCFG_WPR1_P3WP_Pos (3U) +#define RAMCFG_WPR1_P3WP_Msk (0x1UL << RAMCFG_WPR1_P3WP_Pos) /*!< 0x00000008 */ +#define RAMCFG_WPR1_P3WP RAMCFG_WPR1_P3WP_Msk /*!< Write Protection Page 03 */ +#define RAMCFG_WPR1_P4WP_Pos (4U) +#define RAMCFG_WPR1_P4WP_Msk (0x1UL << RAMCFG_WPR1_P4WP_Pos) /*!< 0x00000010 */ +#define RAMCFG_WPR1_P4WP RAMCFG_WPR1_P4WP_Msk /*!< Write Protection Page 04 */ +#define RAMCFG_WPR1_P5WP_Pos (5U) +#define RAMCFG_WPR1_P5WP_Msk (0x1UL << RAMCFG_WPR1_P5WP_Pos) /*!< 0x00000020 */ +#define RAMCFG_WPR1_P5WP RAMCFG_WPR1_P5WP_Msk /*!< Write Protection Page 05 */ +#define RAMCFG_WPR1_P6WP_Pos (6U) +#define RAMCFG_WPR1_P6WP_Msk (0x1UL << RAMCFG_WPR1_P6WP_Pos) /*!< 0x00000040 */ +#define RAMCFG_WPR1_P6WP RAMCFG_WPR1_P6WP_Msk /*!< Write Protection Page 06 */ +#define RAMCFG_WPR1_P7WP_Pos (7U) +#define RAMCFG_WPR1_P7WP_Msk (0x1UL << RAMCFG_WPR1_P7WP_Pos) /*!< 0x00000080 */ +#define RAMCFG_WPR1_P7WP RAMCFG_WPR1_P7WP_Msk /*!< Write Protection Page 07 */ +#define RAMCFG_WPR1_P8WP_Pos (8U) +#define RAMCFG_WPR1_P8WP_Msk (0x1UL << RAMCFG_WPR1_P8WP_Pos) /*!< 0x00000100 */ +#define RAMCFG_WPR1_P8WP RAMCFG_WPR1_P8WP_Msk /*!< Write Protection Page 08 */ +#define RAMCFG_WPR1_P9WP_Pos (9U) +#define RAMCFG_WPR1_P9WP_Msk (0x1UL << RAMCFG_WPR1_P9WP_Pos) /*!< 0x00000200 */ +#define RAMCFG_WPR1_P9WP RAMCFG_WPR1_P9WP_Msk /*!< Write Protection Page 09 */ +#define RAMCFG_WPR1_P10WP_Pos (10U) +#define RAMCFG_WPR1_P10WP_Msk (0x1UL << RAMCFG_WPR1_P10WP_Pos) /*!< 0x00000400 */ +#define RAMCFG_WPR1_P10WP RAMCFG_WPR1_P10WP_Msk /*!< Write Protection Page 10 */ +#define RAMCFG_WPR1_P11WP_Pos (11U) +#define RAMCFG_WPR1_P11WP_Msk (0x1UL << RAMCFG_WPR1_P11WP_Pos) /*!< 0x00000800 */ +#define RAMCFG_WPR1_P11WP RAMCFG_WPR1_P11WP_Msk /*!< Write Protection Page 11 */ +#define RAMCFG_WPR1_P12WP_Pos (12U) +#define RAMCFG_WPR1_P12WP_Msk (0x1UL << RAMCFG_WPR1_P12WP_Pos) /*!< 0x00001000 */ +#define RAMCFG_WPR1_P12WP RAMCFG_WPR1_P12WP_Msk /*!< Write Protection Page 12 */ +#define RAMCFG_WPR1_P13WP_Pos (13U) +#define RAMCFG_WPR1_P13WP_Msk (0x1UL << RAMCFG_WPR1_P13WP_Pos) /*!< 0x00002000 */ +#define RAMCFG_WPR1_P13WP RAMCFG_WPR1_P13WP_Msk /*!< Write Protection Page 13 */ +#define RAMCFG_WPR1_P14WP_Pos (14U) +#define RAMCFG_WPR1_P14WP_Msk (0x1UL << RAMCFG_WPR1_P14WP_Pos) /*!< 0x00004000 */ +#define RAMCFG_WPR1_P14WP RAMCFG_WPR1_P14WP_Msk /*!< Write Protection Page 14 */ +#define RAMCFG_WPR1_P15WP_Pos (15U) +#define RAMCFG_WPR1_P15WP_Msk (0x1UL << RAMCFG_WPR1_P15WP_Pos) /*!< 0x00008000 */ +#define RAMCFG_WPR1_P15WP RAMCFG_WPR1_P15WP_Msk /*!< Write Protection Page 15 */ +#define RAMCFG_WPR1_P16WP_Pos (16U) +#define RAMCFG_WPR1_P16WP_Msk (0x1UL << RAMCFG_WPR1_P16WP_Pos) /*!< 0x00010000 */ +#define RAMCFG_WPR1_P16WP RAMCFG_WPR1_P16WP_Msk /*!< Write Protection Page 16 */ +#define RAMCFG_WPR1_P17WP_Pos (17U) +#define RAMCFG_WPR1_P17WP_Msk (0x1UL << RAMCFG_WPR1_P17WP_Pos) /*!< 0x00020000 */ +#define RAMCFG_WPR1_P17WP RAMCFG_WPR1_P17WP_Msk /*!< Write Protection Page 17 */ +#define RAMCFG_WPR1_P18WP_Pos (18U) +#define RAMCFG_WPR1_P18WP_Msk (0x1UL << RAMCFG_WPR1_P18WP_Pos) /*!< 0x00040000 */ +#define RAMCFG_WPR1_P18WP RAMCFG_WPR1_P18WP_Msk /*!< Write Protection Page 18 */ +#define RAMCFG_WPR1_P19WP_Pos (19U) +#define RAMCFG_WPR1_P19WP_Msk (0x1UL << RAMCFG_WPR1_P19WP_Pos) /*!< 0x00080000 */ +#define RAMCFG_WPR1_P19WP RAMCFG_WPR1_P19WP_Msk /*!< Write Protection Page 19 */ +#define RAMCFG_WPR1_P20WP_Pos (20U) +#define RAMCFG_WPR1_P20WP_Msk (0x1UL << RAMCFG_WPR1_P20WP_Pos) /*!< 0x00100000 */ +#define RAMCFG_WPR1_P20WP RAMCFG_WPR1_P20WP_Msk /*!< Write Protection Page 20 */ +#define RAMCFG_WPR1_P21WP_Pos (21U) +#define RAMCFG_WPR1_P21WP_Msk (0x1UL << RAMCFG_WPR1_P21WP_Pos) /*!< 0x00200000 */ +#define RAMCFG_WPR1_P21WP RAMCFG_WPR1_P21WP_Msk /*!< Write Protection Page 21 */ +#define RAMCFG_WPR1_P22WP_Pos (22U) +#define RAMCFG_WPR1_P22WP_Msk (0x1UL << RAMCFG_WPR1_P22WP_Pos) /*!< 0x00400000 */ +#define RAMCFG_WPR1_P22WP RAMCFG_WPR1_P22WP_Msk /*!< Write Protection Page 22 */ +#define RAMCFG_WPR1_P23WP_Pos (23U) +#define RAMCFG_WPR1_P23WP_Msk (0x1UL << RAMCFG_WPR1_P23WP_Pos) /*!< 0x00800000 */ +#define RAMCFG_WPR1_P23WP RAMCFG_WPR1_P23WP_Msk /*!< Write Protection Page 23 */ +#define RAMCFG_WPR1_P24WP_Pos (24U) +#define RAMCFG_WPR1_P24WP_Msk (0x1UL << RAMCFG_WPR1_P24WP_Pos) /*!< 0x01000000 */ +#define RAMCFG_WPR1_P24WP RAMCFG_WPR1_P24WP_Msk /*!< Write Protection Page 24 */ +#define RAMCFG_WPR1_P25WP_Pos (25U) +#define RAMCFG_WPR1_P25WP_Msk (0x1UL << RAMCFG_WPR1_P25WP_Pos) /*!< 0x02000000 */ +#define RAMCFG_WPR1_P25WP RAMCFG_WPR1_P25WP_Msk /*!< Write Protection Page 25 */ +#define RAMCFG_WPR1_P26WP_Pos (26U) +#define RAMCFG_WPR1_P26WP_Msk (0x1UL << RAMCFG_WPR1_P26WP_Pos) /*!< 0x04000000 */ +#define RAMCFG_WPR1_P26WP RAMCFG_WPR1_P26WP_Msk /*!< Write Protection Page 26 */ +#define RAMCFG_WPR1_P27WP_Pos (27U) +#define RAMCFG_WPR1_P27WP_Msk (0x1UL << RAMCFG_WPR1_P27WP_Pos) /*!< 0x08000000 */ +#define RAMCFG_WPR1_P27WP RAMCFG_WPR1_P27WP_Msk /*!< Write Protection Page 27 */ +#define RAMCFG_WPR1_P28WP_Pos (28U) +#define RAMCFG_WPR1_P28WP_Msk (0x1UL << RAMCFG_WPR1_P28WP_Pos) /*!< 0x10000000 */ +#define RAMCFG_WPR1_P28WP RAMCFG_WPR1_P28WP_Msk /*!< Write Protection Page 28 */ +#define RAMCFG_WPR1_P29WP_Pos (29U) +#define RAMCFG_WPR1_P29WP_Msk (0x1UL << RAMCFG_WPR1_P29WP_Pos) /*!< 0x20000000 */ +#define RAMCFG_WPR1_P29WP RAMCFG_WPR1_P29WP_Msk /*!< Write Protection Page 29 */ +#define RAMCFG_WPR1_P30WP_Pos (30U) +#define RAMCFG_WPR1_P30WP_Msk (0x1UL << RAMCFG_WPR1_P30WP_Pos) /*!< 0x40000000 */ +#define RAMCFG_WPR1_P30WP RAMCFG_WPR1_P30WP_Msk /*!< Write Protection Page 30 */ +#define RAMCFG_WPR1_P31WP_Pos (31U) +#define RAMCFG_WPR1_P31WP_Msk (0x1UL << RAMCFG_WPR1_P31WP_Pos) /*!< 0x80000000 */ +#define RAMCFG_WPR1_P31WP RAMCFG_WPR1_P31WP_Msk /*!< Write Protection Page 31 */ + +/****************** Bit definition for RAMCFG_MxWPR2 register ****************/ +#define RAMCFG_WPR2_P32WP_Pos (0U) +#define RAMCFG_WPR2_P32WP_Msk (0x1UL << RAMCFG_WPR2_P32WP_Pos) /*!< 0x00000001 */ +#define RAMCFG_WPR2_P32WP RAMCFG_WPR2_P32WP_Msk /*!< Write Protection Page 32 */ +#define RAMCFG_WPR2_P33WP_Pos (1U) +#define RAMCFG_WPR2_P33WP_Msk (0x1UL << RAMCFG_WPR2_P33WP_Pos) /*!< 0x00000002 */ +#define RAMCFG_WPR2_P33WP RAMCFG_WPR2_P33WP_Msk /*!< Write Protection Page 33 */ +#define RAMCFG_WPR2_P34WP_Pos (2U) +#define RAMCFG_WPR2_P34WP_Msk (0x1UL << RAMCFG_WPR2_P34WP_Pos) /*!< 0x00000004 */ +#define RAMCFG_WPR2_P34WP RAMCFG_WPR2_P34WP_Msk /*!< Write Protection Page 34 */ +#define RAMCFG_WPR2_P35WP_Pos (3U) +#define RAMCFG_WPR2_P35WP_Msk (0x1UL << RAMCFG_WPR2_P35WP_Pos) /*!< 0x00000008 */ +#define RAMCFG_WPR2_P35WP RAMCFG_WPR2_P35WP_Msk /*!< Write Protection Page 35 */ +#define RAMCFG_WPR2_P36WP_Pos (4U) +#define RAMCFG_WPR2_P36WP_Msk (0x1UL << RAMCFG_WPR2_P36WP_Pos) /*!< 0x00000010 */ +#define RAMCFG_WPR2_P36WP RAMCFG_WPR2_P36WP_Msk /*!< Write Protection Page 36 */ +#define RAMCFG_WPR2_P37WP_Pos (5U) +#define RAMCFG_WPR2_P37WP_Msk (0x1UL << RAMCFG_WPR2_P37WP_Pos) /*!< 0x00000020 */ +#define RAMCFG_WPR2_P37WP RAMCFG_WPR2_P37WP_Msk /*!< Write Protection Page 37 */ +#define RAMCFG_WPR2_P38WP_Pos (6U) +#define RAMCFG_WPR2_P38WP_Msk (0x1UL << RAMCFG_WPR2_P38WP_Pos) /*!< 0x00000040 */ +#define RAMCFG_WPR2_P38WP RAMCFG_WPR2_P38WP_Msk /*!< Write Protection Page 38 */ +#define RAMCFG_WPR2_P39WP_Pos (7U) +#define RAMCFG_WPR2_P39WP_Msk (0x1UL << RAMCFG_WPR2_P39WP_Pos) /*!< 0x00000080 */ +#define RAMCFG_WPR2_P39WP RAMCFG_WPR2_P39WP_Msk /*!< Write Protection Page 39 */ +#define RAMCFG_WPR2_P40WP_Pos (8U) +#define RAMCFG_WPR2_P40WP_Msk (0x1UL << RAMCFG_WPR2_P40WP_Pos) /*!< 0x00000100 */ +#define RAMCFG_WPR2_P40WP RAMCFG_WPR2_P40WP_Msk /*!< Write Protection Page 40 */ +#define RAMCFG_WPR2_P41WP_Pos (9U) +#define RAMCFG_WPR2_P41WP_Msk (0x1UL << RAMCFG_WPR2_P41WP_Pos) /*!< 0x00000200 */ +#define RAMCFG_WPR2_P41WP RAMCFG_WPR2_P41WP_Msk /*!< Write Protection Page 41 */ +#define RAMCFG_WPR2_P42WP_Pos (10U) +#define RAMCFG_WPR2_P42WP_Msk (0x1UL << RAMCFG_WPR2_P42WP_Pos) /*!< 0x00000400 */ +#define RAMCFG_WPR2_P42WP RAMCFG_WPR2_P42WP_Msk /*!< Write Protection Page 42 */ +#define RAMCFG_WPR2_P43WP_Pos (11U) +#define RAMCFG_WPR2_P43WP_Msk (0x1UL << RAMCFG_WPR2_P43WP_Pos) /*!< 0x00000800 */ +#define RAMCFG_WPR2_P43WP RAMCFG_WPR2_P43WP_Msk /*!< Write Protection Page 43 */ +#define RAMCFG_WPR2_P44WP_Pos (12U) +#define RAMCFG_WPR2_P44WP_Msk (0x1UL << RAMCFG_WPR2_P44WP_Pos) /*!< 0x00001000 */ +#define RAMCFG_WPR2_P44WP RAMCFG_WPR2_P44WP_Msk /*!< Write Protection Page 44 */ +#define RAMCFG_WPR2_P45WP_Pos (13U) +#define RAMCFG_WPR2_P45WP_Msk (0x1UL << RAMCFG_WPR2_P45WP_Pos) /*!< 0x00002000 */ +#define RAMCFG_WPR2_P45WP RAMCFG_WPR2_P45WP_Msk /*!< Write Protection Page 45 */ +#define RAMCFG_WPR2_P46WP_Pos (14U) +#define RAMCFG_WPR2_P46WP_Msk (0x1UL << RAMCFG_WPR2_P46WP_Pos) /*!< 0x00004000 */ +#define RAMCFG_WPR2_P46WP RAMCFG_WPR2_P46WP_Msk /*!< Write Protection Page 46 */ +#define RAMCFG_WPR2_P47WP_Pos (15U) +#define RAMCFG_WPR2_P47WP_Msk (0x1UL << RAMCFG_WPR2_P47WP_Pos) /*!< 0x00008000 */ +#define RAMCFG_WPR2_P47WP RAMCFG_WPR2_P47WP_Msk /*!< Write Protection Page 47 */ +#define RAMCFG_WPR2_P48WP_Pos (16U) +#define RAMCFG_WPR2_P48WP_Msk (0x1UL << RAMCFG_WPR2_P48WP_Pos) /*!< 0x00010000 */ +#define RAMCFG_WPR2_P48WP RAMCFG_WPR2_P48WP_Msk /*!< Write Protection Page 48 */ +#define RAMCFG_WPR2_P49WP_Pos (17U) +#define RAMCFG_WPR2_P49WP_Msk (0x1UL << RAMCFG_WPR2_P49WP_Pos) /*!< 0x00020000 */ +#define RAMCFG_WPR2_P49WP RAMCFG_WPR2_P49WP_Msk /*!< Write Protection Page 49 */ +#define RAMCFG_WPR2_P50WP_Pos (18U) +#define RAMCFG_WPR2_P50WP_Msk (0x1UL << RAMCFG_WPR2_P50WP_Pos) /*!< 0x00040000 */ +#define RAMCFG_WPR2_P50WP RAMCFG_WPR2_P50WP_Msk /*!< Write Protection Page 50 */ +#define RAMCFG_WPR2_P51WP_Pos (19U) +#define RAMCFG_WPR2_P51WP_Msk (0x1UL << RAMCFG_WPR2_P51WP_Pos) /*!< 0x00080000 */ +#define RAMCFG_WPR2_P51WP RAMCFG_WPR2_P51WP_Msk /*!< Write Protection Page 51 */ +#define RAMCFG_WPR2_P52WP_Pos (20U) +#define RAMCFG_WPR2_P52WP_Msk (0x1UL << RAMCFG_WPR2_P52WP_Pos) /*!< 0x00100000 */ +#define RAMCFG_WPR2_P52WP RAMCFG_WPR2_P52WP_Msk /*!< Write Protection Page 52 */ +#define RAMCFG_WPR2_P53WP_Pos (21U) +#define RAMCFG_WPR2_P53WP_Msk (0x1UL << RAMCFG_WPR2_P53WP_Pos) /*!< 0x00200000 */ +#define RAMCFG_WPR2_P53WP RAMCFG_WPR2_P53WP_Msk /*!< Write Protection Page 53 */ +#define RAMCFG_WPR2_P54WP_Pos (22U) +#define RAMCFG_WPR2_P54WP_Msk (0x1UL << RAMCFG_WPR2_P54WP_Pos) /*!< 0x00400000 */ +#define RAMCFG_WPR2_P54WP RAMCFG_WPR2_P54WP_Msk /*!< Write Protection Page 54 */ +#define RAMCFG_WPR2_P55WP_Pos (23U) +#define RAMCFG_WPR2_P55WP_Msk (0x1UL << RAMCFG_WPR2_P55WP_Pos) /*!< 0x00800000 */ +#define RAMCFG_WPR2_P55WP RAMCFG_WPR2_P55WP_Msk /*!< Write Protection Page 55 */ +#define RAMCFG_WPR2_P56WP_Pos (25U) +#define RAMCFG_WPR2_P56WP_Msk (0x1UL << RAMCFG_WPR2_P56WP_Pos) /*!< 0x01000000 */ +#define RAMCFG_WPR2_P56WP RAMCFG_WPR2_P56WP_Msk /*!< Write Protection Page 56 */ +#define RAMCFG_WPR2_P57WP_Pos (26U) +#define RAMCFG_WPR2_P57WP_Msk (0x1UL << RAMCFG_WPR2_P57WP_Pos) /*!< 0x02000000 */ +#define RAMCFG_WPR2_P57WP RAMCFG_WPR2_P57WP_Msk /*!< Write Protection Page 57 */ +#define RAMCFG_WPR2_P58WP_Pos (27U) +#define RAMCFG_WPR2_P58WP_Msk (0x1UL << RAMCFG_WPR2_P58WP_Pos) /*!< 0x04000000 */ +#define RAMCFG_WPR2_P58WP RAMCFG_WPR2_P58WP_Msk /*!< Write Protection Page 58 */ +#define RAMCFG_WPR2_P59WP_Pos (28U) +#define RAMCFG_WPR2_P59WP_Msk (0x1UL << RAMCFG_WPR2_P59WP_Pos) /*!< 0x08000000 */ +#define RAMCFG_WPR2_P59WP RAMCFG_WPR2_P59WP_Msk /*!< Write Protection Page 59 */ +#define RAMCFG_WPR2_P60WP_Pos (29U) +#define RAMCFG_WPR2_P60WP_Msk (0x1UL << RAMCFG_WPR2_P60WP_Pos) /*!< 0x10000000 */ +#define RAMCFG_WPR2_P60WP RAMCFG_WPR2_P60WP_Msk /*!< Write Protection Page 60 */ +#define RAMCFG_WPR2_P61WP_Pos (30U) +#define RAMCFG_WPR2_P61WP_Msk (0x1UL << RAMCFG_WPR2_P61WP_Pos) /*!< 0x20000000 */ +#define RAMCFG_WPR2_P61WP RAMCFG_WPR2_P61WP_Msk /*!< Write Protection Page 61 */ +#define RAMCFG_WPR2_P62WP_Pos (31U) +#define RAMCFG_WPR2_P62WP_Msk (0x1UL << RAMCFG_WPR2_P62WP_Pos) /*!< 0x40000000 */ +#define RAMCFG_WPR2_P62WP RAMCFG_WPR2_P62WP_Msk /*!< Write Protection Page 62 */ +#define RAMCFG_WPR2_P63WP_Pos (31U) +#define RAMCFG_WPR2_P63WP_Msk (0x1UL << RAMCFG_WPR2_P63WP_Pos) /*!< 0x80000000 */ +#define RAMCFG_WPR2_P63WP RAMCFG_WPR2_P63WP_Msk /*!< Write Protection Page 63 */ + + +/******************************************************************************/ +/* */ +/* Reset and Clock Control */ +/* */ +/******************************************************************************/ +#define RCC_LSI2_SUPPORT + +/******************** Bit definition for RCC_CR register ********************/ +#define RCC_CR_HSION_Pos (8U) +#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000100 */ +#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed oscillator (HSI16) clock enable */ +#define RCC_CR_HSIKERON_Pos (9U) +#define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos) /*!< 0x00000200 */ +#define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel */ +#define RCC_CR_HSIRDY_Pos (10U) +#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000400 */ +#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed oscillator (HSI16) clock ready flag */ +#define RCC_CR_HSEON_Pos (16U) +#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */ +#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed oscillator (HSE) clock enable */ +#define RCC_CR_HSERDY_Pos (17U) +#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */ +#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed oscillator (HSE) clock ready */ +#define RCC_CR_HSECSSON_Pos (19U) +#define RCC_CR_HSECSSON_Msk (0x1UL << RCC_CR_HSECSSON_Pos) /*!< 0x00080000 */ +#define RCC_CR_HSECSSON RCC_CR_HSECSSON_Msk /*!< External High Speed oscillator (HSE) clock security system enable */ +#define RCC_CR_HSEPRE_Pos (20U) +#define RCC_CR_HSEPRE_Msk (0x1UL << RCC_CR_HSEPRE_Pos) /*!< 0x00080000 */ +#define RCC_CR_HSEPRE RCC_CR_HSEPRE_Msk /*!< External High Speed oscillator (HSE) clock for sysclk prescaler */ +#define RCC_CR_PLL1ON_Pos (24U) +#define RCC_CR_PLL1ON_Msk (0x1UL << RCC_CR_PLL1ON_Pos) /*!< 0x01000000 */ +#define RCC_CR_PLL1ON RCC_CR_PLL1ON_Msk /*!< System PLL1 clock enable */ +#define RCC_CR_PLL1RDY_Pos (25U) +#define RCC_CR_PLL1RDY_Msk (0x1UL << RCC_CR_PLL1RDY_Pos) /*!< 0x02000000 */ +#define RCC_CR_PLL1RDY RCC_CR_PLL1RDY_Msk /*!< System PLL1 clock ready */ + +/******************** Bit definition for RCC_ICSCR3 register ***************/ +#define RCC_ICSCR3_HSICAL_Pos (0U) +#define RCC_ICSCR3_HSICAL_Msk (0xFFFUL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000FFF */ +#define RCC_ICSCR3_HSICAL RCC_ICSCR3_HSICAL_Msk /*!< HSICAL[11:0] bits */ +#define RCC_ICSCR3_HSICAL_0 (0x01UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000001 */ +#define RCC_ICSCR3_HSICAL_1 (0x002UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000002 */ +#define RCC_ICSCR3_HSICAL_2 (0x004UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000004 */ +#define RCC_ICSCR3_HSICAL_3 (0x008UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000008 */ +#define RCC_ICSCR3_HSICAL_4 (0x010UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000010 */ +#define RCC_ICSCR3_HSICAL_5 (0x020UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000020 */ +#define RCC_ICSCR3_HSICAL_6 (0x040UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000040 */ +#define RCC_ICSCR3_HSICAL_7 (0x080UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000080 */ +#define RCC_ICSCR3_HSICAL_8 (0x100UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000100 */ +#define RCC_ICSCR3_HSICAL_9 (0x200UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000200 */ +#define RCC_ICSCR3_HSICAL_10 (0x400UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000400 */ +#define RCC_ICSCR3_HSICAL_11 (0x800UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000800 */ +#define RCC_ICSCR3_HSITRIM_Pos (16U) +#define RCC_ICSCR3_HSITRIM_Msk (0x1FUL << RCC_ICSCR3_HSITRIM_Pos) /*!< 0x001F0000 */ +#define RCC_ICSCR3_HSITRIM RCC_ICSCR3_HSITRIM_Msk /*!< HSITRIM[4:0] bits */ +#define RCC_ICSCR3_HSITRIM_0 (0x01UL << RCC_ICSCR3_HSITRIM_Pos) /*!< 0x00010000 */ +#define RCC_ICSCR3_HSITRIM_1 (0x02UL << RCC_ICSCR3_HSITRIM_Pos) /*!< 0x00020000 */ +#define RCC_ICSCR3_HSITRIM_2 (0x04UL << RCC_ICSCR3_HSITRIM_Pos) /*!< 0x00040000 */ +#define RCC_ICSCR3_HSITRIM_3 (0x08UL << RCC_ICSCR3_HSITRIM_Pos) /*!< 0x00080000 */ +#define RCC_ICSCR3_HSITRIM_4 (0x10UL << RCC_ICSCR3_HSITRIM_Pos) /*!< 0x00100000 */ + +/******************** Bit definition for RCC_CFGR1 register *****************/ +#define RCC_CFGR1_SW_Pos (0U) +#define RCC_CFGR1_SW_Msk (0x3UL << RCC_CFGR1_SW_Pos) /*!< 0x00000003 */ +#define RCC_CFGR1_SW RCC_CFGR1_SW_Msk /*!< SW[1:0] bits (System clock Switch) */ +#define RCC_CFGR1_SW_0 (0x1UL << RCC_CFGR1_SW_Pos) /*!< 0x00000001 */ +#define RCC_CFGR1_SW_1 (0x2UL << RCC_CFGR1_SW_Pos) /*!< 0x00000002 */ +#define RCC_CFGR1_SWS_Pos (2U) +#define RCC_CFGR1_SWS_Msk (0x3UL << RCC_CFGR1_SWS_Pos) /*!< 0x0000000C */ +#define RCC_CFGR1_SWS RCC_CFGR1_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */ +#define RCC_CFGR1_SWS_0 (0x1UL << RCC_CFGR1_SWS_Pos) /*!< 0x00000004 */ +#define RCC_CFGR1_SWS_1 (0x2UL << RCC_CFGR1_SWS_Pos) /*!< 0x00000008 */ +#define RCC_CFGR1_MCOSEL_Pos (24U) +#define RCC_CFGR1_MCOSEL_Msk (0xFUL << RCC_CFGR1_MCOSEL_Pos) /*!< 0x0F000000 */ +#define RCC_CFGR1_MCOSEL RCC_CFGR1_MCOSEL_Msk /*!< MCOSEL[3:0] bits (Clock output selection) */ +#define RCC_CFGR1_MCOSEL_0 (0x1UL << RCC_CFGR1_MCOSEL_Pos) /*!< 0x01000000 */ +#define RCC_CFGR1_MCOSEL_1 (0x2UL << RCC_CFGR1_MCOSEL_Pos) /*!< 0x02000000 */ +#define RCC_CFGR1_MCOSEL_2 (0x4UL << RCC_CFGR1_MCOSEL_Pos) /*!< 0x04000000 */ +#define RCC_CFGR1_MCOSEL_3 (0x8UL << RCC_CFGR1_MCOSEL_Pos) /*!< 0x08000000 */ +#define RCC_CFGR1_MCOPRE_Pos (28U) +#define RCC_CFGR1_MCOPRE_Msk (0x7UL << RCC_CFGR1_MCOPRE_Pos) /*!< 0x70000000 */ +#define RCC_CFGR1_MCOPRE RCC_CFGR1_MCOPRE_Msk /*!< MCO[220] (Prescaler) */ +#define RCC_CFGR1_MCOPRE_0 (0x1UL << RCC_CFGR1_MCOPRE_Pos) /*!< 0x10000000 */ +#define RCC_CFGR1_MCOPRE_1 (0x2UL << RCC_CFGR1_MCOPRE_Pos) /*!< 0x20000000 */ +#define RCC_CFGR1_MCOPRE_2 (0x4UL << RCC_CFGR1_MCOPRE_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for RCC_CFGR2 register ******************/ +#define RCC_CFGR2_HPRE_Pos (0U) +#define RCC_CFGR2_HPRE_Msk (0x7UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000007 */ +#define RCC_CFGR2_HPRE RCC_CFGR2_HPRE_Msk /*!< HPRE[2:0] bits (AHB prescaler) */ +#define RCC_CFGR2_HPRE_0 (0x1UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000001 */ +#define RCC_CFGR2_HPRE_1 (0x2UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000002 */ +#define RCC_CFGR2_HPRE_2 (0x4UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000004 */ +#define RCC_CFGR2_PPRE1_Pos (4U) +#define RCC_CFGR2_PPRE1_Msk (0x7UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000070 */ +#define RCC_CFGR2_PPRE1 RCC_CFGR2_PPRE1_Msk /*!< PPRE1[2:0] bits (APB1 prescaler) */ +#define RCC_CFGR2_PPRE1_0 (0x1UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000010 */ +#define RCC_CFGR2_PPRE1_1 (0x2UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000020 */ +#define RCC_CFGR2_PPRE1_2 (0x4UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000040 */ +#define RCC_CFGR2_PPRE2_Pos (8U) +#define RCC_CFGR2_PPRE2_Msk (0x7UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000700 */ +#define RCC_CFGR2_PPRE2 RCC_CFGR2_PPRE2_Msk /*!< PPRE2[2:0] bits (APB2 prescaler) */ +#define RCC_CFGR2_PPRE2_0 (0x1UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000100 */ +#define RCC_CFGR2_PPRE2_1 (0x2UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000200 */ +#define RCC_CFGR2_PPRE2_2 (0x4UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000400 */ + +/******************** Bit definition for RCC_CFGR3 register ******************/ +#define RCC_CFGR3_PPRE7_Pos (4U) +#define RCC_CFGR3_PPRE7_Msk (0x7UL << RCC_CFGR3_PPRE7_Pos) /*!< 0x00000070 */ +#define RCC_CFGR3_PPRE7 RCC_CFGR3_PPRE7_Msk /*!< PPRE7[2:0] bits (APB7 prescaler) */ +#define RCC_CFGR3_PPRE7_0 (0x1UL << RCC_CFGR3_PPRE7_Pos) /*!< 0x00000010 */ +#define RCC_CFGR3_PPRE7_1 (0x2UL << RCC_CFGR3_PPRE7_Pos) /*!< 0x00000020 */ +#define RCC_CFGR3_PPRE7_2 (0x4UL << RCC_CFGR3_PPRE7_Pos) /*!< 0x00000040 */ + +/******************** Bit definition for RCC_PLL1CFGR register ***************/ +#define RCC_PLL1CFGR_PLL1SRC_Pos (0U) +#define RCC_PLL1CFGR_PLL1SRC_Msk (0x3UL << RCC_PLL1CFGR_PLL1SRC_Pos) /*!< 0x00000003 */ +#define RCC_PLL1CFGR_PLL1SRC RCC_PLL1CFGR_PLL1SRC_Msk +#define RCC_PLL1CFGR_PLL1SRC_0 (0x1UL << RCC_PLL1CFGR_PLL1SRC_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CFGR_PLL1SRC_1 (0x2UL << RCC_PLL1CFGR_PLL1SRC_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CFGR_PLL1RGE_Pos (2U) +#define RCC_PLL1CFGR_PLL1RGE_Msk (0x3UL << RCC_PLL1CFGR_PLL1RGE_Pos) /*!< 0x0000000C */ +#define RCC_PLL1CFGR_PLL1RGE RCC_PLL1CFGR_PLL1RGE_Msk +#define RCC_PLL1CFGR_PLL1RGE_0 (0x1UL << RCC_PLL1CFGR_PLL1RGE_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CFGR_PLL1RGE_1 (0x2UL << RCC_PLL1CFGR_PLL1RGE_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CFGR_PLL1FRACEN_Pos (4U) +#define RCC_PLL1CFGR_PLL1FRACEN_Msk (0x1UL << RCC_PLL1CFGR_PLL1FRACEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CFGR_PLL1FRACEN RCC_PLL1CFGR_PLL1FRACEN_Msk +#define RCC_PLL1CFGR_PLL1M_Pos (8U) +#define RCC_PLL1CFGR_PLL1M_Msk (0x7UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00000700 */ +#define RCC_PLL1CFGR_PLL1M RCC_PLL1CFGR_PLL1M_Msk +#define RCC_PLL1CFGR_PLL1M_0 (0x01UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CFGR_PLL1M_1 (0x02UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00000200 */ +#define RCC_PLL1CFGR_PLL1M_2 (0x04UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00000400 */ +#define RCC_PLL1CFGR_PLL1PEN_Pos (16U) +#define RCC_PLL1CFGR_PLL1PEN_Msk (0x1UL << RCC_PLL1CFGR_PLL1PEN_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CFGR_PLL1PEN RCC_PLL1CFGR_PLL1PEN_Msk +#define RCC_PLL1CFGR_PLL1QEN_Pos (17U) +#define RCC_PLL1CFGR_PLL1QEN_Msk (0x1UL << RCC_PLL1CFGR_PLL1QEN_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CFGR_PLL1QEN RCC_PLL1CFGR_PLL1QEN_Msk +#define RCC_PLL1CFGR_PLL1REN_Pos (18U) +#define RCC_PLL1CFGR_PLL1REN_Msk (0x1UL << RCC_PLL1CFGR_PLL1REN_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CFGR_PLL1REN RCC_PLL1CFGR_PLL1REN_Msk +#define RCC_PLL1CFGR_PLL1RCLKPRE_Pos (20U) +#define RCC_PLL1CFGR_PLL1RCLKPRE_Msk (0x1UL << RCC_PLL1CFGR_PLL1RCLKPRE_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CFGR_PLL1RCLKPRE RCC_PLL1CFGR_PLL1RCLKPRE_Msk +#define RCC_PLL1CFGR_PLL1RCLKPRESTEP_Pos (21U) +#define RCC_PLL1CFGR_PLL1RCLKPRESTEP_Msk (0x1UL << RCC_PLL1CFGR_PLL1RCLKPRESTEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL1CFGR_PLL1RCLKPRESTEP RCC_PLL1CFGR_PLL1RCLKPRESTEP_Msk +#define RCC_PLL1CFGR_PLL1RCLKPRERDY_Pos (22U) +#define RCC_PLL1CFGR_PLL1RCLKPRERDY_Msk (0x1UL << RCC_PLL1CFGR_PLL1RCLKPRERDY_Pos) /*!< 0x00400000 */ +#define RCC_PLL1CFGR_PLL1RCLKPRERDY RCC_PLL1CFGR_PLL1RCLKPRERDY_Msk + +/******************** Bit definition for RCC_PLL1DIVR register ***************/ +#define RCC_PLL1DIVR_PLL1N_Pos (0U) +#define RCC_PLL1DIVR_PLL1N_Msk (0x1FFUL << RCC_PLL1DIVR_PLL1N_Pos) /*!< 0x000001FF */ +#define RCC_PLL1DIVR_PLL1N RCC_PLL1DIVR_PLL1N_Msk +#define RCC_PLL1DIVR_PLL1N_0 (0x001UL << RCC_PLL1DIVR_PLL1N_Pos) /*!< 0x00000001 */ +#define RCC_PLL1DIVR_PLL1N_1 (0x002UL << RCC_PLL1DIVR_PLL1N_Pos) /*!< 0x00000002 */ +#define RCC_PLL1DIVR_PLL1N_2 (0x004UL << RCC_PLL1DIVR_PLL1N_Pos) /*!< 0x00000004 */ +#define RCC_PLL1DIVR_PLL1N_3 (0x008UL << RCC_PLL1DIVR_PLL1N_Pos) /*!< 0x00000008 */ +#define RCC_PLL1DIVR_PLL1N_4 (0x010UL << RCC_PLL1DIVR_PLL1N_Pos) /*!< 0x00000010 */ +#define RCC_PLL1DIVR_PLL1N_5 (0x020UL << RCC_PLL1DIVR_PLL1N_Pos) /*!< 0x00000020 */ +#define RCC_PLL1DIVR_PLL1N_6 (0x040UL << RCC_PLL1DIVR_PLL1N_Pos) /*!< 0x00000040 */ +#define RCC_PLL1DIVR_PLL1N_7 (0x080UL << RCC_PLL1DIVR_PLL1N_Pos) /*!< 0x00000080 */ +#define RCC_PLL1DIVR_PLL1N_8 (0x100UL << RCC_PLL1DIVR_PLL1N_Pos) /*!< 0x00000100 */ +#define RCC_PLL1DIVR_PLL1P_Pos (9U) +#define RCC_PLL1DIVR_PLL1P_Msk (0x7FUL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x0000FE00 */ +#define RCC_PLL1DIVR_PLL1P RCC_PLL1DIVR_PLL1P_Msk +#define RCC_PLL1DIVR_PLL1P_0 (0x01UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00000200 */ +#define RCC_PLL1DIVR_PLL1P_1 (0x02UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00000400 */ +#define RCC_PLL1DIVR_PLL1P_2 (0x04UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00000800 */ +#define RCC_PLL1DIVR_PLL1P_3 (0x08UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00001000 */ +#define RCC_PLL1DIVR_PLL1P_4 (0x10UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00002000 */ +#define RCC_PLL1DIVR_PLL1P_5 (0x20UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00004000 */ +#define RCC_PLL1DIVR_PLL1P_6 (0x40UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00008000 */ +#define RCC_PLL1DIVR_PLL1Q_Pos (16U) +#define RCC_PLL1DIVR_PLL1Q_Msk (0x7FUL << RCC_PLL1DIVR_PLL1Q_Pos) /*!< 0x007F0000 */ +#define RCC_PLL1DIVR_PLL1Q RCC_PLL1DIVR_PLL1Q_Msk +#define RCC_PLL1DIVR_PLL1Q_0 (0x01UL << RCC_PLL1DIVR_PLL1Q_Pos) /*!< 0x00010000 */ +#define RCC_PLL1DIVR_PLL1Q_1 (0x02UL << RCC_PLL1DIVR_PLL1Q_Pos) /*!< 0x00020000 */ +#define RCC_PLL1DIVR_PLL1Q_2 (0x04UL << RCC_PLL1DIVR_PLL1Q_Pos) /*!< 0x00040000 */ +#define RCC_PLL1DIVR_PLL1Q_3 (0x08UL << RCC_PLL1DIVR_PLL1Q_Pos) /*!< 0x00080000 */ +#define RCC_PLL1DIVR_PLL1Q_4 (0x10UL << RCC_PLL1DIVR_PLL1Q_Pos) /*!< 0x00100000 */ +#define RCC_PLL1DIVR_PLL1Q_5 (0x20UL << RCC_PLL1DIVR_PLL1Q_Pos) /*!< 0x00200020 */ +#define RCC_PLL1DIVR_PLL1Q_6 (0x40UL << RCC_PLL1DIVR_PLL1Q_Pos) /*!< 0x00400000 */ +#define RCC_PLL1DIVR_PLL1R_Pos (24U) +#define RCC_PLL1DIVR_PLL1R_Msk (0x7FUL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x7F000000 */ +#define RCC_PLL1DIVR_PLL1R RCC_PLL1DIVR_PLL1R_Msk +#define RCC_PLL1DIVR_PLL1R_0 (0x01UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x01000000 */ +#define RCC_PLL1DIVR_PLL1R_1 (0x02UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x02000000 */ +#define RCC_PLL1DIVR_PLL1R_2 (0x04UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x04000000 */ +#define RCC_PLL1DIVR_PLL1R_3 (0x08UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x08000000 */ +#define RCC_PLL1DIVR_PLL1R_4 (0x10UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x10000000 */ +#define RCC_PLL1DIVR_PLL1R_5 (0x20UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x20000000 */ +#define RCC_PLL1DIVR_PLL1R_6 (0x40UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for RCC_PLL1FRACR register ***************/ +#define RCC_PLL1FRACR_PLL1FRACN_Pos (3U) +#define RCC_PLL1FRACR_PLL1FRACN_Msk (0x1FFFUL << RCC_PLL1FRACR_PLL1FRACN_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL1FRACR_PLL1FRACN RCC_PLL1FRACR_PLL1FRACN_Msk + +/******************** Bit definition for RCC_CIER register ******************/ +#define RCC_CIER_LSI1RDYIE_Pos (0U) +#define RCC_CIER_LSI1RDYIE_Msk (0x1UL << RCC_CIER_LSI1RDYIE_Pos) /*!< 0x00000001 */ +#define RCC_CIER_LSI1RDYIE RCC_CIER_LSI1RDYIE_Msk +#define RCC_CIER_LSERDYIE_Pos (1U) +#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk +#define RCC_CIER_HSIRDYIE_Pos (3U) +#define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000008 */ +#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk +#define RCC_CIER_HSERDYIE_Pos (4U) +#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000010 */ +#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk +#define RCC_CIER_PLL1RDYIE_Pos (6U) +#define RCC_CIER_PLL1RDYIE_Msk (0x1UL << RCC_CIER_PLL1RDYIE_Pos) /*!< 0x00000040 */ +#define RCC_CIER_PLL1RDYIE RCC_CIER_PLL1RDYIE_Msk +#define RCC_CIER_LSI2RDYIE_Pos (16U) +#define RCC_CIER_LSI2RDYIE_Msk (0x1UL << RCC_CIER_LSI2RDYIE_Pos) /*!< 0x00010000 */ +#define RCC_CIER_LSI2RDYIE RCC_CIER_LSI2RDYIE_Msk + +/******************** Bit definition for RCC_CIFR register ****************/ +#define RCC_CIFR_LSI1RDYF_Pos (0U) +#define RCC_CIFR_LSI1RDYF_Msk (0x1UL << RCC_CIFR_LSI1RDYF_Pos) /*!< 0x00000001 */ +#define RCC_CIFR_LSI1RDYF RCC_CIFR_LSI1RDYF_Msk +#define RCC_CIFR_LSERDYF_Pos (1U) +#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk +#define RCC_CIFR_HSIRDYF_Pos (3U) +#define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000008 */ +#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk +#define RCC_CIFR_HSERDYF_Pos (4U) +#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000010 */ +#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk +#define RCC_CIFR_PLL1RDYF_Pos (6U) +#define RCC_CIFR_PLL1RDYF_Msk (0x1UL << RCC_CIFR_PLL1RDYF_Pos) /*!< 0x00000040 */ +#define RCC_CIFR_PLL1RDYF RCC_CIFR_PLL1RDYF_Msk +#define RCC_CIFR_HSECSSF_Pos (10U) +#define RCC_CIFR_HSECSSF_Msk (0x1UL << RCC_CIFR_HSECSSF_Pos) /*!< 0x00000400 */ +#define RCC_CIFR_HSECSSF RCC_CIFR_HSECSSF_Msk +#define RCC_CIFR_LSI2RDYF_Pos (16U) +#define RCC_CIFR_LSI2RDYF_Msk (0x1UL << RCC_CIFR_LSI2RDYF_Pos) /*!< 0x00010000 */ +#define RCC_CIFR_LSI2RDYF RCC_CIFR_LSI2RDYF_Msk + +/******************** Bit definition for RCC_CICR register ****************/ +#define RCC_CICR_LSI1RDYC_Pos (0U) +#define RCC_CICR_LSI1RDYC_Msk (0x1UL << RCC_CICR_LSI1RDYC_Pos) /*!< 0x00000001 */ +#define RCC_CICR_LSI1RDYC RCC_CICR_LSI1RDYC_Msk +#define RCC_CICR_LSERDYC_Pos (1U) +#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */ +#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk +#define RCC_CICR_HSIRDYC_Pos (3U) +#define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000008 */ +#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk +#define RCC_CICR_HSERDYC_Pos (4U) +#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000010 */ +#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk +#define RCC_CICR_PLL1RDYC_Pos (6U) +#define RCC_CICR_PLL1RDYC_Msk (0x1UL << RCC_CICR_PLL1RDYC_Pos) /*!< 0x00000040 */ +#define RCC_CICR_PLL1RDYC RCC_CICR_PLL1RDYC_Msk +#define RCC_CICR_HSECSSC_Pos (10U) +#define RCC_CICR_HSECSSC_Msk (0x1UL << RCC_CICR_HSECSSC_Pos) /*!< 0x00000400 */ +#define RCC_CICR_HSECSSC RCC_CICR_HSECSSC_Msk +#define RCC_CICR_LSI2RDYC_Pos (16U) +#define RCC_CICR_LSI2RDYC_Msk (0x1UL << RCC_CICR_LSI2RDYC_Pos) /*!< 0x00010000 */ +#define RCC_CICR_LSI2RDYC RCC_CICR_LSI2RDYC_Msk + +/******************** Bit definition for RCC_AHB1RSTR register **************/ +#define RCC_AHB1RSTR_GPDMA1RST_Pos (0U) +#define RCC_AHB1RSTR_GPDMA1RST_Msk (0x1UL << RCC_AHB1RSTR_GPDMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB1RSTR_GPDMA1RST RCC_AHB1RSTR_GPDMA1RST_Msk +#define RCC_AHB1RSTR_CRCRST_Pos (12U) +#define RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk +#define RCC_AHB1RSTR_TSCRST_Pos (16U) +#define RCC_AHB1RSTR_TSCRST_Msk (0x1UL << RCC_AHB1RSTR_TSCRST_Pos) /*!< 0x00010000 */ +#define RCC_AHB1RSTR_TSCRST RCC_AHB1RSTR_TSCRST_Msk + +/******************** Bit definition for RCC_AHB2RSTR register **************/ +#define RCC_AHB2RSTR_GPIOARST_Pos (0U) +#define RCC_AHB2RSTR_GPIOARST_Msk (0x1UL << RCC_AHB2RSTR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB2RSTR_GPIOARST RCC_AHB2RSTR_GPIOARST_Msk +#define RCC_AHB2RSTR_GPIOBRST_Pos (1U) +#define RCC_AHB2RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB2RSTR_GPIOBRST RCC_AHB2RSTR_GPIOBRST_Msk +#define RCC_AHB2RSTR_GPIOCRST_Pos (2U) +#define RCC_AHB2RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB2RSTR_GPIOCRST RCC_AHB2RSTR_GPIOCRST_Msk +#define RCC_AHB2RSTR_GPIOHRST_Pos (7U) +#define RCC_AHB2RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB2RSTR_GPIOHRST RCC_AHB2RSTR_GPIOHRST_Msk +#define RCC_AHB2RSTR_AESRST_Pos (16U) +#define RCC_AHB2RSTR_AESRST_Msk (0x1UL << RCC_AHB2RSTR_AESRST_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTR_AESRST RCC_AHB2RSTR_AESRST_Msk +#define RCC_AHB2RSTR_HASHRST_Pos (17U) +#define RCC_AHB2RSTR_HASHRST_Msk (0x1UL << RCC_AHB2RSTR_HASHRST_Pos) /*!< 0x00020000 */ +#define RCC_AHB2RSTR_HASHRST RCC_AHB2RSTR_HASHRST_Msk +#define RCC_AHB2RSTR_RNGRST_Pos (18U) +#define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00040000 */ +#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk +#define RCC_AHB2RSTR_SAESRST_Pos (19U) +#define RCC_AHB2RSTR_SAESRST_Msk (0x1UL << RCC_AHB2RSTR_SAESRST_Pos) /*!< 0x00080000 */ +#define RCC_AHB2RSTR_SAESRST RCC_AHB2RSTR_SAESRST_Msk +#define RCC_AHB2RSTR_HSEMRST_Pos (20U) +#define RCC_AHB2RSTR_HSEMRST_Msk (0x1UL << RCC_AHB2RSTR_HSEMRST_Pos) /*!< 0x00100000 */ +#define RCC_AHB2RSTR_HSEMRST RCC_AHB2RSTR_HSEMRST_Msk +#define RCC_AHB2RSTR_PKARST_Pos (21U) +#define RCC_AHB2RSTR_PKARST_Msk (0x1UL << RCC_AHB2RSTR_PKARST_Pos) /*!< 0x00200000 */ +#define RCC_AHB2RSTR_PKARST RCC_AHB2RSTR_PKARST_Msk + +/******************** Bit definition for RCC_AHB4RSTR register **************/ +#define RCC_AHB4RSTR_ADC4RST_Pos (5U) +#define RCC_AHB4RSTR_ADC4RST_Msk (0x1UL << RCC_AHB4RSTR_ADC4RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB4RSTR_ADC4RST RCC_AHB4RSTR_ADC4RST_Msk + +/******************** Bit definition for RCC_AHB5RSTR register **************/ +#define RCC_AHB5RSTR_RADIORST_Pos (0U) +#define RCC_AHB5RSTR_RADIORST_Msk (0x1UL << RCC_AHB5RSTR_RADIORST_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTR_RADIORST RCC_AHB5RSTR_RADIORST_Msk +#define RCC_AHB5RSTR_PTACONVRST_Pos (1U) +#define RCC_AHB5RSTR_PTACONVRST_Msk (0x1UL << RCC_AHB5RSTR_PTACONVRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB5RSTR_PTACONVRST RCC_AHB5RSTR_PTACONVRST_Msk + +/******************** Bit definition for RCC_APB1RSTR1 register **************/ +#define RCC_APB1RSTR1_TIM2RST_Pos (0U) +#define RCC_APB1RSTR1_TIM2RST_Msk (0x1UL << RCC_APB1RSTR1_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTR1_TIM2RST RCC_APB1RSTR1_TIM2RST_Msk +#define RCC_APB1RSTR1_TIM3RST_Pos (1U) +#define RCC_APB1RSTR1_TIM3RST_Msk (0x1UL << RCC_APB1RSTR1_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTR1_TIM3RST RCC_APB1RSTR1_TIM3RST_Msk +#define RCC_APB1RSTR1_USART2RST_Pos (17U) +#define RCC_APB1RSTR1_USART2RST_Msk (0x1UL << RCC_APB1RSTR1_USART2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTR1_USART2RST RCC_APB1RSTR1_USART2RST_Msk +#define RCC_APB1RSTR1_I2C1RST_Pos (21U) +#define RCC_APB1RSTR1_I2C1RST_Msk (0x1UL << RCC_APB1RSTR1_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTR1_I2C1RST RCC_APB1RSTR1_I2C1RST_Msk + +/******************** Bit definition for RCC_APB1RSTR2 register **************/ +#define RCC_APB1RSTR2_LPTIM2RST_Pos (5U) +#define RCC_APB1RSTR2_LPTIM2RST_Msk (0x1UL << RCC_APB1RSTR2_LPTIM2RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTR2_LPTIM2RST RCC_APB1RSTR2_LPTIM2RST_Msk + +/******************** Bit definition for RCC_APB2RSTR register **************/ +#define RCC_APB2RSTR_TIM1RST_Pos (11U) +#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */ +#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk +#define RCC_APB2RSTR_SPI1RST_Pos (12U) +#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ +#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk +#define RCC_APB2RSTR_USART1RST_Pos (14U) +#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ +#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk +#define RCC_APB2RSTR_TIM16RST_Pos (17U) +#define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk +#define RCC_APB2RSTR_TIM17RST_Pos (18U) +#define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk +#define RCC_APB2RSTR_SAI1RST_Pos (21U) +#define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk + +/******************** Bit definition for RCC_APB7RSTR register **************/ +#define RCC_APB7RSTR_SYSCFGRST_Pos (1U) +#define RCC_APB7RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB7RSTR_SYSCFGRST_Pos) /*!< 0x00000002 */ +#define RCC_APB7RSTR_SYSCFGRST RCC_APB7RSTR_SYSCFGRST_Msk +#define RCC_APB7RSTR_SPI3RST_Pos (5U) +#define RCC_APB7RSTR_SPI3RST_Msk (0x1UL << RCC_APB7RSTR_SPI3RST_Pos) /*!< 0x00000020 */ +#define RCC_APB7RSTR_SPI3RST RCC_APB7RSTR_SPI3RST_Msk +#define RCC_APB7RSTR_LPUART1RST_Pos (6U) +#define RCC_APB7RSTR_LPUART1RST_Msk (0x1UL << RCC_APB7RSTR_LPUART1RST_Pos) /*!< 0x00000040 */ +#define RCC_APB7RSTR_LPUART1RST RCC_APB7RSTR_LPUART1RST_Msk +#define RCC_APB7RSTR_I2C3RST_Pos (7U) +#define RCC_APB7RSTR_I2C3RST_Msk (0x1UL << RCC_APB7RSTR_I2C3RST_Pos) /*!< 0x00000080 */ +#define RCC_APB7RSTR_I2C3RST RCC_APB7RSTR_I2C3RST_Msk +#define RCC_APB7RSTR_LPTIM1RST_Pos (11U) +#define RCC_APB7RSTR_LPTIM1RST_Msk (0x1UL << RCC_APB7RSTR_LPTIM1RST_Pos) /*!< 0x00000800 */ +#define RCC_APB7RSTR_LPTIM1RST RCC_APB7RSTR_LPTIM1RST_Msk +#define RCC_APB7RSTR_COMPRST_Pos (15U) +#define RCC_APB7RSTR_COMPRST_Msk (0x1UL << RCC_APB7RSTR_COMPRST_Pos) /*!< 0x00008000 */ +#define RCC_APB7RSTR_COMPRST RCC_APB7RSTR_COMPRST_Msk + +/******************** Bit definition for RCC_AHB1ENR register **************/ +#define RCC_AHB1ENR_GPDMA1EN_Pos (0U) +#define RCC_AHB1ENR_GPDMA1EN_Msk (0x1UL << RCC_AHB1ENR_GPDMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_AHB1ENR_GPDMA1EN RCC_AHB1ENR_GPDMA1EN_Msk +#define RCC_AHB1ENR_FLASHEN_Pos (8U) +#define RCC_AHB1ENR_FLASHEN_Msk (0x1UL << RCC_AHB1ENR_FLASHEN_Pos) /*!< 0x00000100 */ +#define RCC_AHB1ENR_FLASHEN RCC_AHB1ENR_FLASHEN_Msk +#define RCC_AHB1ENR_CRCEN_Pos (12U) +#define RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */ +#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk +#define RCC_AHB1ENR_TSCEN_Pos (16U) +#define RCC_AHB1ENR_TSCEN_Msk (0x1UL << RCC_AHB1ENR_TSCEN_Pos) /*!< 0x00010000 */ +#define RCC_AHB1ENR_TSCEN RCC_AHB1ENR_TSCEN_Msk +#define RCC_AHB1ENR_RAMCFGEN_Pos (17U) +#define RCC_AHB1ENR_RAMCFGEN_Msk (0x1UL << RCC_AHB1ENR_RAMCFGEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB1ENR_RAMCFGEN RCC_AHB1ENR_RAMCFGEN_Msk +#define RCC_AHB1ENR_GTZC1EN_Pos (24U) +#define RCC_AHB1ENR_GTZC1EN_Msk (0x1UL << RCC_AHB1ENR_GTZC1EN_Pos) /*!< 0x01000000 */ +#define RCC_AHB1ENR_GTZC1EN RCC_AHB1ENR_GTZC1EN_Msk +#define RCC_AHB1ENR_SRAM1EN_Pos (31U) +#define RCC_AHB1ENR_SRAM1EN_Msk (0x1UL << RCC_AHB1ENR_SRAM1EN_Pos) /*!< 0x80000000 */ +#define RCC_AHB1ENR_SRAM1EN RCC_AHB1ENR_SRAM1EN_Msk + +/******************** Bit definition for RCC_AHB2ENR register **************/ +#define RCC_AHB2ENR_GPIOAEN_Pos (0U) +#define RCC_AHB2ENR_GPIOAEN_Msk (0x1UL << RCC_AHB2ENR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB2ENR_GPIOAEN RCC_AHB2ENR_GPIOAEN_Msk +#define RCC_AHB2ENR_GPIOBEN_Pos (1U) +#define RCC_AHB2ENR_GPIOBEN_Msk (0x1UL << RCC_AHB2ENR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB2ENR_GPIOBEN RCC_AHB2ENR_GPIOBEN_Msk +#define RCC_AHB2ENR_GPIOCEN_Pos (2U) +#define RCC_AHB2ENR_GPIOCEN_Msk (0x1UL << RCC_AHB2ENR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB2ENR_GPIOCEN RCC_AHB2ENR_GPIOCEN_Msk +#define RCC_AHB2ENR_GPIOHEN_Pos (7U) +#define RCC_AHB2ENR_GPIOHEN_Msk (0x1UL << RCC_AHB2ENR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_AHB2ENR_GPIOHEN RCC_AHB2ENR_GPIOHEN_Msk +#define RCC_AHB2ENR_AESEN_Pos (16U) +#define RCC_AHB2ENR_AESEN_Msk (0x1UL << RCC_AHB2ENR_AESEN_Pos) /*!< 0x00010000 */ +#define RCC_AHB2ENR_AESEN RCC_AHB2ENR_AESEN_Msk +#define RCC_AHB2ENR_HASHEN_Pos (17U) +#define RCC_AHB2ENR_HASHEN_Msk (0x1UL << RCC_AHB2ENR_HASHEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB2ENR_HASHEN RCC_AHB2ENR_HASHEN_Msk +#define RCC_AHB2ENR_RNGEN_Pos (18U) +#define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00040000 */ +#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk +#define RCC_AHB2ENR_SAESEN_Pos (19U) +#define RCC_AHB2ENR_SAESEN_Msk (0x1UL << RCC_AHB2ENR_SAESEN_Pos) /*!< 0x00080000 */ +#define RCC_AHB2ENR_SAESEN RCC_AHB2ENR_SAESEN_Msk +#define RCC_AHB2ENR_HSEMEN_Pos (20U) +#define RCC_AHB2ENR_HSEMEN_Msk (0x1UL << RCC_AHB2ENR_HSEMEN_Pos) /*!< 0x00100000 */ +#define RCC_AHB2ENR_HSEMEN RCC_AHB2ENR_HSEMEN_Msk +#define RCC_AHB2ENR_PKAEN_Pos (21U) +#define RCC_AHB2ENR_PKAEN_Msk (0x1UL << RCC_AHB2ENR_PKAEN_Pos) /*!< 0x00200000 */ +#define RCC_AHB2ENR_PKAEN RCC_AHB2ENR_PKAEN_Msk +#define RCC_AHB2ENR_SRAM2EN_Pos (30U) +#define RCC_AHB2ENR_SRAM2EN_Msk (0x1UL << RCC_AHB2ENR_SRAM2EN_Pos) /*!< 0x40000000 */ +#define RCC_AHB2ENR_SRAM2EN RCC_AHB2ENR_SRAM2EN_Msk + +/******************** Bit definition for RCC_AHB4ENR register **************/ +#define RCC_AHB4ENR_PWREN_Pos (2U) +#define RCC_AHB4ENR_PWREN_Msk (0x1UL << RCC_AHB4ENR_PWREN_Pos) /*!< 0x00000004 */ +#define RCC_AHB4ENR_PWREN RCC_AHB4ENR_PWREN_Msk +#define RCC_AHB4ENR_ADC4EN_Pos (5U) +#define RCC_AHB4ENR_ADC4EN_Msk (0x1UL << RCC_AHB4ENR_ADC4EN_Pos) /*!< 0x00000020 */ +#define RCC_AHB4ENR_ADC4EN RCC_AHB4ENR_ADC4EN_Msk + +/******************** Bit definition for RCC_AHB5ENR register **************/ +#define RCC_AHB5ENR_RADIOEN_Pos (0U) +#define RCC_AHB5ENR_RADIOEN_Msk (0x1UL << RCC_AHB5ENR_RADIOEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB5ENR_RADIOEN RCC_AHB5ENR_RADIOEN_Msk +#define RCC_AHB5ENR_PTACONVEN_Pos (1U) +#define RCC_AHB5ENR_PTACONVEN_Msk (0x1UL << RCC_AHB5ENR_PTACONVEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB5ENR_PTACONVEN RCC_AHB5ENR_PTACONVEN_Msk + +/******************** Bit definition for RCC_APB1ENR1 register **************/ +#define RCC_APB1ENR1_TIM2EN_Pos (0U) +#define RCC_APB1ENR1_TIM2EN_Msk (0x1UL << RCC_APB1ENR1_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_APB1ENR1_TIM2EN RCC_APB1ENR1_TIM2EN_Msk +#define RCC_APB1ENR1_TIM3EN_Pos (1U) +#define RCC_APB1ENR1_TIM3EN_Msk (0x1UL << RCC_APB1ENR1_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_APB1ENR1_TIM3EN RCC_APB1ENR1_TIM3EN_Msk +#define RCC_APB1ENR1_WWDGEN_Pos (11U) +#define RCC_APB1ENR1_WWDGEN_Msk (0x1UL << RCC_APB1ENR1_WWDGEN_Pos) /*!< 0x00000800 */ +#define RCC_APB1ENR1_WWDGEN RCC_APB1ENR1_WWDGEN_Msk +#define RCC_APB1ENR1_USART2EN_Pos (17U) +#define RCC_APB1ENR1_USART2EN_Msk (0x1UL << RCC_APB1ENR1_USART2EN_Pos) /*!< 0x00020000 */ +#define RCC_APB1ENR1_USART2EN RCC_APB1ENR1_USART2EN_Msk +#define RCC_APB1ENR1_I2C1EN_Pos (21U) +#define RCC_APB1ENR1_I2C1EN_Msk (0x1UL << RCC_APB1ENR1_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_APB1ENR1_I2C1EN RCC_APB1ENR1_I2C1EN_Msk + +/******************** Bit definition for RCC_APB1ENR2 register **************/ +#define RCC_APB1ENR2_LPTIM2EN_Pos (5U) +#define RCC_APB1ENR2_LPTIM2EN_Msk (0x1UL << RCC_APB1ENR2_LPTIM2EN_Pos) /*!< 0x00000020 */ +#define RCC_APB1ENR2_LPTIM2EN RCC_APB1ENR2_LPTIM2EN_Msk + +/******************** Bit definition for RCC_APB2ENR register **************/ +#define RCC_APB2ENR_TIM1EN_Pos (11U) +#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */ +#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk +#define RCC_APB2ENR_SPI1EN_Pos (12U) +#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ +#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk +#define RCC_APB2ENR_USART1EN_Pos (14U) +#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */ +#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk +#define RCC_APB2ENR_TIM16EN_Pos (17U) +#define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */ +#define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk +#define RCC_APB2ENR_TIM17EN_Pos (18U) +#define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */ +#define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk +#define RCC_APB2ENR_SAI1EN_Pos (21U) +#define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00200000 */ +#define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk + +/******************** Bit definition for RCC_APB7ENR register **************/ +#define RCC_APB7ENR_SYSCFGEN_Pos (1U) +#define RCC_APB7ENR_SYSCFGEN_Msk (0x1UL << RCC_APB7ENR_SYSCFGEN_Pos) /*!< 0x00000002 */ +#define RCC_APB7ENR_SYSCFGEN RCC_APB7ENR_SYSCFGEN_Msk +#define RCC_APB7ENR_SPI3EN_Pos (5U) +#define RCC_APB7ENR_SPI3EN_Msk (0x1UL << RCC_APB7ENR_SPI3EN_Pos) /*!< 0x00000020 */ +#define RCC_APB7ENR_SPI3EN RCC_APB7ENR_SPI3EN_Msk +#define RCC_APB7ENR_LPUART1EN_Pos (6U) +#define RCC_APB7ENR_LPUART1EN_Msk (0x1UL << RCC_APB7ENR_LPUART1EN_Pos) /*!< 0x00000040 */ +#define RCC_APB7ENR_LPUART1EN RCC_APB7ENR_LPUART1EN_Msk +#define RCC_APB7ENR_I2C3EN_Pos (7U) +#define RCC_APB7ENR_I2C3EN_Msk (0x1UL << RCC_APB7ENR_I2C3EN_Pos) /*!< 0x00000080 */ +#define RCC_APB7ENR_I2C3EN RCC_APB7ENR_I2C3EN_Msk +#define RCC_APB7ENR_LPTIM1EN_Pos (11U) +#define RCC_APB7ENR_LPTIM1EN_Msk (0x1UL << RCC_APB7ENR_LPTIM1EN_Pos) /*!< 0x00000800 */ +#define RCC_APB7ENR_LPTIM1EN RCC_APB7ENR_LPTIM1EN_Msk +#define RCC_APB7ENR_COMPEN_Pos (15U) +#define RCC_APB7ENR_COMPEN_Msk (0x1UL << RCC_APB7ENR_COMPEN_Pos) /*!< 0x00008000 */ +#define RCC_APB7ENR_COMPEN RCC_APB7ENR_COMPEN_Msk +#define RCC_APB7ENR_RTCAPBEN_Pos (21U) +#define RCC_APB7ENR_RTCAPBEN_Msk (0x1UL << RCC_APB7ENR_RTCAPBEN_Pos) /*!< 0x00200000 */ +#define RCC_APB7ENR_RTCAPBEN RCC_APB7ENR_RTCAPBEN_Msk + +/******************** Bit definition for RCC_AHB1SMENR register **************/ +#define RCC_AHB1SMENR_GPDMA1SMEN_Pos (0U) +#define RCC_AHB1SMENR_GPDMA1SMEN_Msk (0x1UL << RCC_AHB1SMENR_GPDMA1SMEN_Pos) /*!< 0x00000000*/ +#define RCC_AHB1SMENR_GPDMA1SMEN RCC_AHB1SMENR_GPDMA1SMEN_Msk +#define RCC_AHB1SMENR_FLASHSMEN_Pos (8U) +#define RCC_AHB1SMENR_FLASHSMEN_Msk (0x1UL << RCC_AHB1SMENR_FLASHSMEN_Pos) /*!< 0x00000100 */ +#define RCC_AHB1SMENR_FLASHSMEN RCC_AHB1SMENR_FLASHSMEN_Msk +#define RCC_AHB1SMENR_CRCSMEN_Pos (12U) +#define RCC_AHB1SMENR_CRCSMEN_Msk (0x1UL << RCC_AHB1SMENR_CRCSMEN_Pos) /*!< 0x00001000 */ +#define RCC_AHB1SMENR_CRCSMEN RCC_AHB1SMENR_CRCSMEN_Msk +#define RCC_AHB1SMENR_TSCSMEN_Pos (16U) +#define RCC_AHB1SMENR_TSCSMEN_Msk (0x1UL << RCC_AHB1SMENR_TSCSMEN_Pos) /*!< 0x00010000 */ +#define RCC_AHB1SMENR_TSCSMEN RCC_AHB1SMENR_TSCSMEN_Msk +#define RCC_AHB1SMENR_RAMCFGSMEN_Pos (17U) +#define RCC_AHB1SMENR_RAMCFGSMEN_Msk (0x1UL << RCC_AHB1SMENR_RAMCFGSMEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB1SMENR_RAMCFGSMEN RCC_AHB1SMENR_RAMCFGSMEN_Msk +#define RCC_AHB1SMENR_GTZC1SMEN_Pos (24U) +#define RCC_AHB1SMENR_GTZC1SMEN_Msk (0x1UL << RCC_AHB1SMENR_GTZC1SMEN_Pos) /*!< 0x01000000 */ +#define RCC_AHB1SMENR_GTZC1SMEN RCC_AHB1SMENR_GTZC1SMEN_Msk +#define RCC_AHB1SMENR_ICACHESMEN_Pos (29U) +#define RCC_AHB1SMENR_ICACHESMEN_Msk (0x1UL << RCC_AHB1SMENR_ICACHESMEN_Pos) /*!< 0x20000000 */ +#define RCC_AHB1SMENR_ICACHESMEN RCC_AHB1SMENR_ICACHESMEN_Msk +#define RCC_AHB1SMENR_SRAM1SMEN_Pos (31U) +#define RCC_AHB1SMENR_SRAM1SMEN_Msk (0x1UL << RCC_AHB1SMENR_SRAM1SMEN_Pos) /*!< 0x80000000 */ +#define RCC_AHB1SMENR_SRAM1SMEN RCC_AHB1SMENR_SRAM1SMEN_Msk + +/******************** Bit definition for RCC_AHB2SMENR register **************/ +#define RCC_AHB2SMENR_GPIOASMEN_Pos (0U) +#define RCC_AHB2SMENR_GPIOASMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOASMEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB2SMENR_GPIOASMEN RCC_AHB2SMENR_GPIOASMEN_Msk +#define RCC_AHB2SMENR_GPIOBSMEN_Pos (1U) +#define RCC_AHB2SMENR_GPIOBSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOBSMEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB2SMENR_GPIOBSMEN RCC_AHB2SMENR_GPIOBSMEN_Msk +#define RCC_AHB2SMENR_GPIOCSMEN_Pos (2U) +#define RCC_AHB2SMENR_GPIOCSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOCSMEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB2SMENR_GPIOCSMEN RCC_AHB2SMENR_GPIOCSMEN_Msk +#define RCC_AHB2SMENR_GPIOHSMEN_Pos (7U) +#define RCC_AHB2SMENR_GPIOHSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOHSMEN_Pos) /*!< 0x00000080 */ +#define RCC_AHB2SMENR_GPIOHSMEN RCC_AHB2SMENR_GPIOHSMEN_Msk +#define RCC_AHB2SMENR_AESSMEN_Pos (16U) +#define RCC_AHB2SMENR_AESSMEN_Msk (0x1UL << RCC_AHB2SMENR_AESSMEN_Pos) /*!< 0x00010000 */ +#define RCC_AHB2SMENR_AESSMEN RCC_AHB2SMENR_AESSMEN_Msk +#define RCC_AHB2SMENR_HASHSMEN_Pos (17U) +#define RCC_AHB2SMENR_HASHSMEN_Msk (0x1UL << RCC_AHB2SMENR_HASHSMEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB2SMENR_HASHSMEN RCC_AHB2SMENR_HASHSMEN_Msk +#define RCC_AHB2SMENR_RNGSMEN_Pos (18U) +#define RCC_AHB2SMENR_RNGSMEN_Msk (0x1UL << RCC_AHB2SMENR_RNGSMEN_Pos) /*!< 0x00040000 */ +#define RCC_AHB2SMENR_RNGSMEN RCC_AHB2SMENR_RNGSMEN_Msk +#define RCC_AHB2SMENR_SAESSMEN_Pos (19U) +#define RCC_AHB2SMENR_SAESSMEN_Msk (0x1UL << RCC_AHB2SMENR_SAESSMEN_Pos) /*!< 0x00080000 */ +#define RCC_AHB2SMENR_SAESSMEN RCC_AHB2SMENR_SAESSMEN_Msk +#define RCC_AHB2SMENR_PKASMEN_Pos (21U) +#define RCC_AHB2SMENR_PKASMEN_Msk (0x1UL << RCC_AHB2SMENR_PKASMEN_Pos) /*!< 0x00200000 */ +#define RCC_AHB2SMENR_PKASMEN RCC_AHB2SMENR_PKASMEN_Msk +#define RCC_AHB2SMENR_SRAM2SMEN_Pos (30U) +#define RCC_AHB2SMENR_SRAM2SMEN_Msk (0x1UL << RCC_AHB2SMENR_SRAM2SMEN_Pos) /*!< 0x40000000 */ +#define RCC_AHB2SMENR_SRAM2SMEN RCC_AHB2SMENR_SRAM2SMEN_Msk + +/******************** Bit definition for RCC_AHB4SMENR register **************/ +#define RCC_AHB4SMENR_PWRSMEN_Pos (2U) +#define RCC_AHB4SMENR_PWRSMEN_Msk (0x1UL << RCC_AHB4SMENR_PWRSMEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB4SMENR_PWRSMEN RCC_AHB4SMENR_PWRSMEN_Msk +#define RCC_AHB4SMENR_ADC4SMEN_Pos (5U) +#define RCC_AHB4SMENR_ADC4SMEN_Msk (0x1UL << RCC_AHB4SMENR_ADC4SMEN_Pos) /*!< 0x00000040 */ +#define RCC_AHB4SMENR_ADC4SMEN RCC_AHB4SMENR_ADC4SMEN_Msk + +/******************** Bit definition for RCC_AHB5SMENR register **************/ +#define RCC_AHB5SMENR_RADIOSMEN_Pos (0U) +#define RCC_AHB5SMENR_RADIOSMEN_Msk (0x1UL << RCC_AHB5SMENR_RADIOSMEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB5SMENR_RADIOSMEN RCC_AHB5SMENR_RADIOSMEN_Msk +#define RCC_AHB5SMENR_PTACONVSMEN_Pos (1U) +#define RCC_AHB5SMENR_PTACONVSMEN_Msk (0x1UL << RCC_AHB5SMENR_PTACONVSMEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB5SMENR_PTACONVSMEN RCC_AHB5SMENR_PTACONVSMEN_Msk + +/******************** Bit definition for RCC_APB1SMENR1 register **************/ +#define RCC_APB1SMENR1_TIM2SMEN_Pos (0U) +#define RCC_APB1SMENR1_TIM2SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM2SMEN_Pos) /*!< 0x00000001 */ +#define RCC_APB1SMENR1_TIM2SMEN RCC_APB1SMENR1_TIM2SMEN_Msk +#define RCC_APB1SMENR1_TIM3SMEN_Pos (1U) +#define RCC_APB1SMENR1_TIM3SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM3SMEN_Pos) /*!< 0x00000002 */ +#define RCC_APB1SMENR1_TIM3SMEN RCC_APB1SMENR1_TIM3SMEN_Msk +#define RCC_APB1SMENR1_WWDGSMEN_Pos (11U) +#define RCC_APB1SMENR1_WWDGSMEN_Msk (0x1UL << RCC_APB1SMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */ +#define RCC_APB1SMENR1_WWDGSMEN RCC_APB1SMENR1_WWDGSMEN_Msk +#define RCC_APB1SMENR1_USART2SMEN_Pos (17U) +#define RCC_APB1SMENR1_USART2SMEN_Msk (0x1UL << RCC_APB1SMENR1_USART2SMEN_Pos) /*!< 0x00020000 */ +#define RCC_APB1SMENR1_USART2SMEN RCC_APB1SMENR1_USART2SMEN_Msk +#define RCC_APB1SMENR1_I2C1SMEN_Pos (21U) +#define RCC_APB1SMENR1_I2C1SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C1SMEN_Pos) /*!< 0x00200000 */ +#define RCC_APB1SMENR1_I2C1SMEN RCC_APB1SMENR1_I2C1SMEN_Msk + +/******************** Bit definition for RCC_APB1SMENR2 register **************/ +#define RCC_APB1SMENR2_LPTIM2SMEN_Pos (5U) +#define RCC_APB1SMENR2_LPTIM2SMEN_Msk (0x1UL << RCC_APB1SMENR2_LPTIM2SMEN_Pos) /*!< 0x00000020 */ +#define RCC_APB1SMENR2_LPTIM2SMEN RCC_APB1SMENR2_LPTIM2SMEN_Msk + +/******************** Bit definition for RCC_APB2SMENR register **************/ +#define RCC_APB2SMENR_TIM1SMEN_Pos (11U) +#define RCC_APB2SMENR_TIM1SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM1SMEN_Pos) /*!< 0x00000800 */ +#define RCC_APB2SMENR_TIM1SMEN RCC_APB2SMENR_TIM1SMEN_Msk +#define RCC_APB2SMENR_SPI1SMEN_Pos (12U) +#define RCC_APB2SMENR_SPI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */ +#define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk +#define RCC_APB2SMENR_USART1SMEN_Pos (14U) +#define RCC_APB2SMENR_USART1SMEN_Msk (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */ +#define RCC_APB2SMENR_USART1SMEN RCC_APB2SMENR_USART1SMEN_Msk +#define RCC_APB2SMENR_TIM16SMEN_Pos (17U) +#define RCC_APB2SMENR_TIM16SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM16SMEN_Pos) /*!< 0x00020000 */ +#define RCC_APB2SMENR_TIM16SMEN RCC_APB2SMENR_TIM16SMEN_Msk +#define RCC_APB2SMENR_TIM17SMEN_Pos (18U) +#define RCC_APB2SMENR_TIM17SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM17SMEN_Pos) /*!< 0x00040000 */ +#define RCC_APB2SMENR_TIM17SMEN RCC_APB2SMENR_TIM17SMEN_Msk +#define RCC_APB2SMENR_SAI1SMEN_Pos (21U) +#define RCC_APB2SMENR_SAI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SAI1SMEN_Pos) /*!< 0x00200000 */ +#define RCC_APB2SMENR_SAI1SMEN RCC_APB2SMENR_SAI1SMEN_Msk + +/******************** Bit definition for RCC_APB7SMENR register **************/ +#define RCC_APB7SMENR_SYSCFGSMEN_Pos (1U) +#define RCC_APB7SMENR_SYSCFGSMEN_Msk (0x1UL << RCC_APB7SMENR_SYSCFGSMEN_Pos) /*!< 0x00000002 */ +#define RCC_APB7SMENR_SYSCFGSMEN RCC_APB7SMENR_SYSCFGSMEN_Msk +#define RCC_APB7SMENR_SPI3SMEN_Pos (5U) +#define RCC_APB7SMENR_SPI3SMEN_Msk (0x1UL << RCC_APB7SMENR_SPI3SMEN_Pos) /*!< 0x00000020 */ +#define RCC_APB7SMENR_SPI3SMEN RCC_APB7SMENR_SPI3SMEN_Msk +#define RCC_APB7SMENR_LPUART1SMEN_Pos (6U) +#define RCC_APB7SMENR_LPUART1SMEN_Msk (0x1UL << RCC_APB7SMENR_LPUART1SMEN_Pos) /*!< 0x00000040 */ +#define RCC_APB7SMENR_LPUART1SMEN RCC_APB7SMENR_LPUART1SMEN_Msk +#define RCC_APB7SMENR_I2C3SMEN_Pos (7U) +#define RCC_APB7SMENR_I2C3SMEN_Msk (0x1UL << RCC_APB7SMENR_I2C3SMEN_Pos) /*!< 0x00000080 */ +#define RCC_APB7SMENR_I2C3SMEN RCC_APB7SMENR_I2C3SMEN_Msk +#define RCC_APB7SMENR_LPTIM1SMEN_Pos (11U) +#define RCC_APB7SMENR_LPTIM1SMEN_Msk (0x1UL << RCC_APB7SMENR_LPTIM1SMEN_Pos) /*!< 0x00000800 */ +#define RCC_APB7SMENR_LPTIM1SMEN RCC_APB7SMENR_LPTIM1SMEN_Msk +#define RCC_APB7SMENR_COMPSMEN_Pos (15U) +#define RCC_APB7SMENR_COMPSMEN_Msk (0x1UL << RCC_APB7SMENR_COMPSMEN_Pos) /*!< 0x00008000 */ +#define RCC_APB7SMENR_COMPSMEN RCC_APB7SMENR_COMPSMEN_Msk +#define RCC_APB7SMENR_RTCAPBSMEN_Pos (21U) +#define RCC_APB7SMENR_RTCAPBSMEN_Msk (0x1UL << RCC_APB7SMENR_RTCAPBSMEN_Pos) /*!< 0x00200000 */ +#define RCC_APB7SMENR_RTCAPBSMEN RCC_APB7SMENR_RTCAPBSMEN_Msk + +/******************** Bit definition for RCC_CCIPR1 register ******************/ +#define RCC_CCIPR1_USART1SEL_Pos (0U) +#define RCC_CCIPR1_USART1SEL_Msk (0x3UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000003 */ +#define RCC_CCIPR1_USART1SEL RCC_CCIPR1_USART1SEL_Msk +#define RCC_CCIPR1_USART1SEL_0 (0x1UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR1_USART1SEL_1 (0x2UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR1_USART2SEL_Pos (2U) +#define RCC_CCIPR1_USART2SEL_Msk (0x3UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x0000000C */ +#define RCC_CCIPR1_USART2SEL RCC_CCIPR1_USART2SEL_Msk +#define RCC_CCIPR1_USART2SEL_0 (0x1UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x00000004 */ +#define RCC_CCIPR1_USART2SEL_1 (0x2UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x00000008 */ +#define RCC_CCIPR1_I2C1SEL_Pos (10U) +#define RCC_CCIPR1_I2C1SEL_Msk (0x3UL << RCC_CCIPR1_I2C1SEL_Pos) /*!< 0x00000C00 */ +#define RCC_CCIPR1_I2C1SEL RCC_CCIPR1_I2C1SEL_Msk +#define RCC_CCIPR1_I2C1SEL_0 (0x1UL << RCC_CCIPR1_I2C1SEL_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR1_I2C1SEL_1 (0x2UL << RCC_CCIPR1_I2C1SEL_Pos) /*!< 0x00000800 */ +#define RCC_CCIPR1_LPTIM2SEL_Pos (18U) +#define RCC_CCIPR1_LPTIM2SEL_Msk (0x3UL << RCC_CCIPR1_LPTIM2SEL_Pos) /*!< 0x000C0000 */ +#define RCC_CCIPR1_LPTIM2SEL RCC_CCIPR1_LPTIM2SEL_Msk +#define RCC_CCIPR1_LPTIM2SEL_0 (0x1UL << RCC_CCIPR1_LPTIM2SEL_Pos) /*!< 0x00040000 */ +#define RCC_CCIPR1_LPTIM2SEL_1 (0x2UL << RCC_CCIPR1_LPTIM2SEL_Pos) /*!< 0x00080000 */ +#define RCC_CCIPR1_SPI1SEL_Pos (20U) +#define RCC_CCIPR1_SPI1SEL_Msk (0x3UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x00300000 */ +#define RCC_CCIPR1_SPI1SEL RCC_CCIPR1_SPI1SEL_Msk +#define RCC_CCIPR1_SPI1SEL_0 (0x1UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x00100000 */ +#define RCC_CCIPR1_SPI1SEL_1 (0x2UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x00200000 */ +#define RCC_CCIPR1_SYSTICKSEL_Pos (22U) +#define RCC_CCIPR1_SYSTICKSEL_Msk (0x3UL << RCC_CCIPR1_SYSTICKSEL_Pos) /*!< 0x00C00000 */ +#define RCC_CCIPR1_SYSTICKSEL RCC_CCIPR1_SYSTICKSEL_Msk +#define RCC_CCIPR1_SYSTICKSEL_0 (0x1UL << RCC_CCIPR1_SYSTICKSEL_Pos) /*!< 0x00400000 */ +#define RCC_CCIPR1_SYSTICKSEL_1 (0x2UL << RCC_CCIPR1_SYSTICKSEL_Pos) /*!< 0x00800000 */ +#define RCC_CCIPR1_TIMICSEL_Pos (31U) +#define RCC_CCIPR1_TIMICSEL_Msk (0x1UL << RCC_CCIPR1_TIMICSEL_Pos) /*!< 0x80000000 */ +#define RCC_CCIPR1_TIMICSEL RCC_CCIPR1_TIMICSEL_Msk + +/******************** Bit definition for RCC_CCIPR2 register ******************/ +#define RCC_CCIPR2_SAI1SEL_Pos (5U) +#define RCC_CCIPR2_SAI1SEL_Msk (0x7UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x000000E0 */ +#define RCC_CCIPR2_SAI1SEL RCC_CCIPR2_SAI1SEL_Msk +#define RCC_CCIPR2_SAI1SEL_0 (0x1UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR2_SAI1SEL_1 (0x2UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR2_SAI1SEL_2 (0x4UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x00000080 */ +#define RCC_CCIPR2_RNGSEL_Pos (12U) +#define RCC_CCIPR2_RNGSEL_Msk (0x3UL << RCC_CCIPR2_RNGSEL_Pos) /*!< 0x00300000 */ +#define RCC_CCIPR2_RNGSEL RCC_CCIPR2_RNGSEL_Msk +#define RCC_CCIPR2_RNGSEL_0 (0x1UL << RCC_CCIPR2_RNGSEL_Pos) /*!< 0x00100000 */ +#define RCC_CCIPR2_RNGSEL_1 (0x2UL << RCC_CCIPR2_RNGSEL_Pos) /*!< 0x00200000 */ +#if !defined (STM32WBAXX_SI_CUT1_0) +#define RCC_CCIPR2_ASSEL_Pos (30U) +#define RCC_CCIPR2_ASSEL_Msk (0x1UL << RCC_CCIPR2_ASSEL_Pos) /*!< 0x40000000 */ +#define RCC_CCIPR2_ASSEL RCC_CCIPR2_ASSEL_Msk +#endif + +/******************** Bit definition for RCC_CCIPR3 register ***************/ +#define RCC_CCIPR3_LPUART1SEL_Pos (0U) +#define RCC_CCIPR3_LPUART1SEL_Msk (0x3UL << RCC_CCIPR3_LPUART1SEL_Pos) /*!< 0x00000003 */ +#define RCC_CCIPR3_LPUART1SEL RCC_CCIPR3_LPUART1SEL_Msk +#define RCC_CCIPR3_LPUART1SEL_0 (0x1UL << RCC_CCIPR3_LPUART1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR3_LPUART1SEL_1 (0x2UL << RCC_CCIPR3_LPUART1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR3_SPI3SEL_Pos (3U) +#define RCC_CCIPR3_SPI3SEL_Msk (0x3UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000018 */ +#define RCC_CCIPR3_SPI3SEL RCC_CCIPR3_SPI3SEL_Msk +#define RCC_CCIPR3_SPI3SEL_0 (0x1UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000008 */ +#define RCC_CCIPR3_SPI3SEL_1 (0x2UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR3_I2C3SEL_Pos (6U) +#define RCC_CCIPR3_I2C3SEL_Msk (0x3UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x000000C0 */ +#define RCC_CCIPR3_I2C3SEL RCC_CCIPR3_I2C3SEL_Msk +#define RCC_CCIPR3_I2C3SEL_0 (0x1UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR3_I2C3SEL_1 (0x2UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000080 */ +#define RCC_CCIPR3_LPTIM1SEL_Pos (10U) +#define RCC_CCIPR3_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00000C00 */ +#define RCC_CCIPR3_LPTIM1SEL RCC_CCIPR3_LPTIM1SEL_Msk +#define RCC_CCIPR3_LPTIM1SEL_0 (0x1UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR3_LPTIM1SEL_1 (0x2UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00000800 */ +#define RCC_CCIPR3_ADCSEL_Pos (12U) +#define RCC_CCIPR3_ADCSEL_Msk (0x7UL << RCC_CCIPR3_ADCSEL_Pos) /*!< 0x00007000 */ +#define RCC_CCIPR3_ADCSEL RCC_CCIPR3_ADCSEL_Msk +#define RCC_CCIPR3_ADCSEL_0 (0x1UL << RCC_CCIPR3_ADCSEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR3_ADCSEL_1 (0x2UL << RCC_CCIPR3_ADCSEL_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR3_ADCSEL_2 (0x4UL << RCC_CCIPR3_ADCSEL_Pos) /*!< 0x00004000 */ + +/******************** Bit definition for RCC_BDCR1 register ******************/ +#define RCC_BDCR1_LSEON_Pos (0U) +#define RCC_BDCR1_LSEON_Msk (0x1UL << RCC_BDCR1_LSEON_Pos) /*!< 0x00000001 */ +#define RCC_BDCR1_LSEON RCC_BDCR1_LSEON_Msk +#define RCC_BDCR1_LSERDY_Pos (1U) +#define RCC_BDCR1_LSERDY_Msk (0x1UL << RCC_BDCR1_LSERDY_Pos) /*!< 0x00000002 */ +#define RCC_BDCR1_LSERDY RCC_BDCR1_LSERDY_Msk +#define RCC_BDCR1_LSEBYP_Pos (2U) +#define RCC_BDCR1_LSEBYP_Msk (0x1UL << RCC_BDCR1_LSEBYP_Pos) /*!< 0x00000004 */ +#define RCC_BDCR1_LSEBYP RCC_BDCR1_LSEBYP_Msk +#define RCC_BDCR1_LSEDRV_Pos (3U) +#define RCC_BDCR1_LSEDRV_Msk (0x3UL << RCC_BDCR1_LSEDRV_Pos) /*!< 0x00000018 */ +#define RCC_BDCR1_LSEDRV RCC_BDCR1_LSEDRV_Msk +#define RCC_BDCR1_LSEDRV_0 (0x1UL << RCC_BDCR1_LSEDRV_Pos) /*!< 0x00000008 */ +#define RCC_BDCR1_LSEDRV_1 (0x2UL << RCC_BDCR1_LSEDRV_Pos) /*!< 0x00000010 */ +#define RCC_BDCR1_LSECSSON_Pos (5U) +#define RCC_BDCR1_LSECSSON_Msk (0x1UL << RCC_BDCR1_LSECSSON_Pos) /*!< 0x00000020 */ +#define RCC_BDCR1_LSECSSON RCC_BDCR1_LSECSSON_Msk +#define RCC_BDCR1_LSECSSD_Pos (6U) +#define RCC_BDCR1_LSECSSD_Msk (0x1UL << RCC_BDCR1_LSECSSD_Pos) /*!< 0x00000040 */ +#define RCC_BDCR1_LSECSSD RCC_BDCR1_LSECSSD_Msk +#define RCC_BDCR1_LSESYSEN_Pos (7U) +#define RCC_BDCR1_LSESYSEN_Msk (0x1UL << RCC_BDCR1_LSESYSEN_Pos) /*!< 0x00000080 */ +#define RCC_BDCR1_LSESYSEN RCC_BDCR1_LSESYSEN_Msk +#define RCC_BDCR1_RTCSEL_Pos (8U) +#define RCC_BDCR1_RTCSEL_Msk (0x3UL << RCC_BDCR1_RTCSEL_Pos) /*!< 0x00000300 */ +#define RCC_BDCR1_RTCSEL RCC_BDCR1_RTCSEL_Msk +#define RCC_BDCR1_RTCSEL_0 (0x1UL << RCC_BDCR1_RTCSEL_Pos) /*!< 0x00000100 */ +#define RCC_BDCR1_RTCSEL_1 (0x2UL << RCC_BDCR1_RTCSEL_Pos) /*!< 0x00000200 */ +#define RCC_BDCR1_LSESYSRDY_Pos (11U) +#define RCC_BDCR1_LSESYSRDY_Msk (0x1UL << RCC_BDCR1_LSESYSRDY_Pos) /*!< 0x00000800 */ +#define RCC_BDCR1_LSESYSRDY RCC_BDCR1_LSESYSRDY_Msk +#define RCC_BDCR1_LSEGFON_Pos (12U) +#define RCC_BDCR1_LSEGFON_Msk (0x1UL << RCC_BDCR1_LSEGFON_Pos) /*!< 0x00001000 */ +#define RCC_BDCR1_LSEGFON RCC_BDCR1_LSEGFON_Msk +#define RCC_BDCR1_LSETRIM_Pos (13U) +#define RCC_BDCR1_LSETRIM_Msk (0x3UL << RCC_BDCR1_LSETRIM_Pos) /*!< 0x00006000 */ +#define RCC_BDCR1_LSETRIM RCC_BDCR1_LSETRIM_Msk +#define RCC_BDCR1_LSETRIM_0 (0x1UL << RCC_BDCR1_LSETRIM_Pos) /*!< 0x00002000 */ +#define RCC_BDCR1_LSETRIM_1 (0x2UL << RCC_BDCR1_LSETRIM_Pos) /*!< 0x00004000 */ +#define RCC_BDCR1_BDRST_Pos (16U) +#define RCC_BDCR1_BDRST_Msk (0x1UL << RCC_BDCR1_BDRST_Pos) /*!< 0x00010000 */ +#define RCC_BDCR1_BDRST RCC_BDCR1_BDRST_Msk +#define RCC_BDCR1_RADIOSTSEL_Pos (18U) +#define RCC_BDCR1_RADIOSTSEL_Msk (0x3UL << RCC_BDCR1_RADIOSTSEL_Pos) /*!< 0x000C0000 */ +#define RCC_BDCR1_RADIOSTSEL RCC_BDCR1_RADIOSTSEL_Msk +#define RCC_BDCR1_RADIOSTSEL_0 (0x1UL << RCC_BDCR1_RADIOSTSEL_Pos) /*!< 0x00040000 */ +#define RCC_BDCR1_RADIOSTSEL_1 (0x2UL << RCC_BDCR1_RADIOSTSEL_Pos) /*!< 0x00080000 */ +#define RCC_BDCR1_LSCOEN_Pos (24U) +#define RCC_BDCR1_LSCOEN_Msk (0x1UL << RCC_BDCR1_LSCOEN_Pos) /*!< 0x01000000 */ +#define RCC_BDCR1_LSCOEN RCC_BDCR1_LSCOEN_Msk +#define RCC_BDCR1_LSCOSEL_Pos (25U) +#define RCC_BDCR1_LSCOSEL_Msk (0x1UL << RCC_BDCR1_LSCOSEL_Pos) /*!< 0x02000000 */ +#define RCC_BDCR1_LSCOSEL RCC_BDCR1_LSCOSEL_Msk +#define RCC_BDCR1_LSI1ON_Pos (26U) +#define RCC_BDCR1_LSI1ON_Msk (0x1UL << RCC_BDCR1_LSI1ON_Pos) /*!< 0x04000000 */ +#define RCC_BDCR1_LSI1ON RCC_BDCR1_LSI1ON_Msk +#define RCC_BDCR1_LSI1RDY_Pos (27U) +#define RCC_BDCR1_LSI1RDY_Msk (0x1UL << RCC_BDCR1_LSI1RDY_Pos) /*!< 0x08000000 */ +#define RCC_BDCR1_LSI1RDY RCC_BDCR1_LSI1RDY_Msk +#define RCC_BDCR1_LSI1PREDIV_Pos (28U) +#define RCC_BDCR1_LSI1PREDIV_Msk (0x1UL << RCC_BDCR1_LSI1PREDIV_Pos) /*!< 0x10000000 */ +#define RCC_BDCR1_LSI1PREDIV RCC_BDCR1_LSI1PREDIV_Msk +#define RCC_BDCR1_LSI2ON_Pos (29U) +#define RCC_BDCR1_LSI2ON_Msk (0x1UL << RCC_BDCR1_LSI2ON_Pos) /*!< 0x20000000 */ +#define RCC_BDCR1_LSI2ON RCC_BDCR1_LSI2ON_Msk +#define RCC_BDCR1_LSI2RDY_Pos (30U) +#define RCC_BDCR1_LSI2RDY_Msk (0x1UL << RCC_BDCR1_LSI2RDY_Pos) /*!< 0x40000000 */ +#define RCC_BDCR1_LSI2RDY RCC_BDCR1_LSI2RDY_Msk + +/******************** Bit definition for RCC_CSR register *******************/ +#define RCC_CSR_RMVF_Pos (23U) +#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */ +#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk +#define RCC_CSR_OBLRSTF_Pos (25U) +#define RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */ +#define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk +#define RCC_CSR_PINRSTF_Pos (26U) +#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */ +#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk +#define RCC_CSR_BORRSTF_Pos (27U) +#define RCC_CSR_BORRSTF_Msk (0x1UL << RCC_CSR_BORRSTF_Pos) /*!< 0x08000000 */ +#define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk +#define RCC_CSR_SFTRSTF_Pos (28U) +#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */ +#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk +#define RCC_CSR_IWDGRSTF_Pos (29U) +#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */ +#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk +#define RCC_CSR_WWDGRSTF_Pos (30U) +#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */ +#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk +#define RCC_CSR_LPWRRSTF_Pos (31U) +#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */ +#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk + +/******************** Bit definition for RCC_BDCR2 register *******************/ +#define RCC_BDCR2_LSI2MODE_Pos (0U) +#define RCC_BDCR2_LSI2MODE_Msk (0x7UL << RCC_BDCR2_LSI2MODE_Pos) /*!< 0x00000007 */ +#define RCC_BDCR2_LSI2MODE RCC_BDCR2_LSI2MODE_Msk +#define RCC_BDCR2_LSI2MODE_0 (0x1UL << RCC_BDCR2_LSI2MODE_Pos) /*!< 0x00000001 */ +#define RCC_BDCR2_LSI2MODE_1 (0x2UL << RCC_BDCR2_LSI2MODE_Pos) /*!< 0x00000002 */ +#define RCC_BDCR2_LSI2MODE_2 (0x4UL << RCC_BDCR2_LSI2MODE_Pos) /*!< 0x00000004 */ +#define RCC_BDCR2_LSI2CFG_Pos (4U) +#define RCC_BDCR2_LSI2CFG_Msk (0xFUL << RCC_BDCR2_LSI2CFG_Pos) /*!< 0x000000F0 */ +#define RCC_BDCR2_LSI2CFG RCC_BDCR2_LSI2CFG_Msk +#define RCC_BDCR2_LSI2CFG_0 (0x1UL << RCC_BDCR2_LSI2CFG_Pos) /*!< 0x00000010 */ +#define RCC_BDCR2_LSI2CFG_1 (0x2UL << RCC_BDCR2_LSI2CFG_Pos) /*!< 0x00000020 */ +#define RCC_BDCR2_LSI2CFG_2 (0x4UL << RCC_BDCR2_LSI2CFG_Pos) /*!< 0x00000040 */ +#define RCC_BDCR2_LSI2CFG_3 (0x8UL << RCC_BDCR2_LSI2CFG_Pos) /*!< 0x00000080 */ + +/******************** Bit definition for RCC_SECCFGR register **************/ +#define RCC_SECCFGR_HSISEC_Pos (0U) +#define RCC_SECCFGR_HSISEC_Msk (0x1UL << RCC_SECCFGR_HSISEC_Pos) /*!< 0x00000001 */ +#define RCC_SECCFGR_HSISEC RCC_SECCFGR_HSISEC_Msk +#define RCC_SECCFGR_HSESEC_Pos (1U) +#define RCC_SECCFGR_HSESEC_Msk (0x1UL << RCC_SECCFGR_HSESEC_Pos) /*!< 0x00000002 */ +#define RCC_SECCFGR_HSESEC RCC_SECCFGR_HSESEC_Msk +#define RCC_SECCFGR_LSISEC_Pos (3U) +#define RCC_SECCFGR_LSISEC_Msk (0x1UL << RCC_SECCFGR_LSISEC_Pos) /*!< 0x00000008 */ +#define RCC_SECCFGR_LSISEC RCC_SECCFGR_LSISEC_Msk +#define RCC_SECCFGR_LSESEC_Pos (4U) +#define RCC_SECCFGR_LSESEC_Msk (0x1UL << RCC_SECCFGR_LSESEC_Pos) /*!< 0x00000010 */ +#define RCC_SECCFGR_LSESEC RCC_SECCFGR_LSESEC_Msk +#define RCC_SECCFGR_SYSCLKSEC_Pos (5U) +#define RCC_SECCFGR_SYSCLKSEC_Msk (0x1UL << RCC_SECCFGR_SYSCLKSEC_Pos) /*!< 0x00000020 */ +#define RCC_SECCFGR_SYSCLKSEC RCC_SECCFGR_SYSCLKSEC_Msk +#define RCC_SECCFGR_PRESCSEC_Pos (6U) +#define RCC_SECCFGR_PRESCSEC_Msk (0x1UL << RCC_SECCFGR_PRESCSEC_Pos) /*!< 0x00000040 */ +#define RCC_SECCFGR_PRESCSEC RCC_SECCFGR_PRESCSEC_Msk +#define RCC_SECCFGR_PLL1SEC_Pos (7U) +#define RCC_SECCFGR_PLL1SEC_Msk (0x1UL << RCC_SECCFGR_PLL1SEC_Pos) /*!< 0x00000080 */ +#define RCC_SECCFGR_PLL1SEC RCC_SECCFGR_PLL1SEC_Msk +#define RCC_SECCFGR_RMVFSEC_Pos (12U) +#define RCC_SECCFGR_RMVFSEC_Msk (0x1UL << RCC_SECCFGR_RMVFSEC_Pos) /*!< 0x00001000 */ +#define RCC_SECCFGR_RMVFSEC RCC_SECCFGR_RMVFSEC_Msk + +/******************** Bit definition for RCC_PRIVCFGR register **************/ +#define RCC_PRIVCFGR_SPRIV_Pos (0U) +#define RCC_PRIVCFGR_SPRIV_Msk (0x1UL << RCC_PRIVCFGR_SPRIV_Pos) /*!< 0x00000001 */ +#define RCC_PRIVCFGR_SPRIV RCC_PRIVCFGR_SPRIV_Msk +#define RCC_PRIVCFGR_NSPRIV_Pos (1U) +#define RCC_PRIVCFGR_NSPRIV_Msk (0x1UL << RCC_PRIVCFGR_NSPRIV_Pos) /*!< 0x00000002 */ +#define RCC_PRIVCFGR_NSPRIV RCC_PRIVCFGR_NSPRIV_Msk + +#if !defined (STM32WBAXX_SI_CUT1_0) +/******************** Bit definition for RCC_ASCR register **************/ +#define RCC_ASCR_CEN_Pos (0U) +#define RCC_ASCR_CEN RCC_ASCR_CEN_Msk +#define RCC_ASCR_CEN_Msk (0x1UL << RCC_ASCR_CEN_Pos) /*!< 0x00000001 */ +#define RCC_ASCR_PSC_Pos (8U) +#define RCC_ASCR_PSC_Msk (0x7FUL << RCC_ASCR_PSC_Pos) /*!< 0x00007F00 */ +#define RCC_ASCR_PSC RCC_ASCR_PSC_Msk +#define RCC_ASCR_CPS_Pos (16U) +#define RCC_ASCR_CPS_Msk (0x7FUL << RCC_ASCR_CPS_Pos) /*!< 0x007F0000 */ +#define RCC_ASCR_CPS RCC_ASCR_CPS_Msk + +/******************** Bit definition for RCC_ASIER register **************/ +#define RCC_ASIER_CAIE_Pos (0U) +#define RCC_ASIER_CAIE RCC_ASIER_CAIE_Msk +#define RCC_ASIER_CAIE_Msk (0x1UL << RCC_ASIER_CAIE_Pos) /*!< 0x00000001 */ +#define RCC_ASIER_COIE_Pos (1U) +#define RCC_ASIER_COIE_Msk (0x1UL << RCC_ASIER_COIE_Pos) /*!< 0x00000002 */ +#define RCC_ASIER_COIE RCC_ASIER_COIE_Msk +#define RCC_ASIER_CAEIE_Pos (2U) +#define RCC_ASIER_CAEIE_Msk (0x1UL << RCC_ASIER_CAEIE_Pos) /*!< 0x00000004 */ +#define RCC_ASIER_CAEIE RCC_ASIER_CAEIE_Msk + +/******************** Bit definition for RCC_ASSR register **************/ +#define RCC_ASSR_CAF_Pos (0U) +#define RCC_ASSR_CAF RCC_ASSR_CAF_Msk +#define RCC_ASSR_CAF_Msk (0x1UL << RCC_ASSR_CAF_Pos) /*!< 0x00000001 */ +#define RCC_ASSR_COF_Pos (1U) +#define RCC_ASSR_COF_Msk (0x1UL << RCC_ASSR_COF_Pos) /*!< 0x00000002 */ +#define RCC_ASSR_COF RCC_ASSR_COF_Msk +#define RCC_ASSR_CAEF_Pos (2U) +#define RCC_ASSR_CAEF_Msk (0x1UL << RCC_ASSR_CAEF_Pos) /*!< 0x00000004 */ +#define RCC_ASSR_CAEF RCC_ASSR_CAEF_Msk + +/******************** Bit definition for RCC_ASCNTR register **************/ +#define RCC_ASCNTR_CNT_Pos (0U) +#define RCC_ASCNTR_CNT RCC_ASCNTR_CNT_Msk +#define RCC_ASCNTR_CNT_Msk (0xFFFFFUL << RCC_ASCNTR_CNT_Pos) /*!< 0x000FFFFF */ + +/******************** Bit definition for RCC_ASARR register **************/ +#define RCC_ASARR_AR_Pos (0U) +#define RCC_ASARR_AR RCC_ASARR_AR_Msk +#define RCC_ASARR_AR_Msk (0xFFFFFUL << RCC_ASARR_AR_Pos) /*!< 0x000FFFFF */ + +/******************** Bit definition for RCC_ASCAR register **************/ +#define RCC_ASCAR_CA_Pos (0U) +#define RCC_ASCAR_CA RCC_ASCAR_CA_Msk +#define RCC_ASCAR_CA_Msk (0x7FFFFFFUL << RCC_ASCAR_CA_Pos) /*!< 0x07FFFFFF */ + +/******************** Bit definition for RCC_ASCOR register **************/ +#define RCC_ASCOR_CO_Pos (0U) +#define RCC_ASCOR_CO RCC_ASCOR_CO_Msk +#define RCC_ASCOR_CO_Msk (0xFFFFFUL << RCC_ASCOR_CO_Pos) /*!< 0x000FFFFF */ + +#endif +/******************** Bit definition for RCC_CFGR4 register *******************/ +#define RCC_CFGR4_HPRE5_Pos (0U) +#define RCC_CFGR4_HPRE5_Msk (0x7UL << RCC_CFGR4_HPRE5_Pos) /*!< 0x00000007 */ +#define RCC_CFGR4_HPRE5 RCC_CFGR4_HPRE5_Msk +#define RCC_CFGR4_HPRE5_0 (0x1UL << RCC_CFGR4_HPRE5_Pos) /*!< 0x00000001 */ +#define RCC_CFGR4_HPRE5_1 (0x2UL << RCC_CFGR4_HPRE5_Pos) /*!< 0x00000002 */ +#define RCC_CFGR4_HPRE5_2 (0x4UL << RCC_CFGR4_HPRE5_Pos) /*!< 0x00000004 */ +#define RCC_CFGR4_HDIV5_Pos (4U) +#define RCC_CFGR4_HDIV5_Msk (0x1UL << RCC_CFGR4_HDIV5_Pos) /*!< 0x00000080 */ +#define RCC_CFGR4_HDIV5 RCC_CFGR4_HDIV5_Msk + +/******************** Bit definition for RCC_RADIOENR register **************/ +#define RCC_RADIOENR_BBCLKEN_Pos (1U) +#define RCC_RADIOENR_BBCLKEN_Msk (0x1UL << RCC_RADIOENR_BBCLKEN_Pos) /*!< 0x00000002 */ +#define RCC_RADIOENR_BBCLKEN RCC_RADIOENR_BBCLKEN_Msk +#define RCC_RADIOENR_STRADIOCLKON_Pos (16U) +#define RCC_RADIOENR_STRADIOCLKON_Msk (0x1UL << RCC_RADIOENR_STRADIOCLKON_Pos) /*!< 0x00010000 */ +#define RCC_RADIOENR_STRADIOCLKON RCC_RADIOENR_STRADIOCLKON_Msk +#define RCC_RADIOENR_RADIOCLKRDY_Pos (17U) +#define RCC_RADIOENR_RADIOCLKRDY_Msk (0x1UL << RCC_RADIOENR_RADIOCLKRDY_Pos) /*!< 0x00020000 */ +#define RCC_RADIOENR_RADIOCLKRDY RCC_RADIOENR_RADIOCLKRDY_Msk + +/******************** Bit definition for RCC_ECSCR1 register *******************/ +#define RCC_ECSCR1_HSETRIM_Pos (16U) +#define RCC_ECSCR1_HSETRIM_Msk (0x3FUL << RCC_ECSCR1_HSETRIM_Pos) /*!< 0x003F0000 */ +#define RCC_ECSCR1_HSETRIM RCC_ECSCR1_HSETRIM_Msk +#define RCC_ECSCR1_HSETRIM_0 (0x1UL << RCC_ECSCR1_HSETRIM_Pos) /*!< 0x00010000 */ +#define RCC_ECSCR1_HSETRIM_1 (0x2UL << RCC_ECSCR1_HSETRIM_Pos) /*!< 0x00020000 */ +#define RCC_ECSCR1_HSETRIM_2 (0x4UL << RCC_ECSCR1_HSETRIM_Pos) /*!< 0x00040000 */ +#define RCC_ECSCR1_HSETRIM_3 (0x8UL << RCC_ECSCR1_HSETRIM_Pos) /*!< 0x00080000 */ +#define RCC_ECSCR1_HSETRIM_4 (0x10UL << RCC_ECSCR1_HSETRIM_Pos) /*!< 0x00100000 */ +#define RCC_ECSCR1_HSETRIM_5 (0x20UL << RCC_ECSCR1_HSETRIM_Pos) /*!< 0x00200000 */ + + +/******************************************************************************/ +/* */ +/* RNG */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RNG_CR register *******************/ +#define RNG_CR_RNGEN_Pos (2U) +#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_IE_Pos (3U) +#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_CED_Pos (5U) +#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ +#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_ARDIS_Pos (7U) +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_RNG_CONFIG3_Pos (8U) +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_NISTC_Pos (12U) +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) +#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_RNG_CONFIG2_Pos (13U) +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_CLKDIV_Pos (16U) +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_RNG_CONFIG1_Pos (20U) +#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_CONDRST_Pos (30U) +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONFIGLOCK_Pos (31U) +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk + +/******************** Bits definition for RNG_SR register *******************/ +#define RNG_SR_DRDY_Pos (0U) +#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ +#define RNG_SR_DRDY RNG_SR_DRDY_Msk +#define RNG_SR_CECS_Pos (1U) +#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ +#define RNG_SR_CECS RNG_SR_CECS_Msk +#define RNG_SR_SECS_Pos (2U) +#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ +#define RNG_SR_SECS RNG_SR_SECS_Msk +#define RNG_SR_CEIS_Pos (5U) +#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ +#define RNG_SR_CEIS RNG_SR_CEIS_Msk +#define RNG_SR_SEIS_Pos (6U) +#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ +#define RNG_SR_SEIS RNG_SR_SEIS_Msk + +/******************** Bits definition for RNG_DR register *******************/ +#define RNG_DR_RNDATA_Pos (0U) +#define RNG_DR_RNDATA_Msk (0xFFFFFFFFUL << RNG_DR_RNDATA_Pos) /*!< 0xFFFFFFFF */ +#define RNG_DR_RNDATA RNG_DR_RNDATA_Msk + +/******************** Bits definition for RNG_HTCR register *******************/ +#define RNG_HTCR_HTCFG_Pos (0U) +#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk + + +/******************************************************************************/ +/* */ +/* Real-Time Clock (RTC) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RTC_TR register *******************/ +#define RTC_TR_SU_Pos (0U) +#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */ +#define RTC_TR_SU RTC_TR_SU_Msk +#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */ +#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */ +#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */ +#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */ +#define RTC_TR_ST_Pos (4U) +#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */ +#define RTC_TR_ST RTC_TR_ST_Msk +#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */ +#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */ +#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */ +#define RTC_TR_MNU_Pos (8U) +#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_TR_MNU RTC_TR_MNU_Msk +#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_TR_MNT_Pos (12U) +#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_TR_MNT RTC_TR_MNT_Msk +#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_TR_HU_Pos (16U) +#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_TR_HU RTC_TR_HU_Msk +#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */ +#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */ +#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */ +#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */ +#define RTC_TR_HT_Pos (20U) +#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */ +#define RTC_TR_HT RTC_TR_HT_Msk +#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */ +#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */ +#define RTC_TR_PM_Pos (22U) +#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */ +#define RTC_TR_PM RTC_TR_PM_Msk + +/******************** Bits definition for RTC_DR register *******************/ +#define RTC_DR_DU_Pos (0U) +#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */ +#define RTC_DR_DU RTC_DR_DU_Msk +#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */ +#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */ +#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */ +#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */ +#define RTC_DR_DT_Pos (4U) +#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */ +#define RTC_DR_DT RTC_DR_DT_Msk +#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */ +#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */ +#define RTC_DR_MU_Pos (8U) +#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */ +#define RTC_DR_MU RTC_DR_MU_Msk +#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */ +#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */ +#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */ +#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */ +#define RTC_DR_MT_Pos (12U) +#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */ +#define RTC_DR_MT RTC_DR_MT_Msk +#define RTC_DR_WDU_Pos (13U) +#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */ +#define RTC_DR_WDU RTC_DR_WDU_Msk +#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */ +#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */ +#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */ +#define RTC_DR_YU_Pos (16U) +#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */ +#define RTC_DR_YU RTC_DR_YU_Msk +#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */ +#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */ +#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */ +#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */ +#define RTC_DR_YT_Pos (20U) +#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */ +#define RTC_DR_YT RTC_DR_YT_Msk +#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */ +#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */ +#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */ +#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */ + +/******************** Bits definition for RTC_SSR register ******************/ +#define RTC_SSR_SS_Pos (0U) +#define RTC_SSR_SS_Msk (0xFFFFFFFFUL << RTC_SSR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_SSR_SS RTC_SSR_SS_Msk + +/******************** Bits definition for RTC_ICSR register ******************/ +#define RTC_ICSR_WUTWF_Pos (2U) +#define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */ +#define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk +#define RTC_ICSR_SHPF_Pos (3U) +#define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */ +#define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk +#define RTC_ICSR_INITS_Pos (4U) +#define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */ +#define RTC_ICSR_INITS RTC_ICSR_INITS_Msk +#define RTC_ICSR_RSF_Pos (5U) +#define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */ +#define RTC_ICSR_RSF RTC_ICSR_RSF_Msk +#define RTC_ICSR_INITF_Pos (6U) +#define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */ +#define RTC_ICSR_INITF RTC_ICSR_INITF_Msk +#define RTC_ICSR_INIT_Pos (7U) +#define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */ +#define RTC_ICSR_INIT RTC_ICSR_INIT_Msk +#define RTC_ICSR_BIN_Pos (8U) +#define RTC_ICSR_BIN_Msk (0x3UL << RTC_ICSR_BIN_Pos) /*!< 0x00000300 */ +#define RTC_ICSR_BIN RTC_ICSR_BIN_Msk +#define RTC_ICSR_BIN_0 (0x1UL << RTC_ICSR_BIN_Pos) /*!< 0x00000100 */ +#define RTC_ICSR_BIN_1 (0x2UL << RTC_ICSR_BIN_Pos) /*!< 0x00000200 */ +#define RTC_ICSR_BCDU_Pos (10U) +#define RTC_ICSR_BCDU_Msk (0x7UL << RTC_ICSR_BCDU_Pos) /*!< 0x00001C00 */ +#define RTC_ICSR_BCDU RTC_ICSR_BCDU_Msk +#define RTC_ICSR_BCDU_0 (0x1UL << RTC_ICSR_BCDU_Pos) /*!< 0x00000400 */ +#define RTC_ICSR_BCDU_1 (0x2UL << RTC_ICSR_BCDU_Pos) /*!< 0x00000800 */ +#define RTC_ICSR_BCDU_2 (0x4UL << RTC_ICSR_BCDU_Pos) /*!< 0x00001000 */ +#define RTC_ICSR_RECALPF_Pos (16U) +#define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */ +#define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk + +/******************** Bits definition for RTC_PRER register *****************/ +#define RTC_PRER_PREDIV_S_Pos (0U) +#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */ +#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk +#define RTC_PRER_PREDIV_A_Pos (16U) +#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ +#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk + +/******************** Bits definition for RTC_WUTR register *****************/ +#define RTC_WUTR_WUT_Pos (0U) +#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk +#define RTC_WUTR_WUTOCLR_Pos (16U) +#define RTC_WUTR_WUTOCLR_Msk (0xFFFFUL << RTC_WUTR_WUTOCLR_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUTOCLR RTC_WUTR_WUTOCLR_Msk + +/******************** Bits definition for RTC_CR register *******************/ +#define RTC_CR_WUCKSEL_Pos (0U) +#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */ +#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk +#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */ +#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ +#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ +#define RTC_CR_TSEDGE_Pos (3U) +#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ +#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk +#define RTC_CR_REFCKON_Pos (4U) +#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ +#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk +#define RTC_CR_BYPSHAD_Pos (5U) +#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ +#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk +#define RTC_CR_FMT_Pos (6U) +#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */ +#define RTC_CR_FMT RTC_CR_FMT_Msk +#define RTC_CR_SSRUIE_Pos (7U) +#define RTC_CR_SSRUIE_Msk (0x1UL << RTC_CR_SSRUIE_Pos) /*!< 0x00000080 */ +#define RTC_CR_SSRUIE RTC_CR_SSRUIE_Msk +#define RTC_CR_ALRAE_Pos (8U) +#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ +#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk +#define RTC_CR_ALRBE_Pos (9U) +#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */ +#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk +#define RTC_CR_WUTE_Pos (10U) +#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */ +#define RTC_CR_WUTE RTC_CR_WUTE_Msk +#define RTC_CR_TSE_Pos (11U) +#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */ +#define RTC_CR_TSE RTC_CR_TSE_Msk +#define RTC_CR_ALRAIE_Pos (12U) +#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ +#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk +#define RTC_CR_ALRBIE_Pos (13U) +#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */ +#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk +#define RTC_CR_WUTIE_Pos (14U) +#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */ +#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk +#define RTC_CR_TSIE_Pos (15U) +#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */ +#define RTC_CR_TSIE RTC_CR_TSIE_Msk +#define RTC_CR_ADD1H_Pos (16U) +#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */ +#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk +#define RTC_CR_SUB1H_Pos (17U) +#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ +#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk +#define RTC_CR_BKP_Pos (18U) +#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk +#define RTC_CR_COSEL_Pos (19U) +#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ +#define RTC_CR_COSEL RTC_CR_COSEL_Msk +#define RTC_CR_POL_Pos (20U) +#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */ +#define RTC_CR_POL RTC_CR_POL_Msk +#define RTC_CR_OSEL_Pos (21U) +#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */ +#define RTC_CR_OSEL RTC_CR_OSEL_Msk +#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */ +#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ +#define RTC_CR_COE_Pos (23U) +#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */ +#define RTC_CR_COE RTC_CR_COE_Msk +#define RTC_CR_TAMPTS_Pos (25U) +#define RTC_CR_TAMPTS_Msk (0x1UL << RTC_CR_TAMPTS_Pos) /*!< 0x02000000 */ +#define RTC_CR_TAMPTS RTC_CR_TAMPTS_Msk /*! */ + +/******************** Bits definition for RTC_ALRMAR register ***************/ +#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk +#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk +#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk +#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk +#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk +#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk +#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk +#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk +#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk +#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk +#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk +#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk +#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk +#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk +#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Msk (0x3FUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x3F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_MASKSS_4 (0x10UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x10000000 */ +#define RTC_ALRMASSR_MASKSS_5 (0x20UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x20000000 */ +#define RTC_ALRMASSR_SSCLR_Pos (31U) +#define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk + +/******************** Bits definition for RTC_ALRMBR register ***************/ +#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk +#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk +#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk +#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk +#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk +#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk +#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk +#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk +#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk +#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk +#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk +#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk +#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk +#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMBSSR register *************/ +#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk +#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Msk (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x3F000000 */ +#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk +#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBSSR_MASKSS_4 (0x10UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBSSR_MASKSS_5 (0x20UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBSSR_SSCLR_Pos (31U) +#define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk + +/******************** Bits definition for RTC_SR register *******************/ +#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk +#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk +#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ +#define RTC_SR_WUTF RTC_SR_WUTF_Msk +#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ +#define RTC_SR_TSF RTC_SR_TSF_Msk +#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk +#define RTC_SR_SSRUF_Pos (6U) +#define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SR_SSRUF RTC_SR_SSRUF_Msk + +/******************** Bits definition for RTC_MISR register *****************/ +#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk +#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk +#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk +#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk +#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk +#define RTC_MISR_SSRUMF_Pos (6U) +#define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SMISR register *****************/ +#define RTC_SMISR_ALRAMF_Pos (0U) +#define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk +#define RTC_SMISR_ALRBMF_Pos (1U) +#define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk +#define RTC_SMISR_WUTMF_Pos (2U) +#define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk +#define RTC_SMISR_TSMF_Pos (3U) +#define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk +#define RTC_SMISR_TSOVMF_Pos (4U) +#define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk +#define RTC_SMISR_SSRUMF_Pos (6U) +#define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SCR register ******************/ +#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk +#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk +#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ +#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk +#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ +#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk +#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk +#define RTC_SCR_CSSRUF_Pos (6U) +#define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk + +/******************** Bits definition for RTC_ALRABINR register ******************/ +#define RTC_ALRABINR_SS_Pos (0U) +#define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk + +/******************** Bits definition for RTC_ALRBBINR register ******************/ +#define RTC_ALRBBINR_SS_Pos (0U) +#define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk + + +/******************************************************************************/ +/* */ +/* Serial Audio Interface */ +/* */ +/******************************************************************************/ +/******************** Bit definition for SAI_GCR register *******************/ +#define SAI_GCR_SYNCIN_Pos (0U) +#define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */ +#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!> HSEM_CR_LOCKID_Pos)/* Semaphore Lock ID */ + +#define HSEM_SEMID_MIN (0U) /* HSEM ID Min*/ +#define HSEM_SEMID_MAX (15U) /* HSEM ID Max */ + +#define HSEM_PROCESSID_MIN (0U) /* HSEM Process ID Min */ +#define HSEM_PROCESSID_MAX (255U) /* HSEM Process ID Max */ + +#define HSEM_CLEAR_KEY_MIN (0U) /* HSEM clear Key Min value */ +#define HSEM_CLEAR_KEY_MAX (0xFFFFU) /* HSEM clear Key Max value */ + +/******************************** I2C Instances *******************************/ +#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S)) + +/****************** I2C Instances : wakeup capability from stop modes *********/ +#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) + +/******************* I2C Instances : Group belongingness *********************/ +#define IS_I2C_GRP1_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S)) + +#define IS_I2C_GRP2_INSTANCE(INSTANCE) (((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S)) + +/******************************* AES Instances ********************************/ +#define IS_PKA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == PKA_NS) || ((INSTANCE) == PKA_S)) + +/******************************* RNG Instances ********************************/ +#define IS_RNG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RNG_NS) || ((INSTANCE) == RNG_S)) + +/****************************** RTC Instances *********************************/ +#define IS_RTC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RTC_NS) || ((INSTANCE) == RTC_S)) + +/******************************** SAI Instances *******************************/ +#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A_NS) || ((INSTANCE) == SAI1_Block_A_S) || \ + ((INSTANCE) == SAI1_Block_B_NS) || ((INSTANCE) == SAI1_Block_B_S)) + +/****************************** SMBUS Instances *******************************/ +#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S)) + +/******************* SMBUS Instances : Group membership ***********************/ +#define IS_SMBUS_GRP1_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S)) + +#define IS_SMBUS_GRP2_INSTANCE(INSTANCE) (((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S)) + +/******************************** SPI Instances *******************************/ +#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \ + ((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S)) + +#define IS_SPI_LIMITED_INSTANCE(INSTANCE) (((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S)) + +#define IS_SPI_FULL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S)) + +/******************* SPI Instances : Group belongingness *********************/ +#define IS_SPI_GRP1_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S)) + +#define IS_SPI_GRP2_INSTANCE(INSTANCE) (((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S)) + +/****************** LPTIM Instances : All supported instances *****************/ +#define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/****************** LPTIM Instances : DMA supported instances *****************/ +#define IS_LPTIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/************* LPTIM Instances : at least 1 capture/compare channel ***********/ +#define IS_LPTIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/************* LPTIM Instances : at least 2 capture/compare channel ***********/ +#define IS_LPTIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/****************** LPTIM Instances : supporting encoder interface **************/ +#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/****************** LPTIM Instances : supporting Input Capture **************/ +#define IS_LPTIM_INPUT_CAPTURE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/****************** TIM Instances : All supported instances *******************/ +#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting 32 bits counter ****************/ +#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S)) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/****************** TIM Instances : supporting the break function *************/ +#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/************** TIM Instances : supporting Break source selection *************/ +#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting 2 break inputs *****************/ +#define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) + +/************* TIM Instances : at least 1 capture/compare channel *************/ +#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/************ TIM Instances : at least 2 capture/compare channels *************/ +#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/************ TIM Instances : at least 3 capture/compare channels *************/ +#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/************ TIM Instances : at least 4 capture/compare channels *************/ +#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/****************** TIM Instances : at least 5 capture/compare channels *******/ +#define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) + +/****************** TIM Instances : at least 6 capture/compare channels *******/ +#define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) + +/************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/ +#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/ +#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/ +#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/******************** TIM Instances : DMA burst feature ***********************/ +#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/******************* TIM Instances : output(s) available **********************/ +#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ + (((((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4) || \ + ((CHANNEL) == TIM_CHANNEL_5) || \ + ((CHANNEL) == TIM_CHANNEL_6))) \ + || \ + ((((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1))) \ + || \ + ((((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1)))) + +/****************** TIM Instances : supporting complementary output(s) ********/ +#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ + (((((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)) && \ + ((CHANNEL) == TIM_CHANNEL_1)) \ + || \ + ((((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) && \ + ((CHANNEL) == TIM_CHANNEL_1))) + +/****************** TIM Instances : supporting clock division *****************/ +#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/ +#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/ +#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/****************** TIM Instances : supporting combined 3-phase PWM mode ******/ +#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) + +/****************** TIM Instances : supporting commutation event generation ***/ +#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting counting mode selection ********/ +#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/****************** TIM Instances : supporting encoder interface **************/ +#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/****************** TIM Instances : supporting Hall sensor interface **********/ +#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/**************** TIM Instances : external trigger input available ************/ +#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/************* TIM Instances : supporting ETR source selection ***************/ +#define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/ +#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/ +#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/****************** TIM Instances : supporting OCxREF clear *******************/ +#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/****************** TIM Instances : remapping capability **********************/ +#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/****************** TIM Instances : supporting repetition counter *************/ +#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/ +#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) + +/******************* TIM Instances : Timer input XOR function *****************/ +#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/******************* TIM Instances : Timer input selection ********************/ +#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) ||\ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) ||\ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) ||\ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)||\ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/******************* TIM Instances : supporting HSE32 as input ********************/ +#define IS_TIM_HSE32_INSTANCE(INSTANCE) (((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) ||\ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : Advanced timer instances *******************/ +#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) + +/****************** TIM Instances : supporting synchronization ****************/ +#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1_NS) || ((__INSTANCE__) == TIM1_S) || \ + ((__INSTANCE__) == TIM2_NS) || ((__INSTANCE__) == TIM2_S) || \ + ((__INSTANCE__) == TIM3_NS) || ((__INSTANCE__) == TIM3_S)) + +/****************************** TSC Instances *********************************/ +#define IS_TSC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == TSC_NS) || ((INSTANCE) == TSC_S)) + +/******************** USART Instances : Synchronous mode **********************/ +#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S)) + +/******************** UART Instances : Asynchronous mode **********************/ +#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S)) + +/*********************** UART Instances : FIFO mode ***************************/ +#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/*********************** UART Instances : SPI Slave mode **********************/ +#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S)) + +/****************** UART Instances : Auto Baud Rate detection ****************/ +#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S)) + +/****************** UART Instances : Driver Enable *****************/ +#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/******************** UART Instances : Half-Duplex mode **********************/ +#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/****************** UART Instances : Hardware Flow control ********************/ +#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/******************** UART Instances : LIN mode **********************/ +#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S)) + +/******************** UART Instances : Wake-up from Stop mode **********************/ +#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/*********************** UART Instances : IRDA mode ***************************/ +#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S)) + +/********************* USART Instances : Smard card mode ***********************/ +#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S)) + +/******************** LPUART Instance *****************************************/ +#define IS_LPUART_INSTANCE(INSTANCE) (((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/*********************** UART Instances : AUTONOMOUS mode ***************************/ +#define IS_UART_AUTONOMOUS_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/****************************** IWDG Instances ********************************/ +#define IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG_NS) || ((INSTANCE) == IWDG_S)) + +/****************************** WWDG Instances ********************************/ +#define IS_WWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == WWDG_NS) || ((INSTANCE) == WWDG_S)) + +#else /* #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/* Instances allowed from Non-Secure state - only alias Non-Secure */ + +/******************************* ADC Instances ********************************/ +#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC4_NS) + +#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC4_COMMON_NS) + +/******************************* AES Instances ********************************/ +#define IS_AES_ALL_INSTANCE(INSTANCE) ((INSTANCE) == AES_NS) + +/******************************** COMP Instances ******************************/ +#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1_NS) || ((INSTANCE) == COMP2_NS)) + +/******************** COMP Instances with window mode capability **************/ +#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) (((INSTANCE) == COMP1_NS) || ((INSTANCE) == COMP2_NS)) + +/******************************* CRC Instances ********************************/ +#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC_NS) + +/******************************** DMA Instances *******************************/ +#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS) || \ + ((INSTANCE) == GPDMA1_Channel1_NS) || \ + ((INSTANCE) == GPDMA1_Channel2_NS) || \ + ((INSTANCE) == GPDMA1_Channel3_NS) || \ + ((INSTANCE) == GPDMA1_Channel4_NS) || \ + ((INSTANCE) == GPDMA1_Channel5_NS) || \ + ((INSTANCE) == GPDMA1_Channel6_NS) || \ + ((INSTANCE) == GPDMA1_Channel7_NS)) + +#define IS_GPDMA_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS) || \ + ((INSTANCE) == GPDMA1_Channel1_NS) || \ + ((INSTANCE) == GPDMA1_Channel2_NS) || \ + ((INSTANCE) == GPDMA1_Channel3_NS) || \ + ((INSTANCE) == GPDMA1_Channel4_NS) || \ + ((INSTANCE) == GPDMA1_Channel5_NS) || \ + ((INSTANCE) == GPDMA1_Channel6_NS) || \ + ((INSTANCE) == GPDMA1_Channel7_NS)) + +/****************************** RAMCFG Instances ********************************/ +#define IS_RAMCFG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM1_NS) || \ + ((INSTANCE) == RAMCFG_SRAM2_NS) || \ + ((INSTANCE) == RAMCFG_SRAM6_NS)) + +/***************************** RAMCFG PED Instances *****************************/ +#define IS_RAMCFG_PED_INSTANCE(INSTANCE) ((INSTANCE) == RAMCFG_SRAM2_NS) + +/***************************** RAMCFG IT Instances ******************************/ +#define IS_RAMCFG_IT_INSTANCE(INSTANCE) ((INSTANCE) == RAMCFG_SRAM2_NS) + +/************************ RAMCFG Write Protection Instances *********************/ +#define IS_RAMCFG_WP_INSTANCE(INSTANCE) ((INSTANCE) == RAMCFG_SRAM2_NS) + +/************************ RAMCFG Erase Instances ********************************/ +#define IS_RAMCFG_ER_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM1_NS) || \ + ((INSTANCE) == RAMCFG_SRAM2_NS)) + +/******************************* GPIO Instances *******************************/ +#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA_NS) || \ + ((INSTANCE) == GPIOB_NS) || \ + ((INSTANCE) == GPIOC_NS) || \ + ((INSTANCE) == GPIOH_NS)) + +/******************************* GPIO AF Instances ****************************/ +/* On WBA, all GPIO Bank support AF */ +#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) + +/**************************** GPIO Lock Instances *****************************/ +/* On WBA, all GPIO Bank support the Lock mechanism */ +#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) + +/**************************** HSEM Lock Instances *****************************/ +#define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM_NS) + +#define HSEM_CPU1_LOCKID (HSEM_CR_LOCKID_CURRENT >> HSEM_CR_LOCKID_Pos)/* Semaphore Lock ID */ + +#define HSEM_SEMID_MIN (0U) /* HSEM ID Min*/ +#define HSEM_SEMID_MAX (15U) /* HSEM ID Max */ + +#define HSEM_PROCESSID_MIN (0U) /* HSEM Process ID Min */ +#define HSEM_PROCESSID_MAX (255U) /* HSEM Process ID Max */ + +#define HSEM_CLEAR_KEY_MIN (0U) /* HSEM clear Key Min value */ +#define HSEM_CLEAR_KEY_MAX (0xFFFFU) /* HSEM clear Key Max value */ + +/******************************** I2C Instances *******************************/ +#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C3_NS)) + +/******************* I2C Instances : Group belongingness *********************/ +#define IS_I2C_GRP1_INSTANCE(INSTANCE) ((INSTANCE) == I2C1_NS) + +#define IS_I2C_GRP2_INSTANCE(INSTANCE) ((INSTANCE) == I2C3_NS) + +/****************** I2C Instances : wakeup capability from stop modes *********/ +#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) + +/******************************* AES Instances ********************************/ +#define IS_PKA_ALL_INSTANCE(INSTANCE) ((INSTANCE) == PKA_NS) + +/******************************* RNG Instances ********************************/ +#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG_NS) + +/****************************** RTC Instances *********************************/ +#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC_NS) + +/******************************** SAI Instances *******************************/ +#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A_NS) || ((INSTANCE) == SAI1_Block_B_NS)) + +/****************************** SMBUS Instances *******************************/ +#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C3_NS)) + +/******************* SMBUS Instances : Group membership ***********************/ +#define IS_SMBUS_GRP1_INSTANCE(INSTANCE) ((INSTANCE) == I2C1_NS) + +#define IS_SMBUS_GRP2_INSTANCE(INSTANCE) ((INSTANCE) == I2C3_NS) + +/******************************** SPI Instances *******************************/ +#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI3_NS)) + +#define IS_SPI_LIMITED_INSTANCE(INSTANCE) ((INSTANCE) == SPI3_NS) + +#define IS_SPI_FULL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1_NS) + +/******************* SPI Instances : Group belongingness *********************/ +#define IS_SPI_GRP1_INSTANCE(INSTANCE) ((INSTANCE) == SPI1_NS) + +#define IS_SPI_GRP2_INSTANCE(INSTANCE) ((INSTANCE) == SPI3_NS) + +/****************** LPTIM Instances : All supported instances *****************/ +#define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM2_NS)) + +/****************** LPTIM Instances : DMA supported instances *****************/ +#define IS_LPTIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM2_NS)) + +/************* LPTIM Instances : at least 1 capture/compare channel ***********/ +#define IS_LPTIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM2_NS)) + +/************* LPTIM Instances : at least 2 capture/compare channel ***********/ +#define IS_LPTIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM2_NS)) + +/****************** LPTIM Instances : supporting encoder interface **************/ +#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM2_NS)) + +/****************** LPTIM Instances : supporting Input Capture **************/ +#define IS_LPTIM_INPUT_CAPTURE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM2_NS)) + +/****************** TIM Instances : All supported instances *******************/ +#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS) || \ + ((INSTANCE) == TIM16_NS) || \ + ((INSTANCE) == TIM17_NS)) + +/****************** TIM Instances : supporting 32 bits counter ****************/ +#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/****************** TIM Instances : supporting the break function *************/ +#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM16_NS) || \ + ((INSTANCE) == TIM17_NS)) + +/************** TIM Instances : supporting Break source selection *************/ +#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM16_NS) || \ + ((INSTANCE) == TIM17_NS)) + +/****************** TIM Instances : supporting 2 break inputs *****************/ +#define IS_TIM_BKIN2_INSTANCE(INSTANCE) ((INSTANCE) == TIM1_NS) + +/************* TIM Instances : at least 1 capture/compare channel *************/ +#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS) || \ + ((INSTANCE) == TIM16_NS) || \ + ((INSTANCE) == TIM17_NS)) + +/************ TIM Instances : at least 2 capture/compare channels *************/ +#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/************ TIM Instances : at least 3 capture/compare channels *************/ +#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/************ TIM Instances : at least 4 capture/compare channels *************/ +#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/****************** TIM Instances : at least 5 capture/compare channels *******/ +#define IS_TIM_CC5_INSTANCE(INSTANCE) ((INSTANCE) == TIM1_NS) + +/****************** TIM Instances : at least 6 capture/compare channels *******/ +#define IS_TIM_CC6_INSTANCE(INSTANCE) ((INSTANCE) == TIM1_NS) + +/************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/ +#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM16_NS) || \ + ((INSTANCE) == TIM17_NS)) + +/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/ +#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS) || \ + ((INSTANCE) == TIM16_NS) || \ + ((INSTANCE) == TIM17_NS)) + +/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/ +#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS) || \ + ((INSTANCE) == TIM16_NS) || \ + ((INSTANCE) == TIM17_NS)) + +/******************** TIM Instances : DMA burst feature ***********************/ +#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS) || \ + ((INSTANCE) == TIM16_NS) || \ + ((INSTANCE) == TIM17_NS)) + +/******************* TIM Instances : output(s) available **********************/ +#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ + ((((INSTANCE) == TIM1_NS) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4) || \ + ((CHANNEL) == TIM_CHANNEL_5) || \ + ((CHANNEL) == TIM_CHANNEL_6))) \ + || \ + (((INSTANCE) == TIM2_NS) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + (((INSTANCE) == TIM3_NS) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + (((INSTANCE) == TIM16_NS) && \ + (((CHANNEL) == TIM_CHANNEL_1))) \ + || \ + (((INSTANCE) == TIM17_NS) && \ + (((CHANNEL) == TIM_CHANNEL_1)))) + +/****************** TIM Instances : supporting complementary output(s) ********/ +#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ + ((((INSTANCE) == TIM1_NS) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + (((INSTANCE) == TIM16_NS) && \ + ((CHANNEL) == TIM_CHANNEL_1)) \ + || \ + (((INSTANCE) == TIM17_NS) && \ + ((CHANNEL) == TIM_CHANNEL_1))) + +/****************** TIM Instances : supporting clock division *****************/ +#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS) || \ + ((INSTANCE) == TIM16_NS) || \ + ((INSTANCE) == TIM17_NS)) + +/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/ +#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/ +#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/****************** TIM Instances : supporting combined 3-phase PWM mode ******/ +#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) ((INSTANCE) == TIM1_NS) + +/****************** TIM Instances : supporting commutation event generation ***/ +#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM16_NS) || \ + ((INSTANCE) == TIM17_NS)) + +/****************** TIM Instances : supporting counting mode selection ********/ +#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/****************** TIM Instances : supporting encoder interface **************/ +#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/****************** TIM Instances : supporting Hall sensor interface **********/ +#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/**************** TIM Instances : external trigger input available ************/ +#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/************* TIM Instances : supporting ETR source selection ***************/ +#define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/ +#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/ +#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/****************** TIM Instances : supporting OCxREF clear *******************/ +#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/****************** TIM Instances : remapping capability **********************/ +#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/****************** TIM Instances : supporting repetition counter *************/ +#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM16_NS) || \ + ((INSTANCE) == TIM17_NS)) + +/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/ +#define IS_TIM_TRGO2_INSTANCE(INSTANCE) ((INSTANCE) == TIM1_NS) + +/******************* TIM Instances : Timer input XOR function *****************/ +#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/******************* TIM Instances : Timer input selection ********************/ +#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS) || \ + ((INSTANCE) == TIM16_NS) || \ + ((INSTANCE) == TIM17_NS)) + +/******************* TIM Instances : supporting HSE32 as input ********************/ +#define IS_TIM_HSE32_INSTANCE(INSTANCE) (((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM17_NS)) + +/****************** TIM Instances : Advanced timer instances *******************/ +#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1_NS) + +/****************** TIM Instances : supporting synchronization ****************/ +#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1_NS) || \ + ((__INSTANCE__) == TIM2_NS) || \ + ((__INSTANCE__) == TIM3_NS)) + +/****************************** TSC Instances *********************************/ +#define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC_NS) + +/******************** USART Instances : Synchronous mode **********************/ +#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART2_NS)) + +/******************** UART Instances : Asynchronous mode **********************/ +#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART2_NS)) + +/*********************** UART Instances : FIFO mode ***************************/ +#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \ + ((INSTANCE) == USART2_NS) || \ + ((INSTANCE) == LPUART1_NS)) + +/*********************** UART Instances : SPI Slave mode **********************/ +#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART2_NS)) + +/****************** UART Instances : Auto Baud Rate detection ****************/ +#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART2_NS)) + +/****************** UART Instances : Driver Enable *****************/ +#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \ + ((INSTANCE) == USART2_NS) || \ + ((INSTANCE) == LPUART1_NS)) + +/******************** UART Instances : Half-Duplex mode **********************/ +#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \ + ((INSTANCE) == USART2_NS) || \ + ((INSTANCE) == LPUART1_NS)) + +/****************** UART Instances : Hardware Flow control ********************/ +#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \ + ((INSTANCE) == USART2_NS) || \ + ((INSTANCE) == LPUART1_NS)) + +/******************** UART Instances : LIN mode **********************/ +#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART2_NS)) + +/******************** UART Instances : Wake-up from Stop mode **********************/ +#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \ + ((INSTANCE) == USART2_NS) || \ + ((INSTANCE) == LPUART1_NS)) + +/*********************** UART Instances : IRDA mode ***************************/ +#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART2_NS)) + +/********************* USART Instances : Smard card mode ***********************/ +#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART2_NS)) + +/*********************** UART Instances : AUTONOMOUS mode ***************************/ +#define IS_UART_AUTONOMOUS_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \ + ((INSTANCE) == USART2_NS) || \ + ((INSTANCE) == LPUART1_NS)) + +/******************** LPUART Instance *****************************************/ +#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1_NS) + +/****************************** IWDG Instances ********************************/ +#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG_NS) + +/****************************** WWDG Instances ********************************/ +#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG_NS) + +#endif /* #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** @} */ /* End of group STM32WBAxx_Peripheral_Exported_macros */ + +/** @} */ /* End of group STM32WBA54xx */ + +/** @} */ /* End of group ST */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WBA54xx_H */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba55xx.h b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba55xx.h new file mode 100644 index 0000000000..680b40a9ff --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba55xx.h @@ -0,0 +1,15819 @@ +/** + ****************************************************************************** + * @file stm32wba55xx.h + * @author MCD Application Team + * @brief CMSIS STM32WBA55xx Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral's registers hardware + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#ifndef STM32WBA55xx_H +#define STM32WBA55xx_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup ST + * @{ + */ + +/** @addtogroup STM32WBA55xx + * @{ + */ + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ +typedef enum +{ +/* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ======================================= */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation + and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory + related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SecureFault_IRQn = -9, /*!< -9 Secure Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + +/* =========================================== STM32WBA55xx Specific Interrupt Numbers ====================================== */ + WWDG_IRQn = 0, /*!< Window WatchDog interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + RTC_IRQn = 2, /*!< RTC non-secure interrupt */ + RTC_S_IRQn = 3, /*!< RTC secure interrupt */ + TAMP_IRQn = 4, /*!< Tamper global interrupt */ + RAMCFG_IRQn = 5, /*!< RAMCFG global interrupt */ + FLASH_IRQn = 6, /*!< FLASH non-secure global interrupt */ + FLASH_S_IRQn = 7, /*!< FLASH secure global interrupt */ + GTZC_IRQn = 8, /*!< Global TrustZone Controller interrupt */ + RCC_IRQn = 9, /*!< RCC non secure global interrupt */ + RCC_S_IRQn = 10, /*!< RCC secure global interrupt */ + EXTI0_IRQn = 11, /*!< EXTI Line0 interrupt */ + EXTI1_IRQn = 12, /*!< EXTI Line1 interrupt */ + EXTI2_IRQn = 13, /*!< EXTI Line2 interrupt */ + EXTI3_IRQn = 14, /*!< EXTI Line3 interrupt */ + EXTI4_IRQn = 15, /*!< EXTI Line4 interrupt */ + EXTI5_IRQn = 16, /*!< EXTI Line5 interrupt */ + EXTI6_IRQn = 17, /*!< EXTI Line6 interrupt */ + EXTI7_IRQn = 18, /*!< EXTI Line7 interrupt */ + EXTI8_IRQn = 19, /*!< EXTI Line8 interrupt */ + EXTI9_IRQn = 20, /*!< EXTI Line9 interrupt */ + EXTI10_IRQn = 21, /*!< EXTI Line10 interrupt */ + EXTI11_IRQn = 22, /*!< EXTI Line11 interrupt */ + EXTI12_IRQn = 23, /*!< EXTI Line12 interrupt */ + EXTI13_IRQn = 24, /*!< EXTI Line13 interrupt */ + EXTI14_IRQn = 25, /*!< EXTI Line14 interrupt */ + EXTI15_IRQn = 26, /*!< EXTI Line15 interrupt */ + IWDG_IRQn = 27, /*!< IWDG global interrupt */ + SAES_IRQn = 28, /*!< Secure AES global interrupt */ + GPDMA1_Channel0_IRQn = 29, /*!< GPDMA1 Channel 0 global interrupt */ + GPDMA1_Channel1_IRQn = 30, /*!< GPDMA1 Channel 1 global interrupt */ + GPDMA1_Channel2_IRQn = 31, /*!< GPDMA1 Channel 2 global interrupt */ + GPDMA1_Channel3_IRQn = 32, /*!< GPDMA1 Channel 3 global interrupt */ + GPDMA1_Channel4_IRQn = 33, /*!< GPDMA1 Channel 4 global interrupt */ + GPDMA1_Channel5_IRQn = 34, /*!< GPDMA1 Channel 5 global interrupt */ + GPDMA1_Channel6_IRQn = 35, /*!< GPDMA1 Channel 6 global interrupt */ + GPDMA1_Channel7_IRQn = 36, /*!< GPDMA1 Channel 7 global interrupt */ + TIM1_BRK_IRQn = 37, /*!< TIM1 Break interrupt */ + TIM1_UP_IRQn = 38, /*!< TIM1 Update interrupt */ + TIM1_TRG_COM_IRQn = 39, /*!< TIM1 Trigger and Commutation interrupt */ + TIM1_CC_IRQn = 40, /*!< TIM1 Capture Compare interrupt */ + TIM2_IRQn = 41, /*!< TIM2 global interrupt */ + TIM3_IRQn = 42, /*!< TIM3 global interrupt */ + I2C1_EV_IRQn = 43, /*!< I2C1 Event interrupt */ + I2C1_ER_IRQn = 44, /*!< I2C1 Error interrupt */ + SPI1_IRQn = 45, /*!< SPI1 global interrupt */ + USART1_IRQn = 46, /*!< USART1 global interrupt */ + USART2_IRQn = 47, /*!< USART2 global interrupt */ + LPUART1_IRQn = 48, /*!< LPUART1 global interrupt */ + LPTIM1_IRQn = 49, /*!< LPTIM1 global interrupt */ + LPTIM2_IRQn = 50, /*!< LPTIM2 global interrupt */ + TIM16_IRQn = 51, /*!< TIM16 global interrupt */ + TIM17_IRQn = 52, /*!< TIM17 global interrupt */ + COMP_IRQn = 53, /*!< COMP1 and COMP2 through EXTI Lines interrupts */ + I2C3_EV_IRQn = 54, /*!< I2C3 Event interrupt */ + I2C3_ER_IRQn = 55, /*!< I2C3 Error interrupt */ + SAI1_IRQn = 56, /*!< Serial Audio Interface 1 global interrupt */ + TSC_IRQn = 57, /*!< Touch Sense Controller global interrupt */ + AES_IRQn = 58, /*!< AES global interrupt */ + RNG_IRQn = 59, /*!< RNG global interrupt */ + FPU_IRQn = 60, /*!< FPU global interrupt */ + HASH_IRQn = 61, /*!< HASH global interrupt */ + PKA_IRQn = 62, /*!< PKA global interrupt */ + SPI3_IRQn = 63, /*!< SPI3 global interrupt */ + ICACHE_IRQn = 64, /*!< Instruction cache global interrupt */ + ADC4_IRQn = 65, /*!< ADC4 global interrupt */ + RADIO_IRQn = 66, /*!< 2.4GHz RADIO global interrupt */ + WKUP_IRQn = 67, /*!< PWR global WKUP pin interrupt */ + HSEM_IRQn = 68, /*!< HSEM non-secure global interrupt */ + HSEM_S_IRQn = 69, /*!< HSEM secure global interrupt */ + WKUP_S_IRQn = 70, /*!< PWR secure global WKUP pin interrupt */ + RCC_AUDIOSYNC_IRQn = 71, /*!< RCC audio synchronization interrupt */ +} IRQn_Type; + + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ +/* ------- Start of section using anonymous unions and disabling warnings ------- */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/* -------- Configuration of the STM32WBAxx System On Chip ------ */ + +/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */ +#define __CM33_REV 0x0000U /* Core revision r0p1 */ +#define __SAUREGION_PRESENT 1U /* SAU regions present */ +#define __MPU_PRESENT 1U /* MPU present */ +#define __VTOR_PRESENT 1U /* VTOR present */ +#define __NVIC_PRIO_BITS 4U /* Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /* FPU present */ +#define __DSP_PRESENT 1U /* DSP extension present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include /*!< ARM Cortex-M33 processor and core peripherals */ +#include "system_stm32wbaxx.h" /*!< system_stm32wbaxx System */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ +/** @addtogroup STM32WBAxx_peripherals + * @{ + */ + +/** + * @brief Analog to Digital Converter (ADC) + */ +typedef struct +{ + __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR; /*!< ADC sampling time register, Address offset: 0x14 */ + uint32_t RESERVED0[2]; /*!< Reserved, Address offset: 0x18-0x1C */ + __IO uint32_t AWD1TR; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ + __IO uint32_t AWD2TR; /*!< ADC watchdog threshold register, Address offset: 0x24 */ + __IO uint32_t CHSELR; /*!< ADC channel select register, Address offset: 0x28 */ + __IO uint32_t AWD3TR; /*!< ADC watchdog threshold register, Address offset: 0x02C */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x30-0x3C */ + __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ + __IO uint32_t PWRR; /*!< ADC power register, Address offset: 0x44 */ + uint32_t RESERVED2[22];/*!< Reserved, Address offset: 0x48-0x9C */ + __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 configuration register, Address offset: 0xA4 */ + uint32_t RESERVED3[7]; /*!< Reserved, Address offset: 0xA8-0xC0 */ + __IO uint32_t CALFACT; /*!< ADC Calibration factor register, Address offset: 0xC4 */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: 0x308 */ +} ADC_Common_TypeDef; + +/** + * @brief Analog comparators (COMP) + */ +typedef struct +{ + __IO uint32_t CSR; /*!< Comparator control and status register, Address offset: 0x00 */ +} COMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR_ODD; /*!< COMP control and status register located in register of comparator instance odd, used for bits common to several COMP instances, Address offset: 0x00 */ + __IO uint32_t CSR_EVEN; /*!< COMP control and status register located in register of comparator instance even, used for bits common to several COMP instances, Address offset: 0x04 */ +} COMP_Common_TypeDef; + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED0; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief AES hardware accelerator + */ +typedef struct +{ + __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */ + __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */ + __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */ + __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */ + __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */ + __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */ + __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */ + __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */ + __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */ + __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */ + __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */ + __IO uint32_t KEYR4; /*!< AES key register 4, Address offset: 0x30 */ + __IO uint32_t KEYR5; /*!< AES key register 5, Address offset: 0x34 */ + __IO uint32_t KEYR6; /*!< AES key register 6, Address offset: 0x38 */ + __IO uint32_t KEYR7; /*!< AES key register 7, Address offset: 0x3C */ + __IO uint32_t SUSP0R; /*!< AES Suspend register 0, Address offset: 0x40 */ + __IO uint32_t SUSP1R; /*!< AES Suspend register 1, Address offset: 0x44 */ + __IO uint32_t SUSP2R; /*!< AES Suspend register 2, Address offset: 0x48 */ + __IO uint32_t SUSP3R; /*!< AES Suspend register 3, Address offset: 0x4C */ + __IO uint32_t SUSP4R; /*!< AES Suspend register 4, Address offset: 0x50 */ + __IO uint32_t SUSP5R; /*!< AES Suspend register 5, Address offset: 0x54 */ + __IO uint32_t SUSP6R; /*!< AES Suspend register 6, Address offset: 0x58 */ + __IO uint32_t SUSP7R; /*!< AES Suspend register 7, Address offset: 0x5C */ + uint32_t RESERVED1[168];/*!< Reserved, Address offset: 0x60 -- 0x2FC */ + __IO uint32_t IER; /*!< AES Interrupt Enable Register, Address offset: 0x300 */ + __IO uint32_t ISR; /*!< AES Interrupt Status Register, Address offset: 0x304 */ + __IO uint32_t ICR; /*!< AES Interrupt Clear Register, Address offset: 0x308 */ +} AES_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t SCR; /*!< Debug MCU status and configuration register, Address offset: 0x04 */ + __IO uint32_t APB1LFZR; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ + __IO uint32_t APB1HFZR; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ + __IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ + uint32_t RESERVED1[4];/*!< Reserved, 0x14 - 0x20 */ + __IO uint32_t APB7FZR; /*!< Debug MCU APB7 freeze register, Address offset: 0x24 */ + __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x28 */ +} DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ +typedef struct +{ + __IO uint32_t SECCFGR; /*!< DMA secure configuration register, Address offset: 0x00 */ + __IO uint32_t PRIVCFGR; /*!< DMA privileged configuration register, Address offset: 0x04 */ + __IO uint32_t RCFGLOCKR; /*!< DMA secure and privilege lock register, Address offset: 0x08 */ + __IO uint32_t MISR; /*!< DMA non secure masked interrupt status register, Address offset: 0x0C */ + __IO uint32_t SMISR; /*!< DMA secure masked interrupt status register, Address offset: 0x10 */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */ + uint32_t RESERVED1[2]; /*!< Reserved 1, Address offset: 0x54 -- 0x58 */ + __IO uint32_t CFCR; /*!< DMA channel x flag clear register, Address offset: 0x5C + (x * 0x80) */ + __IO uint32_t CSR; /*!< DMA channel x flag status register, Address offset: 0x60 + (x * 0x80) */ + __IO uint32_t CCR; /*!< DMA channel x control register, Address offset: 0x64 + (x * 0x80) */ + uint32_t RESERVED2[10]; /*!< Reserved 2, Address offset: 0x68 -- 0x8C */ + __IO uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: 0x90 + (x * 0x80) */ + __IO uint32_t CTR2; /*!< DMA channel x transfer register 2, Address offset: 0x94 + (x * 0x80) */ + __IO uint32_t CBR1; /*!< DMA channel x block register 1, Address offset: 0x98 + (x * 0x80) */ + __IO uint32_t CSAR; /*!< DMA channel x source address register, Address offset: 0x9C + (x * 0x80) */ + __IO uint32_t CDAR; /*!< DMA channel x destination address register, Address offset: 0xA0 + (x * 0x80) */ + uint32_t RESERVED3[10]; /*!< Reserved 3, Address offset: 0xA4 -- 0xC8 */ + __IO uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: 0xCC + (x * 0x80) */ +} DMA_Channel_TypeDef; + +/** + * @brief Asynch Interrupt/Event Controller (EXTI) + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR1; /*!< EXTI Security Configuration Register 1, Address offset: 0x14 */ + __IO uint32_t PRIVCFGR1; /*!< EXTI Privilege Configuration Register 1, Address offset: 0x18 */ + uint32_t RESERVED1[17]; /*!< Reserved 1, 0x1C -- 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXIT External Interrupt Configuration Register, 0x60 -- 0x6C */ + __IO uint32_t LOCKR; /*!< EXTI Lock Register, Address offset: 0x70 */ + uint32_t RESERVED2[3]; /*!< Reserved 2, 0x74 -- 0x7C */ + __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + uint32_t RESERVED0; /*!< RESERVED1, Address offset: 0x04 */ + __IO uint32_t NSKEYR; /*!< FLASH non-secure key register, Address offset: 0x08 */ + __IO uint32_t SECKEYR; /*!< FLASH secure key register, Address offset: 0x0C */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x10 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x14 */ + __IO uint32_t PDKEYR; /*!< FLASH Bank power-down key register, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ + __IO uint32_t NSSR; /*!< FLASH non-secure status register, Address offset: 0x20 */ + __IO uint32_t SECSR; /*!< FLASH secure status register, Address offset: 0x24 */ + __IO uint32_t NSCR1; /*!< FLASH non-secure control register, Address offset: 0x28 */ + __IO uint32_t SECCR1; /*!< FLASH secure control register, Address offset: 0x2C */ + __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x30 */ + __IO uint32_t OPSR; /*!< FLASH OPSR register, Address offset: 0x34 */ + __IO uint32_t NSCR2; /*!< FLASH non-secure control register, Address offset: 0x38 */ + __IO uint32_t SECCR2; /*!< FLASH secure control register, Address offset: 0x3C */ + __IO uint32_t OPTR; /*!< FLASH option control register, Address offset: 0x40 */ + __IO uint32_t NSBOOTADD0R; /*!< FLASH non-secure boot address 0 register, Address offset: 0x44 */ + __IO uint32_t NSBOOTADD1R; /*!< FLASH non-secure boot address 1 register, Address offset: 0x48 */ + __IO uint32_t SECBOOTADD0R; /*!< FLASH secure boot address 0 register, Address offset: 0x4C */ + __IO uint32_t SECWMR1; /*!< FLASH secure watermark1 register 1, Address offset: 0x50 */ + __IO uint32_t SECWMR2; /*!< FLASH secure watermark1 register 2, Address offset: 0x54 */ + __IO uint32_t WRPAR; /*!< FLASH WRP area A address register, Address offset: 0x58 */ + __IO uint32_t WRPBR; /*!< FLASH WRP area B address register, Address offset: 0x5C */ + uint32_t RESERVED3[4]; /*!< Reserved3, Address offset: 0x60-0x6C */ + __IO uint32_t OEM1KEYR1; /*!< FLASH OEM1 key register 1, Address offset: 0x70 */ + __IO uint32_t OEM1KEYR2; /*!< FLASH OEM1 key register 2, Address offset: 0x74 */ + __IO uint32_t OEM2KEYR1; /*!< FLASH OEM2 key register 1, Address offset: 0x78 */ + __IO uint32_t OEM2KEYR2; /*!< FLASH OEM2 key register 2, Address offset: 0x7C */ + __IO uint32_t SECBBR1; /*!< FLASH secure block-based bank register 1, Address offset: 0x80 */ + __IO uint32_t SECBBR2; /*!< FLASH secure block-based bank register 2, Address offset: 0x84 */ + __IO uint32_t SECBBR3; /*!< FLASH secure block-based bank register 3, Address offset: 0x88 */ + __IO uint32_t SECBBR4; /*!< FLASH secure block-based bank register 4, Address offset: 0x8C */ + uint32_t RESERVED4[12]; /*!< Reserved4, Address offset: 0x90-0xBC */ + __IO uint32_t SECHDPCR; /*!< FLASH secure HDP control register, Address offset: 0xC0 */ + __IO uint32_t PRIVCFGR; /*!< FLASH privilege configuration register, Address offset: 0xC4 */ + uint32_t RESERVED5[2]; /*!< Reserved5, Address offset: 0xC8-0xCC */ + __IO uint32_t PRIVBBR1; /*!< FLASH privilege block-based bank register 1, Address offset: 0xD0 */ + __IO uint32_t PRIVBBR2; /*!< FLASH privilege block-based bank register 2, Address offset: 0xD4 */ + __IO uint32_t PRIVBBR3; /*!< FLASH privilege block-based bank register 3, Address offset: 0xD8 */ + __IO uint32_t PRIVBBR4; /*!< FLASH privilege block-based bank register 4, Address offset: 0xDC */ +} FLASH_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ + uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register, Address offset: 0x30 */ +} GPIO_TypeDef; + +/** + * @brief Global TrustZone Controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< TZSC control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t SECCFGR1; /*!< TZSC secure configuration register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR2; /*!< TZSC secure configuration register 2, Address offset: 0x14 */ + __IO uint32_t SECCFGR3; /*!< TZSC secure configuration register 3, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ + __IO uint32_t PRIVCFGR1; /*!< TZSC privilege configuration register 1, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR2; /*!< TZSC privilege configuration register 2, Address offset: 0x24 */ + __IO uint32_t PRIVCFGR3; /*!< TZSC privilege configuration register 3, Address offset: 0x28 */ +} GTZC_TZSC_TypeDef; + +typedef struct +{ + __IO uint32_t CR; /*!< MPCBBx control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t CFGLOCK; /*!< MPCBBx lock register, Address offset: 0x10 */ + uint32_t RESERVED2[59]; /*!< Reserved2, Address offset: 0x14-0xFC */ + __IO uint32_t SECCFGR[4]; /*!< MPCBBx security configuration registers, Address offset: 0x100-0x10C */ + uint32_t RESERVED3[60]; /*!< Reserved3, Address offset: 0x110-0x1FC */ + __IO uint32_t PRIVCFGR[4]; /*!< MPCBBx privilege configuration registers, Address offset: 0x200-0x20C */ +} GTZC_MPCBB_TypeDef; + +typedef struct +{ + __IO uint32_t IER1; /*!< TZIC interrupt enable register 1, Address offset: 0x00 */ + __IO uint32_t IER2; /*!< TZIC interrupt enable register 2, Address offset: 0x04 */ + __IO uint32_t IER3; /*!< TZIC interrupt enable register 3, Address offset: 0x08 */ + __IO uint32_t IER4; /*!< TZIC interrupt enable register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< TZIC status register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< TZIC status register 2, Address offset: 0x14 */ + __IO uint32_t SR3; /*!< TZIC status register 3, Address offset: 0x18 */ + __IO uint32_t SR4; /*!< TZIC status register 4, Address offset: 0x1C */ + __IO uint32_t FCR1; /*!< TZIC flag clear register 1, Address offset: 0x20 */ + __IO uint32_t FCR2; /*!< TZIC flag clear register 2, Address offset: 0x24 */ + __IO uint32_t FCR3; /*!< TZIC flag clear register 3, Address offset: 0x28 */ + __IO uint32_t FCR4; /*!< TZIC flag clear register 3, Address offset: 0x2C */ +} GTZC_TZIC_TypeDef; + +/** + * @brief HASH + */ +typedef struct +{ + __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ + __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ + __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ + __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ + __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ + __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ + uint32_t RESERVED0[52]; /*!< Reserved, Address offset: 0x28-0xF4 */ + __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */ +} HASH_TypeDef; + +/** + * @brief HASH_DIGEST + */ +typedef struct +{ + __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */ +} HASH_DIGEST_TypeDef; + +/** + * @brief HW Semaphore HSEM + */ +typedef struct +{ + __IO uint32_t R[16]; /*!< HSEM 2-step write lock and read back registers, Address offset: 00h-3Ch */ + uint32_t Reserved1[16]; /*!< Reserved Address offset: 40h-7Ch */ + __IO uint32_t RLR[16]; /*!< HSEM 1-step read lock registers, Address offset: 80h-BCh */ + uint32_t Reserved2[16]; /*!< Reserved Address offset: C0h-FCh */ + __IO uint32_t IER; /*!< HSEM interrupt enable register, Address offset: 100h */ + __IO uint32_t ICR; /*!< HSEM interrupt clear register, Address offset: 104h */ + __IO uint32_t ISR; /*!< HSEM interrupt status register, Address offset: 108h */ + __IO uint32_t MISR; /*!< HSEM masked interrupt status register, Address offset: 10Ch */ + uint32_t Reserved3[28]; /*!< Reserved Address offset: 110h-17Ch */ + __IO uint32_t SIER; /*!< HSEM secure interrupt enable register, Address offset: 180h */ + __IO uint32_t SICR; /*!< HSEM secure interrupt clear register, Address offset: 184h */ + __IO uint32_t SISR; /*!< HSEM secure interrupt status register, Address offset: 188h */ + __IO uint32_t SMISR; /*!< HSEM secure masked interrupt status register, Address offset: 18Ch */ + uint32_t Reserved4[28]; /*!< Reserved Address offset: 190h-1FCh */ + __IO uint32_t SECCFGR; /*!< HSEM security configuration register, Address offset: 200h */ + uint32_t Reserved5[3]; /*!< Reserved Address offset: 204h-20Ch */ + __IO uint32_t PRIVCFGR; /*!< HSEM privilege configuration register, Address offset: 210h */ + uint32_t Reserved6[7]; /*!< Reserved Address offset: 214h-22Ch */ + __IO uint32_t CR; /*!< HSEM Semaphore clear register, Address offset: 230h */ + __IO uint32_t KEYR; /*!< HSEM Semaphore clear key register, Address offset: 234h */ +} HSEM_TypeDef; + +typedef struct +{ + __IO uint32_t IER; /*!< HSEM interrupt enable register, Address offset: 0h */ + __IO uint32_t ICR; /*!< HSEM interrupt clear register, Address offset: 4h */ + __IO uint32_t ISR; /*!< HSEM interrupt status register, Address offset: 8h */ + __IO uint32_t MISR; /*!< HSEM masked interrupt status register, Address offset: Ch */ + uint32_t Reserved3[28]; /*!< Reserved Address offset: 10h-7Ch */ + __IO uint32_t SIER; /*!< HSEM secure interrupt enable register, Address offset: 80h */ + __IO uint32_t SICR; /*!< HSEM secure interrupt clear register, Address offset: 84h */ + __IO uint32_t SISR; /*!< HSEM secure interrupt status register, Address offset: 88h */ + __IO uint32_t SMISR; /*!< HSEM secure masked interrupt status register, Address offset: 8Ch */ +} HSEM_Common_TypeDef; + +/** + * @brief Instruction Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< ICACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< ICACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< ICACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< ICACHE Flag clear register, Address offset: 0x0C */ + __IO uint32_t HMONR; /*!< ICACHE hit monitor register, Address offset: 0x10 */ + __IO uint32_t MMONR; /*!< ICACHE miss monitor register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t CRR0; /*!< ICACHE region 0 configuration register, Address offset: 0x20 */ + __IO uint32_t CRR1; /*!< ICACHE region 1 configuration register, Address offset: 0x24 */ + __IO uint32_t CRR2; /*!< ICACHE region 2 configuration register, Address offset: 0x28 */ + __IO uint32_t CRR3; /*!< ICACHE region 3 configuration register, Address offset: 0x2C */ +} ICACHE_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ + __IO uint32_t AUTOCR; /*!< I2C Autonomous mode control register, Address offset: 0x2C */ +} I2C_TypeDef; + +/** + * @brief IWDG + */ +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ + __IO uint32_t EWCR; /*!< IWDG Early Wakeup register, Address offset: 0x14 */ +} IWDG_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t DIER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CCR1; /*!< LPTIM Capture/Compare register 1, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ + __IO uint32_t RCR; /*!< LPTIM Repetition register, Address offset: 0x28 */ + __IO uint32_t CCMR1; /*!< LPTIM Capture/Compare mode register, Address offset: 0x2C */ + __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x30 */ + __IO uint32_t CCR2; /*!< LPTIM Capture/Compare register 2, Address offset: 0x34 */ +} LPTIM_TypeDef; + +/** + * @brief PKA + */ +typedef struct +{ + __IO uint32_t CR; /*!< PKA control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< PKA status register, Address offset: 0x04 */ + __IO uint32_t CLRFR; /*!< PKA clear flag register, Address offset: 0x08 */ + uint32_t Reserved[253]; /*!< Reserved memory area Address offset: 0x0C -> 0x03FC */ + __IO uint32_t RAM[1334]; /*!< PKA RAM Address offset: 0x400 -> 0x18D4 */ +} PKA_TypeDef; + +/** + * @brief PTACONV + */ +typedef struct +{ + __IO uint32_t ACTCR; /*!< PTACONV active control register, Address offset: 0x00 */ + __IO uint32_t PRICR; /*!< PTACONV priority control register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< PTACONV control register, Address offset: 0x08 */ +} PTACONV_TypeDef; + +/** + * @brief Power Control + */ +typedef struct +{ + __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */ + __IO uint32_t VOSR; /*!< PWR voltage scaling register, Address offset: 0x0C */ + __IO uint32_t SVMCR; /*!< PWR supply voltage monitoring control register, Address offset: 0x10 */ + __IO uint32_t WUCR1; /*!< PWR wakeup control register 1, Address offset: 0x14 */ + __IO uint32_t WUCR2; /*!< PWR wakeup control register 2, Address offset: 0x18 */ + __IO uint32_t WUCR3; /*!< PWR wakeup control register 3, Address offset: 0x1C */ + __IO uint32_t RESERVED0[2]; /*!< Reserved, Address offset: 0x20 -- 0x24 */ + __IO uint32_t DBPR; /*!< PWR disable backup domain register, Address offset: 0x28 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< PWR Security configuration register, Address offset: 0x30 */ + __IO uint32_t PRIVCFGR; /*!< PWR privilege control register, Address offset: 0x34 */ + __IO uint32_t SR; /*!< PWR status register, Address offset: 0x38 */ + __IO uint32_t SVMSR; /*!< PWR supply voltage monitoring status register, Address offset: 0x3C */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x40 */ + __IO uint32_t WUSR; /*!< PWR wakeup status register, Address offset: 0x44 */ + __IO uint32_t WUSCR; /*!< PWR wakeup status clear register, Address offset: 0x48 */ + __IO uint32_t APCR; /*!< PWR apply pull configuration register, Address offset: 0x4C */ + __IO uint32_t IORETENRA; /*!< PWR Port A IO retention in Standby register, Address offset: 0x50 */ + __IO uint32_t IORETRA; /*!< PWR Port A IO retention status in Standby register, Address offset: 0x54 */ + __IO uint32_t IORETENRB; /*!< PWR Port B IO retention in Standby register, Address offset: 0x58 */ + __IO uint32_t IORETRB; /*!< PWR Port B IO retention status in Standby register, Address offset: 0x5C */ + __IO uint32_t IORETENRC; /*!< PWR Port C IO retention in Standby register, Address offset: 0x60 */ + __IO uint32_t IORETRC; /*!< PWR Port C IO retention status in Standby register, Address offset: 0x64 */ + uint32_t RESERVED3[8]; /*!< Reserved, Address offset: 0x68 -- 0x84 */ + __IO uint32_t IORETENRH; /*!< PWR Port H IO retention in Standby register, Address offset: 0x88 */ + __IO uint32_t IORETRH; /*!< PWR Port H IO retention status in Standby register, Address offset: 0x8C */ + uint32_t RESERVED4[28]; /*!< Reserved, Address offset: 0x90 -- 0xFC */ + __IO uint32_t RADIOSCR; /*!< PWR 2.4 GHZ radio status and control register, Address offset: 0x100 */ +} PWR_TypeDef; + +/** + * @brief SRAMs configuration controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< Control Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< Interrupt enable register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< Interrupt status register, Address offset: 0x08 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x0C */ + __IO uint32_t PEAR; /*!< Parity error address register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< Interrupt clear register, Address offset: 0x14 */ + __IO uint32_t WPR1; /*!< Write protection register 1, Address offset: 0x18 */ + __IO uint32_t WPR2; /*!< Write protection register 2, Address offset: 0x1C */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x20 -- 0x24 */ + __IO uint32_t ERKEYR; /*!< Erase key register, Address offset: 0x28 */ +}RAMCFG_TypeDef; + +/** + * @brief Reset and Clock Control + */ +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register Address offset: 0x000 */ + uint32_t RESERVED0[3]; /*!< Reserved 0x004 -- 0x00C */ + __IO uint32_t ICSCR3; /*!< RCC internal clock sources calibration register 3 Address offset: 0x010 */ + uint32_t RESERVED1[2]; /*!< Reserved 0x014 -- 0x018 */ + __IO uint32_t CFGR1; /*!< RCC clock configuration register 1 Address offset: 0x01C */ + __IO uint32_t CFGR2; /*!< RCC clock configuration register 2 Address offset: 0x020 */ + __IO uint32_t CFGR3; /*!< RCC clock configuration register 3 Address offset: 0x024 */ + __IO uint32_t PLL1CFGR; /*!< PLL1 Configuration Register Address offset: 0x028 */ + uint32_t RESERVED2[2]; /*!< Reserved 0x02C -- 0x030 */ + __IO uint32_t PLL1DIVR; /*!< PLL1 Dividers Configuration Register Address offset: 0x034 */ + __IO uint32_t PLL1FRACR; /*!< PLL1 Fractional Divider Configuration Register Address offset: 0x038 */ + uint32_t RESERVED3[5]; /*!< Reserved 0x03C -- 0x04C */ + __IO uint32_t CIER; /*!< Clock Interrupt Enable Register Address offset: 0x050 */ + __IO uint32_t CIFR; /*!< Clock Interrupt Flag Register Address offset: 0x054 */ + __IO uint32_t CICR; /*!< Clock Interrupt Clear Register Address offset: 0x058 */ + uint32_t RESERVED4; /*!< Reserved Address offset: 0x05C */ + __IO uint32_t AHB1RSTR; /*!< AHB1 Peripherals Reset Register Address offset: 0x060 */ + __IO uint32_t AHB2RSTR; /*!< AHB2 Peripherals Reset Register Address offset: 0x064 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x068 */ + __IO uint32_t AHB4RSTR; /*!< AHB4 Peripherals Reset Register Address offset: 0x06C */ + __IO uint32_t AHB5RSTR; /*!< AHB5 Peripherals Reset Register Address offset: 0x070 */ + __IO uint32_t APB1RSTR1; /*!< APB1 Peripherals Reset Low Register Address offset: 0x074 */ + __IO uint32_t APB1RSTR2; /*!< APB1 Peripherals Reset High Register Address offset: 0x078 */ + __IO uint32_t APB2RSTR; /*!< APB2 Peripherals Reset Register Address offset: 0x07C */ + __IO uint32_t APB7RSTR; /*!< APB7 Peripherals Reset Register Address offset: 0x080 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x084 */ + __IO uint32_t AHB1ENR; /*!< AHB1 Peripherals Clock Enable Register Address offset: 0x088 */ + __IO uint32_t AHB2ENR; /*!< AHB2 Peripherals Clock Enable Register Address offset: 0x08C */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x090 */ + __IO uint32_t AHB4ENR; /*!< AHB4 Peripherals Clock Enable Register Address offset: 0x094 */ + __IO uint32_t AHB5ENR; /*!< AHB5 Peripherals Clock Enable Register Address offset: 0x098 */ + __IO uint32_t APB1ENR1; /*!< APB1 Peripherals Clock Enable Low Register Address offset: 0x09C */ + __IO uint32_t APB1ENR2; /*!< APB1 Peripherals Clock Enable High Register Address offset: 0x0A0 */ + __IO uint32_t APB2ENR; /*!< APB2 Peripherals Clock Enable Register Address offset: 0x0A4 */ + __IO uint32_t APB7ENR; /*!< APB7 Peripherals Clock Enable Register Address offset: 0x0A8 */ + uint32_t RESERVED8; /*!< Reserved Address offset: 0x0AC */ + __IO uint32_t AHB1SMENR; /*!< AHB1 Peripherals Clock Low Power Enable Register Address offset: 0x0B0 */ + __IO uint32_t AHB2SMENR; /*!< AHB2 Peripherals Clock Low Power Enable Register Address offset: 0x0B4 */ + uint32_t RESERVED9; /*!< Reserved Address offset: 0x0B8 */ + __IO uint32_t AHB4SMENR; /*!< AHB4 Peripherals Clock Low Power Enable Register Address offset: 0x0BC */ + __IO uint32_t AHB5SMENR; /*!< AHB5 Peripherals Clock Low Power Enable Register Address offset: 0x0C0 */ + __IO uint32_t APB1SMENR1; /*!< APB1 Peripherals Clock Low Power Enable Low Register Address offset: 0x0C4 */ + __IO uint32_t APB1SMENR2; /*!< APB1 Peripherals Clock Low Power Enable High Register Address offset: 0x0C8 */ + __IO uint32_t APB2SMENR; /*!< APB2 Peripherals Clock Low Power Enable Register Address offset: 0x0CC */ + __IO uint32_t APB7SMENR; /*!< APB7 Peripherals Clock Low Power Enable Register Address offset: 0x0D0 */ + uint32_t RESERVED10[3]; /*!< Reserved 0x0D4 -- 0x0DC */ + __IO uint32_t CCIPR1; /*!< IPs Clocks Configuration Register 1 Address offset: 0x0E0 */ + __IO uint32_t CCIPR2; /*!< IPs Clocks Configuration Register 2 Address offset: 0x0E4 */ + __IO uint32_t CCIPR3; /*!< IPs Clocks Configuration Register 3 Address offset: 0x0E8 */ + uint32_t RESERVED11; /*!< Reserved, Address offset: 0x0EC */ + __IO uint32_t BDCR1; /*!< Backup Domain Control Register 1 Address offset: 0x0F0 */ + __IO uint32_t CSR; /*!< V33 Clock Control & Status Register Address offset: 0x0F4 */ + __IO uint32_t BDCR2; /*!< Backup Domain Control Register 2 Address offset: 0x0F8 */ + uint32_t RESERVED12[5]; /*!< Reserved 0x0FC -- 0x010C */ + __IO uint32_t SECCFGR; /*!< RCC secure configuration register Address offset: 0x110 */ + __IO uint32_t PRIVCFGR; /*!< RCC privilege configuration register Address offset: 0x114 */ +#if !defined (STM32WBAXX_SI_CUT1_0) + uint32_t RESERVED13[42]; /*!< Reserved 0x118 -- 0x1BC */ + __IO uint32_t ASCR; /*!< RCC privilege configuration register Address offset: 0x1C0 */ + __IO uint32_t ASIER; /*!< RCC privilege configuration register Address offset: 0x1C4 */ + __IO uint32_t ASSR; /*!< RCC privilege configuration register Address offset: 0x1C8 */ + __IO uint32_t ASCNTR; /*!< RCC privilege configuration register Address offset: 0x1CC */ + __IO uint32_t ASARR; /*!< RCC privilege configuration register Address offset: 0x1D0 */ + __IO uint32_t ASCAR; /*!< RCC privilege configuration register Address offset: 0x1D4 */ + __IO uint32_t ASCOR; /*!< RCC privilege configuration register Address offset: 0x1D8 */ + uint32_t RESERVED14[9]; /*!< Reserved 0x1DC -- 0x1FC */ +#else + uint32_t RESERVED13[58]; /*!< Reserved 0x118 -- 0x1FC */ +#endif + __IO uint32_t CFGR4; /*!< RCC clock configuration register 4 Address offset: 0x200 */ + uint32_t RESERVED15; /*!< Reserved Address offset: 0x204 */ + __IO uint32_t RADIOENR; /*!< RCC RADIO peripheral clock enable register Address offset: 0x208 */ + uint32_t RESERVED16; /*!< Reserved Address offset: 0x20C */ + __IO uint32_t ECSCR1; /*!< RCC external clock sources calibration register 1 Address offset: 0x210 */ +} RCC_TypeDef; + +/** + * @brief RNG + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + uint32_t RESERVED; + __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ +} RNG_TypeDef; + +/* +* @brief RTC Specific device feature definitions +*/ +#define RTC_BKP_NB 32U +#define RTC_BACKUP_NB RTC_BKP_NB + +#define RTC_TAMP_NB 6U + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + __IO uint32_t PRIVCFGR; /*!< RTC privilege mode control register, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< RTC secure mode control register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x3C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */ + uint32_t RESERVED3[4];/*!< Reserved, Address offset: 0x58 */ + __IO uint32_t ALRABINR; /*!< RTC alarm A binary mode register, Address offset: 0x70 */ + __IO uint32_t ALRBBINR; /*!< RTC alarm B binary mode register, Address offset: 0x74 */ +} RTC_TypeDef; + +/** + * @brief Serial Audio Interface + */ +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ + uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ + __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ + __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief SPI + */ +typedef struct +{ + __IO uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */ + __IO uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */ + __IO uint32_t IER; /*!< SPI Interrupt Enable register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x14 */ + __IO uint32_t IFCR; /*!< SPI Interrupt/Status Flags Clear register, Address offset: 0x18 */ + __IO uint32_t AUTOCR; /*!< SPI Autonomous Mode Control register, Address offset: 0x1C */ + __IO uint32_t TXDR; /*!< SPI Transmit data register, Address offset: 0x20 */ + uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C */ + __IO uint32_t RXDR; /*!< SPI/I2S data register, Address offset: 0x30 */ + uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */ + __IO uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */ + __IO uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */ + __IO uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */ + __IO uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */ +} SPI_TypeDef; + +/** + * @brief System configuration controller + */ +typedef struct +{ + __IO uint32_t SECCFGR; /*!< SYSCFG secure configuration register, Address offset: 0x00 */ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ + __IO uint32_t FPUIMR; /*!< SYSCFG FPU interrupt mask register, Address offset: 0x08 */ + __IO uint32_t CNSLCKR; /*!< SYSCFG CPU non-secure lock register, Address offset: 0x0C */ + __IO uint32_t CSLCKR; /*!< SYSCFG CPU secure lock register, Address offset: 0x10 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x14 */ + __IO uint32_t MESR; /*!< SYSCFG Memory Erase Status register, Address offset: 0x18 */ + __IO uint32_t CCCSR; /*!< SYSCFG Conpensaion Cell Control&Status register, Address offset: 0x1C */ + __IO uint32_t CCVR; /*!< SYSCFG Conpensaion Cell value register, Address offset: 0x20 */ + __IO uint32_t CCCR; /*!< SYSCFG Conpensaion Cell Code register, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x28 */ + __IO uint32_t RSSCMDR; /*!< SYSCFG RSS command mode register, Address offset: 0x2C */ +} SYSCFG_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< TAMP configuration register 3, Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ + __IO uint32_t ATCR1; /*!< TAMP filter control register 1 Address offset: 0x10 */ + __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ + __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ + __IO uint32_t ATCR2; /*!< TAMP filter control register 2, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< TAMP secure mode control register, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR; /*!< TAMP privilege mode control register, Address offset: 0x24 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x28 */ + __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */ + __IO uint32_t SMISR; /*!< TAMP secure masked interrupt status register, Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ + __IO uint32_t COUNT1R; /*!< TAMP monotonic counter 1 register, Address offset: 0x40 */ + uint32_t RESERVED2[4];/*!< Reserved, Address offset: 0x44 -- 0x50 */ + __IO uint32_t RPCFGR; /*!< TAMP resources protection configuration register, Address offset: 0x54 */ + uint32_t RESERVED3[42];/*!< Reserved, Address offset: 0x58 -- 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ + __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ + __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ + __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ + __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ + __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ + __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ + __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ + __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ + __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ + __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ + __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ + __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ +} TAMP_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ + __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ + __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + __IO uint32_t OR; /*!< TIM option register, Address offset: 0x68 */ + uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x68-0x3D8 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + +/** + * @brief TSC + */ +typedef struct +{ + __IO uint32_t CR; /*!< TSC Control register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< TSC Interrupt Enable register, Address offset: 0x04 */ + __IO uint32_t ICR; /*!< TSC Interrupt Control register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< TSC Interrupt Status register, Address offset: 0x0C */ + __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x2C */ + __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */ + __IO uint32_t IOGXCR[6]; /*!< TSC I/O group x counter register, Address offset: 0x34-48 */ +} TSC_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ + __IO uint32_t AUTOCR; /*!< USART Autonomous mode control register Address offset: 0x30 */ +} USART_TypeDef; + +/** + * @brief WWDG + */ +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/*@}*/ /* end of group STM32WBA55xx_Peripherals */ + +/* -------- End of section using anonymous unions and disabling warnings -------- */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ +/** @addtogroup STM32WBAxx_Peripheral_peripheralAddr + * @{ + */ + +/* Flash, Peripheral and internal SRAMs base addresses - Non secure */ +#define FLASH_BASE_NS 0x08000000UL /*!< FLASH non-secure base address */ +#define SYSTEM_FLASH_BASE_NS 0x0BF88000UL /*!< System FLASH non-secure base address */ +#define SRAM1_BASE_NS 0x20000000UL /*!< SRAM1 non-secure base address */ +#define SRAM2_BASE_NS 0x20010000UL /*!< SRAM2 non-secure base address */ +#define SRAM6_BASE_NS 0x48028000UL /*!< 2.4 GHz RADIO TXRX SRAM non-secure base address */ +#define SEQSRAM_BASE_NS 0x48021000UL /*!< SRAM Sequence / retention non-secure base address */ +#define PERIPH_BASE_NS 0x40000000UL /*!< Peripheral non-secure base address */ +#define DBGMCU_BASE 0xE0044000UL /*!< Debug MCU registers base address */ + +/*!< Memory sizes */ +/* Internal Flash size */ +#define FLASH_SIZE ((((*((uint16_t *)FLASHSIZE_BASE)) == 0xFFFFU)) ? 0x100000U : \ + ((((*((uint16_t *)FLASHSIZE_BASE)) == 0x0000U)) ? 0x100000U : \ + (((uint32_t)(*((uint16_t *)FLASHSIZE_BASE)) & (0xFFFFU)) << 10U))) + +/* Internal SRAMs size */ +#define SRAM1_SIZE 0x00010000UL /*!< SRAM1 = 64 Kbytes */ +#define SRAM2_SIZE 0x00010000UL /*!< SRAM2 = 64 Kbytes */ +#define SRAM6_SIZE 0x00004000UL /*!< 2.4 GHz RADIO TXRX SRAM 16 Kbytes */ +#define SEQSRAM_SIZE 0x00000200UL /*!< SRAM Sequence / retention 512 bytes */ + +/*!< OTP, Engineering bytes, Option bytes defines */ +#define FLASH_OTP_BASE (SYSTEM_FLASH_BASE_NS + 0x00008000UL) +#define FLASH_OTP_SIZE 0x00000200U /*!< 512 bytes OTP (one-time programmable) */ + +#define FLASH_ENGY_BASE (SYSTEM_FLASH_BASE_NS + 0x00008500UL) +#define PACKAGE_BASE (FLASH_ENGY_BASE) /*!< Package data register base address */ +#define UID_BASE (FLASH_ENGY_BASE + 0x00000200UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (FLASH_ENGY_BASE + 0x000002A0UL) /*!< Flash size data register base address */ +#define UID64_BASE (FLASH_ENGY_BASE + 0x00000500UL) /*!< 64-bit Unique device Identification */ + +/* Peripheral memory map - Non secure */ +#define APB1PERIPH_BASE_NS PERIPH_BASE_NS +#define APB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00010000UL) +#define AHB1PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00020000UL) +#define AHB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x02020000UL) +#define APB7PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06000000UL) +#define AHB4PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06020000UL) +#define AHB5PERIPH_BASE_NS (PERIPH_BASE_NS + 0x08020000UL) + +/*!< APB1 Non secure peripherals */ +#define TIM2_BASE_NS APB1PERIPH_BASE_NS +#define TIM3_BASE_NS (APB1PERIPH_BASE_NS + 0x0400UL) +#define WWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x2C00UL) +#define IWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x3000UL) +#define USART2_BASE_NS (APB1PERIPH_BASE_NS + 0x4400UL) +#define I2C1_BASE_NS (APB1PERIPH_BASE_NS + 0x5400UL) +#define LPTIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x9400UL) + +/*!< APB2 Non secure peripherals */ +#define TIM1_BASE_NS (APB2PERIPH_BASE_NS + 0x2C00UL) +#define SPI1_BASE_NS (APB2PERIPH_BASE_NS + 0x3000UL) +#define USART1_BASE_NS (APB2PERIPH_BASE_NS + 0x3800UL) +#define TIM16_BASE_NS (APB2PERIPH_BASE_NS + 0x4400UL) +#define TIM17_BASE_NS (APB2PERIPH_BASE_NS + 0x4800UL) +#define SAI1_BASE_NS (APB2PERIPH_BASE_NS + 0x5400UL) +#define SAI1_Block_A_BASE_NS (SAI1_BASE_NS + 0x004UL) +#define SAI1_Block_B_BASE_NS (SAI1_BASE_NS + 0x024UL) + +/*!< AHB1 Non secure peripherals */ +#define GPDMA1_BASE_NS AHB1PERIPH_BASE_NS +#define FLASH_R_BASE_NS (AHB1PERIPH_BASE_NS + 0x02000UL) +#define CRC_BASE_NS (AHB1PERIPH_BASE_NS + 0x03000UL) +#define TSC_BASE_NS (AHB1PERIPH_BASE_NS + 0x04000UL) +#define RAMCFG_BASE_NS (AHB1PERIPH_BASE_NS + 0x06000UL) +#define ICACHE_BASE_NS (AHB1PERIPH_BASE_NS + 0x10400UL) +#define GTZC_TZSC_BASE_NS (AHB1PERIPH_BASE_NS + 0x12400UL) +#define GTZC_MPCBB1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12C00UL) +#define GTZC_MPCBB2_BASE_NS (AHB1PERIPH_BASE_NS + 0x13000UL) +#define GTZC_MPCBB6_BASE_NS (AHB1PERIPH_BASE_NS + 0x14000UL) + +#define GPDMA1_Channel0_BASE_NS (GPDMA1_BASE_NS + 0x0050UL) +#define GPDMA1_Channel1_BASE_NS (GPDMA1_BASE_NS + 0x00D0UL) +#define GPDMA1_Channel2_BASE_NS (GPDMA1_BASE_NS + 0x0150UL) +#define GPDMA1_Channel3_BASE_NS (GPDMA1_BASE_NS + 0x01D0UL) +#define GPDMA1_Channel4_BASE_NS (GPDMA1_BASE_NS + 0x0250UL) +#define GPDMA1_Channel5_BASE_NS (GPDMA1_BASE_NS + 0x02D0UL) +#define GPDMA1_Channel6_BASE_NS (GPDMA1_BASE_NS + 0x0350UL) +#define GPDMA1_Channel7_BASE_NS (GPDMA1_BASE_NS + 0x03D0UL) + +#define RAMCFG_SRAM1_BASE_NS (RAMCFG_BASE_NS) +#define RAMCFG_SRAM2_BASE_NS (RAMCFG_BASE_NS + 0x0040UL) +#define RAMCFG_SRAM6_BASE_NS (RAMCFG_BASE_NS + 0x0140UL) + +/*!< AHB2 Non secure peripherals */ +#define GPIOA_BASE_NS AHB2PERIPH_BASE_NS +#define GPIOB_BASE_NS (AHB2PERIPH_BASE_NS + 0x00400UL) +#define GPIOC_BASE_NS (AHB2PERIPH_BASE_NS + 0x00800UL) +#define GPIOH_BASE_NS (AHB2PERIPH_BASE_NS + 0x01C00UL) +#define AES_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0000UL) +#define HASH_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0400UL) +#define HASH_DIGEST_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0710UL) +#define RNG_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0800UL) +#define SAES_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0C00UL) +#define HSEM_BASE_NS (AHB2PERIPH_BASE_NS + 0xA1C00UL) +#define PKA_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2000UL) +#define PKA_RAM_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2400UL) + +/*!< APB7 Non secure peripherals */ +#define SYSCFG_BASE_NS (APB7PERIPH_BASE_NS + 0x0400UL) +#define SPI3_BASE_NS (APB7PERIPH_BASE_NS + 0x2000UL) +#define LPUART1_BASE_NS (APB7PERIPH_BASE_NS + 0x2400UL) +#define I2C3_BASE_NS (APB7PERIPH_BASE_NS + 0x2800UL) +#define LPTIM1_BASE_NS (APB7PERIPH_BASE_NS + 0x4400UL) +#define COMP12_BASE_NS (APB7PERIPH_BASE_NS + 0x5400UL) +#define COMP1_BASE_NS (COMP12_BASE_NS) +#define COMP2_BASE_NS (COMP12_BASE_NS + 0x04UL) +#define RTC_BASE_NS (APB7PERIPH_BASE_NS + 0x7800UL) +#define TAMP_BASE_NS (APB7PERIPH_BASE_NS + 0x7C00UL) + +/*!< AHB4 Non secure peripherals */ +#define PWR_BASE_NS (AHB4PERIPH_BASE_NS + 0x0800UL) +#define RCC_BASE_NS (AHB4PERIPH_BASE_NS + 0x0C00UL) +#define ADC4_BASE_NS (AHB4PERIPH_BASE_NS + 0x1000UL) +#define ADC4_COMMON_BASE_NS (AHB4PERIPH_BASE_NS + 0x1308UL) +#define EXTI_BASE_NS (AHB4PERIPH_BASE_NS + 0x2000UL) + +/*!< AHB5 Non secure peripherals */ +#define RADIO_BASE_NS AHB5PERIPH_BASE_NS +#define PTACONV_BASE_NS (AHB5PERIPH_BASE_NS + 0x18000UL) + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/* Flash, Peripheral and internal SRAMs base addresses - Secure */ +#define FLASH_BASE_S 0x0C000000UL /*!< FLASH secure base address */ +#define SYSTEM_FLASH_BASE_S 0x0FF80000UL /*!< System FLASH non-secure base address */ +#define SRAM1_BASE_S 0x30000000UL /*!< SRAM1 secure base address */ +#define SRAM2_BASE_S 0x30010000UL /*!< SRAM2 secure base address */ +#define SRAM6_BASE_S 0x58028000UL /*!< 2.4 GHz RADIO TXRX SRAM secure base address */ +#define SEQSRAM_BASE_S 0x58021000UL /*!< SRAM Sequence / retention non-secure base address */ +#define PERIPH_BASE_S 0x50000000UL /*!< Peripheral secure base address */ + +/* Peripheral memory map - Secure */ +#define APB1PERIPH_BASE_S PERIPH_BASE_S +#define APB2PERIPH_BASE_S (PERIPH_BASE_S + 0x00010000UL) +#define AHB1PERIPH_BASE_S (PERIPH_BASE_S + 0x00020000UL) +#define AHB2PERIPH_BASE_S (PERIPH_BASE_S + 0x02020000UL) +#define APB7PERIPH_BASE_S (PERIPH_BASE_S + 0x06000000UL) +#define AHB4PERIPH_BASE_S (PERIPH_BASE_S + 0x06020000UL) +#define AHB5PERIPH_BASE_S (PERIPH_BASE_S + 0x08020000UL) + +/*!< APB1 Secure peripherals */ +#define TIM2_BASE_S APB1PERIPH_BASE_S +#define TIM3_BASE_S (APB1PERIPH_BASE_S + 0x0400UL) +#define WWDG_BASE_S (APB1PERIPH_BASE_S + 0x2C00UL) +#define IWDG_BASE_S (APB1PERIPH_BASE_S + 0x3000UL) +#define USART2_BASE_S (APB1PERIPH_BASE_S + 0x4400UL) +#define I2C1_BASE_S (APB1PERIPH_BASE_S + 0x5400UL) +#define LPTIM2_BASE_S (APB1PERIPH_BASE_S + 0x9400UL) + +/*!< APB2 Secure peripherals */ +#define TIM1_BASE_S (APB2PERIPH_BASE_S + 0x2C00UL) +#define SPI1_BASE_S (APB2PERIPH_BASE_S + 0x3000UL) +#define USART1_BASE_S (APB2PERIPH_BASE_S + 0x3800UL) +#define TIM16_BASE_S (APB2PERIPH_BASE_S + 0x4400UL) +#define TIM17_BASE_S (APB2PERIPH_BASE_S + 0x4800UL) +#define SAI1_BASE_S (APB2PERIPH_BASE_S + 0x5400UL) +#define SAI1_Block_A_BASE_S (SAI1_BASE_S + 0x004UL) +#define SAI1_Block_B_BASE_S (SAI1_BASE_S + 0x024UL) + +/*!< AHB1 Secure peripherals */ +#define GPDMA1_BASE_S AHB1PERIPH_BASE_S +#define FLASH_R_BASE_S (AHB1PERIPH_BASE_S + 0x02000UL) +#define CRC_BASE_S (AHB1PERIPH_BASE_S + 0x03000UL) +#define TSC_BASE_S (AHB1PERIPH_BASE_S + 0x04000UL) +#define RAMCFG_BASE_S (AHB1PERIPH_BASE_S + 0x06000UL) +#define ICACHE_BASE_S (AHB1PERIPH_BASE_S + 0x10400UL) +#define GTZC_TZSC_BASE_S (AHB1PERIPH_BASE_S + 0x12400UL) +#define GTZC_TZIC_BASE_S (AHB1PERIPH_BASE_S + 0x12800UL) +#define GTZC_MPCBB1_BASE_S (AHB1PERIPH_BASE_S + 0x12C00UL) +#define GTZC_MPCBB2_BASE_S (AHB1PERIPH_BASE_S + 0x13000UL) +#define GTZC_MPCBB6_BASE_S (AHB1PERIPH_BASE_S + 0x14000UL) + +#define GPDMA1_Channel0_BASE_S (GPDMA1_BASE_S + 0x0050UL) +#define GPDMA1_Channel1_BASE_S (GPDMA1_BASE_S + 0x00D0UL) +#define GPDMA1_Channel2_BASE_S (GPDMA1_BASE_S + 0x0150UL) +#define GPDMA1_Channel3_BASE_S (GPDMA1_BASE_S + 0x01D0UL) +#define GPDMA1_Channel4_BASE_S (GPDMA1_BASE_S + 0x0250UL) +#define GPDMA1_Channel5_BASE_S (GPDMA1_BASE_S + 0x02D0UL) +#define GPDMA1_Channel6_BASE_S (GPDMA1_BASE_S + 0x0350UL) +#define GPDMA1_Channel7_BASE_S (GPDMA1_BASE_S + 0x03D0UL) + +#define RAMCFG_SRAM1_BASE_S (RAMCFG_BASE_S) +#define RAMCFG_SRAM2_BASE_S (RAMCFG_BASE_S + 0x0040UL) +#define RAMCFG_SRAM6_BASE_S (RAMCFG_BASE_S + 0x0140UL) + +/*!< AHB2 Secure peripherals */ +#define GPIOA_BASE_S AHB2PERIPH_BASE_S +#define GPIOB_BASE_S (AHB2PERIPH_BASE_S + 0x00400UL) +#define GPIOC_BASE_S (AHB2PERIPH_BASE_S + 0x00800UL) +#define GPIOH_BASE_S (AHB2PERIPH_BASE_S + 0x01C00UL) +#define AES_BASE_S (AHB2PERIPH_BASE_S + 0xA0000UL) +#define HASH_BASE_S (AHB2PERIPH_BASE_S + 0xA0400UL) +#define HASH_DIGEST_BASE_S (AHB2PERIPH_BASE_S + 0xA0710UL) +#define RNG_BASE_S (AHB2PERIPH_BASE_S + 0xA0800UL) +#define SAES_BASE_S (AHB2PERIPH_BASE_S + 0xA0C00UL) +#define HSEM_BASE_S (AHB2PERIPH_BASE_S + 0xA1C00UL) +#define PKA_BASE_S (AHB2PERIPH_BASE_S + 0xA2000UL) +#define PKA_RAM_BASE_S (AHB2PERIPH_BASE_S + 0xA2400UL) + +/*!< APB7 Secure peripherals */ +#define SYSCFG_BASE_S (APB7PERIPH_BASE_S + 0x0400UL) +#define SPI3_BASE_S (APB7PERIPH_BASE_S + 0x2000UL) +#define LPUART1_BASE_S (APB7PERIPH_BASE_S + 0x2400UL) +#define I2C3_BASE_S (APB7PERIPH_BASE_S + 0x2800UL) +#define LPTIM1_BASE_S (APB7PERIPH_BASE_S + 0x4400UL) +#define COMP12_BASE_S (APB7PERIPH_BASE_S + 0x5400UL) +#define COMP1_BASE_S (COMP12_BASE_S) +#define COMP2_BASE_S (COMP12_BASE_S + 0x04UL) +#define RTC_BASE_S (APB7PERIPH_BASE_S + 0x7800UL) +#define TAMP_BASE_S (APB7PERIPH_BASE_S + 0x7C00UL) + +/*!< AHB4 Secure peripherals */ +#define PWR_BASE_S (AHB4PERIPH_BASE_S + 0x0800UL) +#define RCC_BASE_S (AHB4PERIPH_BASE_S + 0x0C00UL) +#define ADC4_BASE_S (AHB4PERIPH_BASE_S + 0x1000UL) +#define ADC4_COMMON_BASE_S (AHB4PERIPH_BASE_S + 0x1308UL) +#define EXTI_BASE_S (AHB4PERIPH_BASE_S + 0x2000UL) + +/*!< AHB5 Secure peripherals */ +#define RADIO_BASE_S AHB5PERIPH_BASE_S +#define PTACONV_BASE_S (AHB5PERIPH_BASE_S + 0x18000UL) +#endif + +/************ RSSLIB SAU system Flash region definition constants *************/ +#define RSSLIB_SYS_FLASH_NS_PFUNC_START (SYSTEM_FLASH_BASE_NS + 0x00007E40UL) +#define RSSLIB_SYS_FLASH_NS_PFUNC_END (SYSTEM_FLASH_BASE_NS + 0x00007E6BUL) + +/************ RSSLIB function return constants ********************************/ +#define RSSLIB_ERROR 0xF5F5F5F5UL +#define RSSLIB_SUCCESS 0xEAEAEAEAUL + +/*!< RSSLIB pointer function structure address definition */ +#define RSSLIB_PFUNC_BASE RSSLIB_SYS_FLASH_NS_PFUNC_START +#define RSSLIB_PFUNC ((RSSLIB_pFunc_TypeDef *)RSSLIB_PFUNC_BASE) + +/*!< HDP Area constant definition */ +#define RSSLIB_HDP_AREA_Pos (0U) +#define RSSLIB_HDP_AREA_Msk (0x1UL << RSSLIB_HDP_AREA_Pos ) + +/** + * @brief Prototype of RSSLIB Close and exit HDP Function + * @detail This function close the requested hdp area passed in input + * parameter and jump to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param HdpArea notifies which hdp area to close, can be a combination of + * hdpa area 1 and hdp area 2 + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t ( *RSSLIB_S_CloseExitHDP_TypeDef)( uint32_t HdpArea, uint32_t VectorTableAddr ); + +/** + * @brief RSSLib non-secure callable function pointer structure + */ +typedef struct +{ + __IM uint32_t Reserved[8]; +}NSC_pFuncTypeDef; + +/** + * @brief RSSLib secure callable function pointer structure + */ +typedef struct +{ + __IM uint32_t Reserved2[2]; + __IM RSSLIB_S_CloseExitHDP_TypeDef CloseExitHDP; /*!< RSSLIB Bootloader Close and exit HDP Address offset: 0x28 */ +}S_pFuncTypeDef; + +/** + * @brief RSSLib function pointer structure + */ +typedef struct +{ + NSC_pFuncTypeDef NSC; + S_pFuncTypeDef S; +}RSSLIB_pFunc_TypeDef; + + +/** @} */ /* End of group STM32WBAxx_Peripheral_peripheralAddr */ +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ +/** @addtogroup STM32WBAxx_Peripheral_declaration + * @{ + */ +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +#define ADC4_NS ((ADC_TypeDef *) ADC4_BASE_NS) +#define ADC4_COMMON_NS ((ADC_Common_TypeDef *) ADC4_COMMON_BASE_NS) +#define AES_NS ((AES_TypeDef *) AES_BASE_NS) +#define COMP1_NS ((COMP_TypeDef *) COMP1_BASE_NS) +#define COMP2_NS ((COMP_TypeDef *) COMP2_BASE_NS) +#define COMP12_COMMON_NS ((COMP_Common_TypeDef *) COMP1_BASE_NS) +#define CRC_NS ((CRC_TypeDef *) CRC_BASE_NS) +#define EXTI_NS ((EXTI_TypeDef *) EXTI_BASE_NS) +#define FLASH_NS ((FLASH_TypeDef *) FLASH_R_BASE_NS) +#define GPDMA1_NS ((DMA_TypeDef *) GPDMA1_BASE_NS) +#define GPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_NS) +#define GPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_NS) +#define GPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_NS) +#define GPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_NS) +#define GPDMA1_Channel4_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_NS) +#define GPDMA1_Channel5_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_NS) +#define GPDMA1_Channel6_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_NS) +#define GPDMA1_Channel7_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_NS) +#define GPIOA_NS ((GPIO_TypeDef *) GPIOA_BASE_NS) +#define GPIOB_NS ((GPIO_TypeDef *) GPIOB_BASE_NS) +#define GPIOC_NS ((GPIO_TypeDef *) GPIOC_BASE_NS) +#define GPIOH_NS ((GPIO_TypeDef *) GPIOH_BASE_NS) +#define GTZC_MPCBB1_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_NS) +#define GTZC_MPCBB2_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_NS) +#define GTZC_MPCBB6_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB6_BASE_NS) +#define GTZC_TZSC_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC_BASE_NS) +#define HASH_NS ((HASH_TypeDef *) HASH_BASE_NS) +#define HASH_DIGEST_NS ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS) +#define HSEM_NS ((HSEM_TypeDef *) HSEM_BASE_NS) +#define HSEM_COMMON_NS ((HSEM_Common_TypeDef *) (HSEM_BASE_NS + 0x100U)) +#define I2C1_NS ((I2C_TypeDef *) I2C1_BASE_NS) +#define I2C3_NS ((I2C_TypeDef *) I2C3_BASE_NS) +#define ICACHE_NS ((ICACHE_TypeDef *) ICACHE_BASE_NS) +#define IWDG_NS ((IWDG_TypeDef *) IWDG_BASE_NS) +#define LPTIM1_NS ((LPTIM_TypeDef *) LPTIM1_BASE_NS) +#define LPTIM2_NS ((LPTIM_TypeDef *) LPTIM2_BASE_NS) +#define LPUART1_NS ((USART_TypeDef *) LPUART1_BASE_NS) +#define PKA_NS ((PKA_TypeDef *) PKA_BASE_NS) +#define PTACONV_NS ((PTACONV_TypeDef *) PTACONV_BASE_NS) +#define PWR_NS ((PWR_TypeDef *) PWR_BASE_NS) +#define RAMCFG_SRAM1_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_NS) +#define RAMCFG_SRAM2_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_NS) +#define RAMCFG_SRAM6_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM6_BASE_NS) +#define RCC_NS ((RCC_TypeDef *) RCC_BASE_NS) +#define RNG_NS ((RNG_TypeDef *) RNG_BASE_NS) +#define RTC_NS ((RTC_TypeDef *) RTC_BASE_NS) +#define SAES_NS ((AES_TypeDef *) SAES_BASE_NS) +#define SAI1_NS ((SAI_TypeDef *) SAI1_BASE_NS) +#define SAI1_Block_A_NS ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_NS) +#define SAI1_Block_B_NS ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_NS) +#define SPI1_NS ((SPI_TypeDef *) SPI1_BASE_NS) +#define SPI3_NS ((SPI_TypeDef *) SPI3_BASE_NS) +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_BASE_NS) +#define TAMP_NS ((TAMP_TypeDef *) TAMP_BASE_NS) +#define TIM1_NS ((TIM_TypeDef *) TIM1_BASE_NS) +#define TIM2_NS ((TIM_TypeDef *) TIM2_BASE_NS) +#define TIM3_NS ((TIM_TypeDef *) TIM3_BASE_NS) +#define TIM16_NS ((TIM_TypeDef *) TIM16_BASE_NS) +#define TIM17_NS ((TIM_TypeDef *) TIM17_BASE_NS) +#define TSC_NS ((TSC_TypeDef *) TSC_BASE_NS) +#define USART1_NS ((USART_TypeDef *) USART1_BASE_NS) +#define USART2_NS ((USART_TypeDef *) USART2_BASE_NS) +#define WWDG_NS ((WWDG_TypeDef *) WWDG_BASE_NS) + +/*!< Memory & Instance aliases and base addresses for Non-Secure/Secure peripherals */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define ADC4_S ((ADC_TypeDef *) ADC4_BASE_S) +#define ADC4_COMMON_S ((ADC_Common_TypeDef *) ADC4_COMMON_BASE_S) +#define AES_S ((AES_TypeDef *) AES_BASE_S) +#define COMP1_S ((COMP_TypeDef *) COMP1_BASE_S) +#define COMP2_S ((COMP_TypeDef *) COMP2_BASE_S) +#define COMP12_COMMON_S ((COMP_Common_TypeDef *) COMP1_BASE_S) +#define CRC_S ((CRC_TypeDef *) CRC_BASE_S) +#define EXTI_S ((EXTI_TypeDef *) EXTI_BASE_S) +#define FLASH_S ((FLASH_TypeDef *) FLASH_R_BASE_S) +#define GPDMA1_S ((DMA_TypeDef *) GPDMA1_BASE_S) +#define GPDMA1_Channel0_S ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_S) +#define GPDMA1_Channel1_S ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_S) +#define GPDMA1_Channel2_S ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_S) +#define GPDMA1_Channel3_S ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_S) +#define GPDMA1_Channel4_S ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_S) +#define GPDMA1_Channel5_S ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_S) +#define GPDMA1_Channel6_S ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_S) +#define GPDMA1_Channel7_S ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_S) +#define GPIOA_S ((GPIO_TypeDef *) GPIOA_BASE_S) +#define GPIOB_S ((GPIO_TypeDef *) GPIOB_BASE_S) +#define GPIOC_S ((GPIO_TypeDef *) GPIOC_BASE_S) +#define GPIOH_S ((GPIO_TypeDef *) GPIOH_BASE_S) +#define GTZC_MPCBB1_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_S) +#define GTZC_MPCBB2_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_S) +#define GTZC_MPCBB6_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB6_BASE_S) +#define GTZC_TZIC_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC_BASE_S) +#define GTZC_TZSC_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC_BASE_S) +#define HASH_S ((HASH_TypeDef *) HASH_BASE_S) +#define HASH_DIGEST_S ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S) +#define HSEM_S ((HSEM_TypeDef *) HSEM_BASE_S) +#define HSEM_COMMON_S ((HSEM_Common_TypeDef *) (HSEM_BASE_S + 0x100U)) +#define I2C1_S ((I2C_TypeDef *) I2C1_BASE_S) +#define I2C3_S ((I2C_TypeDef *) I2C3_BASE_S) +#define ICACHE_S ((ICACHE_TypeDef *) ICACHE_BASE_S) +#define IWDG_S ((IWDG_TypeDef *) IWDG_BASE_S) +#define LPTIM1_S ((LPTIM_TypeDef *) LPTIM1_BASE_S) +#define LPTIM2_S ((LPTIM_TypeDef *) LPTIM2_BASE_S) +#define LPUART1_S ((USART_TypeDef *) LPUART1_BASE_S) +#define PKA_S ((PKA_TypeDef *) PKA_BASE_S) +#define PTACONV_S ((PTACONV_TypeDef *) PTACONV_BASE_S) +#define PWR_S ((PWR_TypeDef *) PWR_BASE_S) +#define RAMCFG_SRAM1_S ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_S) +#define RAMCFG_SRAM2_S ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_S) +#define RAMCFG_SRAM6_S ((RAMCFG_TypeDef *) RAMCFG_SRAM6_BASE_S) +#define RCC_S ((RCC_TypeDef *) RCC_BASE_S) +#define RNG_S ((RNG_TypeDef *) RNG_BASE_S) +#define RTC_S ((RTC_TypeDef *) RTC_BASE_S) +#define SAES_S ((AES_TypeDef *) SAES_BASE_S) +#define SAI1_S ((SAI_TypeDef *) SAI1_BASE_S) +#define SAI1_Block_A_S ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_S) +#define SAI1_Block_B_S ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_S) +#define SPI1_S ((SPI_TypeDef *) SPI1_BASE_S) +#define SPI3_S ((SPI_TypeDef *) SPI3_BASE_S) +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE_S) +#define TAMP_S ((TAMP_TypeDef *) TAMP_BASE_S) +#define TIM1_S ((TIM_TypeDef *) TIM1_BASE_S) +#define TIM2_S ((TIM_TypeDef *) TIM2_BASE_S) +#define TIM3_S ((TIM_TypeDef *) TIM3_BASE_S) +#define TIM16_S ((TIM_TypeDef *) TIM16_BASE_S) +#define TIM17_S ((TIM_TypeDef *) TIM17_BASE_S) +#define TSC_S ((TSC_TypeDef *) TSC_BASE_S) +#define USART1_S ((USART_TypeDef *) USART1_BASE_S) +#define USART2_S ((USART_TypeDef *) USART2_BASE_S) +#define WWDG_S ((WWDG_TypeDef *) WWDG_BASE_S) + + +/*!< Memory base addresses for Secure peripherals */ +#define FLASH_BASE FLASH_BASE_S +#define SRAM1_BASE SRAM1_BASE_S +#define SRAM2_BASE SRAM2_BASE_S +#define SRAM6_BASE SRAM6_BASE_S +#define SEQSRAM_BASE SEQSRAM_BASE_S + +/*!< Instance aliases and base addresses for Secure peripherals */ +#define ADC4 ADC4_S +#define ADC4_BASE ADC4_BASE_S +#define ADC4_COMMON ADC4_COMMON_S +#define ADC4_COMMON_BASE ADC4_COMMON_BASE_S +#define AES AES_S +#define AES_BASE AES_BASE_S +#define COMP1 COMP1_S +#define COMP1_BASE COMP1_BASE_S +#define COMP2 COMP2_S +#define COMP2_BASE COMP2_BASE_S +#define COMP12_COMMON COMP12_COMMON_S +#define CRC CRC_S +#define CRC_BASE CRC_BASE_S +#define EXTI EXTI_S +#define EXTI_BASE EXTI_BASE_S +#define FLASH FLASH_S +#define FLASH_R_BASE FLASH_R_BASE_S +#define GPDMA1 GPDMA1_S +#define GPDMA1_BASE GPDMA1_BASE_S +#define GPDMA1_Channel0 GPDMA1_Channel0_S +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_S +#define GPDMA1_Channel1 GPDMA1_Channel1_S +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_S +#define GPDMA1_Channel2 GPDMA1_Channel2_S +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_S +#define GPDMA1_Channel3 GPDMA1_Channel3_S +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_S +#define GPDMA1_Channel4 GPDMA1_Channel4_S +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_S +#define GPDMA1_Channel5 GPDMA1_Channel5_S +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_S +#define GPDMA1_Channel6 GPDMA1_Channel6_S +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_S +#define GPDMA1_Channel7 GPDMA1_Channel7_S +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_S +#define GPIOA GPIOA_S +#define GPIOA_BASE GPIOA_BASE_S +#define GPIOB GPIOB_S +#define GPIOB_BASE GPIOB_BASE_S +#define GPIOC GPIOC_S +#define GPIOC_BASE GPIOC_BASE_S +#define GPIOH GPIOH_S +#define GPIOH_BASE GPIOH_BASE_S +#define GTZC_MPCBB1 GTZC_MPCBB1_S +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_S +#define GTZC_MPCBB2 GTZC_MPCBB2_S +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_S +#define GTZC_MPCBB6 GTZC_MPCBB6_S +#define GTZC_MPCBB6_BASE GTZC_MPCBB6_BASE_S +#define GTZC_TZIC GTZC_TZIC_S +#define GTZC_TZIC_BASE GTZC_TZIC_BASE_S +#define GTZC_TZSC GTZC_TZSC_S +#define GTZC_TZSC_BASE GTZC_TZSC_BASE_S +#define HASH HASH_S +#define HASH_BASE HASH_BASE_S +#define HASH_DIGEST HASH_DIGEST_S +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_S +#define HSEM HSEM_S +#define HSEM_BASE HSEM_BASE_S +#define HSEM_COMMON HSEM_COMMON_S +#define I2C1 I2C1_S +#define I2C1_BASE I2C1_BASE_S +#define I2C3 I2C3_S +#define I2C3_BASE I2C3_BASE_S +#define ICACHE ICACHE_S +#define ICACHE_BASE ICACHE_BASE_S +#define IWDG IWDG_S +#define IWDG_BASE IWDG_BASE_S +#define LPTIM1 LPTIM1_S +#define LPTIM1_BASE LPTIM1_BASE_S +#define LPTIM2 LPTIM2_S +#define LPTIM2_BASE LPTIM2_BASE_S +#define LPUART1 LPUART1_S +#define LPUART1_BASE LPUART1_BASE_S +#define PKA PKA_S +#define PKA_BASE PKA_BASE_S +#define PKA_RAM_BASE PKA_RAM_BASE_S +#define PTACONV_BASE PTACONV_BASE_S +#define PTACONV PTACONV_S +#define PWR PWR_S +#define PWR_BASE PWR_BASE_S +#define RADIO_BASE RADIO_BASE_S +#define RAMCFG_SRAM1 RAMCFG_SRAM1_S +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_S +#define RAMCFG_SRAM2 RAMCFG_SRAM2_S +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_S +#define RAMCFG_SRAM6 RAMCFG_SRAM6_S +#define RAMCFG_SRAM6_BASE RAMCFG_SRAM6_BASE_S +#define RCC RCC_S +#define RCC_BASE RCC_BASE_S +#define RNG RNG_S +#define RNG_BASE RNG_BASE_S +#define RTC RTC_S +#define RTC_BASE RTC_BASE_S +#define SAES SAES_S +#define SAES_BASE SAES_BASE_S +#define SAI1 SAI1_S +#define SAI1_BASE SAI1_BASE_S +#define SAI1_Block_A SAI1_Block_A_S +#define SAI1_Block_A_BASE SAI1_Block_A_BASE_S +#define SAI1_Block_B SAI1_Block_B_S +#define SAI1_Block_B_BASE SAI1_Block_B_BASE_S +#define SPI1 SPI1_S +#define SPI1_BASE SPI1_BASE_S +#define SPI3 SPI3_S +#define SPI3_BASE SPI3_BASE_S +#define SYSCFG SYSCFG_S +#define SYSCFG_BASE SYSCFG_BASE_S +#define TAMP TAMP_S +#define TAMP_BASE TAMP_BASE_S +#define TIM1 TIM1_S +#define TIM1_BASE TIM1_BASE_S +#define TIM2 TIM2_S +#define TIM2_BASE TIM2_BASE_S +#define TIM3 TIM3_S +#define TIM3_BASE TIM3_BASE_S +#define TIM16 TIM16_S +#define TIM16_BASE TIM16_BASE_S +#define TIM17 TIM17_S +#define TIM17_BASE TIM17_BASE_S +#define TSC TSC_S +#define TSC_BASE TSC_BASE_S +#define USART1 USART1_S +#define USART1_BASE USART1_BASE_S +#define USART2 USART2_S +#define USART2_BASE USART2_BASE_S +#define WWDG WWDG_S +#define WWDG_BASE WWDG_BASE_S + +#else +/*!< Memory base addresses for Non secure peripherals */ +#define FLASH_BASE FLASH_BASE_NS +#define SRAM1_BASE SRAM1_BASE_NS +#define SRAM2_BASE SRAM2_BASE_NS +#define SRAM6_BASE SRAM6_BASE_NS +#define SEQSRAM_BASE SEQSRAM_BASE_NS + +/*!< Instance aliases and base addresses for Non secure peripherals */ +#define ADC4 ADC4_NS +#define ADC4_BASE ADC4_BASE_NS +#define ADC4_COMMON ADC4_COMMON_NS +#define ADC4_COMMON_BASE ADC4_COMMON_BASE_NS +#define AES AES_NS +#define AES_BASE AES_BASE_NS +#define COMP1 COMP1_NS +#define COMP1_BASE COMP1_BASE_NS +#define COMP2 COMP2_NS +#define COMP2_BASE COMP2_BASE_NS +#define COMP12_COMMON COMP12_COMMON_NS +#define CRC CRC_NS +#define CRC_BASE CRC_BASE_NS +#define EXTI EXTI_NS +#define EXTI_BASE EXTI_BASE_NS +#define FLASH FLASH_NS +#define FLASH_R_BASE FLASH_R_BASE_NS +#define GPDMA1 GPDMA1_NS +#define GPDMA1_BASE GPDMA1_BASE_NS +#define GPDMA1_Channel0 GPDMA1_Channel0_NS +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_NS +#define GPDMA1_Channel1 GPDMA1_Channel1_NS +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_NS +#define GPDMA1_Channel2 GPDMA1_Channel2_NS +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_NS +#define GPDMA1_Channel3 GPDMA1_Channel3_NS +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_NS +#define GPDMA1_Channel4 GPDMA1_Channel4_NS +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_NS +#define GPDMA1_Channel5 GPDMA1_Channel5_NS +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_NS +#define GPDMA1_Channel6 GPDMA1_Channel6_NS +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_NS +#define GPDMA1_Channel7 GPDMA1_Channel7_NS +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_NS +#define GPIOA GPIOA_NS +#define GPIOA_BASE GPIOA_BASE_NS +#define GPIOB GPIOB_NS +#define GPIOB_BASE GPIOB_BASE_NS +#define GPIOC GPIOC_NS +#define GPIOC_BASE GPIOC_BASE_NS +#define GPIOH GPIOH_NS +#define GPIOH_BASE GPIOH_BASE_NS +#define GTZC_MPCBB1 GTZC_MPCBB1_NS +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_NS +#define GTZC_MPCBB2 GTZC_MPCBB2_NS +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_NS +#define GTZC_MPCBB6 GTZC_MPCBB6_NS +#define GTZC_MPCBB6_BASE GTZC_MPCBB6_BASE_NS +#define GTZC_TZSC GTZC_TZSC_NS +#define GTZC_TZSC_BASE GTZC_TZSC_BASE_NS +#define HASH HASH_NS +#define HASH_BASE HASH_BASE_NS +#define HASH_DIGEST HASH_DIGEST_NS +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_NS +#define HSEM HSEM_NS +#define HSEM_BASE HSEM_BASE_NS +#define HSEM_COMMON HSEM_COMMON_NS +#define I2C1 I2C1_NS +#define I2C1_BASE I2C1_BASE_NS +#define I2C3 I2C3_NS +#define I2C3_BASE I2C3_BASE_NS +#define ICACHE ICACHE_NS +#define ICACHE_BASE ICACHE_BASE_NS +#define IWDG IWDG_NS +#define IWDG_BASE IWDG_BASE_NS +#define LPTIM1 LPTIM1_NS +#define LPTIM1_BASE LPTIM1_BASE_NS +#define LPTIM2 LPTIM2_NS +#define LPTIM2_BASE LPTIM2_BASE_NS +#define LPUART1 LPUART1_NS +#define LPUART1_BASE LPUART1_BASE_NS +#define PKA PKA_NS +#define PKA_BASE PKA_BASE_NS +#define PKA_RAM_BASE PKA_RAM_BASE_NS +#define PTACONV_BASE PTACONV_BASE_NS +#define PTACONV PTACONV_NS +#define PWR PWR_NS +#define PWR_BASE PWR_BASE_NS +#define RADIO_BASE RADIO_BASE_NS +#define RAMCFG_SRAM1 RAMCFG_SRAM1_NS +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_NS +#define RAMCFG_SRAM2 RAMCFG_SRAM2_NS +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_NS +#define RAMCFG_SRAM6 RAMCFG_SRAM6_NS +#define RAMCFG_SRAM6_BASE RAMCFG_SRAM6_BASE_NS +#define RCC RCC_NS +#define RCC_BASE RCC_BASE_NS +#define RNG RNG_NS +#define RNG_BASE RNG_BASE_NS +#define RTC RTC_NS +#define RTC_BASE RTC_BASE_NS +#define SAES SAES_NS +#define SAES_BASE SAES_BASE_NS +#define SAI1 SAI1_NS +#define SAI1_BASE SAI1_BASE_NS +#define SAI1_Block_A SAI1_Block_A_NS +#define SAI1_Block_A_BASE SAI1_Block_A_BASE_NS +#define SAI1_Block_B SAI1_Block_B_NS +#define SAI1_Block_B_BASE SAI1_Block_B_BASE_NS +#define SPI1 SPI1_NS +#define SPI1_BASE SPI1_BASE_NS +#define SPI3 SPI3_NS +#define SPI3_BASE SPI3_BASE_NS +#define SYSCFG SYSCFG_NS +#define SYSCFG_BASE SYSCFG_BASE_NS +#define TAMP TAMP_NS +#define TAMP_BASE TAMP_BASE_NS +#define TIM1 TIM1_NS +#define TIM1_BASE TIM1_BASE_NS +#define TIM2 TIM2_NS +#define TIM2_BASE TIM2_BASE_NS +#define TIM3 TIM3_NS +#define TIM3_BASE TIM3_BASE_NS +#define TIM16 TIM16_NS +#define TIM16_BASE TIM16_BASE_NS +#define TIM17 TIM17_NS +#define TIM17_BASE TIM17_BASE_NS +#define TSC TSC_NS +#define TSC_BASE TSC_BASE_NS +#define USART1 USART1_NS +#define USART1_BASE USART1_BASE_NS +#define USART2 USART2_NS +#define USART2_BASE USART2_BASE_NS +#define WWDG WWDG_NS +#define WWDG_BASE WWDG_BASE_NS +#endif + + +/** @addtogroup Exported_constants + * @{ + */ + +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 16000U /*!< LSI Maximum startup time in us : 4 cycles @ 250 Hz = 16 ms */ +/** + * @} + */ + +/** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter (ADC) */ +/* */ +/******************************************************************************/ +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ +#define ADC_ISR_EOCAL_Pos (11U) +#define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */ +#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< ADC end of calibration flag */ +#define ADC_ISR_LDORDY_Pos (12U) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC internal voltage regulator ready flag */ + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ +#define ADC_IER_EOCALIE_Pos (11U) +#define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */ +#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< ADC end of calibration interrupt */ +#define ADC_IER_LDORDYIE_Pos (12U) +#define ADC_IER_LDORDYIE_Msk (0x1UL << ADC_IER_LDORDYIE_Pos) /*!< 0x00001000 */ +#define ADC_IER_LDORDYIE ADC_IER_LDORDYIE_Msk /*!< ADC Voltage Regulator Ready interrupt source */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR1 register *****************/ +#define ADC_CFGR1_DMAEN_Pos (0U) +#define ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC_CFGR1_DMACFG_Pos (1U) +#define ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC_CFGR1_RES_Pos (2U) +#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x0000000C */ +#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC Data resolution */ +#define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000004 */ +#define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ + +#define ADC_CFGR1_SCANDIR_Pos (4U) +#define ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000010 */ +#define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */ +#define ADC_CFGR1_ALIGN_Pos (5U) +#define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignment */ + +#define ADC_CFGR1_EXTSEL_Pos (6U) +#define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ +#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR1_EXTEN_Pos (10U) +#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR1_OVRMOD_Pos (12U) +#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR1_CONT_Pos (13U) +#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR1_WAIT_Pos (14U) +#define ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */ +#define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC low power auto wait */ +#define ADC_CFGR1_DISCEN_Pos (16U) +#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ +#define ADC_CFGR1_CHSELRMOD_Pos (21U) +#define ADC_CFGR1_CHSELRMOD_Msk (0x1UL << ADC_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */ +#define ADC_CFGR1_CHSELRMOD ADC_CFGR1_CHSELRMOD_Msk /*!< ADC group regular sequencer mode */ + +#define ADC_CFGR1_AWD1SGL_Pos (22U) +#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR1_AWD1EN_Pos (23U) +#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ + +#define ADC_CFGR1_AWD1CH_Pos (26U) +#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_OVSE_Pos (0U) +#define ADC_CFGR2_OVSE_Msk (0x1UL << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ + +#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TOVS_Pos (9U) +#define ADC_CFGR2_TOVS_Msk (0x1UL << ADC_CFGR2_TOVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ + +#define ADC_CFGR2_LFTRIG_Pos (29U) +#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC low frequency trigger mode */ + +/******************** Bit definition for ADC_SMPR register ******************/ +#define ADC_SMPR_SMP1_Pos (0U) +#define ADC_SMPR_SMP1_Msk (0x7UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000007 */ +#define ADC_SMPR_SMP1 ADC_SMPR_SMP1_Msk /*!< ADC group of channels sampling time 1 */ +#define ADC_SMPR_SMP1_0 (0x1UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000001 */ +#define ADC_SMPR_SMP1_1 (0x2UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000002 */ +#define ADC_SMPR_SMP1_2 (0x4UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR_SMP2_Pos (4U) +#define ADC_SMPR_SMP2_Msk (0x7UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000070 */ +#define ADC_SMPR_SMP2 ADC_SMPR_SMP2_Msk /*!< ADC group of channels sampling time 2 */ +#define ADC_SMPR_SMP2_0 (0x1UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000010 */ +#define ADC_SMPR_SMP2_1 (0x2UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000020 */ +#define ADC_SMPR_SMP2_2 (0x4UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000040 */ + +#define ADC_SMPR_SMPSEL_Pos (8U) +#define ADC_SMPR_SMPSEL_Msk (0x3FFFFUL << ADC_SMPR_SMPSEL_Pos) /*!< 0x03FFFF00 */ +#define ADC_SMPR_SMPSEL ADC_SMPR_SMPSEL_Msk /*!< ADC all channels sampling time selection */ +#define ADC_SMPR_SMPSEL0_Pos (8U) +#define ADC_SMPR_SMPSEL0_Msk (0x1UL << ADC_SMPR_SMPSEL0_Pos) /*!< 0x00000100 */ +#define ADC_SMPR_SMPSEL0 ADC_SMPR_SMPSEL0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR_SMPSEL1_Pos (9U) +#define ADC_SMPR_SMPSEL1_Msk (0x1UL << ADC_SMPR_SMPSEL1_Pos) /*!< 0x00000200 */ +#define ADC_SMPR_SMPSEL1 ADC_SMPR_SMPSEL1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR_SMPSEL2_Pos (10U) +#define ADC_SMPR_SMPSEL2_Msk (0x1UL << ADC_SMPR_SMPSEL2_Pos) /*!< 0x00000400 */ +#define ADC_SMPR_SMPSEL2 ADC_SMPR_SMPSEL2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR_SMPSEL3_Pos (11U) +#define ADC_SMPR_SMPSEL3_Msk (0x1UL << ADC_SMPR_SMPSEL3_Pos) /*!< 0x00000800 */ +#define ADC_SMPR_SMPSEL3 ADC_SMPR_SMPSEL3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR_SMPSEL4_Pos (12U) +#define ADC_SMPR_SMPSEL4_Msk (0x1UL << ADC_SMPR_SMPSEL4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR_SMPSEL4 ADC_SMPR_SMPSEL4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR_SMPSEL5_Pos (13U) +#define ADC_SMPR_SMPSEL5_Msk (0x1UL << ADC_SMPR_SMPSEL5_Pos) /*!< 0x00002000 */ +#define ADC_SMPR_SMPSEL5 ADC_SMPR_SMPSEL5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR_SMPSEL6_Pos (14U) +#define ADC_SMPR_SMPSEL6_Msk (0x1UL << ADC_SMPR_SMPSEL6_Pos) /*!< 0x00004000 */ +#define ADC_SMPR_SMPSEL6 ADC_SMPR_SMPSEL6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR_SMPSEL7_Pos (15U) +#define ADC_SMPR_SMPSEL7_Msk (0x1UL << ADC_SMPR_SMPSEL7_Pos) /*!< 0x00008000 */ +#define ADC_SMPR_SMPSEL7 ADC_SMPR_SMPSEL7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR_SMPSEL8_Pos (16U) +#define ADC_SMPR_SMPSEL8_Msk (0x1UL << ADC_SMPR_SMPSEL8_Pos) /*!< 0x00010000 */ +#define ADC_SMPR_SMPSEL8 ADC_SMPR_SMPSEL8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR_SMPSEL9_Pos (17U) +#define ADC_SMPR_SMPSEL9_Msk (0x1UL << ADC_SMPR_SMPSEL9_Pos) /*!< 0x00020000 */ +#define ADC_SMPR_SMPSEL9 ADC_SMPR_SMPSEL9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR_SMPSEL10_Pos (18U) +#define ADC_SMPR_SMPSEL10_Msk (0x1UL << ADC_SMPR_SMPSEL10_Pos) /*!< 0x00040000 */ +#define ADC_SMPR_SMPSEL10 ADC_SMPR_SMPSEL10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR_SMPSEL11_Pos (19U) +#define ADC_SMPR_SMPSEL11_Msk (0x1UL << ADC_SMPR_SMPSEL11_Pos) /*!< 0x00080000 */ +#define ADC_SMPR_SMPSEL11 ADC_SMPR_SMPSEL11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR_SMPSEL12_Pos (20U) +#define ADC_SMPR_SMPSEL12_Msk (0x1UL << ADC_SMPR_SMPSEL12_Pos) /*!< 0x00100000 */ +#define ADC_SMPR_SMPSEL12 ADC_SMPR_SMPSEL12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR_SMPSEL13_Pos (21U) +#define ADC_SMPR_SMPSEL13_Msk (0x1UL << ADC_SMPR_SMPSEL13_Pos) /*!< 0x00200000 */ +#define ADC_SMPR_SMPSEL13 ADC_SMPR_SMPSEL13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR_SMPSEL14_Pos (22U) +#define ADC_SMPR_SMPSEL14_Msk (0x1UL << ADC_SMPR_SMPSEL14_Pos) /*!< 0x00400000 */ +#define ADC_SMPR_SMPSEL14 ADC_SMPR_SMPSEL14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR_SMPSEL15_Pos (23U) +#define ADC_SMPR_SMPSEL15_Msk (0x1UL << ADC_SMPR_SMPSEL15_Pos) /*!< 0x00800000 */ +#define ADC_SMPR_SMPSEL15 ADC_SMPR_SMPSEL15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR_SMPSEL16_Pos (24U) +#define ADC_SMPR_SMPSEL16_Msk (0x1UL << ADC_SMPR_SMPSEL16_Pos) /*!< 0x01000000 */ +#define ADC_SMPR_SMPSEL16 ADC_SMPR_SMPSEL16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR_SMPSEL17_Pos (25U) +#define ADC_SMPR_SMPSEL17_Msk (0x1UL << ADC_SMPR_SMPSEL17_Pos) /*!< 0x02000000 */ +#define ADC_SMPR_SMPSEL17 ADC_SMPR_SMPSEL17_Msk /*!< ADC channel 17 sampling time selection */ + +/******************** Bit definition for ADC_AWD1TR register *******************/ +#define ADC_AWD1TR_LT1_Pos (0U) +#define ADC_AWD1TR_LT1_Msk (0xFFFUL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_AWD1TR_LT1 ADC_AWD1TR_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ +#define ADC_AWD1TR_LT1_0 (0x001UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000001 */ +#define ADC_AWD1TR_LT1_1 (0x002UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000002 */ +#define ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000004 */ +#define ADC_AWD1TR_LT1_3 (0x008UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000008 */ +#define ADC_AWD1TR_LT1_4 (0x010UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000010 */ +#define ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000020 */ +#define ADC_AWD1TR_LT1_6 (0x040UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000040 */ +#define ADC_AWD1TR_LT1_7 (0x080UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000080 */ +#define ADC_AWD1TR_LT1_8 (0x100UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000100 */ +#define ADC_AWD1TR_LT1_9 (0x200UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000200 */ +#define ADC_AWD1TR_LT1_10 (0x400UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000400 */ +#define ADC_AWD1TR_LT1_11 (0x800UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000800 */ + +#define ADC_AWD1TR_HT1_Pos (16U) +#define ADC_AWD1TR_HT1_Msk (0xFFFUL << ADC_AWD1TR_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD1TR_HT1 ADC_AWD1TR_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ +#define ADC_AWD1TR_HT1_0 (0x001UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00010000 */ +#define ADC_AWD1TR_HT1_1 (0x002UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00020000 */ +#define ADC_AWD1TR_HT1_2 (0x004UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00040000 */ +#define ADC_AWD1TR_HT1_3 (0x008UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00080000 */ +#define ADC_AWD1TR_HT1_4 (0x010UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00100000 */ +#define ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00200000 */ +#define ADC_AWD1TR_HT1_6 (0x040UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00400000 */ +#define ADC_AWD1TR_HT1_7 (0x080UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00800000 */ +#define ADC_AWD1TR_HT1_8 (0x100UL << ADC_AWD1TR_HT1_Pos) /*!< 0x01000000 */ +#define ADC_AWD1TR_HT1_9 (0x200UL << ADC_AWD1TR_HT1_Pos) /*!< 0x02000000 */ +#define ADC_AWD1TR_HT1_10 (0x400UL << ADC_AWD1TR_HT1_Pos) /*!< 0x04000000 */ +#define ADC_AWD1TR_HT1_11 (0x800UL << ADC_AWD1TR_HT1_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_AWDTR2 register *******************/ +#define ADC_AWD2TR_LT2_Pos (0U) +#define ADC_AWD2TR_LT2_Msk (0xFFFUL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000FFF */ +#define ADC_AWD2TR_LT2 ADC_AWD2TR_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ +#define ADC_AWD2TR_LT2_0 (0x001UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000001 */ +#define ADC_AWD2TR_LT2_1 (0x002UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000002 */ +#define ADC_AWD2TR_LT2_2 (0x004UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000004 */ +#define ADC_AWD2TR_LT2_3 (0x008UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000008 */ +#define ADC_AWD2TR_LT2_4 (0x010UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000010 */ +#define ADC_AWD2TR_LT2_5 (0x020UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000020 */ +#define ADC_AWD2TR_LT2_6 (0x040UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000040 */ +#define ADC_AWD2TR_LT2_7 (0x080UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000080 */ +#define ADC_AWD2TR_LT2_8 (0x100UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000100 */ +#define ADC_AWD2TR_LT2_9 (0x200UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000200 */ +#define ADC_AWD2TR_LT2_10 (0x400UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000400 */ +#define ADC_AWD2TR_LT2_11 (0x800UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000800 */ + +#define ADC_AWD2TR_HT2_Pos (16U) +#define ADC_AWD2TR_HT2_Msk (0xFFFUL << ADC_AWD2TR_HT2_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD2TR_HT2 ADC_AWD2TR_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ +#define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ +#define ADC_AWD2TR_HT2_1 (0x002UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00020000 */ +#define ADC_AWD2TR_HT2_2 (0x004UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00040000 */ +#define ADC_AWD2TR_HT2_3 (0x008UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00080000 */ +#define ADC_AWD2TR_HT2_4 (0x010UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00100000 */ +#define ADC_AWD2TR_HT2_5 (0x020UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00200000 */ +#define ADC_AWD2TR_HT2_6 (0x040UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00400000 */ +#define ADC_AWD2TR_HT2_7 (0x080UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00800000 */ +#define ADC_AWD2TR_HT2_8 (0x100UL << ADC_AWD2TR_HT2_Pos) /*!< 0x01000000 */ +#define ADC_AWD2TR_HT2_9 (0x200UL << ADC_AWD2TR_HT2_Pos) /*!< 0x02000000 */ +#define ADC_AWD2TR_HT2_10 (0x400UL << ADC_AWD2TR_HT2_Pos) /*!< 0x04000000 */ +#define ADC_AWD2TR_HT2_11 (0x800UL << ADC_AWD2TR_HT2_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_CHSELR register ****************/ +#define ADC_CHSELR_CHSEL_Pos (0U) +#define ADC_CHSELR_CHSEL_Msk (0x3FFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0003FFFF */ +#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL17_Pos (17U) +#define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL16_Pos (16U) +#define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL15_Pos (15U) +#define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ +#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL14_Pos (14U) +#define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL13_Pos (13U) +#define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL12_Pos (12U) +#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL11_Pos (11U) +#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ +#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL10_Pos (10U) +#define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL9_Pos (9U) +#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL8_Pos (8U) +#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL7_Pos (7U) +#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ +#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL6_Pos (6U) +#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL5_Pos (5U) +#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL4_Pos (4U) +#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL3_Pos (3U) +#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ +#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL2_Pos (2U) +#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL1_Pos (1U) +#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL0_Pos (0U) +#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */ + +#define ADC_CHSELR_SQ_ALL_Pos (0U) +#define ADC_CHSELR_SQ_ALL_Msk (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CHSELR_SQ_ALL ADC_CHSELR_SQ_ALL_Msk /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */ + +#define ADC_CHSELR_SQ8_Pos (28U) +#define ADC_CHSELR_SQ8_Msk (0xFUL << ADC_CHSELR_SQ8_Pos) /*!< 0xF0000000 */ +#define ADC_CHSELR_SQ8 ADC_CHSELR_SQ8_Msk /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ8_0 (0x1UL << ADC_CHSELR_SQ8_Pos) /*!< 0x10000000 */ +#define ADC_CHSELR_SQ8_1 (0x2UL << ADC_CHSELR_SQ8_Pos) /*!< 0x20000000 */ +#define ADC_CHSELR_SQ8_2 (0x4UL << ADC_CHSELR_SQ8_Pos) /*!< 0x40000000 */ +#define ADC_CHSELR_SQ8_3 (0x8UL << ADC_CHSELR_SQ8_Pos) /*!< 0x80000000 */ + +#define ADC_CHSELR_SQ7_Pos (24U) +#define ADC_CHSELR_SQ7_Msk (0xFUL << ADC_CHSELR_SQ7_Pos) /*!< 0x0F000000 */ +#define ADC_CHSELR_SQ7 ADC_CHSELR_SQ7_Msk /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ7_0 (0x1UL << ADC_CHSELR_SQ7_Pos) /*!< 0x01000000 */ +#define ADC_CHSELR_SQ7_1 (0x2UL << ADC_CHSELR_SQ7_Pos) /*!< 0x02000000 */ +#define ADC_CHSELR_SQ7_2 (0x4UL << ADC_CHSELR_SQ7_Pos) /*!< 0x04000000 */ +#define ADC_CHSELR_SQ7_3 (0x8UL << ADC_CHSELR_SQ7_Pos) /*!< 0x08000000 */ + +#define ADC_CHSELR_SQ6_Pos (20U) +#define ADC_CHSELR_SQ6_Msk (0xFUL << ADC_CHSELR_SQ6_Pos) /*!< 0x00F00000 */ +#define ADC_CHSELR_SQ6 ADC_CHSELR_SQ6_Msk /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ6_0 (0x1UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00100000 */ +#define ADC_CHSELR_SQ6_1 (0x2UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00200000 */ +#define ADC_CHSELR_SQ6_2 (0x4UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00400000 */ +#define ADC_CHSELR_SQ6_3 (0x8UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00800000 */ + +#define ADC_CHSELR_SQ5_Pos (16U) +#define ADC_CHSELR_SQ5_Msk (0xFUL << ADC_CHSELR_SQ5_Pos) /*!< 0x000F0000 */ +#define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ5_0 (0x1UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_SQ5_1 (0x2UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_SQ5_2 (0x4UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_SQ5_3 (0x8UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00080000 */ + +#define ADC_CHSELR_SQ4_Pos (12U) +#define ADC_CHSELR_SQ4_Msk (0xFUL << ADC_CHSELR_SQ4_Pos) /*!< 0x0000F000 */ +#define ADC_CHSELR_SQ4 ADC_CHSELR_SQ4_Msk /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ4_0 (0x1UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_SQ4_1 (0x2UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_SQ4_2 (0x4UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_SQ4_3 (0x8UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00008000 */ + +#define ADC_CHSELR_SQ3_Pos (8U) +#define ADC_CHSELR_SQ3_Msk (0xFUL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000F00 */ +#define ADC_CHSELR_SQ3 ADC_CHSELR_SQ3_Msk /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ3_0 (0x1UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_SQ3_1 (0x2UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_SQ3_2 (0x4UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_SQ3_3 (0x8UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000800 */ + +#define ADC_CHSELR_SQ2_Pos (4U) +#define ADC_CHSELR_SQ2_Msk (0xFUL << ADC_CHSELR_SQ2_Pos) /*!< 0x000000F0 */ +#define ADC_CHSELR_SQ2 ADC_CHSELR_SQ2_Msk /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ2_0 (0x1UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_SQ2_1 (0x2UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_SQ2_2 (0x4UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_SQ2_3 (0x8UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000080 */ + +#define ADC_CHSELR_SQ1_Pos (0U) +#define ADC_CHSELR_SQ1_Msk (0xFUL << ADC_CHSELR_SQ1_Pos) /*!< 0x0000000F */ +#define ADC_CHSELR_SQ1 ADC_CHSELR_SQ1_Msk /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ1_0 (0x1UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_SQ1_1 (0x2UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_SQ1_2 (0x4UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_SQ1_3 (0x8UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000008 */ + +/******************** Bit definition for ADC_AWD3TR register *******************/ +#define ADC_AWD3TR_LT3_Pos (0U) +#define ADC_AWD3TR_LT3_Msk (0xFFFUL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000FFF */ +#define ADC_AWD3TR_LT3 ADC_AWD3TR_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ +#define ADC_AWD3TR_LT3_0 (0x001UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000001 */ +#define ADC_AWD3TR_LT3_1 (0x002UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000002 */ +#define ADC_AWD3TR_LT3_2 (0x004UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000004 */ +#define ADC_AWD3TR_LT3_3 (0x008UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000008 */ +#define ADC_AWD3TR_LT3_4 (0x010UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000010 */ +#define ADC_AWD3TR_LT3_5 (0x020UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000020 */ +#define ADC_AWD3TR_LT3_6 (0x040UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000040 */ +#define ADC_AWD3TR_LT3_7 (0x080UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000080 */ +#define ADC_AWD3TR_LT3_8 (0x100UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000100 */ +#define ADC_AWD3TR_LT3_9 (0x200UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000200 */ +#define ADC_AWD3TR_LT3_10 (0x400UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000400 */ +#define ADC_AWD3TR_LT3_11 (0x800UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000800 */ + +#define ADC_AWD3TR_HT3_Pos (16U) +#define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD3TR_HT3 ADC_AWD3TR_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ +#define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */ +#define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */ +#define ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00040000 */ +#define ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00080000 */ +#define ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00100000 */ +#define ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00200000 */ +#define ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00400000 */ +#define ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00800000 */ +#define ADC_AWD3TR_HT3_8 (0x100UL << ADC_AWD3TR_HT3_Pos) /*!< 0x01000000 */ +#define ADC_AWD3TR_HT3_9 (0x200UL << ADC_AWD3TR_HT3_Pos) /*!< 0x02000000 */ +#define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) /*!< 0x04000000 */ +#define ADC_AWD3TR_HT3_11 (0x800UL << ADC_AWD3TR_HT3_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_DATA_Pos (0U) +#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */ + +/******************** Bit definition for ADC_PWRR register ******************/ +#define ADC_PWRR_AUTOFF_Pos (0U) +#define ADC_PWRR_AUTOFF_Msk (0x1UL << ADC_PWRR_AUTOFF_Pos) /*!< 0x00000001 */ +#define ADC_PWRR_AUTOFF ADC_PWRR_AUTOFF_Msk /*!< ADC auto-off mode */ +#define ADC_PWRR_DPD_Pos (1U) +#define ADC_PWRR_DPD_Msk (0x1UL << ADC_PWRR_DPD_Pos) /*!< 0x00000002 */ +#define ADC_PWRR_DPD ADC_PWRR_DPD_Msk /*!< ADC deep power down mode */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0x3FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0003FFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0x3FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0003FFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_Pos (0U) +#define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_0 (0x01UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_1 (0x02UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_2 (0x04UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_3 (0x08UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_4 (0x10UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_5 (0x20UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_6 (0x40UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000040 */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ + + +/******************************************************************************/ +/* */ +/* Analog comparators (COMP) */ +/* */ +/******************************************************************************/ +/********************** Bit definition for COMP_CSR register ****************/ +#define COMP_CSR_EN_Pos (0U) +#define COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos) /*!< 0x00000001 */ +#define COMP_CSR_EN COMP_CSR_EN_Msk /*!< Comparator enable */ + +#define COMP_CSR_INMSEL_Pos (4U) +#define COMP_CSR_INMSEL_Msk (0xFUL << COMP_CSR_INMSEL_Pos) /*!< 0x000000F0 */ +#define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< Comparator input minus selection */ +#define COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000010 */ +#define COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000020 */ +#define COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000040 */ +#define COMP_CSR_INMSEL_3 (0x8UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000080 */ + +#define COMP_CSR_INPSEL_Pos (8U) +#define COMP_CSR_INPSEL_Msk (0x3UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000300 */ +#define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< Comparator input plus selection */ +#define COMP_CSR_INPSEL_0 (0x1UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000100 */ +#define COMP_CSR_INPSEL_1 (0x2UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000200 */ + +#define COMP_CSR_WINMODE_Pos (11U) +#define COMP_CSR_WINMODE_Msk (0x1UL << COMP_CSR_WINMODE_Pos) /*!< 0x00000800 */ +#define COMP_CSR_WINMODE COMP_CSR_WINMODE_Msk /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */ + +#define COMP_CSR_WINOUT_Pos (14U) +#define COMP_CSR_WINOUT_Msk (0x1UL << COMP_CSR_WINOUT_Pos) /*!< 0x00004000 */ +#define COMP_CSR_WINOUT COMP_CSR_WINOUT_Msk /*!< Pair of comparators window output level. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */ + +#define COMP_CSR_POLARITY_Pos (15U) +#define COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos) /*!< 0x00008000 */ +#define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< Comparator output polarity */ + +#define COMP_CSR_HYST_Pos (16U) +#define COMP_CSR_HYST_Msk (0x3UL << COMP_CSR_HYST_Pos) /*!< 0x00030000 */ +#define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< Comparator input hysteresis */ +#define COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos) /*!< 0x00010000 */ +#define COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos) /*!< 0x00020000 */ + +#define COMP_CSR_PWRMODE_Pos (18U) +#define COMP_CSR_PWRMODE_Msk (0x3UL << COMP_CSR_PWRMODE_Pos) /*!< 0x000C0000 */ +#define COMP_CSR_PWRMODE COMP_CSR_PWRMODE_Msk /*!< Comparator power mode */ +#define COMP_CSR_PWRMODE_0 (0x1UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00001000 */ +#define COMP_CSR_PWRMODE_1 (0x2UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00002000 */ + +#define COMP_CSR_BLANKSEL_Pos (20U) +#define COMP_CSR_BLANKSEL_Msk (0x1FUL << COMP_CSR_BLANKSEL_Pos) /*!< 0x01F00000 */ +#define COMP_CSR_BLANKSEL COMP_CSR_BLANKSEL_Msk /*!< Comparator blanking source */ +#define COMP_CSR_BLANKSEL_0 (0x01UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x00100000 */ +#define COMP_CSR_BLANKSEL_1 (0x02UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x00200000 */ +#define COMP_CSR_BLANKSEL_2 (0x04UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x00400000 */ +#define COMP_CSR_BLANKSEL_3 (0x08UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x00800000 */ +#define COMP_CSR_BLANKSEL_4 (0x10UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x01000000 */ + +#define COMP_CSR_VALUE_Pos (30U) +#define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */ +#define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< Comparator output level */ + +#define COMP_CSR_LOCK_Pos (31U) +#define COMP_CSR_LOCK_Msk (0x1UL << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */ +#define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< Comparator lock */ + + + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + + +/******************************************************************************/ +/* */ +/* Advanced Encryption Standard (AES) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for AES_CR register *********************/ +#define AES_CR_EN_Pos (0U) +#define AES_CR_EN_Msk (0x1UL << AES_CR_EN_Pos) /*!< 0x00000001 */ +#define AES_CR_EN AES_CR_EN_Msk /*!< AES Enable */ +#define AES_CR_DATATYPE_Pos (1U) +#define AES_CR_DATATYPE_Msk (0x3UL << AES_CR_DATATYPE_Pos) /*!< 0x00000006 */ +#define AES_CR_DATATYPE AES_CR_DATATYPE_Msk /*!< Data type selection */ +#define AES_CR_DATATYPE_0 (0x1UL << AES_CR_DATATYPE_Pos) /*!< 0x00000002 */ +#define AES_CR_DATATYPE_1 (0x2UL << AES_CR_DATATYPE_Pos) /*!< 0x00000004 */ +#define AES_CR_MODE_Pos (3U) +#define AES_CR_MODE_Msk (0x3UL << AES_CR_MODE_Pos) /*!< 0x00000018 */ +#define AES_CR_MODE AES_CR_MODE_Msk /*!< AES Mode Of Operation */ +#define AES_CR_MODE_0 (0x1UL << AES_CR_MODE_Pos) /*!< 0x00000008 */ +#define AES_CR_MODE_1 (0x2UL << AES_CR_MODE_Pos) /*!< 0x00000010 */ +#define AES_CR_CHMOD_Pos (5U) +#define AES_CR_CHMOD_Msk (0x803UL << AES_CR_CHMOD_Pos) /*!< 0x00010060 */ +#define AES_CR_CHMOD AES_CR_CHMOD_Msk /*!< AES Chaining Mode */ +#define AES_CR_CHMOD_0 (0x001UL << AES_CR_CHMOD_Pos) /*!< 0x00000020 */ +#define AES_CR_CHMOD_1 (0x002UL << AES_CR_CHMOD_Pos) /*!< 0x00000040 */ +#define AES_CR_CHMOD_2 (0x800UL << AES_CR_CHMOD_Pos) /*!< 0x00010000 */ +#define AES_CR_DMAINEN_Pos (11U) +#define AES_CR_DMAINEN_Msk (0x1UL << AES_CR_DMAINEN_Pos) /*!< 0x00000800 */ +#define AES_CR_DMAINEN AES_CR_DMAINEN_Msk /*!< Enable data input phase DMA management */ +#define AES_CR_DMAOUTEN_Pos (12U) +#define AES_CR_DMAOUTEN_Msk (0x1UL << AES_CR_DMAOUTEN_Pos) /*!< 0x00001000 */ +#define AES_CR_DMAOUTEN AES_CR_DMAOUTEN_Msk /*!< Enable data output phase DMA management */ +#define AES_CR_GCMPH_Pos (13U) +#define AES_CR_GCMPH_Msk (0x3UL << AES_CR_GCMPH_Pos) /*!< 0x00006000 */ +#define AES_CR_GCMPH AES_CR_GCMPH_Msk /*!< GCM Phase */ +#define AES_CR_GCMPH_0 (0x1UL << AES_CR_GCMPH_Pos) /*!< 0x00002000 */ +#define AES_CR_GCMPH_1 (0x2UL << AES_CR_GCMPH_Pos) /*!< 0x00004000 */ +#define AES_CR_KEYSIZE_Pos (18U) +#define AES_CR_KEYSIZE_Msk (0x1UL << AES_CR_KEYSIZE_Pos) /*!< 0x00040000 */ +#define AES_CR_KEYSIZE AES_CR_KEYSIZE_Msk /*!< Key size selection */ +#define AES_CR_KEYPROT_Pos (19U) +#define AES_CR_KEYPROT_Msk (0x1UL << AES_CR_KEYPROT_Pos) /*!< 0x00080000 */ +#define AES_CR_KEYPROT AES_CR_KEYPROT_Msk /*!< Key protection */ +#define AES_CR_NPBLB_Pos (20U) +#define AES_CR_NPBLB_Msk (0xFUL << AES_CR_NPBLB_Pos) /*!< 0x00F00000 */ +#define AES_CR_NPBLB AES_CR_NPBLB_Msk /*!< Number of padding bytes in payload last block */ +#define AES_CR_NPBLB_0 (0x1UL << AES_CR_NPBLB_Pos) /*!< 0x00100000 */ +#define AES_CR_NPBLB_1 (0x2UL << AES_CR_NPBLB_Pos) /*!< 0x00200000 */ +#define AES_CR_NPBLB_2 (0x4UL << AES_CR_NPBLB_Pos) /*!< 0x00400000 */ +#define AES_CR_NPBLB_3 (0x8UL << AES_CR_NPBLB_Pos) /*!< 0x00800000 */ +#define AES_CR_KMOD_Pos (24U) +#define AES_CR_KMOD_Msk (0x3UL << AES_CR_KMOD_Pos) /*!< 0x03000000 */ +#define AES_CR_KMOD AES_CR_KMOD_Msk /*!< Key mode selection */ +#define AES_CR_KMOD_0 (0x1UL << AES_CR_KMOD_Pos) /*!< 0x01000000 */ +#define AES_CR_KMOD_1 (0x2UL << AES_CR_KMOD_Pos) /*!< 0x02000000 */ +#define AES_CR_KSHAREID_Pos (26U) +#define AES_CR_KSHAREID_Msk (0x3UL << AES_CR_KSHAREID_Pos) /*!< 0x0C000000 */ +#define AES_CR_KSHAREID AES_CR_KSHAREID_Msk /*!< Key Shared ID */ +#define AES_CR_KEYSEL_Pos (28U) +#define AES_CR_KEYSEL_Msk (0x7UL << AES_CR_KEYSEL_Pos) /*!< 0x70000000 */ +#define AES_CR_KEYSEL AES_CR_KEYSEL_Msk /*!< Key Selection */ +#define AES_CR_KEYSEL_0 (0x1UL << AES_CR_KEYSEL_Pos) /*!< 0x10000000 */ +#define AES_CR_KEYSEL_1 (0x2UL << AES_CR_KEYSEL_Pos) /*!< 0x20000000 */ +#define AES_CR_KEYSEL_2 (0x4UL << AES_CR_KEYSEL_Pos) /*!< 0x40000000 */ +#define AES_CR_IPRST_Pos (31U) +#define AES_CR_IPRST_Msk (0x1UL << AES_CR_IPRST_Pos) /*!< 0x80000000 */ +#define AES_CR_IPRST AES_CR_IPRST_Msk /*!< AES IP software reset */ + + +/******************* Bit definition for AES_SR register *********************/ +#define AES_SR_CCF_Pos (0U) +#define AES_SR_CCF_Msk (0x1UL << AES_SR_CCF_Pos) /*!< 0x00000001 */ +#define AES_SR_CCF AES_SR_CCF_Msk /*!< Computation Complete Flag */ +#define AES_SR_RDERR_Pos (1U) +#define AES_SR_RDERR_Msk (0x1UL << AES_SR_RDERR_Pos) /*!< 0x00000002 */ +#define AES_SR_RDERR AES_SR_RDERR_Msk /*!< Read Error Flag */ +#define AES_SR_WRERR_Pos (2U) +#define AES_SR_WRERR_Msk (0x1UL << AES_SR_WRERR_Pos) /*!< 0x00000004 */ +#define AES_SR_WRERR AES_SR_WRERR_Msk /*!< Write Error Flag */ +#define AES_SR_BUSY_Pos (3U) +#define AES_SR_BUSY_Msk (0x1UL << AES_SR_BUSY_Pos) /*!< 0x00000008 */ +#define AES_SR_BUSY AES_SR_BUSY_Msk /*!< Busy Flag */ +#define AES_SR_KEYVALID_Pos (7U) +#define AES_SR_KEYVALID_Msk (0x1UL << AES_SR_KEYVALID_Pos) /*!< 0x00000080 */ +#define AES_SR_KEYVALID AES_SR_KEYVALID_Msk /*!< Key Valid Flag */ + +/******************* Bit definition for AES_DINR register *******************/ +#define AES_DINR_Pos (0U) +#define AES_DINR_Msk (0xFFFFFFFFUL << AES_DINR_Pos) /*!< 0xFFFFFFFF */ +#define AES_DINR AES_DINR_Msk /*!< AES Data Input Register */ + +/******************* Bit definition for AES_DOUTR register ******************/ +#define AES_DOUTR_Pos (0U) +#define AES_DOUTR_Msk (0xFFFFFFFFUL << AES_DOUTR_Pos) /*!< 0xFFFFFFFF */ +#define AES_DOUTR AES_DOUTR_Msk /*!< AES Data Output Register */ + +/******************* Bit definition for AES_KEYR0 register ******************/ +#define AES_KEYR0_Pos (0U) +#define AES_KEYR0_Msk (0xFFFFFFFFUL << AES_KEYR0_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR0 AES_KEYR0_Msk /*!< AES Key Register 0 */ + +/******************* Bit definition for AES_KEYR1 register ******************/ +#define AES_KEYR1_Pos (0U) +#define AES_KEYR1_Msk (0xFFFFFFFFUL << AES_KEYR1_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR1 AES_KEYR1_Msk /*!< AES Key Register 1 */ + +/******************* Bit definition for AES_KEYR2 register ******************/ +#define AES_KEYR2_Pos (0U) +#define AES_KEYR2_Msk (0xFFFFFFFFUL << AES_KEYR2_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR2 AES_KEYR2_Msk /*!< AES Key Register 2 */ + +/******************* Bit definition for AES_KEYR3 register ******************/ +#define AES_KEYR3_Pos (0U) +#define AES_KEYR3_Msk (0xFFFFFFFFUL << AES_KEYR3_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR3 AES_KEYR3_Msk /*!< AES Key Register 3 */ + +/******************* Bit definition for AES_KEYR4 register ******************/ +#define AES_KEYR4_Pos (0U) +#define AES_KEYR4_Msk (0xFFFFFFFFUL << AES_KEYR4_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR4 AES_KEYR4_Msk /*!< AES Key Register 4 */ + +/******************* Bit definition for AES_KEYR5 register ******************/ +#define AES_KEYR5_Pos (0U) +#define AES_KEYR5_Msk (0xFFFFFFFFUL << AES_KEYR5_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR5 AES_KEYR5_Msk /*!< AES Key Register 5 */ + +/******************* Bit definition for AES_KEYR6 register ******************/ +#define AES_KEYR6_Pos (0U) +#define AES_KEYR6_Msk (0xFFFFFFFFUL << AES_KEYR6_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR6 AES_KEYR6_Msk /*!< AES Key Register 6 */ + +/******************* Bit definition for AES_KEYR7 register ******************/ +#define AES_KEYR7_Pos (0U) +#define AES_KEYR7_Msk (0xFFFFFFFFUL << AES_KEYR7_Pos) /*!< 0xFFFFFFFF */ +#define AES_KEYR7 AES_KEYR7_Msk /*!< AES Key Register 7 */ + +/******************* Bit definition for AES_IVR0 register ******************/ +#define AES_IVR0_Pos (0U) +#define AES_IVR0_Msk (0xFFFFFFFFUL << AES_IVR0_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR0 AES_IVR0_Msk /*!< AES Initialization Vector Register 0 */ + +/******************* Bit definition for AES_IVR1 register ******************/ +#define AES_IVR1_Pos (0U) +#define AES_IVR1_Msk (0xFFFFFFFFUL << AES_IVR1_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR1 AES_IVR1_Msk /*!< AES Initialization Vector Register 1 */ + +/******************* Bit definition for AES_IVR2 register ******************/ +#define AES_IVR2_Pos (0U) +#define AES_IVR2_Msk (0xFFFFFFFFUL << AES_IVR2_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR2 AES_IVR2_Msk /*!< AES Initialization Vector Register 2 */ + +/******************* Bit definition for AES_IVR3 register ******************/ +#define AES_IVR3_Pos (0U) +#define AES_IVR3_Msk (0xFFFFFFFFUL << AES_IVR3_Pos) /*!< 0xFFFFFFFF */ +#define AES_IVR3 AES_IVR3_Msk /*!< AES Initialization Vector Register 3 */ + +/******************* Bit definition for AES_SUSP0R register ******************/ +#define AES_SUSP0R_Pos (0U) +#define AES_SUSP0R_Msk (0xFFFFFFFFUL << AES_SUSP0R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP0R AES_SUSP0R_Msk /*!< AES Suspend registers 0 */ + +/******************* Bit definition for AES_SUSP1R register ******************/ +#define AES_SUSP1R_Pos (0U) +#define AES_SUSP1R_Msk (0xFFFFFFFFUL << AES_SUSP1R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP1R AES_SUSP1R_Msk /*!< AES Suspend registers 1 */ + +/******************* Bit definition for AES_SUSP2R register ******************/ +#define AES_SUSP2R_Pos (0U) +#define AES_SUSP2R_Msk (0xFFFFFFFFUL << AES_SUSP2R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP2R AES_SUSP2R_Msk /*!< AES Suspend registers 2 */ + +/******************* Bit definition for AES_SUSP3R register ******************/ +#define AES_SUSP3R_Pos (0U) +#define AES_SUSP3R_Msk (0xFFFFFFFFUL << AES_SUSP3R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP3R AES_SUSP3R_Msk /*!< AES Suspend registers 3 */ + +/******************* Bit definition for AES_SUSP4R register ******************/ +#define AES_SUSP4R_Pos (0U) +#define AES_SUSP4R_Msk (0xFFFFFFFFUL << AES_SUSP4R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP4R AES_SUSP4R_Msk /*!< AES Suspend registers 4 */ + +/******************* Bit definition for AES_SUSP5R register ******************/ +#define AES_SUSP5R_Pos (0U) +#define AES_SUSP5R_Msk (0xFFFFFFFFUL << AES_SUSP5R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP5R AES_SUSP5R_Msk /*!< AES Suspend registers 5 */ + +/******************* Bit definition for AES_SUSP6R register ******************/ +#define AES_SUSP6R_Pos (0U) +#define AES_SUSP6R_Msk (0xFFFFFFFFUL << AES_SUSP6R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP6R AES_SUSP6R_Msk /*!< AES Suspend registers 6 */ + +/******************* Bit definition for AES_SUSP7R register ******************/ +#define AES_SUSP7R_Pos (0U) +#define AES_SUSP7R_Msk (0xFFFFFFFFUL << AES_SUSP7R_Pos) /*!< 0xFFFFFFFF */ +#define AES_SUSP7R AES_SUSP7R_Msk /*!< AES Suspend registers 7 */ + +/******************* Bit definition for AES_IER register ******************/ +#define AES_IER_CCFIE_Pos (0U) +#define AES_IER_CCFIE_Msk (0x1UL << AES_IER_CCFIE_Pos) /*!< 0x00000001 */ +#define AES_IER_CCFIE AES_IER_CCFIE_Msk /*!< Computation complete flag interrupt enable */ +#define AES_IER_RWEIE_Pos (1U) +#define AES_IER_RWEIE_Msk (0x1UL << AES_IER_RWEIE_Pos) /*!< 0x00000002 */ +#define AES_IER_RWEIE AES_IER_RWEIE_Msk /*!< Read or write error Interrupt Enable */ +#define AES_IER_KEIE_Pos (2U) +#define AES_IER_KEIE_Msk (0x1UL << AES_IER_KEIE_Pos) /*!< 0x00000004 */ +#define AES_IER_KEIE AES_IER_KEIE_Msk /*!< Key error interrupt enable */ +#define AES_IER_RNGEIE_Pos (3U) +#define AES_IER_RNGEIE_Msk (0x1UL << AES_IER_RNGEIE_Pos) /*!< 0x00000008 */ +#define AES_IER_RNGEIE AES_IER_RNGEIE_Msk /*!< SAES Rng error interrupt enable */ + +/******************* Bit definition for AES_ISR register ******************/ +#define AES_ISR_CCF_Pos (0U) +#define AES_ISR_CCF_Msk (0x1UL << AES_ISR_CCF_Pos) /*!< 0x00000001 */ +#define AES_ISR_CCF AES_ISR_CCF_Msk /*!< Computation complete flag */ +#define AES_ISR_RWEIF_Pos (1U) +#define AES_ISR_RWEIF_Msk (0x1UL << AES_ISR_RWEIF_Pos) /*!< 0x00000002 */ +#define AES_ISR_RWEIF AES_ISR_RWEIF_Msk /*!< Read or write error Interrupt flag */ +#define AES_ISR_KEIF_Pos (2U) +#define AES_ISR_KEIF_Msk (0x1UL << AES_ISR_KEIF_Pos) /*!< 0x00000004 */ +#define AES_ISR_KEIF AES_ISR_KEIF_Msk /*!< Key error interrupt flag */ +#define AES_ISR_RNGEIF_Pos (3U) +#define AES_ISR_RNGEIF_Msk (0x1UL << AES_ISR_RNGEIF_Pos) /*!< 0x00000008 */ +#define AES_ISR_RNGEIF AES_ISR_RNGEIF_Msk /*!< SAES Rng error interrupt flag */ + +/******************* Bit definition for AES_ICR register ******************/ +#define AES_ICR_CCF_Pos (0U) +#define AES_ICR_CCF_Msk (0x1UL << AES_ICR_CCF_Pos) /*!< 0x00000001 */ +#define AES_ICR_CCF AES_ICR_CCF_Msk /*!< Computation complete flag clear */ +#define AES_ICR_RWEIF_Pos (1U) +#define AES_ICR_RWEIF_Msk (0x1UL << AES_ICR_RWEIF_Pos) /*!< 0x00000002 */ +#define AES_ICR_RWEIF AES_ICR_RWEIF_Msk /*!< Read or write error Interrupt flag clear */ +#define AES_ICR_KEIF_Pos (2U) +#define AES_ICR_KEIF_Msk (0x1UL << AES_ICR_KEIF_Pos) /*!< 0x00000004 */ +#define AES_ICR_KEIF AES_ICR_KEIF_Msk /*!< Key error interrupt flag clear */ +#define AES_ICR_RNGEIF_Pos (3U) +#define AES_ICR_RNGEIF_Msk (0x1UL << AES_ICR_RNGEIF_Pos) /*!< 0x00000008 */ +#define AES_ICR_RNGEIF AES_ICR_RNGEIF_Msk /*!< SAES Rng error interrupt flag clear */ + +/******************************************************************************/ +/* */ +/* Debug MCU */ +/* */ +/******************************************************************************/ +/******************** Bit definition for DBGMCU_IDCODE register *************/ +#define DBGMCU_IDCODE_DEV_ID_Pos (0U) +#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ +#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk +#define DBGMCU_IDCODE_REV_ID_Pos (16U) +#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ +#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk + +/******************** Bit definition for DBGMCU_SCR register *****************/ +#define DBGMCU_SCR_DBG_STOP_Pos (1U) +#define DBGMCU_SCR_DBG_STOP_Msk (0x1UL << DBGMCU_SCR_DBG_STOP_Pos) /*!< 0x00000002 */ +#define DBGMCU_SCR_DBG_STOP DBGMCU_SCR_DBG_STOP_Msk +#define DBGMCU_SCR_DBG_STANDBY_Pos (2U) +#define DBGMCU_SCR_DBG_STANDBY_Msk (0x1UL << DBGMCU_SCR_DBG_STANDBY_Pos) /*!< 0x00000004 */ +#define DBGMCU_SCR_DBG_STANDBY DBGMCU_SCR_DBG_STANDBY_Msk +#define DBGMCU_SCR_DBG_LPMS_Pos (16U) +#define DBGMCU_SCR_DBG_LPMS_Msk (0x7UL << DBGMCU_SCR_DBG_LPMS_Pos) /*!< 0x00070000 */ +#define DBGMCU_SCR_DBG_LPMS DBGMCU_SCR_DBG_LPMS_Msk +#define DBGMCU_SCR_DBG_LPMS_0 (0x1UL << DBGMCU_SCR_DBG_LPMS_Pos) +#define DBGMCU_SCR_DBG_LPMS_1 (0x2UL << DBGMCU_SCR_DBG_LPMS_Pos) +#define DBGMCU_SCR_DBG_LPMS_2 (0x4UL << DBGMCU_SCR_DBG_LPMS_Pos) +#define DBGMCU_SCR_DBG_STOPF_Pos (19U) +#define DBGMCU_SCR_DBG_STOPF_Msk (0x1UL << DBGMCU_SCR_DBG_STOPF_Pos) /*!< 0x00080000 */ +#define DBGMCU_SCR_DBG_STOPF DBGMCU_SCR_DBG_STOPF_Msk +#define DBGMCU_SCR_DBG_SBF_Pos (20U) +#define DBGMCU_SCR_DBG_SBF_Msk (0x1UL << DBGMCU_SCR_DBG_SBF_Pos) /*!< 0x00100000 */ +#define DBGMCU_SCR_DBG_SBF DBGMCU_SCR_DBG_SBF_Msk +#define DBGMCU_SCR_DBG_CS_Pos (24U) +#define DBGMCU_SCR_DBG_CS_Msk (0x1UL << DBGMCU_SCR_DBG_CS_Pos) /*!< 0x01000000 */ +#define DBGMCU_SCR_DBG_CS DBGMCU_SCR_DBG_CS_Msk +#define DBGMCU_SCR_DBG_CDS_Pos (25U) +#define DBGMCU_SCR_DBG_CDS_Msk (0x1UL << DBGMCU_SCR_DBG_CDS_Pos) /*!< 0x02000000 */ +#define DBGMCU_SCR_DBG_CDS DBGMCU_SCR_DBG_CDS_Msk + +/******************** Bit definition for DBGMCU_APB1LFZR register ***********/ +#define DBGMCU_APB1LFZR_DBG_TIM2_STOP_Pos (0U) +#define DBGMCU_APB1LFZR_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_TIM2_STOP_Pos) +#define DBGMCU_APB1LFZR_DBG_TIM2_STOP DBGMCU_APB1LFZR_DBG_TIM2_STOP_Msk +#define DBGMCU_APB1LFZR_DBG_TIM3_STOP_Pos (1U) +#define DBGMCU_APB1LFZR_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_TIM3_STOP_Pos) +#define DBGMCU_APB1LFZR_DBG_TIM3_STOP DBGMCU_APB1LFZR_DBG_TIM3_STOP_Msk +#define DBGMCU_APB1LFZR_DBG_WWDG_STOP_Pos (11U) +#define DBGMCU_APB1LFZR_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_WWDG_STOP_Pos) +#define DBGMCU_APB1LFZR_DBG_WWDG_STOP DBGMCU_APB1LFZR_DBG_WWDG_STOP_Msk +#define DBGMCU_APB1LFZR_DBG_IWDG_STOP_Pos (12U) +#define DBGMCU_APB1LFZR_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_IWDG_STOP_Pos) +#define DBGMCU_APB1LFZR_DBG_IWDG_STOP DBGMCU_APB1LFZR_DBG_IWDG_STOP_Msk +#define DBGMCU_APB1LFZR_DBG_I2C1_STOP_Pos (21U) +#define DBGMCU_APB1LFZR_DBG_I2C1_STOP_Msk (0x1UL << DBGMCU_APB1LFZR_DBG_I2C1_STOP_Pos) +#define DBGMCU_APB1LFZR_DBG_I2C1_STOP DBGMCU_APB1LFZR_DBG_I2C1_STOP_Msk + +/******************** Bit definition for DBGMCU_APB1HFZR register ***********/ +#define DBGMCU_APB1HFZR_DBG_LPTIM2_STOP_Pos (5U) +#define DBGMCU_APB1HFZR_DBG_LPTIM2_STOP_Msk (0x1UL << DBGMCU_APB1HFZR_DBG_LPTIM2_STOP_Pos) +#define DBGMCU_APB1HFZR_DBG_LPTIM2_STOP DBGMCU_APB1HFZR_DBG_LPTIM2_STOP_Msk + +/******************** Bit definition for DBGMCU_APB2FZR register ***********/ +#define DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos (11U) +#define DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos) +#define DBGMCU_APB2FZR_DBG_TIM1_STOP DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk +#define DBGMCU_APB2FZR_DBG_TIM16_STOP_Pos (17U) +#define DBGMCU_APB2FZR_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM16_STOP_Pos) +#define DBGMCU_APB2FZR_DBG_TIM16_STOP DBGMCU_APB2FZR_DBG_TIM16_STOP_Msk +#define DBGMCU_APB2FZR_DBG_TIM17_STOP_Pos (18U) +#define DBGMCU_APB2FZR_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM17_STOP_Pos) +#define DBGMCU_APB2FZR_DBG_TIM17_STOP DBGMCU_APB2FZR_DBG_TIM17_STOP_Msk + +/******************** Bit definition for DBGMCU_APB7FZR register ***********/ +#define DBGMCU_APB7FZR_DBG_I2C3_STOP_Pos (10U) +#define DBGMCU_APB7FZR_DBG_I2C3_STOP_Msk (0x1UL << DBGMCU_APB7FZR_DBG_I2C3_STOP_Pos) +#define DBGMCU_APB7FZR_DBG_I2C3_STOP DBGMCU_APB7FZR_DBG_I2C3_STOP_Msk +#define DBGMCU_APB7FZR_DBG_LPTIM1_STOP_Pos (17U) +#define DBGMCU_APB7FZR_DBG_LPTIM1_STOP_Msk (0x1UL << DBGMCU_APB7FZR_DBG_LPTIM1_STOP_Pos) +#define DBGMCU_APB7FZR_DBG_LPTIM1_STOP DBGMCU_APB7FZR_DBG_LPTIM1_STOP_Msk +#define DBGMCU_APB7FZR_DBG_RTC_STOP_Pos (30U) +#define DBGMCU_APB7FZR_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB7FZR_DBG_RTC_STOP_Pos) +#define DBGMCU_APB7FZR_DBG_RTC_STOP DBGMCU_APB7FZR_DBG_RTC_STOP_Msk + +/******************** Bit definition for DBGMCU_AHB1FZR register ***********/ +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP_Pos (0U) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP_Pos) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP_Msk +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP_Pos (1U) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP_Pos) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP_Msk +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP_Pos (2U) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP_Pos) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP_Msk +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP_Pos (3U) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP_Pos) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP_Msk +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP_Pos (4U) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP_Pos) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP_Msk +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP_Pos (5U) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP_Pos) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP_Msk +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP_Pos (6U) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP_Pos) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP_Msk +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP_Pos (7U) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP_Pos) +#define DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP_Msk + + +/******************************************************************************/ +/* */ +/* DMA Controller (DMA) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for DMA_SECCFGR register ****************/ +#define DMA_SECCFGR_SEC0_Pos (0U) +#define DMA_SECCFGR_SEC0_Msk (0x1UL << DMA_SECCFGR_SEC0_Pos) /*!< 0x00000001 */ +#define DMA_SECCFGR_SEC0 DMA_SECCFGR_SEC0_Msk /*!< Secure State of Channel 0 */ +#define DMA_SECCFGR_SEC1_Pos (1U) +#define DMA_SECCFGR_SEC1_Msk (0x1UL << DMA_SECCFGR_SEC1_Pos) /*!< 0x00000002 */ +#define DMA_SECCFGR_SEC1 DMA_SECCFGR_SEC1_Msk /*!< Secure State of Channel 1 */ +#define DMA_SECCFGR_SEC2_Pos (2U) +#define DMA_SECCFGR_SEC2_Msk (0x1UL << DMA_SECCFGR_SEC2_Pos) /*!< 0x00000004 */ +#define DMA_SECCFGR_SEC2 DMA_SECCFGR_SEC2_Msk /*!< Secure State of Channel 2 */ +#define DMA_SECCFGR_SEC3_Pos (3U) +#define DMA_SECCFGR_SEC3_Msk (0x1UL << DMA_SECCFGR_SEC3_Pos) /*!< 0x00000008 */ +#define DMA_SECCFGR_SEC3 DMA_SECCFGR_SEC3_Msk /*!< Secure State of Channel 3 */ +#define DMA_SECCFGR_SEC4_Pos (4U) +#define DMA_SECCFGR_SEC4_Msk (0x1UL << DMA_SECCFGR_SEC4_Pos) /*!< 0x00000010 */ +#define DMA_SECCFGR_SEC4 DMA_SECCFGR_SEC4_Msk /*!< Secure State of Channel 4 */ +#define DMA_SECCFGR_SEC5_Pos (5U) +#define DMA_SECCFGR_SEC5_Msk (0x1UL << DMA_SECCFGR_SEC5_Pos) /*!< 0x00000020 */ +#define DMA_SECCFGR_SEC5 DMA_SECCFGR_SEC5_Msk /*!< Secure State of Channel 5 */ +#define DMA_SECCFGR_SEC6_Pos (6U) +#define DMA_SECCFGR_SEC6_Msk (0x1UL << DMA_SECCFGR_SEC6_Pos) /*!< 0x00000040 */ +#define DMA_SECCFGR_SEC6 DMA_SECCFGR_SEC6_Msk /*!< Secure State of Channel 6 */ +#define DMA_SECCFGR_SEC7_Pos (7U) +#define DMA_SECCFGR_SEC7_Msk (0x1UL << DMA_SECCFGR_SEC7_Pos) /*!< 0x00000080 */ +#define DMA_SECCFGR_SEC7 DMA_SECCFGR_SEC7_Msk /*!< Secure State of Channel 7 */ + +/******************* Bit definition for DMA_PRIVCFGR register ****************/ +#define DMA_PRIVCFGR_PRIV0_Pos (0U) +#define DMA_PRIVCFGR_PRIV0_Msk (0x1UL << DMA_PRIVCFGR_PRIV0_Pos) /*!< 0x00000001 */ +#define DMA_PRIVCFGR_PRIV0 DMA_PRIVCFGR_PRIV0_Msk /*!< Privileged State of Channel 0 */ +#define DMA_PRIVCFGR_PRIV1_Pos (1U) +#define DMA_PRIVCFGR_PRIV1_Msk (0x1UL << DMA_PRIVCFGR_PRIV1_Pos) /*!< 0x00000002 */ +#define DMA_PRIVCFGR_PRIV1 DMA_PRIVCFGR_PRIV1_Msk /*!< Privileged State of Channel 1 */ +#define DMA_PRIVCFGR_PRIV2_Pos (2U) +#define DMA_PRIVCFGR_PRIV2_Msk (0x1UL << DMA_PRIVCFGR_PRIV2_Pos) /*!< 0x00000004 */ +#define DMA_PRIVCFGR_PRIV2 DMA_PRIVCFGR_PRIV2_Msk /*!< Privileged State of Channel 2 */ +#define DMA_PRIVCFGR_PRIV3_Pos (3U) +#define DMA_PRIVCFGR_PRIV3_Msk (0x1UL << DMA_PRIVCFGR_PRIV3_Pos) /*!< 0x00000008 */ +#define DMA_PRIVCFGR_PRIV3 DMA_PRIVCFGR_PRIV3_Msk /*!< Privileged State of Channel 3 */ +#define DMA_PRIVCFGR_PRIV4_Pos (4U) +#define DMA_PRIVCFGR_PRIV4_Msk (0x1UL << DMA_PRIVCFGR_PRIV4_Pos) /*!< 0x00000010 */ +#define DMA_PRIVCFGR_PRIV4 DMA_PRIVCFGR_PRIV4_Msk /*!< Privileged State of Channel 4 */ +#define DMA_PRIVCFGR_PRIV5_Pos (5U) +#define DMA_PRIVCFGR_PRIV5_Msk (0x1UL << DMA_PRIVCFGR_PRIV5_Pos) /*!< 0x00000020 */ +#define DMA_PRIVCFGR_PRIV5 DMA_PRIVCFGR_PRIV5_Msk /*!< Privileged State of Channel 5 */ +#define DMA_PRIVCFGR_PRIV6_Pos (6U) +#define DMA_PRIVCFGR_PRIV6_Msk (0x1UL << DMA_PRIVCFGR_PRIV6_Pos) /*!< 0x00000040 */ +#define DMA_PRIVCFGR_PRIV6 DMA_PRIVCFGR_PRIV6_Msk /*!< Privileged State of Channel 6 */ +#define DMA_PRIVCFGR_PRIV7_Pos (7U) +#define DMA_PRIVCFGR_PRIV7_Msk (0x1UL << DMA_PRIVCFGR_PRIV7_Pos) /*!< 0x00000080 */ +#define DMA_PRIVCFGR_PRIV7 DMA_PRIVCFGR_PRIV7_Msk /*!< Privileged State of Channel 7 */ + +/******************* Bit definition for DMA_RCFGLOCKR register ****************/ +#define DMA_RCFGLOCKR_LOCK0_Pos (0U) +#define DMA_RCFGLOCKR_LOCK0_Msk (0x1UL << DMA_RCFGLOCKR_LOCK0_Pos) /*!< 0x00000001 */ +#define DMA_RCFGLOCKR_LOCK0 DMA_RCFGLOCKR_LOCK0_Msk /*!< Privileged and Secure State Lock of Channel 0 */ +#define DMA_RCFGLOCKR_LOCK1_Pos (1U) +#define DMA_RCFGLOCKR_LOCK1_Msk (0x1UL << DMA_RCFGLOCKR_LOCK1_Pos) /*!< 0x00000002 */ +#define DMA_RCFGLOCKR_LOCK1 DMA_RCFGLOCKR_LOCK1_Msk /*!< Privileged and Secure State Lock of Channel 1 */ +#define DMA_RCFGLOCKR_LOCK2_Pos (2U) +#define DMA_RCFGLOCKR_LOCK2_Msk (0x1UL << DMA_RCFGLOCKR_LOCK2_Pos) /*!< 0x00000004 */ +#define DMA_RCFGLOCKR_LOCK2 DMA_RCFGLOCKR_LOCK2_Msk /*!< Privileged and Secure State Lock of Channel 2 */ +#define DMA_RCFGLOCKR_LOCK3_Pos (3U) +#define DMA_RCFGLOCKR_LOCK3_Msk (0x1UL << DMA_RCFGLOCKR_LOCK3_Pos) /*!< 0x00000008 */ +#define DMA_RCFGLOCKR_LOCK3 DMA_RCFGLOCKR_LOCK3_Msk /*!< Privileged and Secure State Lock of Channel 3 */ +#define DMA_RCFGLOCKR_LOCK4_Pos (4U) +#define DMA_RCFGLOCKR_LOCK4_Msk (0x1UL << DMA_RCFGLOCKR_LOCK4_Pos) /*!< 0x00000010 */ +#define DMA_RCFGLOCKR_LOCK4 DMA_RCFGLOCKR_LOCK4_Msk /*!< Privileged and Secure State Lock of Channel 4 */ +#define DMA_RCFGLOCKR_LOCK5_Pos (5U) +#define DMA_RCFGLOCKR_LOCK5_Msk (0x1UL << DMA_RCFGLOCKR_LOCK5_Pos) /*!< 0x00000020 */ +#define DMA_RCFGLOCKR_LOCK5 DMA_RCFGLOCKR_LOCK5_Msk /*!< Privileged and Secure State Lock of Channel 5 */ +#define DMA_RCFGLOCKR_LOCK6_Pos (6U) +#define DMA_RCFGLOCKR_LOCK6_Msk (0x1UL << DMA_RCFGLOCKR_LOCK6_Pos) /*!< 0x00000040 */ +#define DMA_RCFGLOCKR_LOCK6 DMA_RCFGLOCKR_LOCK6_Msk /*!< Privileged and Secure State Lock of Channel 6 */ +#define DMA_RCFGLOCKR_LOCK7_Pos (7U) +#define DMA_RCFGLOCKR_LOCK7_Msk (0x1UL << DMA_RCFGLOCKR_LOCK7_Pos) /*!< 0x00000080 */ +#define DMA_RCFGLOCKR_LOCK7 DMA_RCFGLOCKR_LOCK7_Msk /*!< Privileged and Secure State Lock of Channel 7 */ + +/******************* Bit definition for DMA_MISR register ****************/ +#define DMA_MISR_MIS0_Pos (0U) +#define DMA_MISR_MIS0_Msk (0x1UL << DMA_MISR_MIS0_Pos) /*!< 0x00000001 */ +#define DMA_MISR_MIS0 DMA_MISR_MIS0_Msk /*!< Masked Interrupt State of Non-Secure Channel 0 */ +#define DMA_MISR_MIS1_Pos (1U) +#define DMA_MISR_MIS1_Msk (0x1UL << DMA_MISR_MIS1_Pos) /*!< 0x00000002 */ +#define DMA_MISR_MIS1 DMA_MISR_MIS1_Msk /*!< Masked Interrupt State of Non-Secure Channel 1 */ +#define DMA_MISR_MIS2_Pos (2U) +#define DMA_MISR_MIS2_Msk (0x1UL << DMA_MISR_MIS2_Pos) /*!< 0x00000004 */ +#define DMA_MISR_MIS2 DMA_MISR_MIS2_Msk /*!< Masked Interrupt State of Non-Secure Channel 2 */ +#define DMA_MISR_MIS3_Pos (3U) +#define DMA_MISR_MIS3_Msk (0x1UL << DMA_MISR_MIS3_Pos) /*!< 0x00000008 */ +#define DMA_MISR_MIS3 DMA_MISR_MIS3_Msk /*!< Masked Interrupt State of Non-Secure Channel 3 */ +#define DMA_MISR_MIS4_Pos (4U) +#define DMA_MISR_MIS4_Msk (0x1UL << DMA_MISR_MIS4_Pos) /*!< 0x00000010 */ +#define DMA_MISR_MIS4 DMA_MISR_MIS4_Msk /*!< Masked Interrupt State of Non-Secure Channel 4 */ +#define DMA_MISR_MIS5_Pos (5U) +#define DMA_MISR_MIS5_Msk (0x1UL << DMA_MISR_MIS5_Pos) /*!< 0x00000020 */ +#define DMA_MISR_MIS5 DMA_MISR_MIS5_Msk /*!< Masked Interrupt State of Non-Secure Channel 5 */ +#define DMA_MISR_MIS6_Pos (6U) +#define DMA_MISR_MIS6_Msk (0x1UL << DMA_MISR_MIS6_Pos) /*!< 0x00000040 */ +#define DMA_MISR_MIS6 DMA_MISR_MIS6_Msk /*!< Masked Interrupt State of Non-Secure Channel 6 */ +#define DMA_MISR_MIS7_Pos (7U) +#define DMA_MISR_MIS7_Msk (0x1UL << DMA_MISR_MIS7_Pos) /*!< 0x00000080 */ +#define DMA_MISR_MIS7 DMA_MISR_MIS7_Msk /*!< Masked Interrupt State of Non-Secure Channel 7 */ + +/******************* Bit definition for DMA_SMISR register ****************/ +#define DMA_SMISR_MIS0_Pos (0U) +#define DMA_SMISR_MIS0_Msk (0x1UL << DMA_SMISR_MIS0_Pos) /*!< 0x00000001 */ +#define DMA_SMISR_MIS0 DMA_SMISR_MIS0_Msk /*!< Masked Interrupt State of Secure Channel 0 */ +#define DMA_SMISR_MIS1_Pos (1U) +#define DMA_SMISR_MIS1_Msk (0x1UL << DMA_SMISR_MIS1_Pos) /*!< 0x00000002 */ +#define DMA_SMISR_MIS1 DMA_SMISR_MIS1_Msk /*!< Masked Interrupt State of Secure Channel 1 */ +#define DMA_SMISR_MIS2_Pos (2U) +#define DMA_SMISR_MIS2_Msk (0x1UL << DMA_SMISR_MIS2_Pos) /*!< 0x00000004 */ +#define DMA_SMISR_MIS2 DMA_SMISR_MIS2_Msk /*!< Masked Interrupt State of Secure Channel 2 */ +#define DMA_SMISR_MIS3_Pos (3U) +#define DMA_SMISR_MIS3_Msk (0x1UL << DMA_SMISR_MIS3_Pos) /*!< 0x00000008 */ +#define DMA_SMISR_MIS3 DMA_SMISR_MIS3_Msk /*!< Masked Interrupt State of Secure Channel 3 */ +#define DMA_SMISR_MIS4_Pos (4U) +#define DMA_SMISR_MIS4_Msk (0x1UL << DMA_SMISR_MIS4_Pos) /*!< 0x00000010 */ +#define DMA_SMISR_MIS4 DMA_SMISR_MIS4_Msk /*!< Masked Interrupt State of Secure Channel 4 */ +#define DMA_SMISR_MIS5_Pos (5U) +#define DMA_SMISR_MIS5_Msk (0x1UL << DMA_SMISR_MIS5_Pos) /*!< 0x00000020 */ +#define DMA_SMISR_MIS5 DMA_SMISR_MIS5_Msk /*!< Masked Interrupt State of Secure Channel 5 */ +#define DMA_SMISR_MIS6_Pos (6U) +#define DMA_SMISR_MIS6_Msk (0x1UL << DMA_SMISR_MIS6_Pos) /*!< 0x00000040 */ +#define DMA_SMISR_MIS6 DMA_SMISR_MIS6_Msk /*!< Masked Interrupt State of Secure Channel 6 */ +#define DMA_SMISR_MIS7_Pos (7U) +#define DMA_SMISR_MIS7_Msk (0x1UL << DMA_SMISR_MIS7_Pos) /*!< 0x00000080 */ +#define DMA_SMISR_MIS7 DMA_SMISR_MIS7_Msk /*!< Masked Interrupt State of Secure Channel 7 */ + +/******************* Bit definition for DMA_CLBAR register ****************/ +#define DMA_CLBAR_LBA_Pos (16U) +#define DMA_CLBAR_LBA_Msk (0xFFFFUL << DMA_CLBAR_LBA_Pos) /*!< 0xFFFF0000 */ +#define DMA_CLBAR_LBA DMA_CLBAR_LBA_Msk /*!< Linked-list Base Address of DMA channel x */ + +/******************* Bit definition for DMA_CFCR register *******************/ +#define DMA_CFCR_TCF_Pos (8U) +#define DMA_CFCR_TCF_Msk (0x1UL << DMA_CFCR_TCF_Pos) /*!< 0x00000100 */ +#define DMA_CFCR_TCF DMA_CFCR_TCF_Msk /*!< Transfer complete flag clear */ +#define DMA_CFCR_HTF_Pos (9U) +#define DMA_CFCR_HTF_Msk (0x1UL << DMA_CFCR_HTF_Pos) /*!< 0x00000200 */ +#define DMA_CFCR_HTF DMA_CFCR_HTF_Msk /*!< Half transfer complete flag clear */ +#define DMA_CFCR_DTEF_Pos (10U) +#define DMA_CFCR_DTEF_Msk (0x1UL << DMA_CFCR_DTEF_Pos) /*!< 0x00000400 */ +#define DMA_CFCR_DTEF DMA_CFCR_DTEF_Msk /*!< Data transfer error flag clear */ +#define DMA_CFCR_ULEF_Pos (11U) +#define DMA_CFCR_ULEF_Msk (0x1UL << DMA_CFCR_ULEF_Pos) /*!< 0x00000800 */ +#define DMA_CFCR_ULEF DMA_CFCR_ULEF_Msk /*!< Update linked-list item error flag clear */ +#define DMA_CFCR_USEF_Pos (12U) +#define DMA_CFCR_USEF_Msk (0x1UL << DMA_CFCR_USEF_Pos) /*!< 0x00001000 */ +#define DMA_CFCR_USEF DMA_CFCR_USEF_Msk /*!< User setting error flag clear */ +#define DMA_CFCR_SUSPF_Pos (13U) +#define DMA_CFCR_SUSPF_Msk (0x1UL << DMA_CFCR_SUSPF_Pos) /*!< 0x00002000 */ +#define DMA_CFCR_SUSPF DMA_CFCR_SUSPF_Msk /*!< Completed suspension flag clear */ +#define DMA_CFCR_TOF_Pos (14U) +#define DMA_CFCR_TOF_Msk (0x1UL << DMA_CFCR_TOF_Pos) /*!< 0x00004000 */ +#define DMA_CFCR_TOF DMA_CFCR_TOF_Msk /*!< Trigger overrun flag clear */ + +/******************* Bit definition for DMA_CSR register *******************/ +#define DMA_CSR_IDLEF_Pos (0U) +#define DMA_CSR_IDLEF_Msk (0x1UL << DMA_CSR_IDLEF_Pos) /*!< 0x00000001 */ +#define DMA_CSR_IDLEF DMA_CSR_IDLEF_Msk /*!< Idle flag */ +#define DMA_CSR_TCF_Pos (8U) +#define DMA_CSR_TCF_Msk (0x1UL << DMA_CSR_TCF_Pos) /*!< 0x00000100 */ +#define DMA_CSR_TCF DMA_CSR_TCF_Msk /*!< Transfer complete flag */ +#define DMA_CSR_HTF_Pos (9U) +#define DMA_CSR_HTF_Msk (0x1UL << DMA_CSR_HTF_Pos) /*!< 0x00000200 */ +#define DMA_CSR_HTF DMA_CSR_HTF_Msk /*!< Half transfer complete flag */ +#define DMA_CSR_DTEF_Pos (10U) +#define DMA_CSR_DTEF_Msk (0x1UL << DMA_CSR_DTEF_Pos) /*!< 0x00000400 */ +#define DMA_CSR_DTEF DMA_CSR_DTEF_Msk /*!< Data transfer error flag */ +#define DMA_CSR_ULEF_Pos (11U) +#define DMA_CSR_ULEF_Msk (0x1UL << DMA_CSR_ULEF_Pos) /*!< 0x00000800 */ +#define DMA_CSR_ULEF DMA_CSR_ULEF_Msk /*!< Update linked-list item error flag */ +#define DMA_CSR_USEF_Pos (12U) +#define DMA_CSR_USEF_Msk (0x1UL << DMA_CSR_USEF_Pos) /*!< 0x00001000 */ +#define DMA_CSR_USEF DMA_CSR_USEF_Msk /*!< User setting error flag */ +#define DMA_CSR_SUSPF_Pos (13U) +#define DMA_CSR_SUSPF_Msk (0x1UL << DMA_CSR_SUSPF_Pos) /*!< 0x00002000 */ +#define DMA_CSR_SUSPF DMA_CSR_SUSPF_Msk /*!< User setting error flag */ +#define DMA_CSR_TOF_Pos (14U) +#define DMA_CSR_TOF_Msk (0x1UL << DMA_CSR_TOF_Pos) /*!< 0x00004000 */ +#define DMA_CSR_TOF DMA_CSR_TOF_Msk /*!< Trigger overrun event flag */ +#define DMA_CSR_FIFOL_Pos (16U) +#define DMA_CSR_FIFOL_Msk (0xFFUL << DMA_CSR_FIFOL_Pos) /*!< 0x00FF0000 */ +#define DMA_CSR_FIFOL DMA_CSR_FIFOL_Msk /*!< Monitored FIFO level in bytes */ + +/******************* Bit definition for DMA_CCR register ********************/ +#define DMA_CCR_EN_Pos (0U) +#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */ +#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ +#define DMA_CCR_RESET_Pos (1U) +#define DMA_CCR_RESET_Msk (0x1UL << DMA_CCR_RESET_Pos) /*!< 0x00000002 */ +#define DMA_CCR_RESET DMA_CCR_RESET_Msk /*!< Channel reset */ +#define DMA_CCR_SUSP_Pos (2U) +#define DMA_CCR_SUSP_Msk (0x1UL << DMA_CCR_SUSP_Pos) /*!< 0x00000004 */ +#define DMA_CCR_SUSP DMA_CCR_SUSP_Msk /*!< Channel suspend */ +#define DMA_CCR_TCIE_Pos (8U) +#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000100 */ +#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ +#define DMA_CCR_HTIE_Pos (9U) +#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000200 */ +#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half transfer complete interrupt enable */ +#define DMA_CCR_DTEIE_Pos (10U) +#define DMA_CCR_DTEIE_Msk (0x1UL << DMA_CCR_DTEIE_Pos) /*!< 0x00000400 */ +#define DMA_CCR_DTEIE DMA_CCR_DTEIE_Msk /*!< Data transfer error interrupt enable */ +#define DMA_CCR_ULEIE_Pos (11U) +#define DMA_CCR_ULEIE_Msk (0x1UL << DMA_CCR_ULEIE_Pos) /*!< 0x00000800 */ +#define DMA_CCR_ULEIE DMA_CCR_ULEIE_Msk /*!< Update linked-list item error interrupt enable */ +#define DMA_CCR_USEIE_Pos (12U) +#define DMA_CCR_USEIE_Msk (0x1UL << DMA_CCR_USEIE_Pos) /*!< 0x00001000 */ +#define DMA_CCR_USEIE DMA_CCR_USEIE_Msk /*!< User setting error interrupt enable */ +#define DMA_CCR_SUSPIE_Pos (13U) +#define DMA_CCR_SUSPIE_Msk (0x1UL << DMA_CCR_SUSPIE_Pos) /*!< 0x00002000 */ +#define DMA_CCR_SUSPIE DMA_CCR_SUSPIE_Msk /*!< Completed suspension interrupt enable */ +#define DMA_CCR_TOIE_Pos (14U) +#define DMA_CCR_TOIE_Msk (0x1UL << DMA_CCR_TOIE_Pos) /*!< 0x00004000 */ +#define DMA_CCR_TOIE DMA_CCR_TOIE_Msk /*!< Trigger overrun interrupt enable */ +#define DMA_CCR_LSM_Pos (16U) +#define DMA_CCR_LSM_Msk (0x1UL << DMA_CCR_LSM_Pos) /*!< 0x00010000 */ +#define DMA_CCR_LSM DMA_CCR_LSM_Msk /*!< Link step mode */ +#define DMA_CCR_LAP_Pos (17U) +#define DMA_CCR_LAP_Msk (0x1UL << DMA_CCR_LAP_Pos) /*!< 0x00020000 */ +#define DMA_CCR_LAP DMA_CCR_LAP_Msk /*!< Linked-list allocated port */ +#define DMA_CCR_PRIO_Pos (22U) +#define DMA_CCR_PRIO_Msk (0x3UL << DMA_CCR_PRIO_Pos) /*!< 0x00C00000 */ +#define DMA_CCR_PRIO DMA_CCR_PRIO_Msk /*!< Priority level */ +#define DMA_CCR_PRIO_0 (0x1UL << DMA_CCR_PRIO_Pos) /*!< 0x00400000 */ +#define DMA_CCR_PRIO_1 (0x2UL << DMA_CCR_PRIO_Pos) /*!< 0x00800000 */ + +/******************* Bit definition for DMA_CTR1 register *******************/ +#define DMA_CTR1_SDW_LOG2_Pos (0U) +#define DMA_CTR1_SDW_LOG2_Msk (0x3UL << DMA_CTR1_SDW_LOG2_Pos) /*!< 0x00000003 */ +#define DMA_CTR1_SDW_LOG2 DMA_CTR1_SDW_LOG2_Msk /*!< Binary logarithm of the source data width of a burst */ +#define DMA_CTR1_SDW_LOG2_0 (0x1UL << DMA_CTR1_SDW_LOG2_Pos) /*!< Bit 0 */ +#define DMA_CTR1_SDW_LOG2_1 (0x2UL << DMA_CTR1_SDW_LOG2_Pos) /*!< Bit 1 */ +#define DMA_CTR1_SINC_Pos (3U) +#define DMA_CTR1_SINC_Msk (0x1UL << DMA_CTR1_SINC_Pos) /*!< 0x00000008 */ +#define DMA_CTR1_SINC DMA_CTR1_SINC_Msk /*!< Source incrementing burst */ +#define DMA_CTR1_SBL_1_Pos (4U) +#define DMA_CTR1_SBL_1_Msk (0x3FUL << DMA_CTR1_SBL_1_Pos) /*!< 0x000003F0 */ +#define DMA_CTR1_SBL_1 DMA_CTR1_SBL_1_Msk /*!< Source burst length minus 1 */ +#define DMA_CTR1_PAM_Pos (11U) +#define DMA_CTR1_PAM_Msk (0x3UL << DMA_CTR1_PAM_Pos) /*!< 0x0001800 */ +#define DMA_CTR1_PAM DMA_CTR1_PAM_Msk /*!< Padding / alignment mode */ +#define DMA_CTR1_PAM_0 (0x1UL << DMA_CTR1_PAM_Pos) /*!< Bit 0 */ +#define DMA_CTR1_PAM_1 (0x2UL << DMA_CTR1_PAM_Pos) /*!< Bit 1 */ +#define DMA_CTR1_SBX_Pos (13U) +#define DMA_CTR1_SBX_Msk (0x1UL << DMA_CTR1_SBX_Pos) /*!< 0x00002000 */ +#define DMA_CTR1_SBX DMA_CTR1_SBX_Msk /*!< Source byte exchange within the unaligned half-word of each source word */ +#define DMA_CTR1_SAP_Pos (14U) +#define DMA_CTR1_SAP_Msk (0x1UL << DMA_CTR1_SAP_Pos) /*!< 0x00004000 */ +#define DMA_CTR1_SAP DMA_CTR1_SAP_Msk /*!< Source allocated port */ +#define DMA_CTR1_SSEC_Pos (15U) +#define DMA_CTR1_SSEC_Msk (0x1UL << DMA_CTR1_SSEC_Pos) /*!< 0x00008000 */ +#define DMA_CTR1_SSEC DMA_CTR1_SSEC_Msk /*!< Security attribute of the DMA transfer from the source */ +#define DMA_CTR1_DDW_LOG2_Pos (16U) +#define DMA_CTR1_DDW_LOG2_Msk (0x3UL << DMA_CTR1_DDW_LOG2_Pos) /*!< 0x00030000 */ +#define DMA_CTR1_DDW_LOG2 DMA_CTR1_DDW_LOG2_Msk /*!< Binary logarithm of the destination data width of a burst */ +#define DMA_CTR1_DDW_LOG2_0 (0x1UL << DMA_CTR1_DDW_LOG2_Pos) /*!< Bit 0 */ +#define DMA_CTR1_DDW_LOG2_1 (0x2UL << DMA_CTR1_DDW_LOG2_Pos) /*!< Bit 1 */ +#define DMA_CTR1_DINC_Pos (19U) +#define DMA_CTR1_DINC_Msk (0x1UL << DMA_CTR1_DINC_Pos) /*!< 0x00080000 */ +#define DMA_CTR1_DINC DMA_CTR1_DINC_Msk /*!< Destination incrementing burst */ +#define DMA_CTR1_DBL_1_Pos (20U) +#define DMA_CTR1_DBL_1_Msk (0x3FUL << DMA_CTR1_DBL_1_Pos) /*!< 0x03F00000 */ +#define DMA_CTR1_DBL_1 DMA_CTR1_DBL_1_Msk /*!< Destination burst length minus 1 */ +#define DMA_CTR1_DBX_Pos (26U) +#define DMA_CTR1_DBX_Msk (0x1UL << DMA_CTR1_DBX_Pos) /*!< 0x04000000 */ +#define DMA_CTR1_DBX DMA_CTR1_DBX_Msk /*!< Destination byte exchange */ +#define DMA_CTR1_DHX_Pos (27U) +#define DMA_CTR1_DHX_Msk (0x1UL << DMA_CTR1_DHX_Pos) /*!< 0x08000000 */ +#define DMA_CTR1_DHX DMA_CTR1_DHX_Msk /*!< Destination half-word exchange */ +#define DMA_CTR1_DAP_Pos (30U) +#define DMA_CTR1_DAP_Msk (0x1UL << DMA_CTR1_DAP_Pos) /*!< 0x40000000 */ +#define DMA_CTR1_DAP DMA_CTR1_DAP_Msk /*!< Destination allocated port */ +#define DMA_CTR1_DSEC_Pos (31U) +#define DMA_CTR1_DSEC_Msk (0x1UL << DMA_CTR1_DSEC_Pos) /*!< 0x80000000 */ +#define DMA_CTR1_DSEC DMA_CTR1_DSEC_Msk /*!< Security attribute of the DMA transfer from the destination */ + +/****************** Bit definition for DMA_CTR2 register *******************/ +#define DMA_CTR2_REQSEL_Pos (0U) +#define DMA_CTR2_REQSEL_Msk (0x3FUL << DMA_CTR2_REQSEL_Pos) /*!< 0x0000003F */ +#define DMA_CTR2_REQSEL DMA_CTR2_REQSEL_Msk /*!< DMA hardware request selection */ +#define DMA_CTR2_SWREQ_Pos (9U) +#define DMA_CTR2_SWREQ_Msk (0x1UL << DMA_CTR2_SWREQ_Pos) /*!< 0x00000100 */ +#define DMA_CTR2_SWREQ DMA_CTR2_SWREQ_Msk /*!< Software request */ +#define DMA_CTR2_DREQ_Pos (10U) +#define DMA_CTR2_DREQ_Msk (0x1UL << DMA_CTR2_DREQ_Pos) /*!< 0x00000100 */ +#define DMA_CTR2_DREQ DMA_CTR2_DREQ_Msk /*!< Destination hardware request */ +#define DMA_CTR2_BREQ_Pos (11U) +#define DMA_CTR2_BREQ_Msk (0x1UL << DMA_CTR2_BREQ_Pos) /*!< 0x00000200 */ +#define DMA_CTR2_BREQ DMA_CTR2_BREQ_Msk /*!< Block hardware request */ +#define DMA_CTR2_TRIGM_Pos (14U) +#define DMA_CTR2_TRIGM_Msk (0x3UL << DMA_CTR2_TRIGM_Pos) /*!< 0x0000C000 */ +#define DMA_CTR2_TRIGM DMA_CTR2_TRIGM_Msk /*!< Trigger mode */ +#define DMA_CTR2_TRIGM_0 (0x1UL << DMA_CTR2_TRIGM_Pos) /*!< Bit 0 */ +#define DMA_CTR2_TRIGM_1 (0x2UL << DMA_CTR2_TRIGM_Pos) /*!< Bit 1 */ +#define DMA_CTR2_TRIGSEL_Pos (16U) +#define DMA_CTR2_TRIGSEL_Msk (0x1FUL << DMA_CTR2_TRIGSEL_Pos) /*!< 0x001F0000 */ +#define DMA_CTR2_TRIGSEL DMA_CTR2_TRIGSEL_Msk /*!< Trigger event input selection */ +#define DMA_CTR2_TRIGPOL_Pos (24U) +#define DMA_CTR2_TRIGPOL_Msk (0x3UL << DMA_CTR2_TRIGPOL_Pos) /*!< 0x03000000 */ +#define DMA_CTR2_TRIGPOL DMA_CTR2_TRIGPOL_Msk /*!< Trigger event polarity */ +#define DMA_CTR2_TRIGPOL_0 (0x1UL << DMA_CTR2_TRIGPOL_Pos) /*!< Bit 0 */ +#define DMA_CTR2_TRIGPOL_1 (0x2UL << DMA_CTR2_TRIGPOL_Pos) /*!< Bit 1 */ +#define DMA_CTR2_TCEM_Pos (30U) +#define DMA_CTR2_TCEM_Msk (0x3UL << DMA_CTR2_TCEM_Pos) /*!< 0xC0000000 */ +#define DMA_CTR2_TCEM DMA_CTR2_TCEM_Msk /*!< Transfer complete event mode */ +#define DMA_CTR2_TCEM_0 (0x1UL << DMA_CTR2_TCEM_Pos) /*!< Bit 0 */ +#define DMA_CTR2_TCEM_1 (0x2UL << DMA_CTR2_TCEM_Pos) /*!< Bit 1 */ + +/****************** Bit definition for DMA_CBR1 register *******************/ +#define DMA_CBR1_BNDT_Pos (0U) +#define DMA_CBR1_BNDT_Msk (0xFFFFUL << DMA_CBR1_BNDT_Pos) /*!< 0x0000FFFF */ +#define DMA_CBR1_BNDT DMA_CBR1_BNDT_Msk /*!< Block number of data bytes to transfer from the source */ + +/****************** Bit definition for DMA_CSAR register ********************/ +#define DMA_CSAR_SA_Pos (0U) +#define DMA_CSAR_SA_Msk (0xFFFFFFFFUL << DMA_CSAR_SA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CSAR_SA DMA_CSAR_SA_Msk /*!< Source Address */ + +/****************** Bit definition for DMA_CDAR register *******************/ +#define DMA_CDAR_DA_Pos (0U) +#define DMA_CDAR_DA_Msk (0xFFFFFFFFUL << DMA_CDAR_DA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CDAR_DA DMA_CDAR_DA_Msk /*!< Destination address */ + +/****************** Bit definition for DMA_CLLR register *******************/ +#define DMA_CLLR_LA_Pos (2U) +#define DMA_CLLR_LA_Msk (0x3FFFUL << DMA_CLLR_LA_Pos) /*!< 0x0000FFFC */ +#define DMA_CLLR_LA DMA_CLLR_LA_Msk /*!< Pointer to the next linked-list data structure */ +#define DMA_CLLR_ULL_Pos (16U) +#define DMA_CLLR_ULL_Msk (0x1UL << DMA_CLLR_ULL_Pos) /*!< 0x00010000 */ +#define DMA_CLLR_ULL DMA_CLLR_ULL_Msk /*!< Update link address register from memory */ +#define DMA_CLLR_UDA_Pos (27U) +#define DMA_CLLR_UDA_Msk (0x1UL << DMA_CLLR_UDA_Pos) /*!< 0x08000000 */ +#define DMA_CLLR_UDA DMA_CLLR_UDA_Msk /*!< Update destination address register from SRAM */ +#define DMA_CLLR_USA_Pos (28U) +#define DMA_CLLR_USA_Msk (0x1UL << DMA_CLLR_USA_Pos) /*!< 0x10000000 */ +#define DMA_CLLR_USA DMA_CLLR_USA_Msk /*!< Update source address register from SRAM */ +#define DMA_CLLR_UB1_Pos (29U) +#define DMA_CLLR_UB1_Msk (0x1UL << DMA_CLLR_UB1_Pos) /*!< 0x20000000 */ +#define DMA_CLLR_UB1 DMA_CLLR_UB1_Msk /*!< Update block register 1 from SRAM */ +#define DMA_CLLR_UT2_Pos (30U) +#define DMA_CLLR_UT2_Msk (0x1UL << DMA_CLLR_UT2_Pos) /*!< 0x40000000 */ +#define DMA_CLLR_UT2 DMA_CLLR_UT2_Msk /*!< Update transfer register 2 from SRAM */ +#define DMA_CLLR_UT1_Pos (31U) +#define DMA_CLLR_UT1_Msk (0x1UL << DMA_CLLR_UT1_Pos) /*!< 0x80000000 */ +#define DMA_CLLR_UT1 DMA_CLLR_UT1_Msk /*!< Update transfer register 1 from SRAM */ + +/******************************************************************************/ +/* */ +/* External Interrupt/Event Controller */ +/* */ +/******************************************************************************/ +/****************** Bit definition for EXTI_RTSR1 register ******************/ +#define EXTI_RTSR1_RT0_Pos (0U) +#define EXTI_RTSR1_RT0_Msk (0x1UL << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */ +#define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger configuration for input line 0 */ +#define EXTI_RTSR1_RT1_Pos (1U) +#define EXTI_RTSR1_RT1_Msk (0x1UL << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */ +#define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger configuration for input line 1 */ +#define EXTI_RTSR1_RT2_Pos (2U) +#define EXTI_RTSR1_RT2_Msk (0x1UL << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */ +#define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger configuration for input line 2 */ +#define EXTI_RTSR1_RT3_Pos (3U) +#define EXTI_RTSR1_RT3_Msk (0x1UL << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */ +#define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger configuration for input line 3 */ +#define EXTI_RTSR1_RT4_Pos (4U) +#define EXTI_RTSR1_RT4_Msk (0x1UL << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */ +#define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger configuration for input line 4 */ +#define EXTI_RTSR1_RT5_Pos (5U) +#define EXTI_RTSR1_RT5_Msk (0x1UL << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */ +#define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger configuration for input line 5 */ +#define EXTI_RTSR1_RT6_Pos (6U) +#define EXTI_RTSR1_RT6_Msk (0x1UL << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */ +#define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger configuration for input line 6 */ +#define EXTI_RTSR1_RT7_Pos (7U) +#define EXTI_RTSR1_RT7_Msk (0x1UL << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */ +#define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger configuration for input line 7 */ +#define EXTI_RTSR1_RT8_Pos (8U) +#define EXTI_RTSR1_RT8_Msk (0x1UL << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */ +#define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger configuration for input line 8 */ +#define EXTI_RTSR1_RT9_Pos (9U) +#define EXTI_RTSR1_RT9_Msk (0x1UL << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */ +#define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger configuration for input line 9 */ +#define EXTI_RTSR1_RT10_Pos (10U) +#define EXTI_RTSR1_RT10_Msk (0x1UL << EXTI_RTSR1_RT10_Pos) /*!< 0x00000400 */ +#define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk /*!< Rising trigger configuration for input line 10 */ +#define EXTI_RTSR1_RT11_Pos (11U) +#define EXTI_RTSR1_RT11_Msk (0x1UL << EXTI_RTSR1_RT11_Pos) /*!< 0x00000800 */ +#define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk /*!< Rising trigger configuration for input line 11 */ +#define EXTI_RTSR1_RT12_Pos (12U) +#define EXTI_RTSR1_RT12_Msk (0x1UL << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */ +#define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger configuration for input line 12 */ +#define EXTI_RTSR1_RT13_Pos (13U) +#define EXTI_RTSR1_RT13_Msk (0x1UL << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */ +#define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger configuration for input line 13 */ +#define EXTI_RTSR1_RT14_Pos (14U) +#define EXTI_RTSR1_RT14_Msk (0x1UL << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */ +#define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger configuration for input line 14 */ +#define EXTI_RTSR1_RT15_Pos (15U) +#define EXTI_RTSR1_RT15_Msk (0x1UL << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */ +#define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger configuration for input line 15 */ +#define EXTI_RTSR1_RT16_Pos (16U) +#define EXTI_RTSR1_RT16_Msk (0x1UL << EXTI_RTSR1_RT16_Pos) /*!< 0x00010000 */ +#define EXTI_RTSR1_RT16 EXTI_RTSR1_RT16_Msk /*!< Rising trigger configuration for input line 16 */ +#define EXTI_RTSR1_RT17_Pos (17U) +#define EXTI_RTSR1_RT17_Msk (0x1UL << EXTI_RTSR1_RT17_Pos) /*!< 0x00020000 */ +#define EXTI_RTSR1_RT17 EXTI_RTSR1_RT17_Msk /*!< Rising trigger configuration for input line 17 */ +#define EXTI_RTSR1_RT18_Pos (18U) +#define EXTI_RTSR1_RT18_Msk (0x1UL << EXTI_RTSR1_RT18_Pos) /*!< 0x00040000 */ +#define EXTI_RTSR1_RT18 EXTI_RTSR1_RT18_Msk /*!< Rising trigger configuration for input line 18 */ + +/****************** Bit definition for EXTI_FTSR1 register ******************/ +#define EXTI_FTSR1_FT0_Pos (0U) +#define EXTI_FTSR1_FT0_Msk (0x1UL << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */ +#define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger configuration for input line 0 */ +#define EXTI_FTSR1_FT1_Pos (1U) +#define EXTI_FTSR1_FT1_Msk (0x1UL << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */ +#define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger configuration for input line 1 */ +#define EXTI_FTSR1_FT2_Pos (2U) +#define EXTI_FTSR1_FT2_Msk (0x1UL << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */ +#define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger configuration for input line 2 */ +#define EXTI_FTSR1_FT3_Pos (3U) +#define EXTI_FTSR1_FT3_Msk (0x1UL << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */ +#define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger configuration for input line 3 */ +#define EXTI_FTSR1_FT4_Pos (4U) +#define EXTI_FTSR1_FT4_Msk (0x1UL << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */ +#define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger configuration for input line 4 */ +#define EXTI_FTSR1_FT5_Pos (5U) +#define EXTI_FTSR1_FT5_Msk (0x1UL << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */ +#define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger configuration for input line 5 */ +#define EXTI_FTSR1_FT6_Pos (6U) +#define EXTI_FTSR1_FT6_Msk (0x1UL << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */ +#define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger configuration for input line 6 */ +#define EXTI_FTSR1_FT7_Pos (7U) +#define EXTI_FTSR1_FT7_Msk (0x1UL << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */ +#define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger configuration for input line 7 */ +#define EXTI_FTSR1_FT8_Pos (8U) +#define EXTI_FTSR1_FT8_Msk (0x1UL << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */ +#define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger configuration for input line 8 */ +#define EXTI_FTSR1_FT9_Pos (9U) +#define EXTI_FTSR1_FT9_Msk (0x1UL << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */ +#define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger configuration for input line 9 */ +#define EXTI_FTSR1_FT10_Pos (10U) +#define EXTI_FTSR1_FT10_Msk (0x1UL << EXTI_FTSR1_FT10_Pos) /*!< 0x00000400 */ +#define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk /*!< Falling trigger configuration for input line 10 */ +#define EXTI_FTSR1_FT11_Pos (11U) +#define EXTI_FTSR1_FT11_Msk (0x1UL << EXTI_FTSR1_FT11_Pos) /*!< 0x00000800 */ +#define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk /*!< Falling trigger configuration for input line 11 */ +#define EXTI_FTSR1_FT12_Pos (12U) +#define EXTI_FTSR1_FT12_Msk (0x1UL << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */ +#define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger configuration for input line 12 */ +#define EXTI_FTSR1_FT13_Pos (13U) +#define EXTI_FTSR1_FT13_Msk (0x1UL << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */ +#define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger configuration for input line 13 */ +#define EXTI_FTSR1_FT14_Pos (14U) +#define EXTI_FTSR1_FT14_Msk (0x1UL << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */ +#define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger configuration for input line 14 */ +#define EXTI_FTSR1_FT15_Pos (15U) +#define EXTI_FTSR1_FT15_Msk (0x1UL << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */ +#define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger configuration for input line 15 */ +#define EXTI_FTSR1_FT16_Pos (16U) +#define EXTI_FTSR1_FT16_Msk (0x1UL << EXTI_FTSR1_FT16_Pos) /*!< 0x00010000 */ +#define EXTI_FTSR1_FT16 EXTI_FTSR1_FT16_Msk /*!< Falling trigger configuration for input line 16 */ +#define EXTI_FTSR1_FT17_Pos (17U) +#define EXTI_FTSR1_FT17_Msk (0x1UL << EXTI_FTSR1_FT17_Pos) /*!< 0x00020000 */ +#define EXTI_FTSR1_FT17 EXTI_FTSR1_FT17_Msk /*!< Falling trigger configuration for input line 17 */ +#define EXTI_FTSR1_FT18_Pos (18U) +#define EXTI_FTSR1_FT18_Msk (0x1UL << EXTI_FTSR1_FT18_Pos) /*!< 0x00040000 */ +#define EXTI_FTSR1_FT18 EXTI_FTSR1_FT18_Msk /*!< Falling trigger configuration for input line 18 */ + +/****************** Bit definition for EXTI_SWIER1 register *****************/ +#define EXTI_SWIER1_SWI0_Pos (0U) +#define EXTI_SWIER1_SWI0_Msk (0x1UL << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */ +#define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software Interrupt on line 0 */ +#define EXTI_SWIER1_SWI1_Pos (1U) +#define EXTI_SWIER1_SWI1_Msk (0x1UL << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */ +#define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software Interrupt on line 1 */ +#define EXTI_SWIER1_SWI2_Pos (2U) +#define EXTI_SWIER1_SWI2_Msk (0x1UL << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */ +#define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software Interrupt on line 2 */ +#define EXTI_SWIER1_SWI3_Pos (3U) +#define EXTI_SWIER1_SWI3_Msk (0x1UL << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */ +#define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software Interrupt on line 3 */ +#define EXTI_SWIER1_SWI4_Pos (4U) +#define EXTI_SWIER1_SWI4_Msk (0x1UL << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */ +#define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software Interrupt on line 4 */ +#define EXTI_SWIER1_SWI5_Pos (5U) +#define EXTI_SWIER1_SWI5_Msk (0x1UL << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */ +#define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software Interrupt on line 5 */ +#define EXTI_SWIER1_SWI6_Pos (6U) +#define EXTI_SWIER1_SWI6_Msk (0x1UL << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */ +#define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software Interrupt on line 6 */ +#define EXTI_SWIER1_SWI7_Pos (7U) +#define EXTI_SWIER1_SWI7_Msk (0x1UL << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */ +#define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software Interrupt on line 7 */ +#define EXTI_SWIER1_SWI8_Pos (8U) +#define EXTI_SWIER1_SWI8_Msk (0x1UL << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */ +#define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software Interrupt on line 8 */ +#define EXTI_SWIER1_SWI9_Pos (9U) +#define EXTI_SWIER1_SWI9_Msk (0x1UL << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */ +#define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software Interrupt on line 9 */ +#define EXTI_SWIER1_SWI10_Pos (10U) +#define EXTI_SWIER1_SWI10_Msk (0x1UL << EXTI_SWIER1_SWI10_Pos) /*!< 0x00000400 */ +#define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk /*!< Software Interrupt on line 10 */ +#define EXTI_SWIER1_SWI11_Pos (11U) +#define EXTI_SWIER1_SWI11_Msk (0x1UL << EXTI_SWIER1_SWI11_Pos) /*!< 0x00000800 */ +#define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk /*!< Software Interrupt on line 11 */ +#define EXTI_SWIER1_SWI12_Pos (12U) +#define EXTI_SWIER1_SWI12_Msk (0x1UL << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */ +#define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software Interrupt on line 12 */ +#define EXTI_SWIER1_SWI13_Pos (13U) +#define EXTI_SWIER1_SWI13_Msk (0x1UL << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */ +#define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software Interrupt on line 13 */ +#define EXTI_SWIER1_SWI14_Pos (14U) +#define EXTI_SWIER1_SWI14_Msk (0x1UL << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */ +#define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software Interrupt on line 14 */ +#define EXTI_SWIER1_SWI15_Pos (15U) +#define EXTI_SWIER1_SWI15_Msk (0x1UL << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */ +#define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software Interrupt on line 15 */ +#define EXTI_SWIER1_SWI16_Pos (16U) +#define EXTI_SWIER1_SWI16_Msk (0x1UL << EXTI_SWIER1_SWI16_Pos) /*!< 0x00010000 */ +#define EXTI_SWIER1_SWI16 EXTI_SWIER1_SWI16_Msk /*!< Software Interrupt on line 16 */ +#define EXTI_SWIER1_SWI17_Pos (17U) +#define EXTI_SWIER1_SWI17_Msk (0x1UL << EXTI_SWIER1_SWI17_Pos) /*!< 0x00020000 */ +#define EXTI_SWIER1_SWI17 EXTI_SWIER1_SWI17_Msk /*!< Software Interrupt on line 17 */ +#define EXTI_SWIER1_SWI18_Pos (18U) +#define EXTI_SWIER1_SWI18_Msk (0x1UL << EXTI_SWIER1_SWI18_Pos) /*!< 0x00040000 */ +#define EXTI_SWIER1_SWI18 EXTI_SWIER1_SWI18_Msk /*!< Software Interrupt on line 18 */ + +/******************* Bit definition for EXTI_RPR1 register ******************/ +#define EXTI_RPR1_RPIF0_Pos (0U) +#define EXTI_RPR1_RPIF0_Msk (0x1UL << EXTI_RPR1_RPIF0_Pos) /*!< 0x00000001 */ +#define EXTI_RPR1_RPIF0 EXTI_RPR1_RPIF0_Msk /*!< Rising Pending Interrupt Flag on line 0 */ +#define EXTI_RPR1_RPIF1_Pos (1U) +#define EXTI_RPR1_RPIF1_Msk (0x1UL << EXTI_RPR1_RPIF1_Pos) /*!< 0x00000002 */ +#define EXTI_RPR1_RPIF1 EXTI_RPR1_RPIF1_Msk /*!< Rising Pending Interrupt Flag on line 1 */ +#define EXTI_RPR1_RPIF2_Pos (2U) +#define EXTI_RPR1_RPIF2_Msk (0x1UL << EXTI_RPR1_RPIF2_Pos) /*!< 0x00000004 */ +#define EXTI_RPR1_RPIF2 EXTI_RPR1_RPIF2_Msk /*!< Rising Pending Interrupt Flag on line 2 */ +#define EXTI_RPR1_RPIF3_Pos (3U) +#define EXTI_RPR1_RPIF3_Msk (0x1UL << EXTI_RPR1_RPIF3_Pos) /*!< 0x00000008 */ +#define EXTI_RPR1_RPIF3 EXTI_RPR1_RPIF3_Msk /*!< Rising Pending Interrupt Flag on line 3 */ +#define EXTI_RPR1_RPIF4_Pos (4U) +#define EXTI_RPR1_RPIF4_Msk (0x1UL << EXTI_RPR1_RPIF4_Pos) /*!< 0x00000010 */ +#define EXTI_RPR1_RPIF4 EXTI_RPR1_RPIF4_Msk /*!< Rising Pending Interrupt Flag on line 4 */ +#define EXTI_RPR1_RPIF5_Pos (5U) +#define EXTI_RPR1_RPIF5_Msk (0x1UL << EXTI_RPR1_RPIF5_Pos) /*!< 0x00000020 */ +#define EXTI_RPR1_RPIF5 EXTI_RPR1_RPIF5_Msk /*!< Rising Pending Interrupt Flag on line 5 */ +#define EXTI_RPR1_RPIF6_Pos (6U) +#define EXTI_RPR1_RPIF6_Msk (0x1UL << EXTI_RPR1_RPIF6_Pos) /*!< 0x00000040 */ +#define EXTI_RPR1_RPIF6 EXTI_RPR1_RPIF6_Msk /*!< Rising Pending Interrupt Flag on line 6 */ +#define EXTI_RPR1_RPIF7_Pos (7U) +#define EXTI_RPR1_RPIF7_Msk (0x1UL << EXTI_RPR1_RPIF7_Pos) /*!< 0x00000080 */ +#define EXTI_RPR1_RPIF7 EXTI_RPR1_RPIF7_Msk /*!< Rising Pending Interrupt Flag on line 7 */ +#define EXTI_RPR1_RPIF8_Pos (8U) +#define EXTI_RPR1_RPIF8_Msk (0x1UL << EXTI_RPR1_RPIF8_Pos) /*!< 0x00000100 */ +#define EXTI_RPR1_RPIF8 EXTI_RPR1_RPIF8_Msk /*!< Rising Pending Interrupt Flag on line 8 */ +#define EXTI_RPR1_RPIF9_Pos (9U) +#define EXTI_RPR1_RPIF9_Msk (0x1UL << EXTI_RPR1_RPIF9_Pos) /*!< 0x00000200 */ +#define EXTI_RPR1_RPIF9 EXTI_RPR1_RPIF9_Msk /*!< Rising Pending Interrupt Flag on line 9 */ +#define EXTI_RPR1_RPIF10_Pos (10U) +#define EXTI_RPR1_RPIF10_Msk (0x1UL << EXTI_RPR1_RPIF10_Pos) /*!< 0x00000400 */ +#define EXTI_RPR1_RPIF10 EXTI_RPR1_RPIF10_Msk /*!< Rising Pending Interrupt Flag on line 10 */ +#define EXTI_RPR1_RPIF11_Pos (11U) +#define EXTI_RPR1_RPIF11_Msk (0x1UL << EXTI_RPR1_RPIF11_Pos) /*!< 0x00000800 */ +#define EXTI_RPR1_RPIF11 EXTI_RPR1_RPIF11_Msk /*!< Rising Pending Interrupt Flag on line 11 */ +#define EXTI_RPR1_RPIF12_Pos (12U) +#define EXTI_RPR1_RPIF12_Msk (0x1UL << EXTI_RPR1_RPIF12_Pos) /*!< 0x00001000 */ +#define EXTI_RPR1_RPIF12 EXTI_RPR1_RPIF12_Msk /*!< Rising Pending Interrupt Flag on line 12 */ +#define EXTI_RPR1_RPIF13_Pos (13U) +#define EXTI_RPR1_RPIF13_Msk (0x1UL << EXTI_RPR1_RPIF13_Pos) /*!< 0x00002000 */ +#define EXTI_RPR1_RPIF13 EXTI_RPR1_RPIF13_Msk /*!< Rising Pending Interrupt Flag on line 13 */ +#define EXTI_RPR1_RPIF14_Pos (14U) +#define EXTI_RPR1_RPIF14_Msk (0x1UL << EXTI_RPR1_RPIF14_Pos) /*!< 0x00004000 */ +#define EXTI_RPR1_RPIF14 EXTI_RPR1_RPIF14_Msk /*!< Rising Pending Interrupt Flag on line 14 */ +#define EXTI_RPR1_RPIF15_Pos (15U) +#define EXTI_RPR1_RPIF15_Msk (0x1UL << EXTI_RPR1_RPIF15_Pos) /*!< 0x00008000 */ +#define EXTI_RPR1_RPIF15 EXTI_RPR1_RPIF15_Msk /*!< Rising Pending Interrupt Flag on line 15 */ +#define EXTI_RPR1_RPIF16_Pos (16U) +#define EXTI_RPR1_RPIF16_Msk (0x1UL << EXTI_RPR1_RPIF16_Pos) /*!< 0x00010000 */ +#define EXTI_RPR1_RPIF16 EXTI_RPR1_RPIF16_Msk /*!< Rising Pending Interrupt Flag on line 16 */ +#define EXTI_RPR1_RPIF17_Pos (17U) +#define EXTI_RPR1_RPIF17_Msk (0x1UL << EXTI_RPR1_RPIF17_Pos) /*!< 0x00020000 */ +#define EXTI_RPR1_RPIF17 EXTI_RPR1_RPIF17_Msk /*!< Rising Pending Interrupt Flag on line 17 */ +#define EXTI_RPR1_RPIF18_Pos (18U) +#define EXTI_RPR1_RPIF18_Msk (0x1UL << EXTI_RPR1_RPIF18_Pos) /*!< 0x00040000 */ +#define EXTI_RPR1_RPIF18 EXTI_RPR1_RPIF18_Msk /*!< Rising Pending Interrupt Flag on line 18 */ + +/******************* Bit definition for EXTI_FPR1 register ******************/ +#define EXTI_FPR1_FPIF0_Pos (0U) +#define EXTI_FPR1_FPIF0_Msk (0x1UL << EXTI_FPR1_FPIF0_Pos) /*!< 0x00000001 */ +#define EXTI_FPR1_FPIF0 EXTI_FPR1_FPIF0_Msk /*!< Falling Pending Interrupt Flag on line 0 */ +#define EXTI_FPR1_FPIF1_Pos (1U) +#define EXTI_FPR1_FPIF1_Msk (0x1UL << EXTI_FPR1_FPIF1_Pos) /*!< 0x00000002 */ +#define EXTI_FPR1_FPIF1 EXTI_FPR1_FPIF1_Msk /*!< Falling Pending Interrupt Flag on line 1 */ +#define EXTI_FPR1_FPIF2_Pos (2U) +#define EXTI_FPR1_FPIF2_Msk (0x1UL << EXTI_FPR1_FPIF2_Pos) /*!< 0x00000004 */ +#define EXTI_FPR1_FPIF2 EXTI_FPR1_FPIF2_Msk /*!< Falling Pending Interrupt Flag on line 2 */ +#define EXTI_FPR1_FPIF3_Pos (3U) +#define EXTI_FPR1_FPIF3_Msk (0x1UL << EXTI_FPR1_FPIF3_Pos) /*!< 0x00000008 */ +#define EXTI_FPR1_FPIF3 EXTI_FPR1_FPIF3_Msk /*!< Falling Pending Interrupt Flag on line 3 */ +#define EXTI_FPR1_FPIF4_Pos (4U) +#define EXTI_FPR1_FPIF4_Msk (0x1UL << EXTI_FPR1_FPIF4_Pos) /*!< 0x00000010 */ +#define EXTI_FPR1_FPIF4 EXTI_FPR1_FPIF4_Msk /*!< Falling Pending Interrupt Flag on line 4 */ +#define EXTI_FPR1_FPIF5_Pos (5U) +#define EXTI_FPR1_FPIF5_Msk (0x1UL << EXTI_FPR1_FPIF5_Pos) /*!< 0x00000020 */ +#define EXTI_FPR1_FPIF5 EXTI_FPR1_FPIF5_Msk /*!< Falling Pending Interrupt Flag on line 5 */ +#define EXTI_FPR1_FPIF6_Pos (6U) +#define EXTI_FPR1_FPIF6_Msk (0x1UL << EXTI_FPR1_FPIF6_Pos) /*!< 0x00000040 */ +#define EXTI_FPR1_FPIF6 EXTI_FPR1_FPIF6_Msk /*!< Falling Pending Interrupt Flag on line 6 */ +#define EXTI_FPR1_FPIF7_Pos (7U) +#define EXTI_FPR1_FPIF7_Msk (0x1UL << EXTI_FPR1_FPIF7_Pos) /*!< 0x00000080 */ +#define EXTI_FPR1_FPIF7 EXTI_FPR1_FPIF7_Msk /*!< Falling Pending Interrupt Flag on line 7 */ +#define EXTI_FPR1_FPIF8_Pos (8U) +#define EXTI_FPR1_FPIF8_Msk (0x1UL << EXTI_FPR1_FPIF8_Pos) /*!< 0x00000100 */ +#define EXTI_FPR1_FPIF8 EXTI_FPR1_FPIF8_Msk /*!< Falling Pending Interrupt Flag on line 8 */ +#define EXTI_FPR1_FPIF9_Pos (9U) +#define EXTI_FPR1_FPIF9_Msk (0x1UL << EXTI_FPR1_FPIF9_Pos) /*!< 0x00000200 */ +#define EXTI_FPR1_FPIF9 EXTI_FPR1_FPIF9_Msk /*!< Falling Pending Interrupt Flag on line 9 */ +#define EXTI_FPR1_FPIF10_Pos (10U) +#define EXTI_FPR1_FPIF10_Msk (0x1UL << EXTI_FPR1_FPIF10_Pos) /*!< 0x00000400 */ +#define EXTI_FPR1_FPIF10 EXTI_FPR1_FPIF10_Msk /*!< Falling Pending Interrupt Flag on line 10 */ +#define EXTI_FPR1_FPIF11_Pos (11U) +#define EXTI_FPR1_FPIF11_Msk (0x1UL << EXTI_FPR1_FPIF11_Pos) /*!< 0x00000800 */ +#define EXTI_FPR1_FPIF11 EXTI_FPR1_FPIF11_Msk /*!< Falling Pending Interrupt Flag on line 11 */ +#define EXTI_FPR1_FPIF12_Pos (12U) +#define EXTI_FPR1_FPIF12_Msk (0x1UL << EXTI_FPR1_FPIF12_Pos) /*!< 0x00001000 */ +#define EXTI_FPR1_FPIF12 EXTI_FPR1_FPIF12_Msk /*!< Falling Pending Interrupt Flag on line 12 */ +#define EXTI_FPR1_FPIF13_Pos (13U) +#define EXTI_FPR1_FPIF13_Msk (0x1UL << EXTI_FPR1_FPIF13_Pos) /*!< 0x00002000 */ +#define EXTI_FPR1_FPIF13 EXTI_FPR1_FPIF13_Msk /*!< Falling Pending Interrupt Flag on line 13 */ +#define EXTI_FPR1_FPIF14_Pos (14U) +#define EXTI_FPR1_FPIF14_Msk (0x1UL << EXTI_FPR1_FPIF14_Pos) /*!< 0x00004000 */ +#define EXTI_FPR1_FPIF14 EXTI_FPR1_FPIF14_Msk /*!< Falling Pending Interrupt Flag on line 14 */ +#define EXTI_FPR1_FPIF15_Pos (15U) +#define EXTI_FPR1_FPIF15_Msk (0x1UL << EXTI_FPR1_FPIF15_Pos) /*!< 0x00008000 */ +#define EXTI_FPR1_FPIF15 EXTI_FPR1_FPIF15_Msk /*!< Falling Pending Interrupt Flag on line 15 */ +#define EXTI_FPR1_FPIF16_Pos (16U) +#define EXTI_FPR1_FPIF16_Msk (0x1UL << EXTI_FPR1_FPIF16_Pos) /*!< 0x00010000 */ +#define EXTI_FPR1_FPIF16 EXTI_FPR1_FPIF16_Msk /*!< Falling Pending Interrupt Flag on line 16 */ +#define EXTI_FPR1_FPIF17_Pos (17U) +#define EXTI_FPR1_FPIF17_Msk (0x1UL << EXTI_FPR1_FPIF17_Pos) /*!< 0x00020000 */ +#define EXTI_FPR1_FPIF17 EXTI_FPR1_FPIF17_Msk /*!< Falling Pending Interrupt Flag on line 17 */ +#define EXTI_FPR1_FPIF18_Pos (18U) +#define EXTI_FPR1_FPIF18_Msk (0x1UL << EXTI_FPR1_FPIF18_Pos) /*!< 0x00040000 */ +#define EXTI_FPR1_FPIF18 EXTI_FPR1_FPIF18_Msk /*!< Falling Pending Interrupt Flag on line 18 */ + +/******************* Bit definition for EXTI_SECCFGR1 register ******************/ +#define EXTI_SECCFGR1_SEC0_Pos (0U) +#define EXTI_SECCFGR1_SEC0_Msk (0x1UL << EXTI_SECCFGR1_SEC0_Pos) /*!< 0x00000001 */ +#define EXTI_SECCFGR1_SEC0 EXTI_SECCFGR1_SEC0_Msk /*!< Security enable on line 0 */ +#define EXTI_SECCFGR1_SEC1_Pos (1U) +#define EXTI_SECCFGR1_SEC1_Msk (0x1UL << EXTI_SECCFGR1_SEC1_Pos) /*!< 0x00000002 */ +#define EXTI_SECCFGR1_SEC1 EXTI_SECCFGR1_SEC1_Msk /*!< Security enable on line 1 */ +#define EXTI_SECCFGR1_SEC2_Pos (2U) +#define EXTI_SECCFGR1_SEC2_Msk (0x1UL << EXTI_SECCFGR1_SEC2_Pos) /*!< 0x00000004 */ +#define EXTI_SECCFGR1_SEC2 EXTI_SECCFGR1_SEC2_Msk /*!< Security enable on line 2 */ +#define EXTI_SECCFGR1_SEC3_Pos (3U) +#define EXTI_SECCFGR1_SEC3_Msk (0x1UL << EXTI_SECCFGR1_SEC3_Pos) /*!< 0x00000008 */ +#define EXTI_SECCFGR1_SEC3 EXTI_SECCFGR1_SEC3_Msk /*!< Security enable on line 3 */ +#define EXTI_SECCFGR1_SEC4_Pos (4U) +#define EXTI_SECCFGR1_SEC4_Msk (0x1UL << EXTI_SECCFGR1_SEC4_Pos) /*!< 0x00000010 */ +#define EXTI_SECCFGR1_SEC4 EXTI_SECCFGR1_SEC4_Msk /*!< Security enable on line 4 */ +#define EXTI_SECCFGR1_SEC5_Pos (5U) +#define EXTI_SECCFGR1_SEC5_Msk (0x1UL << EXTI_SECCFGR1_SEC5_Pos) /*!< 0x00000020 */ +#define EXTI_SECCFGR1_SEC5 EXTI_SECCFGR1_SEC5_Msk /*!< Security enable on line 5 */ +#define EXTI_SECCFGR1_SEC6_Pos (6U) +#define EXTI_SECCFGR1_SEC6_Msk (0x1UL << EXTI_SECCFGR1_SEC6_Pos) /*!< 0x00000040 */ +#define EXTI_SECCFGR1_SEC6 EXTI_SECCFGR1_SEC6_Msk /*!< Security enable on line 6 */ +#define EXTI_SECCFGR1_SEC7_Pos (7U) +#define EXTI_SECCFGR1_SEC7_Msk (0x1UL << EXTI_SECCFGR1_SEC7_Pos) /*!< 0x00000080 */ +#define EXTI_SECCFGR1_SEC7 EXTI_SECCFGR1_SEC7_Msk /*!< Security enable on line 7 */ +#define EXTI_SECCFGR1_SEC8_Pos (8U) +#define EXTI_SECCFGR1_SEC8_Msk (0x1UL << EXTI_SECCFGR1_SEC8_Pos) /*!< 0x00000100 */ +#define EXTI_SECCFGR1_SEC8 EXTI_SECCFGR1_SEC8_Msk /*!< Security enable on line 8 */ +#define EXTI_SECCFGR1_SEC9_Pos (9U) +#define EXTI_SECCFGR1_SEC9_Msk (0x1UL << EXTI_SECCFGR1_SEC9_Pos) /*!< 0x00000200 */ +#define EXTI_SECCFGR1_SEC9 EXTI_SECCFGR1_SEC9_Msk /*!< Security enable on line 9 */ +#define EXTI_SECCFGR1_SEC10_Pos (10U) +#define EXTI_SECCFGR1_SEC10_Msk (0x1UL << EXTI_SECCFGR1_SEC10_Pos) /*!< 0x00000400 */ +#define EXTI_SECCFGR1_SEC10 EXTI_SECCFGR1_SEC10_Msk /*!< Security enable on line 10 */ +#define EXTI_SECCFGR1_SEC11_Pos (11U) +#define EXTI_SECCFGR1_SEC11_Msk (0x1UL << EXTI_SECCFGR1_SEC11_Pos) /*!< 0x00000800 */ +#define EXTI_SECCFGR1_SEC11 EXTI_SECCFGR1_SEC11_Msk /*!< Security enable on line 11 */ +#define EXTI_SECCFGR1_SEC12_Pos (12U) +#define EXTI_SECCFGR1_SEC12_Msk (0x1UL << EXTI_SECCFGR1_SEC12_Pos) /*!< 0x00001000 */ +#define EXTI_SECCFGR1_SEC12 EXTI_SECCFGR1_SEC12_Msk /*!< Security enable on line 12 */ +#define EXTI_SECCFGR1_SEC13_Pos (13U) +#define EXTI_SECCFGR1_SEC13_Msk (0x1UL << EXTI_SECCFGR1_SEC13_Pos) /*!< 0x00002000 */ +#define EXTI_SECCFGR1_SEC13 EXTI_SECCFGR1_SEC13_Msk /*!< Security enable on line 13 */ +#define EXTI_SECCFGR1_SEC14_Pos (14U) +#define EXTI_SECCFGR1_SEC14_Msk (0x1UL << EXTI_SECCFGR1_SEC14_Pos) /*!< 0x00004000 */ +#define EXTI_SECCFGR1_SEC14 EXTI_SECCFGR1_SEC14_Msk /*!< Security enable on line 14 */ +#define EXTI_SECCFGR1_SEC15_Pos (15U) +#define EXTI_SECCFGR1_SEC15_Msk (0x1UL << EXTI_SECCFGR1_SEC15_Pos) /*!< 0x00008000 */ +#define EXTI_SECCFGR1_SEC15 EXTI_SECCFGR1_SEC15_Msk /*!< Security enable on line 15 */ +#define EXTI_SECCFGR1_SEC16_Pos (16U) +#define EXTI_SECCFGR1_SEC16_Msk (0x1UL << EXTI_SECCFGR1_SEC16_Pos) /*!< 0x00010000 */ +#define EXTI_SECCFGR1_SEC16 EXTI_SECCFGR1_SEC16_Msk /*!< Security enable on line 16 */ +#define EXTI_SECCFGR1_SEC17_Pos (17U) +#define EXTI_SECCFGR1_SEC17_Msk (0x1UL << EXTI_SECCFGR1_SEC17_Pos) /*!< 0x00020000 */ +#define EXTI_SECCFGR1_SEC17 EXTI_SECCFGR1_SEC17_Msk /*!< Security enable on line 17 */ +#define EXTI_SECCFGR1_SEC18_Pos (18U) +#define EXTI_SECCFGR1_SEC18_Msk (0x1UL << EXTI_SECCFGR1_SEC18_Pos) /*!< 0x00040000 */ +#define EXTI_SECCFGR1_SEC18 EXTI_SECCFGR1_SEC18_Msk /*!< Security enable on line 18 */ + +/******************* Bit definition for EXTI_PRIVCFGR1 register ******************/ +#define EXTI_PRIVCFGR1_PRIV0_Pos (0U) +#define EXTI_PRIVCFGR1_PRIV0_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV0_Pos) /*!< 0x00000001 */ +#define EXTI_PRIVCFGR1_PRIV0 EXTI_PRIVCFGR1_PRIV0_Msk /*!< Privilege enable on line 0 */ +#define EXTI_PRIVCFGR1_PRIV1_Pos (1U) +#define EXTI_PRIVCFGR1_PRIV1_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV1_Pos) /*!< 0x00000002 */ +#define EXTI_PRIVCFGR1_PRIV1 EXTI_PRIVCFGR1_PRIV1_Msk /*!< Privilege enable on line 1 */ +#define EXTI_PRIVCFGR1_PRIV2_Pos (2U) +#define EXTI_PRIVCFGR1_PRIV2_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV2_Pos) /*!< 0x00000004 */ +#define EXTI_PRIVCFGR1_PRIV2 EXTI_PRIVCFGR1_PRIV2_Msk /*!< Privilege enable on line 2 */ +#define EXTI_PRIVCFGR1_PRIV3_Pos (3U) +#define EXTI_PRIVCFGR1_PRIV3_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV3_Pos) /*!< 0x00000008 */ +#define EXTI_PRIVCFGR1_PRIV3 EXTI_PRIVCFGR1_PRIV3_Msk /*!< Privilege enable on line 3 */ +#define EXTI_PRIVCFGR1_PRIV4_Pos (4U) +#define EXTI_PRIVCFGR1_PRIV4_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV4_Pos) /*!< 0x00000010 */ +#define EXTI_PRIVCFGR1_PRIV4 EXTI_PRIVCFGR1_PRIV4_Msk /*!< Privilege enable on line 4 */ +#define EXTI_PRIVCFGR1_PRIV5_Pos (5U) +#define EXTI_PRIVCFGR1_PRIV5_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV5_Pos) /*!< 0x00000020 */ +#define EXTI_PRIVCFGR1_PRIV5 EXTI_PRIVCFGR1_PRIV5_Msk /*!< Privilege enable on line 5 */ +#define EXTI_PRIVCFGR1_PRIV6_Pos (6U) +#define EXTI_PRIVCFGR1_PRIV6_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV6_Pos) /*!< 0x00000040 */ +#define EXTI_PRIVCFGR1_PRIV6 EXTI_PRIVCFGR1_PRIV6_Msk /*!< Privilege enable on line 6 */ +#define EXTI_PRIVCFGR1_PRIV7_Pos (7U) +#define EXTI_PRIVCFGR1_PRIV7_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV7_Pos) /*!< 0x00000080 */ +#define EXTI_PRIVCFGR1_PRIV7 EXTI_PRIVCFGR1_PRIV7_Msk /*!< Privilege enable on line 7 */ +#define EXTI_PRIVCFGR1_PRIV8_Pos (8U) +#define EXTI_PRIVCFGR1_PRIV8_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV8_Pos) /*!< 0x00000100 */ +#define EXTI_PRIVCFGR1_PRIV8 EXTI_PRIVCFGR1_PRIV8_Msk /*!< Privilege enable on line 8 */ +#define EXTI_PRIVCFGR1_PRIV9_Pos (9U) +#define EXTI_PRIVCFGR1_PRIV9_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV9_Pos) /*!< 0x00000200 */ +#define EXTI_PRIVCFGR1_PRIV9 EXTI_PRIVCFGR1_PRIV9_Msk /*!< Privilege enable on line 9 */ +#define EXTI_PRIVCFGR1_PRIV10_Pos (10U) +#define EXTI_PRIVCFGR1_PRIV10_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV10_Pos) /*!< 0x00000400 */ +#define EXTI_PRIVCFGR1_PRIV10 EXTI_PRIVCFGR1_PRIV10_Msk /*!< Privilege enable on line 10 */ +#define EXTI_PRIVCFGR1_PRIV11_Pos (11U) +#define EXTI_PRIVCFGR1_PRIV11_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV11_Pos) /*!< 0x00000800 */ +#define EXTI_PRIVCFGR1_PRIV11 EXTI_PRIVCFGR1_PRIV11_Msk /*!< Privilege enable on line 11 */ +#define EXTI_PRIVCFGR1_PRIV12_Pos (12U) +#define EXTI_PRIVCFGR1_PRIV12_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV12_Pos) /*!< 0x00001000 */ +#define EXTI_PRIVCFGR1_PRIV12 EXTI_PRIVCFGR1_PRIV12_Msk /*!< Privilege enable on line 12 */ +#define EXTI_PRIVCFGR1_PRIV13_Pos (13U) +#define EXTI_PRIVCFGR1_PRIV13_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV13_Pos) /*!< 0x00002000 */ +#define EXTI_PRIVCFGR1_PRIV13 EXTI_PRIVCFGR1_PRIV13_Msk /*!< Privilege enable on line 13 */ +#define EXTI_PRIVCFGR1_PRIV14_Pos (14U) +#define EXTI_PRIVCFGR1_PRIV14_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV14_Pos) /*!< 0x00004000 */ +#define EXTI_PRIVCFGR1_PRIV14 EXTI_PRIVCFGR1_PRIV14_Msk /*!< Privilege enable on line 14 */ +#define EXTI_PRIVCFGR1_PRIV15_Pos (15U) +#define EXTI_PRIVCFGR1_PRIV15_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV15_Pos) /*!< 0x00008000 */ +#define EXTI_PRIVCFGR1_PRIV15 EXTI_PRIVCFGR1_PRIV15_Msk /*!< Privilege enable on line 15 */ +#define EXTI_PRIVCFGR1_PRIV16_Pos (16U) +#define EXTI_PRIVCFGR1_PRIV16_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV16_Pos) /*!< 0x00010000 */ +#define EXTI_PRIVCFGR1_PRIV16 EXTI_PRIVCFGR1_PRIV16_Msk /*!< Privilege enable on line 16 */ +#define EXTI_PRIVCFGR1_PRIV17_Pos (17U) +#define EXTI_PRIVCFGR1_PRIV17_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV17_Pos) /*!< 0x00020000 */ +#define EXTI_PRIVCFGR1_PRIV17 EXTI_PRIVCFGR1_PRIV17_Msk /*!< Privilege enable on line 17 */ +#define EXTI_PRIVCFGR1_PRIV18_Pos (18U) +#define EXTI_PRIVCFGR1_PRIV18_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV18_Pos) /*!< 0x00040000 */ +#define EXTI_PRIVCFGR1_PRIV18 EXTI_PRIVCFGR1_PRIV18_Msk /*!< Privilege enable on line 18 */ + +/***************** Bit definition for EXTI_EXTICR1 register **************/ +#define EXTI_EXTICR1_EXTI0_Pos (0U) +#define EXTI_EXTICR1_EXTI0_Msk (0xFFUL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x000000FF */ +#define EXTI_EXTICR1_EXTI0 EXTI_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */ +#define EXTI_EXTICR1_EXTI0_0 (0x1UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR1_EXTI0_1 (0x2UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR1_EXTI0_2 (0x4UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR1_EXTI0_3 (0x8UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000008 */ +#define EXTI_EXTICR1_EXTI0_4 (0x10UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000010 */ +#define EXTI_EXTICR1_EXTI0_5 (0x20UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000020 */ +#define EXTI_EXTICR1_EXTI0_6 (0x40UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000040 */ +#define EXTI_EXTICR1_EXTI0_7 (0x80UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000080 */ +#define EXTI_EXTICR1_EXTI1_Pos (8U) +#define EXTI_EXTICR1_EXTI1_Msk (0xFFUL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x0000FF00 */ +#define EXTI_EXTICR1_EXTI1 EXTI_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */ +#define EXTI_EXTICR1_EXTI1_0 (0x1UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR1_EXTI1_1 (0x2UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR1_EXTI1_2 (0x4UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR1_EXTI1_3 (0x8UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000800 */ +#define EXTI_EXTICR1_EXTI1_4 (0x10UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00001000 */ +#define EXTI_EXTICR1_EXTI1_5 (0x20UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00002000 */ +#define EXTI_EXTICR1_EXTI1_6 (0x40UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00004000 */ +#define EXTI_EXTICR1_EXTI1_7 (0x80UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00008000 */ +#define EXTI_EXTICR1_EXTI2_Pos (16U) +#define EXTI_EXTICR1_EXTI2_Msk (0xFFUL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00FF0000 */ +#define EXTI_EXTICR1_EXTI2 EXTI_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */ +#define EXTI_EXTICR1_EXTI2_0 (0x1UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR1_EXTI2_1 (0x2UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR1_EXTI2_2 (0x4UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR1_EXTI2_3 (0x8UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00080000 */ +#define EXTI_EXTICR1_EXTI2_4 (0x10UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00100000 */ +#define EXTI_EXTICR1_EXTI2_5 (0x20UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00200000 */ +#define EXTI_EXTICR1_EXTI2_6 (0x40UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00400000 */ +#define EXTI_EXTICR1_EXTI2_7 (0x80UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00800000 */ +#define EXTI_EXTICR1_EXTI3_Pos (24U) +#define EXTI_EXTICR1_EXTI3_Msk (0xFFUL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0xFF000000 */ +#define EXTI_EXTICR1_EXTI3 EXTI_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */ +#define EXTI_EXTICR1_EXTI3_0 (0x1UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR1_EXTI3_1 (0x2UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR1_EXTI3_2 (0x4UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x04000000 */ +#define EXTI_EXTICR1_EXTI3_3 (0x8UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x08000000 */ +#define EXTI_EXTICR1_EXTI3_4 (0x10UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x10000000 */ +#define EXTI_EXTICR1_EXTI3_5 (0x20UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x20000000 */ +#define EXTI_EXTICR1_EXTI3_6 (0x40UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x40000000 */ +#define EXTI_EXTICR1_EXTI3_7 (0x80UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for EXTI_EXTICR2 register **************/ +#define EXTI_EXTICR2_EXTI4_Pos (0U) +#define EXTI_EXTICR2_EXTI4_Msk (0xFFUL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x000000FF */ +#define EXTI_EXTICR2_EXTI4 EXTI_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */ +#define EXTI_EXTICR2_EXTI4_0 (0x1UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR2_EXTI4_1 (0x2UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR2_EXTI4_2 (0x4UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR2_EXTI4_3 (0x8UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000008 */ +#define EXTI_EXTICR2_EXTI4_4 (0x10UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000010 */ +#define EXTI_EXTICR2_EXTI4_5 (0x20UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000020 */ +#define EXTI_EXTICR2_EXTI4_6 (0x40UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000040 */ +#define EXTI_EXTICR2_EXTI4_7 (0x80UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000080 */ +#define EXTI_EXTICR2_EXTI5_Pos (8U) +#define EXTI_EXTICR2_EXTI5_Msk (0xFFUL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x0000FF00 */ +#define EXTI_EXTICR2_EXTI5 EXTI_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */ +#define EXTI_EXTICR2_EXTI5_0 (0x1UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR2_EXTI5_1 (0x2UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR2_EXTI5_2 (0x4UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR2_EXTI5_3 (0x8UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000800 */ +#define EXTI_EXTICR2_EXTI5_4 (0x10UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00001000 */ +#define EXTI_EXTICR2_EXTI5_5 (0x20UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00002000 */ +#define EXTI_EXTICR2_EXTI5_6 (0x40UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00004000 */ +#define EXTI_EXTICR2_EXTI5_7 (0x80UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00008000 */ +#define EXTI_EXTICR2_EXTI6_Pos (16U) +#define EXTI_EXTICR2_EXTI6_Msk (0xFFUL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00FF0000 */ +#define EXTI_EXTICR2_EXTI6 EXTI_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */ +#define EXTI_EXTICR2_EXTI6_0 (0x1UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR2_EXTI6_1 (0x2UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR2_EXTI6_2 (0x4UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR2_EXTI6_3 (0x8UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00080000 */ +#define EXTI_EXTICR2_EXTI6_4 (0x10UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00100000 */ +#define EXTI_EXTICR2_EXTI6_5 (0x20UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00200000 */ +#define EXTI_EXTICR2_EXTI6_6 (0x40UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00400000 */ +#define EXTI_EXTICR2_EXTI6_7 (0x80UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00800000 */ +#define EXTI_EXTICR2_EXTI7_Pos (24U) +#define EXTI_EXTICR2_EXTI7_Msk (0xFFUL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0xFF000000 */ +#define EXTI_EXTICR2_EXTI7 EXTI_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */ +#define EXTI_EXTICR2_EXTI7_0 (0x1UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR2_EXTI7_1 (0x2UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR2_EXTI7_2 (0x4UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x04000000 */ +#define EXTI_EXTICR2_EXTI7_3 (0x8UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x08000000 */ +#define EXTI_EXTICR2_EXTI7_4 (0x10UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x10000000 */ +#define EXTI_EXTICR2_EXTI7_5 (0x20UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x20000000 */ +#define EXTI_EXTICR2_EXTI7_6 (0x40UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x40000000 */ +#define EXTI_EXTICR2_EXTI7_7 (0x80UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for EXTI_EXTICR3 register **************/ +#define EXTI_EXTICR3_EXTI8_Pos (0U) +#define EXTI_EXTICR3_EXTI8_Msk (0xFFUL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x000000FF */ +#define EXTI_EXTICR3_EXTI8 EXTI_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */ +#define EXTI_EXTICR3_EXTI8_0 (0x1UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR3_EXTI8_1 (0x2UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR3_EXTI8_2 (0x4UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR3_EXTI8_3 (0x8UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000008 */ +#define EXTI_EXTICR3_EXTI8_4 (0x10UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000010 */ +#define EXTI_EXTICR3_EXTI8_5 (0x20UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000020 */ +#define EXTI_EXTICR3_EXTI8_6 (0x40UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000040 */ +#define EXTI_EXTICR3_EXTI8_7 (0x80UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000080 */ +#define EXTI_EXTICR3_EXTI9_Pos (8U) +#define EXTI_EXTICR3_EXTI9_Msk (0xFFUL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x0000FF00 */ +#define EXTI_EXTICR3_EXTI9 EXTI_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */ +#define EXTI_EXTICR3_EXTI9_0 (0x1UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR3_EXTI9_1 (0x2UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR3_EXTI9_2 (0x4UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR3_EXTI9_3 (0x8UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000800 */ +#define EXTI_EXTICR3_EXTI9_4 (0x10UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00001000 */ +#define EXTI_EXTICR3_EXTI9_5 (0x20UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00002000 */ +#define EXTI_EXTICR3_EXTI9_6 (0x40UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00004000 */ +#define EXTI_EXTICR3_EXTI9_7 (0x80UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00008000 */ +#define EXTI_EXTICR3_EXTI10_Pos (16U) +#define EXTI_EXTICR3_EXTI10_Msk (0xFFUL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00FF0000 */ +#define EXTI_EXTICR3_EXTI10 EXTI_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */ +#define EXTI_EXTICR3_EXTI10_0 (0x1UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR3_EXTI10_1 (0x2UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR3_EXTI10_2 (0x4UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR3_EXTI10_3 (0x8UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00080000 */ +#define EXTI_EXTICR3_EXTI10_4 (0x10UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00100000 */ +#define EXTI_EXTICR3_EXTI10_5 (0x20UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00200000 */ +#define EXTI_EXTICR3_EXTI10_6 (0x40UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00400000 */ +#define EXTI_EXTICR3_EXTI10_7 (0x80UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00800000 */ +#define EXTI_EXTICR3_EXTI11_Pos (24U) +#define EXTI_EXTICR3_EXTI11_Msk (0xFFUL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0xFF000000 */ +#define EXTI_EXTICR3_EXTI11 EXTI_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */ +#define EXTI_EXTICR3_EXTI11_0 (0x1UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR3_EXTI11_1 (0x2UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR3_EXTI11_2 (0x4UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x04000000 */ +#define EXTI_EXTICR3_EXTI11_3 (0x8UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x08000000 */ +#define EXTI_EXTICR3_EXTI11_4 (0x10UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x10000000 */ +#define EXTI_EXTICR3_EXTI11_5 (0x20UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x20000000 */ +#define EXTI_EXTICR3_EXTI11_6 (0x40UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x40000000 */ +#define EXTI_EXTICR3_EXTI11_7 (0x80UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x80000000 */ + +/***************** Bit definition for EXTI_EXTICR4 register **************/ +#define EXTI_EXTICR4_EXTI12_Pos (0U) +#define EXTI_EXTICR4_EXTI12_Msk (0xFFUL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x000000FF */ +#define EXTI_EXTICR4_EXTI12 EXTI_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */ +#define EXTI_EXTICR4_EXTI12_0 (0x1UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000001 */ +#define EXTI_EXTICR4_EXTI12_1 (0x2UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000002 */ +#define EXTI_EXTICR4_EXTI12_2 (0x4UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000004 */ +#define EXTI_EXTICR4_EXTI12_3 (0x8UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000008 */ +#define EXTI_EXTICR4_EXTI12_4 (0x10UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000010 */ +#define EXTI_EXTICR4_EXTI12_5 (0x20UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000020 */ +#define EXTI_EXTICR4_EXTI12_6 (0x40UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000040 */ +#define EXTI_EXTICR4_EXTI12_7 (0x80UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000080 */ +#define EXTI_EXTICR4_EXTI13_Pos (8U) +#define EXTI_EXTICR4_EXTI13_Msk (0xFFUL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x0000FF00 */ +#define EXTI_EXTICR4_EXTI13 EXTI_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */ +#define EXTI_EXTICR4_EXTI13_0 (0x1UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000100 */ +#define EXTI_EXTICR4_EXTI13_1 (0x2UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000200 */ +#define EXTI_EXTICR4_EXTI13_2 (0x4UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000400 */ +#define EXTI_EXTICR4_EXTI13_3 (0x8UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000800 */ +#define EXTI_EXTICR4_EXTI13_4 (0x10UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00001000 */ +#define EXTI_EXTICR4_EXTI13_5 (0x20UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00002000 */ +#define EXTI_EXTICR4_EXTI13_6 (0x40UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00004000 */ +#define EXTI_EXTICR4_EXTI13_7 (0x80UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00008000 */ +#define EXTI_EXTICR4_EXTI14_Pos (16U) +#define EXTI_EXTICR4_EXTI14_Msk (0xFFUL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00FF0000 */ +#define EXTI_EXTICR4_EXTI14 EXTI_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */ +#define EXTI_EXTICR4_EXTI14_0 (0x1UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00010000 */ +#define EXTI_EXTICR4_EXTI14_1 (0x2UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00020000 */ +#define EXTI_EXTICR4_EXTI14_2 (0x4UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00040000 */ +#define EXTI_EXTICR4_EXTI14_3 (0x8UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00080000 */ +#define EXTI_EXTICR4_EXTI14_4 (0x10UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00100000 */ +#define EXTI_EXTICR4_EXTI14_5 (0x20UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00200000 */ +#define EXTI_EXTICR4_EXTI14_6 (0x40UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00400000 */ +#define EXTI_EXTICR4_EXTI14_7 (0x80UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00800000 */ +#define EXTI_EXTICR4_EXTI15_Pos (24U) +#define EXTI_EXTICR4_EXTI15_Msk (0xFFUL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0xFF000000 */ +#define EXTI_EXTICR4_EXTI15 EXTI_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */ +#define EXTI_EXTICR4_EXTI15_0 (0x1UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x01000000 */ +#define EXTI_EXTICR4_EXTI15_1 (0x2UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x02000000 */ +#define EXTI_EXTICR4_EXTI15_2 (0x4UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x04000000 */ +#define EXTI_EXTICR4_EXTI15_3 (0x8UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x08000000 */ +#define EXTI_EXTICR4_EXTI15_4 (0x10UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x10000000 */ +#define EXTI_EXTICR4_EXTI15_5 (0x20UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x20000000 */ +#define EXTI_EXTICR4_EXTI15_6 (0x40UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x40000000 */ +#define EXTI_EXTICR4_EXTI15_7 (0x80UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x80000000 */ + +/******************* Bit definition for EXTI_LOCKR register ******************/ +#define EXTI_LOCKR_LOCK_Pos (0U) +#define EXTI_LOCKR_LOCK_Msk (0x1UL << EXTI_LOCKR_LOCK_Pos) /*!< 0x00000001 */ +#define EXTI_LOCKR_LOCK EXTI_LOCKR_LOCK_Msk /*!< Security and privilege configuration lock */ + +/******************* Bit definition for EXTI_IMR1 register ******************/ +#define EXTI_IMR1_IM0_Pos (0U) +#define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */ +#define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< Interrupt Mask on line 0 */ +#define EXTI_IMR1_IM1_Pos (1U) +#define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */ +#define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< Interrupt Mask on line 1 */ +#define EXTI_IMR1_IM2_Pos (2U) +#define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */ +#define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< Interrupt Mask on line 2 */ +#define EXTI_IMR1_IM3_Pos (3U) +#define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */ +#define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< Interrupt Mask on line 3 */ +#define EXTI_IMR1_IM4_Pos (4U) +#define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */ +#define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< Interrupt Mask on line 4 */ +#define EXTI_IMR1_IM5_Pos (5U) +#define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */ +#define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< Interrupt Mask on line 5 */ +#define EXTI_IMR1_IM6_Pos (6U) +#define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */ +#define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< Interrupt Mask on line 6 */ +#define EXTI_IMR1_IM7_Pos (7U) +#define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */ +#define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< Interrupt Mask on line 7 */ +#define EXTI_IMR1_IM8_Pos (8U) +#define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */ +#define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< Interrupt Mask on line 8 */ +#define EXTI_IMR1_IM9_Pos (9U) +#define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */ +#define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< Interrupt Mask on line 9 */ +#define EXTI_IMR1_IM10_Pos (10U) +#define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */ +#define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< Interrupt Mask on line 10 */ +#define EXTI_IMR1_IM11_Pos (11U) +#define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */ +#define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< Interrupt Mask on line 11 */ +#define EXTI_IMR1_IM12_Pos (12U) +#define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */ +#define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< Interrupt Mask on line 12 */ +#define EXTI_IMR1_IM13_Pos (13U) +#define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */ +#define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< Interrupt Mask on line 13 */ +#define EXTI_IMR1_IM14_Pos (14U) +#define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */ +#define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< Interrupt Mask on line 14 */ +#define EXTI_IMR1_IM15_Pos (15U) +#define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */ +#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< Interrupt Mask on line 15 */ +#define EXTI_IMR1_IM16_Pos (16U) +#define EXTI_IMR1_IM16_Msk (0x1UL << EXTI_IMR1_IM16_Pos) /*!< 0x00010000 */ +#define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk /*!< Interrupt Mask on line 16 */ +#define EXTI_IMR1_IM17_Pos (17U) +#define EXTI_IMR1_IM17_Msk (0x1UL << EXTI_IMR1_IM17_Pos) /*!< 0x00020000 */ +#define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk /*!< Interrupt Mask on line 17 */ +#define EXTI_IMR1_IM18_Pos (18U) +#define EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */ +#define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< Interrupt Mask on line 18 */ + +/******************* Bit definition for EXTI_EMR1 register ******************/ +#define EXTI_EMR1_EM0_Pos (0U) +#define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */ +#define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< Event Mask on line 0 */ +#define EXTI_EMR1_EM1_Pos (1U) +#define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */ +#define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< Event Mask on line 1 */ +#define EXTI_EMR1_EM2_Pos (2U) +#define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */ +#define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< Event Mask on line 2 */ +#define EXTI_EMR1_EM3_Pos (3U) +#define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */ +#define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< Event Mask on line 3 */ +#define EXTI_EMR1_EM4_Pos (4U) +#define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */ +#define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< Event Mask on line 4 */ +#define EXTI_EMR1_EM5_Pos (5U) +#define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */ +#define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< Event Mask on line 5 */ +#define EXTI_EMR1_EM6_Pos (6U) +#define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */ +#define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< Event Mask on line 6 */ +#define EXTI_EMR1_EM7_Pos (7U) +#define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */ +#define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< Event Mask on line 7 */ +#define EXTI_EMR1_EM8_Pos (8U) +#define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */ +#define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< Event Mask on line 8 */ +#define EXTI_EMR1_EM9_Pos (9U) +#define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */ +#define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< Event Mask on line 9 */ +#define EXTI_EMR1_EM10_Pos (10U) +#define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */ +#define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< Event Mask on line 10 */ +#define EXTI_EMR1_EM11_Pos (11U) +#define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */ +#define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< Event Mask on line 11 */ +#define EXTI_EMR1_EM12_Pos (12U) +#define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */ +#define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< Event Mask on line 12 */ +#define EXTI_EMR1_EM13_Pos (13U) +#define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */ +#define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< Event Mask on line 13 */ +#define EXTI_EMR1_EM14_Pos (14U) +#define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */ +#define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< Event Mask on line 14 */ +#define EXTI_EMR1_EM15_Pos (15U) +#define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */ +#define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< Event Mask on line 15 */ +#define EXTI_EMR1_EM16_Pos (16U) +#define EXTI_EMR1_EM16_Msk (0x1UL << EXTI_EMR1_EM16_Pos) /*!< 0x00010000 */ +#define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk /*!< Event Mask on line 16 */ +#define EXTI_EMR1_EM17_Pos (17U) +#define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */ +#define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< Event Mask on line 17 */ +#define EXTI_EMR1_EM18_Pos (18U) +#define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */ +#define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< Event Mask on line 18 */ + + +/******************************************************************************/ +/* */ +/* FLASH */ +/* */ +/******************************************************************************/ +#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_0 /* FLASH Latency 1 Wait State */ + +/******************* Bits definition for FLASH_ACR register *****************/ +#define FLASH_ACR_LATENCY_Pos (0U) +#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */ +#define FLASH_ACR_LATENCY_0 (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */ +#define FLASH_ACR_LATENCY_1 (0x2UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */ +#define FLASH_ACR_LATENCY_2 (0x4UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000004 */ +#define FLASH_ACR_LATENCY_3 (0x8UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000008 */ +#define FLASH_ACR_PRFTEN_Pos (8U) +#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ +#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch enable */ +#define FLASH_ACR_LPM_Pos (11U) +#define FLASH_ACR_LPM_Msk (0x1UL << FLASH_ACR_LPM_Pos) /*!< 0x00000800 */ +#define FLASH_ACR_LPM FLASH_ACR_LPM_Msk /*!< Low-Power read mode */ +#define FLASH_ACR_PDREQ_Pos (12U) +#define FLASH_ACR_PDREQ_Msk (0x1UL << FLASH_ACR_PDREQ_Pos) /*!< 0x00001000 */ +#define FLASH_ACR_PDREQ FLASH_ACR_PDREQ_Msk /*!< Flash power-down mode request */ +#define FLASH_ACR_SLEEP_PD_Pos (14U) +#define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00004000 */ +#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash power-down mode during sleep */ + +/****************** Bits definition for FLASH_NSKEYR register *****************/ +#define FLASH_NSKEYR_NSKEY_Pos (0U) +#define FLASH_NSKEYR_NSKEY_Msk (0xFFFFFFFFUL << FLASH_NSKEYR_NSKEY_Pos) /*!< 0xFFFFFFFFF */ +#define FLASH_NSKEYR_NSKEY FLASH_NSKEYR_NSKEY_Msk /*!< Flash memory non-secure key */ + +/****************** Bits definition for FLASH_SECKEYR register *****************/ +#define FLASH_SECKEYR_SECKEY_Pos (0U) +#define FLASH_SECKEYR_SECKEY_Msk (0xFFFFFFFFUL << FLASH_SECKEYR_SECKEY_Pos) /*!< 0xFFFFFFFFF */ +#define FLASH_SECKEYR_SECKEY FLASH_SECKEYR_SECKEY_Msk /*!< Flash memory secure key */ + +/****************** Bits definition for FLASH_OPTKEYR register *****************/ +#define FLASH_OPTKEYR_OPTKEY_Pos (0U) +#define FLASH_OPTKEYR_OPTKEY_Msk (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEY_Pos) /*!< 0xFFFFFFFFF */ +#define FLASH_OPTKEYR_OPTKEY FLASH_OPTKEYR_OPTKEY_Msk /*!< Option byte key */ + +/****************** Bits definition for FLASH_PDKEYR register *****************/ +#define FLASH_PDKEYR_PDKEY_Pos (0U) +#define FLASH_PDKEYR_PDKEY_Msk (0xFFFFFFFFUL << FLASH_PDKEYR_PDKEY_Pos) /*!< 0xFFFFFFFFF */ +#define FLASH_PDKEYR_PDKEY FLASH_PDKEYR_PDKEY_Msk /*!< Flash power-down key */ + +/****************** Bits definition for FLASH_NSSR register *****************/ +#define FLASH_NSSR_EOP_Pos (0U) +#define FLASH_NSSR_EOP_Msk (0x1UL << FLASH_NSSR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_NSSR_EOP FLASH_NSSR_EOP_Msk /*!< Non-secure end of operation */ +#define FLASH_NSSR_OPERR_Pos (1U) +#define FLASH_NSSR_OPERR_Msk (0x1UL << FLASH_NSSR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_NSSR_OPERR FLASH_NSSR_OPERR_Msk /*!< Non-secure operation error */ +#define FLASH_NSSR_PROGERR_Pos (3U) +#define FLASH_NSSR_PROGERR_Msk (0x1UL << FLASH_NSSR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_NSSR_PROGERR FLASH_NSSR_PROGERR_Msk /*!< Non-secure programming error */ +#define FLASH_NSSR_WRPERR_Pos (4U) +#define FLASH_NSSR_WRPERR_Msk (0x1UL << FLASH_NSSR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_NSSR_WRPERR FLASH_NSSR_WRPERR_Msk /*!< Non-secure write protection error */ +#define FLASH_NSSR_PGAERR_Pos (5U) +#define FLASH_NSSR_PGAERR_Msk (0x1UL << FLASH_NSSR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_NSSR_PGAERR FLASH_NSSR_PGAERR_Msk /*!< Non-secure programming alignment error */ +#define FLASH_NSSR_SIZERR_Pos (6U) +#define FLASH_NSSR_SIZERR_Msk (0x1UL << FLASH_NSSR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_NSSR_SIZERR FLASH_NSSR_SIZERR_Msk /*!< Non-secure size error */ +#define FLASH_NSSR_PGSERR_Pos (7U) +#define FLASH_NSSR_PGSERR_Msk (0x1UL << FLASH_NSSR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_NSSR_PGSERR FLASH_NSSR_PGSERR_Msk /*!< Non-secure programming sequence error */ +#define FLASH_NSSR_OPTWERR_Pos (13U) +#define FLASH_NSSR_OPTWERR_Msk (0x1UL << FLASH_NSSR_OPTWERR_Pos) /*!< 0x00002000 */ +#define FLASH_NSSR_OPTWERR FLASH_NSSR_OPTWERR_Msk /*!< Option write error */ +#define FLASH_NSSR_BSY_Pos (16U) +#define FLASH_NSSR_BSY_Msk (0x1UL << FLASH_NSSR_BSY_Pos) /*!< 0x00010000 */ +#define FLASH_NSSR_BSY FLASH_NSSR_BSY_Msk /*!< Non-secure busy */ +#define FLASH_NSSR_WDW_Pos (17U) +#define FLASH_NSSR_WDW_Msk (0x1UL << FLASH_NSSR_WDW_Pos) /*!< 0x00020000 */ +#define FLASH_NSSR_WDW FLASH_NSSR_WDW_Msk /*!< Non-secure wait data to write */ +#define FLASH_NSSR_OEM1LOCK_Pos (18U) +#define FLASH_NSSR_OEM1LOCK_Msk (0x1UL << FLASH_NSSR_OEM1LOCK_Pos) /*!< 0x00040000 */ +#define FLASH_NSSR_OEM1LOCK FLASH_NSSR_OEM1LOCK_Msk /*!< OEM1 lock */ +#define FLASH_NSSR_OEM2LOCK_Pos (19U) +#define FLASH_NSSR_OEM2LOCK_Msk (0x1UL << FLASH_NSSR_OEM2LOCK_Pos) /*!< 0x00080000 */ +#define FLASH_NSSR_OEM2LOCK FLASH_NSSR_OEM2LOCK_Msk /*!< OEM2 lock */ +#define FLASH_NSSR_PD_Pos (20U) +#define FLASH_NSSR_PD_Msk (0x1UL << FLASH_NSSR_PD_Pos) /*!< 0x00100000 */ +#define FLASH_NSSR_PD FLASH_NSSR_PD_Msk /*!< Flash in power-down mode */ + +/****************** Bits definition for FLASH_SECSR register ****************/ +#define FLASH_SECSR_EOP_Pos (0U) +#define FLASH_SECSR_EOP_Msk (0x1UL << FLASH_SECSR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_SECSR_EOP FLASH_SECSR_EOP_Msk /*!< Secure end of operation */ +#define FLASH_SECSR_OPERR_Pos (1U) +#define FLASH_SECSR_OPERR_Msk (0x1UL << FLASH_SECSR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_SECSR_OPERR FLASH_SECSR_OPERR_Msk /*!< Secure operation error */ +#define FLASH_SECSR_PROGERR_Pos (3U) +#define FLASH_SECSR_PROGERR_Msk (0x1UL << FLASH_SECSR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_SECSR_PROGERR FLASH_SECSR_PROGERR_Msk /*!< Secure programming error */ +#define FLASH_SECSR_WRPERR_Pos (4U) +#define FLASH_SECSR_WRPERR_Msk (0x1UL << FLASH_SECSR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_SECSR_WRPERR FLASH_SECSR_WRPERR_Msk /*!< Secure write protection error */ +#define FLASH_SECSR_PGAERR_Pos (5U) +#define FLASH_SECSR_PGAERR_Msk (0x1UL << FLASH_SECSR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_SECSR_PGAERR FLASH_SECSR_PGAERR_Msk /*!< Secure programming alignment error */ +#define FLASH_SECSR_SIZERR_Pos (6U) +#define FLASH_SECSR_SIZERR_Msk (0x1UL << FLASH_SECSR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_SECSR_SIZERR FLASH_SECSR_SIZERR_Msk /*!< Secure size error */ +#define FLASH_SECSR_PGSERR_Pos (7U) +#define FLASH_SECSR_PGSERR_Msk (0x1UL << FLASH_SECSR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_SECSR_PGSERR FLASH_SECSR_PGSERR_Msk /*!< Secure programming sequence error */ +#define FLASH_SECSR_BSY_Pos (16U) +#define FLASH_SECSR_BSY_Msk (0x1UL << FLASH_SECSR_BSY_Pos) /*!< 0x00010000 */ +#define FLASH_SECSR_BSY FLASH_SECSR_BSY_Msk /*!< Secure busy */ +#define FLASH_SECSR_WDW_Pos (17U) +#define FLASH_SECSR_WDW_Msk (0x1UL << FLASH_SECSR_WDW_Pos) /*!< 0x00020000 */ +#define FLASH_SECSR_WDW FLASH_SECSR_WDW_Msk /*!< Secure wait data to write */ + +/****************** Bits definition for FLASH_NSCR1 register *****************/ +#define FLASH_NSCR1_PG_Pos (0U) +#define FLASH_NSCR1_PG_Msk (0x1UL << FLASH_NSCR1_PG_Pos) /*!< 0x00000001 */ +#define FLASH_NSCR1_PG FLASH_NSCR1_PG_Msk /*!< Non-secure Programming */ +#define FLASH_NSCR1_PER_Pos (1U) +#define FLASH_NSCR1_PER_Msk (0x1UL << FLASH_NSCR1_PER_Pos) /*!< 0x00000002 */ +#define FLASH_NSCR1_PER FLASH_NSCR1_PER_Msk /*!< Non-secure Page Erase */ +#define FLASH_NSCR1_MER_Pos (2U) +#define FLASH_NSCR1_MER_Msk (0x1UL << FLASH_NSCR1_MER_Pos) /*!< 0x00000004 */ +#define FLASH_NSCR1_MER FLASH_NSCR1_MER_Msk /*!< Non-secure Mass Erase */ +#define FLASH_NSCR1_PNB_Pos (3U) +#define FLASH_NSCR1_PNB_Msk (0x7FUL << FLASH_NSCR1_PNB_Pos) /*!< 0x000003F8 */ +#define FLASH_NSCR1_PNB FLASH_NSCR1_PNB_Msk /*!< Non-secure Page Number selection */ +#define FLASH_NSCR1_BWR_Pos (14U) +#define FLASH_NSCR1_BWR_Msk (0x1UL << FLASH_NSCR1_BWR_Pos) /*!< 0x00004000 */ +#define FLASH_NSCR1_BWR FLASH_NSCR1_BWR_Msk /*!< Non-secure Burst Write Programming mode */ +#define FLASH_NSCR1_STRT_Pos (16U) +#define FLASH_NSCR1_STRT_Msk (0x1UL << FLASH_NSCR1_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_NSCR1_STRT FLASH_NSCR1_STRT_Msk /*!< Non-secure Start */ +#define FLASH_NSCR1_OPTSTRT_Pos (17U) +#define FLASH_NSCR1_OPTSTRT_Msk (0x1UL << FLASH_NSCR1_OPTSTRT_Pos) /*!< 0x00020000 */ +#define FLASH_NSCR1_OPTSTRT FLASH_NSCR1_OPTSTRT_Msk /*!< Option Modification Start */ +#define FLASH_NSCR1_EOPIE_Pos (24U) +#define FLASH_NSCR1_EOPIE_Msk (0x1UL << FLASH_NSCR1_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_NSCR1_EOPIE FLASH_NSCR1_EOPIE_Msk /*!< Non-secure End of operation interrupt enable */ +#define FLASH_NSCR1_ERRIE_Pos (25U) +#define FLASH_NSCR1_ERRIE_Msk (0x1UL << FLASH_NSCR1_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_NSCR1_ERRIE FLASH_NSCR1_ERRIE_Msk /*!< Non-secure error interrupt enable */ +#define FLASH_NSCR1_OBL_LAUNCH_Pos (27U) +#define FLASH_NSCR1_OBL_LAUNCH_Msk (0x1UL << FLASH_NSCR1_OBL_LAUNCH_Pos) /*!< 0x08000000 */ +#define FLASH_NSCR1_OBL_LAUNCH FLASH_NSCR1_OBL_LAUNCH_Msk /*!< Force the option byte loading */ +#define FLASH_NSCR1_OPTLOCK_Pos (30U) +#define FLASH_NSCR1_OPTLOCK_Msk (0x1UL << FLASH_NSCR1_OPTLOCK_Pos) /*!< 0x40000000 */ +#define FLASH_NSCR1_OPTLOCK FLASH_NSCR1_OPTLOCK_Msk /*!< Option Lock */ +#define FLASH_NSCR1_LOCK_Pos (31U) +#define FLASH_NSCR1_LOCK_Msk (0x1UL << FLASH_NSCR1_LOCK_Pos) /*!< 0x80000000 */ +#define FLASH_NSCR1_LOCK FLASH_NSCR1_LOCK_Msk /*!< Non-secure Lock */ + +/****************** Bits definition for FLASH_SECCR1 register ****************/ +#define FLASH_SECCR1_PG_Pos (0U) +#define FLASH_SECCR1_PG_Msk (0x1UL << FLASH_SECCR1_PG_Pos) /*!< 0x00000001 */ +#define FLASH_SECCR1_PG FLASH_SECCR1_PG_Msk /*!< Secure Programming */ +#define FLASH_SECCR1_PER_Pos (1U) +#define FLASH_SECCR1_PER_Msk (0x1UL << FLASH_SECCR1_PER_Pos) /*!< 0x00000002 */ +#define FLASH_SECCR1_PER FLASH_SECCR1_PER_Msk /*!< Secure Page Erase */ +#define FLASH_SECCR1_MER_Pos (2U) +#define FLASH_SECCR1_MER_Msk (0x1UL << FLASH_SECCR1_MER_Pos) /*!< 0x00000004 */ +#define FLASH_SECCR1_MER FLASH_SECCR1_MER_Msk /*!< Secure Bank 1 Mass Erase */ +#define FLASH_SECCR1_PNB_Pos (3U) +#define FLASH_SECCR1_PNB_Msk (0x7FUL << FLASH_SECCR1_PNB_Pos) /*!< 0x000003F8 */ +#define FLASH_SECCR1_PNB FLASH_SECCR1_PNB_Msk /*!< Secure Page Number selection */ +#define FLASH_SECCR1_BWR_Pos (14U) +#define FLASH_SECCR1_BWR_Msk (0x1UL << FLASH_SECCR1_BWR_Pos) /*!< 0x00004000 */ +#define FLASH_SECCR1_BWR FLASH_SECCR1_BWR_Msk /*!< Secure Burst Write programming mode */ +#define FLASH_SECCR1_STRT_Pos (16U) +#define FLASH_SECCR1_STRT_Msk (0x1UL << FLASH_SECCR1_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_SECCR1_STRT FLASH_SECCR1_STRT_Msk /*!< Secure Start */ +#define FLASH_SECCR1_EOPIE_Pos (24U) +#define FLASH_SECCR1_EOPIE_Msk (0x1UL << FLASH_SECCR1_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_SECCR1_EOPIE FLASH_SECCR1_EOPIE_Msk /*!< Secure end of operation interrupt enable */ +#define FLASH_SECCR1_ERRIE_Pos (25U) +#define FLASH_SECCR1_ERRIE_Msk (0x1UL << FLASH_SECCR1_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_SECCR1_ERRIE FLASH_SECCR1_ERRIE_Msk /*!< Secure error interrupt enable */ +#define FLASH_SECCR1_INV_Pos (29U) +#define FLASH_SECCR1_INV_Msk (0x1UL << FLASH_SECCR1_INV_Pos) /*!< 0x20000000 */ +#define FLASH_SECCR1_INV FLASH_SECCR1_INV_Msk /*!< Flash Security State Invert */ +#define FLASH_SECCR1_LOCK_Pos (31U) +#define FLASH_SECCR1_LOCK_Msk (0x1UL << FLASH_SECCR1_LOCK_Pos) /*!< 0x80000000 */ +#define FLASH_SECCR1_LOCK FLASH_SECCR1_LOCK_Msk /*!< Secure Lock */ + +/******************* Bits definition for FLASH_ECCR register ***************/ +#define FLASH_ECCR_ADDR_ECC_Pos (0U) +#define FLASH_ECCR_ADDR_ECC_Msk (0xFFFFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x000FFFFF */ +#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk /*!< ECC fail address */ +#define FLASH_ECCR_SYSF_ECC_Pos (22U) +#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk /*!< System Flash ECC fail */ +#define FLASH_ECCR_ECCIE_Pos (24U) +#define FLASH_ECCR_ECCIE_Msk (0x1UL << FLASH_ECCR_ECCIE_Pos) /*!< 0x01000000 */ +#define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk /*!< ECC correction interrupt enable */ +#define FLASH_ECCR_ECCC_Pos (30U) +#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */ +#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk /*!< ECC correction */ +#define FLASH_ECCR_ECCD_Pos (31U) +#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */ +#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk /*!< ECC detection */ + +/******************* Bits definition for FLASH_OPSR register ***************/ +#define FLASH_OPSR_ADDR_OP_Pos (0U) +#define FLASH_OPSR_ADDR_OP_Msk (0xFFFFFUL << FLASH_OPSR_ADDR_OP_Pos) /*!< 0x000FFFFF */ +#define FLASH_OPSR_ADDR_OP FLASH_OPSR_ADDR_OP_Msk /*!< Interrupted operation address */ +#define FLASH_OPSR_SYSF_OP_Pos (22U) +#define FLASH_OPSR_SYSF_OP_Msk (0x1UL << FLASH_OPSR_SYSF_OP_Pos) /*!< 0x00400000 */ +#define FLASH_OPSR_SYSF_OP FLASH_OPSR_SYSF_OP_Msk /*!< Operation in system Flash memory interrupted */ +#define FLASH_OPSR_CODE_OP_Pos (29U) +#define FLASH_OPSR_CODE_OP_Msk (0x7UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x07000000 */ +#define FLASH_OPSR_CODE_OP FLASH_OPSR_CODE_OP_Msk /*!< Flash memory operation code */ +#define FLASH_OPSR_CODE_OP_0 (0x1UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x01000000 */ +#define FLASH_OPSR_CODE_OP_1 (0x2UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x02000000 */ +#define FLASH_OPSR_CODE_OP_2 (0x4UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x04000000 */ + +/******************* Bits definition for FLASH_NSCR2 register ***************/ +#define FLASH_NSCR2_PS_Pos (0U) +#define FLASH_NSCR2_PS_Msk (0x1UL << FLASH_NSCR2_PS_Pos) /*!< 0x00000001 */ +#define FLASH_NSCR2_PS FLASH_NSCR2_PS_Msk /*!< Program suspend request */ +#define FLASH_NSCR2_ES_Pos (1U) +#define FLASH_NSCR2_ES_Msk (0x1UL << FLASH_NSCR2_ES_Pos) /*!< 0x00000002 */ +#define FLASH_NSCR2_ES FLASH_NSCR2_ES_Msk /*!< Erase suspend request */ + +/******************* Bits definition for FLASH_SECCR2 register ***************/ +#define FLASH_SECCR2_PS_Pos (0U) +#define FLASH_SECCR2_PS_Msk (0x1UL << FLASH_SECCR2_PS_Pos) /*!< 0x00000001 */ +#define FLASH_SECCR2_PS FLASH_SECCR2_PS_Msk /*!< Program suspend request */ +#define FLASH_SECCR2_ES_Pos (1U) +#define FLASH_SECCR2_ES_Msk (0x1UL << FLASH_SECCR2_ES_Pos) /*!< 0x00000002 */ +#define FLASH_SECCR2_ES FLASH_SECCR2_ES_Msk /*!< Erase suspend request */ + +/******************* Bits definition for FLASH_OPTR register ***************/ +#define FLASH_OPTR_RDP_Pos (0U) +#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */ +#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk /*!< Readout protection level */ +#define FLASH_OPTR_BOR_LEV_Pos (8U) +#define FLASH_OPTR_BOR_LEV_Msk (0x7UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000700 */ +#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR reset Level */ +#define FLASH_OPTR_BOR_LEV_0 (0x1UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000100 */ +#define FLASH_OPTR_BOR_LEV_1 (0x2UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000200 */ +#define FLASH_OPTR_BOR_LEV_2 (0x4UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000400 */ +#define FLASH_OPTR_nRST_STOP_Pos (12U) +#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00001000 */ +#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< nRST_STOP */ +#define FLASH_OPTR_nRST_STDBY_Pos (13U) +#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */ +#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< nRST_STDBY */ +#define FLASH_OPTR_SRAM1_RST_Pos (15U) +#define FLASH_OPTR_SRAM1_RST_Msk (0x1UL << FLASH_OPTR_SRAM1_RST_Pos) /*!< 0x00008000 */ +#define FLASH_OPTR_SRAM1_RST FLASH_OPTR_SRAM1_RST_Msk /*!< SRAM1 erase upon system reset */ +#define FLASH_OPTR_IWDG_SW_Pos (16U) +#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */ +#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< Independent watchdog selection */ +#define FLASH_OPTR_IWDG_STOP_Pos (17U) +#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */ +#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk /*!< Independent watchdog counter freeze in Stop mode */ +#define FLASH_OPTR_IWDG_STDBY_Pos (18U) +#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */ +#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk /*!< Independent watchdog counter freeze in Standby mode */ +#define FLASH_OPTR_WWDG_SW_Pos (19U) +#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */ +#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk /*!< Window watchdog selection */ +#define FLASH_OPTR_SRAM2_PE_Pos (24U) +#define FLASH_OPTR_SRAM2_PE_Msk (0x1UL << FLASH_OPTR_SRAM2_PE_Pos) /*!< 0x01000000 */ +#define FLASH_OPTR_SRAM2_PE FLASH_OPTR_SRAM2_PE_Msk /*!< SRAM2 ECC detection and correction enable*/ +#define FLASH_OPTR_SRAM2_RST_Pos (25U) +#define FLASH_OPTR_SRAM2_RST_Msk (0x1UL << FLASH_OPTR_SRAM2_RST_Pos) /*!< 0x02000000 */ +#define FLASH_OPTR_SRAM2_RST FLASH_OPTR_SRAM2_RST_Msk /*!< SRAM2 erase when system reset */ +#define FLASH_OPTR_nSWBOOT0_Pos (26U) +#define FLASH_OPTR_nSWBOOT0_Msk (0x1UL << FLASH_OPTR_nSWBOOT0_Pos) /*!< 0x04000000 */ +#define FLASH_OPTR_nSWBOOT0 FLASH_OPTR_nSWBOOT0_Msk /*!< Software BOOT0 */ +#define FLASH_OPTR_nBOOT0_Pos (27U) +#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x08000000 */ +#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk /*!< nBOOT0 option bit */ +#define FLASH_OPTR_TZEN_Pos (31U) +#define FLASH_OPTR_TZEN_Msk (0x1UL << FLASH_OPTR_TZEN_Pos) /*!< 0x80000000 */ +#define FLASH_OPTR_TZEN FLASH_OPTR_TZEN_Msk /*!< Global TrustZone security enable */ + +/**************** Bits definition for FLASH_NSBOOTADD0R register ************/ +#define FLASH_NSBOOTADD0R_NSBOOTADD0_Pos (7U) +#define FLASH_NSBOOTADD0R_NSBOOTADD0_Msk (0x1FFFFFFUL << FLASH_NSBOOTADD0R_NSBOOTADD0_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_NSBOOTADD0R_NSBOOTADD0 FLASH_NSBOOTADD0R_NSBOOTADD0_Msk /*!< Non-secure boot address 0 */ + +/**************** Bits definition for FLASH_NSBOOTADD1R register ************/ +#define FLASH_NSBOOTADD1R_NSBOOTADD1_Pos (7U) +#define FLASH_NSBOOTADD1R_NSBOOTADD1_Msk (0x1FFFFFFUL << FLASH_NSBOOTADD1R_NSBOOTADD1_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_NSBOOTADD1R_NSBOOTADD1 FLASH_NSBOOTADD1R_NSBOOTADD1_Msk /*!< Non-secure boot address 1 */ + +/**************** Bits definition for FLASH_SECBOOTADD0R register ***********/ +#define FLASH_SECBOOTADD0R_BOOT_LOCK_Pos (0U) +#define FLASH_SECBOOTADD0R_BOOT_LOCK_Msk (0x1UL << FLASH_SECBOOTADD0R_BOOT_LOCK_Pos) /*!< 0x00000001 */ +#define FLASH_SECBOOTADD0R_BOOT_LOCK FLASH_SECBOOTADD0R_BOOT_LOCK_Msk /*!< Boot Lock */ +#define FLASH_SECBOOTADD0R_SECBOOTADD0_Pos (7U) +#define FLASH_SECBOOTADD0R_SECBOOTADD0_Msk (0x1FFFFFFUL << FLASH_SECBOOTADD0R_SECBOOTADD0_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_SECBOOTADD0R_SECBOOTADD0 FLASH_SECBOOTADD0R_SECBOOTADD0_Msk /*!< Secure boot address 0 */ + +/***************** Bits definition for FLASH_SECWMR1 register **************/ +#define FLASH_SECWMR1_SECWM_PSTRT_Pos (0U) +#define FLASH_SECWMR1_SECWM_PSTRT_Msk (0x7FUL << FLASH_SECWMR1_SECWM_PSTRT_Pos) /*!< 0x0000007F */ +#define FLASH_SECWMR1_SECWM_PSTRT FLASH_SECWMR1_SECWM_PSTRT_Msk /*!< Start page of first secure area */ +#define FLASH_SECWMR1_SECWM_PEND_Pos (16U) +#define FLASH_SECWMR1_SECWM_PEND_Msk (0x7FUL << FLASH_SECWMR1_SECWM_PEND_Pos) /*!< 0x007F0000 */ +#define FLASH_SECWMR1_SECWM_PEND FLASH_SECWMR1_SECWM_PEND_Msk /*!< End page of first secure area */ + +/***************** Bits definition for FLASH_SECWMR2 register **************/ +#define FLASH_SECWMR2_HDP_PEND_Pos (16U) +#define FLASH_SECWMR2_HDP_PEND_Msk (0x7FUL << FLASH_SECWMR2_HDP_PEND_Pos) /*!< 0x007F0000 */ +#define FLASH_SECWMR2_HDP_PEND FLASH_SECWMR2_HDP_PEND_Msk /*!< End page of first hide protection area */ +#define FLASH_SECWMR2_HDPEN_Pos (31U) +#define FLASH_SECWMR2_HDPEN_Msk (0x1UL << FLASH_SECWMR2_HDPEN_Pos) /*!< 0x80000000 */ +#define FLASH_SECWMR2_HDPEN FLASH_SECWMR2_HDPEN_Msk /*!< Hide protection first area enable */ + +/****************** Bits definition for FLASH_WRPAR register ***************/ +#define FLASH_WRPAR_WRPA_PSTRT_Pos (0U) +#define FLASH_WRPAR_WRPA_PSTRT_Msk (0x7FUL << FLASH_WRPAR_WRPA_PSTRT_Pos) /*!< 0x0000007F */ +#define FLASH_WRPAR_WRPA_PSTRT FLASH_WRPAR_WRPA_PSTRT_Msk /*!< WPR first area A start page */ +#define FLASH_WRPAR_WRPA_PEND_Pos (16U) +#define FLASH_WRPAR_WRPA_PEND_Msk (0x7FUL << FLASH_WRPAR_WRPA_PEND_Pos) /*!< 0x007F0000 */ +#define FLASH_WRPAR_WRPA_PEND FLASH_WRPAR_WRPA_PEND_Msk /*!< WPR first area A end page */ +#define FLASH_WRPAR_UNLOCK_Pos (31U) +#define FLASH_WRPAR_UNLOCK_Msk (0x1UL << FLASH_WRPAR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRPAR_UNLOCK FLASH_WRPAR_UNLOCK_Msk /*!< WPR first area A unlock */ + +/****************** Bits definition for FLASH_WRPBR register ***************/ +#define FLASH_WRPBR_WRPB_PSTRT_Pos (0U) +#define FLASH_WRPBR_WRPB_PSTRT_Msk (0x7FUL << FLASH_WRPBR_WRPB_PSTRT_Pos) /*!< 0x0000007F */ +#define FLASH_WRPBR_WRPB_PSTRT FLASH_WRPBR_WRPB_PSTRT_Msk /*!< WPR second area B start page */ +#define FLASH_WRPBR_WRPB_PEND_Pos (16U) +#define FLASH_WRPBR_WRPB_PEND_Msk (0x7FUL << FLASH_WRPBR_WRPB_PEND_Pos) /*!< 0x007F0000 */ +#define FLASH_WRPBR_WRPB_PEND FLASH_WRPBR_WRPB_PEND_Msk /*!< WPR second area B end page */ +#define FLASH_WRPBR_UNLOCK_Pos (31U) +#define FLASH_WRPBR_UNLOCK_Msk (0x1UL << FLASH_WRPBR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRPBR_UNLOCK FLASH_WRPBR_UNLOCK_Msk /*!< WPR first area B unlock */ + +/****************** Bits definition for FLASH_OEM1KEYR1 register *****************/ +#define FLASH_OEM1KEYR1_OEM1KEY_Pos (0U) +#define FLASH_OEM1KEYR1_OEM1KEY_Msk (0xFFFFFFFFUL << FLASH_OEM1KEYR1_OEM1KEY_Pos) /*!< 0xFFFFFFFFF */ +#define FLASH_OEM1KEYR1_OEM1KEY FLASH_OEM1KEYR1_OEM1KEY_Msk /*!< OEM1 least significant bytes key */ + +/****************** Bits definition for FLASH_OEM1KEYR2 register *****************/ +#define FLASH_OEM1KEYR2_OEM1KEY_Pos (0U) +#define FLASH_OEM1KEYR2_OEM1KEY_Msk (0xFFFFFFFFUL << FLASH_OEM1KEYR2_OEM1KEY_Pos) /*!< 0xFFFFFFFFF */ +#define FLASH_OEM1KEYR2_OEM1KEY FLASH_OEM1KEYR2_OEM1KEY_Msk /*!< OEM1 most significant bytes key */ + +/****************** Bits definition for FLASH_OEM2KEYR1 register *****************/ +#define FLASH_OEM2KEYR1_OEM2KEY_Pos (0U) +#define FLASH_OEM2KEYR1_OEM2KEY_Msk (0xFFFFFFFFUL << FLASH_OEM2KEYR1_OEM2KEY_Pos) /*!< 0xFFFFFFFFF */ +#define FLASH_OEM2KEYR1_OEM2KEY FLASH_OEM2KEYR1_OEM2KEY_Msk /*!< OEM2 least significant bytes key */ + +/****************** Bits definition for FLASH_OEM2KEYR2 register *****************/ +#define FLASH_OEM2KEYR2_OEM2KEY_Pos (0U) +#define FLASH_OEM2KEYR2_OEM2KEY_Msk (0xFFFFFFFFUL << FLASH_OEM2KEYR2_OEM2KEY_Pos) /*!< 0xFFFFFFFFF */ +#define FLASH_OEM2KEYR2_OEM2KEY FLASH_OEM2KEYR2_OEM2KEY_Msk /*!< OEM2 most significant bytes key */ + +/******************* Bit definition for FLASH_SECBBR1 register ******************/ +#define FLASH_SECBBR1_SECBB0_Pos (0U) +#define FLASH_SECBBR1_SECBB0_Msk (0x1UL << FLASH_SECBBR1_SECBB0_Pos) /*!< 0x00000001 */ +#define FLASH_SECBBR1_SECBB0 FLASH_SECBBR1_SECBB0_Msk /*!< Page 0 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB1_Pos (1U) +#define FLASH_SECBBR1_SECBB1_Msk (0x1UL << FLASH_SECBBR1_SECBB1_Pos) /*!< 0x00000002 */ +#define FLASH_SECBBR1_SECBB1 FLASH_SECBBR1_SECBB1_Msk /*!< Page 1 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB2_Pos (2U) +#define FLASH_SECBBR1_SECBB2_Msk (0x1UL << FLASH_SECBBR1_SECBB2_Pos) /*!< 0x00000004 */ +#define FLASH_SECBBR1_SECBB2 FLASH_SECBBR1_SECBB2_Msk /*!< Page 2 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB3_Pos (3U) +#define FLASH_SECBBR1_SECBB3_Msk (0x1UL << FLASH_SECBBR1_SECBB3_Pos) /*!< 0x00000008 */ +#define FLASH_SECBBR1_SECBB3 FLASH_SECBBR1_SECBB3_Msk /*!< Page 3 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB4_Pos (4U) +#define FLASH_SECBBR1_SECBB4_Msk (0x1UL << FLASH_SECBBR1_SECBB4_Pos) /*!< 0x00000010 */ +#define FLASH_SECBBR1_SECBB4 FLASH_SECBBR1_SECBB4_Msk /*!< Page 4 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB5_Pos (5U) +#define FLASH_SECBBR1_SECBB5_Msk (0x1UL << FLASH_SECBBR1_SECBB5_Pos) /*!< 0x00000020 */ +#define FLASH_SECBBR1_SECBB5 FLASH_SECBBR1_SECBB5_Msk /*!< Page 5 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB6_Pos (6U) +#define FLASH_SECBBR1_SECBB6_Msk (0x1UL << FLASH_SECBBR1_SECBB6_Pos) /*!< 0x00000040 */ +#define FLASH_SECBBR1_SECBB6 FLASH_SECBBR1_SECBB6_Msk /*!< Page 6 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB7_Pos (7U) +#define FLASH_SECBBR1_SECBB7_Msk (0x1UL << FLASH_SECBBR1_SECBB7_Pos) /*!< 0x00000080 */ +#define FLASH_SECBBR1_SECBB7 FLASH_SECBBR1_SECBB7_Msk /*!< Page 7 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB8_Pos (8U) +#define FLASH_SECBBR1_SECBB8_Msk (0x1UL << FLASH_SECBBR1_SECBB8_Pos) /*!< 0x00000100 */ +#define FLASH_SECBBR1_SECBB8 FLASH_SECBBR1_SECBB8_Msk /*!< Page 8 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB9_Pos (9U) +#define FLASH_SECBBR1_SECBB9_Msk (0x1UL << FLASH_SECBBR1_SECBB9_Pos) /*!< 0x00000200 */ +#define FLASH_SECBBR1_SECBB9 FLASH_SECBBR1_SECBB9_Msk /*!< Page 9 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB10_Pos (10U) +#define FLASH_SECBBR1_SECBB10_Msk (0x1UL << FLASH_SECBBR1_SECBB10_Pos) /*!< 0x00000400 */ +#define FLASH_SECBBR1_SECBB10 FLASH_SECBBR1_SECBB10_Msk /*!< Page 10 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB11_Pos (11U) +#define FLASH_SECBBR1_SECBB11_Msk (0x1UL << FLASH_SECBBR1_SECBB11_Pos) /*!< 0x00000800 */ +#define FLASH_SECBBR1_SECBB11 FLASH_SECBBR1_SECBB11_Msk /*!< Page 11 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB12_Pos (12U) +#define FLASH_SECBBR1_SECBB12_Msk (0x1UL << FLASH_SECBBR1_SECBB12_Pos) /*!< 0x00001000 */ +#define FLASH_SECBBR1_SECBB12 FLASH_SECBBR1_SECBB12_Msk /*!< Page 12 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB13_Pos (13U) +#define FLASH_SECBBR1_SECBB13_Msk (0x1UL << FLASH_SECBBR1_SECBB13_Pos) /*!< 0x00002000 */ +#define FLASH_SECBBR1_SECBB13 FLASH_SECBBR1_SECBB13_Msk /*!< Page 13 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB14_Pos (14U) +#define FLASH_SECBBR1_SECBB14_Msk (0x1UL << FLASH_SECBBR1_SECBB14_Pos) /*!< 0x00004000 */ +#define FLASH_SECBBR1_SECBB14 FLASH_SECBBR1_SECBB14_Msk /*!< Page 14 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB15_Pos (15U) +#define FLASH_SECBBR1_SECBB15_Msk (0x1UL << FLASH_SECBBR1_SECBB15_Pos) /*!< 0x00008000 */ +#define FLASH_SECBBR1_SECBB15 FLASH_SECBBR1_SECBB15_Msk /*!< Page 15 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB16_Pos (16U) +#define FLASH_SECBBR1_SECBB16_Msk (0x1UL << FLASH_SECBBR1_SECBB16_Pos) /*!< 0x00010000 */ +#define FLASH_SECBBR1_SECBB16 FLASH_SECBBR1_SECBB16_Msk /*!< Page 16 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB17_Pos (17U) +#define FLASH_SECBBR1_SECBB17_Msk (0x1UL << FLASH_SECBBR1_SECBB17_Pos) /*!< 0x00020000 */ +#define FLASH_SECBBR1_SECBB17 FLASH_SECBBR1_SECBB17_Msk /*!< Page 17 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB18_Pos (18U) +#define FLASH_SECBBR1_SECBB18_Msk (0x1UL << FLASH_SECBBR1_SECBB18_Pos) /*!< 0x00040000 */ +#define FLASH_SECBBR1_SECBB18 FLASH_SECBBR1_SECBB18_Msk /*!< Page 18 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB19_Pos (19U) +#define FLASH_SECBBR1_SECBB19_Msk (0x1UL << FLASH_SECBBR1_SECBB19_Pos) /*!< 0x00080000 */ +#define FLASH_SECBBR1_SECBB19 FLASH_SECBBR1_SECBB19_Msk /*!< Page 19 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB20_Pos (20U) +#define FLASH_SECBBR1_SECBB20_Msk (0x1UL << FLASH_SECBBR1_SECBB20_Pos) /*!< 0x00100000 */ +#define FLASH_SECBBR1_SECBB20 FLASH_SECBBR1_SECBB20_Msk /*!< Page 20 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB21_Pos (21U) +#define FLASH_SECBBR1_SECBB21_Msk (0x1UL << FLASH_SECBBR1_SECBB21_Pos) /*!< 0x00200000 */ +#define FLASH_SECBBR1_SECBB21 FLASH_SECBBR1_SECBB21_Msk /*!< Page 21 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB22_Pos (22U) +#define FLASH_SECBBR1_SECBB22_Msk (0x1UL << FLASH_SECBBR1_SECBB22_Pos) /*!< 0x00400000 */ +#define FLASH_SECBBR1_SECBB22 FLASH_SECBBR1_SECBB22_Msk /*!< Page 22 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB23_Pos (23U) +#define FLASH_SECBBR1_SECBB23_Msk (0x1UL << FLASH_SECBBR1_SECBB23_Pos) /*!< 0x00800000 */ +#define FLASH_SECBBR1_SECBB23 FLASH_SECBBR1_SECBB23_Msk /*!< Page 23 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB24_Pos (24U) +#define FLASH_SECBBR1_SECBB24_Msk (0x1UL << FLASH_SECBBR1_SECBB24_Pos) /*!< 0x01000000 */ +#define FLASH_SECBBR1_SECBB24 FLASH_SECBBR1_SECBB24_Msk /*!< Page 24 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB25_Pos (25U) +#define FLASH_SECBBR1_SECBB25_Msk (0x1UL << FLASH_SECBBR1_SECBB25_Pos) /*!< 0x02000000 */ +#define FLASH_SECBBR1_SECBB25 FLASH_SECBBR1_SECBB25_Msk /*!< Page 25 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB26_Pos (26U) +#define FLASH_SECBBR1_SECBB26_Msk (0x1UL << FLASH_SECBBR1_SECBB26_Pos) /*!< 0x04000000 */ +#define FLASH_SECBBR1_SECBB26 FLASH_SECBBR1_SECBB26_Msk /*!< Page 26 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB27_Pos (27U) +#define FLASH_SECBBR1_SECBB27_Msk (0x1UL << FLASH_SECBBR1_SECBB27_Pos) /*!< 0x08000000 */ +#define FLASH_SECBBR1_SECBB27 FLASH_SECBBR1_SECBB27_Msk /*!< Page 27 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB28_Pos (28U) +#define FLASH_SECBBR1_SECBB28_Msk (0x1UL << FLASH_SECBBR1_SECBB28_Pos) /*!< 0x10000000 */ +#define FLASH_SECBBR1_SECBB28 FLASH_SECBBR1_SECBB28_Msk /*!< Page 28 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB29_Pos (29U) +#define FLASH_SECBBR1_SECBB29_Msk (0x1UL << FLASH_SECBBR1_SECBB29_Pos) /*!< 0x20000000 */ +#define FLASH_SECBBR1_SECBB29 FLASH_SECBBR1_SECBB29_Msk /*!< Page 29 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB30_Pos (30U) +#define FLASH_SECBBR1_SECBB30_Msk (0x1UL << FLASH_SECBBR1_SECBB30_Pos) /*!< 0x40000000 */ +#define FLASH_SECBBR1_SECBB30 FLASH_SECBBR1_SECBB30_Msk /*!< Page 30 in Flash block-based secure */ +#define FLASH_SECBBR1_SECBB31_Pos (31U) +#define FLASH_SECBBR1_SECBB31_Msk (0x1UL << FLASH_SECBBR1_SECBB31_Pos) /*!< 0x80000000 */ +#define FLASH_SECBBR1_SECBB31 FLASH_SECBBR1_SECBB31_Msk /*!< Page 31 in Flash block-based secure */ + +/******************* Bit definition for FLASH_SECBBR2 register ******************/ +#define FLASH_SECBBR2_SECBB0_Pos (0U) +#define FLASH_SECBBR2_SECBB0_Msk (0x1UL << FLASH_SECBBR2_SECBB0_Pos) /*!< 0x00000001 */ +#define FLASH_SECBBR2_SECBB0 FLASH_SECBBR2_SECBB0_Msk /*!< Page 32 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB1_Pos (1U) +#define FLASH_SECBBR2_SECBB1_Msk (0x1UL << FLASH_SECBBR2_SECBB1_Pos) /*!< 0x00000002 */ +#define FLASH_SECBBR2_SECBB1 FLASH_SECBBR2_SECBB1_Msk /*!< Page 33 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB2_Pos (2U) +#define FLASH_SECBBR2_SECBB2_Msk (0x1UL << FLASH_SECBBR2_SECBB2_Pos) /*!< 0x00000004 */ +#define FLASH_SECBBR2_SECBB2 FLASH_SECBBR2_SECBB2_Msk /*!< Page 34 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB3_Pos (3U) +#define FLASH_SECBBR2_SECBB3_Msk (0x1UL << FLASH_SECBBR2_SECBB3_Pos) /*!< 0x00000008 */ +#define FLASH_SECBBR2_SECBB3 FLASH_SECBBR2_SECBB3_Msk /*!< Page 35 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB4_Pos (4U) +#define FLASH_SECBBR2_SECBB4_Msk (0x1UL << FLASH_SECBBR2_SECBB4_Pos) /*!< 0x00000010 */ +#define FLASH_SECBBR2_SECBB4 FLASH_SECBBR2_SECBB4_Msk /*!< Page 36 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB5_Pos (5U) +#define FLASH_SECBBR2_SECBB5_Msk (0x1UL << FLASH_SECBBR2_SECBB5_Pos) /*!< 0x00000020 */ +#define FLASH_SECBBR2_SECBB5 FLASH_SECBBR2_SECBB5_Msk /*!< Page 37 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB6_Pos (6U) +#define FLASH_SECBBR2_SECBB6_Msk (0x1UL << FLASH_SECBBR2_SECBB6_Pos) /*!< 0x00000040 */ +#define FLASH_SECBBR2_SECBB6 FLASH_SECBBR2_SECBB6_Msk /*!< Page 38 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB7_Pos (7U) +#define FLASH_SECBBR2_SECBB7_Msk (0x1UL << FLASH_SECBBR2_SECBB7_Pos) /*!< 0x00000080 */ +#define FLASH_SECBBR2_SECBB7 FLASH_SECBBR2_SECBB7_Msk /*!< Page 39 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB8_Pos (8U) +#define FLASH_SECBBR2_SECBB8_Msk (0x1UL << FLASH_SECBBR2_SECBB8_Pos) /*!< 0x00000100 */ +#define FLASH_SECBBR2_SECBB8 FLASH_SECBBR2_SECBB8_Msk /*!< Page 40 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB9_Pos (9U) +#define FLASH_SECBBR2_SECBB9_Msk (0x1UL << FLASH_SECBBR2_SECBB9_Pos) /*!< 0x00000200 */ +#define FLASH_SECBBR2_SECBB9 FLASH_SECBBR2_SECBB9_Msk /*!< Page 41 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB10_Pos (10U) +#define FLASH_SECBBR2_SECBB10_Msk (0x1UL << FLASH_SECBBR2_SECBB10_Pos) /*!< 0x00000400 */ +#define FLASH_SECBBR2_SECBB10 FLASH_SECBBR2_SECBB10_Msk /*!< Page 42 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB11_Pos (11U) +#define FLASH_SECBBR2_SECBB11_Msk (0x1UL << FLASH_SECBBR2_SECBB11_Pos) /*!< 0x00000800 */ +#define FLASH_SECBBR2_SECBB11 FLASH_SECBBR2_SECBB11_Msk /*!< Page 43 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB12_Pos (12U) +#define FLASH_SECBBR2_SECBB12_Msk (0x1UL << FLASH_SECBBR2_SECBB12_Pos) /*!< 0x00001000 */ +#define FLASH_SECBBR2_SECBB12 FLASH_SECBBR2_SECBB12_Msk /*!< Page 44 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB13_Pos (13U) +#define FLASH_SECBBR2_SECBB13_Msk (0x1UL << FLASH_SECBBR2_SECBB13_Pos) /*!< 0x00002000 */ +#define FLASH_SECBBR2_SECBB13 FLASH_SECBBR2_SECBB13_Msk /*!< Page 45 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB14_Pos (14U) +#define FLASH_SECBBR2_SECBB14_Msk (0x1UL << FLASH_SECBBR2_SECBB14_Pos) /*!< 0x00004000 */ +#define FLASH_SECBBR2_SECBB14 FLASH_SECBBR2_SECBB14_Msk /*!< Page 46 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB15_Pos (15U) +#define FLASH_SECBBR2_SECBB15_Msk (0x1UL << FLASH_SECBBR2_SECBB15_Pos) /*!< 0x00008000 */ +#define FLASH_SECBBR2_SECBB15 FLASH_SECBBR2_SECBB15_Msk /*!< Page 47 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB16_Pos (16U) +#define FLASH_SECBBR2_SECBB16_Msk (0x1UL << FLASH_SECBBR2_SECBB16_Pos) /*!< 0x00010000 */ +#define FLASH_SECBBR2_SECBB16 FLASH_SECBBR2_SECBB16_Msk /*!< Page 48 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB17_Pos (17U) +#define FLASH_SECBBR2_SECBB17_Msk (0x1UL << FLASH_SECBBR2_SECBB17_Pos) /*!< 0x00020000 */ +#define FLASH_SECBBR2_SECBB17 FLASH_SECBBR2_SECBB17_Msk /*!< Page 49 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB18_Pos (18U) +#define FLASH_SECBBR2_SECBB18_Msk (0x1UL << FLASH_SECBBR2_SECBB18_Pos) /*!< 0x00040000 */ +#define FLASH_SECBBR2_SECBB18 FLASH_SECBBR2_SECBB18_Msk /*!< Page 50 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB19_Pos (19U) +#define FLASH_SECBBR2_SECBB19_Msk (0x1UL << FLASH_SECBBR2_SECBB19_Pos) /*!< 0x00080000 */ +#define FLASH_SECBBR2_SECBB19 FLASH_SECBBR2_SECBB19_Msk /*!< Page 51 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB20_Pos (20U) +#define FLASH_SECBBR2_SECBB20_Msk (0x1UL << FLASH_SECBBR2_SECBB20_Pos) /*!< 0x00100000 */ +#define FLASH_SECBBR2_SECBB20 FLASH_SECBBR2_SECBB20_Msk /*!< Page 52 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB21_Pos (21U) +#define FLASH_SECBBR2_SECBB21_Msk (0x1UL << FLASH_SECBBR2_SECBB21_Pos) /*!< 0x00200000 */ +#define FLASH_SECBBR2_SECBB21 FLASH_SECBBR2_SECBB21_Msk /*!< Page 53 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB22_Pos (22U) +#define FLASH_SECBBR2_SECBB22_Msk (0x1UL << FLASH_SECBBR2_SECBB22_Pos) /*!< 0x00400000 */ +#define FLASH_SECBBR2_SECBB22 FLASH_SECBBR2_SECBB22_Msk /*!< Page 54 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB23_Pos (23U) +#define FLASH_SECBBR2_SECBB23_Msk (0x1UL << FLASH_SECBBR2_SECBB23_Pos) /*!< 0x00800000 */ +#define FLASH_SECBBR2_SECBB23 FLASH_SECBBR2_SECBB23_Msk /*!< Page 55 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB24_Pos (24U) +#define FLASH_SECBBR2_SECBB24_Msk (0x1UL << FLASH_SECBBR2_SECBB24_Pos) /*!< 0x01000000 */ +#define FLASH_SECBBR2_SECBB24 FLASH_SECBBR2_SECBB24_Msk /*!< Page 56 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB25_Pos (25U) +#define FLASH_SECBBR2_SECBB25_Msk (0x1UL << FLASH_SECBBR2_SECBB25_Pos) /*!< 0x02000000 */ +#define FLASH_SECBBR2_SECBB25 FLASH_SECBBR2_SECBB25_Msk /*!< Page 57 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB26_Pos (26U) +#define FLASH_SECBBR2_SECBB26_Msk (0x1UL << FLASH_SECBBR2_SECBB26_Pos) /*!< 0x04000000 */ +#define FLASH_SECBBR2_SECBB26 FLASH_SECBBR2_SECBB26_Msk /*!< Page 58 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB27_Pos (27U) +#define FLASH_SECBBR2_SECBB27_Msk (0x1UL << FLASH_SECBBR2_SECBB27_Pos) /*!< 0x08000000 */ +#define FLASH_SECBBR2_SECBB27 FLASH_SECBBR2_SECBB27_Msk /*!< Page 59 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB28_Pos (28U) +#define FLASH_SECBBR2_SECBB28_Msk (0x1UL << FLASH_SECBBR2_SECBB28_Pos) /*!< 0x10000000 */ +#define FLASH_SECBBR2_SECBB28 FLASH_SECBBR2_SECBB28_Msk /*!< Page 60 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB29_Pos (29U) +#define FLASH_SECBBR2_SECBB29_Msk (0x1UL << FLASH_SECBBR2_SECBB29_Pos) /*!< 0x20000000 */ +#define FLASH_SECBBR2_SECBB29 FLASH_SECBBR2_SECBB29_Msk /*!< Page 61 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB30_Pos (30U) +#define FLASH_SECBBR2_SECBB30_Msk (0x1UL << FLASH_SECBBR2_SECBB30_Pos) /*!< 0x40000000 */ +#define FLASH_SECBBR2_SECBB30 FLASH_SECBBR2_SECBB30_Msk /*!< Page 62 in Flash block-based secure */ +#define FLASH_SECBBR2_SECBB31_Pos (31U) +#define FLASH_SECBBR2_SECBB31_Msk (0x1UL << FLASH_SECBBR2_SECBB31_Pos) /*!< 0x80000000 */ +#define FLASH_SECBBR2_SECBB31 FLASH_SECBBR2_SECBB31_Msk /*!< Page 63 in Flash block-based secure */ + +/******************* Bit definition for FLASH_SECBBR3 register ******************/ +#define FLASH_SECBBR3_SECBB0_Pos (0U) +#define FLASH_SECBBR3_SECBB0_Msk (0x1UL << FLASH_SECBBR3_SECBB0_Pos) /*!< 0x00000001 */ +#define FLASH_SECBBR3_SECBB0 FLASH_SECBBR3_SECBB0_Msk /*!< Page 64 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB1_Pos (1U) +#define FLASH_SECBBR3_SECBB1_Msk (0x1UL << FLASH_SECBBR3_SECBB1_Pos) /*!< 0x00000002 */ +#define FLASH_SECBBR3_SECBB1 FLASH_SECBBR3_SECBB1_Msk /*!< Page 65 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB2_Pos (2U) +#define FLASH_SECBBR3_SECBB2_Msk (0x1UL << FLASH_SECBBR3_SECBB2_Pos) /*!< 0x00000004 */ +#define FLASH_SECBBR3_SECBB2 FLASH_SECBBR3_SECBB2_Msk /*!< Page 66 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB3_Pos (3U) +#define FLASH_SECBBR3_SECBB3_Msk (0x1UL << FLASH_SECBBR3_SECBB3_Pos) /*!< 0x00000008 */ +#define FLASH_SECBBR3_SECBB3 FLASH_SECBBR3_SECBB3_Msk /*!< Page 67 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB4_Pos (4U) +#define FLASH_SECBBR3_SECBB4_Msk (0x1UL << FLASH_SECBBR3_SECBB4_Pos) /*!< 0x00000010 */ +#define FLASH_SECBBR3_SECBB4 FLASH_SECBBR3_SECBB4_Msk /*!< Page 68 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB5_Pos (5U) +#define FLASH_SECBBR3_SECBB5_Msk (0x1UL << FLASH_SECBBR3_SECBB5_Pos) /*!< 0x00000020 */ +#define FLASH_SECBBR3_SECBB5 FLASH_SECBBR3_SECBB5_Msk /*!< Page 69 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB6_Pos (6U) +#define FLASH_SECBBR3_SECBB6_Msk (0x1UL << FLASH_SECBBR3_SECBB6_Pos) /*!< 0x00000040 */ +#define FLASH_SECBBR3_SECBB6 FLASH_SECBBR3_SECBB6_Msk /*!< Page 70 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB7_Pos (7U) +#define FLASH_SECBBR3_SECBB7_Msk (0x1UL << FLASH_SECBBR3_SECBB7_Pos) /*!< 0x00000080 */ +#define FLASH_SECBBR3_SECBB7 FLASH_SECBBR3_SECBB7_Msk /*!< Page 71 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB8_Pos (8U) +#define FLASH_SECBBR3_SECBB8_Msk (0x1UL << FLASH_SECBBR3_SECBB8_Pos) /*!< 0x00000100 */ +#define FLASH_SECBBR3_SECBB8 FLASH_SECBBR3_SECBB8_Msk /*!< Page 72 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB9_Pos (9U) +#define FLASH_SECBBR3_SECBB9_Msk (0x1UL << FLASH_SECBBR3_SECBB9_Pos) /*!< 0x00000200 */ +#define FLASH_SECBBR3_SECBB9 FLASH_SECBBR3_SECBB9_Msk /*!< Page 73 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB10_Pos (10U) +#define FLASH_SECBBR3_SECBB10_Msk (0x1UL << FLASH_SECBBR3_SECBB10_Pos) /*!< 0x00000400 */ +#define FLASH_SECBBR3_SECBB10 FLASH_SECBBR3_SECBB10_Msk /*!< Page 74 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB11_Pos (11U) +#define FLASH_SECBBR3_SECBB11_Msk (0x1UL << FLASH_SECBBR3_SECBB11_Pos) /*!< 0x00000800 */ +#define FLASH_SECBBR3_SECBB11 FLASH_SECBBR3_SECBB11_Msk /*!< Page 75 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB12_Pos (12U) +#define FLASH_SECBBR3_SECBB12_Msk (0x1UL << FLASH_SECBBR3_SECBB12_Pos) /*!< 0x00001000 */ +#define FLASH_SECBBR3_SECBB12 FLASH_SECBBR3_SECBB12_Msk /*!< Page 76 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB13_Pos (13U) +#define FLASH_SECBBR3_SECBB13_Msk (0x1UL << FLASH_SECBBR3_SECBB13_Pos) /*!< 0x00002000 */ +#define FLASH_SECBBR3_SECBB13 FLASH_SECBBR3_SECBB13_Msk /*!< Page 77 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB14_Pos (14U) +#define FLASH_SECBBR3_SECBB14_Msk (0x1UL << FLASH_SECBBR3_SECBB14_Pos) /*!< 0x00004000 */ +#define FLASH_SECBBR3_SECBB14 FLASH_SECBBR3_SECBB14_Msk /*!< Page 78 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB15_Pos (15U) +#define FLASH_SECBBR3_SECBB15_Msk (0x1UL << FLASH_SECBBR3_SECBB15_Pos) /*!< 0x00008000 */ +#define FLASH_SECBBR3_SECBB15 FLASH_SECBBR3_SECBB15_Msk /*!< Page 79 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB16_Pos (16U) +#define FLASH_SECBBR3_SECBB16_Msk (0x1UL << FLASH_SECBBR3_SECBB16_Pos) /*!< 0x00010000 */ +#define FLASH_SECBBR3_SECBB16 FLASH_SECBBR3_SECBB16_Msk /*!< Page 80 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB17_Pos (17U) +#define FLASH_SECBBR3_SECBB17_Msk (0x1UL << FLASH_SECBBR3_SECBB17_Pos) /*!< 0x00020000 */ +#define FLASH_SECBBR3_SECBB17 FLASH_SECBBR3_SECBB17_Msk /*!< Page 81 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB18_Pos (18U) +#define FLASH_SECBBR3_SECBB18_Msk (0x1UL << FLASH_SECBBR3_SECBB18_Pos) /*!< 0x00040000 */ +#define FLASH_SECBBR3_SECBB18 FLASH_SECBBR3_SECBB18_Msk /*!< Page 82 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB19_Pos (19U) +#define FLASH_SECBBR3_SECBB19_Msk (0x1UL << FLASH_SECBBR3_SECBB19_Pos) /*!< 0x00080000 */ +#define FLASH_SECBBR3_SECBB19 FLASH_SECBBR3_SECBB19_Msk /*!< Page 83 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB20_Pos (20U) +#define FLASH_SECBBR3_SECBB20_Msk (0x1UL << FLASH_SECBBR3_SECBB20_Pos) /*!< 0x00100000 */ +#define FLASH_SECBBR3_SECBB20 FLASH_SECBBR3_SECBB20_Msk /*!< Page 84 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB21_Pos (21U) +#define FLASH_SECBBR3_SECBB21_Msk (0x1UL << FLASH_SECBBR3_SECBB21_Pos) /*!< 0x00200000 */ +#define FLASH_SECBBR3_SECBB21 FLASH_SECBBR3_SECBB21_Msk /*!< Page 85 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB22_Pos (22U) +#define FLASH_SECBBR3_SECBB22_Msk (0x1UL << FLASH_SECBBR3_SECBB22_Pos) /*!< 0x00400000 */ +#define FLASH_SECBBR3_SECBB22 FLASH_SECBBR3_SECBB22_Msk /*!< Page 86 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB23_Pos (23U) +#define FLASH_SECBBR3_SECBB23_Msk (0x1UL << FLASH_SECBBR3_SECBB23_Pos) /*!< 0x00800000 */ +#define FLASH_SECBBR3_SECBB23 FLASH_SECBBR3_SECBB23_Msk /*!< Page 87 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB24_Pos (24U) +#define FLASH_SECBBR3_SECBB24_Msk (0x1UL << FLASH_SECBBR3_SECBB24_Pos) /*!< 0x01000000 */ +#define FLASH_SECBBR3_SECBB24 FLASH_SECBBR3_SECBB24_Msk /*!< Page 88 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB25_Pos (25U) +#define FLASH_SECBBR3_SECBB25_Msk (0x1UL << FLASH_SECBBR3_SECBB25_Pos) /*!< 0x02000000 */ +#define FLASH_SECBBR3_SECBB25 FLASH_SECBBR3_SECBB25_Msk /*!< Page 89 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB26_Pos (26U) +#define FLASH_SECBBR3_SECBB26_Msk (0x1UL << FLASH_SECBBR3_SECBB26_Pos) /*!< 0x04000000 */ +#define FLASH_SECBBR3_SECBB26 FLASH_SECBBR3_SECBB26_Msk /*!< Page 90 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB27_Pos (27U) +#define FLASH_SECBBR3_SECBB27_Msk (0x1UL << FLASH_SECBBR3_SECBB27_Pos) /*!< 0x08000000 */ +#define FLASH_SECBBR3_SECBB27 FLASH_SECBBR3_SECBB27_Msk /*!< Page 91 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB28_Pos (28U) +#define FLASH_SECBBR3_SECBB28_Msk (0x1UL << FLASH_SECBBR3_SECBB28_Pos) /*!< 0x10000000 */ +#define FLASH_SECBBR3_SECBB28 FLASH_SECBBR3_SECBB28_Msk /*!< Page 92 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB29_Pos (29U) +#define FLASH_SECBBR3_SECBB29_Msk (0x1UL << FLASH_SECBBR3_SECBB29_Pos) /*!< 0x20000000 */ +#define FLASH_SECBBR3_SECBB29 FLASH_SECBBR3_SECBB29_Msk /*!< Page 93 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB30_Pos (30U) +#define FLASH_SECBBR3_SECBB30_Msk (0x1UL << FLASH_SECBBR3_SECBB30_Pos) /*!< 0x40000000 */ +#define FLASH_SECBBR3_SECBB30 FLASH_SECBBR3_SECBB30_Msk /*!< Page 94 in Flash block-based secure */ +#define FLASH_SECBBR3_SECBB31_Pos (31U) +#define FLASH_SECBBR3_SECBB31_Msk (0x1UL << FLASH_SECBBR3_SECBB31_Pos) /*!< 0x80000000 */ +#define FLASH_SECBBR3_SECBB31 FLASH_SECBBR3_SECBB31_Msk /*!< Page 95 in Flash block-based secure */ + +/******************* Bit definition for FLASH_SECBBR4 register ******************/ +#define FLASH_SECBBR4_SECBB0_Pos (0U) +#define FLASH_SECBBR4_SECBB0_Msk (0x1UL << FLASH_SECBBR4_SECBB0_Pos) /*!< 0x00000001 */ +#define FLASH_SECBBR4_SECBB0 FLASH_SECBBR4_SECBB0_Msk /*!< Page 96 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB1_Pos (1U) +#define FLASH_SECBBR4_SECBB1_Msk (0x1UL << FLASH_SECBBR4_SECBB1_Pos) /*!< 0x00000002 */ +#define FLASH_SECBBR4_SECBB1 FLASH_SECBBR4_SECBB1_Msk /*!< Page 97 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB2_Pos (2U) +#define FLASH_SECBBR4_SECBB2_Msk (0x1UL << FLASH_SECBBR4_SECBB2_Pos) /*!< 0x00000004 */ +#define FLASH_SECBBR4_SECBB2 FLASH_SECBBR4_SECBB2_Msk /*!< Page 98 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB3_Pos (3U) +#define FLASH_SECBBR4_SECBB3_Msk (0x1UL << FLASH_SECBBR4_SECBB3_Pos) /*!< 0x00000008 */ +#define FLASH_SECBBR4_SECBB3 FLASH_SECBBR4_SECBB3_Msk /*!< Page 99 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB4_Pos (4U) +#define FLASH_SECBBR4_SECBB4_Msk (0x1UL << FLASH_SECBBR4_SECBB4_Pos) /*!< 0x00000010 */ +#define FLASH_SECBBR4_SECBB4 FLASH_SECBBR4_SECBB4_Msk /*!< Page 100 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB5_Pos (5U) +#define FLASH_SECBBR4_SECBB5_Msk (0x1UL << FLASH_SECBBR4_SECBB5_Pos) /*!< 0x00000020 */ +#define FLASH_SECBBR4_SECBB5 FLASH_SECBBR4_SECBB5_Msk /*!< Page 101 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB6_Pos (6U) +#define FLASH_SECBBR4_SECBB6_Msk (0x1UL << FLASH_SECBBR4_SECBB6_Pos) /*!< 0x00000040 */ +#define FLASH_SECBBR4_SECBB6 FLASH_SECBBR4_SECBB6_Msk /*!< Page 102 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB7_Pos (7U) +#define FLASH_SECBBR4_SECBB7_Msk (0x1UL << FLASH_SECBBR4_SECBB7_Pos) /*!< 0x00000080 */ +#define FLASH_SECBBR4_SECBB7 FLASH_SECBBR4_SECBB7_Msk /*!< Page 103 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB8_Pos (8U) +#define FLASH_SECBBR4_SECBB8_Msk (0x1UL << FLASH_SECBBR4_SECBB8_Pos) /*!< 0x00000100 */ +#define FLASH_SECBBR4_SECBB8 FLASH_SECBBR4_SECBB8_Msk /*!< Page 104 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB9_Pos (9U) +#define FLASH_SECBBR4_SECBB9_Msk (0x1UL << FLASH_SECBBR4_SECBB9_Pos) /*!< 0x00000200 */ +#define FLASH_SECBBR4_SECBB9 FLASH_SECBBR4_SECBB9_Msk /*!< Page 105 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB10_Pos (10U) +#define FLASH_SECBBR4_SECBB10_Msk (0x1UL << FLASH_SECBBR4_SECBB10_Pos) /*!< 0x00000400 */ +#define FLASH_SECBBR4_SECBB10 FLASH_SECBBR4_SECBB10_Msk /*!< Page 106 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB11_Pos (11U) +#define FLASH_SECBBR4_SECBB11_Msk (0x1UL << FLASH_SECBBR4_SECBB11_Pos) /*!< 0x00000800 */ +#define FLASH_SECBBR4_SECBB11 FLASH_SECBBR4_SECBB11_Msk /*!< Page 107 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB12_Pos (12U) +#define FLASH_SECBBR4_SECBB12_Msk (0x1UL << FLASH_SECBBR4_SECBB12_Pos) /*!< 0x00001000 */ +#define FLASH_SECBBR4_SECBB12 FLASH_SECBBR4_SECBB12_Msk /*!< Page 108 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB13_Pos (13U) +#define FLASH_SECBBR4_SECBB13_Msk (0x1UL << FLASH_SECBBR4_SECBB13_Pos) /*!< 0x00002000 */ +#define FLASH_SECBBR4_SECBB13 FLASH_SECBBR4_SECBB13_Msk /*!< Page 109 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB14_Pos (14U) +#define FLASH_SECBBR4_SECBB14_Msk (0x1UL << FLASH_SECBBR4_SECBB14_Pos) /*!< 0x00004000 */ +#define FLASH_SECBBR4_SECBB14 FLASH_SECBBR4_SECBB14_Msk /*!< Page 110 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB15_Pos (15U) +#define FLASH_SECBBR4_SECBB15_Msk (0x1UL << FLASH_SECBBR4_SECBB15_Pos) /*!< 0x00008000 */ +#define FLASH_SECBBR4_SECBB15 FLASH_SECBBR4_SECBB15_Msk /*!< Page 111 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB16_Pos (16U) +#define FLASH_SECBBR4_SECBB16_Msk (0x1UL << FLASH_SECBBR4_SECBB16_Pos) /*!< 0x00010000 */ +#define FLASH_SECBBR4_SECBB16 FLASH_SECBBR4_SECBB16_Msk /*!< Page 112 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB17_Pos (17U) +#define FLASH_SECBBR4_SECBB17_Msk (0x1UL << FLASH_SECBBR4_SECBB17_Pos) /*!< 0x00020000 */ +#define FLASH_SECBBR4_SECBB17 FLASH_SECBBR4_SECBB17_Msk /*!< Page 113 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB18_Pos (18U) +#define FLASH_SECBBR4_SECBB18_Msk (0x1UL << FLASH_SECBBR4_SECBB18_Pos) /*!< 0x00040000 */ +#define FLASH_SECBBR4_SECBB18 FLASH_SECBBR4_SECBB18_Msk /*!< Page 114 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB19_Pos (19U) +#define FLASH_SECBBR4_SECBB19_Msk (0x1UL << FLASH_SECBBR4_SECBB19_Pos) /*!< 0x00080000 */ +#define FLASH_SECBBR4_SECBB19 FLASH_SECBBR4_SECBB19_Msk /*!< Page 115 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB20_Pos (20U) +#define FLASH_SECBBR4_SECBB20_Msk (0x1UL << FLASH_SECBBR4_SECBB20_Pos) /*!< 0x00100000 */ +#define FLASH_SECBBR4_SECBB20 FLASH_SECBBR4_SECBB20_Msk /*!< Page 116 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB21_Pos (21U) +#define FLASH_SECBBR4_SECBB21_Msk (0x1UL << FLASH_SECBBR4_SECBB21_Pos) /*!< 0x00200000 */ +#define FLASH_SECBBR4_SECBB21 FLASH_SECBBR4_SECBB21_Msk /*!< Page 117 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB22_Pos (22U) +#define FLASH_SECBBR4_SECBB22_Msk (0x1UL << FLASH_SECBBR4_SECBB22_Pos) /*!< 0x00400000 */ +#define FLASH_SECBBR4_SECBB22 FLASH_SECBBR4_SECBB22_Msk /*!< Page 118 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB23_Pos (23U) +#define FLASH_SECBBR4_SECBB23_Msk (0x1UL << FLASH_SECBBR4_SECBB23_Pos) /*!< 0x00800000 */ +#define FLASH_SECBBR4_SECBB23 FLASH_SECBBR4_SECBB23_Msk /*!< Page 119 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB24_Pos (24U) +#define FLASH_SECBBR4_SECBB24_Msk (0x1UL << FLASH_SECBBR4_SECBB24_Pos) /*!< 0x01000000 */ +#define FLASH_SECBBR4_SECBB24 FLASH_SECBBR4_SECBB24_Msk /*!< Page 120 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB25_Pos (25U) +#define FLASH_SECBBR4_SECBB25_Msk (0x1UL << FLASH_SECBBR4_SECBB25_Pos) /*!< 0x02000000 */ +#define FLASH_SECBBR4_SECBB25 FLASH_SECBBR4_SECBB25_Msk /*!< Page 121 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB26_Pos (26U) +#define FLASH_SECBBR4_SECBB26_Msk (0x1UL << FLASH_SECBBR4_SECBB26_Pos) /*!< 0x04000000 */ +#define FLASH_SECBBR4_SECBB26 FLASH_SECBBR4_SECBB26_Msk /*!< Page 122 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB27_Pos (27U) +#define FLASH_SECBBR4_SECBB27_Msk (0x1UL << FLASH_SECBBR4_SECBB27_Pos) /*!< 0x08000000 */ +#define FLASH_SECBBR4_SECBB27 FLASH_SECBBR4_SECBB27_Msk /*!< Page 123 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB28_Pos (28U) +#define FLASH_SECBBR4_SECBB28_Msk (0x1UL << FLASH_SECBBR4_SECBB28_Pos) /*!< 0x10000000 */ +#define FLASH_SECBBR4_SECBB28 FLASH_SECBBR4_SECBB28_Msk /*!< Page 124 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB29_Pos (29U) +#define FLASH_SECBBR4_SECBB29_Msk (0x1UL << FLASH_SECBBR4_SECBB29_Pos) /*!< 0x20000000 */ +#define FLASH_SECBBR4_SECBB29 FLASH_SECBBR4_SECBB29_Msk /*!< Page 125 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB30_Pos (30U) +#define FLASH_SECBBR4_SECBB30_Msk (0x1UL << FLASH_SECBBR4_SECBB30_Pos) /*!< 0x40000000 */ +#define FLASH_SECBBR4_SECBB30 FLASH_SECBBR4_SECBB30_Msk /*!< Page 126 in Flash block-based secure */ +#define FLASH_SECBBR4_SECBB31_Pos (31U) +#define FLASH_SECBBR4_SECBB31_Msk (0x1UL << FLASH_SECBBR4_SECBB31_Pos) /*!< 0x80000000 */ +#define FLASH_SECBBR4_SECBB31 FLASH_SECBBR4_SECBB31_Msk /*!< Page 127 in Flash block-based secure */ + +/****************** Bits definition for FLASH_SECHDPCR register ***********/ +#define FLASH_SECHDPCR_HDP_ACCDIS_Pos (0U) +#define FLASH_SECHDPCR_HDP_ACCDIS_Msk (0x1UL << FLASH_SECHDPCR_HDP_ACCDIS_Pos) /*!< 0x00000001 */ +#define FLASH_SECHDPCR_HDP_ACCDIS FLASH_SECHDPCR_HDP_ACCDIS_Msk /*!< HDP area access disable */ + +/****************** Bits definition for FLASH_PRIVCFGR register ***********/ +#define FLASH_PRIVCFGR_SPRIV_Pos (0U) +#define FLASH_PRIVCFGR_SPRIV_Msk (0x1UL << FLASH_PRIVCFGR_SPRIV_Pos) /*!< 0x00000001 */ +#define FLASH_PRIVCFGR_SPRIV FLASH_PRIVCFGR_SPRIV_Msk /*!< Privilege protection for secure registers */ +#define FLASH_PRIVCFGR_NSPRIV_Pos (1U) +#define FLASH_PRIVCFGR_NSPRIV_Msk (0x1UL << FLASH_PRIVCFGR_NSPRIV_Pos) /*!< 0x00000002 */ +#define FLASH_PRIVCFGR_NSPRIV FLASH_PRIVCFGR_NSPRIV_Msk /*!< Privilege protection for non-secure registers */ + +/******************* Bit definition for FLASH_PRIVBBR1 register ******************/ +#define FLASH_PRIVBBR1_PRIVBB0_Pos (0U) +#define FLASH_PRIVBBR1_PRIVBB0_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB0_Pos) /*!< 0x00000001 */ +#define FLASH_PRIVBBR1_PRIVBB0 FLASH_PRIVBBR1_PRIVBB0_Msk /*!< Page 0 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB1_Pos (1U) +#define FLASH_PRIVBBR1_PRIVBB1_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB1_Pos) /*!< 0x00000002 */ +#define FLASH_PRIVBBR1_PRIVBB1 FLASH_PRIVBBR1_PRIVBB1_Msk /*!< Page 1 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB2_Pos (2U) +#define FLASH_PRIVBBR1_PRIVBB2_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB2_Pos) /*!< 0x00000004 */ +#define FLASH_PRIVBBR1_PRIVBB2 FLASH_PRIVBBR1_PRIVBB2_Msk /*!< Page 2 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB3_Pos (3U) +#define FLASH_PRIVBBR1_PRIVBB3_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB3_Pos) /*!< 0x00000008 */ +#define FLASH_PRIVBBR1_PRIVBB3 FLASH_PRIVBBR1_PRIVBB3_Msk /*!< Page 3 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB4_Pos (4U) +#define FLASH_PRIVBBR1_PRIVBB4_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB4_Pos) /*!< 0x00000010 */ +#define FLASH_PRIVBBR1_PRIVBB4 FLASH_PRIVBBR1_PRIVBB4_Msk /*!< Page 4 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB5_Pos (5U) +#define FLASH_PRIVBBR1_PRIVBB5_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB5_Pos) /*!< 0x00000020 */ +#define FLASH_PRIVBBR1_PRIVBB5 FLASH_PRIVBBR1_PRIVBB5_Msk /*!< Page 5 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB6_Pos (6U) +#define FLASH_PRIVBBR1_PRIVBB6_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB6_Pos) /*!< 0x00000040 */ +#define FLASH_PRIVBBR1_PRIVBB6 FLASH_PRIVBBR1_PRIVBB6_Msk /*!< Page 6 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB7_Pos (7U) +#define FLASH_PRIVBBR1_PRIVBB7_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB7_Pos) /*!< 0x00000080 */ +#define FLASH_PRIVBBR1_PRIVBB7 FLASH_PRIVBBR1_PRIVBB7_Msk /*!< Page 7 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB8_Pos (8U) +#define FLASH_PRIVBBR1_PRIVBB8_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB8_Pos) /*!< 0x00000100 */ +#define FLASH_PRIVBBR1_PRIVBB8 FLASH_PRIVBBR1_PRIVBB8_Msk /*!< Page 8 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB9_Pos (9U) +#define FLASH_PRIVBBR1_PRIVBB9_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB9_Pos) /*!< 0x00000200 */ +#define FLASH_PRIVBBR1_PRIVBB9 FLASH_PRIVBBR1_PRIVBB9_Msk /*!< Page 9 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB10_Pos (10U) +#define FLASH_PRIVBBR1_PRIVBB10_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB10_Pos) /*!< 0x00000400 */ +#define FLASH_PRIVBBR1_PRIVBB10 FLASH_PRIVBBR1_PRIVBB10_Msk /*!< Page 10 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB11_Pos (11U) +#define FLASH_PRIVBBR1_PRIVBB11_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB11_Pos) /*!< 0x00000800 */ +#define FLASH_PRIVBBR1_PRIVBB11 FLASH_PRIVBBR1_PRIVBB11_Msk /*!< Page 11 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB12_Pos (12U) +#define FLASH_PRIVBBR1_PRIVBB12_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB12_Pos) /*!< 0x00001000 */ +#define FLASH_PRIVBBR1_PRIVBB12 FLASH_PRIVBBR1_PRIVBB12_Msk /*!< Page 12 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB13_Pos (13U) +#define FLASH_PRIVBBR1_PRIVBB13_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB13_Pos) /*!< 0x00002000 */ +#define FLASH_PRIVBBR1_PRIVBB13 FLASH_PRIVBBR1_PRIVBB13_Msk /*!< Page 13 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB14_Pos (14U) +#define FLASH_PRIVBBR1_PRIVBB14_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB14_Pos) /*!< 0x00004000 */ +#define FLASH_PRIVBBR1_PRIVBB14 FLASH_PRIVBBR1_PRIVBB14_Msk /*!< Page 14 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB15_Pos (15U) +#define FLASH_PRIVBBR1_PRIVBB15_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB15_Pos) /*!< 0x00008000 */ +#define FLASH_PRIVBBR1_PRIVBB15 FLASH_PRIVBBR1_PRIVBB15_Msk /*!< Page 15 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB16_Pos (16U) +#define FLASH_PRIVBBR1_PRIVBB16_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB16_Pos) /*!< 0x00010000 */ +#define FLASH_PRIVBBR1_PRIVBB16 FLASH_PRIVBBR1_PRIVBB16_Msk /*!< Page 16 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB17_Pos (17U) +#define FLASH_PRIVBBR1_PRIVBB17_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB17_Pos) /*!< 0x00020000 */ +#define FLASH_PRIVBBR1_PRIVBB17 FLASH_PRIVBBR1_PRIVBB17_Msk /*!< Page 17 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB18_Pos (18U) +#define FLASH_PRIVBBR1_PRIVBB18_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB18_Pos) /*!< 0x00040000 */ +#define FLASH_PRIVBBR1_PRIVBB18 FLASH_PRIVBBR1_PRIVBB18_Msk /*!< Page 18 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB19_Pos (19U) +#define FLASH_PRIVBBR1_PRIVBB19_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB19_Pos) /*!< 0x00080000 */ +#define FLASH_PRIVBBR1_PRIVBB19 FLASH_PRIVBBR1_PRIVBB19_Msk /*!< Page 19 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB20_Pos (20U) +#define FLASH_PRIVBBR1_PRIVBB20_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB20_Pos) /*!< 0x00100000 */ +#define FLASH_PRIVBBR1_PRIVBB20 FLASH_PRIVBBR1_PRIVBB20_Msk /*!< Page 20 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB21_Pos (21U) +#define FLASH_PRIVBBR1_PRIVBB21_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB21_Pos) /*!< 0x00200000 */ +#define FLASH_PRIVBBR1_PRIVBB21 FLASH_PRIVBBR1_PRIVBB21_Msk /*!< Page 21 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB22_Pos (22U) +#define FLASH_PRIVBBR1_PRIVBB22_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB22_Pos) /*!< 0x00400000 */ +#define FLASH_PRIVBBR1_PRIVBB22 FLASH_PRIVBBR1_PRIVBB22_Msk /*!< Page 22 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB23_Pos (23U) +#define FLASH_PRIVBBR1_PRIVBB23_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB23_Pos) /*!< 0x00800000 */ +#define FLASH_PRIVBBR1_PRIVBB23 FLASH_PRIVBBR1_PRIVBB23_Msk /*!< Page 23 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB24_Pos (24U) +#define FLASH_PRIVBBR1_PRIVBB24_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB24_Pos) /*!< 0x01000000 */ +#define FLASH_PRIVBBR1_PRIVBB24 FLASH_PRIVBBR1_PRIVBB24_Msk /*!< Page 24 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB25_Pos (25U) +#define FLASH_PRIVBBR1_PRIVBB25_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB25_Pos) /*!< 0x02000000 */ +#define FLASH_PRIVBBR1_PRIVBB25 FLASH_PRIVBBR1_PRIVBB25_Msk /*!< Page 25 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB26_Pos (26U) +#define FLASH_PRIVBBR1_PRIVBB26_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB26_Pos) /*!< 0x04000000 */ +#define FLASH_PRIVBBR1_PRIVBB26 FLASH_PRIVBBR1_PRIVBB26_Msk /*!< Page 26 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB27_Pos (27U) +#define FLASH_PRIVBBR1_PRIVBB27_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB27_Pos) /*!< 0x08000000 */ +#define FLASH_PRIVBBR1_PRIVBB27 FLASH_PRIVBBR1_PRIVBB27_Msk /*!< Page 27 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB28_Pos (28U) +#define FLASH_PRIVBBR1_PRIVBB28_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB28_Pos) /*!< 0x10000000 */ +#define FLASH_PRIVBBR1_PRIVBB28 FLASH_PRIVBBR1_PRIVBB28_Msk /*!< Page 28 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB29_Pos (29U) +#define FLASH_PRIVBBR1_PRIVBB29_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB29_Pos) /*!< 0x20000000 */ +#define FLASH_PRIVBBR1_PRIVBB29 FLASH_PRIVBBR1_PRIVBB29_Msk /*!< Page 29 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB30_Pos (30U) +#define FLASH_PRIVBBR1_PRIVBB30_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB30_Pos) /*!< 0x40000000 */ +#define FLASH_PRIVBBR1_PRIVBB30 FLASH_PRIVBBR1_PRIVBB30_Msk /*!< Page 30 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR1_PRIVBB31_Pos (31U) +#define FLASH_PRIVBBR1_PRIVBB31_Msk (0x1UL << FLASH_PRIVBBR1_PRIVBB31_Pos) /*!< 0x80000000 */ +#define FLASH_PRIVBBR1_PRIVBB31 FLASH_PRIVBBR1_PRIVBB31_Msk /*!< Page 31 in Flash only accessible by privileged access */ + +/******************* Bit definition for FLASH_PRIVBBR2 register ******************/ +#define FLASH_PRIVBBR2_PRIVBB0_Pos (0U) +#define FLASH_PRIVBBR2_PRIVBB0_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB0_Pos) /*!< 0x00000001 */ +#define FLASH_PRIVBBR2_PRIVBB0 FLASH_PRIVBBR2_PRIVBB0_Msk /*!< Page 32 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB1_Pos (1U) +#define FLASH_PRIVBBR2_PRIVBB1_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB1_Pos) /*!< 0x00000002 */ +#define FLASH_PRIVBBR2_PRIVBB1 FLASH_PRIVBBR2_PRIVBB1_Msk /*!< Page 33 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB2_Pos (2U) +#define FLASH_PRIVBBR2_PRIVBB2_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB2_Pos) /*!< 0x00000004 */ +#define FLASH_PRIVBBR2_PRIVBB2 FLASH_PRIVBBR2_PRIVBB2_Msk /*!< Page 34 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB3_Pos (3U) +#define FLASH_PRIVBBR2_PRIVBB3_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB3_Pos) /*!< 0x00000008 */ +#define FLASH_PRIVBBR2_PRIVBB3 FLASH_PRIVBBR2_PRIVBB3_Msk /*!< Page 35 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB4_Pos (4U) +#define FLASH_PRIVBBR2_PRIVBB4_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB4_Pos) /*!< 0x00000010 */ +#define FLASH_PRIVBBR2_PRIVBB4 FLASH_PRIVBBR2_PRIVBB4_Msk /*!< Page 36 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB5_Pos (5U) +#define FLASH_PRIVBBR2_PRIVBB5_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB5_Pos) /*!< 0x00000020 */ +#define FLASH_PRIVBBR2_PRIVBB5 FLASH_PRIVBBR2_PRIVBB5_Msk /*!< Page 37 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB6_Pos (6U) +#define FLASH_PRIVBBR2_PRIVBB6_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB6_Pos) /*!< 0x00000040 */ +#define FLASH_PRIVBBR2_PRIVBB6 FLASH_PRIVBBR2_PRIVBB6_Msk /*!< Page 38 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB7_Pos (7U) +#define FLASH_PRIVBBR2_PRIVBB7_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB7_Pos) /*!< 0x00000080 */ +#define FLASH_PRIVBBR2_PRIVBB7 FLASH_PRIVBBR2_PRIVBB7_Msk /*!< Page 39 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB8_Pos (8U) +#define FLASH_PRIVBBR2_PRIVBB8_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB8_Pos) /*!< 0x00000100 */ +#define FLASH_PRIVBBR2_PRIVBB8 FLASH_PRIVBBR2_PRIVBB8_Msk /*!< Page 40 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB9_Pos (9U) +#define FLASH_PRIVBBR2_PRIVBB9_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB9_Pos) /*!< 0x00000200 */ +#define FLASH_PRIVBBR2_PRIVBB9 FLASH_PRIVBBR2_PRIVBB9_Msk /*!< Page 41 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB10_Pos (10U) +#define FLASH_PRIVBBR2_PRIVBB10_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB10_Pos) /*!< 0x00000400 */ +#define FLASH_PRIVBBR2_PRIVBB10 FLASH_PRIVBBR2_PRIVBB10_Msk /*!< Page 42 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB11_Pos (11U) +#define FLASH_PRIVBBR2_PRIVBB11_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB11_Pos) /*!< 0x00000800 */ +#define FLASH_PRIVBBR2_PRIVBB11 FLASH_PRIVBBR2_PRIVBB11_Msk /*!< Page 43 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB12_Pos (12U) +#define FLASH_PRIVBBR2_PRIVBB12_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB12_Pos) /*!< 0x00001000 */ +#define FLASH_PRIVBBR2_PRIVBB12 FLASH_PRIVBBR2_PRIVBB12_Msk /*!< Page 44 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB13_Pos (13U) +#define FLASH_PRIVBBR2_PRIVBB13_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB13_Pos) /*!< 0x00002000 */ +#define FLASH_PRIVBBR2_PRIVBB13 FLASH_PRIVBBR2_PRIVBB13_Msk /*!< Page 45 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB14_Pos (14U) +#define FLASH_PRIVBBR2_PRIVBB14_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB14_Pos) /*!< 0x00004000 */ +#define FLASH_PRIVBBR2_PRIVBB14 FLASH_PRIVBBR2_PRIVBB14_Msk /*!< Page 46 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB15_Pos (15U) +#define FLASH_PRIVBBR2_PRIVBB15_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB15_Pos) /*!< 0x00008000 */ +#define FLASH_PRIVBBR2_PRIVBB15 FLASH_PRIVBBR2_PRIVBB15_Msk /*!< Page 47 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB16_Pos (16U) +#define FLASH_PRIVBBR2_PRIVBB16_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB16_Pos) /*!< 0x00010000 */ +#define FLASH_PRIVBBR2_PRIVBB16 FLASH_PRIVBBR2_PRIVBB16_Msk /*!< Page 48 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB17_Pos (17U) +#define FLASH_PRIVBBR2_PRIVBB17_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB17_Pos) /*!< 0x00020000 */ +#define FLASH_PRIVBBR2_PRIVBB17 FLASH_PRIVBBR2_PRIVBB17_Msk /*!< Page 49 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB18_Pos (18U) +#define FLASH_PRIVBBR2_PRIVBB18_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB18_Pos) /*!< 0x00040000 */ +#define FLASH_PRIVBBR2_PRIVBB18 FLASH_PRIVBBR2_PRIVBB18_Msk /*!< Page 50 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB19_Pos (19U) +#define FLASH_PRIVBBR2_PRIVBB19_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB19_Pos) /*!< 0x00080000 */ +#define FLASH_PRIVBBR2_PRIVBB19 FLASH_PRIVBBR2_PRIVBB19_Msk /*!< Page 51 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB20_Pos (20U) +#define FLASH_PRIVBBR2_PRIVBB20_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB20_Pos) /*!< 0x00100000 */ +#define FLASH_PRIVBBR2_PRIVBB20 FLASH_PRIVBBR2_PRIVBB20_Msk /*!< Page 52 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB21_Pos (21U) +#define FLASH_PRIVBBR2_PRIVBB21_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB21_Pos) /*!< 0x00200000 */ +#define FLASH_PRIVBBR2_PRIVBB21 FLASH_PRIVBBR2_PRIVBB21_Msk /*!< Page 53 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB22_Pos (22U) +#define FLASH_PRIVBBR2_PRIVBB22_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB22_Pos) /*!< 0x00400000 */ +#define FLASH_PRIVBBR2_PRIVBB22 FLASH_PRIVBBR2_PRIVBB22_Msk /*!< Page 54 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB23_Pos (23U) +#define FLASH_PRIVBBR2_PRIVBB23_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB23_Pos) /*!< 0x00800000 */ +#define FLASH_PRIVBBR2_PRIVBB23 FLASH_PRIVBBR2_PRIVBB23_Msk /*!< Page 55 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB24_Pos (24U) +#define FLASH_PRIVBBR2_PRIVBB24_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB24_Pos) /*!< 0x01000000 */ +#define FLASH_PRIVBBR2_PRIVBB24 FLASH_PRIVBBR2_PRIVBB24_Msk /*!< Page 56 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB25_Pos (25U) +#define FLASH_PRIVBBR2_PRIVBB25_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB25_Pos) /*!< 0x02000000 */ +#define FLASH_PRIVBBR2_PRIVBB25 FLASH_PRIVBBR2_PRIVBB25_Msk /*!< Page 57 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB26_Pos (26U) +#define FLASH_PRIVBBR2_PRIVBB26_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB26_Pos) /*!< 0x04000000 */ +#define FLASH_PRIVBBR2_PRIVBB26 FLASH_PRIVBBR2_PRIVBB26_Msk /*!< Page 58 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB27_Pos (27U) +#define FLASH_PRIVBBR2_PRIVBB27_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB27_Pos) /*!< 0x08000000 */ +#define FLASH_PRIVBBR2_PRIVBB27 FLASH_PRIVBBR2_PRIVBB27_Msk /*!< Page 59 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB28_Pos (28U) +#define FLASH_PRIVBBR2_PRIVBB28_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB28_Pos) /*!< 0x10000000 */ +#define FLASH_PRIVBBR2_PRIVBB28 FLASH_PRIVBBR2_PRIVBB28_Msk /*!< Page 60 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB29_Pos (29U) +#define FLASH_PRIVBBR2_PRIVBB29_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB29_Pos) /*!< 0x20000000 */ +#define FLASH_PRIVBBR2_PRIVBB29 FLASH_PRIVBBR2_PRIVBB29_Msk /*!< Page 61 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB30_Pos (30U) +#define FLASH_PRIVBBR2_PRIVBB30_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB30_Pos) /*!< 0x40000000 */ +#define FLASH_PRIVBBR2_PRIVBB30 FLASH_PRIVBBR2_PRIVBB30_Msk /*!< Page 62 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR2_PRIVBB31_Pos (31U) +#define FLASH_PRIVBBR2_PRIVBB31_Msk (0x1UL << FLASH_PRIVBBR2_PRIVBB31_Pos) /*!< 0x80000000 */ +#define FLASH_PRIVBBR2_PRIVBB31 FLASH_PRIVBBR2_PRIVBB31_Msk /*!< Page 63 in Flash only accessible by privileged access */ + +/******************* Bit definition for FLASH_PRIVBBR3 register ******************/ +#define FLASH_PRIVBBR3_PRIVBB0_Pos (0U) +#define FLASH_PRIVBBR3_PRIVBB0_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB0_Pos) /*!< 0x00000001 */ +#define FLASH_PRIVBBR3_PRIVBB0 FLASH_PRIVBBR3_PRIVBB0_Msk /*!< Page 64 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB1_Pos (1U) +#define FLASH_PRIVBBR3_PRIVBB1_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB1_Pos) /*!< 0x00000002 */ +#define FLASH_PRIVBBR3_PRIVBB1 FLASH_PRIVBBR3_PRIVBB1_Msk /*!< Page 65 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB2_Pos (2U) +#define FLASH_PRIVBBR3_PRIVBB2_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB2_Pos) /*!< 0x00000004 */ +#define FLASH_PRIVBBR3_PRIVBB2 FLASH_PRIVBBR3_PRIVBB2_Msk /*!< Page 66 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB3_Pos (3U) +#define FLASH_PRIVBBR3_PRIVBB3_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB3_Pos) /*!< 0x00000008 */ +#define FLASH_PRIVBBR3_PRIVBB3 FLASH_PRIVBBR3_PRIVBB3_Msk /*!< Page 67 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB4_Pos (4U) +#define FLASH_PRIVBBR3_PRIVBB4_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB4_Pos) /*!< 0x00000010 */ +#define FLASH_PRIVBBR3_PRIVBB4 FLASH_PRIVBBR3_PRIVBB4_Msk /*!< Page 68 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB5_Pos (5U) +#define FLASH_PRIVBBR3_PRIVBB5_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB5_Pos) /*!< 0x00000020 */ +#define FLASH_PRIVBBR3_PRIVBB5 FLASH_PRIVBBR3_PRIVBB5_Msk /*!< Page 69 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB6_Pos (6U) +#define FLASH_PRIVBBR3_PRIVBB6_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB6_Pos) /*!< 0x00000040 */ +#define FLASH_PRIVBBR3_PRIVBB6 FLASH_PRIVBBR3_PRIVBB6_Msk /*!< Page 70 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB7_Pos (7U) +#define FLASH_PRIVBBR3_PRIVBB7_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB7_Pos) /*!< 0x00000080 */ +#define FLASH_PRIVBBR3_PRIVBB7 FLASH_PRIVBBR3_PRIVBB7_Msk /*!< Page 71 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB8_Pos (8U) +#define FLASH_PRIVBBR3_PRIVBB8_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB8_Pos) /*!< 0x00000100 */ +#define FLASH_PRIVBBR3_PRIVBB8 FLASH_PRIVBBR3_PRIVBB8_Msk /*!< Page 72 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB9_Pos (9U) +#define FLASH_PRIVBBR3_PRIVBB9_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB9_Pos) /*!< 0x00000200 */ +#define FLASH_PRIVBBR3_PRIVBB9 FLASH_PRIVBBR3_PRIVBB9_Msk /*!< Page 73 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB10_Pos (10U) +#define FLASH_PRIVBBR3_PRIVBB10_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB10_Pos) /*!< 0x00000400 */ +#define FLASH_PRIVBBR3_PRIVBB10 FLASH_PRIVBBR3_PRIVBB10_Msk /*!< Page 74 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB11_Pos (11U) +#define FLASH_PRIVBBR3_PRIVBB11_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB11_Pos) /*!< 0x00000800 */ +#define FLASH_PRIVBBR3_PRIVBB11 FLASH_PRIVBBR3_PRIVBB11_Msk /*!< Page 75 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB12_Pos (12U) +#define FLASH_PRIVBBR3_PRIVBB12_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB12_Pos) /*!< 0x00001000 */ +#define FLASH_PRIVBBR3_PRIVBB12 FLASH_PRIVBBR3_PRIVBB12_Msk /*!< Page 76 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB13_Pos (13U) +#define FLASH_PRIVBBR3_PRIVBB13_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB13_Pos) /*!< 0x00002000 */ +#define FLASH_PRIVBBR3_PRIVBB13 FLASH_PRIVBBR3_PRIVBB13_Msk /*!< Page 77 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB14_Pos (14U) +#define FLASH_PRIVBBR3_PRIVBB14_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB14_Pos) /*!< 0x00004000 */ +#define FLASH_PRIVBBR3_PRIVBB14 FLASH_PRIVBBR3_PRIVBB14_Msk /*!< Page 78 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB15_Pos (15U) +#define FLASH_PRIVBBR3_PRIVBB15_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB15_Pos) /*!< 0x00008000 */ +#define FLASH_PRIVBBR3_PRIVBB15 FLASH_PRIVBBR3_PRIVBB15_Msk /*!< Page 79 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB16_Pos (16U) +#define FLASH_PRIVBBR3_PRIVBB16_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB16_Pos) /*!< 0x00010000 */ +#define FLASH_PRIVBBR3_PRIVBB16 FLASH_PRIVBBR3_PRIVBB16_Msk /*!< Page 80 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB17_Pos (17U) +#define FLASH_PRIVBBR3_PRIVBB17_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB17_Pos) /*!< 0x00020000 */ +#define FLASH_PRIVBBR3_PRIVBB17 FLASH_PRIVBBR3_PRIVBB17_Msk /*!< Page 81 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB18_Pos (18U) +#define FLASH_PRIVBBR3_PRIVBB18_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB18_Pos) /*!< 0x00040000 */ +#define FLASH_PRIVBBR3_PRIVBB18 FLASH_PRIVBBR3_PRIVBB18_Msk /*!< Page 82 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB19_Pos (19U) +#define FLASH_PRIVBBR3_PRIVBB19_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB19_Pos) /*!< 0x00080000 */ +#define FLASH_PRIVBBR3_PRIVBB19 FLASH_PRIVBBR3_PRIVBB19_Msk /*!< Page 83 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB20_Pos (20U) +#define FLASH_PRIVBBR3_PRIVBB20_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB20_Pos) /*!< 0x00100000 */ +#define FLASH_PRIVBBR3_PRIVBB20 FLASH_PRIVBBR3_PRIVBB20_Msk /*!< Page 84 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB21_Pos (21U) +#define FLASH_PRIVBBR3_PRIVBB21_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB21_Pos) /*!< 0x00200000 */ +#define FLASH_PRIVBBR3_PRIVBB21 FLASH_PRIVBBR3_PRIVBB21_Msk /*!< Page 85 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB22_Pos (22U) +#define FLASH_PRIVBBR3_PRIVBB22_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB22_Pos) /*!< 0x00400000 */ +#define FLASH_PRIVBBR3_PRIVBB22 FLASH_PRIVBBR3_PRIVBB22_Msk /*!< Page 86 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB23_Pos (23U) +#define FLASH_PRIVBBR3_PRIVBB23_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB23_Pos) /*!< 0x00800000 */ +#define FLASH_PRIVBBR3_PRIVBB23 FLASH_PRIVBBR3_PRIVBB23_Msk /*!< Page 87 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB24_Pos (24U) +#define FLASH_PRIVBBR3_PRIVBB24_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB24_Pos) /*!< 0x01000000 */ +#define FLASH_PRIVBBR3_PRIVBB24 FLASH_PRIVBBR3_PRIVBB24_Msk /*!< Page 88 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB25_Pos (25U) +#define FLASH_PRIVBBR3_PRIVBB25_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB25_Pos) /*!< 0x02000000 */ +#define FLASH_PRIVBBR3_PRIVBB25 FLASH_PRIVBBR3_PRIVBB25_Msk /*!< Page 89 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB26_Pos (26U) +#define FLASH_PRIVBBR3_PRIVBB26_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB26_Pos) /*!< 0x04000000 */ +#define FLASH_PRIVBBR3_PRIVBB26 FLASH_PRIVBBR3_PRIVBB26_Msk /*!< Page 90 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB27_Pos (27U) +#define FLASH_PRIVBBR3_PRIVBB27_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB27_Pos) /*!< 0x08000000 */ +#define FLASH_PRIVBBR3_PRIVBB27 FLASH_PRIVBBR3_PRIVBB27_Msk /*!< Page 91 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB28_Pos (28U) +#define FLASH_PRIVBBR3_PRIVBB28_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB28_Pos) /*!< 0x10000000 */ +#define FLASH_PRIVBBR3_PRIVBB28 FLASH_PRIVBBR3_PRIVBB28_Msk /*!< Page 92 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB29_Pos (29U) +#define FLASH_PRIVBBR3_PRIVBB29_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB29_Pos) /*!< 0x20000000 */ +#define FLASH_PRIVBBR3_PRIVBB29 FLASH_PRIVBBR3_PRIVBB29_Msk /*!< Page 93 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB30_Pos (30U) +#define FLASH_PRIVBBR3_PRIVBB30_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB30_Pos) /*!< 0x40000000 */ +#define FLASH_PRIVBBR3_PRIVBB30 FLASH_PRIVBBR3_PRIVBB30_Msk /*!< Page 94 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR3_PRIVBB31_Pos (31U) +#define FLASH_PRIVBBR3_PRIVBB31_Msk (0x1UL << FLASH_PRIVBBR3_PRIVBB31_Pos) /*!< 0x80000000 */ +#define FLASH_PRIVBBR3_PRIVBB31 FLASH_PRIVBBR3_PRIVBB31_Msk /*!< Page 95 in Flash only accessible by privileged access */ + +/******************* Bit definition for FLASH_PRIVBBR4 register ******************/ +#define FLASH_PRIVBBR4_PRIVBB0_Pos (0U) +#define FLASH_PRIVBBR4_PRIVBB0_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB0_Pos) /*!< 0x00000001 */ +#define FLASH_PRIVBBR4_PRIVBB0 FLASH_PRIVBBR4_PRIVBB0_Msk /*!< Page 96 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB1_Pos (1U) +#define FLASH_PRIVBBR4_PRIVBB1_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB1_Pos) /*!< 0x00000002 */ +#define FLASH_PRIVBBR4_PRIVBB1 FLASH_PRIVBBR4_PRIVBB1_Msk /*!< Page 97 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB2_Pos (2U) +#define FLASH_PRIVBBR4_PRIVBB2_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB2_Pos) /*!< 0x00000004 */ +#define FLASH_PRIVBBR4_PRIVBB2 FLASH_PRIVBBR4_PRIVBB2_Msk /*!< Page 98 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB3_Pos (3U) +#define FLASH_PRIVBBR4_PRIVBB3_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB3_Pos) /*!< 0x00000008 */ +#define FLASH_PRIVBBR4_PRIVBB3 FLASH_PRIVBBR4_PRIVBB3_Msk /*!< Page 99 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB4_Pos (4U) +#define FLASH_PRIVBBR4_PRIVBB4_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB4_Pos) /*!< 0x00000010 */ +#define FLASH_PRIVBBR4_PRIVBB4 FLASH_PRIVBBR4_PRIVBB4_Msk /*!< Page 100 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB5_Pos (5U) +#define FLASH_PRIVBBR4_PRIVBB5_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB5_Pos) /*!< 0x00000020 */ +#define FLASH_PRIVBBR4_PRIVBB5 FLASH_PRIVBBR4_PRIVBB5_Msk /*!< Page 101 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB6_Pos (6U) +#define FLASH_PRIVBBR4_PRIVBB6_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB6_Pos) /*!< 0x00000040 */ +#define FLASH_PRIVBBR4_PRIVBB6 FLASH_PRIVBBR4_PRIVBB6_Msk /*!< Page 102 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB7_Pos (7U) +#define FLASH_PRIVBBR4_PRIVBB7_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB7_Pos) /*!< 0x00000080 */ +#define FLASH_PRIVBBR4_PRIVBB7 FLASH_PRIVBBR4_PRIVBB7_Msk /*!< Page 103 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB8_Pos (8U) +#define FLASH_PRIVBBR4_PRIVBB8_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB8_Pos) /*!< 0x00000100 */ +#define FLASH_PRIVBBR4_PRIVBB8 FLASH_PRIVBBR4_PRIVBB8_Msk /*!< Page 104 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB9_Pos (9U) +#define FLASH_PRIVBBR4_PRIVBB9_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB9_Pos) /*!< 0x00000200 */ +#define FLASH_PRIVBBR4_PRIVBB9 FLASH_PRIVBBR4_PRIVBB9_Msk /*!< Page 105 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB10_Pos (10U) +#define FLASH_PRIVBBR4_PRIVBB10_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB10_Pos) /*!< 0x00000400 */ +#define FLASH_PRIVBBR4_PRIVBB10 FLASH_PRIVBBR4_PRIVBB10_Msk /*!< Page 106 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB11_Pos (11U) +#define FLASH_PRIVBBR4_PRIVBB11_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB11_Pos) /*!< 0x00000800 */ +#define FLASH_PRIVBBR4_PRIVBB11 FLASH_PRIVBBR4_PRIVBB11_Msk /*!< Page 107 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB12_Pos (12U) +#define FLASH_PRIVBBR4_PRIVBB12_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB12_Pos) /*!< 0x00001000 */ +#define FLASH_PRIVBBR4_PRIVBB12 FLASH_PRIVBBR4_PRIVBB12_Msk /*!< Page 108 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB13_Pos (13U) +#define FLASH_PRIVBBR4_PRIVBB13_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB13_Pos) /*!< 0x00002000 */ +#define FLASH_PRIVBBR4_PRIVBB13 FLASH_PRIVBBR4_PRIVBB13_Msk /*!< Page 109 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB14_Pos (14U) +#define FLASH_PRIVBBR4_PRIVBB14_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB14_Pos) /*!< 0x00004000 */ +#define FLASH_PRIVBBR4_PRIVBB14 FLASH_PRIVBBR4_PRIVBB14_Msk /*!< Page 110 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB15_Pos (15U) +#define FLASH_PRIVBBR4_PRIVBB15_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB15_Pos) /*!< 0x00008000 */ +#define FLASH_PRIVBBR4_PRIVBB15 FLASH_PRIVBBR4_PRIVBB15_Msk /*!< Page 111 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB16_Pos (16U) +#define FLASH_PRIVBBR4_PRIVBB16_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB16_Pos) /*!< 0x00010000 */ +#define FLASH_PRIVBBR4_PRIVBB16 FLASH_PRIVBBR4_PRIVBB16_Msk /*!< Page 112 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB17_Pos (17U) +#define FLASH_PRIVBBR4_PRIVBB17_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB17_Pos) /*!< 0x00020000 */ +#define FLASH_PRIVBBR4_PRIVBB17 FLASH_PRIVBBR4_PRIVBB17_Msk /*!< Page 113 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB18_Pos (18U) +#define FLASH_PRIVBBR4_PRIVBB18_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB18_Pos) /*!< 0x00040000 */ +#define FLASH_PRIVBBR4_PRIVBB18 FLASH_PRIVBBR4_PRIVBB18_Msk /*!< Page 114 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB19_Pos (19U) +#define FLASH_PRIVBBR4_PRIVBB19_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB19_Pos) /*!< 0x00080000 */ +#define FLASH_PRIVBBR4_PRIVBB19 FLASH_PRIVBBR4_PRIVBB19_Msk /*!< Page 115 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB20_Pos (20U) +#define FLASH_PRIVBBR4_PRIVBB20_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB20_Pos) /*!< 0x00100000 */ +#define FLASH_PRIVBBR4_PRIVBB20 FLASH_PRIVBBR4_PRIVBB20_Msk /*!< Page 116 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB21_Pos (21U) +#define FLASH_PRIVBBR4_PRIVBB21_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB21_Pos) /*!< 0x00200000 */ +#define FLASH_PRIVBBR4_PRIVBB21 FLASH_PRIVBBR4_PRIVBB21_Msk /*!< Page 117 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB22_Pos (22U) +#define FLASH_PRIVBBR4_PRIVBB22_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB22_Pos) /*!< 0x00400000 */ +#define FLASH_PRIVBBR4_PRIVBB22 FLASH_PRIVBBR4_PRIVBB22_Msk /*!< Page 118 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB23_Pos (23U) +#define FLASH_PRIVBBR4_PRIVBB23_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB23_Pos) /*!< 0x00800000 */ +#define FLASH_PRIVBBR4_PRIVBB23 FLASH_PRIVBBR4_PRIVBB23_Msk /*!< Page 119 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB24_Pos (24U) +#define FLASH_PRIVBBR4_PRIVBB24_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB24_Pos) /*!< 0x01000000 */ +#define FLASH_PRIVBBR4_PRIVBB24 FLASH_PRIVBBR4_PRIVBB24_Msk /*!< Page 120 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB25_Pos (25U) +#define FLASH_PRIVBBR4_PRIVBB25_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB25_Pos) /*!< 0x02000000 */ +#define FLASH_PRIVBBR4_PRIVBB25 FLASH_PRIVBBR4_PRIVBB25_Msk /*!< Page 121 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB26_Pos (26U) +#define FLASH_PRIVBBR4_PRIVBB26_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB26_Pos) /*!< 0x04000000 */ +#define FLASH_PRIVBBR4_PRIVBB26 FLASH_PRIVBBR4_PRIVBB26_Msk /*!< Page 122 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB27_Pos (27U) +#define FLASH_PRIVBBR4_PRIVBB27_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB27_Pos) /*!< 0x08000000 */ +#define FLASH_PRIVBBR4_PRIVBB27 FLASH_PRIVBBR4_PRIVBB27_Msk /*!< Page 123 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB28_Pos (28U) +#define FLASH_PRIVBBR4_PRIVBB28_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB28_Pos) /*!< 0x10000000 */ +#define FLASH_PRIVBBR4_PRIVBB28 FLASH_PRIVBBR4_PRIVBB28_Msk /*!< Page 124 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB29_Pos (29U) +#define FLASH_PRIVBBR4_PRIVBB29_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB29_Pos) /*!< 0x20000000 */ +#define FLASH_PRIVBBR4_PRIVBB29 FLASH_PRIVBBR4_PRIVBB29_Msk /*!< Page 125 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB30_Pos (30U) +#define FLASH_PRIVBBR4_PRIVBB30_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB30_Pos) /*!< 0x40000000 */ +#define FLASH_PRIVBBR4_PRIVBB30 FLASH_PRIVBBR4_PRIVBB30_Msk /*!< Page 126 in Flash only accessible by privileged access */ +#define FLASH_PRIVBBR4_PRIVBB31_Pos (31U) +#define FLASH_PRIVBBR4_PRIVBB31_Msk (0x1UL << FLASH_PRIVBBR4_PRIVBB31_Pos) /*!< 0x80000000 */ +#define FLASH_PRIVBBR4_PRIVBB31 FLASH_PRIVBBR4_PRIVBB31_Msk /*!< Page 127 in Flash only accessible by privileged access */ + +/******************************************************************************/ +/* */ +/* General Purpose IOs (GPIO) */ +/* */ +/******************************************************************************/ +/****************** Bits definition for GPIO_MODER register *****************/ +#define GPIO_MODER_MODE0_Pos (0U) +#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ +#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk +#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ +#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ +#define GPIO_MODER_MODE1_Pos (2U) +#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ +#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk +#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ +#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ +#define GPIO_MODER_MODE2_Pos (4U) +#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ +#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk +#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ +#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ +#define GPIO_MODER_MODE3_Pos (6U) +#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ +#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk +#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ +#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ +#define GPIO_MODER_MODE4_Pos (8U) +#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ +#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk +#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ +#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ +#define GPIO_MODER_MODE5_Pos (10U) +#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ +#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk +#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ +#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ +#define GPIO_MODER_MODE6_Pos (12U) +#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ +#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk +#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ +#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ +#define GPIO_MODER_MODE7_Pos (14U) +#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ +#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk +#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ +#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ +#define GPIO_MODER_MODE8_Pos (16U) +#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ +#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk +#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ +#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ +#define GPIO_MODER_MODE9_Pos (18U) +#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ +#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk +#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ +#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ +#define GPIO_MODER_MODE10_Pos (20U) +#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ +#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk +#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ +#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ +#define GPIO_MODER_MODE11_Pos (22U) +#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ +#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk +#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ +#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ +#define GPIO_MODER_MODE12_Pos (24U) +#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ +#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk +#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ +#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ +#define GPIO_MODER_MODE13_Pos (26U) +#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ +#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk +#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ +#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ +#define GPIO_MODER_MODE14_Pos (28U) +#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ +#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk +#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ +#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ +#define GPIO_MODER_MODE15_Pos (30U) +#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ +#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk +#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ +#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_OTYPER register ****************/ +#define GPIO_OTYPER_OT0_Pos (0U) +#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */ +#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk +#define GPIO_OTYPER_OT1_Pos (1U) +#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */ +#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk +#define GPIO_OTYPER_OT2_Pos (2U) +#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */ +#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk +#define GPIO_OTYPER_OT3_Pos (3U) +#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */ +#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk +#define GPIO_OTYPER_OT4_Pos (4U) +#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */ +#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk +#define GPIO_OTYPER_OT5_Pos (5U) +#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */ +#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk +#define GPIO_OTYPER_OT6_Pos (6U) +#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */ +#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk +#define GPIO_OTYPER_OT7_Pos (7U) +#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */ +#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk +#define GPIO_OTYPER_OT8_Pos (8U) +#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */ +#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk +#define GPIO_OTYPER_OT9_Pos (9U) +#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */ +#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk +#define GPIO_OTYPER_OT10_Pos (10U) +#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */ +#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk +#define GPIO_OTYPER_OT11_Pos (11U) +#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */ +#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk +#define GPIO_OTYPER_OT12_Pos (12U) +#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */ +#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk +#define GPIO_OTYPER_OT13_Pos (13U) +#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */ +#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk +#define GPIO_OTYPER_OT14_Pos (14U) +#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */ +#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk +#define GPIO_OTYPER_OT15_Pos (15U) +#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */ +#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk + +/****************** Bits definition for GPIO_OSPEEDR register ***************/ +#define GPIO_OSPEEDR_OSPEED0_Pos (0U) +#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */ +#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk +#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */ +#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */ +#define GPIO_OSPEEDR_OSPEED1_Pos (2U) +#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */ +#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk +#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */ +#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */ +#define GPIO_OSPEEDR_OSPEED2_Pos (4U) +#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */ +#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk +#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */ +#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */ +#define GPIO_OSPEEDR_OSPEED3_Pos (6U) +#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */ +#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk +#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */ +#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */ +#define GPIO_OSPEEDR_OSPEED4_Pos (8U) +#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */ +#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk +#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */ +#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */ +#define GPIO_OSPEEDR_OSPEED5_Pos (10U) +#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */ +#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk +#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */ +#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */ +#define GPIO_OSPEEDR_OSPEED6_Pos (12U) +#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */ +#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk +#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */ +#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */ +#define GPIO_OSPEEDR_OSPEED7_Pos (14U) +#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */ +#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk +#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */ +#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */ +#define GPIO_OSPEEDR_OSPEED8_Pos (16U) +#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */ +#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk +#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */ +#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */ +#define GPIO_OSPEEDR_OSPEED9_Pos (18U) +#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */ +#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk +#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */ +#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */ +#define GPIO_OSPEEDR_OSPEED10_Pos (20U) +#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */ +#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk +#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */ +#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */ +#define GPIO_OSPEEDR_OSPEED11_Pos (22U) +#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */ +#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk +#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */ +#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */ +#define GPIO_OSPEEDR_OSPEED12_Pos (24U) +#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */ +#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk +#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */ +#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */ +#define GPIO_OSPEEDR_OSPEED13_Pos (26U) +#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */ +#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk +#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */ +#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */ +#define GPIO_OSPEEDR_OSPEED14_Pos (28U) +#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */ +#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk +#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */ +#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */ +#define GPIO_OSPEEDR_OSPEED15_Pos (30U) +#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */ +#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk +#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */ +#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_PUPDR register *****************/ +#define GPIO_PUPDR_PUPD0_Pos (0U) +#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */ +#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk +#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */ +#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */ +#define GPIO_PUPDR_PUPD1_Pos (2U) +#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */ +#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk +#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */ +#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */ +#define GPIO_PUPDR_PUPD2_Pos (4U) +#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */ +#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk +#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */ +#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */ +#define GPIO_PUPDR_PUPD3_Pos (6U) +#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */ +#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk +#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */ +#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */ +#define GPIO_PUPDR_PUPD4_Pos (8U) +#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */ +#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk +#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */ +#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */ +#define GPIO_PUPDR_PUPD5_Pos (10U) +#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */ +#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk +#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */ +#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */ +#define GPIO_PUPDR_PUPD6_Pos (12U) +#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */ +#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk +#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */ +#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */ +#define GPIO_PUPDR_PUPD7_Pos (14U) +#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */ +#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk +#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */ +#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */ +#define GPIO_PUPDR_PUPD8_Pos (16U) +#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */ +#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk +#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */ +#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */ +#define GPIO_PUPDR_PUPD9_Pos (18U) +#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */ +#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk +#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */ +#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */ +#define GPIO_PUPDR_PUPD10_Pos (20U) +#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */ +#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk +#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */ +#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */ +#define GPIO_PUPDR_PUPD11_Pos (22U) +#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */ +#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk +#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */ +#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */ +#define GPIO_PUPDR_PUPD12_Pos (24U) +#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */ +#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk +#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */ +#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */ +#define GPIO_PUPDR_PUPD13_Pos (26U) +#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */ +#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk +#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */ +#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */ +#define GPIO_PUPDR_PUPD14_Pos (28U) +#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */ +#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk +#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */ +#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */ +#define GPIO_PUPDR_PUPD15_Pos (30U) +#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */ +#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk +#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */ +#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_IDR register *******************/ +#define GPIO_IDR_ID0_Pos (0U) +#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk +#define GPIO_IDR_ID1_Pos (1U) +#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk +#define GPIO_IDR_ID2_Pos (2U) +#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk +#define GPIO_IDR_ID3_Pos (3U) +#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk +#define GPIO_IDR_ID4_Pos (4U) +#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk +#define GPIO_IDR_ID5_Pos (5U) +#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk +#define GPIO_IDR_ID6_Pos (6U) +#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk +#define GPIO_IDR_ID7_Pos (7U) +#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk +#define GPIO_IDR_ID8_Pos (8U) +#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk +#define GPIO_IDR_ID9_Pos (9U) +#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk +#define GPIO_IDR_ID10_Pos (10U) +#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk +#define GPIO_IDR_ID11_Pos (11U) +#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk +#define GPIO_IDR_ID12_Pos (12U) +#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk +#define GPIO_IDR_ID13_Pos (13U) +#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk +#define GPIO_IDR_ID14_Pos (14U) +#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk +#define GPIO_IDR_ID15_Pos (15U) +#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk + +/****************** Bits definition for GPIO_ODR register *******************/ +#define GPIO_ODR_OD0_Pos (0U) +#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk +#define GPIO_ODR_OD1_Pos (1U) +#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk +#define GPIO_ODR_OD2_Pos (2U) +#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk +#define GPIO_ODR_OD3_Pos (3U) +#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk +#define GPIO_ODR_OD4_Pos (4U) +#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk +#define GPIO_ODR_OD5_Pos (5U) +#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk +#define GPIO_ODR_OD6_Pos (6U) +#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk +#define GPIO_ODR_OD7_Pos (7U) +#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk +#define GPIO_ODR_OD8_Pos (8U) +#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk +#define GPIO_ODR_OD9_Pos (9U) +#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk +#define GPIO_ODR_OD10_Pos (10U) +#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk +#define GPIO_ODR_OD11_Pos (11U) +#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk +#define GPIO_ODR_OD12_Pos (12U) +#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk +#define GPIO_ODR_OD13_Pos (13U) +#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk +#define GPIO_ODR_OD14_Pos (14U) +#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk +#define GPIO_ODR_OD15_Pos (15U) +#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk + +/****************** Bits definition for GPIO_BSRR register ******************/ +#define GPIO_BSRR_BS0_Pos (0U) +#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ +#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk +#define GPIO_BSRR_BS1_Pos (1U) +#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ +#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk +#define GPIO_BSRR_BS2_Pos (2U) +#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ +#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk +#define GPIO_BSRR_BS3_Pos (3U) +#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ +#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk +#define GPIO_BSRR_BS4_Pos (4U) +#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ +#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk +#define GPIO_BSRR_BS5_Pos (5U) +#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ +#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk +#define GPIO_BSRR_BS6_Pos (6U) +#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ +#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk +#define GPIO_BSRR_BS7_Pos (7U) +#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ +#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk +#define GPIO_BSRR_BS8_Pos (8U) +#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ +#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk +#define GPIO_BSRR_BS9_Pos (9U) +#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ +#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk +#define GPIO_BSRR_BS10_Pos (10U) +#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ +#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk +#define GPIO_BSRR_BS11_Pos (11U) +#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ +#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk +#define GPIO_BSRR_BS12_Pos (12U) +#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ +#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk +#define GPIO_BSRR_BS13_Pos (13U) +#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ +#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk +#define GPIO_BSRR_BS14_Pos (14U) +#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ +#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk +#define GPIO_BSRR_BS15_Pos (15U) +#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ +#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk +#define GPIO_BSRR_BR0_Pos (16U) +#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ +#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk +#define GPIO_BSRR_BR1_Pos (17U) +#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ +#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk +#define GPIO_BSRR_BR2_Pos (18U) +#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ +#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk +#define GPIO_BSRR_BR3_Pos (19U) +#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ +#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk +#define GPIO_BSRR_BR4_Pos (20U) +#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ +#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk +#define GPIO_BSRR_BR5_Pos (21U) +#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ +#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk +#define GPIO_BSRR_BR6_Pos (22U) +#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ +#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk +#define GPIO_BSRR_BR7_Pos (23U) +#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ +#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk +#define GPIO_BSRR_BR8_Pos (24U) +#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ +#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk +#define GPIO_BSRR_BR9_Pos (25U) +#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ +#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk +#define GPIO_BSRR_BR10_Pos (26U) +#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ +#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk +#define GPIO_BSRR_BR11_Pos (27U) +#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ +#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk +#define GPIO_BSRR_BR12_Pos (28U) +#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ +#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk +#define GPIO_BSRR_BR13_Pos (29U) +#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ +#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk +#define GPIO_BSRR_BR14_Pos (30U) +#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ +#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk +#define GPIO_BSRR_BR15_Pos (31U) +#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ +#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk + +/****************** Bit definition for GPIO_LCKR register *********************/ +#define GPIO_LCKR_LCK0_Pos (0U) +#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ +#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk +#define GPIO_LCKR_LCK1_Pos (1U) +#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ +#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk +#define GPIO_LCKR_LCK2_Pos (2U) +#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ +#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk +#define GPIO_LCKR_LCK3_Pos (3U) +#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ +#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk +#define GPIO_LCKR_LCK4_Pos (4U) +#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ +#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk +#define GPIO_LCKR_LCK5_Pos (5U) +#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ +#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk +#define GPIO_LCKR_LCK6_Pos (6U) +#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ +#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk +#define GPIO_LCKR_LCK7_Pos (7U) +#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ +#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk +#define GPIO_LCKR_LCK8_Pos (8U) +#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ +#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk +#define GPIO_LCKR_LCK9_Pos (9U) +#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ +#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk +#define GPIO_LCKR_LCK10_Pos (10U) +#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ +#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk +#define GPIO_LCKR_LCK11_Pos (11U) +#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ +#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk +#define GPIO_LCKR_LCK12_Pos (12U) +#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ +#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk +#define GPIO_LCKR_LCK13_Pos (13U) +#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ +#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk +#define GPIO_LCKR_LCK14_Pos (14U) +#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ +#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk +#define GPIO_LCKR_LCK15_Pos (15U) +#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ +#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk +#define GPIO_LCKR_LCKK_Pos (16U) +#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ +#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk + +/****************** Bit definition for GPIO_AFRL register *********************/ +#define GPIO_AFRL_AFSEL0_Pos (0U) +#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk +#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ +#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ +#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ +#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ +#define GPIO_AFRL_AFSEL1_Pos (4U) +#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk +#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ +#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ +#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ +#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ +#define GPIO_AFRL_AFSEL2_Pos (8U) +#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk +#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ +#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ +#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ +#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ +#define GPIO_AFRL_AFSEL3_Pos (12U) +#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk +#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ +#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ +#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ +#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ +#define GPIO_AFRL_AFSEL4_Pos (16U) +#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk +#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ +#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ +#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ +#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ +#define GPIO_AFRL_AFSEL5_Pos (20U) +#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk +#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ +#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ +#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ +#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ +#define GPIO_AFRL_AFSEL6_Pos (24U) +#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk +#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ +#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ +#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ +#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ +#define GPIO_AFRL_AFSEL7_Pos (28U) +#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk +#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ +#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ +#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ +#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ + +/****************** Bit definition for GPIO_AFRH register *********************/ +#define GPIO_AFRH_AFSEL8_Pos (0U) +#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk +#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ +#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ +#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ +#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ +#define GPIO_AFRH_AFSEL9_Pos (4U) +#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk +#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ +#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ +#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ +#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ +#define GPIO_AFRH_AFSEL10_Pos (8U) +#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk +#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ +#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ +#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ +#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ +#define GPIO_AFRH_AFSEL11_Pos (12U) +#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk +#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ +#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ +#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ +#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ +#define GPIO_AFRH_AFSEL12_Pos (16U) +#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk +#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ +#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ +#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ +#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ +#define GPIO_AFRH_AFSEL13_Pos (20U) +#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk +#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ +#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ +#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ +#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ +#define GPIO_AFRH_AFSEL14_Pos (24U) +#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk +#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ +#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ +#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ +#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ +#define GPIO_AFRH_AFSEL15_Pos (28U) +#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk +#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ +#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ +#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ +#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_BRR register ******************/ +#define GPIO_BRR_BR0_Pos (0U) +#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk +#define GPIO_BRR_BR1_Pos (1U) +#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk +#define GPIO_BRR_BR2_Pos (2U) +#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk +#define GPIO_BRR_BR3_Pos (3U) +#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk +#define GPIO_BRR_BR4_Pos (4U) +#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk +#define GPIO_BRR_BR5_Pos (5U) +#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk +#define GPIO_BRR_BR6_Pos (6U) +#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk +#define GPIO_BRR_BR7_Pos (7U) +#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk +#define GPIO_BRR_BR8_Pos (8U) +#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk +#define GPIO_BRR_BR9_Pos (9U) +#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk +#define GPIO_BRR_BR10_Pos (10U) +#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk +#define GPIO_BRR_BR11_Pos (11U) +#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk +#define GPIO_BRR_BR12_Pos (12U) +#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk +#define GPIO_BRR_BR13_Pos (13U) +#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk +#define GPIO_BRR_BR14_Pos (14U) +#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk +#define GPIO_BRR_BR15_Pos (15U) +#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk + +/****************** Bits definition for GPIO_SECCFGR register ******************/ +#define GPIO_SECCFGR_SEC0_Pos (0U) +#define GPIO_SECCFGR_SEC0_Msk (0x1UL << GPIO_SECCFGR_SEC0_Pos) /*!< 0x00000001 */ +#define GPIO_SECCFGR_SEC0 GPIO_SECCFGR_SEC0_Msk +#define GPIO_SECCFGR_SEC1_Pos (1U) +#define GPIO_SECCFGR_SEC1_Msk (0x1UL << GPIO_SECCFGR_SEC1_Pos) /*!< 0x00000002 */ +#define GPIO_SECCFGR_SEC1 GPIO_SECCFGR_SEC1_Msk +#define GPIO_SECCFGR_SEC2_Pos (2U) +#define GPIO_SECCFGR_SEC2_Msk (0x1UL << GPIO_SECCFGR_SEC2_Pos) /*!< 0x00000004 */ +#define GPIO_SECCFGR_SEC2 GPIO_SECCFGR_SEC2_Msk +#define GPIO_SECCFGR_SEC3_Pos (3U) +#define GPIO_SECCFGR_SEC3_Msk (0x1UL << GPIO_SECCFGR_SEC3_Pos) /*!< 0x00000008 */ +#define GPIO_SECCFGR_SEC3 GPIO_SECCFGR_SEC3_Msk +#define GPIO_SECCFGR_SEC4_Pos (4U) +#define GPIO_SECCFGR_SEC4_Msk (0x1UL << GPIO_SECCFGR_SEC4_Pos) /*!< 0x00000010 */ +#define GPIO_SECCFGR_SEC4 GPIO_SECCFGR_SEC4_Msk +#define GPIO_SECCFGR_SEC5_Pos (5U) +#define GPIO_SECCFGR_SEC5_Msk (0x1UL << GPIO_SECCFGR_SEC5_Pos) /*!< 0x00000020 */ +#define GPIO_SECCFGR_SEC5 GPIO_SECCFGR_SEC5_Msk +#define GPIO_SECCFGR_SEC6_Pos (6U) +#define GPIO_SECCFGR_SEC6_Msk (0x1UL << GPIO_SECCFGR_SEC6_Pos) /*!< 0x00000040 */ +#define GPIO_SECCFGR_SEC6 GPIO_SECCFGR_SEC6_Msk +#define GPIO_SECCFGR_SEC7_Pos (7U) +#define GPIO_SECCFGR_SEC7_Msk (0x1UL << GPIO_SECCFGR_SEC7_Pos) /*!< 0x00000080 */ +#define GPIO_SECCFGR_SEC7 GPIO_SECCFGR_SEC7_Msk +#define GPIO_SECCFGR_SEC8_Pos (8U) +#define GPIO_SECCFGR_SEC8_Msk (0x1UL << GPIO_SECCFGR_SEC8_Pos) /*!< 0x00000100 */ +#define GPIO_SECCFGR_SEC8 GPIO_SECCFGR_SEC8_Msk +#define GPIO_SECCFGR_SEC9_Pos (9U) +#define GPIO_SECCFGR_SEC9_Msk (0x1UL << GPIO_SECCFGR_SEC9_Pos) /*!< 0x00000200 */ +#define GPIO_SECCFGR_SEC9 GPIO_SECCFGR_SEC9_Msk +#define GPIO_SECCFGR_SEC10_Pos (10U) +#define GPIO_SECCFGR_SEC10_Msk (0x1UL << GPIO_SECCFGR_SEC10_Pos) /*!< 0x00000400 */ +#define GPIO_SECCFGR_SEC10 GPIO_SECCFGR_SEC10_Msk +#define GPIO_SECCFGR_SEC11_Pos (11U) +#define GPIO_SECCFGR_SEC11_Msk (x1UL << GPIO_SECCFGR_SEC11_Pos) /*!< 0x00000800 */ +#define GPIO_SECCFGR_SEC11 GPIO_SECCFGR_SEC11_Msk +#define GPIO_SECCFGR_SEC12_Pos (12U) +#define GPIO_SECCFGR_SEC12_Msk (0x1UL << GPIO_SECCFGR_SEC12_Pos) /*!< 0x00001000 */ +#define GPIO_SECCFGR_SEC12 GPIO_SECCFGR_SEC12_Msk +#define GPIO_SECCFGR_SEC13_Pos (13U) +#define GPIO_SECCFGR_SEC13_Msk (0x1UL << GPIO_SECCFGR_SEC13_Pos) /*!< 0x00002000 */ +#define GPIO_SECCFGR_SEC13 GPIO_SECCFGR_SEC13_Msk +#define GPIO_SECCFGR_SEC14_Pos (14U) +#define GPIO_SECCFGR_SEC14_Msk (0x1UL << GPIO_SECCFGR_SEC14_Pos) /*!< 0x00004000 */ +#define GPIO_SECCFGR_SEC14 GPIO_SECCFGR_SEC14_Msk +#define GPIO_SECCFGR_SEC15_Pos (15U) +#define GPIO_SECCFGR_SEC15_Msk (0x1UL << GPIO_SECCFGR_SEC15_Pos) /*!< 0x00008000 */ +#define GPIO_SECCFGR_SEC15 GPIO_SECCFGR_SEC15_Msk + + +/*****************************************************************************/ +/* */ +/* Global TrustZone Control */ +/* */ +/*****************************************************************************/ +/******************* Bits definition for GTZC_TZSC_CR register ******************/ +#define GTZC_TZSC_CR_LCK_Pos (0U) +#define GTZC_TZSC_CR_LCK_Msk (0x01UL << GTZC_TZSC_CR_LCK_Pos) /*!< 0x00000001 */ +#define GTZC_TZSC_CR_LCK GTZC_TZSC_CR_LCK_Msk /*!< GTZC Secure and privilege configurations lock */ + +/******* Bits definition for GTZC_TZSC_SECCFGRx/_PRIVCFGRx registers *****/ +/******* Bits definition for GTZC_TZIC_IERx/_SRx/_IFCRx registers ********/ + +/******************* Bits definition for GTZC_TZSC_SECCFGR1 register ***************/ +#define GTZC_CFGR1_TIM2_Pos GTZC_TZSC_SECCFGR1_TIM2SEC_Pos +#define GTZC_CFGR1_TIM2_Msk (0x01UL << GTZC_CFGR1_TIM2_Pos) +#define GTZC_CFGR1_TIM3_Pos GTZC_TZSC_SECCFGR1_TIM3SEC_Pos +#define GTZC_CFGR1_TIM3_Msk (0x01UL << GTZC_CFGR1_TIM3_Pos) +#define GTZC_CFGR1_WWDG_Pos GTZC_TZSC_SECCFGR1_WWDGSEC_Pos +#define GTZC_CFGR1_WWDG_Msk (0x01UL << GTZC_CFGR1_WWDG_Pos) +#define GTZC_CFGR1_IWDG_Pos GTZC_TZSC_SECCFGR1_IWDGSEC_Pos +#define GTZC_CFGR1_IWDG_Msk (0x01UL << GTZC_CFGR1_IWDG_Pos) +#define GTZC_CFGR1_USART2_Pos GTZC_TZSC_SECCFGR1_USART2SEC_Pos +#define GTZC_CFGR1_USART2_Msk (0x01UL << GTZC_CFGR1_USART2_Pos) +#define GTZC_CFGR1_I2C1_Pos GTZC_TZSC_SECCFGR1_I2C1SEC_Pos +#define GTZC_CFGR1_I2C1_Msk (0x01UL << GTZC_CFGR1_I2C1_Pos) +#define GTZC_CFGR1_LPTIM2_Pos GTZC_TZSC_SECCFGR1_LPTIM2SEC_Pos +#define GTZC_CFGR1_LPTIM2_Msk (0x01UL << GTZC_CFGR1_LPTIM2_Pos) + +/******************* Bits definition for GTZC_TZSC_SECCFGR2 register ***************/ +#define GTZC_CFGR2_TIM1_Pos GTZC_TZSC_SECCFGR2_TIM1SEC_Pos +#define GTZC_CFGR2_TIM1_Msk (0x01UL << GTZC_CFGR2_TIM1_Pos) +#define GTZC_CFGR2_SPI1_Pos GTZC_TZSC_SECCFGR2_SPI1SEC_Pos +#define GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos) +#define GTZC_CFGR2_USART1_Pos GTZC_TZSC_SECCFGR2_USART1SEC_Pos +#define GTZC_CFGR2_USART1_Msk (0x01UL << GTZC_CFGR2_USART1_Pos) +#define GTZC_CFGR2_TIM16_Pos GTZC_TZSC_SECCFGR2_TIM16SEC_Pos +#define GTZC_CFGR2_TIM16_Msk (0x01UL << GTZC_CFGR2_TIM16_Pos) +#define GTZC_CFGR2_TIM17_Pos GTZC_TZSC_SECCFGR2_TIM17SEC_Pos +#define GTZC_CFGR2_TIM17_Msk (0x01UL << GTZC_CFGR2_TIM17_Pos) +#define GTZC_CFGR2_SAI1_Pos GTZC_TZSC_SECCFGR2_SAI1SEC_Pos +#define GTZC_CFGR2_SAI1_Msk (0x01UL << GTZC_CFGR2_SAI1_Pos) +#define GTZC_CFGR2_SPI3_Pos GTZC_TZSC_SECCFGR2_SPI3SEC_Pos +#define GTZC_CFGR2_SPI3_Msk (0x01UL << GTZC_CFGR2_SPI3_Pos) +#define GTZC_CFGR2_LPUART1_Pos GTZC_TZSC_SECCFGR2_LPUART1SEC_Pos +#define GTZC_CFGR2_LPUART1_Msk (0x01UL << GTZC_CFGR2_LPUART1_Pos) +#define GTZC_CFGR2_I2C3_Pos GTZC_TZSC_SECCFGR2_I2C3SEC_Pos +#define GTZC_CFGR2_I2C3_Msk (0x01UL << GTZC_CFGR2_I2C3_Pos) +#define GTZC_CFGR2_LPTIM1_Pos GTZC_TZSC_SECCFGR2_LPTIM1SEC_Pos +#define GTZC_CFGR2_LPTIM1_Msk (0x01UL << GTZC_CFGR2_LPTIM1_Pos) +#define GTZC_CFGR2_COMP_Pos GTZC_TZSC_SECCFGR2_COMPSEC_Pos +#define GTZC_CFGR2_COMP_Msk (0x01UL << GTZC_CFGR2_COMP_Pos) +#define GTZC_CFGR2_ADC4_Pos GTZC_TZSC_SECCFGR2_ADC4SEC_Pos +#define GTZC_CFGR2_ADC4_Msk (0x01UL << GTZC_CFGR2_ADC4_Pos) + +/******************* Bits definition for GTZC_TZSC_SECCFGR3 register ***************/ +#define GTZC_CFGR3_CRC_Pos GTZC_TZSC_SECCFGR3_CRCSEC_Pos +#define GTZC_CFGR3_CRC_Msk (0x01UL << GTZC_CFGR3_CRC_Pos) +#define GTZC_CFGR3_TSC_Pos GTZC_TZSC_SECCFGR3_TSCSEC_Pos +#define GTZC_CFGR3_TSC_Msk (0x01UL << GTZC_CFGR3_TSC_Pos) +#define GTZC_CFGR3_ICACHE_REG_Pos GTZC_TZSC_SECCFGR3_ICACHE_REGSEC_Pos +#define GTZC_CFGR3_ICACHE_REG_Msk (0x01UL << GTZC_CFGR3_ICACHE_REG_Pos) +#define GTZC_CFGR3_AES_Pos GTZC_TZSC_SECCFGR3_AESSEC_Pos +#define GTZC_CFGR3_AES_Msk (0x01UL << GTZC_CFGR3_AES_Pos) +#define GTZC_CFGR3_HASH_Pos GTZC_TZSC_SECCFGR3_HASHSEC_Pos +#define GTZC_CFGR3_HASH_Msk (0x01UL << GTZC_CFGR3_HASH_Pos) +#define GTZC_CFGR3_RNG_Pos GTZC_TZSC_SECCFGR3_RNGSEC_Pos +#define GTZC_CFGR3_RNG_Msk (0x01UL << GTZC_CFGR3_RNG_Pos) +#define GTZC_CFGR3_SAES_Pos GTZC_TZSC_SECCFGR3_SAESSEC_Pos +#define GTZC_CFGR3_SAES_Msk (0x01UL << GTZC_CFGR3_SAES_Pos) +#define GTZC_CFGR3_HSEM_Pos GTZC_TZIC_IER3_HSEMIE_Pos +#define GTZC_CFGR3_HSEM_Msk (0x01UL << GTZC_CFGR3_HSEM_Pos) +#define GTZC_CFGR3_PKA_Pos GTZC_TZSC_SECCFGR3_PKASEC_Pos +#define GTZC_CFGR3_PKA_Msk (0x01UL << GTZC_CFGR3_PKA_Pos) +#define GTZC_CFGR3_RAMCFG_Pos GTZC_TZSC_SECCFGR3_RAMCFGSEC_Pos +#define GTZC_CFGR3_RAMCFG_Msk (0x01UL << GTZC_CFGR3_RAMCFG_Pos) +#define GTZC_CFGR3_RADIO_Pos GTZC_TZSC_SECCFGR3_RADIOSEC_Pos +#define GTZC_CFGR3_RADIO_Msk (0x01UL << GTZC_CFGR3_RADIO_Pos) +#define GTZC_CFGR3_PTACONV_Pos GTZC_TZSC_SECCFGR3_PTACONVSEC_Pos +#define GTZC_CFGR3_PTACONV_Msk (0x01UL << GTZC_CFGR3_PTACONV_Pos) + +/******************* Bits definition for GTZC_TZIC_IER4 register ***************/ +#define GTZC_CFGR4_GPDMA1_Pos GTZC_TZIC_IER4_GPDMA1IE_Pos +#define GTZC_CFGR4_GPDMA1_Msk (0x01UL << GTZC_CFGR4_GPDMA1_Pos) +#define GTZC_CFGR4_FLASH_Pos GTZC_TZIC_IER4_FLASHIE_Pos +#define GTZC_CFGR4_FLASH_Msk (0x01UL << GTZC_CFGR4_FLASH_Pos) +#define GTZC_CFGR4_FLASH_REG_Pos GTZC_TZIC_IER4_FLASH_REGIE_Pos +#define GTZC_CFGR4_FLASH_REG_Msk (0x01UL << GTZC_CFGR4_FLASH_REG_Pos) +#define GTZC_CFGR4_TZSC_Pos GTZC_TZIC_IER4_TZSCIE_Pos +#define GTZC_CFGR4_TZSC_Msk (0x01UL << GTZC_CFGR4_TZSC_Pos) +#define GTZC_CFGR4_TZIC_Pos GTZC_TZIC_IER4_TZICIE_Pos +#define GTZC_CFGR4_TZIC_Msk (0x01UL << GTZC_CFGR4_TZIC_Pos) +#define GTZC_CFGR4_SYSCFG_Pos GTZC_TZIC_IER4_SYSCFGIE_Pos +#define GTZC_CFGR4_SYSCFG_Msk (0x01UL << GTZC_CFGR4_SYSCFG_Pos) +#define GTZC_CFGR4_RTC_Pos GTZC_TZIC_IER4_RTCIE_Pos +#define GTZC_CFGR4_RTC_Msk (0x01UL << GTZC_CFGR4_RTC_Pos) +#define GTZC_CFGR4_TAMP_Pos GTZC_TZIC_IER4_TAMPIE_Pos +#define GTZC_CFGR4_TAMP_Msk (0x01UL << GTZC_CFGR4_TAMP_Pos) +#define GTZC_CFGR4_PWR_Pos GTZC_TZIC_IER4_PWRIE_Pos +#define GTZC_CFGR4_PWR_Msk (0x01UL << GTZC_CFGR4_PWR_Pos) +#define GTZC_CFGR4_RCC_Pos GTZC_TZIC_IER4_RCCIE_Pos +#define GTZC_CFGR4_RCC_sk (0x01UL << GTZC_CFGR4_RCC_Pos) +#define GTZC_CFGR4_EXTI_Pos GTZC_TZIC_IER4_EXTIIE_Pos +#define GTZC_CFGR4_EXTI_Msk (0x01UL << GTZC_CFGR4_EXTI_Pos) +#define GTZC_CFGR4_SRAM1_Pos GTZC_TZIC_IER4_SRAM1IE_Pos +#define GTZC_CFGR4_SRAM1_Msk (0x01UL << GTZC_CFGR4_SRAM1_Pos) +#define GTZC_CFGR4_MPCBB1_REG_Pos GTZC_TZIC_IER4_MPCBB1IE_Pos +#define GTZC_CFGR4_MPCBB1_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB1_REG_Pos) +#define GTZC_CFGR4_SRAM2_Pos GTZC_TZIC_IER4_SRAM2IE_Pos +#define GTZC_CFGR4_SRAM2_Msk (0x01UL << GTZC_CFGR4_SRAM2_Pos) +#define GTZC_CFGR4_MPCBB2_REG_Pos GTZC_TZIC_IER4_MPCBB2IE_Pos +#define GTZC_CFGR4_MPCBB2_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB2_REG_Pos) +#define GTZC_CFGR4_SRAM6_Pos GTZC_TZIC_IER4_SRAM6IE_Pos +#define GTZC_CFGR4_SRAM6_Msk (0x01UL << GTZC_CFGR4_SRAM6_Pos) +#define GTZC_CFGR4_MPCBB6_REG_Pos GTZC_TZIC_IER4_MPCBB6IE_Pos +#define GTZC_CFGR4_MPCBB6_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB6_REG_Pos) + +/*************** Bits definition for register x=1 (GTZC_TZSC_SECCFGR1) *************/ +#define GTZC_TZSC_SECCFGR1_TIM2SEC_Pos (0U) +#define GTZC_TZSC_SECCFGR1_TIM2SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR1_TIM2SEC_Pos) +#define GTZC_TZSC_SECCFGR1_TIM2SEC GTZC_TZSC_SECCFGR1_TIM2SEC_Msk /*!< secure access mode for TIM2 */ +#define GTZC_TZSC_SECCFGR1_TIM3SEC_Pos (1U) +#define GTZC_TZSC_SECCFGR1_TIM3SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR1_TIM3SEC_Pos) +#define GTZC_TZSC_SECCFGR1_TIM3SEC GTZC_TZSC_SECCFGR1_TIM3SEC_Msk /*!< secure access mode for TIM3 */ +#define GTZC_TZSC_SECCFGR1_WWDGSEC_Pos (6U) +#define GTZC_TZSC_SECCFGR1_WWDGSEC_Msk (0x01UL << GTZC_TZSC_SECCFGR1_WWDGSEC_Pos) +#define GTZC_TZSC_SECCFGR1_WWDGSEC GTZC_TZSC_SECCFGR1_WWDGSEC_Msk /*!< secure access mode for WWDG */ +#define GTZC_TZSC_SECCFGR1_IWDGSEC_Pos (7U) +#define GTZC_TZSC_SECCFGR1_IWDGSEC_Msk (0x01UL << GTZC_TZSC_SECCFGR1_IWDGSEC_Pos) +#define GTZC_TZSC_SECCFGR1_IWDGSEC GTZC_TZSC_SECCFGR1_IWDGSEC_Msk /*!< secure access mode for IWDG */ +#define GTZC_TZSC_SECCFGR1_USART2SEC_Pos (9U) +#define GTZC_TZSC_SECCFGR1_USART2SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR1_USART2SEC_Pos) +#define GTZC_TZSC_SECCFGR1_USART2SEC GTZC_TZSC_SECCFGR1_USART2SEC_Msk /*!< secure access mode for USART2 */ +#define GTZC_TZSC_SECCFGR1_I2C1SEC_Pos (13U) +#define GTZC_TZSC_SECCFGR1_I2C1SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR1_I2C1SEC_Pos) +#define GTZC_TZSC_SECCFGR1_I2C1SEC GTZC_TZSC_SECCFGR1_I2C1SEC_Msk /*!< secure access mode for I2C1 */ +#define GTZC_TZSC_SECCFGR1_LPTIM2SEC_Pos (17U) +#define GTZC_TZSC_SECCFGR1_LPTIM2SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR1_LPTIM2SEC_Pos) +#define GTZC_TZSC_SECCFGR1_LPTIM2SEC GTZC_TZSC_SECCFGR1_LPTIM2SEC_Msk /*!< secure access mode for LPTIM2 */ + +/*************** Bits definition for register x=2 (GTZC_TZSC_SECCFGR2) *************/ +#define GTZC_TZSC_SECCFGR2_TIM1SEC_Pos (0U) +#define GTZC_TZSC_SECCFGR2_TIM1SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR2_TIM1SEC_Pos) +#define GTZC_TZSC_SECCFGR2_TIM1SEC GTZC_TZSC_SECCFGR2_TIM1SEC_Msk /*!< secure access mode for TIM1 */ +#define GTZC_TZSC_SECCFGR2_SPI1SEC_Pos (1U) +#define GTZC_TZSC_SECCFGR2_SPI1SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR2_SPI1SEC_Pos) +#define GTZC_TZSC_SECCFGR2_SPI1SEC GTZC_TZSC_SECCFGR2_SPI1SEC_Msk /*!< secure access mode for SPI1 */ +#define GTZC_TZSC_SECCFGR2_USART1SEC_Pos (3U) +#define GTZC_TZSC_SECCFGR2_USART1SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR2_USART1SEC_Pos) +#define GTZC_TZSC_SECCFGR2_USART1SEC GTZC_TZSC_SECCFGR2_USART1SEC_Msk /*!< secure access mode for USART1 */ +#define GTZC_TZSC_SECCFGR2_TIM16SEC_Pos (5U) +#define GTZC_TZSC_SECCFGR2_TIM16SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR2_TIM16SEC_Pos) +#define GTZC_TZSC_SECCFGR2_TIM16SEC GTZC_TZSC_SECCFGR2_TIM16SEC_Msk /*!< secure access mode for TIM16 */ +#define GTZC_TZSC_SECCFGR2_TIM17SEC_Pos (6U) +#define GTZC_TZSC_SECCFGR2_TIM17SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR2_TIM17SEC_Pos) +#define GTZC_TZSC_SECCFGR2_TIM17SEC GTZC_TZSC_SECCFGR2_TIM17SEC_Msk /*!< secure access mode for TIM17 */ +#define GTZC_TZSC_SECCFGR2_SAI1SEC_Pos (7U) +#define GTZC_TZSC_SECCFGR2_SAI1SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR2_SAI1SEC_Pos) +#define GTZC_TZSC_SECCFGR2_SAI1SEC GTZC_TZSC_SECCFGR2_SAI1SEC_Msk /*!< secure access mode for SAI1 */ +#define GTZC_TZSC_SECCFGR2_SPI3SEC_Pos (16U) +#define GTZC_TZSC_SECCFGR2_SPI3SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR2_SPI3SEC_Pos) +#define GTZC_TZSC_SECCFGR2_SPI3SEC GTZC_TZSC_SECCFGR2_SPI3SEC_Msk /*!< secure access mode for SPI3 */ +#define GTZC_TZSC_SECCFGR2_LPUART1SEC_Pos (17U) +#define GTZC_TZSC_SECCFGR2_LPUART1SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR2_LPUART1SEC_Pos) +#define GTZC_TZSC_SECCFGR2_LPUART1SEC GTZC_TZSC_SECCFGR2_LPUART1SEC_Msk /*!< secure access mode for LPUART1 */ +#define GTZC_TZSC_SECCFGR2_I2C3SEC_Pos (18U) +#define GTZC_TZSC_SECCFGR2_I2C3SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR2_I2C3SEC_Pos) +#define GTZC_TZSC_SECCFGR2_I2C3SEC GTZC_TZSC_SECCFGR2_I2C3SEC_Msk /*!< secure access mode for I2C3 */ +#define GTZC_TZSC_SECCFGR2_LPTIM1SEC_Pos (19U) +#define GTZC_TZSC_SECCFGR2_LPTIM1SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR2_LPTIM1SEC_Pos) +#define GTZC_TZSC_SECCFGR2_LPTIM1SEC GTZC_TZSC_SECCFGR2_LPTIM1SEC_Msk /*!< secure access mode for LPTIM1 */ +#define GTZC_TZSC_SECCFGR2_COMPSEC_Pos (23U) +#define GTZC_TZSC_SECCFGR2_COMPSEC_Msk (0x01UL << GTZC_TZSC_SECCFGR2_COMPSEC_Pos) +#define GTZC_TZSC_SECCFGR2_COMPSEC GTZC_TZSC_SECCFGR2_COMPSEC_Msk /*!< secure access mode for COMP */ +#define GTZC_TZSC_SECCFGR2_ADC4SEC_Pos (24U) +#define GTZC_TZSC_SECCFGR2_ADC4SEC_Msk (0x01UL << GTZC_TZSC_SECCFGR2_ADC4SEC_Pos) +#define GTZC_TZSC_SECCFGR2_ADC4SEC GTZC_TZSC_SECCFGR2_ADC4SEC_Msk /*!< secure access mode for ADC4 */ + +/*************** Bits definition for register x=3 (GTZC_TZSC_SECCFGR3) *************/ +#define GTZC_TZSC_SECCFGR3_CRCSEC_Pos (3U) +#define GTZC_TZSC_SECCFGR3_CRCSEC_Msk (0x01UL << GTZC_TZSC_SECCFGR3_CRCSEC_Pos) +#define GTZC_TZSC_SECCFGR3_CRCSEC GTZC_TZSC_SECCFGR3_CRCSEC_Msk /*!< secure access mode for CRC */ +#define GTZC_TZSC_SECCFGR3_TSCSEC_Pos (4U) +#define GTZC_TZSC_SECCFGR3_TSCSEC_Msk (0x01UL << GTZC_TZSC_SECCFGR3_TSCSEC_Pos) +#define GTZC_TZSC_SECCFGR3_TSCSEC GTZC_TZSC_SECCFGR3_TSCSEC_Msk /*!< secure access mode for TSC */ +#define GTZC_TZSC_SECCFGR3_ICACHE_REGSEC_Pos (6U) +#define GTZC_TZSC_SECCFGR3_ICACHE_REGSEC_Msk (0x01UL << GTZC_TZSC_SECCFGR3_ICACHE_REGSEC_Pos) +#define GTZC_TZSC_SECCFGR3_ICACHE_REGSEC GTZC_TZSC_SECCFGR3_ICACHE_REGSEC_Msk /*!< secure access mode for ICACHE_REG */ +#define GTZC_TZSC_SECCFGR3_AESSEC_Pos (11U) +#define GTZC_TZSC_SECCFGR3_AESSEC_Msk (0x01UL << GTZC_TZSC_SECCFGR3_AESSEC_Pos) +#define GTZC_TZSC_SECCFGR3_AESSEC GTZC_TZSC_SECCFGR3_AESSEC_Msk /*!< secure access mode for AES */ +#define GTZC_TZSC_SECCFGR3_HASHSEC_Pos (12U) +#define GTZC_TZSC_SECCFGR3_HASHSEC_Msk (0x01UL << GTZC_TZSC_SECCFGR3_HASHSEC_Pos) +#define GTZC_TZSC_SECCFGR3_HASHSEC GTZC_TZSC_SECCFGR3_HASHSEC_Msk /*!< secure access mode for HASH */ +#define GTZC_TZSC_SECCFGR3_RNGSEC_Pos (13U) +#define GTZC_TZSC_SECCFGR3_RNGSEC_Msk (0x01UL << GTZC_TZSC_SECCFGR3_RNGSEC_Pos) +#define GTZC_TZSC_SECCFGR3_RNGSEC GTZC_TZSC_SECCFGR3_RNGSEC_Msk /*!< secure access mode for RNG */ +#define GTZC_TZSC_SECCFGR3_SAESSEC_Pos (14U) +#define GTZC_TZSC_SECCFGR3_SAESSEC_Msk (0x01UL << GTZC_TZSC_SECCFGR3_SAESSEC_Pos) +#define GTZC_TZSC_SECCFGR3_SAESSEC GTZC_TZSC_SECCFGR3_SAESSEC_Msk /*!< secure access mode for SAES */ +#define GTZC_TZSC_SECCFGR3_PKASEC_Pos (16U) +#define GTZC_TZSC_SECCFGR3_PKASEC_Msk (0x01UL << GTZC_TZSC_SECCFGR3_PKASEC_Pos) +#define GTZC_TZSC_SECCFGR3_PKASEC GTZC_TZSC_SECCFGR3_PKASEC_Msk /*!< secure access mode for PKA */ +#define GTZC_TZSC_SECCFGR3_RAMCFGSEC_Pos (22U) +#define GTZC_TZSC_SECCFGR3_RAMCFGSEC_Msk (0x01UL << GTZC_TZSC_SECCFGR3_RAMCFGSEC_Pos) +#define GTZC_TZSC_SECCFGR3_RAMCFGSEC GTZC_TZSC_SECCFGR3_RAMCFGSEC_Msk /*!< secure access mode for RAMCFG */ +#define GTZC_TZSC_SECCFGR3_RADIOSEC_Pos (23U) +#define GTZC_TZSC_SECCFGR3_RADIOSEC_Msk (0x01UL << GTZC_TZSC_SECCFGR3_RADIOSEC_Pos) +#define GTZC_TZSC_SECCFGR3_RADIOSEC GTZC_TZSC_SECCFGR3_RADIOSEC_Msk /*!< secure access mode for 2.4 GHz RADIO */ +#define GTZC_TZSC_SECCFGR3_PTACONVSEC_Pos (24U) +#define GTZC_TZSC_SECCFGR3_PTACONVSEC_Msk (0x01UL << GTZC_TZSC_SECCFGR3_PTACONVSEC_Pos) +#define GTZC_TZSC_SECCFGR3_PTACONVSEC GTZC_TZSC_SECCFGR3_PTACONVSEC_Msk /*!< secure access mode for PTACONV */ + +/******************* Bits definition for GTZC_TZSC_PRIVCFGR1 register ***************/ +#define GTZC_TZSC_PRIVCFGR1_TIM2PRIV_Pos (0U) +#define GTZC_TZSC_PRIVCFGR1_TIM2PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR1_TIM2PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR1_TIM2PRIV GTZC_TZSC_PRIVCFGR1_TIM2PRIV_Msk /*!< privileged access mode for TIM2 */ +#define GTZC_TZSC_PRIVCFGR1_TIM3PRIV_Pos (1U) +#define GTZC_TZSC_PRIVCFGR1_TIM3PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR1_TIM3PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR1_TIM3PRIV GTZC_TZSC_PRIVCFGR1_TIM3PRIV_Msk /*!< privileged access mode for TIM3 */ +#define GTZC_TZSC_PRIVCFGR1_WWDGPRIV_Pos (6U) +#define GTZC_TZSC_PRIVCFGR1_WWDGPRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR1_WWDGPRIV_Pos) +#define GTZC_TZSC_PRIVCFGR1_WWDGPRIV GTZC_TZSC_PRIVCFGR1_WWDGPRIV_Msk /*!< privileged access mode for WWDG */ +#define GTZC_TZSC_PRIVCFGR1_IWDGPRIV_Pos (7U) +#define GTZC_TZSC_PRIVCFGR1_IWDGPRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR1_IWDGPRIV_Pos) +#define GTZC_TZSC_PRIVCFGR1_IWDGPRIV GTZC_TZSC_PRIVCFGR1_IWDGPRIV_Msk /*!< privileged access mode for IWDG */ +#define GTZC_TZSC_PRIVCFGR1_USART2PRIV_Pos (9U) +#define GTZC_TZSC_PRIVCFGR1_USART2PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR1_USART2PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR1_USART2PRIV GTZC_TZSC_PRIVCFGR1_USART2PRIV_Msk /*!< privileged access mode for USART2 */ +#define GTZC_TZSC_PRIVCFGR1_I2C1PRIV_Pos (13U) +#define GTZC_TZSC_PRIVCFGR1_I2C1PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR1_I2C1PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR1_I2C1PRIV GTZC_TZSC_PRIVCFGR1_I2C1PRIV_Msk /*!< privileged access mode for I2C1 */ +#define GTZC_TZSC_PRIVCFGR1_LPTIM2PRIV_Pos (17U) +#define GTZC_TZSC_PRIVCFGR1_LPTIM2PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR1_LPTIM2PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR1_LPTIM2PRIV GTZC_TZSC_PRIVCFGR1_LPTIM2PRIV_Msk /*!< privileged access mode for LPTIM2 */ + +/******************* Bits definition for GTZC_TZSC_PRIVCFGR2 register ***************/ +#define GTZC_TZSC_PRIVCFGR2_TIM1PRIV_Pos (0U) +#define GTZC_TZSC_PRIVCFGR2_TIM1PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR2_TIM1PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR2_TIM1PRIV GTZC_TZSC_PRIVCFGR2_TIM1PRIV_Msk /*!< privileged access mode for TIM1 */ +#define GTZC_TZSC_PRIVCFGR2_SPI1PRIV_Pos (1U) +#define GTZC_TZSC_PRIVCFGR2_SPI1PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR2_SPI1PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR2_SPI1PRIV GTZC_TZSC_PRIVCFGR2_SPI1PRIV_Msk /*!< privileged access mode for SPI1 */ +#define GTZC_TZSC_PRIVCFGR2_USART1PRIV_Pos (3U) +#define GTZC_TZSC_PRIVCFGR2_USART1PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR2_USART1PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR2_USART1PRIV GTZC_TZSC_PRIVCFGR2_USART1PRIV_Msk /*!< privileged access mode for USART1 */ +#define GTZC_TZSC_PRIVCFGR2_TIM16PRIV_Pos (5U) +#define GTZC_TZSC_PRIVCFGR2_TIM16PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR2_TIM16PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR2_TIM16PRIV GTZC_TZSC_PRIVCFGR2_TIM16PRIV_Msk /*!< privileged access mode for TIM16 */ +#define GTZC_TZSC_PRIVCFGR2_TIM17PRIV_Pos (6U) +#define GTZC_TZSC_PRIVCFGR2_TIM17PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR2_TIM17PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR2_TIM17PRIV GTZC_TZSC_PRIVCFGR2_TIM17PRIV_Msk /*!< privileged access mode for TIM17 */ +#define GTZC_TZSC_PRIVCFGR2_SAI1PRIV_Pos (7U) +#define GTZC_TZSC_PRIVCFGR2_SAI1PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR2_SAI1PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR2_SAI1PRIV GTZC_TZSC_PRIVCFGR2_SAI1PRIV_Msk /*!< privileged access mode for SAI1 */ +#define GTZC_TZSC_PRIVCFGR2_SPI3PRIV_Pos (16U) +#define GTZC_TZSC_PRIVCFGR2_SPI3PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR2_SPI3PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR2_SPI3PRIV GTZC_TZSC_PRIVCFGR2_SPI3PRIV_Msk /*!< privileged access mode for SPI3 */ +#define GTZC_TZSC_PRIVCFGR2_LPUART1PRIV_Pos (17U) +#define GTZC_TZSC_PRIVCFGR2_LPUART1PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR2_LPUART1PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR2_LPUART1PRIV GTZC_TZSC_PRIVCFGR2_LPUART1PRIV_Msk /*!< privileged access mode for LPUART1 */ +#define GTZC_TZSC_PRIVCFGR2_I2C3PRIV_Pos (18U) +#define GTZC_TZSC_PRIVCFGR2_I2C3PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR2_I2C3PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR2_I2C3PRIV GTZC_TZSC_PRIVCFGR2_I2C3PRIV_Msk /*!< privileged access mode for I2C3 */ +#define GTZC_TZSC_PRIVCFGR2_LPTIM1PRIV_Pos (19U) +#define GTZC_TZSC_PRIVCFGR2_LPTIM1PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR2_LPTIM1PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR2_LPTIM1PRIV GTZC_TZSC_PRIVCFGR2_LPTIM1PRIV_Msk /*!< privileged access mode for LPTIM1 */ +#define GTZC_TZSC_PRIVCFGR2_COMPPRIV_Pos (23U) +#define GTZC_TZSC_PRIVCFGR2_COMPPRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR2_COMPPRIV_Pos) +#define GTZC_TZSC_PRIVCFGR2_COMPPRIV GTZC_TZSC_PRIVCFGR2_COMPPRIV_Msk /*!< privileged access mode for COMP */ +#define GTZC_TZSC_PRIVCFGR2_ADC4PRIV_Pos (24U) +#define GTZC_TZSC_PRIVCFGR2_ADC4PRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR2_ADC4PRIV_Pos) +#define GTZC_TZSC_PRIVCFGR2_ADC4PRIV GTZC_TZSC_PRIVCFGR2_ADC4PRIV_Msk /*!< privileged access mode for ADC4 */ + +/******************* Bits definition for GTZC_TZSC_PRIVCFGR3 register ***************/ +#define GTZC_TZSC_PRIVCFGR3_CRCPRIV_Pos (3U) +#define GTZC_TZSC_PRIVCFGR3_CRCPRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR3_CRCPRIV_Pos) +#define GTZC_TZSC_PRIVCFGR3_CRCPRIV GTZC_TZSC_PRIVCFGR3_CRCPRIV_Msk /*!< privileged access mode for CRC */ +#define GTZC_TZSC_PRIVCFGR3_TSCPRIV_Pos (4U) +#define GTZC_TZSC_PRIVCFGR3_TSCPRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR3_TSCPRIV_Pos) +#define GTZC_TZSC_PRIVCFGR3_TSCPRIV GTZC_TZSC_PRIVCFGR3_TSCPRIV_Msk /*!< privileged access mode for TSC */ +#define GTZC_TZSC_PRIVCFGR3_ICACHE_REGPRIV_Pos (6U) +#define GTZC_TZSC_PRIVCFGR3_ICACHE_REGPRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR3_ICACHE_REGPRIV_Pos) +#define GTZC_TZSC_PRIVCFGR3_ICACHE_REGPRIV GTZC_TZSC_PRIVCFGR3_ICACHE_REGPRIV_Msk /*!< privileged access mode for ICACHE_REG */ +#define GTZC_TZSC_PRIVCFGR3_AESPRIV_Pos (11U) +#define GTZC_TZSC_PRIVCFGR3_AESPRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR3_AESPRIV_Pos) +#define GTZC_TZSC_PRIVCFGR3_AESPRIV GTZC_TZSC_PRIVCFGR3_AESPRIV_Msk /*!< privileged access mode for AES */ +#define GTZC_TZSC_PRIVCFGR3_HASHPRIV_Pos (12U) +#define GTZC_TZSC_PRIVCFGR3_HASHPRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR3_HASHPRIV_Pos) +#define GTZC_TZSC_PRIVCFGR3_HASHPRIV GTZC_TZSC_PRIVCFGR3_HASHPRIV_Msk /*!< privileged access mode for HASH */ +#define GTZC_TZSC_PRIVCFGR3_RNGPRIV_Pos (13U) +#define GTZC_TZSC_PRIVCFGR3_RNGPRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR3_RNGPRIV_Pos) +#define GTZC_TZSC_PRIVCFGR3_RNGPRIV GTZC_TZSC_PRIVCFGR3_RNGPRIV_Msk /*!< privileged access mode for RNG */ +#define GTZC_TZSC_PRIVCFGR3_SAESPRIV_Pos (14U) +#define GTZC_TZSC_PRIVCFGR3_SAESPRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR3_SAESPRIV_Pos) +#define GTZC_TZSC_PRIVCFGR3_SAESPRIV GTZC_TZSC_PRIVCFGR3_SAESPRIV_Msk /*!< privileged access mode for SAES */ +#define GTZC_TZSC_PRIVCFGR3_PKAPRIV_Pos (16U) +#define GTZC_TZSC_PRIVCFGR3_PKAPRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR3_PKAPRIV_Pos) +#define GTZC_TZSC_PRIVCFGR3_PKAPRIV GTZC_TZSC_PRIVCFGR3_PKAPRIV_Msk /*!< privileged access mode for PKA */ +#define GTZC_TZSC_PRIVCFGR3_RAMCFGPRIV_Pos (22U) +#define GTZC_TZSC_PRIVCFGR3_RAMCFGPRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR3_RAMCFGPRIV_Pos) +#define GTZC_TZSC_PRIVCFGR3_RAMCFGPRIV GTZC_TZSC_PRIVCFGR3_RAMCFGPRIV_Msk /*!< privileged access mode for RAMCFG */ +#define GTZC_TZSC_PRIVCFGR3_RADIOPRIV_Pos (23U) +#define GTZC_TZSC_PRIVCFGR3_RADIOPRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR3_RADIOPRIV_Pos) +#define GTZC_TZSC_PRIVCFGR3_RADIOPRIV GTZC_TZSC_PRIVCFGR3_RADIOPRIV_Msk /*!< privileged access mode for 2.4 GHz RADIO */ +#define GTZC_TZSC_PRIVCFGR3_PTACONVPRIV_Pos (24U) +#define GTZC_TZSC_PRIVCFGR3_PTACONVPRIV_Msk (0x01UL << GTZC_TZSC_PRIVCFGR3_PTACONVPRIV_Pos) +#define GTZC_TZSC_PRIVCFGR3_PTACONVPRIV GTZC_TZSC_PRIVCFGR3_PTACONVPRIV_Msk /*!< privileged access mode for PTACONV */ + +/******************* Bits definition for GTZC_TZIC_IER1 register ***************/ +#define GTZC_TZIC_IER1_TIM2IE_Pos (0U) +#define GTZC_TZIC_IER1_TIM2IE_Msk (0x01UL << GTZC_TZIC_IER1_TIM2IE_Pos) +#define GTZC_TZIC_IER1_TIM2IE GTZC_TZIC_IER1_TIM2IE_Msk /*!< illegal access interrupt enable for TIM2 */ +#define GTZC_TZIC_IER1_TIM3IE_Pos (1U) +#define GTZC_TZIC_IER1_TIM3IE_Msk (0x01UL << GTZC_TZIC_IER1_TIM3IE_Pos) +#define GTZC_TZIC_IER1_TIM3IE GTZC_TZIC_IER1_TIM3IE_Msk /*!< illegal access interrupt enable for TIM3 */ +#define GTZC_TZIC_IER1_WWDGIE_Pos (6U) +#define GTZC_TZIC_IER1_WWDGIE_Msk (0x01UL << GTZC_TZIC_IER1_WWDGIE_Pos) +#define GTZC_TZIC_IER1_WWDGIE GTZC_TZIC_IER1_WWDGIE_Msk /*!< illegal access interrupt enable for WWDG */ +#define GTZC_TZIC_IER1_IWDGIE_Pos (7U) +#define GTZC_TZIC_IER1_IWDGIE_Msk (0x01UL << GTZC_TZIC_IER1_IWDGIE_Pos) +#define GTZC_TZIC_IER1_IWDGIE GTZC_TZIC_IER1_IWDGIE_Msk /*!< illegal access interrupt enable for IWDG */ +#define GTZC_TZIC_IER1_USART2IE_Pos (9U) +#define GTZC_TZIC_IER1_USART2IE_Msk (0x01UL << GTZC_TZIC_IER1_USART2IE_Pos) +#define GTZC_TZIC_IER1_USART2IE GTZC_TZIC_IER1_USART2IE_Msk /*!< illegal access interrupt enable for USART2 */ +#define GTZC_TZIC_IER1_I2C1IE_Pos (13U) +#define GTZC_TZIC_IER1_I2C1IE_Msk (0x01UL << GTZC_TZIC_IER1_I2C1IE_Pos) +#define GTZC_TZIC_IER1_I2C1IE GTZC_TZIC_IER1_I2C1IE_Msk /*!< illegal access interrupt enable for I2C1 */ +#define GTZC_TZIC_IER1_LPTIM2IE_Pos (17U) +#define GTZC_TZIC_IER1_LPTIM2IE_Msk (0x01UL << GTZC_TZIC_IER1_LPTIM2IE_Pos) +#define GTZC_TZIC_IER1_LPTIM2IE GTZC_TZIC_IER1_LPTIM2IE_Msk /*!< illegal access interrupt enable for LPTIM2 */ + +/******************* Bits definition for GTZC_TZIC_IER2 register ***************/ +#define GTZC_TZIC_IER2_TIM1IE_Pos (0U) +#define GTZC_TZIC_IER2_TIM1IE_Msk (0x01UL << GTZC_TZIC_IER2_TIM1IE_Pos) +#define GTZC_TZIC_IER2_TIM1IE GTZC_TZIC_IER2_TIM1IE_Msk /*!< illegal access interrupt enable for TIM1 */ +#define GTZC_TZIC_IER2_SPI1IE_Pos (1U) +#define GTZC_TZIC_IER2_SPI1IE_Msk (0x01UL << GTZC_TZIC_IER2_SPI1IE_Pos) +#define GTZC_TZIC_IER2_SPI1IE GTZC_TZIC_IER2_SPI1IE_Msk /*!< illegal access interrupt enable for SPI1 */ +#define GTZC_TZIC_IER2_USART1IE_Pos (3U) +#define GTZC_TZIC_IER2_USART1IE_Msk (0x01UL << GTZC_TZIC_IER2_USART1IE_Pos) +#define GTZC_TZIC_IER2_USART1IE GTZC_TZIC_IER2_USART1IE_Msk /*!< illegal access interrupt enable for USART1 */ +#define GTZC_TZIC_IER2_TIM16IE_Pos (5U) +#define GTZC_TZIC_IER2_TIM16IE_Msk (0x01UL << GTZC_TZIC_IER2_TIM16IE_Pos) +#define GTZC_TZIC_IER2_TIM16IE GTZC_TZIC_IER2_TIM16IE_Msk /*!< illegal access interrupt enable for TIM16 */ +#define GTZC_TZIC_IER2_TIM17IE_Pos (6U) +#define GTZC_TZIC_IER2_TIM17IE_Msk (0x01UL << GTZC_TZIC_IER2_TIM17IE_Pos) +#define GTZC_TZIC_IER2_TIM17IE GTZC_TZIC_IER2_TIM17IE_Msk /*!< illegal access interrupt enable for TIM17 */ +#define GTZC_TZIC_IER2_SAI1IE_Pos (7U) +#define GTZC_TZIC_IER2_SAI1IE_Msk (0x01UL << GTZC_TZIC_IER2_SAI1IE_Pos) +#define GTZC_TZIC_IER2_SAI1IE GTZC_TZIC_IER2_SAI1IE_Msk /*!< illegal access interrupt enable for SAI1 */ +#define GTZC_TZIC_IER2_SPI3IE_Pos (16U) +#define GTZC_TZIC_IER2_SPI3IE_Msk (0x01UL << GTZC_TZIC_IER2_SPI3IE_Pos) +#define GTZC_TZIC_IER2_SPI3IE GTZC_TZIC_IER2_SPI3IE_Msk /*!< illegal access interrupt enable for SPI3 */ +#define GTZC_TZIC_IER2_LPUART1IE_Pos (17U) +#define GTZC_TZIC_IER2_LPUART1IE_Msk (0x01UL << GTZC_TZIC_IER2_LPUART1IE_Pos) +#define GTZC_TZIC_IER2_LPUART1IE GTZC_TZIC_IER2_LPUART1IE_Msk /*!< illegal access interrupt enable for LPUART1 */ +#define GTZC_TZIC_IER2_I2C3IE_Pos (18U) +#define GTZC_TZIC_IER2_I2C3IE_Msk (0x01UL << GTZC_TZIC_IER2_I2C3IE_Pos) +#define GTZC_TZIC_IER2_I2C3IE GTZC_TZIC_IER2_I2C3IE_Msk /*!< illegal access interrupt enable for I2C3 */ +#define GTZC_TZIC_IER2_LPTIM1IE_Pos (19U) +#define GTZC_TZIC_IER2_LPTIM1IE_Msk (0x01UL << GTZC_TZIC_IER2_LPTIM1IE_Pos) +#define GTZC_TZIC_IER2_LPTIM1IE GTZC_TZIC_IER2_LPTIM1IE_Msk /*!< illegal access interrupt enable for LPTIM1 */ +#define GTZC_TZIC_IER2_COMPIE_Pos (23U) +#define GTZC_TZIC_IER2_COMPIE_Msk (0x01UL << GTZC_TZIC_IER2_COMPIE_Pos) +#define GTZC_TZIC_IER2_COMPIE GTZC_TZIC_IER2_COMPIE_Msk /*!< illegal access interrupt enable for COMP */ +#define GTZC_TZIC_IER2_ADC4IE_Pos (24U) +#define GTZC_TZIC_IER2_ADC4IE_Msk (0x01UL << GTZC_TZIC_IER2_ADC4IE_Pos) +#define GTZC_TZIC_IER2_ADC4IE GTZC_TZIC_IER2_ADC4IE_Msk /*!< illegal access interrupt enable for ADC4 */ + +/******************* Bits definition for GTZC_TZIC_IER3 register ***************/ +#define GTZC_TZIC_IER3_CRCIE_Pos (3U) +#define GTZC_TZIC_IER3_CRCIE_Msk (0x01UL << GTZC_TZIC_IER3_CRCIE_Pos) +#define GTZC_TZIC_IER3_CRCIE GTZC_TZIC_IER3_CRCIE_Msk /*!< illegal access interrupt enable for CRC */ +#define GTZC_TZIC_IER3_TSCIE_Pos (4U) +#define GTZC_TZIC_IER3_TSCIE_Msk (0x01UL << GTZC_TZIC_IER3_TSCIE_Pos) +#define GTZC_TZIC_IER3_TSCIE GTZC_TZIC_IER3_TSCIE_Msk /*!< illegal access interrupt enable for TSC */ +#define GTZC_TZIC_IER3_ICACHE_REGIE_Pos (6U) +#define GTZC_TZIC_IER3_ICACHE_REGIE_Msk (0x01UL << GTZC_TZIC_IER3_ICACHE_REGIE_Pos) +#define GTZC_TZIC_IER3_ICACHE_REGIE GTZC_TZIC_IER3_ICACHE_REGIE_Msk /*!< illegal access interrupt enable for ICACHE_REG */ +#define GTZC_TZIC_IER3_AESIE_Pos (11U) +#define GTZC_TZIC_IER3_AESIE_Msk (0x01UL << GTZC_TZIC_IER3_AESIE_Pos) +#define GTZC_TZIC_IER3_AESIE GTZC_TZIC_IER3_AESIE_Msk /*!< illegal access interrupt enable for AES */ +#define GTZC_TZIC_IER3_HASHIE_Pos (12U) +#define GTZC_TZIC_IER3_HASHIE_Msk (0x01UL << GTZC_TZIC_IER3_HASHIE_Pos) +#define GTZC_TZIC_IER3_HASHIE GTZC_TZIC_IER3_HASHIE_Msk /*!< illegal access interrupt enable for HASH */ +#define GTZC_TZIC_IER3_RNGIE_Pos (13U) +#define GTZC_TZIC_IER3_RNGIE_Msk (0x01UL << GTZC_TZIC_IER3_RNGIE_Pos) +#define GTZC_TZIC_IER3_RNGIE GTZC_TZIC_IER3_RNGIE_Msk /*!< illegal access interrupt enable for RNG */ +#define GTZC_TZIC_IER3_SAESIE_Pos (14U) +#define GTZC_TZIC_IER3_SAESIE_Msk (0x01UL << GTZC_TZIC_IER3_SAESIE_Pos) +#define GTZC_TZIC_IER3_SAESIE GTZC_TZIC_IER3_SAESIE_Msk /*!< illegal access interrupt enable for SAES */ +#define GTZC_TZIC_IER3_HSEMIE_Pos (15U) +#define GTZC_TZIC_IER3_HSEMIE_Msk (0x01UL << GTZC_TZIC_IER3_HSEMIE_Pos) +#define GTZC_TZIC_IER3_HSEMIE GTZC_TZIC_IER3_HSEMIE_Msk /*!< illegal access interrupt enable for HSEM */ +#define GTZC_TZIC_IER3_PKAIE_Pos (16U) +#define GTZC_TZIC_IER3_PKAIE_Msk (0x01UL << GTZC_TZIC_IER3_PKAIE_Pos) +#define GTZC_TZIC_IER3_PKAIE GTZC_TZIC_IER3_PKAIE_Msk /*!< illegal access interrupt enable for PKA */ +#define GTZC_TZIC_IER3_RAMCFGIE_Pos (22U) +#define GTZC_TZIC_IER3_RAMCFGIE_Msk (0x01UL << GTZC_TZIC_IER3_RAMCFGIE_Pos) +#define GTZC_TZIC_IER3_RAMCFGIE GTZC_TZIC_IER3_RAMCFGIE_Msk /*!< illegal access interrupt enable for RAMCFG */ +#define GTZC_TZIC_IER3_RADIOIE_Pos (23U) +#define GTZC_TZIC_IER3_RADIOIE_Msk (0x01UL << GTZC_TZIC_IER3_RADIOIE_Pos) +#define GTZC_TZIC_IER3_RADIOIE GTZC_TZIC_IER3_RADIOIE_Msk /*!< illegal access interrupt enable for 2.4 GHz RADIO */ +#define GTZC_TZIC_IER3_PTACONVIE_Pos (24U) +#define GTZC_TZIC_IER3_PTACONVIE_Msk (0x01UL << GTZC_TZIC_IER3_PTACONVIE_Pos) +#define GTZC_TZIC_IER3_PTACONVIE GTZC_TZIC_IER3_PTACONVIE_Msk /*!< illegal access interrupt enable for PTACONV */ + +/******************* Bits definition for GTZC_TZIC_IER4 register ***************/ +#define GTZC_TZIC_IER4_GPDMA1IE_Pos (0U) +#define GTZC_TZIC_IER4_GPDMA1IE_Msk (0x01UL << GTZC_TZIC_IER4_GPDMA1IE_Pos) +#define GTZC_TZIC_IER4_GPDMA1IE GTZC_TZIC_IER4_GPDMA1IE_Msk /*!< illegal access interrupt enable for GPDMA1 */ +#define GTZC_TZIC_IER4_FLASHIE_Pos (1U) +#define GTZC_TZIC_IER4_FLASHIE_Msk (0x01UL << GTZC_TZIC_IER4_FLASHIE_Pos) +#define GTZC_TZIC_IER4_FLASHIE GTZC_TZIC_IER4_FLASHIE_Msk /*!< illegal access interrupt enable for FLASH memory */ +#define GTZC_TZIC_IER4_FLASH_REGIE_Pos (2U) +#define GTZC_TZIC_IER4_FLASH_REGIE_Msk (0x01UL << GTZC_TZIC_IER4_FLASH_REGIE_Pos) +#define GTZC_TZIC_IER4_FLASH_REGIE GTZC_TZIC_IER4_FLASH_REGIE_Msk /*!< illegal access interrupt enable for FLASH interface */ +#define GTZC_TZIC_IER4_SYSCFGIE_Pos (7U) +#define GTZC_TZIC_IER4_SYSCFGIE_Msk (0x01UL << GTZC_TZIC_IER4_SYSCFGIE_Pos) +#define GTZC_TZIC_IER4_SYSCFGIE GTZC_TZIC_IER4_SYSCFGIE_Msk /*!< illegal access interrupt enable for SYSCFG interface */ +#define GTZC_TZIC_IER4_RTCIE_Pos (8U) +#define GTZC_TZIC_IER4_RTCIE_Msk (0x01UL << GTZC_TZIC_IER4_RTCIE_Pos) +#define GTZC_TZIC_IER4_RTCIE GTZC_TZIC_IER4_RTCIE_Msk /*!< illegal access interrupt enable for RTC interface */ +#define GTZC_TZIC_IER4_TAMPIE_Pos (9U) +#define GTZC_TZIC_IER4_TAMPIE_Msk (0x01UL << GTZC_TZIC_IER4_TAMPIE_Pos) +#define GTZC_TZIC_IER4_TAMPIE GTZC_TZIC_IER4_TAMPIE_Msk /*!< illegal access interrupt enable for TAMP interface */ +#define GTZC_TZIC_IER4_PWRIE_Pos (10U) +#define GTZC_TZIC_IER4_PWRIE_Msk (0x01UL << GTZC_TZIC_IER4_PWRIE_Pos) +#define GTZC_TZIC_IER4_PWRIE GTZC_TZIC_IER4_PWRIE_Msk /*!< illegal access interrupt enable for PWR interface */ +#define GTZC_TZIC_IER4_RCCIE_Pos (11U) +#define GTZC_TZIC_IER4_RCCIE_Msk (0x01UL << GTZC_TZIC_IER4_RCCIE_Pos) +#define GTZC_TZIC_IER4_RCCIE GTZC_TZIC_IER4_RCCIE_Msk /*!< illegal access interrupt enable for RCC interface */ +#define GTZC_TZIC_IER4_EXTIIE_Pos (13U) +#define GTZC_TZIC_IER4_EXTIIE_Msk (0x01UL << GTZC_TZIC_IER4_EXTIIE_Pos) +#define GTZC_TZIC_IER4_EXTIIE GTZC_TZIC_IER4_EXTIIE_Msk /*!< illegal access interrupt enable for EXTI interface */ +#define GTZC_TZIC_IER4_TZSCIE_Pos (14U) +#define GTZC_TZIC_IER4_TZSCIE_Msk (0x01UL << GTZC_TZIC_IER4_TZSCIE_Pos) +#define GTZC_TZIC_IER4_TZSCIE GTZC_TZIC_IER4_TZSCIE_Msk /*!< illegal access interrupt enable for GTZC TZSC */ +#define GTZC_TZIC_IER4_TZICIE_Pos (15U) +#define GTZC_TZIC_IER4_TZICIE_Msk (0x01UL << GTZC_TZIC_IER4_TZICIE_Pos) +#define GTZC_TZIC_IER4_TZICIE GTZC_TZIC_IER4_TZICIE_Msk /*!< illegal access interrupt enable for GTZC TZIC */ +#define GTZC_TZIC_IER4_SRAM1IE_Pos (22U) +#define GTZC_TZIC_IER4_SRAM1IE_Msk (0x01UL << GTZC_TZIC_IER4_SRAM1IE_Pos) +#define GTZC_TZIC_IER4_SRAM1IE GTZC_TZIC_IER4_SRAM1IE_Msk /*!< illegal access interrupt enable for SRAM1 memory */ +#define GTZC_TZIC_IER4_MPCBB1IE_Pos (23U) +#define GTZC_TZIC_IER4_MPCBB1IE_Msk (0x01UL << GTZC_TZIC_IER4_MPCBB1IE_Pos) +#define GTZC_TZIC_IER4_MPCBB1IE GTZC_TZIC_IER4_MPCBB1IE_Msk /*!< illegal access interrupt enable for MPCBB1 */ +#define GTZC_TZIC_IER4_SRAM2IE_Pos (24U) +#define GTZC_TZIC_IER4_SRAM2IE_Msk (0x01UL << GTZC_TZIC_IER4_SRAM2IE_Pos) +#define GTZC_TZIC_IER4_SRAM2IE GTZC_TZIC_IER4_SRAM2IE_Msk /*!< illegal access interrupt enable for SRAM2 memory */ +#define GTZC_TZIC_IER4_MPCBB2IE_Pos (25U) +#define GTZC_TZIC_IER4_MPCBB2IE_Msk (0x01UL << GTZC_TZIC_IER4_MPCBB2IE_Pos) +#define GTZC_TZIC_IER4_MPCBB2IE GTZC_TZIC_IER4_MPCBB2IE_Msk /*!< illegal access interrupt enable for MPCBB2 */ +#define GTZC_TZIC_IER4_SRAM6IE_Pos (30U) +#define GTZC_TZIC_IER4_SRAM6IE_Msk (0x01UL << GTZC_TZIC_IER4_SRAM6IE_Pos) +#define GTZC_TZIC_IER4_SRAM6IE GTZC_TZIC_IER4_SRAM6IE_Msk /*!< illegal access interrupt enable for 2.4GHz TXRX SRAM memory */ +#define GTZC_TZIC_IER4_MPCBB6IE_Pos (31U) +#define GTZC_TZIC_IER4_MPCBB6IE_Msk (0x01UL << GTZC_TZIC_IER4_MPCBB6IE_Pos) +#define GTZC_TZIC_IER4_MPCBB6IE GTZC_TZIC_IER4_MPCBB6IE_Msk /*!< illegal access interrupt enable for MPCBB6 */ + +/******************* Bits definition for GTZC_TZIC_SR1 register **************/ +#define GTZC_TZIC_SR1_TIM2F_Pos (0U) +#define GTZC_TZIC_SR1_TIM2F_Msk (0x01UL << GTZC_TZIC_SR1_TIM2F_Pos) +#define GTZC_TZIC_SR1_TIM2F GTZC_TZIC_SR1_TIM2F_Msk /*!< illegal access flag for TIM2 */ +#define GTZC_TZIC_SR1_TIM3F_Pos (1U) +#define GTZC_TZIC_SR1_TIM3F_Msk (0x01UL << GTZC_TZIC_SR1_TIM3F_Pos) +#define GTZC_TZIC_SR1_TIM3F GTZC_TZIC_SR1_TIM3F_Msk /*!< illegal access flag for TIM3 */ +#define GTZC_TZIC_SR1_WWDGF_Pos (6U) +#define GTZC_TZIC_SR1_WWDGF_Msk (0x01UL << GTZC_TZIC_SR1_WWDGF_Pos) +#define GTZC_TZIC_SR1_WWDGF GTZC_TZIC_SR1_WWDGF_Msk /*!< illegal access flag for WWDG */ +#define GTZC_TZIC_SR1_IWDGF_Pos (7U) +#define GTZC_TZIC_SR1_IWDGF_Msk (0x01UL << GTZC_TZIC_SR1_IWDGF_Pos) +#define GTZC_TZIC_SR1_IWDGF GTZC_TZIC_SR1_IWDGF_Msk /*!< illegal access flag for IWDG */ +#define GTZC_TZIC_SR1_USART2F_Pos (9U) +#define GTZC_TZIC_SR1_USART2F_Msk (0x01UL << GTZC_TZIC_SR1_USART2F_Pos) +#define GTZC_TZIC_SR1_USART2F GTZC_TZIC_SR1_USART2F_Msk /*!< illegal access flag for USART2 */ +#define GTZC_TZIC_SR1_I2C1F_Pos (13U) +#define GTZC_TZIC_SR1_I2C1F_Msk (0x01UL << GTZC_TZIC_SR1_I2C1F_Pos) +#define GTZC_TZIC_SR1_I2C1F GTZC_TZIC_SR1_I2C1F_Msk /*!< illegal access flag for I2C1 */ +#define GTZC_TZIC_SR1_LPTIM2F_Pos (17U) +#define GTZC_TZIC_SR1_LPTIM2F_Msk (0x01UL << GTZC_TZIC_SR1_LPTIM2F_Pos) +#define GTZC_TZIC_SR1_LPTIM2F GTZC_TZIC_SR1_LPTIM2F_Msk /*!< illegal access flag for LPTIM2 */ + +/******************* Bits definition for GTZC_TZIC_SR2 register **************/ +#define GTZC_TZIC_SR2_TIM1F_Pos (0U) +#define GTZC_TZIC_SR2_TIM1F_Msk (0x01UL << GTZC_TZIC_SR2_TIM1F_Pos) +#define GTZC_TZIC_SR2_TIM1F GTZC_TZIC_SR2_TIM1F_Msk /*!< illegal access flag for TIM1 */ +#define GTZC_TZIC_SR2_SPI1F_Pos (1U) +#define GTZC_TZIC_SR2_SPI1F_Msk (0x01UL << GTZC_TZIC_SR2_SPI1F_Pos) +#define GTZC_TZIC_SR2_SPI1F GTZC_TZIC_SR2_SPI1F_Msk /*!< illegal access flag for SPI1 */ +#define GTZC_TZIC_SR2_USART1F_Pos (3U) +#define GTZC_TZIC_SR2_USART1F_Msk (0x01UL << GTZC_TZIC_SR2_USART1F_Pos) +#define GTZC_TZIC_SR2_USART1F GTZC_TZIC_SR2_USART1F_Msk /*!< illegal access flag for USART1 */ +#define GTZC_TZIC_SR2_TIM16F_Pos (5U) +#define GTZC_TZIC_SR2_TIM16F_Msk (0x01UL << GTZC_TZIC_SR2_TIM16F_Pos) +#define GTZC_TZIC_SR2_TIM16F GTZC_TZIC_SR2_TIM16F_Msk /*!< illegal access flag for TIM16 */ +#define GTZC_TZIC_SR2_TIM17F_Pos (6U) +#define GTZC_TZIC_SR2_TIM17F_Msk (0x01UL << GTZC_TZIC_SR2_TIM17F_Pos) +#define GTZC_TZIC_SR2_TIM17F GTZC_TZIC_SR2_TIM17F_Msk /*!< illegal access flag for TIM17 */ +#define GTZC_TZIC_SR2_SAI1F_Pos (7U) +#define GTZC_TZIC_SR2_SAI1F_Msk (0x01UL << GTZC_TZIC_SR2_SAI1F_Pos) +#define GTZC_TZIC_SR2_SAI1F GTZC_TZIC_SR2_SAI1F_Msk /*!< illegal access flag for SAI1 */ +#define GTZC_TZIC_SR2_SPI3F_Pos (16U) +#define GTZC_TZIC_SR2_SPI3F_Msk (0x01UL << GTZC_TZIC_SR2_SPI3F_Pos) +#define GTZC_TZIC_SR2_SPI3F GTZC_TZIC_SR2_SPI3F_Msk /*!< illegal access flag for SPI3 */ +#define GTZC_TZIC_SR2_LPUART1F_Pos (17U) +#define GTZC_TZIC_SR2_LPUART1F_Msk (0x01UL << GTZC_TZIC_SR2_LPUART1F_Pos) +#define GTZC_TZIC_SR2_LPUART1F GTZC_TZIC_SR2_LPUART1F_Msk /*!< illegal access flag for LPUART1 */ +#define GTZC_TZIC_SR2_I2C3F_Pos (18U) +#define GTZC_TZIC_SR2_I2C3F_Msk (0x01UL << GTZC_TZIC_SR2_I2C3F_Pos) +#define GTZC_TZIC_SR2_I2C3F GTZC_TZIC_SR2_I2C3F_Msk /*!< illegal access flag for I2C3 */ +#define GTZC_TZIC_SR2_LPTIM1F_Pos (19U) +#define GTZC_TZIC_SR2_LPTIM1F_Msk (0x01UL << GTZC_TZIC_SR2_LPTIM1F_Pos) +#define GTZC_TZIC_SR2_LPTIM1F GTZC_TZIC_SR2_LPTIM1F_Msk /*!< illegal access flag for LPTIM1 */ +#define GTZC_TZIC_SR2_COMPF_Pos (23U) +#define GTZC_TZIC_SR2_COMPF_Msk (0x01UL << GTZC_TZIC_SR2_COMPF_Pos) +#define GTZC_TZIC_SR2_COMPF GTZC_TZIC_SR2_COMPF_Msk /*!< illegal access flag for COMP */ +#define GTZC_TZIC_SR2_ADC4F_Pos (24U) +#define GTZC_TZIC_SR2_ADC4F_Msk (0x01UL << GTZC_TZIC_SR2_ADC4F_Pos) +#define GTZC_TZIC_SR2_ADC4F GTZC_TZIC_SR2_ADC4F_Msk /*!< illegal access flag for ADC4 */ + +/******************* Bits definition for GTZC_TZIC_SR3 register **************/ +#define GTZC_TZIC_SR3_CRCF_Pos (3U) +#define GTZC_TZIC_SR3_CRCF_Msk (0x01UL << GTZC_TZIC_SR3_CRCF_Pos) +#define GTZC_TZIC_SR3_CRCF GTZC_TZIC_SR3_CRCF_Msk /*!< illegal access flag for CRC */ +#define GTZC_TZIC_SR3_TSCF_Pos (4U) +#define GTZC_TZIC_SR3_TSCF_Msk (0x01UL << GTZC_TZIC_SR3_TSCF_Pos) +#define GTZC_TZIC_SR3_TSCF GTZC_TZIC_SR3_TSCF_Msk /*!< illegal access flag for TSC */ +#define GTZC_TZIC_SR3_ICACHE_REGF_Pos (6U) +#define GTZC_TZIC_SR3_ICACHE_REGF_Msk (0x01UL << GTZC_TZIC_SR3_ICACHE_REGF_Pos) +#define GTZC_TZIC_SR3_ICACHE_REGF GTZC_TZIC_SR3_ICACHE_REGF_Msk /*!< illegal access flag for ICACHE_REG */ +#define GTZC_TZIC_SR3_AESF_Pos (11U) +#define GTZC_TZIC_SR3_AESF_Msk (0x01UL << GTZC_TZIC_SR3_AESF_Pos) +#define GTZC_TZIC_SR3_AESF GTZC_TZIC_SR3_AESF_Msk /*!< illegal access flag for AES */ +#define GTZC_TZIC_SR3_HASHF_Pos (12U) +#define GTZC_TZIC_SR3_HASHF_Msk (0x01UL << GTZC_TZIC_SR3_HASHF_Pos) +#define GTZC_TZIC_SR3_HASHF GTZC_TZIC_SR3_HASHF_Msk /*!< illegal access flag for HASH */ +#define GTZC_TZIC_SR3_RNGF_Pos (13U) +#define GTZC_TZIC_SR3_RNGF_Msk (0x01UL << GTZC_TZIC_SR3_RNGF_Pos) +#define GTZC_TZIC_SR3_RNGF GTZC_TZIC_SR3_RNGF_Msk /*!< illegal access flag for RNG */ +#define GTZC_TZIC_SR3_SAESF_Pos (14U) +#define GTZC_TZIC_SR3_SAESF_Msk (0x01UL << GTZC_TZIC_SR3_SAESF_Pos) +#define GTZC_TZIC_SR3_SAESF GTZC_TZIC_SR3_SAESF_Msk /*!< illegal access flag for SAES */ +#define GTZC_TZIC_SR3_HSEMF_Pos (15U) +#define GTZC_TZIC_SR3_HSEMF_Msk (0x01UL << GTZC_TZIC_SR3_HSEMF_Pos) +#define GTZC_TZIC_SR3_HSEMF GTZC_TZIC_SR3_HSEMF_Msk /*!< illegal access flag for HSEM */ +#define GTZC_TZIC_SR3_PKAF_Pos (16U) +#define GTZC_TZIC_SR3_PKAF_Msk (0x01UL << GTZC_TZIC_SR3_PKAF_Pos) +#define GTZC_TZIC_SR3_PKAF GTZC_TZIC_SR3_PKAF_Msk /*!< illegal access flag for PKA */ +#define GTZC_TZIC_SR3_RAMCFGF_Pos (22U) +#define GTZC_TZIC_SR3_RAMCFGF_Msk (0x01UL << GTZC_TZIC_SR3_RAMCFGF_Pos) +#define GTZC_TZIC_SR3_RAMCFGF GTZC_TZIC_SR3_RAMCFGF_Msk /*!< illegal access flag for RAMCFG */ +#define GTZC_TZIC_SR3_RADIOF_Pos (23U) +#define GTZC_TZIC_SR3_RADIOF_Msk (0x01UL << GTZC_TZIC_SR3_RADIOF_Pos) +#define GTZC_TZIC_SR3_RADIOF GTZC_TZIC_SR3_RADIOF_Msk /*!< illegal access flag for 2.4 GHz RADIO */ +#define GTZC_TZIC_SR3_PTACONVF_Pos (24U) +#define GTZC_TZIC_SR3_PTACONVF_Msk (0x01UL << GTZC_TZIC_SR3_PTACONVF_Pos) +#define GTZC_TZIC_SR3_PTACONVF GTZC_TZIC_SR3_PTACONVF_Msk /*!< illegal access flag for PTACONV */ + +/******************* Bits definition for GTZC_TZIC_SR4 register ***************/ +#define GTZC_TZIC_SR4_GPDMA1F_Pos (0U) +#define GTZC_TZIC_SR4_GPDMA1F_Msk (0x01UL << GTZC_TZIC_SR4_GPDMA1F_Pos) +#define GTZC_TZIC_SR4_GPDMA1F GTZC_TZIC_SR4_GPDMA1F_Msk /*!< illegal access flag for GPDMA1 */ +#define GTZC_TZIC_SR4_FLASHF_Pos (1U) +#define GTZC_TZIC_SR4_FLASHF_Msk (0x01UL << GTZC_TZIC_SR4_FLASHF_Pos) +#define GTZC_TZIC_SR4_FLASHF GTZC_TZIC_SR4_FLASHF_Msk /*!< illegal access flag for FLASH memory */ +#define GTZC_TZIC_SR4_FLASH_REGF_Pos (2U) +#define GTZC_TZIC_SR4_FLASH_REGF_Msk (0x01UL << GTZC_TZIC_SR4_FLASH_REGF_Pos) +#define GTZC_TZIC_SR4_FLASH_REGF GTZC_TZIC_SR4_FLASH_REGF_Msk /*!< illegal access flag for FLASH interface */ +#define GTZC_TZIC_SR4_SYSCFGF_Pos (7U) +#define GTZC_TZIC_SR4_SYSCFGF_Msk (0x01UL << GTZC_TZIC_SR4_SYSCFGF_Pos) +#define GTZC_TZIC_SR4_SYSCFGF GTZC_TZIC_SR4_SYSCFGF_Msk /*!< illegal access flag for SYSCFG interface */ +#define GTZC_TZIC_SR4_RTCF_Pos (8U) +#define GTZC_TZIC_SR4_RTCF_Msk (0x01UL << GTZC_TZIC_SR4_RTCF_Pos) +#define GTZC_TZIC_SR4_RTCF GTZC_TZIC_SR4_RTCF_Msk /*!< illegal access flag for RTC interface */ +#define GTZC_TZIC_SR4_TAMPF_Pos (9U) +#define GTZC_TZIC_SR4_TAMPF_Msk (0x01UL << GTZC_TZIC_SR4_TAMPF_Pos) +#define GTZC_TZIC_SR4_TAMPF GTZC_TZIC_SR4_TAMPF_Msk /*!< illegal access flag for TAMP interface */ +#define GTZC_TZIC_SR4_PWRF_Pos (10U) +#define GTZC_TZIC_SR4_PWRF_Msk (0x01UL << GTZC_TZIC_SR4_PWRF_Pos) +#define GTZC_TZIC_SR4_PWRF GTZC_TZIC_SR4_PWRF_Msk /*!< illegal access flag for PWR interface */ +#define GTZC_TZIC_SR4_RCCF_Pos (11U) +#define GTZC_TZIC_SR4_RCCF_Msk (0x01UL << GTZC_TZIC_SR4_RCCF_Pos) +#define GTZC_TZIC_SR4_RCCF GTZC_TZIC_SR4_RCCF_Msk /*!< illegal access flag for RCC interface */ +#define GTZC_TZIC_SR4_EXTIF_Pos (13U) +#define GTZC_TZIC_SR4_EXTIF_Msk (0x01UL << GTZC_TZIC_SR4_EXTIF_Pos) +#define GTZC_TZIC_SR4_EXTIF GTZC_TZIC_SR4_EXTIF_Msk /*!< illegal access flag for EXTI interface */ +#define GTZC_TZIC_SR4_TZSCF_Pos (14U) +#define GTZC_TZIC_SR4_TZSCF_Msk (0x01UL << GTZC_TZIC_SR4_TZSCF_Pos) +#define GTZC_TZIC_SR4_TZSCF GTZC_TZIC_SR4_TZSCF_Msk /*!< illegal access flag for GTZC TZSC */ +#define GTZC_TZIC_SR4_TZICF_Pos (15U) +#define GTZC_TZIC_SR4_TZICF_Msk (0x01UL << GTZC_TZIC_SR4_TZICF_Pos) +#define GTZC_TZIC_SR4_TZICF GTZC_TZIC_SR4_TZICF_Msk /*!< illegal access flag for GTZC TZIC */ +#define GTZC_TZIC_SR4_SRAM1F_Pos (22U) +#define GTZC_TZIC_SR4_SRAM1F_Msk (0x01UL << GTZC_TZIC_SR4_SRAM1F_Pos) +#define GTZC_TZIC_SR4_SRAM1F GTZC_TZIC_SR4_SRAM1F_Msk /*!< illegal access flag for SRAM1 memory */ +#define GTZC_TZIC_SR4_MPCBB1F_Pos (23U) +#define GTZC_TZIC_SR4_MPCBB1F_Msk (0x01UL << GTZC_TZIC_SR4_MPCBB1F_Pos) +#define GTZC_TZIC_SR4_MPCBB1F GTZC_TZIC_SR4_MPCBB1F_Msk /*!< illegal access flag for MPCBB1 */ +#define GTZC_TZIC_SR4_SRAM2F_Pos (24U) +#define GTZC_TZIC_SR4_SRAM2F_Msk (0x01UL << GTZC_TZIC_SR4_SRAM2F_Pos) +#define GTZC_TZIC_SR4_SRAM2F GTZC_TZIC_SR4_SRAM2F_Msk /*!< illegal access flag for SRAM2 memory */ +#define GTZC_TZIC_SR4_MPCBB2F_Pos (25U) +#define GTZC_TZIC_SR4_MPCBB2F_Msk (0x01UL << GTZC_TZIC_SR4_MPCBB2F_Pos) +#define GTZC_TZIC_SR4_MPCBB2F GTZC_TZIC_SR4_MPCBB2F_Msk /*!< illegal access flag for MPCBB2 */ +#define GTZC_TZIC_SR4_SRAM6F_Pos (30U) +#define GTZC_TZIC_SR4_SRAM6F_Msk (0x01UL << GTZC_TZIC_SR4_SRAM6F_Pos) +#define GTZC_TZIC_SR4_SRAM6F GTZC_TZIC_SR4_SRAM6F_Msk /*!< illegal access flag for 2.4GHz TXRX SRAM memory */ +#define GTZC_TZIC_SR4_MPCBB6F_Pos (31U) +#define GTZC_TZIC_SR4_MPCBB6F_Msk (0x01UL << GTZC_TZIC_SR4_MPCBB6F_Pos) +#define GTZC_TZIC_SR4_MPCBB6F GTZC_TZIC_SR4_MPCBB6F_Msk /*!< illegal access flag for MPCBB6 */ + +/****************** Bits definition for GTZC_TZIC_FCR1 register ****************/ +#define GTZC_TZIC_FCR1_CTIM2F_Pos (0U) +#define GTZC_TZIC_FCR1_CTIM2F_Msk (0x01UL << GTZC_TZIC_FCR1_CTIM2F_Pos) +#define GTZC_TZIC_FCR1_CTIM2F GTZC_TZIC_FCR1_CTIM2F_Msk /*!< clear the illegal access flag for TIM2 */ +#define GTZC_TZIC_FCR1_CTIM3F_Pos (1U) +#define GTZC_TZIC_FCR1_CTIM3F_Msk (0x01UL << GTZC_TZIC_FCR1_CTIM3F_Pos) +#define GTZC_TZIC_FCR1_CTIM3F GTZC_TZIC_FCR1_CTIM3F_Msk /*!< clear the illegal access flag for TIM3 */ +#define GTZC_TZIC_FCR1_CWWDGF_Pos (6U) +#define GTZC_TZIC_FCR1_CWWDGF_Msk (0x01UL << GTZC_TZIC_FCR1_CWWDGF_Pos) +#define GTZC_TZIC_FCR1_CWWDGF GTZC_TZIC_FCR1_CWWDGF_Msk /*!< clear the illegal access flag for WWDG */ +#define GTZC_TZIC_FCR1_CIWDGF_Pos (7U) +#define GTZC_TZIC_FCR1_CIWDGF_Msk (0x01UL << GTZC_TZIC_FCR1_CIWDGF_Pos) +#define GTZC_TZIC_FCR1_CIWDGF GTZC_TZIC_FCR1_CIWDGF_Msk /*!< clear the illegal access flag for IWDG */ +#define GTZC_TZIC_FCR1_CUSART2F_Pos (9U) +#define GTZC_TZIC_FCR1_CUSART2F_Msk (0x01UL << GTZC_TZIC_FCR1_CUSART2F_Pos) +#define GTZC_TZIC_FCR1_CUSART2F GTZC_TZIC_FCR1_CUSART2F_Msk /*!< clear the illegal access flag for USART2 */ +#define GTZC_TZIC_FCR1_CI2C1F_Pos (13U) +#define GTZC_TZIC_FCR1_CI2C1F_Msk (0x01UL << GTZC_TZIC_FCR1_CI2C1F_Pos) +#define GTZC_TZIC_FCR1_CI2C1F GTZC_TZIC_FCR1_CI2C1F_Msk /*!< clear the illegal access flag for I2C1 */ +#define GTZC_TZIC_FCR1_CLPTIM2F_Pos (17U) +#define GTZC_TZIC_FCR1_CLPTIM2F_Msk (0x01UL << GTZC_TZIC_FCR1_CLPTIM2F_Pos) +#define GTZC_TZIC_FCR1_CLPTIM2F GTZC_TZIC_FCR1_CLPTIM2F_Msk /*!< clear the illegal access flag for LPTIM2 */ + +/****************** Bits definition for GTZC_TZIC_FCR2 register ****************/ +#define GTZC_TZIC_FCR2_CTIM1F_Pos (0U) +#define GTZC_TZIC_FCR2_CTIM1F_Msk (0x01UL << GTZC_TZIC_FCR2_CTIM1F_Pos) +#define GTZC_TZIC_FCR2_CTIM1F GTZC_TZIC_FCR2_CTIM1F_Msk /*!< clear the illegal access flag for TIM1 */ +#define GTZC_TZIC_FCR2_CSPI1F_Pos (1U) +#define GTZC_TZIC_FCR2_CSPI1F_Msk (0x01UL << GTZC_TZIC_FCR2_CSPI1F_Pos) +#define GTZC_TZIC_FCR2_CSPI1F GTZC_TZIC_FCR2_CSPI1F_Msk /*!< clear the illegal access flag for SPI1 */ +#define GTZC_TZIC_FCR2_CUSART1F_Pos (3U) +#define GTZC_TZIC_FCR2_CUSART1F_Msk (0x01UL << GTZC_TZIC_FCR2_CUSART1F_Pos) +#define GTZC_TZIC_FCR2_CUSART1F GTZC_TZIC_FCR2_CUSART1F_Msk /*!< clear the illegal access flag for USART1 */ +#define GTZC_TZIC_FCR2_CTIM16F_Pos (5U) +#define GTZC_TZIC_FCR2_CTIM16F_Msk (0x01UL << GTZC_TZIC_FCR2_CTIM16F_Pos) +#define GTZC_TZIC_FCR2_CTIM16F GTZC_TZIC_FCR2_CTIM16F_Msk /*!< clear the illegal access flag for TIM16 */ +#define GTZC_TZIC_FCR2_CTIM17F_Pos (6U) +#define GTZC_TZIC_FCR2_CTIM17F_Msk (0x01UL << GTZC_TZIC_FCR2_CTIM17F_Pos) +#define GTZC_TZIC_FCR2_CTIM17F GTZC_TZIC_FCR2_CTIM17F_Msk /*!< clear the illegal access flag for TIM17 */ +#define GTZC_TZIC_FCR2_CSAI1F_Pos (7U) +#define GTZC_TZIC_FCR2_CSAI1F_Msk (0x01UL << GTZC_TZIC_FCR2_CSAI1F_Pos) +#define GTZC_TZIC_FCR2_CSAI1F GTZC_TZIC_FCR2_CSAI1F_Msk /*!< clear the illegal access flag for SAI1 */ +#define GTZC_TZIC_FCR2_CSPI3F_Pos (16U) +#define GTZC_TZIC_FCR2_CSPI3F_Msk (0x01UL << GTZC_TZIC_FCR2_CSPI3F_Pos) +#define GTZC_TZIC_FCR2_CSPI3F GTZC_TZIC_FCR2_CSPI3F_Msk /*!< clear the illegal access flag for SPI3 */ +#define GTZC_TZIC_FCR2_CLPUART1F_Pos (17U) +#define GTZC_TZIC_FCR2_CLPUART1F_Msk (0x01UL << GTZC_TZIC_FCR2_CLPUART1F_Pos) +#define GTZC_TZIC_FCR2_CLPUART1F GTZC_TZIC_FCR2_CLPUART1F_Msk /*!< clear the illegal access flag for LPUART1 */ +#define GTZC_TZIC_FCR2_CI2C3F_Pos (18U) +#define GTZC_TZIC_FCR2_CI2C3F_Msk (0x01UL << GTZC_TZIC_FCR2_CI2C3F_Pos) +#define GTZC_TZIC_FCR2_CI2C3F GTZC_TZIC_FCR2_CI2C3F_Msk /*!< clear the illegal access flag for I2C3 */ +#define GTZC_TZIC_FCR2_CLPTIM1F_Pos (19U) +#define GTZC_TZIC_FCR2_CLPTIM1F_Msk (0x01UL << GTZC_TZIC_FCR2_CLPTIM1F_Pos) +#define GTZC_TZIC_FCR2_CLPTIM1F GTZC_TZIC_FCR2_CLPTIM1F_Msk /*!< clear the illegal access flag for LPTIM1 */ +#define GTZC_TZIC_FCR2_CCOMPF_Pos (23U) +#define GTZC_TZIC_FCR2_CCOMPF_Msk (0x01UL << GTZC_TZIC_FCR2_CCOMPF_Pos) +#define GTZC_TZIC_FCR2_CCOMPF GTZC_TZIC_FCR2_CCOMPF_Msk /*!< clear the illegal access flag for COMP */ +#define GTZC_TZIC_FCR2_CADC4F_Pos (24U) +#define GTZC_TZIC_FCR2_CADC4F_Msk (0x01UL << GTZC_TZIC_FCR2_CADC4F_Pos) +#define GTZC_TZIC_FCR2_CADC4F GTZC_TZIC_FCR2_CADC4F_Msk /*!< clear the illegal access flag for ADC4 */ + +/****************** Bits definition for GTZC_TZIC_FCR3 register ****************/ +#define GTZC_TZIC_FCR3_CCRCF_Pos (3U) +#define GTZC_TZIC_FCR3_CCRCF_Msk (0x01UL << GTZC_TZIC_FCR3_CCRCF_Pos) +#define GTZC_TZIC_FCR3_CCRCF GTZC_TZIC_FCR3_CCRCF_Msk /*!< clear the illegal access flag enable for CRC */ +#define GTZC_TZIC_FCR3_CTSCF_Pos (4U) +#define GTZC_TZIC_FCR3_CTSCF_Msk (0x01UL << GTZC_TZIC_FCR3_CTSCF_Pos) +#define GTZC_TZIC_FCR3_CTSCF GTZC_TZIC_FCR3_CTSCF_Msk /*!< clear the illegal access flag enable for TSC */ +#define GTZC_TZIC_FCR3_CICACHE_REGF_Pos (6U) +#define GTZC_TZIC_FCR3_CICACHE_REGF_Msk (0x01UL << GTZC_TZIC_FCR3_CICACHE_REGF_Pos) +#define GTZC_TZIC_FCR3_CICACHE_REGF GTZC_TZIC_FCR3_CICACHE_REGF_Msk /*!< clear the illegal access flag enable for ICACHE_REG */ +#define GTZC_TZIC_FCR3_CAESF_Pos (11U) +#define GTZC_TZIC_FCR3_CAESF_Msk (0x01UL << GTZC_TZIC_FCR3_CAESF_Pos) +#define GTZC_TZIC_FCR3_CAESF GTZC_TZIC_FCR3_CAESF_Msk /*!< clear the illegal access flag enable for AES */ +#define GTZC_TZIC_FCR3_CHASHF_Pos (12U) +#define GTZC_TZIC_FCR3_CHASHF_Msk (0x01UL << GTZC_TZIC_FCR3_CHASHF_Pos) +#define GTZC_TZIC_FCR3_CHASHF GTZC_TZIC_FCR3_CHASHF_Msk /*!< clear the illegal access flag enable for HASH */ +#define GTZC_TZIC_FCR3_CRNGF_Pos (13U) +#define GTZC_TZIC_FCR3_CRNGF_Msk (0x01UL << GTZC_TZIC_FCR3_CRNGF_Pos) +#define GTZC_TZIC_FCR3_CRNGF GTZC_TZIC_FCR3_CRNGF_Msk /*!< clear the illegal access flag enable for RNG */ +#define GTZC_TZIC_FCR3_CSAESF_Pos (14U) +#define GTZC_TZIC_FCR3_CSAESF_Msk (0x01UL << GTZC_TZIC_FCR3_CSAESF_Pos) +#define GTZC_TZIC_FCR3_CSAESF GTZC_TZIC_FCR3_CSAESF_Msk /*!< clear the illegal access flag enable for SAES */ +#define GTZC_TZIC_FCR3_CHSEMF_Pos (15U) +#define GTZC_TZIC_FCR3_CHSEMF_Msk (0x01UL << GTZC_TZIC_FCR3_CHSEMF_Pos) +#define GTZC_TZIC_FCR3_CHSEMF GTZC_TZIC_FCR3_CHSEMF_Msk /*!< clear the illegal access flag enable for HSEM */ +#define GTZC_TZIC_FCR3_CPKAF_Pos (16U) +#define GTZC_TZIC_FCR3_CPKAF_Msk (0x01UL << GTZC_TZIC_FCR3_CPKAF_Pos) +#define GTZC_TZIC_FCR3_CPKAF GTZC_TZIC_FCR3_CPKAF_Msk /*!< clear the illegal access flag enable for PKA */ +#define GTZC_TZIC_FCR3_CRAMCFGF_Pos (22U) +#define GTZC_TZIC_FCR3_CRAMCFGF_Msk (0x01UL << GTZC_TZIC_FCR3_CRAMCFGF_Pos) +#define GTZC_TZIC_FCR3_CRAMCFGF GTZC_TZIC_FCR3_CRAMCFGF_Msk /*!< clear the illegal access flag enable for RAMCFG */ +#define GTZC_TZIC_FCR3_CRADIOF_Pos (23U) +#define GTZC_TZIC_FCR3_CRADIOF_Msk (0x01UL << GTZC_TZIC_FCR3_CRADIOF_Pos) +#define GTZC_TZIC_FCR3_CRADIOF GTZC_TZIC_FCR3_CRADIOF_Msk /*!< clear the illegal access flag enable for 2.4 GHz RADIO */ +#define GTZC_TZIC_FCR3_CPTACONVF_Pos (24U) +#define GTZC_TZIC_FCR3_CPTACONVF_Msk (0x01UL << GTZC_TZIC_FCR3_CPTACONVF_Pos) +#define GTZC_TZIC_FCR3_CPTACONVF GTZC_TZIC_FCR3_CPTACONVF_Msk /*!< clear the illegal access flag enable for PTACONV */ + +/****************** Bits definition for GTZC_TZIC_FCR4 register ****************/ +#define GTZC_TZIC_FCR4_CGPDMA1F_Pos (0U) +#define GTZC_TZIC_FCR4_CGPDMA1F_Msk (0x01UL << GTZC_TZIC_FCR4_CGPDMA1F_Pos) +#define GTZC_TZIC_FCR4_CGPDMA1F GTZC_TZIC_FCR4_CGPDMA1F_Msk /*!< clear the illegal access flag enable for GPDMA1 */ +#define GTZC_TZIC_FCR4_CFLASHF_Pos (1U) +#define GTZC_TZIC_FCR4_CFLASHF_Msk (0x01UL << GTZC_TZIC_FCR4_CFLASHF_Pos) +#define GTZC_TZIC_FCR4_CFLASHF GTZC_TZIC_FCR4_CFLASHF_Msk /*!< clear the illegal access flag enable for FLASH memory */ +#define GTZC_TZIC_FCR4_CFLASH_REGF_Pos (2U) +#define GTZC_TZIC_FCR4_CFLASH_REGF_Msk (0x01UL << GTZC_TZIC_FCR4_CFLASH_REGF_Pos) +#define GTZC_TZIC_FCR4_CFLASH_REGF GTZC_TZIC_FCR4_CFLASH_REGF_Msk /*!< clear the illegal access flag enable for FLASH interface */ +#define GTZC_TZIC_FCR4_CSYSCFGF_Pos (7U) +#define GTZC_TZIC_FCR4_CSYSCFGF_Msk (0x01UL << GTZC_TZIC_FCR4_CSYSCFGF_Pos) +#define GTZC_TZIC_FCR4_CSYSCFGF GTZC_TZIC_FCR4_CSYSCFGF_Msk /*!< clear the illegal access flag enable for SYSCFG interface */ +#define GTZC_TZIC_FCR4_CRTCF_Pos (8U) +#define GTZC_TZIC_FCR4_CRTCF_Msk (0x01UL << GTZC_TZIC_FCR4_CRTCF_Pos) +#define GTZC_TZIC_FCR4_CRTCF GTZC_TZIC_FCR4_CRTCF_Msk /*!< clear the illegal access flag enable for RTC interface */ +#define GTZC_TZIC_FCR4_CTAMPF_Pos (9U) +#define GTZC_TZIC_FCR4_CTAMPF_Msk (0x01UL << GTZC_TZIC_FCR4_CTAMPF_Pos) +#define GTZC_TZIC_FCR4_CTAMPF GTZC_TZIC_FCR4_CTAMPF_Msk /*!< clear the illegal access flag enable for TAMP interface */ +#define GTZC_TZIC_FCR4_CPWRF_Pos (10U) +#define GTZC_TZIC_FCR4_CPWRF_Msk (0x01UL << GTZC_TZIC_FCR4_CPWRF_Pos) +#define GTZC_TZIC_FCR4_CPWRF GTZC_TZIC_FCR4_CPWRF_Msk /*!< clear the illegal access flag enable for PWR interface */ +#define GTZC_TZIC_FCR4_CRCCF_Pos (11U) +#define GTZC_TZIC_FCR4_CRCCF_Msk (0x01UL << GTZC_TZIC_FCR4_CRCCF_Pos) +#define GTZC_TZIC_FCR4_CRCCF GTZC_TZIC_FCR4_CRCCF_Msk /*!< clear the illegal access flag enable for RCC interface */ +#define GTZC_TZIC_FCR4_CEXTIF_Pos (13U) +#define GTZC_TZIC_FCR4_CEXTIF_Msk (0x01UL << GTZC_TZIC_FCR4_CEXTIF_Pos) +#define GTZC_TZIC_FCR4_CEXTIF GTZC_TZIC_FCR4_CEXTIF_Msk /*!< clear the illegal access flag enable for EXTI interface */ +#define GTZC_TZIC_FCR4_CTZSCF_Pos (14U) +#define GTZC_TZIC_FCR4_CTZSCF_Msk (0x01UL << GTZC_TZIC_FCR4_CTZSCF_Pos) +#define GTZC_TZIC_FCR4_CTZSCF GTZC_TZIC_FCR4_CTZSCF_Msk /*!< clear the illegal access flag enable for GTZC TZSC */ +#define GTZC_TZIC_FCR4_CTZICF_Pos (15U) +#define GTZC_TZIC_FCR4_CTZICF_Msk (0x01UL << GTZC_TZIC_FCR4_CTZICF_Pos) +#define GTZC_TZIC_FCR4_CTZICF GTZC_TZIC_FCR4_CTZICF_Msk /*!< clear the illegal access flag enable for GTZC TZIC */ +#define GTZC_TZIC_FCR4_CSRAM1F_Pos (22U) +#define GTZC_TZIC_FCR4_CSRAM1F_Msk (0x01UL << GTZC_TZIC_FCR4_CSRAM1F_Pos) +#define GTZC_TZIC_FCR4_CSRAM1F GTZC_TZIC_FCR4_CSRAM1F_Msk /*!< clear the illegal access flag enable for SRAM1 memory */ +#define GTZC_TZIC_FCR4_CMPCBB1F_Pos (23U) +#define GTZC_TZIC_FCR4_CMPCBB1F_Msk (0x01UL << GTZC_TZIC_FCR4_CMPCBB1F_Pos) +#define GTZC_TZIC_FCR4_CMPCBB1F GTZC_TZIC_FCR4_CMPCBB1F_Msk /*!< clear the illegal access flag enable for MPCBB1 */ +#define GTZC_TZIC_FCR4_CSRAM2F_Pos (24U) +#define GTZC_TZIC_FCR4_CSRAM2F_Msk (0x01UL << GTZC_TZIC_FCR4_CSRAM2F_Pos) +#define GTZC_TZIC_FCR4_CSRAM2F GTZC_TZIC_FCR4_CSRAM2F_Msk /*!< clear the illegal access flag enable for SRAM2 memory */ +#define GTZC_TZIC_FCR4_CMPCBB2F_Pos (25U) +#define GTZC_TZIC_FCR4_CMPCBB2F_Msk (0x01UL << GTZC_TZIC_FCR4_CMPCBB2F_Pos) +#define GTZC_TZIC_FCR4_CMPCBB2F GTZC_TZIC_FCR4_CMPCBB2F_Msk /*!< clear the illegal access flag enable for MPCBB2 */ +#define GTZC_TZIC_FCR4_CSRAM6F_Pos (30U) +#define GTZC_TZIC_FCR4_CSRAM6F_Msk (0x01UL << GTZC_TZIC_FCR4_CSRAM6F_Pos) +#define GTZC_TZIC_FCR4_CSRAM6F GTZC_TZIC_FCR4_CSRAM6F_Msk /*!< clear the illegal access flag enable for 2.4GHz TXRX SRAM memory */ +#define GTZC_TZIC_FCR4_CMPCBB6F_Pos (31U) +#define GTZC_TZIC_FCR4_CMPCBB6F_Msk (0x01UL << GTZC_TZIC_FCR4_CMPCBB6F_Pos) +#define GTZC_TZIC_FCR4_CMPCBB6F GTZC_TZIC_FCR4_CMPCBB6F_Msk /*!< clear the illegal access flag enable for MPCBB6 */ + +/******************* Bits definition for GTZC_MPCBB_CR register *****************/ +#define GTZC_MPCBB_CR_GLOCK_Pos (0U) +#define GTZC_MPCBB_CR_GLOCK_Msk (0x01UL << GTZC_MPCBB_CR_GLOCK_Pos) /*!< 0x00000001 */ +#define GTZC_MPCBB_CR_GLOCK GTZC_MPCBB_CR_GLOCK_Msk /*!< lock the control register of the MPCBB until next reset */ +#define GTZC_MPCBB_CR_INVSECSTATE_Pos (30U) +#define GTZC_MPCBB_CR_INVSECSTATE_Msk (0x01UL << GTZC_MPCBB_CR_INVSECSTATE_Pos) /*!< 0x40000000 */ +#define GTZC_MPCBB_CR_INVSECSTATE GTZC_MPCBB_CR_INVSECSTATE_Msk /*!< SRAM clocks security state */ +#define GTZC_MPCBB_CR_SRWILADIS_Pos (31U) +#define GTZC_MPCBB_CR_SRWILADIS_Msk (0x01UL << GTZC_MPCBB_CR_SRWILADIS_Pos) /*!< 0x80000000 */ +#define GTZC_MPCBB_CR_SRWILADIS GTZC_MPCBB_CR_SRWILADIS_Msk /*!< secure read/write illegal access disable */ + +/******************* Bits definition for GTZC_MPCBB_CFGLOCK register ************/ +#define GTZC_MPCBB_CFGLOCK_SPLCK0_Pos (0U) +#define GTZC_MPCBB_CFGLOCK_SPLCK0_Msk (0x01UL << GTZC_MPCBB_CFGLOCK_SPLCK0_Pos) /*!< 0x00000001 */ +#define GTZC_MPCBB_CFGLOCK_SPLCK0 GTZC_MPCBB_CFGLOCK_SPLCK0_Msk /*!< Security/privilege configuration lock super-block 0 */ +#define GTZC_MPCBB_CFGLOCK_SPLCK1_Pos (1U) +#define GTZC_MPCBB_CFGLOCK_SPLCK1_Msk (0x01UL << GTZC_MPCBB_CFGLOCK_SPLCK1_Pos) /*!< 0x00000002 */ +#define GTZC_MPCBB_CFGLOCK_SPLCK1 GTZC_MPCBB_CFGLOCK_SPLCK1_Msk /*!< Security/privilege configuration lock super-block 1 */ +#define GTZC_MPCBB_CFGLOCK_SPLCK2_Pos (2U) +#define GTZC_MPCBB_CFGLOCK_SPLCK2_Msk (0x01UL << GTZC_MPCBB_CFGLOCK_SPLCK2_Pos) /*!< 0x00000004 */ +#define GTZC_MPCBB_CFGLOCK_SPLCK2 GTZC_MPCBB_CFGLOCK_SPLCK2_Msk /*!< Security/privilege configuration lock super-block 2 */ +#define GTZC_MPCBB_CFGLOCK_SPLCK3_Pos (3U) +#define GTZC_MPCBB_CFGLOCK_SPLCK3_Msk (0x01UL << GTZC_MPCBB_CFGLOCK_SPLCK3_Pos) /*!< 0x00000008 */ +#define GTZC_MPCBB_CFGLOCK_SPLCK3 GTZC_MPCBB_CFGLOCK_SPLCK3_Msk /*!< Security/privilege configuration lock super-block 3 */ + +/******************* Bits definition for GTZC_MPCBB_SECCFGR0 register ************/ +#define GTZC_MPCBB_SECCFGR0_SEC0_Pos (0U) +#define GTZC_MPCBB_SECCFGR0_SEC0_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC0_Pos) /*!< 0x00000001 */ +#define GTZC_MPCBB_SECCFGR0_SEC0 GTZC_MPCBB_SECCFGR0_SEC0_Msk /*!< Security configuration for block 0 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC1_Pos (1U) +#define GTZC_MPCBB_SECCFGR0_SEC1_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC1_Pos) /*!< 0x00000002 */ +#define GTZC_MPCBB_SECCFGR0_SEC1 GTZC_MPCBB_SECCFGR0_SEC1_Msk /*!< Security configuration for block 1 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC2_Pos (2U) +#define GTZC_MPCBB_SECCFGR0_SEC2_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC2_Pos) /*!< 0x00000004 */ +#define GTZC_MPCBB_SECCFGR0_SEC2 GTZC_MPCBB_SECCFGR0_SEC2_Msk /*!< Security configuration for block 2 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC3_Pos (3U) +#define GTZC_MPCBB_SECCFGR0_SEC3_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC3_Pos) /*!< 0x00000008 */ +#define GTZC_MPCBB_SECCFGR0_SEC3 GTZC_MPCBB_SECCFGR0_SEC3_Msk /*!< Security configuration for block 3 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC4_Pos (4U) +#define GTZC_MPCBB_SECCFGR0_SEC4_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC4_Pos) /*!< 0x00000010 */ +#define GTZC_MPCBB_SECCFGR0_SEC4 GTZC_MPCBB_SECCFGR0_SEC4_Msk /*!< Security configuration for block 4 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC5_Pos (5U) +#define GTZC_MPCBB_SECCFGR0_SEC5_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC5_Pos) /*!< 0x00000020 */ +#define GTZC_MPCBB_SECCFGR0_SEC5 GTZC_MPCBB_SECCFGR0_SEC5_Msk /*!< Security configuration for block 5 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC6_Pos (6U) +#define GTZC_MPCBB_SECCFGR0_SEC6_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC6_Pos) /*!< 0x00000040 */ +#define GTZC_MPCBB_SECCFGR0_SEC6 GTZC_MPCBB_SECCFGR0_SEC6_Msk /*!< Security configuration for block 6 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC7_Pos (7U) +#define GTZC_MPCBB_SECCFGR0_SEC7_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC7_Pos) /*!< 0x00000080 */ +#define GTZC_MPCBB_SECCFGR0_SEC7 GTZC_MPCBB_SECCFGR0_SEC7_Msk /*!< Security configuration for block 7 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC8_Pos (8U) +#define GTZC_MPCBB_SECCFGR0_SEC8_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC8_Pos) /*!< 0x00000100 */ +#define GTZC_MPCBB_SECCFGR0_SEC8 GTZC_MPCBB_SECCFGR0_SEC8_Msk /*!< Security configuration for block 8 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC9_Pos (9U) +#define GTZC_MPCBB_SECCFGR0_SEC9_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC9_Pos) /*!< 0x00000200 */ +#define GTZC_MPCBB_SECCFGR0_SEC9 GTZC_MPCBB_SECCFGR0_SEC9_Msk /*!< Security configuration for block 9 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC10_Pos (10U) +#define GTZC_MPCBB_SECCFGR0_SEC10_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC10_Pos) /*!< 0x00000400 */ +#define GTZC_MPCBB_SECCFGR0_SEC10 GTZC_MPCBB_SECCFGR0_SEC10_Msk /*!< Security configuration for block 10 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC11_Pos (11U) +#define GTZC_MPCBB_SECCFGR0_SEC11_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC11_Pos) /*!< 0x00000800 */ +#define GTZC_MPCBB_SECCFGR0_SEC11 GTZC_MPCBB_SECCFGR0_SEC11_Msk /*!< Security configuration for block 11 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC12_Pos (12U) +#define GTZC_MPCBB_SECCFGR0_SEC12_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC12_Pos) /*!< 0x00001000 */ +#define GTZC_MPCBB_SECCFGR0_SEC12 GTZC_MPCBB_SECCFGR0_SEC12_Msk /*!< Security configuration for block 12 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC13_Pos (13U) +#define GTZC_MPCBB_SECCFGR0_SEC13_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC13_Pos) /*!< 0x00002000 */ +#define GTZC_MPCBB_SECCFGR0_SEC13 GTZC_MPCBB_SECCFGR0_SEC13_Msk /*!< Security configuration for block 13 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC14_Pos (14U) +#define GTZC_MPCBB_SECCFGR0_SEC14_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC14_Pos) /*!< 0x00004000 */ +#define GTZC_MPCBB_SECCFGR0_SEC14 GTZC_MPCBB_SECCFGR0_SEC14_Msk /*!< Security configuration for block 14 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC15_Pos (15U) +#define GTZC_MPCBB_SECCFGR0_SEC15_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC15_Pos) /*!< 0x00008000 */ +#define GTZC_MPCBB_SECCFGR0_SEC15 GTZC_MPCBB_SECCFGR0_SEC15_Msk /*!< Security configuration for block 15 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC16_Pos (16U) +#define GTZC_MPCBB_SECCFGR0_SEC16_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC16_Pos) /*!< 0x00010000 */ +#define GTZC_MPCBB_SECCFGR0_SEC16 GTZC_MPCBB_SECCFGR0_SEC16_Msk /*!< Security configuration for block 16 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC17_Pos (17U) +#define GTZC_MPCBB_SECCFGR0_SEC17_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC17_Pos) /*!< 0x00020000 */ +#define GTZC_MPCBB_SECCFGR0_SEC17 GTZC_MPCBB_SECCFGR0_SEC17_Msk /*!< Security configuration for block 17 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC18_Pos (18U) +#define GTZC_MPCBB_SECCFGR0_SEC18_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC18_Pos) /*!< 0x00040000 */ +#define GTZC_MPCBB_SECCFGR0_SEC18 GTZC_MPCBB_SECCFGR0_SEC18_Msk /*!< Security configuration for block 18 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC19_Pos (19U) +#define GTZC_MPCBB_SECCFGR0_SEC19_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC19_Pos) /*!< 0x00080000 */ +#define GTZC_MPCBB_SECCFGR0_SEC19 GTZC_MPCBB_SECCFGR0_SEC19_Msk /*!< Security configuration for block 19 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC20_Pos (20U) +#define GTZC_MPCBB_SECCFGR0_SEC20_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC20_Pos) /*!< 0x00100000 */ +#define GTZC_MPCBB_SECCFGR0_SEC20 GTZC_MPCBB_SECCFGR0_SEC20_Msk /*!< Security configuration for block 20 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC21_Pos (21U) +#define GTZC_MPCBB_SECCFGR0_SEC21_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC21_Pos) /*!< 0x00200000 */ +#define GTZC_MPCBB_SECCFGR0_SEC21 GTZC_MPCBB_SECCFGR0_SEC21_Msk /*!< Security configuration for block 21 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC22_Pos (22U) +#define GTZC_MPCBB_SECCFGR0_SEC22_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC22_Pos) /*!< 0x00400000 */ +#define GTZC_MPCBB_SECCFGR0_SEC22 GTZC_MPCBB_SECCFGR0_SEC22_Msk /*!< Security configuration for block 22 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC23_Pos (23U) +#define GTZC_MPCBB_SECCFGR0_SEC23_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC23_Pos) /*!< 0x00800000 */ +#define GTZC_MPCBB_SECCFGR0_SEC23 GTZC_MPCBB_SECCFGR0_SEC23_Msk /*!< Security configuration for block 23 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC24_Pos (24U) +#define GTZC_MPCBB_SECCFGR0_SEC24_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC24_Pos) /*!< 0x01000000 */ +#define GTZC_MPCBB_SECCFGR0_SEC24 GTZC_MPCBB_SECCFGR0_SEC24_Msk /*!< Security configuration for block 24 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC25_Pos (25U) +#define GTZC_MPCBB_SECCFGR0_SEC25_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC25_Pos) /*!< 0x02000000 */ +#define GTZC_MPCBB_SECCFGR0_SEC25 GTZC_MPCBB_SECCFGR0_SEC25_Msk /*!< Security configuration for block 25 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC26_Pos (26U) +#define GTZC_MPCBB_SECCFGR0_SEC26_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC26_Pos) /*!< 0x04000000 */ +#define GTZC_MPCBB_SECCFGR0_SEC26 GTZC_MPCBB_SECCFGR0_SEC26_Msk /*!< Security configuration for block 26 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC27_Pos (27U) +#define GTZC_MPCBB_SECCFGR0_SEC27_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC27_Pos) /*!< 0x08000000 */ +#define GTZC_MPCBB_SECCFGR0_SEC27 GTZC_MPCBB_SECCFGR0_SEC27_Msk /*!< Security configuration for block 27 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC28_Pos (28U) +#define GTZC_MPCBB_SECCFGR0_SEC28_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC28_Pos) /*!< 0x10000000 */ +#define GTZC_MPCBB_SECCFGR0_SEC28 GTZC_MPCBB_SECCFGR0_SEC28_Msk /*!< Security configuration for block 28 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC29_Pos (29U) +#define GTZC_MPCBB_SECCFGR0_SEC29_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC29_Pos) /*!< 0x20000000 */ +#define GTZC_MPCBB_SECCFGR0_SEC29 GTZC_MPCBB_SECCFGR0_SEC29_Msk /*!< Security configuration for block 29 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC30_Pos (30U) +#define GTZC_MPCBB_SECCFGR0_SEC30_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC30_Pos) /*!< 0x40000000 */ +#define GTZC_MPCBB_SECCFGR0_SEC30 GTZC_MPCBB_SECCFGR0_SEC31_Msk /*!< Security configuration for block 30 in super block 0 */ +#define GTZC_MPCBB_SECCFGR0_SEC31_Pos (31U) +#define GTZC_MPCBB_SECCFGR0_SEC31_Msk (0x01UL << GTZC_MPCBB_SECCFGR0_SEC31_Pos) /*!< 0x80000000 */ +#define GTZC_MPCBB_SECCFGR0_SEC31 GTZC_MPCBB_SECCFGR0_SEC31_Msk /*!< Security configuration for block 31 in super block 0 */ + +/******************* Bits definition for GTZC_MPCBB_SECCFGR1 register ************/ +#define GTZC_MPCBB_SECCFGR1_SEC0_Pos (0U) +#define GTZC_MPCBB_SECCFGR1_SEC0_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC0_Pos) /*!< 0x00000001 */ +#define GTZC_MPCBB_SECCFGR1_SEC0 GTZC_MPCBB_SECCFGR1_SEC0_Msk /*!< Security configuration for block 0 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC1_Pos (1U) +#define GTZC_MPCBB_SECCFGR1_SEC1_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC1_Pos) /*!< 0x00000002 */ +#define GTZC_MPCBB_SECCFGR1_SEC1 GTZC_MPCBB_SECCFGR1_SEC1_Msk /*!< Security configuration for block 1 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC2_Pos (2U) +#define GTZC_MPCBB_SECCFGR1_SEC2_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC2_Pos) /*!< 0x00000004 */ +#define GTZC_MPCBB_SECCFGR1_SEC2 GTZC_MPCBB_SECCFGR1_SEC2_Msk /*!< Security configuration for block 2 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC3_Pos (3U) +#define GTZC_MPCBB_SECCFGR1_SEC3_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC3_Pos) /*!< 0x00000008 */ +#define GTZC_MPCBB_SECCFGR1_SEC3 GTZC_MPCBB_SECCFGR1_SEC3_Msk /*!< Security configuration for block 3 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC4_Pos (4U) +#define GTZC_MPCBB_SECCFGR1_SEC4_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC4_Pos) /*!< 0x00000010 */ +#define GTZC_MPCBB_SECCFGR1_SEC4 GTZC_MPCBB_SECCFGR1_SEC4_Msk /*!< Security configuration for block 4 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC5_Pos (5U) +#define GTZC_MPCBB_SECCFGR1_SEC5_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC5_Pos) /*!< 0x00000020 */ +#define GTZC_MPCBB_SECCFGR1_SEC5 GTZC_MPCBB_SECCFGR1_SEC5_Msk /*!< Security configuration for block 5 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC6_Pos (6U) +#define GTZC_MPCBB_SECCFGR1_SEC6_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC6_Pos) /*!< 0x00000040 */ +#define GTZC_MPCBB_SECCFGR1_SEC6 GTZC_MPCBB_SECCFGR1_SEC6_Msk /*!< Security configuration for block 6 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC7_Pos (7U) +#define GTZC_MPCBB_SECCFGR1_SEC7_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC7_Pos) /*!< 0x00000080 */ +#define GTZC_MPCBB_SECCFGR1_SEC7 GTZC_MPCBB_SECCFGR1_SEC7_Msk /*!< Security configuration for block 7 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC8_Pos (8U) +#define GTZC_MPCBB_SECCFGR1_SEC8_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC8_Pos) /*!< 0x00000100 */ +#define GTZC_MPCBB_SECCFGR1_SEC8 GTZC_MPCBB_SECCFGR1_SEC8_Msk /*!< Security configuration for block 8 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC9_Pos (9U) +#define GTZC_MPCBB_SECCFGR1_SEC9_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC9_Pos) /*!< 0x00000200 */ +#define GTZC_MPCBB_SECCFGR1_SEC9 GTZC_MPCBB_SECCFGR1_SEC9_Msk /*!< Security configuration for block 9 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC10_Pos (10U) +#define GTZC_MPCBB_SECCFGR1_SEC10_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC10_Pos) /*!< 0x00000400 */ +#define GTZC_MPCBB_SECCFGR1_SEC10 GTZC_MPCBB_SECCFGR1_SEC10_Msk /*!< Security configuration for block 10 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC11_Pos (11U) +#define GTZC_MPCBB_SECCFGR1_SEC11_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC11_Pos) /*!< 0x00000800 */ +#define GTZC_MPCBB_SECCFGR1_SEC11 GTZC_MPCBB_SECCFGR1_SEC11_Msk /*!< Security configuration for block 11 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC12_Pos (12U) +#define GTZC_MPCBB_SECCFGR1_SEC12_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC12_Pos) /*!< 0x00001000 */ +#define GTZC_MPCBB_SECCFGR1_SEC12 GTZC_MPCBB_SECCFGR1_SEC12_Msk /*!< Security configuration for block 12 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC13_Pos (13U) +#define GTZC_MPCBB_SECCFGR1_SEC13_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC13_Pos) /*!< 0x00002000 */ +#define GTZC_MPCBB_SECCFGR1_SEC13 GTZC_MPCBB_SECCFGR1_SEC13_Msk /*!< Security configuration for block 13 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC14_Pos (14U) +#define GTZC_MPCBB_SECCFGR1_SEC14_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC14_Pos) /*!< 0x00004000 */ +#define GTZC_MPCBB_SECCFGR1_SEC14 GTZC_MPCBB_SECCFGR1_SEC14_Msk /*!< Security configuration for block 14 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC15_Pos (15U) +#define GTZC_MPCBB_SECCFGR1_SEC15_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC15_Pos) /*!< 0x00008000 */ +#define GTZC_MPCBB_SECCFGR1_SEC15 GTZC_MPCBB_SECCFGR1_SEC15_Msk /*!< Security configuration for block 15 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC16_Pos (16U) +#define GTZC_MPCBB_SECCFGR1_SEC16_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC16_Pos) /*!< 0x00010000 */ +#define GTZC_MPCBB_SECCFGR1_SEC16 GTZC_MPCBB_SECCFGR1_SEC16_Msk /*!< Security configuration for block 16 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC17_Pos (17U) +#define GTZC_MPCBB_SECCFGR1_SEC17_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC17_Pos) /*!< 0x00020000 */ +#define GTZC_MPCBB_SECCFGR1_SEC17 GTZC_MPCBB_SECCFGR1_SEC17_Msk /*!< Security configuration for block 17 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC18_Pos (18U) +#define GTZC_MPCBB_SECCFGR1_SEC18_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC18_Pos) /*!< 0x00040000 */ +#define GTZC_MPCBB_SECCFGR1_SEC18 GTZC_MPCBB_SECCFGR1_SEC18_Msk /*!< Security configuration for block 18 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC19_Pos (19U) +#define GTZC_MPCBB_SECCFGR1_SEC19_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC19_Pos) /*!< 0x00080000 */ +#define GTZC_MPCBB_SECCFGR1_SEC19 GTZC_MPCBB_SECCFGR1_SEC19_Msk /*!< Security configuration for block 19 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC20_Pos (20U) +#define GTZC_MPCBB_SECCFGR1_SEC20_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC20_Pos) /*!< 0x00100000 */ +#define GTZC_MPCBB_SECCFGR1_SEC20 GTZC_MPCBB_SECCFGR1_SEC20_Msk /*!< Security configuration for block 20 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC21_Pos (21U) +#define GTZC_MPCBB_SECCFGR1_SEC21_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC21_Pos) /*!< 0x00200000 */ +#define GTZC_MPCBB_SECCFGR1_SEC21 GTZC_MPCBB_SECCFGR1_SEC21_Msk /*!< Security configuration for block 21 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC22_Pos (22U) +#define GTZC_MPCBB_SECCFGR1_SEC22_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC22_Pos) /*!< 0x00400000 */ +#define GTZC_MPCBB_SECCFGR1_SEC22 GTZC_MPCBB_SECCFGR1_SEC22_Msk /*!< Security configuration for block 22 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC23_Pos (23U) +#define GTZC_MPCBB_SECCFGR1_SEC23_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC23_Pos) /*!< 0x00800000 */ +#define GTZC_MPCBB_SECCFGR1_SEC23 GTZC_MPCBB_SECCFGR1_SEC23_Msk /*!< Security configuration for block 23 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC24_Pos (24U) +#define GTZC_MPCBB_SECCFGR1_SEC24_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC24_Pos) /*!< 0x01000000 */ +#define GTZC_MPCBB_SECCFGR1_SEC24 GTZC_MPCBB_SECCFGR1_SEC24_Msk /*!< Security configuration for block 24 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC25_Pos (25U) +#define GTZC_MPCBB_SECCFGR1_SEC25_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC25_Pos) /*!< 0x02000000 */ +#define GTZC_MPCBB_SECCFGR1_SEC25 GTZC_MPCBB_SECCFGR1_SEC25_Msk /*!< Security configuration for block 25 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC26_Pos (26U) +#define GTZC_MPCBB_SECCFGR1_SEC26_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC26_Pos) /*!< 0x04000000 */ +#define GTZC_MPCBB_SECCFGR1_SEC26 GTZC_MPCBB_SECCFGR1_SEC26_Msk /*!< Security configuration for block 26 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC27_Pos (27U) +#define GTZC_MPCBB_SECCFGR1_SEC27_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC27_Pos) /*!< 0x08000000 */ +#define GTZC_MPCBB_SECCFGR1_SEC27 GTZC_MPCBB_SECCFGR1_SEC27_Msk /*!< Security configuration for block 27 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC28_Pos (28U) +#define GTZC_MPCBB_SECCFGR1_SEC28_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC28_Pos) /*!< 0x10000000 */ +#define GTZC_MPCBB_SECCFGR1_SEC28 GTZC_MPCBB_SECCFGR1_SEC28_Msk /*!< Security configuration for block 28 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC29_Pos (29U) +#define GTZC_MPCBB_SECCFGR1_SEC29_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC29_Pos) /*!< 0x20000000 */ +#define GTZC_MPCBB_SECCFGR1_SEC29 GTZC_MPCBB_SECCFGR1_SEC29_Msk /*!< Security configuration for block 29 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC30_Pos (30U) +#define GTZC_MPCBB_SECCFGR1_SEC30_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC30_Pos) /*!< 0x40000000 */ +#define GTZC_MPCBB_SECCFGR1_SEC30 GTZC_MPCBB_SECCFGR1_SEC31_Msk /*!< Security configuration for block 30 in super block 1 */ +#define GTZC_MPCBB_SECCFGR1_SEC31_Pos (31U) +#define GTZC_MPCBB_SECCFGR1_SEC31_Msk (0x01UL << GTZC_MPCBB_SECCFGR1_SEC31_Pos) /*!< 0x80000000 */ +#define GTZC_MPCBB_SECCFGR1_SEC31 GTZC_MPCBB_SECCFGR1_SEC31_Msk /*!< Security configuration for block 31 in super block 1 */ + +/******************* Bits definition for GTZC_MPCBB_SECCFGR2 register ************/ +#define GTZC_MPCBB_SECCFGR2_SEC0_Pos (0U) +#define GTZC_MPCBB_SECCFGR2_SEC0_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC0_Pos) /*!< 0x00000001 */ +#define GTZC_MPCBB_SECCFGR2_SEC0 GTZC_MPCBB_SECCFGR2_SEC0_Msk /*!< Security configuration for block 0 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC1_Pos (1U) +#define GTZC_MPCBB_SECCFGR2_SEC1_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC1_Pos) /*!< 0x00000002 */ +#define GTZC_MPCBB_SECCFGR2_SEC1 GTZC_MPCBB_SECCFGR2_SEC1_Msk /*!< Security configuration for block 1 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC2_Pos (2U) +#define GTZC_MPCBB_SECCFGR2_SEC2_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC2_Pos) /*!< 0x00000004 */ +#define GTZC_MPCBB_SECCFGR2_SEC2 GTZC_MPCBB_SECCFGR2_SEC2_Msk /*!< Security configuration for block 2 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC3_Pos (3U) +#define GTZC_MPCBB_SECCFGR2_SEC3_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC3_Pos) /*!< 0x00000008 */ +#define GTZC_MPCBB_SECCFGR2_SEC3 GTZC_MPCBB_SECCFGR2_SEC3_Msk /*!< Security configuration for block 3 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC4_Pos (4U) +#define GTZC_MPCBB_SECCFGR2_SEC4_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC4_Pos) /*!< 0x00000010 */ +#define GTZC_MPCBB_SECCFGR2_SEC4 GTZC_MPCBB_SECCFGR2_SEC4_Msk /*!< Security configuration for block 4 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC5_Pos (5U) +#define GTZC_MPCBB_SECCFGR2_SEC5_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC5_Pos) /*!< 0x00000020 */ +#define GTZC_MPCBB_SECCFGR2_SEC5 GTZC_MPCBB_SECCFGR2_SEC5_Msk /*!< Security configuration for block 5 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC6_Pos (6U) +#define GTZC_MPCBB_SECCFGR2_SEC6_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC6_Pos) /*!< 0x00000040 */ +#define GTZC_MPCBB_SECCFGR2_SEC6 GTZC_MPCBB_SECCFGR2_SEC6_Msk /*!< Security configuration for block 6 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC7_Pos (7U) +#define GTZC_MPCBB_SECCFGR2_SEC7_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC7_Pos) /*!< 0x00000080 */ +#define GTZC_MPCBB_SECCFGR2_SEC7 GTZC_MPCBB_SECCFGR2_SEC7_Msk /*!< Security configuration for block 7 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC8_Pos (8U) +#define GTZC_MPCBB_SECCFGR2_SEC8_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC8_Pos) /*!< 0x00000100 */ +#define GTZC_MPCBB_SECCFGR2_SEC8 GTZC_MPCBB_SECCFGR2_SEC8_Msk /*!< Security configuration for block 8 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC9_Pos (9U) +#define GTZC_MPCBB_SECCFGR2_SEC9_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC9_Pos) /*!< 0x00000200 */ +#define GTZC_MPCBB_SECCFGR2_SEC9 GTZC_MPCBB_SECCFGR2_SEC9_Msk /*!< Security configuration for block 9 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC10_Pos (10U) +#define GTZC_MPCBB_SECCFGR2_SEC10_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC10_Pos) /*!< 0x00000400 */ +#define GTZC_MPCBB_SECCFGR2_SEC10 GTZC_MPCBB_SECCFGR2_SEC10_Msk /*!< Security configuration for block 10 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC11_Pos (11U) +#define GTZC_MPCBB_SECCFGR2_SEC11_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC11_Pos) /*!< 0x00000800 */ +#define GTZC_MPCBB_SECCFGR2_SEC11 GTZC_MPCBB_SECCFGR2_SEC11_Msk /*!< Security configuration for block 11 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC12_Pos (12U) +#define GTZC_MPCBB_SECCFGR2_SEC12_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC12_Pos) /*!< 0x00001000 */ +#define GTZC_MPCBB_SECCFGR2_SEC12 GTZC_MPCBB_SECCFGR2_SEC12_Msk /*!< Security configuration for block 12 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC13_Pos (13U) +#define GTZC_MPCBB_SECCFGR2_SEC13_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC13_Pos) /*!< 0x00002000 */ +#define GTZC_MPCBB_SECCFGR2_SEC13 GTZC_MPCBB_SECCFGR2_SEC13_Msk /*!< Security configuration for block 13 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC14_Pos (14U) +#define GTZC_MPCBB_SECCFGR2_SEC14_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC14_Pos) /*!< 0x00004000 */ +#define GTZC_MPCBB_SECCFGR2_SEC14 GTZC_MPCBB_SECCFGR2_SEC14_Msk /*!< Security configuration for block 14 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC15_Pos (15U) +#define GTZC_MPCBB_SECCFGR2_SEC15_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC15_Pos) /*!< 0x00008000 */ +#define GTZC_MPCBB_SECCFGR2_SEC15 GTZC_MPCBB_SECCFGR2_SEC15_Msk /*!< Security configuration for block 15 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC16_Pos (16U) +#define GTZC_MPCBB_SECCFGR2_SEC16_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC16_Pos) /*!< 0x00010000 */ +#define GTZC_MPCBB_SECCFGR2_SEC16 GTZC_MPCBB_SECCFGR2_SEC16_Msk /*!< Security configuration for block 16 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC17_Pos (17U) +#define GTZC_MPCBB_SECCFGR2_SEC17_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC17_Pos) /*!< 0x00020000 */ +#define GTZC_MPCBB_SECCFGR2_SEC17 GTZC_MPCBB_SECCFGR2_SEC17_Msk /*!< Security configuration for block 17 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC18_Pos (18U) +#define GTZC_MPCBB_SECCFGR2_SEC18_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC18_Pos) /*!< 0x00040000 */ +#define GTZC_MPCBB_SECCFGR2_SEC18 GTZC_MPCBB_SECCFGR2_SEC18_Msk /*!< Security configuration for block 18 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC19_Pos (19U) +#define GTZC_MPCBB_SECCFGR2_SEC19_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC19_Pos) /*!< 0x00080000 */ +#define GTZC_MPCBB_SECCFGR2_SEC19 GTZC_MPCBB_SECCFGR2_SEC19_Msk /*!< Security configuration for block 19 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC20_Pos (20U) +#define GTZC_MPCBB_SECCFGR2_SEC20_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC20_Pos) /*!< 0x00100000 */ +#define GTZC_MPCBB_SECCFGR2_SEC20 GTZC_MPCBB_SECCFGR2_SEC20_Msk /*!< Security configuration for block 20 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC21_Pos (21U) +#define GTZC_MPCBB_SECCFGR2_SEC21_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC21_Pos) /*!< 0x00200000 */ +#define GTZC_MPCBB_SECCFGR2_SEC21 GTZC_MPCBB_SECCFGR2_SEC21_Msk /*!< Security configuration for block 21 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC22_Pos (22U) +#define GTZC_MPCBB_SECCFGR2_SEC22_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC22_Pos) /*!< 0x00400000 */ +#define GTZC_MPCBB_SECCFGR2_SEC22 GTZC_MPCBB_SECCFGR2_SEC22_Msk /*!< Security configuration for block 22 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC23_Pos (23U) +#define GTZC_MPCBB_SECCFGR2_SEC23_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC23_Pos) /*!< 0x00800000 */ +#define GTZC_MPCBB_SECCFGR2_SEC23 GTZC_MPCBB_SECCFGR2_SEC23_Msk /*!< Security configuration for block 23 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC24_Pos (24U) +#define GTZC_MPCBB_SECCFGR2_SEC24_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC24_Pos) /*!< 0x01000000 */ +#define GTZC_MPCBB_SECCFGR2_SEC24 GTZC_MPCBB_SECCFGR2_SEC24_Msk /*!< Security configuration for block 24 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC25_Pos (25U) +#define GTZC_MPCBB_SECCFGR2_SEC25_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC25_Pos) /*!< 0x02000000 */ +#define GTZC_MPCBB_SECCFGR2_SEC25 GTZC_MPCBB_SECCFGR2_SEC25_Msk /*!< Security configuration for block 25 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC26_Pos (26U) +#define GTZC_MPCBB_SECCFGR2_SEC26_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC26_Pos) /*!< 0x04000000 */ +#define GTZC_MPCBB_SECCFGR2_SEC26 GTZC_MPCBB_SECCFGR2_SEC26_Msk /*!< Security configuration for block 26 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC27_Pos (27U) +#define GTZC_MPCBB_SECCFGR2_SEC27_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC27_Pos) /*!< 0x08000000 */ +#define GTZC_MPCBB_SECCFGR2_SEC27 GTZC_MPCBB_SECCFGR2_SEC27_Msk /*!< Security configuration for block 27 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC28_Pos (28U) +#define GTZC_MPCBB_SECCFGR2_SEC28_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC28_Pos) /*!< 0x10000000 */ +#define GTZC_MPCBB_SECCFGR2_SEC28 GTZC_MPCBB_SECCFGR2_SEC28_Msk /*!< Security configuration for block 28 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC29_Pos (29U) +#define GTZC_MPCBB_SECCFGR2_SEC29_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC29_Pos) /*!< 0x20000000 */ +#define GTZC_MPCBB_SECCFGR2_SEC29 GTZC_MPCBB_SECCFGR2_SEC29_Msk /*!< Security configuration for block 29 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC30_Pos (30U) +#define GTZC_MPCBB_SECCFGR2_SEC30_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC30_Pos) /*!< 0x40000000 */ +#define GTZC_MPCBB_SECCFGR2_SEC30 GTZC_MPCBB_SECCFGR2_SEC31_Msk /*!< Security configuration for block 30 in super block 2 */ +#define GTZC_MPCBB_SECCFGR2_SEC31_Pos (31U) +#define GTZC_MPCBB_SECCFGR2_SEC31_Msk (0x01UL << GTZC_MPCBB_SECCFGR2_SEC31_Pos) /*!< 0x80000000 */ +#define GTZC_MPCBB_SECCFGR2_SEC31 GTZC_MPCBB_SECCFGR2_SEC31_Msk /*!< Security configuration for block 31 in super block 2 */ + +/******************* Bits definition for GTZC_MPCBB_SECCFGR3 register ************/ +#define GTZC_MPCBB_SECCFGR3_SEC0_Pos (0U) +#define GTZC_MPCBB_SECCFGR3_SEC0_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC0_Pos) /*!< 0x00000001 */ +#define GTZC_MPCBB_SECCFGR3_SEC0 GTZC_MPCBB_SECCFGR3_SEC0_Msk /*!< Security configuration for block 0 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC1_Pos (1U) +#define GTZC_MPCBB_SECCFGR3_SEC1_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC1_Pos) /*!< 0x00000002 */ +#define GTZC_MPCBB_SECCFGR3_SEC1 GTZC_MPCBB_SECCFGR3_SEC1_Msk /*!< Security configuration for block 1 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC2_Pos (2U) +#define GTZC_MPCBB_SECCFGR3_SEC2_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC2_Pos) /*!< 0x00000004 */ +#define GTZC_MPCBB_SECCFGR3_SEC2 GTZC_MPCBB_SECCFGR3_SEC2_Msk /*!< Security configuration for block 2 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC3_Pos (3U) +#define GTZC_MPCBB_SECCFGR3_SEC3_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC3_Pos) /*!< 0x00000008 */ +#define GTZC_MPCBB_SECCFGR3_SEC3 GTZC_MPCBB_SECCFGR3_SEC3_Msk /*!< Security configuration for block 3 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC4_Pos (4U) +#define GTZC_MPCBB_SECCFGR3_SEC4_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC4_Pos) /*!< 0x00000010 */ +#define GTZC_MPCBB_SECCFGR3_SEC4 GTZC_MPCBB_SECCFGR3_SEC4_Msk /*!< Security configuration for block 4 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC5_Pos (5U) +#define GTZC_MPCBB_SECCFGR3_SEC5_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC5_Pos) /*!< 0x00000020 */ +#define GTZC_MPCBB_SECCFGR3_SEC5 GTZC_MPCBB_SECCFGR3_SEC5_Msk /*!< Security configuration for block 5 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC6_Pos (6U) +#define GTZC_MPCBB_SECCFGR3_SEC6_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC6_Pos) /*!< 0x00000040 */ +#define GTZC_MPCBB_SECCFGR3_SEC6 GTZC_MPCBB_SECCFGR3_SEC6_Msk /*!< Security configuration for block 6 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC7_Pos (7U) +#define GTZC_MPCBB_SECCFGR3_SEC7_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC7_Pos) /*!< 0x00000080 */ +#define GTZC_MPCBB_SECCFGR3_SEC7 GTZC_MPCBB_SECCFGR3_SEC7_Msk /*!< Security configuration for block 7 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC8_Pos (8U) +#define GTZC_MPCBB_SECCFGR3_SEC8_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC8_Pos) /*!< 0x00000100 */ +#define GTZC_MPCBB_SECCFGR3_SEC8 GTZC_MPCBB_SECCFGR3_SEC8_Msk /*!< Security configuration for block 8 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC9_Pos (9U) +#define GTZC_MPCBB_SECCFGR3_SEC9_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC9_Pos) /*!< 0x00000200 */ +#define GTZC_MPCBB_SECCFGR3_SEC9 GTZC_MPCBB_SECCFGR3_SEC9_Msk /*!< Security configuration for block 9 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC10_Pos (10U) +#define GTZC_MPCBB_SECCFGR3_SEC10_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC10_Pos) /*!< 0x00000400 */ +#define GTZC_MPCBB_SECCFGR3_SEC10 GTZC_MPCBB_SECCFGR3_SEC10_Msk /*!< Security configuration for block 10 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC11_Pos (11U) +#define GTZC_MPCBB_SECCFGR3_SEC11_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC11_Pos) /*!< 0x00000800 */ +#define GTZC_MPCBB_SECCFGR3_SEC11 GTZC_MPCBB_SECCFGR3_SEC11_Msk /*!< Security configuration for block 11 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC12_Pos (12U) +#define GTZC_MPCBB_SECCFGR3_SEC12_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC12_Pos) /*!< 0x00001000 */ +#define GTZC_MPCBB_SECCFGR3_SEC12 GTZC_MPCBB_SECCFGR3_SEC12_Msk /*!< Security configuration for block 12 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC13_Pos (13U) +#define GTZC_MPCBB_SECCFGR3_SEC13_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC13_Pos) /*!< 0x00002000 */ +#define GTZC_MPCBB_SECCFGR3_SEC13 GTZC_MPCBB_SECCFGR3_SEC13_Msk /*!< Security configuration for block 13 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC14_Pos (14U) +#define GTZC_MPCBB_SECCFGR3_SEC14_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC14_Pos) /*!< 0x00004000 */ +#define GTZC_MPCBB_SECCFGR3_SEC14 GTZC_MPCBB_SECCFGR3_SEC14_Msk /*!< Security configuration for block 14 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC15_Pos (15U) +#define GTZC_MPCBB_SECCFGR3_SEC15_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC15_Pos) /*!< 0x00008000 */ +#define GTZC_MPCBB_SECCFGR3_SEC15 GTZC_MPCBB_SECCFGR3_SEC15_Msk /*!< Security configuration for block 15 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC16_Pos (16U) +#define GTZC_MPCBB_SECCFGR3_SEC16_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC16_Pos) /*!< 0x00010000 */ +#define GTZC_MPCBB_SECCFGR3_SEC16 GTZC_MPCBB_SECCFGR3_SEC16_Msk /*!< Security configuration for block 16 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC17_Pos (17U) +#define GTZC_MPCBB_SECCFGR3_SEC17_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC17_Pos) /*!< 0x00020000 */ +#define GTZC_MPCBB_SECCFGR3_SEC17 GTZC_MPCBB_SECCFGR3_SEC17_Msk /*!< Security configuration for block 17 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC18_Pos (18U) +#define GTZC_MPCBB_SECCFGR3_SEC18_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC18_Pos) /*!< 0x00040000 */ +#define GTZC_MPCBB_SECCFGR3_SEC18 GTZC_MPCBB_SECCFGR3_SEC18_Msk /*!< Security configuration for block 18 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC19_Pos (19U) +#define GTZC_MPCBB_SECCFGR3_SEC19_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC19_Pos) /*!< 0x00080000 */ +#define GTZC_MPCBB_SECCFGR3_SEC19 GTZC_MPCBB_SECCFGR3_SEC19_Msk /*!< Security configuration for block 19 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC20_Pos (20U) +#define GTZC_MPCBB_SECCFGR3_SEC20_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC20_Pos) /*!< 0x00100000 */ +#define GTZC_MPCBB_SECCFGR3_SEC20 GTZC_MPCBB_SECCFGR3_SEC20_Msk /*!< Security configuration for block 20 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC21_Pos (21U) +#define GTZC_MPCBB_SECCFGR3_SEC21_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC21_Pos) /*!< 0x00200000 */ +#define GTZC_MPCBB_SECCFGR3_SEC21 GTZC_MPCBB_SECCFGR3_SEC21_Msk /*!< Security configuration for block 21 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC22_Pos (22U) +#define GTZC_MPCBB_SECCFGR3_SEC22_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC22_Pos) /*!< 0x00400000 */ +#define GTZC_MPCBB_SECCFGR3_SEC22 GTZC_MPCBB_SECCFGR3_SEC22_Msk /*!< Security configuration for block 22 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC23_Pos (23U) +#define GTZC_MPCBB_SECCFGR3_SEC23_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC23_Pos) /*!< 0x00800000 */ +#define GTZC_MPCBB_SECCFGR3_SEC23 GTZC_MPCBB_SECCFGR3_SEC23_Msk /*!< Security configuration for block 23 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC24_Pos (24U) +#define GTZC_MPCBB_SECCFGR3_SEC24_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC24_Pos) /*!< 0x01000000 */ +#define GTZC_MPCBB_SECCFGR3_SEC24 GTZC_MPCBB_SECCFGR3_SEC24_Msk /*!< Security configuration for block 24 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC25_Pos (25U) +#define GTZC_MPCBB_SECCFGR3_SEC25_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC25_Pos) /*!< 0x02000000 */ +#define GTZC_MPCBB_SECCFGR3_SEC25 GTZC_MPCBB_SECCFGR3_SEC25_Msk /*!< Security configuration for block 25 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC26_Pos (26U) +#define GTZC_MPCBB_SECCFGR3_SEC26_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC26_Pos) /*!< 0x04000000 */ +#define GTZC_MPCBB_SECCFGR3_SEC26 GTZC_MPCBB_SECCFGR3_SEC26_Msk /*!< Security configuration for block 26 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC27_Pos (27U) +#define GTZC_MPCBB_SECCFGR3_SEC27_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC27_Pos) /*!< 0x08000000 */ +#define GTZC_MPCBB_SECCFGR3_SEC27 GTZC_MPCBB_SECCFGR3_SEC27_Msk /*!< Security configuration for block 27 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC28_Pos (28U) +#define GTZC_MPCBB_SECCFGR3_SEC28_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC28_Pos) /*!< 0x10000000 */ +#define GTZC_MPCBB_SECCFGR3_SEC28 GTZC_MPCBB_SECCFGR3_SEC28_Msk /*!< Security configuration for block 28 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC29_Pos (29U) +#define GTZC_MPCBB_SECCFGR3_SEC29_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC29_Pos) /*!< 0x20000000 */ +#define GTZC_MPCBB_SECCFGR3_SEC29 GTZC_MPCBB_SECCFGR3_SEC29_Msk /*!< Security configuration for block 29 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC30_Pos (30U) +#define GTZC_MPCBB_SECCFGR3_SEC30_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC30_Pos) /*!< 0x40000000 */ +#define GTZC_MPCBB_SECCFGR3_SEC30 GTZC_MPCBB_SECCFGR3_SEC31_Msk /*!< Security configuration for block 30 in super block 3 */ +#define GTZC_MPCBB_SECCFGR3_SEC31_Pos (31U) +#define GTZC_MPCBB_SECCFGR3_SEC31_Msk (0x01UL << GTZC_MPCBB_SECCFGR3_SEC31_Pos) /*!< 0x80000000 */ +#define GTZC_MPCBB_SECCFGR3_SEC31 GTZC_MPCBB_SECCFGR3_SEC31_Msk /*!< Security configuration for block 31 in super block 3 */ + +/******************* Bits definition for GTZC_MPCBB_PRIVCFGR0 register ************/ +#define GTZC_MPCBB_PRIVCFGR0_PRIV0_Pos (0U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV0_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV0_Pos) /*!< 0x00000001 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV0 GTZC_MPCBB_PRIVCFGR0_PRIV0_Msk /*!< Privileged configuration for block 0 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV1_Pos (1U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV1_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV1_Pos) /*!< 0x00000002 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV1 GTZC_MPCBB_PRIVCFGR0_PRIV1_Msk /*!< Privileged configuration for block 1 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV2_Pos (2U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV2_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV2_Pos) /*!< 0x00000004 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV2 GTZC_MPCBB_PRIVCFGR0_PRIV2_Msk /*!< Privileged configuration for block 2 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV3_Pos (3U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV3_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV3_Pos) /*!< 0x00000008 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV3 GTZC_MPCBB_PRIVCFGR0_PRIV3_Msk /*!< Privileged configuration for block 3 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV4_Pos (4U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV4_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV4_Pos) /*!< 0x00000010 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV4 GTZC_MPCBB_PRIVCFGR0_PRIV4_Msk /*!< Privileged configuration for block 4 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV5_Pos (5U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV5_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV5_Pos) /*!< 0x00000020 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV5 GTZC_MPCBB_PRIVCFGR0_PRIV5_Msk /*!< Privileged configuration for block 5 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV6_Pos (6U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV6_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV6_Pos) /*!< 0x00000040 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV6 GTZC_MPCBB_PRIVCFGR0_PRIV6_Msk /*!< Privileged configuration for block 6 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV7_Pos (7U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV7_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV7_Pos) /*!< 0x00000080 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV7 GTZC_MPCBB_PRIVCFGR0_PRIV7_Msk /*!< Privileged configuration for block 7 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV8_Pos (8U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV8_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV8_Pos) /*!< 0x00000100 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV8 GTZC_MPCBB_PRIVCFGR0_PRIV8_Msk /*!< Privileged configuration for block 8 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV9_Pos (9U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV9_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV9_Pos) /*!< 0x00000200 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV9 GTZC_MPCBB_PRIVCFGR0_PRIV9_Msk /*!< Privileged configuration for block 9 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV10_Pos (10U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV10_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV10_Pos) /*!< 0x00000400 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV10 GTZC_MPCBB_PRIVCFGR0_PRIV10_Msk /*!< Privileged configuration for block 10 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV11_Pos (11U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV11_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV11_Pos) /*!< 0x00000800 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV11 GTZC_MPCBB_PRIVCFGR0_PRIV11_Msk /*!< Privileged configuration for block 11 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV12_Pos (12U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV12_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV12_Pos) /*!< 0x00001000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV12 GTZC_MPCBB_PRIVCFGR0_PRIV12_Msk /*!< Privileged configuration for block 12 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV13_Pos (13U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV13_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV13_Pos) /*!< 0x00002000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV13 GTZC_MPCBB_PRIVCFGR0_PRIV13_Msk /*!< Privileged configuration for block 13 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV14_Pos (14U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV14_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV14_Pos) /*!< 0x00004000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV14 GTZC_MPCBB_PRIVCFGR0_PRIV14_Msk /*!< Privileged configuration for block 14 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV15_Pos (15U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV15_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV15_Pos) /*!< 0x00008000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV15 GTZC_MPCBB_PRIVCFGR0_PRIV15_Msk /*!< Privileged configuration for block 15 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV16_Pos (16U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV16_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV16_Pos) /*!< 0x00010000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV16 GTZC_MPCBB_PRIVCFGR0_PRIV16_Msk /*!< Privileged configuration for block 16 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV17_Pos (17U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV17_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV17_Pos) /*!< 0x00020000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV17 GTZC_MPCBB_PRIVCFGR0_PRIV17_Msk /*!< Privileged configuration for block 17 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV18_Pos (18U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV18_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV18_Pos) /*!< 0x00040000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV18 GTZC_MPCBB_PRIVCFGR0_PRIV18_Msk /*!< Privileged configuration for block 18 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV19_Pos (19U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV19_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV19_Pos) /*!< 0x00080000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV19 GTZC_MPCBB_PRIVCFGR0_PRIV19_Msk /*!< Privileged configuration for block 19 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV20_Pos (20U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV20_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV20_Pos) /*!< 0x00100000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV20 GTZC_MPCBB_PRIVCFGR0_PRIV20_Msk /*!< Privileged configuration for block 20 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV21_Pos (21U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV21_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV21_Pos) /*!< 0x00200000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV21 GTZC_MPCBB_PRIVCFGR0_PRIV21_Msk /*!< Privileged configuration for block 21 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV22_Pos (22U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV22_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV22_Pos) /*!< 0x00400000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV22 GTZC_MPCBB_PRIVCFGR0_PRIV22_Msk /*!< Privileged configuration for block 22 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV23_Pos (23U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV23_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV23_Pos) /*!< 0x00800000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV23 GTZC_MPCBB_PRIVCFGR0_PRIV23_Msk /*!< Privileged configuration for block 23 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV24_Pos (24U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV24_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV24_Pos) /*!< 0x01000000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV24 GTZC_MPCBB_PRIVCFGR0_PRIV24_Msk /*!< Privileged configuration for block 24 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV25_Pos (25U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV25_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV25_Pos) /*!< 0x02000000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV25 GTZC_MPCBB_PRIVCFGR0_PRIV25_Msk /*!< Privileged configuration for block 25 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV26_Pos (26U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV26_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV26_Pos) /*!< 0x04000000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV26 GTZC_MPCBB_PRIVCFGR0_PRIV26_Msk /*!< Privileged configuration for block 26 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV27_Pos (27U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV27_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV27_Pos) /*!< 0x08000000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV27 GTZC_MPCBB_PRIVCFGR0_PRIV27_Msk /*!< Privileged configuration for block 27 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV28_Pos (28U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV28_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV28_Pos) /*!< 0x10000000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV28 GTZC_MPCBB_PRIVCFGR0_PRIV28_Msk /*!< Privileged configuration for block 28 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV29_Pos (29U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV29_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV29_Pos) /*!< 0x20000000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV29 GTZC_MPCBB_PRIVCFGR0_PRIV29_Msk /*!< Privileged configuration for block 29 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV30_Pos (30U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV30_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV30_Pos) /*!< 0x40000000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV30 GTZC_MPCBB_PRIVCFGR0_PRIV31_Msk /*!< Privileged configuration for block 30 in super block 0 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV31_Pos (31U) +#define GTZC_MPCBB_PRIVCFGR0_PRIV31_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR0_PRIV31_Pos) /*!< 0x80000000 */ +#define GTZC_MPCBB_PRIVCFGR0_PRIV31 GTZC_MPCBB_PRIVCFGR0_PRIV31_Msk /*!< Privileged configuration for block 31 in super block 0 */ + +/******************* Bits definition for GTZC_MPCBB_PRIVCFGR1 register ************/ +#define GTZC_MPCBB_PRIVCFGR1_PRIV0_Pos (0U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV0_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV0_Pos) /*!< 0x00000001 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV0 GTZC_MPCBB_PRIVCFGR1_PRIV0_Msk /*!< Privileged configuration for block 0 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV1_Pos (1U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV1_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV1_Pos) /*!< 0x00000002 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV1 GTZC_MPCBB_PRIVCFGR1_PRIV1_Msk /*!< Privileged configuration for block 1 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV2_Pos (2U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV2_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV2_Pos) /*!< 0x00000004 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV2 GTZC_MPCBB_PRIVCFGR1_PRIV2_Msk /*!< Privileged configuration for block 2 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV3_Pos (3U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV3_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV3_Pos) /*!< 0x00000008 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV3 GTZC_MPCBB_PRIVCFGR1_PRIV3_Msk /*!< Privileged configuration for block 3 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV4_Pos (4U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV4_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV4_Pos) /*!< 0x00000010 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV4 GTZC_MPCBB_PRIVCFGR1_PRIV4_Msk /*!< Privileged configuration for block 4 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV5_Pos (5U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV5_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV5_Pos) /*!< 0x00000020 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV5 GTZC_MPCBB_PRIVCFGR1_PRIV5_Msk /*!< Privileged configuration for block 5 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV6_Pos (6U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV6_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV6_Pos) /*!< 0x00000040 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV6 GTZC_MPCBB_PRIVCFGR1_PRIV6_Msk /*!< Privileged configuration for block 6 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV7_Pos (7U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV7_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV7_Pos) /*!< 0x00000080 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV7 GTZC_MPCBB_PRIVCFGR1_PRIV7_Msk /*!< Privileged configuration for block 7 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV8_Pos (8U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV8_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV8_Pos) /*!< 0x00000100 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV8 GTZC_MPCBB_PRIVCFGR1_PRIV8_Msk /*!< Privileged configuration for block 8 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV9_Pos (9U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV9_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV9_Pos) /*!< 0x00000200 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV9 GTZC_MPCBB_PRIVCFGR1_PRIV9_Msk /*!< Privileged configuration for block 9 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV10_Pos (10U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV10_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV10_Pos) /*!< 0x00000400 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV10 GTZC_MPCBB_PRIVCFGR1_PRIV10_Msk /*!< Privileged configuration for block 10 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV11_Pos (11U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV11_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV11_Pos) /*!< 0x00000800 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV11 GTZC_MPCBB_PRIVCFGR1_PRIV11_Msk /*!< Privileged configuration for block 11 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV12_Pos (12U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV12_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV12_Pos) /*!< 0x00001000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV12 GTZC_MPCBB_PRIVCFGR1_PRIV12_Msk /*!< Privileged configuration for block 12 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV13_Pos (13U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV13_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV13_Pos) /*!< 0x00002000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV13 GTZC_MPCBB_PRIVCFGR1_PRIV13_Msk /*!< Privileged configuration for block 13 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV14_Pos (14U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV14_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV14_Pos) /*!< 0x00004000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV14 GTZC_MPCBB_PRIVCFGR1_PRIV14_Msk /*!< Privileged configuration for block 14 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV15_Pos (15U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV15_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV15_Pos) /*!< 0x00008000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV15 GTZC_MPCBB_PRIVCFGR1_PRIV15_Msk /*!< Privileged configuration for block 15 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV16_Pos (16U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV16_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV16_Pos) /*!< 0x00010000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV16 GTZC_MPCBB_PRIVCFGR1_PRIV16_Msk /*!< Privileged configuration for block 16 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV17_Pos (17U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV17_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV17_Pos) /*!< 0x00020000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV17 GTZC_MPCBB_PRIVCFGR1_PRIV17_Msk /*!< Privileged configuration for block 17 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV18_Pos (18U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV18_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV18_Pos) /*!< 0x00040000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV18 GTZC_MPCBB_PRIVCFGR1_PRIV18_Msk /*!< Privileged configuration for block 18 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV19_Pos (19U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV19_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV19_Pos) /*!< 0x00080000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV19 GTZC_MPCBB_PRIVCFGR1_PRIV19_Msk /*!< Privileged configuration for block 19 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV20_Pos (20U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV20_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV20_Pos) /*!< 0x00100000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV20 GTZC_MPCBB_PRIVCFGR1_PRIV20_Msk /*!< Privileged configuration for block 20 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV21_Pos (21U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV21_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV21_Pos) /*!< 0x00200000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV21 GTZC_MPCBB_PRIVCFGR1_PRIV21_Msk /*!< Privileged configuration for block 21 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV22_Pos (22U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV22_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV22_Pos) /*!< 0x00400000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV22 GTZC_MPCBB_PRIVCFGR1_PRIV22_Msk /*!< Privileged configuration for block 22 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV23_Pos (23U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV23_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV23_Pos) /*!< 0x00800000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV23 GTZC_MPCBB_PRIVCFGR1_PRIV23_Msk /*!< Privileged configuration for block 23 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV24_Pos (24U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV24_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV24_Pos) /*!< 0x01000000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV24 GTZC_MPCBB_PRIVCFGR1_PRIV24_Msk /*!< Privileged configuration for block 24 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV25_Pos (25U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV25_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV25_Pos) /*!< 0x02000000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV25 GTZC_MPCBB_PRIVCFGR1_PRIV25_Msk /*!< Privileged configuration for block 25 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV26_Pos (26U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV26_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV26_Pos) /*!< 0x04000000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV26 GTZC_MPCBB_PRIVCFGR1_PRIV26_Msk /*!< Privileged configuration for block 26 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV27_Pos (27U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV27_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV27_Pos) /*!< 0x08000000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV27 GTZC_MPCBB_PRIVCFGR1_PRIV27_Msk /*!< Privileged configuration for block 27 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV28_Pos (28U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV28_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV28_Pos) /*!< 0x10000000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV28 GTZC_MPCBB_PRIVCFGR1_PRIV28_Msk /*!< Privileged configuration for block 28 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV29_Pos (29U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV29_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV29_Pos) /*!< 0x20000000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV29 GTZC_MPCBB_PRIVCFGR1_PRIV29_Msk /*!< Privileged configuration for block 29 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV30_Pos (30U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV30_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV30_Pos) /*!< 0x40000000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV30 GTZC_MPCBB_PRIVCFGR1_PRIV31_Msk /*!< Privileged configuration for block 30 in super block 1 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV31_Pos (31U) +#define GTZC_MPCBB_PRIVCFGR1_PRIV31_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR1_PRIV31_Pos) /*!< 0x80000000 */ +#define GTZC_MPCBB_PRIVCFGR1_PRIV31 GTZC_MPCBB_PRIVCFGR1_PRIV31_Msk /*!< Privileged configuration for block 31 in super block 1 */ + +/******************* Bits definition for GTZC_MPCBB_PRIVCFGR2 register ************/ +#define GTZC_MPCBB_PRIVCFGR2_PRIV0_Pos (0U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV0_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV0_Pos) /*!< 0x00000001 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV0 GTZC_MPCBB_PRIVCFGR2_PRIV0_Msk /*!< Privileged configuration for block 0 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV1_Pos (1U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV1_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV1_Pos) /*!< 0x00000002 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV1 GTZC_MPCBB_PRIVCFGR2_PRIV1_Msk /*!< Privileged configuration for block 1 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV2_Pos (2U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV2_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV2_Pos) /*!< 0x00000004 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV2 GTZC_MPCBB_PRIVCFGR2_PRIV2_Msk /*!< Privileged configuration for block 2 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV3_Pos (3U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV3_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV3_Pos) /*!< 0x00000008 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV3 GTZC_MPCBB_PRIVCFGR2_PRIV3_Msk /*!< Privileged configuration for block 3 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV4_Pos (4U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV4_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV4_Pos) /*!< 0x00000010 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV4 GTZC_MPCBB_PRIVCFGR2_PRIV4_Msk /*!< Privileged configuration for block 4 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV5_Pos (5U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV5_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV5_Pos) /*!< 0x00000020 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV5 GTZC_MPCBB_PRIVCFGR2_PRIV5_Msk /*!< Privileged configuration for block 5 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV6_Pos (6U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV6_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV6_Pos) /*!< 0x00000040 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV6 GTZC_MPCBB_PRIVCFGR2_PRIV6_Msk /*!< Privileged configuration for block 6 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV7_Pos (7U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV7_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV7_Pos) /*!< 0x00000080 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV7 GTZC_MPCBB_PRIVCFGR2_PRIV7_Msk /*!< Privileged configuration for block 7 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV8_Pos (8U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV8_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV8_Pos) /*!< 0x00000100 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV8 GTZC_MPCBB_PRIVCFGR2_PRIV8_Msk /*!< Privileged configuration for block 8 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV9_Pos (9U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV9_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV9_Pos) /*!< 0x00000200 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV9 GTZC_MPCBB_PRIVCFGR2_PRIV9_Msk /*!< Privileged configuration for block 9 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV10_Pos (10U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV10_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV10_Pos) /*!< 0x00000400 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV10 GTZC_MPCBB_PRIVCFGR2_PRIV10_Msk /*!< Privileged configuration for block 10 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV11_Pos (11U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV11_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV11_Pos) /*!< 0x00000800 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV11 GTZC_MPCBB_PRIVCFGR2_PRIV11_Msk /*!< Privileged configuration for block 11 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV12_Pos (12U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV12_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV12_Pos) /*!< 0x00001000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV12 GTZC_MPCBB_PRIVCFGR2_PRIV12_Msk /*!< Privileged configuration for block 12 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV13_Pos (13U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV13_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV13_Pos) /*!< 0x00002000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV13 GTZC_MPCBB_PRIVCFGR2_PRIV13_Msk /*!< Privileged configuration for block 13 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV14_Pos (14U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV14_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV14_Pos) /*!< 0x00004000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV14 GTZC_MPCBB_PRIVCFGR2_PRIV14_Msk /*!< Privileged configuration for block 14 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV15_Pos (15U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV15_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV15_Pos) /*!< 0x00008000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV15 GTZC_MPCBB_PRIVCFGR2_PRIV15_Msk /*!< Privileged configuration for block 15 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV16_Pos (16U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV16_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV16_Pos) /*!< 0x00010000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV16 GTZC_MPCBB_PRIVCFGR2_PRIV16_Msk /*!< Privileged configuration for block 16 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV17_Pos (17U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV17_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV17_Pos) /*!< 0x00020000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV17 GTZC_MPCBB_PRIVCFGR2_PRIV17_Msk /*!< Privileged configuration for block 17 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV18_Pos (18U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV18_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV18_Pos) /*!< 0x00040000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV18 GTZC_MPCBB_PRIVCFGR2_PRIV18_Msk /*!< Privileged configuration for block 18 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV19_Pos (19U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV19_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV19_Pos) /*!< 0x00080000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV19 GTZC_MPCBB_PRIVCFGR2_PRIV19_Msk /*!< Privileged configuration for block 19 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV20_Pos (20U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV20_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV20_Pos) /*!< 0x00100000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV20 GTZC_MPCBB_PRIVCFGR2_PRIV20_Msk /*!< Privileged configuration for block 20 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV21_Pos (21U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV21_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV21_Pos) /*!< 0x00200000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV21 GTZC_MPCBB_PRIVCFGR2_PRIV21_Msk /*!< Privileged configuration for block 21 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV22_Pos (22U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV22_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV22_Pos) /*!< 0x00400000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV22 GTZC_MPCBB_PRIVCFGR2_PRIV22_Msk /*!< Privileged configuration for block 22 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV23_Pos (23U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV23_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV23_Pos) /*!< 0x00800000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV23 GTZC_MPCBB_PRIVCFGR2_PRIV23_Msk /*!< Privileged configuration for block 23 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV24_Pos (24U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV24_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV24_Pos) /*!< 0x01000000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV24 GTZC_MPCBB_PRIVCFGR2_PRIV24_Msk /*!< Privileged configuration for block 24 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV25_Pos (25U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV25_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV25_Pos) /*!< 0x02000000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV25 GTZC_MPCBB_PRIVCFGR2_PRIV25_Msk /*!< Privileged configuration for block 25 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV26_Pos (26U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV26_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV26_Pos) /*!< 0x04000000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV26 GTZC_MPCBB_PRIVCFGR2_PRIV26_Msk /*!< Privileged configuration for block 26 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV27_Pos (27U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV27_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV27_Pos) /*!< 0x08000000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV27 GTZC_MPCBB_PRIVCFGR2_PRIV27_Msk /*!< Privileged configuration for block 27 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV28_Pos (28U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV28_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV28_Pos) /*!< 0x10000000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV28 GTZC_MPCBB_PRIVCFGR2_PRIV28_Msk /*!< Privileged configuration for block 28 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV29_Pos (29U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV29_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV29_Pos) /*!< 0x20000000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV29 GTZC_MPCBB_PRIVCFGR2_PRIV29_Msk /*!< Privileged configuration for block 29 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV30_Pos (30U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV30_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV30_Pos) /*!< 0x40000000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV30 GTZC_MPCBB_PRIVCFGR2_PRIV31_Msk /*!< Privileged configuration for block 30 in super block 2 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV31_Pos (31U) +#define GTZC_MPCBB_PRIVCFGR2_PRIV31_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR2_PRIV31_Pos) /*!< 0x80000000 */ +#define GTZC_MPCBB_PRIVCFGR2_PRIV31 GTZC_MPCBB_PRIVCFGR2_PRIV31_Msk /*!< Privileged configuration for block 31 in super block 2 */ + +/******************* Bits definition for GTZC_MPCBB_PRIVCFGR3 register ************/ +#define GTZC_MPCBB_PRIVCFGR3_PRIV0_Pos (0U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV0_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV0_Pos) /*!< 0x00000001 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV0 GTZC_MPCBB_PRIVCFGR3_PRIV0_Msk /*!< Privileged configuration for block 0 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV1_Pos (1U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV1_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV1_Pos) /*!< 0x00000002 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV1 GTZC_MPCBB_PRIVCFGR3_PRIV1_Msk /*!< Privileged configuration for block 1 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV2_Pos (2U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV2_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV2_Pos) /*!< 0x00000004 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV2 GTZC_MPCBB_PRIVCFGR3_PRIV2_Msk /*!< Privileged configuration for block 2 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV3_Pos (3U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV3_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV3_Pos) /*!< 0x00000008 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV3 GTZC_MPCBB_PRIVCFGR3_PRIV3_Msk /*!< Privileged configuration for block 3 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV4_Pos (4U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV4_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV4_Pos) /*!< 0x00000010 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV4 GTZC_MPCBB_PRIVCFGR3_PRIV4_Msk /*!< Privileged configuration for block 4 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV5_Pos (5U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV5_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV5_Pos) /*!< 0x00000020 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV5 GTZC_MPCBB_PRIVCFGR3_PRIV5_Msk /*!< Privileged configuration for block 5 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV6_Pos (6U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV6_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV6_Pos) /*!< 0x00000040 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV6 GTZC_MPCBB_PRIVCFGR3_PRIV6_Msk /*!< Privileged configuration for block 6 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV7_Pos (7U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV7_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV7_Pos) /*!< 0x00000080 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV7 GTZC_MPCBB_PRIVCFGR3_PRIV7_Msk /*!< Privileged configuration for block 7 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV8_Pos (8U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV8_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV8_Pos) /*!< 0x00000100 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV8 GTZC_MPCBB_PRIVCFGR3_PRIV8_Msk /*!< Privileged configuration for block 8 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV9_Pos (9U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV9_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV9_Pos) /*!< 0x00000200 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV9 GTZC_MPCBB_PRIVCFGR3_PRIV9_Msk /*!< Privileged configuration for block 9 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV10_Pos (10U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV10_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV10_Pos) /*!< 0x00000400 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV10 GTZC_MPCBB_PRIVCFGR3_PRIV10_Msk /*!< Privileged configuration for block 10 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV11_Pos (11U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV11_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV11_Pos) /*!< 0x00000800 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV11 GTZC_MPCBB_PRIVCFGR3_PRIV11_Msk /*!< Privileged configuration for block 11 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV12_Pos (12U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV12_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV12_Pos) /*!< 0x00001000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV12 GTZC_MPCBB_PRIVCFGR3_PRIV12_Msk /*!< Privileged configuration for block 12 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV13_Pos (13U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV13_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV13_Pos) /*!< 0x00002000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV13 GTZC_MPCBB_PRIVCFGR3_PRIV13_Msk /*!< Privileged configuration for block 13 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV14_Pos (14U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV14_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV14_Pos) /*!< 0x00004000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV14 GTZC_MPCBB_PRIVCFGR3_PRIV14_Msk /*!< Privileged configuration for block 14 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV15_Pos (15U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV15_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV15_Pos) /*!< 0x00008000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV15 GTZC_MPCBB_PRIVCFGR3_PRIV15_Msk /*!< Privileged configuration for block 15 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV16_Pos (16U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV16_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV16_Pos) /*!< 0x00010000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV16 GTZC_MPCBB_PRIVCFGR3_PRIV16_Msk /*!< Privileged configuration for block 16 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV17_Pos (17U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV17_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV17_Pos) /*!< 0x00020000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV17 GTZC_MPCBB_PRIVCFGR3_PRIV17_Msk /*!< Privileged configuration for block 17 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV18_Pos (18U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV18_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV18_Pos) /*!< 0x00040000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV18 GTZC_MPCBB_PRIVCFGR3_PRIV18_Msk /*!< Privileged configuration for block 18 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV19_Pos (19U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV19_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV19_Pos) /*!< 0x00080000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV19 GTZC_MPCBB_PRIVCFGR3_PRIV19_Msk /*!< Privileged configuration for block 19 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV20_Pos (20U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV20_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV20_Pos) /*!< 0x00100000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV20 GTZC_MPCBB_PRIVCFGR3_PRIV20_Msk /*!< Privileged configuration for block 20 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV21_Pos (21U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV21_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV21_Pos) /*!< 0x00200000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV21 GTZC_MPCBB_PRIVCFGR3_PRIV21_Msk /*!< Privileged configuration for block 21 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV22_Pos (22U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV22_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV22_Pos) /*!< 0x00400000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV22 GTZC_MPCBB_PRIVCFGR3_PRIV22_Msk /*!< Privileged configuration for block 22 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV23_Pos (23U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV23_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV23_Pos) /*!< 0x00800000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV23 GTZC_MPCBB_PRIVCFGR3_PRIV23_Msk /*!< Privileged configuration for block 23 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV24_Pos (24U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV24_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV24_Pos) /*!< 0x01000000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV24 GTZC_MPCBB_PRIVCFGR3_PRIV24_Msk /*!< Privileged configuration for block 24 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV25_Pos (25U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV25_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV25_Pos) /*!< 0x02000000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV25 GTZC_MPCBB_PRIVCFGR3_PRIV25_Msk /*!< Privileged configuration for block 25 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV26_Pos (26U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV26_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV26_Pos) /*!< 0x04000000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV26 GTZC_MPCBB_PRIVCFGR3_PRIV26_Msk /*!< Privileged configuration for block 26 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV27_Pos (27U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV27_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV27_Pos) /*!< 0x08000000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV27 GTZC_MPCBB_PRIVCFGR3_PRIV27_Msk /*!< Privileged configuration for block 27 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV28_Pos (28U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV28_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV28_Pos) /*!< 0x10000000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV28 GTZC_MPCBB_PRIVCFGR3_PRIV28_Msk /*!< Privileged configuration for block 28 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV29_Pos (29U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV29_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV29_Pos) /*!< 0x20000000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV29 GTZC_MPCBB_PRIVCFGR3_PRIV29_Msk /*!< Privileged configuration for block 29 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV30_Pos (30U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV30_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV30_Pos) /*!< 0x40000000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV30 GTZC_MPCBB_PRIVCFGR3_PRIV31_Msk /*!< Privileged configuration for block 30 in super block 3 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV31_Pos (31U) +#define GTZC_MPCBB_PRIVCFGR3_PRIV31_Msk (0x01UL << GTZC_MPCBB_PRIVCFGR3_PRIV31_Pos) /*!< 0x80000000 */ +#define GTZC_MPCBB_PRIVCFGR3_PRIV31 GTZC_MPCBB_PRIVCFGR3_PRIV31_Msk /*!< Privileged configuration for block 31 in super block 3 */ + + +/******************************************************************************/ +/* */ +/* HASH */ +/* */ +/******************************************************************************/ +/****************** Bits definition for HASH_CR register ********************/ +#define HASH_CR_INIT_Pos (2U) +#define HASH_CR_INIT_Msk (0x1UL << HASH_CR_INIT_Pos) /*!< 0x00000004 */ +#define HASH_CR_INIT HASH_CR_INIT_Msk +#define HASH_CR_DMAE_Pos (3U) +#define HASH_CR_DMAE_Msk (0x1UL << HASH_CR_DMAE_Pos) /*!< 0x00000008 */ +#define HASH_CR_DMAE HASH_CR_DMAE_Msk +#define HASH_CR_DATATYPE_Pos (4U) +#define HASH_CR_DATATYPE_Msk (0x3UL << HASH_CR_DATATYPE_Pos) /*!< 0x00000030 */ +#define HASH_CR_DATATYPE HASH_CR_DATATYPE_Msk +#define HASH_CR_DATATYPE_0 (0x1UL << HASH_CR_DATATYPE_Pos) /*!< 0x00000010 */ +#define HASH_CR_DATATYPE_1 (0x2UL << HASH_CR_DATATYPE_Pos) /*!< 0x00000020 */ +#define HASH_CR_MODE_Pos (6U) +#define HASH_CR_MODE_Msk (0x1UL << HASH_CR_MODE_Pos) /*!< 0x00000040 */ +#define HASH_CR_MODE HASH_CR_MODE_Msk +#define HASH_CR_NBW_Pos (8U) +#define HASH_CR_NBW_Msk (0xFUL << HASH_CR_NBW_Pos) /*!< 0x00000F00 */ +#define HASH_CR_NBW HASH_CR_NBW_Msk +#define HASH_CR_NBW_0 (0x1UL << HASH_CR_NBW_Pos) /*!< 0x00000100 */ +#define HASH_CR_NBW_1 (0x2UL << HASH_CR_NBW_Pos) /*!< 0x00000200 */ +#define HASH_CR_NBW_2 (0x4UL << HASH_CR_NBW_Pos) /*!< 0x00000400 */ +#define HASH_CR_NBW_3 (0x8UL << HASH_CR_NBW_Pos) /*!< 0x00000800 */ +#define HASH_CR_DINNE_Pos (12U) +#define HASH_CR_DINNE_Msk (0x1UL << HASH_CR_DINNE_Pos) /*!< 0x00001000 */ +#define HASH_CR_DINNE HASH_CR_DINNE_Msk +#define HASH_CR_MDMAT_Pos (13U) +#define HASH_CR_MDMAT_Msk (0x1UL << HASH_CR_MDMAT_Pos) /*!< 0x00002000 */ +#define HASH_CR_MDMAT HASH_CR_MDMAT_Msk +#define HASH_CR_LKEY_Pos (16U) +#define HASH_CR_LKEY_Msk (0x1UL << HASH_CR_LKEY_Pos) /*!< 0x00010000 */ +#define HASH_CR_LKEY HASH_CR_LKEY_Msk +#define HASH_CR_ALGO_Pos (17U) +#define HASH_CR_ALGO_Msk (0x3UL << HASH_CR_ALGO_Pos) /*!< 0x00040080 */ +#define HASH_CR_ALGO HASH_CR_ALGO_Msk +#define HASH_CR_ALGO_0 (0x1UL << HASH_CR_ALGO_Pos) /*!< 0x00000080 */ +#define HASH_CR_ALGO_1 (0x2UL << HASH_CR_ALGO_Pos) /*!< 0x00040000 */ + +/****************** Bits definition for HASH_STR register *******************/ +#define HASH_STR_NBLW_Pos (0U) +#define HASH_STR_NBLW_Msk (0x1FUL << HASH_STR_NBLW_Pos) /*!< 0x0000001F */ +#define HASH_STR_NBLW HASH_STR_NBLW_Msk +#define HASH_STR_NBLW_0 (0x01UL << HASH_STR_NBLW_Pos) /*!< 0x00000001 */ +#define HASH_STR_NBLW_1 (0x02UL << HASH_STR_NBLW_Pos) /*!< 0x00000002 */ +#define HASH_STR_NBLW_2 (0x04UL << HASH_STR_NBLW_Pos) /*!< 0x00000004 */ +#define HASH_STR_NBLW_3 (0x08UL << HASH_STR_NBLW_Pos) /*!< 0x00000008 */ +#define HASH_STR_NBLW_4 (0x10UL << HASH_STR_NBLW_Pos) /*!< 0x00000010 */ +#define HASH_STR_DCAL_Pos (8U) +#define HASH_STR_DCAL_Msk (0x1UL << HASH_STR_DCAL_Pos) /*!< 0x00000100 */ +#define HASH_STR_DCAL HASH_STR_DCAL_Msk + +/****************** Bits definition for HASH_IMR register *******************/ +#define HASH_IMR_DINIE_Pos (0U) +#define HASH_IMR_DINIE_Msk (0x1UL << HASH_IMR_DINIE_Pos) /*!< 0x00000001 */ +#define HASH_IMR_DINIE HASH_IMR_DINIE_Msk +#define HASH_IMR_DCIE_Pos (1U) +#define HASH_IMR_DCIE_Msk (0x1UL << HASH_IMR_DCIE_Pos) /*!< 0x00000002 */ +#define HASH_IMR_DCIE HASH_IMR_DCIE_Msk + +/****************** Bits definition for HASH_SR register ********************/ +#define HASH_SR_DINIS_Pos (0U) +#define HASH_SR_DINIS_Msk (0x1UL << HASH_SR_DINIS_Pos) /*!< 0x00000001 */ +#define HASH_SR_DINIS HASH_SR_DINIS_Msk +#define HASH_SR_DCIS_Pos (1U) +#define HASH_SR_DCIS_Msk (0x1UL << HASH_SR_DCIS_Pos) /*!< 0x00000002 */ +#define HASH_SR_DCIS HASH_SR_DCIS_Msk +#define HASH_SR_DMAS_Pos (2U) +#define HASH_SR_DMAS_Msk (0x1UL << HASH_SR_DMAS_Pos) /*!< 0x00000004 */ +#define HASH_SR_DMAS HASH_SR_DMAS_Msk +#define HASH_SR_BUSY_Pos (3U) +#define HASH_SR_BUSY_Msk (0x1UL << HASH_SR_BUSY_Pos) /*!< 0x00000008 */ +#define HASH_SR_BUSY HASH_SR_BUSY_Msk +#define HASH_SR_NBWE_Pos (16U) +#define HASH_SR_NBWE_Msk (0xFUL << HASH_SR_NBWE_Pos) /*!< 0x000F0000 */ +#define HASH_SR_NBWE HASH_SR_NBWE_Msk +#define HASH_SR_NBWE_0 (0x01UL << HASH_SR_NBWE_Pos) /*!< 0x00010000 */ +#define HASH_SR_NBWE_1 (0x02UL << HASH_SR_NBWE_Pos) /*!< 0x00020000 */ +#define HASH_SR_NBWE_2 (0x04UL << HASH_SR_NBWE_Pos) /*!< 0x00040000 */ +#define HASH_SR_NBWE_3 (0x08UL << HASH_SR_NBWE_Pos) /*!< 0x00080000 */ +#define HASH_SR_DINNE_Pos (15U) +#define HASH_SR_DINNE_Msk (0x1UL << HASH_SR_DINNE_Pos) /*!< 0x00008000 */ +#define HASH_SR_DINNE HASH_SR_DINNE_Msk +#define HASH_SR_NBWP_Pos (9U) +#define HASH_SR_NBWP_Msk (0xFUL << HASH_SR_NBWP_Pos) /*!< 0x000F0000 */ +#define HASH_SR_NBWP HASH_SR_NBWP_Msk +#define HASH_SR_NBWP_0 (0x01UL << HASH_SR_NBWP_Pos) /*!< 0x000O0200 */ +#define HASH_SR_NBWP_1 (0x02UL << HASH_SR_NBWP_Pos) /*!< 0x00000400 */ +#define HASH_SR_NBWP_2 (0x04UL << HASH_SR_NBWP_Pos) /*!< 0x00000800 */ +#define HASH_SR_NBWP_3 (0x08UL << HASH_SR_NBWP_Pos) /*!< 0x00001000 */ + + +/******************************************************************************/ +/* */ +/* HSEM HW Semaphore */ +/* */ +/******************************************************************************/ +/******************** Bit definition for HSEM_R register ********************/ +#define HSEM_R_PROCID_Pos (0U) +#define HSEM_R_PROCID_Msk (0xFFUL << HSEM_R_PROCID_Pos) /*!< 0x000000FF */ +#define HSEM_R_PROCID HSEM_R_PROCID_Msk /*!>2) /*!< Input modulus number of bits */ +#define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Compute Montgomery parameter output data */ +#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output Montgomery parameter */ + +/* Compute modular exponentiation input data */ +#define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ +#define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ +#define PKA_MODULAR_EXP_IN_EXPONENT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process */ +#define PKA_MODULAR_EXP_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE ((0x16C8UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT ((0x14B8UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process protected exponentiation*/ +#define PKA_MODULAR_EXP_PROTECT_IN_MODULUS ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus to process protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_PHI ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input phi to process protected exponentiation */ + +/* Compute modular exponentiation output data */ +#define PKA_MODULAR_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_ERROR ((0x1298UL - PKA_RAM_OFFSET)>>2) /*!< Output error of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Output base of the exponentiation */ + +/* Compute ECC scalar multiplication input data */ +#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input curve prime order n number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_SCALAR_MUL_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' of KP */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input prime order n */ + +/* Compute ECC scalar multiplication output data */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Point check input data */ +#define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_POINT_CHECK_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_POINT_CHECK_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_POINT_CHECK_IN_MOD_GF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_POINT_CHECK_IN_MONTGOMERY_PARAM ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Point check output data */ +#define PKA_POINT_CHECK_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ + +/* ECDSA signature input data */ +#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECDSA_SIGN_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_SIGN_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input k value of the ECDSA */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_SIGN_IN_HASH_E ((0x0FE8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0x0F28UL - PKA_RAM_OFFSET)>>2) /*!< Input d, private key */ +#define PKA_ECDSA_SIGN_IN_ORDER_N ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA signature output data */ +#define PKA_ECDSA_SIGN_OUT_ERROR ((0x0FE0UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Output signature r */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Output signature s */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x1400UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point X coordinate */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1458UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point Y coordinate */ + + +/* ECDSA verification input data */ +#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x0468UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_A_COEFF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_MOD_GF ((0x04D0UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x0678UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x06D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0x12F8UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point X coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0x1350UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point Y coordinate */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x10E0UL - PKA_RAM_OFFSET)>>2) /*!< Input r, part of the signature */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input s, part of the signature */ +#define PKA_ECDSA_VERIF_IN_HASH_E ((0x13A8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_VERIF_IN_ORDER_N ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA verification output data */ +#define PKA_ECDSA_VERIF_OUT_RESULT ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* RSA CRT exponentiation input data */ +#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operands number of bits */ +#define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input Dp CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input Dq CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x0948UL - PKA_RAM_OFFSET)>>2) /*!< Input qInv CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x0B60UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime p */ +#define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime q */ +#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ + +/* RSA CRT exponentiation output data */ +#define PKA_RSA_CRT_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular reduction input data */ +#define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input operand length */ +#define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus length */ +#define PKA_MODULAR_REDUC_IN_OPERAND ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand */ +#define PKA_MODULAR_REDUC_IN_MODULUS ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Modular reduction output data */ +#define PKA_MODULAR_REDUC_OUT_RESULT ((0xE78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic addition input data */ +#define PKA_ARITHMETIC_ADD_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic addition output data */ +#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic subtraction input data */ +#define PKA_ARITHMETIC_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic subtraction output data */ +#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic multiplication input data */ +#define PKA_ARITHMETIC_MUL_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic multiplication output data */ +#define PKA_ARITHMETIC_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Comparison input data */ +#define PKA_COMPARISON_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_COMPARISON_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_COMPARISON_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Comparison output data */ +#define PKA_COMPARISON_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular addition input data */ +#define PKA_MODULAR_ADD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_ADD_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 (modulus) */ + +/* Modular addition output data */ +#define PKA_MODULAR_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular inversion input data */ +#define PKA_MODULAR_INV_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_INV_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_INV_IN_OP2_MOD ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 (modulus) */ + +/* Modular inversion output data */ +#define PKA_MODULAR_INV_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular subtraction input data */ +#define PKA_MODULAR_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_SUB_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ + +/* Modular subtraction output data */ +#define PKA_MODULAR_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Montgomery multiplication input data */ +#define PKA_MONTGOMERY_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MONTGOMERY_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MONTGOMERY_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Montgomery multiplication output data */ +#define PKA_MONTGOMERY_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Generic Arithmetic input data */ +#define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Generic Arithmetic output data */ +#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result for arithmetic operations */ + +/* Compute ECC complete addition input data */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC complete addition output data */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Output result Z coordinate */ + +/* Compute ECC double base ladder input data */ +#define PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input 'm' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC double base ladder output data */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_ERROR ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Compute ECC projective to affine conversion input data */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P X coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Y coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Z coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2 ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Compute ECC projective to affine conversion output data */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result x affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result y affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + + +/******************************************************************************/ +/* */ +/* PTA Converter */ +/* */ +/******************************************************************************/ +/****************** Bit definition for PTACONV_ACTCR register ***************/ +#define PTACONV_ACTCR_TACTIVE_Pos (0U) +#define PTACONV_ACTCR_TACTIVE_Msk (0xFFUL << PTACONV_ACTCR_TACTIVE_Pos) /*!< 0x000000FF */ +#define PTACONV_ACTCR_TACTIVE PTACONV_ACTCR_TACTIVE_Msk /*!< PTA_ACTIVE setup time in us */ +#define PTACONV_ACTCR_ACTPOL_Pos (15U) +#define PTACONV_ACTCR_ACTPOL_Msk (0x1UL << PTACONV_ACTCR_ACTPOL_Pos) /*!< 0x00008000 */ +#define PTACONV_ACTCR_ACTPOL PTACONV_ACTCR_ACTPOL_Msk /*!< PTA_ACTIVE polarity */ +#define PTACONV_ACTCR_TABORT_Pos (16U) +#define PTACONV_ACTCR_TABORT_Msk (0xFUL << PTACONV_ACTCR_TABORT_Pos) /*!< 0x000F0000 */ +#define PTACONV_ACTCR_TABORT PTACONV_ACTCR_TABORT_Msk /*!< PTA_ACTIVE delay to cease an ongoing transmission in us */ +#define PTACONV_ACTCR_ABORTDIS_Pos (20U) +#define PTACONV_ACTCR_ABORTDIS_Msk (0x1UL << PTACONV_ACTCR_ABORTDIS_Pos) /*!< 0x00100000 */ +#define PTACONV_ACTCR_ABORTDIS PTACONV_ACTCR_ABORTDIS_Msk /*!< Disable PTA_ACTIVE deny to abort an ongoing transmission */ + +/****************** Bit definition for PTACONV_PRICR register ***************/ +#define PTACONV_PRICR_TPRIORITY_Pos (0U) +#define PTACONV_PRICR_TPRIORITY_Msk (0x1FUL << PTACONV_PRICR_TPRIORITY_Pos) /*!< 0x0000001F */ +#define PTACONV_PRICR_TPRIORITY PTACONV_PRICR_TPRIORITY_Msk /*!< Priority valid time in us */ +#define PTACONV_PRICR_PRIPOL_Pos (15U) +#define PTACONV_PRICR_PRIPOL_Msk (0x1UL << PTACONV_PRICR_PRIPOL_Pos) /*!< 0x00008000 */ +#define PTACONV_PRICR_PRIPOL PTACONV_PRICR_PRIPOL_Msk /*!< Priority polarity */ + +/****************** Bit definition for PTACONV_CR register ******************/ +#define PTACONV_CR_TXRXPOL_Pos (15U) +#define PTACONV_CR_TXRXPOL_Msk (0x1UL << PTACONV_CR_TXRXPOL_Pos) /*!< 0x00008000 */ +#define PTACONV_CR_TXRXPOL PTACONV_CR_TXRXPOL_Msk /*!< PTA_STATUS transmit and receive polarity */ +#define PTACONV_CR_GRANTPOL_Pos (31U) +#define PTACONV_CR_GRANTPOL_Msk (0x1UL << PTACONV_CR_GRANTPOL_Pos) /*!< 0x80000000 */ +#define PTACONV_CR_GRANTPOL PTACONV_CR_GRANTPOL_Msk /*!< PTA_GRANT polarity */ + + +/******************************************************************************/ +/* */ +/* Power Control */ +/* */ +/******************************************************************************/ +/******************** Bit definition for PWR_CR1 register *******************/ +#define PWR_CR1_LPMS_Pos (0U) +#define PWR_CR1_LPMS_Msk (0x7UL << PWR_CR1_LPMS_Pos) /*!< 0x00000007 */ +#define PWR_CR1_LPMS PWR_CR1_LPMS_Msk /*!< LPMS[2:0] Low-power mode selection field */ +#define PWR_CR1_LPMS_0 (0x1UL << PWR_CR1_LPMS_Pos) /*!< 0x00000001 */ +#define PWR_CR1_LPMS_1 (0x2UL << PWR_CR1_LPMS_Pos) /*!< 0x00000002 */ +#define PWR_CR1_LPMS_2 (0x4UL << PWR_CR1_LPMS_Pos) /*!< 0x00000004 */ +#define PWR_CR1_R2RSB1_Pos (5U) +#define PWR_CR1_R2RSB1_Msk (0x1UL << PWR_CR1_R2RSB1_Pos) /*!< 0x00000020 */ +#define PWR_CR1_R2RSB1 PWR_CR1_R2RSB1_Msk /*!< SRAM2 Retention in Standby */ +#define PWR_CR1_ULPMEN_Pos (7U) +#define PWR_CR1_ULPMEN_Msk (0x1UL << PWR_CR1_ULPMEN_Pos) /*!< 0x00000080 */ +#define PWR_CR1_ULPMEN PWR_CR1_ULPMEN_Msk /*!< BOR ultra-low power mode in Standby/Shutdown */ +#define PWR_CR1_RADIORSB_Pos (9U) +#define PWR_CR1_RADIORSB_Msk (0x1UL << PWR_CR1_RADIORSB_Pos) /*!< 0x00000200 */ +#define PWR_CR1_RADIORSB PWR_CR1_RADIORSB_Msk /*!< 2.4GHz RADIO SRAMs (TXRX and Sequence) and Sleep clock retention in Standby mode */ +#define PWR_CR1_R1RSB1_Pos (12U) +#define PWR_CR1_R1RSB1_Msk (0x1UL << PWR_CR1_R1RSB1_Pos) /*!< 0x00001000 */ +#define PWR_CR1_R1RSB1 PWR_CR1_R1RSB1_Msk /*!< SRAM1 Page 1 Retention in Standby */ + +/******************** Bit definition for PWR_CR2 register *******************/ +#define PWR_CR2_SRAM1PDS1_Pos (0U) +#define PWR_CR2_SRAM1PDS1_Msk (0x1UL << PWR_CR2_SRAM1PDS1_Pos) /*!< 0x00000001 */ +#define PWR_CR2_SRAM1PDS1 PWR_CR2_SRAM1PDS1_Msk /*!< SRAM1 Page 1 power-down in Stop modes */ +#define PWR_CR2_SRAM2PDS1_Pos (4U) +#define PWR_CR2_SRAM2PDS1_Msk (0x1UL << PWR_CR2_SRAM2PDS1_Pos) /*!< 0x00000010 */ +#define PWR_CR2_SRAM2PDS1 PWR_CR2_SRAM2PDS1_Msk /*!< SRAM2 power-down in Stop modes */ +#define PWR_CR2_ICRAMPDS_Pos (8U) +#define PWR_CR2_ICRAMPDS_Msk (0x1UL << PWR_CR2_ICRAMPDS_Pos) /*!< 0x00000100 */ +#define PWR_CR2_ICRAMPDS PWR_CR2_ICRAMPDS_Msk /*!< ICACHE SRAM power-down in Stop modes */ +#define PWR_CR2_FLASHFWU_Pos (14U) +#define PWR_CR2_FLASHFWU_Msk (0x1UL << PWR_CR2_FLASHFWU_Pos) /*!< 0x00004000 */ +#define PWR_CR2_FLASHFWU PWR_CR2_FLASHFWU_Msk /*!< Flash low-power mode in Stop modes */ +#define PWR_CR2_FPWM_Pos (30U) +#define PWR_CR2_FPWM_Msk (0x1UL << PWR_CR2_FPWM_Pos) /*!< 0x40000000 */ +#define PWR_CR2_FPWM PWR_CR2_FPWM_Msk /*!< SMPS PWM mode */ + +/******************** Bit definition for PWR_CR3 register *******************/ +#define PWR_CR3_REGSEL_Pos (1U) +#define PWR_CR3_REGSEL_Msk (0x1UL << PWR_CR3_REGSEL_Pos) /*!< 0x00000002 */ +#define PWR_CR3_REGSEL PWR_CR3_REGSEL_Msk /*!< Regulator selection */ +#define PWR_CR3_FSTEN_Pos (2U) +#define PWR_CR3_FSTEN_Msk (0x1UL << PWR_CR3_FSTEN_Pos) /*!< 0x00000004 */ +#define PWR_CR3_FSTEN PWR_CR3_FSTEN_Msk /*!< Fast soft start */ + +/******************* Bit definition for PWR_VOSR register *******************/ +#define PWR_VOSR_VOSRDY_Pos (15U) +#define PWR_VOSR_VOSRDY_Msk (0x1UL << PWR_VOSR_VOSRDY_Pos) /*!< 0x00008000 */ +#define PWR_VOSR_VOSRDY PWR_VOSR_VOSRDY_Msk /*!< Ready bit for VCORE voltage scaling output selection */ +#define PWR_VOSR_VOS_Pos (16U) +#define PWR_VOSR_VOS_Msk (0x1UL << PWR_VOSR_VOS_Pos) /*!< 0x00010000 */ +#define PWR_VOSR_VOS PWR_VOSR_VOS_Msk /*!< Voltage scaling range selection */ + +/******************* Bit definition for PWR_SVMCR register ******************/ +#define PWR_SVMCR_PVDE_Pos (4U) +#define PWR_SVMCR_PVDE_Msk (0x1UL << PWR_SVMCR_PVDE_Pos) /*!< 0x00000010 */ +#define PWR_SVMCR_PVDE PWR_SVMCR_PVDE_Msk /*!< Power voltage detector enable */ +#define PWR_SVMCR_PVDLS_Pos (5U) +#define PWR_SVMCR_PVDLS_Msk (0x7UL << PWR_SVMCR_PVDLS_Pos) /*!< 0x000000E0 */ +#define PWR_SVMCR_PVDLS PWR_SVMCR_PVDLS_Msk /*!< PVDLS[2:0] Power voltage detector level selection field */ +#define PWR_SVMCR_PVDLS_0 (0x1UL << PWR_SVMCR_PVDLS_Pos) /*!< 0x00000020 */ +#define PWR_SVMCR_PVDLS_1 (0x2UL << PWR_SVMCR_PVDLS_Pos) /*!< 0x00000040 */ +#define PWR_SVMCR_PVDLS_2 (0x4UL << PWR_SVMCR_PVDLS_Pos) /*!< 0x00000080 */ + +/******************* Bit definition for PWR_WUCR1 register ******************/ +#define PWR_WUCR1_WUPEN1_Pos (0U) +#define PWR_WUCR1_WUPEN1_Msk (0x1UL << PWR_WUCR1_WUPEN1_Pos) /*!< 0x00000001 */ +#define PWR_WUCR1_WUPEN1 PWR_WUCR1_WUPEN1_Msk /*!< Wakeup pin WKUP1 enable */ +#define PWR_WUCR1_WUPEN2_Pos (1U) +#define PWR_WUCR1_WUPEN2_Msk (0x1UL << PWR_WUCR1_WUPEN2_Pos) /*!< 0x00000002 */ +#define PWR_WUCR1_WUPEN2 PWR_WUCR1_WUPEN2_Msk /*!< Wakeup pin WKUP2 enable */ +#define PWR_WUCR1_WUPEN3_Pos (2U) +#define PWR_WUCR1_WUPEN3_Msk (0x1UL << PWR_WUCR1_WUPEN3_Pos) /*!< 0x00000004 */ +#define PWR_WUCR1_WUPEN3 PWR_WUCR1_WUPEN3_Msk /*!< Wakeup pin WKUP3 enable */ +#define PWR_WUCR1_WUPEN4_Pos (3U) +#define PWR_WUCR1_WUPEN4_Msk (0x1UL << PWR_WUCR1_WUPEN4_Pos) /*!< 0x00000008 */ +#define PWR_WUCR1_WUPEN4 PWR_WUCR1_WUPEN4_Msk /*!< Wakeup pin WKUP4 enable */ +#define PWR_WUCR1_WUPEN5_Pos (4U) +#define PWR_WUCR1_WUPEN5_Msk (0x1UL << PWR_WUCR1_WUPEN5_Pos) /*!< 0x00000010 */ +#define PWR_WUCR1_WUPEN5 PWR_WUCR1_WUPEN5_Msk /*!< Wakeup pin WKUP5 enable */ +#define PWR_WUCR1_WUPEN6_Pos (5U) +#define PWR_WUCR1_WUPEN6_Msk (0x1UL << PWR_WUCR1_WUPEN6_Pos) /*!< 0x00000020 */ +#define PWR_WUCR1_WUPEN6 PWR_WUCR1_WUPEN6_Msk /*!< Wakeup pin WKUP6 enable */ +#define PWR_WUCR1_WUPEN7_Pos (6U) +#define PWR_WUCR1_WUPEN7_Msk (0x1UL << PWR_WUCR1_WUPEN7_Pos) /*!< 0x00000040 */ +#define PWR_WUCR1_WUPEN7 PWR_WUCR1_WUPEN7_Msk /*!< Wakeup pin WKUP7 enable */ +#define PWR_WUCR1_WUPEN8_Pos (7U) +#define PWR_WUCR1_WUPEN8_Msk (0x1UL << PWR_WUCR1_WUPEN8_Pos) /*!< 0x00000080 */ +#define PWR_WUCR1_WUPEN8 PWR_WUCR1_WUPEN8_Msk /*!< Wakeup pin WKUP8 enable */ + +/******************* Bit definition for PWR_WUCR2 register ******************/ +#define PWR_WUCR2_WUPP1_Pos (0U) +#define PWR_WUCR2_WUPP1_Msk (0x1UL << PWR_WUCR2_WUPP1_Pos) /*!< 0x00000001 */ +#define PWR_WUCR2_WUPP1 PWR_WUCR2_WUPP1_Msk /*!< Wakeup pin WKUP1 polarity */ +#define PWR_WUCR2_WUPP2_Pos (1U) +#define PWR_WUCR2_WUPP2_Msk (0x1UL << PWR_WUCR2_WUPP2_Pos) /*!< 0x00000002 */ +#define PWR_WUCR2_WUPP2 PWR_WUCR2_WUPP2_Msk /*!< Wakeup pin WKUP2 polarity */ +#define PWR_WUCR2_WUPP3_Pos (2U) +#define PWR_WUCR2_WUPP3_Msk (0x1UL << PWR_WUCR2_WUPP3_Pos) /*!< 0x00000004 */ +#define PWR_WUCR2_WUPP3 PWR_WUCR2_WUPP3_Msk /*!< Wakeup pin WKUP3 polarity */ +#define PWR_WUCR2_WUPP4_Pos (3U) +#define PWR_WUCR2_WUPP4_Msk (0x1UL << PWR_WUCR2_WUPP4_Pos) /*!< 0x00000008 */ +#define PWR_WUCR2_WUPP4 PWR_WUCR2_WUPP4_Msk /*!< Wakeup pin WKUP4 polarity */ +#define PWR_WUCR2_WUPP5_Pos (4U) +#define PWR_WUCR2_WUPP5_Msk (0x1UL << PWR_WUCR2_WUPP5_Pos) /*!< 0x00000010 */ +#define PWR_WUCR2_WUPP5 PWR_WUCR2_WUPP5_Msk /*!< Wakeup pin WKUP5 polarity */ +#define PWR_WUCR2_WUPP6_Pos (5U) +#define PWR_WUCR2_WUPP6_Msk (0x1UL << PWR_WUCR2_WUPP6_Pos) /*!< 0x00000020 */ +#define PWR_WUCR2_WUPP6 PWR_WUCR2_WUPP6_Msk /*!< Wakeup pin WKUP6 polarity */ +#define PWR_WUCR2_WUPP7_Pos (6U) +#define PWR_WUCR2_WUPP7_Msk (0x1UL << PWR_WUCR2_WUPP7_Pos) /*!< 0x00000040 */ +#define PWR_WUCR2_WUPP7 PWR_WUCR2_WUPP7_Msk /*!< Wakeup pin WKUP7 polarity */ +#define PWR_WUCR2_WUPP8_Pos (7U) +#define PWR_WUCR2_WUPP8_Msk (0x1UL << PWR_WUCR2_WUPP8_Pos) /*!< 0x00000080 */ +#define PWR_WUCR2_WUPP8 PWR_WUCR2_WUPP8_Msk /*!< Wakeup pin WKUP8 polarity */ + +/******************* Bit definition for PWR_WUCR3 register ******************/ +#define PWR_WUCR3_WUSEL1_Pos (0U) +#define PWR_WUCR3_WUSEL1_Msk (0x3UL << PWR_WUCR3_WUSEL1_Pos) /*!< 0x00000003 */ +#define PWR_WUCR3_WUSEL1 PWR_WUCR3_WUSEL1_Msk /*!< Wakeup pin WKUP1 selection field */ +#define PWR_WUCR3_WUSEL1_0 (0x1UL << PWR_WUCR3_WUSEL1_Pos) /*!< 0x00000001 */ +#define PWR_WUCR3_WUSEL1_1 (0x2UL << PWR_WUCR3_WUSEL1_Pos) /*!< 0x00000002 */ +#define PWR_WUCR3_WUSEL2_Pos (2U) +#define PWR_WUCR3_WUSEL2_Msk (0x3UL << PWR_WUCR3_WUSEL2_Pos) /*!< 0x0000000C */ +#define PWR_WUCR3_WUSEL2 PWR_WUCR3_WUSEL2_Msk /*!< Wakeup pin WKUP2 selection field */ +#define PWR_WUCR3_WUSEL2_0 (0x1UL << PWR_WUCR3_WUSEL2_Pos) /*!< 0x00000004 */ +#define PWR_WUCR3_WUSEL2_1 (0x2UL << PWR_WUCR3_WUSEL2_Pos) /*!< 0x00000008 */ +#define PWR_WUCR3_WUSEL3_Pos (4U) +#define PWR_WUCR3_WUSEL3_Msk (0x3UL << PWR_WUCR3_WUSEL3_Pos) /*!< 0x00000030 */ +#define PWR_WUCR3_WUSEL3 PWR_WUCR3_WUSEL3_Msk /*!< Wakeup pin WKUP3 selection field */ +#define PWR_WUCR3_WUSEL3_0 (0x1UL << PWR_WUCR3_WUSEL3_Pos) /*!< 0x00000010 */ +#define PWR_WUCR3_WUSEL3_1 (0x2UL << PWR_WUCR3_WUSEL3_Pos) /*!< 0x00000020 */ +#define PWR_WUCR3_WUSEL4_Pos (6U) +#define PWR_WUCR3_WUSEL4_Msk (0x3UL << PWR_WUCR3_WUSEL4_Pos) /*!< 0x000000C0 */ +#define PWR_WUCR3_WUSEL4 PWR_WUCR3_WUSEL4_Msk /*!< Wakeup pin WKUP4 selection field */ +#define PWR_WUCR3_WUSEL4_0 (0x1UL << PWR_WUCR3_WUSEL4_Pos) /*!< 0x00000040 */ +#define PWR_WUCR3_WUSEL4_1 (0x2UL << PWR_WUCR3_WUSEL4_Pos) /*!< 0x00000080 */ +#define PWR_WUCR3_WUSEL5_Pos (8U) +#define PWR_WUCR3_WUSEL5_Msk (0x3UL << PWR_WUCR3_WUSEL5_Pos) /*!< 0x00000300 */ +#define PWR_WUCR3_WUSEL5 PWR_WUCR3_WUSEL5_Msk /*!< Wakeup pin WKUP5 selection field */ +#define PWR_WUCR3_WUSEL5_0 (0x1UL << PWR_WUCR3_WUSEL5_Pos) /*!< 0x00000100 */ +#define PWR_WUCR3_WUSEL5_1 (0x2UL << PWR_WUCR3_WUSEL5_Pos) /*!< 0x00000200 */ +#define PWR_WUCR3_WUSEL6_Pos (10U) +#define PWR_WUCR3_WUSEL6_Msk (0x3UL << PWR_WUCR3_WUSEL6_Pos) /*!< 0x00000C00 */ +#define PWR_WUCR3_WUSEL6 PWR_WUCR3_WUSEL6_Msk /*!< Wakeup pin WKUP6 selection field */ +#define PWR_WUCR3_WUSEL6_0 (0x1UL << PWR_WUCR3_WUSEL6_Pos) /*!< 0x00000400 */ +#define PWR_WUCR3_WUSEL6_1 (0x2UL << PWR_WUCR3_WUSEL6_Pos) /*!< 0x00000800 */ +#define PWR_WUCR3_WUSEL7_Pos (12U) +#define PWR_WUCR3_WUSEL7_Msk (0x3UL << PWR_WUCR3_WUSEL7_Pos) /*!< 0x00003000 */ +#define PWR_WUCR3_WUSEL7 PWR_WUCR3_WUSEL7_Msk /*!< Wakeup pin WKUP7 selection field */ +#define PWR_WUCR3_WUSEL7_0 (0x1UL << PWR_WUCR3_WUSEL7_Pos) /*!< 0x00001000 */ +#define PWR_WUCR3_WUSEL7_1 (0x2UL << PWR_WUCR3_WUSEL7_Pos) /*!< 0x00002000 */ +#define PWR_WUCR3_WUSEL8_Pos (14U) +#define PWR_WUCR3_WUSEL8_Msk (0x3UL << PWR_WUCR3_WUSEL8_Pos) /*!< 0x0000C000 */ +#define PWR_WUCR3_WUSEL8 PWR_WUCR3_WUSEL8_Msk /*!< Wakeup pin WKUP8 selection field */ +#define PWR_WUCR3_WUSEL8_0 (0x1UL << PWR_WUCR3_WUSEL8_Pos) /*!< 0x00004000 */ +#define PWR_WUCR3_WUSEL8_1 (0x2UL << PWR_WUCR3_WUSEL8_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for PWR_DBPR register ******************/ +#define PWR_DBPR_DBP_Pos (0U) +#define PWR_DBPR_DBP_Msk (0x1UL << PWR_DBPR_DBP_Pos) /*!< 0x00000001 */ +#define PWR_DBPR_DBP PWR_DBPR_DBP_Msk /*!< Disable backup domain write protection */ + +/******************* Bit definition for PWR_SECCFGR register ****************/ +#define PWR_SECCFGR_WUP1SEC_Pos (0U) +#define PWR_SECCFGR_WUP1SEC_Msk (0x1UL << PWR_SECCFGR_WUP1SEC_Pos) /*!< 0x00000001 */ +#define PWR_SECCFGR_WUP1SEC PWR_SECCFGR_WUP1SEC_Msk /*!< WUP1 secure protection */ +#define PWR_SECCFGR_WUP2SEC_Pos (1U) +#define PWR_SECCFGR_WUP2SEC_Msk (0x1UL << PWR_SECCFGR_WUP2SEC_Pos) /*!< 0x00000002 */ +#define PWR_SECCFGR_WUP2SEC PWR_SECCFGR_WUP2SEC_Msk /*!< WUP2 secure protection */ +#define PWR_SECCFGR_WUP3SEC_Pos (2U) +#define PWR_SECCFGR_WUP3SEC_Msk (0x1UL << PWR_SECCFGR_WUP3SEC_Pos) /*!< 0x00000004 */ +#define PWR_SECCFGR_WUP3SEC PWR_SECCFGR_WUP3SEC_Msk /*!< WUP3 secure protection */ +#define PWR_SECCFGR_WUP4SEC_Pos (3U) +#define PWR_SECCFGR_WUP4SEC_Msk (0x1UL << PWR_SECCFGR_WUP4SEC_Pos) /*!< 0x00000008 */ +#define PWR_SECCFGR_WUP4SEC PWR_SECCFGR_WUP4SEC_Msk /*!< WUP4 secure protection */ +#define PWR_SECCFGR_WUP5SEC_Pos (4U) +#define PWR_SECCFGR_WUP5SEC_Msk (0x1UL << PWR_SECCFGR_WUP5SEC_Pos) /*!< 0x00000010 */ +#define PWR_SECCFGR_WUP5SEC PWR_SECCFGR_WUP5SEC_Msk /*!< WUP5 secure protection */ +#define PWR_SECCFGR_WUP6SEC_Pos (5U) +#define PWR_SECCFGR_WUP6SEC_Msk (0x1UL << PWR_SECCFGR_WUP6SEC_Pos) /*!< 0x00000020 */ +#define PWR_SECCFGR_WUP6SEC PWR_SECCFGR_WUP6SEC_Msk /*!< WUP6 secure protection */ +#define PWR_SECCFGR_WUP7SEC_Pos (6U) +#define PWR_SECCFGR_WUP7SEC_Msk (0x1UL << PWR_SECCFGR_WUP7SEC_Pos) /*!< 0x00000040 */ +#define PWR_SECCFGR_WUP7SEC PWR_SECCFGR_WUP7SEC_Msk /*!< WUP7 secure protection */ +#define PWR_SECCFGR_WUP8SEC_Pos (7U) +#define PWR_SECCFGR_WUP8SEC_Msk (0x1UL << PWR_SECCFGR_WUP8SEC_Pos) /*!< 0x00000080 */ +#define PWR_SECCFGR_WUP8SEC PWR_SECCFGR_WUP8SEC_Msk /*!< WUP8 secure protection */ +#define PWR_SECCFGR_LPMSEC_Pos (12U) +#define PWR_SECCFGR_LPMSEC_Msk (0x1UL << PWR_SECCFGR_LPMSEC_Pos) /*!< 0x00001000 */ +#define PWR_SECCFGR_LPMSEC PWR_SECCFGR_LPMSEC_Msk /*!< Low-power modes secure protection */ +#define PWR_SECCFGR_VDMSEC_Pos (13U) +#define PWR_SECCFGR_VDMSEC_Msk (0x1UL << PWR_SECCFGR_VDMSEC_Pos) /*!< 0x00002000 */ +#define PWR_SECCFGR_VDMSEC PWR_SECCFGR_VDMSEC_Msk /*!< Voltage detection and monitoring secure protection */ +#define PWR_SECCFGR_VBSEC_Pos (14U) +#define PWR_SECCFGR_VBSEC_Msk (0x1UL << PWR_SECCFGR_VBSEC_Pos) /*!< 0x00004000 */ +#define PWR_SECCFGR_VBSEC PWR_SECCFGR_VBSEC_Msk /*!< Backup domain secure protection */ + +/******************* Bit definition for PWR_PRIVCFGR register ***************/ +#define PWR_PRIVCFGR_SPRIV_Pos (0U) +#define PWR_PRIVCFGR_SPRIV_Msk (0x1UL << PWR_PRIVCFGR_SPRIV_Pos) /*!< 0x00000001 */ +#define PWR_PRIVCFGR_SPRIV PWR_PRIVCFGR_SPRIV_Msk /*!< RCC secure functions privilege configuration */ +#define PWR_PRIVCFGR_NSPRIV_Pos (1U) +#define PWR_PRIVCFGR_NSPRIV_Msk (0x1UL << PWR_PRIVCFGR_NSPRIV_Pos) /*!< 0x00000002 */ +#define PWR_PRIVCFGR_NSPRIV PWR_PRIVCFGR_NSPRIV_Msk /*!< RCC non-secure functions privilege configuration */ + +/********************** Bit definition for PWR_SR register ******************/ +#define PWR_SR_CSSF_Pos (0U) +#define PWR_SR_CSSF_Msk (0x1UL << PWR_SR_CSSF_Pos) /*!< 0x00000001 */ +#define PWR_SR_CSSF PWR_SR_CSSF_Msk /*!< Clear Stop and Standby/Shutdown flags */ +#define PWR_SR_STOPF_Pos (1U) +#define PWR_SR_STOPF_Msk (0x1UL << PWR_SR_STOPF_Pos) /*!< 0x00000002 */ +#define PWR_SR_STOPF PWR_SR_STOPF_Msk /*!< Stop flag */ +#define PWR_SR_SBF_Pos (2U) +#define PWR_SR_SBF_Msk (0x1UL << PWR_SR_SBF_Pos) /*!< 0x00000004 */ +#define PWR_SR_SBF PWR_SR_SBF_Msk /*!< Standby/Shutdown flag */ + +/******************** Bit definition for PWR_SVMSR register *****************/ +#define PWR_SVMSR_REGS_Pos (1U) +#define PWR_SVMSR_REGS_Msk (0x1UL << PWR_SVMSR_REGS_Pos) /*!< 0x00000002 */ +#define PWR_SVMSR_REGS PWR_SVMSR_REGS_Msk /*!< Regulator status */ +#define PWR_SVMSR_PVDO_Pos (4U) +#define PWR_SVMSR_PVDO_Msk (0x1UL << PWR_SVMSR_PVDO_Pos) /*!< 0x00000010 */ +#define PWR_SVMSR_PVDO PWR_SVMSR_PVDO_Msk /*!< VDD voltage detector output */ +#define PWR_SVMSR_ACTVOSRDY_Pos (15U) +#define PWR_SVMSR_ACTVOSRDY_Msk (0x1UL << PWR_SVMSR_ACTVOSRDY_Pos) /*!< 0x00008000 */ +#define PWR_SVMSR_ACTVOSRDY PWR_SVMSR_ACTVOSRDY_Msk /*!< Voltage level ready for currently used VOS */ +#define PWR_SVMSR_ACTVOS_Pos (16U) +#define PWR_SVMSR_ACTVOS_Msk (0x1UL << PWR_SVMSR_ACTVOS_Pos) /*!< 0x00010000 */ +#define PWR_SVMSR_ACTVOS PWR_SVMSR_ACTVOS_Msk /*!< Voltage Output Scaling currently applied to VCORE */ + +/********************* Bit definition for PWR_WUSR register *****************/ +#define PWR_WUSR_WUF1_Pos (0U) +#define PWR_WUSR_WUF1_Msk (0x1UL << PWR_WUSR_WUF1_Pos) /*!< 0x00000001 */ +#define PWR_WUSR_WUF1 PWR_WUSR_WUF1_Msk /*!< Wakeup flag 1 */ +#define PWR_WUSR_WUF2_Pos (1U) +#define PWR_WUSR_WUF2_Msk (0x1UL << PWR_WUSR_WUF2_Pos) /*!< 0x00000002 */ +#define PWR_WUSR_WUF2 PWR_WUSR_WUF2_Msk /*!< Wakeup flag 2 */ +#define PWR_WUSR_WUF3_Pos (2U) +#define PWR_WUSR_WUF3_Msk (0x1UL << PWR_WUSR_WUF3_Pos) /*!< 0x00000004 */ +#define PWR_WUSR_WUF3 PWR_WUSR_WUF3_Msk /*!< Wakeup flag 3 */ +#define PWR_WUSR_WUF4_Pos (3U) +#define PWR_WUSR_WUF4_Msk (0x1UL << PWR_WUSR_WUF4_Pos) /*!< 0x00000008 */ +#define PWR_WUSR_WUF4 PWR_WUSR_WUF4_Msk /*!< Wakeup flag 4 */ +#define PWR_WUSR_WUF5_Pos (4U) +#define PWR_WUSR_WUF5_Msk (0x1UL << PWR_WUSR_WUF5_Pos) /*!< 0x00000010 */ +#define PWR_WUSR_WUF5 PWR_WUSR_WUF5_Msk /*!< Wakeup flag 5 */ +#define PWR_WUSR_WUF6_Pos (5U) +#define PWR_WUSR_WUF6_Msk (0x1UL << PWR_WUSR_WUF6_Pos) /*!< 0x00000020 */ +#define PWR_WUSR_WUF6 PWR_WUSR_WUF6_Msk /*!< Wakeup flag 6 */ +#define PWR_WUSR_WUF7_Pos (6U) +#define PWR_WUSR_WUF7_Msk (0x1UL << PWR_WUSR_WUF7_Pos) /*!< 0x00000040 */ +#define PWR_WUSR_WUF7 PWR_WUSR_WUF7_Msk /*!< Wakeup flag 7 */ +#define PWR_WUSR_WUF8_Pos (7U) +#define PWR_WUSR_WUF8_Msk (0x1UL << PWR_WUSR_WUF8_Pos) /*!< 0x00000080 */ +#define PWR_WUSR_WUF8 PWR_WUSR_WUF8_Msk /*!< Wakeup flag 8 */ +#define PWR_WUSR_WUF_Pos (0U) +#define PWR_WUSR_WUF_Msk (0xFFUL << PWR_WUSR_WUF_Pos) /*!< 0x000000FF */ +#define PWR_WUSR_WUF PWR_WUSR_WUF_Msk /*!< all Wakeup flag */ + +/********************* Bit definition for PWR_WUSCR register ****************/ +#define PWR_WUSCR_CWUF1_Pos (0U) +#define PWR_WUSCR_CWUF1_Msk (0x1UL << PWR_WUSCR_CWUF1_Pos) /*!< 0x00000001*/ +#define PWR_WUSCR_CWUF1 PWR_WUSCR_CWUF1_Msk /*!< Wakeup clear flag 1 */ +#define PWR_WUSCR_CWUF2_Pos (1U) +#define PWR_WUSCR_CWUF2_Msk (0x1UL << PWR_WUSCR_CWUF2_Pos) /*!< 0x00000002 */ +#define PWR_WUSCR_CWUF2 PWR_WUSCR_CWUF2_Msk /*!< Wakeup clear flag 2 */ +#define PWR_WUSCR_CWUF3_Pos (2U) +#define PWR_WUSCR_CWUF3_Msk (0x1UL << PWR_WUSCR_CWUF3_Pos) /*!< 0x00000004 */ +#define PWR_WUSCR_CWUF3 PWR_WUSCR_CWUF3_Msk /*!< Wakeup clear flag 3 */ +#define PWR_WUSCR_CWUF4_Pos (3U) +#define PWR_WUSCR_CWUF4_Msk (0x1UL << PWR_WUSCR_CWUF4_Pos) /*!< 0x00000008 */ +#define PWR_WUSCR_CWUF4 PWR_WUSCR_CWUF4_Msk /*!< Wakeup clear flag 4 */ +#define PWR_WUSCR_CWUF5_Pos (4U) +#define PWR_WUSCR_CWUF5_Msk (0x1UL << PWR_WUSCR_CWUF5_Pos) /*!< 0x00000010 */ +#define PWR_WUSCR_CWUF5 PWR_WUSCR_CWUF5_Msk /*!< Wakeup clear flag 5 */ +#define PWR_WUSCR_CWUF6_Pos (5U) +#define PWR_WUSCR_CWUF6_Msk (0x1UL << PWR_WUSCR_CWUF6_Pos) /*!< 0x00000020 */ +#define PWR_WUSCR_CWUF6 PWR_WUSCR_CWUF6_Msk /*!< Wakeup clear flag 6 */ +#define PWR_WUSCR_CWUF7_Pos (6U) +#define PWR_WUSCR_CWUF7_Msk (0x1UL << PWR_WUSCR_CWUF7_Pos) /*!< 0x00000040 */ +#define PWR_WUSCR_CWUF7 PWR_WUSCR_CWUF7_Msk /*!< Wakeup clear flag 7 */ +#define PWR_WUSCR_CWUF8_Pos (7U) +#define PWR_WUSCR_CWUF8_Msk (0x1UL << PWR_WUSCR_CWUF8_Pos) /*!< 0x00000080 */ +#define PWR_WUSCR_CWUF8 PWR_WUSCR_CWUF8_Msk /*!< Wakeup clear flag 8 */ +#define PWR_WUSCR_CWUF_Pos (0U) +#define PWR_WUSCR_CWUF_Msk (0xFFUL << PWR_WUSCR_CWUF1_Pos) /*!< 0x000000FF */ +#define PWR_WUSCR_CWUF PWR_WUSCR_CWUF_Msk /*!< all Wakeup clear flag */ + +/******************** Bit definition for PWR_IORETENRA register *****************/ +#define PWR_IORETENRA_EN0_Pos (0U) +#define PWR_IORETENRA_EN0_Msk (0x1UL << PWR_IORETENRA_EN0_Pos) /*!< 0x00000001 */ +#define PWR_IORETENRA_EN0 PWR_IORETENRA_EN0_Msk /*!< Standby GPIO retention enable for PA0 */ +#define PWR_IORETENRA_EN1_Pos (1U) +#define PWR_IORETENRA_EN1_Msk (0x1UL << PWR_IORETENRA_EN1_Pos) /*!< 0x00000002 */ +#define PWR_IORETENRA_EN1 PWR_IORETENRA_EN1_Msk /*!< Standby GPIO retention enable for PA1 */ +#define PWR_IORETENRA_EN2_Pos (2U) +#define PWR_IORETENRA_EN2_Msk (0x1UL << PWR_IORETENRA_EN2_Pos) /*!< 0x00000004 */ +#define PWR_IORETENRA_EN2 PWR_IORETENRA_EN2_Msk /*!< Standby GPIO retention enable for PA2 */ +#define PWR_IORETENRA_EN3_Pos (3U) +#define PWR_IORETENRA_EN3_Msk (0x1UL << PWR_IORETENRA_EN3_Pos) /*!< 0x00000008 */ +#define PWR_IORETENRA_EN3 PWR_IORETENRA_EN3_Msk /*!< Standby GPIO retention enable for PA3 */ +#define PWR_IORETENRA_EN4_Pos (4U) +#define PWR_IORETENRA_EN4_Msk (0x1UL << PWR_IORETENRA_EN4_Pos) /*!< 0x00000010 */ +#define PWR_IORETENRA_EN4 PWR_IORETENRA_EN4_Msk /*!< Standby GPIO retention enable for PA4 */ +#define PWR_IORETENRA_EN5_Pos (5U) +#define PWR_IORETENRA_EN5_Msk (0x1UL << PWR_IORETENRA_EN5_Pos) /*!< 0x00000020 */ +#define PWR_IORETENRA_EN5 PWR_IORETENRA_EN5_Msk /*!< Standby GPIO retention enable for PA5 */ +#define PWR_IORETENRA_EN6_Pos (6U) +#define PWR_IORETENRA_EN6_Msk (0x1UL << PWR_IORETENRA_EN6_Pos) /*!< 0x00000040 */ +#define PWR_IORETENRA_EN6 PWR_IORETENRA_EN6_Msk /*!< Standby GPIO retention enable for PA6 */ +#define PWR_IORETENRA_EN7_Pos (7U) +#define PWR_IORETENRA_EN7_Msk (0x1UL << PWR_IORETENRA_EN7_Pos) /*!< 0x00000080 */ +#define PWR_IORETENRA_EN7 PWR_IORETENRA_EN7_Msk /*!< Standby GPIO retention enable for PA7 */ +#define PWR_IORETENRA_EN8_Pos (8U) +#define PWR_IORETENRA_EN8_Msk (0x1UL << PWR_IORETENRA_EN8_Pos) /*!< 0x00000100 */ +#define PWR_IORETENRA_EN8 PWR_IORETENRA_EN8_Msk /*!< Standby GPIO retention enable for PA8 */ +#define PWR_IORETENRA_EN9_Pos (9U) +#define PWR_IORETENRA_EN9_Msk (0x1UL << PWR_IORETENRA_EN9_Pos) /*!< 0x00000200 */ +#define PWR_IORETENRA_EN9 PWR_IORETENRA_EN9_Msk /*!< Standby GPIO retention enable for PA9 */ +#define PWR_IORETENRA_EN10_Pos (10U) +#define PWR_IORETENRA_EN10_Msk (0x1UL << PWR_IORETENRA_EN10_Pos) /*!< 0x00000400 */ +#define PWR_IORETENRA_EN10 PWR_IORETENRA_EN10_Msk /*!< Standby GPIO retention enable for PA10 */ +#define PWR_IORETENRA_EN11_Pos (11U) +#define PWR_IORETENRA_EN11_Msk (0x1UL << PWR_IORETENRA_EN11_Pos) /*!< 0x00000800 */ +#define PWR_IORETENRA_EN11 PWR_IORETENRA_EN11_Msk /*!< Standby GPIO retention enable for PA11 */ +#define PWR_IORETENRA_EN12_Pos (12U) +#define PWR_IORETENRA_EN12_Msk (0x1UL << PWR_IORETENRA_EN12_Pos) /*!< 0x00001000 */ +#define PWR_IORETENRA_EN12 PWR_IORETENRA_EN12_Msk /*!< Standby GPIO retention enable for PA12 */ +#define PWR_IORETENRA_EN13_Pos (13U) +#define PWR_IORETENRA_EN13_Msk (0x1UL << PWR_IORETENRA_EN13_Pos) /*!< 0x00002000 */ +#define PWR_IORETENRA_EN13 PWR_IORETENRA_EN13_Msk /*!< Standby GPIO retention enable for PA13 */ +#define PWR_IORETENRA_EN14_Pos (14U) +#define PWR_IORETENRA_EN14_Msk (0x1UL << PWR_IORETENRA_EN14_Pos) /*!< 0x00004000 */ +#define PWR_IORETENRA_EN14 PWR_IORETENRA_EN14_Msk /*!< Standby GPIO retention enable for PA14 */ +#define PWR_IORETENRA_EN15_Pos (15U) +#define PWR_IORETENRA_EN15_Msk (0x1UL << PWR_IORETENRA_EN15_Pos) /*!< 0x00008000 */ +#define PWR_IORETENRA_EN15 PWR_IORETENRA_EN15_Msk /*!< Standby GPIO retention enable for PA15 */ + +/******************** Bit definition for PWR_IORETRA register *****************/ +#define PWR_IORETRA_RET0_Pos (0U) +#define PWR_IORETRA_RET0_Msk (0x1UL << PWR_IORETRA_RET0_Pos) /*!< 0x00000001 */ +#define PWR_IORETRA_RET0 PWR_IORETRA_RET0_Msk /*!< Standby GPIO retention status for PA0 */ +#define PWR_IORETRA_RET1_Pos (1U) +#define PWR_IORETRA_RET1_Msk (0x1UL << PWR_IORETRA_RET1_Pos) /*!< 0x00000002 */ +#define PWR_IORETRA_RET1 PWR_IORETRA_RET1_Msk /*!< Standby GPIO retention status for PA1 */ +#define PWR_IORETRA_RET2_Pos (2U) +#define PWR_IORETRA_RET2_Msk (0x1UL << PWR_IORETRA_RET2_Pos) /*!< 0x00000004 */ +#define PWR_IORETRA_RET2 PWR_IORETRA_RET2_Msk /*!< Standby GPIO retention status for PA2 */ +#define PWR_IORETRA_RET3_Pos (3U) +#define PWR_IORETRA_RET3_Msk (0x1UL << PWR_IORETRA_RET3_Pos) /*!< 0x00000008 */ +#define PWR_IORETRA_RET3 PWR_IORETRA_RET3_Msk /*!< Standby GPIO retention status for PA3 */ +#define PWR_IORETRA_RET4_Pos (4U) +#define PWR_IORETRA_RET4_Msk (0x1UL << PWR_IORETRA_RET4_Pos) /*!< 0x00000010 */ +#define PWR_IORETRA_RET4 PWR_IORETRA_RET4_Msk /*!< Standby GPIO retention status for PA4 */ +#define PWR_IORETRA_RET5_Pos (5U) +#define PWR_IORETRA_RET5_Msk (0x1UL << PWR_IORETRA_RET5_Pos) /*!< 0x00000020 */ +#define PWR_IORETRA_RET5 PWR_IORETRA_RET5_Msk /*!< Standby GPIO retention status for PA5 */ +#define PWR_IORETRA_RET6_Pos (6U) +#define PWR_IORETRA_RET6_Msk (0x1UL << PWR_IORETRA_RET6_Pos) /*!< 0x00000040 */ +#define PWR_IORETRA_RET6 PWR_IORETRA_RET6_Msk /*!< Standby GPIO retention status for PA6 */ +#define PWR_IORETRA_RET7_Pos (7U) +#define PWR_IORETRA_RET7_Msk (0x1UL << PWR_IORETRA_RET7_Pos) /*!< 0x00000080 */ +#define PWR_IORETRA_RET7 PWR_IORETRA_RET7_Msk /*!< Standby GPIO retention status for PA7 */ +#define PWR_IORETRA_RET8_Pos (8U) +#define PWR_IORETRA_RET8_Msk (0x1UL << PWR_IORETRA_RET8_Pos) /*!< 0x00000100 */ +#define PWR_IORETRA_RET8 PWR_IORETRA_RET8_Msk /*!< Standby GPIO retention status for PA8 */ +#define PWR_IORETRA_RET9_Pos (9U) +#define PWR_IORETRA_RET9_Msk (0x1UL << PWR_IORETRA_RET9_Pos) /*!< 0x00000200 */ +#define PWR_IORETRA_RET9 PWR_IORETRA_RET9_Msk /*!< Standby GPIO retention status for PA9 */ +#define PWR_IORETRA_RET10_Pos (10U) +#define PWR_IORETRA_RET10_Msk (0x1UL << PWR_IORETRA_RET10_Pos) /*!< 0x00000400 */ +#define PWR_IORETRA_RET10 PWR_IORETRA_RET10_Msk /*!< Standby GPIO retention status for PA10 */ +#define PWR_IORETRA_RET11_Pos (11U) +#define PWR_IORETRA_RET11_Msk (0x1UL << PWR_IORETRA_RET11_Pos) /*!< 0x00000800 */ +#define PWR_IORETRA_RET11 PWR_IORETRA_RET11_Msk /*!< Standby GPIO retention status for PA11 */ +#define PWR_IORETRA_RET12_Pos (12U) +#define PWR_IORETRA_RET12_Msk (0x1UL << PWR_IORETRA_RET12_Pos) /*!< 0x00001000 */ +#define PWR_IORETRA_RET12 PWR_IORETRA_RET12_Msk /*!< Standby GPIO retention status for PA12 */ +#define PWR_IORETRA_RET13_Pos (13U) +#define PWR_IORETRA_RET13_Msk (0x1UL << PWR_IORETRA_RET13_Pos) /*!< 0x00002000 */ +#define PWR_IORETRA_RET13 PWR_IORETRA_RET13_Msk /*!< Standby GPIO retention status for PA13 */ +#define PWR_IORETRA_RET14_Pos (14U) +#define PWR_IORETRA_RET14_Msk (0x1UL << PWR_IORETRA_RET14_Pos) /*!< 0x00004000 */ +#define PWR_IORETRA_RET14 PWR_IORETRA_RET14_Msk /*!< Standby GPIO retention status for PA14 */ +#define PWR_IORETRA_RET15_Pos (15U) +#define PWR_IORETRA_RET15_Msk (0x1UL << PWR_IORETRA_RET15_Pos) /*!< 0x00008000 */ +#define PWR_IORETRA_RET15 PWR_IORETRA_RET15_Msk /*!< Standby GPIO retention status for PA15 */ + +/******************** Bit definition for PWR_IORETENRB register *****************/ +#define PWR_IORETENRB_EN0_Pos (0U) +#define PWR_IORETENRB_EN0_Msk (0x1UL << PWR_IORETENRB_EN0_Pos) /*!< 0x00000001 */ +#define PWR_IORETENRB_EN0 PWR_IORETENRB_EN0_Msk /*!< Standby GPIO retention enable for PB0 */ +#define PWR_IORETENRB_EN1_Pos (1U) +#define PWR_IORETENRB_EN1_Msk (0x1UL << PWR_IORETENRB_EN1_Pos) /*!< 0x00000002 */ +#define PWR_IORETENRB_EN1 PWR_IORETENRB_EN1_Msk /*!< Standby GPIO retention enable for PB1 */ +#define PWR_IORETENRB_EN2_Pos (2U) +#define PWR_IORETENRB_EN2_Msk (0x1UL << PWR_IORETENRB_EN2_Pos) /*!< 0x00000004 */ +#define PWR_IORETENRB_EN2 PWR_IORETENRB_EN2_Msk /*!< Standby GPIO retention enable for PB2 */ +#define PWR_IORETENRB_EN3_Pos (3U) +#define PWR_IORETENRB_EN3_Msk (0x1UL << PWR_IORETENRB_EN3_Pos) /*!< 0x00000008 */ +#define PWR_IORETENRB_EN3 PWR_IORETENRB_EN3_Msk /*!< Standby GPIO retention enable for PB3 */ +#define PWR_IORETENRB_EN4_Pos (4U) +#define PWR_IORETENRB_EN4_Msk (0x1UL << PWR_IORETENRB_EN4_Pos) /*!< 0x00000010 */ +#define PWR_IORETENRB_EN4 PWR_IORETENRB_EN4_Msk /*!< Standby GPIO retention enable for PB4 */ +#define PWR_IORETENRB_EN5_Pos (5U) +#define PWR_IORETENRB_EN5_Msk (0x1UL << PWR_IORETENRB_EN5_Pos) /*!< 0x00000020 */ +#define PWR_IORETENRB_EN5 PWR_IORETENRB_EN5_Msk /*!< Standby GPIO retention enable for PB5 */ +#define PWR_IORETENRB_EN6_Pos (6U) +#define PWR_IORETENRB_EN6_Msk (0x1UL << PWR_IORETENRB_EN6_Pos) /*!< 0x00000040 */ +#define PWR_IORETENRB_EN6 PWR_IORETENRB_EN6_Msk /*!< Standby GPIO retention enable for PB6 */ +#define PWR_IORETENRB_EN7_Pos (7U) +#define PWR_IORETENRB_EN7_Msk (0x1UL << PWR_IORETENRB_EN7_Pos) /*!< 0x00000080 */ +#define PWR_IORETENRB_EN7 PWR_IORETENRB_EN7_Msk /*!< Standby GPIO retention enable for PB7 */ +#define PWR_IORETENRB_EN8_Pos (8U) +#define PWR_IORETENRB_EN8_Msk (0x1UL << PWR_IORETENRB_EN8_Pos) /*!< 0x00000100 */ +#define PWR_IORETENRB_EN8 PWR_IORETENRB_EN8_Msk /*!< Standby GPIO retention enable for PB8 */ +#define PWR_IORETENRB_EN9_Pos (9U) +#define PWR_IORETENRB_EN9_Msk (0x1UL << PWR_IORETENRB_EN9_Pos) /*!< 0x00000200 */ +#define PWR_IORETENRB_EN9 PWR_IORETENRB_EN9_Msk /*!< Standby GPIO retention enable for PB9 */ +#define PWR_IORETENRB_EN10_Pos (10U) +#define PWR_IORETENRB_EN10_Msk (0x1UL << PWR_IORETENRB_EN10_Pos) /*!< 0x00000400 */ +#define PWR_IORETENRB_EN10 PWR_IORETENRB_EN10_Msk /*!< Standby GPIO retention enable for PB10 */ +#define PWR_IORETENRB_EN11_Pos (11U) +#define PWR_IORETENRB_EN11_Msk (0x1UL << PWR_IORETENRB_EN11_Pos) /*!< 0x00000800 */ +#define PWR_IORETENRB_EN11 PWR_IORETENRB_EN11_Msk /*!< Standby GPIO retention enable for PB11 */ +#define PWR_IORETENRB_EN12_Pos (12U) +#define PWR_IORETENRB_EN12_Msk (0x1UL << PWR_IORETENRB_EN12_Pos) /*!< 0x00001000 */ +#define PWR_IORETENRB_EN12 PWR_IORETENRB_EN12_Msk /*!< Standby GPIO retention enable for PB12 */ +#define PWR_IORETENRB_EN13_Pos (13U) +#define PWR_IORETENRB_EN13_Msk (0x1UL << PWR_IORETENRB_EN13_Pos) /*!< 0x00002000 */ +#define PWR_IORETENRB_EN13 PWR_IORETENRB_EN13_Msk /*!< Standby GPIO retention enable for PB13 */ +#define PWR_IORETENRB_EN14_Pos (14U) +#define PWR_IORETENRB_EN14_Msk (0x1UL << PWR_IORETENRB_EN14_Pos) /*!< 0x00004000 */ +#define PWR_IORETENRB_EN14 PWR_IORETENRB_EN14_Msk /*!< Standby GPIO retention enable for PB14 */ +#define PWR_IORETENRB_EN15_Pos (15U) +#define PWR_IORETENRB_EN15_Msk (0x1UL << PWR_IORETENRB_EN15_Pos) /*!< 0x00008000 */ +#define PWR_IORETENRB_EN15 PWR_IORETENRB_EN15_Msk /*!< Standby GPIO retention enable for PB15 */ + +/******************** Bit definition for PWR_IORETRB register *****************/ +#define PWR_IORETRB_RET0_Pos (0U) +#define PWR_IORETRB_RET0_Msk (0x1UL << PWR_IORETRB_RET0_Pos) /*!< 0x00000001 */ +#define PWR_IORETRB_RET0 PWR_IORETRB_RET0_Msk /*!< Standby GPIO retention status for PB0 */ +#define PWR_IORETRB_RET1_Pos (1U) +#define PWR_IORETRB_RET1_Msk (0x1UL << PWR_IORETRB_RET1_Pos) /*!< 0x00000002 */ +#define PWR_IORETRB_RET1 PWR_IORETRB_RET1_Msk /*!< Standby GPIO retention status for PB1 */ +#define PWR_IORETRB_RET2_Pos (2U) +#define PWR_IORETRB_RET2_Msk (0x1UL << PWR_IORETRB_RET2_Pos) /*!< 0x00000004 */ +#define PWR_IORETRB_RET2 PWR_IORETRB_RET2_Msk /*!< Standby GPIO retention status for PB2 */ +#define PWR_IORETRB_RET3_Pos (3U) +#define PWR_IORETRB_RET3_Msk (0x1UL << PWR_IORETRB_RET3_Pos) /*!< 0x00000008 */ +#define PWR_IORETRB_RET3 PWR_IORETRB_RET3_Msk /*!< Standby GPIO retention status for PB3 */ +#define PWR_IORETRB_RET4_Pos (4U) +#define PWR_IORETRB_RET4_Msk (0x1UL << PWR_IORETRB_RET4_Pos) /*!< 0x00000010 */ +#define PWR_IORETRB_RET4 PWR_IORETRB_RET4_Msk /*!< Standby GPIO retention status for PB4 */ +#define PWR_IORETRB_RET5_Pos (5U) +#define PWR_IORETRB_RET5_Msk (0x1UL << PWR_IORETRB_RET5_Pos) /*!< 0x00000020 */ +#define PWR_IORETRB_RET5 PWR_IORETRB_RET5_Msk /*!< Standby GPIO retention status for PB5 */ +#define PWR_IORETRB_RET6_Pos (6U) +#define PWR_IORETRB_RET6_Msk (0x1UL << PWR_IORETRB_RET6_Pos) /*!< 0x00000040 */ +#define PWR_IORETRB_RET6 PWR_IORETRB_RET6_Msk /*!< Standby GPIO retention status for PB6 */ +#define PWR_IORETRB_RET7_Pos (7U) +#define PWR_IORETRB_RET7_Msk (0x1UL << PWR_IORETRB_RET7_Pos) /*!< 0x00000080 */ +#define PWR_IORETRB_RET7 PWR_IORETRB_RET7_Msk /*!< Standby GPIO retention status for PB7 */ +#define PWR_IORETRB_RET8_Pos (8U) +#define PWR_IORETRB_RET8_Msk (0x1UL << PWR_IORETRB_RET8_Pos) /*!< 0x00000100 */ +#define PWR_IORETRB_RET8 PWR_IORETRB_RET8_Msk /*!< Standby GPIO retention status for PB8 */ +#define PWR_IORETRB_RET9_Pos (9U) +#define PWR_IORETRB_RET9_Msk (0x1UL << PWR_IORETRB_RET9_Pos) /*!< 0x00000200 */ +#define PWR_IORETRB_RET9 PWR_IORETRB_RET9_Msk /*!< Standby GPIO retention status for PB9 */ +#define PWR_IORETRB_RET10_Pos (10U) +#define PWR_IORETRB_RET10_Msk (0x1UL << PWR_IORETRB_RET10_Pos) /*!< 0x00000400 */ +#define PWR_IORETRB_RET10 PWR_IORETRB_RET10_Msk /*!< Standby GPIO retention status for PB10 */ +#define PWR_IORETRB_RET11_Pos (11U) +#define PWR_IORETRB_RET11_Msk (0x1UL << PWR_IORETRB_RET11_Pos) /*!< 0x00000800 */ +#define PWR_IORETRB_RET11 PWR_IORETRB_RET11_Msk /*!< Standby GPIO retention status for PB11 */ +#define PWR_IORETRB_RET12_Pos (12U) +#define PWR_IORETRB_RET12_Msk (0x1UL << PWR_IORETRB_RET12_Pos) /*!< 0x00001000 */ +#define PWR_IORETRB_RET12 PWR_IORETRB_RET12_Msk /*!< Standby GPIO retention status for PB12 */ +#define PWR_IORETRB_RET13_Pos (13U) +#define PWR_IORETRB_RET13_Msk (0x1UL << PWR_IORETRB_RET13_Pos) /*!< 0x00002000 */ +#define PWR_IORETRB_RET13 PWR_IORETRB_RET13_Msk /*!< Standby GPIO retention status for PB13 */ +#define PWR_IORETRB_RET14_Pos (14U) +#define PWR_IORETRB_RET14_Msk (0x1UL << PWR_IORETRB_RET14_Pos) /*!< 0x00004000 */ +#define PWR_IORETRB_RET14 PWR_IORETRB_RET14_Msk /*!< Standby GPIO retention status for PB14 */ +#define PWR_IORETRB_RET15_Pos (15U) +#define PWR_IORETRB_RET15_Msk (0x1UL << PWR_IORETRB_RET15_Pos) /*!< 0x00008000 */ +#define PWR_IORETRB_RET15 PWR_IORETRB_RET15_Msk /*!< Standby GPIO retention status for PB15 */ + +/******************** Bit definition for PWR_IORETENRC register *****************/ +#define PWR_IORETENRC_EN13_Pos (13U) +#define PWR_IORETENRC_EN13_Msk (0x1UL << PWR_IORETENRC_EN13_Pos) /*!< 0x00002000 */ +#define PWR_IORETENRC_EN13 PWR_IORETENRC_EN13_Msk /*!< Standby GPIO retention enable for PC13 */ +#define PWR_IORETENRC_EN14_Pos (14U) +#define PWR_IORETENRC_EN14_Msk (0x1UL << PWR_IORETENRC_EN14_Pos) /*!< 0x00004000 */ +#define PWR_IORETENRC_EN14 PWR_IORETENRC_EN14_Msk /*!< Standby GPIO retention enable for PC14 */ +#define PWR_IORETENRC_EN15_Pos (15U) +#define PWR_IORETENRC_EN15_Msk (0x1UL << PWR_IORETENRC_EN15_Pos) /*!< 0x00008000 */ +#define PWR_IORETENRC_EN15 PWR_IORETENRC_EN15_Msk /*!< Standby GPIO retention enable for PC15 */ + +/******************** Bit definition for PWR_IORETRC register *****************/ +#define PWR_IORETRC_RET13_Pos (13U) +#define PWR_IORETRC_RET13_Msk (0x1UL << PWR_IORETRC_RET13_Pos) /*!< 0x00002000 */ +#define PWR_IORETRC_RET13 PWR_IORETRC_RET13_Msk /*!< Standby GPIO retention status for PC13 */ +#define PWR_IORETRC_RET14_Pos (14U) +#define PWR_IORETRC_RET14_Msk (0x1UL << PWR_IORETRC_RET14_Pos) /*!< 0x00004000 */ +#define PWR_IORETRC_RET14 PWR_IORETRC_RET14_Msk /*!< Standby GPIO retention status for PC14 */ +#define PWR_IORETRC_RET15_Pos (15U) +#define PWR_IORETRC_RET15_Msk (0x1UL << PWR_IORETRC_RET15_Pos) /*!< 0x00008000 */ +#define PWR_IORETRC_RET15 PWR_IORETRC_RET15_Msk /*!< Standby GPIO retention status for PC15 */ + +/******************** Bit definition for PWR_IORETENRH register *****************/ +#define PWR_IORETENRH_EN3_Pos (3U) +#define PWR_IORETENRH_EN3_Msk (0x1UL << PWR_IORETENRH_EN3_Pos) /*!< 0x00000008 */ +#define PWR_IORETENRH_EN3 PWR_IORETENRH_EN3_Msk /*!< Standby GPIO retention enable for PH3 */ + +/******************** Bit definition for PWR_IORETRH register *****************/ +#define PWR_IORETRH_RET3_Pos (3U) +#define PWR_IORETRH_RET3_Msk (0x1UL << PWR_IORETRH_RET3_Pos) /*!< 0x00000008 */ +#define PWR_IORETRH_RET3 PWR_IORETRH_RET3_Msk /*!< Standby GPIO retention status for PH3 */ + +/******************** Bit definition for PWR_RADIOSCR register *****************/ +#define PWR_RADIOSCR_MODE_Pos (0U) +#define PWR_RADIOSCR_MODE_Msk (0x3UL << PWR_RADIOSCR_MODE_Pos) /*!< 0x00000003 */ +#define PWR_RADIOSCR_MODE PWR_RADIOSCR_MODE_Msk /*!< 2.4 GHz RADIO operating mode */ +#define PWR_RADIOSCR_MODE_0 (0x1UL << PWR_RADIOSCR_MODE_Pos) /*!< 0x00000001 */ +#define PWR_RADIOSCR_MODE_1 (0x2UL << PWR_RADIOSCR_MODE_Pos) /*!< 0x00000002 */ +#define PWR_RADIOSCR_PHYMODE_Pos (2U) +#define PWR_RADIOSCR_PHYMODE_Msk (0x1UL << PWR_RADIOSCR_PHYMODE_Pos) /*!< 0x00000004 */ +#define PWR_RADIOSCR_PHYMODE PWR_RADIOSCR_PHYMODE_Msk /*!< 2.4 GHz RADIO PHY operating mode */ +#define PWR_RADIOSCR_ENCMODE_Pos (3U) +#define PWR_RADIOSCR_ENCMODE_Msk (0x1UL << PWR_RADIOSCR_ENCMODE_Pos) /*!< 0x00000008 */ +#define PWR_RADIOSCR_ENCMODE PWR_RADIOSCR_ENCMODE_Msk /*!< 2.4 GHz RADIO encryption function operating mode */ +#define PWR_RADIOSCR_RFVDDHPA_Pos (8U) +#define PWR_RADIOSCR_RFVDDHPA_Msk (0x1FUL << PWR_RADIOSCR_RFVDDHPA_Pos) /*!< 0x00001F00 */ +#define PWR_RADIOSCR_RFVDDHPA PWR_RADIOSCR_RFVDDHPA_Msk /*!< 2.4 GHz RADIO VDDHPA control word */ +#define PWR_RADIOSCR_REGPARDYV11_Pos (14U) +#define PWR_RADIOSCR_REGPARDYV11_Msk (0x1UL << PWR_RADIOSCR_REGPARDYV11_Pos) /*!< 0x00004000 */ +#define PWR_RADIOSCR_REGPARDYV11 PWR_RADIOSCR_REGPARDYV11_Msk /*!< Ready bit for VDDHPA voltage level when selecting VDDRFPA input */ +#define PWR_RADIOSCR_REGPARDYVDDRFPA_Pos (15U) +#define PWR_RADIOSCR_REGPARDYVDDRFPA_Msk (0x1UL << PWR_RADIOSCR_REGPARDYVDDRFPA_Pos) /*!< 0x00008000 */ +#define PWR_RADIOSCR_REGPARDYVDDRFPA PWR_RADIOSCR_REGPARDYVDDRFPA_Msk /*!< Ready bit for VDDHPA voltage level when selecting VDDRFPA input */ +#define PWR_RADIOSCR_REGPASEL_Pos (23U) +#define PWR_RADIOSCR_REGPASEL_Msk (0x1UL << PWR_RADIOSCR_REGPASEL_Pos) /*!< 0x00800000 */ +#define PWR_RADIOSCR_REGPASEL PWR_RADIOSCR_REGPASEL_Msk /*!< Regulator REG_VDDHPA input supply selection */ +#define PWR_RADIOSCR_REGPABYPEN_Pos (24U) +#define PWR_RADIOSCR_REGPABYPEN_Msk (0x1UL << PWR_RADIOSCR_REGPABYPEN_Pos) /*!< 0x01000000 */ +#define PWR_RADIOSCR_REGPABYPEN PWR_RADIOSCR_REGPABYPEN_Msk /*!< Regulator REG_VDDHPA bypass enable.*/ + + +/******************************************************************************/ +/* */ +/* SRAMs configuration controller */ +/* */ +/******************************************************************************/ +/******************* Bit definition for RAMCFG_MxCR register ******************/ +#define RAMCFG_CR_ALE_Pos (4U) +#define RAMCFG_CR_ALE_Msk (0x1UL << RAMCFG_CR_ALE_Pos) /*!< 0x00000010 */ +#define RAMCFG_CR_ALE RAMCFG_CR_ALE_Msk /*!< Address Latching Enable */ +#define RAMCFG_CR_SRAMER_Pos (8U) +#define RAMCFG_CR_SRAMER_Msk (0x1UL << RAMCFG_CR_SRAMER_Pos) /*!< 0x00000100 */ +#define RAMCFG_CR_SRAMER RAMCFG_CR_SRAMER_Msk /*!< Start Erase */ +#define RAMCFG_CR_WSC_Pos (16U) +#define RAMCFG_CR_WSC_Msk (0x7UL << RAMCFG_CR_WSC_Pos) /*!< 0x00070000 */ +#define RAMCFG_CR_WSC RAMCFG_CR_WSC_Msk /*!< WSC[18:16] Wait State Configuration field */ +#define RAMCFG_CR_WSC_0 (0x1UL << RAMCFG_CR_WSC_Pos) /*!< 0x00010000 */ +#define RAMCFG_CR_WSC_1 (0x2UL << RAMCFG_CR_WSC_Pos) /*!< 0x00020000 */ +#define RAMCFG_CR_WSC_2 (0x4UL << RAMCFG_CR_WSC_Pos) /*!< 0x00040000 */ + +/******************* Bit definition for RAMCFG_MxISR register ******************/ +#define RAMCFG_ISR_PED_Pos (1U) +#define RAMCFG_ISR_PED_Msk (0x1UL << RAMCFG_ISR_PED_Pos) /*!< 0x00000002 */ +#define RAMCFG_ISR_PED RAMCFG_ISR_PED_Msk /*!< Parity error detected */ +#define RAMCFG_ISR_SRAMBUSY_Pos (8U) +#define RAMCFG_ISR_SRAMBUSY_Msk (0x1UL << RAMCFG_ISR_SRAMBUSY_Pos) /*!< 0x00000100 */ +#define RAMCFG_ISR_SRAMBUSY RAMCFG_ISR_SRAMBUSY_Msk /*!< SRAM busy with erase operation */ + +/***************** Bit definition for RAMCFG_MxERKEYR register ***************/ +#define RAMCFG_ERKEYR_ERASEKEY_Pos (0U) +#define RAMCFG_ERKEYR_ERASEKEY_Msk (0xFFUL << RAMCFG_ERKEYR_ERASEKEY_Pos) /*!< 0x000000FF */ +#define RAMCFG_ERKEYR_ERASEKEY RAMCFG_ERKEYR_ERASEKEY_Msk /*!< Erase write protection key */ + +/******************* Bit definition for RAMCFG_MxIER register ******************/ +#define RAMCFG_IER_PEIE_Pos (1U) +#define RAMCFG_IER_PEIE_Msk (0x1UL << RAMCFG_IER_PEIE_Pos) /*!< 0x00000001 */ +#define RAMCFG_IER_PEIE RAMCFG_IER_PEIE_Msk /*!< Parity error interrupt enable */ +#define RAMCFG_IER_PENMI_Pos (3U) +#define RAMCFG_IER_PENMI_Msk (0x1UL << RAMCFG_IER_PENMI_Pos) /*!< 0x00000004 */ +#define RAMCFG_IER_PENMI RAMCFG_IER_PENMI_Msk /*!< Parity error NMI */ + +/******************* Bit definition for RAMCFG_MxPEAR register ******************/ +#define RAMCFG_PEAR_PEA_Pos (0U) +#define RAMCFG_PEAR_PEA_Msk (0xFFFFUL << RAMCFG_PEAR_PEA_Pos) /*!< 0x0000FFFF */ +#define RAMCFG_PEAR_PEA RAMCFG_PEAR_PEA_Msk /*!< Parity error SRAM word aligned address offset */ +#define RAMCFG_PEAR_ID_Pos (24U) +#define RAMCFG_PEAR_ID_Msk (0xFUL << RAMCFG_PEAR_ID_Pos) /*!< 0x0F000000 */ +#define RAMCFG_PEAR_ID RAMCFG_PEAR_ID_Msk /*!< Parity error AHB bus master ID */ +#define RAMCFG_PEAR_BYTE_Pos (28U) +#define RAMCFG_PEAR_BYTE_Msk (0xFUL << RAMCFG_PEAR_BYTE_Pos) /*!< 0xF0000000 */ +#define RAMCFG_PEAR_BYTE RAMCFG_PEAR_BYTE_Msk /*!< Byte parity error flag */ + +/******************* Bit definition for RAMCFG_MxICR register *****************/ +#define RAMCFG_ICR_CPED_Pos (1U) +#define RAMCFG_ICR_CPED_Msk (0x1UL << RAMCFG_ICR_CPED_Pos) /*!< 0x00000002 */ +#define RAMCFG_ICR_CPED RAMCFG_ICR_CPED_Msk /*!< Clear parity error detect bit */ + +/****************** Bit definition for RAMCFG_MxWPR1 register *****************/ +#define RAMCFG_WPR1_P0WP_Pos (0U) +#define RAMCFG_WPR1_P0WP_Msk (0x1UL << RAMCFG_WPR1_P0WP_Pos) /*!< 0x00000001 */ +#define RAMCFG_WPR1_P0WP RAMCFG_WPR1_P0WP_Msk /*!< Write Protection Page 00 */ +#define RAMCFG_WPR1_P1WP_Pos (1U) +#define RAMCFG_WPR1_P1WP_Msk (0x1UL << RAMCFG_WPR1_P1WP_Pos) /*!< 0x00000002 */ +#define RAMCFG_WPR1_P1WP RAMCFG_WPR1_P1WP_Msk /*!< Write Protection Page 01 */ +#define RAMCFG_WPR1_P2WP_Pos (2U) +#define RAMCFG_WPR1_P2WP_Msk (0x1UL << RAMCFG_WPR1_P2WP_Pos) /*!< 0x00000004 */ +#define RAMCFG_WPR1_P2WP RAMCFG_WPR1_P2WP_Msk /*!< Write Protection Page 02 */ +#define RAMCFG_WPR1_P3WP_Pos (3U) +#define RAMCFG_WPR1_P3WP_Msk (0x1UL << RAMCFG_WPR1_P3WP_Pos) /*!< 0x00000008 */ +#define RAMCFG_WPR1_P3WP RAMCFG_WPR1_P3WP_Msk /*!< Write Protection Page 03 */ +#define RAMCFG_WPR1_P4WP_Pos (4U) +#define RAMCFG_WPR1_P4WP_Msk (0x1UL << RAMCFG_WPR1_P4WP_Pos) /*!< 0x00000010 */ +#define RAMCFG_WPR1_P4WP RAMCFG_WPR1_P4WP_Msk /*!< Write Protection Page 04 */ +#define RAMCFG_WPR1_P5WP_Pos (5U) +#define RAMCFG_WPR1_P5WP_Msk (0x1UL << RAMCFG_WPR1_P5WP_Pos) /*!< 0x00000020 */ +#define RAMCFG_WPR1_P5WP RAMCFG_WPR1_P5WP_Msk /*!< Write Protection Page 05 */ +#define RAMCFG_WPR1_P6WP_Pos (6U) +#define RAMCFG_WPR1_P6WP_Msk (0x1UL << RAMCFG_WPR1_P6WP_Pos) /*!< 0x00000040 */ +#define RAMCFG_WPR1_P6WP RAMCFG_WPR1_P6WP_Msk /*!< Write Protection Page 06 */ +#define RAMCFG_WPR1_P7WP_Pos (7U) +#define RAMCFG_WPR1_P7WP_Msk (0x1UL << RAMCFG_WPR1_P7WP_Pos) /*!< 0x00000080 */ +#define RAMCFG_WPR1_P7WP RAMCFG_WPR1_P7WP_Msk /*!< Write Protection Page 07 */ +#define RAMCFG_WPR1_P8WP_Pos (8U) +#define RAMCFG_WPR1_P8WP_Msk (0x1UL << RAMCFG_WPR1_P8WP_Pos) /*!< 0x00000100 */ +#define RAMCFG_WPR1_P8WP RAMCFG_WPR1_P8WP_Msk /*!< Write Protection Page 08 */ +#define RAMCFG_WPR1_P9WP_Pos (9U) +#define RAMCFG_WPR1_P9WP_Msk (0x1UL << RAMCFG_WPR1_P9WP_Pos) /*!< 0x00000200 */ +#define RAMCFG_WPR1_P9WP RAMCFG_WPR1_P9WP_Msk /*!< Write Protection Page 09 */ +#define RAMCFG_WPR1_P10WP_Pos (10U) +#define RAMCFG_WPR1_P10WP_Msk (0x1UL << RAMCFG_WPR1_P10WP_Pos) /*!< 0x00000400 */ +#define RAMCFG_WPR1_P10WP RAMCFG_WPR1_P10WP_Msk /*!< Write Protection Page 10 */ +#define RAMCFG_WPR1_P11WP_Pos (11U) +#define RAMCFG_WPR1_P11WP_Msk (0x1UL << RAMCFG_WPR1_P11WP_Pos) /*!< 0x00000800 */ +#define RAMCFG_WPR1_P11WP RAMCFG_WPR1_P11WP_Msk /*!< Write Protection Page 11 */ +#define RAMCFG_WPR1_P12WP_Pos (12U) +#define RAMCFG_WPR1_P12WP_Msk (0x1UL << RAMCFG_WPR1_P12WP_Pos) /*!< 0x00001000 */ +#define RAMCFG_WPR1_P12WP RAMCFG_WPR1_P12WP_Msk /*!< Write Protection Page 12 */ +#define RAMCFG_WPR1_P13WP_Pos (13U) +#define RAMCFG_WPR1_P13WP_Msk (0x1UL << RAMCFG_WPR1_P13WP_Pos) /*!< 0x00002000 */ +#define RAMCFG_WPR1_P13WP RAMCFG_WPR1_P13WP_Msk /*!< Write Protection Page 13 */ +#define RAMCFG_WPR1_P14WP_Pos (14U) +#define RAMCFG_WPR1_P14WP_Msk (0x1UL << RAMCFG_WPR1_P14WP_Pos) /*!< 0x00004000 */ +#define RAMCFG_WPR1_P14WP RAMCFG_WPR1_P14WP_Msk /*!< Write Protection Page 14 */ +#define RAMCFG_WPR1_P15WP_Pos (15U) +#define RAMCFG_WPR1_P15WP_Msk (0x1UL << RAMCFG_WPR1_P15WP_Pos) /*!< 0x00008000 */ +#define RAMCFG_WPR1_P15WP RAMCFG_WPR1_P15WP_Msk /*!< Write Protection Page 15 */ +#define RAMCFG_WPR1_P16WP_Pos (16U) +#define RAMCFG_WPR1_P16WP_Msk (0x1UL << RAMCFG_WPR1_P16WP_Pos) /*!< 0x00010000 */ +#define RAMCFG_WPR1_P16WP RAMCFG_WPR1_P16WP_Msk /*!< Write Protection Page 16 */ +#define RAMCFG_WPR1_P17WP_Pos (17U) +#define RAMCFG_WPR1_P17WP_Msk (0x1UL << RAMCFG_WPR1_P17WP_Pos) /*!< 0x00020000 */ +#define RAMCFG_WPR1_P17WP RAMCFG_WPR1_P17WP_Msk /*!< Write Protection Page 17 */ +#define RAMCFG_WPR1_P18WP_Pos (18U) +#define RAMCFG_WPR1_P18WP_Msk (0x1UL << RAMCFG_WPR1_P18WP_Pos) /*!< 0x00040000 */ +#define RAMCFG_WPR1_P18WP RAMCFG_WPR1_P18WP_Msk /*!< Write Protection Page 18 */ +#define RAMCFG_WPR1_P19WP_Pos (19U) +#define RAMCFG_WPR1_P19WP_Msk (0x1UL << RAMCFG_WPR1_P19WP_Pos) /*!< 0x00080000 */ +#define RAMCFG_WPR1_P19WP RAMCFG_WPR1_P19WP_Msk /*!< Write Protection Page 19 */ +#define RAMCFG_WPR1_P20WP_Pos (20U) +#define RAMCFG_WPR1_P20WP_Msk (0x1UL << RAMCFG_WPR1_P20WP_Pos) /*!< 0x00100000 */ +#define RAMCFG_WPR1_P20WP RAMCFG_WPR1_P20WP_Msk /*!< Write Protection Page 20 */ +#define RAMCFG_WPR1_P21WP_Pos (21U) +#define RAMCFG_WPR1_P21WP_Msk (0x1UL << RAMCFG_WPR1_P21WP_Pos) /*!< 0x00200000 */ +#define RAMCFG_WPR1_P21WP RAMCFG_WPR1_P21WP_Msk /*!< Write Protection Page 21 */ +#define RAMCFG_WPR1_P22WP_Pos (22U) +#define RAMCFG_WPR1_P22WP_Msk (0x1UL << RAMCFG_WPR1_P22WP_Pos) /*!< 0x00400000 */ +#define RAMCFG_WPR1_P22WP RAMCFG_WPR1_P22WP_Msk /*!< Write Protection Page 22 */ +#define RAMCFG_WPR1_P23WP_Pos (23U) +#define RAMCFG_WPR1_P23WP_Msk (0x1UL << RAMCFG_WPR1_P23WP_Pos) /*!< 0x00800000 */ +#define RAMCFG_WPR1_P23WP RAMCFG_WPR1_P23WP_Msk /*!< Write Protection Page 23 */ +#define RAMCFG_WPR1_P24WP_Pos (24U) +#define RAMCFG_WPR1_P24WP_Msk (0x1UL << RAMCFG_WPR1_P24WP_Pos) /*!< 0x01000000 */ +#define RAMCFG_WPR1_P24WP RAMCFG_WPR1_P24WP_Msk /*!< Write Protection Page 24 */ +#define RAMCFG_WPR1_P25WP_Pos (25U) +#define RAMCFG_WPR1_P25WP_Msk (0x1UL << RAMCFG_WPR1_P25WP_Pos) /*!< 0x02000000 */ +#define RAMCFG_WPR1_P25WP RAMCFG_WPR1_P25WP_Msk /*!< Write Protection Page 25 */ +#define RAMCFG_WPR1_P26WP_Pos (26U) +#define RAMCFG_WPR1_P26WP_Msk (0x1UL << RAMCFG_WPR1_P26WP_Pos) /*!< 0x04000000 */ +#define RAMCFG_WPR1_P26WP RAMCFG_WPR1_P26WP_Msk /*!< Write Protection Page 26 */ +#define RAMCFG_WPR1_P27WP_Pos (27U) +#define RAMCFG_WPR1_P27WP_Msk (0x1UL << RAMCFG_WPR1_P27WP_Pos) /*!< 0x08000000 */ +#define RAMCFG_WPR1_P27WP RAMCFG_WPR1_P27WP_Msk /*!< Write Protection Page 27 */ +#define RAMCFG_WPR1_P28WP_Pos (28U) +#define RAMCFG_WPR1_P28WP_Msk (0x1UL << RAMCFG_WPR1_P28WP_Pos) /*!< 0x10000000 */ +#define RAMCFG_WPR1_P28WP RAMCFG_WPR1_P28WP_Msk /*!< Write Protection Page 28 */ +#define RAMCFG_WPR1_P29WP_Pos (29U) +#define RAMCFG_WPR1_P29WP_Msk (0x1UL << RAMCFG_WPR1_P29WP_Pos) /*!< 0x20000000 */ +#define RAMCFG_WPR1_P29WP RAMCFG_WPR1_P29WP_Msk /*!< Write Protection Page 29 */ +#define RAMCFG_WPR1_P30WP_Pos (30U) +#define RAMCFG_WPR1_P30WP_Msk (0x1UL << RAMCFG_WPR1_P30WP_Pos) /*!< 0x40000000 */ +#define RAMCFG_WPR1_P30WP RAMCFG_WPR1_P30WP_Msk /*!< Write Protection Page 30 */ +#define RAMCFG_WPR1_P31WP_Pos (31U) +#define RAMCFG_WPR1_P31WP_Msk (0x1UL << RAMCFG_WPR1_P31WP_Pos) /*!< 0x80000000 */ +#define RAMCFG_WPR1_P31WP RAMCFG_WPR1_P31WP_Msk /*!< Write Protection Page 31 */ + +/****************** Bit definition for RAMCFG_MxWPR2 register ****************/ +#define RAMCFG_WPR2_P32WP_Pos (0U) +#define RAMCFG_WPR2_P32WP_Msk (0x1UL << RAMCFG_WPR2_P32WP_Pos) /*!< 0x00000001 */ +#define RAMCFG_WPR2_P32WP RAMCFG_WPR2_P32WP_Msk /*!< Write Protection Page 32 */ +#define RAMCFG_WPR2_P33WP_Pos (1U) +#define RAMCFG_WPR2_P33WP_Msk (0x1UL << RAMCFG_WPR2_P33WP_Pos) /*!< 0x00000002 */ +#define RAMCFG_WPR2_P33WP RAMCFG_WPR2_P33WP_Msk /*!< Write Protection Page 33 */ +#define RAMCFG_WPR2_P34WP_Pos (2U) +#define RAMCFG_WPR2_P34WP_Msk (0x1UL << RAMCFG_WPR2_P34WP_Pos) /*!< 0x00000004 */ +#define RAMCFG_WPR2_P34WP RAMCFG_WPR2_P34WP_Msk /*!< Write Protection Page 34 */ +#define RAMCFG_WPR2_P35WP_Pos (3U) +#define RAMCFG_WPR2_P35WP_Msk (0x1UL << RAMCFG_WPR2_P35WP_Pos) /*!< 0x00000008 */ +#define RAMCFG_WPR2_P35WP RAMCFG_WPR2_P35WP_Msk /*!< Write Protection Page 35 */ +#define RAMCFG_WPR2_P36WP_Pos (4U) +#define RAMCFG_WPR2_P36WP_Msk (0x1UL << RAMCFG_WPR2_P36WP_Pos) /*!< 0x00000010 */ +#define RAMCFG_WPR2_P36WP RAMCFG_WPR2_P36WP_Msk /*!< Write Protection Page 36 */ +#define RAMCFG_WPR2_P37WP_Pos (5U) +#define RAMCFG_WPR2_P37WP_Msk (0x1UL << RAMCFG_WPR2_P37WP_Pos) /*!< 0x00000020 */ +#define RAMCFG_WPR2_P37WP RAMCFG_WPR2_P37WP_Msk /*!< Write Protection Page 37 */ +#define RAMCFG_WPR2_P38WP_Pos (6U) +#define RAMCFG_WPR2_P38WP_Msk (0x1UL << RAMCFG_WPR2_P38WP_Pos) /*!< 0x00000040 */ +#define RAMCFG_WPR2_P38WP RAMCFG_WPR2_P38WP_Msk /*!< Write Protection Page 38 */ +#define RAMCFG_WPR2_P39WP_Pos (7U) +#define RAMCFG_WPR2_P39WP_Msk (0x1UL << RAMCFG_WPR2_P39WP_Pos) /*!< 0x00000080 */ +#define RAMCFG_WPR2_P39WP RAMCFG_WPR2_P39WP_Msk /*!< Write Protection Page 39 */ +#define RAMCFG_WPR2_P40WP_Pos (8U) +#define RAMCFG_WPR2_P40WP_Msk (0x1UL << RAMCFG_WPR2_P40WP_Pos) /*!< 0x00000100 */ +#define RAMCFG_WPR2_P40WP RAMCFG_WPR2_P40WP_Msk /*!< Write Protection Page 40 */ +#define RAMCFG_WPR2_P41WP_Pos (9U) +#define RAMCFG_WPR2_P41WP_Msk (0x1UL << RAMCFG_WPR2_P41WP_Pos) /*!< 0x00000200 */ +#define RAMCFG_WPR2_P41WP RAMCFG_WPR2_P41WP_Msk /*!< Write Protection Page 41 */ +#define RAMCFG_WPR2_P42WP_Pos (10U) +#define RAMCFG_WPR2_P42WP_Msk (0x1UL << RAMCFG_WPR2_P42WP_Pos) /*!< 0x00000400 */ +#define RAMCFG_WPR2_P42WP RAMCFG_WPR2_P42WP_Msk /*!< Write Protection Page 42 */ +#define RAMCFG_WPR2_P43WP_Pos (11U) +#define RAMCFG_WPR2_P43WP_Msk (0x1UL << RAMCFG_WPR2_P43WP_Pos) /*!< 0x00000800 */ +#define RAMCFG_WPR2_P43WP RAMCFG_WPR2_P43WP_Msk /*!< Write Protection Page 43 */ +#define RAMCFG_WPR2_P44WP_Pos (12U) +#define RAMCFG_WPR2_P44WP_Msk (0x1UL << RAMCFG_WPR2_P44WP_Pos) /*!< 0x00001000 */ +#define RAMCFG_WPR2_P44WP RAMCFG_WPR2_P44WP_Msk /*!< Write Protection Page 44 */ +#define RAMCFG_WPR2_P45WP_Pos (13U) +#define RAMCFG_WPR2_P45WP_Msk (0x1UL << RAMCFG_WPR2_P45WP_Pos) /*!< 0x00002000 */ +#define RAMCFG_WPR2_P45WP RAMCFG_WPR2_P45WP_Msk /*!< Write Protection Page 45 */ +#define RAMCFG_WPR2_P46WP_Pos (14U) +#define RAMCFG_WPR2_P46WP_Msk (0x1UL << RAMCFG_WPR2_P46WP_Pos) /*!< 0x00004000 */ +#define RAMCFG_WPR2_P46WP RAMCFG_WPR2_P46WP_Msk /*!< Write Protection Page 46 */ +#define RAMCFG_WPR2_P47WP_Pos (15U) +#define RAMCFG_WPR2_P47WP_Msk (0x1UL << RAMCFG_WPR2_P47WP_Pos) /*!< 0x00008000 */ +#define RAMCFG_WPR2_P47WP RAMCFG_WPR2_P47WP_Msk /*!< Write Protection Page 47 */ +#define RAMCFG_WPR2_P48WP_Pos (16U) +#define RAMCFG_WPR2_P48WP_Msk (0x1UL << RAMCFG_WPR2_P48WP_Pos) /*!< 0x00010000 */ +#define RAMCFG_WPR2_P48WP RAMCFG_WPR2_P48WP_Msk /*!< Write Protection Page 48 */ +#define RAMCFG_WPR2_P49WP_Pos (17U) +#define RAMCFG_WPR2_P49WP_Msk (0x1UL << RAMCFG_WPR2_P49WP_Pos) /*!< 0x00020000 */ +#define RAMCFG_WPR2_P49WP RAMCFG_WPR2_P49WP_Msk /*!< Write Protection Page 49 */ +#define RAMCFG_WPR2_P50WP_Pos (18U) +#define RAMCFG_WPR2_P50WP_Msk (0x1UL << RAMCFG_WPR2_P50WP_Pos) /*!< 0x00040000 */ +#define RAMCFG_WPR2_P50WP RAMCFG_WPR2_P50WP_Msk /*!< Write Protection Page 50 */ +#define RAMCFG_WPR2_P51WP_Pos (19U) +#define RAMCFG_WPR2_P51WP_Msk (0x1UL << RAMCFG_WPR2_P51WP_Pos) /*!< 0x00080000 */ +#define RAMCFG_WPR2_P51WP RAMCFG_WPR2_P51WP_Msk /*!< Write Protection Page 51 */ +#define RAMCFG_WPR2_P52WP_Pos (20U) +#define RAMCFG_WPR2_P52WP_Msk (0x1UL << RAMCFG_WPR2_P52WP_Pos) /*!< 0x00100000 */ +#define RAMCFG_WPR2_P52WP RAMCFG_WPR2_P52WP_Msk /*!< Write Protection Page 52 */ +#define RAMCFG_WPR2_P53WP_Pos (21U) +#define RAMCFG_WPR2_P53WP_Msk (0x1UL << RAMCFG_WPR2_P53WP_Pos) /*!< 0x00200000 */ +#define RAMCFG_WPR2_P53WP RAMCFG_WPR2_P53WP_Msk /*!< Write Protection Page 53 */ +#define RAMCFG_WPR2_P54WP_Pos (22U) +#define RAMCFG_WPR2_P54WP_Msk (0x1UL << RAMCFG_WPR2_P54WP_Pos) /*!< 0x00400000 */ +#define RAMCFG_WPR2_P54WP RAMCFG_WPR2_P54WP_Msk /*!< Write Protection Page 54 */ +#define RAMCFG_WPR2_P55WP_Pos (23U) +#define RAMCFG_WPR2_P55WP_Msk (0x1UL << RAMCFG_WPR2_P55WP_Pos) /*!< 0x00800000 */ +#define RAMCFG_WPR2_P55WP RAMCFG_WPR2_P55WP_Msk /*!< Write Protection Page 55 */ +#define RAMCFG_WPR2_P56WP_Pos (25U) +#define RAMCFG_WPR2_P56WP_Msk (0x1UL << RAMCFG_WPR2_P56WP_Pos) /*!< 0x01000000 */ +#define RAMCFG_WPR2_P56WP RAMCFG_WPR2_P56WP_Msk /*!< Write Protection Page 56 */ +#define RAMCFG_WPR2_P57WP_Pos (26U) +#define RAMCFG_WPR2_P57WP_Msk (0x1UL << RAMCFG_WPR2_P57WP_Pos) /*!< 0x02000000 */ +#define RAMCFG_WPR2_P57WP RAMCFG_WPR2_P57WP_Msk /*!< Write Protection Page 57 */ +#define RAMCFG_WPR2_P58WP_Pos (27U) +#define RAMCFG_WPR2_P58WP_Msk (0x1UL << RAMCFG_WPR2_P58WP_Pos) /*!< 0x04000000 */ +#define RAMCFG_WPR2_P58WP RAMCFG_WPR2_P58WP_Msk /*!< Write Protection Page 58 */ +#define RAMCFG_WPR2_P59WP_Pos (28U) +#define RAMCFG_WPR2_P59WP_Msk (0x1UL << RAMCFG_WPR2_P59WP_Pos) /*!< 0x08000000 */ +#define RAMCFG_WPR2_P59WP RAMCFG_WPR2_P59WP_Msk /*!< Write Protection Page 59 */ +#define RAMCFG_WPR2_P60WP_Pos (29U) +#define RAMCFG_WPR2_P60WP_Msk (0x1UL << RAMCFG_WPR2_P60WP_Pos) /*!< 0x10000000 */ +#define RAMCFG_WPR2_P60WP RAMCFG_WPR2_P60WP_Msk /*!< Write Protection Page 60 */ +#define RAMCFG_WPR2_P61WP_Pos (30U) +#define RAMCFG_WPR2_P61WP_Msk (0x1UL << RAMCFG_WPR2_P61WP_Pos) /*!< 0x20000000 */ +#define RAMCFG_WPR2_P61WP RAMCFG_WPR2_P61WP_Msk /*!< Write Protection Page 61 */ +#define RAMCFG_WPR2_P62WP_Pos (31U) +#define RAMCFG_WPR2_P62WP_Msk (0x1UL << RAMCFG_WPR2_P62WP_Pos) /*!< 0x40000000 */ +#define RAMCFG_WPR2_P62WP RAMCFG_WPR2_P62WP_Msk /*!< Write Protection Page 62 */ +#define RAMCFG_WPR2_P63WP_Pos (31U) +#define RAMCFG_WPR2_P63WP_Msk (0x1UL << RAMCFG_WPR2_P63WP_Pos) /*!< 0x80000000 */ +#define RAMCFG_WPR2_P63WP RAMCFG_WPR2_P63WP_Msk /*!< Write Protection Page 63 */ + + +/******************************************************************************/ +/* */ +/* Reset and Clock Control */ +/* */ +/******************************************************************************/ +#define RCC_LSI2_SUPPORT + +/******************** Bit definition for RCC_CR register ********************/ +#define RCC_CR_HSION_Pos (8U) +#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000100 */ +#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed oscillator (HSI16) clock enable */ +#define RCC_CR_HSIKERON_Pos (9U) +#define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos) /*!< 0x00000200 */ +#define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel */ +#define RCC_CR_HSIRDY_Pos (10U) +#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000400 */ +#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed oscillator (HSI16) clock ready flag */ +#define RCC_CR_HSEON_Pos (16U) +#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */ +#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed oscillator (HSE) clock enable */ +#define RCC_CR_HSERDY_Pos (17U) +#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */ +#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed oscillator (HSE) clock ready */ +#define RCC_CR_HSECSSON_Pos (19U) +#define RCC_CR_HSECSSON_Msk (0x1UL << RCC_CR_HSECSSON_Pos) /*!< 0x00080000 */ +#define RCC_CR_HSECSSON RCC_CR_HSECSSON_Msk /*!< External High Speed oscillator (HSE) clock security system enable */ +#define RCC_CR_HSEPRE_Pos (20U) +#define RCC_CR_HSEPRE_Msk (0x1UL << RCC_CR_HSEPRE_Pos) /*!< 0x00080000 */ +#define RCC_CR_HSEPRE RCC_CR_HSEPRE_Msk /*!< External High Speed oscillator (HSE) clock for sysclk prescaler */ +#define RCC_CR_PLL1ON_Pos (24U) +#define RCC_CR_PLL1ON_Msk (0x1UL << RCC_CR_PLL1ON_Pos) /*!< 0x01000000 */ +#define RCC_CR_PLL1ON RCC_CR_PLL1ON_Msk /*!< System PLL1 clock enable */ +#define RCC_CR_PLL1RDY_Pos (25U) +#define RCC_CR_PLL1RDY_Msk (0x1UL << RCC_CR_PLL1RDY_Pos) /*!< 0x02000000 */ +#define RCC_CR_PLL1RDY RCC_CR_PLL1RDY_Msk /*!< System PLL1 clock ready */ + +/******************** Bit definition for RCC_ICSCR3 register ***************/ +#define RCC_ICSCR3_HSICAL_Pos (0U) +#define RCC_ICSCR3_HSICAL_Msk (0xFFFUL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000FFF */ +#define RCC_ICSCR3_HSICAL RCC_ICSCR3_HSICAL_Msk /*!< HSICAL[11:0] bits */ +#define RCC_ICSCR3_HSICAL_0 (0x01UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000001 */ +#define RCC_ICSCR3_HSICAL_1 (0x002UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000002 */ +#define RCC_ICSCR3_HSICAL_2 (0x004UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000004 */ +#define RCC_ICSCR3_HSICAL_3 (0x008UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000008 */ +#define RCC_ICSCR3_HSICAL_4 (0x010UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000010 */ +#define RCC_ICSCR3_HSICAL_5 (0x020UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000020 */ +#define RCC_ICSCR3_HSICAL_6 (0x040UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000040 */ +#define RCC_ICSCR3_HSICAL_7 (0x080UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000080 */ +#define RCC_ICSCR3_HSICAL_8 (0x100UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000100 */ +#define RCC_ICSCR3_HSICAL_9 (0x200UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000200 */ +#define RCC_ICSCR3_HSICAL_10 (0x400UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000400 */ +#define RCC_ICSCR3_HSICAL_11 (0x800UL << RCC_ICSCR3_HSICAL_Pos) /*!< 0x00000800 */ +#define RCC_ICSCR3_HSITRIM_Pos (16U) +#define RCC_ICSCR3_HSITRIM_Msk (0x1FUL << RCC_ICSCR3_HSITRIM_Pos) /*!< 0x001F0000 */ +#define RCC_ICSCR3_HSITRIM RCC_ICSCR3_HSITRIM_Msk /*!< HSITRIM[4:0] bits */ +#define RCC_ICSCR3_HSITRIM_0 (0x01UL << RCC_ICSCR3_HSITRIM_Pos) /*!< 0x00010000 */ +#define RCC_ICSCR3_HSITRIM_1 (0x02UL << RCC_ICSCR3_HSITRIM_Pos) /*!< 0x00020000 */ +#define RCC_ICSCR3_HSITRIM_2 (0x04UL << RCC_ICSCR3_HSITRIM_Pos) /*!< 0x00040000 */ +#define RCC_ICSCR3_HSITRIM_3 (0x08UL << RCC_ICSCR3_HSITRIM_Pos) /*!< 0x00080000 */ +#define RCC_ICSCR3_HSITRIM_4 (0x10UL << RCC_ICSCR3_HSITRIM_Pos) /*!< 0x00100000 */ + +/******************** Bit definition for RCC_CFGR1 register *****************/ +#define RCC_CFGR1_SW_Pos (0U) +#define RCC_CFGR1_SW_Msk (0x3UL << RCC_CFGR1_SW_Pos) /*!< 0x00000003 */ +#define RCC_CFGR1_SW RCC_CFGR1_SW_Msk /*!< SW[1:0] bits (System clock Switch) */ +#define RCC_CFGR1_SW_0 (0x1UL << RCC_CFGR1_SW_Pos) /*!< 0x00000001 */ +#define RCC_CFGR1_SW_1 (0x2UL << RCC_CFGR1_SW_Pos) /*!< 0x00000002 */ +#define RCC_CFGR1_SWS_Pos (2U) +#define RCC_CFGR1_SWS_Msk (0x3UL << RCC_CFGR1_SWS_Pos) /*!< 0x0000000C */ +#define RCC_CFGR1_SWS RCC_CFGR1_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */ +#define RCC_CFGR1_SWS_0 (0x1UL << RCC_CFGR1_SWS_Pos) /*!< 0x00000004 */ +#define RCC_CFGR1_SWS_1 (0x2UL << RCC_CFGR1_SWS_Pos) /*!< 0x00000008 */ +#define RCC_CFGR1_MCOSEL_Pos (24U) +#define RCC_CFGR1_MCOSEL_Msk (0xFUL << RCC_CFGR1_MCOSEL_Pos) /*!< 0x0F000000 */ +#define RCC_CFGR1_MCOSEL RCC_CFGR1_MCOSEL_Msk /*!< MCOSEL[3:0] bits (Clock output selection) */ +#define RCC_CFGR1_MCOSEL_0 (0x1UL << RCC_CFGR1_MCOSEL_Pos) /*!< 0x01000000 */ +#define RCC_CFGR1_MCOSEL_1 (0x2UL << RCC_CFGR1_MCOSEL_Pos) /*!< 0x02000000 */ +#define RCC_CFGR1_MCOSEL_2 (0x4UL << RCC_CFGR1_MCOSEL_Pos) /*!< 0x04000000 */ +#define RCC_CFGR1_MCOSEL_3 (0x8UL << RCC_CFGR1_MCOSEL_Pos) /*!< 0x08000000 */ +#define RCC_CFGR1_MCOPRE_Pos (28U) +#define RCC_CFGR1_MCOPRE_Msk (0x7UL << RCC_CFGR1_MCOPRE_Pos) /*!< 0x70000000 */ +#define RCC_CFGR1_MCOPRE RCC_CFGR1_MCOPRE_Msk /*!< MCO[220] (Prescaler) */ +#define RCC_CFGR1_MCOPRE_0 (0x1UL << RCC_CFGR1_MCOPRE_Pos) /*!< 0x10000000 */ +#define RCC_CFGR1_MCOPRE_1 (0x2UL << RCC_CFGR1_MCOPRE_Pos) /*!< 0x20000000 */ +#define RCC_CFGR1_MCOPRE_2 (0x4UL << RCC_CFGR1_MCOPRE_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for RCC_CFGR2 register ******************/ +#define RCC_CFGR2_HPRE_Pos (0U) +#define RCC_CFGR2_HPRE_Msk (0x7UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000007 */ +#define RCC_CFGR2_HPRE RCC_CFGR2_HPRE_Msk /*!< HPRE[2:0] bits (AHB prescaler) */ +#define RCC_CFGR2_HPRE_0 (0x1UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000001 */ +#define RCC_CFGR2_HPRE_1 (0x2UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000002 */ +#define RCC_CFGR2_HPRE_2 (0x4UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00000004 */ +#define RCC_CFGR2_PPRE1_Pos (4U) +#define RCC_CFGR2_PPRE1_Msk (0x7UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000070 */ +#define RCC_CFGR2_PPRE1 RCC_CFGR2_PPRE1_Msk /*!< PPRE1[2:0] bits (APB1 prescaler) */ +#define RCC_CFGR2_PPRE1_0 (0x1UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000010 */ +#define RCC_CFGR2_PPRE1_1 (0x2UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000020 */ +#define RCC_CFGR2_PPRE1_2 (0x4UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000040 */ +#define RCC_CFGR2_PPRE2_Pos (8U) +#define RCC_CFGR2_PPRE2_Msk (0x7UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000700 */ +#define RCC_CFGR2_PPRE2 RCC_CFGR2_PPRE2_Msk /*!< PPRE2[2:0] bits (APB2 prescaler) */ +#define RCC_CFGR2_PPRE2_0 (0x1UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000100 */ +#define RCC_CFGR2_PPRE2_1 (0x2UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000200 */ +#define RCC_CFGR2_PPRE2_2 (0x4UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000400 */ + +/******************** Bit definition for RCC_CFGR3 register ******************/ +#define RCC_CFGR3_PPRE7_Pos (4U) +#define RCC_CFGR3_PPRE7_Msk (0x7UL << RCC_CFGR3_PPRE7_Pos) /*!< 0x00000070 */ +#define RCC_CFGR3_PPRE7 RCC_CFGR3_PPRE7_Msk /*!< PPRE7[2:0] bits (APB7 prescaler) */ +#define RCC_CFGR3_PPRE7_0 (0x1UL << RCC_CFGR3_PPRE7_Pos) /*!< 0x00000010 */ +#define RCC_CFGR3_PPRE7_1 (0x2UL << RCC_CFGR3_PPRE7_Pos) /*!< 0x00000020 */ +#define RCC_CFGR3_PPRE7_2 (0x4UL << RCC_CFGR3_PPRE7_Pos) /*!< 0x00000040 */ + +/******************** Bit definition for RCC_PLL1CFGR register ***************/ +#define RCC_PLL1CFGR_PLL1SRC_Pos (0U) +#define RCC_PLL1CFGR_PLL1SRC_Msk (0x3UL << RCC_PLL1CFGR_PLL1SRC_Pos) /*!< 0x00000003 */ +#define RCC_PLL1CFGR_PLL1SRC RCC_PLL1CFGR_PLL1SRC_Msk +#define RCC_PLL1CFGR_PLL1SRC_0 (0x1UL << RCC_PLL1CFGR_PLL1SRC_Pos) /*!< 0x00000001 */ +#define RCC_PLL1CFGR_PLL1SRC_1 (0x2UL << RCC_PLL1CFGR_PLL1SRC_Pos) /*!< 0x00000002 */ +#define RCC_PLL1CFGR_PLL1RGE_Pos (2U) +#define RCC_PLL1CFGR_PLL1RGE_Msk (0x3UL << RCC_PLL1CFGR_PLL1RGE_Pos) /*!< 0x0000000C */ +#define RCC_PLL1CFGR_PLL1RGE RCC_PLL1CFGR_PLL1RGE_Msk +#define RCC_PLL1CFGR_PLL1RGE_0 (0x1UL << RCC_PLL1CFGR_PLL1RGE_Pos) /*!< 0x00000004 */ +#define RCC_PLL1CFGR_PLL1RGE_1 (0x2UL << RCC_PLL1CFGR_PLL1RGE_Pos) /*!< 0x00000008 */ +#define RCC_PLL1CFGR_PLL1FRACEN_Pos (4U) +#define RCC_PLL1CFGR_PLL1FRACEN_Msk (0x1UL << RCC_PLL1CFGR_PLL1FRACEN_Pos) /*!< 0x00000010 */ +#define RCC_PLL1CFGR_PLL1FRACEN RCC_PLL1CFGR_PLL1FRACEN_Msk +#define RCC_PLL1CFGR_PLL1M_Pos (8U) +#define RCC_PLL1CFGR_PLL1M_Msk (0x7UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00000700 */ +#define RCC_PLL1CFGR_PLL1M RCC_PLL1CFGR_PLL1M_Msk +#define RCC_PLL1CFGR_PLL1M_0 (0x01UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00000100 */ +#define RCC_PLL1CFGR_PLL1M_1 (0x02UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00000200 */ +#define RCC_PLL1CFGR_PLL1M_2 (0x04UL << RCC_PLL1CFGR_PLL1M_Pos) /*!< 0x00000400 */ +#define RCC_PLL1CFGR_PLL1PEN_Pos (16U) +#define RCC_PLL1CFGR_PLL1PEN_Msk (0x1UL << RCC_PLL1CFGR_PLL1PEN_Pos) /*!< 0x00010000 */ +#define RCC_PLL1CFGR_PLL1PEN RCC_PLL1CFGR_PLL1PEN_Msk +#define RCC_PLL1CFGR_PLL1QEN_Pos (17U) +#define RCC_PLL1CFGR_PLL1QEN_Msk (0x1UL << RCC_PLL1CFGR_PLL1QEN_Pos) /*!< 0x00020000 */ +#define RCC_PLL1CFGR_PLL1QEN RCC_PLL1CFGR_PLL1QEN_Msk +#define RCC_PLL1CFGR_PLL1REN_Pos (18U) +#define RCC_PLL1CFGR_PLL1REN_Msk (0x1UL << RCC_PLL1CFGR_PLL1REN_Pos) /*!< 0x00040000 */ +#define RCC_PLL1CFGR_PLL1REN RCC_PLL1CFGR_PLL1REN_Msk +#define RCC_PLL1CFGR_PLL1RCLKPRE_Pos (20U) +#define RCC_PLL1CFGR_PLL1RCLKPRE_Msk (0x1UL << RCC_PLL1CFGR_PLL1RCLKPRE_Pos) /*!< 0x00100000 */ +#define RCC_PLL1CFGR_PLL1RCLKPRE RCC_PLL1CFGR_PLL1RCLKPRE_Msk +#define RCC_PLL1CFGR_PLL1RCLKPRESTEP_Pos (21U) +#define RCC_PLL1CFGR_PLL1RCLKPRESTEP_Msk (0x1UL << RCC_PLL1CFGR_PLL1RCLKPRESTEP_Pos) /*!< 0x00200000 */ +#define RCC_PLL1CFGR_PLL1RCLKPRESTEP RCC_PLL1CFGR_PLL1RCLKPRESTEP_Msk +#define RCC_PLL1CFGR_PLL1RCLKPRERDY_Pos (22U) +#define RCC_PLL1CFGR_PLL1RCLKPRERDY_Msk (0x1UL << RCC_PLL1CFGR_PLL1RCLKPRERDY_Pos) /*!< 0x00400000 */ +#define RCC_PLL1CFGR_PLL1RCLKPRERDY RCC_PLL1CFGR_PLL1RCLKPRERDY_Msk + +/******************** Bit definition for RCC_PLL1DIVR register ***************/ +#define RCC_PLL1DIVR_PLL1N_Pos (0U) +#define RCC_PLL1DIVR_PLL1N_Msk (0x1FFUL << RCC_PLL1DIVR_PLL1N_Pos) /*!< 0x000001FF */ +#define RCC_PLL1DIVR_PLL1N RCC_PLL1DIVR_PLL1N_Msk +#define RCC_PLL1DIVR_PLL1N_0 (0x001UL << RCC_PLL1DIVR_PLL1N_Pos) /*!< 0x00000001 */ +#define RCC_PLL1DIVR_PLL1N_1 (0x002UL << RCC_PLL1DIVR_PLL1N_Pos) /*!< 0x00000002 */ +#define RCC_PLL1DIVR_PLL1N_2 (0x004UL << RCC_PLL1DIVR_PLL1N_Pos) /*!< 0x00000004 */ +#define RCC_PLL1DIVR_PLL1N_3 (0x008UL << RCC_PLL1DIVR_PLL1N_Pos) /*!< 0x00000008 */ +#define RCC_PLL1DIVR_PLL1N_4 (0x010UL << RCC_PLL1DIVR_PLL1N_Pos) /*!< 0x00000010 */ +#define RCC_PLL1DIVR_PLL1N_5 (0x020UL << RCC_PLL1DIVR_PLL1N_Pos) /*!< 0x00000020 */ +#define RCC_PLL1DIVR_PLL1N_6 (0x040UL << RCC_PLL1DIVR_PLL1N_Pos) /*!< 0x00000040 */ +#define RCC_PLL1DIVR_PLL1N_7 (0x080UL << RCC_PLL1DIVR_PLL1N_Pos) /*!< 0x00000080 */ +#define RCC_PLL1DIVR_PLL1N_8 (0x100UL << RCC_PLL1DIVR_PLL1N_Pos) /*!< 0x00000100 */ +#define RCC_PLL1DIVR_PLL1P_Pos (9U) +#define RCC_PLL1DIVR_PLL1P_Msk (0x7FUL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x0000FE00 */ +#define RCC_PLL1DIVR_PLL1P RCC_PLL1DIVR_PLL1P_Msk +#define RCC_PLL1DIVR_PLL1P_0 (0x01UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00000200 */ +#define RCC_PLL1DIVR_PLL1P_1 (0x02UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00000400 */ +#define RCC_PLL1DIVR_PLL1P_2 (0x04UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00000800 */ +#define RCC_PLL1DIVR_PLL1P_3 (0x08UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00001000 */ +#define RCC_PLL1DIVR_PLL1P_4 (0x10UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00002000 */ +#define RCC_PLL1DIVR_PLL1P_5 (0x20UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00004000 */ +#define RCC_PLL1DIVR_PLL1P_6 (0x40UL << RCC_PLL1DIVR_PLL1P_Pos) /*!< 0x00008000 */ +#define RCC_PLL1DIVR_PLL1Q_Pos (16U) +#define RCC_PLL1DIVR_PLL1Q_Msk (0x7FUL << RCC_PLL1DIVR_PLL1Q_Pos) /*!< 0x007F0000 */ +#define RCC_PLL1DIVR_PLL1Q RCC_PLL1DIVR_PLL1Q_Msk +#define RCC_PLL1DIVR_PLL1Q_0 (0x01UL << RCC_PLL1DIVR_PLL1Q_Pos) /*!< 0x00010000 */ +#define RCC_PLL1DIVR_PLL1Q_1 (0x02UL << RCC_PLL1DIVR_PLL1Q_Pos) /*!< 0x00020000 */ +#define RCC_PLL1DIVR_PLL1Q_2 (0x04UL << RCC_PLL1DIVR_PLL1Q_Pos) /*!< 0x00040000 */ +#define RCC_PLL1DIVR_PLL1Q_3 (0x08UL << RCC_PLL1DIVR_PLL1Q_Pos) /*!< 0x00080000 */ +#define RCC_PLL1DIVR_PLL1Q_4 (0x10UL << RCC_PLL1DIVR_PLL1Q_Pos) /*!< 0x00100000 */ +#define RCC_PLL1DIVR_PLL1Q_5 (0x20UL << RCC_PLL1DIVR_PLL1Q_Pos) /*!< 0x00200020 */ +#define RCC_PLL1DIVR_PLL1Q_6 (0x40UL << RCC_PLL1DIVR_PLL1Q_Pos) /*!< 0x00400000 */ +#define RCC_PLL1DIVR_PLL1R_Pos (24U) +#define RCC_PLL1DIVR_PLL1R_Msk (0x7FUL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x7F000000 */ +#define RCC_PLL1DIVR_PLL1R RCC_PLL1DIVR_PLL1R_Msk +#define RCC_PLL1DIVR_PLL1R_0 (0x01UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x01000000 */ +#define RCC_PLL1DIVR_PLL1R_1 (0x02UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x02000000 */ +#define RCC_PLL1DIVR_PLL1R_2 (0x04UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x04000000 */ +#define RCC_PLL1DIVR_PLL1R_3 (0x08UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x08000000 */ +#define RCC_PLL1DIVR_PLL1R_4 (0x10UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x10000000 */ +#define RCC_PLL1DIVR_PLL1R_5 (0x20UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x20000000 */ +#define RCC_PLL1DIVR_PLL1R_6 (0x40UL << RCC_PLL1DIVR_PLL1R_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for RCC_PLL1FRACR register ***************/ +#define RCC_PLL1FRACR_PLL1FRACN_Pos (3U) +#define RCC_PLL1FRACR_PLL1FRACN_Msk (0x1FFFUL << RCC_PLL1FRACR_PLL1FRACN_Pos) /*!< 0x0000FFF8 */ +#define RCC_PLL1FRACR_PLL1FRACN RCC_PLL1FRACR_PLL1FRACN_Msk + +/******************** Bit definition for RCC_CIER register ******************/ +#define RCC_CIER_LSI1RDYIE_Pos (0U) +#define RCC_CIER_LSI1RDYIE_Msk (0x1UL << RCC_CIER_LSI1RDYIE_Pos) /*!< 0x00000001 */ +#define RCC_CIER_LSI1RDYIE RCC_CIER_LSI1RDYIE_Msk +#define RCC_CIER_LSERDYIE_Pos (1U) +#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ +#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk +#define RCC_CIER_HSIRDYIE_Pos (3U) +#define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000008 */ +#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk +#define RCC_CIER_HSERDYIE_Pos (4U) +#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000010 */ +#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk +#define RCC_CIER_PLL1RDYIE_Pos (6U) +#define RCC_CIER_PLL1RDYIE_Msk (0x1UL << RCC_CIER_PLL1RDYIE_Pos) /*!< 0x00000040 */ +#define RCC_CIER_PLL1RDYIE RCC_CIER_PLL1RDYIE_Msk +#define RCC_CIER_LSI2RDYIE_Pos (16U) +#define RCC_CIER_LSI2RDYIE_Msk (0x1UL << RCC_CIER_LSI2RDYIE_Pos) /*!< 0x00010000 */ +#define RCC_CIER_LSI2RDYIE RCC_CIER_LSI2RDYIE_Msk + +/******************** Bit definition for RCC_CIFR register ****************/ +#define RCC_CIFR_LSI1RDYF_Pos (0U) +#define RCC_CIFR_LSI1RDYF_Msk (0x1UL << RCC_CIFR_LSI1RDYF_Pos) /*!< 0x00000001 */ +#define RCC_CIFR_LSI1RDYF RCC_CIFR_LSI1RDYF_Msk +#define RCC_CIFR_LSERDYF_Pos (1U) +#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ +#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk +#define RCC_CIFR_HSIRDYF_Pos (3U) +#define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000008 */ +#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk +#define RCC_CIFR_HSERDYF_Pos (4U) +#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000010 */ +#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk +#define RCC_CIFR_PLL1RDYF_Pos (6U) +#define RCC_CIFR_PLL1RDYF_Msk (0x1UL << RCC_CIFR_PLL1RDYF_Pos) /*!< 0x00000040 */ +#define RCC_CIFR_PLL1RDYF RCC_CIFR_PLL1RDYF_Msk +#define RCC_CIFR_HSECSSF_Pos (10U) +#define RCC_CIFR_HSECSSF_Msk (0x1UL << RCC_CIFR_HSECSSF_Pos) /*!< 0x00000400 */ +#define RCC_CIFR_HSECSSF RCC_CIFR_HSECSSF_Msk +#define RCC_CIFR_LSI2RDYF_Pos (16U) +#define RCC_CIFR_LSI2RDYF_Msk (0x1UL << RCC_CIFR_LSI2RDYF_Pos) /*!< 0x00010000 */ +#define RCC_CIFR_LSI2RDYF RCC_CIFR_LSI2RDYF_Msk + +/******************** Bit definition for RCC_CICR register ****************/ +#define RCC_CICR_LSI1RDYC_Pos (0U) +#define RCC_CICR_LSI1RDYC_Msk (0x1UL << RCC_CICR_LSI1RDYC_Pos) /*!< 0x00000001 */ +#define RCC_CICR_LSI1RDYC RCC_CICR_LSI1RDYC_Msk +#define RCC_CICR_LSERDYC_Pos (1U) +#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */ +#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk +#define RCC_CICR_HSIRDYC_Pos (3U) +#define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000008 */ +#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk +#define RCC_CICR_HSERDYC_Pos (4U) +#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000010 */ +#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk +#define RCC_CICR_PLL1RDYC_Pos (6U) +#define RCC_CICR_PLL1RDYC_Msk (0x1UL << RCC_CICR_PLL1RDYC_Pos) /*!< 0x00000040 */ +#define RCC_CICR_PLL1RDYC RCC_CICR_PLL1RDYC_Msk +#define RCC_CICR_HSECSSC_Pos (10U) +#define RCC_CICR_HSECSSC_Msk (0x1UL << RCC_CICR_HSECSSC_Pos) /*!< 0x00000400 */ +#define RCC_CICR_HSECSSC RCC_CICR_HSECSSC_Msk +#define RCC_CICR_LSI2RDYC_Pos (16U) +#define RCC_CICR_LSI2RDYC_Msk (0x1UL << RCC_CICR_LSI2RDYC_Pos) /*!< 0x00010000 */ +#define RCC_CICR_LSI2RDYC RCC_CICR_LSI2RDYC_Msk + +/******************** Bit definition for RCC_AHB1RSTR register **************/ +#define RCC_AHB1RSTR_GPDMA1RST_Pos (0U) +#define RCC_AHB1RSTR_GPDMA1RST_Msk (0x1UL << RCC_AHB1RSTR_GPDMA1RST_Pos) /*!< 0x00000001 */ +#define RCC_AHB1RSTR_GPDMA1RST RCC_AHB1RSTR_GPDMA1RST_Msk +#define RCC_AHB1RSTR_CRCRST_Pos (12U) +#define RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */ +#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk +#define RCC_AHB1RSTR_TSCRST_Pos (16U) +#define RCC_AHB1RSTR_TSCRST_Msk (0x1UL << RCC_AHB1RSTR_TSCRST_Pos) /*!< 0x00010000 */ +#define RCC_AHB1RSTR_TSCRST RCC_AHB1RSTR_TSCRST_Msk + +/******************** Bit definition for RCC_AHB2RSTR register **************/ +#define RCC_AHB2RSTR_GPIOARST_Pos (0U) +#define RCC_AHB2RSTR_GPIOARST_Msk (0x1UL << RCC_AHB2RSTR_GPIOARST_Pos) /*!< 0x00000001 */ +#define RCC_AHB2RSTR_GPIOARST RCC_AHB2RSTR_GPIOARST_Msk +#define RCC_AHB2RSTR_GPIOBRST_Pos (1U) +#define RCC_AHB2RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOBRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB2RSTR_GPIOBRST RCC_AHB2RSTR_GPIOBRST_Msk +#define RCC_AHB2RSTR_GPIOCRST_Pos (2U) +#define RCC_AHB2RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOCRST_Pos) /*!< 0x00000004 */ +#define RCC_AHB2RSTR_GPIOCRST RCC_AHB2RSTR_GPIOCRST_Msk +#define RCC_AHB2RSTR_GPIOHRST_Pos (7U) +#define RCC_AHB2RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOHRST_Pos) /*!< 0x00000080 */ +#define RCC_AHB2RSTR_GPIOHRST RCC_AHB2RSTR_GPIOHRST_Msk +#define RCC_AHB2RSTR_AESRST_Pos (16U) +#define RCC_AHB2RSTR_AESRST_Msk (0x1UL << RCC_AHB2RSTR_AESRST_Pos) /*!< 0x00010000 */ +#define RCC_AHB2RSTR_AESRST RCC_AHB2RSTR_AESRST_Msk +#define RCC_AHB2RSTR_HASHRST_Pos (17U) +#define RCC_AHB2RSTR_HASHRST_Msk (0x1UL << RCC_AHB2RSTR_HASHRST_Pos) /*!< 0x00020000 */ +#define RCC_AHB2RSTR_HASHRST RCC_AHB2RSTR_HASHRST_Msk +#define RCC_AHB2RSTR_RNGRST_Pos (18U) +#define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00040000 */ +#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk +#define RCC_AHB2RSTR_SAESRST_Pos (19U) +#define RCC_AHB2RSTR_SAESRST_Msk (0x1UL << RCC_AHB2RSTR_SAESRST_Pos) /*!< 0x00080000 */ +#define RCC_AHB2RSTR_SAESRST RCC_AHB2RSTR_SAESRST_Msk +#define RCC_AHB2RSTR_HSEMRST_Pos (20U) +#define RCC_AHB2RSTR_HSEMRST_Msk (0x1UL << RCC_AHB2RSTR_HSEMRST_Pos) /*!< 0x00100000 */ +#define RCC_AHB2RSTR_HSEMRST RCC_AHB2RSTR_HSEMRST_Msk +#define RCC_AHB2RSTR_PKARST_Pos (21U) +#define RCC_AHB2RSTR_PKARST_Msk (0x1UL << RCC_AHB2RSTR_PKARST_Pos) /*!< 0x00200000 */ +#define RCC_AHB2RSTR_PKARST RCC_AHB2RSTR_PKARST_Msk + +/******************** Bit definition for RCC_AHB4RSTR register **************/ +#define RCC_AHB4RSTR_ADC4RST_Pos (5U) +#define RCC_AHB4RSTR_ADC4RST_Msk (0x1UL << RCC_AHB4RSTR_ADC4RST_Pos) /*!< 0x00000020 */ +#define RCC_AHB4RSTR_ADC4RST RCC_AHB4RSTR_ADC4RST_Msk + +/******************** Bit definition for RCC_AHB5RSTR register **************/ +#define RCC_AHB5RSTR_RADIORST_Pos (0U) +#define RCC_AHB5RSTR_RADIORST_Msk (0x1UL << RCC_AHB5RSTR_RADIORST_Pos) /*!< 0x00000001 */ +#define RCC_AHB5RSTR_RADIORST RCC_AHB5RSTR_RADIORST_Msk +#define RCC_AHB5RSTR_PTACONVRST_Pos (1U) +#define RCC_AHB5RSTR_PTACONVRST_Msk (0x1UL << RCC_AHB5RSTR_PTACONVRST_Pos) /*!< 0x00000002 */ +#define RCC_AHB5RSTR_PTACONVRST RCC_AHB5RSTR_PTACONVRST_Msk + +/******************** Bit definition for RCC_APB1RSTR1 register **************/ +#define RCC_APB1RSTR1_TIM2RST_Pos (0U) +#define RCC_APB1RSTR1_TIM2RST_Msk (0x1UL << RCC_APB1RSTR1_TIM2RST_Pos) /*!< 0x00000001 */ +#define RCC_APB1RSTR1_TIM2RST RCC_APB1RSTR1_TIM2RST_Msk +#define RCC_APB1RSTR1_TIM3RST_Pos (1U) +#define RCC_APB1RSTR1_TIM3RST_Msk (0x1UL << RCC_APB1RSTR1_TIM3RST_Pos) /*!< 0x00000002 */ +#define RCC_APB1RSTR1_TIM3RST RCC_APB1RSTR1_TIM3RST_Msk +#define RCC_APB1RSTR1_USART2RST_Pos (17U) +#define RCC_APB1RSTR1_USART2RST_Msk (0x1UL << RCC_APB1RSTR1_USART2RST_Pos) /*!< 0x00020000 */ +#define RCC_APB1RSTR1_USART2RST RCC_APB1RSTR1_USART2RST_Msk +#define RCC_APB1RSTR1_I2C1RST_Pos (21U) +#define RCC_APB1RSTR1_I2C1RST_Msk (0x1UL << RCC_APB1RSTR1_I2C1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB1RSTR1_I2C1RST RCC_APB1RSTR1_I2C1RST_Msk + +/******************** Bit definition for RCC_APB1RSTR2 register **************/ +#define RCC_APB1RSTR2_LPTIM2RST_Pos (5U) +#define RCC_APB1RSTR2_LPTIM2RST_Msk (0x1UL << RCC_APB1RSTR2_LPTIM2RST_Pos) /*!< 0x00000020 */ +#define RCC_APB1RSTR2_LPTIM2RST RCC_APB1RSTR2_LPTIM2RST_Msk + +/******************** Bit definition for RCC_APB2RSTR register **************/ +#define RCC_APB2RSTR_TIM1RST_Pos (11U) +#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */ +#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk +#define RCC_APB2RSTR_SPI1RST_Pos (12U) +#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ +#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk +#define RCC_APB2RSTR_USART1RST_Pos (14U) +#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ +#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk +#define RCC_APB2RSTR_TIM16RST_Pos (17U) +#define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */ +#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk +#define RCC_APB2RSTR_TIM17RST_Pos (18U) +#define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */ +#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk +#define RCC_APB2RSTR_SAI1RST_Pos (21U) +#define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00200000 */ +#define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk + +/******************** Bit definition for RCC_APB7RSTR register **************/ +#define RCC_APB7RSTR_SYSCFGRST_Pos (1U) +#define RCC_APB7RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB7RSTR_SYSCFGRST_Pos) /*!< 0x00000002 */ +#define RCC_APB7RSTR_SYSCFGRST RCC_APB7RSTR_SYSCFGRST_Msk +#define RCC_APB7RSTR_SPI3RST_Pos (5U) +#define RCC_APB7RSTR_SPI3RST_Msk (0x1UL << RCC_APB7RSTR_SPI3RST_Pos) /*!< 0x00000020 */ +#define RCC_APB7RSTR_SPI3RST RCC_APB7RSTR_SPI3RST_Msk +#define RCC_APB7RSTR_LPUART1RST_Pos (6U) +#define RCC_APB7RSTR_LPUART1RST_Msk (0x1UL << RCC_APB7RSTR_LPUART1RST_Pos) /*!< 0x00000040 */ +#define RCC_APB7RSTR_LPUART1RST RCC_APB7RSTR_LPUART1RST_Msk +#define RCC_APB7RSTR_I2C3RST_Pos (7U) +#define RCC_APB7RSTR_I2C3RST_Msk (0x1UL << RCC_APB7RSTR_I2C3RST_Pos) /*!< 0x00000080 */ +#define RCC_APB7RSTR_I2C3RST RCC_APB7RSTR_I2C3RST_Msk +#define RCC_APB7RSTR_LPTIM1RST_Pos (11U) +#define RCC_APB7RSTR_LPTIM1RST_Msk (0x1UL << RCC_APB7RSTR_LPTIM1RST_Pos) /*!< 0x00000800 */ +#define RCC_APB7RSTR_LPTIM1RST RCC_APB7RSTR_LPTIM1RST_Msk +#define RCC_APB7RSTR_COMPRST_Pos (15U) +#define RCC_APB7RSTR_COMPRST_Msk (0x1UL << RCC_APB7RSTR_COMPRST_Pos) /*!< 0x00008000 */ +#define RCC_APB7RSTR_COMPRST RCC_APB7RSTR_COMPRST_Msk + +/******************** Bit definition for RCC_AHB1ENR register **************/ +#define RCC_AHB1ENR_GPDMA1EN_Pos (0U) +#define RCC_AHB1ENR_GPDMA1EN_Msk (0x1UL << RCC_AHB1ENR_GPDMA1EN_Pos) /*!< 0x00000001 */ +#define RCC_AHB1ENR_GPDMA1EN RCC_AHB1ENR_GPDMA1EN_Msk +#define RCC_AHB1ENR_FLASHEN_Pos (8U) +#define RCC_AHB1ENR_FLASHEN_Msk (0x1UL << RCC_AHB1ENR_FLASHEN_Pos) /*!< 0x00000100 */ +#define RCC_AHB1ENR_FLASHEN RCC_AHB1ENR_FLASHEN_Msk +#define RCC_AHB1ENR_CRCEN_Pos (12U) +#define RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */ +#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk +#define RCC_AHB1ENR_TSCEN_Pos (16U) +#define RCC_AHB1ENR_TSCEN_Msk (0x1UL << RCC_AHB1ENR_TSCEN_Pos) /*!< 0x00010000 */ +#define RCC_AHB1ENR_TSCEN RCC_AHB1ENR_TSCEN_Msk +#define RCC_AHB1ENR_RAMCFGEN_Pos (17U) +#define RCC_AHB1ENR_RAMCFGEN_Msk (0x1UL << RCC_AHB1ENR_RAMCFGEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB1ENR_RAMCFGEN RCC_AHB1ENR_RAMCFGEN_Msk +#define RCC_AHB1ENR_GTZC1EN_Pos (24U) +#define RCC_AHB1ENR_GTZC1EN_Msk (0x1UL << RCC_AHB1ENR_GTZC1EN_Pos) /*!< 0x01000000 */ +#define RCC_AHB1ENR_GTZC1EN RCC_AHB1ENR_GTZC1EN_Msk +#define RCC_AHB1ENR_SRAM1EN_Pos (31U) +#define RCC_AHB1ENR_SRAM1EN_Msk (0x1UL << RCC_AHB1ENR_SRAM1EN_Pos) /*!< 0x80000000 */ +#define RCC_AHB1ENR_SRAM1EN RCC_AHB1ENR_SRAM1EN_Msk + +/******************** Bit definition for RCC_AHB2ENR register **************/ +#define RCC_AHB2ENR_GPIOAEN_Pos (0U) +#define RCC_AHB2ENR_GPIOAEN_Msk (0x1UL << RCC_AHB2ENR_GPIOAEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB2ENR_GPIOAEN RCC_AHB2ENR_GPIOAEN_Msk +#define RCC_AHB2ENR_GPIOBEN_Pos (1U) +#define RCC_AHB2ENR_GPIOBEN_Msk (0x1UL << RCC_AHB2ENR_GPIOBEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB2ENR_GPIOBEN RCC_AHB2ENR_GPIOBEN_Msk +#define RCC_AHB2ENR_GPIOCEN_Pos (2U) +#define RCC_AHB2ENR_GPIOCEN_Msk (0x1UL << RCC_AHB2ENR_GPIOCEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB2ENR_GPIOCEN RCC_AHB2ENR_GPIOCEN_Msk +#define RCC_AHB2ENR_GPIOHEN_Pos (7U) +#define RCC_AHB2ENR_GPIOHEN_Msk (0x1UL << RCC_AHB2ENR_GPIOHEN_Pos) /*!< 0x00000080 */ +#define RCC_AHB2ENR_GPIOHEN RCC_AHB2ENR_GPIOHEN_Msk +#define RCC_AHB2ENR_AESEN_Pos (16U) +#define RCC_AHB2ENR_AESEN_Msk (0x1UL << RCC_AHB2ENR_AESEN_Pos) /*!< 0x00010000 */ +#define RCC_AHB2ENR_AESEN RCC_AHB2ENR_AESEN_Msk +#define RCC_AHB2ENR_HASHEN_Pos (17U) +#define RCC_AHB2ENR_HASHEN_Msk (0x1UL << RCC_AHB2ENR_HASHEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB2ENR_HASHEN RCC_AHB2ENR_HASHEN_Msk +#define RCC_AHB2ENR_RNGEN_Pos (18U) +#define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00040000 */ +#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk +#define RCC_AHB2ENR_SAESEN_Pos (19U) +#define RCC_AHB2ENR_SAESEN_Msk (0x1UL << RCC_AHB2ENR_SAESEN_Pos) /*!< 0x00080000 */ +#define RCC_AHB2ENR_SAESEN RCC_AHB2ENR_SAESEN_Msk +#define RCC_AHB2ENR_HSEMEN_Pos (20U) +#define RCC_AHB2ENR_HSEMEN_Msk (0x1UL << RCC_AHB2ENR_HSEMEN_Pos) /*!< 0x00100000 */ +#define RCC_AHB2ENR_HSEMEN RCC_AHB2ENR_HSEMEN_Msk +#define RCC_AHB2ENR_PKAEN_Pos (21U) +#define RCC_AHB2ENR_PKAEN_Msk (0x1UL << RCC_AHB2ENR_PKAEN_Pos) /*!< 0x00200000 */ +#define RCC_AHB2ENR_PKAEN RCC_AHB2ENR_PKAEN_Msk +#define RCC_AHB2ENR_SRAM2EN_Pos (30U) +#define RCC_AHB2ENR_SRAM2EN_Msk (0x1UL << RCC_AHB2ENR_SRAM2EN_Pos) /*!< 0x40000000 */ +#define RCC_AHB2ENR_SRAM2EN RCC_AHB2ENR_SRAM2EN_Msk + +/******************** Bit definition for RCC_AHB4ENR register **************/ +#define RCC_AHB4ENR_PWREN_Pos (2U) +#define RCC_AHB4ENR_PWREN_Msk (0x1UL << RCC_AHB4ENR_PWREN_Pos) /*!< 0x00000004 */ +#define RCC_AHB4ENR_PWREN RCC_AHB4ENR_PWREN_Msk +#define RCC_AHB4ENR_ADC4EN_Pos (5U) +#define RCC_AHB4ENR_ADC4EN_Msk (0x1UL << RCC_AHB4ENR_ADC4EN_Pos) /*!< 0x00000020 */ +#define RCC_AHB4ENR_ADC4EN RCC_AHB4ENR_ADC4EN_Msk + +/******************** Bit definition for RCC_AHB5ENR register **************/ +#define RCC_AHB5ENR_RADIOEN_Pos (0U) +#define RCC_AHB5ENR_RADIOEN_Msk (0x1UL << RCC_AHB5ENR_RADIOEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB5ENR_RADIOEN RCC_AHB5ENR_RADIOEN_Msk +#define RCC_AHB5ENR_PTACONVEN_Pos (1U) +#define RCC_AHB5ENR_PTACONVEN_Msk (0x1UL << RCC_AHB5ENR_PTACONVEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB5ENR_PTACONVEN RCC_AHB5ENR_PTACONVEN_Msk + +/******************** Bit definition for RCC_APB1ENR1 register **************/ +#define RCC_APB1ENR1_TIM2EN_Pos (0U) +#define RCC_APB1ENR1_TIM2EN_Msk (0x1UL << RCC_APB1ENR1_TIM2EN_Pos) /*!< 0x00000001 */ +#define RCC_APB1ENR1_TIM2EN RCC_APB1ENR1_TIM2EN_Msk +#define RCC_APB1ENR1_TIM3EN_Pos (1U) +#define RCC_APB1ENR1_TIM3EN_Msk (0x1UL << RCC_APB1ENR1_TIM3EN_Pos) /*!< 0x00000002 */ +#define RCC_APB1ENR1_TIM3EN RCC_APB1ENR1_TIM3EN_Msk +#define RCC_APB1ENR1_WWDGEN_Pos (11U) +#define RCC_APB1ENR1_WWDGEN_Msk (0x1UL << RCC_APB1ENR1_WWDGEN_Pos) /*!< 0x00000800 */ +#define RCC_APB1ENR1_WWDGEN RCC_APB1ENR1_WWDGEN_Msk +#define RCC_APB1ENR1_USART2EN_Pos (17U) +#define RCC_APB1ENR1_USART2EN_Msk (0x1UL << RCC_APB1ENR1_USART2EN_Pos) /*!< 0x00020000 */ +#define RCC_APB1ENR1_USART2EN RCC_APB1ENR1_USART2EN_Msk +#define RCC_APB1ENR1_I2C1EN_Pos (21U) +#define RCC_APB1ENR1_I2C1EN_Msk (0x1UL << RCC_APB1ENR1_I2C1EN_Pos) /*!< 0x00200000 */ +#define RCC_APB1ENR1_I2C1EN RCC_APB1ENR1_I2C1EN_Msk + +/******************** Bit definition for RCC_APB1ENR2 register **************/ +#define RCC_APB1ENR2_LPTIM2EN_Pos (5U) +#define RCC_APB1ENR2_LPTIM2EN_Msk (0x1UL << RCC_APB1ENR2_LPTIM2EN_Pos) /*!< 0x00000020 */ +#define RCC_APB1ENR2_LPTIM2EN RCC_APB1ENR2_LPTIM2EN_Msk + +/******************** Bit definition for RCC_APB2ENR register **************/ +#define RCC_APB2ENR_TIM1EN_Pos (11U) +#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */ +#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk +#define RCC_APB2ENR_SPI1EN_Pos (12U) +#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ +#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk +#define RCC_APB2ENR_USART1EN_Pos (14U) +#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */ +#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk +#define RCC_APB2ENR_TIM16EN_Pos (17U) +#define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */ +#define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk +#define RCC_APB2ENR_TIM17EN_Pos (18U) +#define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */ +#define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk +#define RCC_APB2ENR_SAI1EN_Pos (21U) +#define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00200000 */ +#define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk + +/******************** Bit definition for RCC_APB7ENR register **************/ +#define RCC_APB7ENR_SYSCFGEN_Pos (1U) +#define RCC_APB7ENR_SYSCFGEN_Msk (0x1UL << RCC_APB7ENR_SYSCFGEN_Pos) /*!< 0x00000002 */ +#define RCC_APB7ENR_SYSCFGEN RCC_APB7ENR_SYSCFGEN_Msk +#define RCC_APB7ENR_SPI3EN_Pos (5U) +#define RCC_APB7ENR_SPI3EN_Msk (0x1UL << RCC_APB7ENR_SPI3EN_Pos) /*!< 0x00000020 */ +#define RCC_APB7ENR_SPI3EN RCC_APB7ENR_SPI3EN_Msk +#define RCC_APB7ENR_LPUART1EN_Pos (6U) +#define RCC_APB7ENR_LPUART1EN_Msk (0x1UL << RCC_APB7ENR_LPUART1EN_Pos) /*!< 0x00000040 */ +#define RCC_APB7ENR_LPUART1EN RCC_APB7ENR_LPUART1EN_Msk +#define RCC_APB7ENR_I2C3EN_Pos (7U) +#define RCC_APB7ENR_I2C3EN_Msk (0x1UL << RCC_APB7ENR_I2C3EN_Pos) /*!< 0x00000080 */ +#define RCC_APB7ENR_I2C3EN RCC_APB7ENR_I2C3EN_Msk +#define RCC_APB7ENR_LPTIM1EN_Pos (11U) +#define RCC_APB7ENR_LPTIM1EN_Msk (0x1UL << RCC_APB7ENR_LPTIM1EN_Pos) /*!< 0x00000800 */ +#define RCC_APB7ENR_LPTIM1EN RCC_APB7ENR_LPTIM1EN_Msk +#define RCC_APB7ENR_COMPEN_Pos (15U) +#define RCC_APB7ENR_COMPEN_Msk (0x1UL << RCC_APB7ENR_COMPEN_Pos) /*!< 0x00008000 */ +#define RCC_APB7ENR_COMPEN RCC_APB7ENR_COMPEN_Msk +#define RCC_APB7ENR_RTCAPBEN_Pos (21U) +#define RCC_APB7ENR_RTCAPBEN_Msk (0x1UL << RCC_APB7ENR_RTCAPBEN_Pos) /*!< 0x00200000 */ +#define RCC_APB7ENR_RTCAPBEN RCC_APB7ENR_RTCAPBEN_Msk + +/******************** Bit definition for RCC_AHB1SMENR register **************/ +#define RCC_AHB1SMENR_GPDMA1SMEN_Pos (0U) +#define RCC_AHB1SMENR_GPDMA1SMEN_Msk (0x1UL << RCC_AHB1SMENR_GPDMA1SMEN_Pos) /*!< 0x00000000*/ +#define RCC_AHB1SMENR_GPDMA1SMEN RCC_AHB1SMENR_GPDMA1SMEN_Msk +#define RCC_AHB1SMENR_FLASHSMEN_Pos (8U) +#define RCC_AHB1SMENR_FLASHSMEN_Msk (0x1UL << RCC_AHB1SMENR_FLASHSMEN_Pos) /*!< 0x00000100 */ +#define RCC_AHB1SMENR_FLASHSMEN RCC_AHB1SMENR_FLASHSMEN_Msk +#define RCC_AHB1SMENR_CRCSMEN_Pos (12U) +#define RCC_AHB1SMENR_CRCSMEN_Msk (0x1UL << RCC_AHB1SMENR_CRCSMEN_Pos) /*!< 0x00001000 */ +#define RCC_AHB1SMENR_CRCSMEN RCC_AHB1SMENR_CRCSMEN_Msk +#define RCC_AHB1SMENR_TSCSMEN_Pos (16U) +#define RCC_AHB1SMENR_TSCSMEN_Msk (0x1UL << RCC_AHB1SMENR_TSCSMEN_Pos) /*!< 0x00010000 */ +#define RCC_AHB1SMENR_TSCSMEN RCC_AHB1SMENR_TSCSMEN_Msk +#define RCC_AHB1SMENR_RAMCFGSMEN_Pos (17U) +#define RCC_AHB1SMENR_RAMCFGSMEN_Msk (0x1UL << RCC_AHB1SMENR_RAMCFGSMEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB1SMENR_RAMCFGSMEN RCC_AHB1SMENR_RAMCFGSMEN_Msk +#define RCC_AHB1SMENR_GTZC1SMEN_Pos (24U) +#define RCC_AHB1SMENR_GTZC1SMEN_Msk (0x1UL << RCC_AHB1SMENR_GTZC1SMEN_Pos) /*!< 0x01000000 */ +#define RCC_AHB1SMENR_GTZC1SMEN RCC_AHB1SMENR_GTZC1SMEN_Msk +#define RCC_AHB1SMENR_ICACHESMEN_Pos (29U) +#define RCC_AHB1SMENR_ICACHESMEN_Msk (0x1UL << RCC_AHB1SMENR_ICACHESMEN_Pos) /*!< 0x20000000 */ +#define RCC_AHB1SMENR_ICACHESMEN RCC_AHB1SMENR_ICACHESMEN_Msk +#define RCC_AHB1SMENR_SRAM1SMEN_Pos (31U) +#define RCC_AHB1SMENR_SRAM1SMEN_Msk (0x1UL << RCC_AHB1SMENR_SRAM1SMEN_Pos) /*!< 0x80000000 */ +#define RCC_AHB1SMENR_SRAM1SMEN RCC_AHB1SMENR_SRAM1SMEN_Msk + +/******************** Bit definition for RCC_AHB2SMENR register **************/ +#define RCC_AHB2SMENR_GPIOASMEN_Pos (0U) +#define RCC_AHB2SMENR_GPIOASMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOASMEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB2SMENR_GPIOASMEN RCC_AHB2SMENR_GPIOASMEN_Msk +#define RCC_AHB2SMENR_GPIOBSMEN_Pos (1U) +#define RCC_AHB2SMENR_GPIOBSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOBSMEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB2SMENR_GPIOBSMEN RCC_AHB2SMENR_GPIOBSMEN_Msk +#define RCC_AHB2SMENR_GPIOCSMEN_Pos (2U) +#define RCC_AHB2SMENR_GPIOCSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOCSMEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB2SMENR_GPIOCSMEN RCC_AHB2SMENR_GPIOCSMEN_Msk +#define RCC_AHB2SMENR_GPIOHSMEN_Pos (7U) +#define RCC_AHB2SMENR_GPIOHSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOHSMEN_Pos) /*!< 0x00000080 */ +#define RCC_AHB2SMENR_GPIOHSMEN RCC_AHB2SMENR_GPIOHSMEN_Msk +#define RCC_AHB2SMENR_AESSMEN_Pos (16U) +#define RCC_AHB2SMENR_AESSMEN_Msk (0x1UL << RCC_AHB2SMENR_AESSMEN_Pos) /*!< 0x00010000 */ +#define RCC_AHB2SMENR_AESSMEN RCC_AHB2SMENR_AESSMEN_Msk +#define RCC_AHB2SMENR_HASHSMEN_Pos (17U) +#define RCC_AHB2SMENR_HASHSMEN_Msk (0x1UL << RCC_AHB2SMENR_HASHSMEN_Pos) /*!< 0x00020000 */ +#define RCC_AHB2SMENR_HASHSMEN RCC_AHB2SMENR_HASHSMEN_Msk +#define RCC_AHB2SMENR_RNGSMEN_Pos (18U) +#define RCC_AHB2SMENR_RNGSMEN_Msk (0x1UL << RCC_AHB2SMENR_RNGSMEN_Pos) /*!< 0x00040000 */ +#define RCC_AHB2SMENR_RNGSMEN RCC_AHB2SMENR_RNGSMEN_Msk +#define RCC_AHB2SMENR_SAESSMEN_Pos (19U) +#define RCC_AHB2SMENR_SAESSMEN_Msk (0x1UL << RCC_AHB2SMENR_SAESSMEN_Pos) /*!< 0x00080000 */ +#define RCC_AHB2SMENR_SAESSMEN RCC_AHB2SMENR_SAESSMEN_Msk +#define RCC_AHB2SMENR_PKASMEN_Pos (21U) +#define RCC_AHB2SMENR_PKASMEN_Msk (0x1UL << RCC_AHB2SMENR_PKASMEN_Pos) /*!< 0x00200000 */ +#define RCC_AHB2SMENR_PKASMEN RCC_AHB2SMENR_PKASMEN_Msk +#define RCC_AHB2SMENR_SRAM2SMEN_Pos (30U) +#define RCC_AHB2SMENR_SRAM2SMEN_Msk (0x1UL << RCC_AHB2SMENR_SRAM2SMEN_Pos) /*!< 0x40000000 */ +#define RCC_AHB2SMENR_SRAM2SMEN RCC_AHB2SMENR_SRAM2SMEN_Msk + +/******************** Bit definition for RCC_AHB4SMENR register **************/ +#define RCC_AHB4SMENR_PWRSMEN_Pos (2U) +#define RCC_AHB4SMENR_PWRSMEN_Msk (0x1UL << RCC_AHB4SMENR_PWRSMEN_Pos) /*!< 0x00000004 */ +#define RCC_AHB4SMENR_PWRSMEN RCC_AHB4SMENR_PWRSMEN_Msk +#define RCC_AHB4SMENR_ADC4SMEN_Pos (5U) +#define RCC_AHB4SMENR_ADC4SMEN_Msk (0x1UL << RCC_AHB4SMENR_ADC4SMEN_Pos) /*!< 0x00000040 */ +#define RCC_AHB4SMENR_ADC4SMEN RCC_AHB4SMENR_ADC4SMEN_Msk + +/******************** Bit definition for RCC_AHB5SMENR register **************/ +#define RCC_AHB5SMENR_RADIOSMEN_Pos (0U) +#define RCC_AHB5SMENR_RADIOSMEN_Msk (0x1UL << RCC_AHB5SMENR_RADIOSMEN_Pos) /*!< 0x00000001 */ +#define RCC_AHB5SMENR_RADIOSMEN RCC_AHB5SMENR_RADIOSMEN_Msk +#define RCC_AHB5SMENR_PTACONVSMEN_Pos (1U) +#define RCC_AHB5SMENR_PTACONVSMEN_Msk (0x1UL << RCC_AHB5SMENR_PTACONVSMEN_Pos) /*!< 0x00000002 */ +#define RCC_AHB5SMENR_PTACONVSMEN RCC_AHB5SMENR_PTACONVSMEN_Msk + +/******************** Bit definition for RCC_APB1SMENR1 register **************/ +#define RCC_APB1SMENR1_TIM2SMEN_Pos (0U) +#define RCC_APB1SMENR1_TIM2SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM2SMEN_Pos) /*!< 0x00000001 */ +#define RCC_APB1SMENR1_TIM2SMEN RCC_APB1SMENR1_TIM2SMEN_Msk +#define RCC_APB1SMENR1_TIM3SMEN_Pos (1U) +#define RCC_APB1SMENR1_TIM3SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM3SMEN_Pos) /*!< 0x00000002 */ +#define RCC_APB1SMENR1_TIM3SMEN RCC_APB1SMENR1_TIM3SMEN_Msk +#define RCC_APB1SMENR1_WWDGSMEN_Pos (11U) +#define RCC_APB1SMENR1_WWDGSMEN_Msk (0x1UL << RCC_APB1SMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */ +#define RCC_APB1SMENR1_WWDGSMEN RCC_APB1SMENR1_WWDGSMEN_Msk +#define RCC_APB1SMENR1_USART2SMEN_Pos (17U) +#define RCC_APB1SMENR1_USART2SMEN_Msk (0x1UL << RCC_APB1SMENR1_USART2SMEN_Pos) /*!< 0x00020000 */ +#define RCC_APB1SMENR1_USART2SMEN RCC_APB1SMENR1_USART2SMEN_Msk +#define RCC_APB1SMENR1_I2C1SMEN_Pos (21U) +#define RCC_APB1SMENR1_I2C1SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C1SMEN_Pos) /*!< 0x00200000 */ +#define RCC_APB1SMENR1_I2C1SMEN RCC_APB1SMENR1_I2C1SMEN_Msk + +/******************** Bit definition for RCC_APB1SMENR2 register **************/ +#define RCC_APB1SMENR2_LPTIM2SMEN_Pos (5U) +#define RCC_APB1SMENR2_LPTIM2SMEN_Msk (0x1UL << RCC_APB1SMENR2_LPTIM2SMEN_Pos) /*!< 0x00000020 */ +#define RCC_APB1SMENR2_LPTIM2SMEN RCC_APB1SMENR2_LPTIM2SMEN_Msk + +/******************** Bit definition for RCC_APB2SMENR register **************/ +#define RCC_APB2SMENR_TIM1SMEN_Pos (11U) +#define RCC_APB2SMENR_TIM1SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM1SMEN_Pos) /*!< 0x00000800 */ +#define RCC_APB2SMENR_TIM1SMEN RCC_APB2SMENR_TIM1SMEN_Msk +#define RCC_APB2SMENR_SPI1SMEN_Pos (12U) +#define RCC_APB2SMENR_SPI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */ +#define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk +#define RCC_APB2SMENR_USART1SMEN_Pos (14U) +#define RCC_APB2SMENR_USART1SMEN_Msk (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */ +#define RCC_APB2SMENR_USART1SMEN RCC_APB2SMENR_USART1SMEN_Msk +#define RCC_APB2SMENR_TIM16SMEN_Pos (17U) +#define RCC_APB2SMENR_TIM16SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM16SMEN_Pos) /*!< 0x00020000 */ +#define RCC_APB2SMENR_TIM16SMEN RCC_APB2SMENR_TIM16SMEN_Msk +#define RCC_APB2SMENR_TIM17SMEN_Pos (18U) +#define RCC_APB2SMENR_TIM17SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM17SMEN_Pos) /*!< 0x00040000 */ +#define RCC_APB2SMENR_TIM17SMEN RCC_APB2SMENR_TIM17SMEN_Msk +#define RCC_APB2SMENR_SAI1SMEN_Pos (21U) +#define RCC_APB2SMENR_SAI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SAI1SMEN_Pos) /*!< 0x00200000 */ +#define RCC_APB2SMENR_SAI1SMEN RCC_APB2SMENR_SAI1SMEN_Msk + +/******************** Bit definition for RCC_APB7SMENR register **************/ +#define RCC_APB7SMENR_SYSCFGSMEN_Pos (1U) +#define RCC_APB7SMENR_SYSCFGSMEN_Msk (0x1UL << RCC_APB7SMENR_SYSCFGSMEN_Pos) /*!< 0x00000002 */ +#define RCC_APB7SMENR_SYSCFGSMEN RCC_APB7SMENR_SYSCFGSMEN_Msk +#define RCC_APB7SMENR_SPI3SMEN_Pos (5U) +#define RCC_APB7SMENR_SPI3SMEN_Msk (0x1UL << RCC_APB7SMENR_SPI3SMEN_Pos) /*!< 0x00000020 */ +#define RCC_APB7SMENR_SPI3SMEN RCC_APB7SMENR_SPI3SMEN_Msk +#define RCC_APB7SMENR_LPUART1SMEN_Pos (6U) +#define RCC_APB7SMENR_LPUART1SMEN_Msk (0x1UL << RCC_APB7SMENR_LPUART1SMEN_Pos) /*!< 0x00000040 */ +#define RCC_APB7SMENR_LPUART1SMEN RCC_APB7SMENR_LPUART1SMEN_Msk +#define RCC_APB7SMENR_I2C3SMEN_Pos (7U) +#define RCC_APB7SMENR_I2C3SMEN_Msk (0x1UL << RCC_APB7SMENR_I2C3SMEN_Pos) /*!< 0x00000080 */ +#define RCC_APB7SMENR_I2C3SMEN RCC_APB7SMENR_I2C3SMEN_Msk +#define RCC_APB7SMENR_LPTIM1SMEN_Pos (11U) +#define RCC_APB7SMENR_LPTIM1SMEN_Msk (0x1UL << RCC_APB7SMENR_LPTIM1SMEN_Pos) /*!< 0x00000800 */ +#define RCC_APB7SMENR_LPTIM1SMEN RCC_APB7SMENR_LPTIM1SMEN_Msk +#define RCC_APB7SMENR_COMPSMEN_Pos (15U) +#define RCC_APB7SMENR_COMPSMEN_Msk (0x1UL << RCC_APB7SMENR_COMPSMEN_Pos) /*!< 0x00008000 */ +#define RCC_APB7SMENR_COMPSMEN RCC_APB7SMENR_COMPSMEN_Msk +#define RCC_APB7SMENR_RTCAPBSMEN_Pos (21U) +#define RCC_APB7SMENR_RTCAPBSMEN_Msk (0x1UL << RCC_APB7SMENR_RTCAPBSMEN_Pos) /*!< 0x00200000 */ +#define RCC_APB7SMENR_RTCAPBSMEN RCC_APB7SMENR_RTCAPBSMEN_Msk + +/******************** Bit definition for RCC_CCIPR1 register ******************/ +#define RCC_CCIPR1_USART1SEL_Pos (0U) +#define RCC_CCIPR1_USART1SEL_Msk (0x3UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000003 */ +#define RCC_CCIPR1_USART1SEL RCC_CCIPR1_USART1SEL_Msk +#define RCC_CCIPR1_USART1SEL_0 (0x1UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR1_USART1SEL_1 (0x2UL << RCC_CCIPR1_USART1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR1_USART2SEL_Pos (2U) +#define RCC_CCIPR1_USART2SEL_Msk (0x3UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x0000000C */ +#define RCC_CCIPR1_USART2SEL RCC_CCIPR1_USART2SEL_Msk +#define RCC_CCIPR1_USART2SEL_0 (0x1UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x00000004 */ +#define RCC_CCIPR1_USART2SEL_1 (0x2UL << RCC_CCIPR1_USART2SEL_Pos) /*!< 0x00000008 */ +#define RCC_CCIPR1_I2C1SEL_Pos (10U) +#define RCC_CCIPR1_I2C1SEL_Msk (0x3UL << RCC_CCIPR1_I2C1SEL_Pos) /*!< 0x00000C00 */ +#define RCC_CCIPR1_I2C1SEL RCC_CCIPR1_I2C1SEL_Msk +#define RCC_CCIPR1_I2C1SEL_0 (0x1UL << RCC_CCIPR1_I2C1SEL_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR1_I2C1SEL_1 (0x2UL << RCC_CCIPR1_I2C1SEL_Pos) /*!< 0x00000800 */ +#define RCC_CCIPR1_LPTIM2SEL_Pos (18U) +#define RCC_CCIPR1_LPTIM2SEL_Msk (0x3UL << RCC_CCIPR1_LPTIM2SEL_Pos) /*!< 0x000C0000 */ +#define RCC_CCIPR1_LPTIM2SEL RCC_CCIPR1_LPTIM2SEL_Msk +#define RCC_CCIPR1_LPTIM2SEL_0 (0x1UL << RCC_CCIPR1_LPTIM2SEL_Pos) /*!< 0x00040000 */ +#define RCC_CCIPR1_LPTIM2SEL_1 (0x2UL << RCC_CCIPR1_LPTIM2SEL_Pos) /*!< 0x00080000 */ +#define RCC_CCIPR1_SPI1SEL_Pos (20U) +#define RCC_CCIPR1_SPI1SEL_Msk (0x3UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x00300000 */ +#define RCC_CCIPR1_SPI1SEL RCC_CCIPR1_SPI1SEL_Msk +#define RCC_CCIPR1_SPI1SEL_0 (0x1UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x00100000 */ +#define RCC_CCIPR1_SPI1SEL_1 (0x2UL << RCC_CCIPR1_SPI1SEL_Pos) /*!< 0x00200000 */ +#define RCC_CCIPR1_SYSTICKSEL_Pos (22U) +#define RCC_CCIPR1_SYSTICKSEL_Msk (0x3UL << RCC_CCIPR1_SYSTICKSEL_Pos) /*!< 0x00C00000 */ +#define RCC_CCIPR1_SYSTICKSEL RCC_CCIPR1_SYSTICKSEL_Msk +#define RCC_CCIPR1_SYSTICKSEL_0 (0x1UL << RCC_CCIPR1_SYSTICKSEL_Pos) /*!< 0x00400000 */ +#define RCC_CCIPR1_SYSTICKSEL_1 (0x2UL << RCC_CCIPR1_SYSTICKSEL_Pos) /*!< 0x00800000 */ +#define RCC_CCIPR1_TIMICSEL_Pos (31U) +#define RCC_CCIPR1_TIMICSEL_Msk (0x1UL << RCC_CCIPR1_TIMICSEL_Pos) /*!< 0x80000000 */ +#define RCC_CCIPR1_TIMICSEL RCC_CCIPR1_TIMICSEL_Msk + +/******************** Bit definition for RCC_CCIPR2 register ******************/ +#define RCC_CCIPR2_SAI1SEL_Pos (5U) +#define RCC_CCIPR2_SAI1SEL_Msk (0x7UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x000000E0 */ +#define RCC_CCIPR2_SAI1SEL RCC_CCIPR2_SAI1SEL_Msk +#define RCC_CCIPR2_SAI1SEL_0 (0x1UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x00000020 */ +#define RCC_CCIPR2_SAI1SEL_1 (0x2UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR2_SAI1SEL_2 (0x4UL << RCC_CCIPR2_SAI1SEL_Pos) /*!< 0x00000080 */ +#define RCC_CCIPR2_RNGSEL_Pos (12U) +#define RCC_CCIPR2_RNGSEL_Msk (0x3UL << RCC_CCIPR2_RNGSEL_Pos) /*!< 0x00300000 */ +#define RCC_CCIPR2_RNGSEL RCC_CCIPR2_RNGSEL_Msk +#define RCC_CCIPR2_RNGSEL_0 (0x1UL << RCC_CCIPR2_RNGSEL_Pos) /*!< 0x00100000 */ +#define RCC_CCIPR2_RNGSEL_1 (0x2UL << RCC_CCIPR2_RNGSEL_Pos) /*!< 0x00200000 */ +#if !defined (STM32WBAXX_SI_CUT1_0) +#define RCC_CCIPR2_ASSEL_Pos (30U) +#define RCC_CCIPR2_ASSEL_Msk (0x1UL << RCC_CCIPR2_ASSEL_Pos) /*!< 0x40000000 */ +#define RCC_CCIPR2_ASSEL RCC_CCIPR2_ASSEL_Msk +#endif + +/******************** Bit definition for RCC_CCIPR3 register ***************/ +#define RCC_CCIPR3_LPUART1SEL_Pos (0U) +#define RCC_CCIPR3_LPUART1SEL_Msk (0x3UL << RCC_CCIPR3_LPUART1SEL_Pos) /*!< 0x00000003 */ +#define RCC_CCIPR3_LPUART1SEL RCC_CCIPR3_LPUART1SEL_Msk +#define RCC_CCIPR3_LPUART1SEL_0 (0x1UL << RCC_CCIPR3_LPUART1SEL_Pos) /*!< 0x00000001 */ +#define RCC_CCIPR3_LPUART1SEL_1 (0x2UL << RCC_CCIPR3_LPUART1SEL_Pos) /*!< 0x00000002 */ +#define RCC_CCIPR3_SPI3SEL_Pos (3U) +#define RCC_CCIPR3_SPI3SEL_Msk (0x3UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000018 */ +#define RCC_CCIPR3_SPI3SEL RCC_CCIPR3_SPI3SEL_Msk +#define RCC_CCIPR3_SPI3SEL_0 (0x1UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000008 */ +#define RCC_CCIPR3_SPI3SEL_1 (0x2UL << RCC_CCIPR3_SPI3SEL_Pos) /*!< 0x00000010 */ +#define RCC_CCIPR3_I2C3SEL_Pos (6U) +#define RCC_CCIPR3_I2C3SEL_Msk (0x3UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x000000C0 */ +#define RCC_CCIPR3_I2C3SEL RCC_CCIPR3_I2C3SEL_Msk +#define RCC_CCIPR3_I2C3SEL_0 (0x1UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000040 */ +#define RCC_CCIPR3_I2C3SEL_1 (0x2UL << RCC_CCIPR3_I2C3SEL_Pos) /*!< 0x00000080 */ +#define RCC_CCIPR3_LPTIM1SEL_Pos (10U) +#define RCC_CCIPR3_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00000C00 */ +#define RCC_CCIPR3_LPTIM1SEL RCC_CCIPR3_LPTIM1SEL_Msk +#define RCC_CCIPR3_LPTIM1SEL_0 (0x1UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00000400 */ +#define RCC_CCIPR3_LPTIM1SEL_1 (0x2UL << RCC_CCIPR3_LPTIM1SEL_Pos) /*!< 0x00000800 */ +#define RCC_CCIPR3_ADCSEL_Pos (12U) +#define RCC_CCIPR3_ADCSEL_Msk (0x7UL << RCC_CCIPR3_ADCSEL_Pos) /*!< 0x00007000 */ +#define RCC_CCIPR3_ADCSEL RCC_CCIPR3_ADCSEL_Msk +#define RCC_CCIPR3_ADCSEL_0 (0x1UL << RCC_CCIPR3_ADCSEL_Pos) /*!< 0x00001000 */ +#define RCC_CCIPR3_ADCSEL_1 (0x2UL << RCC_CCIPR3_ADCSEL_Pos) /*!< 0x00002000 */ +#define RCC_CCIPR3_ADCSEL_2 (0x4UL << RCC_CCIPR3_ADCSEL_Pos) /*!< 0x00004000 */ + +/******************** Bit definition for RCC_BDCR1 register ******************/ +#define RCC_BDCR1_LSEON_Pos (0U) +#define RCC_BDCR1_LSEON_Msk (0x1UL << RCC_BDCR1_LSEON_Pos) /*!< 0x00000001 */ +#define RCC_BDCR1_LSEON RCC_BDCR1_LSEON_Msk +#define RCC_BDCR1_LSERDY_Pos (1U) +#define RCC_BDCR1_LSERDY_Msk (0x1UL << RCC_BDCR1_LSERDY_Pos) /*!< 0x00000002 */ +#define RCC_BDCR1_LSERDY RCC_BDCR1_LSERDY_Msk +#define RCC_BDCR1_LSEBYP_Pos (2U) +#define RCC_BDCR1_LSEBYP_Msk (0x1UL << RCC_BDCR1_LSEBYP_Pos) /*!< 0x00000004 */ +#define RCC_BDCR1_LSEBYP RCC_BDCR1_LSEBYP_Msk +#define RCC_BDCR1_LSEDRV_Pos (3U) +#define RCC_BDCR1_LSEDRV_Msk (0x3UL << RCC_BDCR1_LSEDRV_Pos) /*!< 0x00000018 */ +#define RCC_BDCR1_LSEDRV RCC_BDCR1_LSEDRV_Msk +#define RCC_BDCR1_LSEDRV_0 (0x1UL << RCC_BDCR1_LSEDRV_Pos) /*!< 0x00000008 */ +#define RCC_BDCR1_LSEDRV_1 (0x2UL << RCC_BDCR1_LSEDRV_Pos) /*!< 0x00000010 */ +#define RCC_BDCR1_LSECSSON_Pos (5U) +#define RCC_BDCR1_LSECSSON_Msk (0x1UL << RCC_BDCR1_LSECSSON_Pos) /*!< 0x00000020 */ +#define RCC_BDCR1_LSECSSON RCC_BDCR1_LSECSSON_Msk +#define RCC_BDCR1_LSECSSD_Pos (6U) +#define RCC_BDCR1_LSECSSD_Msk (0x1UL << RCC_BDCR1_LSECSSD_Pos) /*!< 0x00000040 */ +#define RCC_BDCR1_LSECSSD RCC_BDCR1_LSECSSD_Msk +#define RCC_BDCR1_LSESYSEN_Pos (7U) +#define RCC_BDCR1_LSESYSEN_Msk (0x1UL << RCC_BDCR1_LSESYSEN_Pos) /*!< 0x00000080 */ +#define RCC_BDCR1_LSESYSEN RCC_BDCR1_LSESYSEN_Msk +#define RCC_BDCR1_RTCSEL_Pos (8U) +#define RCC_BDCR1_RTCSEL_Msk (0x3UL << RCC_BDCR1_RTCSEL_Pos) /*!< 0x00000300 */ +#define RCC_BDCR1_RTCSEL RCC_BDCR1_RTCSEL_Msk +#define RCC_BDCR1_RTCSEL_0 (0x1UL << RCC_BDCR1_RTCSEL_Pos) /*!< 0x00000100 */ +#define RCC_BDCR1_RTCSEL_1 (0x2UL << RCC_BDCR1_RTCSEL_Pos) /*!< 0x00000200 */ +#define RCC_BDCR1_LSESYSRDY_Pos (11U) +#define RCC_BDCR1_LSESYSRDY_Msk (0x1UL << RCC_BDCR1_LSESYSRDY_Pos) /*!< 0x00000800 */ +#define RCC_BDCR1_LSESYSRDY RCC_BDCR1_LSESYSRDY_Msk +#define RCC_BDCR1_LSEGFON_Pos (12U) +#define RCC_BDCR1_LSEGFON_Msk (0x1UL << RCC_BDCR1_LSEGFON_Pos) /*!< 0x00001000 */ +#define RCC_BDCR1_LSEGFON RCC_BDCR1_LSEGFON_Msk +#define RCC_BDCR1_LSETRIM_Pos (13U) +#define RCC_BDCR1_LSETRIM_Msk (0x3UL << RCC_BDCR1_LSETRIM_Pos) /*!< 0x00006000 */ +#define RCC_BDCR1_LSETRIM RCC_BDCR1_LSETRIM_Msk +#define RCC_BDCR1_LSETRIM_0 (0x1UL << RCC_BDCR1_LSETRIM_Pos) /*!< 0x00002000 */ +#define RCC_BDCR1_LSETRIM_1 (0x2UL << RCC_BDCR1_LSETRIM_Pos) /*!< 0x00004000 */ +#define RCC_BDCR1_BDRST_Pos (16U) +#define RCC_BDCR1_BDRST_Msk (0x1UL << RCC_BDCR1_BDRST_Pos) /*!< 0x00010000 */ +#define RCC_BDCR1_BDRST RCC_BDCR1_BDRST_Msk +#define RCC_BDCR1_RADIOSTSEL_Pos (18U) +#define RCC_BDCR1_RADIOSTSEL_Msk (0x3UL << RCC_BDCR1_RADIOSTSEL_Pos) /*!< 0x000C0000 */ +#define RCC_BDCR1_RADIOSTSEL RCC_BDCR1_RADIOSTSEL_Msk +#define RCC_BDCR1_RADIOSTSEL_0 (0x1UL << RCC_BDCR1_RADIOSTSEL_Pos) /*!< 0x00040000 */ +#define RCC_BDCR1_RADIOSTSEL_1 (0x2UL << RCC_BDCR1_RADIOSTSEL_Pos) /*!< 0x00080000 */ +#define RCC_BDCR1_LSCOEN_Pos (24U) +#define RCC_BDCR1_LSCOEN_Msk (0x1UL << RCC_BDCR1_LSCOEN_Pos) /*!< 0x01000000 */ +#define RCC_BDCR1_LSCOEN RCC_BDCR1_LSCOEN_Msk +#define RCC_BDCR1_LSCOSEL_Pos (25U) +#define RCC_BDCR1_LSCOSEL_Msk (0x1UL << RCC_BDCR1_LSCOSEL_Pos) /*!< 0x02000000 */ +#define RCC_BDCR1_LSCOSEL RCC_BDCR1_LSCOSEL_Msk +#define RCC_BDCR1_LSI1ON_Pos (26U) +#define RCC_BDCR1_LSI1ON_Msk (0x1UL << RCC_BDCR1_LSI1ON_Pos) /*!< 0x04000000 */ +#define RCC_BDCR1_LSI1ON RCC_BDCR1_LSI1ON_Msk +#define RCC_BDCR1_LSI1RDY_Pos (27U) +#define RCC_BDCR1_LSI1RDY_Msk (0x1UL << RCC_BDCR1_LSI1RDY_Pos) /*!< 0x08000000 */ +#define RCC_BDCR1_LSI1RDY RCC_BDCR1_LSI1RDY_Msk +#define RCC_BDCR1_LSI1PREDIV_Pos (28U) +#define RCC_BDCR1_LSI1PREDIV_Msk (0x1UL << RCC_BDCR1_LSI1PREDIV_Pos) /*!< 0x10000000 */ +#define RCC_BDCR1_LSI1PREDIV RCC_BDCR1_LSI1PREDIV_Msk +#define RCC_BDCR1_LSI2ON_Pos (29U) +#define RCC_BDCR1_LSI2ON_Msk (0x1UL << RCC_BDCR1_LSI2ON_Pos) /*!< 0x20000000 */ +#define RCC_BDCR1_LSI2ON RCC_BDCR1_LSI2ON_Msk +#define RCC_BDCR1_LSI2RDY_Pos (30U) +#define RCC_BDCR1_LSI2RDY_Msk (0x1UL << RCC_BDCR1_LSI2RDY_Pos) /*!< 0x40000000 */ +#define RCC_BDCR1_LSI2RDY RCC_BDCR1_LSI2RDY_Msk + +/******************** Bit definition for RCC_CSR register *******************/ +#define RCC_CSR_RMVF_Pos (23U) +#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */ +#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk +#define RCC_CSR_OBLRSTF_Pos (25U) +#define RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */ +#define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk +#define RCC_CSR_PINRSTF_Pos (26U) +#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */ +#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk +#define RCC_CSR_BORRSTF_Pos (27U) +#define RCC_CSR_BORRSTF_Msk (0x1UL << RCC_CSR_BORRSTF_Pos) /*!< 0x08000000 */ +#define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk +#define RCC_CSR_SFTRSTF_Pos (28U) +#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */ +#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk +#define RCC_CSR_IWDGRSTF_Pos (29U) +#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */ +#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk +#define RCC_CSR_WWDGRSTF_Pos (30U) +#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */ +#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk +#define RCC_CSR_LPWRRSTF_Pos (31U) +#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */ +#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk + +/******************** Bit definition for RCC_BDCR2 register *******************/ +#define RCC_BDCR2_LSI2MODE_Pos (0U) +#define RCC_BDCR2_LSI2MODE_Msk (0x7UL << RCC_BDCR2_LSI2MODE_Pos) /*!< 0x00000007 */ +#define RCC_BDCR2_LSI2MODE RCC_BDCR2_LSI2MODE_Msk +#define RCC_BDCR2_LSI2MODE_0 (0x1UL << RCC_BDCR2_LSI2MODE_Pos) /*!< 0x00000001 */ +#define RCC_BDCR2_LSI2MODE_1 (0x2UL << RCC_BDCR2_LSI2MODE_Pos) /*!< 0x00000002 */ +#define RCC_BDCR2_LSI2MODE_2 (0x4UL << RCC_BDCR2_LSI2MODE_Pos) /*!< 0x00000004 */ +#define RCC_BDCR2_LSI2CFG_Pos (4U) +#define RCC_BDCR2_LSI2CFG_Msk (0xFUL << RCC_BDCR2_LSI2CFG_Pos) /*!< 0x000000F0 */ +#define RCC_BDCR2_LSI2CFG RCC_BDCR2_LSI2CFG_Msk +#define RCC_BDCR2_LSI2CFG_0 (0x1UL << RCC_BDCR2_LSI2CFG_Pos) /*!< 0x00000010 */ +#define RCC_BDCR2_LSI2CFG_1 (0x2UL << RCC_BDCR2_LSI2CFG_Pos) /*!< 0x00000020 */ +#define RCC_BDCR2_LSI2CFG_2 (0x4UL << RCC_BDCR2_LSI2CFG_Pos) /*!< 0x00000040 */ +#define RCC_BDCR2_LSI2CFG_3 (0x8UL << RCC_BDCR2_LSI2CFG_Pos) /*!< 0x00000080 */ + +/******************** Bit definition for RCC_SECCFGR register **************/ +#define RCC_SECCFGR_HSISEC_Pos (0U) +#define RCC_SECCFGR_HSISEC_Msk (0x1UL << RCC_SECCFGR_HSISEC_Pos) /*!< 0x00000001 */ +#define RCC_SECCFGR_HSISEC RCC_SECCFGR_HSISEC_Msk +#define RCC_SECCFGR_HSESEC_Pos (1U) +#define RCC_SECCFGR_HSESEC_Msk (0x1UL << RCC_SECCFGR_HSESEC_Pos) /*!< 0x00000002 */ +#define RCC_SECCFGR_HSESEC RCC_SECCFGR_HSESEC_Msk +#define RCC_SECCFGR_LSISEC_Pos (3U) +#define RCC_SECCFGR_LSISEC_Msk (0x1UL << RCC_SECCFGR_LSISEC_Pos) /*!< 0x00000008 */ +#define RCC_SECCFGR_LSISEC RCC_SECCFGR_LSISEC_Msk +#define RCC_SECCFGR_LSESEC_Pos (4U) +#define RCC_SECCFGR_LSESEC_Msk (0x1UL << RCC_SECCFGR_LSESEC_Pos) /*!< 0x00000010 */ +#define RCC_SECCFGR_LSESEC RCC_SECCFGR_LSESEC_Msk +#define RCC_SECCFGR_SYSCLKSEC_Pos (5U) +#define RCC_SECCFGR_SYSCLKSEC_Msk (0x1UL << RCC_SECCFGR_SYSCLKSEC_Pos) /*!< 0x00000020 */ +#define RCC_SECCFGR_SYSCLKSEC RCC_SECCFGR_SYSCLKSEC_Msk +#define RCC_SECCFGR_PRESCSEC_Pos (6U) +#define RCC_SECCFGR_PRESCSEC_Msk (0x1UL << RCC_SECCFGR_PRESCSEC_Pos) /*!< 0x00000040 */ +#define RCC_SECCFGR_PRESCSEC RCC_SECCFGR_PRESCSEC_Msk +#define RCC_SECCFGR_PLL1SEC_Pos (7U) +#define RCC_SECCFGR_PLL1SEC_Msk (0x1UL << RCC_SECCFGR_PLL1SEC_Pos) /*!< 0x00000080 */ +#define RCC_SECCFGR_PLL1SEC RCC_SECCFGR_PLL1SEC_Msk +#define RCC_SECCFGR_RMVFSEC_Pos (12U) +#define RCC_SECCFGR_RMVFSEC_Msk (0x1UL << RCC_SECCFGR_RMVFSEC_Pos) /*!< 0x00001000 */ +#define RCC_SECCFGR_RMVFSEC RCC_SECCFGR_RMVFSEC_Msk + +/******************** Bit definition for RCC_PRIVCFGR register **************/ +#define RCC_PRIVCFGR_SPRIV_Pos (0U) +#define RCC_PRIVCFGR_SPRIV_Msk (0x1UL << RCC_PRIVCFGR_SPRIV_Pos) /*!< 0x00000001 */ +#define RCC_PRIVCFGR_SPRIV RCC_PRIVCFGR_SPRIV_Msk +#define RCC_PRIVCFGR_NSPRIV_Pos (1U) +#define RCC_PRIVCFGR_NSPRIV_Msk (0x1UL << RCC_PRIVCFGR_NSPRIV_Pos) /*!< 0x00000002 */ +#define RCC_PRIVCFGR_NSPRIV RCC_PRIVCFGR_NSPRIV_Msk + +#if !defined (STM32WBAXX_SI_CUT1_0) +/******************** Bit definition for RCC_ASCR register **************/ +#define RCC_ASCR_CEN_Pos (0U) +#define RCC_ASCR_CEN RCC_ASCR_CEN_Msk +#define RCC_ASCR_CEN_Msk (0x1UL << RCC_ASCR_CEN_Pos) /*!< 0x00000001 */ +#define RCC_ASCR_PSC_Pos (8U) +#define RCC_ASCR_PSC_Msk (0x7FUL << RCC_ASCR_PSC_Pos) /*!< 0x00007F00 */ +#define RCC_ASCR_PSC RCC_ASCR_PSC_Msk +#define RCC_ASCR_CPS_Pos (16U) +#define RCC_ASCR_CPS_Msk (0x7FUL << RCC_ASCR_CPS_Pos) /*!< 0x007F0000 */ +#define RCC_ASCR_CPS RCC_ASCR_CPS_Msk + +/******************** Bit definition for RCC_ASIER register **************/ +#define RCC_ASIER_CAIE_Pos (0U) +#define RCC_ASIER_CAIE RCC_ASIER_CAIE_Msk +#define RCC_ASIER_CAIE_Msk (0x1UL << RCC_ASIER_CAIE_Pos) /*!< 0x00000001 */ +#define RCC_ASIER_COIE_Pos (1U) +#define RCC_ASIER_COIE_Msk (0x1UL << RCC_ASIER_COIE_Pos) /*!< 0x00000002 */ +#define RCC_ASIER_COIE RCC_ASIER_COIE_Msk +#define RCC_ASIER_CAEIE_Pos (2U) +#define RCC_ASIER_CAEIE_Msk (0x1UL << RCC_ASIER_CAEIE_Pos) /*!< 0x00000004 */ +#define RCC_ASIER_CAEIE RCC_ASIER_CAEIE_Msk + +/******************** Bit definition for RCC_ASSR register **************/ +#define RCC_ASSR_CAF_Pos (0U) +#define RCC_ASSR_CAF RCC_ASSR_CAF_Msk +#define RCC_ASSR_CAF_Msk (0x1UL << RCC_ASSR_CAF_Pos) /*!< 0x00000001 */ +#define RCC_ASSR_COF_Pos (1U) +#define RCC_ASSR_COF_Msk (0x1UL << RCC_ASSR_COF_Pos) /*!< 0x00000002 */ +#define RCC_ASSR_COF RCC_ASSR_COF_Msk +#define RCC_ASSR_CAEF_Pos (2U) +#define RCC_ASSR_CAEF_Msk (0x1UL << RCC_ASSR_CAEF_Pos) /*!< 0x00000004 */ +#define RCC_ASSR_CAEF RCC_ASSR_CAEF_Msk + +/******************** Bit definition for RCC_ASCNTR register **************/ +#define RCC_ASCNTR_CNT_Pos (0U) +#define RCC_ASCNTR_CNT RCC_ASCNTR_CNT_Msk +#define RCC_ASCNTR_CNT_Msk (0xFFFFFUL << RCC_ASCNTR_CNT_Pos) /*!< 0x000FFFFF */ + +/******************** Bit definition for RCC_ASARR register **************/ +#define RCC_ASARR_AR_Pos (0U) +#define RCC_ASARR_AR RCC_ASARR_AR_Msk +#define RCC_ASARR_AR_Msk (0xFFFFFUL << RCC_ASARR_AR_Pos) /*!< 0x000FFFFF */ + +/******************** Bit definition for RCC_ASCAR register **************/ +#define RCC_ASCAR_CA_Pos (0U) +#define RCC_ASCAR_CA RCC_ASCAR_CA_Msk +#define RCC_ASCAR_CA_Msk (0x7FFFFFFUL << RCC_ASCAR_CA_Pos) /*!< 0x07FFFFFF */ + +/******************** Bit definition for RCC_ASCOR register **************/ +#define RCC_ASCOR_CO_Pos (0U) +#define RCC_ASCOR_CO RCC_ASCOR_CO_Msk +#define RCC_ASCOR_CO_Msk (0xFFFFFUL << RCC_ASCOR_CO_Pos) /*!< 0x000FFFFF */ + +#endif +/******************** Bit definition for RCC_CFGR4 register *******************/ +#define RCC_CFGR4_HPRE5_Pos (0U) +#define RCC_CFGR4_HPRE5_Msk (0x7UL << RCC_CFGR4_HPRE5_Pos) /*!< 0x00000007 */ +#define RCC_CFGR4_HPRE5 RCC_CFGR4_HPRE5_Msk +#define RCC_CFGR4_HPRE5_0 (0x1UL << RCC_CFGR4_HPRE5_Pos) /*!< 0x00000001 */ +#define RCC_CFGR4_HPRE5_1 (0x2UL << RCC_CFGR4_HPRE5_Pos) /*!< 0x00000002 */ +#define RCC_CFGR4_HPRE5_2 (0x4UL << RCC_CFGR4_HPRE5_Pos) /*!< 0x00000004 */ +#define RCC_CFGR4_HDIV5_Pos (4U) +#define RCC_CFGR4_HDIV5_Msk (0x1UL << RCC_CFGR4_HDIV5_Pos) /*!< 0x00000080 */ +#define RCC_CFGR4_HDIV5 RCC_CFGR4_HDIV5_Msk + +/******************** Bit definition for RCC_RADIOENR register **************/ +#define RCC_RADIOENR_BBCLKEN_Pos (1U) +#define RCC_RADIOENR_BBCLKEN_Msk (0x1UL << RCC_RADIOENR_BBCLKEN_Pos) /*!< 0x00000002 */ +#define RCC_RADIOENR_BBCLKEN RCC_RADIOENR_BBCLKEN_Msk +#define RCC_RADIOENR_STRADIOCLKON_Pos (16U) +#define RCC_RADIOENR_STRADIOCLKON_Msk (0x1UL << RCC_RADIOENR_STRADIOCLKON_Pos) /*!< 0x00010000 */ +#define RCC_RADIOENR_STRADIOCLKON RCC_RADIOENR_STRADIOCLKON_Msk +#define RCC_RADIOENR_RADIOCLKRDY_Pos (17U) +#define RCC_RADIOENR_RADIOCLKRDY_Msk (0x1UL << RCC_RADIOENR_RADIOCLKRDY_Pos) /*!< 0x00020000 */ +#define RCC_RADIOENR_RADIOCLKRDY RCC_RADIOENR_RADIOCLKRDY_Msk + +/******************** Bit definition for RCC_ECSCR1 register *******************/ +#define RCC_ECSCR1_HSETRIM_Pos (16U) +#define RCC_ECSCR1_HSETRIM_Msk (0x3FUL << RCC_ECSCR1_HSETRIM_Pos) /*!< 0x003F0000 */ +#define RCC_ECSCR1_HSETRIM RCC_ECSCR1_HSETRIM_Msk +#define RCC_ECSCR1_HSETRIM_0 (0x1UL << RCC_ECSCR1_HSETRIM_Pos) /*!< 0x00010000 */ +#define RCC_ECSCR1_HSETRIM_1 (0x2UL << RCC_ECSCR1_HSETRIM_Pos) /*!< 0x00020000 */ +#define RCC_ECSCR1_HSETRIM_2 (0x4UL << RCC_ECSCR1_HSETRIM_Pos) /*!< 0x00040000 */ +#define RCC_ECSCR1_HSETRIM_3 (0x8UL << RCC_ECSCR1_HSETRIM_Pos) /*!< 0x00080000 */ +#define RCC_ECSCR1_HSETRIM_4 (0x10UL << RCC_ECSCR1_HSETRIM_Pos) /*!< 0x00100000 */ +#define RCC_ECSCR1_HSETRIM_5 (0x20UL << RCC_ECSCR1_HSETRIM_Pos) /*!< 0x00200000 */ + + +/******************************************************************************/ +/* */ +/* RNG */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RNG_CR register *******************/ +#define RNG_CR_RNGEN_Pos (2U) +#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_IE_Pos (3U) +#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_CED_Pos (5U) +#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ +#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_ARDIS_Pos (7U) +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_RNG_CONFIG3_Pos (8U) +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_NISTC_Pos (12U) +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) +#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_RNG_CONFIG2_Pos (13U) +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_CLKDIV_Pos (16U) +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_RNG_CONFIG1_Pos (20U) +#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_CONDRST_Pos (30U) +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONFIGLOCK_Pos (31U) +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk + +/******************** Bits definition for RNG_SR register *******************/ +#define RNG_SR_DRDY_Pos (0U) +#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ +#define RNG_SR_DRDY RNG_SR_DRDY_Msk +#define RNG_SR_CECS_Pos (1U) +#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ +#define RNG_SR_CECS RNG_SR_CECS_Msk +#define RNG_SR_SECS_Pos (2U) +#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ +#define RNG_SR_SECS RNG_SR_SECS_Msk +#define RNG_SR_CEIS_Pos (5U) +#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ +#define RNG_SR_CEIS RNG_SR_CEIS_Msk +#define RNG_SR_SEIS_Pos (6U) +#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ +#define RNG_SR_SEIS RNG_SR_SEIS_Msk + +/******************** Bits definition for RNG_DR register *******************/ +#define RNG_DR_RNDATA_Pos (0U) +#define RNG_DR_RNDATA_Msk (0xFFFFFFFFUL << RNG_DR_RNDATA_Pos) /*!< 0xFFFFFFFF */ +#define RNG_DR_RNDATA RNG_DR_RNDATA_Msk + +/******************** Bits definition for RNG_HTCR register *******************/ +#define RNG_HTCR_HTCFG_Pos (0U) +#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk + + +/******************************************************************************/ +/* */ +/* Real-Time Clock (RTC) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RTC_TR register *******************/ +#define RTC_TR_SU_Pos (0U) +#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */ +#define RTC_TR_SU RTC_TR_SU_Msk +#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */ +#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */ +#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */ +#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */ +#define RTC_TR_ST_Pos (4U) +#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */ +#define RTC_TR_ST RTC_TR_ST_Msk +#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */ +#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */ +#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */ +#define RTC_TR_MNU_Pos (8U) +#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_TR_MNU RTC_TR_MNU_Msk +#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_TR_MNT_Pos (12U) +#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_TR_MNT RTC_TR_MNT_Msk +#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_TR_HU_Pos (16U) +#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_TR_HU RTC_TR_HU_Msk +#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */ +#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */ +#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */ +#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */ +#define RTC_TR_HT_Pos (20U) +#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */ +#define RTC_TR_HT RTC_TR_HT_Msk +#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */ +#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */ +#define RTC_TR_PM_Pos (22U) +#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */ +#define RTC_TR_PM RTC_TR_PM_Msk + +/******************** Bits definition for RTC_DR register *******************/ +#define RTC_DR_DU_Pos (0U) +#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */ +#define RTC_DR_DU RTC_DR_DU_Msk +#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */ +#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */ +#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */ +#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */ +#define RTC_DR_DT_Pos (4U) +#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */ +#define RTC_DR_DT RTC_DR_DT_Msk +#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */ +#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */ +#define RTC_DR_MU_Pos (8U) +#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */ +#define RTC_DR_MU RTC_DR_MU_Msk +#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */ +#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */ +#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */ +#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */ +#define RTC_DR_MT_Pos (12U) +#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */ +#define RTC_DR_MT RTC_DR_MT_Msk +#define RTC_DR_WDU_Pos (13U) +#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */ +#define RTC_DR_WDU RTC_DR_WDU_Msk +#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */ +#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */ +#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */ +#define RTC_DR_YU_Pos (16U) +#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */ +#define RTC_DR_YU RTC_DR_YU_Msk +#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */ +#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */ +#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */ +#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */ +#define RTC_DR_YT_Pos (20U) +#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */ +#define RTC_DR_YT RTC_DR_YT_Msk +#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */ +#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */ +#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */ +#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */ + +/******************** Bits definition for RTC_SSR register ******************/ +#define RTC_SSR_SS_Pos (0U) +#define RTC_SSR_SS_Msk (0xFFFFFFFFUL << RTC_SSR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_SSR_SS RTC_SSR_SS_Msk + +/******************** Bits definition for RTC_ICSR register ******************/ +#define RTC_ICSR_WUTWF_Pos (2U) +#define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */ +#define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk +#define RTC_ICSR_SHPF_Pos (3U) +#define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */ +#define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk +#define RTC_ICSR_INITS_Pos (4U) +#define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */ +#define RTC_ICSR_INITS RTC_ICSR_INITS_Msk +#define RTC_ICSR_RSF_Pos (5U) +#define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */ +#define RTC_ICSR_RSF RTC_ICSR_RSF_Msk +#define RTC_ICSR_INITF_Pos (6U) +#define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */ +#define RTC_ICSR_INITF RTC_ICSR_INITF_Msk +#define RTC_ICSR_INIT_Pos (7U) +#define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */ +#define RTC_ICSR_INIT RTC_ICSR_INIT_Msk +#define RTC_ICSR_BIN_Pos (8U) +#define RTC_ICSR_BIN_Msk (0x3UL << RTC_ICSR_BIN_Pos) /*!< 0x00000300 */ +#define RTC_ICSR_BIN RTC_ICSR_BIN_Msk +#define RTC_ICSR_BIN_0 (0x1UL << RTC_ICSR_BIN_Pos) /*!< 0x00000100 */ +#define RTC_ICSR_BIN_1 (0x2UL << RTC_ICSR_BIN_Pos) /*!< 0x00000200 */ +#define RTC_ICSR_BCDU_Pos (10U) +#define RTC_ICSR_BCDU_Msk (0x7UL << RTC_ICSR_BCDU_Pos) /*!< 0x00001C00 */ +#define RTC_ICSR_BCDU RTC_ICSR_BCDU_Msk +#define RTC_ICSR_BCDU_0 (0x1UL << RTC_ICSR_BCDU_Pos) /*!< 0x00000400 */ +#define RTC_ICSR_BCDU_1 (0x2UL << RTC_ICSR_BCDU_Pos) /*!< 0x00000800 */ +#define RTC_ICSR_BCDU_2 (0x4UL << RTC_ICSR_BCDU_Pos) /*!< 0x00001000 */ +#define RTC_ICSR_RECALPF_Pos (16U) +#define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */ +#define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk + +/******************** Bits definition for RTC_PRER register *****************/ +#define RTC_PRER_PREDIV_S_Pos (0U) +#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */ +#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk +#define RTC_PRER_PREDIV_A_Pos (16U) +#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ +#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk + +/******************** Bits definition for RTC_WUTR register *****************/ +#define RTC_WUTR_WUT_Pos (0U) +#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk +#define RTC_WUTR_WUTOCLR_Pos (16U) +#define RTC_WUTR_WUTOCLR_Msk (0xFFFFUL << RTC_WUTR_WUTOCLR_Pos) /*!< 0x0000FFFF */ +#define RTC_WUTR_WUTOCLR RTC_WUTR_WUTOCLR_Msk + +/******************** Bits definition for RTC_CR register *******************/ +#define RTC_CR_WUCKSEL_Pos (0U) +#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */ +#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk +#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */ +#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ +#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ +#define RTC_CR_TSEDGE_Pos (3U) +#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ +#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk +#define RTC_CR_REFCKON_Pos (4U) +#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ +#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk +#define RTC_CR_BYPSHAD_Pos (5U) +#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ +#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk +#define RTC_CR_FMT_Pos (6U) +#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */ +#define RTC_CR_FMT RTC_CR_FMT_Msk +#define RTC_CR_SSRUIE_Pos (7U) +#define RTC_CR_SSRUIE_Msk (0x1UL << RTC_CR_SSRUIE_Pos) /*!< 0x00000080 */ +#define RTC_CR_SSRUIE RTC_CR_SSRUIE_Msk +#define RTC_CR_ALRAE_Pos (8U) +#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ +#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk +#define RTC_CR_ALRBE_Pos (9U) +#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */ +#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk +#define RTC_CR_WUTE_Pos (10U) +#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */ +#define RTC_CR_WUTE RTC_CR_WUTE_Msk +#define RTC_CR_TSE_Pos (11U) +#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */ +#define RTC_CR_TSE RTC_CR_TSE_Msk +#define RTC_CR_ALRAIE_Pos (12U) +#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ +#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk +#define RTC_CR_ALRBIE_Pos (13U) +#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */ +#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk +#define RTC_CR_WUTIE_Pos (14U) +#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */ +#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk +#define RTC_CR_TSIE_Pos (15U) +#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */ +#define RTC_CR_TSIE RTC_CR_TSIE_Msk +#define RTC_CR_ADD1H_Pos (16U) +#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */ +#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk +#define RTC_CR_SUB1H_Pos (17U) +#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ +#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk +#define RTC_CR_BKP_Pos (18U) +#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */ +#define RTC_CR_BKP RTC_CR_BKP_Msk +#define RTC_CR_COSEL_Pos (19U) +#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ +#define RTC_CR_COSEL RTC_CR_COSEL_Msk +#define RTC_CR_POL_Pos (20U) +#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */ +#define RTC_CR_POL RTC_CR_POL_Msk +#define RTC_CR_OSEL_Pos (21U) +#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */ +#define RTC_CR_OSEL RTC_CR_OSEL_Msk +#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */ +#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ +#define RTC_CR_COE_Pos (23U) +#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */ +#define RTC_CR_COE RTC_CR_COE_Msk +#define RTC_CR_TAMPTS_Pos (25U) +#define RTC_CR_TAMPTS_Msk (0x1UL << RTC_CR_TAMPTS_Pos) /*!< 0x02000000 */ +#define RTC_CR_TAMPTS RTC_CR_TAMPTS_Msk /*! */ + +/******************** Bits definition for RTC_ALRMAR register ***************/ +#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk +#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk +#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk +#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk +#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk +#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk +#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk +#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk +#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk +#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk +#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk +#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk +#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk +#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk +#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Msk (0x3FUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x3F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_MASKSS_4 (0x10UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x10000000 */ +#define RTC_ALRMASSR_MASKSS_5 (0x20UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x20000000 */ +#define RTC_ALRMASSR_SSCLR_Pos (31U) +#define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk + +/******************** Bits definition for RTC_ALRMBR register ***************/ +#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk +#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk +#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk +#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk +#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk +#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk +#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk +#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk +#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk +#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk +#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk +#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk +#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk +#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMBSSR register *************/ +#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk +#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Msk (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x3F000000 */ +#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk +#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBSSR_MASKSS_4 (0x10UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBSSR_MASKSS_5 (0x20UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBSSR_SSCLR_Pos (31U) +#define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk + +/******************** Bits definition for RTC_SR register *******************/ +#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk +#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk +#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ +#define RTC_SR_WUTF RTC_SR_WUTF_Msk +#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ +#define RTC_SR_TSF RTC_SR_TSF_Msk +#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk +#define RTC_SR_SSRUF_Pos (6U) +#define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SR_SSRUF RTC_SR_SSRUF_Msk + +/******************** Bits definition for RTC_MISR register *****************/ +#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk +#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk +#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk +#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk +#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk +#define RTC_MISR_SSRUMF_Pos (6U) +#define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SMISR register *****************/ +#define RTC_SMISR_ALRAMF_Pos (0U) +#define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk +#define RTC_SMISR_ALRBMF_Pos (1U) +#define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk +#define RTC_SMISR_WUTMF_Pos (2U) +#define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk +#define RTC_SMISR_TSMF_Pos (3U) +#define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk +#define RTC_SMISR_TSOVMF_Pos (4U) +#define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk +#define RTC_SMISR_SSRUMF_Pos (6U) +#define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SCR register ******************/ +#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk +#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk +#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ +#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk +#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ +#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk +#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk +#define RTC_SCR_CSSRUF_Pos (6U) +#define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk + +/******************** Bits definition for RTC_ALRABINR register ******************/ +#define RTC_ALRABINR_SS_Pos (0U) +#define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk + +/******************** Bits definition for RTC_ALRBBINR register ******************/ +#define RTC_ALRBBINR_SS_Pos (0U) +#define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk + + +/******************************************************************************/ +/* */ +/* Serial Audio Interface */ +/* */ +/******************************************************************************/ +/******************** Bit definition for SAI_GCR register *******************/ +#define SAI_GCR_SYNCIN_Pos (0U) +#define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */ +#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!> HSEM_CR_LOCKID_Pos)/* Semaphore Lock ID */ + +#define HSEM_SEMID_MIN (0U) /* HSEM ID Min*/ +#define HSEM_SEMID_MAX (15U) /* HSEM ID Max */ + +#define HSEM_PROCESSID_MIN (0U) /* HSEM Process ID Min */ +#define HSEM_PROCESSID_MAX (255U) /* HSEM Process ID Max */ + +#define HSEM_CLEAR_KEY_MIN (0U) /* HSEM clear Key Min value */ +#define HSEM_CLEAR_KEY_MAX (0xFFFFU) /* HSEM clear Key Max value */ + +/******************************** I2C Instances *******************************/ +#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S)) + +/****************** I2C Instances : wakeup capability from stop modes *********/ +#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) + +/******************* I2C Instances : Group belongingness *********************/ +#define IS_I2C_GRP1_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S)) + +#define IS_I2C_GRP2_INSTANCE(INSTANCE) (((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S)) + +/******************************* AES Instances ********************************/ +#define IS_PKA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == PKA_NS) || ((INSTANCE) == PKA_S)) + +/******************************* RNG Instances ********************************/ +#define IS_RNG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RNG_NS) || ((INSTANCE) == RNG_S)) + +/****************************** RTC Instances *********************************/ +#define IS_RTC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RTC_NS) || ((INSTANCE) == RTC_S)) + +/******************************** SAI Instances *******************************/ +#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A_NS) || ((INSTANCE) == SAI1_Block_A_S) || \ + ((INSTANCE) == SAI1_Block_B_NS) || ((INSTANCE) == SAI1_Block_B_S)) + +/****************************** SMBUS Instances *******************************/ +#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S)) + +/******************* SMBUS Instances : Group membership ***********************/ +#define IS_SMBUS_GRP1_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S)) + +#define IS_SMBUS_GRP2_INSTANCE(INSTANCE) (((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S)) + +/******************************** SPI Instances *******************************/ +#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \ + ((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S)) + +#define IS_SPI_LIMITED_INSTANCE(INSTANCE) (((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S)) + +#define IS_SPI_FULL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S)) + +/******************* SPI Instances : Group belongingness *********************/ +#define IS_SPI_GRP1_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S)) + +#define IS_SPI_GRP2_INSTANCE(INSTANCE) (((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S)) + +/****************** LPTIM Instances : All supported instances *****************/ +#define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/****************** LPTIM Instances : DMA supported instances *****************/ +#define IS_LPTIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/************* LPTIM Instances : at least 1 capture/compare channel ***********/ +#define IS_LPTIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/************* LPTIM Instances : at least 2 capture/compare channel ***********/ +#define IS_LPTIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/****************** LPTIM Instances : supporting encoder interface **************/ +#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/****************** LPTIM Instances : supporting Input Capture **************/ +#define IS_LPTIM_INPUT_CAPTURE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/****************** TIM Instances : All supported instances *******************/ +#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting 32 bits counter ****************/ +#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S)) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/****************** TIM Instances : supporting the break function *************/ +#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/************** TIM Instances : supporting Break source selection *************/ +#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting 2 break inputs *****************/ +#define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) + +/************* TIM Instances : at least 1 capture/compare channel *************/ +#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/************ TIM Instances : at least 2 capture/compare channels *************/ +#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/************ TIM Instances : at least 3 capture/compare channels *************/ +#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/************ TIM Instances : at least 4 capture/compare channels *************/ +#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/****************** TIM Instances : at least 5 capture/compare channels *******/ +#define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) + +/****************** TIM Instances : at least 6 capture/compare channels *******/ +#define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) + +/************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/ +#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/ +#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/ +#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/******************** TIM Instances : DMA burst feature ***********************/ +#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/******************* TIM Instances : output(s) available **********************/ +#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ + (((((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4) || \ + ((CHANNEL) == TIM_CHANNEL_5) || \ + ((CHANNEL) == TIM_CHANNEL_6))) \ + || \ + ((((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1))) \ + || \ + ((((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1)))) + +/****************** TIM Instances : supporting complementary output(s) ********/ +#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ + (((((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)) && \ + ((CHANNEL) == TIM_CHANNEL_1)) \ + || \ + ((((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) && \ + ((CHANNEL) == TIM_CHANNEL_1))) + +/****************** TIM Instances : supporting clock division *****************/ +#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/ +#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/ +#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/****************** TIM Instances : supporting combined 3-phase PWM mode ******/ +#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) + +/****************** TIM Instances : supporting commutation event generation ***/ +#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting counting mode selection ********/ +#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/****************** TIM Instances : supporting encoder interface **************/ +#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/****************** TIM Instances : supporting Hall sensor interface **********/ +#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/**************** TIM Instances : external trigger input available ************/ +#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/************* TIM Instances : supporting ETR source selection ***************/ +#define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/ +#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/ +#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/****************** TIM Instances : supporting OCxREF clear *******************/ +#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/****************** TIM Instances : remapping capability **********************/ +#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/****************** TIM Instances : supporting repetition counter *************/ +#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/ +#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) + +/******************* TIM Instances : Timer input XOR function *****************/ +#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) + +/******************* TIM Instances : Timer input selection ********************/ +#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) ||\ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) ||\ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) ||\ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)||\ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/******************* TIM Instances : supporting HSE32 as input ********************/ +#define IS_TIM_HSE32_INSTANCE(INSTANCE) (((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) ||\ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : Advanced timer instances *******************/ +#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) + +/****************** TIM Instances : supporting synchronization ****************/ +#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1_NS) || ((__INSTANCE__) == TIM1_S) || \ + ((__INSTANCE__) == TIM2_NS) || ((__INSTANCE__) == TIM2_S) || \ + ((__INSTANCE__) == TIM3_NS) || ((__INSTANCE__) == TIM3_S)) + +/****************************** TSC Instances *********************************/ +#define IS_TSC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == TSC_NS) || ((INSTANCE) == TSC_S)) + +/******************** USART Instances : Synchronous mode **********************/ +#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S)) + +/******************** UART Instances : Asynchronous mode **********************/ +#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S)) + +/*********************** UART Instances : FIFO mode ***************************/ +#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/*********************** UART Instances : SPI Slave mode **********************/ +#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S)) + +/****************** UART Instances : Auto Baud Rate detection ****************/ +#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S)) + +/****************** UART Instances : Driver Enable *****************/ +#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/******************** UART Instances : Half-Duplex mode **********************/ +#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/****************** UART Instances : Hardware Flow control ********************/ +#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/******************** UART Instances : LIN mode **********************/ +#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S)) + +/******************** UART Instances : Wake-up from Stop mode **********************/ +#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/*********************** UART Instances : IRDA mode ***************************/ +#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S)) + +/********************* USART Instances : Smard card mode ***********************/ +#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S)) + +/******************** LPUART Instance *****************************************/ +#define IS_LPUART_INSTANCE(INSTANCE) (((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/*********************** UART Instances : AUTONOMOUS mode ***************************/ +#define IS_UART_AUTONOMOUS_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/****************************** IWDG Instances ********************************/ +#define IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG_NS) || ((INSTANCE) == IWDG_S)) + +/****************************** WWDG Instances ********************************/ +#define IS_WWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == WWDG_NS) || ((INSTANCE) == WWDG_S)) + +#else /* #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/* Instances allowed from Non-Secure state - only alias Non-Secure */ + +/******************************* ADC Instances ********************************/ +#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC4_NS) + +#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC4_COMMON_NS) + +/******************************* AES Instances ********************************/ +#define IS_AES_ALL_INSTANCE(INSTANCE) ((INSTANCE) == AES_NS) + +/******************************** COMP Instances ******************************/ +#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1_NS) || ((INSTANCE) == COMP2_NS)) + +/******************** COMP Instances with window mode capability **************/ +#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) (((INSTANCE) == COMP1_NS) || ((INSTANCE) == COMP2_NS)) + +/******************************* CRC Instances ********************************/ +#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC_NS) + +/******************************** DMA Instances *******************************/ +#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS) || \ + ((INSTANCE) == GPDMA1_Channel1_NS) || \ + ((INSTANCE) == GPDMA1_Channel2_NS) || \ + ((INSTANCE) == GPDMA1_Channel3_NS) || \ + ((INSTANCE) == GPDMA1_Channel4_NS) || \ + ((INSTANCE) == GPDMA1_Channel5_NS) || \ + ((INSTANCE) == GPDMA1_Channel6_NS) || \ + ((INSTANCE) == GPDMA1_Channel7_NS)) + +#define IS_GPDMA_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS) || \ + ((INSTANCE) == GPDMA1_Channel1_NS) || \ + ((INSTANCE) == GPDMA1_Channel2_NS) || \ + ((INSTANCE) == GPDMA1_Channel3_NS) || \ + ((INSTANCE) == GPDMA1_Channel4_NS) || \ + ((INSTANCE) == GPDMA1_Channel5_NS) || \ + ((INSTANCE) == GPDMA1_Channel6_NS) || \ + ((INSTANCE) == GPDMA1_Channel7_NS)) + +/****************************** RAMCFG Instances ********************************/ +#define IS_RAMCFG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM1_NS) || \ + ((INSTANCE) == RAMCFG_SRAM2_NS) || \ + ((INSTANCE) == RAMCFG_SRAM6_NS)) + +/***************************** RAMCFG PED Instances *****************************/ +#define IS_RAMCFG_PED_INSTANCE(INSTANCE) ((INSTANCE) == RAMCFG_SRAM2_NS) + +/***************************** RAMCFG IT Instances ******************************/ +#define IS_RAMCFG_IT_INSTANCE(INSTANCE) ((INSTANCE) == RAMCFG_SRAM2_NS) + +/************************ RAMCFG Write Protection Instances *********************/ +#define IS_RAMCFG_WP_INSTANCE(INSTANCE) ((INSTANCE) == RAMCFG_SRAM2_NS) + +/************************ RAMCFG Erase Instances ********************************/ +#define IS_RAMCFG_ER_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM1_NS) || \ + ((INSTANCE) == RAMCFG_SRAM2_NS)) + +/******************************* GPIO Instances *******************************/ +#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA_NS) || \ + ((INSTANCE) == GPIOB_NS) || \ + ((INSTANCE) == GPIOC_NS) || \ + ((INSTANCE) == GPIOH_NS)) + +/******************************* GPIO AF Instances ****************************/ +/* On WBA, all GPIO Bank support AF */ +#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) + +/**************************** GPIO Lock Instances *****************************/ +/* On WBA, all GPIO Bank support the Lock mechanism */ +#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) + +/**************************** HSEM Lock Instances *****************************/ +#define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM_NS) + +#define HSEM_CPU1_LOCKID (HSEM_CR_LOCKID_CURRENT >> HSEM_CR_LOCKID_Pos)/* Semaphore Lock ID */ + +#define HSEM_SEMID_MIN (0U) /* HSEM ID Min*/ +#define HSEM_SEMID_MAX (15U) /* HSEM ID Max */ + +#define HSEM_PROCESSID_MIN (0U) /* HSEM Process ID Min */ +#define HSEM_PROCESSID_MAX (255U) /* HSEM Process ID Max */ + +#define HSEM_CLEAR_KEY_MIN (0U) /* HSEM clear Key Min value */ +#define HSEM_CLEAR_KEY_MAX (0xFFFFU) /* HSEM clear Key Max value */ + +/******************************** I2C Instances *******************************/ +#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C3_NS)) + +/******************* I2C Instances : Group belongingness *********************/ +#define IS_I2C_GRP1_INSTANCE(INSTANCE) ((INSTANCE) == I2C1_NS) + +#define IS_I2C_GRP2_INSTANCE(INSTANCE) ((INSTANCE) == I2C3_NS) + +/****************** I2C Instances : wakeup capability from stop modes *********/ +#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) + +/******************************* AES Instances ********************************/ +#define IS_PKA_ALL_INSTANCE(INSTANCE) ((INSTANCE) == PKA_NS) + +/******************************* RNG Instances ********************************/ +#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG_NS) + +/****************************** RTC Instances *********************************/ +#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC_NS) + +/******************************** SAI Instances *******************************/ +#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A_NS) || ((INSTANCE) == SAI1_Block_B_NS)) + +/****************************** SMBUS Instances *******************************/ +#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C3_NS)) + +/******************* SMBUS Instances : Group membership ***********************/ +#define IS_SMBUS_GRP1_INSTANCE(INSTANCE) ((INSTANCE) == I2C1_NS) + +#define IS_SMBUS_GRP2_INSTANCE(INSTANCE) ((INSTANCE) == I2C3_NS) + +/******************************** SPI Instances *******************************/ +#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI3_NS)) + +#define IS_SPI_LIMITED_INSTANCE(INSTANCE) ((INSTANCE) == SPI3_NS) + +#define IS_SPI_FULL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1_NS) + +/******************* SPI Instances : Group belongingness *********************/ +#define IS_SPI_GRP1_INSTANCE(INSTANCE) ((INSTANCE) == SPI1_NS) + +#define IS_SPI_GRP2_INSTANCE(INSTANCE) ((INSTANCE) == SPI3_NS) + +/****************** LPTIM Instances : All supported instances *****************/ +#define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM2_NS)) + +/****************** LPTIM Instances : DMA supported instances *****************/ +#define IS_LPTIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM2_NS)) + +/************* LPTIM Instances : at least 1 capture/compare channel ***********/ +#define IS_LPTIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM2_NS)) + +/************* LPTIM Instances : at least 2 capture/compare channel ***********/ +#define IS_LPTIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM2_NS)) + +/****************** LPTIM Instances : supporting encoder interface **************/ +#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM2_NS)) + +/****************** LPTIM Instances : supporting Input Capture **************/ +#define IS_LPTIM_INPUT_CAPTURE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM2_NS)) + +/****************** TIM Instances : All supported instances *******************/ +#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS) || \ + ((INSTANCE) == TIM16_NS) || \ + ((INSTANCE) == TIM17_NS)) + +/****************** TIM Instances : supporting 32 bits counter ****************/ +#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/****************** TIM Instances : supporting the break function *************/ +#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM16_NS) || \ + ((INSTANCE) == TIM17_NS)) + +/************** TIM Instances : supporting Break source selection *************/ +#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM16_NS) || \ + ((INSTANCE) == TIM17_NS)) + +/****************** TIM Instances : supporting 2 break inputs *****************/ +#define IS_TIM_BKIN2_INSTANCE(INSTANCE) ((INSTANCE) == TIM1_NS) + +/************* TIM Instances : at least 1 capture/compare channel *************/ +#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS) || \ + ((INSTANCE) == TIM16_NS) || \ + ((INSTANCE) == TIM17_NS)) + +/************ TIM Instances : at least 2 capture/compare channels *************/ +#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/************ TIM Instances : at least 3 capture/compare channels *************/ +#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/************ TIM Instances : at least 4 capture/compare channels *************/ +#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/****************** TIM Instances : at least 5 capture/compare channels *******/ +#define IS_TIM_CC5_INSTANCE(INSTANCE) ((INSTANCE) == TIM1_NS) + +/****************** TIM Instances : at least 6 capture/compare channels *******/ +#define IS_TIM_CC6_INSTANCE(INSTANCE) ((INSTANCE) == TIM1_NS) + +/************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/ +#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM16_NS) || \ + ((INSTANCE) == TIM17_NS)) + +/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/ +#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS) || \ + ((INSTANCE) == TIM16_NS) || \ + ((INSTANCE) == TIM17_NS)) + +/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/ +#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS) || \ + ((INSTANCE) == TIM16_NS) || \ + ((INSTANCE) == TIM17_NS)) + +/******************** TIM Instances : DMA burst feature ***********************/ +#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS) || \ + ((INSTANCE) == TIM16_NS) || \ + ((INSTANCE) == TIM17_NS)) + +/******************* TIM Instances : output(s) available **********************/ +#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ + ((((INSTANCE) == TIM1_NS) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4) || \ + ((CHANNEL) == TIM_CHANNEL_5) || \ + ((CHANNEL) == TIM_CHANNEL_6))) \ + || \ + (((INSTANCE) == TIM2_NS) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + (((INSTANCE) == TIM3_NS) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + (((INSTANCE) == TIM16_NS) && \ + (((CHANNEL) == TIM_CHANNEL_1))) \ + || \ + (((INSTANCE) == TIM17_NS) && \ + (((CHANNEL) == TIM_CHANNEL_1)))) + +/****************** TIM Instances : supporting complementary output(s) ********/ +#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ + ((((INSTANCE) == TIM1_NS) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + (((INSTANCE) == TIM16_NS) && \ + ((CHANNEL) == TIM_CHANNEL_1)) \ + || \ + (((INSTANCE) == TIM17_NS) && \ + ((CHANNEL) == TIM_CHANNEL_1))) + +/****************** TIM Instances : supporting clock division *****************/ +#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS) || \ + ((INSTANCE) == TIM16_NS) || \ + ((INSTANCE) == TIM17_NS)) + +/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/ +#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/ +#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/****************** TIM Instances : supporting combined 3-phase PWM mode ******/ +#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) ((INSTANCE) == TIM1_NS) + +/****************** TIM Instances : supporting commutation event generation ***/ +#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM16_NS) || \ + ((INSTANCE) == TIM17_NS)) + +/****************** TIM Instances : supporting counting mode selection ********/ +#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/****************** TIM Instances : supporting encoder interface **************/ +#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/****************** TIM Instances : supporting Hall sensor interface **********/ +#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/**************** TIM Instances : external trigger input available ************/ +#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/************* TIM Instances : supporting ETR source selection ***************/ +#define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/ +#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/ +#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/****************** TIM Instances : supporting OCxREF clear *******************/ +#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/****************** TIM Instances : remapping capability **********************/ +#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/****************** TIM Instances : supporting repetition counter *************/ +#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM16_NS) || \ + ((INSTANCE) == TIM17_NS)) + +/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/ +#define IS_TIM_TRGO2_INSTANCE(INSTANCE) ((INSTANCE) == TIM1_NS) + +/******************* TIM Instances : Timer input XOR function *****************/ +#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS)) + +/******************* TIM Instances : Timer input selection ********************/ +#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \ + ((INSTANCE) == TIM2_NS) || \ + ((INSTANCE) == TIM3_NS) || \ + ((INSTANCE) == TIM16_NS) || \ + ((INSTANCE) == TIM17_NS)) + +/******************* TIM Instances : supporting HSE32 as input ********************/ +#define IS_TIM_HSE32_INSTANCE(INSTANCE) (((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM17_NS)) + +/****************** TIM Instances : Advanced timer instances *******************/ +#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1_NS) + +/****************** TIM Instances : supporting synchronization ****************/ +#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1_NS) || \ + ((__INSTANCE__) == TIM2_NS) || \ + ((__INSTANCE__) == TIM3_NS)) + +/****************************** TSC Instances *********************************/ +#define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC_NS) + +/******************** USART Instances : Synchronous mode **********************/ +#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART2_NS)) + +/******************** UART Instances : Asynchronous mode **********************/ +#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART2_NS)) + +/*********************** UART Instances : FIFO mode ***************************/ +#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \ + ((INSTANCE) == USART2_NS) || \ + ((INSTANCE) == LPUART1_NS)) + +/*********************** UART Instances : SPI Slave mode **********************/ +#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART2_NS)) + +/****************** UART Instances : Auto Baud Rate detection ****************/ +#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART2_NS)) + +/****************** UART Instances : Driver Enable *****************/ +#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \ + ((INSTANCE) == USART2_NS) || \ + ((INSTANCE) == LPUART1_NS)) + +/******************** UART Instances : Half-Duplex mode **********************/ +#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \ + ((INSTANCE) == USART2_NS) || \ + ((INSTANCE) == LPUART1_NS)) + +/****************** UART Instances : Hardware Flow control ********************/ +#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \ + ((INSTANCE) == USART2_NS) || \ + ((INSTANCE) == LPUART1_NS)) + +/******************** UART Instances : LIN mode **********************/ +#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART2_NS)) + +/******************** UART Instances : Wake-up from Stop mode **********************/ +#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \ + ((INSTANCE) == USART2_NS) || \ + ((INSTANCE) == LPUART1_NS)) + +/*********************** UART Instances : IRDA mode ***************************/ +#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART2_NS)) + +/********************* USART Instances : Smard card mode ***********************/ +#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART2_NS)) + +/*********************** UART Instances : AUTONOMOUS mode ***************************/ +#define IS_UART_AUTONOMOUS_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \ + ((INSTANCE) == USART2_NS) || \ + ((INSTANCE) == LPUART1_NS)) + +/******************** LPUART Instance *****************************************/ +#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1_NS) + +/****************************** IWDG Instances ********************************/ +#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG_NS) + +/****************************** WWDG Instances ********************************/ +#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG_NS) + +#endif /* #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** @} */ /* End of group STM32WBAxx_Peripheral_Exported_macros */ + +/** @} */ /* End of group STM32WBA55xx */ + +/** @} */ /* End of group ST */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WBA55xx_H */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wbaxx.h b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wbaxx.h new file mode 100644 index 0000000000..c1fdad82ac --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wbaxx.h @@ -0,0 +1,235 @@ +/** + ****************************************************************************** + * @file stm32wbaxx.h + * @author MCD Application Team + * @brief CMSIS STM32WBAxx Device Peripheral Access Layer Header File. + * + * The file is the unique include file that the application programmer + * is using in the C source code, usually in main.c. This file contains: + * - Configuration section that allows to select: + * - The STM32WBAxx device used in the target application + * - To use or not the peripheral's drivers in application code(i.e. + * code will be based on direct access to peripheral's registers + * rather than drivers API), this option is controlled by + * "#define USE_HAL_DRIVER" + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32wbaxx + * @{ + */ + +#ifndef STM32WBAxx_H +#define STM32WBAxx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Library_configuration_section + * @{ + */ + +/** + * @brief STM32 Family + */ +#if !defined(STM32WBA) +#define STM32WBA +#endif /* !STM32WBA */ + +/* Uncomment the line below according to the target STM32WBA device used in your + application + */ + +#if !defined(STM32WBA50xx) && !defined(STM32WBA52xx) && !defined(STM32WBA54xx) && !defined(STM32WBA55xx) + /* #define STM32WBA50xx */ /*!< STM32WBA50xx Devices */ + /* #define STM32WBA52xx */ /*!< STM32WBA52xx Devices */ + /* #define STM32WBA54xx */ /*!< STM32WBA54xx Devices */ + /* #define STM32WBA55xx */ /*!< STM32WBA55xx Devices */ +#endif /* !STM32WBA55xx && !STM32WBA52xx ...*/ + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ +#if !defined(USE_HAL_DRIVER) +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + /*#define USE_HAL_DRIVER */ +#endif /* USE_HAL_DRIVER */ + +/** + * @brief CMSIS Device version number + */ +#define __STM32WBA_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */ +#define __STM32WBA_CMSIS_VERSION_SUB1 (0x02U) /*!< [23:16] sub1 version */ +#define __STM32WBA_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ +#define __STM32WBA_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */ +#define __STM32WBA_CMSIS_VERSION ((__STM32WBA_CMSIS_VERSION_MAIN << 24U)\ + |(__STM32WBA_CMSIS_VERSION_SUB1 << 16U)\ + |(__STM32WBA_CMSIS_VERSION_SUB2 << 8U )\ + |(__STM32WBA_CMSIS_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Device_Included + * @{ + */ + +#if defined(STM32WBA50xx) + #include "stm32wba50xx.h" +#elif defined(STM32WBA52xx) + #include "stm32wba52xx.h" +#elif defined(STM32WBA54xx) + #include "stm32wba54xx.h" +#elif defined(STM32WBA55xx) + #include "stm32wba55xx.h" +#else + #error "Please select first the target STM32WBAxx device used in your application (in stm32wbaxx.h file)" +#endif /* STM32WBA50xx */ + +/** + * @} + */ + +/** @addtogroup Exported_types + * @{ + */ +typedef enum +{ + RESET = 0, + SET = !RESET +} FlagStatus, ITStatus; + +typedef enum +{ + DISABLE = 0, + ENABLE = !DISABLE +} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum +{ + SUCCESS = 0, + ERROR = !SUCCESS +} ErrorStatus; + +/** + * @} + */ + + +/** @addtogroup Exported_macros + * @{ + */ +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + +/* Use of CMSIS compiler intrinsics for register exclusive access */ +/* Atomic 32-bit register access macro to set one or several bits */ +#define ATOMIC_SET_BIT(REG, BIT) \ + do { \ + uint32_t val; \ + do { \ + val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT); \ + } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \ + } while(0) + +/* Atomic 32-bit register access macro to clear one or several bits */ +#define ATOMIC_CLEAR_BIT(REG, BIT) \ + do { \ + uint32_t val; \ + do { \ + val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT); \ + } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \ + } while(0) + +/* Atomic 32-bit register access macro to clear and set one or several bits */ +#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \ + do { \ + uint32_t val; \ + do { \ + val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \ + } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \ + } while(0) + +/* Atomic 16-bit register access macro to set one or several bits */ +#define ATOMIC_SETH_BIT(REG, BIT) \ + do { \ + uint16_t val; \ + do { \ + val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT); \ + } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \ + } while(0) + +/* Atomic 16-bit register access macro to clear one or several bits */ +#define ATOMIC_CLEARH_BIT(REG, BIT) \ + do { \ + uint16_t val; \ + do { \ + val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT); \ + } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \ + } while(0) + +/* Atomic 16-bit register access macro to clear and set one or several bits */ +#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) \ + do { \ + uint16_t val; \ + do { \ + val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \ + } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \ + } while(0) + +#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) + + +/** + * @} + */ + +#if defined (USE_HAL_DRIVER) + #include "stm32wbaxx_hal.h" +#endif /* USE_HAL_DRIVER */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STM32WBAxx_H */ +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/system_stm32wbaxx.h b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/system_stm32wbaxx.h new file mode 100644 index 0000000000..c58c46f08b --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/system_stm32wbaxx.h @@ -0,0 +1,108 @@ +/** + ****************************************************************************** + * @file system_stm32wbaxx.h + * @author MCD Application Team + * @brief CMSIS Cortex-M33 Device System Source File for STM32WBAxx devices. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup STM32WBAxx_system + * @{ + */ + +#ifndef SYSTEM_STM32WBAxx_H +#define SYSTEM_STM32WBAxx_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup STM32WBAxx_System_Includes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32WBAxx_System_Exported_Variables + * @{ + */ + /* The SystemCoreClock variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetSysClockFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +extern const uint8_t AHBPrescTable[8]; /*!< AHB prescalers table values */ +extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ +extern const uint8_t AHB5PrescTable[8]; /*!< AHB5 prescalers table values */ + +/** + * @} + */ + + +/** @addtogroup STM32WBAxx_System_Exported_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + + +/** + * @brief Update SystemCoreClock variable. + * + * Updates the SystemCoreClock with current core Clock retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + + +/** + * @brief Update SystemCoreClock variable from secure application and return its value + * when security is implemented in the system (Non-secure callable function). + * + * Returns the SystemCoreClock value with current core Clock retrieved from cpu registers. + */ +extern uint32_t SECURE_SystemCoreClockUpdate(void); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_STM32WBAxx_H */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/LICENSE.md b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/LICENSE.md new file mode 100644 index 0000000000..261eeb9e9f --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/LICENSE.md @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. Definitions. + + "License" shall mean the terms and conditions for use, reproduction, + and distribution as defined by Sections 1 through 9 of this document. + + "Licensor" shall mean the copyright owner or entity authorized by + the copyright owner that is granting the License. + + "Legal Entity" shall mean the union of the acting entity and all + other entities that control, are controlled by, or are under common + control with that entity. For the purposes of this definition, + "control" means (i) the power, direct or indirect, to cause the + direction or management of such entity, whether by contract or + otherwise, or (ii) ownership of fifty percent (50%) or more of the + outstanding shares, or (iii) beneficial ownership of such entity. + + "You" (or "Your") shall mean an individual or Legal Entity + exercising permissions granted by this License. + + "Source" form shall mean the preferred form for making modifications, + including but not limited to software source code, documentation + source, and configuration files. + + "Object" form shall mean any form resulting from mechanical + transformation or translation of a Source form, including but + not limited to compiled object code, generated documentation, + and conversions to other media types. + + "Work" shall mean the work of authorship, whether in Source or + Object form, made available under the License, as indicated by a + copyright notice that is included in or attached to the work + (an example is provided in the Appendix below). + + "Derivative Works" shall mean any work, whether in Source or Object + form, that is based on (or derived from) the Work and for which the + editorial revisions, annotations, elaborations, or other modifications + represent, as a whole, an original work of authorship. For the purposes + of this License, Derivative Works shall not include works that remain + separable from, or merely link (or bind by name) to the interfaces of, + the Work and Derivative Works thereof. + + "Contribution" shall mean any work of authorship, including + the original version of the Work and any modifications or additions + to that Work or Derivative Works thereof, that is intentionally + submitted to Licensor for inclusion in the Work by the copyright owner + or by an individual or Legal Entity authorized to submit on behalf of + the copyright owner. For the purposes of this definition, "submitted" + means any form of electronic, verbal, or written communication sent + to the Licensor or its representatives, including but not limited to + communication on electronic mailing lists, source code control systems, + and issue tracking systems that are managed by, or on behalf of, the + Licensor for the purpose of discussing and improving the Work, but + excluding communication that is conspicuously marked or otherwise + designated in writing by the copyright owner as "Not a Contribution." + + "Contributor" shall mean Licensor and any individual or Legal Entity + on behalf of whom a Contribution has been received by Licensor and + subsequently incorporated within the Work. + + 2. Grant of Copyright License. Subject to the terms and conditions of + this License, each Contributor hereby grants to You a perpetual, + worldwide, non-exclusive, no-charge, royalty-free, irrevocable + copyright license to reproduce, prepare Derivative Works of, + publicly display, publicly perform, sublicense, and distribute the + Work and such Derivative Works in Source or Object form. + + 3. Grant of Patent License. Subject to the terms and conditions of + this License, each Contributor hereby grants to You a perpetual, + worldwide, non-exclusive, no-charge, royalty-free, irrevocable + (except as stated in this section) patent license to make, have made, + use, offer to sell, sell, import, and otherwise transfer the Work, + where such license applies only to those patent claims licensable + by such Contributor that are necessarily infringed by their + Contribution(s) alone or by combination of their Contribution(s) + with the Work to which such Contribution(s) was submitted. If You + institute patent litigation against any entity (including a + cross-claim or counterclaim in a lawsuit) alleging that the Work + or a Contribution incorporated within the Work constitutes direct + or contributory patent infringement, then any patent licenses + granted to You under this License for that Work shall terminate + as of the date such litigation is filed. + + 4. Redistribution. You may reproduce and distribute copies of the + Work or Derivative Works thereof in any medium, with or without + modifications, and in Source or Object form, provided that You + meet the following conditions: + + (a) You must give any other recipients of the Work or + Derivative Works a copy of this License; and + + (b) You must cause any modified files to carry prominent notices + stating that You changed the files; and + + (c) You must retain, in the Source form of any Derivative Works + that You distribute, all copyright, patent, trademark, and + attribution notices from the Source form of the Work, + excluding those notices that do not pertain to any part of + the Derivative Works; and + + (d) If the Work includes a "NOTICE" text file as part of its + distribution, then any Derivative Works that You distribute must + include a readable copy of the attribution notices contained + within such NOTICE file, excluding those notices that do not + pertain to any part of the Derivative Works, in at least one + of the following places: within a NOTICE text file distributed + as part of the Derivative Works; within the Source form or + documentation, if provided along with the Derivative Works; or, + within a display generated by the Derivative Works, if and + wherever such third-party notices normally appear. The contents + of the NOTICE file are for informational purposes only and + do not modify the License. You may add Your own attribution + notices within Derivative Works that You distribute, alongside + or as an addendum to the NOTICE text from the Work, provided + that such additional attribution notices cannot be construed + as modifying the License. + + You may add Your own copyright statement to Your modifications and + may provide additional or different license terms and conditions + for use, reproduction, or distribution of Your modifications, or + for any such Derivative Works as a whole, provided Your use, + reproduction, and distribution of the Work otherwise complies with + the conditions stated in this License. + + 5. Submission of Contributions. Unless You explicitly state otherwise, + any Contribution intentionally submitted for inclusion in the Work + by You to the Licensor shall be under the terms and conditions of + this License, without any additional terms or conditions. + Notwithstanding the above, nothing herein shall supersede or modify + the terms of any separate license agreement you may have executed + with Licensor regarding such Contributions. + + 6. Trademarks. This License does not grant permission to use the trade + names, trademarks, service marks, or product names of the Licensor, + except as required for reasonable and customary use in describing the + origin of the Work and reproducing the content of the NOTICE file. + + 7. Disclaimer of Warranty. Unless required by applicable law or + agreed to in writing, Licensor provides the Work (and each + Contributor provides its Contributions) on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied, including, without limitation, any warranties or conditions + of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A + PARTICULAR PURPOSE. You are solely responsible for determining the + appropriateness of using or redistributing the Work and assume any + risks associated with Your exercise of permissions under this License. + + 8. Limitation of Liability. In no event and under no legal theory, + whether in tort (including negligence), contract, or otherwise, + unless required by applicable law (such as deliberate and grossly + negligent acts) or agreed to in writing, shall any Contributor be + liable to You for damages, including any direct, indirect, special, + incidental, or consequential damages of any character arising as a + result of this License or out of the use or inability to use the + Work (including but not limited to damages for loss of goodwill, + work stoppage, computer failure or malfunction, or any and all + other commercial damages or losses), even if such Contributor + has been advised of the possibility of such damages. + + 9. Accepting Warranty or Additional Liability. While redistributing + the Work or Derivative Works thereof, You may choose to offer, + and charge a fee for, acceptance of support, warranty, indemnity, + or other liability obligations and/or rights consistent with this + License. However, in accepting such obligations, You may act only + on Your own behalf and on Your sole responsibility, not on behalf + of any other Contributor, and only if You agree to indemnify, + defend, and hold each Contributor harmless for any liability + incurred by, or claims asserted against, such Contributor by reason + of your accepting any such warranty or additional liability. + + END OF TERMS AND CONDITIONS + + APPENDIX: How to apply the Apache License to your work. + + To apply the Apache License to your work, attach the following + boilerplate notice, with the fields enclosed by brackets "[]" + replaced with your own identifying information. (Don't include + the brackets!) The text should be enclosed in the appropriate + comment syntax for the file format. We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + + Copyright [yyyy] [name of copyright owner] + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/README.md b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/README.md new file mode 100644 index 0000000000..df73b4cd3f --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/README.md @@ -0,0 +1,36 @@ +# STM32CubeWBA CMSIS Device MCU Component + +![latest tag](https://img.shields.io/github/v/tag/STMicroelectronics/cmsis_device_wba.svg?color=brightgreen) + +## Overview + +**STM32Cube** is a STMicroelectronics original initiative aimed at making life easier for developers by reducing effort, time and cost. + +**STM32Cube** covers the overall STM32 products portfolio. It includes a comprehensive embedded software platform delivered for each STM32 series. + * The CMSIS modules (core and device) corresponding to the ARM(tm) core implemented in this STM32 product. + * The STM32 HAL-LL drivers, an abstraction layer offering a set of APIs ensuring maximized portability across the STM32 portfolio. + * The BSP drivers of each evaluation, demonstration, or nucleo board provided for this STM32 series. + * A consistent set of middleware libraries such as WPAN, ThreadX, FileX, USBX, NetXDuo, OpenBootloader, trustedfirmware, mbed-crypto... + * A full set of software projects (basic examples, applications, and demonstrations) for each board, each project developed in three flavors using three toolchains (EWARM, MDK-ARM, and STM32CubeIDE). + +Two models of publication are proposed for the STM32Cube embedded software: + * The monolithic **MCU Package**: all STM32Cube software modules of one STM32 series are present (Drivers, Middleware, Projects, Utilities) in the repository (usual name **STM32Cubexx**, xx corresponding to the STM32 series). + * The **MCU component**: each STM32Cube software module being part of the STM32Cube MCU Package, is delivered as an individual repository, allowing the user to select and get only the required software functions. + +## Description + +This **cmsis_device_wba** MCU component repo is one element of the STM32CubeWBA MCU embedded software package, providing the **cmsis device** part. + +## Release note + +Details about the content of this release are available in the release note [here](https://htmlpreview.github.io/?https://github.com/STMicroelectronics/cmsis_device_wba/blob/main/Release_Notes.html). + +## Compatibility information + +It is **crucial** that you use a consistent set of versions for the CMSIS Core - CMSIS Device, as mentioned in [this](https://htmlpreview.github.io/?https://github.com/STMicroelectronics/STM32CubeWBA/blob/main/Release_Notes.html) release note. + +The full **STM32CubeWBA** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeWBA). + +## Troubleshooting + +Please refer to the [CONTRIBUTING.md](CONTRIBUTING.md) guide. diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Release_Notes.html b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Release_Notes.html new file mode 100644 index 0000000000..572d83e938 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Release_Notes.html @@ -0,0 +1,145 @@ + + + + + + + Release Notes for STM32WBAxx CMSIS + + + + + + +
+
+
+

Release Notes for

+

STM32WBAxx CMSIS

+

Copyright © 2022 STMicroelectronics
+

+ +
+

Purpose

+

This driver provides the CMSIS device for the STM32WBAxx products. This covers

+
    +
  • STM32WBA52xx devices
    • +
  • STM32WBA55xx devices
    • +
+

This driver is composed of the description of the registers under “Include” directory.

+

Various template file are provided to easily build an application. They can be adapted to fit applications requirements.

+
    +
  • Templates/system_stm32wbaxx.c contains the initialization code referred as SystemInit.
    • +
  • Startup files are provided as example for EWARM©, MDK-ARM©, STM32CubeIDE©.
    • +
  • Linker files are provided as example for EWARM©, MDK-ARM©, STM32CubeIDE©.
    • +
+
+
+

Update History

+
+ +
+

Main Changes

+

Official Release of STM32CubeWBA Firmware package supporting STM32WBA52xx and STM32WBA55xx devices

+

Contents

+

Official Release of CMSIS devices drivers supporting STM32WBA52xx and STM32WBA55xx devices

+
    +
  • Update CMSIS devices to include latest corrections +
      +
    • Add support of WKUP_S_IRQn and RCC_AUDIOSYNC_IRQn interrupts in CMSIS devices, startup_stm32wba5xxx.s and partition_stmwba5xxx.h files
      • +
    • Update Licensing header in partition_stm325xxx.h files based on partition_ARMCM33.h
      • +
    • Update declaration of g_pfnVectors size in gcc/startup_stm32wba5xxx.s files
      • +
    • +
+


+

+

Known Limitations

+
    +
  • None
    • +
+

Dependencies

+
    +
  • None
    • +
+

Notes

+
    +
  • None
    • +
+
+
+
+ +
+

Main Changes

+

Official Release of STM32CubeWBA Firmware package supporting STM32WBA52xx devices

+

Contents

+

Official Release of CMSIS devices drivers supporting STM32WBA52xx devices

+
    +
  • Update CMSIS devices to include latest corrections +
      +
    • Align SAU region end address on Flash end address
      • +
    • +
+


+

+

Known Limitations

+
    +
  • None
    • +
+

Dependencies

+
    +
  • None
    • +
+

Notes

+
    +
  • None
    • +
+
+
+
+ +
+

Main Changes

+

First Official Release of STM32CubeWBA Firmware package supporting STM32WBA52xx devices

+

Contents

+
    +
  • First official release of CMSIS devices drivers +
      +
    • Support of STM32WBA52xx devices
      • +
    • +
+

Known Limitations

+
    +
  • None
    • +
+

Dependencies

+
    +
  • None
    • +
+

Notes

+
    +
  • None
    • +
+
+
+
+
+
+
+
+

For complete documentation on STM32WBAxx, visit: www.st.com/stm32wba

+

This release note uses up to date web standards and, for this reason, should not be opened with Internet Explorer but preferably with popular browsers such as Google Chrome, Mozilla Firefox, Opera or Microsoft Edge.

+
+

Info

+
+
+
+ + diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA50xx_FLASH.ld b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA50xx_FLASH.ld new file mode 100644 index 0000000000..efadacdd03 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA50xx_FLASH.ld @@ -0,0 +1,185 @@ +/* +****************************************************************************** +** +** File : LinkerScript.ld +** +** Author : STM32CubeIDE +** +** Abstract : Linker script for STM32WBA50xx Device from STM32WBA series +** 512Kbytes FLASH +** 16Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2022 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 16K + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM : { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} \ No newline at end of file diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA50xx_RAM.ld b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA50xx_RAM.ld new file mode 100644 index 0000000000..a2f5c4d133 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA50xx_RAM.ld @@ -0,0 +1,185 @@ +/* +****************************************************************************** +** +** File : LinkerScript.ld +** +** Author : STM32CubeIDE +** +** Abstract : Linker script for STM32WBA50xx Device from STM32WBA series +** 512Kbytes FLASH +** 64Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2022 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20010000, LENGTH = 48K + FLASH (rx) : ORIGIN = 0x20000000, LENGTH = 16K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM : { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} \ No newline at end of file diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA52xx_FLASH.ld b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA52xx_FLASH.ld new file mode 100644 index 0000000000..82b2f381cf --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA52xx_FLASH.ld @@ -0,0 +1,185 @@ +/* +****************************************************************************** +** +** File : LinkerScript.ld +** +** Author : STM32CubeIDE +** +** Abstract : Linker script for STM32WBA52xx Device from STM32WBA series +** 1024Kbytes FLASH +** 128Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2022 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM : { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} \ No newline at end of file diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA52xx_FLASH_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA52xx_FLASH_ns.ld new file mode 100644 index 0000000000..1f84c70513 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA52xx_FLASH_ns.ld @@ -0,0 +1,185 @@ +/* +****************************************************************************** +** +** File : LinkerScript.ld +** +** Author : STM32CubeIDE +** +** Abstract : Linker script for STM32WBA52xx Device from STM32WBA series +** 1024Kbytes FLASH +** 128Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2022 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20010000, LENGTH = 64K + FLASH (rx) : ORIGIN = 0x08080000, LENGTH = 512K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM : { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} \ No newline at end of file diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA52xx_FLASH_s.ld b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA52xx_FLASH_s.ld new file mode 100644 index 0000000000..dc5b2f874b --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA52xx_FLASH_s.ld @@ -0,0 +1,193 @@ +/* +****************************************************************************** +** +** File : LinkerScript.ld +** +** Author : STM32CubeIDE +** +** Abstract : Linker script for STM32WBA52xx Device from STM32WBA series +** 1024Kbytes FLASH +** 128Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2022 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x30000000, LENGTH = 64K + FLASH (rx) : ORIGIN = 0x0C000000, LENGTH = 504K + FLASH_NSC (rx) : ORIGIN = 0x0C07E000, LENGTH = 8K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM : { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + .gnu.sgstubs : + { + . = ALIGN(4); + *(.gnu.sgstubs*) /* Secure Gateway stubs */ + . = ALIGN(4); + } >FLASH_NSC + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} \ No newline at end of file diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA52xx_RAM.ld b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA52xx_RAM.ld new file mode 100644 index 0000000000..f13e43e293 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA52xx_RAM.ld @@ -0,0 +1,185 @@ +/* +****************************************************************************** +** +** File : LinkerScript.ld +** +** Author : STM32CubeIDE +** +** Abstract : Linker script for STM32WBA52xx Device from STM32WBA series +** 1024Kbytes FLASH +** 128Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2022 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20010000, LENGTH = 64K + FLASH (rx) : ORIGIN = 0x20000000, LENGTH = 64K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM : { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} \ No newline at end of file diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA52xx_RAM_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA52xx_RAM_ns.ld new file mode 100644 index 0000000000..bceb65c93d --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA52xx_RAM_ns.ld @@ -0,0 +1,185 @@ +/* +****************************************************************************** +** +** File : LinkerScript.ld +** +** Author : STM32CubeIDE +** +** Abstract : Linker script for STM32WBA52xx Device from STM32WBA series +** 1024Kbytes FLASH +** 128Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2022 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20018000, LENGTH = 32K + FLASH (rx) : ORIGIN = 0x20010000, LENGTH = 32K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM : { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} \ No newline at end of file diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA52xx_RAM_s.ld b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA52xx_RAM_s.ld new file mode 100644 index 0000000000..194febae17 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA52xx_RAM_s.ld @@ -0,0 +1,193 @@ +/* +****************************************************************************** +** +** File : LinkerScript.ld +** +** Author : STM32CubeIDE +** +** Abstract : Linker script for STM32WBA52xx Device from STM32WBA series +** 1024Kbytes FLASH +** 128Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2022 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x30008000, LENGTH = 32K + FLASH (rx) : ORIGIN = 0x30000000, LENGTH = 32256 + FLASH_NSC (rx) : ORIGIN = 0x30007E00, LENGTH = 512 +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM : { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + .gnu.sgstubs : + { + . = ALIGN(4); + *(.gnu.sgstubs*) /* Secure Gateway stubs */ + . = ALIGN(4); + } >FLASH_NSC + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} \ No newline at end of file diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA54xx_FLASH.ld b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA54xx_FLASH.ld new file mode 100644 index 0000000000..5333b36395 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA54xx_FLASH.ld @@ -0,0 +1,185 @@ +/* +****************************************************************************** +** +** File : LinkerScript.ld +** +** Author : STM32CubeIDE +** +** Abstract : Linker script for STM32WBA54xx Device from STM32WBA series +** 1024Kbytes FLASH +** 128Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2022 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM : { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} \ No newline at end of file diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA54xx_FLASH_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA54xx_FLASH_ns.ld new file mode 100644 index 0000000000..256d0f96d8 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA54xx_FLASH_ns.ld @@ -0,0 +1,185 @@ +/* +****************************************************************************** +** +** File : LinkerScript.ld +** +** Author : STM32CubeIDE +** +** Abstract : Linker script for STM32WBA54xx Device from STM32WBA series +** 1024Kbytes FLASH +** 128Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2022 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20010000, LENGTH = 64K + FLASH (rx) : ORIGIN = 0x08080000, LENGTH = 512K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM : { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} \ No newline at end of file diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA54xx_FLASH_s.ld b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA54xx_FLASH_s.ld new file mode 100644 index 0000000000..26dfeb4ac4 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA54xx_FLASH_s.ld @@ -0,0 +1,193 @@ +/* +****************************************************************************** +** +** File : LinkerScript.ld +** +** Author : STM32CubeIDE +** +** Abstract : Linker script for STM32WBA54xx Device from STM32WBA series +** 1024Kbytes FLASH +** 128Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2022 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x30000000, LENGTH = 64K + FLASH (rx) : ORIGIN = 0x0C000000, LENGTH = 504K + FLASH_NSC (rx) : ORIGIN = 0x0C07E000, LENGTH = 8K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM : { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + .gnu.sgstubs : + { + . = ALIGN(4); + *(.gnu.sgstubs*) /* Secure Gateway stubs */ + . = ALIGN(4); + } >FLASH_NSC + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} \ No newline at end of file diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA54xx_RAM.ld b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA54xx_RAM.ld new file mode 100644 index 0000000000..92955d4e79 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA54xx_RAM.ld @@ -0,0 +1,185 @@ +/* +****************************************************************************** +** +** File : LinkerScript.ld +** +** Author : STM32CubeIDE +** +** Abstract : Linker script for STM32WBA54xx Device from STM32WBA series +** 1024Kbytes FLASH +** 128Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2022 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20010000, LENGTH = 64K + FLASH (rx) : ORIGIN = 0x20000000, LENGTH = 64K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM : { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} \ No newline at end of file diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA54xx_RAM_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA54xx_RAM_ns.ld new file mode 100644 index 0000000000..f7a3b9cce1 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA54xx_RAM_ns.ld @@ -0,0 +1,185 @@ +/* +****************************************************************************** +** +** File : LinkerScript.ld +** +** Author : STM32CubeIDE +** +** Abstract : Linker script for STM32WBA54xx Device from STM32WBA series +** 1024Kbytes FLASH +** 128Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2022 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20018000, LENGTH = 32K + FLASH (rx) : ORIGIN = 0x20010000, LENGTH = 32K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM : { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} \ No newline at end of file diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA54xx_RAM_s.ld b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA54xx_RAM_s.ld new file mode 100644 index 0000000000..1aa0fdccfc --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA54xx_RAM_s.ld @@ -0,0 +1,193 @@ +/* +****************************************************************************** +** +** File : LinkerScript.ld +** +** Author : STM32CubeIDE +** +** Abstract : Linker script for STM32WBA54xx Device from STM32WBA series +** 1024Kbytes FLASH +** 128Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2022 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x30008000, LENGTH = 32K + FLASH (rx) : ORIGIN = 0x30000000, LENGTH = 32256 + FLASH_NSC (rx) : ORIGIN = 0x30007E00, LENGTH = 512 +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM : { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + .gnu.sgstubs : + { + . = ALIGN(4); + *(.gnu.sgstubs*) /* Secure Gateway stubs */ + . = ALIGN(4); + } >FLASH_NSC + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} \ No newline at end of file diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA55xx_FLASH.ld b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA55xx_FLASH.ld new file mode 100644 index 0000000000..e67c850c5e --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA55xx_FLASH.ld @@ -0,0 +1,185 @@ +/* +****************************************************************************** +** +** File : LinkerScript.ld +** +** Author : STM32CubeIDE +** +** Abstract : Linker script for STM32WBA55xx Device from STM32WBA series +** 1024Kbytes FLASH +** 128Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2022 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM : { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} \ No newline at end of file diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA55xx_FLASH_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA55xx_FLASH_ns.ld new file mode 100644 index 0000000000..0f533e7b95 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA55xx_FLASH_ns.ld @@ -0,0 +1,185 @@ +/* +****************************************************************************** +** +** File : LinkerScript.ld +** +** Author : STM32CubeIDE +** +** Abstract : Linker script for STM32WBA55xx Device from STM32WBA series +** 1024Kbytes FLASH +** 128Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2022 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20010000, LENGTH = 64K + FLASH (rx) : ORIGIN = 0x08080000, LENGTH = 512K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM : { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} \ No newline at end of file diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA55xx_FLASH_s.ld b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA55xx_FLASH_s.ld new file mode 100644 index 0000000000..8e672f64c0 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA55xx_FLASH_s.ld @@ -0,0 +1,193 @@ +/* +****************************************************************************** +** +** File : LinkerScript.ld +** +** Author : STM32CubeIDE +** +** Abstract : Linker script for STM32WBA55xx Device from STM32WBA series +** 1024Kbytes FLASH +** 128Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2022 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x30000000, LENGTH = 64K + FLASH (rx) : ORIGIN = 0x0C000000, LENGTH = 504K + FLASH_NSC (rx) : ORIGIN = 0x0C07E000, LENGTH = 8K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM : { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + .gnu.sgstubs : + { + . = ALIGN(4); + *(.gnu.sgstubs*) /* Secure Gateway stubs */ + . = ALIGN(4); + } >FLASH_NSC + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} \ No newline at end of file diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA55xx_RAM.ld b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA55xx_RAM.ld new file mode 100644 index 0000000000..6b8d81543c --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA55xx_RAM.ld @@ -0,0 +1,185 @@ +/* +****************************************************************************** +** +** File : LinkerScript.ld +** +** Author : STM32CubeIDE +** +** Abstract : Linker script for STM32WBA55xx Device from STM32WBA series +** 1024Kbytes FLASH +** 128Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2022 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20010000, LENGTH = 64K + FLASH (rx) : ORIGIN = 0x20000000, LENGTH = 64K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM : { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} \ No newline at end of file diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA55xx_RAM_ns.ld b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA55xx_RAM_ns.ld new file mode 100644 index 0000000000..ca67ca61b3 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA55xx_RAM_ns.ld @@ -0,0 +1,185 @@ +/* +****************************************************************************** +** +** File : LinkerScript.ld +** +** Author : STM32CubeIDE +** +** Abstract : Linker script for STM32WBA55xx Device from STM32WBA series +** 1024Kbytes FLASH +** 128Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2022 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20018000, LENGTH = 32K + FLASH (rx) : ORIGIN = 0x20010000, LENGTH = 32K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM : { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} \ No newline at end of file diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA55xx_RAM_s.ld b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA55xx_RAM_s.ld new file mode 100644 index 0000000000..810b150d95 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/linker/STM32WBA55xx_RAM_s.ld @@ -0,0 +1,193 @@ +/* +****************************************************************************** +** +** File : LinkerScript.ld +** +** Author : STM32CubeIDE +** +** Abstract : Linker script for STM32WBA55xx Device from STM32WBA series +** 1024Kbytes FLASH +** 128Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2022 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x30008000, LENGTH = 32K + FLASH (rx) : ORIGIN = 0x30000000, LENGTH = 32256 + FLASH_NSC (rx) : ORIGIN = 0x30007E00, LENGTH = 512 +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM : { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + .gnu.sgstubs : + { + . = ALIGN(4); + *(.gnu.sgstubs*) /* Secure Gateway stubs */ + . = ALIGN(4); + } >FLASH_NSC + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} \ No newline at end of file diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/startup_stm32wba50xx.s b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/startup_stm32wba50xx.s new file mode 100644 index 0000000000..8047165747 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/startup_stm32wba50xx.s @@ -0,0 +1,423 @@ +/** + ****************************************************************************** + * @file startup_stm32wba50xx.s + * @author MCD Application Team + * @brief STM32WBA50xx devices vector table GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address, + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M33 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ******************************************************************************* + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ******************************************************************************* + */ + + .syntax unified + .cpu cortex-m33 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF1E0F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + +/* Call the clock system initialization function.*/ + bl SystemInit + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex-M33. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word SecureFault_Handler + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word RTC_IRQHandler + .word 0 + .word TAMP_IRQHandler + .word RAMCFG_IRQHandler + .word FLASH_IRQHandler + .word 0 + .word 0 + .word RCC_IRQHandler + .word 0 + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word EXTI5_IRQHandler + .word EXTI6_IRQHandler + .word EXTI7_IRQHandler + .word EXTI8_IRQHandler + .word EXTI9_IRQHandler + .word EXTI10_IRQHandler + .word EXTI11_IRQHandler + .word EXTI12_IRQHandler + .word EXTI13_IRQHandler + .word EXTI14_IRQHandler + .word EXTI15_IRQHandler + .word IWDG_IRQHandler + .word 0 + .word GPDMA1_Channel0_IRQHandler + .word GPDMA1_Channel1_IRQHandler + .word GPDMA1_Channel2_IRQHandler + .word GPDMA1_Channel3_IRQHandler + .word GPDMA1_Channel4_IRQHandler + .word GPDMA1_Channel5_IRQHandler + .word GPDMA1_Channel6_IRQHandler + .word GPDMA1_Channel7_IRQHandler + .word TIM1_BRK_IRQHandler + .word TIM1_UP_IRQHandler + .word TIM1_TRG_COM_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word USART1_IRQHandler + .word 0 + .word LPUART1_IRQHandler + .word LPTIM1_IRQHandler + .word 0 + .word TIM16_IRQHandler + .word 0 + .word 0 + .word I2C3_EV_IRQHandler + .word I2C3_ER_IRQHandler + .word 0 + .word TSC_IRQHandler + .word AES_IRQHandler + .word RNG_IRQHandler + .word FPU_IRQHandler + .word HASH_IRQHandler + .word PKA_IRQHandler + .word SPI3_IRQHandler + .word ICACHE_IRQHandler + .word ADC4_IRQHandler + .word RADIO_IRQHandler + .word WKUP_IRQHandler + .word HSEM_IRQHandler + + .size g_pfnVectors, .-g_pfnVectors + + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SecureFault_Handler + .thumb_set SecureFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak TAMP_IRQHandler + .thumb_set TAMP_IRQHandler,Default_Handler + + .weak RAMCFG_IRQHandler + .thumb_set RAMCFG_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak EXTI5_IRQHandler + .thumb_set EXTI5_IRQHandler,Default_Handler + + .weak EXTI6_IRQHandler + .thumb_set EXTI6_IRQHandler,Default_Handler + + .weak EXTI7_IRQHandler + .thumb_set EXTI7_IRQHandler,Default_Handler + + .weak EXTI8_IRQHandler + .thumb_set EXTI8_IRQHandler,Default_Handler + + .weak EXTI9_IRQHandler + .thumb_set EXTI9_IRQHandler,Default_Handler + + .weak EXTI10_IRQHandler + .thumb_set EXTI10_IRQHandler,Default_Handler + + .weak EXTI11_IRQHandler + .thumb_set EXTI11_IRQHandler,Default_Handler + + .weak EXTI12_IRQHandler + .thumb_set EXTI12_IRQHandler,Default_Handler + + .weak EXTI13_IRQHandler + .thumb_set EXTI13_IRQHandler,Default_Handler + + .weak EXTI14_IRQHandler + .thumb_set EXTI14_IRQHandler,Default_Handler + + .weak EXTI15_IRQHandler + .thumb_set EXTI15_IRQHandler,Default_Handler + + .weak IWDG_IRQHandler + .thumb_set IWDG_IRQHandler,Default_Handler + + .weak GPDMA1_Channel0_IRQHandler + .thumb_set GPDMA1_Channel0_IRQHandler,Default_Handler + + .weak GPDMA1_Channel1_IRQHandler + .thumb_set GPDMA1_Channel1_IRQHandler,Default_Handler + + .weak GPDMA1_Channel2_IRQHandler + .thumb_set GPDMA1_Channel2_IRQHandler,Default_Handler + + .weak GPDMA1_Channel3_IRQHandler + .thumb_set GPDMA1_Channel3_IRQHandler,Default_Handler + + .weak GPDMA1_Channel4_IRQHandler + .thumb_set GPDMA1_Channel4_IRQHandler,Default_Handler + + .weak GPDMA1_Channel5_IRQHandler + .thumb_set GPDMA1_Channel5_IRQHandler,Default_Handler + + .weak GPDMA1_Channel6_IRQHandler + .thumb_set GPDMA1_Channel6_IRQHandler,Default_Handler + + .weak GPDMA1_Channel7_IRQHandler + .thumb_set GPDMA1_Channel7_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak LPUART1_IRQHandler + .thumb_set LPUART1_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak TSC_IRQHandler + .thumb_set TSC_IRQHandler,Default_Handler + + .weak AES_IRQHandler + .thumb_set AES_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak HASH_IRQHandler + .thumb_set HASH_IRQHandler,Default_Handler + + .weak PKA_IRQHandler + .thumb_set PKA_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak ICACHE_IRQHandler + .thumb_set ICACHE_IRQHandler,Default_Handler + + .weak ADC4_IRQHandler + .thumb_set ADC4_IRQHandler,Default_Handler + + .weak RADIO_IRQHandler + .thumb_set RADIO_IRQHandler,Default_Handler + + .weak WKUP_IRQHandler + .thumb_set WKUP_IRQHandler,Default_Handler + + .weak HSEM_IRQHandler + .thumb_set HSEM_IRQHandler,Default_Handler diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/startup_stm32wba52xx.s b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/startup_stm32wba52xx.s new file mode 100644 index 0000000000..ad128040f1 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/startup_stm32wba52xx.s @@ -0,0 +1,464 @@ +/** + ****************************************************************************** + * @file startup_stm32wba52xx.s + * @author MCD Application Team + * @brief STM32WBA52xx devices vector table GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address, + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M33 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ******************************************************************************* + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ******************************************************************************* + */ + + .syntax unified + .cpu cortex-m33 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF1E0F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + +/* Call the clock system initialization function.*/ + bl SystemInit + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex-M33. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word SecureFault_Handler + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word RTC_IRQHandler + .word RTC_S_IRQHandler + .word TAMP_IRQHandler + .word RAMCFG_IRQHandler + .word FLASH_IRQHandler + .word FLASH_S_IRQHandler + .word GTZC_IRQHandler + .word RCC_IRQHandler + .word RCC_S_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word EXTI5_IRQHandler + .word EXTI6_IRQHandler + .word EXTI7_IRQHandler + .word EXTI8_IRQHandler + .word EXTI9_IRQHandler + .word EXTI10_IRQHandler + .word EXTI11_IRQHandler + .word EXTI12_IRQHandler + .word EXTI13_IRQHandler + .word EXTI14_IRQHandler + .word EXTI15_IRQHandler + .word IWDG_IRQHandler + .word SAES_IRQHandler + .word GPDMA1_Channel0_IRQHandler + .word GPDMA1_Channel1_IRQHandler + .word GPDMA1_Channel2_IRQHandler + .word GPDMA1_Channel3_IRQHandler + .word GPDMA1_Channel4_IRQHandler + .word GPDMA1_Channel5_IRQHandler + .word GPDMA1_Channel6_IRQHandler + .word GPDMA1_Channel7_IRQHandler + .word TIM1_BRK_IRQHandler + .word TIM1_UP_IRQHandler + .word TIM1_TRG_COM_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word SPI1_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word LPUART1_IRQHandler + .word LPTIM1_IRQHandler + .word LPTIM2_IRQHandler + .word TIM16_IRQHandler + .word TIM17_IRQHandler + .word 0 + .word I2C3_EV_IRQHandler + .word I2C3_ER_IRQHandler + .word 0 + .word TSC_IRQHandler + .word AES_IRQHandler + .word RNG_IRQHandler + .word FPU_IRQHandler + .word HASH_IRQHandler + .word PKA_IRQHandler + .word SPI3_IRQHandler + .word ICACHE_IRQHandler + .word ADC4_IRQHandler + .word RADIO_IRQHandler + .word WKUP_IRQHandler + .word HSEM_IRQHandler + .word HSEM_S_IRQHandler + .word WKUP_S_IRQHandler + + .size g_pfnVectors, .-g_pfnVectors + + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SecureFault_Handler + .thumb_set SecureFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak RTC_S_IRQHandler + .thumb_set RTC_S_IRQHandler,Default_Handler + + .weak TAMP_IRQHandler + .thumb_set TAMP_IRQHandler,Default_Handler + + .weak RAMCFG_IRQHandler + .thumb_set RAMCFG_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak FLASH_S_IRQHandler + .thumb_set FLASH_S_IRQHandler,Default_Handler + + .weak GTZC_IRQHandler + .thumb_set GTZC_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak RCC_S_IRQHandler + .thumb_set RCC_S_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak EXTI5_IRQHandler + .thumb_set EXTI5_IRQHandler,Default_Handler + + .weak EXTI6_IRQHandler + .thumb_set EXTI6_IRQHandler,Default_Handler + + .weak EXTI7_IRQHandler + .thumb_set EXTI7_IRQHandler,Default_Handler + + .weak EXTI8_IRQHandler + .thumb_set EXTI8_IRQHandler,Default_Handler + + .weak EXTI9_IRQHandler + .thumb_set EXTI9_IRQHandler,Default_Handler + + .weak EXTI10_IRQHandler + .thumb_set EXTI10_IRQHandler,Default_Handler + + .weak EXTI11_IRQHandler + .thumb_set EXTI11_IRQHandler,Default_Handler + + .weak EXTI12_IRQHandler + .thumb_set EXTI12_IRQHandler,Default_Handler + + .weak EXTI13_IRQHandler + .thumb_set EXTI13_IRQHandler,Default_Handler + + .weak EXTI14_IRQHandler + .thumb_set EXTI14_IRQHandler,Default_Handler + + .weak EXTI15_IRQHandler + .thumb_set EXTI15_IRQHandler,Default_Handler + + .weak IWDG_IRQHandler + .thumb_set IWDG_IRQHandler,Default_Handler + + .weak SAES_IRQHandler + .thumb_set SAES_IRQHandler,Default_Handler + + .weak GPDMA1_Channel0_IRQHandler + .thumb_set GPDMA1_Channel0_IRQHandler,Default_Handler + + .weak GPDMA1_Channel1_IRQHandler + .thumb_set GPDMA1_Channel1_IRQHandler,Default_Handler + + .weak GPDMA1_Channel2_IRQHandler + .thumb_set GPDMA1_Channel2_IRQHandler,Default_Handler + + .weak GPDMA1_Channel3_IRQHandler + .thumb_set GPDMA1_Channel3_IRQHandler,Default_Handler + + .weak GPDMA1_Channel4_IRQHandler + .thumb_set GPDMA1_Channel4_IRQHandler,Default_Handler + + .weak GPDMA1_Channel5_IRQHandler + .thumb_set GPDMA1_Channel5_IRQHandler,Default_Handler + + .weak GPDMA1_Channel6_IRQHandler + .thumb_set GPDMA1_Channel6_IRQHandler,Default_Handler + + .weak GPDMA1_Channel7_IRQHandler + .thumb_set GPDMA1_Channel7_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak LPUART1_IRQHandler + .thumb_set LPUART1_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak LPTIM2_IRQHandler + .thumb_set LPTIM2_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak TSC_IRQHandler + .thumb_set TSC_IRQHandler,Default_Handler + + .weak AES_IRQHandler + .thumb_set AES_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak HASH_IRQHandler + .thumb_set HASH_IRQHandler,Default_Handler + + .weak PKA_IRQHandler + .thumb_set PKA_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak ICACHE_IRQHandler + .thumb_set ICACHE_IRQHandler,Default_Handler + + .weak ADC4_IRQHandler + .thumb_set ADC4_IRQHandler,Default_Handler + + .weak RADIO_IRQHandler + .thumb_set RADIO_IRQHandler,Default_Handler + + .weak WKUP_IRQHandler + .thumb_set WKUP_IRQHandler,Default_Handler + + .weak HSEM_IRQHandler + .thumb_set HSEM_IRQHandler,Default_Handler + + .weak HSEM_S_IRQHandler + .thumb_set HSEM_S_IRQHandler,Default_Handler + + .weak WKUP_S_IRQHandler + .thumb_set WKUP_S_IRQHandler,Default_Handler diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/startup_stm32wba54xx.s b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/startup_stm32wba54xx.s new file mode 100644 index 0000000000..a653fe4d2a --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/startup_stm32wba54xx.s @@ -0,0 +1,474 @@ +/** + ****************************************************************************** + * @file startup_stm32wba54xx.s + * @author MCD Application Team + * @brief STM32WBA54xx devices vector table GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address, + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M33 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ******************************************************************************* + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ******************************************************************************* + */ + + .syntax unified + .cpu cortex-m33 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF1E0F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + +/* Call the clock system initialization function.*/ + bl SystemInit + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex-M33. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word SecureFault_Handler + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word RTC_IRQHandler + .word RTC_S_IRQHandler + .word TAMP_IRQHandler + .word RAMCFG_IRQHandler + .word FLASH_IRQHandler + .word FLASH_S_IRQHandler + .word GTZC_IRQHandler + .word RCC_IRQHandler + .word RCC_S_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word EXTI5_IRQHandler + .word EXTI6_IRQHandler + .word EXTI7_IRQHandler + .word EXTI8_IRQHandler + .word EXTI9_IRQHandler + .word EXTI10_IRQHandler + .word EXTI11_IRQHandler + .word EXTI12_IRQHandler + .word EXTI13_IRQHandler + .word EXTI14_IRQHandler + .word EXTI15_IRQHandler + .word IWDG_IRQHandler + .word SAES_IRQHandler + .word GPDMA1_Channel0_IRQHandler + .word GPDMA1_Channel1_IRQHandler + .word GPDMA1_Channel2_IRQHandler + .word GPDMA1_Channel3_IRQHandler + .word GPDMA1_Channel4_IRQHandler + .word GPDMA1_Channel5_IRQHandler + .word GPDMA1_Channel6_IRQHandler + .word GPDMA1_Channel7_IRQHandler + .word TIM1_BRK_IRQHandler + .word TIM1_UP_IRQHandler + .word TIM1_TRG_COM_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word SPI1_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word LPUART1_IRQHandler + .word LPTIM1_IRQHandler + .word LPTIM2_IRQHandler + .word TIM16_IRQHandler + .word TIM17_IRQHandler + .word COMP_IRQHandler + .word I2C3_EV_IRQHandler + .word I2C3_ER_IRQHandler + .word SAI1_IRQHandler + .word TSC_IRQHandler + .word AES_IRQHandler + .word RNG_IRQHandler + .word FPU_IRQHandler + .word HASH_IRQHandler + .word PKA_IRQHandler + .word SPI3_IRQHandler + .word ICACHE_IRQHandler + .word ADC4_IRQHandler + .word RADIO_IRQHandler + .word WKUP_IRQHandler + .word HSEM_IRQHandler + .word HSEM_S_IRQHandler + .word WKUP_S_IRQHandler + .word RCC_AUDIOSYNC_IRQHandler + + .size g_pfnVectors, .-g_pfnVectors + + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SecureFault_Handler + .thumb_set SecureFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak RTC_S_IRQHandler + .thumb_set RTC_S_IRQHandler,Default_Handler + + .weak TAMP_IRQHandler + .thumb_set TAMP_IRQHandler,Default_Handler + + .weak RAMCFG_IRQHandler + .thumb_set RAMCFG_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak FLASH_S_IRQHandler + .thumb_set FLASH_S_IRQHandler,Default_Handler + + .weak GTZC_IRQHandler + .thumb_set GTZC_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak RCC_S_IRQHandler + .thumb_set RCC_S_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak EXTI5_IRQHandler + .thumb_set EXTI5_IRQHandler,Default_Handler + + .weak EXTI6_IRQHandler + .thumb_set EXTI6_IRQHandler,Default_Handler + + .weak EXTI7_IRQHandler + .thumb_set EXTI7_IRQHandler,Default_Handler + + .weak EXTI8_IRQHandler + .thumb_set EXTI8_IRQHandler,Default_Handler + + .weak EXTI9_IRQHandler + .thumb_set EXTI9_IRQHandler,Default_Handler + + .weak EXTI10_IRQHandler + .thumb_set EXTI10_IRQHandler,Default_Handler + + .weak EXTI11_IRQHandler + .thumb_set EXTI11_IRQHandler,Default_Handler + + .weak EXTI12_IRQHandler + .thumb_set EXTI12_IRQHandler,Default_Handler + + .weak EXTI13_IRQHandler + .thumb_set EXTI13_IRQHandler,Default_Handler + + .weak EXTI14_IRQHandler + .thumb_set EXTI14_IRQHandler,Default_Handler + + .weak EXTI15_IRQHandler + .thumb_set EXTI15_IRQHandler,Default_Handler + + .weak IWDG_IRQHandler + .thumb_set IWDG_IRQHandler,Default_Handler + + .weak SAES_IRQHandler + .thumb_set SAES_IRQHandler,Default_Handler + + .weak GPDMA1_Channel0_IRQHandler + .thumb_set GPDMA1_Channel0_IRQHandler,Default_Handler + + .weak GPDMA1_Channel1_IRQHandler + .thumb_set GPDMA1_Channel1_IRQHandler,Default_Handler + + .weak GPDMA1_Channel2_IRQHandler + .thumb_set GPDMA1_Channel2_IRQHandler,Default_Handler + + .weak GPDMA1_Channel3_IRQHandler + .thumb_set GPDMA1_Channel3_IRQHandler,Default_Handler + + .weak GPDMA1_Channel4_IRQHandler + .thumb_set GPDMA1_Channel4_IRQHandler,Default_Handler + + .weak GPDMA1_Channel5_IRQHandler + .thumb_set GPDMA1_Channel5_IRQHandler,Default_Handler + + .weak GPDMA1_Channel6_IRQHandler + .thumb_set GPDMA1_Channel6_IRQHandler,Default_Handler + + .weak GPDMA1_Channel7_IRQHandler + .thumb_set GPDMA1_Channel7_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak LPUART1_IRQHandler + .thumb_set LPUART1_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak LPTIM2_IRQHandler + .thumb_set LPTIM2_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak COMP_IRQHandler + .thumb_set COMP_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak SAI1_IRQHandler + .thumb_set SAI1_IRQHandler,Default_Handler + + .weak TSC_IRQHandler + .thumb_set TSC_IRQHandler,Default_Handler + + .weak AES_IRQHandler + .thumb_set AES_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak HASH_IRQHandler + .thumb_set HASH_IRQHandler,Default_Handler + + .weak PKA_IRQHandler + .thumb_set PKA_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak ICACHE_IRQHandler + .thumb_set ICACHE_IRQHandler,Default_Handler + + .weak ADC4_IRQHandler + .thumb_set ADC4_IRQHandler,Default_Handler + + .weak RADIO_IRQHandler + .thumb_set RADIO_IRQHandler,Default_Handler + + .weak WKUP_IRQHandler + .thumb_set WKUP_IRQHandler,Default_Handler + + .weak HSEM_IRQHandler + .thumb_set HSEM_IRQHandler,Default_Handler + + .weak HSEM_S_IRQHandler + .thumb_set HSEM_S_IRQHandler,Default_Handler + + .weak WKUP_S_IRQHandler + .thumb_set WKUP_S_IRQHandler,Default_Handler + + .weak RCC_AUDIOSYNC_IRQHandler + .thumb_set RCC_AUDIOSYNC_IRQHandler,Default_Handler diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/startup_stm32wba55xx.s b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/startup_stm32wba55xx.s new file mode 100644 index 0000000000..c4a46add7b --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/startup_stm32wba55xx.s @@ -0,0 +1,474 @@ +/** + ****************************************************************************** + * @file startup_stm32wba55xx.s + * @author MCD Application Team + * @brief STM32WBA55xx devices vector table GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address, + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M33 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ******************************************************************************* + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ******************************************************************************* + */ + + .syntax unified + .cpu cortex-m33 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF1E0F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + +/* Call the clock system initialization function.*/ + bl SystemInit + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex-M33. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word SecureFault_Handler + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word RTC_IRQHandler + .word RTC_S_IRQHandler + .word TAMP_IRQHandler + .word RAMCFG_IRQHandler + .word FLASH_IRQHandler + .word FLASH_S_IRQHandler + .word GTZC_IRQHandler + .word RCC_IRQHandler + .word RCC_S_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word EXTI5_IRQHandler + .word EXTI6_IRQHandler + .word EXTI7_IRQHandler + .word EXTI8_IRQHandler + .word EXTI9_IRQHandler + .word EXTI10_IRQHandler + .word EXTI11_IRQHandler + .word EXTI12_IRQHandler + .word EXTI13_IRQHandler + .word EXTI14_IRQHandler + .word EXTI15_IRQHandler + .word IWDG_IRQHandler + .word SAES_IRQHandler + .word GPDMA1_Channel0_IRQHandler + .word GPDMA1_Channel1_IRQHandler + .word GPDMA1_Channel2_IRQHandler + .word GPDMA1_Channel3_IRQHandler + .word GPDMA1_Channel4_IRQHandler + .word GPDMA1_Channel5_IRQHandler + .word GPDMA1_Channel6_IRQHandler + .word GPDMA1_Channel7_IRQHandler + .word TIM1_BRK_IRQHandler + .word TIM1_UP_IRQHandler + .word TIM1_TRG_COM_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word SPI1_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word LPUART1_IRQHandler + .word LPTIM1_IRQHandler + .word LPTIM2_IRQHandler + .word TIM16_IRQHandler + .word TIM17_IRQHandler + .word COMP_IRQHandler + .word I2C3_EV_IRQHandler + .word I2C3_ER_IRQHandler + .word SAI1_IRQHandler + .word TSC_IRQHandler + .word AES_IRQHandler + .word RNG_IRQHandler + .word FPU_IRQHandler + .word HASH_IRQHandler + .word PKA_IRQHandler + .word SPI3_IRQHandler + .word ICACHE_IRQHandler + .word ADC4_IRQHandler + .word RADIO_IRQHandler + .word WKUP_IRQHandler + .word HSEM_IRQHandler + .word HSEM_S_IRQHandler + .word WKUP_S_IRQHandler + .word RCC_AUDIOSYNC_IRQHandler + + .size g_pfnVectors, .-g_pfnVectors + + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SecureFault_Handler + .thumb_set SecureFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak RTC_S_IRQHandler + .thumb_set RTC_S_IRQHandler,Default_Handler + + .weak TAMP_IRQHandler + .thumb_set TAMP_IRQHandler,Default_Handler + + .weak RAMCFG_IRQHandler + .thumb_set RAMCFG_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak FLASH_S_IRQHandler + .thumb_set FLASH_S_IRQHandler,Default_Handler + + .weak GTZC_IRQHandler + .thumb_set GTZC_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak RCC_S_IRQHandler + .thumb_set RCC_S_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak EXTI5_IRQHandler + .thumb_set EXTI5_IRQHandler,Default_Handler + + .weak EXTI6_IRQHandler + .thumb_set EXTI6_IRQHandler,Default_Handler + + .weak EXTI7_IRQHandler + .thumb_set EXTI7_IRQHandler,Default_Handler + + .weak EXTI8_IRQHandler + .thumb_set EXTI8_IRQHandler,Default_Handler + + .weak EXTI9_IRQHandler + .thumb_set EXTI9_IRQHandler,Default_Handler + + .weak EXTI10_IRQHandler + .thumb_set EXTI10_IRQHandler,Default_Handler + + .weak EXTI11_IRQHandler + .thumb_set EXTI11_IRQHandler,Default_Handler + + .weak EXTI12_IRQHandler + .thumb_set EXTI12_IRQHandler,Default_Handler + + .weak EXTI13_IRQHandler + .thumb_set EXTI13_IRQHandler,Default_Handler + + .weak EXTI14_IRQHandler + .thumb_set EXTI14_IRQHandler,Default_Handler + + .weak EXTI15_IRQHandler + .thumb_set EXTI15_IRQHandler,Default_Handler + + .weak IWDG_IRQHandler + .thumb_set IWDG_IRQHandler,Default_Handler + + .weak SAES_IRQHandler + .thumb_set SAES_IRQHandler,Default_Handler + + .weak GPDMA1_Channel0_IRQHandler + .thumb_set GPDMA1_Channel0_IRQHandler,Default_Handler + + .weak GPDMA1_Channel1_IRQHandler + .thumb_set GPDMA1_Channel1_IRQHandler,Default_Handler + + .weak GPDMA1_Channel2_IRQHandler + .thumb_set GPDMA1_Channel2_IRQHandler,Default_Handler + + .weak GPDMA1_Channel3_IRQHandler + .thumb_set GPDMA1_Channel3_IRQHandler,Default_Handler + + .weak GPDMA1_Channel4_IRQHandler + .thumb_set GPDMA1_Channel4_IRQHandler,Default_Handler + + .weak GPDMA1_Channel5_IRQHandler + .thumb_set GPDMA1_Channel5_IRQHandler,Default_Handler + + .weak GPDMA1_Channel6_IRQHandler + .thumb_set GPDMA1_Channel6_IRQHandler,Default_Handler + + .weak GPDMA1_Channel7_IRQHandler + .thumb_set GPDMA1_Channel7_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak LPUART1_IRQHandler + .thumb_set LPUART1_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak LPTIM2_IRQHandler + .thumb_set LPTIM2_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak COMP_IRQHandler + .thumb_set COMP_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak SAI1_IRQHandler + .thumb_set SAI1_IRQHandler,Default_Handler + + .weak TSC_IRQHandler + .thumb_set TSC_IRQHandler,Default_Handler + + .weak AES_IRQHandler + .thumb_set AES_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak HASH_IRQHandler + .thumb_set HASH_IRQHandler,Default_Handler + + .weak PKA_IRQHandler + .thumb_set PKA_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak ICACHE_IRQHandler + .thumb_set ICACHE_IRQHandler,Default_Handler + + .weak ADC4_IRQHandler + .thumb_set ADC4_IRQHandler,Default_Handler + + .weak RADIO_IRQHandler + .thumb_set RADIO_IRQHandler,Default_Handler + + .weak WKUP_IRQHandler + .thumb_set WKUP_IRQHandler,Default_Handler + + .weak HSEM_IRQHandler + .thumb_set HSEM_IRQHandler,Default_Handler + + .weak HSEM_S_IRQHandler + .thumb_set HSEM_S_IRQHandler,Default_Handler + + .weak WKUP_S_IRQHandler + .thumb_set WKUP_S_IRQHandler,Default_Handler + + .weak RCC_AUDIOSYNC_IRQHandler + .thumb_set RCC_AUDIOSYNC_IRQHandler,Default_Handler diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/system_stm32wbaxx.c b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/system_stm32wbaxx.c new file mode 100644 index 0000000000..dfe26150f3 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/system_stm32wbaxx.c @@ -0,0 +1,381 @@ +/** + ****************************************************************************** + * @file system_stm32wbaxx.c + * @author MCD Application Team + * @brief CMSIS Cortex-M33 Device Peripheral Access Layer System Source File + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32wbaxx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32wbaxx.s" file, to + * configure the system clock before to branch to main program. + * + * This file configures the system clock as follows: + *============================================================================= + *----------------------------------------------------------------------------- + * System Clock source | HSI + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 16000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 16000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 1 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 1 + *----------------------------------------------------------------------------- + * PLL1_SRC | No clock + *----------------------------------------------------------------------------- + * PLL1_M | 1 + *----------------------------------------------------------------------------- + * PLL1_N | 128 + *----------------------------------------------------------------------------- + * PLL1_P | 1 + *----------------------------------------------------------------------------- + * PLL1_Q | 1 + *----------------------------------------------------------------------------- + * PLL1_R | 1 + *----------------------------------------------------------------------------- + * Require 48MHz for | Disabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup STM32WBAxx_system + * @{ + */ + +/** @addtogroup STM32WBAxx_System_Private_Includes + * @{ + */ + +#include "stm32wbaxx.h" +#include + +/** + * @} + */ + +/** @addtogroup STM32WBAxx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32WBAxx_System_Private_Defines + * @{ + */ +#if !defined (HSE_VALUE) +#define HSE_VALUE (32000000U) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) +#define HSI_VALUE (16000000U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/* Note: Following vector table addresses must be defined in line with linker + configuration. */ +/*!< Uncomment the following line if you need to relocate the vector table + anywhere in Flash or Sram, else the vector table is kept at the automatic + remap of boot address selected */ +/* #define USER_VECT_TAB_ADDRESS */ + +#if defined(USER_VECT_TAB_ADDRESS) +/*!< Uncomment the following line if you need to relocate your vector Table + in Sram else user remap will be done in Flash. */ +/* #define VECT_TAB_SRAM */ +#if defined(VECT_TAB_SRAM) +#define VECT_TAB_BASE_ADDRESS SRAM1_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +#else +#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_SRAM */ +#endif /* USER_VECT_TAB_ADDRESS */ + +/******************************************************************************/ + +/** + * @} + */ + +/** @addtogroup STM32WBAxx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32WBAxx_System_Private_Variables + * @{ + */ + /* The SystemCoreClock variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ + uint32_t SystemCoreClock = 16000000U; /* The HSI16 is used as system clock source after startup from reset, configured at 16 MHz. */ + + const uint8_t AHBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U}; + const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U}; + const uint8_t AHB5PrescTable[8] = {1U, 1U, 1U, 1U, 2U, 3U, 4U, 6U}; +/** + * @} + */ + +/** @addtogroup STM32WBAxx_System_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32WBAxx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * @param None + * @retval None + */ + +void SystemInit(void) +{ +#if defined(STM32WBAXX_SI_CUT1_0) + __IO uint32_t timeout_cpu_cycles; + __IO uint32_t tmpreg; +#endif + + /* FPU settings ------------------------------------------------------------*/ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */ +#endif + + /* Configure the Vector Table location -------------------------------------*/ +#if defined(USER_VECT_TAB_ADDRESS) + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation */ +#endif /* USER_VECT_TAB_ADDRESS */ + +#if defined(STM32WBAXX_SI_CUT1_0) + /* Work-around for ADC peripheral issue possibly impacting system + power consumption. + Refer to STM32WBA errata sheet item "HSI16 clock cannot be stopped when + used as kernel clock by ADC". + Actions: Perform a ADC activation sequence in order to update state + of internal signals. + */ + /* Enable ADC kernel clock */ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_ADC4EN); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_ADC4EN); + (void)tmpreg; + + /* Enable ADC */ + SET_BIT(ADC4->CR, ADC_CR_ADEN); + + /* Poll for ADC ready */ + /* Set timeout 2 ADC clock cycles */ + /* Note: Approximative computation and timeout execution not taking into + account processing CPU cycles */ + timeout_cpu_cycles = 2; + while (READ_BIT(ADC4->ISR, ADC_ISR_ADRDY) == 0U) + { + timeout_cpu_cycles--; + if(timeout_cpu_cycles == 0U) + { + break; + } + } + + /* Disable ADC */ + SET_BIT(ADC4->CR, ADC_CR_ADDIS); + + /* Poll for ADC disable is effective */ + /* Set timeout 6 ADC clock cycles */ + /* Note: Approximative computation and timeout execution not taking into + account processing CPU cycles */ + timeout_cpu_cycles = 6; + while (READ_BIT(ADC4->CR, ADC_CR_ADEN) != 0U) + { + timeout_cpu_cycles--; + if(timeout_cpu_cycles == 0U) + { + break; + } + } + + /* Disable ADC internal voltage regulator */ + CLEAR_BIT(ADC4->CR, ADC_CR_ADVREGEN); + + /* Disable ADC kernel clock */ + CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_ADC4EN); +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) + * + * - If SYSCLK source is PLL1, SystemCoreClock will contain the HSE_VALUE(***) + * or HSI_VALUE(*) multiplied/divided by the PLL1 factors. + * + * (**) HSI_VALUE is a constant defined in STM32WBAxx_hal.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (***) HSE_VALUE is a constant defined in STM32WBAxx_hal.h file (default value + * 32 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp1; + uint32_t tmp2; + uint32_t pllsource; + uint32_t pllr; + uint32_t pllm; + uint32_t plln; + float_t fracn; + float_t pllvco; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (RCC->CFGR1 & RCC_CFGR1_SWS) + { + case RCC_CFGR1_SWS_1: /* HSE used as system clock source */ + SystemCoreClock = (HSE_VALUE >> ((RCC->CR & RCC_CR_HSEPRE) >> RCC_CR_HSEPRE_Pos)); + break; + + case (RCC_CFGR1_SWS_0 | RCC_CFGR1_SWS_1): /* PLL1 used as system clock source */ + /* PLL_VCO = (PLLsource / PLLM) * PLLN * FractionnalPart + SYSCLK = PLL_VCO / PLLR */ + /* Get PLL1 CFGR and DIVR register values */ + tmp1 = RCC->PLL1CFGR; + tmp2 = RCC->PLL1DIVR; + + /* Retrieve PLL1 multiplication factor and divider */ + pllm = ((tmp1 & RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos) + 1U; + plln = (tmp2 & RCC_PLL1DIVR_PLL1N) + 1U; + pllr = ((tmp2 & RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1U; + + /* Check if fractional part is enable */ + if ((tmp1 & RCC_PLL1CFGR_PLL1FRACEN) != 0x00u) + { + fracn = (float_t)((uint32_t)((RCC->PLL1FRACR & RCC_PLL1FRACR_PLL1FRACN) >> RCC_PLL1FRACR_PLL1FRACN_Pos)); + } + else + { + fracn = (float_t)0U; + } + + /* determine PLL source */ + pllsource = (tmp1 & RCC_PLL1CFGR_PLL1SRC); + switch (pllsource) + { + /* HSI used as PLL1 clock source */ + case RCC_PLL1CFGR_PLL1SRC_1: + tmp1 = HSI_VALUE; + break; + + /* HSE used as PLL1 clock source */ + case (RCC_PLL1CFGR_PLL1SRC_0 | RCC_PLL1CFGR_PLL1SRC_1): + tmp1 = (HSE_VALUE >> ((RCC->CR & RCC_CR_HSEPRE) >> RCC_CR_HSEPRE_Pos)); + break; + + default: + tmp1 = 0U; + break; + } + + /* Compute VCO output frequency */ + pllvco = ((float_t) tmp1 / (float_t)pllm) * (((float_t)plln + (float_t)(fracn / (float_t)0x2000U))); + SystemCoreClock = (uint32_t)((float_t)(pllvco / (float_t)pllr)); + break; + + case 0x00u: /* HSI used as system clock source */ + default: + SystemCoreClock = HSI_VALUE; + break; + } + + /* Compute HCLK clock frequency --------------------------------------------*/ + /* Get HCLK prescaler */ + tmp1 = AHBPrescTable[(RCC->CFGR2 & RCC_CFGR2_HPRE)]; + + /* HCLK clock frequency */ + SystemCoreClock >>= tmp1; +} + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/system_stm32wbaxx_ns.c b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/system_stm32wbaxx_ns.c new file mode 100644 index 0000000000..faed2e6722 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/system_stm32wbaxx_ns.c @@ -0,0 +1,233 @@ +/** + ****************************************************************************** + * @file system_stm32wbaxx_ns.c + * @author MCD Application Team + * @brief CMSIS Cortex-M33 Device Peripheral Access Layer System Source File + * to be used in non-secure application when the system implements + * the TrustZone-M security. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at non-secure startup before + * branch to non-secure main program. + * This call is made inside the "startup_stm32wbaxx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32wbaxx.s" file, to + * configure the system clock before to branch to main secure program. + * Later, when non-secure SystemInit() function is called, in "startup_stm32wbaxx.s" + * file, the system clock may have been updated from reset value by the main + * secure program. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup STM32WBAxx_system + * @{ + */ + +/** @addtogroup STM32WBAxx_System_Private_Includes + * @{ + */ + +#include "stm32wbaxx.h" + +/** + * @} + */ + +/** @addtogroup STM32WBAxx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32WBAxx_System_Private_Defines + * @{ + */ +#if !defined (HSE_VALUE) +#define HSE_VALUE (32000000U) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) +#define HSI_VALUE (16000000U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/* Note: Following vector table addresses must be defined in line with linker + configuration. */ +/*!< Uncomment the following line if you need to relocate the vector table + anywhere in Flash or Sram, else the vector table is kept at the automatic + remap of boot address selected */ +/* #define USER_VECT_TAB_ADDRESS */ + +#if defined(USER_VECT_TAB_ADDRESS) +/*!< Uncomment the following line if you need to relocate your vector Table + in Sram else user remap will be done in Flash. */ +/* #define VECT_TAB_SRAM */ +#if defined(VECT_TAB_SRAM) +#define VECT_TAB_BASE_ADDRESS SRAM2_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +#else +#define VECT_TAB_BASE_ADDRESS (FLASH_BASE + 0x00080000U) /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_SRAM */ +#endif /* USER_VECT_TAB_ADDRESS */ + +/******************************************************************************/ + +/** + * @} + */ + +/** @addtogroup STM32WBAxx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32WBAxx_System_Private_Variables + * @{ + */ + /* The SystemCoreClock variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ + uint32_t SystemCoreClock = 16000000U; /* The HSI16 is used as system clock source after startup from reset, configured at 16 MHz. */ + + const uint8_t AHBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U}; + const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U}; + const uint8_t AHB5PrescTable[8] = {1U, 1U, 1U, 1U, 2U, 3U, 4U, 6U}; +/** + * @} + */ + +/** @addtogroup STM32WBAxx_System_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32WBAxx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * @param None + * @retval None + */ + +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */ +#endif + + /* Configure the Vector Table location -------------------------------------*/ +#if defined(USER_VECT_TAB_ADDRESS) + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation */ +#endif /* USER_VECT_TAB_ADDRESS */ + + /* Non-secure main application shall call SystemCoreClockUpdate() to update */ + /* the SystemCoreClock variable to insure non-secure application relies on */ + /* the initial clock reference set by secure application. */ +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note From the non-secure application, the SystemCoreClock value is + * retrieved from the secure domain via a Non-Secure Callable function + * since the RCC peripheral may be protected with security attributes + * that prevent to compute the SystemCoreClock variable from the RCC + * peripheral registers. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) + * + * - If SYSCLK source is PLL1, SystemCoreClock will contain the HSE_VALUE(***) + * or HSI_VALUE(*) multiplied/divided by the PLL1 factors. + * + * (**) HSI_VALUE is a constant defined in STM32WBAxx_hal.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (***) HSE_VALUE is a constant defined in STM32WBAxx_hal.h file (default value + * 32 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + /* Get the SystemCoreClock value from the secure domain */ + SystemCoreClock = SECURE_SystemCoreClockUpdate(); +} + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/system_stm32wbaxx_s.c b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/system_stm32wbaxx_s.c new file mode 100644 index 0000000000..89b09e225c --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/system_stm32wbaxx_s.c @@ -0,0 +1,418 @@ +/** + ****************************************************************************** + * @file system_stm32wbaxx_s.c + * @author MCD Application Team + * @brief CMSIS Cortex-M33 Device Peripheral Access Layer System Source File + * to be used in secure application when the system implements + * the TrustZone-M security. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at secure startup just after reset + * and before branch to secure main program. + * This call is made inside the "startup_stm32wbaxx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * - SECURE_SystemCoreClockUpdate(): Non-secure callable function to update + * the variable SystemCoreClock and return + * its value to the non-secure calling + * application. It must be called whenever + * the core clock is changed during program + * execution. + * + * After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32wbaxx.s" file, to + * configure the system clock before to branch to main program. + * + * This file configures the system clock as follows: + *============================================================================= + *----------------------------------------------------------------------------- + * System Clock source | HSI + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 16000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 16000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 1 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 1 + *----------------------------------------------------------------------------- + * PLL1_SRC | No clock + *----------------------------------------------------------------------------- + * PLL1_M | 1 + *----------------------------------------------------------------------------- + * PLL1_N | 128 + *----------------------------------------------------------------------------- + * PLL1_P | 1 + *----------------------------------------------------------------------------- + * PLL1_Q | 1 + *----------------------------------------------------------------------------- + * PLL1_R | 1 + *----------------------------------------------------------------------------- + * Require 48MHz for | Disabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup STM32WBAxx_system + * @{ + */ + +/** @addtogroup STM32WBAxx_System_Private_Includes + * @{ + */ + +#include "stm32wbaxx.h" +#include "partition_stm32wbaxx.h" /* Trustzone-M core secure attributes */ +#include + +/** + * @} + */ + +/** @addtogroup STM32WBAxx_System_Private_TypesDefinitions + * @{ + */ +#if defined ( __ICCARM__ ) +# define CMSE_NS_ENTRY __cmse_nonsecure_entry +#else +# define CMSE_NS_ENTRY __attribute((cmse_nonsecure_entry)) +#endif +/** + * @} + */ + +/** @addtogroup STM32WBAxx_System_Private_Defines + * @{ + */ +#if !defined (HSE_VALUE) +#define HSE_VALUE (32000000U) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) +#define HSI_VALUE (16000000U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/* Note: Following vector table addresses must be defined in line with linker + configuration. */ +/*!< Uncomment the following line if you need to relocate the vector table + anywhere in Flash or Sram, else the vector table is kept at the automatic + remap of boot address selected */ +/* #define USER_VECT_TAB_ADDRESS */ + +#if defined(USER_VECT_TAB_ADDRESS) +/*!< Uncomment the following line if you need to relocate your vector Table + in Sram else user remap will be done in Flash. */ +/* #define VECT_TAB_SRAM */ +#if defined(VECT_TAB_SRAM) +#define VECT_TAB_BASE_ADDRESS SRAM1_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +#else +#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_SRAM */ +#endif /* USER_VECT_TAB_ADDRESS */ + +/******************************************************************************/ + +/** + * @} + */ + +/** @addtogroup STM32WBAxx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32WBAxx_System_Private_Variables + * @{ + */ + /* The SystemCoreClock variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ + uint32_t SystemCoreClock = 16000000U; /* The HSI16 is used as system clock source after startup from reset, configured at 16 MHz. */ + + const uint8_t AHBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U}; + const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U}; + const uint8_t AHB5PrescTable[8] = {1U, 1U, 1U, 1U, 2U, 3U, 4U, 6U}; +/** + * @} + */ + +/** @addtogroup STM32WBAxx_System_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32WBAxx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * @param None + * @retval None + */ + +void SystemInit(void) +{ +#if defined(STM32WBAXX_SI_CUT1_0) + __IO uint32_t timeout_cpu_cycles; + __IO uint32_t tmpreg; +#endif + + /* SAU/IDAU, FPU and Interrupts secure/non-secure allocation settings */ + TZ_SAU_Setup(); + + /* FPU settings ------------------------------------------------------------*/ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */ +#endif + + /* Configure the Vector Table location -------------------------------------*/ +#if defined(USER_VECT_TAB_ADDRESS) + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation */ +#endif /* USER_VECT_TAB_ADDRESS */ + +#if defined(STM32WBAXX_SI_CUT1_0) + /* Work-around for ADC peripheral issue possibly impacting system + power consumption. + Refer to STM32WBA errata sheet item "HSI16 clock cannot be stopped when + used as kernel clock by ADC". + Actions: Perform a ADC activation sequence in order to update state + of internal signals. + */ + /* Enable ADC kernel clock */ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_ADC4EN); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_ADC4EN); + (void)tmpreg; + + /* Enable ADC */ + SET_BIT(ADC4->CR, ADC_CR_ADEN); + + /* Poll for ADC ready */ + /* Set timeout 2 ADC clock cycles */ + /* Note: Approximative computation and timeout execution not taking into + account processing CPU cycles */ + timeout_cpu_cycles = 2; + while (READ_BIT(ADC4->ISR, ADC_ISR_ADRDY) == 0U) + { + timeout_cpu_cycles--; + if(timeout_cpu_cycles == 0U) + { + break; + } + } + + /* Disable ADC */ + SET_BIT(ADC4->CR, ADC_CR_ADDIS); + + /* Poll for ADC disable is effective */ + /* Set timeout 6 ADC clock cycles */ + /* Note: Approximative computation and timeout execution not taking into + account processing CPU cycles */ + timeout_cpu_cycles = 6; + while (READ_BIT(ADC4->CR, ADC_CR_ADEN) != 0U) + { + timeout_cpu_cycles--; + if(timeout_cpu_cycles == 0U) + { + break; + } + } + + /* Disable ADC internal voltage regulator */ + CLEAR_BIT(ADC4->CR, ADC_CR_ADVREGEN); + + /* Disable ADC kernel clock */ + CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_ADC4EN); +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Depending on secure or non-secure compilation, the adequate RCC peripheral + * memory are is accessed thanks to RCC alias defined in stm32wbxxxx.h device file + * so either from RCC_S peripheral register mapped memory in secure or from + * RCC_NS peripheral register mapped memory in non-secure. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) + * + * - If SYSCLK source is PLL1, SystemCoreClock will contain the HSE_VALUE(***) + * or HSI_VALUE(*) multiplied/divided by the PLL1 factors. + * + * (**) HSI_VALUE is a constant defined in STM32WBAxx_hal.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (***) HSE_VALUE is a constant defined in STM32WBAxx_hal.h file (default value + * 32 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp1; + uint32_t tmp2; + uint32_t pllsource; + uint32_t pllr; + uint32_t pllm; + uint32_t plln; + float_t fracn; + float_t pllvco; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (RCC->CFGR1 & RCC_CFGR1_SWS) + { + case RCC_CFGR1_SWS_1: /* HSE used as system clock source */ + SystemCoreClock = (HSE_VALUE >> ((RCC->CR & RCC_CR_HSEPRE) >> RCC_CR_HSEPRE_Pos)); + break; + + case (RCC_CFGR1_SWS_0 | RCC_CFGR1_SWS_1): /* PLL1 used as system clock source */ + /* PLL_VCO = (PLLsource / PLLM) * PLLN * FractionnalPart + SYSCLK = PLL_VCO / PLLR */ + /* Get PLL1 CFGR and DIVR register values */ + tmp1 = RCC->PLL1CFGR; + tmp2 = RCC->PLL1DIVR; + + /* Retrieve PLL1 multiplication factor and divider */ + pllm = ((tmp1 & RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos) + 1U; + plln = (tmp2 & RCC_PLL1DIVR_PLL1N) + 1U; + pllr = ((tmp2 & RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1U; + + /* Check if fractional part is enable */ + if ((tmp1 & RCC_PLL1CFGR_PLL1FRACEN) != 0x00u) + { + fracn = (float_t)((uint32_t)((RCC->PLL1FRACR & RCC_PLL1FRACR_PLL1FRACN) >> RCC_PLL1FRACR_PLL1FRACN_Pos)); + } + else + { + fracn = (float_t)0U; + } + + /* determine PLL source */ + pllsource = (tmp1 & RCC_PLL1CFGR_PLL1SRC); + switch (pllsource) + { + /* HSI used as PLL1 clock source */ + case RCC_PLL1CFGR_PLL1SRC_1: + tmp1 = HSI_VALUE; + break; + + /* HSE used as PLL1 clock source */ + case (RCC_PLL1CFGR_PLL1SRC_0 | RCC_PLL1CFGR_PLL1SRC_1): + tmp1 = (HSE_VALUE >> ((RCC->CR & RCC_CR_HSEPRE) >> RCC_CR_HSEPRE_Pos)); + break; + + default: + tmp1 = 0U; + break; + } + + /* Compute VCO output frequency */ + pllvco = ((float_t) tmp1 / (float_t)pllm) * (((float_t)plln + (float_t)(fracn / (float_t)0x2000U))); + SystemCoreClock = (uint32_t)((float_t)(pllvco / (float_t)pllr)); + break; + + case 0x00u: /* HSI used as system clock source */ + default: + SystemCoreClock = HSI_VALUE; + break; + } + + /* Compute HCLK clock frequency --------------------------------------------*/ + /* Get HCLK prescaler */ + tmp1 = AHBPrescTable[(RCC->CFGR2 & RCC_CFGR2_HPRE)]; + + /* HCLK clock frequency */ + SystemCoreClock >>= tmp1; +} + +/** + * @brief Secure Non-Secure-Callable function to return the current + * SystemCoreClock value after SystemCoreClock update. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * @retval SystemCoreClock value (HCLK) + */ +CMSE_NS_ENTRY uint32_t SECURE_SystemCoreClockUpdate(void) +{ + SystemCoreClockUpdate(); + + return SystemCoreClock; +} + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/_htmresc/Add button.svg b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/_htmresc/Add button.svg new file mode 100644 index 0000000000..c211545dad --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/_htmresc/Add button.svg @@ -0,0 +1,2 @@ + + diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/_htmresc/Update.svg b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/_htmresc/Update.svg new file mode 100644 index 0000000000..f88381f1e6 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/_htmresc/Update.svg @@ -0,0 +1,2 @@ + + diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/_htmresc/favicon.png b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/_htmresc/favicon.png new file mode 100644 index 0000000000000000000000000000000000000000..06713eec4974e141c6e9b4156d34e61e89f282ca GIT binary patch literal 4126 zcmV+(5aI8MP)ZIGU@QfPy~$kHP}Vz9c$a)g>fT6hB^OaK4>c|MGS0000HbW%=J|NsC0|NsC0 z|NsC0|NsC0041%NVgLXD!bwCyRCwCllie1CAP9sJ&9ooo{hxLjw5@YC+xxf~%TE}{ zNd5%935b--eKa7{Q8)vZ;eI6pGFH>rL)887WOA={e(b_&0g-g6to#Hm2B3vqWV>1u z@z7*I(bdWdx-Y=OT@|og)oZEgAbc7ep|Gf{$7j1Oa#T&r4>0xv(+}tR_4biWa z1Q-BfcsgeLIJPbT0000rV&neh&#Q1i z007~1e$oCcFS8neI|hJl{-P!B1ZZ9hpmq0)X0i`JwE&>$+E?>%_LC6RbVIkUx0b+_+BaR3cnT7Zv!AJxW zizFb)h!jyGOOZ85F;a?DAXP{m@;!0_IfqH8(HlgRxt7s3}k3K`kFu>>-2Q$QMFfPW!La{h336o>X zu_CMttHv6zR;&ZNiS=X8v3CR#fknUxHUxJ0uoBa_M6WNWeqIg~6QE69c9o#eyhGvpiOA@W-aonk<7r1(?fC{oI5N*U!4 zfg=2N-7=cNnjjOr{yriy6mMFgG#l znCF=fnQv8CDz++o6_Lscl}eQ+l^ZHARH>?_s@|##Rr6KLRFA1%Q+=*RRWnoLsR`7U zt5vFIcfW3@?wFpwUVxrVZ>QdQz32KIeJ}k~{cZZE^+ya? z2D1z#2HOnI7(B%_ac?{wFUQ;QQA1tBKtrWrm0_3Rgps+?Jfqb{jYbcQX~taRB;#$y zZN{S}1|}gUOHJxc?wV3fxuz+mJ4`!F$IZ;mqRrNsHJd##*D~ju=bP7?-?v~|cv>vB zsJ6IeNwVZxrdjT`yl#bBIa#GxRa#xMMy;K#CDyyGyQdMSxlWT#tDe?p!?5wT$+oGt z8L;Kp2HUQ-ZMJ=3XJQv;x5ci*?vuTfeY$;({XGW_huIFR9a(?@3)XSs8O^N5RyOM=TTmp(3=8^+zpz2r)C z^>JO{deZfso3oq3?Wo(Y?l$ge?uXo;%ru`Vo>?<<(8I_>;8Eq#KMS9gFl*neeosSB zfoHYnBQIkwkyowPu(zdms`p{<7e4kra-ZWq<2*OsGTvEV%s0Td$hXT+!*8Bnh2KMe zBmZRodjHV?r+_5^X9J0WL4jKW`}lf%A-|44I@@LTvf1rHjG(ze6+w@Jt%Bvjts!X0 z?2xS?_ve_-kiKB_KiJlZ$9G`c^=E@oNG)mWWaNo-3TIW8)$Hg0Ub-~8?KhvJ>$ z3*&nim@mj(aCxE5!t{lw7O5^0EIO7zOo&c6l<+|iDySBWCGrz@C5{St!X3hAA}`T4 z(TLbXTq+(;@<=L8dXnssyft|w#WSTW<++3>sgS%(4NTpeI-VAqb|7ssJvzNHgOZVu zaYCvgO_R1~>SyL=cFU|~g|hy|Zi}}s9+d~lYqOB71z9Z$wnC=pR9Yz4DhIM>Wmjgu z&56o6maCpC&F##y%G;1PobR9i?GnNg;gYtchD%p19a!eQtZF&3JaKv33gZ<8D~47E ztUS1iwkmDaPpj=$m#%)jCVEY4fnLGNg2A-`YwHVD3gv};>)hAvT~AmqS>Lr``i7kw zJ{5_It`yrBmlc25DBO7E8;5VoznR>Ww5hAaxn$2~(q`%A-YuS64wkBy=9dm`4cXeX z4c}I@?e+FW+b@^RDBHV(wnMq2zdX3SWv9u`%{xC-q*U}&`cyXV(%rRT*Z6MH?i+i& z_B8C(+grT%{XWUQ+f@NoP1R=AW&26{v-dx)iK^-Nmiuj8txj!m?Z*Ss1N{dh4z}01 z)YTo*JycSU)+_5r4#yw9{+;i4Ee$peRgIj+;v;ZGdF1K$3E%e~4LaI(jC-u%2h$&R z9cLXcYC@Xwnns&bn)_Q~Te?roKGD|d-g^8;+aC{{G(1^(O7m37Y1-+6)01cN&y1aw zoqc{T`P^XJqPBbIW6s}d4{z_f5Om?vMgNQEJG?v2T=KYd^0M3I6IZxbny)%vZR&LD zJpPl@Psh8QyPB@KTx+@RdcC!KX7}kEo;S|j^u2lU7XQ}Oo;f|;z4Ll+_r>@1-xl3| zawq-H%e&ckC+@AhPrP6BKT#_XdT7&;F71j}Joy zkC~6lh7E@6o;W@^IpRNZ{ptLtL(gQ-CY~4mqW;US7Zxvm_|@yz&e53Bp_lTPlfP|z zrTyx_>lv@x#=^!PzR7qqF<$gm`|ZJZ+;<)Cqu&ot2z=0000WV@Og>004R=004l4008;_004mL004C`008P>0026e000+nl3&F} z000F^NklQWRUVq~pvFslpiNq83Yr*1(ELa!!kppKfxQKEkPzz^I>0W)!71xam z(B64`)5a~kHf9SBOp*Wvo{xA*e4|Kv3g6TCo+fF8q^C$|g>#NlXyY$%lmkmCh$x1Z zFbJ_hiDG`37w>KPVB83d7E3>R@-M9$`|}|QFF}1qSk!nanPdVd3K38edo3y+D*=Uo zfOWCwj(F@GSjPG&B<0O;H!Zm0g>eDeK09{b@xB};mEy; z;Gp5H_Cr65qKM1uYIu6x&16!Ei=BHfJLe)1IUnFqc6d#D=ZVQmV9C73vy1=x$SK;s z=*CYZP+Ei1D5Vjl#u88v5dv#jId?iu)8mM}{mD`GcMXtAC5ap?ZoKr&iYuqTKHe$t zTR%R$ZZwxec?l+0r_LIVbe-mzH+D0*ZYsu4BE~~JA2A+AD?BAArO=g8ZfvXtU~o9c zZ(Bd-RFK5jh*DvM1v6^41HB@0K0qn7E8E&Xz1mk6hvmx?*|WB_H!dcO;5R$=<4b~s z5zr3N4zxlkMKOrDeny(PGpEM6^hGyc7lhg>MWtM!af*pn%&q_PxI(n^(-Zd{ICPAp z(WE@Zz5|EZyt{MEDy&l5$Cba^zU!9k&;Vs7lk$@o02LOwb#e2{#3%Cn2>kQF(RKUU z+tW!;FT0@d+TX^L;>@3RytlTP&ts$pqA}TwENBlg9?$-D zF9Sn4URZx8)hVBw<~NY=h3=so7{jEhG%Zc_0QBSvY~K4BS|W5MAem5XSb6m}VDN$f zy+b3n9qjIJoHM5pqYa`IPH9AIoM=!AE1Er>r|3E}#Jq-S)cTrfD&TZjAuN@+V}3mi zlhOce+q<8>Y?i93G=*Z3Web`ri!Q%p%LR*(bB?;|)B`&=J&ab0Z(UKpbzyZV5o*#& z0FLzzaI$v*-#WB)+`n>BoJ*1AwU0XSu;@w&Hu1WYXVR#!8itC%68CzMeiXhL#`9W$9J30NB-Wg!ex`hBlg9F5u@&o4>hd`TWPv z{r{JbyvQGZzbyvPS}zAifbhF49z~X|@9v|!=No>qsF|P~vf=g>7#%0yk<U?Ha8*Z4HW>#8w>z$A3 z>^uQlk;$a-6CQ(uc@RM)Cbss!xuPVl2@c1u-5tEUw}U8OfP_J+QYhfu$B<0Cj3xm7 c?*aZZ00ulYFs-m=@&Et;07*qoM6N<$f~=14i~s-t literal 0 HcmV?d00001 diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/_htmresc/mini-st_2020.css b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/_htmresc/mini-st_2020.css new file mode 100644 index 0000000000..db8b406aa4 --- /dev/null +++ b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/_htmresc/mini-st_2020.css @@ -0,0 +1,1711 @@ +@charset "UTF-8"; +/* + Flavor name: Custom (mini-custom) + Generated online - https://minicss.org/flavors + mini.css version: v3.0.1 +*/ +/* + Browsers resets and base typography. +*/ +/* Core module CSS variable definitions */ +:root { + --fore-color: #03234b; + --secondary-fore-color: #03234b; + --back-color: #ffffff; + --secondary-back-color: #ffffff; + --blockquote-color: #e6007e; + --pre-color: #e6007e; + --border-color: #3cb4e6; + --secondary-border-color: #3cb4e6; + --heading-ratio: 1.2; + --universal-margin: 0.5rem; + --universal-padding: 0.25rem; + --universal-border-radius: 0.075rem; + --background-margin: 1.5%; + --a-link-color: #3cb4e6; + --a-visited-color: #8c0078; } + +html { + font-size: 13.5px; } + +a, b, del, em, i, ins, q, span, strong, u { + font-size: 1em; } + +html, * { + font-family: -apple-system, BlinkMacSystemFont, Helvetica, arial, sans-serif; + line-height: 1.25; + -webkit-text-size-adjust: 100%; } + +* { + font-size: 1rem; } + +body { + margin: 0; + color: var(--fore-color); + @background: var(--back-color); + background: var(--back-color) linear-gradient(#ffd200, #ffd200) repeat-y left top; + background-size: var(--background-margin); + } + +details { + display: block; } + +summary { + display: list-item; } + +abbr[title] { + border-bottom: none; + text-decoration: underline dotted; } + +input { + overflow: visible; } + +img { + max-width: 100%; + height: auto; } + +h1, h2, h3, h4, h5, h6 { + line-height: 1.25; + margin: calc(1.5 * var(--universal-margin)) var(--universal-margin); + font-weight: 400; } + h1 small, h2 small, h3 small, h4 small, h5 small, h6 small { + color: var(--secondary-fore-color); + display: block; + margin-top: -0.25rem; } + +h1 { + font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) * var(--heading-ratio)); } + +h2 { + font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) ); + border-style: none none solid none ; + border-width: thin; + border-color: var(--border-color); } +h3 { + font-size: calc(1rem * var(--heading-ratio) ); } + +h4 { + font-size: calc(1rem * var(--heading-ratio)); } + +h5 { + font-size: 1rem; } + +h6 { + font-size: calc(1rem / var(--heading-ratio)); } + +p { + margin: var(--universal-margin); } + +ol, ul { + margin: var(--universal-margin); + padding-left: calc(3 * var(--universal-margin)); } + +b, strong { + font-weight: 700; } + +hr { + box-sizing: content-box; + border: 0; + line-height: 1.25em; + margin: var(--universal-margin); + height: 0.0714285714rem; + background: linear-gradient(to right, transparent, var(--border-color) 20%, var(--border-color) 80%, transparent); } + +blockquote { + display: block; + position: relative; + font-style: italic; + color: var(--secondary-fore-color); + margin: var(--universal-margin); + padding: calc(3 * var(--universal-padding)); + border: 0.0714285714rem solid var(--secondary-border-color); + border-left: 0.3rem solid var(--blockquote-color); + border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; } + blockquote:before { + position: absolute; + top: calc(0rem - var(--universal-padding)); + left: 0; + font-family: sans-serif; + font-size: 2rem; + font-weight: 800; + content: "\201c"; + color: var(--blockquote-color); } + blockquote[cite]:after { + font-style: normal; + font-size: 0.75em; + font-weight: 700; + content: "\a— " attr(cite); + white-space: pre; } + +code, kbd, pre, samp { + font-family: Menlo, Consolas, monospace; + font-size: 0.85em; } + +code { + background: var(--secondary-back-color); + border-radius: var(--universal-border-radius); + padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); } + +kbd { + background: var(--fore-color); + color: var(--back-color); + border-radius: var(--universal-border-radius); + padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); } + +pre { + overflow: auto; + background: var(--secondary-back-color); + padding: calc(1.5 * var(--universal-padding)); + margin: var(--universal-margin); + border: 0.0714285714rem solid var(--secondary-border-color); + border-left: 0.2857142857rem solid var(--pre-color); + border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; } + +sup, sub, code, kbd { + line-height: 0; + position: relative; + vertical-align: baseline; } + +small, sup, sub, figcaption { + font-size: 0.75em; } + +sup { + top: -0.5em; } + +sub { + bottom: -0.25em; } + +figure { + margin: var(--universal-margin); } + +figcaption { + color: var(--secondary-fore-color); } + +a { + text-decoration: none; } + a:link { + color: var(--a-link-color); } + a:visited { + color: var(--a-visited-color); } + a:hover, a:focus { + text-decoration: underline; } + +/* + Definitions for the grid system, cards and containers. +*/ +.container { + margin: 0 auto; + padding: 0 calc(1.5 * var(--universal-padding)); } + +.row { + box-sizing: border-box; + display: flex; + flex: 0 1 auto; + flex-flow: row wrap; + margin: 0 0 0 var(--background-margin); } + +.col-sm, +[class^='col-sm-'], +[class^='col-sm-offset-'], +.row[class*='cols-sm-'] > * { + box-sizing: border-box; + flex: 0 0 auto; + padding: 0 calc(var(--universal-padding) / 2); } + +.col-sm, +.row.cols-sm > * { + max-width: 100%; + flex-grow: 1; + flex-basis: 0; } + +.col-sm-1, +.row.cols-sm-1 > * { + max-width: 8.3333333333%; + flex-basis: 8.3333333333%; } + +.col-sm-offset-0 { + margin-left: 0; } + +.col-sm-2, +.row.cols-sm-2 > * { + max-width: 16.6666666667%; + flex-basis: 16.6666666667%; } + +.col-sm-offset-1 { + margin-left: 8.3333333333%; } + +.col-sm-3, +.row.cols-sm-3 > * { + max-width: 25%; + flex-basis: 25%; } + +.col-sm-offset-2 { + margin-left: 16.6666666667%; } + +.col-sm-4, +.row.cols-sm-4 > * { + max-width: 33.3333333333%; + flex-basis: 33.3333333333%; } + +.col-sm-offset-3 { + margin-left: 25%; } + +.col-sm-5, +.row.cols-sm-5 > * { + max-width: 41.6666666667%; + flex-basis: 41.6666666667%; } + +.col-sm-offset-4 { + margin-left: 33.3333333333%; } + +.col-sm-6, +.row.cols-sm-6 > * { + max-width: 50%; + flex-basis: 50%; } + +.col-sm-offset-5 { + margin-left: 41.6666666667%; } + +.col-sm-7, +.row.cols-sm-7 > * { + max-width: 58.3333333333%; + flex-basis: 58.3333333333%; } + +.col-sm-offset-6 { + margin-left: 50%; } + +.col-sm-8, +.row.cols-sm-8 > * { + max-width: 66.6666666667%; + flex-basis: 66.6666666667%; } + +.col-sm-offset-7 { + margin-left: 58.3333333333%; } + +.col-sm-9, +.row.cols-sm-9 > * { + max-width: 75%; + flex-basis: 75%; } + +.col-sm-offset-8 { + margin-left: 66.6666666667%; } + +.col-sm-10, +.row.cols-sm-10 > * { + max-width: 83.3333333333%; + flex-basis: 83.3333333333%; } + +.col-sm-offset-9 { + margin-left: 75%; } + +.col-sm-11, +.row.cols-sm-11 > * { + max-width: 91.6666666667%; + flex-basis: 91.6666666667%; } + +.col-sm-offset-10 { + margin-left: 83.3333333333%; } + +.col-sm-12, +.row.cols-sm-12 > * { + max-width: 100%; + flex-basis: 100%; } + +.col-sm-offset-11 { + margin-left: 91.6666666667%; } + +.col-sm-normal { + order: initial; } + +.col-sm-first { + order: -999; } + +.col-sm-last { + order: 999; } + +@media screen and (min-width: 500px) { + .col-md, + [class^='col-md-'], + [class^='col-md-offset-'], + .row[class*='cols-md-'] > * { + box-sizing: border-box; + flex: 0 0 auto; + padding: 0 calc(var(--universal-padding) / 2); } + + .col-md, + .row.cols-md > * { + max-width: 100%; + flex-grow: 1; + flex-basis: 0; } + + .col-md-1, + .row.cols-md-1 > * { + max-width: 8.3333333333%; + flex-basis: 8.3333333333%; } + + .col-md-offset-0 { + margin-left: 0; } + + .col-md-2, + .row.cols-md-2 > * { + max-width: 16.6666666667%; + flex-basis: 16.6666666667%; } + + .col-md-offset-1 { + margin-left: 8.3333333333%; } + + .col-md-3, + .row.cols-md-3 > * { + max-width: 25%; + flex-basis: 25%; } + + .col-md-offset-2 { + margin-left: 16.6666666667%; } + + .col-md-4, + .row.cols-md-4 > * { + max-width: 33.3333333333%; + flex-basis: 33.3333333333%; } + + .col-md-offset-3 { + margin-left: 25%; } + + .col-md-5, + .row.cols-md-5 > * { + max-width: 41.6666666667%; + flex-basis: 41.6666666667%; } + + .col-md-offset-4 { + margin-left: 33.3333333333%; } + + .col-md-6, + .row.cols-md-6 > * { + max-width: 50%; + flex-basis: 50%; } + + .col-md-offset-5 { + margin-left: 41.6666666667%; } + + .col-md-7, + .row.cols-md-7 > * { + max-width: 58.3333333333%; + flex-basis: 58.3333333333%; } + + .col-md-offset-6 { + margin-left: 50%; } + + .col-md-8, + .row.cols-md-8 > * { + max-width: 66.6666666667%; + flex-basis: 66.6666666667%; } + + .col-md-offset-7 { + margin-left: 58.3333333333%; } + + .col-md-9, + .row.cols-md-9 > * { + max-width: 75%; + flex-basis: 75%; } + + .col-md-offset-8 { + margin-left: 66.6666666667%; } + + .col-md-10, + .row.cols-md-10 > * { + max-width: 83.3333333333%; + flex-basis: 83.3333333333%; } + + .col-md-offset-9 { + margin-left: 75%; } + + .col-md-11, + .row.cols-md-11 > * { + max-width: 91.6666666667%; + flex-basis: 91.6666666667%; } + + .col-md-offset-10 { + margin-left: 83.3333333333%; } + + .col-md-12, + .row.cols-md-12 > * { + max-width: 100%; + flex-basis: 100%; } + + .col-md-offset-11 { + margin-left: 91.6666666667%; } + + .col-md-normal { + order: initial; } + + .col-md-first { + order: -999; } + + .col-md-last { + order: 999; } } +@media screen and (min-width: 1280px) { + .col-lg, + [class^='col-lg-'], + [class^='col-lg-offset-'], + .row[class*='cols-lg-'] > * { + box-sizing: border-box; + flex: 0 0 auto; + padding: 0 calc(var(--universal-padding) / 2); } + + .col-lg, + .row.cols-lg > * { + max-width: 100%; + flex-grow: 1; + flex-basis: 0; } + + .col-lg-1, + .row.cols-lg-1 > * { + max-width: 8.3333333333%; + flex-basis: 8.3333333333%; } + + .col-lg-offset-0 { + margin-left: 0; } + + .col-lg-2, + .row.cols-lg-2 > * { + max-width: 16.6666666667%; + flex-basis: 16.6666666667%; } + + .col-lg-offset-1 { + margin-left: 8.3333333333%; } + + .col-lg-3, + .row.cols-lg-3 > * { + max-width: 25%; + flex-basis: 25%; } + + .col-lg-offset-2 { + margin-left: 16.6666666667%; } + + .col-lg-4, + .row.cols-lg-4 > * { + max-width: 33.3333333333%; + flex-basis: 33.3333333333%; } + + .col-lg-offset-3 { + margin-left: 25%; } + + .col-lg-5, + .row.cols-lg-5 > * { + max-width: 41.6666666667%; + flex-basis: 41.6666666667%; } + + .col-lg-offset-4 { + margin-left: 33.3333333333%; } + + .col-lg-6, + .row.cols-lg-6 > * { + max-width: 50%; + flex-basis: 50%; } + + .col-lg-offset-5 { + margin-left: 41.6666666667%; } + + .col-lg-7, + .row.cols-lg-7 > * { + max-width: 58.3333333333%; + flex-basis: 58.3333333333%; } + + .col-lg-offset-6 { + margin-left: 50%; } + + .col-lg-8, + .row.cols-lg-8 > * { + max-width: 66.6666666667%; + flex-basis: 66.6666666667%; } + + .col-lg-offset-7 { + margin-left: 58.3333333333%; } + + .col-lg-9, + .row.cols-lg-9 > * { + max-width: 75%; + flex-basis: 75%; } + + .col-lg-offset-8 { + margin-left: 66.6666666667%; } + + .col-lg-10, + .row.cols-lg-10 > * { + max-width: 83.3333333333%; + flex-basis: 83.3333333333%; } + + .col-lg-offset-9 { + margin-left: 75%; } + + .col-lg-11, + .row.cols-lg-11 > * { + max-width: 91.6666666667%; + flex-basis: 91.6666666667%; } + + .col-lg-offset-10 { + margin-left: 83.3333333333%; } + + .col-lg-12, + .row.cols-lg-12 > * { + max-width: 100%; + flex-basis: 100%; } + + .col-lg-offset-11 { + margin-left: 91.6666666667%; } + + .col-lg-normal { + order: initial; } + + .col-lg-first { + order: -999; } + + .col-lg-last { + order: 999; } } +/* Card component CSS variable definitions */ +:root { + --card-back-color: #3cb4e6; + --card-fore-color: #03234b; + --card-border-color: #03234b; } + +.card { + display: flex; + flex-direction: column; + justify-content: space-between; + align-self: center; + position: relative; + width: 100%; + background: var(--card-back-color); + color: var(--card-fore-color); + border: 0.0714285714rem solid var(--card-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); + overflow: hidden; } + @media screen and (min-width: 320px) { + .card { + max-width: 320px; } } + .card > .sectione { + background: var(--card-back-color); + color: var(--card-fore-color); + box-sizing: border-box; + margin: 0; + border: 0; + border-radius: 0; + border-bottom: 0.0714285714rem solid var(--card-border-color); + padding: var(--universal-padding); + width: 100%; } + .card > .sectione.media { + height: 200px; + padding: 0; + -o-object-fit: cover; + object-fit: cover; } + .card > .sectione:last-child { + border-bottom: 0; } + +/* + Custom elements for card elements. +*/ +@media screen and (min-width: 240px) { + .card.small { + max-width: 240px; } } +@media screen and (min-width: 480px) { + .card.large { + max-width: 480px; } } +.card.fluid { + max-width: 100%; + width: auto; } + +.card.warning { + --card-back-color: #e5b8b7; + --card-fore-color: #3b234b; + --card-border-color: #8c0078; } + +.card.error { + --card-back-color: #464650; + --card-fore-color: #ffffff; + --card-border-color: #8c0078; } + +.card > .sectione.dark { + --card-back-color: #3b234b; + --card-fore-color: #ffffff; } + +.card > .sectione.double-padded { + padding: calc(1.5 * var(--universal-padding)); } + +/* + Definitions for forms and input elements. +*/ +/* Input_control module CSS variable definitions */ +:root { + --form-back-color: #ffe97f; + --form-fore-color: #03234b; + --form-border-color: #3cb4e6; + --input-back-color: #ffffff; + --input-fore-color: #03234b; + --input-border-color: #3cb4e6; + --input-focus-color: #0288d1; + --input-invalid-color: #d32f2f; + --button-back-color: #e2e2e2; + --button-hover-back-color: #dcdcdc; + --button-fore-color: #212121; + --button-border-color: transparent; + --button-hover-border-color: transparent; + --button-group-border-color: rgba(124, 124, 124, 0.54); } + +form { + background: var(--form-back-color); + color: var(--form-fore-color); + border: 0.0714285714rem solid var(--form-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); + padding: calc(2 * var(--universal-padding)) var(--universal-padding); } + +fieldset { + border: 0.0714285714rem solid var(--form-border-color); + border-radius: var(--universal-border-radius); + margin: calc(var(--universal-margin) / 4); + padding: var(--universal-padding); } + +legend { + box-sizing: border-box; + display: table; + max-width: 100%; + white-space: normal; + font-weight: 500; + padding: calc(var(--universal-padding) / 2); } + +label { + padding: calc(var(--universal-padding) / 2) var(--universal-padding); } + +.input-group { + display: inline-block; } + .input-group.fluid { + display: flex; + align-items: center; + justify-content: center; } + .input-group.fluid > input { + max-width: 100%; + flex-grow: 1; + flex-basis: 0px; } + @media screen and (max-width: 499px) { + .input-group.fluid { + align-items: stretch; + flex-direction: column; } } + .input-group.vertical { + display: flex; + align-items: stretch; + flex-direction: column; } + .input-group.vertical > input { + max-width: 100%; + flex-grow: 1; + flex-basis: 0px; } + +[type="number"]::-webkit-inner-spin-button, [type="number"]::-webkit-outer-spin-button { + height: auto; } + +[type="search"] { + -webkit-appearance: textfield; + outline-offset: -2px; } + +[type="search"]::-webkit-search-cancel-button, +[type="search"]::-webkit-search-decoration { + -webkit-appearance: none; } + +input:not([type]), [type="text"], [type="email"], [type="number"], [type="search"], +[type="password"], [type="url"], [type="tel"], [type="checkbox"], [type="radio"], textarea, select { + box-sizing: border-box; + background: var(--input-back-color); + color: var(--input-fore-color); + border: 0.0714285714rem solid var(--input-border-color); + border-radius: var(--universal-border-radius); + margin: calc(var(--universal-margin) / 2); + padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); } + +input:not([type="button"]):not([type="submit"]):not([type="reset"]):hover, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus, textarea:hover, textarea:focus, select:hover, select:focus { + border-color: var(--input-focus-color); + box-shadow: none; } +input:not([type="button"]):not([type="submit"]):not([type="reset"]):invalid, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus:invalid, textarea:invalid, textarea:focus:invalid, select:invalid, select:focus:invalid { + border-color: var(--input-invalid-color); + box-shadow: none; } +input:not([type="button"]):not([type="submit"]):not([type="reset"])[readonly], textarea[readonly], select[readonly] { + background: var(--secondary-back-color); } + +select { + max-width: 100%; } + +option { + overflow: hidden; + text-overflow: ellipsis; } + +[type="checkbox"], [type="radio"] { + -webkit-appearance: none; + -moz-appearance: none; + appearance: none; + position: relative; + height: calc(1rem + var(--universal-padding) / 2); + width: calc(1rem + var(--universal-padding) / 2); + vertical-align: text-bottom; + padding: 0; + flex-basis: calc(1rem + var(--universal-padding) / 2) !important; + flex-grow: 0 !important; } + [type="checkbox"]:checked:before, [type="radio"]:checked:before { + position: absolute; } + +[type="checkbox"]:checked:before { + content: '\2713'; + font-family: sans-serif; + font-size: calc(1rem + var(--universal-padding) / 2); + top: calc(0rem - var(--universal-padding)); + left: calc(var(--universal-padding) / 4); } + +[type="radio"] { + border-radius: 100%; } + [type="radio"]:checked:before { + border-radius: 100%; + content: ''; + top: calc(0.0714285714rem + var(--universal-padding) / 2); + left: calc(0.0714285714rem + var(--universal-padding) / 2); + background: var(--input-fore-color); + width: 0.5rem; + height: 0.5rem; } + +:placeholder-shown { + color: var(--input-fore-color); } + +::-ms-placeholder { + color: var(--input-fore-color); + opacity: 0.54; } + +button::-moz-focus-inner, [type="button"]::-moz-focus-inner, [type="reset"]::-moz-focus-inner, [type="submit"]::-moz-focus-inner { + border-style: none; + padding: 0; } + +button, html [type="button"], [type="reset"], [type="submit"] { + -webkit-appearance: button; } + +button { + overflow: visible; + text-transform: none; } + +button, [type="button"], [type="submit"], [type="reset"], +a.button, label.button, .button, +a[role="button"], label[role="button"], [role="button"] { + display: inline-block; + background: var(--button-back-color); + color: var(--button-fore-color); + border: 0.0714285714rem solid var(--button-border-color); + border-radius: var(--universal-border-radius); + padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); + margin: var(--universal-margin); + text-decoration: none; + cursor: pointer; + transition: background 0.3s; } + button:hover, button:focus, [type="button"]:hover, [type="button"]:focus, [type="submit"]:hover, [type="submit"]:focus, [type="reset"]:hover, [type="reset"]:focus, + a.button:hover, + a.button:focus, label.button:hover, label.button:focus, .button:hover, .button:focus, + a[role="button"]:hover, + a[role="button"]:focus, label[role="button"]:hover, label[role="button"]:focus, [role="button"]:hover, [role="button"]:focus { + background: var(--button-hover-back-color); + border-color: var(--button-hover-border-color); } + +input:disabled, input[disabled], textarea:disabled, textarea[disabled], select:disabled, select[disabled], button:disabled, button[disabled], .button:disabled, .button[disabled], [role="button"]:disabled, [role="button"][disabled] { + cursor: not-allowed; + opacity: 0.75; } + +.button-group { + display: flex; + border: 0.0714285714rem solid var(--button-group-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); } + .button-group > button, .button-group [type="button"], .button-group > [type="submit"], .button-group > [type="reset"], .button-group > .button, .button-group > [role="button"] { + margin: 0; + max-width: 100%; + flex: 1 1 auto; + text-align: center; + border: 0; + border-radius: 0; + box-shadow: none; } + .button-group > :not(:first-child) { + border-left: 0.0714285714rem solid var(--button-group-border-color); } + @media screen and (max-width: 499px) { + .button-group { + flex-direction: column; } + .button-group > :not(:first-child) { + border: 0; + border-top: 0.0714285714rem solid var(--button-group-border-color); } } + +/* + Custom elements for forms and input elements. +*/ +button.primary, [type="button"].primary, [type="submit"].primary, [type="reset"].primary, .button.primary, [role="button"].primary { + --button-back-color: #1976d2; + --button-fore-color: #f8f8f8; } + button.primary:hover, button.primary:focus, [type="button"].primary:hover, [type="button"].primary:focus, [type="submit"].primary:hover, [type="submit"].primary:focus, [type="reset"].primary:hover, [type="reset"].primary:focus, .button.primary:hover, .button.primary:focus, [role="button"].primary:hover, [role="button"].primary:focus { + --button-hover-back-color: #1565c0; } + +button.secondary, [type="button"].secondary, [type="submit"].secondary, [type="reset"].secondary, .button.secondary, [role="button"].secondary { + --button-back-color: #d32f2f; + --button-fore-color: #f8f8f8; } + button.secondary:hover, button.secondary:focus, [type="button"].secondary:hover, [type="button"].secondary:focus, [type="submit"].secondary:hover, [type="submit"].secondary:focus, [type="reset"].secondary:hover, [type="reset"].secondary:focus, .button.secondary:hover, .button.secondary:focus, [role="button"].secondary:hover, [role="button"].secondary:focus { + --button-hover-back-color: #c62828; } + +button.tertiary, [type="button"].tertiary, [type="submit"].tertiary, [type="reset"].tertiary, .button.tertiary, [role="button"].tertiary { + --button-back-color: #308732; + --button-fore-color: #f8f8f8; } + button.tertiary:hover, button.tertiary:focus, [type="button"].tertiary:hover, [type="button"].tertiary:focus, [type="submit"].tertiary:hover, [type="submit"].tertiary:focus, [type="reset"].tertiary:hover, [type="reset"].tertiary:focus, .button.tertiary:hover, .button.tertiary:focus, [role="button"].tertiary:hover, [role="button"].tertiary:focus { + --button-hover-back-color: #277529; } + +button.inverse, [type="button"].inverse, [type="submit"].inverse, [type="reset"].inverse, .button.inverse, [role="button"].inverse { + --button-back-color: #212121; + --button-fore-color: #f8f8f8; } + button.inverse:hover, button.inverse:focus, [type="button"].inverse:hover, [type="button"].inverse:focus, [type="submit"].inverse:hover, [type="submit"].inverse:focus, [type="reset"].inverse:hover, [type="reset"].inverse:focus, .button.inverse:hover, .button.inverse:focus, [role="button"].inverse:hover, [role="button"].inverse:focus { + --button-hover-back-color: #111; } + +button.small, [type="button"].small, [type="submit"].small, [type="reset"].small, .button.small, [role="button"].small { + padding: calc(0.5 * var(--universal-padding)) calc(0.75 * var(--universal-padding)); + margin: var(--universal-margin); } + +button.large, [type="button"].large, [type="submit"].large, [type="reset"].large, .button.large, [role="button"].large { + padding: calc(1.5 * var(--universal-padding)) calc(2 * var(--universal-padding)); + margin: var(--universal-margin); } + +/* + Definitions for navigation elements. +*/ +/* Navigation module CSS variable definitions */ +:root { + --header-back-color: #03234b; + --header-hover-back-color: #ffd200; + --header-fore-color: #ffffff; + --header-border-color: #3cb4e6; + --nav-back-color: #ffffff; + --nav-hover-back-color: #ffe97f; + --nav-fore-color: #e6007e; + --nav-border-color: #3cb4e6; + --nav-link-color: #3cb4e6; + --footer-fore-color: #ffffff; + --footer-back-color: #03234b; + --footer-border-color: #3cb4e6; + --footer-link-color: #3cb4e6; + --drawer-back-color: #ffffff; + --drawer-hover-back-color: #ffe97f; + --drawer-border-color: #3cb4e6; + --drawer-close-color: #e6007e; } + +header { + height: 2.75rem; + background: var(--header-back-color); + color: var(--header-fore-color); + border-bottom: 0.0714285714rem solid var(--header-border-color); + padding: calc(var(--universal-padding) / 4) 0; + white-space: nowrap; + overflow-x: auto; + overflow-y: hidden; } + header.row { + box-sizing: content-box; } + header .logo { + color: var(--header-fore-color); + font-size: 1.75rem; + padding: var(--universal-padding) calc(2 * var(--universal-padding)); + text-decoration: none; } + header button, header [type="button"], header .button, header [role="button"] { + box-sizing: border-box; + position: relative; + top: calc(0rem - var(--universal-padding) / 4); + height: calc(3.1875rem + var(--universal-padding) / 2); + background: var(--header-back-color); + line-height: calc(3.1875rem - var(--universal-padding) * 1.5); + text-align: center; + color: var(--header-fore-color); + border: 0; + border-radius: 0; + margin: 0; + text-transform: uppercase; } + header button:hover, header button:focus, header [type="button"]:hover, header [type="button"]:focus, header .button:hover, header .button:focus, header [role="button"]:hover, header [role="button"]:focus { + background: var(--header-hover-back-color); } + +nav { + background: var(--nav-back-color); + color: var(--nav-fore-color); + border: 0.0714285714rem solid var(--nav-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); } + nav * { + padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); } + nav a, nav a:visited { + display: block; + color: var(--nav-link-color); + border-radius: var(--universal-border-radius); + transition: background 0.3s; } + nav a:hover, nav a:focus, nav a:visited:hover, nav a:visited:focus { + text-decoration: none; + background: var(--nav-hover-back-color); } + nav .sublink-1 { + position: relative; + margin-left: calc(2 * var(--universal-padding)); } + nav .sublink-1:before { + position: absolute; + left: calc(var(--universal-padding) - 1 * var(--universal-padding)); + top: -0.0714285714rem; + content: ''; + height: 100%; + border: 0.0714285714rem solid var(--nav-border-color); + border-left: 0; } + nav .sublink-2 { + position: relative; + margin-left: calc(4 * var(--universal-padding)); } + nav .sublink-2:before { + position: absolute; + left: calc(var(--universal-padding) - 3 * var(--universal-padding)); + top: -0.0714285714rem; + content: ''; + height: 100%; + border: 0.0714285714rem solid var(--nav-border-color); + border-left: 0; } + +footer { + background: var(--footer-back-color); + color: var(--footer-fore-color); + border-top: 0.0714285714rem solid var(--footer-border-color); + padding: calc(2 * var(--universal-padding)) var(--universal-padding); + font-size: 0.875rem; } + footer a, footer a:visited { + color: var(--footer-link-color); } + +header.sticky { + position: -webkit-sticky; + position: sticky; + z-index: 1101; + top: 0; } + +footer.sticky { + position: -webkit-sticky; + position: sticky; + z-index: 1101; + bottom: 0; } + +.drawer-toggle:before { + display: inline-block; + position: relative; + vertical-align: bottom; + content: '\00a0\2261\00a0'; + font-family: sans-serif; + font-size: 1.5em; } +@media screen and (min-width: 500px) { + .drawer-toggle:not(.persistent) { + display: none; } } + +[type="checkbox"].drawer { + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + [type="checkbox"].drawer + * { + display: block; + box-sizing: border-box; + position: fixed; + top: 0; + width: 320px; + height: 100vh; + overflow-y: auto; + background: var(--drawer-back-color); + border: 0.0714285714rem solid var(--drawer-border-color); + border-radius: 0; + margin: 0; + z-index: 1110; + right: -320px; + transition: right 0.3s; } + [type="checkbox"].drawer + * .drawer-close { + position: absolute; + top: var(--universal-margin); + right: var(--universal-margin); + z-index: 1111; + width: 2rem; + height: 2rem; + border-radius: var(--universal-border-radius); + padding: var(--universal-padding); + margin: 0; + cursor: pointer; + transition: background 0.3s; } + [type="checkbox"].drawer + * .drawer-close:before { + display: block; + content: '\00D7'; + color: var(--drawer-close-color); + position: relative; + font-family: sans-serif; + font-size: 2rem; + line-height: 1; + text-align: center; } + [type="checkbox"].drawer + * .drawer-close:hover, [type="checkbox"].drawer + * .drawer-close:focus { + background: var(--drawer-hover-back-color); } + @media screen and (max-width: 320px) { + [type="checkbox"].drawer + * { + width: 100%; } } + [type="checkbox"].drawer:checked + * { + right: 0; } + @media screen and (min-width: 500px) { + [type="checkbox"].drawer:not(.persistent) + * { + position: static; + height: 100%; + z-index: 1100; } + [type="checkbox"].drawer:not(.persistent) + * .drawer-close { + display: none; } } + +/* + Definitions for the responsive table component. +*/ +/* Table module CSS variable definitions. */ +:root { + --table-border-color: #03234b; + --table-border-separator-color: #03234b; + --table-head-back-color: #03234b; + --table-head-fore-color: #ffffff; + --table-body-back-color: #ffffff; + --table-body-fore-color: #03234b; + --table-body-alt-back-color: #f4f4f4; } + +table { + border-collapse: separate; + border-spacing: 0; + margin: 0; + display: flex; + flex: 0 1 auto; + flex-flow: row wrap; + padding: var(--universal-padding); + padding-top: 0; } + table caption { + font-size: 1rem; + margin: calc(2 * var(--universal-margin)) 0; + max-width: 100%; + flex: 0 0 100%; } + table thead, table tbody { + display: flex; + flex-flow: row wrap; + border: 0.0714285714rem solid var(--table-border-color); } + table thead { + z-index: 999; + border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0; + border-bottom: 0.0714285714rem solid var(--table-border-separator-color); } + table tbody { + border-top: 0; + margin-top: calc(0 - var(--universal-margin)); + border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } + table tr { + display: flex; + padding: 0; } + table th, table td { + padding: calc(0.5 * var(--universal-padding)); + font-size: 0.9rem; } + table th { + text-align: left; + background: var(--table-head-back-color); + color: var(--table-head-fore-color); } + table td { + background: var(--table-body-back-color); + color: var(--table-body-fore-color); + border-top: 0.0714285714rem solid var(--table-border-color); } + +table:not(.horizontal) { + overflow: auto; + max-height: 100%; } + table:not(.horizontal) thead, table:not(.horizontal) tbody { + max-width: 100%; + flex: 0 0 100%; } + table:not(.horizontal) tr { + flex-flow: row wrap; + flex: 0 0 100%; } + table:not(.horizontal) th, table:not(.horizontal) td { + flex: 1 0 0%; + overflow: hidden; + text-overflow: ellipsis; } + table:not(.horizontal) thead { + position: sticky; + top: 0; } + table:not(.horizontal) tbody tr:first-child td { + border-top: 0; } + +table.horizontal { + border: 0; } + table.horizontal thead, table.horizontal tbody { + border: 0; + flex: .2 0 0; + flex-flow: row nowrap; } + table.horizontal tbody { + overflow: auto; + justify-content: space-between; + flex: .8 0 0; + margin-left: 0; + padding-bottom: calc(var(--universal-padding) / 4); } + table.horizontal tr { + flex-direction: column; + flex: 1 0 auto; } + table.horizontal th, table.horizontal td { + width: auto; + border: 0; + border-bottom: 0.0714285714rem solid var(--table-border-color); } + table.horizontal th:not(:first-child), table.horizontal td:not(:first-child) { + border-top: 0; } + table.horizontal th { + text-align: right; + border-left: 0.0714285714rem solid var(--table-border-color); + border-right: 0.0714285714rem solid var(--table-border-separator-color); } + table.horizontal thead tr:first-child { + padding-left: 0; } + table.horizontal th:first-child, table.horizontal td:first-child { + border-top: 0.0714285714rem solid var(--table-border-color); } + table.horizontal tbody tr:last-child td { + border-right: 0.0714285714rem solid var(--table-border-color); } + table.horizontal tbody tr:last-child td:first-child { + border-top-right-radius: 0.25rem; } + table.horizontal tbody tr:last-child td:last-child { + border-bottom-right-radius: 0.25rem; } + table.horizontal thead tr:first-child th:first-child { + border-top-left-radius: 0.25rem; } + table.horizontal thead tr:first-child th:last-child { + border-bottom-left-radius: 0.25rem; } + +@media screen and (max-width: 499px) { + table, table.horizontal { + border-collapse: collapse; + border: 0; + width: 100%; + display: table; } + table thead, table th, table.horizontal thead, table.horizontal th { + border: 0; + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + padding: 0; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + table tbody, table.horizontal tbody { + border: 0; + display: table-row-group; } + table tr, table.horizontal tr { + display: block; + border: 0.0714285714rem solid var(--table-border-color); + border-radius: var(--universal-border-radius); + background: #ffffff; + padding: var(--universal-padding); + margin: var(--universal-margin); + margin-bottom: calc(1 * var(--universal-margin)); } + table th, table td, table.horizontal th, table.horizontal td { + width: auto; } + table td, table.horizontal td { + display: block; + border: 0; + text-align: right; } + table td:before, table.horizontal td:before { + content: attr(data-label); + float: left; + font-weight: 600; } + table th:first-child, table td:first-child, table.horizontal th:first-child, table.horizontal td:first-child { + border-top: 0; } + table tbody tr:last-child td, table.horizontal tbody tr:last-child td { + border-right: 0; } } +table tr:nth-of-type(2n) > td { + background: var(--table-body-alt-back-color); } + +@media screen and (max-width: 500px) { + table tr:nth-of-type(2n) { + background: var(--table-body-alt-back-color); } } +:root { + --table-body-hover-back-color: #90caf9; } + +table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td { + background: var(--table-body-hover-back-color); } + +@media screen and (max-width: 500px) { + table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td { + background: var(--table-body-hover-back-color); } } +/* + Definitions for contextual background elements, toasts and tooltips. +*/ +/* Contextual module CSS variable definitions */ +:root { + --mark-back-color: #3cb4e6; + --mark-fore-color: #ffffff; } + +mark { + background: var(--mark-back-color); + color: var(--mark-fore-color); + font-size: 0.95em; + line-height: 1em; + border-radius: var(--universal-border-radius); + padding: calc(var(--universal-padding) / 4) var(--universal-padding); } + mark.inline-block { + display: inline-block; + font-size: 1em; + line-height: 1.4; + padding: calc(var(--universal-padding) / 2) var(--universal-padding); } + +:root { + --toast-back-color: #424242; + --toast-fore-color: #fafafa; } + +.toast { + position: fixed; + bottom: calc(var(--universal-margin) * 3); + left: 50%; + transform: translate(-50%, -50%); + z-index: 1111; + color: var(--toast-fore-color); + background: var(--toast-back-color); + border-radius: calc(var(--universal-border-radius) * 16); + padding: var(--universal-padding) calc(var(--universal-padding) * 3); } + +:root { + --tooltip-back-color: #212121; + --tooltip-fore-color: #fafafa; } + +.tooltip { + position: relative; + display: inline-block; } + .tooltip:before, .tooltip:after { + position: absolute; + opacity: 0; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); + transition: all 0.3s; + z-index: 1010; + left: 50%; } + .tooltip:not(.bottom):before, .tooltip:not(.bottom):after { + bottom: 75%; } + .tooltip.bottom:before, .tooltip.bottom:after { + top: 75%; } + .tooltip:hover:before, .tooltip:hover:after, .tooltip:focus:before, .tooltip:focus:after { + opacity: 1; + clip: auto; + -webkit-clip-path: inset(0%); + clip-path: inset(0%); } + .tooltip:before { + content: ''; + background: transparent; + border: var(--universal-margin) solid transparent; + left: calc(50% - var(--universal-margin)); } + .tooltip:not(.bottom):before { + border-top-color: #212121; } + .tooltip.bottom:before { + border-bottom-color: #212121; } + .tooltip:after { + content: attr(aria-label); + color: var(--tooltip-fore-color); + background: var(--tooltip-back-color); + border-radius: var(--universal-border-radius); + padding: var(--universal-padding); + white-space: nowrap; + transform: translateX(-50%); } + .tooltip:not(.bottom):after { + margin-bottom: calc(2 * var(--universal-margin)); } + .tooltip.bottom:after { + margin-top: calc(2 * var(--universal-margin)); } + +:root { + --modal-overlay-color: rgba(0, 0, 0, 0.45); + --modal-close-color: #e6007e; + --modal-close-hover-color: #ffe97f; } + +[type="checkbox"].modal { + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + [type="checkbox"].modal + div { + position: fixed; + top: 0; + left: 0; + display: none; + width: 100vw; + height: 100vh; + background: var(--modal-overlay-color); } + [type="checkbox"].modal + div .card { + margin: 0 auto; + max-height: 50vh; + overflow: auto; } + [type="checkbox"].modal + div .card .modal-close { + position: absolute; + top: 0; + right: 0; + width: 1.75rem; + height: 1.75rem; + border-radius: var(--universal-border-radius); + padding: var(--universal-padding); + margin: 0; + cursor: pointer; + transition: background 0.3s; } + [type="checkbox"].modal + div .card .modal-close:before { + display: block; + content: '\00D7'; + color: var(--modal-close-color); + position: relative; + font-family: sans-serif; + font-size: 1.75rem; + line-height: 1; + text-align: center; } + [type="checkbox"].modal + div .card .modal-close:hover, [type="checkbox"].modal + div .card .modal-close:focus { + background: var(--modal-close-hover-color); } + [type="checkbox"].modal:checked + div { + display: flex; + flex: 0 1 auto; + z-index: 1200; } + [type="checkbox"].modal:checked + div .card .modal-close { + z-index: 1211; } + +:root { + --collapse-label-back-color: #03234b; + --collapse-label-fore-color: #ffffff; + --collapse-label-hover-back-color: #3cb4e6; + --collapse-selected-label-back-color: #3cb4e6; + --collapse-border-color: var(--collapse-label-back-color); + --collapse-selected-border-color: #ceecf8; + --collapse-content-back-color: #ffffff; + --collapse-selected-label-border-color: #3cb4e6; } + +.collapse { + width: calc(100% - 2 * var(--universal-margin)); + opacity: 1; + display: flex; + flex-direction: column; + margin: var(--universal-margin); + border-radius: var(--universal-border-radius); } + .collapse > [type="radio"], .collapse > [type="checkbox"] { + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + .collapse > label { + flex-grow: 1; + display: inline-block; + height: 1.25rem; + cursor: pointer; + transition: background 0.2s; + color: var(--collapse-label-fore-color); + background: var(--collapse-label-back-color); + border: 0.0714285714rem solid var(--collapse-selected-border-color); + padding: calc(1.25 * var(--universal-padding)); } + .collapse > label:hover, .collapse > label:focus { + background: var(--collapse-label-hover-back-color); } + .collapse > label + div { + flex-basis: auto; + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); + transition: max-height 0.3s; + max-height: 1px; } + .collapse > :checked + label { + background: var(--collapse-selected-label-back-color); + border-color: var(--collapse-selected-label-border-color); } + .collapse > :checked + label + div { + box-sizing: border-box; + position: relative; + width: 100%; + height: auto; + overflow: auto; + margin: 0; + background: var(--collapse-content-back-color); + border: 0.0714285714rem solid var(--collapse-selected-border-color); + border-top: 0; + padding: var(--universal-padding); + clip: auto; + -webkit-clip-path: inset(0%); + clip-path: inset(0%); + max-height: 100%; } + .collapse > label:not(:first-of-type) { + border-top: 0; } + .collapse > label:first-of-type { + border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0; } + .collapse > label:last-of-type:not(:first-of-type) { + border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } + .collapse > label:last-of-type:first-of-type { + border-radius: var(--universal-border-radius); } + .collapse > :checked:last-of-type:not(:first-of-type) + label { + border-radius: 0; } + .collapse > :checked:last-of-type + label + div { + border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } + +/* + Custom elements for contextual background elements, toasts and tooltips. +*/ +mark.tertiary { + --mark-back-color: #3cb4e6; } + +mark.tag { + padding: calc(var(--universal-padding)/2) var(--universal-padding); + border-radius: 1em; } + +/* + Definitions for progress elements and spinners. +*/ +/* Progress module CSS variable definitions */ +:root { + --progress-back-color: #3cb4e6; + --progress-fore-color: #555; } + +progress { + display: block; + vertical-align: baseline; + -webkit-appearance: none; + -moz-appearance: none; + appearance: none; + height: 0.75rem; + width: calc(100% - 2 * var(--universal-margin)); + margin: var(--universal-margin); + border: 0; + border-radius: calc(2 * var(--universal-border-radius)); + background: var(--progress-back-color); + color: var(--progress-fore-color); } + progress::-webkit-progress-value { + background: var(--progress-fore-color); + border-top-left-radius: calc(2 * var(--universal-border-radius)); + border-bottom-left-radius: calc(2 * var(--universal-border-radius)); } + progress::-webkit-progress-bar { + background: var(--progress-back-color); } + progress::-moz-progress-bar { + background: var(--progress-fore-color); + border-top-left-radius: calc(2 * var(--universal-border-radius)); + border-bottom-left-radius: calc(2 * var(--universal-border-radius)); } + progress[value="1000"]::-webkit-progress-value { + border-radius: calc(2 * var(--universal-border-radius)); } + progress[value="1000"]::-moz-progress-bar { + border-radius: calc(2 * var(--universal-border-radius)); } + progress.inline { + display: inline-block; + vertical-align: middle; + width: 60%; } + +:root { + --spinner-back-color: #ddd; + --spinner-fore-color: #555; } + +@keyframes spinner-donut-anim { + 0% { + transform: rotate(0deg); } + 100% { + transform: rotate(360deg); } } +.spinner { + display: inline-block; + margin: var(--universal-margin); + border: 0.25rem solid var(--spinner-back-color); + border-left: 0.25rem solid var(--spinner-fore-color); + border-radius: 50%; + width: 1.25rem; + height: 1.25rem; + animation: spinner-donut-anim 1.2s linear infinite; } + +/* + Custom elements for progress bars and spinners. +*/ +progress.primary { + --progress-fore-color: #1976d2; } + +progress.secondary { + --progress-fore-color: #d32f2f; } + +progress.tertiary { + --progress-fore-color: #308732; } + +.spinner.primary { + --spinner-fore-color: #1976d2; } + +.spinner.secondary { + --spinner-fore-color: #d32f2f; } + +.spinner.tertiary { + --spinner-fore-color: #308732; } + +/* + Definitions for icons - powered by Feather (https://feathericons.com/). +*/ +span[class^='icon-'] { + display: inline-block; + height: 1em; + width: 1em; + vertical-align: -0.125em; + background-size: contain; + margin: 0 calc(var(--universal-margin) / 4); } + span[class^='icon-'].secondary { + -webkit-filter: invert(25%); + filter: invert(25%); } + span[class^='icon-'].inverse { + -webkit-filter: invert(100%); + filter: invert(100%); } + +span.icon-alert { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='8' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='16' x2='12' y2='16'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-bookmark { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M19 21l-7-5-7 5V5a2 2 0 0 1 2-2h10a2 2 0 0 1 2 2z'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-calendar { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='4' width='18' height='18' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='16' y1='2' x2='16' y2='6'%3E%3C/line%3E%3Cline x1='8' y1='2' x2='8' y2='6'%3E%3C/line%3E%3Cline x1='3' y1='10' x2='21' y2='10'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-credit { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='1' y='4' width='22' height='16' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='1' y1='10' x2='23' y2='10'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-edit { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 14.66V20a2 2 0 0 1-2 2H4a2 2 0 0 1-2-2V6a2 2 0 0 1 2-2h5.34'%3E%3C/path%3E%3Cpolygon points='18 2 22 6 12 16 8 16 8 12 18 2'%3E%3C/polygon%3E%3C/svg%3E"); } +span.icon-link { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M18 13v6a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2V8a2 2 0 0 1 2-2h6'%3E%3C/path%3E%3Cpolyline points='15 3 21 3 21 9'%3E%3C/polyline%3E%3Cline x1='10' y1='14' x2='21' y2='3'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-help { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M9.09 9a3 3 0 0 1 5.83 1c0 2-3 3-3 3'%3E%3C/path%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='17' x2='12' y2='17'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-home { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M3 9l9-7 9 7v11a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2z'%3E%3C/path%3E%3Cpolyline points='9 22 9 12 15 12 15 22'%3E%3C/polyline%3E%3C/svg%3E"); } +span.icon-info { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='16' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='8' x2='12' y2='8'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-lock { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='11' width='18' height='11' rx='2' ry='2'%3E%3C/rect%3E%3Cpath d='M7 11V7a5 5 0 0 1 10 0v4'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-mail { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 4h16c1.1 0 2 .9 2 2v12c0 1.1-.9 2-2 2H4c-1.1 0-2-.9-2-2V6c0-1.1.9-2 2-2z'%3E%3C/path%3E%3Cpolyline points='22,6 12,13 2,6'%3E%3C/polyline%3E%3C/svg%3E"); } +span.icon-location { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 10c0 7-9 13-9 13s-9-6-9-13a9 9 0 0 1 18 0z'%3E%3C/path%3E%3Ccircle cx='12' cy='10' r='3'%3E%3C/circle%3E%3C/svg%3E"); } +span.icon-phone { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M22 16.92v3a2 2 0 0 1-2.18 2 19.79 19.79 0 0 1-8.63-3.07 19.5 19.5 0 0 1-6-6 19.79 19.79 0 0 1-3.07-8.67A2 2 0 0 1 4.11 2h3a2 2 0 0 1 2 1.72 12.84 12.84 0 0 0 .7 2.81 2 2 0 0 1-.45 2.11L8.09 9.91a16 16 0 0 0 6 6l1.27-1.27a2 2 0 0 1 2.11-.45 12.84 12.84 0 0 0 2.81.7A2 2 0 0 1 22 16.92z'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-rss { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 11a9 9 0 0 1 9 9'%3E%3C/path%3E%3Cpath d='M4 4a16 16 0 0 1 16 16'%3E%3C/path%3E%3Ccircle cx='5' cy='19' r='1'%3E%3C/circle%3E%3C/svg%3E"); } +span.icon-search { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='11' cy='11' r='8'%3E%3C/circle%3E%3Cline x1='21' y1='21' x2='16.65' y2='16.65'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-settings { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='3'%3E%3C/circle%3E%3Cpath d='M19.4 15a1.65 1.65 0 0 0 .33 1.82l.06.06a2 2 0 0 1 0 2.83 2 2 0 0 1-2.83 0l-.06-.06a1.65 1.65 0 0 0-1.82-.33 1.65 1.65 0 0 0-1 1.51V21a2 2 0 0 1-2 2 2 2 0 0 1-2-2v-.09A1.65 1.65 0 0 0 9 19.4a1.65 1.65 0 0 0-1.82.33l-.06.06a2 2 0 0 1-2.83 0 2 2 0 0 1 0-2.83l.06-.06a1.65 1.65 0 0 0 .33-1.82 1.65 1.65 0 0 0-1.51-1H3a2 2 0 0 1-2-2 2 2 0 0 1 2-2h.09A1.65 1.65 0 0 0 4.6 9a1.65 1.65 0 0 0-.33-1.82l-.06-.06a2 2 0 0 1 0-2.83 2 2 0 0 1 2.83 0l.06.06a1.65 1.65 0 0 0 1.82.33H9a1.65 1.65 0 0 0 1-1.51V3a2 2 0 0 1 2-2 2 2 0 0 1 2 2v.09a1.65 1.65 0 0 0 1 1.51 1.65 1.65 0 0 0 1.82-.33l.06-.06a2 2 0 0 1 2.83 0 2 2 0 0 1 0 2.83l-.06.06a1.65 1.65 0 0 0-.33 1.82V9a1.65 1.65 0 0 0 1.51 1H21a2 2 0 0 1 2 2 2 2 0 0 1-2 2h-.09a1.65 1.65 0 0 0-1.51 1z'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-share { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='18' cy='5' r='3'%3E%3C/circle%3E%3Ccircle cx='6' cy='12' r='3'%3E%3C/circle%3E%3Ccircle cx='18' cy='19' r='3'%3E%3C/circle%3E%3Cline x1='8.59' y1='13.51' x2='15.42' y2='17.49'%3E%3C/line%3E%3Cline x1='15.41' y1='6.51' x2='8.59' y2='10.49'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-cart { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='9' cy='21' r='1'%3E%3C/circle%3E%3Ccircle cx='20' cy='21' r='1'%3E%3C/circle%3E%3Cpath d='M1 1h4l2.68 13.39a2 2 0 0 0 2 1.61h9.72a2 2 0 0 0 2-1.61L23 6H6'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-upload { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 15v4a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2v-4'%3E%3C/path%3E%3Cpolyline points='17 8 12 3 7 8'%3E%3C/polyline%3E%3Cline x1='12' y1='3' x2='12' y2='15'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-user { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 21v-2a4 4 0 0 0-4-4H8a4 4 0 0 0-4 4v2'%3E%3C/path%3E%3Ccircle cx='12' cy='7' r='4'%3E%3C/circle%3E%3C/svg%3E"); } + +/* + Definitions for STMicroelectronics icons (https://brandportal.st.com/document/26). +*/ +span.icon-st-update { + background-image: url("Update.svg"); } +span.icon-st-add { + background-image: url("Add button.svg"); } + +/* + Definitions for utilities and helper classes. +*/ +/* Utility module CSS variable definitions */ +:root { + --generic-border-color: rgba(0, 0, 0, 0.3); + --generic-box-shadow: 0 0.2857142857rem 0.2857142857rem 0 rgba(0, 0, 0, 0.125), 0 0.1428571429rem 0.1428571429rem -0.1428571429rem rgba(0, 0, 0, 0.125); } + +.hidden { + display: none !important; } + +.visually-hidden { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } + +.bordered { + border: 0.0714285714rem solid var(--generic-border-color) !important; } + +.rounded { + border-radius: var(--universal-border-radius) !important; } + +.circular { + border-radius: 50% !important; } + +.shadowed { + box-shadow: var(--generic-box-shadow) !important; } + +.responsive-margin { + margin: calc(var(--universal-margin) / 4) !important; } + @media screen and (min-width: 500px) { + .responsive-margin { + margin: calc(var(--universal-margin) / 2) !important; } } + @media screen and (min-width: 1280px) { + .responsive-margin { + margin: var(--universal-margin) !important; } } + +.responsive-padding { + padding: calc(var(--universal-padding) / 4) !important; } + @media screen and (min-width: 500px) { + .responsive-padding { + padding: calc(var(--universal-padding) / 2) !important; } } + @media screen and (min-width: 1280px) { + .responsive-padding { + padding: var(--universal-padding) !important; } } + +@media screen and (max-width: 499px) { + .hidden-sm { + display: none !important; } } +@media screen and (min-width: 500px) and (max-width: 1279px) { + .hidden-md { + display: none !important; } } +@media screen and (min-width: 1280px) { + .hidden-lg { + display: none !important; } } +@media screen and (max-width: 499px) { + .visually-hidden-sm { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } } +@media screen and (min-width: 500px) and (max-width: 1279px) { + .visually-hidden-md { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } } +@media screen and (min-width: 1280px) { + .visually-hidden-lg { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } } + +/*# sourceMappingURL=mini-custom.css.map */ + +img[alt="ST logo"] { display: block; margin: auto; width: 75%; max-width: 250px; min-width: 71px; } +img[alt="Cube logo"] { float: right; width: 30%; max-width: 10rem; min-width: 8rem; padding-right: 1rem;} + +.figure { + display: block; + margin-left: auto; + margin-right: auto; + text-align: center; +} \ No newline at end of file diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/_htmresc/st_logo_2020.png b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/_htmresc/st_logo_2020.png new file mode 100644 index 0000000000000000000000000000000000000000..d6cebb5ac70e0594cbe37a6b60036a80ef3bed37 GIT binary patch literal 7520 zcmcI|WmKC@*KTl!K!Z~t6qn*&DDF_CK%q#B6QmH_DHL}I6b%;K-J$eBN|2xh0+bea zmtyV5bG|?CpZBcu=iF<}z4q*xz1LhL*PcBwx;m;Pgmi=e0DweYO-UaBz)*UWZ}4#+ zCC-V!SC16}H#HLv0Dy?%--0o{5_}H;Jf%=ql7H=+dziOk_)KzUSaiQ9L<^g!49k}} z?4y$V zrsn3Ul^TY`00G_J_8;F7Sr5c3Y)f-yOYl{fS0avfKJg7R%r!y-ohcBkr6XBZBkE)( z_t+tVV2}G1_CN!)yWes*wa-AGwk31N_T1`)4COlfz+o(9S90e?6jHV4)!>`j+oRqp z)gb?rtSdw<#&c?q!OKB+Ncn!kr5JR2EYan8HAPXBw*Oh-F(6GmaC!`$p7fl!_Cdu> z5@PUMR_K5&jgevDepWqepZVdMHR$q>ga=7k0ltW$HHVn>HRa!#(+BW_jN$5rx^MtR zzWT7tNWQeFzEp+86jOYI=I)*GZYEiXlf-Mw%tJ^ptL%2)%#PmUjxC4wx@%KxQ)8kO?|7E1 zd@5gd9_$*6nx?fj*iF_EJT*PYLFP}d8*Fw>cu3@&nm%V_C}V7HMmg|Nl#1J1^#)uz zZag|X>{6j-myvL}3(H8o3resNBq_jcuJuyT!QuXnNN&zG^tG? z>y*dy1#XfwyCE#UiLT(~LYAVwp)epErJLsHBA|l0xo)kxLAPob+7tFlr{7x8(#v|O zknK}QC6|~=cTJ0;x9MWMKua;LdTKIHX>35a@7{5y0MQ|zqsP64mM~`gJ&&R{pSUBA zf3Y>k>d|xdzBFztjtO~{y%@LUdwSgzEj=69hH3-NNWx7<|49%2%lvTEeE3_|$~iDd zlktnxf|NB>Bui)yY;%TXgWA;rhODxR!-4GzxKd473I)3;j zS4-Vun<^vqZ4)HbwVzq%5%)S!>Q(Y&PkF ze1ab_oy?_$PZT-mKJ3K^;6MrB*Wc$lkYJ_460AFYEq{AjlDxm;5GRwOsm>doJy3Z;a$FSu-q`X)Hw&o~?_`Dnpx4dOj6#)bGOdZbj4hD`l|&#v~K+WrGO zpLCVQg=*h=4H1sK)D*Pxtb#p`c+g-eK65k!CEZjLIrfm}5<4@KVqZ#8(S$vs{?Xv) zN(}CKeeLR%I)W!p(l-`utKmBbJk-On{)ciqUN5%?TS8uwKU(8}Mxhsb&qHL~DDcB@qi} z4z%efV#K69a#lShPt5}*7ME@^xunFR{k;|qp z`_Hgdj_Qle?%Ydlr3f^SdRkUncIj7qTiu85tA$v`#419Nlof8tjqUjO z!Rwyq$Krfh`(@MiE+)yie&jU^crprYV&?zN!2b33S2qtW+zB$nahDhVZiQ12bmcwYBcT8KS>v`jsuI@X zy^k^7>TM5Ndp@}pSl6vmkk*u`@C`z(gq||K2>y=Y#w1i`Nk2zAP7{_^ACq;bQmT<4 z;b~K3=?mhZX#~jQnZjdU={NFp^HRr~;^PXQ*UIHzkq}Xsn!56*ZCOOEt|^ zawUwGqs;zCEGKTz&(a(@h#0sCE+@`3Y<&}9!(;Pw&`C+d#D?`##&!@*ERaH0fksrh zfk2svh3!d~h{SC6BNKN2j6(lzC>S^_*eh{@gR zP$rV4$nqV1y|zYpd;nQr-`Vlp(5sQXx9AibC?xc7pUV)v2cWfHu3{KLbfP;;;`I&)mWqLcXt6s+5fps9R?K>hGR$5;=( zo#;zzQ5!w+(99p1_gh^?F#$tpMd+4%G|K`XG_#@A>30WD2L9!0a>wRASg`M?^z#)| zifb$d^KUD&3qLsr-@}r_7p${gdmRqhy819bj?yI-v({I?0o3_8d>CZmCzqH4{{QtD z|6dvgm<^~668G`6wLw4C4y-o9E9ZG3RiH^&;rrKSBT@bMR+!TlYo*9P;?Z>xORMV3ndQp9EyNn!!~j&x&$gDVke|t#!{QoegHm+sT7cSjwSu z)jZlx1pHrrx0&YCZWJ4xC&U%r_IwfJOxnYqYMcZn&_hgnKuls z>(Y$qjIhcweo^A_VVq_#UR&urF%UbI^><5L5zbV9owMQviM*_{@i|dke!!v8a_yG! zl%#ay{(6U_N3-)yeif3tx6>aQSf1r zO~OuNW<8a~bi6Xby0@tKw0@f1R!@+3S2nf#F&j~l0mrNCtjoZdPYob?g!Vx4F-uA2 z4uS>8eR?dA9i>C|cm-m5lO0m@$f(DB6Z<9Pe07xR`l4$ks3eZ@v5}1?^YNQy-tB(` zgUNZrGVf#b~`}jew;MQG1O~VDk_i*<)p9DfFfd;vLy4QZT zMYh|DxJg3-!{szUN*uo&`&DUkzq4qG2`Lj;Ar46DYUymcviS{Unhzmx z=LwZ-Lr{t1z?9Oip%!z{j+Z%_@u?C78I`V4fC`icG1c|2;`EoLK$ z)9|wrAV&V1Vgts~tQCw0X?X{74W"NJQ zW3BP!5c~4zzHJScwQK9L_%m%L`*q{1aW_3rObki~B~=Dwp`;@w`>xZ6;L_6oR^ecEcmup`yb}lgsmv zQByrxc)Qqm(Hwmq%fLjqcrJ5QR?z_*vb~Iy~RXUY8u-D8AqTzetwNNA8~N z$j&1>#IrkSslUqXW|l}q_TlTVKAjRI@~7(GLf4M>GM!3u_)y6ORe6BQUmrQ16%OdZKo(?AYXK$u@=)TPUi1EZaLBu zuEB(5GX2vcoHS%zMUW!DZ)&xRo@mhouk|hMgHIG>cO-Ah(0AMNlq@?cPpy==-!#qR zBov7l3G?P*KM(vU;Apo-(-Bw;sdQJkh~r)W$KRQKd!#(A8M34^MhD10Ra={AqSvjy z3>PkgA}f^@Rg1$dX=jaEB_V%_vn(W<111_s!g>CYrcwJTJ63Eeg6{_C`aMQIgKctR zHMjkr+y6gK!v6=6;CGl#?PqmiX`A@dmmvZ}-X$*q8}G(xq|voo`=$YZuQAa8f9ApK z1VQiEUQC=OO{|Nc8ZrXH208X|XCzIRO?+Nb55Jt@va9hqBpv)uY6ma-csvSlJoJOC zK;w~s?#r)K@gm*;((JsWHU-KvFTF)q>AzwPq)I+}OrSpxh!-CM1VEMfw1fpfVL7p{ z)I$rNp5kPYDsvXL>8nV{#0fa*lm`Z;0Z=c^1qveY2uk&7nhMRl`0EsvUuvwdF&o)PCVN3wmFBPegWzooF6y~b} zY>X2;LO~&rbvx59?(4^aR+s1C6hI4r&x9Q9jL9);KZEw_x%TWZXaMzK6|2XG9$IU% zkEq}t^YOaa4s`%7F31X-#SfMgNp+4R=g2G|O^W)6^2fEsmkTTaVhKCip+3qWuN8?y zaSD_k6%-@Ifhm`z02=ZWA-pi5`A=7ztHWpP2K5rCW{>!wIUOYrH``#bz>qVSH76=8 zyJ!sNBxt;dMTn}yzUTCq1!w;N7pzb?WJrQ50W+`meL{k8i0VhFsPUz(07k`l` zg1Ifl1fc-^p^MQCpK~Jk&L!*mWfNA!&MSu`sPmti>K-;I5Dk00nB3vOl4!JwjEx^X zWQsIp2Ea_>`9f@%zGl4i3FAO9=e$2^b_>_I*dqiLJ=@TejStM?^yX$9dW`#ha)PEF zPr0zUJX!j-juYK*olG_9axQniXhF|E}oSTG_S)FZ3sN4T@q zy{l;!{UGc};YVaT97tx3s7P$WsW2^*I+Hy;vqndG!9S?tZtDIRif1=bBsqtW-n7$O zWy}Z%jKSkgLX#1p>|#4l-!$c+kA`++Ixv(Rm`;Ilb3q3tD|QjaPQ8)BJ=8R*15?nL zJR{yuqOG&!JrSZ${#NY#b!k)yDajQ$A}fUQhe7ueN6h2Pj3wY5eo|7$PaJD zM69(ee1qlSyLn)Ln6)o53Lj)elqG}gb^c}qd(q&$8B5N%nSvEjUIoEXO^obv=A7QGZzNzjO*H=*b2!86Wnqdy~8ePkq@1D1)Q^O)JG;fUCV z`rgD}dJ{7BUyBbgoTL91w^q-CfBpDr?0R38`L%p9&Q#%r*@=9p-Ioqy+WscLq?jq5 zfyYNkxr7w)-(!c85mt!FjNJ4UE6P8p8sc#Kb4L1N3!yaCo9@t3n8s}K)1!w8x77xU zo-NY3SR*Pgt#~7F;y^J&Y%z^+C9wu;hN|TC7dqSHOB&kE)Q)6Ad(l&+tA@$@w0bhJ z6xc6EJ6nm{=|V7Vo&qcXc4i)D?X0Uk$p7~iI#ci?#fxvM z78`u%m5S@^_F;_foidufzP z&ueh-zU1yM&8~0lmOfkio-gBex`)?hCJcI8Jv*R0c|WUqSq z?RU?Rmm=3t_2C%%UW9c*D%T{T{EjryCKnsz9-*Bs0}M*xS&-odhCK5eS_Eqi&c6J4o|f&;uUT=p7Fedw#EUl4%Jv{w zq-cCF^otBvw~~$yj6O>>;VqU)3Ml&Atm$B(Ht8=+&x2VS5aWD&t*+04{@k^Gn~yHY zWYC%@ld;g_qz=k*;Iv&xs5M85cEZCU&n2Baf>R6*bN>V|!)eF&l#C93eAMLD=ZF7= zOISFfB5P;F!ngWD3jfMJE_53F&dFc{h2TwSbT*(h6!c}_5_UFeB_*DiyCrtQ7Byr@ z-aCWVt?J}YP7-lfelbrCgZ5mdv(^W&Yf^OvpI}#NbS1Lc`r4&t#3kM!utm&#a;?GR z-1FusfX7&?a9h`%8wf-ub7UXp44xm4w04)S$}}_hPqn-#IabO^bo6$K07>?%G5Xs( zA$*lz_K>lAJ_o<;fsP-*-%~O(716KRqVq+X@=5J~Z~bba(yWL`;EN`@Mr2it&Lkgb z&I|R5!`ZSk%)xFX*FYDaAh=5qWSY@rx1Du9J$$=lh#!~NcFJM&aOv)eqg_@`i^zJCR9a%_{k_i%msw5q z*3!~#Xx3r|VaAwiG}~9M#c`=$Uk6~xe)47ymW+;0DD_lV67L#ouJBa7mF{)X^?eIvPdOMu4ksr`jUP$~{x@?ev2 zdX#ite2RMim01PEg`;qfwg^;v8nx9F!CtNCvz)V{PVgCs*;_@_Rk*oLx@f7hJ7^^1 zu66b)mb!ZMXLZ%8dj-+JCMoWS-Wji-Q-~U7Pt~UiXMej8JcNjk<6?Wk9eLBIhu&Vo^0;AH> z;Q5^a!NZhP(vDfBv&?jdnQavv#8N0E{ZEgs>|1)qYo^t5 zIV$g~`C2%g$*(z4)8hJlK2mF-MJW#3%Cs6`uAvsgRtTo8n!Et)1pZx@_9I18 zw7ER9v~DyrC*R$do9aEw5r@B)YzHOLB^-c9Eu9D!sFmI8^VljVKE89{zY_8PTSF+J b^}%0^qYmp2WD(pA|JtZ4>nPPKybJpu3@X?! literal 0 HcmV?d00001 diff --git a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md index c196d1b070..8b5055d8db 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md +++ b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md @@ -18,6 +18,7 @@ * STM32MP1: 1.6.0 * STM32U5: 1.3.1 * STM32WB: 1.12.0 + * STM32WBA: 1.2.0 * STM32WL: 1.2.0 Release notes of each STM32YYxx CMSIS available here: From 6f1848bf22842c4dc7a4df02babc521156bbb966 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Fri, 9 Feb 2024 17:16:26 +0100 Subject: [PATCH 03/21] system(WBA): add STM32WBAxx system source files Signed-off-by: Frederic Pillon --- system/STM32WBAxx/stm32wbaxx_hal_conf.h | 16 + .../STM32WBAxx/stm32wbaxx_hal_conf_default.h | 350 ++++++++++++++++ system/STM32WBAxx/system_stm32wbaxx.c | 381 ++++++++++++++++++ 3 files changed, 747 insertions(+) create mode 100644 system/STM32WBAxx/stm32wbaxx_hal_conf.h create mode 100644 system/STM32WBAxx/stm32wbaxx_hal_conf_default.h create mode 100644 system/STM32WBAxx/system_stm32wbaxx.c diff --git a/system/STM32WBAxx/stm32wbaxx_hal_conf.h b/system/STM32WBAxx/stm32wbaxx_hal_conf.h new file mode 100644 index 0000000000..fe75d2f0b9 --- /dev/null +++ b/system/STM32WBAxx/stm32wbaxx_hal_conf.h @@ -0,0 +1,16 @@ +#ifndef __STM32WBAxx_HAL_CONF_H +#define __STM32WBAxx_HAL_CONF_H + +#include "variant.h" + +/* STM32WBAxx specific HAL configuration options. */ +#if __has_include("hal_conf_custom.h") +#include "hal_conf_custom.h" +#else +#if __has_include("hal_conf_extra.h") +#include "hal_conf_extra.h" +#endif +#include "stm32wbaxx_hal_conf_default.h" +#endif + +#endif /* __STM32WBAxx_HAL_CONF_H */ \ No newline at end of file diff --git a/system/STM32WBAxx/stm32wbaxx_hal_conf_default.h b/system/STM32WBAxx/stm32wbaxx_hal_conf_default.h new file mode 100644 index 0000000000..4f8c0988be --- /dev/null +++ b/system/STM32WBAxx/stm32wbaxx_hal_conf_default.h @@ -0,0 +1,350 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_conf_template.h + * @author MCD Application Team + * @brief HAL configuration template file. + * This file should be copied to the application folder and renamed + * to stm32wbaxx_hal_conf.h. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_HAL_CONF_H +#define STM32WBAxx_HAL_CONF_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED +#define HAL_ADC_MODULE_ENABLED +#define HAL_COMP_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED +#define HAL_CRC_MODULE_ENABLED +#define HAL_CRYP_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_GPIO_MODULE_ENABLED +#define HAL_GTZC_MODULE_ENABLED +#define HAL_HASH_MODULE_ENABLED +#define HAL_HSEM_MODULE_ENABLED +#define HAL_I2C_MODULE_ENABLED +#define HAL_ICACHE_MODULE_ENABLED +#define HAL_IRDA_MODULE_ENABLED +#define HAL_IWDG_MODULE_ENABLED +#define HAL_LPTIM_MODULE_ENABLED +#define HAL_PKA_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_RAMCFG_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_RNG_MODULE_ENABLED +#define HAL_RTC_MODULE_ENABLED +#define HAL_SAI_MODULE_ENABLED +#define HAL_SMARTCARD_MODULE_ENABLED +#define HAL_SMBUS_MODULE_ENABLED +#define HAL_SPI_MODULE_ENABLED +#define HAL_TIM_MODULE_ENABLED +#define HAL_TSC_MODULE_ENABLED +#define HAL_UART_MODULE_ENABLED +#define HAL_USART_MODULE_ENABLED +#define HAL_WWDG_MODULE_ENABLED + +/* ########################## Oscillator Values adaptation ####################*/ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) +#define HSE_VALUE 32000000UL /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) +#define HSE_STARTUP_TIMEOUT 100UL /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) +#define HSI_VALUE 16000000UL /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) +#define LSI_VALUE 32000UL /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz. The real value may vary depending on the variations in voltage and temperature.*/ + +#if defined (RCC_LSI2_SUPPORT) +#if !defined (LSI2_VALUE) +#define LSI2_VALUE 32000UL /*!< LSI2 Typical Value in Hz*/ +#endif /* LSI2_VALUE */ +#endif + +/** + * @brief External Low Speed oscillator (LSE) value. + * This value is used by the UART, RTC HAL module to compute the system frequency + */ +#if !defined (LSE_VALUE) +#define LSE_VALUE 32768UL /*!< Value of the External oscillator in Hz*/ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) +#define LSE_STARTUP_TIMEOUT 5000UL /*!< Time out for LSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief External clock source for SAI1 peripheral + * This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source + * frequency. + */ +#if !defined (EXTERNAL_SAI1_CLOCK_VALUE) +#define EXTERNAL_SAI1_CLOCK_VALUE 48000UL /*!< Value of the SAI1 External clock source in Hz*/ +#endif /* EXTERNAL_SAI1_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE 3300UL /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((1UL<<__NVIC_PRIO_BITS) - 1UL) /*!< tick interrupt priority (lowest by default) */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 1U /*!< Enable prefetch */ + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* ################## Register callback feature configuration ############### */ +/** + * @brief Set below the peripheral configuration to "1U" to add the support + * of HAL callback registration/unregistration feature for the HAL + * driver(s). This allows user application to provide specific callback + * functions thanks to HAL_PPP_RegisterCallback() rather than overwriting + * the default weak callback functions (see each stm32wbaxx_hal_ppp.h file + * for possible callback identifiers defined in HAL_PPP_CallbackIDTypeDef + * for each PPP peripheral). + */ +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ +#define USE_HAL_COMP_REGISTER_CALLBACKS 0U /* COMP register callback disabled */ +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ +#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ +#define USE_HAL_IWDG_REGISTER_CALLBACKS 0U /* IWDG register callback disabled */ +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ +#define USE_HAL_PKA_REGISTER_CALLBACKS 0U /* PKA register callback disabled */ +#define USE_HAL_RAMCFG_REGISTER_CALLBACKS 0U /* RAMCFG register callback disabled */ +#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ +#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ +#define USE_HAL_TSC_REGISTER_CALLBACKS 0U /* TSC register callback disabled */ +#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ +#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver + * Activated: CRC code is present inside driver + * Deactivated: CRC code cleaned from driver + */ +#define USE_SPI_CRC 1U + +/* ################## CRYP peripheral configuration ########################## */ + +#define USE_HAL_CRYP_SUSPEND_RESUME 0U + +/* ################## HASH peripheral configuration ########################## */ + +#define USE_HAL_HASH_SUSPEND_RESUME 0U + + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_DMA_MODULE_ENABLED +#include "stm32wbaxx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED +#include "stm32wbaxx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_COMP_MODULE_ENABLED +#include "stm32wbaxx_hal_comp.h" +#endif /* HAL_COMP_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED +#include "stm32wbaxx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED +#include "stm32wbaxx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED +#include "stm32wbaxx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED +#include "stm32wbaxx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED +#include "stm32wbaxx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED +#include "stm32wbaxx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_GTZC_MODULE_ENABLED +#include "stm32wbaxx_hal_gtzc.h" +#endif /* HAL_GTZC_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED +#include "stm32wbaxx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_HSEM_MODULE_ENABLED +#include "stm32wbaxx_hal_hsem.h" +#endif /* HAL_HSEM_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED +#include "stm32wbaxx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_ICACHE_MODULE_ENABLED +#include "stm32wbaxx_hal_icache.h" +#endif /* HAL_ICACHE_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED +#include "stm32wbaxx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED +#include "stm32wbaxx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED +#include "stm32wbaxx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_PKA_MODULE_ENABLED +#include "stm32wbaxx_hal_pka.h" +#endif /* HAL_PKA_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED +#include "stm32wbaxx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_RAMCFG_MODULE_ENABLED +#include "stm32wbaxx_hal_ramcfg.h" +#endif /* HAL_RAMCFG_MODULE_ENABLED */ + +#ifdef HAL_RCC_MODULE_ENABLED +#include "stm32wbaxx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED +#include "stm32wbaxx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED +#include "stm32wbaxx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED +#include "stm32wbaxx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED +#include "stm32wbaxx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED +#include "stm32wbaxx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED +#include "stm32wbaxx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED +#include "stm32wbaxx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_TSC_MODULE_ENABLED +#include "stm32wbaxx_hal_tsc.h" +#endif /* HAL_TSC_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED +#include "stm32wbaxx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED +#include "stm32wbaxx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED +#include "stm32wbaxx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ +#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ +void assert_failed(uint8_t *file, uint32_t line); +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WBAxx_HAL_CONF_H */ diff --git a/system/STM32WBAxx/system_stm32wbaxx.c b/system/STM32WBAxx/system_stm32wbaxx.c new file mode 100644 index 0000000000..dfe26150f3 --- /dev/null +++ b/system/STM32WBAxx/system_stm32wbaxx.c @@ -0,0 +1,381 @@ +/** + ****************************************************************************** + * @file system_stm32wbaxx.c + * @author MCD Application Team + * @brief CMSIS Cortex-M33 Device Peripheral Access Layer System Source File + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32wbaxx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32wbaxx.s" file, to + * configure the system clock before to branch to main program. + * + * This file configures the system clock as follows: + *============================================================================= + *----------------------------------------------------------------------------- + * System Clock source | HSI + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 16000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 16000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 1 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 1 + *----------------------------------------------------------------------------- + * PLL1_SRC | No clock + *----------------------------------------------------------------------------- + * PLL1_M | 1 + *----------------------------------------------------------------------------- + * PLL1_N | 128 + *----------------------------------------------------------------------------- + * PLL1_P | 1 + *----------------------------------------------------------------------------- + * PLL1_Q | 1 + *----------------------------------------------------------------------------- + * PLL1_R | 1 + *----------------------------------------------------------------------------- + * Require 48MHz for | Disabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup STM32WBAxx_system + * @{ + */ + +/** @addtogroup STM32WBAxx_System_Private_Includes + * @{ + */ + +#include "stm32wbaxx.h" +#include + +/** + * @} + */ + +/** @addtogroup STM32WBAxx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32WBAxx_System_Private_Defines + * @{ + */ +#if !defined (HSE_VALUE) +#define HSE_VALUE (32000000U) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) +#define HSI_VALUE (16000000U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/* Note: Following vector table addresses must be defined in line with linker + configuration. */ +/*!< Uncomment the following line if you need to relocate the vector table + anywhere in Flash or Sram, else the vector table is kept at the automatic + remap of boot address selected */ +/* #define USER_VECT_TAB_ADDRESS */ + +#if defined(USER_VECT_TAB_ADDRESS) +/*!< Uncomment the following line if you need to relocate your vector Table + in Sram else user remap will be done in Flash. */ +/* #define VECT_TAB_SRAM */ +#if defined(VECT_TAB_SRAM) +#define VECT_TAB_BASE_ADDRESS SRAM1_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +#else +#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_SRAM */ +#endif /* USER_VECT_TAB_ADDRESS */ + +/******************************************************************************/ + +/** + * @} + */ + +/** @addtogroup STM32WBAxx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32WBAxx_System_Private_Variables + * @{ + */ + /* The SystemCoreClock variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ + uint32_t SystemCoreClock = 16000000U; /* The HSI16 is used as system clock source after startup from reset, configured at 16 MHz. */ + + const uint8_t AHBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U}; + const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U}; + const uint8_t AHB5PrescTable[8] = {1U, 1U, 1U, 1U, 2U, 3U, 4U, 6U}; +/** + * @} + */ + +/** @addtogroup STM32WBAxx_System_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32WBAxx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * @param None + * @retval None + */ + +void SystemInit(void) +{ +#if defined(STM32WBAXX_SI_CUT1_0) + __IO uint32_t timeout_cpu_cycles; + __IO uint32_t tmpreg; +#endif + + /* FPU settings ------------------------------------------------------------*/ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */ +#endif + + /* Configure the Vector Table location -------------------------------------*/ +#if defined(USER_VECT_TAB_ADDRESS) + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation */ +#endif /* USER_VECT_TAB_ADDRESS */ + +#if defined(STM32WBAXX_SI_CUT1_0) + /* Work-around for ADC peripheral issue possibly impacting system + power consumption. + Refer to STM32WBA errata sheet item "HSI16 clock cannot be stopped when + used as kernel clock by ADC". + Actions: Perform a ADC activation sequence in order to update state + of internal signals. + */ + /* Enable ADC kernel clock */ + SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_ADC4EN); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_ADC4EN); + (void)tmpreg; + + /* Enable ADC */ + SET_BIT(ADC4->CR, ADC_CR_ADEN); + + /* Poll for ADC ready */ + /* Set timeout 2 ADC clock cycles */ + /* Note: Approximative computation and timeout execution not taking into + account processing CPU cycles */ + timeout_cpu_cycles = 2; + while (READ_BIT(ADC4->ISR, ADC_ISR_ADRDY) == 0U) + { + timeout_cpu_cycles--; + if(timeout_cpu_cycles == 0U) + { + break; + } + } + + /* Disable ADC */ + SET_BIT(ADC4->CR, ADC_CR_ADDIS); + + /* Poll for ADC disable is effective */ + /* Set timeout 6 ADC clock cycles */ + /* Note: Approximative computation and timeout execution not taking into + account processing CPU cycles */ + timeout_cpu_cycles = 6; + while (READ_BIT(ADC4->CR, ADC_CR_ADEN) != 0U) + { + timeout_cpu_cycles--; + if(timeout_cpu_cycles == 0U) + { + break; + } + } + + /* Disable ADC internal voltage regulator */ + CLEAR_BIT(ADC4->CR, ADC_CR_ADVREGEN); + + /* Disable ADC kernel clock */ + CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_ADC4EN); +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) + * + * - If SYSCLK source is PLL1, SystemCoreClock will contain the HSE_VALUE(***) + * or HSI_VALUE(*) multiplied/divided by the PLL1 factors. + * + * (**) HSI_VALUE is a constant defined in STM32WBAxx_hal.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (***) HSE_VALUE is a constant defined in STM32WBAxx_hal.h file (default value + * 32 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp1; + uint32_t tmp2; + uint32_t pllsource; + uint32_t pllr; + uint32_t pllm; + uint32_t plln; + float_t fracn; + float_t pllvco; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (RCC->CFGR1 & RCC_CFGR1_SWS) + { + case RCC_CFGR1_SWS_1: /* HSE used as system clock source */ + SystemCoreClock = (HSE_VALUE >> ((RCC->CR & RCC_CR_HSEPRE) >> RCC_CR_HSEPRE_Pos)); + break; + + case (RCC_CFGR1_SWS_0 | RCC_CFGR1_SWS_1): /* PLL1 used as system clock source */ + /* PLL_VCO = (PLLsource / PLLM) * PLLN * FractionnalPart + SYSCLK = PLL_VCO / PLLR */ + /* Get PLL1 CFGR and DIVR register values */ + tmp1 = RCC->PLL1CFGR; + tmp2 = RCC->PLL1DIVR; + + /* Retrieve PLL1 multiplication factor and divider */ + pllm = ((tmp1 & RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos) + 1U; + plln = (tmp2 & RCC_PLL1DIVR_PLL1N) + 1U; + pllr = ((tmp2 & RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1U; + + /* Check if fractional part is enable */ + if ((tmp1 & RCC_PLL1CFGR_PLL1FRACEN) != 0x00u) + { + fracn = (float_t)((uint32_t)((RCC->PLL1FRACR & RCC_PLL1FRACR_PLL1FRACN) >> RCC_PLL1FRACR_PLL1FRACN_Pos)); + } + else + { + fracn = (float_t)0U; + } + + /* determine PLL source */ + pllsource = (tmp1 & RCC_PLL1CFGR_PLL1SRC); + switch (pllsource) + { + /* HSI used as PLL1 clock source */ + case RCC_PLL1CFGR_PLL1SRC_1: + tmp1 = HSI_VALUE; + break; + + /* HSE used as PLL1 clock source */ + case (RCC_PLL1CFGR_PLL1SRC_0 | RCC_PLL1CFGR_PLL1SRC_1): + tmp1 = (HSE_VALUE >> ((RCC->CR & RCC_CR_HSEPRE) >> RCC_CR_HSEPRE_Pos)); + break; + + default: + tmp1 = 0U; + break; + } + + /* Compute VCO output frequency */ + pllvco = ((float_t) tmp1 / (float_t)pllm) * (((float_t)plln + (float_t)(fracn / (float_t)0x2000U))); + SystemCoreClock = (uint32_t)((float_t)(pllvco / (float_t)pllr)); + break; + + case 0x00u: /* HSI used as system clock source */ + default: + SystemCoreClock = HSI_VALUE; + break; + } + + /* Compute HCLK clock frequency --------------------------------------------*/ + /* Get HCLK prescaler */ + tmp1 = AHBPrescTable[(RCC->CFGR2 & RCC_CFGR2_HPRE)]; + + /* HCLK clock frequency */ + SystemCoreClock >>= tmp1; +} + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ From 0bb18d41b7260c285e4b3c9e18de09879434ed4a Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Fri, 9 Feb 2024 17:16:26 +0100 Subject: [PATCH 04/21] system(WBA): update STM32WBAxx hal default config Signed-off-by: Frederic Pillon --- system/STM32WBAxx/stm32wbaxx_hal_conf_default.h | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/system/STM32WBAxx/stm32wbaxx_hal_conf_default.h b/system/STM32WBAxx/stm32wbaxx_hal_conf_default.h index 4f8c0988be..e47c2d549b 100644 --- a/system/STM32WBAxx/stm32wbaxx_hal_conf_default.h +++ b/system/STM32WBAxx/stm32wbaxx_hal_conf_default.h @@ -1,8 +1,7 @@ /** ****************************************************************************** * @file stm32wbaxx_hal_conf_template.h - * @author MCD Application Team - * @brief HAL configuration template file. + * @brief HAL default configuration template file. * This file should be copied to the application folder and renamed * to stm32wbaxx_hal_conf.h. ****************************************************************************** @@ -19,8 +18,8 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32WBAxx_HAL_CONF_H -#define STM32WBAxx_HAL_CONF_H +#ifndef STM32WBAxx_HAL_CONF_DEFAULT_H +#define STM32WBAxx_HAL_CONF_DEFAULT_H #ifdef __cplusplus extern "C" { @@ -30,6 +29,12 @@ extern "C" { /* Exported constants --------------------------------------------------------*/ /* ########################## Module Selection ############################## */ +/** + * @brief Include the default list of modules to be used in the HAL driver + * and manage module deactivation + */ +#include "stm32yyxx_hal_conf.h" +#if 0 /** * @brief This is the list of modules to be used in the HAL driver */ @@ -66,6 +71,7 @@ extern "C" { #define HAL_UART_MODULE_ENABLED #define HAL_USART_MODULE_ENABLED #define HAL_WWDG_MODULE_ENABLED +#endif /* ########################## Oscillator Values adaptation ####################*/ /** @@ -347,4 +353,4 @@ void assert_failed(uint8_t *file, uint32_t line); } #endif -#endif /* STM32WBAxx_HAL_CONF_H */ +#endif /* STM32WBAxx_HAL_CONF_DEFAULT_H */ From d00afd93fa735004ebe5c69f12203f87b706bcc8 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Fri, 9 Feb 2024 17:16:26 +0100 Subject: [PATCH 05/21] core(WBA): add top HAL include Signed-off-by: Frederic Pillon --- cores/arduino/stm32/stm32_def.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/cores/arduino/stm32/stm32_def.h b/cores/arduino/stm32/stm32_def.h index 52a27ff051..3a62be66b0 100644 --- a/cores/arduino/stm32/stm32_def.h +++ b/cores/arduino/stm32/stm32_def.h @@ -58,6 +58,8 @@ #include "stm32u5xx.h" #elif defined(STM32WBxx) #include "stm32wbxx.h" +#elif defined(STM32WBAxx) + #include "stm32wbaxx.h" #elif defined(STM32WLxx) #include "stm32wlxx.h" #else From 555b956f7132082acd4b272cf97474093228c021 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Fri, 9 Feb 2024 17:16:26 +0100 Subject: [PATCH 06/21] core(WBA): add wrapped files Signed-off-by: Frederic Pillon --- cores/arduino/stm32/LL/stm32yyxx_ll_adc.h | 2 ++ cores/arduino/stm32/LL/stm32yyxx_ll_bus.h | 2 ++ cores/arduino/stm32/LL/stm32yyxx_ll_comp.h | 2 ++ cores/arduino/stm32/LL/stm32yyxx_ll_cortex.h | 2 ++ cores/arduino/stm32/LL/stm32yyxx_ll_crc.h | 2 ++ cores/arduino/stm32/LL/stm32yyxx_ll_dma.h | 2 ++ cores/arduino/stm32/LL/stm32yyxx_ll_exti.h | 2 ++ cores/arduino/stm32/LL/stm32yyxx_ll_gpio.h | 2 ++ cores/arduino/stm32/LL/stm32yyxx_ll_hsem.h | 2 ++ cores/arduino/stm32/LL/stm32yyxx_ll_i2c.h | 2 ++ cores/arduino/stm32/LL/stm32yyxx_ll_icache.h | 2 ++ cores/arduino/stm32/LL/stm32yyxx_ll_iwdg.h | 2 ++ cores/arduino/stm32/LL/stm32yyxx_ll_lptim.h | 2 ++ cores/arduino/stm32/LL/stm32yyxx_ll_lpuart.h | 2 ++ cores/arduino/stm32/LL/stm32yyxx_ll_pka.h | 2 ++ cores/arduino/stm32/LL/stm32yyxx_ll_pwr.h | 2 ++ cores/arduino/stm32/LL/stm32yyxx_ll_rcc.h | 2 ++ cores/arduino/stm32/LL/stm32yyxx_ll_rng.h | 2 ++ cores/arduino/stm32/LL/stm32yyxx_ll_rtc.h | 2 ++ cores/arduino/stm32/LL/stm32yyxx_ll_spi.h | 2 ++ cores/arduino/stm32/LL/stm32yyxx_ll_system.h | 2 ++ cores/arduino/stm32/LL/stm32yyxx_ll_tim.h | 2 ++ cores/arduino/stm32/LL/stm32yyxx_ll_usart.h | 2 ++ cores/arduino/stm32/LL/stm32yyxx_ll_utils.h | 2 ++ cores/arduino/stm32/LL/stm32yyxx_ll_wwdg.h | 2 ++ cores/arduino/stm32/stm32_def_build.h | 8 ++++++++ libraries/SrcWrapper/src/HAL/stm32yyxx_hal.c | 2 ++ libraries/SrcWrapper/src/HAL/stm32yyxx_hal_adc.c | 2 ++ libraries/SrcWrapper/src/HAL/stm32yyxx_hal_adc_ex.c | 2 ++ libraries/SrcWrapper/src/HAL/stm32yyxx_hal_comp.c | 2 ++ libraries/SrcWrapper/src/HAL/stm32yyxx_hal_cortex.c | 2 ++ libraries/SrcWrapper/src/HAL/stm32yyxx_hal_crc.c | 2 ++ libraries/SrcWrapper/src/HAL/stm32yyxx_hal_crc_ex.c | 2 ++ libraries/SrcWrapper/src/HAL/stm32yyxx_hal_cryp.c | 2 ++ libraries/SrcWrapper/src/HAL/stm32yyxx_hal_cryp_ex.c | 2 ++ libraries/SrcWrapper/src/HAL/stm32yyxx_hal_dma.c | 2 ++ libraries/SrcWrapper/src/HAL/stm32yyxx_hal_dma_ex.c | 2 ++ libraries/SrcWrapper/src/HAL/stm32yyxx_hal_exti.c | 2 ++ libraries/SrcWrapper/src/HAL/stm32yyxx_hal_flash.c | 2 ++ libraries/SrcWrapper/src/HAL/stm32yyxx_hal_flash_ex.c | 2 ++ libraries/SrcWrapper/src/HAL/stm32yyxx_hal_gpio.c | 2 ++ libraries/SrcWrapper/src/HAL/stm32yyxx_hal_gtzc.c | 2 ++ libraries/SrcWrapper/src/HAL/stm32yyxx_hal_hash.c | 2 ++ libraries/SrcWrapper/src/HAL/stm32yyxx_hal_hsem.c | 2 ++ libraries/SrcWrapper/src/HAL/stm32yyxx_hal_i2c.c | 2 ++ libraries/SrcWrapper/src/HAL/stm32yyxx_hal_i2c_ex.c | 2 ++ libraries/SrcWrapper/src/HAL/stm32yyxx_hal_icache.c | 2 ++ libraries/SrcWrapper/src/HAL/stm32yyxx_hal_irda.c | 2 ++ libraries/SrcWrapper/src/HAL/stm32yyxx_hal_iwdg.c | 2 ++ libraries/SrcWrapper/src/HAL/stm32yyxx_hal_lptim.c | 2 ++ libraries/SrcWrapper/src/HAL/stm32yyxx_hal_pka.c | 2 ++ libraries/SrcWrapper/src/HAL/stm32yyxx_hal_pwr.c | 2 ++ libraries/SrcWrapper/src/HAL/stm32yyxx_hal_pwr_ex.c | 2 ++ libraries/SrcWrapper/src/HAL/stm32yyxx_hal_ramcfg.c | 2 ++ libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rcc.c | 2 ++ libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rcc_ex.c | 2 ++ libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rng.c | 2 ++ libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rng_ex.c | 2 ++ libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rtc.c | 2 ++ libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rtc_ex.c | 2 ++ libraries/SrcWrapper/src/HAL/stm32yyxx_hal_sai.c | 2 ++ libraries/SrcWrapper/src/HAL/stm32yyxx_hal_sai_ex.c | 2 ++ libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smartcard.c | 2 ++ libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smartcard_ex.c | 2 ++ libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smbus.c | 2 ++ libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smbus_ex.c | 2 ++ libraries/SrcWrapper/src/HAL/stm32yyxx_hal_spi.c | 2 ++ libraries/SrcWrapper/src/HAL/stm32yyxx_hal_spi_ex.c | 2 ++ libraries/SrcWrapper/src/HAL/stm32yyxx_hal_tim.c | 2 ++ libraries/SrcWrapper/src/HAL/stm32yyxx_hal_tim_ex.c | 2 ++ libraries/SrcWrapper/src/HAL/stm32yyxx_hal_tsc.c | 2 ++ libraries/SrcWrapper/src/HAL/stm32yyxx_hal_uart.c | 2 ++ libraries/SrcWrapper/src/HAL/stm32yyxx_hal_uart_ex.c | 2 ++ libraries/SrcWrapper/src/HAL/stm32yyxx_hal_usart.c | 2 ++ libraries/SrcWrapper/src/HAL/stm32yyxx_hal_usart_ex.c | 2 ++ libraries/SrcWrapper/src/HAL/stm32yyxx_hal_wwdg.c | 2 ++ libraries/SrcWrapper/src/LL/stm32yyxx_ll_adc.c | 2 ++ libraries/SrcWrapper/src/LL/stm32yyxx_ll_comp.c | 2 ++ libraries/SrcWrapper/src/LL/stm32yyxx_ll_crc.c | 2 ++ libraries/SrcWrapper/src/LL/stm32yyxx_ll_dma.c | 2 ++ libraries/SrcWrapper/src/LL/stm32yyxx_ll_exti.c | 2 ++ libraries/SrcWrapper/src/LL/stm32yyxx_ll_gpio.c | 2 ++ libraries/SrcWrapper/src/LL/stm32yyxx_ll_i2c.c | 2 ++ libraries/SrcWrapper/src/LL/stm32yyxx_ll_icache.c | 2 ++ libraries/SrcWrapper/src/LL/stm32yyxx_ll_lptim.c | 2 ++ libraries/SrcWrapper/src/LL/stm32yyxx_ll_lpuart.c | 2 ++ libraries/SrcWrapper/src/LL/stm32yyxx_ll_pka.c | 2 ++ libraries/SrcWrapper/src/LL/stm32yyxx_ll_pwr.c | 2 ++ libraries/SrcWrapper/src/LL/stm32yyxx_ll_rcc.c | 2 ++ libraries/SrcWrapper/src/LL/stm32yyxx_ll_rng.c | 2 ++ libraries/SrcWrapper/src/LL/stm32yyxx_ll_rtc.c | 2 ++ libraries/SrcWrapper/src/LL/stm32yyxx_ll_spi.c | 2 ++ libraries/SrcWrapper/src/LL/stm32yyxx_ll_tim.c | 2 ++ libraries/SrcWrapper/src/LL/stm32yyxx_ll_usart.c | 2 ++ libraries/SrcWrapper/src/LL/stm32yyxx_ll_utils.c | 2 ++ libraries/SrcWrapper/src/stm32/system_stm32yyxx.c | 2 ++ 96 files changed, 198 insertions(+) diff --git a/cores/arduino/stm32/LL/stm32yyxx_ll_adc.h b/cores/arduino/stm32/LL/stm32yyxx_ll_adc.h index 657b7917b0..7469a19545 100644 --- a/cores/arduino/stm32/LL/stm32yyxx_ll_adc.h +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_adc.h @@ -44,6 +44,8 @@ #include "stm32u5xx_ll_adc.h" #elif STM32WBxx #include "stm32wbxx_ll_adc.h" +#elif STM32WBAxx + #include "stm32wbaxx_ll_adc.h" #elif STM32WLxx #include "stm32wlxx_ll_adc.h" #endif diff --git a/cores/arduino/stm32/LL/stm32yyxx_ll_bus.h b/cores/arduino/stm32/LL/stm32yyxx_ll_bus.h index d145450c10..e27fd52729 100644 --- a/cores/arduino/stm32/LL/stm32yyxx_ll_bus.h +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_bus.h @@ -44,6 +44,8 @@ #include "stm32u5xx_ll_bus.h" #elif STM32WBxx #include "stm32wbxx_ll_bus.h" +#elif STM32WBAxx + #include "stm32wbaxx_ll_bus.h" #elif STM32WLxx #include "stm32wlxx_ll_bus.h" #endif diff --git a/cores/arduino/stm32/LL/stm32yyxx_ll_comp.h b/cores/arduino/stm32/LL/stm32yyxx_ll_comp.h index 9b2bec9b49..fb3c8d2b74 100644 --- a/cores/arduino/stm32/LL/stm32yyxx_ll_comp.h +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_comp.h @@ -32,6 +32,8 @@ #include "stm32u5xx_ll_comp.h" #elif STM32WBxx #include "stm32wbxx_ll_comp.h" +#elif STM32WBAxx + #include "stm32wbaxx_ll_comp.h" #elif STM32WLxx #include "stm32wlxx_ll_comp.h" #endif diff --git a/cores/arduino/stm32/LL/stm32yyxx_ll_cortex.h b/cores/arduino/stm32/LL/stm32yyxx_ll_cortex.h index c7e7c490e6..8ece363f26 100644 --- a/cores/arduino/stm32/LL/stm32yyxx_ll_cortex.h +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_cortex.h @@ -44,6 +44,8 @@ #include "stm32u5xx_ll_cortex.h" #elif STM32WBxx #include "stm32wbxx_ll_cortex.h" +#elif STM32WBAxx + #include "stm32wbaxx_ll_cortex.h" #elif STM32WLxx #include "stm32wlxx_ll_cortex.h" #endif diff --git a/cores/arduino/stm32/LL/stm32yyxx_ll_crc.h b/cores/arduino/stm32/LL/stm32yyxx_ll_crc.h index 2282b63e81..5a8c391488 100644 --- a/cores/arduino/stm32/LL/stm32yyxx_ll_crc.h +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_crc.h @@ -42,6 +42,8 @@ #include "stm32u5xx_ll_crc.h" #elif STM32WBxx #include "stm32wbxx_ll_crc.h" +#elif STM32WBAxx + #include "stm32wbaxx_ll_crc.h" #elif STM32WLxx #include "stm32wlxx_ll_crc.h" #endif diff --git a/cores/arduino/stm32/LL/stm32yyxx_ll_dma.h b/cores/arduino/stm32/LL/stm32yyxx_ll_dma.h index c58eb5fc84..ec71d34c54 100644 --- a/cores/arduino/stm32/LL/stm32yyxx_ll_dma.h +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_dma.h @@ -44,6 +44,8 @@ #include "stm32u5xx_ll_dma.h" #elif STM32WBxx #include "stm32wbxx_ll_dma.h" +#elif STM32WBAxx + #include "stm32wbaxx_ll_dma.h" #elif STM32WLxx #include "stm32wlxx_ll_dma.h" #endif diff --git a/cores/arduino/stm32/LL/stm32yyxx_ll_exti.h b/cores/arduino/stm32/LL/stm32yyxx_ll_exti.h index e25bc6d475..826b8eb513 100644 --- a/cores/arduino/stm32/LL/stm32yyxx_ll_exti.h +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_exti.h @@ -44,6 +44,8 @@ #include "stm32u5xx_ll_exti.h" #elif STM32WBxx #include "stm32wbxx_ll_exti.h" +#elif STM32WBAxx + #include "stm32wbaxx_ll_exti.h" #elif STM32WLxx #include "stm32wlxx_ll_exti.h" #endif diff --git a/cores/arduino/stm32/LL/stm32yyxx_ll_gpio.h b/cores/arduino/stm32/LL/stm32yyxx_ll_gpio.h index b6ae1ea43a..7e5d262e4a 100644 --- a/cores/arduino/stm32/LL/stm32yyxx_ll_gpio.h +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_gpio.h @@ -44,6 +44,8 @@ #include "stm32u5xx_ll_gpio.h" #elif STM32WBxx #include "stm32wbxx_ll_gpio.h" +#elif STM32WBAxx + #include "stm32wbaxx_ll_gpio.h" #elif STM32WLxx #include "stm32wlxx_ll_gpio.h" #endif diff --git a/cores/arduino/stm32/LL/stm32yyxx_ll_hsem.h b/cores/arduino/stm32/LL/stm32yyxx_ll_hsem.h index 042ef3e537..ccd539004d 100644 --- a/cores/arduino/stm32/LL/stm32yyxx_ll_hsem.h +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_hsem.h @@ -14,6 +14,8 @@ #include "stm32mp1xx_ll_hsem.h" #elif STM32WBxx #include "stm32wbxx_ll_hsem.h" +#elif STM32WBAxx + #include "stm32wbaxx_ll_hsem.h" #elif STM32WLxx #include "stm32wlxx_ll_hsem.h" #endif diff --git a/cores/arduino/stm32/LL/stm32yyxx_ll_i2c.h b/cores/arduino/stm32/LL/stm32yyxx_ll_i2c.h index 5f16edb53f..298956a73f 100644 --- a/cores/arduino/stm32/LL/stm32yyxx_ll_i2c.h +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_i2c.h @@ -44,6 +44,8 @@ #include "stm32u5xx_ll_i2c.h" #elif STM32WBxx #include "stm32wbxx_ll_i2c.h" +#elif STM32WBAxx + #include "stm32wbaxx_ll_i2c.h" #elif STM32WLxx #include "stm32wlxx_ll_i2c.h" #endif diff --git a/cores/arduino/stm32/LL/stm32yyxx_ll_icache.h b/cores/arduino/stm32/LL/stm32yyxx_ll_icache.h index 3ad222b5d4..5b20ed0a49 100644 --- a/cores/arduino/stm32/LL/stm32yyxx_ll_icache.h +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_icache.h @@ -14,6 +14,8 @@ #include "stm32l5xx_ll_icache.h" #elif STM32U5xx #include "stm32u5xx_ll_icache.h" +#elif STM32WBAxx + #include "stm32wbaxx_ll_icache.h" #endif #pragma GCC diagnostic pop #endif /* _STM32YYXX_LL_ICACHE_H_ */ diff --git a/cores/arduino/stm32/LL/stm32yyxx_ll_iwdg.h b/cores/arduino/stm32/LL/stm32yyxx_ll_iwdg.h index da8b0a3e16..9c2a009386 100644 --- a/cores/arduino/stm32/LL/stm32yyxx_ll_iwdg.h +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_iwdg.h @@ -42,6 +42,8 @@ #include "stm32u5xx_ll_iwdg.h" #elif STM32WBxx #include "stm32wbxx_ll_iwdg.h" +#elif STM32WBAxx + #include "stm32wbaxx_ll_iwdg.h" #elif STM32WLxx #include "stm32wlxx_ll_iwdg.h" #endif diff --git a/cores/arduino/stm32/LL/stm32yyxx_ll_lptim.h b/cores/arduino/stm32/LL/stm32yyxx_ll_lptim.h index d974400620..fb86d8bf52 100644 --- a/cores/arduino/stm32/LL/stm32yyxx_ll_lptim.h +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_lptim.h @@ -32,6 +32,8 @@ #include "stm32u5xx_ll_lptim.h" #elif STM32WBxx #include "stm32wbxx_ll_lptim.h" +#elif STM32WBAxx + #include "stm32wbaxx_ll_lptim.h" #elif STM32WLxx #include "stm32wlxx_ll_lptim.h" #endif diff --git a/cores/arduino/stm32/LL/stm32yyxx_ll_lpuart.h b/cores/arduino/stm32/LL/stm32yyxx_ll_lpuart.h index f4bbea98bd..3b3d880de9 100644 --- a/cores/arduino/stm32/LL/stm32yyxx_ll_lpuart.h +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_lpuart.h @@ -26,6 +26,8 @@ #include "stm32u5xx_ll_lpuart.h" #elif STM32WBxx #include "stm32wbxx_ll_lpuart.h" +#elif STM32WBAxx + #include "stm32wbaxx_ll_lpuart.h" #elif STM32WLxx #include "stm32wlxx_ll_lpuart.h" #endif diff --git a/cores/arduino/stm32/LL/stm32yyxx_ll_pka.h b/cores/arduino/stm32/LL/stm32yyxx_ll_pka.h index bdbc7918c5..f6c96bf3d8 100644 --- a/cores/arduino/stm32/LL/stm32yyxx_ll_pka.h +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_pka.h @@ -18,6 +18,8 @@ #include "stm32u5xx_ll_pka.h" #elif STM32WBxx #include "stm32wbxx_ll_pka.h" +#elif STM32WBAxx + #include "stm32wbaxx_ll_pka.h" #elif STM32WLxx #include "stm32wlxx_ll_pka.h" #endif diff --git a/cores/arduino/stm32/LL/stm32yyxx_ll_pwr.h b/cores/arduino/stm32/LL/stm32yyxx_ll_pwr.h index e92b3eb4b8..df1367df3e 100644 --- a/cores/arduino/stm32/LL/stm32yyxx_ll_pwr.h +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_pwr.h @@ -44,6 +44,8 @@ #include "stm32u5xx_ll_pwr.h" #elif STM32WBxx #include "stm32wbxx_ll_pwr.h" +#elif STM32WBAxx + #include "stm32wbaxx_ll_pwr.h" #elif STM32WLxx #include "stm32wlxx_ll_pwr.h" #endif diff --git a/cores/arduino/stm32/LL/stm32yyxx_ll_rcc.h b/cores/arduino/stm32/LL/stm32yyxx_ll_rcc.h index 701c161a3c..bd613a4ba7 100644 --- a/cores/arduino/stm32/LL/stm32yyxx_ll_rcc.h +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_rcc.h @@ -44,6 +44,8 @@ #include "stm32u5xx_ll_rcc.h" #elif STM32WBxx #include "stm32wbxx_ll_rcc.h" +#elif STM32WBAxx + #include "stm32wbaxx_ll_rcc.h" #elif STM32WLxx #include "stm32wlxx_ll_rcc.h" #endif diff --git a/cores/arduino/stm32/LL/stm32yyxx_ll_rng.h b/cores/arduino/stm32/LL/stm32yyxx_ll_rng.h index cddaad98d9..34a6f8747c 100644 --- a/cores/arduino/stm32/LL/stm32yyxx_ll_rng.h +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_rng.h @@ -32,6 +32,8 @@ #include "stm32u5xx_ll_rng.h" #elif STM32WBxx #include "stm32wbxx_ll_rng.h" +#elif STM32WBAxx + #include "stm32wbaxx_ll_rng.h" #elif STM32WLxx #include "stm32wlxx_ll_rng.h" #endif diff --git a/cores/arduino/stm32/LL/stm32yyxx_ll_rtc.h b/cores/arduino/stm32/LL/stm32yyxx_ll_rtc.h index 929998b3a4..0ee36f5a27 100644 --- a/cores/arduino/stm32/LL/stm32yyxx_ll_rtc.h +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_rtc.h @@ -44,6 +44,8 @@ #include "stm32u5xx_ll_rtc.h" #elif STM32WBxx #include "stm32wbxx_ll_rtc.h" +#elif STM32WBAxx + #include "stm32wbaxx_ll_rtc.h" #elif STM32WLxx #include "stm32wlxx_ll_rtc.h" #endif diff --git a/cores/arduino/stm32/LL/stm32yyxx_ll_spi.h b/cores/arduino/stm32/LL/stm32yyxx_ll_spi.h index 4a948f20ef..53e172a32b 100644 --- a/cores/arduino/stm32/LL/stm32yyxx_ll_spi.h +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_spi.h @@ -44,6 +44,8 @@ #include "stm32u5xx_ll_spi.h" #elif STM32WBxx #include "stm32wbxx_ll_spi.h" +#elif STM32WBAxx + #include "stm32wbaxx_ll_spi.h" #elif STM32WLxx #include "stm32wlxx_ll_spi.h" #endif diff --git a/cores/arduino/stm32/LL/stm32yyxx_ll_system.h b/cores/arduino/stm32/LL/stm32yyxx_ll_system.h index 29fc4cab3f..4b2eea4b10 100644 --- a/cores/arduino/stm32/LL/stm32yyxx_ll_system.h +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_system.h @@ -44,6 +44,8 @@ #include "stm32u5xx_ll_system.h" #elif STM32WBxx #include "stm32wbxx_ll_system.h" +#elif STM32WBAxx + #include "stm32wbaxx_ll_system.h" #elif STM32WLxx #include "stm32wlxx_ll_system.h" #endif diff --git a/cores/arduino/stm32/LL/stm32yyxx_ll_tim.h b/cores/arduino/stm32/LL/stm32yyxx_ll_tim.h index a8164c0529..7f8aa0a1ee 100644 --- a/cores/arduino/stm32/LL/stm32yyxx_ll_tim.h +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_tim.h @@ -44,6 +44,8 @@ #include "stm32u5xx_ll_tim.h" #elif STM32WBxx #include "stm32wbxx_ll_tim.h" +#elif STM32WBAxx + #include "stm32wbaxx_ll_tim.h" #elif STM32WLxx #include "stm32wlxx_ll_tim.h" #endif diff --git a/cores/arduino/stm32/LL/stm32yyxx_ll_usart.h b/cores/arduino/stm32/LL/stm32yyxx_ll_usart.h index 78bce43234..3e2686ee9f 100644 --- a/cores/arduino/stm32/LL/stm32yyxx_ll_usart.h +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_usart.h @@ -44,6 +44,8 @@ #include "stm32u5xx_ll_usart.h" #elif STM32WBxx #include "stm32wbxx_ll_usart.h" +#elif STM32WBAxx + #include "stm32wbaxx_ll_usart.h" #elif STM32WLxx #include "stm32wlxx_ll_usart.h" #endif diff --git a/cores/arduino/stm32/LL/stm32yyxx_ll_utils.h b/cores/arduino/stm32/LL/stm32yyxx_ll_utils.h index a9b4326272..c290596002 100644 --- a/cores/arduino/stm32/LL/stm32yyxx_ll_utils.h +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_utils.h @@ -44,6 +44,8 @@ #include "stm32u5xx_ll_utils.h" #elif STM32WBxx #include "stm32wbxx_ll_utils.h" +#elif STM32WBAxx + #include "stm32wbaxx_ll_utils.h" #elif STM32WLxx #include "stm32wlxx_ll_utils.h" #endif diff --git a/cores/arduino/stm32/LL/stm32yyxx_ll_wwdg.h b/cores/arduino/stm32/LL/stm32yyxx_ll_wwdg.h index 1244c703c6..c674adf268 100644 --- a/cores/arduino/stm32/LL/stm32yyxx_ll_wwdg.h +++ b/cores/arduino/stm32/LL/stm32yyxx_ll_wwdg.h @@ -44,6 +44,8 @@ #include "stm32u5xx_ll_wwdg.h" #elif STM32WBxx #include "stm32wbxx_ll_wwdg.h" +#elif STM32WBAxx + #include "stm32wbaxx_ll_wwdg.h" #elif STM32WLxx #include "stm32wlxx_ll_wwdg.h" #endif diff --git a/cores/arduino/stm32/stm32_def_build.h b/cores/arduino/stm32/stm32_def_build.h index 1f66604003..12d45ea5b4 100644 --- a/cores/arduino/stm32/stm32_def_build.h +++ b/cores/arduino/stm32/stm32_def_build.h @@ -446,6 +446,14 @@ #define CMSIS_STARTUP_FILE "startup_stm32u5g7xx.s" #elif defined(STM32U5G9xx) #define CMSIS_STARTUP_FILE "startup_stm32u5g9xx.s" + #elif defined(STM32WBA50xx) + #define CMSIS_STARTUP_FILE "startup_stm32wba50xx.s" + #elif defined(STM32WBA52xx) + #define CMSIS_STARTUP_FILE "startup_stm32wba52xx.s" + #elif defined(STM32WBA54xx) + #define CMSIS_STARTUP_FILE "startup_stm32wba54xx.s" + #elif defined(STM32WBA55xx) + #define CMSIS_STARTUP_FILE "startup_stm32wba55xx.s" #elif defined(STM32WB10xx) #define CMSIS_STARTUP_FILE "startup_stm32wb10xx_cm4.s" #elif defined(STM32WB15xx) diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal.c index 9093c2e59d..eea39cec0a 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal.c @@ -40,6 +40,8 @@ #include "stm32u5xx_hal.c" #elif STM32WBxx #include "stm32wbxx_hal.c" +#elif STM32WBAxx + #include "stm32wbaxx_hal.c" #elif STM32WLxx #include "stm32wlxx_hal.c" #endif diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_adc.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_adc.c index ac30bf4198..8e8a9218e1 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_adc.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_adc.c @@ -38,6 +38,8 @@ #include "stm32u5xx_hal_adc.c" #elif STM32WBxx #include "stm32wbxx_hal_adc.c" +#elif STM32WBAxx + #include "stm32wbaxx_hal_adc.c" #elif STM32WLxx #include "stm32wlxx_hal_adc.c" #endif diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_adc_ex.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_adc_ex.c index c900ddda1b..bb702d7ec6 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_adc_ex.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_adc_ex.c @@ -38,6 +38,8 @@ #include "stm32u5xx_hal_adc_ex.c" #elif STM32WBxx #include "stm32wbxx_hal_adc_ex.c" +#elif STM32WBAxx + #include "stm32wbaxx_hal_adc_ex.c" #elif STM32WLxx #include "stm32wlxx_hal_adc_ex.c" #endif diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_comp.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_comp.c index 5c061f1f67..6e08e521ff 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_comp.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_comp.c @@ -26,6 +26,8 @@ #include "stm32u5xx_hal_comp.c" #elif STM32WBxx #include "stm32wbxx_hal_comp.c" +#elif STM32WBAxx + #include "stm32wbaxx_hal_comp.c" #elif STM32WLxx #include "stm32wlxx_hal_comp.c" #endif diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_cortex.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_cortex.c index 36f35eeb94..9ab250a266 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_cortex.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_cortex.c @@ -38,6 +38,8 @@ #include "stm32u5xx_hal_cortex.c" #elif STM32WBxx #include "stm32wbxx_hal_cortex.c" +#elif STM32WBAxx + #include "stm32wbaxx_hal_cortex.c" #elif STM32WLxx #include "stm32wlxx_hal_cortex.c" #endif diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_crc.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_crc.c index d58c3b2270..0f89a23176 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_crc.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_crc.c @@ -38,6 +38,8 @@ #include "stm32u5xx_hal_crc.c" #elif STM32WBxx #include "stm32wbxx_hal_crc.c" +#elif STM32WBAxx + #include "stm32wbaxx_hal_crc.c" #elif STM32WLxx #include "stm32wlxx_hal_crc.c" #endif diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_crc_ex.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_crc_ex.c index df9c04590b..9879d990a6 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_crc_ex.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_crc_ex.c @@ -30,6 +30,8 @@ #include "stm32u5xx_hal_crc_ex.c" #elif STM32WBxx #include "stm32wbxx_hal_crc_ex.c" +#elif STM32WBAxx + #include "stm32wbaxx_hal_crc_ex.c" #elif STM32WLxx #include "stm32wlxx_hal_crc_ex.c" #endif diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_cryp.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_cryp.c index 2113baaa24..3093fa8f64 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_cryp.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_cryp.c @@ -30,6 +30,8 @@ #include "stm32u5xx_hal_cryp.c" #elif STM32WBxx #include "stm32wbxx_hal_cryp.c" +#elif STM32WBAxx + #include "stm32wbaxx_hal_cryp.c" #elif STM32WLxx #include "stm32wlxx_hal_cryp.c" #endif diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_cryp_ex.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_cryp_ex.c index df46a519ee..a6c18f4a04 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_cryp_ex.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_cryp_ex.c @@ -28,6 +28,8 @@ #include "stm32u5xx_hal_cryp_ex.c" #elif STM32WBxx #include "stm32wbxx_hal_cryp_ex.c" +#elif STM32WBAxx + #include "stm32wbaxx_hal_cryp_ex.c" #elif STM32WLxx #include "stm32wlxx_hal_cryp_ex.c" #endif diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_dma.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_dma.c index 9f4d6bb6d3..c30a0752a3 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_dma.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_dma.c @@ -38,6 +38,8 @@ #include "stm32u5xx_hal_dma.c" #elif STM32WBxx #include "stm32wbxx_hal_dma.c" +#elif STM32WBAxx + #include "stm32wbaxx_hal_dma.c" #elif STM32WLxx #include "stm32wlxx_hal_dma.c" #endif diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_dma_ex.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_dma_ex.c index 07518e9d7e..b0a512159f 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_dma_ex.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_dma_ex.c @@ -28,6 +28,8 @@ #include "stm32u5xx_hal_dma_ex.c" #elif STM32WBxx #include "stm32wbxx_hal_dma_ex.c" +#elif STM32WBAxx + #include "stm32wbaxx_hal_dma_ex.c" #elif STM32WLxx #include "stm32wlxx_hal_dma_ex.c" #endif diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_exti.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_exti.c index 6eb44ba3ff..bd73d21953 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_exti.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_exti.c @@ -38,6 +38,8 @@ #include "stm32u5xx_hal_exti.c" #elif STM32WBxx #include "stm32wbxx_hal_exti.c" +#elif STM32WBAxx + #include "stm32wbaxx_hal_exti.c" #elif STM32WLxx #include "stm32wlxx_hal_exti.c" #endif diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_flash.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_flash.c index 4464928792..dcc93f730d 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_flash.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_flash.c @@ -36,6 +36,8 @@ #include "stm32u5xx_hal_flash.c" #elif STM32WBxx #include "stm32wbxx_hal_flash.c" +#elif STM32WBAxx + #include "stm32wbaxx_hal_flash.c" #elif STM32WLxx #include "stm32wlxx_hal_flash.c" #endif diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_flash_ex.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_flash_ex.c index 228dc84774..45a01e02b7 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_flash_ex.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_flash_ex.c @@ -36,6 +36,8 @@ #include "stm32u5xx_hal_flash_ex.c" #elif STM32WBxx #include "stm32wbxx_hal_flash_ex.c" +#elif STM32WBAxx + #include "stm32wbaxx_hal_flash_ex.c" #elif STM32WLxx #include "stm32wlxx_hal_flash_ex.c" #endif diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_gpio.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_gpio.c index 25efe43a3e..db30784153 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_gpio.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_gpio.c @@ -38,6 +38,8 @@ #include "stm32u5xx_hal_gpio.c" #elif STM32WBxx #include "stm32wbxx_hal_gpio.c" +#elif STM32WBAxx + #include "stm32wbaxx_hal_gpio.c" #elif STM32WLxx #include "stm32wlxx_hal_gpio.c" #endif diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_gtzc.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_gtzc.c index bbed4555ac..8d6378d6fb 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_gtzc.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_gtzc.c @@ -8,6 +8,8 @@ #include "stm32l5xx_hal_gtzc.c" #elif STM32U5xx #include "stm32u5xx_hal_gtzc.c" +#elif STM32WBAxx + #include "stm32wbaxx_hal_gtzc.c" #elif STM32WLxx #include "stm32wlxx_hal_gtzc.c" #endif diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_hash.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_hash.c index c95f79a259..0dd13a4463 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_hash.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_hash.c @@ -20,5 +20,7 @@ #include "stm32mp1xx_hal_hash.c" #elif STM32U5xx #include "stm32u5xx_hal_hash.c" +#elif STM32WBAxx + #include "stm32wbaxx_hal_hash.c" #endif #pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_hsem.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_hsem.c index 28d31ce115..111db3d7f2 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_hsem.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_hsem.c @@ -8,6 +8,8 @@ #include "stm32mp1xx_hal_hsem.c" #elif STM32WBxx #include "stm32wbxx_hal_hsem.c" +#elif STM32WBAxx + #include "stm32wbaxx_hal_hsem.c" #elif STM32WLxx #include "stm32wlxx_hal_hsem.c" #endif diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_i2c.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_i2c.c index 2819ed0a60..6cccae82a5 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_i2c.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_i2c.c @@ -38,6 +38,8 @@ #include "stm32u5xx_hal_i2c.c" #elif STM32WBxx #include "stm32wbxx_hal_i2c.c" +#elif STM32WBAxx + #include "stm32wbaxx_hal_i2c.c" #elif STM32WLxx #include "stm32wlxx_hal_i2c.c" #endif diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_i2c_ex.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_i2c_ex.c index 67d36e26c6..c527eb3ade 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_i2c_ex.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_i2c_ex.c @@ -32,6 +32,8 @@ #include "stm32u5xx_hal_i2c_ex.c" #elif STM32WBxx #include "stm32wbxx_hal_i2c_ex.c" +#elif STM32WBAxx + #include "stm32wbaxx_hal_i2c_ex.c" #elif STM32WLxx #include "stm32wlxx_hal_i2c_ex.c" #endif diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_icache.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_icache.c index 9bafb14709..7d29686ac9 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_icache.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_icache.c @@ -8,5 +8,7 @@ #include "stm32l5xx_hal_icache.c" #elif STM32U5xx #include "stm32u5xx_hal_icache.c" +#elif STM32WBAxx + #include "stm32wbaxx_hal_icache.c" #endif #pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_irda.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_irda.c index d4518e2626..1ea4a2399b 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_irda.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_irda.c @@ -36,6 +36,8 @@ #include "stm32u5xx_hal_irda.c" #elif STM32WBxx #include "stm32wbxx_hal_irda.c" +#elif STM32WBAxx + #include "stm32wbaxx_hal_irda.c" #elif STM32WLxx #include "stm32wlxx_hal_irda.c" #endif diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_iwdg.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_iwdg.c index fec855662a..be9c3e93f4 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_iwdg.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_iwdg.c @@ -36,6 +36,8 @@ #include "stm32u5xx_hal_iwdg.c" #elif STM32WBxx #include "stm32wbxx_hal_iwdg.c" +#elif STM32WBAxx + #include "stm32wbaxx_hal_iwdg.c" #elif STM32WLxx #include "stm32wlxx_hal_iwdg.c" #endif diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_lptim.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_lptim.c index 5515eb0938..c1c7659250 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_lptim.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_lptim.c @@ -26,6 +26,8 @@ #include "stm32u5xx_hal_lptim.c" #elif STM32WBxx #include "stm32wbxx_hal_lptim.c" +#elif STM32WBAxx + #include "stm32wbaxx_hal_lptim.c" #elif STM32WLxx #include "stm32wlxx_hal_lptim.c" #endif diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_pka.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_pka.c index a72ea1471c..9bb260cc72 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_pka.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_pka.c @@ -12,6 +12,8 @@ #include "stm32u5xx_hal_pka.c" #elif STM32WBxx #include "stm32wbxx_hal_pka.c" +#elif STM32WBAxx + #include "stm32wbaxx_hal_pka.c" #elif STM32WLxx #include "stm32wlxx_hal_pka.c" #endif diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_pwr.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_pwr.c index df4ea28354..da93008e4a 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_pwr.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_pwr.c @@ -38,6 +38,8 @@ #include "stm32u5xx_hal_pwr.c" #elif STM32WBxx #include "stm32wbxx_hal_pwr.c" +#elif STM32WBAxx + #include "stm32wbaxx_hal_pwr.c" #elif STM32WLxx #include "stm32wlxx_hal_pwr.c" #endif diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_pwr_ex.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_pwr_ex.c index 070aef7eda..53935ad857 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_pwr_ex.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_pwr_ex.c @@ -36,6 +36,8 @@ #include "stm32u5xx_hal_pwr_ex.c" #elif STM32WBxx #include "stm32wbxx_hal_pwr_ex.c" +#elif STM32WBAxx + #include "stm32wbaxx_hal_pwr_ex.c" #elif STM32WLxx #include "stm32wlxx_hal_pwr_ex.c" #endif diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_ramcfg.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_ramcfg.c index fdf54967cb..786e5b6521 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_ramcfg.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_ramcfg.c @@ -6,5 +6,7 @@ #include "stm32h5xx_hal_ramcfg.c" #elif STM32U5xx #include "stm32u5xx_hal_ramcfg.c" +#elif STM32WBAxx + #include "stm32wbaxx_hal_ramcfg.c" #endif #pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rcc.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rcc.c index 217f9158b7..e8b19bb48c 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rcc.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rcc.c @@ -38,6 +38,8 @@ #include "stm32u5xx_hal_rcc.c" #elif STM32WBxx #include "stm32wbxx_hal_rcc.c" +#elif STM32WBAxx + #include "stm32wbaxx_hal_rcc.c" #elif STM32WLxx #include "stm32wlxx_hal_rcc.c" #endif diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rcc_ex.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rcc_ex.c index ca46a0bb6c..b7136950ca 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rcc_ex.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rcc_ex.c @@ -38,6 +38,8 @@ #include "stm32u5xx_hal_rcc_ex.c" #elif STM32WBxx #include "stm32wbxx_hal_rcc_ex.c" +#elif STM32WBAxx + #include "stm32wbaxx_hal_rcc_ex.c" #elif STM32WLxx #include "stm32wlxx_hal_rcc_ex.c" #endif diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rng.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rng.c index 41bedadbc9..7ff451dd39 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rng.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rng.c @@ -28,6 +28,8 @@ #include "stm32u5xx_hal_rng.c" #elif STM32WBxx #include "stm32wbxx_hal_rng.c" +#elif STM32WBAxx + #include "stm32wbaxx_hal_rng.c" #elif STM32WLxx #include "stm32wlxx_hal_rng.c" #endif diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rng_ex.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rng_ex.c index a6cf27e68d..d548a5b6b0 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rng_ex.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rng_ex.c @@ -12,6 +12,8 @@ #include "stm32l5xx_hal_rng_ex.c" #elif STM32U5xx #include "stm32u5xx_hal_rng_ex.c" +#elif STM32WBAxx + #include "stm32wbaxx_hal_rng_ex.c" #elif STM32WLxx #include "stm32wlxx_hal_rng_ex.c" #endif diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rtc.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rtc.c index 5f8e6c1a37..16d2b6bd23 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rtc.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rtc.c @@ -38,6 +38,8 @@ #include "stm32u5xx_hal_rtc.c" #elif STM32WBxx #include "stm32wbxx_hal_rtc.c" +#elif STM32WBAxx + #include "stm32wbaxx_hal_rtc.c" #elif STM32WLxx #include "stm32wlxx_hal_rtc.c" #endif diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rtc_ex.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rtc_ex.c index 570d63aa14..0ea69b3906 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rtc_ex.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_rtc_ex.c @@ -38,6 +38,8 @@ #include "stm32u5xx_hal_rtc_ex.c" #elif STM32WBxx #include "stm32wbxx_hal_rtc_ex.c" +#elif STM32WBAxx + #include "stm32wbaxx_hal_rtc_ex.c" #elif STM32WLxx #include "stm32wlxx_hal_rtc_ex.c" #endif diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_sai.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_sai.c index 29e4aa5650..56555bf4a3 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_sai.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_sai.c @@ -22,5 +22,7 @@ #include "stm32u5xx_hal_sai.c" #elif STM32WBxx #include "stm32wbxx_hal_sai.c" +#elif STM32WBAxx + #include "stm32wbaxx_hal_sai.c" #endif #pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_sai_ex.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_sai_ex.c index bea93ee083..86aab66b5d 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_sai_ex.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_sai_ex.c @@ -22,5 +22,7 @@ #include "stm32u5xx_hal_sai_ex.c" #elif STM32WBxx #include "stm32wbxx_hal_sai_ex.c" +#elif STM32WBAxx + #include "stm32wbaxx_hal_sai_ex.c" #endif #pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smartcard.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smartcard.c index f72baaf339..a2b3f60d71 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smartcard.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smartcard.c @@ -38,6 +38,8 @@ #include "stm32u5xx_hal_smartcard.c" #elif STM32WBxx #include "stm32wbxx_hal_smartcard.c" +#elif STM32WBAxx + #include "stm32wbaxx_hal_smartcard.c" #elif STM32WLxx #include "stm32wlxx_hal_smartcard.c" #endif diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smartcard_ex.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smartcard_ex.c index c5bf037764..4728afa4d1 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smartcard_ex.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smartcard_ex.c @@ -30,6 +30,8 @@ #include "stm32u5xx_hal_smartcard_ex.c" #elif STM32WBxx #include "stm32wbxx_hal_smartcard_ex.c" +#elif STM32WBAxx + #include "stm32wbaxx_hal_smartcard_ex.c" #elif STM32WLxx #include "stm32wlxx_hal_smartcard_ex.c" #endif diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smbus.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smbus.c index 688a0563c6..13cecbf353 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smbus.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smbus.c @@ -34,6 +34,8 @@ #include "stm32u5xx_hal_smbus.c" #elif STM32WBxx #include "stm32wbxx_hal_smbus.c" +#elif STM32WBAxx + #include "stm32wbaxx_hal_smbus.c" #elif STM32WLxx #include "stm32wlxx_hal_smbus.c" #endif diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smbus_ex.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smbus_ex.c index 869115fd03..a5935a430b 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smbus_ex.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_smbus_ex.c @@ -24,6 +24,8 @@ #include "stm32u5xx_hal_smbus_ex.c" #elif STM32WBxx #include "stm32wbxx_hal_smbus_ex.c" +#elif STM32WBAxx + #include "stm32wbaxx_hal_smbus_ex.c" #elif STM32WLxx #include "stm32wlxx_hal_smbus_ex.c" #endif diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_spi.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_spi.c index d54977b4ba..d2ad9ce026 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_spi.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_spi.c @@ -38,6 +38,8 @@ #include "stm32u5xx_hal_spi.c" #elif STM32WBxx #include "stm32wbxx_hal_spi.c" +#elif STM32WBAxx + #include "stm32wbaxx_hal_spi.c" #elif STM32WLxx #include "stm32wlxx_hal_spi.c" #endif diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_spi_ex.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_spi_ex.c index a5e02b61f1..207d51c808 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_spi_ex.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_spi_ex.c @@ -28,6 +28,8 @@ #include "stm32u5xx_hal_spi_ex.c" #elif STM32WBxx #include "stm32wbxx_hal_spi_ex.c" +#elif STM32WBAxx + #include "stm32wbaxx_hal_spi_ex.c" #elif STM32WLxx #include "stm32wlxx_hal_spi_ex.c" #endif diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_tim.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_tim.c index e99fefa07b..eebb60a48f 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_tim.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_tim.c @@ -38,6 +38,8 @@ #include "stm32u5xx_hal_tim.c" #elif STM32WBxx #include "stm32wbxx_hal_tim.c" +#elif STM32WBAxx + #include "stm32wbaxx_hal_tim.c" #elif STM32WLxx #include "stm32wlxx_hal_tim.c" #endif diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_tim_ex.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_tim_ex.c index 79fd6e400e..fcab96885e 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_tim_ex.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_tim_ex.c @@ -38,6 +38,8 @@ #include "stm32u5xx_hal_tim_ex.c" #elif STM32WBxx #include "stm32wbxx_hal_tim_ex.c" +#elif STM32WBAxx + #include "stm32wbaxx_hal_tim_ex.c" #elif STM32WLxx #include "stm32wlxx_hal_tim_ex.c" #endif diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_tsc.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_tsc.c index 257721ec48..c964318e61 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_tsc.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_tsc.c @@ -16,5 +16,7 @@ #include "stm32u5xx_hal_tsc.c" #elif STM32WBxx #include "stm32wbxx_hal_tsc.c" +#elif STM32WBAxx + #include "stm32wbaxx_hal_tsc.c" #endif #pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_uart.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_uart.c index 5bff5cabf2..50d34509b3 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_uart.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_uart.c @@ -38,6 +38,8 @@ #include "stm32u5xx_hal_uart.c" #elif STM32WBxx #include "stm32wbxx_hal_uart.c" +#elif STM32WBAxx + #include "stm32wbaxx_hal_uart.c" #elif STM32WLxx #include "stm32wlxx_hal_uart.c" #endif diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_uart_ex.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_uart_ex.c index 28d98e94a6..399b417b67 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_uart_ex.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_uart_ex.c @@ -30,6 +30,8 @@ #include "stm32u5xx_hal_uart_ex.c" #elif STM32WBxx #include "stm32wbxx_hal_uart_ex.c" +#elif STM32WBAxx + #include "stm32wbaxx_hal_uart_ex.c" #elif STM32WLxx #include "stm32wlxx_hal_uart_ex.c" #endif diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_usart.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_usart.c index 23364343d2..8ddc53370b 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_usart.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_usart.c @@ -38,6 +38,8 @@ #include "stm32u5xx_hal_usart.c" #elif STM32WBxx #include "stm32wbxx_hal_usart.c" +#elif STM32WBAxx + #include "stm32wbaxx_hal_usart.c" #elif STM32WLxx #include "stm32wlxx_hal_usart.c" #endif diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_usart_ex.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_usart_ex.c index b2d5165fd0..2643bef3cd 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_usart_ex.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_usart_ex.c @@ -26,6 +26,8 @@ #include "stm32u5xx_hal_usart_ex.c" #elif STM32WBxx #include "stm32wbxx_hal_usart_ex.c" +#elif STM32WBAxx + #include "stm32wbaxx_hal_usart_ex.c" #elif STM32WLxx #include "stm32wlxx_hal_usart_ex.c" #endif diff --git a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_wwdg.c b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_wwdg.c index 615bc465df..1e0e040f68 100644 --- a/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_wwdg.c +++ b/libraries/SrcWrapper/src/HAL/stm32yyxx_hal_wwdg.c @@ -38,6 +38,8 @@ #include "stm32u5xx_hal_wwdg.c" #elif STM32WBxx #include "stm32wbxx_hal_wwdg.c" +#elif STM32WBAxx + #include "stm32wbaxx_hal_wwdg.c" #elif STM32WLxx #include "stm32wlxx_hal_wwdg.c" #endif diff --git a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_adc.c b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_adc.c index 5150ef440f..0a9c4cbf0f 100644 --- a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_adc.c +++ b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_adc.c @@ -38,6 +38,8 @@ #include "stm32u5xx_ll_adc.c" #elif STM32WBxx #include "stm32wbxx_ll_adc.c" +#elif STM32WBAxx + #include "stm32wbaxx_ll_adc.c" #elif STM32WLxx #include "stm32wlxx_ll_adc.c" #endif diff --git a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_comp.c b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_comp.c index 751c55408c..98c9f713d4 100644 --- a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_comp.c +++ b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_comp.c @@ -26,6 +26,8 @@ #include "stm32u5xx_ll_comp.c" #elif STM32WBxx #include "stm32wbxx_ll_comp.c" +#elif STM32WBAxx + #include "stm32wbaxx_ll_comp.c" #elif STM32WLxx #include "stm32wlxx_ll_comp.c" #endif diff --git a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_crc.c b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_crc.c index fe5362aa09..3d8ffc2b3a 100644 --- a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_crc.c +++ b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_crc.c @@ -36,6 +36,8 @@ #include "stm32u5xx_ll_crc.c" #elif STM32WBxx #include "stm32wbxx_ll_crc.c" +#elif STM32WBAxx + #include "stm32wbaxx_ll_crc.c" #elif STM32WLxx #include "stm32wlxx_ll_crc.c" #endif diff --git a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_dma.c b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_dma.c index 499829e9cf..7b61d86c39 100644 --- a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_dma.c +++ b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_dma.c @@ -38,6 +38,8 @@ #include "stm32u5xx_ll_dma.c" #elif STM32WBxx #include "stm32wbxx_ll_dma.c" +#elif STM32WBAxx + #include "stm32wbaxx_ll_dma.c" #elif STM32WLxx #include "stm32wlxx_ll_dma.c" #endif diff --git a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_exti.c b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_exti.c index 3b745db45b..a61f9511c7 100644 --- a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_exti.c +++ b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_exti.c @@ -38,6 +38,8 @@ #include "stm32u5xx_ll_exti.c" #elif STM32WBxx #include "stm32wbxx_ll_exti.c" +#elif STM32WBAxx + #include "stm32wbaxx_ll_exti.c" #elif STM32WLxx #include "stm32wlxx_ll_exti.c" #endif diff --git a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_gpio.c b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_gpio.c index 800205402c..b436de00ff 100644 --- a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_gpio.c +++ b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_gpio.c @@ -38,6 +38,8 @@ #include "stm32u5xx_ll_gpio.c" #elif STM32WBxx #include "stm32wbxx_ll_gpio.c" +#elif STM32WBAxx + #include "stm32wbaxx_ll_gpio.c" #elif STM32WLxx #include "stm32wlxx_ll_gpio.c" #endif diff --git a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_i2c.c b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_i2c.c index cf0c0a4ed8..a15fe1695e 100644 --- a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_i2c.c +++ b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_i2c.c @@ -38,6 +38,8 @@ #include "stm32u5xx_ll_i2c.c" #elif STM32WBxx #include "stm32wbxx_ll_i2c.c" +#elif STM32WBAxx + #include "stm32wbaxx_ll_i2c.c" #elif STM32WLxx #include "stm32wlxx_ll_i2c.c" #endif diff --git a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_icache.c b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_icache.c index a4398a2ea6..03667a27b7 100644 --- a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_icache.c +++ b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_icache.c @@ -8,5 +8,7 @@ #include "stm32l5xx_ll_icache.c" #elif STM32U5xx #include "stm32u5xx_ll_icache.c" +#elif STM32WBAxx + #include "stm32wbaxx_ll_icache.c" #endif #pragma GCC diagnostic pop diff --git a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_lptim.c b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_lptim.c index ddfe613d2c..d80493464a 100644 --- a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_lptim.c +++ b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_lptim.c @@ -26,6 +26,8 @@ #include "stm32u5xx_ll_lptim.c" #elif STM32WBxx #include "stm32wbxx_ll_lptim.c" +#elif STM32WBAxx + #include "stm32wbaxx_ll_lptim.c" #elif STM32WLxx #include "stm32wlxx_ll_lptim.c" #endif diff --git a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_lpuart.c b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_lpuart.c index 51954ec17a..6fbf1b6439 100644 --- a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_lpuart.c +++ b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_lpuart.c @@ -20,6 +20,8 @@ #include "stm32u5xx_ll_lpuart.c" #elif STM32WBxx #include "stm32wbxx_ll_lpuart.c" +#elif STM32WBAxx + #include "stm32wbaxx_ll_lpuart.c" #elif STM32WLxx #include "stm32wlxx_ll_lpuart.c" #endif diff --git a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_pka.c b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_pka.c index f4af2d69d8..67f62342c1 100644 --- a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_pka.c +++ b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_pka.c @@ -12,6 +12,8 @@ #include "stm32u5xx_ll_pka.c" #elif STM32WBxx #include "stm32wbxx_ll_pka.c" +#elif STM32WBAxx + #include "stm32wbaxx_ll_pka.c" #elif STM32WLxx #include "stm32wlxx_ll_pka.c" #endif diff --git a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_pwr.c b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_pwr.c index 84281ba39b..63d6bf7b62 100644 --- a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_pwr.c +++ b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_pwr.c @@ -38,6 +38,8 @@ #include "stm32u5xx_ll_pwr.c" #elif STM32WBxx #include "stm32wbxx_ll_pwr.c" +#elif STM32WBAxx + #include "stm32wbaxx_ll_pwr.c" #elif STM32WLxx #include "stm32wlxx_ll_pwr.c" #endif diff --git a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_rcc.c b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_rcc.c index 267edc093d..b68896c489 100644 --- a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_rcc.c +++ b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_rcc.c @@ -38,6 +38,8 @@ #include "stm32u5xx_ll_rcc.c" #elif STM32WBxx #include "stm32wbxx_ll_rcc.c" +#elif STM32WBAxx + #include "stm32wbaxx_ll_rcc.c" #elif STM32WLxx #include "stm32wlxx_ll_rcc.c" #endif diff --git a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_rng.c b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_rng.c index cd3b1ec7c2..98063b6b8c 100644 --- a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_rng.c +++ b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_rng.c @@ -26,6 +26,8 @@ #include "stm32u5xx_ll_rng.c" #elif STM32WBxx #include "stm32wbxx_ll_rng.c" +#elif STM32WBAxx + #include "stm32wbaxx_ll_rng.c" #elif STM32WLxx #include "stm32wlxx_ll_rng.c" #endif diff --git a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_rtc.c b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_rtc.c index e8132a5d69..027e6ce25d 100644 --- a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_rtc.c +++ b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_rtc.c @@ -38,6 +38,8 @@ #include "stm32u5xx_ll_rtc.c" #elif STM32WBxx #include "stm32wbxx_ll_rtc.c" +#elif STM32WBAxx + #include "stm32wbaxx_ll_rtc.c" #elif STM32WLxx #include "stm32wlxx_ll_rtc.c" #endif diff --git a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_spi.c b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_spi.c index 58b1dae2b7..6f28b4f9de 100644 --- a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_spi.c +++ b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_spi.c @@ -38,6 +38,8 @@ #include "stm32u5xx_ll_spi.c" #elif STM32WBxx #include "stm32wbxx_ll_spi.c" +#elif STM32WBAxx + #include "stm32wbaxx_ll_spi.c" #elif STM32WLxx #include "stm32wlxx_ll_spi.c" #endif diff --git a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_tim.c b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_tim.c index 4417d88aa8..2af56b4a0f 100644 --- a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_tim.c +++ b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_tim.c @@ -38,6 +38,8 @@ #include "stm32u5xx_ll_tim.c" #elif STM32WBxx #include "stm32wbxx_ll_tim.c" +#elif STM32WBAxx + #include "stm32wbaxx_ll_tim.c" #elif STM32WLxx #include "stm32wlxx_ll_tim.c" #endif diff --git a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_usart.c b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_usart.c index 1c51985d34..a77516d52e 100644 --- a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_usart.c +++ b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_usart.c @@ -38,6 +38,8 @@ #include "stm32u5xx_ll_usart.c" #elif STM32WBxx #include "stm32wbxx_ll_usart.c" +#elif STM32WBAxx + #include "stm32wbaxx_ll_usart.c" #elif STM32WLxx #include "stm32wlxx_ll_usart.c" #endif diff --git a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_utils.c b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_utils.c index 18546e825a..2c85934ad3 100644 --- a/libraries/SrcWrapper/src/LL/stm32yyxx_ll_utils.c +++ b/libraries/SrcWrapper/src/LL/stm32yyxx_ll_utils.c @@ -38,6 +38,8 @@ #include "stm32u5xx_ll_utils.c" #elif STM32WBxx #include "stm32wbxx_ll_utils.c" +#elif STM32WBAxx + #include "stm32wbaxx_ll_utils.c" #elif STM32WLxx #include "stm32wlxx_ll_utils.c" #endif diff --git a/libraries/SrcWrapper/src/stm32/system_stm32yyxx.c b/libraries/SrcWrapper/src/stm32/system_stm32yyxx.c index fd194446b0..1a04669fb4 100644 --- a/libraries/SrcWrapper/src/stm32/system_stm32yyxx.c +++ b/libraries/SrcWrapper/src/stm32/system_stm32yyxx.c @@ -34,6 +34,8 @@ #include "system_stm32mp1xx.c" #elif STM32U5xx #include "system_stm32u5xx.c" +#elif STM32WBAxx + #include "system_stm32wbaxx.c" #elif STM32WBxx #include "system_stm32wbxx.c" #elif STM32WLxx From 5d911230832d30675a6c3ed3abe7ef308f1db826 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 15 Feb 2024 15:00:54 +0100 Subject: [PATCH 07/21] system(WBA): update STM32WBAxx hal default config Allow some redefinition. Signed-off-by: Frederic Pillon --- system/STM32WBAxx/stm32wbaxx_hal_conf_default.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/system/STM32WBAxx/stm32wbaxx_hal_conf_default.h b/system/STM32WBAxx/stm32wbaxx_hal_conf_default.h index e47c2d549b..75d96c6a62 100644 --- a/system/STM32WBAxx/stm32wbaxx_hal_conf_default.h +++ b/system/STM32WBAxx/stm32wbaxx_hal_conf_default.h @@ -137,10 +137,18 @@ extern "C" { /** * @brief This is the HAL system configuration section */ +#if !defined (VDD_VALUE) #define VDD_VALUE 3300UL /*!< Value of VDD in mv */ +#endif +#if !defined (TICK_INT_PRIORITY) #define TICK_INT_PRIORITY ((1UL<<__NVIC_PRIO_BITS) - 1UL) /*!< tick interrupt priority (lowest by default) */ +#endif +#if !defined (USE_RTOS) #define USE_RTOS 0U +#endif +#if !defined (PREFETCH_ENABLE) #define PREFETCH_ENABLE 1U /*!< Enable prefetch */ +#endif /* ########################## Assert Selection ############################## */ /** From 71a554bf4801e7d4101ea1144b0a21f8acb14372 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 15 Feb 2024 15:22:18 +0100 Subject: [PATCH 08/21] system(WBA): update STM32WBAxx system Remove duplicate clock definition. Allow VECT_TAB_OFFSET redefinition. Signed-off-by: Frederic Pillon --- system/STM32WBAxx/system_stm32wbaxx.c | 25 +++++++++---------------- 1 file changed, 9 insertions(+), 16 deletions(-) diff --git a/system/STM32WBAxx/system_stm32wbaxx.c b/system/STM32WBAxx/system_stm32wbaxx.c index dfe26150f3..d7e1b12eaf 100644 --- a/system/STM32WBAxx/system_stm32wbaxx.c +++ b/system/STM32WBAxx/system_stm32wbaxx.c @@ -96,37 +96,32 @@ /** @addtogroup STM32WBAxx_System_Private_Defines * @{ */ -#if !defined (HSE_VALUE) -#define HSE_VALUE (32000000U) /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (HSI_VALUE) -#define HSI_VALUE (16000000U) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ /* Note: Following vector table addresses must be defined in line with linker configuration. */ /*!< Uncomment the following line if you need to relocate the vector table anywhere in Flash or Sram, else the vector table is kept at the automatic remap of boot address selected */ -/* #define USER_VECT_TAB_ADDRESS */ +/* #define VECT_TAB_BASE_ADDRESS 0x08000000 */ -#if defined(USER_VECT_TAB_ADDRESS) /*!< Uncomment the following line if you need to relocate your vector Table in Sram else user remap will be done in Flash. */ /* #define VECT_TAB_SRAM */ + +#ifndef VECT_TAB_OFFSET +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +#endif + +#ifndef VECT_TAB_BASE_ADDRESS #if defined(VECT_TAB_SRAM) #define VECT_TAB_BASE_ADDRESS SRAM1_BASE /*!< Vector Table base address field. This value must be a multiple of 0x200. */ -#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ #else #define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. This value must be a multiple of 0x200. */ -#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ #endif /* VECT_TAB_SRAM */ -#endif /* USER_VECT_TAB_ADDRESS */ +#endif /* VECT_TAB_BASE_ADDRESS */ /******************************************************************************/ @@ -193,9 +188,7 @@ void SystemInit(void) #endif /* Configure the Vector Table location -------------------------------------*/ -#if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation */ -#endif /* USER_VECT_TAB_ADDRESS */ #if defined(STM32WBAXX_SI_CUT1_0) /* Work-around for ADC peripheral issue possibly impacting system From 6f9e43c86e0fe85944b9d3b06b645353aa9899af Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 20 Feb 2024 15:46:27 +0100 Subject: [PATCH 09/21] ci(variants): manage mcu family naming higher than 2 Previously, mcu family name contained 2 characters except MP1. New series can have 3 characters, example WBA. So, manage it dynamically. Signed-off-by: Frederic Pillon --- CI/update/stm32variant.py | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/CI/update/stm32variant.py b/CI/update/stm32variant.py index 596ece9add..7386fc4bde 100644 --- a/CI/update/stm32variant.py +++ b/CI/update/stm32variant.py @@ -2141,10 +2141,11 @@ def merge_dir(out_temp_path, group_mcu_dir, mcu_family, periph_xml, variant_exp) mcu_dir = group_mcu_dir[0] # Merge if needed if len(group_mcu_dir) != 1: - index_mcu_base = 5 - # Key function - if "MP1" in mcu_family.name: - index_mcu_base += 1 + # Handle mcu name length dynamically + # Add 3 for extra information line, #pin and flash + index_mcu_base = ( + len(mcu_family.name.removeprefix("STM32").removesuffix("xx")) + 3 + ) # Extract only dir name for dir_name in group_mcu_dir: From 776f02c34c36260a7b540ee0524cbe63b21ff85a Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 20 Feb 2024 15:46:57 +0100 Subject: [PATCH 10/21] variants(WBA): add all generated STM32WBAxx generic variant files Signed-off-by: Frederic Pillon --- .../STM32WBAxx/WBA50K(E-G)U/PeripheralPins.c | 167 ++++++++++++++ .../STM32WBAxx/WBA50K(E-G)U/PinNamesVar.h | 37 +++ .../STM32WBAxx/WBA50K(E-G)U/boards_entry.txt | 21 ++ .../STM32WBAxx/WBA50K(E-G)U/generic_clock.c | 27 +++ .../WBA50K(E-G)U/variant_generic.cpp | 52 +++++ .../STM32WBAxx/WBA50K(E-G)U/variant_generic.h | 140 ++++++++++++ .../PeripheralPins.c | 215 +++++++++++++++++ .../PinNamesVar.h | 62 +++++ .../boards_entry.txt | 53 +++++ .../generic_clock.c | 29 +++ .../variant_generic.cpp | 70 ++++++ .../variant_generic.h | 170 ++++++++++++++ .../PeripheralPins.c | 187 +++++++++++++++ .../WBA52K(E-G)U_WBA54K(E-G)U/PinNamesVar.h | 45 ++++ .../boards_entry.txt | 37 +++ .../WBA52K(E-G)U_WBA54K(E-G)U/generic_clock.c | 28 +++ .../variant_generic.cpp | 53 +++++ .../variant_generic.h | 148 ++++++++++++ .../STM32WBAxx/WBA55C(E-G)U/PeripheralPins.c | 208 +++++++++++++++++ .../STM32WBAxx/WBA55C(E-G)U/PinNamesVar.h | 59 +++++ .../STM32WBAxx/WBA55C(E-G)U/boards_entry.txt | 21 ++ .../STM32WBAxx/WBA55C(E-G)U/generic_clock.c | 27 +++ .../WBA55C(E-G)U/variant_generic.cpp | 63 +++++ .../STM32WBAxx/WBA55C(E-G)U/variant_generic.h | 165 +++++++++++++ .../STM32WBAxx/WBA55U(E-G)I/PeripheralPins.c | 216 ++++++++++++++++++ .../STM32WBAxx/WBA55U(E-G)I/PinNamesVar.h | 65 ++++++ .../STM32WBAxx/WBA55U(E-G)I/boards_entry.txt | 21 ++ .../STM32WBAxx/WBA55U(E-G)I/generic_clock.c | 27 +++ .../WBA55U(E-G)I/variant_generic.cpp | 69 ++++++ .../STM32WBAxx/WBA55U(E-G)I/variant_generic.h | 171 ++++++++++++++ 30 files changed, 2653 insertions(+) create mode 100644 variants/STM32WBAxx/WBA50K(E-G)U/PeripheralPins.c create mode 100644 variants/STM32WBAxx/WBA50K(E-G)U/PinNamesVar.h create mode 100644 variants/STM32WBAxx/WBA50K(E-G)U/boards_entry.txt create mode 100644 variants/STM32WBAxx/WBA50K(E-G)U/generic_clock.c create mode 100644 variants/STM32WBAxx/WBA50K(E-G)U/variant_generic.cpp create mode 100644 variants/STM32WBAxx/WBA50K(E-G)U/variant_generic.h create mode 100644 variants/STM32WBAxx/WBA52C(E-G)U_WBA54C(E-G)U_WBA55H(E-G)F/PeripheralPins.c create mode 100644 variants/STM32WBAxx/WBA52C(E-G)U_WBA54C(E-G)U_WBA55H(E-G)F/PinNamesVar.h create mode 100644 variants/STM32WBAxx/WBA52C(E-G)U_WBA54C(E-G)U_WBA55H(E-G)F/boards_entry.txt create mode 100644 variants/STM32WBAxx/WBA52C(E-G)U_WBA54C(E-G)U_WBA55H(E-G)F/generic_clock.c create mode 100644 variants/STM32WBAxx/WBA52C(E-G)U_WBA54C(E-G)U_WBA55H(E-G)F/variant_generic.cpp create mode 100644 variants/STM32WBAxx/WBA52C(E-G)U_WBA54C(E-G)U_WBA55H(E-G)F/variant_generic.h create mode 100644 variants/STM32WBAxx/WBA52K(E-G)U_WBA54K(E-G)U/PeripheralPins.c create mode 100644 variants/STM32WBAxx/WBA52K(E-G)U_WBA54K(E-G)U/PinNamesVar.h create mode 100644 variants/STM32WBAxx/WBA52K(E-G)U_WBA54K(E-G)U/boards_entry.txt create mode 100644 variants/STM32WBAxx/WBA52K(E-G)U_WBA54K(E-G)U/generic_clock.c create mode 100644 variants/STM32WBAxx/WBA52K(E-G)U_WBA54K(E-G)U/variant_generic.cpp create mode 100644 variants/STM32WBAxx/WBA52K(E-G)U_WBA54K(E-G)U/variant_generic.h create mode 100644 variants/STM32WBAxx/WBA55C(E-G)U/PeripheralPins.c create mode 100644 variants/STM32WBAxx/WBA55C(E-G)U/PinNamesVar.h create mode 100644 variants/STM32WBAxx/WBA55C(E-G)U/boards_entry.txt create mode 100644 variants/STM32WBAxx/WBA55C(E-G)U/generic_clock.c create mode 100644 variants/STM32WBAxx/WBA55C(E-G)U/variant_generic.cpp create mode 100644 variants/STM32WBAxx/WBA55C(E-G)U/variant_generic.h create mode 100644 variants/STM32WBAxx/WBA55U(E-G)I/PeripheralPins.c create mode 100644 variants/STM32WBAxx/WBA55U(E-G)I/PinNamesVar.h create mode 100644 variants/STM32WBAxx/WBA55U(E-G)I/boards_entry.txt create mode 100644 variants/STM32WBAxx/WBA55U(E-G)I/generic_clock.c create mode 100644 variants/STM32WBAxx/WBA55U(E-G)I/variant_generic.cpp create mode 100644 variants/STM32WBAxx/WBA55U(E-G)I/variant_generic.h diff --git a/variants/STM32WBAxx/WBA50K(E-G)U/PeripheralPins.c b/variants/STM32WBAxx/WBA50K(E-G)U/PeripheralPins.c new file mode 100644 index 0000000000..a9a00bad08 --- /dev/null +++ b/variants/STM32WBAxx/WBA50K(E-G)U/PeripheralPins.c @@ -0,0 +1,167 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32WBA50KEUx.xml, STM32WBA50KGUx.xml + * CubeMX DB release 6.0.100 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC4_IN9 + {PA_1, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC4_IN8 + {PA_2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC4_IN7 + {PA_5, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC4_IN4 + {PA_6, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC4_IN3 + {PA_7, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC4_IN2 + {PA_8, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC4_IN1 + {PB_9, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC4_IN10 + {NC, NP, 0} +}; +#endif + +//*** No DAC *** + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PA_7, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_6, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {NC, NP, 0} +}; +#endif + +//*** No I3C *** + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PA_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_2, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_6, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PA_7, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PA_8, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_12, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PB_3, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PB_4, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PB_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 1)}, // TIM16_CH1N + {PB_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_9_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PB_12, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PA_8, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PA_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_15, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PB_8, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PB_9, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_0, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_5, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NP, 0} +}; +#endif + +//*** No CAN *** + +//*** No ETHERNET *** + +//*** No QUADSPI *** + +//*** No USB *** + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32WBAxx/WBA50K(E-G)U/PinNamesVar.h b/variants/STM32WBAxx/WBA50K(E-G)U/PinNamesVar.h new file mode 100644 index 0000000000..8d3aa21e5b --- /dev/null +++ b/variants/STM32WBAxx/WBA50K(E-G)U/PinNamesVar.h @@ -0,0 +1,37 @@ +/* Alternate pin name */ +PB_8_ALT1 = PB_8 | ALT1, +PB_9_ALT1 = PB_9 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = NC, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = PA_1, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = NC, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = PA_5, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6_1 = PA_12, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = PA_6, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = PA_7, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8_1 = PB_9, +#endif + +/* No USB */ diff --git a/variants/STM32WBAxx/WBA50K(E-G)U/boards_entry.txt b/variants/STM32WBAxx/WBA50K(E-G)U/boards_entry.txt new file mode 100644 index 0000000000..ea081fa566 --- /dev/null +++ b/variants/STM32WBAxx/WBA50K(E-G)U/boards_entry.txt @@ -0,0 +1,21 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic WBA50KEUx +GenWBA.menu.pnum.GENERIC_WBA50KEUX=Generic WBA50KEUx +GenWBA.menu.pnum.GENERIC_WBA50KEUX.upload.maximum_size=524288 +GenWBA.menu.pnum.GENERIC_WBA50KEUX.upload.maximum_data_size=65536 +GenWBA.menu.pnum.GENERIC_WBA50KEUX.build.board=GENERIC_WBA50KEUX +GenWBA.menu.pnum.GENERIC_WBA50KEUX.build.product_line=STM32WBA50xx +GenWBA.menu.pnum.GENERIC_WBA50KEUX.build.variant=STM32WBAxx/WBA50K(E-G)U + +# Generic WBA50KGUx +GenWBA.menu.pnum.GENERIC_WBA50KGUX=Generic WBA50KGUx +GenWBA.menu.pnum.GENERIC_WBA50KGUX.upload.maximum_size=1048576 +GenWBA.menu.pnum.GENERIC_WBA50KGUX.upload.maximum_data_size=65536 +GenWBA.menu.pnum.GENERIC_WBA50KGUX.build.board=GENERIC_WBA50KGUX +GenWBA.menu.pnum.GENERIC_WBA50KGUX.build.product_line=STM32WBA50xx +GenWBA.menu.pnum.GENERIC_WBA50KGUX.build.variant=STM32WBAxx/WBA50K(E-G)U + diff --git a/variants/STM32WBAxx/WBA50K(E-G)U/generic_clock.c b/variants/STM32WBAxx/WBA50K(E-G)U/generic_clock.c new file mode 100644 index 0000000000..e4a6b66c93 --- /dev/null +++ b/variants/STM32WBAxx/WBA50K(E-G)U/generic_clock.c @@ -0,0 +1,27 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_WBA50KEUX) || defined(ARDUINO_GENERIC_WBA50KGUX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32WBAxx/WBA50K(E-G)U/variant_generic.cpp b/variants/STM32WBAxx/WBA50K(E-G)U/variant_generic.cpp new file mode 100644 index 0000000000..608f57deb4 --- /dev/null +++ b/variants/STM32WBAxx/WBA50K(E-G)U/variant_generic.cpp @@ -0,0 +1,52 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_WBA50KEUX) || defined(ARDUINO_GENERIC_WBA50KGUX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_5, // D3/A3 + PA_6, // D4/A4 + PA_7, // D5/A5 + PA_8, // D6/A6 + PA_12, // D7 + PA_13, // D8 + PA_14, // D9 + PA_15, // D10 + PB_3, // D11 + PB_4, // D12 + PB_8, // D13 + PB_9, // D14/A7 + PB_12, // D15 + PB_15, // D16 + PC_14, // D17 + PC_15, // D18 + PH_3 // D19 +}; + +// Analog (Ax) pin number array +const uint32_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA5 + 4, // A4, PA6 + 5, // A5, PA7 + 6, // A6, PA8 + 14 // A7, PB9 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32WBAxx/WBA50K(E-G)U/variant_generic.h b/variants/STM32WBAxx/WBA50K(E-G)U/variant_generic.h new file mode 100644 index 0000000000..75709e24dc --- /dev/null +++ b/variants/STM32WBAxx/WBA50K(E-G)U/variant_generic.h @@ -0,0 +1,140 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA5 PIN_A3 +#define PA6 PIN_A4 +#define PA7 PIN_A5 +#define PA8 PIN_A6 +#define PA12 7 +#define PA13 8 +#define PA14 9 +#define PA15 10 +#define PB3 11 +#define PB4 12 +#define PB8 13 +#define PB9 PIN_A7 +#define PB12 15 +#define PB15 16 +#define PC14 17 +#define PC15 18 +#define PH3 19 + +// Alternate pins number +#define PB8_ALT1 (PB8 | ALT1) +#define PB9_ALT1 (PB9 | ALT1) + +#define NUM_DIGITAL_PINS 20 +#define NUM_ANALOG_INPUTS 8 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA5 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PB8 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PB9 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA0 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PA7 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PA6 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM16 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM2 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 101 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA2 +#endif + +// Alternate SYS_WKUP definition +#define PWR_WAKEUP_PIN6_1 +#define PWR_WAKEUP_PIN8_1 + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32WBAxx/WBA52C(E-G)U_WBA54C(E-G)U_WBA55H(E-G)F/PeripheralPins.c b/variants/STM32WBAxx/WBA52C(E-G)U_WBA54C(E-G)U_WBA55H(E-G)F/PeripheralPins.c new file mode 100644 index 0000000000..4c99410f86 --- /dev/null +++ b/variants/STM32WBAxx/WBA52C(E-G)U_WBA54C(E-G)U_WBA55H(E-G)F/PeripheralPins.c @@ -0,0 +1,215 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32WBA52CEUx.xml, STM32WBA52CGUx.xml + * STM32WBA54CEUx.xml, STM32WBA54CGUx.xml + * STM32WBA55HEFx.xml, STM32WBA55HGFx.xml + * CubeMX DB release 6.0.100 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC4_IN9 + {PA_1, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC4_IN8 + {PA_2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC4_IN7 + {PA_3, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC4_IN6 + {PA_5, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC4_IN4 + {PA_6, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC4_IN3 + {PA_7, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC4_IN2 + {PA_8, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC4_IN1 + {PB_9, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC4_IN10 + {NC, NP, 0} +}; +#endif + +//*** No DAC *** + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PA_7, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PB_1, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_1_ALT1, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C3)}, + {PB_3, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_6, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PA_15, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_2, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_2_ALT1, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C3)}, + {NC, NP, 0} +}; +#endif + +//*** No I3C *** + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PA_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PA_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_1_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PA_2, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_2_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PA_3, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 1)}, // TIM16_CH1N + {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_6, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PA_7, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PA_8, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_10, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_12, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_2, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_3, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PB_3_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 1)}, // TIM17_CH1N + {PB_4, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PB_4_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_6, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 1)}, // TIM1_CH4N + {PB_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 1)}, // TIM16_CH1N + {PB_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_9_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_9_ALT2, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PB_12, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_13, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_14, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PA_12, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)}, + {PA_14, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)}, + {PB_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)}, + {PB_5, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PA_8, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PA_11, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)}, + {PB_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)}, + {PB_8, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_3, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PA_15, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)}, + {PB_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)}, + {PB_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PA_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)}, + {PB_15, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_15_ALT1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_8, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_9, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_0, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_5, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PA_12, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {NC, NP, 0} +}; +#endif + +//*** No CAN *** + +//*** No ETHERNET *** + +//*** No QUADSPI *** + +//*** No USB *** + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32WBAxx/WBA52C(E-G)U_WBA54C(E-G)U_WBA55H(E-G)F/PinNamesVar.h b/variants/STM32WBAxx/WBA52C(E-G)U_WBA54C(E-G)U_WBA55H(E-G)F/PinNamesVar.h new file mode 100644 index 0000000000..0df967d7af --- /dev/null +++ b/variants/STM32WBAxx/WBA52C(E-G)U_WBA54C(E-G)U_WBA55H(E-G)F/PinNamesVar.h @@ -0,0 +1,62 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_2_ALT1 = PA_2 | ALT1, +PB_1_ALT1 = PB_1 | ALT1, +PB_2_ALT1 = PB_2 | ALT1, +PB_3_ALT1 = PB_3 | ALT1, +PB_4_ALT1 = PB_4 | ALT1, +PB_8_ALT1 = PB_8 | ALT1, +PB_9_ALT1 = PB_9 | ALT1, +PB_9_ALT2 = PB_9 | ALT2, +PB_15_ALT1 = PB_15 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1_1 = PB_2, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PC_13, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = PA_1, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3_1 = PB_6, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4_1 = PB_1, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PA_3, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5_1 = PB_7, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = PA_5, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6_1 = PA_12, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = PA_6, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7_1 = PB_14, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = PA_7, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8_1 = PB_9, +#endif + +/* No USB */ diff --git a/variants/STM32WBAxx/WBA52C(E-G)U_WBA54C(E-G)U_WBA55H(E-G)F/boards_entry.txt b/variants/STM32WBAxx/WBA52C(E-G)U_WBA54C(E-G)U_WBA55H(E-G)F/boards_entry.txt new file mode 100644 index 0000000000..9c141c81e0 --- /dev/null +++ b/variants/STM32WBAxx/WBA52C(E-G)U_WBA54C(E-G)U_WBA55H(E-G)F/boards_entry.txt @@ -0,0 +1,53 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic WBA52CEUx +GenWBA.menu.pnum.GENERIC_WBA52CEUX=Generic WBA52CEUx +GenWBA.menu.pnum.GENERIC_WBA52CEUX.upload.maximum_size=524288 +GenWBA.menu.pnum.GENERIC_WBA52CEUX.upload.maximum_data_size=98304 +GenWBA.menu.pnum.GENERIC_WBA52CEUX.build.board=GENERIC_WBA52CEUX +GenWBA.menu.pnum.GENERIC_WBA52CEUX.build.product_line=STM32WBA52xx +GenWBA.menu.pnum.GENERIC_WBA52CEUX.build.variant=STM32WBAxx/WBA52C(E-G)U_WBA54C(E-G)U_WBA55H(E-G)F + +# Generic WBA52CGUx +GenWBA.menu.pnum.GENERIC_WBA52CGUX=Generic WBA52CGUx +GenWBA.menu.pnum.GENERIC_WBA52CGUX.upload.maximum_size=1048576 +GenWBA.menu.pnum.GENERIC_WBA52CGUX.upload.maximum_data_size=131072 +GenWBA.menu.pnum.GENERIC_WBA52CGUX.build.board=GENERIC_WBA52CGUX +GenWBA.menu.pnum.GENERIC_WBA52CGUX.build.product_line=STM32WBA52xx +GenWBA.menu.pnum.GENERIC_WBA52CGUX.build.variant=STM32WBAxx/WBA52C(E-G)U_WBA54C(E-G)U_WBA55H(E-G)F + +# Generic WBA54CEUx +GenWBA.menu.pnum.GENERIC_WBA54CEUX=Generic WBA54CEUx +GenWBA.menu.pnum.GENERIC_WBA54CEUX.upload.maximum_size=524288 +GenWBA.menu.pnum.GENERIC_WBA54CEUX.upload.maximum_data_size=98304 +GenWBA.menu.pnum.GENERIC_WBA54CEUX.build.board=GENERIC_WBA54CEUX +GenWBA.menu.pnum.GENERIC_WBA54CEUX.build.product_line=STM32WBA54xx +GenWBA.menu.pnum.GENERIC_WBA54CEUX.build.variant=STM32WBAxx/WBA52C(E-G)U_WBA54C(E-G)U_WBA55H(E-G)F + +# Generic WBA54CGUx +GenWBA.menu.pnum.GENERIC_WBA54CGUX=Generic WBA54CGUx +GenWBA.menu.pnum.GENERIC_WBA54CGUX.upload.maximum_size=1048576 +GenWBA.menu.pnum.GENERIC_WBA54CGUX.upload.maximum_data_size=131072 +GenWBA.menu.pnum.GENERIC_WBA54CGUX.build.board=GENERIC_WBA54CGUX +GenWBA.menu.pnum.GENERIC_WBA54CGUX.build.product_line=STM32WBA54xx +GenWBA.menu.pnum.GENERIC_WBA54CGUX.build.variant=STM32WBAxx/WBA52C(E-G)U_WBA54C(E-G)U_WBA55H(E-G)F + +# Generic WBA55HEFx +GenWBA.menu.pnum.GENERIC_WBA55HEFX=Generic WBA55HEFx +GenWBA.menu.pnum.GENERIC_WBA55HEFX.upload.maximum_size=524288 +GenWBA.menu.pnum.GENERIC_WBA55HEFX.upload.maximum_data_size=98304 +GenWBA.menu.pnum.GENERIC_WBA55HEFX.build.board=GENERIC_WBA55HEFX +GenWBA.menu.pnum.GENERIC_WBA55HEFX.build.product_line=STM32WBA55xx +GenWBA.menu.pnum.GENERIC_WBA55HEFX.build.variant=STM32WBAxx/WBA52C(E-G)U_WBA54C(E-G)U_WBA55H(E-G)F + +# Generic WBA55HGFx +GenWBA.menu.pnum.GENERIC_WBA55HGFX=Generic WBA55HGFx +GenWBA.menu.pnum.GENERIC_WBA55HGFX.upload.maximum_size=1048576 +GenWBA.menu.pnum.GENERIC_WBA55HGFX.upload.maximum_data_size=131072 +GenWBA.menu.pnum.GENERIC_WBA55HGFX.build.board=GENERIC_WBA55HGFX +GenWBA.menu.pnum.GENERIC_WBA55HGFX.build.product_line=STM32WBA55xx +GenWBA.menu.pnum.GENERIC_WBA55HGFX.build.variant=STM32WBAxx/WBA52C(E-G)U_WBA54C(E-G)U_WBA55H(E-G)F + diff --git a/variants/STM32WBAxx/WBA52C(E-G)U_WBA54C(E-G)U_WBA55H(E-G)F/generic_clock.c b/variants/STM32WBAxx/WBA52C(E-G)U_WBA54C(E-G)U_WBA55H(E-G)F/generic_clock.c new file mode 100644 index 0000000000..a27a547a62 --- /dev/null +++ b/variants/STM32WBAxx/WBA52C(E-G)U_WBA54C(E-G)U_WBA55H(E-G)F/generic_clock.c @@ -0,0 +1,29 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_WBA52CEUX) || defined(ARDUINO_GENERIC_WBA52CGUX) ||\ + defined(ARDUINO_GENERIC_WBA54CEUX) || defined(ARDUINO_GENERIC_WBA54CGUX) ||\ + defined(ARDUINO_GENERIC_WBA55HEFX) || defined(ARDUINO_GENERIC_WBA55HGFX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32WBAxx/WBA52C(E-G)U_WBA54C(E-G)U_WBA55H(E-G)F/variant_generic.cpp b/variants/STM32WBAxx/WBA52C(E-G)U_WBA54C(E-G)U_WBA55H(E-G)F/variant_generic.cpp new file mode 100644 index 0000000000..48b953da2f --- /dev/null +++ b/variants/STM32WBAxx/WBA52C(E-G)U_WBA54C(E-G)U_WBA55H(E-G)F/variant_generic.cpp @@ -0,0 +1,70 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_WBA52CEUX) || defined(ARDUINO_GENERIC_WBA52CGUX) ||\ + defined(ARDUINO_GENERIC_WBA54CEUX) || defined(ARDUINO_GENERIC_WBA54CGUX) ||\ + defined(ARDUINO_GENERIC_WBA55HEFX) || defined(ARDUINO_GENERIC_WBA55HGFX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_5, // D4/A4 + PA_6, // D5/A5 + PA_7, // D6/A6 + PA_8, // D7/A7 + PA_9, // D8 + PA_10, // D9 + PA_11, // D10 + PA_12, // D11 + PA_13, // D12 + PA_14, // D13 + PA_15, // D14 + PB_0, // D15 + PB_1, // D16 + PB_2, // D17 + PB_3, // D18 + PB_4, // D19 + PB_5, // D20 + PB_6, // D21 + PB_7, // D22 + PB_8, // D23 + PB_9, // D24/A8 + PB_10, // D25 + PB_11, // D26 + PB_12, // D27 + PB_13, // D28 + PB_14, // D29 + PB_15, // D30 + PC_13, // D31 + PC_14, // D32 + PC_15, // D33 + PH_3 // D34 +}; + +// Analog (Ax) pin number array +const uint32_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA5 + 5, // A5, PA6 + 6, // A6, PA7 + 7, // A7, PA8 + 24 // A8, PB9 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32WBAxx/WBA52C(E-G)U_WBA54C(E-G)U_WBA55H(E-G)F/variant_generic.h b/variants/STM32WBAxx/WBA52C(E-G)U_WBA54C(E-G)U_WBA55H(E-G)F/variant_generic.h new file mode 100644 index 0000000000..3695f71db0 --- /dev/null +++ b/variants/STM32WBAxx/WBA52C(E-G)U_WBA54C(E-G)U_WBA55H(E-G)F/variant_generic.h @@ -0,0 +1,170 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA5 PIN_A4 +#define PA6 PIN_A5 +#define PA7 PIN_A6 +#define PA8 PIN_A7 +#define PA9 8 +#define PA10 9 +#define PA11 10 +#define PA12 11 +#define PA13 12 +#define PA14 13 +#define PA15 14 +#define PB0 15 +#define PB1 16 +#define PB2 17 +#define PB3 18 +#define PB4 19 +#define PB5 20 +#define PB6 21 +#define PB7 22 +#define PB8 23 +#define PB9 PIN_A8 +#define PB10 25 +#define PB11 26 +#define PB12 27 +#define PB13 28 +#define PB14 29 +#define PB15 30 +#define PC13 31 +#define PC14 32 +#define PC15 33 +#define PH3 34 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA2_ALT1 (PA2 | ALT1) +#define PB1_ALT1 (PB1 | ALT1) +#define PB2_ALT1 (PB2 | ALT1) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB8_ALT1 (PB8 | ALT1) +#define PB9_ALT1 (PB9 | ALT1) +#define PB9_ALT2 (PB9 | ALT2) +#define PB15_ALT1 (PB15 | ALT1) + +#define NUM_DIGITAL_PINS 35 +#define NUM_ANALOG_INPUTS 9 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA12 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA15 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PB3 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PB4 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PA7 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PA6 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM16 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM17 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 101 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA2 +#endif + +// Alternate SYS_WKUP definition +#define PWR_WAKEUP_PIN1_1 +#define PWR_WAKEUP_PIN3_1 +#define PWR_WAKEUP_PIN4_1 +#define PWR_WAKEUP_PIN5_1 +#define PWR_WAKEUP_PIN6_1 +#define PWR_WAKEUP_PIN7_1 +#define PWR_WAKEUP_PIN8_1 + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32WBAxx/WBA52K(E-G)U_WBA54K(E-G)U/PeripheralPins.c b/variants/STM32WBAxx/WBA52K(E-G)U_WBA54K(E-G)U/PeripheralPins.c new file mode 100644 index 0000000000..a6aea956f6 --- /dev/null +++ b/variants/STM32WBAxx/WBA52K(E-G)U_WBA54K(E-G)U/PeripheralPins.c @@ -0,0 +1,187 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32WBA52KEUx.xml, STM32WBA52KGUx.xml + * STM32WBA54KEUx.xml, STM32WBA54KGUx.xml + * CubeMX DB release 6.0.100 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC4_IN9 + {PA_1, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC4_IN8 + {PA_2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC4_IN7 + {PA_5, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC4_IN4 + {PA_6, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC4_IN3 + {PA_7, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC4_IN2 + {PA_8, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC4_IN1 + {PB_9, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC4_IN10 + {NC, NP, 0} +}; +#endif + +//*** No DAC *** + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PA_7, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PB_3, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_6, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PA_15, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {NC, NP, 0} +}; +#endif + +//*** No I3C *** + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PA_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PA_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_1_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PA_2, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_2_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_6, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PA_7, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PA_8, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_12, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PB_3, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PB_3_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 1)}, // TIM17_CH1N + {PB_4, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PB_4_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PB_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 1)}, // TIM16_CH1N + {PB_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_9_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_9_ALT2, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PB_12, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PA_12, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)}, + {PA_14, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)}, + {PB_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PA_8, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)}, + {PB_8, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_15, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)}, + {PB_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PA_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_15, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_15_ALT1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_8, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_9, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_0, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_5, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PA_12, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {NC, NP, 0} +}; +#endif + +//*** No CAN *** + +//*** No ETHERNET *** + +//*** No QUADSPI *** + +//*** No USB *** + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32WBAxx/WBA52K(E-G)U_WBA54K(E-G)U/PinNamesVar.h b/variants/STM32WBAxx/WBA52K(E-G)U_WBA54K(E-G)U/PinNamesVar.h new file mode 100644 index 0000000000..465ce318c2 --- /dev/null +++ b/variants/STM32WBAxx/WBA52K(E-G)U_WBA54K(E-G)U/PinNamesVar.h @@ -0,0 +1,45 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_2_ALT1 = PA_2 | ALT1, +PB_3_ALT1 = PB_3 | ALT1, +PB_4_ALT1 = PB_4 | ALT1, +PB_8_ALT1 = PB_8 | ALT1, +PB_9_ALT1 = PB_9 | ALT1, +PB_9_ALT2 = PB_9 | ALT2, +PB_15_ALT1 = PB_15 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = NC, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = PA_1, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = NC, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = PA_5, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6_1 = PA_12, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = PA_6, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = PA_7, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8_1 = PB_9, +#endif + +/* No USB */ diff --git a/variants/STM32WBAxx/WBA52K(E-G)U_WBA54K(E-G)U/boards_entry.txt b/variants/STM32WBAxx/WBA52K(E-G)U_WBA54K(E-G)U/boards_entry.txt new file mode 100644 index 0000000000..0d82cba4ab --- /dev/null +++ b/variants/STM32WBAxx/WBA52K(E-G)U_WBA54K(E-G)U/boards_entry.txt @@ -0,0 +1,37 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic WBA52KEUx +GenWBA.menu.pnum.GENERIC_WBA52KEUX=Generic WBA52KEUx +GenWBA.menu.pnum.GENERIC_WBA52KEUX.upload.maximum_size=524288 +GenWBA.menu.pnum.GENERIC_WBA52KEUX.upload.maximum_data_size=98304 +GenWBA.menu.pnum.GENERIC_WBA52KEUX.build.board=GENERIC_WBA52KEUX +GenWBA.menu.pnum.GENERIC_WBA52KEUX.build.product_line=STM32WBA52xx +GenWBA.menu.pnum.GENERIC_WBA52KEUX.build.variant=STM32WBAxx/WBA52K(E-G)U_WBA54K(E-G)U + +# Generic WBA52KGUx +GenWBA.menu.pnum.GENERIC_WBA52KGUX=Generic WBA52KGUx +GenWBA.menu.pnum.GENERIC_WBA52KGUX.upload.maximum_size=1048576 +GenWBA.menu.pnum.GENERIC_WBA52KGUX.upload.maximum_data_size=131072 +GenWBA.menu.pnum.GENERIC_WBA52KGUX.build.board=GENERIC_WBA52KGUX +GenWBA.menu.pnum.GENERIC_WBA52KGUX.build.product_line=STM32WBA52xx +GenWBA.menu.pnum.GENERIC_WBA52KGUX.build.variant=STM32WBAxx/WBA52K(E-G)U_WBA54K(E-G)U + +# Generic WBA54KEUx +GenWBA.menu.pnum.GENERIC_WBA54KEUX=Generic WBA54KEUx +GenWBA.menu.pnum.GENERIC_WBA54KEUX.upload.maximum_size=524288 +GenWBA.menu.pnum.GENERIC_WBA54KEUX.upload.maximum_data_size=98304 +GenWBA.menu.pnum.GENERIC_WBA54KEUX.build.board=GENERIC_WBA54KEUX +GenWBA.menu.pnum.GENERIC_WBA54KEUX.build.product_line=STM32WBA54xx +GenWBA.menu.pnum.GENERIC_WBA54KEUX.build.variant=STM32WBAxx/WBA52K(E-G)U_WBA54K(E-G)U + +# Generic WBA54KGUx +GenWBA.menu.pnum.GENERIC_WBA54KGUX=Generic WBA54KGUx +GenWBA.menu.pnum.GENERIC_WBA54KGUX.upload.maximum_size=1048576 +GenWBA.menu.pnum.GENERIC_WBA54KGUX.upload.maximum_data_size=131072 +GenWBA.menu.pnum.GENERIC_WBA54KGUX.build.board=GENERIC_WBA54KGUX +GenWBA.menu.pnum.GENERIC_WBA54KGUX.build.product_line=STM32WBA54xx +GenWBA.menu.pnum.GENERIC_WBA54KGUX.build.variant=STM32WBAxx/WBA52K(E-G)U_WBA54K(E-G)U + diff --git a/variants/STM32WBAxx/WBA52K(E-G)U_WBA54K(E-G)U/generic_clock.c b/variants/STM32WBAxx/WBA52K(E-G)U_WBA54K(E-G)U/generic_clock.c new file mode 100644 index 0000000000..9d191ccae9 --- /dev/null +++ b/variants/STM32WBAxx/WBA52K(E-G)U_WBA54K(E-G)U/generic_clock.c @@ -0,0 +1,28 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_WBA52KEUX) || defined(ARDUINO_GENERIC_WBA52KGUX) ||\ + defined(ARDUINO_GENERIC_WBA54KEUX) || defined(ARDUINO_GENERIC_WBA54KGUX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32WBAxx/WBA52K(E-G)U_WBA54K(E-G)U/variant_generic.cpp b/variants/STM32WBAxx/WBA52K(E-G)U_WBA54K(E-G)U/variant_generic.cpp new file mode 100644 index 0000000000..53f94598c1 --- /dev/null +++ b/variants/STM32WBAxx/WBA52K(E-G)U_WBA54K(E-G)U/variant_generic.cpp @@ -0,0 +1,53 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_WBA52KEUX) || defined(ARDUINO_GENERIC_WBA52KGUX) ||\ + defined(ARDUINO_GENERIC_WBA54KEUX) || defined(ARDUINO_GENERIC_WBA54KGUX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_5, // D3/A3 + PA_6, // D4/A4 + PA_7, // D5/A5 + PA_8, // D6/A6 + PA_12, // D7 + PA_13, // D8 + PA_14, // D9 + PA_15, // D10 + PB_3, // D11 + PB_4, // D12 + PB_8, // D13 + PB_9, // D14/A7 + PB_12, // D15 + PB_15, // D16 + PC_14, // D17 + PC_15, // D18 + PH_3 // D19 +}; + +// Analog (Ax) pin number array +const uint32_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA5 + 4, // A4, PA6 + 5, // A5, PA7 + 6, // A6, PA8 + 14 // A7, PB9 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32WBAxx/WBA52K(E-G)U_WBA54K(E-G)U/variant_generic.h b/variants/STM32WBAxx/WBA52K(E-G)U_WBA54K(E-G)U/variant_generic.h new file mode 100644 index 0000000000..1b698ce60c --- /dev/null +++ b/variants/STM32WBAxx/WBA52K(E-G)U_WBA54K(E-G)U/variant_generic.h @@ -0,0 +1,148 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA5 PIN_A3 +#define PA6 PIN_A4 +#define PA7 PIN_A5 +#define PA8 PIN_A6 +#define PA12 7 +#define PA13 8 +#define PA14 9 +#define PA15 10 +#define PB3 11 +#define PB4 12 +#define PB8 13 +#define PB9 PIN_A7 +#define PB12 15 +#define PB15 16 +#define PC14 17 +#define PC15 18 +#define PH3 19 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA2_ALT1 (PA2 | ALT1) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB8_ALT1 (PB8 | ALT1) +#define PB9_ALT1 (PB9 | ALT1) +#define PB9_ALT2 (PB9 | ALT2) +#define PB15_ALT1 (PB15 | ALT1) + +#define NUM_DIGITAL_PINS 20 +#define NUM_ANALOG_INPUTS 8 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA12 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA15 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PB3 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PB4 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PA7 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PA6 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM16 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM17 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 101 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA2 +#endif + +// Alternate SYS_WKUP definition +#define PWR_WAKEUP_PIN6_1 +#define PWR_WAKEUP_PIN8_1 + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32WBAxx/WBA55C(E-G)U/PeripheralPins.c b/variants/STM32WBAxx/WBA55C(E-G)U/PeripheralPins.c new file mode 100644 index 0000000000..547e19544b --- /dev/null +++ b/variants/STM32WBAxx/WBA55C(E-G)U/PeripheralPins.c @@ -0,0 +1,208 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32WBA55CEUx.xml, STM32WBA55CGUx.xml + * CubeMX DB release 6.0.100 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC4_IN9 + {PA_1, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC4_IN8 + {PA_2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC4_IN7 + {PA_5, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC4_IN4 + {PA_6, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC4_IN3 + {PA_7, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC4_IN2 + {PA_8, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC4_IN1 + {PB_9, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC4_IN10 + {NC, NP, 0} +}; +#endif + +//*** No DAC *** + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PA_7, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PB_1, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_1_ALT1, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C3)}, + {PB_3, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_6, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PA_15, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_2, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_2_ALT1, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C3)}, + {NC, NP, 0} +}; +#endif + +//*** No I3C *** + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PA_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PA_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_1_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PA_2, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_2_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_6, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PA_7, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PA_8, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_10, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_12, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_2, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_3, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PB_3_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 1)}, // TIM17_CH1N + {PB_4, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PB_4_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_6, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 1)}, // TIM1_CH4N + {PB_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 1)}, // TIM16_CH1N + {PB_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_9_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_9_ALT2, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PB_12, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_14, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PA_12, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)}, + {PA_14, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)}, + {PB_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)}, + {PB_5, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PA_8, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PA_11, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)}, + {PB_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)}, + {PB_8, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PA_15, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)}, + {PB_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)}, + {PB_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PA_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)}, + {PB_15, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_15_ALT1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_8, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_9, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_0, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_5, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PA_12, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {NC, NP, 0} +}; +#endif + +//*** No CAN *** + +//*** No ETHERNET *** + +//*** No QUADSPI *** + +//*** No USB *** + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32WBAxx/WBA55C(E-G)U/PinNamesVar.h b/variants/STM32WBAxx/WBA55C(E-G)U/PinNamesVar.h new file mode 100644 index 0000000000..cecfe5478f --- /dev/null +++ b/variants/STM32WBAxx/WBA55C(E-G)U/PinNamesVar.h @@ -0,0 +1,59 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_2_ALT1 = PA_2 | ALT1, +PB_1_ALT1 = PB_1 | ALT1, +PB_2_ALT1 = PB_2 | ALT1, +PB_3_ALT1 = PB_3 | ALT1, +PB_4_ALT1 = PB_4 | ALT1, +PB_8_ALT1 = PB_8 | ALT1, +PB_9_ALT1 = PB_9 | ALT1, +PB_9_ALT2 = PB_9 | ALT2, +PB_15_ALT1 = PB_15 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1_1 = PB_2, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PC_13, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = PA_1, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3_1 = PB_6, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4_1 = PB_1, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PB_7, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = PA_5, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6_1 = PA_12, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = PA_6, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7_1 = PB_14, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = PA_7, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8_1 = PB_9, +#endif + +/* No USB */ diff --git a/variants/STM32WBAxx/WBA55C(E-G)U/boards_entry.txt b/variants/STM32WBAxx/WBA55C(E-G)U/boards_entry.txt new file mode 100644 index 0000000000..61968aeb49 --- /dev/null +++ b/variants/STM32WBAxx/WBA55C(E-G)U/boards_entry.txt @@ -0,0 +1,21 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic WBA55CEUx +GenWBA.menu.pnum.GENERIC_WBA55CEUX=Generic WBA55CEUx +GenWBA.menu.pnum.GENERIC_WBA55CEUX.upload.maximum_size=524288 +GenWBA.menu.pnum.GENERIC_WBA55CEUX.upload.maximum_data_size=98304 +GenWBA.menu.pnum.GENERIC_WBA55CEUX.build.board=GENERIC_WBA55CEUX +GenWBA.menu.pnum.GENERIC_WBA55CEUX.build.product_line=STM32WBA55xx +GenWBA.menu.pnum.GENERIC_WBA55CEUX.build.variant=STM32WBAxx/WBA55C(E-G)U + +# Generic WBA55CGUx +GenWBA.menu.pnum.GENERIC_WBA55CGUX=Generic WBA55CGUx +GenWBA.menu.pnum.GENERIC_WBA55CGUX.upload.maximum_size=1048576 +GenWBA.menu.pnum.GENERIC_WBA55CGUX.upload.maximum_data_size=131072 +GenWBA.menu.pnum.GENERIC_WBA55CGUX.build.board=GENERIC_WBA55CGUX +GenWBA.menu.pnum.GENERIC_WBA55CGUX.build.product_line=STM32WBA55xx +GenWBA.menu.pnum.GENERIC_WBA55CGUX.build.variant=STM32WBAxx/WBA55C(E-G)U + diff --git a/variants/STM32WBAxx/WBA55C(E-G)U/generic_clock.c b/variants/STM32WBAxx/WBA55C(E-G)U/generic_clock.c new file mode 100644 index 0000000000..69077431a4 --- /dev/null +++ b/variants/STM32WBAxx/WBA55C(E-G)U/generic_clock.c @@ -0,0 +1,27 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_WBA55CEUX) || defined(ARDUINO_GENERIC_WBA55CGUX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32WBAxx/WBA55C(E-G)U/variant_generic.cpp b/variants/STM32WBAxx/WBA55C(E-G)U/variant_generic.cpp new file mode 100644 index 0000000000..429ae850c6 --- /dev/null +++ b/variants/STM32WBAxx/WBA55C(E-G)U/variant_generic.cpp @@ -0,0 +1,63 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_WBA55CEUX) || defined(ARDUINO_GENERIC_WBA55CGUX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_5, // D3/A3 + PA_6, // D4/A4 + PA_7, // D5/A5 + PA_8, // D6/A6 + PA_9, // D7 + PA_10, // D8 + PA_11, // D9 + PA_12, // D10 + PA_13, // D11 + PA_14, // D12 + PA_15, // D13 + PB_0, // D14 + PB_1, // D15 + PB_2, // D16 + PB_3, // D17 + PB_4, // D18 + PB_5, // D19 + PB_6, // D20 + PB_7, // D21 + PB_8, // D22 + PB_9, // D23/A7 + PB_12, // D24 + PB_14, // D25 + PB_15, // D26 + PC_13, // D27 + PC_14, // D28 + PC_15, // D29 + PH_3 // D30 +}; + +// Analog (Ax) pin number array +const uint32_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA5 + 4, // A4, PA6 + 5, // A5, PA7 + 6, // A6, PA8 + 23 // A7, PB9 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32WBAxx/WBA55C(E-G)U/variant_generic.h b/variants/STM32WBAxx/WBA55C(E-G)U/variant_generic.h new file mode 100644 index 0000000000..00f4f108d4 --- /dev/null +++ b/variants/STM32WBAxx/WBA55C(E-G)U/variant_generic.h @@ -0,0 +1,165 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA5 PIN_A3 +#define PA6 PIN_A4 +#define PA7 PIN_A5 +#define PA8 PIN_A6 +#define PA9 7 +#define PA10 8 +#define PA11 9 +#define PA12 10 +#define PA13 11 +#define PA14 12 +#define PA15 13 +#define PB0 14 +#define PB1 15 +#define PB2 16 +#define PB3 17 +#define PB4 18 +#define PB5 19 +#define PB6 20 +#define PB7 21 +#define PB8 22 +#define PB9 PIN_A7 +#define PB12 24 +#define PB14 25 +#define PB15 26 +#define PC13 27 +#define PC14 28 +#define PC15 29 +#define PH3 30 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA2_ALT1 (PA2 | ALT1) +#define PB1_ALT1 (PB1 | ALT1) +#define PB2_ALT1 (PB2 | ALT1) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB8_ALT1 (PB8 | ALT1) +#define PB9_ALT1 (PB9 | ALT1) +#define PB9_ALT2 (PB9 | ALT2) +#define PB15_ALT1 (PB15 | ALT1) + +#define NUM_DIGITAL_PINS 31 +#define NUM_ANALOG_INPUTS 8 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA12 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA15 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PB3 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PB4 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PA7 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PA6 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM16 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM17 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 101 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA2 +#endif + +// Alternate SYS_WKUP definition +#define PWR_WAKEUP_PIN1_1 +#define PWR_WAKEUP_PIN3_1 +#define PWR_WAKEUP_PIN4_1 +#define PWR_WAKEUP_PIN6_1 +#define PWR_WAKEUP_PIN7_1 +#define PWR_WAKEUP_PIN8_1 + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif diff --git a/variants/STM32WBAxx/WBA55U(E-G)I/PeripheralPins.c b/variants/STM32WBAxx/WBA55U(E-G)I/PeripheralPins.c new file mode 100644 index 0000000000..b06b23cf61 --- /dev/null +++ b/variants/STM32WBAxx/WBA55U(E-G)I/PeripheralPins.c @@ -0,0 +1,216 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32WBA55UEIx.xml, STM32WBA55UGIx.xml + * CubeMX DB release 6.0.100 + */ +#if !defined(CUSTOM_PERIPHERAL_PINS) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC4_IN9 + {PA_1, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC4_IN8 + {PA_2, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC4_IN7 + {PA_3, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC4_IN6 + {PA_4, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC4_IN5 + {PA_5, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC4_IN4 + {PA_6, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC4_IN3 + {PA_7, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC4_IN2 + {PA_8, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC4_IN1 + {PB_9, ADC4, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC4_IN10 + {NC, NP, 0} +}; +#endif + +//*** No DAC *** + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PA_7, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PB_1, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_1_ALT1, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C3)}, + {PB_3, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_6, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PA_15, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_2, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_2_ALT1, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C3)}, + {NC, NP, 0} +}; +#endif + +//*** No I3C *** + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PA_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PA_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_1_ALT2, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PA_2, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_2_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PA_3, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 1)}, // TIM16_CH1N + {PA_4, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_6, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PA_7, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PA_8, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_10, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_12, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_2, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_3, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PB_3_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 1)}, // TIM17_CH1N + {PB_4, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PB_4_ALT1, TIM17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_6, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 1)}, // TIM1_CH4N + {PB_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PB_8_ALT1, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 1)}, // TIM16_CH1N + {PB_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_9_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_9_ALT2, TIM16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PB_12, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_13, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_14, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_2, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PA_12, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)}, + {PA_14, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)}, + {PB_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)}, + {PB_5, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_11, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_14, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PA_8, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_10, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PA_11, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)}, + {PB_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)}, + {PB_8, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_2, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_3, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PA_15, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)}, + {PB_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)}, + {PB_9, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PA_4, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)}, + {PB_15, LPUART1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_15_ALT1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)}, + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_8, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_9, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_0, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_5, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PA_12, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {NC, NP, 0} +}; +#endif + +//*** No CAN *** + +//*** No ETHERNET *** + +//*** No QUADSPI *** + +//*** No USB *** + +//*** No SD *** + +#endif /* !CUSTOM_PERIPHERAL_PINS */ diff --git a/variants/STM32WBAxx/WBA55U(E-G)I/PinNamesVar.h b/variants/STM32WBAxx/WBA55U(E-G)I/PinNamesVar.h new file mode 100644 index 0000000000..541a712588 --- /dev/null +++ b/variants/STM32WBAxx/WBA55U(E-G)I/PinNamesVar.h @@ -0,0 +1,65 @@ +/* Alternate pin name */ +PA_0_ALT1 = PA_0 | ALT1, +PA_1_ALT1 = PA_1 | ALT1, +PA_1_ALT2 = PA_1 | ALT2, +PA_2_ALT1 = PA_2 | ALT1, +PB_1_ALT1 = PB_1 | ALT1, +PB_2_ALT1 = PB_2 | ALT1, +PB_3_ALT1 = PB_3 | ALT1, +PB_4_ALT1 = PB_4 | ALT1, +PB_8_ALT1 = PB_8 | ALT1, +PB_9_ALT1 = PB_9 | ALT1, +PB_9_ALT2 = PB_9 | ALT2, +PB_15_ALT1 = PB_15 | ALT1, + +/* SYS_WKUP */ +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1 = PB_2, +#endif +#ifdef PWR_WAKEUP_PIN1 + SYS_WKUP1_1 = PA_0, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2 = PA_4, +#endif +#ifdef PWR_WAKEUP_PIN2 + SYS_WKUP2_1 = PC_13, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3 = PB_6, +#endif +#ifdef PWR_WAKEUP_PIN3 + SYS_WKUP3_1 = PA_1, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4 = PB_1, +#endif +#ifdef PWR_WAKEUP_PIN4 + SYS_WKUP4_1 = PA_2, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5 = PA_3, +#endif +#ifdef PWR_WAKEUP_PIN5 + SYS_WKUP5_1 = PB_7, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6 = PA_5, +#endif +#ifdef PWR_WAKEUP_PIN6 + SYS_WKUP6_1 = PA_12, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7 = PB_14, +#endif +#ifdef PWR_WAKEUP_PIN7 + SYS_WKUP7_1 = PA_6, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8 = PA_7, +#endif +#ifdef PWR_WAKEUP_PIN8 + SYS_WKUP8_1 = PB_9, +#endif + +/* No USB */ diff --git a/variants/STM32WBAxx/WBA55U(E-G)I/boards_entry.txt b/variants/STM32WBAxx/WBA55U(E-G)I/boards_entry.txt new file mode 100644 index 0000000000..1656e98c57 --- /dev/null +++ b/variants/STM32WBAxx/WBA55U(E-G)I/boards_entry.txt @@ -0,0 +1,21 @@ +# This file help to add generic board entry. +# upload.maximum_size and product_line have to be verified +# and changed if needed. +# See: https://github.com/stm32duino/Arduino_Core_STM32/wiki/Add-a-new-variant-%28board%29 + +# Generic WBA55UEIx +GenWBA.menu.pnum.GENERIC_WBA55UEIX=Generic WBA55UEIx +GenWBA.menu.pnum.GENERIC_WBA55UEIX.upload.maximum_size=524288 +GenWBA.menu.pnum.GENERIC_WBA55UEIX.upload.maximum_data_size=98304 +GenWBA.menu.pnum.GENERIC_WBA55UEIX.build.board=GENERIC_WBA55UEIX +GenWBA.menu.pnum.GENERIC_WBA55UEIX.build.product_line=STM32WBA55xx +GenWBA.menu.pnum.GENERIC_WBA55UEIX.build.variant=STM32WBAxx/WBA55U(E-G)I + +# Generic WBA55UGIx +GenWBA.menu.pnum.GENERIC_WBA55UGIX=Generic WBA55UGIx +GenWBA.menu.pnum.GENERIC_WBA55UGIX.upload.maximum_size=1048576 +GenWBA.menu.pnum.GENERIC_WBA55UGIX.upload.maximum_data_size=131072 +GenWBA.menu.pnum.GENERIC_WBA55UGIX.build.board=GENERIC_WBA55UGIX +GenWBA.menu.pnum.GENERIC_WBA55UGIX.build.product_line=STM32WBA55xx +GenWBA.menu.pnum.GENERIC_WBA55UGIX.build.variant=STM32WBAxx/WBA55U(E-G)I + diff --git a/variants/STM32WBAxx/WBA55U(E-G)I/generic_clock.c b/variants/STM32WBAxx/WBA55U(E-G)I/generic_clock.c new file mode 100644 index 0000000000..372712bf7c --- /dev/null +++ b/variants/STM32WBAxx/WBA55U(E-G)I/generic_clock.c @@ -0,0 +1,27 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_WBA55UEIX) || defined(ARDUINO_GENERIC_WBA55UGIX) +#include "pins_arduino.h" + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + /* SystemClock_Config can be generated by STM32CubeMX */ +#warning "SystemClock_Config() is empty. Default clock at reset is used." +} + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32WBAxx/WBA55U(E-G)I/variant_generic.cpp b/variants/STM32WBAxx/WBA55U(E-G)I/variant_generic.cpp new file mode 100644 index 0000000000..f2d0375fb1 --- /dev/null +++ b/variants/STM32WBAxx/WBA55U(E-G)I/variant_generic.cpp @@ -0,0 +1,69 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_GENERIC_WBA55UEIX) || defined(ARDUINO_GENERIC_WBA55UGIX) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_0, // D0/A0 + PA_1, // D1/A1 + PA_2, // D2/A2 + PA_3, // D3/A3 + PA_4, // D4/A4 + PA_5, // D5/A5 + PA_6, // D6/A6 + PA_7, // D7/A7 + PA_8, // D8/A8 + PA_9, // D9 + PA_10, // D10 + PA_11, // D11 + PA_12, // D12 + PA_13, // D13 + PA_14, // D14 + PA_15, // D15 + PB_0, // D16 + PB_1, // D17 + PB_2, // D18 + PB_3, // D19 + PB_4, // D20 + PB_5, // D21 + PB_6, // D22 + PB_7, // D23 + PB_8, // D24 + PB_9, // D25/A9 + PB_11, // D26 + PB_12, // D27 + PB_13, // D28 + PB_14, // D29 + PB_15, // D30 + PC_13, // D31 + PC_14, // D32 + PC_15, // D33 + PH_3 // D34 +}; + +// Analog (Ax) pin number array +const uint32_t analogInputPin[] = { + 0, // A0, PA0 + 1, // A1, PA1 + 2, // A2, PA2 + 3, // A3, PA3 + 4, // A4, PA4 + 5, // A5, PA5 + 6, // A6, PA6 + 7, // A7, PA7 + 8, // A8, PA8 + 25 // A9, PB9 +}; + +#endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32WBAxx/WBA55U(E-G)I/variant_generic.h b/variants/STM32WBAxx/WBA55U(E-G)I/variant_generic.h new file mode 100644 index 0000000000..15ae017f73 --- /dev/null +++ b/variants/STM32WBAxx/WBA55U(E-G)I/variant_generic.h @@ -0,0 +1,171 @@ +/* + ******************************************************************************* + * Copyright (c) 2020, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA0 PIN_A0 +#define PA1 PIN_A1 +#define PA2 PIN_A2 +#define PA3 PIN_A3 +#define PA4 PIN_A4 +#define PA5 PIN_A5 +#define PA6 PIN_A6 +#define PA7 PIN_A7 +#define PA8 PIN_A8 +#define PA9 9 +#define PA10 10 +#define PA11 11 +#define PA12 12 +#define PA13 13 +#define PA14 14 +#define PA15 15 +#define PB0 16 +#define PB1 17 +#define PB2 18 +#define PB3 19 +#define PB4 20 +#define PB5 21 +#define PB6 22 +#define PB7 23 +#define PB8 24 +#define PB9 PIN_A9 +#define PB11 26 +#define PB12 27 +#define PB13 28 +#define PB14 29 +#define PB15 30 +#define PC13 31 +#define PC14 32 +#define PC15 33 +#define PH3 34 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA2_ALT1 (PA2 | ALT1) +#define PB1_ALT1 (PB1 | ALT1) +#define PB2_ALT1 (PB2 | ALT1) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB8_ALT1 (PB8 | ALT1) +#define PB9_ALT1 (PB9 | ALT1) +#define PB9_ALT2 (PB9 | ALT2) +#define PB15_ALT1 (PB15 | ALT1) + +#define NUM_DIGITAL_PINS 35 +#define NUM_ANALOG_INPUTS 10 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PNUM_NOT_DEFINED +#endif + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PNUM_NOT_DEFINED +#endif + +// SPI definitions +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA12 +#endif +#ifndef PIN_SPI_SS1 + #define PIN_SPI_SS1 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_SS2 + #define PIN_SPI_SS2 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_SS3 + #define PIN_SPI_SS3 PNUM_NOT_DEFINED +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PA15 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PB3 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PB4 +#endif + +// I2C definitions +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PA7 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PA6 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM16 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM17 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 101 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA1 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PA2 +#endif + +// Alternate SYS_WKUP definition +#define PWR_WAKEUP_PIN1_1 +#define PWR_WAKEUP_PIN2_1 +#define PWR_WAKEUP_PIN3_1 +#define PWR_WAKEUP_PIN4_1 +#define PWR_WAKEUP_PIN5_1 +#define PWR_WAKEUP_PIN6_1 +#define PWR_WAKEUP_PIN7_1 +#define PWR_WAKEUP_PIN8_1 + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif From 73fb7f9b934c5658d8e09b72687c3369eff250e0 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 15 Feb 2024 16:07:40 +0100 Subject: [PATCH 11/21] variant(WBA): add WBA55C(E-G)U generic support Signed-off-by: Frederic Pillon --- README.md | 7 + boards.txt | 86 ++++++++ .../STM32WBAxx/WBA55C(E-G)U/generic_clock.c | 53 ++++- variants/STM32WBAxx/WBA55C(E-G)U/ldscript.ld | 185 ++++++++++++++++++ 4 files changed, 329 insertions(+), 2 deletions(-) create mode 100644 variants/STM32WBAxx/WBA55C(E-G)U/ldscript.ld diff --git a/README.md b/README.md index 6d717fe09c..0da6bdf8c5 100644 --- a/README.md +++ b/README.md @@ -72,6 +72,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d - [Generic STM32L5 boards](#generic-stm32l5-boards) - [Generic STM32U5 boards](#generic-stm32u5-boards) - [Generic STM32WB boards](#generic-stm32wb-boards) + - [Generic STM32WBA boards](#generic-stm32wba-boards) - [Generic STM32WL boards](#generic-stm32wl-boards) - [3D printer boards](#3d-printer-boards) - [Blues Wireless boards](#blues-wireless-boards) @@ -727,6 +728,12 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d | :green_heart: | STM32WB5MMG | Generic Board | *2.1.0* | | | :green_heart: | STM32WB55RC
STM32WB55RE
STM32WB55RG | Generic Board | *2.0.0* | | +### Generic STM32WBA boards + +| Status | Device(s) | Name | Release | Notes | +| :----: | :-------: | ---- | :-----: | :---- | +| :yellow_heart: | STM32WBA55CEU
STM32WBA55CGU | Generic Board | **2.8.0** | | + ### Generic STM32WL boards | Status | Device(s) | Name | Release | Notes | diff --git a/boards.txt b/boards.txt index ef5443fc94..10a01e47de 100644 --- a/boards.txt +++ b/boards.txt @@ -10274,6 +10274,48 @@ GenWB.menu.upload_method.dfuMethod.upload.protocol=2 GenWB.menu.upload_method.dfuMethod.upload.options= GenWB.menu.upload_method.dfuMethod.upload.tool=stm32CubeProg +################################################################################ +# Generic WBA +GenWBA.name=Generic STM32WBA series + +GenWBA.build.core=arduino +GenWBA.build.board=GenWBA +GenWBA.build.st_extra_flags=-D{build.product_line} {build.xSerial} +GenWBA.build.mcu=cortex-m33 +GenWBA.build.fpu=-mfpu=fpv4-sp-d16 +GenWBA.build.float-abi=-mfloat-abi=hard +GenWBA.build.series=STM32WBAxx +GenWBA.build.flash_offset=0x0 +GenWBA.upload.maximum_size=0 +GenWBA.upload.maximum_data_size=0 + +# Generic WBA55CEUx +GenWBA.menu.pnum.GENERIC_WBA55CEUX=Generic WBA55CEUx +GenWBA.menu.pnum.GENERIC_WBA55CEUX.upload.maximum_size=524288 +GenWBA.menu.pnum.GENERIC_WBA55CEUX.upload.maximum_data_size=98304 +GenWBA.menu.pnum.GENERIC_WBA55CEUX.build.board=GENERIC_WBA55CEUX +GenWBA.menu.pnum.GENERIC_WBA55CEUX.build.product_line=STM32WBA55xx +GenWBA.menu.pnum.GENERIC_WBA55CEUX.build.variant=STM32WBAxx/WBA55C(E-G)U + +# Generic WBA55CGUx +GenWBA.menu.pnum.GENERIC_WBA55CGUX=Generic WBA55CGUx +GenWBA.menu.pnum.GENERIC_WBA55CGUX.upload.maximum_size=1048576 +GenWBA.menu.pnum.GENERIC_WBA55CGUX.upload.maximum_data_size=131072 +GenWBA.menu.pnum.GENERIC_WBA55CGUX.build.board=GENERIC_WBA55CGUX +GenWBA.menu.pnum.GENERIC_WBA55CGUX.build.product_line=STM32WBA55xx +GenWBA.menu.pnum.GENERIC_WBA55CGUX.build.variant=STM32WBAxx/WBA55C(E-G)U + +# Upload menu +GenWBA.menu.upload_method.swdMethod=STM32CubeProgrammer (SWD) +GenWBA.menu.upload_method.swdMethod.upload.protocol=0 +GenWBA.menu.upload_method.swdMethod.upload.options= +GenWBA.menu.upload_method.swdMethod.upload.tool=stm32CubeProg + +GenWBA.menu.upload_method.serialMethod=STM32CubeProgrammer (Serial) +GenWBA.menu.upload_method.serialMethod.upload.protocol=1 +GenWBA.menu.upload_method.serialMethod.upload.options={serial.port.file} +GenWBA.menu.upload_method.serialMethod.upload.tool=stm32CubeProg + ################################################################################ # Generic WL GenWL.name=Generic STM32WL series @@ -11355,6 +11397,12 @@ GenWB.menu.xserial.none.build.xSerial=-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE GenWB.menu.xserial.disabled=Disabled (no Serial support) GenWB.menu.xserial.disabled.build.xSerial= +GenWBA.menu.xserial.generic=Enabled (generic 'Serial') +GenWBA.menu.xserial.none=Enabled (no generic 'Serial') +GenWBA.menu.xserial.none.build.xSerial=-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE +GenWBA.menu.xserial.disabled=Disabled (no Serial support) +GenWBA.menu.xserial.disabled.build.xSerial= + GenWL.menu.xserial.generic=Enabled (generic 'Serial') GenWL.menu.xserial.none=Enabled (no generic 'Serial') GenWL.menu.xserial.none.build.xSerial=-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE @@ -12231,6 +12279,26 @@ GenWB.menu.opt.ogstd.build.flags.optimize=-Og GenWB.menu.opt.o0std=No Optimization (-O0) GenWB.menu.opt.o0std.build.flags.optimize=-O0 +GenWBA.menu.opt.osstd=Smallest (-Os default) +GenWBA.menu.opt.oslto=Smallest (-Os) with LTO +GenWBA.menu.opt.oslto.build.flags.optimize=-Os -flto +GenWBA.menu.opt.o1std=Fast (-O1) +GenWBA.menu.opt.o1std.build.flags.optimize=-O1 +GenWBA.menu.opt.o1lto=Fast (-O1) with LTO +GenWBA.menu.opt.o1lto.build.flags.optimize=-O1 -flto +GenWBA.menu.opt.o2std=Faster (-O2) +GenWBA.menu.opt.o2std.build.flags.optimize=-O2 +GenWBA.menu.opt.o2lto=Faster (-O2) with LTO +GenWBA.menu.opt.o2lto.build.flags.optimize=-O2 -flto +GenWBA.menu.opt.o3std=Fastest (-O3) +GenWBA.menu.opt.o3std.build.flags.optimize=-O3 +GenWBA.menu.opt.o3lto=Fastest (-O3) with LTO +GenWBA.menu.opt.o3lto.build.flags.optimize=-O3 -flto +GenWBA.menu.opt.ogstd=Debug (-Og) +GenWBA.menu.opt.ogstd.build.flags.optimize=-Og +GenWBA.menu.opt.o0std=No Optimization (-O0) +GenWBA.menu.opt.o0std.build.flags.optimize=-O0 + GenWL.menu.opt.osstd=Smallest (-Os default) GenWL.menu.opt.oslto=Smallest (-Os) with LTO GenWL.menu.opt.oslto.build.flags.optimize=-Os -flto @@ -12624,6 +12692,14 @@ GenWB.menu.dbg.enable_log.build.flags.debug= GenWB.menu.dbg.enable_all=Core Logs and Symbols Enabled (-g) GenWB.menu.dbg.enable_all.build.flags.debug=-g +GenWBA.menu.dbg.none=None +GenWBA.menu.dbg.enable_sym=Symbols Enabled (-g) +GenWBA.menu.dbg.enable_sym.build.flags.debug=-g -DNDEBUG +GenWBA.menu.dbg.enable_log=Core logs Enabled +GenWBA.menu.dbg.enable_log.build.flags.debug= +GenWBA.menu.dbg.enable_all=Core Logs and Symbols Enabled (-g) +GenWBA.menu.dbg.enable_all.build.flags.debug=-g + GenWL.menu.dbg.none=None GenWL.menu.dbg.enable_sym=Symbols Enabled (-g) GenWL.menu.dbg.enable_sym.build.flags.debug=-g -DNDEBUG @@ -12943,6 +13019,16 @@ GenWB.menu.rtlib.nanofps.build.flags.ldspecs=--specs=nano.specs -u _printf_float GenWB.menu.rtlib.full=Newlib Standard GenWB.menu.rtlib.full.build.flags.ldspecs= +GenWBA.menu.rtlib.nano=Newlib Nano (default) +GenWBA.menu.rtlib.nanofp=Newlib Nano + Float Printf +GenWBA.menu.rtlib.nanofp.build.flags.ldspecs=--specs=nano.specs -u _printf_float +GenWBA.menu.rtlib.nanofs=Newlib Nano + Float Scanf +GenWBA.menu.rtlib.nanofs.build.flags.ldspecs=--specs=nano.specs -u _scanf_float +GenWBA.menu.rtlib.nanofps=Newlib Nano + Float Printf/Scanf +GenWBA.menu.rtlib.nanofps.build.flags.ldspecs=--specs=nano.specs -u _printf_float -u _scanf_float +GenWBA.menu.rtlib.full=Newlib Standard +GenWBA.menu.rtlib.full.build.flags.ldspecs= + GenWL.menu.rtlib.nano=Newlib Nano (default) GenWL.menu.rtlib.nanofp=Newlib Nano + Float Printf GenWL.menu.rtlib.nanofp.build.flags.ldspecs=--specs=nano.specs -u _printf_float diff --git a/variants/STM32WBAxx/WBA55C(E-G)U/generic_clock.c b/variants/STM32WBAxx/WBA55C(E-G)U/generic_clock.c index 69077431a4..42459d52ea 100644 --- a/variants/STM32WBAxx/WBA55C(E-G)U/generic_clock.c +++ b/variants/STM32WBAxx/WBA55C(E-G)U/generic_clock.c @@ -20,8 +20,57 @@ */ WEAK void SystemClock_Config(void) { - /* SystemClock_Config can be generated by STM32CubeMX */ -#warning "SystemClock_Config() is empty. Default clock at reset is used." + RCC_OscInitTypeDef RCC_OscInitStruct = {}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {}; + RCC_PeriphCLKInitTypeDef PeriphClkInit = {}; + + /** Configure the main internal regulator output voltage + */ + if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) { + Error_Handler(); + } + + /** Initializes the CPU, AHB and APB busses clocks + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL1.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL1.PLLSource = RCC_PLLSOURCE_HSI; + RCC_OscInitStruct.PLL1.PLLM = 1; + RCC_OscInitStruct.PLL1.PLLN = 12; + RCC_OscInitStruct.PLL1.PLLP = 2; + RCC_OscInitStruct.PLL1.PLLQ = 2; + RCC_OscInitStruct.PLL1.PLLR = 2; + RCC_OscInitStruct.PLL1.PLLFractional = 4096; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + Error_Handler(); + } + + /** Initializes the CPU, AHB and APB busses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK + | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 + | RCC_CLOCKTYPE_PCLK7 | RCC_CLOCKTYPE_HCLK5; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB7CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.AHB5_PLL1_CLKDivider = RCC_SYSCLK_PLL1_DIV4; + RCC_ClkInitStruct.AHB5_HSEHSI_CLKDivider = RCC_SYSCLK_HSEHSI_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) { + Error_Handler(); + } + + /** Initializes the peripherals clocks + */ + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPUART1; + PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) { + Error_Handler(); + } } #endif /* ARDUINO_GENERIC_* */ diff --git a/variants/STM32WBAxx/WBA55C(E-G)U/ldscript.ld b/variants/STM32WBAxx/WBA55C(E-G)U/ldscript.ld new file mode 100644 index 0000000000..83cf331b03 --- /dev/null +++ b/variants/STM32WBAxx/WBA55C(E-G)U/ldscript.ld @@ -0,0 +1,185 @@ +/* +****************************************************************************** +** +** @file : LinkerScript.ld +** +** @author : Auto-generated by STM32CubeIDE +** +** @brief : Linker script for STM32WBA55CGUx Device from STM32WBA series +** 1024KBytes FLASH +** 128KBytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2024 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE + FLASH (rx) : ORIGIN = 0x8000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM : { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} From c645cc5a2faeaa4b7a6a1211d171f9e8c3f0f6d9 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 15 Feb 2024 16:17:26 +0100 Subject: [PATCH 12/21] core(WBA): Backup register API update Signed-off-by: Frederic Pillon --- cores/arduino/stm32/backup.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/cores/arduino/stm32/backup.h b/cores/arduino/stm32/backup.h index 9965f68c79..6a2be641d5 100644 --- a/cores/arduino/stm32/backup.h +++ b/cores/arduino/stm32/backup.h @@ -120,7 +120,8 @@ static inline void setBackupRegister(uint32_t index, uint32_t value) LL_RTC_BAK_SetRegister(RTC, index, value); #elif defined(TAMP_BKP0R) #if defined(STM32G4xx) || defined(STM32H5xx) || defined(STM32L5xx) ||\ - defined(STM32U5xx) || defined(STM32MP1xx) || defined(STM32WLxx) + defined(STM32U5xx) || defined(STM32MP1xx) || defined(STM32WBAxx) ||\ + defined(STM32WLxx) /* For those series this API requires RTC even if it is not used and TAMP is used instead */ LL_RTC_BKP_SetRegister(RTC, index, value); @@ -143,7 +144,8 @@ static inline uint32_t getBackupRegister(uint32_t index) return LL_RTC_BAK_GetRegister(RTC, index); #elif defined(TAMP_BKP0R) #if defined(STM32G4xx) || defined(STM32H5xx) || defined(STM32L5xx) ||\ - defined(STM32U5xx) || defined(STM32MP1xx) || defined(STM32WLxx) + defined(STM32U5xx) || defined(STM32MP1xx) || defined(STM32WBAxx) ||\ + defined(STM32WLxx) /* For those series this API requires RTC even if it is not used and TAMP is used instead */ return LL_RTC_BKP_GetRegister(RTC, index); From e453b7e2b47eda921b7c2c14c34327a253be12ae Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Fri, 16 Feb 2024 10:10:31 +0100 Subject: [PATCH 13/21] libraries(WBA): update RCC configuration Signed-off-by: Frederic Pillon --- libraries/SrcWrapper/src/stm32/clock.c | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/libraries/SrcWrapper/src/stm32/clock.c b/libraries/SrcWrapper/src/stm32/clock.c index b0ef8e32a2..c535607ca3 100644 --- a/libraries/SrcWrapper/src/stm32/clock.c +++ b/libraries/SrcWrapper/src/stm32/clock.c @@ -78,8 +78,12 @@ void enableClock(sourceClock_t source) { RCC_OscInitTypeDef RCC_OscInitStruct = {0}; #if defined(RCC_PLL_NONE) +#if defined(STM32WBAxx) + RCC_OscInitStruct.PLL1.PLLState = RCC_PLL_NONE; +#else RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; #endif +#endif #if defined(STM32MP1xx) /** Clock source selection is done by First Stage Boot Loader on Cortex A @@ -97,14 +101,24 @@ void enableClock(sourceClock_t source) #ifdef RCC_FLAG_LSI1RDY __HAL_RCC_LSI1_ENABLE(); if (__HAL_RCC_GET_FLAG(RCC_FLAG_LSI1RDY) == RESET) { +#ifdef RCC_OSCILLATORTYPE_LSI1 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI1; +#else + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI; +#endif +#ifdef RCC_LSI1_ON + RCC_OscInitStruct.LSIState = RCC_LSI1_ON; +#else + RCC_OscInitStruct.LSIState = RCC_LSI_ON; +#endif + } #else __HAL_RCC_LSI_ENABLE(); if (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) { RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI; -#endif RCC_OscInitStruct.LSIState = RCC_LSI_ON; } +#endif break; case HSI_CLOCK: __HAL_RCC_HSI_ENABLE(); @@ -122,7 +136,11 @@ void enableClock(sourceClock_t source) __HAL_RCC_LSE_CONFIG(RCC_LSE_ON); if (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) { #ifdef __HAL_RCC_LSEDRIVE_CONFIG +#ifdef RCC_LSEDRIVE_LOW __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW); +#else + __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_MEDIUMLOW); +#endif #endif RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; RCC_OscInitStruct.LSEState = RCC_LSE_ON; From c20e41123661c1c22c3228b1824b59ff0b9fd7b8 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Fri, 16 Feb 2024 10:14:13 +0100 Subject: [PATCH 14/21] core(WBA): TIM1_IRQn definition Signed-off-by: Frederic Pillon --- cores/arduino/stm32/timer.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cores/arduino/stm32/timer.h b/cores/arduino/stm32/timer.h index 3210f59159..7ce0941ff8 100644 --- a/cores/arduino/stm32/timer.h +++ b/cores/arduino/stm32/timer.h @@ -61,7 +61,7 @@ extern "C" { #endif #elif defined(STM32H5xx) || defined(STM32H7xx) || defined(STM32L5xx) ||\ defined(STM32MP1xx) || defined(STM32U5xx) || defined(STM32WBxx) ||\ - defined(STM32WLxx) + defined(STM32WBAxx) ||defined(STM32WLxx) #define TIM1_IRQn TIM1_UP_IRQn #define TIM1_IRQHandler TIM1_UP_IRQHandler #endif From ef8b4c0ea812252ac56f6ac6ef4834e2e87218b3 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Fri, 16 Feb 2024 10:16:10 +0100 Subject: [PATCH 15/21] libraries(WBA): add GPIO EXTI support Signed-off-by: Frederic Pillon --- libraries/SrcWrapper/src/stm32/interrupt.cpp | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/libraries/SrcWrapper/src/stm32/interrupt.cpp b/libraries/SrcWrapper/src/stm32/interrupt.cpp index c11780ab5c..40327e94ec 100644 --- a/libraries/SrcWrapper/src/stm32/interrupt.cpp +++ b/libraries/SrcWrapper/src/stm32/interrupt.cpp @@ -70,7 +70,8 @@ static gpio_irq_conf_str gpio_irq_conf[NB_EXTI] = { {.irqnb = EXTI4_15_IRQn, .callback = NULL}, //GPIO_PIN_13 {.irqnb = EXTI4_15_IRQn, .callback = NULL}, //GPIO_PIN_14 {.irqnb = EXTI4_15_IRQn, .callback = NULL} //GPIO_PIN_15 -#elif defined (STM32H5xx) || defined (STM32MP1xx) || defined (STM32L5xx) || defined (STM32U5xx) +#elif defined (STM32H5xx) || defined (STM32MP1xx) || defined (STM32L5xx) ||\ + defined (STM32U5xx) || defined (STM32WBAxx) {.irqnb = EXTI0_IRQn, .callback = NULL}, //GPIO_PIN_0 {.irqnb = EXTI1_IRQn, .callback = NULL}, //GPIO_PIN_1 {.irqnb = EXTI2_IRQn, .callback = NULL}, //GPIO_PIN_2 @@ -251,7 +252,8 @@ void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) } #if defined(STM32C0xx) || defined(STM32G0xx) || defined(STM32H5xx) || \ - defined(STM32MP1xx) || defined(STM32L5xx) || defined(STM32U5xx) + defined(STM32MP1xx) || defined(STM32L5xx) || defined(STM32U5xx) || \ + defined(STM32WBAxx) /** * @brief EXTI line detection callback. * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. @@ -374,7 +376,8 @@ void EXTI4_IRQHandler(void) HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_4); } -#if !defined(STM32H5xx) && !defined(STM32MP1xx) && !defined(STM32L5xx) && !defined(STM32U5xx) +#if !defined(STM32H5xx) && !defined(STM32MP1xx) && !defined(STM32L5xx) && \ + !defined(STM32U5xx)&& !defined(STM32WBAxx) /** * @brief This function handles external line 5 to 9 interrupt request. * @param None From 08f6d5d52f2c76219cc4e1994a04af4dea6b189a Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Fri, 16 Feb 2024 10:33:39 +0100 Subject: [PATCH 16/21] libraries(WBA): ADC support Signed-off-by: Frederic Pillon --- cores/arduino/stm32/stm32_def.h | 2 +- libraries/SrcWrapper/src/stm32/analog.cpp | 35 +++++++++++++++-------- 2 files changed, 24 insertions(+), 13 deletions(-) diff --git a/cores/arduino/stm32/stm32_def.h b/cores/arduino/stm32/stm32_def.h index 3a62be66b0..8b193a8c87 100644 --- a/cores/arduino/stm32/stm32_def.h +++ b/cores/arduino/stm32/stm32_def.h @@ -71,7 +71,7 @@ #endif // Here define some compatibility -#ifndef ADC1 +#if !defined (ADC1) && defined (ADC) #define ADC1 ADC #endif #ifndef CAN1 diff --git a/libraries/SrcWrapper/src/stm32/analog.cpp b/libraries/SrcWrapper/src/stm32/analog.cpp index 63ff690c47..356643eb81 100644 --- a/libraries/SrcWrapper/src/stm32/analog.cpp +++ b/libraries/SrcWrapper/src/stm32/analog.cpp @@ -82,6 +82,8 @@ static PinName g_current_pin = NC; #define ADC_SAMPLINGTIME_INTERNAL ADC_SAMPLETIME_239CYCLES_5 #elif defined(ADC_SAMPLETIME_160CYCLES_5) #define ADC_SAMPLINGTIME_INTERNAL ADC_SAMPLETIME_160CYCLES_5 +#elif defined(ADC_SAMPLETIME_814CYCLES_5) +#define ADC_SAMPLINGTIME_INTERNAL ADC_SAMPLETIME_814CYCLES_5 #else #error "ADC sampling time could not be defined for internal channels!" #endif @@ -157,6 +159,7 @@ uint32_t get_adc_channel(PinName pin, uint32_t *bank) case 13: channel = ADC_CHANNEL_13; break; +#ifdef ADC_CHANNEL_14 case 14: channel = ADC_CHANNEL_14; break; @@ -224,6 +227,7 @@ uint32_t get_adc_channel(PinName pin, uint32_t *bank) #endif #endif #endif +#endif #endif default: _Error_Handler("ADC: Unknown adc channel", (int)(STM_PIN_CHANNEL(function))); @@ -563,6 +567,7 @@ void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc) { /*##-1- Enable peripherals and GPIO Clocks #################################*/ /* ADC Periph clock enable */ +#ifdef ADC1 if (hadc->Instance == ADC1) { #ifdef __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE(); @@ -571,8 +576,9 @@ void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc) __HAL_RCC_ADC12_CLK_ENABLE(); #endif } +#endif #ifdef ADC2 - else if (hadc->Instance == ADC2) { + if (hadc->Instance == ADC2) { #ifdef __HAL_RCC_ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE(); #endif @@ -582,7 +588,7 @@ void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc) } #endif #ifdef ADC3 - else if (hadc->Instance == ADC3) { + if (hadc->Instance == ADC3) { #ifdef __HAL_RCC_ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE(); #endif @@ -595,7 +601,7 @@ void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc) } #endif #ifdef ADC4 - else if (hadc->Instance == ADC4) { + if (hadc->Instance == ADC4) { #ifdef __HAL_RCC_ADC4_CLK_ENABLE __HAL_RCC_ADC4_CLK_ENABLE(); #endif @@ -608,7 +614,7 @@ void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc) } #endif #ifdef ADC5 - else if (hadc->Instance == ADC5) { + if (hadc->Instance == ADC5) { #if defined(ADC345_COMMON) __HAL_RCC_ADC345_CLK_ENABLE(); #endif @@ -647,6 +653,7 @@ void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc) __HAL_RCC_ADC_RELEASE_RESET(); #endif +#ifdef ADC1 if (hadc->Instance == ADC1) { #ifdef __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET(); @@ -667,8 +674,9 @@ void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc) __HAL_RCC_ADC12_CLK_DISABLE(); #endif } +#endif #ifdef ADC2 - else if (hadc->Instance == ADC2) { + if (hadc->Instance == ADC2) { #ifdef __HAL_RCC_ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET(); #endif @@ -690,7 +698,7 @@ void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc) } #endif #ifdef ADC3 - else if (hadc->Instance == ADC3) { + if (hadc->Instance == ADC3) { #ifdef __HAL_RCC_ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET(); #endif @@ -717,7 +725,7 @@ void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc) } #endif #ifdef ADC4 - else if (hadc->Instance == ADC4) { + if (hadc->Instance == ADC4) { #ifdef __HAL_RCC_ADC4_FORCE_RESET __HAL_RCC_ADC4_FORCE_RESET(); #endif @@ -744,7 +752,7 @@ void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc) } #endif #ifdef ADC5 - else if (hadc->Instance == ADC5) { + if (hadc->Instance == ADC5) { #if defined(ADC345_COMMON) __HAL_RCC_ADC345_FORCE_RESET(); __HAL_RCC_ADC345_RELEASE_RESET(); @@ -781,6 +789,8 @@ uint16_t adc_read_value(PinName pin, uint32_t resolution) #else AdcHandle.Instance = ADC2; #endif +#elif defined(STM32WBAxx) + AdcHandle.Instance = ADC4; #else AdcHandle.Instance = ADC1; #if defined(ADC5) && defined(ADC_CHANNEL_TEMPSENSOR_ADC5) @@ -877,7 +887,8 @@ uint16_t adc_read_value(PinName pin, uint32_t resolution) #endif AdcHandle.Init.DiscontinuousConvMode = DISABLE; /* Parameter discarded because sequencer is disabled */ #if !defined(STM32C0xx) && !defined(STM32F0xx) && !defined(STM32G0xx) && \ - !defined(STM32L0xx) && !defined(STM32WLxx) && !defined(ADC_SUPPORT_2_5_MSPS) + !defined(STM32L0xx) && !defined(STM32WBAxx) && !defined(STM32WLxx) && \ + !defined(ADC_SUPPORT_2_5_MSPS) AdcHandle.Init.NbrOfDiscConversion = 0; /* Parameter discarded because sequencer is disabled */ #endif AdcHandle.Init.ExternalTrigConv = ADC_SOFTWARE_START; /* Software start to trig the 1st conversion manually, without external event */ @@ -902,7 +913,7 @@ uint16_t adc_read_value(PinName pin, uint32_t resolution) AdcHandle.Init.SamplingTimeCommon = samplingTime; #endif #if defined(STM32C0xx) || defined(STM32G0xx) || defined(STM32U5xx) || \ - defined(STM32WLxx) || defined(ADC_SUPPORT_2_5_MSPS) + defined(STM32WBAxx) || defined(STM32WLxx) || defined(ADC_SUPPORT_2_5_MSPS) AdcHandle.Init.SamplingTimeCommon1 = samplingTime; /* Set sampling time common to a group of channels. */ AdcHandle.Init.SamplingTimeCommon2 = samplingTime; /* Set sampling time common to a group of channels, second common setting possible.*/ #endif @@ -966,8 +977,8 @@ uint16_t adc_read_value(PinName pin, uint32_t resolution) #endif #if !defined(STM32C0xx) && !defined(STM32F0xx) && !defined(STM32F1xx) && \ !defined(STM32F2xx) && !defined(STM32G0xx) && !defined(STM32L0xx) && \ - !defined(STM32L1xx) && !defined(STM32WBxx) && !defined(STM32WLxx) && \ - !defined(ADC1_V2_5) + !defined(STM32L1xx) && !defined(STM32WBAxx) && !defined(STM32WBxx) && \ + !defined(STM32WLxx) && !defined(ADC1_V2_5) AdcChannelConf.Offset = 0; /* Parameter discarded because offset correction is disabled */ #endif #if defined (STM32H7xx) || defined(STM32MP1xx) From d62a7c92f498cadacd0ce111a6fbb9f3bd62af11 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Wed, 28 Feb 2024 15:35:03 +0100 Subject: [PATCH 17/21] libraries(WBA): IWDG support Signed-off-by: Frederic Pillon --- libraries/IWatchdog/src/IWatchdog.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libraries/IWatchdog/src/IWatchdog.cpp b/libraries/IWatchdog/src/IWatchdog.cpp index b44f8a80e3..2fd20bb268 100644 --- a/libraries/IWatchdog/src/IWatchdog.cpp +++ b/libraries/IWatchdog/src/IWatchdog.cpp @@ -38,7 +38,7 @@ void IWatchdogClass::begin(uint32_t timeout, uint32_t window) } // Enable the peripheral clock IWDG -#ifdef RCC_CSR_LSI1ON +#if defined(RCC_CSR_LSI1ON) || defined(RCC_BDCR1_LSI1ON) LL_RCC_LSI1_Enable(); while (LL_RCC_LSI1_IsReady() != 1) { } From 2124d42e7d04254dbaebf60a48d97973a30ee7e5 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Sat, 24 Feb 2024 16:35:07 +0100 Subject: [PATCH 18/21] lib(eeprom): add STM32WBAxx support Signed-off-by: Frederic Pillon --- libraries/EEPROM/src/utility/stm32_eeprom.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libraries/EEPROM/src/utility/stm32_eeprom.c b/libraries/EEPROM/src/utility/stm32_eeprom.c index 68f50fb7da..14410e151d 100644 --- a/libraries/EEPROM/src/utility/stm32_eeprom.c +++ b/libraries/EEPROM/src/utility/stm32_eeprom.c @@ -26,7 +26,7 @@ extern "C" { #endif /* Be able to change FLASH_BANK_NUMBER to use if relevant */ -#if !defined(FLASH_BANK_NUMBER) && defined(FLASH_BANK_1) +#if !defined(FLASH_BANK_NUMBER) && defined(FLASH_BANK_1) && !defined(STM32WBAxx) #if defined(FLASH_BANK_2) #define FLASH_BANK_NUMBER FLASH_BANK_2 #else /* FLASH_BANK_1 */ From 93d8e59f2dc2e7363c400b94e812d57858b3785c Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Tue, 20 Feb 2024 16:46:33 +0100 Subject: [PATCH 19/21] variant(WBA): add Nucleo WBA55CG support Signed-off-by: Frederic Pillon --- README.md | 1 + boards.txt | 13 ++ .../WBA55C(E-G)U/variant_NUCLEO_WBA55CG.cpp | 138 +++++++++++++++++ .../WBA55C(E-G)U/variant_NUCLEO_WBA55CG.h | 145 ++++++++++++++++++ 4 files changed, 297 insertions(+) create mode 100644 variants/STM32WBAxx/WBA55C(E-G)U/variant_NUCLEO_WBA55CG.cpp create mode 100644 variants/STM32WBAxx/WBA55C(E-G)U/variant_NUCLEO_WBA55CG.h diff --git a/README.md b/README.md index 0da6bdf8c5..ca3f470831 100644 --- a/README.md +++ b/README.md @@ -143,6 +143,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d | :green_heart: | STM32L452RE-P | [Nucleo L452RE-P](http://www.st.com/en/evaluation-tools/nucleo-l452re-p.html) | *1.8.0* | | | :green_heart: | STM32L476RG | [Nucleo L476RG](http://www.st.com/en/evaluation-tools/nucleo-l476rg.html) | *0.1.0* | | | :green_heart: | STM32WB15CCU | [Nucleo-WB15CC](https://www.st.com/en/evaluation-tools/nucleo-wb15cc.html) | *2.5.0* | | +| :yellow_heart: | STM32WBA55CGU | Nucleo-WBA55CG | **2.8.0** | | | :green_heart: | STM32WB55RG | [P-Nucleo-WB55RG](https://www.st.com/en/evaluation-tools/p-nucleo-wb55.html) | *1.6.0* | BLE support with [STM32duinoBLE](https://github.com/stm32duino/STM32duinoBLE) | | :green_heart: | STM32WB55CG | [P-Nucleo-WB55 USB Dongle](https://www.st.com/en/evaluation-tools/p-nucleo-wb55.html) | *2.5.0* | BLE support with [STM32duinoBLE](https://github.com/stm32duino/STM32duinoBLE) | | :green_heart: | STM32WL55JC | [Nucleo WL55JC1](https://www.st.com/en/evaluation-tools/nucleo-wl55jc.html) | *2.1.0* | LoRa support not available | diff --git a/boards.txt b/boards.txt index 10a01e47de..88a4a97f2a 100644 --- a/boards.txt +++ b/boards.txt @@ -666,6 +666,19 @@ Nucleo_64.menu.pnum.P_NUCLEO_WB55_USB_DONGLE.build.series=STM32WBxx Nucleo_64.menu.pnum.P_NUCLEO_WB55_USB_DONGLE.build.product_line=STM32WB55xx Nucleo_64.menu.pnum.P_NUCLEO_WB55_USB_DONGLE.build.variant=STM32WBxx/WB35C(C-E)UxA_WB55C(C-E-G)U +# NUCLEO WBA55CG +Nucleo_64.menu.pnum.NUCLEO_WBA55CG=Nucleo WBA55CG +Nucleo_64.menu.pnum.NUCLEO_WBA55CG.node="NOD_WBA52CG,NOD_WBA55CG" +Nucleo_64.menu.pnum.NUCLEO_WBA55CG.upload.maximum_size=1048576 +Nucleo_64.menu.pnum.NUCLEO_WBA55CG.upload.maximum_data_size=131072 +Nucleo_64.menu.pnum.NUCLEO_WBA55CG.build.mcu=cortex-m33 +Nucleo_64.menu.pnum.NUCLEO_WBA55CG.build.fpu=-mfpu=fpv4-sp-d16 +Nucleo_64.menu.pnum.NUCLEO_WBA55CG.build.float-abi=-mfloat-abi=hard +Nucleo_64.menu.pnum.NUCLEO_WBA55CG.build.board=NUCLEO_WBA55CG +Nucleo_64.menu.pnum.NUCLEO_WBA55CG.build.series=STM32WBAxx +Nucleo_64.menu.pnum.NUCLEO_WBA55CG.build.product_line=STM32WBA55xx +Nucleo_64.menu.pnum.NUCLEO_WBA55CG.build.variant=STM32WBAxx/WBA55C(E-G)U + # NUCLEO_WL55JC1 board Nucleo_64.menu.pnum.NUCLEO_WL55JC1=Nucleo WL55JC1 Nucleo_64.menu.pnum.NUCLEO_WL55JC1.node="NOD_WL55JC" diff --git a/variants/STM32WBAxx/WBA55C(E-G)U/variant_NUCLEO_WBA55CG.cpp b/variants/STM32WBAxx/WBA55C(E-G)U/variant_NUCLEO_WBA55CG.cpp new file mode 100644 index 0000000000..75063feb1a --- /dev/null +++ b/variants/STM32WBAxx/WBA55C(E-G)U/variant_NUCLEO_WBA55CG.cpp @@ -0,0 +1,138 @@ +/* + ******************************************************************************* + * Copyright (c) 2023, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_NUCLEO_WBA55CG) +#include "pins_arduino.h" + +// Digital PinName array +const PinName digitalPin[] = { + PA_10, //D0 + PB_5, //D1 + PB_7, //D2 + PB_6, //D3 + PA_11, //D4 + PB_14, //D5 + PB_0, //D6 + PB_9, //D7/A7 + PB_15, //D8 + PA_9, //D9 + PA_12, //D10 + PA_15, //D11 + PB_3, //D12 + PB_4, //D13 + PB_1, //D14 + PB_2, //D15 + PA_7, //D16/A0 + PA_6, //D17/A1 + PA_2, //D18/A2 + PA_1, //D19/A3 + PA_5, //D20/A4 + PA_0, //D21/A5 + PB_8, //D22 + PC_13, //D23 + PB_12, //D24 + PA_8, //D25 + PC_15, //D26 + PC_14, //D27 + PA_14, //D28 + PA_13, //D29 + PH_3 //D30 +}; + +// Analog (Ax) pin number array +const uint32_t analogInputPin[] = { + 16, // A0, PA7 + 17, // A1, PA6 + 18, // A2, PA2 + 19, // A3, PA1 + 20, // A4, PA5 + 21, // A5, PA0 + 7 // A6, PB9 +}; + +// ---------------------------------------------------------------------------- +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief System Clock Configuration + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {}; + RCC_PeriphCLKInitTypeDef PeriphClkInit = {}; + + /** Configure the main internal regulator output voltage + */ + if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) { + Error_Handler(); + } + + /** Configure LSE Drive Capability + */ + HAL_PWR_EnableBkUpAccess(); + __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_MEDIUMLOW); + + /** Initializes the CPU, AHB and APB busses clocks + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE + | RCC_OSCILLATORTYPE_LSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.HSEDiv = RCC_HSE_DIV1; + RCC_OscInitStruct.LSEState = RCC_LSE_ON; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL1.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL1.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL1.PLLM = 2; + RCC_OscInitStruct.PLL1.PLLN = 12; + RCC_OscInitStruct.PLL1.PLLP = 2; + RCC_OscInitStruct.PLL1.PLLQ = 2; + RCC_OscInitStruct.PLL1.PLLR = 2; + RCC_OscInitStruct.PLL1.PLLFractional = 4096; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + Error_Handler(); + } + + /** Initializes the CPU, AHB and APB busses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK + | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 + | RCC_CLOCKTYPE_PCLK7 | RCC_CLOCKTYPE_HCLK5; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB7CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.AHB5_PLL1_CLKDivider = RCC_SYSCLK_PLL1_DIV4; + RCC_ClkInitStruct.AHB5_HSEHSI_CLKDivider = RCC_SYSCLK_HSEHSI_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) { + Error_Handler(); + } + /** Initializes the peripherals clock + */ + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPUART1; + PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) { + Error_Handler(); + } +} + +#ifdef __cplusplus +} +#endif +#endif /* ARDUINO_NUCLEO_WBA55CG* */ diff --git a/variants/STM32WBAxx/WBA55C(E-G)U/variant_NUCLEO_WBA55CG.h b/variants/STM32WBAxx/WBA55C(E-G)U/variant_NUCLEO_WBA55CG.h new file mode 100644 index 0000000000..3edf95f5a8 --- /dev/null +++ b/variants/STM32WBAxx/WBA55C(E-G)U/variant_NUCLEO_WBA55CG.h @@ -0,0 +1,145 @@ +/* + ******************************************************************************* + * Copyright (c) 2023, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +#define PA10 0 +#define PB5 1 +#define PB7 2 // B2 +#define PB6 3 // B3 +#define PA11 4 +#define PB14 5 +#define PB0 6 +#define PB9 PIN_A6 +#define PB15 8 +#define PA9 9 // LED2 (default not connected SB28 off) +#define PA12 10 +#define PA15 11 +#define PB3 12 +#define PB4 13 // LED1 +#define PB1 14 +#define PB2 15 + +#define PA7 PIN_A0 +#define PA6 PIN_A1 +#define PA2 PIN_A2 +#define PA1 PIN_A3 +#define PA5 PIN_A4 +#define PA0 PIN_A5 + +#define PB8 22 // LED3 +#define PC13 23 // B1 +#define PB12 24 // VCP1_TX +#define PA8 25 // VCP1_RX +#define PC15 26 // OSC32_IN +#define PC14 27 // OSC32_OUT +#define PA14 28 // SWCLK +#define PA13 29 // SWDIO +#define PH3 30 // BOOT0 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA2_ALT1 (PA2 | ALT1) +#define PB1_ALT1 (PB1 | ALT1) +#define PB2_ALT1 (PB2 | ALT1) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB8_ALT1 (PB8 | ALT1) +#define PB9_ALT1 (PB9 | ALT1) +#define PB9_ALT2 (PB9 | ALT2) +#define PB15_ALT1 (PB15 | ALT1) + +#define NUM_DIGITAL_PINS 31 +#define NUM_ANALOG_INPUTS 7 + +// On-board LED pin number +#define LED1 PB4 +#define LED2 PA9 +#define LED3 PB8 +#ifndef LED_BUILTIN + #define LED_BUILTIN LED1 +#endif +#define LED_BLUE LED1 +#define LED_GREEN LED2 +#define LED_RED LED3 + +// On-board user button +#define B1_BTN PC13 +#define B2_BTN PB6 +#define B3_BTN PB7 +#ifndef USER_BTN + #define USER_BTN B1_BTN +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM16 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM17 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 1 +#endif + +// Default pin used for generic 'Serial' instance +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PA8 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PB12 +#endif + +// Alternate SYS_WKUP definition +#define PWR_WAKEUP_PIN1_1 +#define PWR_WAKEUP_PIN3_1 +#define PWR_WAKEUP_PIN4_1 +#define PWR_WAKEUP_PIN6_1 +#define PWR_WAKEUP_PIN7_1 +#define PWR_WAKEUP_PIN8_1 + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif From 56ccb92116b22c8536142ac84c4a1834aa405b20 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Wed, 28 Feb 2024 15:14:59 +0100 Subject: [PATCH 20/21] chore(cmake): update after WBA addition Signed-off-by: Frederic Pillon --- cmake/boards_db.cmake | 190 ++++++++++++++++++ .../STM32WBAxx/WBA50K(E-G)U/CMakeLists.txt | 31 +++ .../CMakeLists.txt | 31 +++ .../WBA52K(E-G)U_WBA54K(E-G)U/CMakeLists.txt | 31 +++ .../STM32WBAxx/WBA55C(E-G)U/CMakeLists.txt | 32 +++ .../STM32WBAxx/WBA55U(E-G)I/CMakeLists.txt | 31 +++ 6 files changed, 346 insertions(+) create mode 100644 variants/STM32WBAxx/WBA50K(E-G)U/CMakeLists.txt create mode 100644 variants/STM32WBAxx/WBA52C(E-G)U_WBA54C(E-G)U_WBA55H(E-G)F/CMakeLists.txt create mode 100644 variants/STM32WBAxx/WBA52K(E-G)U_WBA54K(E-G)U/CMakeLists.txt create mode 100644 variants/STM32WBAxx/WBA55C(E-G)U/CMakeLists.txt create mode 100644 variants/STM32WBAxx/WBA55U(E-G)I/CMakeLists.txt diff --git a/cmake/boards_db.cmake b/cmake/boards_db.cmake index e812ef6461..af691d12f5 100644 --- a/cmake/boards_db.cmake +++ b/cmake/boards_db.cmake @@ -97092,6 +97092,114 @@ target_compile_options(GENERIC_WB5MMGHX_xusb_HSFS INTERFACE "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" ) +# GENERIC_WBA55CEUX +# ----------------------------------------------------------------------------- + +set(GENERIC_WBA55CEUX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32WBAxx/WBA55C(E-G)U") +set(GENERIC_WBA55CEUX_MAXSIZE 524288) +set(GENERIC_WBA55CEUX_MAXDATASIZE 98304) +set(GENERIC_WBA55CEUX_MCU cortex-m33) +set(GENERIC_WBA55CEUX_FPCONF "-") +add_library(GENERIC_WBA55CEUX INTERFACE) +target_compile_options(GENERIC_WBA55CEUX INTERFACE + "SHELL:-DSTM32WBA55xx " + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_WBA55CEUX_MCU} +) +target_compile_definitions(GENERIC_WBA55CEUX INTERFACE + "STM32WBAxx" + "ARDUINO_GENERIC_WBA55CEUX" + "BOARD_NAME=\"GENERIC_WBA55CEUX\"" + "BOARD_ID=GENERIC_WBA55CEUX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_WBA55CEUX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32WBAxx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WBAxx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WBAxx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/ + ${GENERIC_WBA55CEUX_VARIANT_PATH} +) + +target_link_options(GENERIC_WBA55CEUX INTERFACE + "LINKER:--default-script=${GENERIC_WBA55CEUX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=524288" + "LINKER:--defsym=LD_MAX_DATA_SIZE=98304" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_WBA55CEUX_MCU} +) + +add_library(GENERIC_WBA55CEUX_serial_disabled INTERFACE) +target_compile_options(GENERIC_WBA55CEUX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_WBA55CEUX_serial_generic INTERFACE) +target_compile_options(GENERIC_WBA55CEUX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_WBA55CEUX_serial_none INTERFACE) +target_compile_options(GENERIC_WBA55CEUX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) + +# GENERIC_WBA55CGUX +# ----------------------------------------------------------------------------- + +set(GENERIC_WBA55CGUX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32WBAxx/WBA55C(E-G)U") +set(GENERIC_WBA55CGUX_MAXSIZE 1048576) +set(GENERIC_WBA55CGUX_MAXDATASIZE 131072) +set(GENERIC_WBA55CGUX_MCU cortex-m33) +set(GENERIC_WBA55CGUX_FPCONF "-") +add_library(GENERIC_WBA55CGUX INTERFACE) +target_compile_options(GENERIC_WBA55CGUX INTERFACE + "SHELL:-DSTM32WBA55xx " + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_WBA55CGUX_MCU} +) +target_compile_definitions(GENERIC_WBA55CGUX INTERFACE + "STM32WBAxx" + "ARDUINO_GENERIC_WBA55CGUX" + "BOARD_NAME=\"GENERIC_WBA55CGUX\"" + "BOARD_ID=GENERIC_WBA55CGUX" + "VARIANT_H=\"variant_generic.h\"" +) +target_include_directories(GENERIC_WBA55CGUX INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32WBAxx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WBAxx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WBAxx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/ + ${GENERIC_WBA55CGUX_VARIANT_PATH} +) + +target_link_options(GENERIC_WBA55CGUX INTERFACE + "LINKER:--default-script=${GENERIC_WBA55CGUX_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=1048576" + "LINKER:--defsym=LD_MAX_DATA_SIZE=131072" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${GENERIC_WBA55CGUX_MCU} +) + +add_library(GENERIC_WBA55CGUX_serial_disabled INTERFACE) +target_compile_options(GENERIC_WBA55CGUX_serial_disabled INTERFACE + "SHELL:" +) +add_library(GENERIC_WBA55CGUX_serial_generic INTERFACE) +target_compile_options(GENERIC_WBA55CGUX_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(GENERIC_WBA55CGUX_serial_none INTERFACE) +target_compile_options(GENERIC_WBA55CGUX_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) + # GENERIC_WL54CCUX # ----------------------------------------------------------------------------- @@ -103334,6 +103442,88 @@ target_compile_options(NUCLEO_WB15CC_xusb_HSFS INTERFACE "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" ) +# NUCLEO_WBA55CG +# ----------------------------------------------------------------------------- + +set(NUCLEO_WBA55CG_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32WBAxx/WBA55C(E-G)U") +set(NUCLEO_WBA55CG_MAXSIZE 1048576) +set(NUCLEO_WBA55CG_MAXDATASIZE 131072) +set(NUCLEO_WBA55CG_MCU cortex-m33) +set(NUCLEO_WBA55CG_FPCONF "fpv4-sp-d16-hard") +add_library(NUCLEO_WBA55CG INTERFACE) +target_compile_options(NUCLEO_WBA55CG INTERFACE + "SHELL:-DSTM32WBA55xx " + "SHELL:" + "SHELL:" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${NUCLEO_WBA55CG_MCU} +) +target_compile_definitions(NUCLEO_WBA55CG INTERFACE + "STM32WBAxx" + "ARDUINO_NUCLEO_WBA55CG" + "BOARD_NAME=\"NUCLEO_WBA55CG\"" + "BOARD_ID=NUCLEO_WBA55CG" + "VARIANT_H=\"variant_NUCLEO_WBA55CG.h\"" +) +target_include_directories(NUCLEO_WBA55CG INTERFACE + ${CMAKE_CURRENT_LIST_DIR}/../system/STM32WBAxx + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WBAxx_HAL_Driver/Inc + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32WBAxx_HAL_Driver/Src + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/ + ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32WBAxx/Source/Templates/gcc/ + ${NUCLEO_WBA55CG_VARIANT_PATH} +) + +target_link_options(NUCLEO_WBA55CG INTERFACE + "LINKER:--default-script=${NUCLEO_WBA55CG_VARIANT_PATH}/ldscript.ld" + "LINKER:--defsym=LD_FLASH_OFFSET=0x0" + "LINKER:--defsym=LD_MAX_SIZE=1048576" + "LINKER:--defsym=LD_MAX_DATA_SIZE=131072" + "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard" + -mcpu=${NUCLEO_WBA55CG_MCU} +) + +add_library(NUCLEO_WBA55CG_serial_disabled INTERFACE) +target_compile_options(NUCLEO_WBA55CG_serial_disabled INTERFACE + "SHELL:" +) +add_library(NUCLEO_WBA55CG_serial_generic INTERFACE) +target_compile_options(NUCLEO_WBA55CG_serial_generic INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED" +) +add_library(NUCLEO_WBA55CG_serial_none INTERFACE) +target_compile_options(NUCLEO_WBA55CG_serial_none INTERFACE + "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE" +) +add_library(NUCLEO_WBA55CG_usb_CDC INTERFACE) +target_compile_options(NUCLEO_WBA55CG_usb_CDC INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB" +) +add_library(NUCLEO_WBA55CG_usb_CDCgen INTERFACE) +target_compile_options(NUCLEO_WBA55CG_usb_CDCgen INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC" +) +add_library(NUCLEO_WBA55CG_usb_HID INTERFACE) +target_compile_options(NUCLEO_WBA55CG_usb_HID INTERFACE + "SHELL:-DUSBCON -DUSBD_VID=0 -DUSBD_PID=-1 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE" +) +add_library(NUCLEO_WBA55CG_usb_none INTERFACE) +target_compile_options(NUCLEO_WBA55CG_usb_none INTERFACE + "SHELL:" +) +add_library(NUCLEO_WBA55CG_xusb_FS INTERFACE) +target_compile_options(NUCLEO_WBA55CG_xusb_FS INTERFACE + "SHELL:" +) +add_library(NUCLEO_WBA55CG_xusb_HS INTERFACE) +target_compile_options(NUCLEO_WBA55CG_xusb_HS INTERFACE + "SHELL:-DUSE_USB_HS" +) +add_library(NUCLEO_WBA55CG_xusb_HSFS INTERFACE) +target_compile_options(NUCLEO_WBA55CG_xusb_HSFS INTERFACE + "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS" +) + # NUCLEO_WL55JC1 # ----------------------------------------------------------------------------- diff --git a/variants/STM32WBAxx/WBA50K(E-G)U/CMakeLists.txt b/variants/STM32WBAxx/WBA50K(E-G)U/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32WBAxx/WBA50K(E-G)U/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32WBAxx/WBA52C(E-G)U_WBA54C(E-G)U_WBA55H(E-G)F/CMakeLists.txt b/variants/STM32WBAxx/WBA52C(E-G)U_WBA54C(E-G)U_WBA55H(E-G)F/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32WBAxx/WBA52C(E-G)U_WBA54C(E-G)U_WBA55H(E-G)F/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32WBAxx/WBA52K(E-G)U_WBA54K(E-G)U/CMakeLists.txt b/variants/STM32WBAxx/WBA52K(E-G)U_WBA54K(E-G)U/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32WBAxx/WBA52K(E-G)U_WBA54K(E-G)U/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32WBAxx/WBA55C(E-G)U/CMakeLists.txt b/variants/STM32WBAxx/WBA55C(E-G)U/CMakeLists.txt new file mode 100644 index 0000000000..97c3b03fe4 --- /dev/null +++ b/variants/STM32WBAxx/WBA55C(E-G)U/CMakeLists.txt @@ -0,0 +1,32 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp + variant_NUCLEO_WBA55CG.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + diff --git a/variants/STM32WBAxx/WBA55U(E-G)I/CMakeLists.txt b/variants/STM32WBAxx/WBA55U(E-G)I/CMakeLists.txt new file mode 100644 index 0000000000..2a4d55b6b1 --- /dev/null +++ b/variants/STM32WBAxx/WBA55U(E-G)I/CMakeLists.txt @@ -0,0 +1,31 @@ +# v3.21 implemented semantic changes regarding $ +# See https://cmake.org/cmake/help/v3.21/command/target_link_libraries.html#linking-object-libraries-via-target-objects +cmake_minimum_required(VERSION 3.21) + +add_library(variant INTERFACE) +add_library(variant_usage INTERFACE) + +target_include_directories(variant_usage INTERFACE + . +) + + +target_link_libraries(variant_usage INTERFACE + base_config +) + +target_link_libraries(variant INTERFACE variant_usage) + + + +add_library(variant_bin STATIC EXCLUDE_FROM_ALL + generic_clock.c + PeripheralPins.c + variant_generic.cpp +) +target_link_libraries(variant_bin PUBLIC variant_usage) + +target_link_libraries(variant INTERFACE + variant_bin +) + From e22e3fd7c9a6ab15d2057ae5e1665ef92a0d2af9 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Wed, 28 Feb 2024 15:16:28 +0100 Subject: [PATCH 21/21] ci(cmake): add Nucleo WBA55CG board Signed-off-by: Frederic Pillon --- .github/workflows/Cmake.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.github/workflows/Cmake.yml b/.github/workflows/Cmake.yml index 933e5f3eea..cdd55482a2 100644 --- a/.github/workflows/Cmake.yml +++ b/.github/workflows/Cmake.yml @@ -47,6 +47,7 @@ jobs: - NUCLEO_L552ZE_Q - NUCLEO_U575ZI_Q - P_NUCLEO_WB55RG + - NUCLEO_WBA55CG - NUCLEO_WL55JC1 steps: